/*
 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	memory {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		/* this allow the ethaddr uboot environmnet variable contents
		 * to be added to the gmac1 device tree blob.
		 */
		ethernet0 = &gmac1;
		udc0 = &usb1;
	};

	regulator_3_3v: 3-3-v-regulator {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	soc {
		u-boot,dm-pre-reloc;
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";

	rxd0-skew-ps = <0>;
	rxd1-skew-ps = <0>;
	rxd2-skew-ps = <0>;
	rxd3-skew-ps = <0>;
	txen-skew-ps = <0>;
	txc-skew-ps = <2600>;
	rxdv-skew-ps = <0>;
	rxc-skew-ps = <2000>;
};

&gpio1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

&mmc0 {
	status = "okay";
	u-boot,dm-pre-reloc;

	cd-gpios = <&portb 18 0>;
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
};

&qspi {
	status = "okay";

	flash0: n25q00@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q00";
		reg = <0>;      /* chip select */
		spi-max-frequency = <100000000>;
		m25p,fast-read;
		page-size = <256>;
		block-size = <16>; /* 2^16, 64KB */
		read-delay = <4>;  /* delay value in read data capture register */
		tshsl-ns = <50>;
		tsd2d-ns = <50>;
		tchsh-ns = <4>;
		tslch-ns = <4>;
	};
};

&usb1 {
	status = "okay";
};