/*
 * Device Tree Source for UniPhier PH1-Pro5 SoC
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+	X11
 */

/include/ "uniphier-common32.dtsi"

/ {
	compatible = "socionext,ph1-pro5";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,uniphier-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&l2>;
		};
	};

	clocks {
		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <73728000>;
		};

		i2c_clk: i2c_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};
};

&soc {
	l2: l2-cache@500c0000 {
		compatible = "socionext,uniphier-system-cache";
		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
		interrupts = <0 190 4>, <0 191 4>;
		cache-unified;
		cache-size = <(2 * 1024 * 1024)>;
		cache-sets = <512>;
		cache-line-size = <128>;
		cache-level = <2>;
		next-level-cache = <&l3>;
	};

	l3: l3-cache@500c8000 {
		compatible = "socionext,uniphier-system-cache";
		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
		interrupts = <0 174 4>, <0 175 4>;
		cache-unified;
		cache-size = <(2 * 1024 * 1024)>;
		cache-sets = <512>;
		cache-line-size = <256>;
		cache-level = <3>;
	};

	i2c0: i2c@58780000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58780000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 41 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c0>;
		clocks = <&i2c_clk>;
		clock-frequency = <100000>;
	};

	i2c1: i2c@58781000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58781000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 42 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c1>;
		clocks = <&i2c_clk>;
		clock-frequency = <100000>;
	};

	i2c2: i2c@58782000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58782000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 43 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2>;
		clocks = <&i2c_clk>;
		clock-frequency = <100000>;
	};

	i2c3: i2c@58783000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58783000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 44 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3>;
		clocks = <&i2c_clk>;
		clock-frequency = <100000>;
	};

	/* i2c4 does not exist */

	/* chip-internal connection for DMD */
	i2c5: i2c@58785000 {
		compatible = "socionext,uniphier-fi2c";
		reg = <0x58785000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 25 4>;
		clocks = <&i2c_clk>;
		clock-frequency = <400000>;
	};

	/* chip-internal connection for HDMI */
	i2c6: i2c@58786000 {
		compatible = "socionext,uniphier-fi2c";
		reg = <0x58786000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 26 4>;
		clocks = <&i2c_clk>;
		clock-frequency = <400000>;
	};

	usb0: usb@65a00000 {
		compatible = "socionext,uniphier-xhci", "generic-xhci";
		status = "disabled";
		reg = <0x65a00000 0x100>;
		interrupts = <0 134 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb0>;
	};

	usb1: usb@65c00000 {
		compatible = "socionext,uniphier-xhci", "generic-xhci";
		status = "disabled";
		reg = <0x65c00000 0x100>;
		interrupts = <0 137 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
	};
};

&serial0 {
	clock-frequency = <73728000>;
};

&serial1 {
	clock-frequency = <73728000>;
};

&serial2 {
	clock-frequency = <73728000>;
};

&serial3 {
	clock-frequency = <73728000>;
};

&pinctrl {
	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
};