/*
 * Copyright (C) Marvell International Ltd. and its affiliates
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef _DDR3_TOPOLOGY_DEF_H
#define _DDR3_TOPOLOGY_DEF_H

/* TOPOLOGY */

enum hws_speed_bin {
	SPEED_BIN_DDR_800D,
	SPEED_BIN_DDR_800E,
	SPEED_BIN_DDR_1066E,
	SPEED_BIN_DDR_1066F,
	SPEED_BIN_DDR_1066G,
	SPEED_BIN_DDR_1333F,
	SPEED_BIN_DDR_1333G,
	SPEED_BIN_DDR_1333H,
	SPEED_BIN_DDR_1333J,
	SPEED_BIN_DDR_1600G,
	SPEED_BIN_DDR_1600H,
	SPEED_BIN_DDR_1600J,
	SPEED_BIN_DDR_1600K,
	SPEED_BIN_DDR_1866J,
	SPEED_BIN_DDR_1866K,
	SPEED_BIN_DDR_1866L,
	SPEED_BIN_DDR_1866M,
	SPEED_BIN_DDR_2133K,
	SPEED_BIN_DDR_2133L,
	SPEED_BIN_DDR_2133M,
	SPEED_BIN_DDR_2133N,

	SPEED_BIN_DDR_1333H_EXT,
	SPEED_BIN_DDR_1600K_EXT,
	SPEED_BIN_DDR_1866M_EXT
};

enum hws_ddr_freq {
	DDR_FREQ_LOW_FREQ,
	DDR_FREQ_400,
	DDR_FREQ_533,
	DDR_FREQ_667,
	DDR_FREQ_800,
	DDR_FREQ_933,
	DDR_FREQ_1066,
	DDR_FREQ_311,
	DDR_FREQ_333,
	DDR_FREQ_467,
	DDR_FREQ_850,
	DDR_FREQ_600,
	DDR_FREQ_300,
	DDR_FREQ_900,
	DDR_FREQ_360,
	DDR_FREQ_1000,
	DDR_FREQ_LIMIT
};

enum speed_bin_table_elements {
	SPEED_BIN_TRCD,
	SPEED_BIN_TRP,
	SPEED_BIN_TRAS,
	SPEED_BIN_TRC,
	SPEED_BIN_TRRD1K,
	SPEED_BIN_TRRD2K,
	SPEED_BIN_TPD,
	SPEED_BIN_TFAW1K,
	SPEED_BIN_TFAW2K,
	SPEED_BIN_TWTR,
	SPEED_BIN_TRTP,
	SPEED_BIN_TWR,
	SPEED_BIN_TMOD
};

#endif /* _DDR3_TOPOLOGY_DEF_H */