/*
 * NDA AND NEED-TO-KNOW REQUIRED
 *
 * Copyright © 2013-2018 Synaptics Incorporated. All rights reserved.
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 * Use of the materials may require a license of intellectual property
 * from a third party or from Synaptics. This file conveys no express
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 * to Synaptics.
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 * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND
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 * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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#include "Galois_memmap.h"
#include "global.h"
#include "util.h"

void init_clock(void)
{
    T32clkD4_ctrl g1CoreClkCtrl;

    // G1 clock: 400 MHz
    BFM_HOST_Bus_Read32((MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_g1CoreClk), &g1CoreClkCtrl.u32);
    g1CoreClkCtrl.uctrl_ClkEn = clkD4_ctrl_ClkEn_enable;
    g1CoreClkCtrl.uctrl_ClkPllSel = clkD4_ctrl_ClkPllSel_SYSPLL;
    g1CoreClkCtrl.uctrl_ClkPllSwitch = clkD4_ctrl_ClkPllSwitch_SYSPLL;
    g1CoreClkCtrl.uctrl_ClkSwitch = clkD4_ctrl_ClkSwitch_DivClk;
    g1CoreClkCtrl.uctrl_ClkD3Switch = clkD4_ctrl_ClkD3Switch_NonDiv3Clk;
    g1CoreClkCtrl.uctrl_ClkSel = clkD4_ctrl_ClkSel_d2;
    BFM_HOST_Bus_Write32((MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_g1CoreClk), g1CoreClkCtrl.u32);
}