/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

#ifndef __PLLDIAG__H_
#define __PLLDIAG__H_
#include "Galois_memmap.h"
#include "avioGbl.h"

#undef DIAG_ENV
#undef DIAG_PRT

#if 1
//Diag code use phy_addr directly
#define AVPLL_A (MEMMAP_AVIO_GBL_BASE + RA_avioGbl_AVPLLA)
#define AVPLL_B (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_AVPLLB)
#else
#define AVPLL_A ((volatile unsigned int *)devmem_phy_to_virt(MEMMAP_AVIO_GBL_BASE + RA_avioGbl_AVPLLA))
#define AVPLL_B ((volatile unsigned int *)devmem_phy_to_virt(MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_AVPLLB))
#endif

#define PHY_HOST_Bus_Read32(addr_var, u32) *((volatile unsigned*)&(u32)) = *((volatile unsigned*)&(addr_var))
#define PHY_HOST_Bus_Write32(addr_var, u32) *((volatile unsigned*)&(addr_var)) = (u32)

extern int diag_pll_A_VCO_Setting;
extern int diag_pll_B_VCO_Setting;

enum
{
	VCO_FREQ_1_512G=0,
	VCO_FREQ_1_620G,
	VCO_FREQ_1_856G,
	VCO_FREQ_2_160G,
	VCO_FREQ_2_227G,
	VCO_FREQ_2_520G,
	VCO_FREQ_2_700G,
	VCO_FREQ_2_970G,
};

enum PRINT_LEVEL
{
	PRN_NONE=0,
	PRN_ERR,
	PRN_RES,
	PRN_INFO,
	PRN_DBG
};

#ifdef DIAG_PRT
//#define dbg_printf(RES, fmt, ...) printf("%d(%s:%d)--" fmt, RES, __FUNCTION__, __LINE__, ##__VA_ARGS__)
#else
#define dbg_printf(RES, fmt, ...) 
#endif

extern double diag_vcoFreqs[];
extern double diag_videoFreqs[];

extern void diag_setDPll(SIE_avPll *avPllBase, int enable, int p_sync1, int p_sync2, int chId);
//extern void diag_setVCO(SIE_avPll *avPllBase, int vco_freq_index);
extern void diag_setChanOffset(SIE_avPll *avPllBase, int offset, int chId);
void diag_set_Post_Div(SIE_avPll *avPllBase, int div, int chId);
void diag_set_Post_0P5_Div(SIE_avPll *avPllBase, int enable, int chId);
extern void diag_set1KPPM(SIE_avPll *avPllBase, int inc, int chId);
extern void diag_changeRefFreq(int vco_freq_index, int grp);
extern void diag_avpllFreq(SIE_avPll *avPllBase, int chId);
extern void diag_vcoFreq(SIE_avPll *avPllBase);
extern void diag_videoFreq(SIE_avPll *avPllBase, int freqIndex, int hdmiMode, int frameRate, float overSampleRate, int chId);
extern int diag_clockFreq(SIE_avPll *avPllBase, int vco_freq_index, unsigned int target_freq, int chId);
extern void diag_assertReset(SIE_avPll *avPllBase);
extern void diag_deassertReset(SIE_avPll *avPllBase);
void diag_powerDown(SIE_avPll *avPllBase);
void diag_powerUp(SIE_avPll *avPllBase);
void diag_calibrate(SIE_avPll *avPllBase, double fvco);
extern void diag_initAvPll(void);

extern int diag_pll_A_VCO_Setting;
extern int diag_pll_B_VCO_Setting;

void cpu_cycle_count_delay(unsigned int udelay);
int diag_powerStatus(SIE_avPll *avPllBase);
void dump_AVPLL_regs(int nRegs);

#define BFM_HOST_Bus_Write32    GA_REG_WORD32_WRITE
#define BFM_HOST_Bus_Read32     GA_REG_WORD32_READ

#endif