/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//////
/// don't edit! auto-generated by docc: SysMgr.h
////////////////////////////////////////////////////////////
#ifndef SysMgr_h
#define SysMgr_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE smSysCtl                biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 SM_ID                (R-)
///               ###
///               * SM ID information
///               ###
///               %unsigned 4  REV_ID                    0xA
///                                    ###
///                                    * SM revision ID
///                                    ###
///               %unsigned 16 PART_ID                   0x7788
///                                    ###
///                                    * SM part number ID
///                                    ###
///               %unsigned 12 MFC_ID                    0x8D
///                                    ###
///                                    * SM manufacture
///                                    ###
///     @ 0x00004 SM_CPU_CTRL          (RW)
///               ###
///               * SM CPU control
///               ###
///               %unsigned 1  CPU_RST_GO                0x0
///                                    ###
///                                    * SM CPU reset control
///                                    * 0: assert CPU reset
///                                    * 1: de-assert CPU reset
///                                    ###
///               %unsigned 1  CPU_VINITHI               0x0
///                                    ###
///                                    * High exception vector address select
///                                    * 0: starts from 0x0000_0000
///                                    * 1: starts from 0xFFFF_0000
///                                    ###
///               %unsigned 1  CPU_INITRAM               0x1
///                                    ###
///                                    * TCM enable at reset
///                                    * 0: TCM disable at reet
///                                    * 1: TCM is enabled at reset
///                                    ###
///               %unsigned 1  CPU_BIGEND                0x0
///                                    ###
///                                    * SM CPU endian status
///                                    * 0: little endian
///                                    * 1: big endian
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00008 SM_RST_CTRL          (RW)
///               ###
///               * SM reset control
///               ###
///               %unsigned 1  SOC_RST_GO                0x1
///                                    ###
///                                    * Berlin SoC reset control
///                                    * 0: assert Berlin SoC reset
///                                    * 1: de-assert Berlin SoC reset
///                                    ###
///               %unsigned 1  APB_RST_GO                0x1
///                                    ###
///                                    * SM APB component reset control, write 1 to assert APB reset. This reset automatically de-assert after 3 SM system clocks
///                                    * 0: assert APB reset, de-assert automatically
///                                    * 1: no effect
///                                    ###
///               %unsigned 1  SXBAR_RST_GO              0x1
///                                    ###
///                                    * SM crossbar reset control, write 1 to assert SXBAR reset. This reset automatically de-assert after 3 SM system clocks
///                                    * 0: assert SXBAR reset, de-assert automatically.
///                                    * 1: no effect
///                                    ###
///               %unsigned 1  WOL_RST_GO                0x1
///                                    ###
///                                    * WOL reset control.
///                                    * 0: assert WOL reset.
///                                    * 1: de-assert WOL reset.
///                                    ###
///               %unsigned 1  FEPHY_RST_GO              0x1
///                                    ###
///                                    * FEPHY reset control.
///                                    * 0: assert FEPHY reset.
///                                    * 1: de-assert FEPHY reset.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x0000C SM_RST_STATUS        (RW)
///               ###
///               * SM reset status control
///               ###
///               %unsigned 1  RST_WD_0                  0x0
///                                    ###
///                                    * Watch dog 0 status
///                                    * 0: no watch dog 0 event happen
///                                    * 1: watch dog 0 event happen
///                                    ###
///               %unsigned 1  RST_WD_1                  0x0
///                                    ###
///                                    * Watch dog 1 status
///                                    * 0: no watch dog 1 event happen
///                                    * 1: watch dog 1 event happen
///                                    ###
///               %unsigned 1  RST_WD_2                  0x0
///                                    ###
///                                    * Watch dog 2 status
///                                    * 0: no watch dog 2 event happen
///                                    * 1: watch dog 2 event happen
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00010 SM_STRP_STATUS       (RW)
///               ###
///               * SM power strapping status control
///               ###
///               %unsigned 2  BOOT_MODE                 0x0
///                                    ###
///                                    * SM boot up mode[1:0]
///                                    * 00: Boot typical way 0
///                                    * 01: Boot typical way 1 (with power stable in)
///                                    * 10: Bo0t new way
///                                    * 11: Disable SM
///                                    ###
///               %unsigned 1  STRP_2                    0x0
///                                    ###
///                                    * Reserved
///                                    ###
///               %unsigned 1  STRP_3                    0x0
///                                    ###
///                                    * Reserved
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00014 SM_CTRL              (RW)
///               ###
///               * SM misc control
///               ###
///               %unsigned 1  ISO_EN                    0x0
///                                    ###
///                                    * Isolation cell enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  SM2SOC_SW_INTR            0x0
///                                    ###
///                                    * SM to SOC software interrupt
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  SOC2SM_SW_INTR            0x1
///                                    ###
///                                    * SOC to SM software interrupt, connects to IRQ13, active low
///                                    * 0: enable
///                                    * 1: disable
///                                    ###
///               %unsigned 2  REV_0                     0x0
///                                    ###
///                                    * Reserved
///                                    ###
///               %unsigned 4  ADC_SEL                   0x7
///                                    ###
///                                    * ADC input selection
///                                    * 4'h0: ADC_IN[0]
///                                    * 4'h1: ADC_IN[1]
///                                    * 4'h2: ADC_IN[2]
///                                    * 4'h3: ADC_IN[3]
///                                    * 4'h4: ADC_IN[4]
///                                    * 4'h5: ADC_IN[5]
///                                    * 4'h6: ADC_IN[6]
///                                    * 4'h7: ADC_IN[7]
///                                    * 4'h8: ADC_IN[8]
///                                    * 4'h9: ADC_IN[9]
///                                    * 4'hA: ADC_IN[10]
///                                    * 4'hB: ADC_IN[11]
///                                    * 4'hC: ADC_IN[12]
///                                    * 4'hD: ADC_IN[13]
///                                    * 4'hE: ADC_IN[14]
///                                    * 4'hF: ADC_IN[15]
///                                    ###
///               %unsigned 1  ADC_PU                    0x0
///                                    ###
///                                    * SM ADC power control
///                                    * 0: power-down
///                                    * 1: power-up
///                                    ###
///               %unsigned 2  ADC_CKSEL                 0x3
///                                    ###
///                                    * ADC internal clock divider selection
///                                    * 2'h0: ck / 2
///                                    * 2'h1: ck / 3
///                                    * 2'h2: ck / 4
///                                    * 2'h3: ck / 8
///                                    ###
///               %unsigned 1  ADC_START                 0x0
///                                    ###
///                                    * Start ADC digitalization process, write 1 to start ADC digitalization. This bit automatically clear after receiving ADC done signal
///                                    * 0: no effect
///                                    * 1: Start ADC digitalization, clear automatically.
///                                    ###
///               %unsigned 1  ADC_RESET                 0x1
///                                    ###
///                                    * ADC reset control input, active high.
///                                    * 1: the digital circuitry is held in reset .
///                                    * 0: the digital circuitry is enabled and the analog circuitry will be powered up if ADC_PU_SAR11=1, BG_RDY11=1, and VAA is present.
///                                    ###
///               %unsigned 1  ADC_BG_RDY                0x0
///                                    ###
///                                    * bandgap reference block is powered up and ready
///                                    ###
///               %unsigned 1  ADC_CONT                  0x0
///                                    ###
///                                    * continuous mode vs. single-shot mode
///                                    * 0: ADC is in single-shot conversion operating mode.
///                                    * 1: ADC is in continuous conversion operating mode.
///                                    ###
///               %unsigned 1  ADC_BUF_EN                0x0
///                                    ###
///                                    * enables analog ADC input buffer
///                                    ###
///               %unsigned 1  ADC_VREF_SEL              0x0
///                                    ###
///                                    * selects ext. reference vs. int. ref.
///                                    ###
///               %unsigned 1  ADC_ROTATE_SEL            0x0
///                                    ###
///                                    * Orientation bit
///                                    ###
///               %unsigned 1  TSEN_EN                   0x0
///                                    ###
///                                    * Temperature sensor measurement enable signal. It should last for complete TS measurement cycles and will be deserted by DATA_RDY. When asserted, measurement gets started. uC should wait till DATA_RDY= 1 to desert TS_EN.
///                                    ###
///               %unsigned 1  TSEN_CLK_SEL              0x0
///                                    ###
///                                    * CLK_SEL= 1 will choose 2.5MHz clock, otherwise 1.25MHz will be chosen.
///                                    ###
///               %unsigned 1  TSEN_MODE_SEL             0x0
///                                    ###
///                                    * MODE_SEL= 1 will choose 10 ~ 50 degree Centigrade temperature testing range, otherwise 0 ~ 125 degree Centigrade temperature testing range will be chosen.
///                                    ###
///               %unsigned 2  TSEN_ADC_CAL              0x0
///                                    ###
///                                    * ADC calibration mode select bits from uC. 00 = normal function 10 = gain calibration function 01 = offset calibration (0.6V) 11 = Not used
///                                    ###
///               %unsigned 5  TSEN_ADC_TST_SEL          0x0
///                                    ###
///                                    * DC test point select signal
///                                    ###
///               %unsigned 1  TSEN_RESET                0x1
///                                    ###
///                                    * 1'b1 to reset TSEN after power up
///                                    ###
///               %unsigned 1  TSEN_ADC_ISO_EN           0x0
///                                    ###
///                                    * It's used as digital power availability indicator for digital 1.1V power domain and analog 1.8V power domain isolation purpose.
///                                    ###
///               %%        1          # Stuffing bits...
///     @ 0x00018 SM_ADC_CTRL          (RW)
///               ###
///               * SM ADCs Control
///               ###
///               %unsigned 5  TSEN_DAT_LT               0x0
///                                    ###
///                                    * Delay interms of pclk after data ready at which the data is to be latched
///                                    ###
///               %unsigned 5  ADC_DAT_LT                0x0
///                                    ###
///                                    * Delay interms of pclk after data ready at which the data is to be latched
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x0001C SM_ADC_STATUS        (RW)
///               ###
///               * SM ADC status and interrupt enable
///               ###
///               %unsigned 1  CH0_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 0 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH1_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 1 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH2_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 2 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH3_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 3 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH4_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 4 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH5_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 5 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH6_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 6 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH7_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 7 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH8_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 8 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH9_DATA_RDY              0x0
///                                    ###
///                                    * ADC channel 9 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH10_DATA_RDY             0x0
///                                    ###
///                                    * ADC channel 10 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH11_DATA_RDY             0x0
///                                    ###
///                                    * ADC channel 11 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH12_DATA_RDY             0x0
///                                    ###
///                                    * ADC channel 12 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH13_DATA_RDY             0x0
///                                    ###
///                                    * ADC channel 13 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH14_DATA_RDY             0x0
///                                    ###
///                                    * ADC channel 14 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH15_DATA_RDY             0x0
///                                    ###
///                                    * ADC channel 15 data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  CH0_INT_EN                0x0
///                                    ###
///                                    * ADC channel 0 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH1_INT_EN                0x0
///                                    ###
///                                    * ADC channel 1 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH2_INT_EN                0x0
///                                    ###
///                                    * ADC channel 2 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH3_INT_EN                0x0
///                                    ###
///                                    * ADC channel 3 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH4_INT_EN                0x0
///                                    ###
///                                    * ADC channel 4 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH5_INT_EN                0x0
///                                    ###
///                                    * ADC channel 5 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH6_INT_EN                0x0
///                                    ###
///                                    * ADC channel 6 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH7_INT_EN                0x0
///                                    ###
///                                    * ADC channel 7 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH8_INT_EN                0x0
///                                    ###
///                                    * ADC channel 8 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH9_INT_EN                0x0
///                                    ###
///                                    * ADC channel 9 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH10_INT_EN               0x0
///                                    ###
///                                    * ADC channel 10 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH11_INT_EN               0x0
///                                    ###
///                                    * ADC channel 11 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH12_INT_EN               0x0
///                                    ###
///                                    * ADC channel 12 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH13_INT_EN               0x0
///                                    ###
///                                    * ADC channel 13 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH14_INT_EN               0x0
///                                    ###
///                                    * ADC channel 14 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 1  CH15_INT_EN               0x0
///                                    ###
///                                    * ADC channel 15 interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///     @ 0x00020 SM_ADC_DATA          (R-)
///               ###
///               * SM ADC digitalized data
///               ###
///               %unsigned 10 ADC_DATA                  0x0
///                                    ###
///                                    * ADC data
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00024 TSEN_ADC_STATUS      (RW)
///               ###
///               * SM TSEN ADC status and interrupt enable
///               ###
///               %unsigned 1  DATA_RDY                  0x0
///                                    ###
///                                    * ADC data ready, write 0 to clear interrupt, write 1 won't effect anything
///                                    * 0: no valid data
///                                    * 1: data ready to read
///                                    ###
///               %unsigned 1  INT_EN                    0x0
///                                    ###
///                                    * ADC interrupt enable
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00028 TSEN_ADC_DATA        (R-)
///               ###
///               * SM TSEN ADC digitalized data
///               ###
///               %unsigned 12 ADC_DATA                  0x0
///                                    ###
///                                    * 12-bit post-average and calibration TSEN result.
///                                    * Data format is signed 12-bit with sign bit on the 1st MSB.
///                                    ###
///               %%        20         # Stuffing bits...
///     @ 0x0002C TSEN_CHK_CTRL        (RW)
///               ###
///               * SM TSEN Data Thresholds
///               ###
///               %unsigned 12 TSEN_DATA_MAX             0xFFF
///                                    ###
///                                    * Maximum value used to check against TSEN_DATA
///                                    ###
///               %unsigned 12 TSEN_DATA_MIN             0x0
///                                    ###
///                                    * Minimum value used to check against TSEN_DATA
///                                    ###
///               %unsigned 1  TSEN_OVERHEAT_SEL         0x0
///                                    ###
///                                    * 0: Overheat flag uses TSEN_MAX_FAIL
///                                    * 1: Overheat flag uses TSEN_MIN_FAIL
///                                    ###
///               %%        7          # Stuffing bits...
///     @ 0x00030 TSEN_DATA_STATUS     (R-)
///               ###
///               * SM TSEN Data Threshold Check Status
///               ###
///               %unsigned 1  TSEN_MAX_FAIL             0x0
///                                    ###
///                                    * 0: TSEN_DATA <= TSEN_DATA_MAX
///                                    * 1: TSEN_DATA > TSEN_DATA_MAX
///                                    ###
///               %unsigned 1  TSEN_MIN_FAIL             0x0
///                                    ###
///                                    * 0: TSEN_DATA >= TSEN_DATA_MIN
///                                    * 1: TSEN_DATA < TSEN_DATA_MIN
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00034 SM_BOOT_STATUS       (RW)
///               ###
///               * SM Software Boot status
///               ###
///               %unsigned 32 MODE                      0x0
///                                    ###
///                                    * Used by software only to store boot up status. HW can only clean to 0 with POR
///                                    ###
///     @ 0x00038 SM_LDO_CTRL          (RW)
///               ###
///               * SM LDO control & status register
///               ###
///               %unsigned 3  TEST_SEL                  0x0
///                                    ###
///                                    * Select output of test mux (VDD domain)
///                                    ###
///               %unsigned 3  VOUT_SEL                  0x0
///                                    ###
///                                    * Select LDO output voltage (VDD domain)
///                                    * 000   :	0.9V
///                                    * 001   :	0.789V
///                                    * 010   :	0.826V
///                                    * 011   :	0.863V
///                                    * 100   :	0.937V
///                                    * 101   :	0.974V
///                                    * 110   :	1.011V
///                                    * 111   :	1.048V
///                                    ###
///               %unsigned 1  TEST_EN                   0x0
///                                    ###
///                                    * Enable test mux (VDD domain )
///                                    ###
///               %unsigned 1  LDO_RDY                   0x0
///                                    ###
///                                    * Assert the LDO ready
///                                    ###
///               %unsigned 1  CHP_EN_1P1                0x0
///               %unsigned 1  ICLAMP_EN_1P1             0x0
///               %%        22         # Stuffing bits...
///     @ 0x0003C SM_WDT_MASK          (RW)
///               ###
///               * SM WDT Mask
///               ###
///               %unsigned 3  SM_RST                    0x7
///                                    ###
///                                    * WDT reset mask bit for SM reset signal.
///                                    * 1 : disable WDT (0,1,2) timeout to reset SM for each WDT
///                                    ###
///               %unsigned 3  SOC_RST                   0x7
///                                    ###
///                                    * WDT reset mask bit for SOC reset signal.
///                                    * 1 : disable WDT (0,1,2) timeout to reset SOC for each WDT
///                                    ###
///               %%        26         # Stuffing bits...
///     @ 0x00040 SM_CLK_CTRL          (RW)
///               ###
///               * SM Clock control register
///               ###
///               %unsigned 1  tsenClkSel                0x0
///                                    ###
///                                    * Tsen clock select
///                                    * 0 : 2.5MHz
///                                    * 1 : 1.25MHz
///                                    ###
///               %unsigned 1  tsenClkEn                 0x1
///                                    ###
///                                    * Tsen Clock Enable
///                                    * 0 : disabled
///                                    * 1 : enabled
///                                    ###
///               %unsigned 1  ssmiiTxClkSel             0x0
///                                    ###
///                                    * SSMI Interface transmit clock select
///                                    * 0 : 2.5MHz
///                                    * 1 : 25MHz
///                                    ###
///               %unsigned 1  ssmiiTxClkEn              0x1
///                                    ###
///                                    * SSMI Interface transmit clock enable
///                                    * 0 : disabled
///                                    * 1 : enabled
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00044 smAnaGrpCtl          (P-)
///               ###
///               * SM Analog group registers
///               ###
///               %unsigned 1  pu                        0x1
///                                    ###
///                                    * Power-up signal for the whole block
///                                    * 1: power-up
///                                    * 0: power-down
///                                    ###
///               %unsigned 2  bgSel                     0x1
///                                    ###
///                                    * Selects the reference Voltage
///                                    * 00:0.575V
///                                    * 01:0.6V
///                                    * 10:0.625V
///                                    * 11:0.65V
///                                    ###
///               %unsigned 1  puXtl                     0x1
///                                    ###
///                                    * Power-up signal for the XTL OSC circuit.
///                                    * 1: Power-up XTAL
///                                    * 0: power-down XTAL
///                                    ###
///               %unsigned 1  bypass                    0x0
///                                    ###
///                                    * OSC bypass control
///                                    * 1: in bypass mode
///                                    * 0: in osc mode
///                                    * **INTERNAL_ONLY***
///                                    ###
///               %unsigned 1  gainX2                    0x0
///                                    ###
///                                    * Gain control
///                                    * 1: 2x buffer size 30M-50MHz
///                                    * 0: 1x buffer size 10-30MHz
///                                    ###
///               %unsigned 2  selClkDigDiv1             0x0
///                                    ###
///                                    * Selection of clock division ratio for CLKOUT_DIG[0]
///                                    * 00: divided by 1
///                                    * 01: divided by 2
///                                    * 10: divided by 4
///                                    * 11: divided by 8
///                                    ###
///               %unsigned 2  selClkDigDiv2             0x0
///                                    ###
///                                    * Selection of clock division ratio for CLKOUT_DIG[1]
///                                    * 00: divided by 1
///                                    * 01: divided by 2
///                                    * 10: divided by 4
///                                    * 11: divided by 8
///                                    ###
///               %unsigned 2  selClkDigDiv3             0x0
///                                    ###
///                                    * Selection of clock division ratio for CLKOUT_DIG[2]
///                                    * 00: divided by 1
///                                    * 01: divided by 2
///                                    * 10: divided by 4
///                                    * 11: divided by 8
///                                    ###
///               %unsigned 2  selClkDigDiv4             0x0
///                                    ###
///                                    * Selection of clock division ratio for CLKOUT_DIG[3]
///                                    * 00: divided by 1
///                                    * 01: divided by 2
///                                    * 10: divided by 4
///                                    * 11: divided by 8
///                                    ###
///               %unsigned 1  puOsc                     0x0
///                                    ###
///                                    * Power-up control for the free-running ring oscillator
///                                    ###
///               %unsigned 2  speedOsc                  0x2
///                                    ###
///                                    * Speed selection for the frequency of CLKOUT_OSC
///                                    * 00: 9 MHz +/-20%
///                                    * 01: 12MHz +/-20%
///                                    * 10: 16 MHz +/-20%
///                                    * 11: 20 MHz +/-20%
///                                    ###
///               %unsigned 4  testAna                   0x0
///                                    ###
///                                    * Analog test control bits.
///                                    ###
///               %unsigned 1  bgRdy                     0x0
///                                    ###
///                                    * BG Ready status bit.
///                                    ###
///               %unsigned 10 reserve_in                0x1AF
///                                    ###
///                                    * Reserved Input Register Pins
///                                    ###
///     # 0x00048 smAnaGrpCtl1         
///               %unsigned 1  xtl_pecl_sel              0x1
///                                    ###
///                                    * Choose Regulator Supply “ON”
///                                    * For XTAL Or PECL “On”
///                                    * When XTL_PECL_SEL = 1, PU_XTL = 1, regulator supply for XTAL ON, regulator supply for PECL OFF then choose XTAL output clock for final clock CLKOUT_ANA[3:0], CLKOUT_DIG[3:0] and REFCLKC1, REFCLKC2.
///                                    * When XTL_PECL_SEL= 0, PU_PECL= 1 then choose output clock CLKOUT_ANA[3:0], CLKOUT_DIG[3:0] , REFCLKC1 and REFCLKC2 from PECL output.
///                                    ###
///               %unsigned 2  vreg_1p2v_sel             0x1
///                                    ###
///                                    * XTAL 1.2V Select. Selects 1.2V voltage for the crystal. (XTAL_VDDR1P2V)
///                                    * 00: 1.116V
///                                    * 01: 1.2V
///                                    * 10: 1.24V
///                                    * 11: 1.28V.
///                                    ###
///               %unsigned 3  vreg_1p05v_sel_xtl        0x3
///                                    ###
///                                    * Regulator1.05V Select. Voltage(XTAL_VDDR1P05V)
///                                    * 000: XTAL_VDDR1P2-10mV*21
///                                    * 001: XTAL_VDDR1P2-10mV*19
///                                    * 010: XTAL_VDDR1P2-10mV*17
///                                    * 011: XTAL_VDDR1P2-10mV*15
///                                    * 100: XTAL_VDDR1P2-10mV*13
///                                    * 101: XTAL_VDDR1P2-10mV*11
///                                    * 110: XTAL_VDDR1P2-10mV*9
///                                    * 111: XTAL_VDDR1P2-10mV*7
///                                    ###
///               %unsigned 3  vreg_1p05v_sel_pecl       0x3
///                                    ###
///                                    * Regulator1.05V Select. Voltage(PECL_VDDR1P05V)
///                                    * 000: XTAL_VDDR1P2-10 mV*21
///                                    * 001: XTAL_VDDR1P2-10 mV*19
///                                    * 010: XTAL_VDDR1P2-10 mV*17
///                                    * 011: XTAL_VDDR1P2-10 mV*15
///                                    * 100: XTAL_VDDR1P2-10 mV*13
///                                    * 101: XTAL_VDDR1P2-10 mV*11
///                                    * 110: XTAL_VDDR1P2-10 mV*9
///                                    * 111: XTAL_VDDR1P2-10 mV*7
///                                    ###
///               %unsigned 1  term                      0x1
///                                    ###
///                                    * PECL Internal Block Common Mode Voltage Control. When PECL_EN = 1,
///                                    * 1. DC coupling:
///                                    * common mode 1.0V ~1.2V TERM = 0
///                                    * common mode1.2V~1.4V TERM = 1
///                                    * 2. Input clock AC coupling, TERM must be set to 0.
///                                    * When PECL_EN = 0, set TERM = 1.
///                                    ###
///               %unsigned 1  pu_pecl                   0x0
///                                    ###
///                                    * Power-Up Signal For PECL Circuit Select.
///                                    * 1: Power-up PECL
///                                    * 0: Power-down PECL
///                                    ###
///               %unsigned 1  pecl_en                   0x0
///                                    ###
///                                    * PECL Level or CMOS Level Input Port Select.
///                                    * 1: REFCLKP and REFCLKN are PECL level differential input.
///                                    * 0: REFCLKP and REFCLKN are CMOS level input from the REFCLKP port.
///                                    ###
///               %unsigned 1  pu_limiter                0x0
///                                    ###
///                                    * Power-Up Signal For Limiter Circuit Select.
///                                    * 1: Power-up limiter
///                                    * 0: power-down limiter
///                                    ###
///               %unsigned 1  limiter_dc_clk_en         0x0
///                                    ###
///                                    * When = 0, LIMITER_DC_CLK has no clock output
///                                    * When = 1, LIMITER_DC_CLK has clock output.
///                                    ###
///               %unsigned 2  ipp_adj                   0x1
///                                    ###
///                                    * IPP_ADJ Current Select.
///                                    * IPP_ADJ[1:0] IPP Current
///                                    * 00 .........................197%
///                                    * 01 .........................100%
///                                    * 10..........................103%
///                                    * 111........................ 107%
///                                    ###
///               %unsigned 2  icc_adj                   0x1
///                                    ###
///                                    * ICC_ADJ Current Select.
///                                    * ICC_ADJ[1:0] ICC Current
///                                    * 00 .........................197%
///                                    * 01 .........................100%
///                                    * 10..........................103%
///                                    * 111........................ 107%
///                                    ###
///               %unsigned 2  ixtal                     0x1
///                                    ###
///                                    * XTAL Block Current Change.
///                                    * 00: 100 uA
///                                    * 01: 150 uA
///                                    * 10: 200 uA
///                                    * 11: 250 uA.
///                                    ###
///               %unsigned 1  icc10u_in_sel             0x0
///                                    ###
///                                    * CLKOUT_OSC ICC Current Select
///                                    * 1: Use external ICC current for CLKOUT_OSC. Feed external constant 10 uA current to ICC10U_IN.
///                                    * 0: Use internal ICC current for CLKOUT_OSC. ICC10U_IN can be tied low.
///                                    ###
///               %unsigned 6  reserve_out               0x3F
///                                    ###
///                                    * Reserve Out
///                                    ###
///               %%        5          # Stuffing bits...
///     @ 0x0004C SM_CORE_CTRL         (RW)
///               ###
///               * SM core control for pad(padring 1)
///               ###
///               %unsigned 1  PAD_REG_PDB_CORE          0x1
///               %unsigned 1  PAD_V18EN_CORE            0x0
///               %unsigned 1  PAD_V25EN_CORE            0x0
///               %unsigned 4  PAD_ZP                    0x0
///               %unsigned 4  PAD_ZN                    0x0
///               %%        21         # Stuffing bits...
///     @ 0x00050 SM_TEST              (R-)
///               ###
///               * SM ADC Test Results
///               ###
///               %unsigned 1  ADC_TEST_FAIL             0x0
///                                    ###
///                                    * ADC Test result bit
///                                    * 1: ADC data is not in the valid window
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00054 SM_TEST_DATA0        (RW)
///               ###
///               * SM ADC Test Registers High
///               ###
///               %unsigned 10 ADC_DATA_HIGH             0x0
///                                    ###
///                                    * ADC test data upper boundary
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00058 SM_TEST_DATA1        (RW)
///               ###
///               * SM ADC Test Registers Low
///               ###
///               %unsigned 10 ADC_DATA_LOW              0x0
///                                    ###
///                                    * ADC test data Lower boundary
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x0005C SM_RWTC_CTRL_0       (RW)
///               ###
///               * SM memory strength control register 0
///               ###
///               %unsigned 4  RF1P_LOW                  0xA
///                                    ###
///                                    * RF1P memory RWTC control for LOW SPEED
///                                    ###
///               %unsigned 4  RF1P_HIGH                 0xA
///                                    ###
///                                    * RF1P memory RWTC control for HIGH SPEED
///                                    ###
///               %unsigned 4  RF2P_LOW                  0x9
///                                    ###
///                                    * RF2P memory RWTC control for LOW SPEED
///                                    ###
///               %unsigned 4  RF2P_HIGH                 0x9
///                                    ###
///                                    * RF2P memory RWTC control for HIGH SPEED
///                                    ###
///               %unsigned 4  SR1P_LOW                  0xA
///                                    ###
///                                    * SR1P memory RWTC control for LOW SPEED
///                                    ###
///               %unsigned 4  SR1P_HIGH                 0xA
///                                    ###
///                                    * SR1P memory RWTC control for HIGH SPEED
///                                    ###
///               %unsigned 4  SR2P_LOW                  0xA
///                                    ###
///                                    * SR2P memory RWTC control for LOW SPEED
///                                    ###
///               %unsigned 4  SR2P_HIGH                 0xA
///                                    ###
///                                    * SR2P memory RWTC control for HIGH SPEED
///                                    ###
///     @ 0x00060 SM_RWTC_CTRL_1       (RW)
///               ###
///               * SM memory strength control register 1
///               ###
///               %unsigned 5  ROM_LOW                   0x1A
///                                    ###
///                                    * ROM memory RWTC control for LOW SPEED
///                                    ###
///               %unsigned 5  ROM_HIGH                  0x1A
///                                    ###
///                                    * ROM memory RWTC control for HIGH SPEED
///                                    ###
///               %unsigned 4  ACMEM                     0x5
///                                    ###
///                                    * AC memory RTC control for HIGH SPEED
///                                    ###
///               %%        18         # Stuffing bits...
///     @ 0x00064 SM_PORT_SEL_CTRL     (RW)
///               %unsigned 1  TW2                       0x0
///                                    ###
///                                    * 0: use SM_SPI2_SS2n and SM_SPI2_SS2n
///                                    * 1: use SM_URT0_CTSn and SM_URT0_RTSn
///                                    ###
///               %unsigned 1  URT1                      0x0
///                                    ###
///                                    * 0: use SM_URT1_RXD and SM_URT1_TXD
///                                    * 1: use SM_URT0_CTSn and SM_URT0_RTSn
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00068 TSEN_ADC_RAW_DATA    (R-)
///               ###
///               * SM TSEN ADC RAW DATA for debug purpose
///               ###
///               %unsigned 12 TSEN_DATA_RAW             0x0
///                                    ###
///                                    * ADC 12-bit raw data for debug purpose
///                                    ###
///               %%        20         # Stuffing bits...
///     @ 0x0006C TSEN_ADC_CLK_DIV     (RW)
///               ###
///               * TSEN ADC_clock dividers
///               ###
///               %unsigned 3  ADC_DIV                   0x0
///               %unsigned 4  TSEN_DIV                  0x1
///                                    ###
///                                    * Clock divider set. Select TSEN internal operating frequency.
///                                    * 0000: divide-by-32.(500KHz if main clock is 16MHz).
///                                    * 0001: divide-by-48. (500KHz~521KHz if main clock is 24MHz~25MHz).
///                                    * 0010: divide-by-64. (500KHz if main clock is 32MHz).
///                                    * 0011: divide-by-80. (450KHz~550KHz if main clock is 36MHz~44MHz).
///                                    * 0100: divide-by-94. (468KHz~532KHz if main clock is 44MHz~50MHz).
///                                    * 0101: divide-by-112. (450KHz~550KHz if main clock is 50.4MHz~61.5MHz).
///                                    * 0110: divide-by-132. (466KHz~532KHz if main clock is 61.5MHz~70.2MHz).
///                                    * 0111: divide-by-150. (468KHz~528KHz if main clock is 70.2MHz~79.2MHz).
///                                    * 1000: divide-by-168. (471KHz~524KHz if main clock is 79.2MHz~88MHz).
///                                    * 1001: divide-by-184. (478KHz~526KHz if main clock is 88MHz~96.8MHz).
///                                    * 1010: divide-by-210. (461KHz~545KHz if main clock is 96.8MHz~114.4MHz).
///                                    * 1011: divide-by-246. - 13 – (465KHz~537KHz if main clock is 114.4MHz~132MHz).
///                                    * 1100: divide-by-282. (468KHz~530KHz if main clock is 132MHz~149.6MHz).
///                                    * 1101: divide-by-326. (459KHz~540KHz if main clock is 149.6MHz~176MHz).
///                                    * 1110: divide-by-376. (468KHz~532KHz if main clock is 176MHz~200MHz).
///                                    * 1111 reserved
///                                    ###
///               %%        25         # Stuffing bits...
///     @ 0x00070 TSEN_ADC_CTRL        (RW)
///               ###
///               * TSEN ADC control registers
///               ###
///               %unsigned 8  ADC_VREF_ADJ              0x34
///                                    ###
///                                    * Used for trimming the reference voltage based on correction factors determined during manufacturing test.
///                                    ###
///               %unsigned 1  TSEN_START                0x0
///               %unsigned 3  TSEN_AVG_NUM              0x3
///                                    ###
///                                    * Temperature measurement result averaging:
///                                    * 000: no average
///                                    * 001: average 2
///                                    * 010: average 4
///                                    * 011: average 8
///                                    * 100: reserved
///                                    * 101: reserved
///                                    * 110: reserved
///                                    * 111: reserved
///                                    ###
///               %unsigned 1  TSEN_EXT_EN               0x0
///               %unsigned 2  TSEN_CHOP_EN              0x3
///                                    ###
///                                    * Chopper enable bits.
///                                    * 00: all choppers are off.
///                                    * 01: TSEN chopper is on, cap swap is off
///                                    * 10: TSEN cap swap is off, cap swap is on
///                                    * 11: all choppers are on
///                                    ###
///               %unsigned 2  TSEN_CAL                  0x2
///                                    ###
///                                    * ADC foreground calibration select
///                                    * 00: automatic self-cal skipped, TSEN in normal mode.
///                                    * 01: automatic self-cal skipped, TSEN in ADC gain cal mode.
///                                    * 10: automatic self-cal enforced, TSEN in normal mode.
///                                    * 11: automatic self-cal enforced, TSEN in ADC gain cal mode.
///                                    ###
///               %unsigned 4  TSEN_RSVD                 0xC
///                                    ###
///                                    * Reserved bits.
///                                    ###
///               %unsigned 1  BG_CHP_SEL                0x0
///                                    ###
///                                    * Chopper enable signal(1.1V):
///                                    * 0 disable, the settling time is 4us,
///                                    * 1 enable, the settling time is 12us0
///                                    ###
///               %unsigned 4  BG_DTRIM                  0x7
///                                    ###
///                                    * Band gap curve trimming control signal(1.1V)
///                                    * 0000:1.219V
///                                    * .
///                                    * 0111:1.232V
///                                    * 1111:1.247V
///                                    ###
///               %%        6          # Stuffing bits...
///     @ 0x00074 TSEN_ADC_DBG         (RW)
///               ###
///               * Tsen ADC debug register.
///               ###
///               %unsigned 2  TSEN_RAW_SEL              0x0
///                                    ###
///                                    * Default 2'b00
///                                    * Digital raw data select bits:
///                                    * '00' =12-b post-avg post_cal tsen measurement data in code (Raw1 reg)
///                                    * '01' =12-b post-avg but pre-cal tsen measurement data in code (Raw2 reg)
///                                    * '10' = 12-b self cal data in code (Raw3 reg)
///                                    * '11' =12-b pre-avg tsen measurement data in code (Raw4 reg)
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00078 SM_DUMMY_REG         (RW)
///               ###
///               * Dummy Register for ECOs and Etc
///               ###
///               %unsigned 32 REG0                      0x0
///                                    ###
///                                    * 32-bit Dummy Spare Register
///                                    ###
///     @ 0x0007C                      (W-)
///     #         # Stuffing bytes...
///               %% 3104
///     @ 0x00200 smPinMuxCntlBus      (P-)
///               %unsigned 3  SM_TMS                    0x0
///                                    ###
///                                    * smPinMuxCntlBus[0*3+2:0*3]	 pinMux Control for SM_TMS
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  SM_TDI                    0x0
///                                    ###
///                                    * smPinMuxCntlBus[1*3+2:1*3]	 pinMux Control for SM_TDI
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  SM_TDO                    0x0
///                                    ###
///                                    * smPinMuxCntlBus[2*3+2:2*3]	 pinMux Control for SM_TDO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %%        23         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     516B, bits:     451b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_smSysCtl
#define h_smSysCtl (){}

    #define     RA_smSysCtl_SM_ID                              0x0000

    #define     BA_smSysCtl_SM_ID_REV_ID                       0x0000
    #define     B16smSysCtl_SM_ID_REV_ID                       0x0000
    #define   LSb32smSysCtl_SM_ID_REV_ID                          0
    #define   LSb16smSysCtl_SM_ID_REV_ID                          0
    #define       bsmSysCtl_SM_ID_REV_ID                       4
    #define   MSK32smSysCtl_SM_ID_REV_ID                          0x0000000F

    #define     BA_smSysCtl_SM_ID_PART_ID                      0x0000
    #define     B16smSysCtl_SM_ID_PART_ID                      0x0000
    #define   LSb32smSysCtl_SM_ID_PART_ID                         4
    #define   LSb16smSysCtl_SM_ID_PART_ID                         4
    #define       bsmSysCtl_SM_ID_PART_ID                      16
    #define   MSK32smSysCtl_SM_ID_PART_ID                         0x000FFFF0

    #define     BA_smSysCtl_SM_ID_MFC_ID                       0x0002
    #define     B16smSysCtl_SM_ID_MFC_ID                       0x0002
    #define   LSb32smSysCtl_SM_ID_MFC_ID                          20
    #define   LSb16smSysCtl_SM_ID_MFC_ID                          4
    #define       bsmSysCtl_SM_ID_MFC_ID                       12
    #define   MSK32smSysCtl_SM_ID_MFC_ID                          0xFFF00000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_CPU_CTRL                        0x0004

    #define     BA_smSysCtl_SM_CPU_CTRL_CPU_RST_GO             0x0004
    #define     B16smSysCtl_SM_CPU_CTRL_CPU_RST_GO             0x0004
    #define   LSb32smSysCtl_SM_CPU_CTRL_CPU_RST_GO                0
    #define   LSb16smSysCtl_SM_CPU_CTRL_CPU_RST_GO                0
    #define       bsmSysCtl_SM_CPU_CTRL_CPU_RST_GO             1
    #define   MSK32smSysCtl_SM_CPU_CTRL_CPU_RST_GO                0x00000001

    #define     BA_smSysCtl_SM_CPU_CTRL_CPU_VINITHI            0x0004
    #define     B16smSysCtl_SM_CPU_CTRL_CPU_VINITHI            0x0004
    #define   LSb32smSysCtl_SM_CPU_CTRL_CPU_VINITHI               1
    #define   LSb16smSysCtl_SM_CPU_CTRL_CPU_VINITHI               1
    #define       bsmSysCtl_SM_CPU_CTRL_CPU_VINITHI            1
    #define   MSK32smSysCtl_SM_CPU_CTRL_CPU_VINITHI               0x00000002

    #define     BA_smSysCtl_SM_CPU_CTRL_CPU_INITRAM            0x0004
    #define     B16smSysCtl_SM_CPU_CTRL_CPU_INITRAM            0x0004
    #define   LSb32smSysCtl_SM_CPU_CTRL_CPU_INITRAM               2
    #define   LSb16smSysCtl_SM_CPU_CTRL_CPU_INITRAM               2
    #define       bsmSysCtl_SM_CPU_CTRL_CPU_INITRAM            1
    #define   MSK32smSysCtl_SM_CPU_CTRL_CPU_INITRAM               0x00000004

    #define     BA_smSysCtl_SM_CPU_CTRL_CPU_BIGEND             0x0004
    #define     B16smSysCtl_SM_CPU_CTRL_CPU_BIGEND             0x0004
    #define   LSb32smSysCtl_SM_CPU_CTRL_CPU_BIGEND                3
    #define   LSb16smSysCtl_SM_CPU_CTRL_CPU_BIGEND                3
    #define       bsmSysCtl_SM_CPU_CTRL_CPU_BIGEND             1
    #define   MSK32smSysCtl_SM_CPU_CTRL_CPU_BIGEND                0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_RST_CTRL                        0x0008

    #define     BA_smSysCtl_SM_RST_CTRL_SOC_RST_GO             0x0008
    #define     B16smSysCtl_SM_RST_CTRL_SOC_RST_GO             0x0008
    #define   LSb32smSysCtl_SM_RST_CTRL_SOC_RST_GO                0
    #define   LSb16smSysCtl_SM_RST_CTRL_SOC_RST_GO                0
    #define       bsmSysCtl_SM_RST_CTRL_SOC_RST_GO             1
    #define   MSK32smSysCtl_SM_RST_CTRL_SOC_RST_GO                0x00000001

    #define     BA_smSysCtl_SM_RST_CTRL_APB_RST_GO             0x0008
    #define     B16smSysCtl_SM_RST_CTRL_APB_RST_GO             0x0008
    #define   LSb32smSysCtl_SM_RST_CTRL_APB_RST_GO                1
    #define   LSb16smSysCtl_SM_RST_CTRL_APB_RST_GO                1
    #define       bsmSysCtl_SM_RST_CTRL_APB_RST_GO             1
    #define   MSK32smSysCtl_SM_RST_CTRL_APB_RST_GO                0x00000002

    #define     BA_smSysCtl_SM_RST_CTRL_SXBAR_RST_GO           0x0008
    #define     B16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO           0x0008
    #define   LSb32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO              2
    #define   LSb16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO              2
    #define       bsmSysCtl_SM_RST_CTRL_SXBAR_RST_GO           1
    #define   MSK32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO              0x00000004

    #define     BA_smSysCtl_SM_RST_CTRL_WOL_RST_GO             0x0008
    #define     B16smSysCtl_SM_RST_CTRL_WOL_RST_GO             0x0008
    #define   LSb32smSysCtl_SM_RST_CTRL_WOL_RST_GO                3
    #define   LSb16smSysCtl_SM_RST_CTRL_WOL_RST_GO                3
    #define       bsmSysCtl_SM_RST_CTRL_WOL_RST_GO             1
    #define   MSK32smSysCtl_SM_RST_CTRL_WOL_RST_GO                0x00000008

    #define     BA_smSysCtl_SM_RST_CTRL_FEPHY_RST_GO           0x0008
    #define     B16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO           0x0008
    #define   LSb32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO              4
    #define   LSb16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO              4
    #define       bsmSysCtl_SM_RST_CTRL_FEPHY_RST_GO           1
    #define   MSK32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO              0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_RST_STATUS                      0x000C

    #define     BA_smSysCtl_SM_RST_STATUS_RST_WD_0             0x000C
    #define     B16smSysCtl_SM_RST_STATUS_RST_WD_0             0x000C
    #define   LSb32smSysCtl_SM_RST_STATUS_RST_WD_0                0
    #define   LSb16smSysCtl_SM_RST_STATUS_RST_WD_0                0
    #define       bsmSysCtl_SM_RST_STATUS_RST_WD_0             1
    #define   MSK32smSysCtl_SM_RST_STATUS_RST_WD_0                0x00000001

    #define     BA_smSysCtl_SM_RST_STATUS_RST_WD_1             0x000C
    #define     B16smSysCtl_SM_RST_STATUS_RST_WD_1             0x000C
    #define   LSb32smSysCtl_SM_RST_STATUS_RST_WD_1                1
    #define   LSb16smSysCtl_SM_RST_STATUS_RST_WD_1                1
    #define       bsmSysCtl_SM_RST_STATUS_RST_WD_1             1
    #define   MSK32smSysCtl_SM_RST_STATUS_RST_WD_1                0x00000002

    #define     BA_smSysCtl_SM_RST_STATUS_RST_WD_2             0x000C
    #define     B16smSysCtl_SM_RST_STATUS_RST_WD_2             0x000C
    #define   LSb32smSysCtl_SM_RST_STATUS_RST_WD_2                2
    #define   LSb16smSysCtl_SM_RST_STATUS_RST_WD_2                2
    #define       bsmSysCtl_SM_RST_STATUS_RST_WD_2             1
    #define   MSK32smSysCtl_SM_RST_STATUS_RST_WD_2                0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_STRP_STATUS                     0x0010

    #define     BA_smSysCtl_SM_STRP_STATUS_BOOT_MODE           0x0010
    #define     B16smSysCtl_SM_STRP_STATUS_BOOT_MODE           0x0010
    #define   LSb32smSysCtl_SM_STRP_STATUS_BOOT_MODE              0
    #define   LSb16smSysCtl_SM_STRP_STATUS_BOOT_MODE              0
    #define       bsmSysCtl_SM_STRP_STATUS_BOOT_MODE           2
    #define   MSK32smSysCtl_SM_STRP_STATUS_BOOT_MODE              0x00000003

    #define     BA_smSysCtl_SM_STRP_STATUS_STRP_2              0x0010
    #define     B16smSysCtl_SM_STRP_STATUS_STRP_2              0x0010
    #define   LSb32smSysCtl_SM_STRP_STATUS_STRP_2                 2
    #define   LSb16smSysCtl_SM_STRP_STATUS_STRP_2                 2
    #define       bsmSysCtl_SM_STRP_STATUS_STRP_2              1
    #define   MSK32smSysCtl_SM_STRP_STATUS_STRP_2                 0x00000004

    #define     BA_smSysCtl_SM_STRP_STATUS_STRP_3              0x0010
    #define     B16smSysCtl_SM_STRP_STATUS_STRP_3              0x0010
    #define   LSb32smSysCtl_SM_STRP_STATUS_STRP_3                 3
    #define   LSb16smSysCtl_SM_STRP_STATUS_STRP_3                 3
    #define       bsmSysCtl_SM_STRP_STATUS_STRP_3              1
    #define   MSK32smSysCtl_SM_STRP_STATUS_STRP_3                 0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_CTRL                            0x0014

    #define     BA_smSysCtl_SM_CTRL_ISO_EN                     0x0014
    #define     B16smSysCtl_SM_CTRL_ISO_EN                     0x0014
    #define   LSb32smSysCtl_SM_CTRL_ISO_EN                        0
    #define   LSb16smSysCtl_SM_CTRL_ISO_EN                        0
    #define       bsmSysCtl_SM_CTRL_ISO_EN                     1
    #define   MSK32smSysCtl_SM_CTRL_ISO_EN                        0x00000001

    #define     BA_smSysCtl_SM_CTRL_SM2SOC_SW_INTR             0x0014
    #define     B16smSysCtl_SM_CTRL_SM2SOC_SW_INTR             0x0014
    #define   LSb32smSysCtl_SM_CTRL_SM2SOC_SW_INTR                1
    #define   LSb16smSysCtl_SM_CTRL_SM2SOC_SW_INTR                1
    #define       bsmSysCtl_SM_CTRL_SM2SOC_SW_INTR             1
    #define   MSK32smSysCtl_SM_CTRL_SM2SOC_SW_INTR                0x00000002

    #define     BA_smSysCtl_SM_CTRL_SOC2SM_SW_INTR             0x0014
    #define     B16smSysCtl_SM_CTRL_SOC2SM_SW_INTR             0x0014
    #define   LSb32smSysCtl_SM_CTRL_SOC2SM_SW_INTR                2
    #define   LSb16smSysCtl_SM_CTRL_SOC2SM_SW_INTR                2
    #define       bsmSysCtl_SM_CTRL_SOC2SM_SW_INTR             1
    #define   MSK32smSysCtl_SM_CTRL_SOC2SM_SW_INTR                0x00000004

    #define     BA_smSysCtl_SM_CTRL_REV_0                      0x0014
    #define     B16smSysCtl_SM_CTRL_REV_0                      0x0014
    #define   LSb32smSysCtl_SM_CTRL_REV_0                         3
    #define   LSb16smSysCtl_SM_CTRL_REV_0                         3
    #define       bsmSysCtl_SM_CTRL_REV_0                      2
    #define   MSK32smSysCtl_SM_CTRL_REV_0                         0x00000018

    #define     BA_smSysCtl_SM_CTRL_ADC_SEL                    0x0014
    #define     B16smSysCtl_SM_CTRL_ADC_SEL                    0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_SEL                       5
    #define   LSb16smSysCtl_SM_CTRL_ADC_SEL                       5
    #define       bsmSysCtl_SM_CTRL_ADC_SEL                    4
    #define   MSK32smSysCtl_SM_CTRL_ADC_SEL                       0x000001E0

    #define     BA_smSysCtl_SM_CTRL_ADC_PU                     0x0015
    #define     B16smSysCtl_SM_CTRL_ADC_PU                     0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_PU                        9
    #define   LSb16smSysCtl_SM_CTRL_ADC_PU                        9
    #define       bsmSysCtl_SM_CTRL_ADC_PU                     1
    #define   MSK32smSysCtl_SM_CTRL_ADC_PU                        0x00000200

    #define     BA_smSysCtl_SM_CTRL_ADC_CKSEL                  0x0015
    #define     B16smSysCtl_SM_CTRL_ADC_CKSEL                  0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_CKSEL                     10
    #define   LSb16smSysCtl_SM_CTRL_ADC_CKSEL                     10
    #define       bsmSysCtl_SM_CTRL_ADC_CKSEL                  2
    #define   MSK32smSysCtl_SM_CTRL_ADC_CKSEL                     0x00000C00

    #define     BA_smSysCtl_SM_CTRL_ADC_START                  0x0015
    #define     B16smSysCtl_SM_CTRL_ADC_START                  0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_START                     12
    #define   LSb16smSysCtl_SM_CTRL_ADC_START                     12
    #define       bsmSysCtl_SM_CTRL_ADC_START                  1
    #define   MSK32smSysCtl_SM_CTRL_ADC_START                     0x00001000

    #define     BA_smSysCtl_SM_CTRL_ADC_RESET                  0x0015
    #define     B16smSysCtl_SM_CTRL_ADC_RESET                  0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_RESET                     13
    #define   LSb16smSysCtl_SM_CTRL_ADC_RESET                     13
    #define       bsmSysCtl_SM_CTRL_ADC_RESET                  1
    #define   MSK32smSysCtl_SM_CTRL_ADC_RESET                     0x00002000

    #define     BA_smSysCtl_SM_CTRL_ADC_BG_RDY                 0x0015
    #define     B16smSysCtl_SM_CTRL_ADC_BG_RDY                 0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_BG_RDY                    14
    #define   LSb16smSysCtl_SM_CTRL_ADC_BG_RDY                    14
    #define       bsmSysCtl_SM_CTRL_ADC_BG_RDY                 1
    #define   MSK32smSysCtl_SM_CTRL_ADC_BG_RDY                    0x00004000

    #define     BA_smSysCtl_SM_CTRL_ADC_CONT                   0x0015
    #define     B16smSysCtl_SM_CTRL_ADC_CONT                   0x0014
    #define   LSb32smSysCtl_SM_CTRL_ADC_CONT                      15
    #define   LSb16smSysCtl_SM_CTRL_ADC_CONT                      15
    #define       bsmSysCtl_SM_CTRL_ADC_CONT                   1
    #define   MSK32smSysCtl_SM_CTRL_ADC_CONT                      0x00008000

    #define     BA_smSysCtl_SM_CTRL_ADC_BUF_EN                 0x0016
    #define     B16smSysCtl_SM_CTRL_ADC_BUF_EN                 0x0016
    #define   LSb32smSysCtl_SM_CTRL_ADC_BUF_EN                    16
    #define   LSb16smSysCtl_SM_CTRL_ADC_BUF_EN                    0
    #define       bsmSysCtl_SM_CTRL_ADC_BUF_EN                 1
    #define   MSK32smSysCtl_SM_CTRL_ADC_BUF_EN                    0x00010000

    #define     BA_smSysCtl_SM_CTRL_ADC_VREF_SEL               0x0016
    #define     B16smSysCtl_SM_CTRL_ADC_VREF_SEL               0x0016
    #define   LSb32smSysCtl_SM_CTRL_ADC_VREF_SEL                  17
    #define   LSb16smSysCtl_SM_CTRL_ADC_VREF_SEL                  1
    #define       bsmSysCtl_SM_CTRL_ADC_VREF_SEL               1
    #define   MSK32smSysCtl_SM_CTRL_ADC_VREF_SEL                  0x00020000

    #define     BA_smSysCtl_SM_CTRL_ADC_ROTATE_SEL             0x0016
    #define     B16smSysCtl_SM_CTRL_ADC_ROTATE_SEL             0x0016
    #define   LSb32smSysCtl_SM_CTRL_ADC_ROTATE_SEL                18
    #define   LSb16smSysCtl_SM_CTRL_ADC_ROTATE_SEL                2
    #define       bsmSysCtl_SM_CTRL_ADC_ROTATE_SEL             1
    #define   MSK32smSysCtl_SM_CTRL_ADC_ROTATE_SEL                0x00040000

    #define     BA_smSysCtl_SM_CTRL_TSEN_EN                    0x0016
    #define     B16smSysCtl_SM_CTRL_TSEN_EN                    0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_EN                       19
    #define   LSb16smSysCtl_SM_CTRL_TSEN_EN                       3
    #define       bsmSysCtl_SM_CTRL_TSEN_EN                    1
    #define   MSK32smSysCtl_SM_CTRL_TSEN_EN                       0x00080000

    #define     BA_smSysCtl_SM_CTRL_TSEN_CLK_SEL               0x0016
    #define     B16smSysCtl_SM_CTRL_TSEN_CLK_SEL               0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_CLK_SEL                  20
    #define   LSb16smSysCtl_SM_CTRL_TSEN_CLK_SEL                  4
    #define       bsmSysCtl_SM_CTRL_TSEN_CLK_SEL               1
    #define   MSK32smSysCtl_SM_CTRL_TSEN_CLK_SEL                  0x00100000

    #define     BA_smSysCtl_SM_CTRL_TSEN_MODE_SEL              0x0016
    #define     B16smSysCtl_SM_CTRL_TSEN_MODE_SEL              0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_MODE_SEL                 21
    #define   LSb16smSysCtl_SM_CTRL_TSEN_MODE_SEL                 5
    #define       bsmSysCtl_SM_CTRL_TSEN_MODE_SEL              1
    #define   MSK32smSysCtl_SM_CTRL_TSEN_MODE_SEL                 0x00200000

    #define     BA_smSysCtl_SM_CTRL_TSEN_ADC_CAL               0x0016
    #define     B16smSysCtl_SM_CTRL_TSEN_ADC_CAL               0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_ADC_CAL                  22
    #define   LSb16smSysCtl_SM_CTRL_TSEN_ADC_CAL                  6
    #define       bsmSysCtl_SM_CTRL_TSEN_ADC_CAL               2
    #define   MSK32smSysCtl_SM_CTRL_TSEN_ADC_CAL                  0x00C00000

    #define     BA_smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL           0x0017
    #define     B16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL           0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL              24
    #define   LSb16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL              8
    #define       bsmSysCtl_SM_CTRL_TSEN_ADC_TST_SEL           5
    #define   MSK32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL              0x1F000000

    #define     BA_smSysCtl_SM_CTRL_TSEN_RESET                 0x0017
    #define     B16smSysCtl_SM_CTRL_TSEN_RESET                 0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_RESET                    29
    #define   LSb16smSysCtl_SM_CTRL_TSEN_RESET                    13
    #define       bsmSysCtl_SM_CTRL_TSEN_RESET                 1
    #define   MSK32smSysCtl_SM_CTRL_TSEN_RESET                    0x20000000

    #define     BA_smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN            0x0017
    #define     B16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN            0x0016
    #define   LSb32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN               30
    #define   LSb16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN               14
    #define       bsmSysCtl_SM_CTRL_TSEN_ADC_ISO_EN            1
    #define   MSK32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN               0x40000000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_ADC_CTRL                        0x0018

    #define     BA_smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT            0x0018
    #define     B16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT            0x0018
    #define   LSb32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT               0
    #define   LSb16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT               0
    #define       bsmSysCtl_SM_ADC_CTRL_TSEN_DAT_LT            5
    #define   MSK32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT               0x0000001F

    #define     BA_smSysCtl_SM_ADC_CTRL_ADC_DAT_LT             0x0018
    #define     B16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT             0x0018
    #define   LSb32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT                5
    #define   LSb16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT                5
    #define       bsmSysCtl_SM_ADC_CTRL_ADC_DAT_LT             5
    #define   MSK32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT                0x000003E0
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_ADC_STATUS                      0x001C

    #define     BA_smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY            0
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY            0
    #define       bsmSysCtl_SM_ADC_STATUS_CH0_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY            0x00000001

    #define     BA_smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY            1
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY            1
    #define       bsmSysCtl_SM_ADC_STATUS_CH1_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY            0x00000002

    #define     BA_smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY            2
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY            2
    #define       bsmSysCtl_SM_ADC_STATUS_CH2_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY            0x00000004

    #define     BA_smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY            3
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY            3
    #define       bsmSysCtl_SM_ADC_STATUS_CH3_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY            0x00000008

    #define     BA_smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY            4
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY            4
    #define       bsmSysCtl_SM_ADC_STATUS_CH4_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY            0x00000010

    #define     BA_smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY            5
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY            5
    #define       bsmSysCtl_SM_ADC_STATUS_CH5_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY            0x00000020

    #define     BA_smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY            6
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY            6
    #define       bsmSysCtl_SM_ADC_STATUS_CH6_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY            0x00000040

    #define     BA_smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY         0x001C
    #define     B16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY            7
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY            7
    #define       bsmSysCtl_SM_ADC_STATUS_CH7_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY            0x00000080

    #define     BA_smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY         0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY            8
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY            8
    #define       bsmSysCtl_SM_ADC_STATUS_CH8_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY            0x00000100

    #define     BA_smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY         0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY         0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY            9
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY            9
    #define       bsmSysCtl_SM_ADC_STATUS_CH9_DATA_RDY         1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY            0x00000200

    #define     BA_smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY        0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY        0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY           10
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY           10
    #define       bsmSysCtl_SM_ADC_STATUS_CH10_DATA_RDY        1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY           0x00000400

    #define     BA_smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY        0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY        0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY           11
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY           11
    #define       bsmSysCtl_SM_ADC_STATUS_CH11_DATA_RDY        1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY           0x00000800

    #define     BA_smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY        0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY        0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY           12
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY           12
    #define       bsmSysCtl_SM_ADC_STATUS_CH12_DATA_RDY        1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY           0x00001000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY        0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY        0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY           13
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY           13
    #define       bsmSysCtl_SM_ADC_STATUS_CH13_DATA_RDY        1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY           0x00002000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY        0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY        0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY           14
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY           14
    #define       bsmSysCtl_SM_ADC_STATUS_CH14_DATA_RDY        1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY           0x00004000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY        0x001D
    #define     B16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY        0x001C
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY           15
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY           15
    #define       bsmSysCtl_SM_ADC_STATUS_CH15_DATA_RDY        1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY           0x00008000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH0_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH0_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH0_INT_EN              16
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH0_INT_EN              0
    #define       bsmSysCtl_SM_ADC_STATUS_CH0_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH0_INT_EN              0x00010000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH1_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH1_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH1_INT_EN              17
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH1_INT_EN              1
    #define       bsmSysCtl_SM_ADC_STATUS_CH1_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH1_INT_EN              0x00020000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH2_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH2_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH2_INT_EN              18
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH2_INT_EN              2
    #define       bsmSysCtl_SM_ADC_STATUS_CH2_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH2_INT_EN              0x00040000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH3_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH3_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH3_INT_EN              19
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH3_INT_EN              3
    #define       bsmSysCtl_SM_ADC_STATUS_CH3_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH3_INT_EN              0x00080000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH4_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH4_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH4_INT_EN              20
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH4_INT_EN              4
    #define       bsmSysCtl_SM_ADC_STATUS_CH4_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH4_INT_EN              0x00100000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH5_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH5_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH5_INT_EN              21
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH5_INT_EN              5
    #define       bsmSysCtl_SM_ADC_STATUS_CH5_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH5_INT_EN              0x00200000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH6_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH6_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH6_INT_EN              22
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH6_INT_EN              6
    #define       bsmSysCtl_SM_ADC_STATUS_CH6_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH6_INT_EN              0x00400000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH7_INT_EN           0x001E
    #define     B16smSysCtl_SM_ADC_STATUS_CH7_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH7_INT_EN              23
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH7_INT_EN              7
    #define       bsmSysCtl_SM_ADC_STATUS_CH7_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH7_INT_EN              0x00800000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH8_INT_EN           0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH8_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH8_INT_EN              24
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH8_INT_EN              8
    #define       bsmSysCtl_SM_ADC_STATUS_CH8_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH8_INT_EN              0x01000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH9_INT_EN           0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH9_INT_EN           0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH9_INT_EN              25
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH9_INT_EN              9
    #define       bsmSysCtl_SM_ADC_STATUS_CH9_INT_EN           1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH9_INT_EN              0x02000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH10_INT_EN          0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH10_INT_EN          0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH10_INT_EN             26
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH10_INT_EN             10
    #define       bsmSysCtl_SM_ADC_STATUS_CH10_INT_EN          1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH10_INT_EN             0x04000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH11_INT_EN          0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH11_INT_EN          0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH11_INT_EN             27
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH11_INT_EN             11
    #define       bsmSysCtl_SM_ADC_STATUS_CH11_INT_EN          1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH11_INT_EN             0x08000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH12_INT_EN          0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH12_INT_EN          0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH12_INT_EN             28
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH12_INT_EN             12
    #define       bsmSysCtl_SM_ADC_STATUS_CH12_INT_EN          1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH12_INT_EN             0x10000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH13_INT_EN          0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH13_INT_EN          0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH13_INT_EN             29
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH13_INT_EN             13
    #define       bsmSysCtl_SM_ADC_STATUS_CH13_INT_EN          1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH13_INT_EN             0x20000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH14_INT_EN          0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH14_INT_EN          0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH14_INT_EN             30
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH14_INT_EN             14
    #define       bsmSysCtl_SM_ADC_STATUS_CH14_INT_EN          1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH14_INT_EN             0x40000000

    #define     BA_smSysCtl_SM_ADC_STATUS_CH15_INT_EN          0x001F
    #define     B16smSysCtl_SM_ADC_STATUS_CH15_INT_EN          0x001E
    #define   LSb32smSysCtl_SM_ADC_STATUS_CH15_INT_EN             31
    #define   LSb16smSysCtl_SM_ADC_STATUS_CH15_INT_EN             15
    #define       bsmSysCtl_SM_ADC_STATUS_CH15_INT_EN          1
    #define   MSK32smSysCtl_SM_ADC_STATUS_CH15_INT_EN             0x80000000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_ADC_DATA                        0x0020

    #define     BA_smSysCtl_SM_ADC_DATA_ADC_DATA               0x0020
    #define     B16smSysCtl_SM_ADC_DATA_ADC_DATA               0x0020
    #define   LSb32smSysCtl_SM_ADC_DATA_ADC_DATA                  0
    #define   LSb16smSysCtl_SM_ADC_DATA_ADC_DATA                  0
    #define       bsmSysCtl_SM_ADC_DATA_ADC_DATA               10
    #define   MSK32smSysCtl_SM_ADC_DATA_ADC_DATA                  0x000003FF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_ADC_STATUS                    0x0024

    #define     BA_smSysCtl_TSEN_ADC_STATUS_DATA_RDY           0x0024
    #define     B16smSysCtl_TSEN_ADC_STATUS_DATA_RDY           0x0024
    #define   LSb32smSysCtl_TSEN_ADC_STATUS_DATA_RDY              0
    #define   LSb16smSysCtl_TSEN_ADC_STATUS_DATA_RDY              0
    #define       bsmSysCtl_TSEN_ADC_STATUS_DATA_RDY           1
    #define   MSK32smSysCtl_TSEN_ADC_STATUS_DATA_RDY              0x00000001

    #define     BA_smSysCtl_TSEN_ADC_STATUS_INT_EN             0x0024
    #define     B16smSysCtl_TSEN_ADC_STATUS_INT_EN             0x0024
    #define   LSb32smSysCtl_TSEN_ADC_STATUS_INT_EN                1
    #define   LSb16smSysCtl_TSEN_ADC_STATUS_INT_EN                1
    #define       bsmSysCtl_TSEN_ADC_STATUS_INT_EN             1
    #define   MSK32smSysCtl_TSEN_ADC_STATUS_INT_EN                0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_ADC_DATA                      0x0028

    #define     BA_smSysCtl_TSEN_ADC_DATA_ADC_DATA             0x0028
    #define     B16smSysCtl_TSEN_ADC_DATA_ADC_DATA             0x0028
    #define   LSb32smSysCtl_TSEN_ADC_DATA_ADC_DATA                0
    #define   LSb16smSysCtl_TSEN_ADC_DATA_ADC_DATA                0
    #define       bsmSysCtl_TSEN_ADC_DATA_ADC_DATA             12
    #define   MSK32smSysCtl_TSEN_ADC_DATA_ADC_DATA                0x00000FFF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_CHK_CTRL                      0x002C

    #define     BA_smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX        0x002C
    #define     B16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX        0x002C
    #define   LSb32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX           0
    #define   LSb16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX           0
    #define       bsmSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX        12
    #define   MSK32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX           0x00000FFF

    #define     BA_smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN        0x002D
    #define     B16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN        0x002C
    #define   LSb32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN           12
    #define   LSb16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN           12
    #define       bsmSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN        12
    #define   MSK32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN           0x00FFF000

    #define     BA_smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL    0x002F
    #define     B16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL    0x002E
    #define   LSb32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL       24
    #define   LSb16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL       8
    #define       bsmSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL    1
    #define   MSK32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL       0x01000000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_DATA_STATUS                   0x0030

    #define     BA_smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL     0x0030
    #define     B16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL     0x0030
    #define   LSb32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL        0
    #define   LSb16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL        0
    #define       bsmSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL     1
    #define   MSK32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL        0x00000001

    #define     BA_smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL     0x0030
    #define     B16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL     0x0030
    #define   LSb32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL        1
    #define   LSb16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL        1
    #define       bsmSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL     1
    #define   MSK32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL        0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_BOOT_STATUS                     0x0034

    #define     BA_smSysCtl_SM_BOOT_STATUS_MODE                0x0034
    #define     B16smSysCtl_SM_BOOT_STATUS_MODE                0x0034
    #define   LSb32smSysCtl_SM_BOOT_STATUS_MODE                   0
    #define   LSb16smSysCtl_SM_BOOT_STATUS_MODE                   0
    #define       bsmSysCtl_SM_BOOT_STATUS_MODE                32
    #define   MSK32smSysCtl_SM_BOOT_STATUS_MODE                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_LDO_CTRL                        0x0038

    #define     BA_smSysCtl_SM_LDO_CTRL_TEST_SEL               0x0038
    #define     B16smSysCtl_SM_LDO_CTRL_TEST_SEL               0x0038
    #define   LSb32smSysCtl_SM_LDO_CTRL_TEST_SEL                  0
    #define   LSb16smSysCtl_SM_LDO_CTRL_TEST_SEL                  0
    #define       bsmSysCtl_SM_LDO_CTRL_TEST_SEL               3
    #define   MSK32smSysCtl_SM_LDO_CTRL_TEST_SEL                  0x00000007

    #define     BA_smSysCtl_SM_LDO_CTRL_VOUT_SEL               0x0038
    #define     B16smSysCtl_SM_LDO_CTRL_VOUT_SEL               0x0038
    #define   LSb32smSysCtl_SM_LDO_CTRL_VOUT_SEL                  3
    #define   LSb16smSysCtl_SM_LDO_CTRL_VOUT_SEL                  3
    #define       bsmSysCtl_SM_LDO_CTRL_VOUT_SEL               3
    #define   MSK32smSysCtl_SM_LDO_CTRL_VOUT_SEL                  0x00000038

    #define     BA_smSysCtl_SM_LDO_CTRL_TEST_EN                0x0038
    #define     B16smSysCtl_SM_LDO_CTRL_TEST_EN                0x0038
    #define   LSb32smSysCtl_SM_LDO_CTRL_TEST_EN                   6
    #define   LSb16smSysCtl_SM_LDO_CTRL_TEST_EN                   6
    #define       bsmSysCtl_SM_LDO_CTRL_TEST_EN                1
    #define   MSK32smSysCtl_SM_LDO_CTRL_TEST_EN                   0x00000040

    #define     BA_smSysCtl_SM_LDO_CTRL_LDO_RDY                0x0038
    #define     B16smSysCtl_SM_LDO_CTRL_LDO_RDY                0x0038
    #define   LSb32smSysCtl_SM_LDO_CTRL_LDO_RDY                   7
    #define   LSb16smSysCtl_SM_LDO_CTRL_LDO_RDY                   7
    #define       bsmSysCtl_SM_LDO_CTRL_LDO_RDY                1
    #define   MSK32smSysCtl_SM_LDO_CTRL_LDO_RDY                   0x00000080

    #define     BA_smSysCtl_SM_LDO_CTRL_CHP_EN_1P1             0x0039
    #define     B16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1             0x0038
    #define   LSb32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1                8
    #define   LSb16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1                8
    #define       bsmSysCtl_SM_LDO_CTRL_CHP_EN_1P1             1
    #define   MSK32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1                0x00000100

    #define     BA_smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1          0x0039
    #define     B16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1          0x0038
    #define   LSb32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1             9
    #define   LSb16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1             9
    #define       bsmSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1          1
    #define   MSK32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1             0x00000200
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_WDT_MASK                        0x003C

    #define     BA_smSysCtl_SM_WDT_MASK_SM_RST                 0x003C
    #define     B16smSysCtl_SM_WDT_MASK_SM_RST                 0x003C
    #define   LSb32smSysCtl_SM_WDT_MASK_SM_RST                    0
    #define   LSb16smSysCtl_SM_WDT_MASK_SM_RST                    0
    #define       bsmSysCtl_SM_WDT_MASK_SM_RST                 3
    #define   MSK32smSysCtl_SM_WDT_MASK_SM_RST                    0x00000007

    #define     BA_smSysCtl_SM_WDT_MASK_SOC_RST                0x003C
    #define     B16smSysCtl_SM_WDT_MASK_SOC_RST                0x003C
    #define   LSb32smSysCtl_SM_WDT_MASK_SOC_RST                   3
    #define   LSb16smSysCtl_SM_WDT_MASK_SOC_RST                   3
    #define       bsmSysCtl_SM_WDT_MASK_SOC_RST                3
    #define   MSK32smSysCtl_SM_WDT_MASK_SOC_RST                   0x00000038
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_CLK_CTRL                        0x0040

    #define     BA_smSysCtl_SM_CLK_CTRL_tsenClkSel             0x0040
    #define     B16smSysCtl_SM_CLK_CTRL_tsenClkSel             0x0040
    #define   LSb32smSysCtl_SM_CLK_CTRL_tsenClkSel                0
    #define   LSb16smSysCtl_SM_CLK_CTRL_tsenClkSel                0
    #define       bsmSysCtl_SM_CLK_CTRL_tsenClkSel             1
    #define   MSK32smSysCtl_SM_CLK_CTRL_tsenClkSel                0x00000001

    #define     BA_smSysCtl_SM_CLK_CTRL_tsenClkEn              0x0040
    #define     B16smSysCtl_SM_CLK_CTRL_tsenClkEn              0x0040
    #define   LSb32smSysCtl_SM_CLK_CTRL_tsenClkEn                 1
    #define   LSb16smSysCtl_SM_CLK_CTRL_tsenClkEn                 1
    #define       bsmSysCtl_SM_CLK_CTRL_tsenClkEn              1
    #define   MSK32smSysCtl_SM_CLK_CTRL_tsenClkEn                 0x00000002

    #define     BA_smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel          0x0040
    #define     B16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel          0x0040
    #define   LSb32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel             2
    #define   LSb16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel             2
    #define       bsmSysCtl_SM_CLK_CTRL_ssmiiTxClkSel          1
    #define   MSK32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel             0x00000004

    #define     BA_smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn           0x0040
    #define     B16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn           0x0040
    #define   LSb32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn              3
    #define   LSb16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn              3
    #define       bsmSysCtl_SM_CLK_CTRL_ssmiiTxClkEn           1
    #define   MSK32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn              0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_smAnaGrpCtl                        0x0044

    #define     BA_smSysCtl_smAnaGrpCtl_pu                     0x0044
    #define     B16smSysCtl_smAnaGrpCtl_pu                     0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_pu                        0
    #define   LSb16smSysCtl_smAnaGrpCtl_pu                        0
    #define       bsmSysCtl_smAnaGrpCtl_pu                     1
    #define   MSK32smSysCtl_smAnaGrpCtl_pu                        0x00000001

    #define     BA_smSysCtl_smAnaGrpCtl_bgSel                  0x0044
    #define     B16smSysCtl_smAnaGrpCtl_bgSel                  0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_bgSel                     1
    #define   LSb16smSysCtl_smAnaGrpCtl_bgSel                     1
    #define       bsmSysCtl_smAnaGrpCtl_bgSel                  2
    #define   MSK32smSysCtl_smAnaGrpCtl_bgSel                     0x00000006

    #define     BA_smSysCtl_smAnaGrpCtl_puXtl                  0x0044
    #define     B16smSysCtl_smAnaGrpCtl_puXtl                  0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_puXtl                     3
    #define   LSb16smSysCtl_smAnaGrpCtl_puXtl                     3
    #define       bsmSysCtl_smAnaGrpCtl_puXtl                  1
    #define   MSK32smSysCtl_smAnaGrpCtl_puXtl                     0x00000008

    #define     BA_smSysCtl_smAnaGrpCtl_bypass                 0x0044
    #define     B16smSysCtl_smAnaGrpCtl_bypass                 0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_bypass                    4
    #define   LSb16smSysCtl_smAnaGrpCtl_bypass                    4
    #define       bsmSysCtl_smAnaGrpCtl_bypass                 1
    #define   MSK32smSysCtl_smAnaGrpCtl_bypass                    0x00000010

    #define     BA_smSysCtl_smAnaGrpCtl_gainX2                 0x0044
    #define     B16smSysCtl_smAnaGrpCtl_gainX2                 0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_gainX2                    5
    #define   LSb16smSysCtl_smAnaGrpCtl_gainX2                    5
    #define       bsmSysCtl_smAnaGrpCtl_gainX2                 1
    #define   MSK32smSysCtl_smAnaGrpCtl_gainX2                    0x00000020

    #define     BA_smSysCtl_smAnaGrpCtl_selClkDigDiv1          0x0044
    #define     B16smSysCtl_smAnaGrpCtl_selClkDigDiv1          0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv1             6
    #define   LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv1             6
    #define       bsmSysCtl_smAnaGrpCtl_selClkDigDiv1          2
    #define   MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv1             0x000000C0

    #define     BA_smSysCtl_smAnaGrpCtl_selClkDigDiv2          0x0045
    #define     B16smSysCtl_smAnaGrpCtl_selClkDigDiv2          0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv2             8
    #define   LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv2             8
    #define       bsmSysCtl_smAnaGrpCtl_selClkDigDiv2          2
    #define   MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv2             0x00000300

    #define     BA_smSysCtl_smAnaGrpCtl_selClkDigDiv3          0x0045
    #define     B16smSysCtl_smAnaGrpCtl_selClkDigDiv3          0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv3             10
    #define   LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv3             10
    #define       bsmSysCtl_smAnaGrpCtl_selClkDigDiv3          2
    #define   MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv3             0x00000C00

    #define     BA_smSysCtl_smAnaGrpCtl_selClkDigDiv4          0x0045
    #define     B16smSysCtl_smAnaGrpCtl_selClkDigDiv4          0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv4             12
    #define   LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv4             12
    #define       bsmSysCtl_smAnaGrpCtl_selClkDigDiv4          2
    #define   MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv4             0x00003000

    #define     BA_smSysCtl_smAnaGrpCtl_puOsc                  0x0045
    #define     B16smSysCtl_smAnaGrpCtl_puOsc                  0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_puOsc                     14
    #define   LSb16smSysCtl_smAnaGrpCtl_puOsc                     14
    #define       bsmSysCtl_smAnaGrpCtl_puOsc                  1
    #define   MSK32smSysCtl_smAnaGrpCtl_puOsc                     0x00004000

    #define     BA_smSysCtl_smAnaGrpCtl_speedOsc               0x0045
    #define     B16smSysCtl_smAnaGrpCtl_speedOsc               0x0044
    #define   LSb32smSysCtl_smAnaGrpCtl_speedOsc                  15
    #define   LSb16smSysCtl_smAnaGrpCtl_speedOsc                  15
    #define       bsmSysCtl_smAnaGrpCtl_speedOsc               2
    #define   MSK32smSysCtl_smAnaGrpCtl_speedOsc                  0x00018000

    #define     BA_smSysCtl_smAnaGrpCtl_testAna                0x0046
    #define     B16smSysCtl_smAnaGrpCtl_testAna                0x0046
    #define   LSb32smSysCtl_smAnaGrpCtl_testAna                   17
    #define   LSb16smSysCtl_smAnaGrpCtl_testAna                   1
    #define       bsmSysCtl_smAnaGrpCtl_testAna                4
    #define   MSK32smSysCtl_smAnaGrpCtl_testAna                   0x001E0000

    #define     BA_smSysCtl_smAnaGrpCtl_bgRdy                  0x0046
    #define     B16smSysCtl_smAnaGrpCtl_bgRdy                  0x0046
    #define   LSb32smSysCtl_smAnaGrpCtl_bgRdy                     21
    #define   LSb16smSysCtl_smAnaGrpCtl_bgRdy                     5
    #define       bsmSysCtl_smAnaGrpCtl_bgRdy                  1
    #define   MSK32smSysCtl_smAnaGrpCtl_bgRdy                     0x00200000

    #define     BA_smSysCtl_smAnaGrpCtl_reserve_in             0x0046
    #define     B16smSysCtl_smAnaGrpCtl_reserve_in             0x0046
    #define   LSb32smSysCtl_smAnaGrpCtl_reserve_in                22
    #define   LSb16smSysCtl_smAnaGrpCtl_reserve_in                6
    #define       bsmSysCtl_smAnaGrpCtl_reserve_in             10
    #define   MSK32smSysCtl_smAnaGrpCtl_reserve_in                0xFFC00000

    #define     RA_smSysCtl_smAnaGrpCtl1                       0x0048

    #define     BA_smSysCtl_smAnaGrpCtl_xtl_pecl_sel           0x0048
    #define     B16smSysCtl_smAnaGrpCtl_xtl_pecl_sel           0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_xtl_pecl_sel              0
    #define   LSb16smSysCtl_smAnaGrpCtl_xtl_pecl_sel              0
    #define       bsmSysCtl_smAnaGrpCtl_xtl_pecl_sel           1
    #define   MSK32smSysCtl_smAnaGrpCtl_xtl_pecl_sel              0x00000001

    #define     BA_smSysCtl_smAnaGrpCtl_vreg_1p2v_sel          0x0048
    #define     B16smSysCtl_smAnaGrpCtl_vreg_1p2v_sel          0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_vreg_1p2v_sel             1
    #define   LSb16smSysCtl_smAnaGrpCtl_vreg_1p2v_sel             1
    #define       bsmSysCtl_smAnaGrpCtl_vreg_1p2v_sel          2
    #define   MSK32smSysCtl_smAnaGrpCtl_vreg_1p2v_sel             0x00000006

    #define     BA_smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl     0x0048
    #define     B16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl     0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl        3
    #define   LSb16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl        3
    #define       bsmSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl     3
    #define   MSK32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl        0x00000038

    #define     BA_smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl    0x0048
    #define     B16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl    0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl       6
    #define   LSb16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl       6
    #define       bsmSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl    3
    #define   MSK32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl       0x000001C0

    #define     BA_smSysCtl_smAnaGrpCtl_term                   0x0049
    #define     B16smSysCtl_smAnaGrpCtl_term                   0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_term                      9
    #define   LSb16smSysCtl_smAnaGrpCtl_term                      9
    #define       bsmSysCtl_smAnaGrpCtl_term                   1
    #define   MSK32smSysCtl_smAnaGrpCtl_term                      0x00000200

    #define     BA_smSysCtl_smAnaGrpCtl_pu_pecl                0x0049
    #define     B16smSysCtl_smAnaGrpCtl_pu_pecl                0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_pu_pecl                   10
    #define   LSb16smSysCtl_smAnaGrpCtl_pu_pecl                   10
    #define       bsmSysCtl_smAnaGrpCtl_pu_pecl                1
    #define   MSK32smSysCtl_smAnaGrpCtl_pu_pecl                   0x00000400

    #define     BA_smSysCtl_smAnaGrpCtl_pecl_en                0x0049
    #define     B16smSysCtl_smAnaGrpCtl_pecl_en                0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_pecl_en                   11
    #define   LSb16smSysCtl_smAnaGrpCtl_pecl_en                   11
    #define       bsmSysCtl_smAnaGrpCtl_pecl_en                1
    #define   MSK32smSysCtl_smAnaGrpCtl_pecl_en                   0x00000800

    #define     BA_smSysCtl_smAnaGrpCtl_pu_limiter             0x0049
    #define     B16smSysCtl_smAnaGrpCtl_pu_limiter             0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_pu_limiter                12
    #define   LSb16smSysCtl_smAnaGrpCtl_pu_limiter                12
    #define       bsmSysCtl_smAnaGrpCtl_pu_limiter             1
    #define   MSK32smSysCtl_smAnaGrpCtl_pu_limiter                0x00001000

    #define     BA_smSysCtl_smAnaGrpCtl_limiter_dc_clk_en      0x0049
    #define     B16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en      0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en         13
    #define   LSb16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en         13
    #define       bsmSysCtl_smAnaGrpCtl_limiter_dc_clk_en      1
    #define   MSK32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en         0x00002000

    #define     BA_smSysCtl_smAnaGrpCtl_ipp_adj                0x0049
    #define     B16smSysCtl_smAnaGrpCtl_ipp_adj                0x0048
    #define   LSb32smSysCtl_smAnaGrpCtl_ipp_adj                   14
    #define   LSb16smSysCtl_smAnaGrpCtl_ipp_adj                   14
    #define       bsmSysCtl_smAnaGrpCtl_ipp_adj                2
    #define   MSK32smSysCtl_smAnaGrpCtl_ipp_adj                   0x0000C000

    #define     BA_smSysCtl_smAnaGrpCtl_icc_adj                0x004A
    #define     B16smSysCtl_smAnaGrpCtl_icc_adj                0x004A
    #define   LSb32smSysCtl_smAnaGrpCtl_icc_adj                   16
    #define   LSb16smSysCtl_smAnaGrpCtl_icc_adj                   0
    #define       bsmSysCtl_smAnaGrpCtl_icc_adj                2
    #define   MSK32smSysCtl_smAnaGrpCtl_icc_adj                   0x00030000

    #define     BA_smSysCtl_smAnaGrpCtl_ixtal                  0x004A
    #define     B16smSysCtl_smAnaGrpCtl_ixtal                  0x004A
    #define   LSb32smSysCtl_smAnaGrpCtl_ixtal                     18
    #define   LSb16smSysCtl_smAnaGrpCtl_ixtal                     2
    #define       bsmSysCtl_smAnaGrpCtl_ixtal                  2
    #define   MSK32smSysCtl_smAnaGrpCtl_ixtal                     0x000C0000

    #define     BA_smSysCtl_smAnaGrpCtl_icc10u_in_sel          0x004A
    #define     B16smSysCtl_smAnaGrpCtl_icc10u_in_sel          0x004A
    #define   LSb32smSysCtl_smAnaGrpCtl_icc10u_in_sel             20
    #define   LSb16smSysCtl_smAnaGrpCtl_icc10u_in_sel             4
    #define       bsmSysCtl_smAnaGrpCtl_icc10u_in_sel          1
    #define   MSK32smSysCtl_smAnaGrpCtl_icc10u_in_sel             0x00100000

    #define     BA_smSysCtl_smAnaGrpCtl_reserve_out            0x004A
    #define     B16smSysCtl_smAnaGrpCtl_reserve_out            0x004A
    #define   LSb32smSysCtl_smAnaGrpCtl_reserve_out               21
    #define   LSb16smSysCtl_smAnaGrpCtl_reserve_out               5
    #define       bsmSysCtl_smAnaGrpCtl_reserve_out            6
    #define   MSK32smSysCtl_smAnaGrpCtl_reserve_out               0x07E00000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_CORE_CTRL                       0x004C

    #define     BA_smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE      0x004C
    #define     B16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE      0x004C
    #define   LSb32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE         0
    #define   LSb16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE         0
    #define       bsmSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE      1
    #define   MSK32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE         0x00000001

    #define     BA_smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE        0x004C
    #define     B16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE        0x004C
    #define   LSb32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE           1
    #define   LSb16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE           1
    #define       bsmSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE        1
    #define   MSK32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE           0x00000002

    #define     BA_smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE        0x004C
    #define     B16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE        0x004C
    #define   LSb32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE           2
    #define   LSb16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE           2
    #define       bsmSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE        1
    #define   MSK32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE           0x00000004

    #define     BA_smSysCtl_SM_CORE_CTRL_PAD_ZP                0x004C
    #define     B16smSysCtl_SM_CORE_CTRL_PAD_ZP                0x004C
    #define   LSb32smSysCtl_SM_CORE_CTRL_PAD_ZP                   3
    #define   LSb16smSysCtl_SM_CORE_CTRL_PAD_ZP                   3
    #define       bsmSysCtl_SM_CORE_CTRL_PAD_ZP                4
    #define   MSK32smSysCtl_SM_CORE_CTRL_PAD_ZP                   0x00000078

    #define     BA_smSysCtl_SM_CORE_CTRL_PAD_ZN                0x004C
    #define     B16smSysCtl_SM_CORE_CTRL_PAD_ZN                0x004C
    #define   LSb32smSysCtl_SM_CORE_CTRL_PAD_ZN                   7
    #define   LSb16smSysCtl_SM_CORE_CTRL_PAD_ZN                   7
    #define       bsmSysCtl_SM_CORE_CTRL_PAD_ZN                4
    #define   MSK32smSysCtl_SM_CORE_CTRL_PAD_ZN                   0x00000780
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_TEST                            0x0050

    #define     BA_smSysCtl_SM_TEST_ADC_TEST_FAIL              0x0050
    #define     B16smSysCtl_SM_TEST_ADC_TEST_FAIL              0x0050
    #define   LSb32smSysCtl_SM_TEST_ADC_TEST_FAIL                 0
    #define   LSb16smSysCtl_SM_TEST_ADC_TEST_FAIL                 0
    #define       bsmSysCtl_SM_TEST_ADC_TEST_FAIL              1
    #define   MSK32smSysCtl_SM_TEST_ADC_TEST_FAIL                 0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_TEST_DATA0                      0x0054

    #define     BA_smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH        0x0054
    #define     B16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH        0x0054
    #define   LSb32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH           0
    #define   LSb16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH           0
    #define       bsmSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH        10
    #define   MSK32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH           0x000003FF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_TEST_DATA1                      0x0058

    #define     BA_smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW         0x0058
    #define     B16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW         0x0058
    #define   LSb32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW            0
    #define   LSb16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW            0
    #define       bsmSysCtl_SM_TEST_DATA1_ADC_DATA_LOW         10
    #define   MSK32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW            0x000003FF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_RWTC_CTRL_0                     0x005C

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW            0x005C
    #define     B16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW            0x005C
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW               0
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW               0
    #define       bsmSysCtl_SM_RWTC_CTRL_0_RF1P_LOW            4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW               0x0000000F

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH           0x005C
    #define     B16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH           0x005C
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH              4
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH              4
    #define       bsmSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH           4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH              0x000000F0

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW            0x005D
    #define     B16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW            0x005C
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW               8
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW               8
    #define       bsmSysCtl_SM_RWTC_CTRL_0_RF2P_LOW            4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW               0x00000F00

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH           0x005D
    #define     B16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH           0x005C
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH              12
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH              12
    #define       bsmSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH           4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH              0x0000F000

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW            0x005E
    #define     B16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW            0x005E
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW               16
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW               0
    #define       bsmSysCtl_SM_RWTC_CTRL_0_SR1P_LOW            4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW               0x000F0000

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH           0x005E
    #define     B16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH           0x005E
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH              20
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH              4
    #define       bsmSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH           4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH              0x00F00000

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW            0x005F
    #define     B16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW            0x005E
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW               24
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW               8
    #define       bsmSysCtl_SM_RWTC_CTRL_0_SR2P_LOW            4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW               0x0F000000

    #define     BA_smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH           0x005F
    #define     B16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH           0x005E
    #define   LSb32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH              28
    #define   LSb16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH              12
    #define       bsmSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH           4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH              0xF0000000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_RWTC_CTRL_1                     0x0060

    #define     BA_smSysCtl_SM_RWTC_CTRL_1_ROM_LOW             0x0060
    #define     B16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW             0x0060
    #define   LSb32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW                0
    #define   LSb16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW                0
    #define       bsmSysCtl_SM_RWTC_CTRL_1_ROM_LOW             5
    #define   MSK32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW                0x0000001F

    #define     BA_smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH            0x0060
    #define     B16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH            0x0060
    #define   LSb32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH               5
    #define   LSb16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH               5
    #define       bsmSysCtl_SM_RWTC_CTRL_1_ROM_HIGH            5
    #define   MSK32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH               0x000003E0

    #define     BA_smSysCtl_SM_RWTC_CTRL_1_ACMEM               0x0061
    #define     B16smSysCtl_SM_RWTC_CTRL_1_ACMEM               0x0060
    #define   LSb32smSysCtl_SM_RWTC_CTRL_1_ACMEM                  10
    #define   LSb16smSysCtl_SM_RWTC_CTRL_1_ACMEM                  10
    #define       bsmSysCtl_SM_RWTC_CTRL_1_ACMEM               4
    #define   MSK32smSysCtl_SM_RWTC_CTRL_1_ACMEM                  0x00003C00
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_PORT_SEL_CTRL                   0x0064

    #define     BA_smSysCtl_SM_PORT_SEL_CTRL_TW2               0x0064
    #define     B16smSysCtl_SM_PORT_SEL_CTRL_TW2               0x0064
    #define   LSb32smSysCtl_SM_PORT_SEL_CTRL_TW2                  0
    #define   LSb16smSysCtl_SM_PORT_SEL_CTRL_TW2                  0
    #define       bsmSysCtl_SM_PORT_SEL_CTRL_TW2               1
    #define   MSK32smSysCtl_SM_PORT_SEL_CTRL_TW2                  0x00000001

    #define     BA_smSysCtl_SM_PORT_SEL_CTRL_URT1              0x0064
    #define     B16smSysCtl_SM_PORT_SEL_CTRL_URT1              0x0064
    #define   LSb32smSysCtl_SM_PORT_SEL_CTRL_URT1                 1
    #define   LSb16smSysCtl_SM_PORT_SEL_CTRL_URT1                 1
    #define       bsmSysCtl_SM_PORT_SEL_CTRL_URT1              1
    #define   MSK32smSysCtl_SM_PORT_SEL_CTRL_URT1                 0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_ADC_RAW_DATA                  0x0068

    #define     BA_smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW    0x0068
    #define     B16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW    0x0068
    #define   LSb32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW       0
    #define   LSb16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW       0
    #define       bsmSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW    12
    #define   MSK32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW       0x00000FFF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_ADC_CLK_DIV                   0x006C

    #define     BA_smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV           0x006C
    #define     B16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV           0x006C
    #define   LSb32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV              0
    #define   LSb16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV              0
    #define       bsmSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV           3
    #define   MSK32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV              0x00000007

    #define     BA_smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV          0x006C
    #define     B16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV          0x006C
    #define   LSb32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV             3
    #define   LSb16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV             3
    #define       bsmSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV          4
    #define   MSK32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV             0x00000078
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_ADC_CTRL                      0x0070

    #define     BA_smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ         0x0070
    #define     B16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ         0x0070
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ            0
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ            0
    #define       bsmSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ         8
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ            0x000000FF

    #define     BA_smSysCtl_TSEN_ADC_CTRL_TSEN_START           0x0071
    #define     B16smSysCtl_TSEN_ADC_CTRL_TSEN_START           0x0070
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_START              8
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_START              8
    #define       bsmSysCtl_TSEN_ADC_CTRL_TSEN_START           1
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_START              0x00000100

    #define     BA_smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM         0x0071
    #define     B16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM         0x0070
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM            9
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM            9
    #define       bsmSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM         3
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM            0x00000E00

    #define     BA_smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN          0x0071
    #define     B16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN          0x0070
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN             12
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN             12
    #define       bsmSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN          1
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN             0x00001000

    #define     BA_smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN         0x0071
    #define     B16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN         0x0070
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN            13
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN            13
    #define       bsmSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN         2
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN            0x00006000

    #define     BA_smSysCtl_TSEN_ADC_CTRL_TSEN_CAL             0x0071
    #define     B16smSysCtl_TSEN_ADC_CTRL_TSEN_CAL             0x0070
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL                15
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_CAL                15
    #define       bsmSysCtl_TSEN_ADC_CTRL_TSEN_CAL             2
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL                0x00018000

    #define     BA_smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD            0x0072
    #define     B16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD            0x0072
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD               17
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD               1
    #define       bsmSysCtl_TSEN_ADC_CTRL_TSEN_RSVD            4
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD               0x001E0000

    #define     BA_smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL           0x0072
    #define     B16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL           0x0072
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL              21
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL              5
    #define       bsmSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL           1
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL              0x00200000

    #define     BA_smSysCtl_TSEN_ADC_CTRL_BG_DTRIM             0x0072
    #define     B16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM             0x0072
    #define   LSb32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM                22
    #define   LSb16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM                6
    #define       bsmSysCtl_TSEN_ADC_CTRL_BG_DTRIM             4
    #define   MSK32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM                0x03C00000
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_TSEN_ADC_DBG                       0x0074

    #define     BA_smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL          0x0074
    #define     B16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL          0x0074
    #define   LSb32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL             0
    #define   LSb16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL             0
    #define       bsmSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL          2
    #define   MSK32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL             0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_SM_DUMMY_REG                       0x0078

    #define     BA_smSysCtl_SM_DUMMY_REG_REG0                  0x0078
    #define     B16smSysCtl_SM_DUMMY_REG_REG0                  0x0078
    #define   LSb32smSysCtl_SM_DUMMY_REG_REG0                     0
    #define   LSb16smSysCtl_SM_DUMMY_REG_REG0                     0
    #define       bsmSysCtl_SM_DUMMY_REG_REG0                  32
    #define   MSK32smSysCtl_SM_DUMMY_REG_REG0                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_smSysCtl_smPinMuxCntlBus                    0x0200

    #define     BA_smSysCtl_smPinMuxCntlBus_SM_TMS             0x0200
    #define     B16smSysCtl_smPinMuxCntlBus_SM_TMS             0x0200
    #define   LSb32smSysCtl_smPinMuxCntlBus_SM_TMS                0
    #define   LSb16smSysCtl_smPinMuxCntlBus_SM_TMS                0
    #define       bsmSysCtl_smPinMuxCntlBus_SM_TMS             3
    #define   MSK32smSysCtl_smPinMuxCntlBus_SM_TMS                0x00000007
    #define        smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_0                   0x0
    #define        smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_1                   0x1
    #define        smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_2                   0x2
    #define        smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_3                   0x3
    #define        smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_4                   0x4
    #define        smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_5                   0x5

    #define     BA_smSysCtl_smPinMuxCntlBus_SM_TDI             0x0200
    #define     B16smSysCtl_smPinMuxCntlBus_SM_TDI             0x0200
    #define   LSb32smSysCtl_smPinMuxCntlBus_SM_TDI                3
    #define   LSb16smSysCtl_smPinMuxCntlBus_SM_TDI                3
    #define       bsmSysCtl_smPinMuxCntlBus_SM_TDI             3
    #define   MSK32smSysCtl_smPinMuxCntlBus_SM_TDI                0x00000038
    #define        smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_0                   0x0
    #define        smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_1                   0x1
    #define        smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_2                   0x2
    #define        smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_3                   0x3
    #define        smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_4                   0x4
    #define        smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_5                   0x5

    #define     BA_smSysCtl_smPinMuxCntlBus_SM_TDO             0x0200
    #define     B16smSysCtl_smPinMuxCntlBus_SM_TDO             0x0200
    #define   LSb32smSysCtl_smPinMuxCntlBus_SM_TDO                6
    #define   LSb16smSysCtl_smPinMuxCntlBus_SM_TDO                6
    #define       bsmSysCtl_smPinMuxCntlBus_SM_TDO             3
    #define   MSK32smSysCtl_smPinMuxCntlBus_SM_TDO                0x000001C0
    #define        smSysCtl_smPinMuxCntlBus_SM_TDO_MODE_0                   0x0
    #define        smSysCtl_smPinMuxCntlBus_SM_TDO_MODE_1                   0x1
    #define        smSysCtl_smPinMuxCntlBus_SM_TDO_MODE_2                   0x2
    ///////////////////////////////////////////////////////////

    typedef struct SIE_smSysCtl {
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_ID_REV_ID(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32smSysCtl_SM_ID_REV_ID(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16smSysCtl_SM_ID_REV_ID(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16smSysCtl_SM_ID_REV_ID(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32smSysCtl_SM_ID_PART_ID(r32)                 _BFGET_(r32,19, 4)
    #define   SET32smSysCtl_SM_ID_PART_ID(r32,v)               _BFSET_(r32,19, 4,v)

    #define   GET32smSysCtl_SM_ID_MFC_ID(r32)                  _BFGET_(r32,31,20)
    #define   SET32smSysCtl_SM_ID_MFC_ID(r32,v)                _BFSET_(r32,31,20,v)
    #define   GET16smSysCtl_SM_ID_MFC_ID(r16)                  _BFGET_(r16,15, 4)
    #define   SET16smSysCtl_SM_ID_MFC_ID(r16,v)                _BFSET_(r16,15, 4,v)

    #define     w32smSysCtl_SM_ID                              {\
            UNSG32 uSM_ID_REV_ID                               :  4;\
            UNSG32 uSM_ID_PART_ID                              : 16;\
            UNSG32 uSM_ID_MFC_ID                               : 12;\
          }
    union { UNSG32 u32smSysCtl_SM_ID;
            struct w32smSysCtl_SM_ID;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r32)        _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r16)        _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r32)       _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r16)       _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r16,v)     _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r32)       _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r16)       _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r16,v)     _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r32)        _BFGET_(r32, 3, 3)
    #define   SET32smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r32,v)      _BFSET_(r32, 3, 3,v)
    #define   GET16smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r16)        _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r16,v)      _BFSET_(r16, 3, 3,v)

    #define     w32smSysCtl_SM_CPU_CTRL                        {\
            UNSG32 uSM_CPU_CTRL_CPU_RST_GO                     :  1;\
            UNSG32 uSM_CPU_CTRL_CPU_VINITHI                    :  1;\
            UNSG32 uSM_CPU_CTRL_CPU_INITRAM                    :  1;\
            UNSG32 uSM_CPU_CTRL_CPU_BIGEND                     :  1;\
            UNSG32 RSVDx4_b4                                   : 28;\
          }
    union { UNSG32 u32smSysCtl_SM_CPU_CTRL;
            struct w32smSysCtl_SM_CPU_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_RST_CTRL_SOC_RST_GO(r32)        _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_RST_CTRL_SOC_RST_GO(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_RST_CTRL_SOC_RST_GO(r16)        _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_RST_CTRL_SOC_RST_GO(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_RST_CTRL_APB_RST_GO(r32)        _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_RST_CTRL_APB_RST_GO(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_RST_CTRL_APB_RST_GO(r16)        _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_RST_CTRL_APB_RST_GO(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r32)      _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r16)      _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_RST_CTRL_WOL_RST_GO(r32)        _BFGET_(r32, 3, 3)
    #define   SET32smSysCtl_SM_RST_CTRL_WOL_RST_GO(r32,v)      _BFSET_(r32, 3, 3,v)
    #define   GET16smSysCtl_SM_RST_CTRL_WOL_RST_GO(r16)        _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_RST_CTRL_WOL_RST_GO(r16,v)      _BFSET_(r16, 3, 3,v)

    #define   GET32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r32)      _BFGET_(r32, 4, 4)
    #define   SET32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r16)      _BFGET_(r16, 4, 4)
    #define   SET16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r16,v)    _BFSET_(r16, 4, 4,v)

    #define     w32smSysCtl_SM_RST_CTRL                        {\
            UNSG32 uSM_RST_CTRL_SOC_RST_GO                     :  1;\
            UNSG32 uSM_RST_CTRL_APB_RST_GO                     :  1;\
            UNSG32 uSM_RST_CTRL_SXBAR_RST_GO                   :  1;\
            UNSG32 uSM_RST_CTRL_WOL_RST_GO                     :  1;\
            UNSG32 uSM_RST_CTRL_FEPHY_RST_GO                   :  1;\
            UNSG32 RSVDx8_b5                                   : 27;\
          }
    union { UNSG32 u32smSysCtl_SM_RST_CTRL;
            struct w32smSysCtl_SM_RST_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_RST_STATUS_RST_WD_0(r32)        _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_RST_STATUS_RST_WD_0(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_RST_STATUS_RST_WD_0(r16)        _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_RST_STATUS_RST_WD_0(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_RST_STATUS_RST_WD_1(r32)        _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_RST_STATUS_RST_WD_1(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_RST_STATUS_RST_WD_1(r16)        _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_RST_STATUS_RST_WD_1(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_RST_STATUS_RST_WD_2(r32)        _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_RST_STATUS_RST_WD_2(r32,v)      _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_RST_STATUS_RST_WD_2(r16)        _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_RST_STATUS_RST_WD_2(r16,v)      _BFSET_(r16, 2, 2,v)

    #define     w32smSysCtl_SM_RST_STATUS                      {\
            UNSG32 uSM_RST_STATUS_RST_WD_0                     :  1;\
            UNSG32 uSM_RST_STATUS_RST_WD_1                     :  1;\
            UNSG32 uSM_RST_STATUS_RST_WD_2                     :  1;\
            UNSG32 RSVDxC_b3                                   : 29;\
          }
    union { UNSG32 u32smSysCtl_SM_RST_STATUS;
            struct w32smSysCtl_SM_RST_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_STRP_STATUS_BOOT_MODE(r32)      _BFGET_(r32, 1, 0)
    #define   SET32smSysCtl_SM_STRP_STATUS_BOOT_MODE(r32,v)    _BFSET_(r32, 1, 0,v)
    #define   GET16smSysCtl_SM_STRP_STATUS_BOOT_MODE(r16)      _BFGET_(r16, 1, 0)
    #define   SET16smSysCtl_SM_STRP_STATUS_BOOT_MODE(r16,v)    _BFSET_(r16, 1, 0,v)

    #define   GET32smSysCtl_SM_STRP_STATUS_STRP_2(r32)         _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_STRP_STATUS_STRP_2(r32,v)       _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_STRP_STATUS_STRP_2(r16)         _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_STRP_STATUS_STRP_2(r16,v)       _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_STRP_STATUS_STRP_3(r32)         _BFGET_(r32, 3, 3)
    #define   SET32smSysCtl_SM_STRP_STATUS_STRP_3(r32,v)       _BFSET_(r32, 3, 3,v)
    #define   GET16smSysCtl_SM_STRP_STATUS_STRP_3(r16)         _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_STRP_STATUS_STRP_3(r16,v)       _BFSET_(r16, 3, 3,v)

    #define     w32smSysCtl_SM_STRP_STATUS                     {\
            UNSG32 uSM_STRP_STATUS_BOOT_MODE                   :  2;\
            UNSG32 uSM_STRP_STATUS_STRP_2                      :  1;\
            UNSG32 uSM_STRP_STATUS_STRP_3                      :  1;\
            UNSG32 RSVDx10_b4                                  : 28;\
          }
    union { UNSG32 u32smSysCtl_SM_STRP_STATUS;
            struct w32smSysCtl_SM_STRP_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_CTRL_ISO_EN(r32)                _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_CTRL_ISO_EN(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_CTRL_ISO_EN(r16)                _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_CTRL_ISO_EN(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r32)        _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r16)        _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r32)        _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r32,v)      _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r16)        _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r16,v)      _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_CTRL_REV_0(r32)                 _BFGET_(r32, 4, 3)
    #define   SET32smSysCtl_SM_CTRL_REV_0(r32,v)               _BFSET_(r32, 4, 3,v)
    #define   GET16smSysCtl_SM_CTRL_REV_0(r16)                 _BFGET_(r16, 4, 3)
    #define   SET16smSysCtl_SM_CTRL_REV_0(r16,v)               _BFSET_(r16, 4, 3,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_SEL(r32)               _BFGET_(r32, 8, 5)
    #define   SET32smSysCtl_SM_CTRL_ADC_SEL(r32,v)             _BFSET_(r32, 8, 5,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_SEL(r16)               _BFGET_(r16, 8, 5)
    #define   SET16smSysCtl_SM_CTRL_ADC_SEL(r16,v)             _BFSET_(r16, 8, 5,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_PU(r32)                _BFGET_(r32, 9, 9)
    #define   SET32smSysCtl_SM_CTRL_ADC_PU(r32,v)              _BFSET_(r32, 9, 9,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_PU(r16)                _BFGET_(r16, 9, 9)
    #define   SET16smSysCtl_SM_CTRL_ADC_PU(r16,v)              _BFSET_(r16, 9, 9,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_CKSEL(r32)             _BFGET_(r32,11,10)
    #define   SET32smSysCtl_SM_CTRL_ADC_CKSEL(r32,v)           _BFSET_(r32,11,10,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_CKSEL(r16)             _BFGET_(r16,11,10)
    #define   SET16smSysCtl_SM_CTRL_ADC_CKSEL(r16,v)           _BFSET_(r16,11,10,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_START(r32)             _BFGET_(r32,12,12)
    #define   SET32smSysCtl_SM_CTRL_ADC_START(r32,v)           _BFSET_(r32,12,12,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_START(r16)             _BFGET_(r16,12,12)
    #define   SET16smSysCtl_SM_CTRL_ADC_START(r16,v)           _BFSET_(r16,12,12,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_RESET(r32)             _BFGET_(r32,13,13)
    #define   SET32smSysCtl_SM_CTRL_ADC_RESET(r32,v)           _BFSET_(r32,13,13,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_RESET(r16)             _BFGET_(r16,13,13)
    #define   SET16smSysCtl_SM_CTRL_ADC_RESET(r16,v)           _BFSET_(r16,13,13,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_BG_RDY(r32)            _BFGET_(r32,14,14)
    #define   SET32smSysCtl_SM_CTRL_ADC_BG_RDY(r32,v)          _BFSET_(r32,14,14,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_BG_RDY(r16)            _BFGET_(r16,14,14)
    #define   SET16smSysCtl_SM_CTRL_ADC_BG_RDY(r16,v)          _BFSET_(r16,14,14,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_CONT(r32)              _BFGET_(r32,15,15)
    #define   SET32smSysCtl_SM_CTRL_ADC_CONT(r32,v)            _BFSET_(r32,15,15,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_CONT(r16)              _BFGET_(r16,15,15)
    #define   SET16smSysCtl_SM_CTRL_ADC_CONT(r16,v)            _BFSET_(r16,15,15,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_BUF_EN(r32)            _BFGET_(r32,16,16)
    #define   SET32smSysCtl_SM_CTRL_ADC_BUF_EN(r32,v)          _BFSET_(r32,16,16,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_BUF_EN(r16)            _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_CTRL_ADC_BUF_EN(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_VREF_SEL(r32)          _BFGET_(r32,17,17)
    #define   SET32smSysCtl_SM_CTRL_ADC_VREF_SEL(r32,v)        _BFSET_(r32,17,17,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_VREF_SEL(r16)          _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_CTRL_ADC_VREF_SEL(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r32)        _BFGET_(r32,18,18)
    #define   SET32smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r32,v)      _BFSET_(r32,18,18,v)
    #define   GET16smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r16)        _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r16,v)      _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_EN(r32)               _BFGET_(r32,19,19)
    #define   SET32smSysCtl_SM_CTRL_TSEN_EN(r32,v)             _BFSET_(r32,19,19,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_EN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_CTRL_TSEN_EN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_CLK_SEL(r32)          _BFGET_(r32,20,20)
    #define   SET32smSysCtl_SM_CTRL_TSEN_CLK_SEL(r32,v)        _BFSET_(r32,20,20,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_CLK_SEL(r16)          _BFGET_(r16, 4, 4)
    #define   SET16smSysCtl_SM_CTRL_TSEN_CLK_SEL(r16,v)        _BFSET_(r16, 4, 4,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_MODE_SEL(r32)         _BFGET_(r32,21,21)
    #define   SET32smSysCtl_SM_CTRL_TSEN_MODE_SEL(r32,v)       _BFSET_(r32,21,21,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_MODE_SEL(r16)         _BFGET_(r16, 5, 5)
    #define   SET16smSysCtl_SM_CTRL_TSEN_MODE_SEL(r16,v)       _BFSET_(r16, 5, 5,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_ADC_CAL(r32)          _BFGET_(r32,23,22)
    #define   SET32smSysCtl_SM_CTRL_TSEN_ADC_CAL(r32,v)        _BFSET_(r32,23,22,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_ADC_CAL(r16)          _BFGET_(r16, 7, 6)
    #define   SET16smSysCtl_SM_CTRL_TSEN_ADC_CAL(r16,v)        _BFSET_(r16, 7, 6,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r32)      _BFGET_(r32,28,24)
    #define   SET32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r32,v)    _BFSET_(r32,28,24,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r16)      _BFGET_(r16,12, 8)
    #define   SET16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r16,v)    _BFSET_(r16,12, 8,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_RESET(r32)            _BFGET_(r32,29,29)
    #define   SET32smSysCtl_SM_CTRL_TSEN_RESET(r32,v)          _BFSET_(r32,29,29,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_RESET(r16)            _BFGET_(r16,13,13)
    #define   SET16smSysCtl_SM_CTRL_TSEN_RESET(r16,v)          _BFSET_(r16,13,13,v)

    #define   GET32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r32)       _BFGET_(r32,30,30)
    #define   SET32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r32,v)     _BFSET_(r32,30,30,v)
    #define   GET16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r16)       _BFGET_(r16,14,14)
    #define   SET16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r16,v)     _BFSET_(r16,14,14,v)

    #define     w32smSysCtl_SM_CTRL                            {\
            UNSG32 uSM_CTRL_ISO_EN                             :  1;\
            UNSG32 uSM_CTRL_SM2SOC_SW_INTR                     :  1;\
            UNSG32 uSM_CTRL_SOC2SM_SW_INTR                     :  1;\
            UNSG32 uSM_CTRL_REV_0                              :  2;\
            UNSG32 uSM_CTRL_ADC_SEL                            :  4;\
            UNSG32 uSM_CTRL_ADC_PU                             :  1;\
            UNSG32 uSM_CTRL_ADC_CKSEL                          :  2;\
            UNSG32 uSM_CTRL_ADC_START                          :  1;\
            UNSG32 uSM_CTRL_ADC_RESET                          :  1;\
            UNSG32 uSM_CTRL_ADC_BG_RDY                         :  1;\
            UNSG32 uSM_CTRL_ADC_CONT                           :  1;\
            UNSG32 uSM_CTRL_ADC_BUF_EN                         :  1;\
            UNSG32 uSM_CTRL_ADC_VREF_SEL                       :  1;\
            UNSG32 uSM_CTRL_ADC_ROTATE_SEL                     :  1;\
            UNSG32 uSM_CTRL_TSEN_EN                            :  1;\
            UNSG32 uSM_CTRL_TSEN_CLK_SEL                       :  1;\
            UNSG32 uSM_CTRL_TSEN_MODE_SEL                      :  1;\
            UNSG32 uSM_CTRL_TSEN_ADC_CAL                       :  2;\
            UNSG32 uSM_CTRL_TSEN_ADC_TST_SEL                   :  5;\
            UNSG32 uSM_CTRL_TSEN_RESET                         :  1;\
            UNSG32 uSM_CTRL_TSEN_ADC_ISO_EN                    :  1;\
            UNSG32 RSVDx14_b31                                 :  1;\
          }
    union { UNSG32 u32smSysCtl_SM_CTRL;
            struct w32smSysCtl_SM_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r32)       _BFGET_(r32, 4, 0)
    #define   SET32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r32,v)     _BFSET_(r32, 4, 0,v)
    #define   GET16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r16)       _BFGET_(r16, 4, 0)
    #define   SET16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r16,v)     _BFSET_(r16, 4, 0,v)

    #define   GET32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r32)        _BFGET_(r32, 9, 5)
    #define   SET32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r32,v)      _BFSET_(r32, 9, 5,v)
    #define   GET16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r16)        _BFGET_(r16, 9, 5)
    #define   SET16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r16,v)      _BFSET_(r16, 9, 5,v)

    #define     w32smSysCtl_SM_ADC_CTRL                        {\
            UNSG32 uSM_ADC_CTRL_TSEN_DAT_LT                    :  5;\
            UNSG32 uSM_ADC_CTRL_ADC_DAT_LT                     :  5;\
            UNSG32 RSVDx18_b10                                 : 22;\
          }
    union { UNSG32 u32smSysCtl_SM_ADC_CTRL;
            struct w32smSysCtl_SM_ADC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r32)    _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r32,v)  _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r16)    _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r16,v)  _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r32)    _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r32,v)  _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r16)    _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r16,v)  _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r32)    _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r32,v)  _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r16)    _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r16,v)  _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r32)    _BFGET_(r32, 3, 3)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r32,v)  _BFSET_(r32, 3, 3,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r16)    _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r16,v)  _BFSET_(r16, 3, 3,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r32)    _BFGET_(r32, 4, 4)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r32,v)  _BFSET_(r32, 4, 4,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r16)    _BFGET_(r16, 4, 4)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r16,v)  _BFSET_(r16, 4, 4,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r32)    _BFGET_(r32, 5, 5)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r32,v)  _BFSET_(r32, 5, 5,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r16)    _BFGET_(r16, 5, 5)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r16,v)  _BFSET_(r16, 5, 5,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r32)    _BFGET_(r32, 6, 6)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r32,v)  _BFSET_(r32, 6, 6,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r16)    _BFGET_(r16, 6, 6)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r16,v)  _BFSET_(r16, 6, 6,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r32)    _BFGET_(r32, 7, 7)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r32,v)  _BFSET_(r32, 7, 7,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r16)    _BFGET_(r16, 7, 7)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r16,v)  _BFSET_(r16, 7, 7,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r32)    _BFGET_(r32, 8, 8)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r32,v)  _BFSET_(r32, 8, 8,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r16)    _BFGET_(r16, 8, 8)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r16,v)  _BFSET_(r16, 8, 8,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r32)    _BFGET_(r32, 9, 9)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r32,v)  _BFSET_(r32, 9, 9,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r16)    _BFGET_(r16, 9, 9)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r16,v)  _BFSET_(r16, 9, 9,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r32)   _BFGET_(r32,10,10)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r32,v) _BFSET_(r32,10,10,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r16)   _BFGET_(r16,10,10)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r16,v) _BFSET_(r16,10,10,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r32)   _BFGET_(r32,11,11)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r32,v) _BFSET_(r32,11,11,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r16)   _BFGET_(r16,11,11)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r16,v) _BFSET_(r16,11,11,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r32)   _BFGET_(r32,12,12)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r32,v) _BFSET_(r32,12,12,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r16)   _BFGET_(r16,12,12)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r16,v) _BFSET_(r16,12,12,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r32)   _BFGET_(r32,13,13)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r32,v) _BFSET_(r32,13,13,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r16)   _BFGET_(r16,13,13)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r16,v) _BFSET_(r16,13,13,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r32)   _BFGET_(r32,14,14)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r32,v) _BFSET_(r32,14,14,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r16)   _BFGET_(r16,14,14)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r16,v) _BFSET_(r16,14,14,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r32)   _BFGET_(r32,15,15)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r32,v) _BFSET_(r32,15,15,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r16)   _BFGET_(r16,15,15)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r16,v) _BFSET_(r16,15,15,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r32)      _BFGET_(r32,16,16)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r32,v)    _BFSET_(r32,16,16,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r16)      _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r16,v)    _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r32)      _BFGET_(r32,17,17)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r32,v)    _BFSET_(r32,17,17,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r16)      _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r16,v)    _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r32)      _BFGET_(r32,18,18)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r32,v)    _BFSET_(r32,18,18,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r16)      _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r32)      _BFGET_(r32,19,19)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r32,v)    _BFSET_(r32,19,19,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r16)      _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r16,v)    _BFSET_(r16, 3, 3,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r32)      _BFGET_(r32,20,20)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r32,v)    _BFSET_(r32,20,20,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r16)      _BFGET_(r16, 4, 4)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r16,v)    _BFSET_(r16, 4, 4,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r32)      _BFGET_(r32,21,21)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r32,v)    _BFSET_(r32,21,21,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r16)      _BFGET_(r16, 5, 5)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r32)      _BFGET_(r32,22,22)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r32,v)    _BFSET_(r32,22,22,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r16)      _BFGET_(r16, 6, 6)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r16,v)    _BFSET_(r16, 6, 6,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r32)      _BFGET_(r32,23,23)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r32,v)    _BFSET_(r32,23,23,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r16)      _BFGET_(r16, 7, 7)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r16,v)    _BFSET_(r16, 7, 7,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r32)      _BFGET_(r32,24,24)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r32,v)    _BFSET_(r32,24,24,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r16)      _BFGET_(r16, 8, 8)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r16,v)    _BFSET_(r16, 8, 8,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r32)      _BFGET_(r32,25,25)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r32,v)    _BFSET_(r32,25,25,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r16)      _BFGET_(r16, 9, 9)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r16,v)    _BFSET_(r16, 9, 9,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r32)     _BFGET_(r32,26,26)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r32,v)   _BFSET_(r32,26,26,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r16)     _BFGET_(r16,10,10)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r16,v)   _BFSET_(r16,10,10,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r32)     _BFGET_(r32,27,27)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r32,v)   _BFSET_(r32,27,27,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r16)     _BFGET_(r16,11,11)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r16,v)   _BFSET_(r16,11,11,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r32)     _BFGET_(r32,28,28)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r32,v)   _BFSET_(r32,28,28,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r16)     _BFGET_(r16,12,12)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r16,v)   _BFSET_(r16,12,12,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r32)     _BFGET_(r32,29,29)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r32,v)   _BFSET_(r32,29,29,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r16)     _BFGET_(r16,13,13)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r16,v)   _BFSET_(r16,13,13,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r32)     _BFGET_(r32,30,30)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r32,v)   _BFSET_(r32,30,30,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r16)     _BFGET_(r16,14,14)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r16,v)   _BFSET_(r16,14,14,v)

    #define   GET32smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r32)     _BFGET_(r32,31,31)
    #define   SET32smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r32,v)   _BFSET_(r32,31,31,v)
    #define   GET16smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r16)     _BFGET_(r16,15,15)
    #define   SET16smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r16,v)   _BFSET_(r16,15,15,v)

    #define     w32smSysCtl_SM_ADC_STATUS                      {\
            UNSG32 uSM_ADC_STATUS_CH0_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH1_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH2_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH3_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH4_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH5_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH6_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH7_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH8_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH9_DATA_RDY                 :  1;\
            UNSG32 uSM_ADC_STATUS_CH10_DATA_RDY                :  1;\
            UNSG32 uSM_ADC_STATUS_CH11_DATA_RDY                :  1;\
            UNSG32 uSM_ADC_STATUS_CH12_DATA_RDY                :  1;\
            UNSG32 uSM_ADC_STATUS_CH13_DATA_RDY                :  1;\
            UNSG32 uSM_ADC_STATUS_CH14_DATA_RDY                :  1;\
            UNSG32 uSM_ADC_STATUS_CH15_DATA_RDY                :  1;\
            UNSG32 uSM_ADC_STATUS_CH0_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH1_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH2_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH3_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH4_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH5_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH6_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH7_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH8_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH9_INT_EN                   :  1;\
            UNSG32 uSM_ADC_STATUS_CH10_INT_EN                  :  1;\
            UNSG32 uSM_ADC_STATUS_CH11_INT_EN                  :  1;\
            UNSG32 uSM_ADC_STATUS_CH12_INT_EN                  :  1;\
            UNSG32 uSM_ADC_STATUS_CH13_INT_EN                  :  1;\
            UNSG32 uSM_ADC_STATUS_CH14_INT_EN                  :  1;\
            UNSG32 uSM_ADC_STATUS_CH15_INT_EN                  :  1;\
          }
    union { UNSG32 u32smSysCtl_SM_ADC_STATUS;
            struct w32smSysCtl_SM_ADC_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_ADC_DATA_ADC_DATA(r32)          _BFGET_(r32, 9, 0)
    #define   SET32smSysCtl_SM_ADC_DATA_ADC_DATA(r32,v)        _BFSET_(r32, 9, 0,v)
    #define   GET16smSysCtl_SM_ADC_DATA_ADC_DATA(r16)          _BFGET_(r16, 9, 0)
    #define   SET16smSysCtl_SM_ADC_DATA_ADC_DATA(r16,v)        _BFSET_(r16, 9, 0,v)

    #define     w32smSysCtl_SM_ADC_DATA                        {\
            UNSG32 uSM_ADC_DATA_ADC_DATA                       : 10;\
            UNSG32 RSVDx20_b10                                 : 22;\
          }
    union { UNSG32 u32smSysCtl_SM_ADC_DATA;
            struct w32smSysCtl_SM_ADC_DATA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r32)      _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r32,v)    _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r16)      _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r16,v)    _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_TSEN_ADC_STATUS_INT_EN(r32)        _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_TSEN_ADC_STATUS_INT_EN(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_TSEN_ADC_STATUS_INT_EN(r16)        _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_TSEN_ADC_STATUS_INT_EN(r16,v)      _BFSET_(r16, 1, 1,v)

    #define     w32smSysCtl_TSEN_ADC_STATUS                    {\
            UNSG32 uTSEN_ADC_STATUS_DATA_RDY                   :  1;\
            UNSG32 uTSEN_ADC_STATUS_INT_EN                     :  1;\
            UNSG32 RSVDx24_b2                                  : 30;\
          }
    union { UNSG32 u32smSysCtl_TSEN_ADC_STATUS;
            struct w32smSysCtl_TSEN_ADC_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_ADC_DATA_ADC_DATA(r32)        _BFGET_(r32,11, 0)
    #define   SET32smSysCtl_TSEN_ADC_DATA_ADC_DATA(r32,v)      _BFSET_(r32,11, 0,v)
    #define   GET16smSysCtl_TSEN_ADC_DATA_ADC_DATA(r16)        _BFGET_(r16,11, 0)
    #define   SET16smSysCtl_TSEN_ADC_DATA_ADC_DATA(r16,v)      _BFSET_(r16,11, 0,v)

    #define     w32smSysCtl_TSEN_ADC_DATA                      {\
            UNSG32 uTSEN_ADC_DATA_ADC_DATA                     : 12;\
            UNSG32 RSVDx28_b12                                 : 20;\
          }
    union { UNSG32 u32smSysCtl_TSEN_ADC_DATA;
            struct w32smSysCtl_TSEN_ADC_DATA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r32)   _BFGET_(r32,11, 0)
    #define   SET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r32,v) _BFSET_(r32,11, 0,v)
    #define   GET16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r16)   _BFGET_(r16,11, 0)
    #define   SET16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r16,v) _BFSET_(r16,11, 0,v)

    #define   GET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN(r32)   _BFGET_(r32,23,12)
    #define   SET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN(r32,v) _BFSET_(r32,23,12,v)

    #define   GET32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r32) _BFGET_(r32,24,24)
    #define   SET32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r32,v) _BFSET_(r32,24,24,v)
    #define   GET16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r16) _BFGET_(r16, 8, 8)
    #define   SET16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r16,v) _BFSET_(r16, 8, 8,v)

    #define     w32smSysCtl_TSEN_CHK_CTRL                      {\
            UNSG32 uTSEN_CHK_CTRL_TSEN_DATA_MAX                : 12;\
            UNSG32 uTSEN_CHK_CTRL_TSEN_DATA_MIN                : 12;\
            UNSG32 uTSEN_CHK_CTRL_TSEN_OVERHEAT_SEL            :  1;\
            UNSG32 RSVDx2C_b25                                 :  7;\
          }
    union { UNSG32 u32smSysCtl_TSEN_CHK_CTRL;
            struct w32smSysCtl_TSEN_CHK_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r32) _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r16) _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r32) _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r16) _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r16,v) _BFSET_(r16, 1, 1,v)

    #define     w32smSysCtl_TSEN_DATA_STATUS                   {\
            UNSG32 uTSEN_DATA_STATUS_TSEN_MAX_FAIL             :  1;\
            UNSG32 uTSEN_DATA_STATUS_TSEN_MIN_FAIL             :  1;\
            UNSG32 RSVDx30_b2                                  : 30;\
          }
    union { UNSG32 u32smSysCtl_TSEN_DATA_STATUS;
            struct w32smSysCtl_TSEN_DATA_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_BOOT_STATUS_MODE(r32)           _BFGET_(r32,31, 0)
    #define   SET32smSysCtl_SM_BOOT_STATUS_MODE(r32,v)         _BFSET_(r32,31, 0,v)

    #define     w32smSysCtl_SM_BOOT_STATUS                     {\
            UNSG32 uSM_BOOT_STATUS_MODE                        : 32;\
          }
    union { UNSG32 u32smSysCtl_SM_BOOT_STATUS;
            struct w32smSysCtl_SM_BOOT_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_LDO_CTRL_TEST_SEL(r32)          _BFGET_(r32, 2, 0)
    #define   SET32smSysCtl_SM_LDO_CTRL_TEST_SEL(r32,v)        _BFSET_(r32, 2, 0,v)
    #define   GET16smSysCtl_SM_LDO_CTRL_TEST_SEL(r16)          _BFGET_(r16, 2, 0)
    #define   SET16smSysCtl_SM_LDO_CTRL_TEST_SEL(r16,v)        _BFSET_(r16, 2, 0,v)

    #define   GET32smSysCtl_SM_LDO_CTRL_VOUT_SEL(r32)          _BFGET_(r32, 5, 3)
    #define   SET32smSysCtl_SM_LDO_CTRL_VOUT_SEL(r32,v)        _BFSET_(r32, 5, 3,v)
    #define   GET16smSysCtl_SM_LDO_CTRL_VOUT_SEL(r16)          _BFGET_(r16, 5, 3)
    #define   SET16smSysCtl_SM_LDO_CTRL_VOUT_SEL(r16,v)        _BFSET_(r16, 5, 3,v)

    #define   GET32smSysCtl_SM_LDO_CTRL_TEST_EN(r32)           _BFGET_(r32, 6, 6)
    #define   SET32smSysCtl_SM_LDO_CTRL_TEST_EN(r32,v)         _BFSET_(r32, 6, 6,v)
    #define   GET16smSysCtl_SM_LDO_CTRL_TEST_EN(r16)           _BFGET_(r16, 6, 6)
    #define   SET16smSysCtl_SM_LDO_CTRL_TEST_EN(r16,v)         _BFSET_(r16, 6, 6,v)

    #define   GET32smSysCtl_SM_LDO_CTRL_LDO_RDY(r32)           _BFGET_(r32, 7, 7)
    #define   SET32smSysCtl_SM_LDO_CTRL_LDO_RDY(r32,v)         _BFSET_(r32, 7, 7,v)
    #define   GET16smSysCtl_SM_LDO_CTRL_LDO_RDY(r16)           _BFGET_(r16, 7, 7)
    #define   SET16smSysCtl_SM_LDO_CTRL_LDO_RDY(r16,v)         _BFSET_(r16, 7, 7,v)

    #define   GET32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r32)        _BFGET_(r32, 8, 8)
    #define   SET32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r32,v)      _BFSET_(r32, 8, 8,v)
    #define   GET16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r16)        _BFGET_(r16, 8, 8)
    #define   SET16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r16,v)      _BFSET_(r16, 8, 8,v)

    #define   GET32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r32)     _BFGET_(r32, 9, 9)
    #define   SET32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r32,v)   _BFSET_(r32, 9, 9,v)
    #define   GET16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r16)     _BFGET_(r16, 9, 9)
    #define   SET16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r16,v)   _BFSET_(r16, 9, 9,v)

    #define     w32smSysCtl_SM_LDO_CTRL                        {\
            UNSG32 uSM_LDO_CTRL_TEST_SEL                       :  3;\
            UNSG32 uSM_LDO_CTRL_VOUT_SEL                       :  3;\
            UNSG32 uSM_LDO_CTRL_TEST_EN                        :  1;\
            UNSG32 uSM_LDO_CTRL_LDO_RDY                        :  1;\
            UNSG32 uSM_LDO_CTRL_CHP_EN_1P1                     :  1;\
            UNSG32 uSM_LDO_CTRL_ICLAMP_EN_1P1                  :  1;\
            UNSG32 RSVDx38_b10                                 : 22;\
          }
    union { UNSG32 u32smSysCtl_SM_LDO_CTRL;
            struct w32smSysCtl_SM_LDO_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_WDT_MASK_SM_RST(r32)            _BFGET_(r32, 2, 0)
    #define   SET32smSysCtl_SM_WDT_MASK_SM_RST(r32,v)          _BFSET_(r32, 2, 0,v)
    #define   GET16smSysCtl_SM_WDT_MASK_SM_RST(r16)            _BFGET_(r16, 2, 0)
    #define   SET16smSysCtl_SM_WDT_MASK_SM_RST(r16,v)          _BFSET_(r16, 2, 0,v)

    #define   GET32smSysCtl_SM_WDT_MASK_SOC_RST(r32)           _BFGET_(r32, 5, 3)
    #define   SET32smSysCtl_SM_WDT_MASK_SOC_RST(r32,v)         _BFSET_(r32, 5, 3,v)
    #define   GET16smSysCtl_SM_WDT_MASK_SOC_RST(r16)           _BFGET_(r16, 5, 3)
    #define   SET16smSysCtl_SM_WDT_MASK_SOC_RST(r16,v)         _BFSET_(r16, 5, 3,v)

    #define     w32smSysCtl_SM_WDT_MASK                        {\
            UNSG32 uSM_WDT_MASK_SM_RST                         :  3;\
            UNSG32 uSM_WDT_MASK_SOC_RST                        :  3;\
            UNSG32 RSVDx3C_b6                                  : 26;\
          }
    union { UNSG32 u32smSysCtl_SM_WDT_MASK;
            struct w32smSysCtl_SM_WDT_MASK;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_CLK_CTRL_tsenClkSel(r32)        _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_CLK_CTRL_tsenClkSel(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_CLK_CTRL_tsenClkSel(r16)        _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_CLK_CTRL_tsenClkSel(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_CLK_CTRL_tsenClkEn(r32)         _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_CLK_CTRL_tsenClkEn(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_CLK_CTRL_tsenClkEn(r16)         _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_CLK_CTRL_tsenClkEn(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r32)     _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r32,v)   _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r16)     _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r16,v)   _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r32)      _BFGET_(r32, 3, 3)
    #define   SET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r32,v)    _BFSET_(r32, 3, 3,v)
    #define   GET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r16)      _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r16,v)    _BFSET_(r16, 3, 3,v)

    #define     w32smSysCtl_SM_CLK_CTRL                        {\
            UNSG32 uSM_CLK_CTRL_tsenClkSel                     :  1;\
            UNSG32 uSM_CLK_CTRL_tsenClkEn                      :  1;\
            UNSG32 uSM_CLK_CTRL_ssmiiTxClkSel                  :  1;\
            UNSG32 uSM_CLK_CTRL_ssmiiTxClkEn                   :  1;\
            UNSG32 RSVDx40_b4                                  : 28;\
          }
    union { UNSG32 u32smSysCtl_SM_CLK_CTRL;
            struct w32smSysCtl_SM_CLK_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_smAnaGrpCtl_pu(r32)                _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_smAnaGrpCtl_pu(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_smAnaGrpCtl_pu(r16)                _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_smAnaGrpCtl_pu(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_smAnaGrpCtl_bgSel(r32)             _BFGET_(r32, 2, 1)
    #define   SET32smSysCtl_smAnaGrpCtl_bgSel(r32,v)           _BFSET_(r32, 2, 1,v)
    #define   GET16smSysCtl_smAnaGrpCtl_bgSel(r16)             _BFGET_(r16, 2, 1)
    #define   SET16smSysCtl_smAnaGrpCtl_bgSel(r16,v)           _BFSET_(r16, 2, 1,v)

    #define   GET32smSysCtl_smAnaGrpCtl_puXtl(r32)             _BFGET_(r32, 3, 3)
    #define   SET32smSysCtl_smAnaGrpCtl_puXtl(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16smSysCtl_smAnaGrpCtl_puXtl(r16)             _BFGET_(r16, 3, 3)
    #define   SET16smSysCtl_smAnaGrpCtl_puXtl(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32smSysCtl_smAnaGrpCtl_bypass(r32)            _BFGET_(r32, 4, 4)
    #define   SET32smSysCtl_smAnaGrpCtl_bypass(r32,v)          _BFSET_(r32, 4, 4,v)
    #define   GET16smSysCtl_smAnaGrpCtl_bypass(r16)            _BFGET_(r16, 4, 4)
    #define   SET16smSysCtl_smAnaGrpCtl_bypass(r16,v)          _BFSET_(r16, 4, 4,v)

    #define   GET32smSysCtl_smAnaGrpCtl_gainX2(r32)            _BFGET_(r32, 5, 5)
    #define   SET32smSysCtl_smAnaGrpCtl_gainX2(r32,v)          _BFSET_(r32, 5, 5,v)
    #define   GET16smSysCtl_smAnaGrpCtl_gainX2(r16)            _BFGET_(r16, 5, 5)
    #define   SET16smSysCtl_smAnaGrpCtl_gainX2(r16,v)          _BFSET_(r16, 5, 5,v)

    #define   GET32smSysCtl_smAnaGrpCtl_selClkDigDiv1(r32)     _BFGET_(r32, 7, 6)
    #define   SET32smSysCtl_smAnaGrpCtl_selClkDigDiv1(r32,v)   _BFSET_(r32, 7, 6,v)
    #define   GET16smSysCtl_smAnaGrpCtl_selClkDigDiv1(r16)     _BFGET_(r16, 7, 6)
    #define   SET16smSysCtl_smAnaGrpCtl_selClkDigDiv1(r16,v)   _BFSET_(r16, 7, 6,v)

    #define   GET32smSysCtl_smAnaGrpCtl_selClkDigDiv2(r32)     _BFGET_(r32, 9, 8)
    #define   SET32smSysCtl_smAnaGrpCtl_selClkDigDiv2(r32,v)   _BFSET_(r32, 9, 8,v)
    #define   GET16smSysCtl_smAnaGrpCtl_selClkDigDiv2(r16)     _BFGET_(r16, 9, 8)
    #define   SET16smSysCtl_smAnaGrpCtl_selClkDigDiv2(r16,v)   _BFSET_(r16, 9, 8,v)

    #define   GET32smSysCtl_smAnaGrpCtl_selClkDigDiv3(r32)     _BFGET_(r32,11,10)
    #define   SET32smSysCtl_smAnaGrpCtl_selClkDigDiv3(r32,v)   _BFSET_(r32,11,10,v)
    #define   GET16smSysCtl_smAnaGrpCtl_selClkDigDiv3(r16)     _BFGET_(r16,11,10)
    #define   SET16smSysCtl_smAnaGrpCtl_selClkDigDiv3(r16,v)   _BFSET_(r16,11,10,v)

    #define   GET32smSysCtl_smAnaGrpCtl_selClkDigDiv4(r32)     _BFGET_(r32,13,12)
    #define   SET32smSysCtl_smAnaGrpCtl_selClkDigDiv4(r32,v)   _BFSET_(r32,13,12,v)
    #define   GET16smSysCtl_smAnaGrpCtl_selClkDigDiv4(r16)     _BFGET_(r16,13,12)
    #define   SET16smSysCtl_smAnaGrpCtl_selClkDigDiv4(r16,v)   _BFSET_(r16,13,12,v)

    #define   GET32smSysCtl_smAnaGrpCtl_puOsc(r32)             _BFGET_(r32,14,14)
    #define   SET32smSysCtl_smAnaGrpCtl_puOsc(r32,v)           _BFSET_(r32,14,14,v)
    #define   GET16smSysCtl_smAnaGrpCtl_puOsc(r16)             _BFGET_(r16,14,14)
    #define   SET16smSysCtl_smAnaGrpCtl_puOsc(r16,v)           _BFSET_(r16,14,14,v)

    #define   GET32smSysCtl_smAnaGrpCtl_speedOsc(r32)          _BFGET_(r32,16,15)
    #define   SET32smSysCtl_smAnaGrpCtl_speedOsc(r32,v)        _BFSET_(r32,16,15,v)

    #define   GET32smSysCtl_smAnaGrpCtl_testAna(r32)           _BFGET_(r32,20,17)
    #define   SET32smSysCtl_smAnaGrpCtl_testAna(r32,v)         _BFSET_(r32,20,17,v)
    #define   GET16smSysCtl_smAnaGrpCtl_testAna(r16)           _BFGET_(r16, 4, 1)
    #define   SET16smSysCtl_smAnaGrpCtl_testAna(r16,v)         _BFSET_(r16, 4, 1,v)

    #define   GET32smSysCtl_smAnaGrpCtl_bgRdy(r32)             _BFGET_(r32,21,21)
    #define   SET32smSysCtl_smAnaGrpCtl_bgRdy(r32,v)           _BFSET_(r32,21,21,v)
    #define   GET16smSysCtl_smAnaGrpCtl_bgRdy(r16)             _BFGET_(r16, 5, 5)
    #define   SET16smSysCtl_smAnaGrpCtl_bgRdy(r16,v)           _BFSET_(r16, 5, 5,v)

    #define   GET32smSysCtl_smAnaGrpCtl_reserve_in(r32)        _BFGET_(r32,31,22)
    #define   SET32smSysCtl_smAnaGrpCtl_reserve_in(r32,v)      _BFSET_(r32,31,22,v)
    #define   GET16smSysCtl_smAnaGrpCtl_reserve_in(r16)        _BFGET_(r16,15, 6)
    #define   SET16smSysCtl_smAnaGrpCtl_reserve_in(r16,v)      _BFSET_(r16,15, 6,v)

    #define     w32smSysCtl_smAnaGrpCtl                        {\
            UNSG32 usmAnaGrpCtl_pu                             :  1;\
            UNSG32 usmAnaGrpCtl_bgSel                          :  2;\
            UNSG32 usmAnaGrpCtl_puXtl                          :  1;\
            UNSG32 usmAnaGrpCtl_bypass                         :  1;\
            UNSG32 usmAnaGrpCtl_gainX2                         :  1;\
            UNSG32 usmAnaGrpCtl_selClkDigDiv1                  :  2;\
            UNSG32 usmAnaGrpCtl_selClkDigDiv2                  :  2;\
            UNSG32 usmAnaGrpCtl_selClkDigDiv3                  :  2;\
            UNSG32 usmAnaGrpCtl_selClkDigDiv4                  :  2;\
            UNSG32 usmAnaGrpCtl_puOsc                          :  1;\
            UNSG32 usmAnaGrpCtl_speedOsc                       :  2;\
            UNSG32 usmAnaGrpCtl_testAna                        :  4;\
            UNSG32 usmAnaGrpCtl_bgRdy                          :  1;\
            UNSG32 usmAnaGrpCtl_reserve_in                     : 10;\
          }
    union { UNSG32 u32smSysCtl_smAnaGrpCtl;
            struct w32smSysCtl_smAnaGrpCtl;
          };
    #define   GET32smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r32)      _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r32,v)    _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r16)      _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r16,v)    _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_smAnaGrpCtl_vreg_1p2v_sel(r32)     _BFGET_(r32, 2, 1)
    #define   SET32smSysCtl_smAnaGrpCtl_vreg_1p2v_sel(r32,v)   _BFSET_(r32, 2, 1,v)
    #define   GET16smSysCtl_smAnaGrpCtl_vreg_1p2v_sel(r16)     _BFGET_(r16, 2, 1)
    #define   SET16smSysCtl_smAnaGrpCtl_vreg_1p2v_sel(r16,v)   _BFSET_(r16, 2, 1,v)

    #define   GET32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl(r32) _BFGET_(r32, 5, 3)
    #define   SET32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl(r32,v) _BFSET_(r32, 5, 3,v)
    #define   GET16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl(r16) _BFGET_(r16, 5, 3)
    #define   SET16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_xtl(r16,v) _BFSET_(r16, 5, 3,v)

    #define   GET32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl(r32) _BFGET_(r32, 8, 6)
    #define   SET32smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl(r32,v) _BFSET_(r32, 8, 6,v)
    #define   GET16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl(r16) _BFGET_(r16, 8, 6)
    #define   SET16smSysCtl_smAnaGrpCtl_vreg_1p05v_sel_pecl(r16,v) _BFSET_(r16, 8, 6,v)

    #define   GET32smSysCtl_smAnaGrpCtl_term(r32)              _BFGET_(r32, 9, 9)
    #define   SET32smSysCtl_smAnaGrpCtl_term(r32,v)            _BFSET_(r32, 9, 9,v)
    #define   GET16smSysCtl_smAnaGrpCtl_term(r16)              _BFGET_(r16, 9, 9)
    #define   SET16smSysCtl_smAnaGrpCtl_term(r16,v)            _BFSET_(r16, 9, 9,v)

    #define   GET32smSysCtl_smAnaGrpCtl_pu_pecl(r32)           _BFGET_(r32,10,10)
    #define   SET32smSysCtl_smAnaGrpCtl_pu_pecl(r32,v)         _BFSET_(r32,10,10,v)
    #define   GET16smSysCtl_smAnaGrpCtl_pu_pecl(r16)           _BFGET_(r16,10,10)
    #define   SET16smSysCtl_smAnaGrpCtl_pu_pecl(r16,v)         _BFSET_(r16,10,10,v)

    #define   GET32smSysCtl_smAnaGrpCtl_pecl_en(r32)           _BFGET_(r32,11,11)
    #define   SET32smSysCtl_smAnaGrpCtl_pecl_en(r32,v)         _BFSET_(r32,11,11,v)
    #define   GET16smSysCtl_smAnaGrpCtl_pecl_en(r16)           _BFGET_(r16,11,11)
    #define   SET16smSysCtl_smAnaGrpCtl_pecl_en(r16,v)         _BFSET_(r16,11,11,v)

    #define   GET32smSysCtl_smAnaGrpCtl_pu_limiter(r32)        _BFGET_(r32,12,12)
    #define   SET32smSysCtl_smAnaGrpCtl_pu_limiter(r32,v)      _BFSET_(r32,12,12,v)
    #define   GET16smSysCtl_smAnaGrpCtl_pu_limiter(r16)        _BFGET_(r16,12,12)
    #define   SET16smSysCtl_smAnaGrpCtl_pu_limiter(r16,v)      _BFSET_(r16,12,12,v)

    #define   GET32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r32) _BFGET_(r32,13,13)
    #define   SET32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r32,v) _BFSET_(r32,13,13,v)
    #define   GET16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r16) _BFGET_(r16,13,13)
    #define   SET16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r16,v) _BFSET_(r16,13,13,v)

    #define   GET32smSysCtl_smAnaGrpCtl_ipp_adj(r32)           _BFGET_(r32,15,14)
    #define   SET32smSysCtl_smAnaGrpCtl_ipp_adj(r32,v)         _BFSET_(r32,15,14,v)
    #define   GET16smSysCtl_smAnaGrpCtl_ipp_adj(r16)           _BFGET_(r16,15,14)
    #define   SET16smSysCtl_smAnaGrpCtl_ipp_adj(r16,v)         _BFSET_(r16,15,14,v)

    #define   GET32smSysCtl_smAnaGrpCtl_icc_adj(r32)           _BFGET_(r32,17,16)
    #define   SET32smSysCtl_smAnaGrpCtl_icc_adj(r32,v)         _BFSET_(r32,17,16,v)
    #define   GET16smSysCtl_smAnaGrpCtl_icc_adj(r16)           _BFGET_(r16, 1, 0)
    #define   SET16smSysCtl_smAnaGrpCtl_icc_adj(r16,v)         _BFSET_(r16, 1, 0,v)

    #define   GET32smSysCtl_smAnaGrpCtl_ixtal(r32)             _BFGET_(r32,19,18)
    #define   SET32smSysCtl_smAnaGrpCtl_ixtal(r32,v)           _BFSET_(r32,19,18,v)
    #define   GET16smSysCtl_smAnaGrpCtl_ixtal(r16)             _BFGET_(r16, 3, 2)
    #define   SET16smSysCtl_smAnaGrpCtl_ixtal(r16,v)           _BFSET_(r16, 3, 2,v)

    #define   GET32smSysCtl_smAnaGrpCtl_icc10u_in_sel(r32)     _BFGET_(r32,20,20)
    #define   SET32smSysCtl_smAnaGrpCtl_icc10u_in_sel(r32,v)   _BFSET_(r32,20,20,v)
    #define   GET16smSysCtl_smAnaGrpCtl_icc10u_in_sel(r16)     _BFGET_(r16, 4, 4)
    #define   SET16smSysCtl_smAnaGrpCtl_icc10u_in_sel(r16,v)   _BFSET_(r16, 4, 4,v)

    #define   GET32smSysCtl_smAnaGrpCtl_reserve_out(r32)       _BFGET_(r32,26,21)
    #define   SET32smSysCtl_smAnaGrpCtl_reserve_out(r32,v)     _BFSET_(r32,26,21,v)
    #define   GET16smSysCtl_smAnaGrpCtl_reserve_out(r16)       _BFGET_(r16,10, 5)
    #define   SET16smSysCtl_smAnaGrpCtl_reserve_out(r16,v)     _BFSET_(r16,10, 5,v)

    #define     w32smSysCtl_smAnaGrpCtl1                       {\
            UNSG32 usmAnaGrpCtl_xtl_pecl_sel                   :  1;\
            UNSG32 usmAnaGrpCtl_vreg_1p2v_sel                  :  2;\
            UNSG32 usmAnaGrpCtl_vreg_1p05v_sel_xtl             :  3;\
            UNSG32 usmAnaGrpCtl_vreg_1p05v_sel_pecl            :  3;\
            UNSG32 usmAnaGrpCtl_term                           :  1;\
            UNSG32 usmAnaGrpCtl_pu_pecl                        :  1;\
            UNSG32 usmAnaGrpCtl_pecl_en                        :  1;\
            UNSG32 usmAnaGrpCtl_pu_limiter                     :  1;\
            UNSG32 usmAnaGrpCtl_limiter_dc_clk_en              :  1;\
            UNSG32 usmAnaGrpCtl_ipp_adj                        :  2;\
            UNSG32 usmAnaGrpCtl_icc_adj                        :  2;\
            UNSG32 usmAnaGrpCtl_ixtal                          :  2;\
            UNSG32 usmAnaGrpCtl_icc10u_in_sel                  :  1;\
            UNSG32 usmAnaGrpCtl_reserve_out                    :  6;\
            UNSG32 RSVDx48_b27                                 :  5;\
          }
    union { UNSG32 u32smSysCtl_smAnaGrpCtl1;
            struct w32smSysCtl_smAnaGrpCtl1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r32)   _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r16)   _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r32)   _BFGET_(r32, 2, 2)
    #define   SET32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r16)   _BFGET_(r16, 2, 2)
    #define   SET16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32smSysCtl_SM_CORE_CTRL_PAD_ZP(r32)           _BFGET_(r32, 6, 3)
    #define   SET32smSysCtl_SM_CORE_CTRL_PAD_ZP(r32,v)         _BFSET_(r32, 6, 3,v)
    #define   GET16smSysCtl_SM_CORE_CTRL_PAD_ZP(r16)           _BFGET_(r16, 6, 3)
    #define   SET16smSysCtl_SM_CORE_CTRL_PAD_ZP(r16,v)         _BFSET_(r16, 6, 3,v)

    #define   GET32smSysCtl_SM_CORE_CTRL_PAD_ZN(r32)           _BFGET_(r32,10, 7)
    #define   SET32smSysCtl_SM_CORE_CTRL_PAD_ZN(r32,v)         _BFSET_(r32,10, 7,v)
    #define   GET16smSysCtl_SM_CORE_CTRL_PAD_ZN(r16)           _BFGET_(r16,10, 7)
    #define   SET16smSysCtl_SM_CORE_CTRL_PAD_ZN(r16,v)         _BFSET_(r16,10, 7,v)

    #define     w32smSysCtl_SM_CORE_CTRL                       {\
            UNSG32 uSM_CORE_CTRL_PAD_REG_PDB_CORE              :  1;\
            UNSG32 uSM_CORE_CTRL_PAD_V18EN_CORE                :  1;\
            UNSG32 uSM_CORE_CTRL_PAD_V25EN_CORE                :  1;\
            UNSG32 uSM_CORE_CTRL_PAD_ZP                        :  4;\
            UNSG32 uSM_CORE_CTRL_PAD_ZN                        :  4;\
            UNSG32 RSVDx4C_b11                                 : 21;\
          }
    union { UNSG32 u32smSysCtl_SM_CORE_CTRL;
            struct w32smSysCtl_SM_CORE_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_TEST_ADC_TEST_FAIL(r32)         _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_TEST_ADC_TEST_FAIL(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_TEST_ADC_TEST_FAIL(r16)         _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_TEST_ADC_TEST_FAIL(r16,v)       _BFSET_(r16, 0, 0,v)

    #define     w32smSysCtl_SM_TEST                            {\
            UNSG32 uSM_TEST_ADC_TEST_FAIL                      :  1;\
            UNSG32 RSVDx50_b1                                  : 31;\
          }
    union { UNSG32 u32smSysCtl_SM_TEST;
            struct w32smSysCtl_SM_TEST;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r32)   _BFGET_(r32, 9, 0)
    #define   SET32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r32,v) _BFSET_(r32, 9, 0,v)
    #define   GET16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r16)   _BFGET_(r16, 9, 0)
    #define   SET16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r16,v) _BFSET_(r16, 9, 0,v)

    #define     w32smSysCtl_SM_TEST_DATA0                      {\
            UNSG32 uSM_TEST_DATA0_ADC_DATA_HIGH                : 10;\
            UNSG32 RSVDx54_b10                                 : 22;\
          }
    union { UNSG32 u32smSysCtl_SM_TEST_DATA0;
            struct w32smSysCtl_SM_TEST_DATA0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r32)    _BFGET_(r32, 9, 0)
    #define   SET32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r32,v)  _BFSET_(r32, 9, 0,v)
    #define   GET16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r16)    _BFGET_(r16, 9, 0)
    #define   SET16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r16,v)  _BFSET_(r16, 9, 0,v)

    #define     w32smSysCtl_SM_TEST_DATA1                      {\
            UNSG32 uSM_TEST_DATA1_ADC_DATA_LOW                 : 10;\
            UNSG32 RSVDx58_b10                                 : 22;\
          }
    union { UNSG32 u32smSysCtl_SM_TEST_DATA1;
            struct w32smSysCtl_SM_TEST_DATA1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r32)       _BFGET_(r32, 3, 0)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r32,v)     _BFSET_(r32, 3, 0,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r16)       _BFGET_(r16, 3, 0)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r16,v)     _BFSET_(r16, 3, 0,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r32)      _BFGET_(r32, 7, 4)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r32,v)    _BFSET_(r32, 7, 4,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r16)      _BFGET_(r16, 7, 4)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r16,v)    _BFSET_(r16, 7, 4,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r32)       _BFGET_(r32,11, 8)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r32,v)     _BFSET_(r32,11, 8,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r16)       _BFGET_(r16,11, 8)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r16,v)     _BFSET_(r16,11, 8,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r32)      _BFGET_(r32,15,12)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r32,v)    _BFSET_(r32,15,12,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r16)      _BFGET_(r16,15,12)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r16,v)    _BFSET_(r16,15,12,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r32)       _BFGET_(r32,19,16)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r32,v)     _BFSET_(r32,19,16,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r16)       _BFGET_(r16, 3, 0)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r16,v)     _BFSET_(r16, 3, 0,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r32)      _BFGET_(r32,23,20)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r32,v)    _BFSET_(r32,23,20,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r16)      _BFGET_(r16, 7, 4)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r16,v)    _BFSET_(r16, 7, 4,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r32)       _BFGET_(r32,27,24)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r32,v)     _BFSET_(r32,27,24,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r16)       _BFGET_(r16,11, 8)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r16,v)     _BFSET_(r16,11, 8,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r32)      _BFGET_(r32,31,28)
    #define   SET32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r32,v)    _BFSET_(r32,31,28,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r16)      _BFGET_(r16,15,12)
    #define   SET16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r16,v)    _BFSET_(r16,15,12,v)

    #define     w32smSysCtl_SM_RWTC_CTRL_0                     {\
            UNSG32 uSM_RWTC_CTRL_0_RF1P_LOW                    :  4;\
            UNSG32 uSM_RWTC_CTRL_0_RF1P_HIGH                   :  4;\
            UNSG32 uSM_RWTC_CTRL_0_RF2P_LOW                    :  4;\
            UNSG32 uSM_RWTC_CTRL_0_RF2P_HIGH                   :  4;\
            UNSG32 uSM_RWTC_CTRL_0_SR1P_LOW                    :  4;\
            UNSG32 uSM_RWTC_CTRL_0_SR1P_HIGH                   :  4;\
            UNSG32 uSM_RWTC_CTRL_0_SR2P_LOW                    :  4;\
            UNSG32 uSM_RWTC_CTRL_0_SR2P_HIGH                   :  4;\
          }
    union { UNSG32 u32smSysCtl_SM_RWTC_CTRL_0;
            struct w32smSysCtl_SM_RWTC_CTRL_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r32)        _BFGET_(r32, 4, 0)
    #define   SET32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r32,v)      _BFSET_(r32, 4, 0,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r16)        _BFGET_(r16, 4, 0)
    #define   SET16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r16,v)      _BFSET_(r16, 4, 0,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r32)       _BFGET_(r32, 9, 5)
    #define   SET32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r32,v)     _BFSET_(r32, 9, 5,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r16)       _BFGET_(r16, 9, 5)
    #define   SET16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r16,v)     _BFSET_(r16, 9, 5,v)

    #define   GET32smSysCtl_SM_RWTC_CTRL_1_ACMEM(r32)          _BFGET_(r32,13,10)
    #define   SET32smSysCtl_SM_RWTC_CTRL_1_ACMEM(r32,v)        _BFSET_(r32,13,10,v)
    #define   GET16smSysCtl_SM_RWTC_CTRL_1_ACMEM(r16)          _BFGET_(r16,13,10)
    #define   SET16smSysCtl_SM_RWTC_CTRL_1_ACMEM(r16,v)        _BFSET_(r16,13,10,v)

    #define     w32smSysCtl_SM_RWTC_CTRL_1                     {\
            UNSG32 uSM_RWTC_CTRL_1_ROM_LOW                     :  5;\
            UNSG32 uSM_RWTC_CTRL_1_ROM_HIGH                    :  5;\
            UNSG32 uSM_RWTC_CTRL_1_ACMEM                       :  4;\
            UNSG32 RSVDx60_b14                                 : 18;\
          }
    union { UNSG32 u32smSysCtl_SM_RWTC_CTRL_1;
            struct w32smSysCtl_SM_RWTC_CTRL_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_PORT_SEL_CTRL_TW2(r32)          _BFGET_(r32, 0, 0)
    #define   SET32smSysCtl_SM_PORT_SEL_CTRL_TW2(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16smSysCtl_SM_PORT_SEL_CTRL_TW2(r16)          _BFGET_(r16, 0, 0)
    #define   SET16smSysCtl_SM_PORT_SEL_CTRL_TW2(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32smSysCtl_SM_PORT_SEL_CTRL_URT1(r32)         _BFGET_(r32, 1, 1)
    #define   SET32smSysCtl_SM_PORT_SEL_CTRL_URT1(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16smSysCtl_SM_PORT_SEL_CTRL_URT1(r16)         _BFGET_(r16, 1, 1)
    #define   SET16smSysCtl_SM_PORT_SEL_CTRL_URT1(r16,v)       _BFSET_(r16, 1, 1,v)

    #define     w32smSysCtl_SM_PORT_SEL_CTRL                   {\
            UNSG32 uSM_PORT_SEL_CTRL_TW2                       :  1;\
            UNSG32 uSM_PORT_SEL_CTRL_URT1                      :  1;\
            UNSG32 RSVDx64_b2                                  : 30;\
          }
    union { UNSG32 u32smSysCtl_SM_PORT_SEL_CTRL;
            struct w32smSysCtl_SM_PORT_SEL_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r32) _BFGET_(r32,11, 0)
    #define   SET32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r32,v) _BFSET_(r32,11, 0,v)
    #define   GET16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r16) _BFGET_(r16,11, 0)
    #define   SET16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r16,v) _BFSET_(r16,11, 0,v)

    #define     w32smSysCtl_TSEN_ADC_RAW_DATA                  {\
            UNSG32 uTSEN_ADC_RAW_DATA_TSEN_DATA_RAW            : 12;\
            UNSG32 RSVDx68_b12                                 : 20;\
          }
    union { UNSG32 u32smSysCtl_TSEN_ADC_RAW_DATA;
            struct w32smSysCtl_TSEN_ADC_RAW_DATA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r32)      _BFGET_(r32, 2, 0)
    #define   SET32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r32,v)    _BFSET_(r32, 2, 0,v)
    #define   GET16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r16)      _BFGET_(r16, 2, 0)
    #define   SET16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r16,v)    _BFSET_(r16, 2, 0,v)

    #define   GET32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r32)     _BFGET_(r32, 6, 3)
    #define   SET32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r32,v)   _BFSET_(r32, 6, 3,v)
    #define   GET16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r16)     _BFGET_(r16, 6, 3)
    #define   SET16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r16,v)   _BFSET_(r16, 6, 3,v)

    #define     w32smSysCtl_TSEN_ADC_CLK_DIV                   {\
            UNSG32 uTSEN_ADC_CLK_DIV_ADC_DIV                   :  3;\
            UNSG32 uTSEN_ADC_CLK_DIV_TSEN_DIV                  :  4;\
            UNSG32 RSVDx6C_b7                                  : 25;\
          }
    union { UNSG32 u32smSysCtl_TSEN_ADC_CLK_DIV;
            struct w32smSysCtl_TSEN_ADC_CLK_DIV;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r32)    _BFGET_(r32, 7, 0)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r32,v)  _BFSET_(r32, 7, 0,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r16)    _BFGET_(r16, 7, 0)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r16,v)  _BFSET_(r16, 7, 0,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_TSEN_START(r32)      _BFGET_(r32, 8, 8)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_TSEN_START(r32,v)    _BFSET_(r32, 8, 8,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_TSEN_START(r16)      _BFGET_(r16, 8, 8)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_TSEN_START(r16,v)    _BFSET_(r16, 8, 8,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r32)    _BFGET_(r32,11, 9)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r32,v)  _BFSET_(r32,11, 9,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r16)    _BFGET_(r16,11, 9)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r16,v)  _BFSET_(r16,11, 9,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r32)     _BFGET_(r32,12,12)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r32,v)   _BFSET_(r32,12,12,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r16)     _BFGET_(r16,12,12)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r16,v)   _BFSET_(r16,12,12,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r32)    _BFGET_(r32,14,13)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r32,v)  _BFSET_(r32,14,13,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r16)    _BFGET_(r16,14,13)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r16,v)  _BFSET_(r16,14,13,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL(r32)        _BFGET_(r32,16,15)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL(r32,v)      _BFSET_(r32,16,15,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r32)       _BFGET_(r32,20,17)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r32,v)     _BFSET_(r32,20,17,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r16)       _BFGET_(r16, 4, 1)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r16,v)     _BFSET_(r16, 4, 1,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r32)      _BFGET_(r32,21,21)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r32,v)    _BFSET_(r32,21,21,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r16)      _BFGET_(r16, 5, 5)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r32)        _BFGET_(r32,25,22)
    #define   SET32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r32,v)      _BFSET_(r32,25,22,v)
    #define   GET16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r16)        _BFGET_(r16, 9, 6)
    #define   SET16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r16,v)      _BFSET_(r16, 9, 6,v)

    #define     w32smSysCtl_TSEN_ADC_CTRL                      {\
            UNSG32 uTSEN_ADC_CTRL_ADC_VREF_ADJ                 :  8;\
            UNSG32 uTSEN_ADC_CTRL_TSEN_START                   :  1;\
            UNSG32 uTSEN_ADC_CTRL_TSEN_AVG_NUM                 :  3;\
            UNSG32 uTSEN_ADC_CTRL_TSEN_EXT_EN                  :  1;\
            UNSG32 uTSEN_ADC_CTRL_TSEN_CHOP_EN                 :  2;\
            UNSG32 uTSEN_ADC_CTRL_TSEN_CAL                     :  2;\
            UNSG32 uTSEN_ADC_CTRL_TSEN_RSVD                    :  4;\
            UNSG32 uTSEN_ADC_CTRL_BG_CHP_SEL                   :  1;\
            UNSG32 uTSEN_ADC_CTRL_BG_DTRIM                     :  4;\
            UNSG32 RSVDx70_b26                                 :  6;\
          }
    union { UNSG32 u32smSysCtl_TSEN_ADC_CTRL;
            struct w32smSysCtl_TSEN_ADC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r32)     _BFGET_(r32, 1, 0)
    #define   SET32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r32,v)   _BFSET_(r32, 1, 0,v)
    #define   GET16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r16)     _BFGET_(r16, 1, 0)
    #define   SET16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r16,v)   _BFSET_(r16, 1, 0,v)

    #define     w32smSysCtl_TSEN_ADC_DBG                       {\
            UNSG32 uTSEN_ADC_DBG_TSEN_RAW_SEL                  :  2;\
            UNSG32 RSVDx74_b2                                  : 30;\
          }
    union { UNSG32 u32smSysCtl_TSEN_ADC_DBG;
            struct w32smSysCtl_TSEN_ADC_DBG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_SM_DUMMY_REG_REG0(r32)             _BFGET_(r32,31, 0)
    #define   SET32smSysCtl_SM_DUMMY_REG_REG0(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32smSysCtl_SM_DUMMY_REG                       {\
            UNSG32 uSM_DUMMY_REG_REG0                          : 32;\
          }
    union { UNSG32 u32smSysCtl_SM_DUMMY_REG;
            struct w32smSysCtl_SM_DUMMY_REG;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx7C                                     [388];
    ///////////////////////////////////////////////////////////
    #define   GET32smSysCtl_smPinMuxCntlBus_SM_TMS(r32)        _BFGET_(r32, 2, 0)
    #define   SET32smSysCtl_smPinMuxCntlBus_SM_TMS(r32,v)      _BFSET_(r32, 2, 0,v)
    #define   GET16smSysCtl_smPinMuxCntlBus_SM_TMS(r16)        _BFGET_(r16, 2, 0)
    #define   SET16smSysCtl_smPinMuxCntlBus_SM_TMS(r16,v)      _BFSET_(r16, 2, 0,v)

    #define   GET32smSysCtl_smPinMuxCntlBus_SM_TDI(r32)        _BFGET_(r32, 5, 3)
    #define   SET32smSysCtl_smPinMuxCntlBus_SM_TDI(r32,v)      _BFSET_(r32, 5, 3,v)
    #define   GET16smSysCtl_smPinMuxCntlBus_SM_TDI(r16)        _BFGET_(r16, 5, 3)
    #define   SET16smSysCtl_smPinMuxCntlBus_SM_TDI(r16,v)      _BFSET_(r16, 5, 3,v)

    #define   GET32smSysCtl_smPinMuxCntlBus_SM_TDO(r32)        _BFGET_(r32, 8, 6)
    #define   SET32smSysCtl_smPinMuxCntlBus_SM_TDO(r32,v)      _BFSET_(r32, 8, 6,v)
    #define   GET16smSysCtl_smPinMuxCntlBus_SM_TDO(r16)        _BFGET_(r16, 8, 6)
    #define   SET16smSysCtl_smPinMuxCntlBus_SM_TDO(r16,v)      _BFSET_(r16, 8, 6,v)

    #define     w32smSysCtl_smPinMuxCntlBus                    {\
            UNSG32 usmPinMuxCntlBus_SM_TMS                     :  3;\
            UNSG32 usmPinMuxCntlBus_SM_TDI                     :  3;\
            UNSG32 usmPinMuxCntlBus_SM_TDO                     :  3;\
            UNSG32 RSVDx200_b9                                 : 23;\
          }
    union { UNSG32 u32smSysCtl_smPinMuxCntlBus;
            struct w32smSysCtl_smPinMuxCntlBus;
          };
    ///////////////////////////////////////////////////////////
    } SIE_smSysCtl;

    typedef union  T32smSysCtl_SM_ID
          { UNSG32 u32;
            struct w32smSysCtl_SM_ID;
                 } T32smSysCtl_SM_ID;
    typedef union  T32smSysCtl_SM_CPU_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_CPU_CTRL;
                 } T32smSysCtl_SM_CPU_CTRL;
    typedef union  T32smSysCtl_SM_RST_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_RST_CTRL;
                 } T32smSysCtl_SM_RST_CTRL;
    typedef union  T32smSysCtl_SM_RST_STATUS
          { UNSG32 u32;
            struct w32smSysCtl_SM_RST_STATUS;
                 } T32smSysCtl_SM_RST_STATUS;
    typedef union  T32smSysCtl_SM_STRP_STATUS
          { UNSG32 u32;
            struct w32smSysCtl_SM_STRP_STATUS;
                 } T32smSysCtl_SM_STRP_STATUS;
    typedef union  T32smSysCtl_SM_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_CTRL;
                 } T32smSysCtl_SM_CTRL;
    typedef union  T32smSysCtl_SM_ADC_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_ADC_CTRL;
                 } T32smSysCtl_SM_ADC_CTRL;
    typedef union  T32smSysCtl_SM_ADC_STATUS
          { UNSG32 u32;
            struct w32smSysCtl_SM_ADC_STATUS;
                 } T32smSysCtl_SM_ADC_STATUS;
    typedef union  T32smSysCtl_SM_ADC_DATA
          { UNSG32 u32;
            struct w32smSysCtl_SM_ADC_DATA;
                 } T32smSysCtl_SM_ADC_DATA;
    typedef union  T32smSysCtl_TSEN_ADC_STATUS
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_ADC_STATUS;
                 } T32smSysCtl_TSEN_ADC_STATUS;
    typedef union  T32smSysCtl_TSEN_ADC_DATA
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_ADC_DATA;
                 } T32smSysCtl_TSEN_ADC_DATA;
    typedef union  T32smSysCtl_TSEN_CHK_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_CHK_CTRL;
                 } T32smSysCtl_TSEN_CHK_CTRL;
    typedef union  T32smSysCtl_TSEN_DATA_STATUS
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_DATA_STATUS;
                 } T32smSysCtl_TSEN_DATA_STATUS;
    typedef union  T32smSysCtl_SM_BOOT_STATUS
          { UNSG32 u32;
            struct w32smSysCtl_SM_BOOT_STATUS;
                 } T32smSysCtl_SM_BOOT_STATUS;
    typedef union  T32smSysCtl_SM_LDO_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_LDO_CTRL;
                 } T32smSysCtl_SM_LDO_CTRL;
    typedef union  T32smSysCtl_SM_WDT_MASK
          { UNSG32 u32;
            struct w32smSysCtl_SM_WDT_MASK;
                 } T32smSysCtl_SM_WDT_MASK;
    typedef union  T32smSysCtl_SM_CLK_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_CLK_CTRL;
                 } T32smSysCtl_SM_CLK_CTRL;
    typedef union  T32smSysCtl_smAnaGrpCtl
          { UNSG32 u32;
            struct w32smSysCtl_smAnaGrpCtl;
                 } T32smSysCtl_smAnaGrpCtl;
    typedef union  T32smSysCtl_smAnaGrpCtl1
          { UNSG32 u32;
            struct w32smSysCtl_smAnaGrpCtl1;
                 } T32smSysCtl_smAnaGrpCtl1;
    typedef union  T32smSysCtl_SM_CORE_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_CORE_CTRL;
                 } T32smSysCtl_SM_CORE_CTRL;
    typedef union  T32smSysCtl_SM_TEST
          { UNSG32 u32;
            struct w32smSysCtl_SM_TEST;
                 } T32smSysCtl_SM_TEST;
    typedef union  T32smSysCtl_SM_TEST_DATA0
          { UNSG32 u32;
            struct w32smSysCtl_SM_TEST_DATA0;
                 } T32smSysCtl_SM_TEST_DATA0;
    typedef union  T32smSysCtl_SM_TEST_DATA1
          { UNSG32 u32;
            struct w32smSysCtl_SM_TEST_DATA1;
                 } T32smSysCtl_SM_TEST_DATA1;
    typedef union  T32smSysCtl_SM_RWTC_CTRL_0
          { UNSG32 u32;
            struct w32smSysCtl_SM_RWTC_CTRL_0;
                 } T32smSysCtl_SM_RWTC_CTRL_0;
    typedef union  T32smSysCtl_SM_RWTC_CTRL_1
          { UNSG32 u32;
            struct w32smSysCtl_SM_RWTC_CTRL_1;
                 } T32smSysCtl_SM_RWTC_CTRL_1;
    typedef union  T32smSysCtl_SM_PORT_SEL_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_SM_PORT_SEL_CTRL;
                 } T32smSysCtl_SM_PORT_SEL_CTRL;
    typedef union  T32smSysCtl_TSEN_ADC_RAW_DATA
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_ADC_RAW_DATA;
                 } T32smSysCtl_TSEN_ADC_RAW_DATA;
    typedef union  T32smSysCtl_TSEN_ADC_CLK_DIV
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_ADC_CLK_DIV;
                 } T32smSysCtl_TSEN_ADC_CLK_DIV;
    typedef union  T32smSysCtl_TSEN_ADC_CTRL
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_ADC_CTRL;
                 } T32smSysCtl_TSEN_ADC_CTRL;
    typedef union  T32smSysCtl_TSEN_ADC_DBG
          { UNSG32 u32;
            struct w32smSysCtl_TSEN_ADC_DBG;
                 } T32smSysCtl_TSEN_ADC_DBG;
    typedef union  T32smSysCtl_SM_DUMMY_REG
          { UNSG32 u32;
            struct w32smSysCtl_SM_DUMMY_REG;
                 } T32smSysCtl_SM_DUMMY_REG;
    typedef union  T32smSysCtl_smPinMuxCntlBus
          { UNSG32 u32;
            struct w32smSysCtl_smPinMuxCntlBus;
                 } T32smSysCtl_smPinMuxCntlBus;
    ///////////////////////////////////////////////////////////

    typedef union  TsmSysCtl_SM_ID
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_ID;
                   };
                 } TsmSysCtl_SM_ID;
    typedef union  TsmSysCtl_SM_CPU_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_CPU_CTRL;
                   };
                 } TsmSysCtl_SM_CPU_CTRL;
    typedef union  TsmSysCtl_SM_RST_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_RST_CTRL;
                   };
                 } TsmSysCtl_SM_RST_CTRL;
    typedef union  TsmSysCtl_SM_RST_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_RST_STATUS;
                   };
                 } TsmSysCtl_SM_RST_STATUS;
    typedef union  TsmSysCtl_SM_STRP_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_STRP_STATUS;
                   };
                 } TsmSysCtl_SM_STRP_STATUS;
    typedef union  TsmSysCtl_SM_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_CTRL;
                   };
                 } TsmSysCtl_SM_CTRL;
    typedef union  TsmSysCtl_SM_ADC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_ADC_CTRL;
                   };
                 } TsmSysCtl_SM_ADC_CTRL;
    typedef union  TsmSysCtl_SM_ADC_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_ADC_STATUS;
                   };
                 } TsmSysCtl_SM_ADC_STATUS;
    typedef union  TsmSysCtl_SM_ADC_DATA
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_ADC_DATA;
                   };
                 } TsmSysCtl_SM_ADC_DATA;
    typedef union  TsmSysCtl_TSEN_ADC_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_ADC_STATUS;
                   };
                 } TsmSysCtl_TSEN_ADC_STATUS;
    typedef union  TsmSysCtl_TSEN_ADC_DATA
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_ADC_DATA;
                   };
                 } TsmSysCtl_TSEN_ADC_DATA;
    typedef union  TsmSysCtl_TSEN_CHK_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_CHK_CTRL;
                   };
                 } TsmSysCtl_TSEN_CHK_CTRL;
    typedef union  TsmSysCtl_TSEN_DATA_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_DATA_STATUS;
                   };
                 } TsmSysCtl_TSEN_DATA_STATUS;
    typedef union  TsmSysCtl_SM_BOOT_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_BOOT_STATUS;
                   };
                 } TsmSysCtl_SM_BOOT_STATUS;
    typedef union  TsmSysCtl_SM_LDO_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_LDO_CTRL;
                   };
                 } TsmSysCtl_SM_LDO_CTRL;
    typedef union  TsmSysCtl_SM_WDT_MASK
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_WDT_MASK;
                   };
                 } TsmSysCtl_SM_WDT_MASK;
    typedef union  TsmSysCtl_SM_CLK_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_CLK_CTRL;
                   };
                 } TsmSysCtl_SM_CLK_CTRL;
    typedef union  TsmSysCtl_smAnaGrpCtl
          { UNSG32 u32[2];
            struct {
            struct w32smSysCtl_smAnaGrpCtl;
            struct w32smSysCtl_smAnaGrpCtl1;
                   };
                 } TsmSysCtl_smAnaGrpCtl;
    typedef union  TsmSysCtl_SM_CORE_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_CORE_CTRL;
                   };
                 } TsmSysCtl_SM_CORE_CTRL;
    typedef union  TsmSysCtl_SM_TEST
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_TEST;
                   };
                 } TsmSysCtl_SM_TEST;
    typedef union  TsmSysCtl_SM_TEST_DATA0
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_TEST_DATA0;
                   };
                 } TsmSysCtl_SM_TEST_DATA0;
    typedef union  TsmSysCtl_SM_TEST_DATA1
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_TEST_DATA1;
                   };
                 } TsmSysCtl_SM_TEST_DATA1;
    typedef union  TsmSysCtl_SM_RWTC_CTRL_0
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_RWTC_CTRL_0;
                   };
                 } TsmSysCtl_SM_RWTC_CTRL_0;
    typedef union  TsmSysCtl_SM_RWTC_CTRL_1
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_RWTC_CTRL_1;
                   };
                 } TsmSysCtl_SM_RWTC_CTRL_1;
    typedef union  TsmSysCtl_SM_PORT_SEL_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_PORT_SEL_CTRL;
                   };
                 } TsmSysCtl_SM_PORT_SEL_CTRL;
    typedef union  TsmSysCtl_TSEN_ADC_RAW_DATA
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_ADC_RAW_DATA;
                   };
                 } TsmSysCtl_TSEN_ADC_RAW_DATA;
    typedef union  TsmSysCtl_TSEN_ADC_CLK_DIV
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_ADC_CLK_DIV;
                   };
                 } TsmSysCtl_TSEN_ADC_CLK_DIV;
    typedef union  TsmSysCtl_TSEN_ADC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_ADC_CTRL;
                   };
                 } TsmSysCtl_TSEN_ADC_CTRL;
    typedef union  TsmSysCtl_TSEN_ADC_DBG
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_TSEN_ADC_DBG;
                   };
                 } TsmSysCtl_TSEN_ADC_DBG;
    typedef union  TsmSysCtl_SM_DUMMY_REG
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_SM_DUMMY_REG;
                   };
                 } TsmSysCtl_SM_DUMMY_REG;
    typedef union  TsmSysCtl_smPinMuxCntlBus
          { UNSG32 u32[1];
            struct {
            struct w32smSysCtl_smPinMuxCntlBus;
                   };
                 } TsmSysCtl_smPinMuxCntlBus;

    ///////////////////////////////////////////////////////////
     SIGN32 smSysCtl_drvrd(SIE_smSysCtl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 smSysCtl_drvwr(SIE_smSysCtl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void smSysCtl_reset(SIE_smSysCtl *p);
     SIGN32 smSysCtl_cmp  (SIE_smSysCtl *p, SIE_smSysCtl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define smSysCtl_check(p,pie,pfx,hLOG) smSysCtl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define smSysCtl_print(p,    pfx,hLOG) smSysCtl_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: smSysCtl
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: SysMgr.h
////////////////////////////////////////////////////////////