/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//////
/// don't edit! auto-generated by docc: cec.h
////////////////////////////////////////////////////////////
#ifndef cec_h
#define cec_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE oneReg                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (R-)
///               %unsigned 32 0x00000000                
///                                    ###
///                                    * One Register in K2 block.
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_oneReg
#define h_oneReg (){}

    #define     BA_oneReg_0x00000000                           0x0000
    #define     B16oneReg_0x00000000                           0x0000
    #define   LSb32oneReg_0x00000000                              0
    #define   LSb16oneReg_0x00000000                              0
    #define       boneReg_0x00000000                           32
    #define   MSK32oneReg_0x00000000                              0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_oneReg {
    ///////////////////////////////////////////////////////////
    #define   GET32oneReg_0x00000000(r32)                      _BFGET_(r32,31, 0)
    #define   SET32oneReg_0x00000000(r32,v)                    _BFSET_(r32,31, 0,v)

            UNSG32 u_0x00000000                                : 32;
    ///////////////////////////////////////////////////////////
    } SIE_oneReg;

    ///////////////////////////////////////////////////////////
     SIGN32 oneReg_drvrd(SIE_oneReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 oneReg_drvwr(SIE_oneReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void oneReg_reset(SIE_oneReg *p);
     SIGN32 oneReg_cmp  (SIE_oneReg *p, SIE_oneReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define oneReg_check(p,pie,pfx,hLOG) oneReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define oneReg_print(p,    pfx,hLOG) oneReg_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: oneReg
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE Cec_REG                                  (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 dummy                
///               $oneReg              dummy             REG     [256]
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    1024B, bits:    8192b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_Cec_REG
#define h_Cec_REG (){}

    #define     RA_Cec_REG_dummy                               0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_Cec_REG {
    ///////////////////////////////////////////////////////////
              SIE_oneReg                                       ie_dummy[256];
    ///////////////////////////////////////////////////////////
    } SIE_Cec_REG;

    ///////////////////////////////////////////////////////////
     SIGN32 Cec_REG_drvrd(SIE_Cec_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 Cec_REG_drvwr(SIE_Cec_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void Cec_REG_reset(SIE_Cec_REG *p);
     SIGN32 Cec_REG_cmp  (SIE_Cec_REG *p, SIE_Cec_REG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define Cec_REG_check(p,pie,pfx,hLOG) Cec_REG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define Cec_REG_print(p,    pfx,hLOG) Cec_REG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: Cec_REG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE Eddc_REG                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 dummy                
///               $oneReg              dummy             REG     [512]
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    2048B, bits:   16384b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_Eddc_REG
#define h_Eddc_REG (){}

    #define     RA_Eddc_REG_dummy                              0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_Eddc_REG {
    ///////////////////////////////////////////////////////////
              SIE_oneReg                                       ie_dummy[512];
    ///////////////////////////////////////////////////////////
    } SIE_Eddc_REG;

    ///////////////////////////////////////////////////////////
     SIGN32 Eddc_REG_drvrd(SIE_Eddc_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 Eddc_REG_drvwr(SIE_Eddc_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void Eddc_REG_reset(SIE_Eddc_REG *p);
     SIGN32 Eddc_REG_cmp  (SIE_Eddc_REG *p, SIE_Eddc_REG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define Eddc_REG_check(p,pie,pfx,hLOG) Eddc_REG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define Eddc_REG_print(p,    pfx,hLOG) Eddc_REG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: Eddc_REG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE Cec                     biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (R-)
///     # 0x00000 cfgReg               
///               $Cec_REG             cfgReg            MEM          
///                                    ###
///                                    * SRAM interface to access CEC MBUS registers.
///                                    ###
///     @ 0x00400 regIfCtrl            (P)
///               %unsigned 8  mwrWidth                  0x1
///                                    ###
///                                    * Specifies the width of the MWR pulse (in terms of sysClks) to CEC block.
///                                    ###
///               %unsigned 8  hold                      0x1
///                                    ###
///                                    * Specifies the time (in terms of vppSysClks) between K2 read data mux output to sample point in VPP BIU.
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00404 FEPHY_CTRL           (P)
///               ###
///               * Configuration registers for Fast Ethernet PHY
///               ###
///               %unsigned 5  ext_pwrdn_a               0x1
///                                    ###
///                                    * When ext_pwrdn_a transitions from 1 to 0 register
///                                    * 0.11 set to 1'b0
///                                    * When ext_pwrdn_a transitions from 0 to 1 register
///                                    * 0.11 set to 1'b1
///                                    ###
///               %unsigned 3  pd_aneg_mode_a            0x0
///                                    ###
///                                    * Port 0 Autoneg default setup:
///                                    * 000 = force 10T
///                                    * 001 = force 100T
///                                    * 010 = advertise all 10/100 capabilities
///                                    * 011 = reserved
///                                    * 1xx = force 100FX
///                                    ###
///               %unsigned 5  pd_phyadr_a               0x0
///                                    ###
///                                    * Starting PHY address for Port0
///                                    * Port 1 PHY address = Port 0 PHY address + 1
///                                    * Port 2 PHY address = Port 1 PHY address + 1
///                                    * Port 3 PHY address = Port 2 PHY address + 1
///                                    * Port 4 PHY address = Port 3 PHY address + 1
///                                    ###
///               %unsigned 3  pd_led_config_a           0x0
///                                    ###
///                                    * change led registers 24:8:0 default
///                                    * 000 : 001 000 101
///                                    * 001 : 000 001 101
///                                    * 010 : 000 001 101
///                                    * 011 : 000 000 001
///                                    * 1xx : 000 000 101
///                                    * and change register 22.15:0 default
///                                    * 000: 0100 0100 0101 1000
///                                    * 001: 0100 0101 0100 1000
///                                    * 010: 0100 0010 0100 1010
///                                    * 011: 0100 1000 1010 0100
///                                    * 100: 0100 0010 0101 1000
///                                    * 101, 11x: 0100 1010 0100 0100
///                                    ###
///               %unsigned 5  yy_pecl_sdet_a            0x0
///                                    ###
///                                    * 100FX signal detect, only bit 0 for port 0 useful
///                                    ###
///               %unsigned 1  ps_en_eee10t_s            0x0
///                                    ###
///                                    * Enable EEE 10T. Compliant with EEE draft 1.2.
///                                    ###
///               %unsigned 1  ps_en_eee100t_s           0x0
///                                    ###
///                                    * Enable EEE 100T. Compliant with EEE draft 1.2.
///                                    ###
///               %unsigned 1  pd_burnin_a               0x0
///                                    ###
///                                    * 1 : put PHY in burn-in mode
///                                    * In Burnin a LFSR will drive RX. Hook up RX to TX to make chip in burnin.
///                                    ###
///               %unsigned 1  pd_ena_edet_a             0x0
///                                    ###
///                                    * Enable Energy detect.
///                                    * It is sampled on the deassertion of hardware reset
///                                    * and set the default of register 16.14
///                                    ###
///               %unsigned 1  pd_ena_xc_a               0x0
///                                    ###
///                                    * 1 : Enable Auto-Crossover; 0 : Disable
///                                    * Auto-Crossover
///                                    * Sets the default of Register 16.5:4
///                                    ###
///               %unsigned 1  ext_coma_a                0x0
///                                    ###
///                                    * To shut off FPHY operation if not in use to save power
///                                    ###
///               %%        5          # Stuffing bits...
///     @ 0x00408 FEPHY_STS            (R-)
///               %unsigned 1  misc_speed_s              0x0
///                                    ###
///                                    * Speed indicator; 1: 100M; 0: 10M
///                                    ###
///               %unsigned 1  misc_duplex_s             0x0
///                                    ###
///                                    * Duplex indicator; 1: full-duplex; 0: half-duplex
///                                    ###
///               %unsigned 1  misc_hcd_resolved_s       0x0
///                                    ###
///                                    * Speed resolved; 1: resolved; 0 : not-resolved
///                                    ###
///               %unsigned 1  misc_link_s               0x0
///                                    ###
///                                    * Link status; 1: up; 0: down
///                                    ###
///               %unsigned 1  misc_lpi_s                0x0
///                                    ###
///                                    * LPI state; 1: in LPI state; 0 : normal state. The
///                                    * misc_lpi_s signal shows PHY EEE capability status.
///                                    * Same as register 17.9.
///                                    ###
///               %unsigned 1  misc_rx_lpi_s             0x0
///                                    ###
///                                    * PHY Rx in lpi state
///                                    ###
///               %unsigned 1  misc_pause_s              0x0
///                                    ###
///                                    * Pause indicator; 1: Pause; 0: normal
///                                    ###
///               %unsigned 1  misc_lp_pause_s           0x0
///                                    ###
///                                    * Link partner Pause indicator; 1: Pause; 0: normal
///                                    ###
///               %unsigned 1  misc_int_s                0x0
///                                    ###
///                                    * Port interrupt; 1: interrupt; 0 : no interrupt
///                                    ###
///               %unsigned 1  misc_edet_status_s        0x0
///                                    ###
///                                    * Energy detect status; 1: detected; 0 : no-detected.
///                                    * Same as register 17.4.
///                                    ###
///               %unsigned 1  tx_latency_mark_a         0x0
///                                    ###
///                                    * transmit enable after TX FIFO
///                                    ###
///               %unsigned 1  misc_por_reset            0x0
///                                    ###
///                                    * Power on reset from analog com
///                                    ###
///               %%        20         # Stuffing bits...
///     @ 0x0040C MC_CTRL              (R-)
///               %unsigned 1  RESETn                    0x1
///                                    ###
///                                    * Controls the RESETn to external DRAM. This is driven to DDR-PHY without any buffering in SoC power-domain. The RESESTn to DRAM shall be asserted high during self-refresh, to drive a stable glitch-free signal, RESETn is moved to SM power-domain.
///                                    * *INTERNAL_ONLY**
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00410 regIfCtrlEddc        (P)
///               %unsigned 8  mwrWidth                  0x1
///                                    ###
///                                    * Specifies the width of the MWR pulse (in terms of 25MHz clock) to EDDC I2C slave and EDID SRAM block.
///                                    ###
///               %unsigned 8  hold                      0x1
///                                    ###
///                                    * Specifies the time (in terms of 25MHz clock) between MBUS read data mux output to sample point in CEC BIU.
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00414 EDID_CTRL0           (P)
///               %unsigned 7  slv0_addr                 0x50
///                                    ###
///                                    * Slave Address of the EDID #0
///                                    ###
///               %unsigned 7  slv1_addr                 0x50
///                                    ###
///                                    * Slave Address of the EDID #1
///                                    ###
///               %unsigned 7  slv2_addr                 0x50
///                                    ###
///                                    * Slave Address of the EDID #2
///                                    ###
///               %unsigned 7  slv3_addr                 0x50
///                                    ###
///                                    * Slave Address of the EDID #3
///                                    ###
///               %%        4          # Stuffing bits...
///     @ 0x00418 EDID_CTRL1           (P)
///               %unsigned 4  edid_sel                  0x0
///                                    ###
///                                    * Edid selection
///                                    * [0] – EDID #0 is selected for cpu access
///                                    * [1] – EDID #1 is selected for cpu access
///                                    * [2] – EDID #2 is selected for cpu access
///                                    * [3] – EDID #3 is selected for cpu access
///                                    ###
///               %unsigned 4  cpu_wr_done               0x0
///                                    ###
///                                    * HDMI-RX has 256 bytes of EDID memory (one segment), in EDDC mode
///                                    * there are maximum 127 segments. To facilitate these 127 segments, an
///                                    * interrupt is raised whenever A0 slave address is received. For this interrupt
///                                    * CPU should read the segment pointer value and copy 256 bytes of this
///                                    * EDID segment from its internal storage to EDID memory and set this bit.
///                                    * This bit will be auto cleared when current I2C transaction is completed
///                                    * (STOP received) unless cpu_wr_done_ac_dis bit is set.
///                                    * 0: CPU not yet wrote EDID memory.
///                                    * 1: CPU wrote EDID memory.
///                                    * [0] - CPU wrote EDID0 memory
///                                    * [1] - CPU wrote EDID1 memory
///                                    * [2] - CPU wrote EDID2 memory
///                                    * [3] - CPU wrote EDID3 memory
///                                    ###
///               %unsigned 4  cpu_wr_done_ac            0x0
///                                    ###
///                                    * 0: cpu_wr_done auto clear enabled.
///                                    * 1: cpu_wr_done auto clear disabled.
///                                    * In non EDDC mode, there will be only one segment of EDID, so S/W doesnt
///                                    * require interrupts to change segments. Once EDID is properly written into
///                                    * EDID memory set cpu_wr_done bit and this bit.
///                                    * [0] - cpu_wr_done auto clear disabled for edid0
///                                    * [1] - cpu_wr_done auto clear disabled for edid1
///                                    * [2] - cpu_wr_done auto clear disabled for edid2
///                                    * [3] - cpu_wr_done auto clear disabled for edid3
///                                    ###
///               %unsigned 4  cpu_wr_done_toggle        0x0
///                                    ###
///                                    * Toggling the cpu_wr_done
///                                    * [0] - cpu_wr_done toggle for edid0
///                                    * [1] - cpu_wr_done toggle for edid1
///                                    * [2] - cpu_wr_done toggle for edid2
///                                    * [3] - cpu_wr_done toggle for edid3
///                                    ###
///               %unsigned 4  edid_i2c_en               0x0
///                                    ###
///                                    * Enable the EDID
///                                    * [0] == 1 – EDID #0 is enabled
///                                    * [1] == 1 – EDID #1 is enabled
///                                    * [2] == 1 – EDID #2 is enabled
///                                    * [3] == 1 – EDID #3 is enabled
///                                    ###
///               %unsigned 4  intr_clr                  0x0
///                                    ###
///                                    * Interrupt clear for the EDID
///                                    * [0] == 1 – EDID #0 interrupt cleared
///                                    * [1] == 1 – EDID #1 interrupt cleared
///                                    * [2] == 1 – EDID #2 interrupt cleared
///                                    * [3] == 1 – EDID #3 interrupt cleared
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x0041C EDID_STS0            (R-)
///               %unsigned 8  edid0_seg_ptr             0x0
///                                    ###
///                                    * Segment pointer received for EDID #0
///                                    ###
///               %unsigned 8  edid1_seg_ptr             0x0
///                                    ###
///                                    * Segment pointer received for EDID #1
///                                    ###
///               %unsigned 8  edid2_seg_ptr             0x0
///                                    ###
///                                    * Segment pointer received for EDID #2
///                                    ###
///               %unsigned 8  edid3_seg_ptr             0x0
///                                    ###
///                                    * Segment pointer received for EDID #3
///                                    ###
///     @ 0x00420 EDID_STS1            (R-)
///               %unsigned 4  cpu_wr_done_sts           
///                                    ###
///                                    * Write from cpu into the edid memory is done.
///                                    * [0] write from cpu into the edid0 memory is done
///                                    * [1] write from cpu into the edid1 memory is done
///                                    * [2] write from cpu into the edid2 memory is done
///                                    * [3] write from cpu into the edid3 memory is done
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00424                      (W-)
///     #         # Stuffing bytes...
///               %% 7904
///     @ 0x00800                      (P)
///     # 0x00800 eddcReg              
///               $Eddc_REG            eddcReg           MEM          
///                                    ###
///                                    * SRAM interface to access EDDC I2C slave and EDID SRAM MBUS registers.
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    4096B, bits:     224b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_Cec
#define h_Cec (){}

    #define     RA_Cec_cfgReg                                  0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_regIfCtrl                               0x0400

    #define     BA_Cec_regIfCtrl_mwrWidth                      0x0400
    #define     B16Cec_regIfCtrl_mwrWidth                      0x0400
    #define   LSb32Cec_regIfCtrl_mwrWidth                         0
    #define   LSb16Cec_regIfCtrl_mwrWidth                         0
    #define       bCec_regIfCtrl_mwrWidth                      8
    #define   MSK32Cec_regIfCtrl_mwrWidth                         0x000000FF

    #define     BA_Cec_regIfCtrl_hold                          0x0401
    #define     B16Cec_regIfCtrl_hold                          0x0400
    #define   LSb32Cec_regIfCtrl_hold                             8
    #define   LSb16Cec_regIfCtrl_hold                             8
    #define       bCec_regIfCtrl_hold                          8
    #define   MSK32Cec_regIfCtrl_hold                             0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_FEPHY_CTRL                              0x0404

    #define     BA_Cec_FEPHY_CTRL_ext_pwrdn_a                  0x0404
    #define     B16Cec_FEPHY_CTRL_ext_pwrdn_a                  0x0404
    #define   LSb32Cec_FEPHY_CTRL_ext_pwrdn_a                     0
    #define   LSb16Cec_FEPHY_CTRL_ext_pwrdn_a                     0
    #define       bCec_FEPHY_CTRL_ext_pwrdn_a                  5
    #define   MSK32Cec_FEPHY_CTRL_ext_pwrdn_a                     0x0000001F

    #define     BA_Cec_FEPHY_CTRL_pd_aneg_mode_a               0x0404
    #define     B16Cec_FEPHY_CTRL_pd_aneg_mode_a               0x0404
    #define   LSb32Cec_FEPHY_CTRL_pd_aneg_mode_a                  5
    #define   LSb16Cec_FEPHY_CTRL_pd_aneg_mode_a                  5
    #define       bCec_FEPHY_CTRL_pd_aneg_mode_a               3
    #define   MSK32Cec_FEPHY_CTRL_pd_aneg_mode_a                  0x000000E0

    #define     BA_Cec_FEPHY_CTRL_pd_phyadr_a                  0x0405
    #define     B16Cec_FEPHY_CTRL_pd_phyadr_a                  0x0404
    #define   LSb32Cec_FEPHY_CTRL_pd_phyadr_a                     8
    #define   LSb16Cec_FEPHY_CTRL_pd_phyadr_a                     8
    #define       bCec_FEPHY_CTRL_pd_phyadr_a                  5
    #define   MSK32Cec_FEPHY_CTRL_pd_phyadr_a                     0x00001F00

    #define     BA_Cec_FEPHY_CTRL_pd_led_config_a              0x0405
    #define     B16Cec_FEPHY_CTRL_pd_led_config_a              0x0404
    #define   LSb32Cec_FEPHY_CTRL_pd_led_config_a                 13
    #define   LSb16Cec_FEPHY_CTRL_pd_led_config_a                 13
    #define       bCec_FEPHY_CTRL_pd_led_config_a              3
    #define   MSK32Cec_FEPHY_CTRL_pd_led_config_a                 0x0000E000

    #define     BA_Cec_FEPHY_CTRL_yy_pecl_sdet_a               0x0406
    #define     B16Cec_FEPHY_CTRL_yy_pecl_sdet_a               0x0406
    #define   LSb32Cec_FEPHY_CTRL_yy_pecl_sdet_a                  16
    #define   LSb16Cec_FEPHY_CTRL_yy_pecl_sdet_a                  0
    #define       bCec_FEPHY_CTRL_yy_pecl_sdet_a               5
    #define   MSK32Cec_FEPHY_CTRL_yy_pecl_sdet_a                  0x001F0000

    #define     BA_Cec_FEPHY_CTRL_ps_en_eee10t_s               0x0406
    #define     B16Cec_FEPHY_CTRL_ps_en_eee10t_s               0x0406
    #define   LSb32Cec_FEPHY_CTRL_ps_en_eee10t_s                  21
    #define   LSb16Cec_FEPHY_CTRL_ps_en_eee10t_s                  5
    #define       bCec_FEPHY_CTRL_ps_en_eee10t_s               1
    #define   MSK32Cec_FEPHY_CTRL_ps_en_eee10t_s                  0x00200000

    #define     BA_Cec_FEPHY_CTRL_ps_en_eee100t_s              0x0406
    #define     B16Cec_FEPHY_CTRL_ps_en_eee100t_s              0x0406
    #define   LSb32Cec_FEPHY_CTRL_ps_en_eee100t_s                 22
    #define   LSb16Cec_FEPHY_CTRL_ps_en_eee100t_s                 6
    #define       bCec_FEPHY_CTRL_ps_en_eee100t_s              1
    #define   MSK32Cec_FEPHY_CTRL_ps_en_eee100t_s                 0x00400000

    #define     BA_Cec_FEPHY_CTRL_pd_burnin_a                  0x0406
    #define     B16Cec_FEPHY_CTRL_pd_burnin_a                  0x0406
    #define   LSb32Cec_FEPHY_CTRL_pd_burnin_a                     23
    #define   LSb16Cec_FEPHY_CTRL_pd_burnin_a                     7
    #define       bCec_FEPHY_CTRL_pd_burnin_a                  1
    #define   MSK32Cec_FEPHY_CTRL_pd_burnin_a                     0x00800000

    #define     BA_Cec_FEPHY_CTRL_pd_ena_edet_a                0x0407
    #define     B16Cec_FEPHY_CTRL_pd_ena_edet_a                0x0406
    #define   LSb32Cec_FEPHY_CTRL_pd_ena_edet_a                   24
    #define   LSb16Cec_FEPHY_CTRL_pd_ena_edet_a                   8
    #define       bCec_FEPHY_CTRL_pd_ena_edet_a                1
    #define   MSK32Cec_FEPHY_CTRL_pd_ena_edet_a                   0x01000000

    #define     BA_Cec_FEPHY_CTRL_pd_ena_xc_a                  0x0407
    #define     B16Cec_FEPHY_CTRL_pd_ena_xc_a                  0x0406
    #define   LSb32Cec_FEPHY_CTRL_pd_ena_xc_a                     25
    #define   LSb16Cec_FEPHY_CTRL_pd_ena_xc_a                     9
    #define       bCec_FEPHY_CTRL_pd_ena_xc_a                  1
    #define   MSK32Cec_FEPHY_CTRL_pd_ena_xc_a                     0x02000000

    #define     BA_Cec_FEPHY_CTRL_ext_coma_a                   0x0407
    #define     B16Cec_FEPHY_CTRL_ext_coma_a                   0x0406
    #define   LSb32Cec_FEPHY_CTRL_ext_coma_a                      26
    #define   LSb16Cec_FEPHY_CTRL_ext_coma_a                      10
    #define       bCec_FEPHY_CTRL_ext_coma_a                   1
    #define   MSK32Cec_FEPHY_CTRL_ext_coma_a                      0x04000000
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_FEPHY_STS                               0x0408

    #define     BA_Cec_FEPHY_STS_misc_speed_s                  0x0408
    #define     B16Cec_FEPHY_STS_misc_speed_s                  0x0408
    #define   LSb32Cec_FEPHY_STS_misc_speed_s                     0
    #define   LSb16Cec_FEPHY_STS_misc_speed_s                     0
    #define       bCec_FEPHY_STS_misc_speed_s                  1
    #define   MSK32Cec_FEPHY_STS_misc_speed_s                     0x00000001

    #define     BA_Cec_FEPHY_STS_misc_duplex_s                 0x0408
    #define     B16Cec_FEPHY_STS_misc_duplex_s                 0x0408
    #define   LSb32Cec_FEPHY_STS_misc_duplex_s                    1
    #define   LSb16Cec_FEPHY_STS_misc_duplex_s                    1
    #define       bCec_FEPHY_STS_misc_duplex_s                 1
    #define   MSK32Cec_FEPHY_STS_misc_duplex_s                    0x00000002

    #define     BA_Cec_FEPHY_STS_misc_hcd_resolved_s           0x0408
    #define     B16Cec_FEPHY_STS_misc_hcd_resolved_s           0x0408
    #define   LSb32Cec_FEPHY_STS_misc_hcd_resolved_s              2
    #define   LSb16Cec_FEPHY_STS_misc_hcd_resolved_s              2
    #define       bCec_FEPHY_STS_misc_hcd_resolved_s           1
    #define   MSK32Cec_FEPHY_STS_misc_hcd_resolved_s              0x00000004

    #define     BA_Cec_FEPHY_STS_misc_link_s                   0x0408
    #define     B16Cec_FEPHY_STS_misc_link_s                   0x0408
    #define   LSb32Cec_FEPHY_STS_misc_link_s                      3
    #define   LSb16Cec_FEPHY_STS_misc_link_s                      3
    #define       bCec_FEPHY_STS_misc_link_s                   1
    #define   MSK32Cec_FEPHY_STS_misc_link_s                      0x00000008

    #define     BA_Cec_FEPHY_STS_misc_lpi_s                    0x0408
    #define     B16Cec_FEPHY_STS_misc_lpi_s                    0x0408
    #define   LSb32Cec_FEPHY_STS_misc_lpi_s                       4
    #define   LSb16Cec_FEPHY_STS_misc_lpi_s                       4
    #define       bCec_FEPHY_STS_misc_lpi_s                    1
    #define   MSK32Cec_FEPHY_STS_misc_lpi_s                       0x00000010

    #define     BA_Cec_FEPHY_STS_misc_rx_lpi_s                 0x0408
    #define     B16Cec_FEPHY_STS_misc_rx_lpi_s                 0x0408
    #define   LSb32Cec_FEPHY_STS_misc_rx_lpi_s                    5
    #define   LSb16Cec_FEPHY_STS_misc_rx_lpi_s                    5
    #define       bCec_FEPHY_STS_misc_rx_lpi_s                 1
    #define   MSK32Cec_FEPHY_STS_misc_rx_lpi_s                    0x00000020

    #define     BA_Cec_FEPHY_STS_misc_pause_s                  0x0408
    #define     B16Cec_FEPHY_STS_misc_pause_s                  0x0408
    #define   LSb32Cec_FEPHY_STS_misc_pause_s                     6
    #define   LSb16Cec_FEPHY_STS_misc_pause_s                     6
    #define       bCec_FEPHY_STS_misc_pause_s                  1
    #define   MSK32Cec_FEPHY_STS_misc_pause_s                     0x00000040

    #define     BA_Cec_FEPHY_STS_misc_lp_pause_s               0x0408
    #define     B16Cec_FEPHY_STS_misc_lp_pause_s               0x0408
    #define   LSb32Cec_FEPHY_STS_misc_lp_pause_s                  7
    #define   LSb16Cec_FEPHY_STS_misc_lp_pause_s                  7
    #define       bCec_FEPHY_STS_misc_lp_pause_s               1
    #define   MSK32Cec_FEPHY_STS_misc_lp_pause_s                  0x00000080

    #define     BA_Cec_FEPHY_STS_misc_int_s                    0x0409
    #define     B16Cec_FEPHY_STS_misc_int_s                    0x0408
    #define   LSb32Cec_FEPHY_STS_misc_int_s                       8
    #define   LSb16Cec_FEPHY_STS_misc_int_s                       8
    #define       bCec_FEPHY_STS_misc_int_s                    1
    #define   MSK32Cec_FEPHY_STS_misc_int_s                       0x00000100

    #define     BA_Cec_FEPHY_STS_misc_edet_status_s            0x0409
    #define     B16Cec_FEPHY_STS_misc_edet_status_s            0x0408
    #define   LSb32Cec_FEPHY_STS_misc_edet_status_s               9
    #define   LSb16Cec_FEPHY_STS_misc_edet_status_s               9
    #define       bCec_FEPHY_STS_misc_edet_status_s            1
    #define   MSK32Cec_FEPHY_STS_misc_edet_status_s               0x00000200

    #define     BA_Cec_FEPHY_STS_tx_latency_mark_a             0x0409
    #define     B16Cec_FEPHY_STS_tx_latency_mark_a             0x0408
    #define   LSb32Cec_FEPHY_STS_tx_latency_mark_a                10
    #define   LSb16Cec_FEPHY_STS_tx_latency_mark_a                10
    #define       bCec_FEPHY_STS_tx_latency_mark_a             1
    #define   MSK32Cec_FEPHY_STS_tx_latency_mark_a                0x00000400

    #define     BA_Cec_FEPHY_STS_misc_por_reset                0x0409
    #define     B16Cec_FEPHY_STS_misc_por_reset                0x0408
    #define   LSb32Cec_FEPHY_STS_misc_por_reset                   11
    #define   LSb16Cec_FEPHY_STS_misc_por_reset                   11
    #define       bCec_FEPHY_STS_misc_por_reset                1
    #define   MSK32Cec_FEPHY_STS_misc_por_reset                   0x00000800
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_MC_CTRL                                 0x040C

    #define     BA_Cec_MC_CTRL_RESETn                          0x040C
    #define     B16Cec_MC_CTRL_RESETn                          0x040C
    #define   LSb32Cec_MC_CTRL_RESETn                             0
    #define   LSb16Cec_MC_CTRL_RESETn                             0
    #define       bCec_MC_CTRL_RESETn                          1
    #define   MSK32Cec_MC_CTRL_RESETn                             0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_regIfCtrlEddc                           0x0410

    #define     BA_Cec_regIfCtrlEddc_mwrWidth                  0x0410
    #define     B16Cec_regIfCtrlEddc_mwrWidth                  0x0410
    #define   LSb32Cec_regIfCtrlEddc_mwrWidth                     0
    #define   LSb16Cec_regIfCtrlEddc_mwrWidth                     0
    #define       bCec_regIfCtrlEddc_mwrWidth                  8
    #define   MSK32Cec_regIfCtrlEddc_mwrWidth                     0x000000FF

    #define     BA_Cec_regIfCtrlEddc_hold                      0x0411
    #define     B16Cec_regIfCtrlEddc_hold                      0x0410
    #define   LSb32Cec_regIfCtrlEddc_hold                         8
    #define   LSb16Cec_regIfCtrlEddc_hold                         8
    #define       bCec_regIfCtrlEddc_hold                      8
    #define   MSK32Cec_regIfCtrlEddc_hold                         0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_EDID_CTRL0                              0x0414

    #define     BA_Cec_EDID_CTRL0_slv0_addr                    0x0414
    #define     B16Cec_EDID_CTRL0_slv0_addr                    0x0414
    #define   LSb32Cec_EDID_CTRL0_slv0_addr                       0
    #define   LSb16Cec_EDID_CTRL0_slv0_addr                       0
    #define       bCec_EDID_CTRL0_slv0_addr                    7
    #define   MSK32Cec_EDID_CTRL0_slv0_addr                       0x0000007F

    #define     BA_Cec_EDID_CTRL0_slv1_addr                    0x0414
    #define     B16Cec_EDID_CTRL0_slv1_addr                    0x0414
    #define   LSb32Cec_EDID_CTRL0_slv1_addr                       7
    #define   LSb16Cec_EDID_CTRL0_slv1_addr                       7
    #define       bCec_EDID_CTRL0_slv1_addr                    7
    #define   MSK32Cec_EDID_CTRL0_slv1_addr                       0x00003F80

    #define     BA_Cec_EDID_CTRL0_slv2_addr                    0x0415
    #define     B16Cec_EDID_CTRL0_slv2_addr                    0x0414
    #define   LSb32Cec_EDID_CTRL0_slv2_addr                       14
    #define   LSb16Cec_EDID_CTRL0_slv2_addr                       14
    #define       bCec_EDID_CTRL0_slv2_addr                    7
    #define   MSK32Cec_EDID_CTRL0_slv2_addr                       0x001FC000

    #define     BA_Cec_EDID_CTRL0_slv3_addr                    0x0416
    #define     B16Cec_EDID_CTRL0_slv3_addr                    0x0416
    #define   LSb32Cec_EDID_CTRL0_slv3_addr                       21
    #define   LSb16Cec_EDID_CTRL0_slv3_addr                       5
    #define       bCec_EDID_CTRL0_slv3_addr                    7
    #define   MSK32Cec_EDID_CTRL0_slv3_addr                       0x0FE00000
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_EDID_CTRL1                              0x0418

    #define     BA_Cec_EDID_CTRL1_edid_sel                     0x0418
    #define     B16Cec_EDID_CTRL1_edid_sel                     0x0418
    #define   LSb32Cec_EDID_CTRL1_edid_sel                        0
    #define   LSb16Cec_EDID_CTRL1_edid_sel                        0
    #define       bCec_EDID_CTRL1_edid_sel                     4
    #define   MSK32Cec_EDID_CTRL1_edid_sel                        0x0000000F

    #define     BA_Cec_EDID_CTRL1_cpu_wr_done                  0x0418
    #define     B16Cec_EDID_CTRL1_cpu_wr_done                  0x0418
    #define   LSb32Cec_EDID_CTRL1_cpu_wr_done                     4
    #define   LSb16Cec_EDID_CTRL1_cpu_wr_done                     4
    #define       bCec_EDID_CTRL1_cpu_wr_done                  4
    #define   MSK32Cec_EDID_CTRL1_cpu_wr_done                     0x000000F0

    #define     BA_Cec_EDID_CTRL1_cpu_wr_done_ac               0x0419
    #define     B16Cec_EDID_CTRL1_cpu_wr_done_ac               0x0418
    #define   LSb32Cec_EDID_CTRL1_cpu_wr_done_ac                  8
    #define   LSb16Cec_EDID_CTRL1_cpu_wr_done_ac                  8
    #define       bCec_EDID_CTRL1_cpu_wr_done_ac               4
    #define   MSK32Cec_EDID_CTRL1_cpu_wr_done_ac                  0x00000F00

    #define     BA_Cec_EDID_CTRL1_cpu_wr_done_toggle           0x0419
    #define     B16Cec_EDID_CTRL1_cpu_wr_done_toggle           0x0418
    #define   LSb32Cec_EDID_CTRL1_cpu_wr_done_toggle              12
    #define   LSb16Cec_EDID_CTRL1_cpu_wr_done_toggle              12
    #define       bCec_EDID_CTRL1_cpu_wr_done_toggle           4
    #define   MSK32Cec_EDID_CTRL1_cpu_wr_done_toggle              0x0000F000

    #define     BA_Cec_EDID_CTRL1_edid_i2c_en                  0x041A
    #define     B16Cec_EDID_CTRL1_edid_i2c_en                  0x041A
    #define   LSb32Cec_EDID_CTRL1_edid_i2c_en                     16
    #define   LSb16Cec_EDID_CTRL1_edid_i2c_en                     0
    #define       bCec_EDID_CTRL1_edid_i2c_en                  4
    #define   MSK32Cec_EDID_CTRL1_edid_i2c_en                     0x000F0000

    #define     BA_Cec_EDID_CTRL1_intr_clr                     0x041A
    #define     B16Cec_EDID_CTRL1_intr_clr                     0x041A
    #define   LSb32Cec_EDID_CTRL1_intr_clr                        20
    #define   LSb16Cec_EDID_CTRL1_intr_clr                        4
    #define       bCec_EDID_CTRL1_intr_clr                     4
    #define   MSK32Cec_EDID_CTRL1_intr_clr                        0x00F00000
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_EDID_STS0                               0x041C

    #define     BA_Cec_EDID_STS0_edid0_seg_ptr                 0x041C
    #define     B16Cec_EDID_STS0_edid0_seg_ptr                 0x041C
    #define   LSb32Cec_EDID_STS0_edid0_seg_ptr                    0
    #define   LSb16Cec_EDID_STS0_edid0_seg_ptr                    0
    #define       bCec_EDID_STS0_edid0_seg_ptr                 8
    #define   MSK32Cec_EDID_STS0_edid0_seg_ptr                    0x000000FF

    #define     BA_Cec_EDID_STS0_edid1_seg_ptr                 0x041D
    #define     B16Cec_EDID_STS0_edid1_seg_ptr                 0x041C
    #define   LSb32Cec_EDID_STS0_edid1_seg_ptr                    8
    #define   LSb16Cec_EDID_STS0_edid1_seg_ptr                    8
    #define       bCec_EDID_STS0_edid1_seg_ptr                 8
    #define   MSK32Cec_EDID_STS0_edid1_seg_ptr                    0x0000FF00

    #define     BA_Cec_EDID_STS0_edid2_seg_ptr                 0x041E
    #define     B16Cec_EDID_STS0_edid2_seg_ptr                 0x041E
    #define   LSb32Cec_EDID_STS0_edid2_seg_ptr                    16
    #define   LSb16Cec_EDID_STS0_edid2_seg_ptr                    0
    #define       bCec_EDID_STS0_edid2_seg_ptr                 8
    #define   MSK32Cec_EDID_STS0_edid2_seg_ptr                    0x00FF0000

    #define     BA_Cec_EDID_STS0_edid3_seg_ptr                 0x041F
    #define     B16Cec_EDID_STS0_edid3_seg_ptr                 0x041E
    #define   LSb32Cec_EDID_STS0_edid3_seg_ptr                    24
    #define   LSb16Cec_EDID_STS0_edid3_seg_ptr                    8
    #define       bCec_EDID_STS0_edid3_seg_ptr                 8
    #define   MSK32Cec_EDID_STS0_edid3_seg_ptr                    0xFF000000
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_EDID_STS1                               0x0420

    #define     BA_Cec_EDID_STS1_cpu_wr_done_sts               0x0420
    #define     B16Cec_EDID_STS1_cpu_wr_done_sts               0x0420
    #define   LSb32Cec_EDID_STS1_cpu_wr_done_sts                  0
    #define   LSb16Cec_EDID_STS1_cpu_wr_done_sts                  0
    #define       bCec_EDID_STS1_cpu_wr_done_sts               4
    #define   MSK32Cec_EDID_STS1_cpu_wr_done_sts                  0x0000000F
    ///////////////////////////////////////////////////////////
    #define     RA_Cec_eddcReg                                 0x0800
    ///////////////////////////////////////////////////////////

    typedef struct SIE_Cec {
    ///////////////////////////////////////////////////////////
              SIE_Cec_REG                                      ie_cfgReg;
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_regIfCtrl_mwrWidth(r32)                 _BFGET_(r32, 7, 0)
    #define   SET32Cec_regIfCtrl_mwrWidth(r32,v)               _BFSET_(r32, 7, 0,v)
    #define   GET16Cec_regIfCtrl_mwrWidth(r16)                 _BFGET_(r16, 7, 0)
    #define   SET16Cec_regIfCtrl_mwrWidth(r16,v)               _BFSET_(r16, 7, 0,v)

    #define   GET32Cec_regIfCtrl_hold(r32)                     _BFGET_(r32,15, 8)
    #define   SET32Cec_regIfCtrl_hold(r32,v)                   _BFSET_(r32,15, 8,v)
    #define   GET16Cec_regIfCtrl_hold(r16)                     _BFGET_(r16,15, 8)
    #define   SET16Cec_regIfCtrl_hold(r16,v)                   _BFSET_(r16,15, 8,v)

    #define     w32Cec_regIfCtrl                               {\
            UNSG32 uregIfCtrl_mwrWidth                         :  8;\
            UNSG32 uregIfCtrl_hold                             :  8;\
            UNSG32 RSVDx400_b16                                : 16;\
          }
    union { UNSG32 u32Cec_regIfCtrl;
            struct w32Cec_regIfCtrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_FEPHY_CTRL_ext_pwrdn_a(r32)             _BFGET_(r32, 4, 0)
    #define   SET32Cec_FEPHY_CTRL_ext_pwrdn_a(r32,v)           _BFSET_(r32, 4, 0,v)
    #define   GET16Cec_FEPHY_CTRL_ext_pwrdn_a(r16)             _BFGET_(r16, 4, 0)
    #define   SET16Cec_FEPHY_CTRL_ext_pwrdn_a(r16,v)           _BFSET_(r16, 4, 0,v)

    #define   GET32Cec_FEPHY_CTRL_pd_aneg_mode_a(r32)          _BFGET_(r32, 7, 5)
    #define   SET32Cec_FEPHY_CTRL_pd_aneg_mode_a(r32,v)        _BFSET_(r32, 7, 5,v)
    #define   GET16Cec_FEPHY_CTRL_pd_aneg_mode_a(r16)          _BFGET_(r16, 7, 5)
    #define   SET16Cec_FEPHY_CTRL_pd_aneg_mode_a(r16,v)        _BFSET_(r16, 7, 5,v)

    #define   GET32Cec_FEPHY_CTRL_pd_phyadr_a(r32)             _BFGET_(r32,12, 8)
    #define   SET32Cec_FEPHY_CTRL_pd_phyadr_a(r32,v)           _BFSET_(r32,12, 8,v)
    #define   GET16Cec_FEPHY_CTRL_pd_phyadr_a(r16)             _BFGET_(r16,12, 8)
    #define   SET16Cec_FEPHY_CTRL_pd_phyadr_a(r16,v)           _BFSET_(r16,12, 8,v)

    #define   GET32Cec_FEPHY_CTRL_pd_led_config_a(r32)         _BFGET_(r32,15,13)
    #define   SET32Cec_FEPHY_CTRL_pd_led_config_a(r32,v)       _BFSET_(r32,15,13,v)
    #define   GET16Cec_FEPHY_CTRL_pd_led_config_a(r16)         _BFGET_(r16,15,13)
    #define   SET16Cec_FEPHY_CTRL_pd_led_config_a(r16,v)       _BFSET_(r16,15,13,v)

    #define   GET32Cec_FEPHY_CTRL_yy_pecl_sdet_a(r32)          _BFGET_(r32,20,16)
    #define   SET32Cec_FEPHY_CTRL_yy_pecl_sdet_a(r32,v)        _BFSET_(r32,20,16,v)
    #define   GET16Cec_FEPHY_CTRL_yy_pecl_sdet_a(r16)          _BFGET_(r16, 4, 0)
    #define   SET16Cec_FEPHY_CTRL_yy_pecl_sdet_a(r16,v)        _BFSET_(r16, 4, 0,v)

    #define   GET32Cec_FEPHY_CTRL_ps_en_eee10t_s(r32)          _BFGET_(r32,21,21)
    #define   SET32Cec_FEPHY_CTRL_ps_en_eee10t_s(r32,v)        _BFSET_(r32,21,21,v)
    #define   GET16Cec_FEPHY_CTRL_ps_en_eee10t_s(r16)          _BFGET_(r16, 5, 5)
    #define   SET16Cec_FEPHY_CTRL_ps_en_eee10t_s(r16,v)        _BFSET_(r16, 5, 5,v)

    #define   GET32Cec_FEPHY_CTRL_ps_en_eee100t_s(r32)         _BFGET_(r32,22,22)
    #define   SET32Cec_FEPHY_CTRL_ps_en_eee100t_s(r32,v)       _BFSET_(r32,22,22,v)
    #define   GET16Cec_FEPHY_CTRL_ps_en_eee100t_s(r16)         _BFGET_(r16, 6, 6)
    #define   SET16Cec_FEPHY_CTRL_ps_en_eee100t_s(r16,v)       _BFSET_(r16, 6, 6,v)

    #define   GET32Cec_FEPHY_CTRL_pd_burnin_a(r32)             _BFGET_(r32,23,23)
    #define   SET32Cec_FEPHY_CTRL_pd_burnin_a(r32,v)           _BFSET_(r32,23,23,v)
    #define   GET16Cec_FEPHY_CTRL_pd_burnin_a(r16)             _BFGET_(r16, 7, 7)
    #define   SET16Cec_FEPHY_CTRL_pd_burnin_a(r16,v)           _BFSET_(r16, 7, 7,v)

    #define   GET32Cec_FEPHY_CTRL_pd_ena_edet_a(r32)           _BFGET_(r32,24,24)
    #define   SET32Cec_FEPHY_CTRL_pd_ena_edet_a(r32,v)         _BFSET_(r32,24,24,v)
    #define   GET16Cec_FEPHY_CTRL_pd_ena_edet_a(r16)           _BFGET_(r16, 8, 8)
    #define   SET16Cec_FEPHY_CTRL_pd_ena_edet_a(r16,v)         _BFSET_(r16, 8, 8,v)

    #define   GET32Cec_FEPHY_CTRL_pd_ena_xc_a(r32)             _BFGET_(r32,25,25)
    #define   SET32Cec_FEPHY_CTRL_pd_ena_xc_a(r32,v)           _BFSET_(r32,25,25,v)
    #define   GET16Cec_FEPHY_CTRL_pd_ena_xc_a(r16)             _BFGET_(r16, 9, 9)
    #define   SET16Cec_FEPHY_CTRL_pd_ena_xc_a(r16,v)           _BFSET_(r16, 9, 9,v)

    #define   GET32Cec_FEPHY_CTRL_ext_coma_a(r32)              _BFGET_(r32,26,26)
    #define   SET32Cec_FEPHY_CTRL_ext_coma_a(r32,v)            _BFSET_(r32,26,26,v)
    #define   GET16Cec_FEPHY_CTRL_ext_coma_a(r16)              _BFGET_(r16,10,10)
    #define   SET16Cec_FEPHY_CTRL_ext_coma_a(r16,v)            _BFSET_(r16,10,10,v)

    #define     w32Cec_FEPHY_CTRL                              {\
            UNSG32 uFEPHY_CTRL_ext_pwrdn_a                     :  5;\
            UNSG32 uFEPHY_CTRL_pd_aneg_mode_a                  :  3;\
            UNSG32 uFEPHY_CTRL_pd_phyadr_a                     :  5;\
            UNSG32 uFEPHY_CTRL_pd_led_config_a                 :  3;\
            UNSG32 uFEPHY_CTRL_yy_pecl_sdet_a                  :  5;\
            UNSG32 uFEPHY_CTRL_ps_en_eee10t_s                  :  1;\
            UNSG32 uFEPHY_CTRL_ps_en_eee100t_s                 :  1;\
            UNSG32 uFEPHY_CTRL_pd_burnin_a                     :  1;\
            UNSG32 uFEPHY_CTRL_pd_ena_edet_a                   :  1;\
            UNSG32 uFEPHY_CTRL_pd_ena_xc_a                     :  1;\
            UNSG32 uFEPHY_CTRL_ext_coma_a                      :  1;\
            UNSG32 RSVDx404_b27                                :  5;\
          }
    union { UNSG32 u32Cec_FEPHY_CTRL;
            struct w32Cec_FEPHY_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_FEPHY_STS_misc_speed_s(r32)             _BFGET_(r32, 0, 0)
    #define   SET32Cec_FEPHY_STS_misc_speed_s(r32,v)           _BFSET_(r32, 0, 0,v)
    #define   GET16Cec_FEPHY_STS_misc_speed_s(r16)             _BFGET_(r16, 0, 0)
    #define   SET16Cec_FEPHY_STS_misc_speed_s(r16,v)           _BFSET_(r16, 0, 0,v)

    #define   GET32Cec_FEPHY_STS_misc_duplex_s(r32)            _BFGET_(r32, 1, 1)
    #define   SET32Cec_FEPHY_STS_misc_duplex_s(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16Cec_FEPHY_STS_misc_duplex_s(r16)            _BFGET_(r16, 1, 1)
    #define   SET16Cec_FEPHY_STS_misc_duplex_s(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32Cec_FEPHY_STS_misc_hcd_resolved_s(r32)      _BFGET_(r32, 2, 2)
    #define   SET32Cec_FEPHY_STS_misc_hcd_resolved_s(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16Cec_FEPHY_STS_misc_hcd_resolved_s(r16)      _BFGET_(r16, 2, 2)
    #define   SET16Cec_FEPHY_STS_misc_hcd_resolved_s(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32Cec_FEPHY_STS_misc_link_s(r32)              _BFGET_(r32, 3, 3)
    #define   SET32Cec_FEPHY_STS_misc_link_s(r32,v)            _BFSET_(r32, 3, 3,v)
    #define   GET16Cec_FEPHY_STS_misc_link_s(r16)              _BFGET_(r16, 3, 3)
    #define   SET16Cec_FEPHY_STS_misc_link_s(r16,v)            _BFSET_(r16, 3, 3,v)

    #define   GET32Cec_FEPHY_STS_misc_lpi_s(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Cec_FEPHY_STS_misc_lpi_s(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Cec_FEPHY_STS_misc_lpi_s(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Cec_FEPHY_STS_misc_lpi_s(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Cec_FEPHY_STS_misc_rx_lpi_s(r32)            _BFGET_(r32, 5, 5)
    #define   SET32Cec_FEPHY_STS_misc_rx_lpi_s(r32,v)          _BFSET_(r32, 5, 5,v)
    #define   GET16Cec_FEPHY_STS_misc_rx_lpi_s(r16)            _BFGET_(r16, 5, 5)
    #define   SET16Cec_FEPHY_STS_misc_rx_lpi_s(r16,v)          _BFSET_(r16, 5, 5,v)

    #define   GET32Cec_FEPHY_STS_misc_pause_s(r32)             _BFGET_(r32, 6, 6)
    #define   SET32Cec_FEPHY_STS_misc_pause_s(r32,v)           _BFSET_(r32, 6, 6,v)
    #define   GET16Cec_FEPHY_STS_misc_pause_s(r16)             _BFGET_(r16, 6, 6)
    #define   SET16Cec_FEPHY_STS_misc_pause_s(r16,v)           _BFSET_(r16, 6, 6,v)

    #define   GET32Cec_FEPHY_STS_misc_lp_pause_s(r32)          _BFGET_(r32, 7, 7)
    #define   SET32Cec_FEPHY_STS_misc_lp_pause_s(r32,v)        _BFSET_(r32, 7, 7,v)
    #define   GET16Cec_FEPHY_STS_misc_lp_pause_s(r16)          _BFGET_(r16, 7, 7)
    #define   SET16Cec_FEPHY_STS_misc_lp_pause_s(r16,v)        _BFSET_(r16, 7, 7,v)

    #define   GET32Cec_FEPHY_STS_misc_int_s(r32)               _BFGET_(r32, 8, 8)
    #define   SET32Cec_FEPHY_STS_misc_int_s(r32,v)             _BFSET_(r32, 8, 8,v)
    #define   GET16Cec_FEPHY_STS_misc_int_s(r16)               _BFGET_(r16, 8, 8)
    #define   SET16Cec_FEPHY_STS_misc_int_s(r16,v)             _BFSET_(r16, 8, 8,v)

    #define   GET32Cec_FEPHY_STS_misc_edet_status_s(r32)       _BFGET_(r32, 9, 9)
    #define   SET32Cec_FEPHY_STS_misc_edet_status_s(r32,v)     _BFSET_(r32, 9, 9,v)
    #define   GET16Cec_FEPHY_STS_misc_edet_status_s(r16)       _BFGET_(r16, 9, 9)
    #define   SET16Cec_FEPHY_STS_misc_edet_status_s(r16,v)     _BFSET_(r16, 9, 9,v)

    #define   GET32Cec_FEPHY_STS_tx_latency_mark_a(r32)        _BFGET_(r32,10,10)
    #define   SET32Cec_FEPHY_STS_tx_latency_mark_a(r32,v)      _BFSET_(r32,10,10,v)
    #define   GET16Cec_FEPHY_STS_tx_latency_mark_a(r16)        _BFGET_(r16,10,10)
    #define   SET16Cec_FEPHY_STS_tx_latency_mark_a(r16,v)      _BFSET_(r16,10,10,v)

    #define   GET32Cec_FEPHY_STS_misc_por_reset(r32)           _BFGET_(r32,11,11)
    #define   SET32Cec_FEPHY_STS_misc_por_reset(r32,v)         _BFSET_(r32,11,11,v)
    #define   GET16Cec_FEPHY_STS_misc_por_reset(r16)           _BFGET_(r16,11,11)
    #define   SET16Cec_FEPHY_STS_misc_por_reset(r16,v)         _BFSET_(r16,11,11,v)

    #define     w32Cec_FEPHY_STS                               {\
            UNSG32 uFEPHY_STS_misc_speed_s                     :  1;\
            UNSG32 uFEPHY_STS_misc_duplex_s                    :  1;\
            UNSG32 uFEPHY_STS_misc_hcd_resolved_s              :  1;\
            UNSG32 uFEPHY_STS_misc_link_s                      :  1;\
            UNSG32 uFEPHY_STS_misc_lpi_s                       :  1;\
            UNSG32 uFEPHY_STS_misc_rx_lpi_s                    :  1;\
            UNSG32 uFEPHY_STS_misc_pause_s                     :  1;\
            UNSG32 uFEPHY_STS_misc_lp_pause_s                  :  1;\
            UNSG32 uFEPHY_STS_misc_int_s                       :  1;\
            UNSG32 uFEPHY_STS_misc_edet_status_s               :  1;\
            UNSG32 uFEPHY_STS_tx_latency_mark_a                :  1;\
            UNSG32 uFEPHY_STS_misc_por_reset                   :  1;\
            UNSG32 RSVDx408_b12                                : 20;\
          }
    union { UNSG32 u32Cec_FEPHY_STS;
            struct w32Cec_FEPHY_STS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_MC_CTRL_RESETn(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32Cec_MC_CTRL_RESETn(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16Cec_MC_CTRL_RESETn(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16Cec_MC_CTRL_RESETn(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32Cec_MC_CTRL                                 {\
            UNSG32 uMC_CTRL_RESETn                             :  1;\
            UNSG32 RSVDx40C_b1                                 : 31;\
          }
    union { UNSG32 u32Cec_MC_CTRL;
            struct w32Cec_MC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_regIfCtrlEddc_mwrWidth(r32)             _BFGET_(r32, 7, 0)
    #define   SET32Cec_regIfCtrlEddc_mwrWidth(r32,v)           _BFSET_(r32, 7, 0,v)
    #define   GET16Cec_regIfCtrlEddc_mwrWidth(r16)             _BFGET_(r16, 7, 0)
    #define   SET16Cec_regIfCtrlEddc_mwrWidth(r16,v)           _BFSET_(r16, 7, 0,v)

    #define   GET32Cec_regIfCtrlEddc_hold(r32)                 _BFGET_(r32,15, 8)
    #define   SET32Cec_regIfCtrlEddc_hold(r32,v)               _BFSET_(r32,15, 8,v)
    #define   GET16Cec_regIfCtrlEddc_hold(r16)                 _BFGET_(r16,15, 8)
    #define   SET16Cec_regIfCtrlEddc_hold(r16,v)               _BFSET_(r16,15, 8,v)

    #define     w32Cec_regIfCtrlEddc                           {\
            UNSG32 uregIfCtrlEddc_mwrWidth                     :  8;\
            UNSG32 uregIfCtrlEddc_hold                         :  8;\
            UNSG32 RSVDx410_b16                                : 16;\
          }
    union { UNSG32 u32Cec_regIfCtrlEddc;
            struct w32Cec_regIfCtrlEddc;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_EDID_CTRL0_slv0_addr(r32)               _BFGET_(r32, 6, 0)
    #define   SET32Cec_EDID_CTRL0_slv0_addr(r32,v)             _BFSET_(r32, 6, 0,v)
    #define   GET16Cec_EDID_CTRL0_slv0_addr(r16)               _BFGET_(r16, 6, 0)
    #define   SET16Cec_EDID_CTRL0_slv0_addr(r16,v)             _BFSET_(r16, 6, 0,v)

    #define   GET32Cec_EDID_CTRL0_slv1_addr(r32)               _BFGET_(r32,13, 7)
    #define   SET32Cec_EDID_CTRL0_slv1_addr(r32,v)             _BFSET_(r32,13, 7,v)
    #define   GET16Cec_EDID_CTRL0_slv1_addr(r16)               _BFGET_(r16,13, 7)
    #define   SET16Cec_EDID_CTRL0_slv1_addr(r16,v)             _BFSET_(r16,13, 7,v)

    #define   GET32Cec_EDID_CTRL0_slv2_addr(r32)               _BFGET_(r32,20,14)
    #define   SET32Cec_EDID_CTRL0_slv2_addr(r32,v)             _BFSET_(r32,20,14,v)

    #define   GET32Cec_EDID_CTRL0_slv3_addr(r32)               _BFGET_(r32,27,21)
    #define   SET32Cec_EDID_CTRL0_slv3_addr(r32,v)             _BFSET_(r32,27,21,v)
    #define   GET16Cec_EDID_CTRL0_slv3_addr(r16)               _BFGET_(r16,11, 5)
    #define   SET16Cec_EDID_CTRL0_slv3_addr(r16,v)             _BFSET_(r16,11, 5,v)

    #define     w32Cec_EDID_CTRL0                              {\
            UNSG32 uEDID_CTRL0_slv0_addr                       :  7;\
            UNSG32 uEDID_CTRL0_slv1_addr                       :  7;\
            UNSG32 uEDID_CTRL0_slv2_addr                       :  7;\
            UNSG32 uEDID_CTRL0_slv3_addr                       :  7;\
            UNSG32 RSVDx414_b28                                :  4;\
          }
    union { UNSG32 u32Cec_EDID_CTRL0;
            struct w32Cec_EDID_CTRL0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_EDID_CTRL1_edid_sel(r32)                _BFGET_(r32, 3, 0)
    #define   SET32Cec_EDID_CTRL1_edid_sel(r32,v)              _BFSET_(r32, 3, 0,v)
    #define   GET16Cec_EDID_CTRL1_edid_sel(r16)                _BFGET_(r16, 3, 0)
    #define   SET16Cec_EDID_CTRL1_edid_sel(r16,v)              _BFSET_(r16, 3, 0,v)

    #define   GET32Cec_EDID_CTRL1_cpu_wr_done(r32)             _BFGET_(r32, 7, 4)
    #define   SET32Cec_EDID_CTRL1_cpu_wr_done(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16Cec_EDID_CTRL1_cpu_wr_done(r16)             _BFGET_(r16, 7, 4)
    #define   SET16Cec_EDID_CTRL1_cpu_wr_done(r16,v)           _BFSET_(r16, 7, 4,v)

    #define   GET32Cec_EDID_CTRL1_cpu_wr_done_ac(r32)          _BFGET_(r32,11, 8)
    #define   SET32Cec_EDID_CTRL1_cpu_wr_done_ac(r32,v)        _BFSET_(r32,11, 8,v)
    #define   GET16Cec_EDID_CTRL1_cpu_wr_done_ac(r16)          _BFGET_(r16,11, 8)
    #define   SET16Cec_EDID_CTRL1_cpu_wr_done_ac(r16,v)        _BFSET_(r16,11, 8,v)

    #define   GET32Cec_EDID_CTRL1_cpu_wr_done_toggle(r32)      _BFGET_(r32,15,12)
    #define   SET32Cec_EDID_CTRL1_cpu_wr_done_toggle(r32,v)    _BFSET_(r32,15,12,v)
    #define   GET16Cec_EDID_CTRL1_cpu_wr_done_toggle(r16)      _BFGET_(r16,15,12)
    #define   SET16Cec_EDID_CTRL1_cpu_wr_done_toggle(r16,v)    _BFSET_(r16,15,12,v)

    #define   GET32Cec_EDID_CTRL1_edid_i2c_en(r32)             _BFGET_(r32,19,16)
    #define   SET32Cec_EDID_CTRL1_edid_i2c_en(r32,v)           _BFSET_(r32,19,16,v)
    #define   GET16Cec_EDID_CTRL1_edid_i2c_en(r16)             _BFGET_(r16, 3, 0)
    #define   SET16Cec_EDID_CTRL1_edid_i2c_en(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32Cec_EDID_CTRL1_intr_clr(r32)                _BFGET_(r32,23,20)
    #define   SET32Cec_EDID_CTRL1_intr_clr(r32,v)              _BFSET_(r32,23,20,v)
    #define   GET16Cec_EDID_CTRL1_intr_clr(r16)                _BFGET_(r16, 7, 4)
    #define   SET16Cec_EDID_CTRL1_intr_clr(r16,v)              _BFSET_(r16, 7, 4,v)

    #define     w32Cec_EDID_CTRL1                              {\
            UNSG32 uEDID_CTRL1_edid_sel                        :  4;\
            UNSG32 uEDID_CTRL1_cpu_wr_done                     :  4;\
            UNSG32 uEDID_CTRL1_cpu_wr_done_ac                  :  4;\
            UNSG32 uEDID_CTRL1_cpu_wr_done_toggle              :  4;\
            UNSG32 uEDID_CTRL1_edid_i2c_en                     :  4;\
            UNSG32 uEDID_CTRL1_intr_clr                        :  4;\
            UNSG32 RSVDx418_b24                                :  8;\
          }
    union { UNSG32 u32Cec_EDID_CTRL1;
            struct w32Cec_EDID_CTRL1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_EDID_STS0_edid0_seg_ptr(r32)            _BFGET_(r32, 7, 0)
    #define   SET32Cec_EDID_STS0_edid0_seg_ptr(r32,v)          _BFSET_(r32, 7, 0,v)
    #define   GET16Cec_EDID_STS0_edid0_seg_ptr(r16)            _BFGET_(r16, 7, 0)
    #define   SET16Cec_EDID_STS0_edid0_seg_ptr(r16,v)          _BFSET_(r16, 7, 0,v)

    #define   GET32Cec_EDID_STS0_edid1_seg_ptr(r32)            _BFGET_(r32,15, 8)
    #define   SET32Cec_EDID_STS0_edid1_seg_ptr(r32,v)          _BFSET_(r32,15, 8,v)
    #define   GET16Cec_EDID_STS0_edid1_seg_ptr(r16)            _BFGET_(r16,15, 8)
    #define   SET16Cec_EDID_STS0_edid1_seg_ptr(r16,v)          _BFSET_(r16,15, 8,v)

    #define   GET32Cec_EDID_STS0_edid2_seg_ptr(r32)            _BFGET_(r32,23,16)
    #define   SET32Cec_EDID_STS0_edid2_seg_ptr(r32,v)          _BFSET_(r32,23,16,v)
    #define   GET16Cec_EDID_STS0_edid2_seg_ptr(r16)            _BFGET_(r16, 7, 0)
    #define   SET16Cec_EDID_STS0_edid2_seg_ptr(r16,v)          _BFSET_(r16, 7, 0,v)

    #define   GET32Cec_EDID_STS0_edid3_seg_ptr(r32)            _BFGET_(r32,31,24)
    #define   SET32Cec_EDID_STS0_edid3_seg_ptr(r32,v)          _BFSET_(r32,31,24,v)
    #define   GET16Cec_EDID_STS0_edid3_seg_ptr(r16)            _BFGET_(r16,15, 8)
    #define   SET16Cec_EDID_STS0_edid3_seg_ptr(r16,v)          _BFSET_(r16,15, 8,v)

    #define     w32Cec_EDID_STS0                               {\
            UNSG32 uEDID_STS0_edid0_seg_ptr                    :  8;\
            UNSG32 uEDID_STS0_edid1_seg_ptr                    :  8;\
            UNSG32 uEDID_STS0_edid2_seg_ptr                    :  8;\
            UNSG32 uEDID_STS0_edid3_seg_ptr                    :  8;\
          }
    union { UNSG32 u32Cec_EDID_STS0;
            struct w32Cec_EDID_STS0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Cec_EDID_STS1_cpu_wr_done_sts(r32)          _BFGET_(r32, 3, 0)
    #define   SET32Cec_EDID_STS1_cpu_wr_done_sts(r32,v)        _BFSET_(r32, 3, 0,v)
    #define   GET16Cec_EDID_STS1_cpu_wr_done_sts(r16)          _BFGET_(r16, 3, 0)
    #define   SET16Cec_EDID_STS1_cpu_wr_done_sts(r16,v)        _BFSET_(r16, 3, 0,v)

    #define     w32Cec_EDID_STS1                               {\
            UNSG32 uEDID_STS1_cpu_wr_done_sts                  :  4;\
            UNSG32 RSVDx420_b4                                 : 28;\
          }
    union { UNSG32 u32Cec_EDID_STS1;
            struct w32Cec_EDID_STS1;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx424                                    [988];
    ///////////////////////////////////////////////////////////
              SIE_Eddc_REG                                     ie_eddcReg;
    ///////////////////////////////////////////////////////////
    } SIE_Cec;

    typedef union  T32Cec_regIfCtrl
          { UNSG32 u32;
            struct w32Cec_regIfCtrl;
                 } T32Cec_regIfCtrl;
    typedef union  T32Cec_FEPHY_CTRL
          { UNSG32 u32;
            struct w32Cec_FEPHY_CTRL;
                 } T32Cec_FEPHY_CTRL;
    typedef union  T32Cec_FEPHY_STS
          { UNSG32 u32;
            struct w32Cec_FEPHY_STS;
                 } T32Cec_FEPHY_STS;
    typedef union  T32Cec_MC_CTRL
          { UNSG32 u32;
            struct w32Cec_MC_CTRL;
                 } T32Cec_MC_CTRL;
    typedef union  T32Cec_regIfCtrlEddc
          { UNSG32 u32;
            struct w32Cec_regIfCtrlEddc;
                 } T32Cec_regIfCtrlEddc;
    typedef union  T32Cec_EDID_CTRL0
          { UNSG32 u32;
            struct w32Cec_EDID_CTRL0;
                 } T32Cec_EDID_CTRL0;
    typedef union  T32Cec_EDID_CTRL1
          { UNSG32 u32;
            struct w32Cec_EDID_CTRL1;
                 } T32Cec_EDID_CTRL1;
    typedef union  T32Cec_EDID_STS0
          { UNSG32 u32;
            struct w32Cec_EDID_STS0;
                 } T32Cec_EDID_STS0;
    typedef union  T32Cec_EDID_STS1
          { UNSG32 u32;
            struct w32Cec_EDID_STS1;
                 } T32Cec_EDID_STS1;
    ///////////////////////////////////////////////////////////

    typedef union  TCec_regIfCtrl
          { UNSG32 u32[1];
            struct {
            struct w32Cec_regIfCtrl;
                   };
                 } TCec_regIfCtrl;
    typedef union  TCec_FEPHY_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32Cec_FEPHY_CTRL;
                   };
                 } TCec_FEPHY_CTRL;
    typedef union  TCec_FEPHY_STS
          { UNSG32 u32[1];
            struct {
            struct w32Cec_FEPHY_STS;
                   };
                 } TCec_FEPHY_STS;
    typedef union  TCec_MC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32Cec_MC_CTRL;
                   };
                 } TCec_MC_CTRL;
    typedef union  TCec_regIfCtrlEddc
          { UNSG32 u32[1];
            struct {
            struct w32Cec_regIfCtrlEddc;
                   };
                 } TCec_regIfCtrlEddc;
    typedef union  TCec_EDID_CTRL0
          { UNSG32 u32[1];
            struct {
            struct w32Cec_EDID_CTRL0;
                   };
                 } TCec_EDID_CTRL0;
    typedef union  TCec_EDID_CTRL1
          { UNSG32 u32[1];
            struct {
            struct w32Cec_EDID_CTRL1;
                   };
                 } TCec_EDID_CTRL1;
    typedef union  TCec_EDID_STS0
          { UNSG32 u32[1];
            struct {
            struct w32Cec_EDID_STS0;
                   };
                 } TCec_EDID_STS0;
    typedef union  TCec_EDID_STS1
          { UNSG32 u32[1];
            struct {
            struct w32Cec_EDID_STS1;
                   };
                 } TCec_EDID_STS1;

    ///////////////////////////////////////////////////////////
     SIGN32 Cec_drvrd(SIE_Cec *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 Cec_drvwr(SIE_Cec *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void Cec_reset(SIE_Cec *p);
     SIGN32 Cec_cmp  (SIE_Cec *p, SIE_Cec *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define Cec_check(p,pie,pfx,hLOG) Cec_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define Cec_print(p,    pfx,hLOG) Cec_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: Cec
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: cec.h
////////////////////////////////////////////////////////////