/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

#ifndef performance_counter_h
#define performance_counter_h

	#define		w32Perc_Config0	 	{									\
			UNSG32				uConfig_pc_event_sel0		:  6;		\
			UNSG32				rsvd0						:  1;		\
			UNSG32				uConfig_pc_reg_en0		 	:  1;		\
			UNSG32				uConfig_pc_event_sel1		:  6;		\
			UNSG32				rsvd1						:  1;		\
			UNSG32				uConfig_pc_reg_en1		 	:  1;		\
			UNSG32				uConfig_pc_event_sel2		:  6;		\
			UNSG32				rsvd2						:  1;		\
			UNSG32				uConfig_pc_reg_en2		 	:  1;		\
			UNSG32				uConfig_pc_event_sel3		:  6;		\
			UNSG32				rsvd3						:  1;		\
			UNSG32				uConfig_pc_reg_en3		 	:  1;		\
		}

	#define		w32Perc_Config1	 	{									\
			UNSG32				uConfig_pc_event_sel4		:  6;		\
			UNSG32				rsvd0						:  1;		\
			UNSG32				uConfig_pc_reg_en4		 	:  1;		\
			UNSG32				uConfig_pc_event_sel5		:  6;		\
			UNSG32				rsvd1						:  1;		\
			UNSG32				uConfig_pc_reg_en5		 	:  1;		\
			UNSG32				uConfig_pc_event_sel6		:  6;		\
			UNSG32				rsvd2						:  1;		\
			UNSG32				uConfig_pc_reg_en6		 	:  1;		\
			UNSG32				uConfig_pc_event_sel7		:  6;		\
			UNSG32				rsvd3						:  1;		\
			UNSG32				uConfig_pc_reg_en7		 	:  1;		\
		}

	#define		w32Perc_Status	 	{									\
			UNSG32				uStatus_pc_overflow0		:  1;		\
			UNSG32				uStatus_pc_overflow1		:  1;		\
			UNSG32				uStatus_pc_overflow2		:  1;		\
			UNSG32				uStatus_pc_overflow3		:  1;		\
			UNSG32				uStatus_pc_overflow4		:  1;		\
			UNSG32				uStatus_pc_overflow5		:  1;		\
			UNSG32				uStatus_pc_overflow6		:  1;		\
			UNSG32				uStatus_pc_overflow7		:  1;		\
			UNSG32				rsvd0						:  24;		\
		}

	#define		w32Perc_Control	 	{									\
			UNSG32				uControl_pc_start_cond		:  1;		\
			UNSG32				rsvd0						:  3;		\
			UNSG32				uControl_pc_stop_cond		:  1;		\
			UNSG32				rsvd1						:  11;		\
			UNSG32				uControl_pc_clk_div			:  3;		\
			UNSG32				rsvd2						:  13;		\
		}

    typedef union  T32Perc_Config
          { UNSG32 u32[2];
            struct {
            struct w32Perc_Config0;
            struct w32Perc_Config1;
                   };
                 } T32Perc_Config;
                 
    typedef union  
          { UNSG32 u32;
            struct w32Perc_Config;
                 } ;

    typedef union  T32Perc_Status
          { UNSG32 u32;
            struct w32Perc_Status;
                 } T32Perc_Status;

    typedef union  T32Perc_Control
          { UNSG32 u32;
            struct w32Perc_Control;
                 } T32Perc_Control;

	/*
		Port0:	CPU
		Port1:	vppDhub
		Port2:	agDhub + vipDhub | AVIF
		Port3:	GC4K[gfx3dM0]
		Port4:	PxBar
				##Ethernet1
				##gmac
				##USB3 && USB2
				##ZSP
				##SDIO0, SDIO1, SDIO2
				##pBridge(NAND Flash)
				##USB0, ##USB1
				## TSP
				##drmDmx
				##Smart Card
				## CI
				## PCIE
				## Sata
		Port5:	GC420 [gfx2D]
		Port6:	VMeta
		Port7:	GC4K[gfx3D] M1
	*/
	#define		w32port_Priority_Control	 	{						\
			UNSG32				priority_p0					:  2;		\
			UNSG32				priority_p1					:  2;		\
			UNSG32				priority_p2					:  2;		\
			UNSG32				priority_p3					:  2;		\
			UNSG32				priority_p4					:  2;		\
			UNSG32				priority_p5					:  2;		\
			UNSG32				priority_p6					:  2;		\
			UNSG32				priority_p7					:  2;		\
			UNSG32				rsvd1						:  8;		\
			UNSG32				port_priority_en	 		:  8;		\
		}

    typedef union  T32port_Priority_Control
          { UNSG32 u32;
            struct w32port_Priority_Control;
                 } T32port_Priority_Control;
                 
#endif

#ifndef TRUST_ZONE
#define TRUST_ZONE

 #define w32mc_control_0 { \
			UNSG32				dfc_mode					:  1;		\
			UNSG32				halt_scdlr					:  1;		\
			UNSG32				reserved0					:  2;		\
			UNSG32				write_level_mode			:  1;		\
			UNSG32				test_mode					:  1;		\
			UNSG32				reserved1					:  2;		\
			UNSG32				block_mstr_data_req			:  8;		\
			UNSG32				block_all_data_req			:  1;		\
			UNSG32				reserved2					:  7;		\
			UNSG32				axi_chop					:  3;		\
			UNSG32				axi_chop_change	 			:  1;		\
			UNSG32				reserved3	 				:  3;		\
			UNSG32				trustzone_lock	 			:  1;		\
			}

    typedef union  T32mc_control_0
          { UNSG32 u32;
            struct w32mc_control_0;
          		 } T32mc_control_0;
          		 
  #define w32trustzone_range_0 { \
			UNSG32				TZACT_R0 					:  3;		\
			UNSG32				reserved0					:  1;		\
			UNSG32				TZACT_RU 					:  3;		\
			UNSG32				reserved1					:  1;		\
			UNSG32				TZ_enable 					:  1;		\
			UNSG32				reserved2					:  3;		\
			UNSG32				TZ_RANGE0 					:  20;		\
			}

    typedef union  T32trustzone_range_0
          { UNSG32 u32;
            struct w32trustzone_range_0;
          		 } T32trustzone_range_0;
          		 
  #define w32trustzone_range_1 { \
			UNSG32				TZACT_R1 					:  3;		\
			UNSG32				reserved0					:  9;		\
			UNSG32				TZ_RANGE1 					:  20;		\
			}

    typedef union  T32trustzone_range_1
          { UNSG32 u32;
            struct w32trustzone_range_1;
          		 } T32trustzone_range_1;
          		 
       #define w32trustzone_range_2 { \
			UNSG32				TZACT_R2 					:  3;		\
			UNSG32				reserved0					:  9;		\
			UNSG32				TZ_RANGE2 					:  20;		\
			}

    typedef union  T32trustzone_range_2
          { UNSG32 u32;
            struct w32trustzone_range_2;
          		 } T32trustzone_range_2;
          		 
  #define w32trustzone_range_3 { \
			UNSG32				TZACT_R3 					:  3;		\
			UNSG32				reserved0					:  9;		\
			UNSG32				TZ_RANGE3 					:  20;		\
			}

    typedef union  T32trustzone_range_3
          { UNSG32 u32;
            struct w32trustzone_range_3;
          		 } T32trustzone_range_3;

  enum 
  {
  	TZ_R0=0,
  	TZ_R1,
  	TZ_R2,
  	TZ_R3,
  	TZ_RU //RU is the undefined zone, whatever left after R3
  };
  
  enum
  {
  	TZ_RW=0,
  	TZ_RO,
  	TZ_WO,
  	TZ_ABT
  };
#endif