/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//////
/// don't edit! auto-generated by docc: pcie.h
////////////////////////////////////////////////////////////
#ifndef pcie_h
#define pcie_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE oneReg                                   (4,4)
///     ###
///     * To create SRAM-like interface creating one 32-bit register (Hier:1)
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (R-)
///               %unsigned 32 0x00000000                
///                                    ###
///                                    * One Register in an external IP block (i.e., PEX)
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_oneReg
#define h_oneReg (){}

    #define     BA_oneReg_0x00000000                           0x0000
    #define     B16oneReg_0x00000000                           0x0000
    #define   LSb32oneReg_0x00000000                              0
    #define   LSb16oneReg_0x00000000                              0
    #define       boneReg_0x00000000                           32
    #define   MSK32oneReg_0x00000000                              0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_oneReg {
    ///////////////////////////////////////////////////////////
    #define   GET32oneReg_0x00000000(r32)                      _BFGET_(r32,31, 0)
    #define   SET32oneReg_0x00000000(r32,v)                    _BFSET_(r32,31, 0,v)

            UNSG32 u_0x00000000                                : 32;
    ///////////////////////////////////////////////////////////
    } SIE_oneReg;

    ///////////////////////////////////////////////////////////
     SIGN32 oneReg_drvrd(SIE_oneReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 oneReg_drvwr(SIE_oneReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void oneReg_reset(SIE_oneReg *p);
     SIGN32 oneReg_cmp  (SIE_oneReg *p, SIE_oneReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define oneReg_check(p,pie,pfx,hLOG) oneReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define oneReg_print(p,    pfx,hLOG) oneReg_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: oneReg
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE IP_REGSP_0                               (4,4)
///     ###
///     * To create SRAM-like interface for PCI-E 3 IP Register access – Creating 32KB address space (Hier:2)
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 dummy                
///               $oneReg              dummy             REG    [8192]
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:   32768B, bits:  262144b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_IP_REGSP_0
#define h_IP_REGSP_0 (){}

    #define     RA_IP_REGSP_0_dummy                            0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_IP_REGSP_0 {
    ///////////////////////////////////////////////////////////
              SIE_oneReg                                       ie_dummy[8192];
    ///////////////////////////////////////////////////////////
    } SIE_IP_REGSP_0;

    ///////////////////////////////////////////////////////////
     SIGN32 IP_REGSP_0_drvrd(SIE_IP_REGSP_0 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 IP_REGSP_0_drvwr(SIE_IP_REGSP_0 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void IP_REGSP_0_reset(SIE_IP_REGSP_0 *p);
     SIGN32 IP_REGSP_0_cmp  (SIE_IP_REGSP_0 *p, SIE_IP_REGSP_0 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define IP_REGSP_0_check(p,pie,pfx,hLOG) IP_REGSP_0_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define IP_REGSP_0_print(p,    pfx,hLOG) IP_REGSP_0_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: IP_REGSP_0
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE IP_REGSP_1                               (4,4)
///     ###
///     * To create SRAM-like interface for PCI-E 3 IP Register access – creating 4KB address space. (Hier:2)
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 dummy                
///               $oneReg              dummy             REG    [2048]
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    8192B, bits:   65536b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_IP_REGSP_1
#define h_IP_REGSP_1 (){}

    #define     RA_IP_REGSP_1_dummy                            0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_IP_REGSP_1 {
    ///////////////////////////////////////////////////////////
              SIE_oneReg                                       ie_dummy[2048];
    ///////////////////////////////////////////////////////////
    } SIE_IP_REGSP_1;

    ///////////////////////////////////////////////////////////
     SIGN32 IP_REGSP_1_drvrd(SIE_IP_REGSP_1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 IP_REGSP_1_drvwr(SIE_IP_REGSP_1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void IP_REGSP_1_reset(SIE_IP_REGSP_1 *p);
     SIGN32 IP_REGSP_1_cmp  (SIE_IP_REGSP_1 *p, SIE_IP_REGSP_1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define IP_REGSP_1_check(p,pie,pfx,hLOG) IP_REGSP_1_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define IP_REGSP_1_print(p,    pfx,hLOG) IP_REGSP_1_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: IP_REGSP_1
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE REFCLK                                   (4,4)
///     ###
///     * PCI-E reference clock buffer control register. This buffer can act in both RX and TX mode.
///     * In RX mode: This buffer takes in 100 Mhz differential clock and generates the single ended 100 Mhz Clock for PCI-E PHY
///     * In TX mode: This buffer receives the single ended 100 Mhz clock from PHY and sends out the differential 100 Mhz clock to Pad
///     * Note: Since the same registers are duplicated for all the 3 PCIE cores. Only the PCIE0 BIU registers are used to control the REFCLK.
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P-)
///               %unsigned 2  PHY_SEL_FOR_RX_EN_PU_CTRL 0x0
///                                    ###
///                                    * Selects which PHY should control the PU and RX_EN for reference clock buffer when operating in RX mode
///                                    * 00 : Phy 0 (PCIE0)
///                                    * 01 : Phy 1 (PCIE0)
///                                    * 10 : Phy 2 (PCIE1)
///                                    * 11 : Phy 3 (PCIE2)
///                                    ###
///               %unsigned 1  SW_CTRL_RX_EN_PU          0x0
///                                    ###
///                                    * Software controls the PU and RX_EN for reference clock buffer when operating in RX mode
///                                    * 0 : PHY controls the RX_EN and PU
///                                    * 1:   SW controls the RX_EN and PU
///                                    ###
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * 0: Power down for minimum power consumption
///                                    * 1: Power UP
///                                    * Note:         If PU = 0 , REFCLK_OUT_RX = 0 and REFCLK_OUT_RX_DIG = 0
///                                    * Must be set to 0 if there are no input clocks
///                                    ###
///               %unsigned 1  SEL_EXT                   0x1
///                                    ###
///                                    * 1: Use external 50Ohm termination
///                                    * 0: Use internal 50Ohm termination.
///                                    ###
///               %unsigned 3  SEL_AMP                   0x3
///                                    ###
///                                    * 111: 0.933V
///                                    * 110: 0.866V
///                                    * 101: 0.800V
///                                    * 100: 0.733V
///                                    * 011: 0.700V
///                                    * 010: 0.666V
///                                    * 001: 0.600V
///                                    * 000: 0.533V
///                                    * Default use 0.7V
///                                    * This choose the output amplitude of the PCIE Reference Clock Buffer
///                                    * Note: If in RX mode only, don't care.
///                                    ###
///               %unsigned 2  SEL_REG_LVL               0x1
///                                    ###
///                                    * PHY Reserved
///                                    ###
///               %unsigned 1  RX_EN                     0x0
///                                    ###
///                                    * 1: Enable RX. The block will act as a receiver and sends clock to PHY.
///                                    * 0: Disable RX.
///                                    * Note:
///                                    * 1) Must be set to 0 if the are no input clocks
///                                    * If RX_EN = 0: then REFCLK_OUT_RX = 0 and REFCLK_OUT_RX_DIG = 0
///                                    * 2) After PU = 1 for 12µs, then only set RX_EN = 1.
///                                    * 3) To turn off RX glitch-lessly, set RX = 0 while maintaining PU = 1 for at least 5 falling edges
///                                    ###
///               %unsigned 1  TX_EN                     0x0
///                                    ###
///                                    * 1: Enable TX. The block will act as a transmitter and sends clock out.
///                                    * 0: Disable TX.
///                                    ###
///               %unsigned 3  TEST_ANA                  0x0
///                                    ###
///                                    * * Analog Test Point:
///                                    * 001: LV regulator output: 0.9V
///                                    * 010: Regulator reference: 0.55V
///                                    * 011: Driver reference: 0.525V
///                                    * 100: AVDD18 1.8V
///                                    * 101: AVSS 0V
///                                    * 110: PD18_RX
///                                    * 111: PD18_TX
///                                    ###
///               %%        17         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      15b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_REFCLK
#define h_REFCLK (){}

    #define     RA_REFCLK_CTRL                                 0x0000

    #define     BA_REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL       0x0000
    #define     B16REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL       0x0000
    #define   LSb32REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL          0
    #define   LSb16REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL          0
    #define       bREFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL       2
    #define   MSK32REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL          0x00000003

    #define     BA_REFCLK_CTRL_SW_CTRL_RX_EN_PU                0x0000
    #define     B16REFCLK_CTRL_SW_CTRL_RX_EN_PU                0x0000
    #define   LSb32REFCLK_CTRL_SW_CTRL_RX_EN_PU                   2
    #define   LSb16REFCLK_CTRL_SW_CTRL_RX_EN_PU                   2
    #define       bREFCLK_CTRL_SW_CTRL_RX_EN_PU                1
    #define   MSK32REFCLK_CTRL_SW_CTRL_RX_EN_PU                   0x00000004

    #define     BA_REFCLK_CTRL_PU                              0x0000
    #define     B16REFCLK_CTRL_PU                              0x0000
    #define   LSb32REFCLK_CTRL_PU                                 3
    #define   LSb16REFCLK_CTRL_PU                                 3
    #define       bREFCLK_CTRL_PU                              1
    #define   MSK32REFCLK_CTRL_PU                                 0x00000008

    #define     BA_REFCLK_CTRL_SEL_EXT                         0x0000
    #define     B16REFCLK_CTRL_SEL_EXT                         0x0000
    #define   LSb32REFCLK_CTRL_SEL_EXT                            4
    #define   LSb16REFCLK_CTRL_SEL_EXT                            4
    #define       bREFCLK_CTRL_SEL_EXT                         1
    #define   MSK32REFCLK_CTRL_SEL_EXT                            0x00000010

    #define     BA_REFCLK_CTRL_SEL_AMP                         0x0000
    #define     B16REFCLK_CTRL_SEL_AMP                         0x0000
    #define   LSb32REFCLK_CTRL_SEL_AMP                            5
    #define   LSb16REFCLK_CTRL_SEL_AMP                            5
    #define       bREFCLK_CTRL_SEL_AMP                         3
    #define   MSK32REFCLK_CTRL_SEL_AMP                            0x000000E0

    #define     BA_REFCLK_CTRL_SEL_REG_LVL                     0x0001
    #define     B16REFCLK_CTRL_SEL_REG_LVL                     0x0000
    #define   LSb32REFCLK_CTRL_SEL_REG_LVL                        8
    #define   LSb16REFCLK_CTRL_SEL_REG_LVL                        8
    #define       bREFCLK_CTRL_SEL_REG_LVL                     2
    #define   MSK32REFCLK_CTRL_SEL_REG_LVL                        0x00000300

    #define     BA_REFCLK_CTRL_RX_EN                           0x0001
    #define     B16REFCLK_CTRL_RX_EN                           0x0000
    #define   LSb32REFCLK_CTRL_RX_EN                              10
    #define   LSb16REFCLK_CTRL_RX_EN                              10
    #define       bREFCLK_CTRL_RX_EN                           1
    #define   MSK32REFCLK_CTRL_RX_EN                              0x00000400

    #define     BA_REFCLK_CTRL_TX_EN                           0x0001
    #define     B16REFCLK_CTRL_TX_EN                           0x0000
    #define   LSb32REFCLK_CTRL_TX_EN                              11
    #define   LSb16REFCLK_CTRL_TX_EN                              11
    #define       bREFCLK_CTRL_TX_EN                           1
    #define   MSK32REFCLK_CTRL_TX_EN                              0x00000800

    #define     BA_REFCLK_CTRL_TEST_ANA                        0x0001
    #define     B16REFCLK_CTRL_TEST_ANA                        0x0000
    #define   LSb32REFCLK_CTRL_TEST_ANA                           12
    #define   LSb16REFCLK_CTRL_TEST_ANA                           12
    #define       bREFCLK_CTRL_TEST_ANA                        3
    #define   MSK32REFCLK_CTRL_TEST_ANA                           0x00007000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_REFCLK {
    ///////////////////////////////////////////////////////////
    #define   GET32REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL(r32)  _BFGET_(r32, 1, 0)
    #define   SET32REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL(r32,v) _BFSET_(r32, 1, 0,v)
    #define   GET16REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL(r16)  _BFGET_(r16, 1, 0)
    #define   SET16REFCLK_CTRL_PHY_SEL_FOR_RX_EN_PU_CTRL(r16,v) _BFSET_(r16, 1, 0,v)

    #define   GET32REFCLK_CTRL_SW_CTRL_RX_EN_PU(r32)           _BFGET_(r32, 2, 2)
    #define   SET32REFCLK_CTRL_SW_CTRL_RX_EN_PU(r32,v)         _BFSET_(r32, 2, 2,v)
    #define   GET16REFCLK_CTRL_SW_CTRL_RX_EN_PU(r16)           _BFGET_(r16, 2, 2)
    #define   SET16REFCLK_CTRL_SW_CTRL_RX_EN_PU(r16,v)         _BFSET_(r16, 2, 2,v)

    #define   GET32REFCLK_CTRL_PU(r32)                         _BFGET_(r32, 3, 3)
    #define   SET32REFCLK_CTRL_PU(r32,v)                       _BFSET_(r32, 3, 3,v)
    #define   GET16REFCLK_CTRL_PU(r16)                         _BFGET_(r16, 3, 3)
    #define   SET16REFCLK_CTRL_PU(r16,v)                       _BFSET_(r16, 3, 3,v)

    #define   GET32REFCLK_CTRL_SEL_EXT(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32REFCLK_CTRL_SEL_EXT(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16REFCLK_CTRL_SEL_EXT(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16REFCLK_CTRL_SEL_EXT(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32REFCLK_CTRL_SEL_AMP(r32)                    _BFGET_(r32, 7, 5)
    #define   SET32REFCLK_CTRL_SEL_AMP(r32,v)                  _BFSET_(r32, 7, 5,v)
    #define   GET16REFCLK_CTRL_SEL_AMP(r16)                    _BFGET_(r16, 7, 5)
    #define   SET16REFCLK_CTRL_SEL_AMP(r16,v)                  _BFSET_(r16, 7, 5,v)

    #define   GET32REFCLK_CTRL_SEL_REG_LVL(r32)                _BFGET_(r32, 9, 8)
    #define   SET32REFCLK_CTRL_SEL_REG_LVL(r32,v)              _BFSET_(r32, 9, 8,v)
    #define   GET16REFCLK_CTRL_SEL_REG_LVL(r16)                _BFGET_(r16, 9, 8)
    #define   SET16REFCLK_CTRL_SEL_REG_LVL(r16,v)              _BFSET_(r16, 9, 8,v)

    #define   GET32REFCLK_CTRL_RX_EN(r32)                      _BFGET_(r32,10,10)
    #define   SET32REFCLK_CTRL_RX_EN(r32,v)                    _BFSET_(r32,10,10,v)
    #define   GET16REFCLK_CTRL_RX_EN(r16)                      _BFGET_(r16,10,10)
    #define   SET16REFCLK_CTRL_RX_EN(r16,v)                    _BFSET_(r16,10,10,v)

    #define   GET32REFCLK_CTRL_TX_EN(r32)                      _BFGET_(r32,11,11)
    #define   SET32REFCLK_CTRL_TX_EN(r32,v)                    _BFSET_(r32,11,11,v)
    #define   GET16REFCLK_CTRL_TX_EN(r16)                      _BFGET_(r16,11,11)
    #define   SET16REFCLK_CTRL_TX_EN(r16,v)                    _BFSET_(r16,11,11,v)

    #define   GET32REFCLK_CTRL_TEST_ANA(r32)                   _BFGET_(r32,14,12)
    #define   SET32REFCLK_CTRL_TEST_ANA(r32,v)                 _BFSET_(r32,14,12,v)
    #define   GET16REFCLK_CTRL_TEST_ANA(r16)                   _BFGET_(r16,14,12)
    #define   SET16REFCLK_CTRL_TEST_ANA(r16,v)                 _BFSET_(r16,14,12,v)

    #define     w32REFCLK_CTRL                                 {\
            UNSG32 uCTRL_PHY_SEL_FOR_RX_EN_PU_CTRL             :  2;\
            UNSG32 uCTRL_SW_CTRL_RX_EN_PU                      :  1;\
            UNSG32 uCTRL_PU                                    :  1;\
            UNSG32 uCTRL_SEL_EXT                               :  1;\
            UNSG32 uCTRL_SEL_AMP                               :  3;\
            UNSG32 uCTRL_SEL_REG_LVL                           :  2;\
            UNSG32 uCTRL_RX_EN                                 :  1;\
            UNSG32 uCTRL_TX_EN                                 :  1;\
            UNSG32 uCTRL_TEST_ANA                              :  3;\
            UNSG32 RSVDx0_b15                                  : 17;\
          }
    union { UNSG32 u32REFCLK_CTRL;
            struct w32REFCLK_CTRL;
          };
    ///////////////////////////////////////////////////////////
    } SIE_REFCLK;

    typedef union  T32REFCLK_CTRL
          { UNSG32 u32;
            struct w32REFCLK_CTRL;
                 } T32REFCLK_CTRL;
    ///////////////////////////////////////////////////////////

    typedef union  TREFCLK_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32REFCLK_CTRL;
                   };
                 } TREFCLK_CTRL;

    ///////////////////////////////////////////////////////////
     SIGN32 REFCLK_drvrd(SIE_REFCLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 REFCLK_drvwr(SIE_REFCLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void REFCLK_reset(SIE_REFCLK *p);
     SIGN32 REFCLK_cmp  (SIE_REFCLK *p, SIE_REFCLK *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define REFCLK_check(p,pie,pfx,hLOG) REFCLK_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define REFCLK_print(p,    pfx,hLOG) REFCLK_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: REFCLK
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE PCIE                    biu              (4,4)
///     ###
///     * PCI-E module register space
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 IP_REGSP_0           
///               $IP_REGSP_0          IP_REGSP_0        MEM          
///                                    ###
///                                    * PCIE 3 IP First 32KB register Space
///                                    ###
///     @ 0x08000                      (P)
///     # 0x08000 IP_REGSP_1           
///               $IP_REGSP_1          IP_REGSP_1        MEM          
///                                    ###
///                                    * PCIE 3 IP Second 8KB register Space, So total IP Register space is 40KB
///                                    ###
///     @ 0x0A000 MSI_INTR_RX          (RW-)
///               ###
///               * PCI-E MSI Received register
///               ###
///               %unsigned 32 DATA                      0x0
///                                    ###
///                                    * Data Received register
///                                    * The received data decides which function generated the interrupt. This data is used to set the corresponding bits in the INTR Status register
///                                    * Note: Software should use the [15:13] bits as the function ID while programming the MSI DATA register in the endpoint
///                                    * Endpoint should use the [1:0] bits to indicate what type of interrupt is this.
///                                    ###
///     @ 0x0A004 MSI_INTR_STATUS      (WOC-)
///               ###
///               * PCI-E MSI Interrupt Status register
///               * BG3 supports MSI for 8 functions and each function can have 4 types of interrupts.
///               * The register implements 4 Interrupt bits for each function.
///               * A value of 1 : indicates that the interrupt is pending for that function
///               * A value of 0 : indicates no interrupt pending
///               * Note: Write-1-to clear the interrupt in this register
///               ###
///               %unsigned 32 VALUE                     0x0
///                                    ###
///                                    * MSI Interrupt status
///                                    * The bits in this register indicates MSI Interrupt status for the 8 functions.
///                                    * For each bit :
///                                    * 0 : means Interrupt is not pending
///                                    * 1 : means Interrupt is pending
///                                    * The following is the mapping between function and interrupt bits:
///                                    * Bits [3:0]     : MSI Interrupt status for Function 0 interrupts
///                                    * Bits [7:4]     : MSI Interrupt status for Function 1 interrupts
///                                    * Bits [11:8]   : MSI Interrupt status for Function 2 interrupts
///                                    * Bits [15:12] : MSI Interrupt status for Function 3 interrupts
///                                    * Bits [19:16] : MSI Interrupt status for Function 4 interrupts
///                                    * Bits [23:20] : MSI Interrupt status for Function 5 interrupts
///                                    * Bits [27:24] : MSI Interrupt status for Function 6 interrupts
///                                    * Bits [31:28] : MSI Interrupt status for Function 7 interrupts
///                                    * Each function has 4-bits each (so can have 4 different types of interrupts). If any of them is set, it means corresponding Interrupt for that function is pending.
///                                    ###
///     @ 0x0A008 MSI_INTR_MASK        (RW)
///               ###
///               * PCI-E MSI Interrupt Mask register
///               ###
///               %unsigned 32 VALUE                     0x0
///                                    ###
///                                    *   Interrupt Mask
///                                    * 0 : Interrupt enabled
///                                    * 1 : Interrupt disabled (masked)
///                                    * Bits [3:0] : Interrupt Mask for Function 0 interrupts
///                                    * Bits [7:4] : Interrupt Mask for Function 1 interrupts
///                                    * Bits [11:8] : Interrupt Mask for Function 2 interrupts
///                                    * Bits [15:12] : Interrupt Mask for Function 3 interrupts
///                                    * Bits [19:16] : Interrupt Mask for Function 4 interrupts
///                                    * Bits [23:20] : Interrupt Mask for Function 5 interrupts
///                                    * Bits [27:24] : Interrupt Mask for Function 6 interrupts
///                                    * Bits [31:28] : Interrupt Mask for Function 7 interrupts
///                                    ###
///     @ 0x0A00C MAC_CTRL             (RW)
///               ###
///               * PCIE MAC control register
///               ###
///               %unsigned 1  SYSWREQ                   0x0
///                                    ###
///                                    * AXI Lower power control bit
///                                    ###
///               %unsigned 1  CPU_INTERFACE_SEL         0x0
///                                    ###
///                                    * CPU Interface selection bit
///                                    * 0 : Use AHB to access PCIE registers
///                                    * 1 : Use SIF Serial interface to access the registers
///                                    ###
///               %unsigned 1  CFG_TYPE                  0x0
///                                    ###
///                                    * Register bit to indicate whether outbound CFG cycles are Type 0 or Type1
///                                    * 0 :   Type 0 configuration cycles (default)
///                                    * 1 :   Type 1 configuration cycles cd
///                                    ###
///               %unsigned 1  MEMMAP_CFG_VALID          0x1
///                                    ###
///                                    * Register bit to indicate whether Memory Mapped CFG cycles are supported or not.
///                                    * 0 : Memory mapped CFG cycles are not supported
///                                    * 1 : Memory mapped CFG cycles are supported
///                                    * Note: When this bit 0 : All the AXI transactions on the outbound will be send as Memory TLPs
///                                    * When this bit is 1     : The 512MB address space for PCIE in the chip is divided into parts, with lower 256MB for MEM and upper 256MB for CFG access.
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x0A010 MAC_STATUS           (R-)
///               ###
///               * PCIE MAC misc status register
///               ###
///               %unsigned 1  DWACK                     
///                                    ###
///                                    * AXI low power status
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x0A014 MAC_CLK_CTRL         (RW)
///               ###
///               * PCIE MAC clock control register
///               ###
///               %unsigned 1  AXI_CLKEN                 0x1
///                                    ###
///                                    * AXI clock enable
///                                    * 0: CLK is not enabled (OFF )
///                                    * 1: CLK is enabled (ON)
///                                    ###
///               %unsigned 1  AHB_CLKEN                 0x1
///                                    ###
///                                    * AHB clock enable
///                                    * 0: CLK is not enabled (OFF )
///                                    * 1: CLK is enabled (ON)
///                                    ###
///               %unsigned 1  CORE_CLKEN                0x1
///                                    ###
///                                    * PCIE Core clock enable
///                                    * 0: CLK is not enabled (OFF )
///                                    * 1: CLK is enabled (ON)
///                                    ###
///               %unsigned 1  PIPE_CLKEN                0x1
///                                    ###
///                                    * PPIE clock enable
///                                    * 0: CLK is not enabled (OFF )
///                                    * 1: CLK is enabled (ON)
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x0A018                      (P)
///     # 0x0A018 REFCLK               
///               $REFCLK              REFCLK            REG          
///                                    ###
///                                    * Reference clock buffer control registers
///                                    ###
///     @ 0x0A01C PHY_CTRL             (RW)
///               ###
///               * PHY control register
///               ###
///               %unsigned 1  RXEIDETECT_DIS            0x0
///                                    ###
///                                    * Rx electrical idle (or squelch) detect disable:
///                                    * 0 : Squelch detector is enabled
///                                    * 1 : Squelch detector is disabled
///                                    ###
///               %unsigned 1  TXCMN_MODE_DIS            0x0
///                                    ###
///                                    * Tx common mode disable
///                                    * 0 : Tx common mode circuit is enabled
///                                    * 1: Tx common mode circuit is disabled
///                                    ###
///               %unsigned 2  SIF_MUX_SEL               0x0
///                                    ###
///                                    * Register bits to select which PHY SIF interface is being used out of the 4 PHY
///                                    * 00 : PHY 0 selected
///                                    * 01 ; PHY 1 Selected
///                                    * 10 ; PHY 2 Selected
///                                    * 11 ; PHY 3 Selected
///                                    ###
///               %unsigned 2  SIF_DEV_SEL               0x1
///                                    ###
///                                    * Device select for serial interface
///                                    * 00 : SIF is disabled
///                                    * 01 : SIF is enabled for PHY (For multi-lanes this bit selects the PHY0)
///                                    * 10 : SIF enabled for PHY1 (Only for multi-lane MAC (PCIE0))
///                                    ###
///               %unsigned 1  ISOLATION_ENB             0x1
///                                    ###
///                                    * Control bit for isolation function
///                                    * 0 : Power down mode
///                                    * 1: Normal function mode
///                                    ###
///               %%        25         # Stuffing bits...
///     @ 0x0A020 HWDBG_CTRL           (RW)
///               ###
///               * Hardware Debug control. This register is used to select the Debug Bus coming out of the PCIE subsystem to the chip pins.
///               ###
///               %unsigned 2  PCIESEL                   0x0
///                                    ###
///                                    * Bit used to select which PCIE debug bus needs to be selected to be observed on the Chip debug port
///                                    * 0 : PCIE 0 (x2 MAC)
///                                    * 1 : PCIE 1 (x1 MAC)
///                                    * 2 : PCIE 2 (x1 MAC)
///                                    * Note: Only PCIE0 register bits are used others are not used
///                                    ###
///               %unsigned 1  DATASEL                   0x0
///                                    ###
///                                    * Bit to select the upper or lower 16-bits of the debug data.
///                                    * 0: Selects the [15:0] data
///                                    * 1: Selects the [31:16] data
///                                    * Note: Only PCIE0 register bits are used others are not used
///                                    ###
///               %unsigned 8  SIGSEL                    0x0
///                                    ###
///                                    * These bits selects the debug signals from each PCIE IP.
///                                    * Note: All the PCIE0/1/2 register bits are used since the debug data from all the 3 PCIE is stored in the HWDBG_DATA regitser
///                                    ###
///               %%        21         # Stuffing bits...
///     @ 0x0A024 HWDBG_DATA           (R-)
///               ###
///               * Debug data from IP
///               ###
///               %unsigned 32 VAL                       
///     @ 0x0A028 SPARE_0              (RW)
///               %unsigned 32 REGBITS                   0x0
///     @ 0x0A02C SPARE_1              (RW)
///               %unsigned 32 REGBITS                   0x0
///     @ 0x0A030 SPARE_2              (RW)
///               %unsigned 32 REGBITS                   0x0
///     @ 0x0A034 SPARE_3              (RW)
///               %unsigned 32 REGBITS                   0x0
///                                    ###
///                                    * **INTERNAL_ONLY**
///                                    * Spare register bits for future use
///                                    ###
///     @ 0x0A038                      (W-)
///     #         # Stuffing bytes...
///               %% 196160
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:   65536B, bits:     362b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_PCIE
#define h_PCIE (){}

    #define     RA_PCIE_IP_REGSP_0                             0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_IP_REGSP_1                             0x8000
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_MSI_INTR_RX                            0xA000

    #define     BA_PCIE_MSI_INTR_RX_DATA                       0xA000
    #define     B16PCIE_MSI_INTR_RX_DATA                       0xA000
    #define   LSb32PCIE_MSI_INTR_RX_DATA                          0
    #define   LSb16PCIE_MSI_INTR_RX_DATA                          0
    #define       bPCIE_MSI_INTR_RX_DATA                       32
    #define   MSK32PCIE_MSI_INTR_RX_DATA                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_MSI_INTR_STATUS                        0xA004

    #define     BA_PCIE_MSI_INTR_STATUS_VALUE                  0xA004
    #define     B16PCIE_MSI_INTR_STATUS_VALUE                  0xA004
    #define   LSb32PCIE_MSI_INTR_STATUS_VALUE                     0
    #define   LSb16PCIE_MSI_INTR_STATUS_VALUE                     0
    #define       bPCIE_MSI_INTR_STATUS_VALUE                  32
    #define   MSK32PCIE_MSI_INTR_STATUS_VALUE                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_MSI_INTR_MASK                          0xA008

    #define     BA_PCIE_MSI_INTR_MASK_VALUE                    0xA008
    #define     B16PCIE_MSI_INTR_MASK_VALUE                    0xA008
    #define   LSb32PCIE_MSI_INTR_MASK_VALUE                       0
    #define   LSb16PCIE_MSI_INTR_MASK_VALUE                       0
    #define       bPCIE_MSI_INTR_MASK_VALUE                    32
    #define   MSK32PCIE_MSI_INTR_MASK_VALUE                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_MAC_CTRL                               0xA00C

    #define     BA_PCIE_MAC_CTRL_SYSWREQ                       0xA00C
    #define     B16PCIE_MAC_CTRL_SYSWREQ                       0xA00C
    #define   LSb32PCIE_MAC_CTRL_SYSWREQ                          0
    #define   LSb16PCIE_MAC_CTRL_SYSWREQ                          0
    #define       bPCIE_MAC_CTRL_SYSWREQ                       1
    #define   MSK32PCIE_MAC_CTRL_SYSWREQ                          0x00000001

    #define     BA_PCIE_MAC_CTRL_CPU_INTERFACE_SEL             0xA00C
    #define     B16PCIE_MAC_CTRL_CPU_INTERFACE_SEL             0xA00C
    #define   LSb32PCIE_MAC_CTRL_CPU_INTERFACE_SEL                1
    #define   LSb16PCIE_MAC_CTRL_CPU_INTERFACE_SEL                1
    #define       bPCIE_MAC_CTRL_CPU_INTERFACE_SEL             1
    #define   MSK32PCIE_MAC_CTRL_CPU_INTERFACE_SEL                0x00000002

    #define     BA_PCIE_MAC_CTRL_CFG_TYPE                      0xA00C
    #define     B16PCIE_MAC_CTRL_CFG_TYPE                      0xA00C
    #define   LSb32PCIE_MAC_CTRL_CFG_TYPE                         2
    #define   LSb16PCIE_MAC_CTRL_CFG_TYPE                         2
    #define       bPCIE_MAC_CTRL_CFG_TYPE                      1
    #define   MSK32PCIE_MAC_CTRL_CFG_TYPE                         0x00000004

    #define     BA_PCIE_MAC_CTRL_MEMMAP_CFG_VALID              0xA00C
    #define     B16PCIE_MAC_CTRL_MEMMAP_CFG_VALID              0xA00C
    #define   LSb32PCIE_MAC_CTRL_MEMMAP_CFG_VALID                 3
    #define   LSb16PCIE_MAC_CTRL_MEMMAP_CFG_VALID                 3
    #define       bPCIE_MAC_CTRL_MEMMAP_CFG_VALID              1
    #define   MSK32PCIE_MAC_CTRL_MEMMAP_CFG_VALID                 0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_MAC_STATUS                             0xA010

    #define     BA_PCIE_MAC_STATUS_DWACK                       0xA010
    #define     B16PCIE_MAC_STATUS_DWACK                       0xA010
    #define   LSb32PCIE_MAC_STATUS_DWACK                          0
    #define   LSb16PCIE_MAC_STATUS_DWACK                          0
    #define       bPCIE_MAC_STATUS_DWACK                       1
    #define   MSK32PCIE_MAC_STATUS_DWACK                          0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_MAC_CLK_CTRL                           0xA014

    #define     BA_PCIE_MAC_CLK_CTRL_AXI_CLKEN                 0xA014
    #define     B16PCIE_MAC_CLK_CTRL_AXI_CLKEN                 0xA014
    #define   LSb32PCIE_MAC_CLK_CTRL_AXI_CLKEN                    0
    #define   LSb16PCIE_MAC_CLK_CTRL_AXI_CLKEN                    0
    #define       bPCIE_MAC_CLK_CTRL_AXI_CLKEN                 1
    #define   MSK32PCIE_MAC_CLK_CTRL_AXI_CLKEN                    0x00000001

    #define     BA_PCIE_MAC_CLK_CTRL_AHB_CLKEN                 0xA014
    #define     B16PCIE_MAC_CLK_CTRL_AHB_CLKEN                 0xA014
    #define   LSb32PCIE_MAC_CLK_CTRL_AHB_CLKEN                    1
    #define   LSb16PCIE_MAC_CLK_CTRL_AHB_CLKEN                    1
    #define       bPCIE_MAC_CLK_CTRL_AHB_CLKEN                 1
    #define   MSK32PCIE_MAC_CLK_CTRL_AHB_CLKEN                    0x00000002

    #define     BA_PCIE_MAC_CLK_CTRL_CORE_CLKEN                0xA014
    #define     B16PCIE_MAC_CLK_CTRL_CORE_CLKEN                0xA014
    #define   LSb32PCIE_MAC_CLK_CTRL_CORE_CLKEN                   2
    #define   LSb16PCIE_MAC_CLK_CTRL_CORE_CLKEN                   2
    #define       bPCIE_MAC_CLK_CTRL_CORE_CLKEN                1
    #define   MSK32PCIE_MAC_CLK_CTRL_CORE_CLKEN                   0x00000004

    #define     BA_PCIE_MAC_CLK_CTRL_PIPE_CLKEN                0xA014
    #define     B16PCIE_MAC_CLK_CTRL_PIPE_CLKEN                0xA014
    #define   LSb32PCIE_MAC_CLK_CTRL_PIPE_CLKEN                   3
    #define   LSb16PCIE_MAC_CLK_CTRL_PIPE_CLKEN                   3
    #define       bPCIE_MAC_CLK_CTRL_PIPE_CLKEN                1
    #define   MSK32PCIE_MAC_CLK_CTRL_PIPE_CLKEN                   0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_REFCLK                                 0xA018
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_PHY_CTRL                               0xA01C

    #define     BA_PCIE_PHY_CTRL_RXEIDETECT_DIS                0xA01C
    #define     B16PCIE_PHY_CTRL_RXEIDETECT_DIS                0xA01C
    #define   LSb32PCIE_PHY_CTRL_RXEIDETECT_DIS                   0
    #define   LSb16PCIE_PHY_CTRL_RXEIDETECT_DIS                   0
    #define       bPCIE_PHY_CTRL_RXEIDETECT_DIS                1
    #define   MSK32PCIE_PHY_CTRL_RXEIDETECT_DIS                   0x00000001

    #define     BA_PCIE_PHY_CTRL_TXCMN_MODE_DIS                0xA01C
    #define     B16PCIE_PHY_CTRL_TXCMN_MODE_DIS                0xA01C
    #define   LSb32PCIE_PHY_CTRL_TXCMN_MODE_DIS                   1
    #define   LSb16PCIE_PHY_CTRL_TXCMN_MODE_DIS                   1
    #define       bPCIE_PHY_CTRL_TXCMN_MODE_DIS                1
    #define   MSK32PCIE_PHY_CTRL_TXCMN_MODE_DIS                   0x00000002

    #define     BA_PCIE_PHY_CTRL_SIF_MUX_SEL                   0xA01C
    #define     B16PCIE_PHY_CTRL_SIF_MUX_SEL                   0xA01C
    #define   LSb32PCIE_PHY_CTRL_SIF_MUX_SEL                      2
    #define   LSb16PCIE_PHY_CTRL_SIF_MUX_SEL                      2
    #define       bPCIE_PHY_CTRL_SIF_MUX_SEL                   2
    #define   MSK32PCIE_PHY_CTRL_SIF_MUX_SEL                      0x0000000C

    #define     BA_PCIE_PHY_CTRL_SIF_DEV_SEL                   0xA01C
    #define     B16PCIE_PHY_CTRL_SIF_DEV_SEL                   0xA01C
    #define   LSb32PCIE_PHY_CTRL_SIF_DEV_SEL                      4
    #define   LSb16PCIE_PHY_CTRL_SIF_DEV_SEL                      4
    #define       bPCIE_PHY_CTRL_SIF_DEV_SEL                   2
    #define   MSK32PCIE_PHY_CTRL_SIF_DEV_SEL                      0x00000030

    #define     BA_PCIE_PHY_CTRL_ISOLATION_ENB                 0xA01C
    #define     B16PCIE_PHY_CTRL_ISOLATION_ENB                 0xA01C
    #define   LSb32PCIE_PHY_CTRL_ISOLATION_ENB                    6
    #define   LSb16PCIE_PHY_CTRL_ISOLATION_ENB                    6
    #define       bPCIE_PHY_CTRL_ISOLATION_ENB                 1
    #define   MSK32PCIE_PHY_CTRL_ISOLATION_ENB                    0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_HWDBG_CTRL                             0xA020

    #define     BA_PCIE_HWDBG_CTRL_PCIESEL                     0xA020
    #define     B16PCIE_HWDBG_CTRL_PCIESEL                     0xA020
    #define   LSb32PCIE_HWDBG_CTRL_PCIESEL                        0
    #define   LSb16PCIE_HWDBG_CTRL_PCIESEL                        0
    #define       bPCIE_HWDBG_CTRL_PCIESEL                     2
    #define   MSK32PCIE_HWDBG_CTRL_PCIESEL                        0x00000003

    #define     BA_PCIE_HWDBG_CTRL_DATASEL                     0xA020
    #define     B16PCIE_HWDBG_CTRL_DATASEL                     0xA020
    #define   LSb32PCIE_HWDBG_CTRL_DATASEL                        2
    #define   LSb16PCIE_HWDBG_CTRL_DATASEL                        2
    #define       bPCIE_HWDBG_CTRL_DATASEL                     1
    #define   MSK32PCIE_HWDBG_CTRL_DATASEL                        0x00000004

    #define     BA_PCIE_HWDBG_CTRL_SIGSEL                      0xA020
    #define     B16PCIE_HWDBG_CTRL_SIGSEL                      0xA020
    #define   LSb32PCIE_HWDBG_CTRL_SIGSEL                         3
    #define   LSb16PCIE_HWDBG_CTRL_SIGSEL                         3
    #define       bPCIE_HWDBG_CTRL_SIGSEL                      8
    #define   MSK32PCIE_HWDBG_CTRL_SIGSEL                         0x000007F8
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_HWDBG_DATA                             0xA024

    #define     BA_PCIE_HWDBG_DATA_VAL                         0xA024
    #define     B16PCIE_HWDBG_DATA_VAL                         0xA024
    #define   LSb32PCIE_HWDBG_DATA_VAL                            0
    #define   LSb16PCIE_HWDBG_DATA_VAL                            0
    #define       bPCIE_HWDBG_DATA_VAL                         32
    #define   MSK32PCIE_HWDBG_DATA_VAL                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_SPARE_0                                0xA028

    #define     BA_PCIE_SPARE_0_REGBITS                        0xA028
    #define     B16PCIE_SPARE_0_REGBITS                        0xA028
    #define   LSb32PCIE_SPARE_0_REGBITS                           0
    #define   LSb16PCIE_SPARE_0_REGBITS                           0
    #define       bPCIE_SPARE_0_REGBITS                        32
    #define   MSK32PCIE_SPARE_0_REGBITS                           0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_SPARE_1                                0xA02C

    #define     BA_PCIE_SPARE_1_REGBITS                        0xA02C
    #define     B16PCIE_SPARE_1_REGBITS                        0xA02C
    #define   LSb32PCIE_SPARE_1_REGBITS                           0
    #define   LSb16PCIE_SPARE_1_REGBITS                           0
    #define       bPCIE_SPARE_1_REGBITS                        32
    #define   MSK32PCIE_SPARE_1_REGBITS                           0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_SPARE_2                                0xA030

    #define     BA_PCIE_SPARE_2_REGBITS                        0xA030
    #define     B16PCIE_SPARE_2_REGBITS                        0xA030
    #define   LSb32PCIE_SPARE_2_REGBITS                           0
    #define   LSb16PCIE_SPARE_2_REGBITS                           0
    #define       bPCIE_SPARE_2_REGBITS                        32
    #define   MSK32PCIE_SPARE_2_REGBITS                           0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PCIE_SPARE_3                                0xA034

    #define     BA_PCIE_SPARE_3_REGBITS                        0xA034
    #define     B16PCIE_SPARE_3_REGBITS                        0xA034
    #define   LSb32PCIE_SPARE_3_REGBITS                           0
    #define   LSb16PCIE_SPARE_3_REGBITS                           0
    #define       bPCIE_SPARE_3_REGBITS                        32
    #define   MSK32PCIE_SPARE_3_REGBITS                           0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_PCIE {
    ///////////////////////////////////////////////////////////
              SIE_IP_REGSP_0                                   ie_IP_REGSP_0;
    ///////////////////////////////////////////////////////////
              SIE_IP_REGSP_1                                   ie_IP_REGSP_1;
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_MSI_INTR_RX_DATA(r32)                  _BFGET_(r32,31, 0)
    #define   SET32PCIE_MSI_INTR_RX_DATA(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32PCIE_MSI_INTR_RX                            {\
            UNSG32 uMSI_INTR_RX_DATA                           : 32;\
          }
    union { UNSG32 u32PCIE_MSI_INTR_RX;
            struct w32PCIE_MSI_INTR_RX;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_MSI_INTR_STATUS_VALUE(r32)             _BFGET_(r32,31, 0)
    #define   SET32PCIE_MSI_INTR_STATUS_VALUE(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32PCIE_MSI_INTR_STATUS                        {\
            UNSG32 uMSI_INTR_STATUS_VALUE                      : 32;\
          }
    union { UNSG32 u32PCIE_MSI_INTR_STATUS;
            struct w32PCIE_MSI_INTR_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_MSI_INTR_MASK_VALUE(r32)               _BFGET_(r32,31, 0)
    #define   SET32PCIE_MSI_INTR_MASK_VALUE(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32PCIE_MSI_INTR_MASK                          {\
            UNSG32 uMSI_INTR_MASK_VALUE                        : 32;\
          }
    union { UNSG32 u32PCIE_MSI_INTR_MASK;
            struct w32PCIE_MSI_INTR_MASK;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_MAC_CTRL_SYSWREQ(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32PCIE_MAC_CTRL_SYSWREQ(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16PCIE_MAC_CTRL_SYSWREQ(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16PCIE_MAC_CTRL_SYSWREQ(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32PCIE_MAC_CTRL_CPU_INTERFACE_SEL(r32)        _BFGET_(r32, 1, 1)
    #define   SET32PCIE_MAC_CTRL_CPU_INTERFACE_SEL(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16PCIE_MAC_CTRL_CPU_INTERFACE_SEL(r16)        _BFGET_(r16, 1, 1)
    #define   SET16PCIE_MAC_CTRL_CPU_INTERFACE_SEL(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32PCIE_MAC_CTRL_CFG_TYPE(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32PCIE_MAC_CTRL_CFG_TYPE(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16PCIE_MAC_CTRL_CFG_TYPE(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16PCIE_MAC_CTRL_CFG_TYPE(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32PCIE_MAC_CTRL_MEMMAP_CFG_VALID(r32)         _BFGET_(r32, 3, 3)
    #define   SET32PCIE_MAC_CTRL_MEMMAP_CFG_VALID(r32,v)       _BFSET_(r32, 3, 3,v)
    #define   GET16PCIE_MAC_CTRL_MEMMAP_CFG_VALID(r16)         _BFGET_(r16, 3, 3)
    #define   SET16PCIE_MAC_CTRL_MEMMAP_CFG_VALID(r16,v)       _BFSET_(r16, 3, 3,v)

    #define     w32PCIE_MAC_CTRL                               {\
            UNSG32 uMAC_CTRL_SYSWREQ                           :  1;\
            UNSG32 uMAC_CTRL_CPU_INTERFACE_SEL                 :  1;\
            UNSG32 uMAC_CTRL_CFG_TYPE                          :  1;\
            UNSG32 uMAC_CTRL_MEMMAP_CFG_VALID                  :  1;\
            UNSG32 RSVDxA00C_b4                                : 28;\
          }
    union { UNSG32 u32PCIE_MAC_CTRL;
            struct w32PCIE_MAC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_MAC_STATUS_DWACK(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32PCIE_MAC_STATUS_DWACK(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16PCIE_MAC_STATUS_DWACK(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16PCIE_MAC_STATUS_DWACK(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32PCIE_MAC_STATUS                             {\
            UNSG32 uMAC_STATUS_DWACK                           :  1;\
            UNSG32 RSVDxA010_b1                                : 31;\
          }
    union { UNSG32 u32PCIE_MAC_STATUS;
            struct w32PCIE_MAC_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_MAC_CLK_CTRL_AXI_CLKEN(r32)            _BFGET_(r32, 0, 0)
    #define   SET32PCIE_MAC_CLK_CTRL_AXI_CLKEN(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16PCIE_MAC_CLK_CTRL_AXI_CLKEN(r16)            _BFGET_(r16, 0, 0)
    #define   SET16PCIE_MAC_CLK_CTRL_AXI_CLKEN(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32PCIE_MAC_CLK_CTRL_AHB_CLKEN(r32)            _BFGET_(r32, 1, 1)
    #define   SET32PCIE_MAC_CLK_CTRL_AHB_CLKEN(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16PCIE_MAC_CLK_CTRL_AHB_CLKEN(r16)            _BFGET_(r16, 1, 1)
    #define   SET16PCIE_MAC_CLK_CTRL_AHB_CLKEN(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32PCIE_MAC_CLK_CTRL_CORE_CLKEN(r32)           _BFGET_(r32, 2, 2)
    #define   SET32PCIE_MAC_CLK_CTRL_CORE_CLKEN(r32,v)         _BFSET_(r32, 2, 2,v)
    #define   GET16PCIE_MAC_CLK_CTRL_CORE_CLKEN(r16)           _BFGET_(r16, 2, 2)
    #define   SET16PCIE_MAC_CLK_CTRL_CORE_CLKEN(r16,v)         _BFSET_(r16, 2, 2,v)

    #define   GET32PCIE_MAC_CLK_CTRL_PIPE_CLKEN(r32)           _BFGET_(r32, 3, 3)
    #define   SET32PCIE_MAC_CLK_CTRL_PIPE_CLKEN(r32,v)         _BFSET_(r32, 3, 3,v)
    #define   GET16PCIE_MAC_CLK_CTRL_PIPE_CLKEN(r16)           _BFGET_(r16, 3, 3)
    #define   SET16PCIE_MAC_CLK_CTRL_PIPE_CLKEN(r16,v)         _BFSET_(r16, 3, 3,v)

    #define     w32PCIE_MAC_CLK_CTRL                           {\
            UNSG32 uMAC_CLK_CTRL_AXI_CLKEN                     :  1;\
            UNSG32 uMAC_CLK_CTRL_AHB_CLKEN                     :  1;\
            UNSG32 uMAC_CLK_CTRL_CORE_CLKEN                    :  1;\
            UNSG32 uMAC_CLK_CTRL_PIPE_CLKEN                    :  1;\
            UNSG32 RSVDxA014_b4                                : 28;\
          }
    union { UNSG32 u32PCIE_MAC_CLK_CTRL;
            struct w32PCIE_MAC_CLK_CTRL;
          };
    ///////////////////////////////////////////////////////////
              SIE_REFCLK                                       ie_REFCLK;
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_PHY_CTRL_RXEIDETECT_DIS(r32)           _BFGET_(r32, 0, 0)
    #define   SET32PCIE_PHY_CTRL_RXEIDETECT_DIS(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16PCIE_PHY_CTRL_RXEIDETECT_DIS(r16)           _BFGET_(r16, 0, 0)
    #define   SET16PCIE_PHY_CTRL_RXEIDETECT_DIS(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32PCIE_PHY_CTRL_TXCMN_MODE_DIS(r32)           _BFGET_(r32, 1, 1)
    #define   SET32PCIE_PHY_CTRL_TXCMN_MODE_DIS(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16PCIE_PHY_CTRL_TXCMN_MODE_DIS(r16)           _BFGET_(r16, 1, 1)
    #define   SET16PCIE_PHY_CTRL_TXCMN_MODE_DIS(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32PCIE_PHY_CTRL_SIF_MUX_SEL(r32)              _BFGET_(r32, 3, 2)
    #define   SET32PCIE_PHY_CTRL_SIF_MUX_SEL(r32,v)            _BFSET_(r32, 3, 2,v)
    #define   GET16PCIE_PHY_CTRL_SIF_MUX_SEL(r16)              _BFGET_(r16, 3, 2)
    #define   SET16PCIE_PHY_CTRL_SIF_MUX_SEL(r16,v)            _BFSET_(r16, 3, 2,v)

    #define   GET32PCIE_PHY_CTRL_SIF_DEV_SEL(r32)              _BFGET_(r32, 5, 4)
    #define   SET32PCIE_PHY_CTRL_SIF_DEV_SEL(r32,v)            _BFSET_(r32, 5, 4,v)
    #define   GET16PCIE_PHY_CTRL_SIF_DEV_SEL(r16)              _BFGET_(r16, 5, 4)
    #define   SET16PCIE_PHY_CTRL_SIF_DEV_SEL(r16,v)            _BFSET_(r16, 5, 4,v)

    #define   GET32PCIE_PHY_CTRL_ISOLATION_ENB(r32)            _BFGET_(r32, 6, 6)
    #define   SET32PCIE_PHY_CTRL_ISOLATION_ENB(r32,v)          _BFSET_(r32, 6, 6,v)
    #define   GET16PCIE_PHY_CTRL_ISOLATION_ENB(r16)            _BFGET_(r16, 6, 6)
    #define   SET16PCIE_PHY_CTRL_ISOLATION_ENB(r16,v)          _BFSET_(r16, 6, 6,v)

    #define     w32PCIE_PHY_CTRL                               {\
            UNSG32 uPHY_CTRL_RXEIDETECT_DIS                    :  1;\
            UNSG32 uPHY_CTRL_TXCMN_MODE_DIS                    :  1;\
            UNSG32 uPHY_CTRL_SIF_MUX_SEL                       :  2;\
            UNSG32 uPHY_CTRL_SIF_DEV_SEL                       :  2;\
            UNSG32 uPHY_CTRL_ISOLATION_ENB                     :  1;\
            UNSG32 RSVDxA01C_b7                                : 25;\
          }
    union { UNSG32 u32PCIE_PHY_CTRL;
            struct w32PCIE_PHY_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_HWDBG_CTRL_PCIESEL(r32)                _BFGET_(r32, 1, 0)
    #define   SET32PCIE_HWDBG_CTRL_PCIESEL(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16PCIE_HWDBG_CTRL_PCIESEL(r16)                _BFGET_(r16, 1, 0)
    #define   SET16PCIE_HWDBG_CTRL_PCIESEL(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32PCIE_HWDBG_CTRL_DATASEL(r32)                _BFGET_(r32, 2, 2)
    #define   SET32PCIE_HWDBG_CTRL_DATASEL(r32,v)              _BFSET_(r32, 2, 2,v)
    #define   GET16PCIE_HWDBG_CTRL_DATASEL(r16)                _BFGET_(r16, 2, 2)
    #define   SET16PCIE_HWDBG_CTRL_DATASEL(r16,v)              _BFSET_(r16, 2, 2,v)

    #define   GET32PCIE_HWDBG_CTRL_SIGSEL(r32)                 _BFGET_(r32,10, 3)
    #define   SET32PCIE_HWDBG_CTRL_SIGSEL(r32,v)               _BFSET_(r32,10, 3,v)
    #define   GET16PCIE_HWDBG_CTRL_SIGSEL(r16)                 _BFGET_(r16,10, 3)
    #define   SET16PCIE_HWDBG_CTRL_SIGSEL(r16,v)               _BFSET_(r16,10, 3,v)

    #define     w32PCIE_HWDBG_CTRL                             {\
            UNSG32 uHWDBG_CTRL_PCIESEL                         :  2;\
            UNSG32 uHWDBG_CTRL_DATASEL                         :  1;\
            UNSG32 uHWDBG_CTRL_SIGSEL                          :  8;\
            UNSG32 RSVDxA020_b11                               : 21;\
          }
    union { UNSG32 u32PCIE_HWDBG_CTRL;
            struct w32PCIE_HWDBG_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_HWDBG_DATA_VAL(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PCIE_HWDBG_DATA_VAL(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32PCIE_HWDBG_DATA                             {\
            UNSG32 uHWDBG_DATA_VAL                             : 32;\
          }
    union { UNSG32 u32PCIE_HWDBG_DATA;
            struct w32PCIE_HWDBG_DATA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_SPARE_0_REGBITS(r32)                   _BFGET_(r32,31, 0)
    #define   SET32PCIE_SPARE_0_REGBITS(r32,v)                 _BFSET_(r32,31, 0,v)

    #define     w32PCIE_SPARE_0                                {\
            UNSG32 uSPARE_0_REGBITS                            : 32;\
          }
    union { UNSG32 u32PCIE_SPARE_0;
            struct w32PCIE_SPARE_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_SPARE_1_REGBITS(r32)                   _BFGET_(r32,31, 0)
    #define   SET32PCIE_SPARE_1_REGBITS(r32,v)                 _BFSET_(r32,31, 0,v)

    #define     w32PCIE_SPARE_1                                {\
            UNSG32 uSPARE_1_REGBITS                            : 32;\
          }
    union { UNSG32 u32PCIE_SPARE_1;
            struct w32PCIE_SPARE_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_SPARE_2_REGBITS(r32)                   _BFGET_(r32,31, 0)
    #define   SET32PCIE_SPARE_2_REGBITS(r32,v)                 _BFSET_(r32,31, 0,v)

    #define     w32PCIE_SPARE_2                                {\
            UNSG32 uSPARE_2_REGBITS                            : 32;\
          }
    union { UNSG32 u32PCIE_SPARE_2;
            struct w32PCIE_SPARE_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PCIE_SPARE_3_REGBITS(r32)                   _BFGET_(r32,31, 0)
    #define   SET32PCIE_SPARE_3_REGBITS(r32,v)                 _BFSET_(r32,31, 0,v)

    #define     w32PCIE_SPARE_3                                {\
            UNSG32 uSPARE_3_REGBITS                            : 32;\
          }
    union { UNSG32 u32PCIE_SPARE_3;
            struct w32PCIE_SPARE_3;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDxA038                                   [24520];
    ///////////////////////////////////////////////////////////
    } SIE_PCIE;

    typedef union  T32PCIE_MSI_INTR_RX
          { UNSG32 u32;
            struct w32PCIE_MSI_INTR_RX;
                 } T32PCIE_MSI_INTR_RX;
    typedef union  T32PCIE_MSI_INTR_STATUS
          { UNSG32 u32;
            struct w32PCIE_MSI_INTR_STATUS;
                 } T32PCIE_MSI_INTR_STATUS;
    typedef union  T32PCIE_MSI_INTR_MASK
          { UNSG32 u32;
            struct w32PCIE_MSI_INTR_MASK;
                 } T32PCIE_MSI_INTR_MASK;
    typedef union  T32PCIE_MAC_CTRL
          { UNSG32 u32;
            struct w32PCIE_MAC_CTRL;
                 } T32PCIE_MAC_CTRL;
    typedef union  T32PCIE_MAC_STATUS
          { UNSG32 u32;
            struct w32PCIE_MAC_STATUS;
                 } T32PCIE_MAC_STATUS;
    typedef union  T32PCIE_MAC_CLK_CTRL
          { UNSG32 u32;
            struct w32PCIE_MAC_CLK_CTRL;
                 } T32PCIE_MAC_CLK_CTRL;
    typedef union  T32PCIE_PHY_CTRL
          { UNSG32 u32;
            struct w32PCIE_PHY_CTRL;
                 } T32PCIE_PHY_CTRL;
    typedef union  T32PCIE_HWDBG_CTRL
          { UNSG32 u32;
            struct w32PCIE_HWDBG_CTRL;
                 } T32PCIE_HWDBG_CTRL;
    typedef union  T32PCIE_HWDBG_DATA
          { UNSG32 u32;
            struct w32PCIE_HWDBG_DATA;
                 } T32PCIE_HWDBG_DATA;
    typedef union  T32PCIE_SPARE_0
          { UNSG32 u32;
            struct w32PCIE_SPARE_0;
                 } T32PCIE_SPARE_0;
    typedef union  T32PCIE_SPARE_1
          { UNSG32 u32;
            struct w32PCIE_SPARE_1;
                 } T32PCIE_SPARE_1;
    typedef union  T32PCIE_SPARE_2
          { UNSG32 u32;
            struct w32PCIE_SPARE_2;
                 } T32PCIE_SPARE_2;
    typedef union  T32PCIE_SPARE_3
          { UNSG32 u32;
            struct w32PCIE_SPARE_3;
                 } T32PCIE_SPARE_3;
    ///////////////////////////////////////////////////////////

    typedef union  TPCIE_MSI_INTR_RX
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_MSI_INTR_RX;
                   };
                 } TPCIE_MSI_INTR_RX;
    typedef union  TPCIE_MSI_INTR_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_MSI_INTR_STATUS;
                   };
                 } TPCIE_MSI_INTR_STATUS;
    typedef union  TPCIE_MSI_INTR_MASK
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_MSI_INTR_MASK;
                   };
                 } TPCIE_MSI_INTR_MASK;
    typedef union  TPCIE_MAC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_MAC_CTRL;
                   };
                 } TPCIE_MAC_CTRL;
    typedef union  TPCIE_MAC_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_MAC_STATUS;
                   };
                 } TPCIE_MAC_STATUS;
    typedef union  TPCIE_MAC_CLK_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_MAC_CLK_CTRL;
                   };
                 } TPCIE_MAC_CLK_CTRL;
    typedef union  TPCIE_PHY_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_PHY_CTRL;
                   };
                 } TPCIE_PHY_CTRL;
    typedef union  TPCIE_HWDBG_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_HWDBG_CTRL;
                   };
                 } TPCIE_HWDBG_CTRL;
    typedef union  TPCIE_HWDBG_DATA
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_HWDBG_DATA;
                   };
                 } TPCIE_HWDBG_DATA;
    typedef union  TPCIE_SPARE_0
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_SPARE_0;
                   };
                 } TPCIE_SPARE_0;
    typedef union  TPCIE_SPARE_1
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_SPARE_1;
                   };
                 } TPCIE_SPARE_1;
    typedef union  TPCIE_SPARE_2
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_SPARE_2;
                   };
                 } TPCIE_SPARE_2;
    typedef union  TPCIE_SPARE_3
          { UNSG32 u32[1];
            struct {
            struct w32PCIE_SPARE_3;
                   };
                 } TPCIE_SPARE_3;

    ///////////////////////////////////////////////////////////
     SIGN32 PCIE_drvrd(SIE_PCIE *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 PCIE_drvwr(SIE_PCIE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void PCIE_reset(SIE_PCIE *p);
     SIGN32 PCIE_cmp  (SIE_PCIE *p, SIE_PCIE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define PCIE_check(p,pie,pfx,hLOG) PCIE_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define PCIE_print(p,    pfx,hLOG) PCIE_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: PCIE
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: pcie.h
////////////////////////////////////////////////////////////