/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//////
/// don't edit! auto-generated by docc: vcache_spec.h
////////////////////////////////////////////////////////////
#ifndef vcache_spec_h
#define vcache_spec_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE vcMsgMV                 biu              (4,4)
///     ###
///     * 8-bit vcMsg return data when ID = F0A64_vcMsgMv
///     * [0:7]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 3  mvX                       
///                                    ###
///                                    * Index of the 4x4 block @ upper-left corner of partition
///                                    ###
///               %unsigned 2  mvYL                      
///                                    ###
///                                    * Block / macroblock partition info
///                                    ###
///               %unsigned 3  mvYC                      
///                                    ###
///                                    * 0: partition is at macroblock level
///                                    * 1: partition is at 8x8 block level
///                                    ###
///               %unsigned 3  mv1X                      
///               %unsigned 2  mv1YL                     
///               %unsigned 3  mv1YC                     
///               %unsigned 3  mv2X                      
///               %unsigned 2  mv2YL                     
///               %unsigned 3  mv2YC                     
///               %unsigned 3  mv3X                      
///               %unsigned 2  mv3YL                     
///               %unsigned 3  mv3YC                     
///                                    ###
///                                    * End vcMsgMV
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vcMsgMV
#define h_vcMsgMV (){}

    #define     BA_vcMsgMV_mvX                                 0x0000
    #define     B16vcMsgMV_mvX                                 0x0000
    #define   LSb32vcMsgMV_mvX                                    0
    #define   LSb16vcMsgMV_mvX                                    0
    #define       bvcMsgMV_mvX                                 3
    #define   MSK32vcMsgMV_mvX                                    0x00000007

    #define     BA_vcMsgMV_mvYL                                0x0000
    #define     B16vcMsgMV_mvYL                                0x0000
    #define   LSb32vcMsgMV_mvYL                                   3
    #define   LSb16vcMsgMV_mvYL                                   3
    #define       bvcMsgMV_mvYL                                2
    #define   MSK32vcMsgMV_mvYL                                   0x00000018

    #define     BA_vcMsgMV_mvYC                                0x0000
    #define     B16vcMsgMV_mvYC                                0x0000
    #define   LSb32vcMsgMV_mvYC                                   5
    #define   LSb16vcMsgMV_mvYC                                   5
    #define       bvcMsgMV_mvYC                                3
    #define   MSK32vcMsgMV_mvYC                                   0x000000E0

    #define     BA_vcMsgMV_mv1X                                0x0001
    #define     B16vcMsgMV_mv1X                                0x0000
    #define   LSb32vcMsgMV_mv1X                                   8
    #define   LSb16vcMsgMV_mv1X                                   8
    #define       bvcMsgMV_mv1X                                3
    #define   MSK32vcMsgMV_mv1X                                   0x00000700

    #define     BA_vcMsgMV_mv1YL                               0x0001
    #define     B16vcMsgMV_mv1YL                               0x0000
    #define   LSb32vcMsgMV_mv1YL                                  11
    #define   LSb16vcMsgMV_mv1YL                                  11
    #define       bvcMsgMV_mv1YL                               2
    #define   MSK32vcMsgMV_mv1YL                                  0x00001800

    #define     BA_vcMsgMV_mv1YC                               0x0001
    #define     B16vcMsgMV_mv1YC                               0x0000
    #define   LSb32vcMsgMV_mv1YC                                  13
    #define   LSb16vcMsgMV_mv1YC                                  13
    #define       bvcMsgMV_mv1YC                               3
    #define   MSK32vcMsgMV_mv1YC                                  0x0000E000

    #define     BA_vcMsgMV_mv2X                                0x0002
    #define     B16vcMsgMV_mv2X                                0x0002
    #define   LSb32vcMsgMV_mv2X                                   16
    #define   LSb16vcMsgMV_mv2X                                   0
    #define       bvcMsgMV_mv2X                                3
    #define   MSK32vcMsgMV_mv2X                                   0x00070000

    #define     BA_vcMsgMV_mv2YL                               0x0002
    #define     B16vcMsgMV_mv2YL                               0x0002
    #define   LSb32vcMsgMV_mv2YL                                  19
    #define   LSb16vcMsgMV_mv2YL                                  3
    #define       bvcMsgMV_mv2YL                               2
    #define   MSK32vcMsgMV_mv2YL                                  0x00180000

    #define     BA_vcMsgMV_mv2YC                               0x0002
    #define     B16vcMsgMV_mv2YC                               0x0002
    #define   LSb32vcMsgMV_mv2YC                                  21
    #define   LSb16vcMsgMV_mv2YC                                  5
    #define       bvcMsgMV_mv2YC                               3
    #define   MSK32vcMsgMV_mv2YC                                  0x00E00000

    #define     BA_vcMsgMV_mv3X                                0x0003
    #define     B16vcMsgMV_mv3X                                0x0002
    #define   LSb32vcMsgMV_mv3X                                   24
    #define   LSb16vcMsgMV_mv3X                                   8
    #define       bvcMsgMV_mv3X                                3
    #define   MSK32vcMsgMV_mv3X                                   0x07000000

    #define     BA_vcMsgMV_mv3YL                               0x0003
    #define     B16vcMsgMV_mv3YL                               0x0002
    #define   LSb32vcMsgMV_mv3YL                                  27
    #define   LSb16vcMsgMV_mv3YL                                  11
    #define       bvcMsgMV_mv3YL                               2
    #define   MSK32vcMsgMV_mv3YL                                  0x18000000

    #define     BA_vcMsgMV_mv3YC                               0x0003
    #define     B16vcMsgMV_mv3YC                               0x0002
    #define   LSb32vcMsgMV_mv3YC                                  29
    #define   LSb16vcMsgMV_mv3YC                                  13
    #define       bvcMsgMV_mv3YC                               3
    #define   MSK32vcMsgMV_mv3YC                                  0xE0000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vcMsgMV {
    ///////////////////////////////////////////////////////////
    #define   GET32vcMsgMV_mvX(r32)                            _BFGET_(r32, 2, 0)
    #define   SET32vcMsgMV_mvX(r32,v)                          _BFSET_(r32, 2, 0,v)
    #define   GET16vcMsgMV_mvX(r16)                            _BFGET_(r16, 2, 0)
    #define   SET16vcMsgMV_mvX(r16,v)                          _BFSET_(r16, 2, 0,v)

    #define   GET32vcMsgMV_mvYL(r32)                           _BFGET_(r32, 4, 3)
    #define   SET32vcMsgMV_mvYL(r32,v)                         _BFSET_(r32, 4, 3,v)
    #define   GET16vcMsgMV_mvYL(r16)                           _BFGET_(r16, 4, 3)
    #define   SET16vcMsgMV_mvYL(r16,v)                         _BFSET_(r16, 4, 3,v)

    #define   GET32vcMsgMV_mvYC(r32)                           _BFGET_(r32, 7, 5)
    #define   SET32vcMsgMV_mvYC(r32,v)                         _BFSET_(r32, 7, 5,v)
    #define   GET16vcMsgMV_mvYC(r16)                           _BFGET_(r16, 7, 5)
    #define   SET16vcMsgMV_mvYC(r16,v)                         _BFSET_(r16, 7, 5,v)

    #define   GET32vcMsgMV_mv1X(r32)                           _BFGET_(r32,10, 8)
    #define   SET32vcMsgMV_mv1X(r32,v)                         _BFSET_(r32,10, 8,v)
    #define   GET16vcMsgMV_mv1X(r16)                           _BFGET_(r16,10, 8)
    #define   SET16vcMsgMV_mv1X(r16,v)                         _BFSET_(r16,10, 8,v)

    #define   GET32vcMsgMV_mv1YL(r32)                          _BFGET_(r32,12,11)
    #define   SET32vcMsgMV_mv1YL(r32,v)                        _BFSET_(r32,12,11,v)
    #define   GET16vcMsgMV_mv1YL(r16)                          _BFGET_(r16,12,11)
    #define   SET16vcMsgMV_mv1YL(r16,v)                        _BFSET_(r16,12,11,v)

    #define   GET32vcMsgMV_mv1YC(r32)                          _BFGET_(r32,15,13)
    #define   SET32vcMsgMV_mv1YC(r32,v)                        _BFSET_(r32,15,13,v)
    #define   GET16vcMsgMV_mv1YC(r16)                          _BFGET_(r16,15,13)
    #define   SET16vcMsgMV_mv1YC(r16,v)                        _BFSET_(r16,15,13,v)

    #define   GET32vcMsgMV_mv2X(r32)                           _BFGET_(r32,18,16)
    #define   SET32vcMsgMV_mv2X(r32,v)                         _BFSET_(r32,18,16,v)
    #define   GET16vcMsgMV_mv2X(r16)                           _BFGET_(r16, 2, 0)
    #define   SET16vcMsgMV_mv2X(r16,v)                         _BFSET_(r16, 2, 0,v)

    #define   GET32vcMsgMV_mv2YL(r32)                          _BFGET_(r32,20,19)
    #define   SET32vcMsgMV_mv2YL(r32,v)                        _BFSET_(r32,20,19,v)
    #define   GET16vcMsgMV_mv2YL(r16)                          _BFGET_(r16, 4, 3)
    #define   SET16vcMsgMV_mv2YL(r16,v)                        _BFSET_(r16, 4, 3,v)

    #define   GET32vcMsgMV_mv2YC(r32)                          _BFGET_(r32,23,21)
    #define   SET32vcMsgMV_mv2YC(r32,v)                        _BFSET_(r32,23,21,v)
    #define   GET16vcMsgMV_mv2YC(r16)                          _BFGET_(r16, 7, 5)
    #define   SET16vcMsgMV_mv2YC(r16,v)                        _BFSET_(r16, 7, 5,v)

    #define   GET32vcMsgMV_mv3X(r32)                           _BFGET_(r32,26,24)
    #define   SET32vcMsgMV_mv3X(r32,v)                         _BFSET_(r32,26,24,v)
    #define   GET16vcMsgMV_mv3X(r16)                           _BFGET_(r16,10, 8)
    #define   SET16vcMsgMV_mv3X(r16,v)                         _BFSET_(r16,10, 8,v)

    #define   GET32vcMsgMV_mv3YL(r32)                          _BFGET_(r32,28,27)
    #define   SET32vcMsgMV_mv3YL(r32,v)                        _BFSET_(r32,28,27,v)
    #define   GET16vcMsgMV_mv3YL(r16)                          _BFGET_(r16,12,11)
    #define   SET16vcMsgMV_mv3YL(r16,v)                        _BFSET_(r16,12,11,v)

    #define   GET32vcMsgMV_mv3YC(r32)                          _BFGET_(r32,31,29)
    #define   SET32vcMsgMV_mv3YC(r32,v)                        _BFSET_(r32,31,29,v)
    #define   GET16vcMsgMV_mv3YC(r16)                          _BFGET_(r16,15,13)
    #define   SET16vcMsgMV_mv3YC(r16,v)                        _BFSET_(r16,15,13,v)

            UNSG32 u_mvX                                       :  3;
            UNSG32 u_mvYL                                      :  2;
            UNSG32 u_mvYC                                      :  3;
            UNSG32 u_mv1X                                      :  3;
            UNSG32 u_mv1YL                                     :  2;
            UNSG32 u_mv1YC                                     :  3;
            UNSG32 u_mv2X                                      :  3;
            UNSG32 u_mv2YL                                     :  2;
            UNSG32 u_mv2YC                                     :  3;
            UNSG32 u_mv3X                                      :  3;
            UNSG32 u_mv3YL                                     :  2;
            UNSG32 u_mv3YC                                     :  3;
    ///////////////////////////////////////////////////////////
    } SIE_vcMsgMV;

    ///////////////////////////////////////////////////////////
     SIGN32 vcMsgMV_drvrd(SIE_vcMsgMV *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vcMsgMV_drvwr(SIE_vcMsgMV *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vcMsgMV_reset(SIE_vcMsgMV *p);
     SIGN32 vcMsgMV_cmp  (SIE_vcMsgMV *p, SIE_vcMsgMV *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vcMsgMV_check(p,pie,pfx,hLOG) vcMsgMV_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vcMsgMV_print(p,    pfx,hLOG) vcMsgMV_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vcMsgMV
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE vcMsgCMD                biu              (4,4)
///     ###
///     * 16-bit vcMsg command parameter
///     * [0:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 4  BLK                       
///                                    ###
///                                    * Index of the 4x4 block @ upper-left corner of partition
///                                    ###
///               %unsigned 2  partition                 
///                                    : 1mv                       0x0
///                                    : 2mvLR                     0x1
///                                    : 2mvTB                     0x2
///                                    : 4mv                       0x3
///                                                 ###
///                                                 * Block / macroblock partition info
///                                                 ###
///               %unsigned 1  level                     
///                                    : mb                        0x0
///                                    : blk8x8                    0x1
///                                                 ###
///                                                 * 0: partition is at macroblock level
///                                                 * 1: partition is at 8x8 block level
///                                                 ###
///               %unsigned 1  RSVD                      0x1
///                                    ###
///                                    * To ensure same defines as in Nloc.category
///                                    * End vcMsgCMD
///                                    ###
///               %%        24         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       8b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vcMsgCMD
#define h_vcMsgCMD (){}

    #define     BA_vcMsgCMD_BLK                                0x0000
    #define     B16vcMsgCMD_BLK                                0x0000
    #define   LSb32vcMsgCMD_BLK                                   0
    #define   LSb16vcMsgCMD_BLK                                   0
    #define       bvcMsgCMD_BLK                                4
    #define   MSK32vcMsgCMD_BLK                                   0x0000000F

    #define     BA_vcMsgCMD_partition                          0x0000
    #define     B16vcMsgCMD_partition                          0x0000
    #define   LSb32vcMsgCMD_partition                             4
    #define   LSb16vcMsgCMD_partition                             4
    #define       bvcMsgCMD_partition                          2
    #define   MSK32vcMsgCMD_partition                             0x00000030
    #define        vcMsgCMD_partition_1mv                                   0x0
    #define        vcMsgCMD_partition_2mvLR                                 0x1
    #define        vcMsgCMD_partition_2mvTB                                 0x2
    #define        vcMsgCMD_partition_4mv                                   0x3

    #define     BA_vcMsgCMD_level                              0x0000
    #define     B16vcMsgCMD_level                              0x0000
    #define   LSb32vcMsgCMD_level                                 6
    #define   LSb16vcMsgCMD_level                                 6
    #define       bvcMsgCMD_level                              1
    #define   MSK32vcMsgCMD_level                                 0x00000040
    #define        vcMsgCMD_level_mb                                        0x0
    #define        vcMsgCMD_level_blk8x8                                    0x1

    #define     BA_vcMsgCMD_RSVD                               0x0000
    #define     B16vcMsgCMD_RSVD                               0x0000
    #define   LSb32vcMsgCMD_RSVD                                  7
    #define   LSb16vcMsgCMD_RSVD                                  7
    #define       bvcMsgCMD_RSVD                               1
    #define   MSK32vcMsgCMD_RSVD                                  0x00000080
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vcMsgCMD {
    ///////////////////////////////////////////////////////////
    #define   GET32vcMsgCMD_BLK(r32)                           _BFGET_(r32, 3, 0)
    #define   SET32vcMsgCMD_BLK(r32,v)                         _BFSET_(r32, 3, 0,v)
    #define   GET16vcMsgCMD_BLK(r16)                           _BFGET_(r16, 3, 0)
    #define   SET16vcMsgCMD_BLK(r16,v)                         _BFSET_(r16, 3, 0,v)

    #define   GET32vcMsgCMD_partition(r32)                     _BFGET_(r32, 5, 4)
    #define   SET32vcMsgCMD_partition(r32,v)                   _BFSET_(r32, 5, 4,v)
    #define   GET16vcMsgCMD_partition(r16)                     _BFGET_(r16, 5, 4)
    #define   SET16vcMsgCMD_partition(r16,v)                   _BFSET_(r16, 5, 4,v)

    #define   GET32vcMsgCMD_level(r32)                         _BFGET_(r32, 6, 6)
    #define   SET32vcMsgCMD_level(r32,v)                       _BFSET_(r32, 6, 6,v)
    #define   GET16vcMsgCMD_level(r16)                         _BFGET_(r16, 6, 6)
    #define   SET16vcMsgCMD_level(r16,v)                       _BFSET_(r16, 6, 6,v)

    #define   GET32vcMsgCMD_RSVD(r32)                          _BFGET_(r32, 7, 7)
    #define   SET32vcMsgCMD_RSVD(r32,v)                        _BFSET_(r32, 7, 7,v)
    #define   GET16vcMsgCMD_RSVD(r16)                          _BFGET_(r16, 7, 7)
    #define   SET16vcMsgCMD_RSVD(r16,v)                        _BFSET_(r16, 7, 7,v)

            UNSG32 u_BLK                                       :  4;
            UNSG32 u_partition                                 :  2;
            UNSG32 u_level                                     :  1;
            UNSG32 u_RSVD                                      :  1;
            UNSG32 RSVDx0_b8                                   : 24;
    ///////////////////////////////////////////////////////////
    } SIE_vcMsgCMD;

    ///////////////////////////////////////////////////////////
     SIGN32 vcMsgCMD_drvrd(SIE_vcMsgCMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vcMsgCMD_drvwr(SIE_vcMsgCMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vcMsgCMD_reset(SIE_vcMsgCMD *p);
     SIGN32 vcMsgCMD_cmp  (SIE_vcMsgCMD *p, SIE_vcMsgCMD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vcMsgCMD_check(p,pie,pfx,hLOG) vcMsgCMD_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vcMsgCMD_print(p,    pfx,hLOG) vcMsgCMD_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vcMsgCMD
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE CacheMSG                                 (4,4)
///     ###
///     * Message to setup vCache prefetching.
///     * [00:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 11 xLoc                      
///                                    ###
///                                    * Exact reference region horizontal location (in pixel)
///                                    ###
///               %unsigned 5  xPix                      
///                                    ###
///                                    * Exact reference region horizontal size (in pixel)
///                                    * 0 represents 32
///                                    ###
///               %unsigned 11 yLoc                      
///                                    ###
///                                    * Exact reference region vertical location (in pixel)
///                                    ###
///               %unsigned 5  yPix                      
///                                    ###
///                                    * Exact reference region vertical size (in pixel)
///                                    * 0 represents 32
///                                    * [32:63]
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 5  xLocExp                   
///                                    ###
///                                    * Expansion horizontal offset (in pixel)
///                                    ###
///               %unsigned 3  xPixExp                   
///                                    ###
///                                    * Expansion horizontal size (in 4-pixel unit)
///                                    * 0 represents 8
///                                    ###
///               %unsigned 5  yLocExp                   
///                                    ###
///                                    * Expansion vertical offset (in pixel)
///                                    ###
///               %unsigned 3  yPixExp                   
///                                    ###
///                                    * Expansion vertical size (in 4-pixel unit)0 represents 8
///                                    ###
///               %unsigned 6  rBID                      
///                                    ###
///                                    * Reference buffer ID, last 1b indicates access mode:
///                                    * 0: frame/progressive or top field
///                                    * 1: bottom field
///                                    ###
///               %unsigned 1  uv                        
///                                    ###
///                                    * 0/1 for Y or UV reference region
///                                    ###
///               %unsigned 1  fldMB                     
///                                    ###
///                                    * 0/1 for frame or field MB(-pair)
///                                    ###
///               %unsigned 2  hint                      
///                                    : bypass                    0x0
///                                                 ###
///                                                 * Force to bypass cache
///                                                 ###
///                                    : FrmX                      0x1
///                                                 ###
///                                                 * Use FID & xLoc to decide cache way
///                                                 ###
///                                    : FrmY                      0x2
///                                                 ###
///                                                 * Use FID & yLoc to decide cache way
///                                                 ###
///                                    : XY                        0x3
///                                                 ###
///                                                 * Use xLoc & yLoc to decide cache way
///                                                 ###
///               %unsigned 6  descID                    
///                                    ###
///                                    * Output transfer descriptor ID
///                                    * A descriptor shall have a (non-zero) semaphore ID to check not full before transfer, destination address and stride (in 4x4)
///                                    ###
///                                    : CFG                      0x3F
///                                                 ###
///                                                 * vCache configuration message
///                                                 * End of CacheMSG
///                                                 ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CacheMSG
#define h_CacheMSG (){}

    #define     BA_CacheMSG_xLoc                               0x0000
    #define     B16CacheMSG_xLoc                               0x0000
    #define   LSb32CacheMSG_xLoc                                  0
    #define   LSb16CacheMSG_xLoc                                  0
    #define       bCacheMSG_xLoc                               11
    #define   MSK32CacheMSG_xLoc                                  0x000007FF

    #define     BA_CacheMSG_xPix                               0x0001
    #define     B16CacheMSG_xPix                               0x0000
    #define   LSb32CacheMSG_xPix                                  11
    #define   LSb16CacheMSG_xPix                                  11
    #define       bCacheMSG_xPix                               5
    #define   MSK32CacheMSG_xPix                                  0x0000F800

    #define     BA_CacheMSG_yLoc                               0x0002
    #define     B16CacheMSG_yLoc                               0x0002
    #define   LSb32CacheMSG_yLoc                                  16
    #define   LSb16CacheMSG_yLoc                                  0
    #define       bCacheMSG_yLoc                               11
    #define   MSK32CacheMSG_yLoc                                  0x07FF0000

    #define     BA_CacheMSG_yPix                               0x0003
    #define     B16CacheMSG_yPix                               0x0002
    #define   LSb32CacheMSG_yPix                                  27
    #define   LSb16CacheMSG_yPix                                  11
    #define       bCacheMSG_yPix                               5
    #define   MSK32CacheMSG_yPix                                  0xF8000000
    ///////////////////////////////////////////////////////////

    #define     BA_CacheMSG_xLocExp                            0x0004
    #define     B16CacheMSG_xLocExp                            0x0004
    #define   LSb32CacheMSG_xLocExp                               0
    #define   LSb16CacheMSG_xLocExp                               0
    #define       bCacheMSG_xLocExp                            5
    #define   MSK32CacheMSG_xLocExp                               0x0000001F

    #define     BA_CacheMSG_xPixExp                            0x0004
    #define     B16CacheMSG_xPixExp                            0x0004
    #define   LSb32CacheMSG_xPixExp                               5
    #define   LSb16CacheMSG_xPixExp                               5
    #define       bCacheMSG_xPixExp                            3
    #define   MSK32CacheMSG_xPixExp                               0x000000E0

    #define     BA_CacheMSG_yLocExp                            0x0005
    #define     B16CacheMSG_yLocExp                            0x0004
    #define   LSb32CacheMSG_yLocExp                               8
    #define   LSb16CacheMSG_yLocExp                               8
    #define       bCacheMSG_yLocExp                            5
    #define   MSK32CacheMSG_yLocExp                               0x00001F00

    #define     BA_CacheMSG_yPixExp                            0x0005
    #define     B16CacheMSG_yPixExp                            0x0004
    #define   LSb32CacheMSG_yPixExp                               13
    #define   LSb16CacheMSG_yPixExp                               13
    #define       bCacheMSG_yPixExp                            3
    #define   MSK32CacheMSG_yPixExp                               0x0000E000

    #define     BA_CacheMSG_rBID                               0x0006
    #define     B16CacheMSG_rBID                               0x0006
    #define   LSb32CacheMSG_rBID                                  16
    #define   LSb16CacheMSG_rBID                                  0
    #define       bCacheMSG_rBID                               6
    #define   MSK32CacheMSG_rBID                                  0x003F0000

    #define     BA_CacheMSG_uv                                 0x0006
    #define     B16CacheMSG_uv                                 0x0006
    #define   LSb32CacheMSG_uv                                    22
    #define   LSb16CacheMSG_uv                                    6
    #define       bCacheMSG_uv                                 1
    #define   MSK32CacheMSG_uv                                    0x00400000

    #define     BA_CacheMSG_fldMB                              0x0006
    #define     B16CacheMSG_fldMB                              0x0006
    #define   LSb32CacheMSG_fldMB                                 23
    #define   LSb16CacheMSG_fldMB                                 7
    #define       bCacheMSG_fldMB                              1
    #define   MSK32CacheMSG_fldMB                                 0x00800000

    #define     BA_CacheMSG_hint                               0x0007
    #define     B16CacheMSG_hint                               0x0006
    #define   LSb32CacheMSG_hint                                  24
    #define   LSb16CacheMSG_hint                                  8
    #define       bCacheMSG_hint                               2
    #define   MSK32CacheMSG_hint                                  0x03000000
    #define        CacheMSG_hint_bypass                                     0x0
    #define        CacheMSG_hint_FrmX                                       0x1
    #define        CacheMSG_hint_FrmY                                       0x2
    #define        CacheMSG_hint_XY                                         0x3

    #define     BA_CacheMSG_descID                             0x0007
    #define     B16CacheMSG_descID                             0x0006
    #define   LSb32CacheMSG_descID                                26
    #define   LSb16CacheMSG_descID                                10
    #define       bCacheMSG_descID                             6
    #define   MSK32CacheMSG_descID                                0xFC000000
    #define        CacheMSG_descID_CFG                                      0x3F
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CacheMSG {
    ///////////////////////////////////////////////////////////
    #define   GET32CacheMSG_xLoc(r32)                          _BFGET_(r32,10, 0)
    #define   SET32CacheMSG_xLoc(r32,v)                        _BFSET_(r32,10, 0,v)
    #define   GET16CacheMSG_xLoc(r16)                          _BFGET_(r16,10, 0)
    #define   SET16CacheMSG_xLoc(r16,v)                        _BFSET_(r16,10, 0,v)

    #define   GET32CacheMSG_xPix(r32)                          _BFGET_(r32,15,11)
    #define   SET32CacheMSG_xPix(r32,v)                        _BFSET_(r32,15,11,v)
    #define   GET16CacheMSG_xPix(r16)                          _BFGET_(r16,15,11)
    #define   SET16CacheMSG_xPix(r16,v)                        _BFSET_(r16,15,11,v)

    #define   GET32CacheMSG_yLoc(r32)                          _BFGET_(r32,26,16)
    #define   SET32CacheMSG_yLoc(r32,v)                        _BFSET_(r32,26,16,v)
    #define   GET16CacheMSG_yLoc(r16)                          _BFGET_(r16,10, 0)
    #define   SET16CacheMSG_yLoc(r16,v)                        _BFSET_(r16,10, 0,v)

    #define   GET32CacheMSG_yPix(r32)                          _BFGET_(r32,31,27)
    #define   SET32CacheMSG_yPix(r32,v)                        _BFSET_(r32,31,27,v)
    #define   GET16CacheMSG_yPix(r16)                          _BFGET_(r16,15,11)
    #define   SET16CacheMSG_yPix(r16,v)                        _BFSET_(r16,15,11,v)

            UNSG32 u_xLoc                                      : 11;
            UNSG32 u_xPix                                      :  5;
            UNSG32 u_yLoc                                      : 11;
            UNSG32 u_yPix                                      :  5;
    ///////////////////////////////////////////////////////////
    #define   GET32CacheMSG_xLocExp(r32)                       _BFGET_(r32, 4, 0)
    #define   SET32CacheMSG_xLocExp(r32,v)                     _BFSET_(r32, 4, 0,v)
    #define   GET16CacheMSG_xLocExp(r16)                       _BFGET_(r16, 4, 0)
    #define   SET16CacheMSG_xLocExp(r16,v)                     _BFSET_(r16, 4, 0,v)

    #define   GET32CacheMSG_xPixExp(r32)                       _BFGET_(r32, 7, 5)
    #define   SET32CacheMSG_xPixExp(r32,v)                     _BFSET_(r32, 7, 5,v)
    #define   GET16CacheMSG_xPixExp(r16)                       _BFGET_(r16, 7, 5)
    #define   SET16CacheMSG_xPixExp(r16,v)                     _BFSET_(r16, 7, 5,v)

    #define   GET32CacheMSG_yLocExp(r32)                       _BFGET_(r32,12, 8)
    #define   SET32CacheMSG_yLocExp(r32,v)                     _BFSET_(r32,12, 8,v)
    #define   GET16CacheMSG_yLocExp(r16)                       _BFGET_(r16,12, 8)
    #define   SET16CacheMSG_yLocExp(r16,v)                     _BFSET_(r16,12, 8,v)

    #define   GET32CacheMSG_yPixExp(r32)                       _BFGET_(r32,15,13)
    #define   SET32CacheMSG_yPixExp(r32,v)                     _BFSET_(r32,15,13,v)
    #define   GET16CacheMSG_yPixExp(r16)                       _BFGET_(r16,15,13)
    #define   SET16CacheMSG_yPixExp(r16,v)                     _BFSET_(r16,15,13,v)

    #define   GET32CacheMSG_rBID(r32)                          _BFGET_(r32,21,16)
    #define   SET32CacheMSG_rBID(r32,v)                        _BFSET_(r32,21,16,v)
    #define   GET16CacheMSG_rBID(r16)                          _BFGET_(r16, 5, 0)
    #define   SET16CacheMSG_rBID(r16,v)                        _BFSET_(r16, 5, 0,v)

    #define   GET32CacheMSG_uv(r32)                            _BFGET_(r32,22,22)
    #define   SET32CacheMSG_uv(r32,v)                          _BFSET_(r32,22,22,v)
    #define   GET16CacheMSG_uv(r16)                            _BFGET_(r16, 6, 6)
    #define   SET16CacheMSG_uv(r16,v)                          _BFSET_(r16, 6, 6,v)

    #define   GET32CacheMSG_fldMB(r32)                         _BFGET_(r32,23,23)
    #define   SET32CacheMSG_fldMB(r32,v)                       _BFSET_(r32,23,23,v)
    #define   GET16CacheMSG_fldMB(r16)                         _BFGET_(r16, 7, 7)
    #define   SET16CacheMSG_fldMB(r16,v)                       _BFSET_(r16, 7, 7,v)

    #define   GET32CacheMSG_hint(r32)                          _BFGET_(r32,25,24)
    #define   SET32CacheMSG_hint(r32,v)                        _BFSET_(r32,25,24,v)
    #define   GET16CacheMSG_hint(r16)                          _BFGET_(r16, 9, 8)
    #define   SET16CacheMSG_hint(r16,v)                        _BFSET_(r16, 9, 8,v)

    #define   GET32CacheMSG_descID(r32)                        _BFGET_(r32,31,26)
    #define   SET32CacheMSG_descID(r32,v)                      _BFSET_(r32,31,26,v)
    #define   GET16CacheMSG_descID(r16)                        _BFGET_(r16,15,10)
    #define   SET16CacheMSG_descID(r16,v)                      _BFSET_(r16,15,10,v)

            UNSG32 u_xLocExp                                   :  5;
            UNSG32 u_xPixExp                                   :  3;
            UNSG32 u_yLocExp                                   :  5;
            UNSG32 u_yPixExp                                   :  3;
            UNSG32 u_rBID                                      :  6;
            UNSG32 u_uv                                        :  1;
            UNSG32 u_fldMB                                     :  1;
            UNSG32 u_hint                                      :  2;
            UNSG32 u_descID                                    :  6;
    ///////////////////////////////////////////////////////////
    } SIE_CacheMSG;

    ///////////////////////////////////////////////////////////
     SIGN32 CacheMSG_drvrd(SIE_CacheMSG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CacheMSG_drvwr(SIE_CacheMSG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CacheMSG_reset(SIE_CacheMSG *p);
     SIGN32 CacheMSG_cmp  (SIE_CacheMSG *p, SIE_CacheMSG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CacheMSG_check(p,pie,pfx,hLOG) CacheMSG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CacheMSG_print(p,    pfx,hLOG) CacheMSG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CacheMSG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE dirMvScale              biu              (4,4)
///     ###
///     * Scaling factors for temporal direct MV calculation
///     * [0:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %signed   12 factor                    
///                                    ###
///                                    * = clip(-1024, 1023, (tb*tx+32)>>6)
///                                    ###
///               %unsigned 20 RSVD20                    
///                                    ###
///                                    * pad to 32 bits
///                                    * [32:63]
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 32 RSVD32                    
///                                    ###
///                                    * pad to 64 bits
///                                    * End dirMvScale
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_dirMvScale
#define h_dirMvScale (){}

    #define     BA_dirMvScale_factor                           0x0000
    #define     B16dirMvScale_factor                           0x0000
    #define   LSb32dirMvScale_factor                              0
    #define   LSb16dirMvScale_factor                              0
    #define       bdirMvScale_factor                           12
    #define   MSK32dirMvScale_factor                              0x00000FFF

    #define     BA_dirMvScale_RSVD20                           0x0001
    #define     B16dirMvScale_RSVD20                           0x0000
    #define   LSb32dirMvScale_RSVD20                              12
    #define   LSb16dirMvScale_RSVD20                              12
    #define       bdirMvScale_RSVD20                           20
    #define   MSK32dirMvScale_RSVD20                              0xFFFFF000
    ///////////////////////////////////////////////////////////

    #define     BA_dirMvScale_RSVD32                           0x0004
    #define     B16dirMvScale_RSVD32                           0x0004
    #define   LSb32dirMvScale_RSVD32                              0
    #define   LSb16dirMvScale_RSVD32                              0
    #define       bdirMvScale_RSVD32                           32
    #define   MSK32dirMvScale_RSVD32                              0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_dirMvScale {
    ///////////////////////////////////////////////////////////
    #define   GET32dirMvScale_factor(r32)                      _BFGET_(r32,11, 0)
    #define   SET32dirMvScale_factor(r32,v)                    _BFSET_(r32,11, 0,v)
    #define   GET16dirMvScale_factor(r16)                      _BFGET_(r16,11, 0)
    #define   SET16dirMvScale_factor(r16,v)                    _BFSET_(r16,11, 0,v)

    #define   GET32dirMvScale_RSVD20(r32)                      _BFGET_(r32,31,12)
    #define   SET32dirMvScale_RSVD20(r32,v)                    _BFSET_(r32,31,12,v)

            UNSG32 s_factor                                    : 12;
            UNSG32 u_RSVD20                                    : 20;
    ///////////////////////////////////////////////////////////
    #define   GET32dirMvScale_RSVD32(r32)                      _BFGET_(r32,31, 0)
    #define   SET32dirMvScale_RSVD32(r32,v)                    _BFSET_(r32,31, 0,v)

            UNSG32 u_RSVD32                                    : 32;
    ///////////////////////////////////////////////////////////
    } SIE_dirMvScale;

    ///////////////////////////////////////////////////////////
     SIGN32 dirMvScale_drvrd(SIE_dirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 dirMvScale_drvwr(SIE_dirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void dirMvScale_reset(SIE_dirMvScale *p);
     SIGN32 dirMvScale_cmp  (SIE_dirMvScale *p, SIE_dirMvScale *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define dirMvScale_check(p,pie,pfx,hLOG) dirMvScale_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define dirMvScale_print(p,    pfx,hLOG) dirMvScale_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: dirMvScale
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE avsDirMvScale           biu              (4,4)
///     ###
///     * Scaling factors for temporal direct MV calculation for AVS
///     * [0:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 16 BlockDistanceFw           
///                                    ###
///                                    * Block Distance between current block and forward reference block.
///                                    ###
///               %unsigned 16 BlockDistanceBw           
///                                    ###
///                                    * Block Distance between backward reference block and current block.
///                                    * [32:63]
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 16 invBlockDistanceRef       
///                                    ###
///                                    * 16384/BlockDistanceRef, where BlockDistanceRef is the block distance between backward reference block and reference block of the co-located block.
///                                    ###
///               %unsigned 16 RSVD16                    
///                                    ###
///                                    * pad to 64 bits
///                                    * End avsDirMvScale
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_avsDirMvScale
#define h_avsDirMvScale (){}

    #define     BA_avsDirMvScale_BlockDistanceFw               0x0000
    #define     B16avsDirMvScale_BlockDistanceFw               0x0000
    #define   LSb32avsDirMvScale_BlockDistanceFw                  0
    #define   LSb16avsDirMvScale_BlockDistanceFw                  0
    #define       bavsDirMvScale_BlockDistanceFw               16
    #define   MSK32avsDirMvScale_BlockDistanceFw                  0x0000FFFF

    #define     BA_avsDirMvScale_BlockDistanceBw               0x0002
    #define     B16avsDirMvScale_BlockDistanceBw               0x0002
    #define   LSb32avsDirMvScale_BlockDistanceBw                  16
    #define   LSb16avsDirMvScale_BlockDistanceBw                  0
    #define       bavsDirMvScale_BlockDistanceBw               16
    #define   MSK32avsDirMvScale_BlockDistanceBw                  0xFFFF0000
    ///////////////////////////////////////////////////////////

    #define     BA_avsDirMvScale_invBlockDistanceRef           0x0004
    #define     B16avsDirMvScale_invBlockDistanceRef           0x0004
    #define   LSb32avsDirMvScale_invBlockDistanceRef              0
    #define   LSb16avsDirMvScale_invBlockDistanceRef              0
    #define       bavsDirMvScale_invBlockDistanceRef           16
    #define   MSK32avsDirMvScale_invBlockDistanceRef              0x0000FFFF

    #define     BA_avsDirMvScale_RSVD16                        0x0006
    #define     B16avsDirMvScale_RSVD16                        0x0006
    #define   LSb32avsDirMvScale_RSVD16                           16
    #define   LSb16avsDirMvScale_RSVD16                           0
    #define       bavsDirMvScale_RSVD16                        16
    #define   MSK32avsDirMvScale_RSVD16                           0xFFFF0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_avsDirMvScale {
    ///////////////////////////////////////////////////////////
    #define   GET32avsDirMvScale_BlockDistanceFw(r32)          _BFGET_(r32,15, 0)
    #define   SET32avsDirMvScale_BlockDistanceFw(r32,v)        _BFSET_(r32,15, 0,v)
    #define   GET16avsDirMvScale_BlockDistanceFw(r16)          _BFGET_(r16,15, 0)
    #define   SET16avsDirMvScale_BlockDistanceFw(r16,v)        _BFSET_(r16,15, 0,v)

    #define   GET32avsDirMvScale_BlockDistanceBw(r32)          _BFGET_(r32,31,16)
    #define   SET32avsDirMvScale_BlockDistanceBw(r32,v)        _BFSET_(r32,31,16,v)
    #define   GET16avsDirMvScale_BlockDistanceBw(r16)          _BFGET_(r16,15, 0)
    #define   SET16avsDirMvScale_BlockDistanceBw(r16,v)        _BFSET_(r16,15, 0,v)

            UNSG32 u_BlockDistanceFw                           : 16;
            UNSG32 u_BlockDistanceBw                           : 16;
    ///////////////////////////////////////////////////////////
    #define   GET32avsDirMvScale_invBlockDistanceRef(r32)      _BFGET_(r32,15, 0)
    #define   SET32avsDirMvScale_invBlockDistanceRef(r32,v)    _BFSET_(r32,15, 0,v)
    #define   GET16avsDirMvScale_invBlockDistanceRef(r16)      _BFGET_(r16,15, 0)
    #define   SET16avsDirMvScale_invBlockDistanceRef(r16,v)    _BFSET_(r16,15, 0,v)

    #define   GET32avsDirMvScale_RSVD16(r32)                   _BFGET_(r32,31,16)
    #define   SET32avsDirMvScale_RSVD16(r32,v)                 _BFSET_(r32,31,16,v)
    #define   GET16avsDirMvScale_RSVD16(r16)                   _BFGET_(r16,15, 0)
    #define   SET16avsDirMvScale_RSVD16(r16,v)                 _BFSET_(r16,15, 0,v)

            UNSG32 u_invBlockDistanceRef                       : 16;
            UNSG32 u_RSVD16                                    : 16;
    ///////////////////////////////////////////////////////////
    } SIE_avsDirMvScale;

    ///////////////////////////////////////////////////////////
     SIGN32 avsDirMvScale_drvrd(SIE_avsDirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 avsDirMvScale_drvwr(SIE_avsDirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void avsDirMvScale_reset(SIE_avsDirMvScale *p);
     SIGN32 avsDirMvScale_cmp  (SIE_avsDirMvScale *p, SIE_avsDirMvScale *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define avsDirMvScale_check(p,pie,pfx,hLOG) avsDirMvScale_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define avsDirMvScale_print(p,    pfx,hLOG) avsDirMvScale_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: avsDirMvScale
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BitOpX4                 biu              (4,4)
///     ###
///     * Operator format for BitOp extension
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 6  idx                       
///                                    ###
///                                    * rS[idx] or xT[idx] is used as source bit
///                                    * In case src==rS, idx[5:4] specifies the operation mode:
///                                    * idx[5:4]==2'b0x: output is from rS
///                                    * idx[5:4]==2'b10: output bit is forced to 0
///                                    * idx[5:4]==2'b11: output bit is forced to 1
///                                    ###
///               %unsigned 1  src                       
///                                    : xT                        0x0
///                                    : rS                        0x1
///                                                 ###
///                                                 * If src=rS, the source is from 16-bit input
///                                                 * If src=xT, the source is from 64-bit input
///                                                 ###
///               %unsigned 1  mode                      
///                                    : copy                      0x0
///                                    : inv                       0x1
///                                                 ###
///                                                 * copy: target bit copied from source bit
///                                                 * inv: target bit copied from source bit then inverted
///                                                 * Not used when src==rS & idx[5]==1'b1
///                                                 ###
///               %unsigned 6  idx1                      
///               %unsigned 1  src1                      
///               %unsigned 1  mode1                     
///               %unsigned 6  idx2                      
///               %unsigned 1  src2                      
///               %unsigned 1  mode2                     
///               %unsigned 6  idx3                      
///               %unsigned 1  src3                      
///               %unsigned 1  mode3                     
///                                    ###
///                                    * End BitOpX4
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BitOpX4
#define h_BitOpX4 (){}

    #define     BA_BitOpX4_idx                                 0x0000
    #define     B16BitOpX4_idx                                 0x0000
    #define   LSb32BitOpX4_idx                                    0
    #define   LSb16BitOpX4_idx                                    0
    #define       bBitOpX4_idx                                 6
    #define   MSK32BitOpX4_idx                                    0x0000003F

    #define     BA_BitOpX4_src                                 0x0000
    #define     B16BitOpX4_src                                 0x0000
    #define   LSb32BitOpX4_src                                    6
    #define   LSb16BitOpX4_src                                    6
    #define       bBitOpX4_src                                 1
    #define   MSK32BitOpX4_src                                    0x00000040
    #define        BitOpX4_src_xT                                           0x0
    #define        BitOpX4_src_rS                                           0x1

    #define     BA_BitOpX4_mode                                0x0000
    #define     B16BitOpX4_mode                                0x0000
    #define   LSb32BitOpX4_mode                                   7
    #define   LSb16BitOpX4_mode                                   7
    #define       bBitOpX4_mode                                1
    #define   MSK32BitOpX4_mode                                   0x00000080
    #define        BitOpX4_mode_copy                                        0x0
    #define        BitOpX4_mode_inv                                         0x1

    #define     BA_BitOpX4_idx1                                0x0001
    #define     B16BitOpX4_idx1                                0x0000
    #define   LSb32BitOpX4_idx1                                   8
    #define   LSb16BitOpX4_idx1                                   8
    #define       bBitOpX4_idx1                                6
    #define   MSK32BitOpX4_idx1                                   0x00003F00

    #define     BA_BitOpX4_src1                                0x0001
    #define     B16BitOpX4_src1                                0x0000
    #define   LSb32BitOpX4_src1                                   14
    #define   LSb16BitOpX4_src1                                   14
    #define       bBitOpX4_src1                                1
    #define   MSK32BitOpX4_src1                                   0x00004000

    #define     BA_BitOpX4_mode1                               0x0001
    #define     B16BitOpX4_mode1                               0x0000
    #define   LSb32BitOpX4_mode1                                  15
    #define   LSb16BitOpX4_mode1                                  15
    #define       bBitOpX4_mode1                               1
    #define   MSK32BitOpX4_mode1                                  0x00008000

    #define     BA_BitOpX4_idx2                                0x0002
    #define     B16BitOpX4_idx2                                0x0002
    #define   LSb32BitOpX4_idx2                                   16
    #define   LSb16BitOpX4_idx2                                   0
    #define       bBitOpX4_idx2                                6
    #define   MSK32BitOpX4_idx2                                   0x003F0000

    #define     BA_BitOpX4_src2                                0x0002
    #define     B16BitOpX4_src2                                0x0002
    #define   LSb32BitOpX4_src2                                   22
    #define   LSb16BitOpX4_src2                                   6
    #define       bBitOpX4_src2                                1
    #define   MSK32BitOpX4_src2                                   0x00400000

    #define     BA_BitOpX4_mode2                               0x0002
    #define     B16BitOpX4_mode2                               0x0002
    #define   LSb32BitOpX4_mode2                                  23
    #define   LSb16BitOpX4_mode2                                  7
    #define       bBitOpX4_mode2                               1
    #define   MSK32BitOpX4_mode2                                  0x00800000

    #define     BA_BitOpX4_idx3                                0x0003
    #define     B16BitOpX4_idx3                                0x0002
    #define   LSb32BitOpX4_idx3                                   24
    #define   LSb16BitOpX4_idx3                                   8
    #define       bBitOpX4_idx3                                6
    #define   MSK32BitOpX4_idx3                                   0x3F000000

    #define     BA_BitOpX4_src3                                0x0003
    #define     B16BitOpX4_src3                                0x0002
    #define   LSb32BitOpX4_src3                                   30
    #define   LSb16BitOpX4_src3                                   14
    #define       bBitOpX4_src3                                1
    #define   MSK32BitOpX4_src3                                   0x40000000

    #define     BA_BitOpX4_mode3                               0x0003
    #define     B16BitOpX4_mode3                               0x0002
    #define   LSb32BitOpX4_mode3                                  31
    #define   LSb16BitOpX4_mode3                                  15
    #define       bBitOpX4_mode3                               1
    #define   MSK32BitOpX4_mode3                                  0x80000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BitOpX4 {
    ///////////////////////////////////////////////////////////
    #define   GET32BitOpX4_idx(r32)                            _BFGET_(r32, 5, 0)
    #define   SET32BitOpX4_idx(r32,v)                          _BFSET_(r32, 5, 0,v)
    #define   GET16BitOpX4_idx(r16)                            _BFGET_(r16, 5, 0)
    #define   SET16BitOpX4_idx(r16,v)                          _BFSET_(r16, 5, 0,v)

    #define   GET32BitOpX4_src(r32)                            _BFGET_(r32, 6, 6)
    #define   SET32BitOpX4_src(r32,v)                          _BFSET_(r32, 6, 6,v)
    #define   GET16BitOpX4_src(r16)                            _BFGET_(r16, 6, 6)
    #define   SET16BitOpX4_src(r16,v)                          _BFSET_(r16, 6, 6,v)

    #define   GET32BitOpX4_mode(r32)                           _BFGET_(r32, 7, 7)
    #define   SET32BitOpX4_mode(r32,v)                         _BFSET_(r32, 7, 7,v)
    #define   GET16BitOpX4_mode(r16)                           _BFGET_(r16, 7, 7)
    #define   SET16BitOpX4_mode(r16,v)                         _BFSET_(r16, 7, 7,v)

    #define   GET32BitOpX4_idx1(r32)                           _BFGET_(r32,13, 8)
    #define   SET32BitOpX4_idx1(r32,v)                         _BFSET_(r32,13, 8,v)
    #define   GET16BitOpX4_idx1(r16)                           _BFGET_(r16,13, 8)
    #define   SET16BitOpX4_idx1(r16,v)                         _BFSET_(r16,13, 8,v)

    #define   GET32BitOpX4_src1(r32)                           _BFGET_(r32,14,14)
    #define   SET32BitOpX4_src1(r32,v)                         _BFSET_(r32,14,14,v)
    #define   GET16BitOpX4_src1(r16)                           _BFGET_(r16,14,14)
    #define   SET16BitOpX4_src1(r16,v)                         _BFSET_(r16,14,14,v)

    #define   GET32BitOpX4_mode1(r32)                          _BFGET_(r32,15,15)
    #define   SET32BitOpX4_mode1(r32,v)                        _BFSET_(r32,15,15,v)
    #define   GET16BitOpX4_mode1(r16)                          _BFGET_(r16,15,15)
    #define   SET16BitOpX4_mode1(r16,v)                        _BFSET_(r16,15,15,v)

    #define   GET32BitOpX4_idx2(r32)                           _BFGET_(r32,21,16)
    #define   SET32BitOpX4_idx2(r32,v)                         _BFSET_(r32,21,16,v)
    #define   GET16BitOpX4_idx2(r16)                           _BFGET_(r16, 5, 0)
    #define   SET16BitOpX4_idx2(r16,v)                         _BFSET_(r16, 5, 0,v)

    #define   GET32BitOpX4_src2(r32)                           _BFGET_(r32,22,22)
    #define   SET32BitOpX4_src2(r32,v)                         _BFSET_(r32,22,22,v)
    #define   GET16BitOpX4_src2(r16)                           _BFGET_(r16, 6, 6)
    #define   SET16BitOpX4_src2(r16,v)                         _BFSET_(r16, 6, 6,v)

    #define   GET32BitOpX4_mode2(r32)                          _BFGET_(r32,23,23)
    #define   SET32BitOpX4_mode2(r32,v)                        _BFSET_(r32,23,23,v)
    #define   GET16BitOpX4_mode2(r16)                          _BFGET_(r16, 7, 7)
    #define   SET16BitOpX4_mode2(r16,v)                        _BFSET_(r16, 7, 7,v)

    #define   GET32BitOpX4_idx3(r32)                           _BFGET_(r32,29,24)
    #define   SET32BitOpX4_idx3(r32,v)                         _BFSET_(r32,29,24,v)
    #define   GET16BitOpX4_idx3(r16)                           _BFGET_(r16,13, 8)
    #define   SET16BitOpX4_idx3(r16,v)                         _BFSET_(r16,13, 8,v)

    #define   GET32BitOpX4_src3(r32)                           _BFGET_(r32,30,30)
    #define   SET32BitOpX4_src3(r32,v)                         _BFSET_(r32,30,30,v)
    #define   GET16BitOpX4_src3(r16)                           _BFGET_(r16,14,14)
    #define   SET16BitOpX4_src3(r16,v)                         _BFSET_(r16,14,14,v)

    #define   GET32BitOpX4_mode3(r32)                          _BFGET_(r32,31,31)
    #define   SET32BitOpX4_mode3(r32,v)                        _BFSET_(r32,31,31,v)
    #define   GET16BitOpX4_mode3(r16)                          _BFGET_(r16,15,15)
    #define   SET16BitOpX4_mode3(r16,v)                        _BFSET_(r16,15,15,v)

            UNSG32 u_idx                                       :  6;
            UNSG32 u_src                                       :  1;
            UNSG32 u_mode                                      :  1;
            UNSG32 u_idx1                                      :  6;
            UNSG32 u_src1                                      :  1;
            UNSG32 u_mode1                                     :  1;
            UNSG32 u_idx2                                      :  6;
            UNSG32 u_src2                                      :  1;
            UNSG32 u_mode2                                     :  1;
            UNSG32 u_idx3                                      :  6;
            UNSG32 u_src3                                      :  1;
            UNSG32 u_mode3                                     :  1;
    ///////////////////////////////////////////////////////////
    } SIE_BitOpX4;

    ///////////////////////////////////////////////////////////
     SIGN32 BitOpX4_drvrd(SIE_BitOpX4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BitOpX4_drvwr(SIE_BitOpX4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BitOpX4_reset(SIE_BitOpX4 *p);
     SIGN32 BitOpX4_cmp  (SIE_BitOpX4 *p, SIE_BitOpX4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BitOpX4_check(p,pie,pfx,hLOG) BitOpX4_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BitOpX4_print(p,    pfx,hLOG) BitOpX4_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BitOpX4
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BITOPRF64               biu              (4,4)
///     ###
///     * Operator format for BitOp extension
///     ###
///     # # ----------------------------------------------------------
///               : BitOp0             0x20
///               : BitOp1             0x21
///               : BitOp2             0x22
///               : BitOp3             0x23
///                            ###
///                            * extension ID definition; must be consistent with vScope_F0A64_BitOp0~3
///                            ###
///     @ 0x00000                      (P)
///     # 0x00000 cmd0                 
///               $BitOpX4             cmd0              REG       [4]
///     @ 0x00010                      (P)
///     # 0x00010 cmd1                 
///               $BitOpX4             cmd1              REG       [4]
///     @ 0x00020                      (P)
///     # 0x00020 cmd2                 
///               $BitOpX4             cmd2              REG       [4]
///     @ 0x00030                      (P)
///     # 0x00030 cmd3                 
///               $BitOpX4             cmd3              REG       [4]
///                                    ###
///                                    * Four BitOp commands, selected by extension ID
///                                    * End BitOpCtx
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      64B, bits:     512b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITOPRF64
#define h_BITOPRF64 (){}

    #define        BITOPRF64_BitOp0                            0x20
    #define        BITOPRF64_BitOp1                            0x21
    #define        BITOPRF64_BitOp2                            0x22
    #define        BITOPRF64_BitOp3                            0x23
    ///////////////////////////////////////////////////////////
    #define     RA_BITOPRF64_cmd0                              0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_BITOPRF64_cmd1                              0x0010
    ///////////////////////////////////////////////////////////
    #define     RA_BITOPRF64_cmd2                              0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_BITOPRF64_cmd3                              0x0030
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITOPRF64 {
    ///////////////////////////////////////////////////////////
              SIE_BitOpX4                                      ie_cmd0[4];
    ///////////////////////////////////////////////////////////
              SIE_BitOpX4                                      ie_cmd1[4];
    ///////////////////////////////////////////////////////////
              SIE_BitOpX4                                      ie_cmd2[4];
    ///////////////////////////////////////////////////////////
              SIE_BitOpX4                                      ie_cmd3[4];
    ///////////////////////////////////////////////////////////
    } SIE_BITOPRF64;

    ///////////////////////////////////////////////////////////
     SIGN32 BITOPRF64_drvrd(SIE_BITOPRF64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITOPRF64_drvwr(SIE_BITOPRF64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITOPRF64_reset(SIE_BITOPRF64 *p);
     SIGN32 BITOPRF64_cmp  (SIE_BITOPRF64 *p, SIE_BITOPRF64 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITOPRF64_check(p,pie,pfx,hLOG) BITOPRF64_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITOPRF64_print(p,    pfx,hLOG) BITOPRF64_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITOPRF64
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE LUT8b                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 8  data                      
///                                    ###
///                                    * Any 8b data
///                                    ###
///               %unsigned 8  data1                     
///               %unsigned 8  data2                     
///               %unsigned 8  data3                     
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_LUT8b
#define h_LUT8b (){}

    #define     BA_LUT8b_data                                  0x0000
    #define     B16LUT8b_data                                  0x0000
    #define   LSb32LUT8b_data                                     0
    #define   LSb16LUT8b_data                                     0
    #define       bLUT8b_data                                  8
    #define   MSK32LUT8b_data                                     0x000000FF

    #define     BA_LUT8b_data1                                 0x0001
    #define     B16LUT8b_data1                                 0x0000
    #define   LSb32LUT8b_data1                                    8
    #define   LSb16LUT8b_data1                                    8
    #define       bLUT8b_data1                                 8
    #define   MSK32LUT8b_data1                                    0x0000FF00

    #define     BA_LUT8b_data2                                 0x0002
    #define     B16LUT8b_data2                                 0x0002
    #define   LSb32LUT8b_data2                                    16
    #define   LSb16LUT8b_data2                                    0
    #define       bLUT8b_data2                                 8
    #define   MSK32LUT8b_data2                                    0x00FF0000

    #define     BA_LUT8b_data3                                 0x0003
    #define     B16LUT8b_data3                                 0x0002
    #define   LSb32LUT8b_data3                                    24
    #define   LSb16LUT8b_data3                                    8
    #define       bLUT8b_data3                                 8
    #define   MSK32LUT8b_data3                                    0xFF000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_LUT8b {
    ///////////////////////////////////////////////////////////
    #define   GET32LUT8b_data(r32)                             _BFGET_(r32, 7, 0)
    #define   SET32LUT8b_data(r32,v)                           _BFSET_(r32, 7, 0,v)
    #define   GET16LUT8b_data(r16)                             _BFGET_(r16, 7, 0)
    #define   SET16LUT8b_data(r16,v)                           _BFSET_(r16, 7, 0,v)

    #define   GET32LUT8b_data1(r32)                            _BFGET_(r32,15, 8)
    #define   SET32LUT8b_data1(r32,v)                          _BFSET_(r32,15, 8,v)
    #define   GET16LUT8b_data1(r16)                            _BFGET_(r16,15, 8)
    #define   SET16LUT8b_data1(r16,v)                          _BFSET_(r16,15, 8,v)

    #define   GET32LUT8b_data2(r32)                            _BFGET_(r32,23,16)
    #define   SET32LUT8b_data2(r32,v)                          _BFSET_(r32,23,16,v)
    #define   GET16LUT8b_data2(r16)                            _BFGET_(r16, 7, 0)
    #define   SET16LUT8b_data2(r16,v)                          _BFSET_(r16, 7, 0,v)

    #define   GET32LUT8b_data3(r32)                            _BFGET_(r32,31,24)
    #define   SET32LUT8b_data3(r32,v)                          _BFSET_(r32,31,24,v)
    #define   GET16LUT8b_data3(r16)                            _BFGET_(r16,15, 8)
    #define   SET16LUT8b_data3(r16,v)                          _BFSET_(r16,15, 8,v)

            UNSG32 u_data                                      :  8;
            UNSG32 u_data1                                     :  8;
            UNSG32 u_data2                                     :  8;
            UNSG32 u_data3                                     :  8;
    ///////////////////////////////////////////////////////////
    } SIE_LUT8b;

    ///////////////////////////////////////////////////////////
     SIGN32 LUT8b_drvrd(SIE_LUT8b *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 LUT8b_drvwr(SIE_LUT8b *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void LUT8b_reset(SIE_LUT8b *p);
     SIGN32 LUT8b_cmp  (SIE_LUT8b *p, SIE_LUT8b *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define LUT8b_check(p,pie,pfx,hLOG) LUT8b_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define LUT8b_print(p,    pfx,hLOG) LUT8b_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: LUT8b
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE LUT64b                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 32 data_0i                   
///               %unsigned 32 data_1i                   
///                                    ###
///                                    * Any 64b data
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_LUT64b
#define h_LUT64b (){}

    #define     BA_LUT64b_data_0i                              0x0000
    #define     B16LUT64b_data_0i                              0x0000
    #define   LSb32LUT64b_data_0i                                 0
    #define   LSb16LUT64b_data_0i                                 0
    #define       bLUT64b_data_0i                              32
    #define   MSK32LUT64b_data_0i                                 0xFFFFFFFF

    #define     BA_LUT64b_data_1i                              0x0004
    #define     B16LUT64b_data_1i                              0x0004
    #define   LSb32LUT64b_data_1i                                 0
    #define   LSb16LUT64b_data_1i                                 0
    #define       bLUT64b_data_1i                              32
    #define   MSK32LUT64b_data_1i                                 0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_LUT64b {
    ///////////////////////////////////////////////////////////
    #define   GET32LUT64b_data_0i(r32)                         _BFGET_(r32,31, 0)
    #define   SET32LUT64b_data_0i(r32,v)                       _BFSET_(r32,31, 0,v)

            UNSG32 u_data_0i                                   : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32LUT64b_data_1i(r32)                         _BFGET_(r32,31, 0)
    #define   SET32LUT64b_data_1i(r32,v)                       _BFSET_(r32,31, 0,v)

            UNSG32 u_data_1i                                   : 32;
    ///////////////////////////////////////////////////////////
    } SIE_LUT64b;

    ///////////////////////////////////////////////////////////
     SIGN32 LUT64b_drvrd(SIE_LUT64b *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 LUT64b_drvwr(SIE_LUT64b *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void LUT64b_reset(SIE_LUT64b *p);
     SIGN32 LUT64b_cmp  (SIE_LUT64b *p, SIE_LUT64b *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define LUT64b_check(p,pie,pfx,hLOG) LUT64b_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define LUT64b_print(p,    pfx,hLOG) LUT64b_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: LUT64b
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE NLoc                                     (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 4  BLK                       
///                                    ###
///                                    * Block index
///                                    ###
///               %unsigned 4  category                  
///                                    : 16x16                     0x8
///                                    : 8x16                      0x9
///                                    : 16x8                      0xA
///                                    : 4mv                       0xB
///                                    : 8x8                       0xC
///                                    : 4x8                       0xD
///                                    : 8x4                       0xE
///                                    : 4x4                       0xF
///                                                 ###
///                                                 * Consistent with vcMsg{RSVD,level,partition}
///                                                 * Valid cases for Neighbor:
///                                                 * 16x16=16x8
///                                                 * 8x16=4mv=8x8=8x4
///                                                 * 4x8=4x4=ACY
///                                                 * Valid cases for PMV:
///                                                 * 16x16=16x8
///                                                 * 8x16
///                                                 * 4mv=8x8=8x4
///                                                 * 4x8=4x4=ACY
///                                                 ###
///                                    : ACY                       0x0
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0~15 (every 4x4 indexed by coding order)
///                                                 ###
///                                    : ACU                       0x2
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0~3 (3rd 4x4 in every 8x8)
///                                                 ###
///                                    : ACV                       0x3
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0~3 (4th 4x4 in every 8x8)
///                                                 ###
///                                    : I16AC                     0x4
///                                                 ###
///                                                 * Only used as category, should be converted to ACY for neighbor look-up
///                                                 ###
///                                    : DCI                       0x4
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0 (3rd 4x4 in 4th 8x8 only)
///                                                 ###
///                                    : DCY                       0x5
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0 (4th 4x4 in 4th 8x8 only)
///                                                 ###
///                                    : SDPMV                     0x5
///                                                 ###
///                                                 * Reuse DCY in PMV extension, for Spatial Direct mode rIDX recovery.
///                                                 ###
///                                    : DCU                       0x6
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0 (3rd 4x4 in 3rd 8x8 only)
///                                                 ###
///                                    : DCV                       0x7
///                                                 ###
///                                                 * Valid block index:
///                                                 * 0 (4th 4x4 in 3rd 8x8 only)
///                                                 ###
///               %unsigned 1  parity                    
///                                    ###
///                                    * 0/1 as even/odd, only for loop-filter
///                                    ###
///               %unsigned 1  direct                    
///                                    ###
///                                    * FW use only: if direct mode
///                                    * AVS: use for sym mode in hardware.
///                                    ###
///               %unsigned 2  motion                    
///                                    ###
///                                    * FW use only: motion type
///                                    ###
///               %unsigned 1  A                         
///                                    ###
///                                    * Left macroblock/block availability
///                                    ###
///               %unsigned 1  B                         
///                                    ###
///                                    * Upper macroblock/block availability
///                                    ###
///               %unsigned 1  C                         
///                                    ###
///                                    * Upper-right macroblock/block availability
///                                    ###
///               %unsigned 1  D                         
///                                    ###
///                                    * Upper-left macroblock/block availability
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      16b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_NLoc
#define h_NLoc (){}

    #define     BA_NLoc_BLK                                    0x0000
    #define     B16NLoc_BLK                                    0x0000
    #define   LSb32NLoc_BLK                                       0
    #define   LSb16NLoc_BLK                                       0
    #define       bNLoc_BLK                                    4
    #define   MSK32NLoc_BLK                                       0x0000000F

    #define     BA_NLoc_category                               0x0000
    #define     B16NLoc_category                               0x0000
    #define   LSb32NLoc_category                                  4
    #define   LSb16NLoc_category                                  4
    #define       bNLoc_category                               4
    #define   MSK32NLoc_category                                  0x000000F0
    #define        NLoc_category_16x16                                      0x8
    #define        NLoc_category_8x16                                       0x9
    #define        NLoc_category_16x8                                       0xA
    #define        NLoc_category_4mv                                        0xB
    #define        NLoc_category_8x8                                        0xC
    #define        NLoc_category_4x8                                        0xD
    #define        NLoc_category_8x4                                        0xE
    #define        NLoc_category_4x4                                        0xF
    #define        NLoc_category_ACY                                        0x0
    #define        NLoc_category_ACU                                        0x2
    #define        NLoc_category_ACV                                        0x3
    #define        NLoc_category_I16AC                                      0x4
    #define        NLoc_category_DCI                                        0x4
    #define        NLoc_category_DCY                                        0x5
    #define        NLoc_category_SDPMV                                      0x5
    #define        NLoc_category_DCU                                        0x6
    #define        NLoc_category_DCV                                        0x7

    #define     BA_NLoc_parity                                 0x0001
    #define     B16NLoc_parity                                 0x0000
    #define   LSb32NLoc_parity                                    8
    #define   LSb16NLoc_parity                                    8
    #define       bNLoc_parity                                 1
    #define   MSK32NLoc_parity                                    0x00000100

    #define     BA_NLoc_direct                                 0x0001
    #define     B16NLoc_direct                                 0x0000
    #define   LSb32NLoc_direct                                    9
    #define   LSb16NLoc_direct                                    9
    #define       bNLoc_direct                                 1
    #define   MSK32NLoc_direct                                    0x00000200

    #define     BA_NLoc_motion                                 0x0001
    #define     B16NLoc_motion                                 0x0000
    #define   LSb32NLoc_motion                                    10
    #define   LSb16NLoc_motion                                    10
    #define       bNLoc_motion                                 2
    #define   MSK32NLoc_motion                                    0x00000C00

    #define     BA_NLoc_A                                      0x0001
    #define     B16NLoc_A                                      0x0000
    #define   LSb32NLoc_A                                         12
    #define   LSb16NLoc_A                                         12
    #define       bNLoc_A                                      1
    #define   MSK32NLoc_A                                         0x00001000

    #define     BA_NLoc_B                                      0x0001
    #define     B16NLoc_B                                      0x0000
    #define   LSb32NLoc_B                                         13
    #define   LSb16NLoc_B                                         13
    #define       bNLoc_B                                      1
    #define   MSK32NLoc_B                                         0x00002000

    #define     BA_NLoc_C                                      0x0001
    #define     B16NLoc_C                                      0x0000
    #define   LSb32NLoc_C                                         14
    #define   LSb16NLoc_C                                         14
    #define       bNLoc_C                                      1
    #define   MSK32NLoc_C                                         0x00004000

    #define     BA_NLoc_D                                      0x0001
    #define     B16NLoc_D                                      0x0000
    #define   LSb32NLoc_D                                         15
    #define   LSb16NLoc_D                                         15
    #define       bNLoc_D                                      1
    #define   MSK32NLoc_D                                         0x00008000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_NLoc {
    ///////////////////////////////////////////////////////////
    #define   GET32NLoc_BLK(r32)                               _BFGET_(r32, 3, 0)
    #define   SET32NLoc_BLK(r32,v)                             _BFSET_(r32, 3, 0,v)
    #define   GET16NLoc_BLK(r16)                               _BFGET_(r16, 3, 0)
    #define   SET16NLoc_BLK(r16,v)                             _BFSET_(r16, 3, 0,v)

    #define   GET32NLoc_category(r32)                          _BFGET_(r32, 7, 4)
    #define   SET32NLoc_category(r32,v)                        _BFSET_(r32, 7, 4,v)
    #define   GET16NLoc_category(r16)                          _BFGET_(r16, 7, 4)
    #define   SET16NLoc_category(r16,v)                        _BFSET_(r16, 7, 4,v)

    #define   GET32NLoc_parity(r32)                            _BFGET_(r32, 8, 8)
    #define   SET32NLoc_parity(r32,v)                          _BFSET_(r32, 8, 8,v)
    #define   GET16NLoc_parity(r16)                            _BFGET_(r16, 8, 8)
    #define   SET16NLoc_parity(r16,v)                          _BFSET_(r16, 8, 8,v)

    #define   GET32NLoc_direct(r32)                            _BFGET_(r32, 9, 9)
    #define   SET32NLoc_direct(r32,v)                          _BFSET_(r32, 9, 9,v)
    #define   GET16NLoc_direct(r16)                            _BFGET_(r16, 9, 9)
    #define   SET16NLoc_direct(r16,v)                          _BFSET_(r16, 9, 9,v)

    #define   GET32NLoc_motion(r32)                            _BFGET_(r32,11,10)
    #define   SET32NLoc_motion(r32,v)                          _BFSET_(r32,11,10,v)
    #define   GET16NLoc_motion(r16)                            _BFGET_(r16,11,10)
    #define   SET16NLoc_motion(r16,v)                          _BFSET_(r16,11,10,v)

    #define   GET32NLoc_A(r32)                                 _BFGET_(r32,12,12)
    #define   SET32NLoc_A(r32,v)                               _BFSET_(r32,12,12,v)
    #define   GET16NLoc_A(r16)                                 _BFGET_(r16,12,12)
    #define   SET16NLoc_A(r16,v)                               _BFSET_(r16,12,12,v)

    #define   GET32NLoc_B(r32)                                 _BFGET_(r32,13,13)
    #define   SET32NLoc_B(r32,v)                               _BFSET_(r32,13,13,v)
    #define   GET16NLoc_B(r16)                                 _BFGET_(r16,13,13)
    #define   SET16NLoc_B(r16,v)                               _BFSET_(r16,13,13,v)

    #define   GET32NLoc_C(r32)                                 _BFGET_(r32,14,14)
    #define   SET32NLoc_C(r32,v)                               _BFSET_(r32,14,14,v)
    #define   GET16NLoc_C(r16)                                 _BFGET_(r16,14,14)
    #define   SET16NLoc_C(r16,v)                               _BFSET_(r16,14,14,v)

    #define   GET32NLoc_D(r32)                                 _BFGET_(r32,15,15)
    #define   SET32NLoc_D(r32,v)                               _BFSET_(r32,15,15,v)
    #define   GET16NLoc_D(r16)                                 _BFGET_(r16,15,15)
    #define   SET16NLoc_D(r16,v)                               _BFSET_(r16,15,15,v)

            UNSG32 u_BLK                                       :  4;
            UNSG32 u_category                                  :  4;
            UNSG32 u_parity                                    :  1;
            UNSG32 u_direct                                    :  1;
            UNSG32 u_motion                                    :  2;
            UNSG32 u_A                                         :  1;
            UNSG32 u_B                                         :  1;
            UNSG32 u_C                                         :  1;
            UNSG32 u_D                                         :  1;
    ///////////////////////////////////////////////////////////
    } SIE_NLoc;

    ///////////////////////////////////////////////////////////
     SIGN32 NLoc_drvrd(SIE_NLoc *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 NLoc_drvwr(SIE_NLoc *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void NLoc_reset(SIE_NLoc *p);
     SIGN32 NLoc_cmp  (SIE_NLoc *p, SIE_NLoc *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define NLoc_check(p,pie,pfx,hLOG) NLoc_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define NLoc_print(p,    pfx,hLOG) NLoc_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: NLoc
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BLK                                      (4,4)
///     # # ----------------------------------------------------------
///               : skip               0x0
///               : direct16x16        0x1
///               : 4BLK               0x2
///               : inter              0x3
///               : IPCM               0x4
///               : intra16x16         0x5
///               : intraNxN           0x6
///                            ###
///                            * Sub-set of mb_type
///                            * MPEG2: only skip, inter, intra (intra16x16)
///                            * MPEG4/VC-1: only 1 intra type (intra16x16)
///                            * AVS: skip, direct16x16, 4BLK, inter, intra16x16 (only 1 intra type)
///                            ###
///     @ 0x00000                      (P)
///               %unsigned 2  motion                    
///                                    : Intra                     0x0
///                                    : Forward                   0x1
///                                    : Backward                  0x2
///                                    : Bi                        0x3
///                                                 ###
///                                                 * Derived 8x8 block motion type
///                                                 * NOTE: direct mode uses 'Bi'
///                                                 ###
///               %unsigned 2  partition                 
///                                    : 1mv                       0x0
///                                    : 2mvLR                     0x1
///                                    : 2mvTB                     0x2
///                                                 ###
///                                                 * MPEG2: 2mvTB used for field prediction
///                                                 * VC-1: 2-field-mv
///                                                 ###
///                                    : 4mv                       0x3
///                                                 ###
///                                                 * Block/macroblock level partitioning
///                                                 * MPEG4: 1mv & 4mv
///                                                 ###
///                                    : 4mvFLD                    0x1
///                                                 ###
///                                                 * VC-1: 4-field-mv
///                                                 ###
///               %unsigned 1  direct                    
///                                    ###
///                                    * Direct mode flag
///                                    * MPEG2: dual-prime prediction
///                                    ###
///               %unsigned 3  mvs                       
///                                    ###
///                                    * Number of motion vectors: 0/1/2/4
///                                    ###
///               %unsigned 2  motion1                   
///               %unsigned 2  partition1                
///               %unsigned 1  direct1                   
///               %unsigned 3  mvs1                      
///               %unsigned 2  motion2                   
///               %unsigned 2  partition2                
///               %unsigned 1  direct2                   
///               %unsigned 3  mvs2                      
///               %unsigned 2  motion3                   
///               %unsigned 2  partition3                
///               %unsigned 1  direct3                   
///               %unsigned 3  mvs3                      
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BLK
#define h_BLK (){}

    #define        BLK_skip                                    0x0
    #define        BLK_direct16x16                             0x1
    #define        BLK_4BLK                                    0x2
    #define        BLK_inter                                   0x3
    #define        BLK_IPCM                                    0x4
    #define        BLK_intra16x16                              0x5
    #define        BLK_intraNxN                                0x6
    ///////////////////////////////////////////////////////////

    #define     BA_BLK_motion                                  0x0000
    #define     B16BLK_motion                                  0x0000
    #define   LSb32BLK_motion                                     0
    #define   LSb16BLK_motion                                     0
    #define       bBLK_motion                                  2
    #define   MSK32BLK_motion                                     0x00000003
    #define        BLK_motion_Intra                                         0x0
    #define        BLK_motion_Forward                                       0x1
    #define        BLK_motion_Backward                                      0x2
    #define        BLK_motion_Bi                                            0x3

    #define     BA_BLK_partition                               0x0000
    #define     B16BLK_partition                               0x0000
    #define   LSb32BLK_partition                                  2
    #define   LSb16BLK_partition                                  2
    #define       bBLK_partition                               2
    #define   MSK32BLK_partition                                  0x0000000C
    #define        BLK_partition_1mv                                        0x0
    #define        BLK_partition_2mvLR                                      0x1
    #define        BLK_partition_2mvTB                                      0x2
    #define        BLK_partition_4mv                                        0x3
    #define        BLK_partition_4mvFLD                                     0x1

    #define     BA_BLK_direct                                  0x0000
    #define     B16BLK_direct                                  0x0000
    #define   LSb32BLK_direct                                     4
    #define   LSb16BLK_direct                                     4
    #define       bBLK_direct                                  1
    #define   MSK32BLK_direct                                     0x00000010

    #define     BA_BLK_mvs                                     0x0000
    #define     B16BLK_mvs                                     0x0000
    #define   LSb32BLK_mvs                                        5
    #define   LSb16BLK_mvs                                        5
    #define       bBLK_mvs                                     3
    #define   MSK32BLK_mvs                                        0x000000E0

    #define     BA_BLK_motion1                                 0x0001
    #define     B16BLK_motion1                                 0x0000
    #define   LSb32BLK_motion1                                    8
    #define   LSb16BLK_motion1                                    8
    #define       bBLK_motion1                                 2
    #define   MSK32BLK_motion1                                    0x00000300

    #define     BA_BLK_partition1                              0x0001
    #define     B16BLK_partition1                              0x0000
    #define   LSb32BLK_partition1                                 10
    #define   LSb16BLK_partition1                                 10
    #define       bBLK_partition1                              2
    #define   MSK32BLK_partition1                                 0x00000C00

    #define     BA_BLK_direct1                                 0x0001
    #define     B16BLK_direct1                                 0x0000
    #define   LSb32BLK_direct1                                    12
    #define   LSb16BLK_direct1                                    12
    #define       bBLK_direct1                                 1
    #define   MSK32BLK_direct1                                    0x00001000

    #define     BA_BLK_mvs1                                    0x0001
    #define     B16BLK_mvs1                                    0x0000
    #define   LSb32BLK_mvs1                                       13
    #define   LSb16BLK_mvs1                                       13
    #define       bBLK_mvs1                                    3
    #define   MSK32BLK_mvs1                                       0x0000E000

    #define     BA_BLK_motion2                                 0x0002
    #define     B16BLK_motion2                                 0x0002
    #define   LSb32BLK_motion2                                    16
    #define   LSb16BLK_motion2                                    0
    #define       bBLK_motion2                                 2
    #define   MSK32BLK_motion2                                    0x00030000

    #define     BA_BLK_partition2                              0x0002
    #define     B16BLK_partition2                              0x0002
    #define   LSb32BLK_partition2                                 18
    #define   LSb16BLK_partition2                                 2
    #define       bBLK_partition2                              2
    #define   MSK32BLK_partition2                                 0x000C0000

    #define     BA_BLK_direct2                                 0x0002
    #define     B16BLK_direct2                                 0x0002
    #define   LSb32BLK_direct2                                    20
    #define   LSb16BLK_direct2                                    4
    #define       bBLK_direct2                                 1
    #define   MSK32BLK_direct2                                    0x00100000

    #define     BA_BLK_mvs2                                    0x0002
    #define     B16BLK_mvs2                                    0x0002
    #define   LSb32BLK_mvs2                                       21
    #define   LSb16BLK_mvs2                                       5
    #define       bBLK_mvs2                                    3
    #define   MSK32BLK_mvs2                                       0x00E00000

    #define     BA_BLK_motion3                                 0x0003
    #define     B16BLK_motion3                                 0x0002
    #define   LSb32BLK_motion3                                    24
    #define   LSb16BLK_motion3                                    8
    #define       bBLK_motion3                                 2
    #define   MSK32BLK_motion3                                    0x03000000

    #define     BA_BLK_partition3                              0x0003
    #define     B16BLK_partition3                              0x0002
    #define   LSb32BLK_partition3                                 26
    #define   LSb16BLK_partition3                                 10
    #define       bBLK_partition3                              2
    #define   MSK32BLK_partition3                                 0x0C000000

    #define     BA_BLK_direct3                                 0x0003
    #define     B16BLK_direct3                                 0x0002
    #define   LSb32BLK_direct3                                    28
    #define   LSb16BLK_direct3                                    12
    #define       bBLK_direct3                                 1
    #define   MSK32BLK_direct3                                    0x10000000

    #define     BA_BLK_mvs3                                    0x0003
    #define     B16BLK_mvs3                                    0x0002
    #define   LSb32BLK_mvs3                                       29
    #define   LSb16BLK_mvs3                                       13
    #define       bBLK_mvs3                                    3
    #define   MSK32BLK_mvs3                                       0xE0000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BLK {
    ///////////////////////////////////////////////////////////
    #define   GET32BLK_motion(r32)                             _BFGET_(r32, 1, 0)
    #define   SET32BLK_motion(r32,v)                           _BFSET_(r32, 1, 0,v)
    #define   GET16BLK_motion(r16)                             _BFGET_(r16, 1, 0)
    #define   SET16BLK_motion(r16,v)                           _BFSET_(r16, 1, 0,v)

    #define   GET32BLK_partition(r32)                          _BFGET_(r32, 3, 2)
    #define   SET32BLK_partition(r32,v)                        _BFSET_(r32, 3, 2,v)
    #define   GET16BLK_partition(r16)                          _BFGET_(r16, 3, 2)
    #define   SET16BLK_partition(r16,v)                        _BFSET_(r16, 3, 2,v)

    #define   GET32BLK_direct(r32)                             _BFGET_(r32, 4, 4)
    #define   SET32BLK_direct(r32,v)                           _BFSET_(r32, 4, 4,v)
    #define   GET16BLK_direct(r16)                             _BFGET_(r16, 4, 4)
    #define   SET16BLK_direct(r16,v)                           _BFSET_(r16, 4, 4,v)

    #define   GET32BLK_mvs(r32)                                _BFGET_(r32, 7, 5)
    #define   SET32BLK_mvs(r32,v)                              _BFSET_(r32, 7, 5,v)
    #define   GET16BLK_mvs(r16)                                _BFGET_(r16, 7, 5)
    #define   SET16BLK_mvs(r16,v)                              _BFSET_(r16, 7, 5,v)

    #define   GET32BLK_motion1(r32)                            _BFGET_(r32, 9, 8)
    #define   SET32BLK_motion1(r32,v)                          _BFSET_(r32, 9, 8,v)
    #define   GET16BLK_motion1(r16)                            _BFGET_(r16, 9, 8)
    #define   SET16BLK_motion1(r16,v)                          _BFSET_(r16, 9, 8,v)

    #define   GET32BLK_partition1(r32)                         _BFGET_(r32,11,10)
    #define   SET32BLK_partition1(r32,v)                       _BFSET_(r32,11,10,v)
    #define   GET16BLK_partition1(r16)                         _BFGET_(r16,11,10)
    #define   SET16BLK_partition1(r16,v)                       _BFSET_(r16,11,10,v)

    #define   GET32BLK_direct1(r32)                            _BFGET_(r32,12,12)
    #define   SET32BLK_direct1(r32,v)                          _BFSET_(r32,12,12,v)
    #define   GET16BLK_direct1(r16)                            _BFGET_(r16,12,12)
    #define   SET16BLK_direct1(r16,v)                          _BFSET_(r16,12,12,v)

    #define   GET32BLK_mvs1(r32)                               _BFGET_(r32,15,13)
    #define   SET32BLK_mvs1(r32,v)                             _BFSET_(r32,15,13,v)
    #define   GET16BLK_mvs1(r16)                               _BFGET_(r16,15,13)
    #define   SET16BLK_mvs1(r16,v)                             _BFSET_(r16,15,13,v)

    #define   GET32BLK_motion2(r32)                            _BFGET_(r32,17,16)
    #define   SET32BLK_motion2(r32,v)                          _BFSET_(r32,17,16,v)
    #define   GET16BLK_motion2(r16)                            _BFGET_(r16, 1, 0)
    #define   SET16BLK_motion2(r16,v)                          _BFSET_(r16, 1, 0,v)

    #define   GET32BLK_partition2(r32)                         _BFGET_(r32,19,18)
    #define   SET32BLK_partition2(r32,v)                       _BFSET_(r32,19,18,v)
    #define   GET16BLK_partition2(r16)                         _BFGET_(r16, 3, 2)
    #define   SET16BLK_partition2(r16,v)                       _BFSET_(r16, 3, 2,v)

    #define   GET32BLK_direct2(r32)                            _BFGET_(r32,20,20)
    #define   SET32BLK_direct2(r32,v)                          _BFSET_(r32,20,20,v)
    #define   GET16BLK_direct2(r16)                            _BFGET_(r16, 4, 4)
    #define   SET16BLK_direct2(r16,v)                          _BFSET_(r16, 4, 4,v)

    #define   GET32BLK_mvs2(r32)                               _BFGET_(r32,23,21)
    #define   SET32BLK_mvs2(r32,v)                             _BFSET_(r32,23,21,v)
    #define   GET16BLK_mvs2(r16)                               _BFGET_(r16, 7, 5)
    #define   SET16BLK_mvs2(r16,v)                             _BFSET_(r16, 7, 5,v)

    #define   GET32BLK_motion3(r32)                            _BFGET_(r32,25,24)
    #define   SET32BLK_motion3(r32,v)                          _BFSET_(r32,25,24,v)
    #define   GET16BLK_motion3(r16)                            _BFGET_(r16, 9, 8)
    #define   SET16BLK_motion3(r16,v)                          _BFSET_(r16, 9, 8,v)

    #define   GET32BLK_partition3(r32)                         _BFGET_(r32,27,26)
    #define   SET32BLK_partition3(r32,v)                       _BFSET_(r32,27,26,v)
    #define   GET16BLK_partition3(r16)                         _BFGET_(r16,11,10)
    #define   SET16BLK_partition3(r16,v)                       _BFSET_(r16,11,10,v)

    #define   GET32BLK_direct3(r32)                            _BFGET_(r32,28,28)
    #define   SET32BLK_direct3(r32,v)                          _BFSET_(r32,28,28,v)
    #define   GET16BLK_direct3(r16)                            _BFGET_(r16,12,12)
    #define   SET16BLK_direct3(r16,v)                          _BFSET_(r16,12,12,v)

    #define   GET32BLK_mvs3(r32)                               _BFGET_(r32,31,29)
    #define   SET32BLK_mvs3(r32,v)                             _BFSET_(r32,31,29,v)
    #define   GET16BLK_mvs3(r16)                               _BFGET_(r16,15,13)
    #define   SET16BLK_mvs3(r16,v)                             _BFSET_(r16,15,13,v)

            UNSG32 u_motion                                    :  2;
            UNSG32 u_partition                                 :  2;
            UNSG32 u_direct                                    :  1;
            UNSG32 u_mvs                                       :  3;
            UNSG32 u_motion1                                   :  2;
            UNSG32 u_partition1                                :  2;
            UNSG32 u_direct1                                   :  1;
            UNSG32 u_mvs1                                      :  3;
            UNSG32 u_motion2                                   :  2;
            UNSG32 u_partition2                                :  2;
            UNSG32 u_direct2                                   :  1;
            UNSG32 u_mvs2                                      :  3;
            UNSG32 u_motion3                                   :  2;
            UNSG32 u_partition3                                :  2;
            UNSG32 u_direct3                                   :  1;
            UNSG32 u_mvs3                                      :  3;
    ///////////////////////////////////////////////////////////
    } SIE_BLK;

    ///////////////////////////////////////////////////////////
     SIGN32 BLK_drvrd(SIE_BLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BLK_drvwr(SIE_BLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BLK_reset(SIE_BLK *p);
     SIGN32 BLK_cmp  (SIE_BLK *p, SIE_BLK *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BLK_check(p,pie,pfx,hLOG) BLK_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BLK_print(p,    pfx,hLOG) BLK_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BLK
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE MV                                       (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 2  motion                    
///                                    ###
///                                    * Derived 8x8 block motion type (direct mode uses 'Bi'), see BLK.motion above
///                                    ###
///               %signed   14 X                         
///                                    ###
///                                    * Horizontal motion vector,
///                                    * Or MVD between parser & syntax processor
///                                    ###
///               %unsigned 3  type                      
///                                    ###
///                                    * Sub-set of mb_type, see MBPROP.type above
///                                    ###
///               %signed   13 Y                         
///                                    ###
///                                    * Vertical motion vector,
///                                    * Or MVD between parser & syntax processor
///                                    * End of MV
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MV
#define h_MV (){}

    #define     BA_MV_motion                                   0x0000
    #define     B16MV_motion                                   0x0000
    #define   LSb32MV_motion                                      0
    #define   LSb16MV_motion                                      0
    #define       bMV_motion                                   2
    #define   MSK32MV_motion                                      0x00000003

    #define     BA_MV_X                                        0x0000
    #define     B16MV_X                                        0x0000
    #define   LSb32MV_X                                           2
    #define   LSb16MV_X                                           2
    #define       bMV_X                                        14
    #define   MSK32MV_X                                           0x0000FFFC

    #define     BA_MV_type                                     0x0002
    #define     B16MV_type                                     0x0002
    #define   LSb32MV_type                                        16
    #define   LSb16MV_type                                        0
    #define       bMV_type                                     3
    #define   MSK32MV_type                                        0x00070000

    #define     BA_MV_Y                                        0x0002
    #define     B16MV_Y                                        0x0002
    #define   LSb32MV_Y                                           19
    #define   LSb16MV_Y                                           3
    #define       bMV_Y                                        13
    #define   MSK32MV_Y                                           0xFFF80000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_MV {
    ///////////////////////////////////////////////////////////
    #define   GET32MV_motion(r32)                              _BFGET_(r32, 1, 0)
    #define   SET32MV_motion(r32,v)                            _BFSET_(r32, 1, 0,v)
    #define   GET16MV_motion(r16)                              _BFGET_(r16, 1, 0)
    #define   SET16MV_motion(r16,v)                            _BFSET_(r16, 1, 0,v)

    #define   GET32MV_X(r32)                                   _BFGET_(r32,15, 2)
    #define   SET32MV_X(r32,v)                                 _BFSET_(r32,15, 2,v)
    #define   GET16MV_X(r16)                                   _BFGET_(r16,15, 2)
    #define   SET16MV_X(r16,v)                                 _BFSET_(r16,15, 2,v)

    #define   GET32MV_type(r32)                                _BFGET_(r32,18,16)
    #define   SET32MV_type(r32,v)                              _BFSET_(r32,18,16,v)
    #define   GET16MV_type(r16)                                _BFGET_(r16, 2, 0)
    #define   SET16MV_type(r16,v)                              _BFSET_(r16, 2, 0,v)

    #define   GET32MV_Y(r32)                                   _BFGET_(r32,31,19)
    #define   SET32MV_Y(r32,v)                                 _BFSET_(r32,31,19,v)
    #define   GET16MV_Y(r16)                                   _BFGET_(r16,15, 3)
    #define   SET16MV_Y(r16,v)                                 _BFSET_(r16,15, 3,v)

            UNSG32 u_motion                                    :  2;
            UNSG32 s_X                                         : 14;
            UNSG32 u_type                                      :  3;
            UNSG32 s_Y                                         : 13;
    ///////////////////////////////////////////////////////////
    } SIE_MV;

    ///////////////////////////////////////////////////////////
     SIGN32 MV_drvrd(SIE_MV *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 MV_drvwr(SIE_MV *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void MV_reset(SIE_MV *p);
     SIGN32 MV_cmp  (SIE_MV *p, SIE_MV *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define MV_check(p,pie,pfx,hLOG) MV_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define MV_print(p,    pfx,hLOG) MV_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: MV
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE FCTX                    biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 6  rBID                      
///                                    ###
///                                    * Flatten 4x4s in each 8x8,
///                                    * 0 for intra (as well as direct mode between parser & syntax processor):
///                                    * Reference buffer ID, last 1b indicates access mode:
///                                    * 0: frame/progressive or top field
///                                    * 1: bottom field
///                                    ###
///               %unsigned 5  rIDX                      
///                                    ###
///                                    * Flatten 4x4s in each 8x8,
///                                    * 0 for intra (as well as P/B-skip & direct mode between parser & syntax processor):
///                                    * Syntax 'RefListIdx' directly decoded from bit stream (field information embedded)
///                                    ###
///               %unsigned 1  FLD                       
///                                    ###
///                                    * Flatten 4x4s in each 8x8:
///                                    * 1 for MBAFF field MB, 0 for otherwise
///                                    ###
///               %unsigned 1  equalpred                 
///                                    ###
///                                    * BLK property for CABAC only:
///                                    * Using block category ACV,
///                                    * (But flatten to all 4x4s in each 8x8s):
///                                    * = !Intra && !skipped && (bi-pred || fore-pred)
///                                    * NOTE: = 0 for direct mode
///                                    * VC-1:
///                                    * PMV output: for hybridPred
///                                    * PMV input: predictor_flag (0: use dominant PMV)
///                                    ###
///               %unsigned 1  transform                 
///                                    ###
///                                    * MB property (flatten in all 4x4s):
///                                    * H.264: if 8x8 transform
///                                    * Others: if field transform
///                                    ###
///               %unsigned 1  NCBPY                     
///                                    ###
///                                    * Loop-filter & CABAC use only:
///                                    * Luma using block category ACV (4th 4x4),
///                                    * (But flatten to all 4x4s in each 8x8s):
///                                    * = !(IPCM || cbp_luma)
///                                    ###
///               %unsigned 1  MixFLG                    
///                                    ###
///                                    * CABAC use only:
///                                    * CBP chroma using block category DCU/DCV,
///                                    * (Only at 3rd & 4th 4x4s in 3rd 8x8):
///                                    * bin[0]: IPCM || !(skipped || (cbp_chroma == 0))
///                                    * bin[1]: IPCM || !(skipped || (cbp_chroma != 2))
///                                    * Or:
///                                    * mb_type using block category DCY,
///                                    * (Only at 4th 4x4 in 4th 8x8):
///                                    * I_SLICE: = !I_NXN
///                                    * P_SLICE: = 0
///                                    * B_SLICE: = !skipped && !direct_16x16
///                                    * Or:
///                                    * intra-chroma_pred using block category DCI,
///                                    * (Only at 3rd 4x4 in 4th 8x8):
///                                    * = Intra && !IPCM && (intra_chroma_pred != 0)
///                                    * Or:
///                                    * Temporal context buffers for direct mode use
///                                    ###
///                                    : 8x8                       0x1
///                                                 ###
///                                                 * Only at 1st 4x4 in 1st 8x8:
///                                                 * = if MB contains no sub-8x8 partition
///                                                 ###
///                                    : 16x16                     0x1
///                                                 ###
///                                                 * Only at 1st 4x4 in 2nd 8x8:
///                                                 * = if MB contains only 1 partition (16x16)
///                                                 ###
///               %unsigned 1  CBFY                      
///                                    ###
///                                    * Loop-filter & CABAC use only:
///                                    * Using block category ACY (every 4x4s):
///                                    * = IPCM || cbf_luma_ac
///                                    ###
///               %unsigned 1  CBFUV                     
///                                    ###
///                                    * CABAC use only:
///                                    * Using block category ACU/ACV,
///                                    * (Only at 3rd & 4th 4x4 in each 8x8s):
///                                    * = IPCM || cbf_chroma_ac
///                                    ###
///               %unsigned 1  CBFDC                     
///                                    ###
///                                    * CABAC use only:
///                                    * LumaDC using block category DCY,
///                                    * (Only at 4th 4x4 in 4th 8x8):
///                                    * = IPCM || (I_16x16 && cbf_luma_dc)
///                                    * ChromaDC using block category DCU/DCV,
///                                    * (Only at 3rd 4x4 in 3rd & 4th 8x8):
///                                    * = IPCM || cbf_chroma_dc
///                                    ###
///               %unsigned 6  ABSMVDX                   
///                                    ###
///                                    * CABAC use only:
///                                    * MIN( ABS(MVD.x), 63 )
///                                    ###
///               %unsigned 7  ABSMVDY                   
///                                    ###
///                                    * CABAC use only:
///                                    * MIN( ABS(MVD.y), 127 )
///                                    ###
///     @ 0x00004                      (P)
///     # 0x00004 mv                   
///               $MV                  mv                REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_FCTX
#define h_FCTX (){}

    #define     BA_FCTX_rBID                                   0x0000
    #define     B16FCTX_rBID                                   0x0000
    #define   LSb32FCTX_rBID                                      0
    #define   LSb16FCTX_rBID                                      0
    #define       bFCTX_rBID                                   6
    #define   MSK32FCTX_rBID                                      0x0000003F

    #define     BA_FCTX_rIDX                                   0x0000
    #define     B16FCTX_rIDX                                   0x0000
    #define   LSb32FCTX_rIDX                                      6
    #define   LSb16FCTX_rIDX                                      6
    #define       bFCTX_rIDX                                   5
    #define   MSK32FCTX_rIDX                                      0x000007C0

    #define     BA_FCTX_FLD                                    0x0001
    #define     B16FCTX_FLD                                    0x0000
    #define   LSb32FCTX_FLD                                       11
    #define   LSb16FCTX_FLD                                       11
    #define       bFCTX_FLD                                    1
    #define   MSK32FCTX_FLD                                       0x00000800

    #define     BA_FCTX_equalpred                              0x0001
    #define     B16FCTX_equalpred                              0x0000
    #define   LSb32FCTX_equalpred                                 12
    #define   LSb16FCTX_equalpred                                 12
    #define       bFCTX_equalpred                              1
    #define   MSK32FCTX_equalpred                                 0x00001000

    #define     BA_FCTX_transform                              0x0001
    #define     B16FCTX_transform                              0x0000
    #define   LSb32FCTX_transform                                 13
    #define   LSb16FCTX_transform                                 13
    #define       bFCTX_transform                              1
    #define   MSK32FCTX_transform                                 0x00002000

    #define     BA_FCTX_NCBPY                                  0x0001
    #define     B16FCTX_NCBPY                                  0x0000
    #define   LSb32FCTX_NCBPY                                     14
    #define   LSb16FCTX_NCBPY                                     14
    #define       bFCTX_NCBPY                                  1
    #define   MSK32FCTX_NCBPY                                     0x00004000

    #define     BA_FCTX_MixFLG                                 0x0001
    #define     B16FCTX_MixFLG                                 0x0000
    #define   LSb32FCTX_MixFLG                                    15
    #define   LSb16FCTX_MixFLG                                    15
    #define       bFCTX_MixFLG                                 1
    #define   MSK32FCTX_MixFLG                                    0x00008000
    #define        FCTX_MixFLG_8x8                                          0x1
    #define        FCTX_MixFLG_16x16                                        0x1

    #define     BA_FCTX_CBFY                                   0x0002
    #define     B16FCTX_CBFY                                   0x0002
    #define   LSb32FCTX_CBFY                                      16
    #define   LSb16FCTX_CBFY                                      0
    #define       bFCTX_CBFY                                   1
    #define   MSK32FCTX_CBFY                                      0x00010000

    #define     BA_FCTX_CBFUV                                  0x0002
    #define     B16FCTX_CBFUV                                  0x0002
    #define   LSb32FCTX_CBFUV                                     17
    #define   LSb16FCTX_CBFUV                                     1
    #define       bFCTX_CBFUV                                  1
    #define   MSK32FCTX_CBFUV                                     0x00020000

    #define     BA_FCTX_CBFDC                                  0x0002
    #define     B16FCTX_CBFDC                                  0x0002
    #define   LSb32FCTX_CBFDC                                     18
    #define   LSb16FCTX_CBFDC                                     2
    #define       bFCTX_CBFDC                                  1
    #define   MSK32FCTX_CBFDC                                     0x00040000

    #define     BA_FCTX_ABSMVDX                                0x0002
    #define     B16FCTX_ABSMVDX                                0x0002
    #define   LSb32FCTX_ABSMVDX                                   19
    #define   LSb16FCTX_ABSMVDX                                   3
    #define       bFCTX_ABSMVDX                                6
    #define   MSK32FCTX_ABSMVDX                                   0x01F80000

    #define     BA_FCTX_ABSMVDY                                0x0003
    #define     B16FCTX_ABSMVDY                                0x0002
    #define   LSb32FCTX_ABSMVDY                                   25
    #define   LSb16FCTX_ABSMVDY                                   9
    #define       bFCTX_ABSMVDY                                7
    #define   MSK32FCTX_ABSMVDY                                   0xFE000000
    ///////////////////////////////////////////////////////////
    #define     RA_FCTX_mv                                     0x0004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_FCTX {
    ///////////////////////////////////////////////////////////
    #define   GET32FCTX_rBID(r32)                              _BFGET_(r32, 5, 0)
    #define   SET32FCTX_rBID(r32,v)                            _BFSET_(r32, 5, 0,v)
    #define   GET16FCTX_rBID(r16)                              _BFGET_(r16, 5, 0)
    #define   SET16FCTX_rBID(r16,v)                            _BFSET_(r16, 5, 0,v)

    #define   GET32FCTX_rIDX(r32)                              _BFGET_(r32,10, 6)
    #define   SET32FCTX_rIDX(r32,v)                            _BFSET_(r32,10, 6,v)
    #define   GET16FCTX_rIDX(r16)                              _BFGET_(r16,10, 6)
    #define   SET16FCTX_rIDX(r16,v)                            _BFSET_(r16,10, 6,v)

    #define   GET32FCTX_FLD(r32)                               _BFGET_(r32,11,11)
    #define   SET32FCTX_FLD(r32,v)                             _BFSET_(r32,11,11,v)
    #define   GET16FCTX_FLD(r16)                               _BFGET_(r16,11,11)
    #define   SET16FCTX_FLD(r16,v)                             _BFSET_(r16,11,11,v)

    #define   GET32FCTX_equalpred(r32)                         _BFGET_(r32,12,12)
    #define   SET32FCTX_equalpred(r32,v)                       _BFSET_(r32,12,12,v)
    #define   GET16FCTX_equalpred(r16)                         _BFGET_(r16,12,12)
    #define   SET16FCTX_equalpred(r16,v)                       _BFSET_(r16,12,12,v)

    #define   GET32FCTX_transform(r32)                         _BFGET_(r32,13,13)
    #define   SET32FCTX_transform(r32,v)                       _BFSET_(r32,13,13,v)
    #define   GET16FCTX_transform(r16)                         _BFGET_(r16,13,13)
    #define   SET16FCTX_transform(r16,v)                       _BFSET_(r16,13,13,v)

    #define   GET32FCTX_NCBPY(r32)                             _BFGET_(r32,14,14)
    #define   SET32FCTX_NCBPY(r32,v)                           _BFSET_(r32,14,14,v)
    #define   GET16FCTX_NCBPY(r16)                             _BFGET_(r16,14,14)
    #define   SET16FCTX_NCBPY(r16,v)                           _BFSET_(r16,14,14,v)

    #define   GET32FCTX_MixFLG(r32)                            _BFGET_(r32,15,15)
    #define   SET32FCTX_MixFLG(r32,v)                          _BFSET_(r32,15,15,v)
    #define   GET16FCTX_MixFLG(r16)                            _BFGET_(r16,15,15)
    #define   SET16FCTX_MixFLG(r16,v)                          _BFSET_(r16,15,15,v)

    #define   GET32FCTX_CBFY(r32)                              _BFGET_(r32,16,16)
    #define   SET32FCTX_CBFY(r32,v)                            _BFSET_(r32,16,16,v)
    #define   GET16FCTX_CBFY(r16)                              _BFGET_(r16, 0, 0)
    #define   SET16FCTX_CBFY(r16,v)                            _BFSET_(r16, 0, 0,v)

    #define   GET32FCTX_CBFUV(r32)                             _BFGET_(r32,17,17)
    #define   SET32FCTX_CBFUV(r32,v)                           _BFSET_(r32,17,17,v)
    #define   GET16FCTX_CBFUV(r16)                             _BFGET_(r16, 1, 1)
    #define   SET16FCTX_CBFUV(r16,v)                           _BFSET_(r16, 1, 1,v)

    #define   GET32FCTX_CBFDC(r32)                             _BFGET_(r32,18,18)
    #define   SET32FCTX_CBFDC(r32,v)                           _BFSET_(r32,18,18,v)
    #define   GET16FCTX_CBFDC(r16)                             _BFGET_(r16, 2, 2)
    #define   SET16FCTX_CBFDC(r16,v)                           _BFSET_(r16, 2, 2,v)

    #define   GET32FCTX_ABSMVDX(r32)                           _BFGET_(r32,24,19)
    #define   SET32FCTX_ABSMVDX(r32,v)                         _BFSET_(r32,24,19,v)
    #define   GET16FCTX_ABSMVDX(r16)                           _BFGET_(r16, 8, 3)
    #define   SET16FCTX_ABSMVDX(r16,v)                         _BFSET_(r16, 8, 3,v)

    #define   GET32FCTX_ABSMVDY(r32)                           _BFGET_(r32,31,25)
    #define   SET32FCTX_ABSMVDY(r32,v)                         _BFSET_(r32,31,25,v)
    #define   GET16FCTX_ABSMVDY(r16)                           _BFGET_(r16,15, 9)
    #define   SET16FCTX_ABSMVDY(r16,v)                         _BFSET_(r16,15, 9,v)

            UNSG32 u_rBID                                      :  6;
            UNSG32 u_rIDX                                      :  5;
            UNSG32 u_FLD                                       :  1;
            UNSG32 u_equalpred                                 :  1;
            UNSG32 u_transform                                 :  1;
            UNSG32 u_NCBPY                                     :  1;
            UNSG32 u_MixFLG                                    :  1;
            UNSG32 u_CBFY                                      :  1;
            UNSG32 u_CBFUV                                     :  1;
            UNSG32 u_CBFDC                                     :  1;
            UNSG32 u_ABSMVDX                                   :  6;
            UNSG32 u_ABSMVDY                                   :  7;
    ///////////////////////////////////////////////////////////
              SIE_MV                                           ie_mv;
    ///////////////////////////////////////////////////////////
    } SIE_FCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 FCTX_drvrd(SIE_FCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 FCTX_drvwr(SIE_FCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void FCTX_reset(SIE_FCTX *p);
     SIGN32 FCTX_cmp  (SIE_FCTX *p, SIE_FCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define FCTX_check(p,pie,pfx,hLOG) FCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define FCTX_print(p,    pfx,hLOG) FCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: FCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE FCTX_VC1                biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 6  rBID                      
///                                    ###
///                                    * Flatten 4x4s in each 8x8,
///                                    * 0 for intra (as well as direct mode between parser & syntax processor):
///                                    * Reference buffer ID, last 1b indicates access mode:
///                                    * 0: frame/progressive or top field
///                                    * 1: bottom field
///                                    ###
///               %unsigned 5  rIDX                      
///                                    ###
///                                    * Flatten 4x4s in each 8x8,
///                                    * 0 for intra (as well as P/B-skip & direct mode between parser & syntax processor):
///                                    * Syntax 'RefListIdx' directly decoded from bit stream (field information embedded)
///                                    ###
///               %unsigned 1  FLD                       
///                                    ###
///                                    * Flatten 4x4s in each 8x8:
///                                    * 1 for MBAFF field MB, 0 for otherwise
///                                    ###
///               %unsigned 1  equalpred                 
///                                    ###
///                                    * BLK property for CABAC only:
///                                    * Using block category ACV,
///                                    * (But flatten to all 4x4s in each 8x8s):
///                                    * = !Intra && !skipped && (bi-pred || fore-pred)
///                                    * NOTE: = 0 for direct mode
///                                    * VC-1:
///                                    * PMV output: for hybridPred
///                                    * PMV input: predictor_flag (0: use dominant PMV)
///                                    ###
///               %unsigned 1  transform                 
///                                    ###
///                                    * MB property (flatten in all 4x4s):
///                                    * H.264: if 8x8 transform
///                                    * Others: if field transform
///                                    ###
///               %unsigned 1  NCBPY                     
///                                    ###
///                                    * Loop-filter & CABAC use only:
///                                    * Luma using block category ACV (4th 4x4),
///                                    * (But flatten to all 4x4s in each 8x8s):
///                                    * = !(IPCM || cbp_luma)
///                                    ###
///               %unsigned 1  MixFLG                    
///                                    ###
///                                    * CABAC use only:
///                                    * CBP chroma using block category DCU/DCV,
///                                    * (Only at 3rd & 4th 4x4s in 3rd 8x8):
///                                    * bin[0]: IPCM || !(skipped || (cbp_chroma == 0))
///                                    * bin[1]: IPCM || !(skipped || (cbp_chroma != 2))
///                                    * Or:
///                                    * mb_type using block category DCY,
///                                    * (Only at 4th 4x4 in 4th 8x8):
///                                    * I_SLICE: = !I_NXN
///                                    * P_SLICE: = 0
///                                    * B_SLICE: = !skipped && !direct_16x16
///                                    * Or:
///                                    * intra-chroma_pred using block category DCI,
///                                    * (Only at 3rd 4x4 in 4th 8x8):
///                                    * = Intra && !IPCM && (intra_chroma_pred != 0)
///                                    * Or:
///                                    * Temporal context buffers for direct mode use
///                                    ###
///                                    : 8x8                       0x1
///                                                 ###
///                                                 * Only at 1st 4x4 in 1st 8x8:
///                                                 * = if MB contains no sub-8x8 partition
///                                                 ###
///                                    : 16x16                     0x1
///                                                 ###
///                                                 * Only at 1st 4x4 in 2nd 8x8:
///                                                 * = if MB contains only 1 partition (16x16)
///                                                 ###
///               %unsigned 2  dctSelY                   
///                                    : 4x4                       0x0
///                                    : 8x8                       0x1
///                                    : 4x8                       0x2
///                                    : 8x4                       0x3
///                                                 ###
///                                                 * DCT transform type for Y, used for VC-1 Fop
///                                                 * flattened to all 4x4 blocks within transform block
///                                                 ###
///               %unsigned 1  CBFY                      
///                                    ###
///                                    * coded block (4x4) flag for Y, used for VC-1 Fop
///                                    ###
///               %unsigned 1  CBFY8x8                   
///                                    ###
///                                    * coded block (8x8) flag for Y, used for VC-1 MP Fop
///                                    ###
///               %unsigned 12 RSVD12                    
///     @ 0x00004                      (P)
///     # 0x00004 mv                   
///               $MV                  mv                REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_FCTX_VC1
#define h_FCTX_VC1 (){}

    #define     BA_FCTX_VC1_rBID                               0x0000
    #define     B16FCTX_VC1_rBID                               0x0000
    #define   LSb32FCTX_VC1_rBID                                  0
    #define   LSb16FCTX_VC1_rBID                                  0
    #define       bFCTX_VC1_rBID                               6
    #define   MSK32FCTX_VC1_rBID                                  0x0000003F

    #define     BA_FCTX_VC1_rIDX                               0x0000
    #define     B16FCTX_VC1_rIDX                               0x0000
    #define   LSb32FCTX_VC1_rIDX                                  6
    #define   LSb16FCTX_VC1_rIDX                                  6
    #define       bFCTX_VC1_rIDX                               5
    #define   MSK32FCTX_VC1_rIDX                                  0x000007C0

    #define     BA_FCTX_VC1_FLD                                0x0001
    #define     B16FCTX_VC1_FLD                                0x0000
    #define   LSb32FCTX_VC1_FLD                                   11
    #define   LSb16FCTX_VC1_FLD                                   11
    #define       bFCTX_VC1_FLD                                1
    #define   MSK32FCTX_VC1_FLD                                   0x00000800

    #define     BA_FCTX_VC1_equalpred                          0x0001
    #define     B16FCTX_VC1_equalpred                          0x0000
    #define   LSb32FCTX_VC1_equalpred                             12
    #define   LSb16FCTX_VC1_equalpred                             12
    #define       bFCTX_VC1_equalpred                          1
    #define   MSK32FCTX_VC1_equalpred                             0x00001000

    #define     BA_FCTX_VC1_transform                          0x0001
    #define     B16FCTX_VC1_transform                          0x0000
    #define   LSb32FCTX_VC1_transform                             13
    #define   LSb16FCTX_VC1_transform                             13
    #define       bFCTX_VC1_transform                          1
    #define   MSK32FCTX_VC1_transform                             0x00002000

    #define     BA_FCTX_VC1_NCBPY                              0x0001
    #define     B16FCTX_VC1_NCBPY                              0x0000
    #define   LSb32FCTX_VC1_NCBPY                                 14
    #define   LSb16FCTX_VC1_NCBPY                                 14
    #define       bFCTX_VC1_NCBPY                              1
    #define   MSK32FCTX_VC1_NCBPY                                 0x00004000

    #define     BA_FCTX_VC1_MixFLG                             0x0001
    #define     B16FCTX_VC1_MixFLG                             0x0000
    #define   LSb32FCTX_VC1_MixFLG                                15
    #define   LSb16FCTX_VC1_MixFLG                                15
    #define       bFCTX_VC1_MixFLG                             1
    #define   MSK32FCTX_VC1_MixFLG                                0x00008000
    #define        FCTX_VC1_MixFLG_8x8                                      0x1
    #define        FCTX_VC1_MixFLG_16x16                                    0x1

    #define     BA_FCTX_VC1_dctSelY                            0x0002
    #define     B16FCTX_VC1_dctSelY                            0x0002
    #define   LSb32FCTX_VC1_dctSelY                               16
    #define   LSb16FCTX_VC1_dctSelY                               0
    #define       bFCTX_VC1_dctSelY                            2
    #define   MSK32FCTX_VC1_dctSelY                               0x00030000
    #define        FCTX_VC1_dctSelY_4x4                                     0x0
    #define        FCTX_VC1_dctSelY_8x8                                     0x1
    #define        FCTX_VC1_dctSelY_4x8                                     0x2
    #define        FCTX_VC1_dctSelY_8x4                                     0x3

    #define     BA_FCTX_VC1_CBFY                               0x0002
    #define     B16FCTX_VC1_CBFY                               0x0002
    #define   LSb32FCTX_VC1_CBFY                                  18
    #define   LSb16FCTX_VC1_CBFY                                  2
    #define       bFCTX_VC1_CBFY                               1
    #define   MSK32FCTX_VC1_CBFY                                  0x00040000

    #define     BA_FCTX_VC1_CBFY8x8                            0x0002
    #define     B16FCTX_VC1_CBFY8x8                            0x0002
    #define   LSb32FCTX_VC1_CBFY8x8                               19
    #define   LSb16FCTX_VC1_CBFY8x8                               3
    #define       bFCTX_VC1_CBFY8x8                            1
    #define   MSK32FCTX_VC1_CBFY8x8                               0x00080000

    #define     BA_FCTX_VC1_RSVD12                             0x0002
    #define     B16FCTX_VC1_RSVD12                             0x0002
    #define   LSb32FCTX_VC1_RSVD12                                20
    #define   LSb16FCTX_VC1_RSVD12                                4
    #define       bFCTX_VC1_RSVD12                             12
    #define   MSK32FCTX_VC1_RSVD12                                0xFFF00000
    ///////////////////////////////////////////////////////////
    #define     RA_FCTX_VC1_mv                                 0x0004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_FCTX_VC1 {
    ///////////////////////////////////////////////////////////
    #define   GET32FCTX_VC1_rBID(r32)                          _BFGET_(r32, 5, 0)
    #define   SET32FCTX_VC1_rBID(r32,v)                        _BFSET_(r32, 5, 0,v)
    #define   GET16FCTX_VC1_rBID(r16)                          _BFGET_(r16, 5, 0)
    #define   SET16FCTX_VC1_rBID(r16,v)                        _BFSET_(r16, 5, 0,v)

    #define   GET32FCTX_VC1_rIDX(r32)                          _BFGET_(r32,10, 6)
    #define   SET32FCTX_VC1_rIDX(r32,v)                        _BFSET_(r32,10, 6,v)
    #define   GET16FCTX_VC1_rIDX(r16)                          _BFGET_(r16,10, 6)
    #define   SET16FCTX_VC1_rIDX(r16,v)                        _BFSET_(r16,10, 6,v)

    #define   GET32FCTX_VC1_FLD(r32)                           _BFGET_(r32,11,11)
    #define   SET32FCTX_VC1_FLD(r32,v)                         _BFSET_(r32,11,11,v)
    #define   GET16FCTX_VC1_FLD(r16)                           _BFGET_(r16,11,11)
    #define   SET16FCTX_VC1_FLD(r16,v)                         _BFSET_(r16,11,11,v)

    #define   GET32FCTX_VC1_equalpred(r32)                     _BFGET_(r32,12,12)
    #define   SET32FCTX_VC1_equalpred(r32,v)                   _BFSET_(r32,12,12,v)
    #define   GET16FCTX_VC1_equalpred(r16)                     _BFGET_(r16,12,12)
    #define   SET16FCTX_VC1_equalpred(r16,v)                   _BFSET_(r16,12,12,v)

    #define   GET32FCTX_VC1_transform(r32)                     _BFGET_(r32,13,13)
    #define   SET32FCTX_VC1_transform(r32,v)                   _BFSET_(r32,13,13,v)
    #define   GET16FCTX_VC1_transform(r16)                     _BFGET_(r16,13,13)
    #define   SET16FCTX_VC1_transform(r16,v)                   _BFSET_(r16,13,13,v)

    #define   GET32FCTX_VC1_NCBPY(r32)                         _BFGET_(r32,14,14)
    #define   SET32FCTX_VC1_NCBPY(r32,v)                       _BFSET_(r32,14,14,v)
    #define   GET16FCTX_VC1_NCBPY(r16)                         _BFGET_(r16,14,14)
    #define   SET16FCTX_VC1_NCBPY(r16,v)                       _BFSET_(r16,14,14,v)

    #define   GET32FCTX_VC1_MixFLG(r32)                        _BFGET_(r32,15,15)
    #define   SET32FCTX_VC1_MixFLG(r32,v)                      _BFSET_(r32,15,15,v)
    #define   GET16FCTX_VC1_MixFLG(r16)                        _BFGET_(r16,15,15)
    #define   SET16FCTX_VC1_MixFLG(r16,v)                      _BFSET_(r16,15,15,v)

    #define   GET32FCTX_VC1_dctSelY(r32)                       _BFGET_(r32,17,16)
    #define   SET32FCTX_VC1_dctSelY(r32,v)                     _BFSET_(r32,17,16,v)
    #define   GET16FCTX_VC1_dctSelY(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16FCTX_VC1_dctSelY(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32FCTX_VC1_CBFY(r32)                          _BFGET_(r32,18,18)
    #define   SET32FCTX_VC1_CBFY(r32,v)                        _BFSET_(r32,18,18,v)
    #define   GET16FCTX_VC1_CBFY(r16)                          _BFGET_(r16, 2, 2)
    #define   SET16FCTX_VC1_CBFY(r16,v)                        _BFSET_(r16, 2, 2,v)

    #define   GET32FCTX_VC1_CBFY8x8(r32)                       _BFGET_(r32,19,19)
    #define   SET32FCTX_VC1_CBFY8x8(r32,v)                     _BFSET_(r32,19,19,v)
    #define   GET16FCTX_VC1_CBFY8x8(r16)                       _BFGET_(r16, 3, 3)
    #define   SET16FCTX_VC1_CBFY8x8(r16,v)                     _BFSET_(r16, 3, 3,v)

    #define   GET32FCTX_VC1_RSVD12(r32)                        _BFGET_(r32,31,20)
    #define   SET32FCTX_VC1_RSVD12(r32,v)                      _BFSET_(r32,31,20,v)
    #define   GET16FCTX_VC1_RSVD12(r16)                        _BFGET_(r16,15, 4)
    #define   SET16FCTX_VC1_RSVD12(r16,v)                      _BFSET_(r16,15, 4,v)

            UNSG32 u_rBID                                      :  6;
            UNSG32 u_rIDX                                      :  5;
            UNSG32 u_FLD                                       :  1;
            UNSG32 u_equalpred                                 :  1;
            UNSG32 u_transform                                 :  1;
            UNSG32 u_NCBPY                                     :  1;
            UNSG32 u_MixFLG                                    :  1;
            UNSG32 u_dctSelY                                   :  2;
            UNSG32 u_CBFY                                      :  1;
            UNSG32 u_CBFY8x8                                   :  1;
            UNSG32 u_RSVD12                                    : 12;
    ///////////////////////////////////////////////////////////
              SIE_MV                                           ie_mv;
    ///////////////////////////////////////////////////////////
    } SIE_FCTX_VC1;

    ///////////////////////////////////////////////////////////
     SIGN32 FCTX_VC1_drvrd(SIE_FCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 FCTX_VC1_drvwr(SIE_FCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void FCTX_VC1_reset(SIE_FCTX_VC1 *p);
     SIGN32 FCTX_VC1_cmp  (SIE_FCTX_VC1 *p, SIE_FCTX_VC1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define FCTX_VC1_check(p,pie,pfx,hLOG) FCTX_VC1_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define FCTX_VC1_print(p,    pfx,hLOG) FCTX_VC1_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: FCTX_VC1
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE FCTX_RV9                biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 6  rBID                      
///                                    ###
///                                    * Flatten 4x4s in each 8x8,
///                                    * 0 for intra (as well as direct mode between parser & syntax processor):
///                                    * Reference buffer ID, last 1b indicates access mode:
///                                    * 0: frame/progressive or top field
///                                    * 1: bottom field
///                                    ###
///               %unsigned 5  rIDX                      
///                                    ###
///                                    * Flatten 4x4s in each 8x8,
///                                    * 0 for intra (as well as P/B-skip & direct mode between parser & syntax processor):
///                                    * Syntax 'RefListIdx' directly decoded from bit stream (field information embedded)
///                                    ###
///               %unsigned 1  FLD                       
///                                    ###
///                                    * Flatten 4x4s in each 8x8:
///                                    * 1 for MBAFF field MB, 0 for otherwise
///                                    ###
///               %unsigned 1  equalpred                 
///                                    ###
///                                    * BLK property for CABAC only:
///                                    * Using block category ACV,
///                                    * (But flatten to all 4x4s in each 8x8s):
///                                    * = !Intra && !skipped && (bi-pred || fore-pred)
///                                    * NOTE: = 0 for direct mode
///                                    * VC-1:
///                                    * PMV output: for hybridPred
///                                    * PMV input: predictor_flag (0: use dominant PMV)
///                                    ###
///               %unsigned 1  transform                 
///                                    ###
///                                    * MB property (flatten in all 4x4s):
///                                    * H.264: if 8x8 transform
///                                    * Others: if field transform
///                                    ###
///               %unsigned 1  NCBPY                     
///                                    ###
///                                    * Loop-filter & CABAC use only:
///                                    * Luma using block category ACV (4th 4x4),
///                                    * (But flatten to all 4x4s in each 8x8s):
///                                    * = !(IPCM || cbp_luma)
///                                    ###
///               %unsigned 1  MixFLG                    
///                                    ###
///                                    * CABAC use only:
///                                    * CBP chroma using block category DCU/DCV,
///                                    * (Only at 3rd & 4th 4x4s in 3rd 8x8):
///                                    * bin[0]: IPCM || !(skipped || (cbp_chroma == 0))
///                                    * bin[1]: IPCM || !(skipped || (cbp_chroma != 2))
///                                    * Or:
///                                    * mb_type using block category DCY,
///                                    * (Only at 4th 4x4 in 4th 8x8):
///                                    * I_SLICE: = !I_NXN
///                                    * P_SLICE: = 0
///                                    * B_SLICE: = !skipped && !direct_16x16
///                                    * Or:
///                                    * intra-chroma_pred using block category DCI,
///                                    * (Only at 3rd 4x4 in 4th 8x8):
///                                    * = Intra && !IPCM && (intra_chroma_pred != 0)
///                                    * Or:
///                                    * Temporal context buffers for direct mode use
///                                    ###
///                                    : 8x8                       0x1
///                                                 ###
///                                                 * Only at 1st 4x4 in 1st 8x8:
///                                                 * = if MB contains no sub-8x8 partition
///                                                 ###
///                                    : 16x16                     0x1
///                                                 ###
///                                                 * Only at 1st 4x4 in 2nd 8x8:
///                                                 * = if MB contains only 1 partition (16x16)
///                                                 ###
///               %unsigned 1  CBPY                      
///                                    ###
///                                    * CBP for Y
///                                    ###
///               %unsigned 1  CBPU                      
///                                    ###
///                                    * CBP for U
///                                    ###
///               %unsigned 1  CBPV                      
///                                    ###
///                                    * CBP for Y
///                                    ###
///               %unsigned 2  BsY                       
///                                    ###
///                                    * Block strength for Y
///                                    ###
///               %unsigned 2  BsU                       
///                                    ###
///                                    * Block strength for U
///                                    ###
///               %unsigned 2  BsV                       
///                                    ###
///                                    * Block strength for V
///                                    ###
///               %unsigned 7  Rsvd                      
///                                    ###
///                                    * Reserved
///                                    ###
///     @ 0x00004                      (P)
///     # 0x00004 mv                   
///               $MV                  mv                REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_FCTX_RV9
#define h_FCTX_RV9 (){}

    #define     BA_FCTX_RV9_rBID                               0x0000
    #define     B16FCTX_RV9_rBID                               0x0000
    #define   LSb32FCTX_RV9_rBID                                  0
    #define   LSb16FCTX_RV9_rBID                                  0
    #define       bFCTX_RV9_rBID                               6
    #define   MSK32FCTX_RV9_rBID                                  0x0000003F

    #define     BA_FCTX_RV9_rIDX                               0x0000
    #define     B16FCTX_RV9_rIDX                               0x0000
    #define   LSb32FCTX_RV9_rIDX                                  6
    #define   LSb16FCTX_RV9_rIDX                                  6
    #define       bFCTX_RV9_rIDX                               5
    #define   MSK32FCTX_RV9_rIDX                                  0x000007C0

    #define     BA_FCTX_RV9_FLD                                0x0001
    #define     B16FCTX_RV9_FLD                                0x0000
    #define   LSb32FCTX_RV9_FLD                                   11
    #define   LSb16FCTX_RV9_FLD                                   11
    #define       bFCTX_RV9_FLD                                1
    #define   MSK32FCTX_RV9_FLD                                   0x00000800

    #define     BA_FCTX_RV9_equalpred                          0x0001
    #define     B16FCTX_RV9_equalpred                          0x0000
    #define   LSb32FCTX_RV9_equalpred                             12
    #define   LSb16FCTX_RV9_equalpred                             12
    #define       bFCTX_RV9_equalpred                          1
    #define   MSK32FCTX_RV9_equalpred                             0x00001000

    #define     BA_FCTX_RV9_transform                          0x0001
    #define     B16FCTX_RV9_transform                          0x0000
    #define   LSb32FCTX_RV9_transform                             13
    #define   LSb16FCTX_RV9_transform                             13
    #define       bFCTX_RV9_transform                          1
    #define   MSK32FCTX_RV9_transform                             0x00002000

    #define     BA_FCTX_RV9_NCBPY                              0x0001
    #define     B16FCTX_RV9_NCBPY                              0x0000
    #define   LSb32FCTX_RV9_NCBPY                                 14
    #define   LSb16FCTX_RV9_NCBPY                                 14
    #define       bFCTX_RV9_NCBPY                              1
    #define   MSK32FCTX_RV9_NCBPY                                 0x00004000

    #define     BA_FCTX_RV9_MixFLG                             0x0001
    #define     B16FCTX_RV9_MixFLG                             0x0000
    #define   LSb32FCTX_RV9_MixFLG                                15
    #define   LSb16FCTX_RV9_MixFLG                                15
    #define       bFCTX_RV9_MixFLG                             1
    #define   MSK32FCTX_RV9_MixFLG                                0x00008000
    #define        FCTX_RV9_MixFLG_8x8                                      0x1
    #define        FCTX_RV9_MixFLG_16x16                                    0x1

    #define     BA_FCTX_RV9_CBPY                               0x0002
    #define     B16FCTX_RV9_CBPY                               0x0002
    #define   LSb32FCTX_RV9_CBPY                                  16
    #define   LSb16FCTX_RV9_CBPY                                  0
    #define       bFCTX_RV9_CBPY                               1
    #define   MSK32FCTX_RV9_CBPY                                  0x00010000

    #define     BA_FCTX_RV9_CBPU                               0x0002
    #define     B16FCTX_RV9_CBPU                               0x0002
    #define   LSb32FCTX_RV9_CBPU                                  17
    #define   LSb16FCTX_RV9_CBPU                                  1
    #define       bFCTX_RV9_CBPU                               1
    #define   MSK32FCTX_RV9_CBPU                                  0x00020000

    #define     BA_FCTX_RV9_CBPV                               0x0002
    #define     B16FCTX_RV9_CBPV                               0x0002
    #define   LSb32FCTX_RV9_CBPV                                  18
    #define   LSb16FCTX_RV9_CBPV                                  2
    #define       bFCTX_RV9_CBPV                               1
    #define   MSK32FCTX_RV9_CBPV                                  0x00040000

    #define     BA_FCTX_RV9_BsY                                0x0002
    #define     B16FCTX_RV9_BsY                                0x0002
    #define   LSb32FCTX_RV9_BsY                                   19
    #define   LSb16FCTX_RV9_BsY                                   3
    #define       bFCTX_RV9_BsY                                2
    #define   MSK32FCTX_RV9_BsY                                   0x00180000

    #define     BA_FCTX_RV9_BsU                                0x0002
    #define     B16FCTX_RV9_BsU                                0x0002
    #define   LSb32FCTX_RV9_BsU                                   21
    #define   LSb16FCTX_RV9_BsU                                   5
    #define       bFCTX_RV9_BsU                                2
    #define   MSK32FCTX_RV9_BsU                                   0x00600000

    #define     BA_FCTX_RV9_BsV                                0x0002
    #define     B16FCTX_RV9_BsV                                0x0002
    #define   LSb32FCTX_RV9_BsV                                   23
    #define   LSb16FCTX_RV9_BsV                                   7
    #define       bFCTX_RV9_BsV                                2
    #define   MSK32FCTX_RV9_BsV                                   0x01800000

    #define     BA_FCTX_RV9_Rsvd                               0x0003
    #define     B16FCTX_RV9_Rsvd                               0x0002
    #define   LSb32FCTX_RV9_Rsvd                                  25
    #define   LSb16FCTX_RV9_Rsvd                                  9
    #define       bFCTX_RV9_Rsvd                               7
    #define   MSK32FCTX_RV9_Rsvd                                  0xFE000000
    ///////////////////////////////////////////////////////////
    #define     RA_FCTX_RV9_mv                                 0x0004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_FCTX_RV9 {
    ///////////////////////////////////////////////////////////
    #define   GET32FCTX_RV9_rBID(r32)                          _BFGET_(r32, 5, 0)
    #define   SET32FCTX_RV9_rBID(r32,v)                        _BFSET_(r32, 5, 0,v)
    #define   GET16FCTX_RV9_rBID(r16)                          _BFGET_(r16, 5, 0)
    #define   SET16FCTX_RV9_rBID(r16,v)                        _BFSET_(r16, 5, 0,v)

    #define   GET32FCTX_RV9_rIDX(r32)                          _BFGET_(r32,10, 6)
    #define   SET32FCTX_RV9_rIDX(r32,v)                        _BFSET_(r32,10, 6,v)
    #define   GET16FCTX_RV9_rIDX(r16)                          _BFGET_(r16,10, 6)
    #define   SET16FCTX_RV9_rIDX(r16,v)                        _BFSET_(r16,10, 6,v)

    #define   GET32FCTX_RV9_FLD(r32)                           _BFGET_(r32,11,11)
    #define   SET32FCTX_RV9_FLD(r32,v)                         _BFSET_(r32,11,11,v)
    #define   GET16FCTX_RV9_FLD(r16)                           _BFGET_(r16,11,11)
    #define   SET16FCTX_RV9_FLD(r16,v)                         _BFSET_(r16,11,11,v)

    #define   GET32FCTX_RV9_equalpred(r32)                     _BFGET_(r32,12,12)
    #define   SET32FCTX_RV9_equalpred(r32,v)                   _BFSET_(r32,12,12,v)
    #define   GET16FCTX_RV9_equalpred(r16)                     _BFGET_(r16,12,12)
    #define   SET16FCTX_RV9_equalpred(r16,v)                   _BFSET_(r16,12,12,v)

    #define   GET32FCTX_RV9_transform(r32)                     _BFGET_(r32,13,13)
    #define   SET32FCTX_RV9_transform(r32,v)                   _BFSET_(r32,13,13,v)
    #define   GET16FCTX_RV9_transform(r16)                     _BFGET_(r16,13,13)
    #define   SET16FCTX_RV9_transform(r16,v)                   _BFSET_(r16,13,13,v)

    #define   GET32FCTX_RV9_NCBPY(r32)                         _BFGET_(r32,14,14)
    #define   SET32FCTX_RV9_NCBPY(r32,v)                       _BFSET_(r32,14,14,v)
    #define   GET16FCTX_RV9_NCBPY(r16)                         _BFGET_(r16,14,14)
    #define   SET16FCTX_RV9_NCBPY(r16,v)                       _BFSET_(r16,14,14,v)

    #define   GET32FCTX_RV9_MixFLG(r32)                        _BFGET_(r32,15,15)
    #define   SET32FCTX_RV9_MixFLG(r32,v)                      _BFSET_(r32,15,15,v)
    #define   GET16FCTX_RV9_MixFLG(r16)                        _BFGET_(r16,15,15)
    #define   SET16FCTX_RV9_MixFLG(r16,v)                      _BFSET_(r16,15,15,v)

    #define   GET32FCTX_RV9_CBPY(r32)                          _BFGET_(r32,16,16)
    #define   SET32FCTX_RV9_CBPY(r32,v)                        _BFSET_(r32,16,16,v)
    #define   GET16FCTX_RV9_CBPY(r16)                          _BFGET_(r16, 0, 0)
    #define   SET16FCTX_RV9_CBPY(r16,v)                        _BFSET_(r16, 0, 0,v)

    #define   GET32FCTX_RV9_CBPU(r32)                          _BFGET_(r32,17,17)
    #define   SET32FCTX_RV9_CBPU(r32,v)                        _BFSET_(r32,17,17,v)
    #define   GET16FCTX_RV9_CBPU(r16)                          _BFGET_(r16, 1, 1)
    #define   SET16FCTX_RV9_CBPU(r16,v)                        _BFSET_(r16, 1, 1,v)

    #define   GET32FCTX_RV9_CBPV(r32)                          _BFGET_(r32,18,18)
    #define   SET32FCTX_RV9_CBPV(r32,v)                        _BFSET_(r32,18,18,v)
    #define   GET16FCTX_RV9_CBPV(r16)                          _BFGET_(r16, 2, 2)
    #define   SET16FCTX_RV9_CBPV(r16,v)                        _BFSET_(r16, 2, 2,v)

    #define   GET32FCTX_RV9_BsY(r32)                           _BFGET_(r32,20,19)
    #define   SET32FCTX_RV9_BsY(r32,v)                         _BFSET_(r32,20,19,v)
    #define   GET16FCTX_RV9_BsY(r16)                           _BFGET_(r16, 4, 3)
    #define   SET16FCTX_RV9_BsY(r16,v)                         _BFSET_(r16, 4, 3,v)

    #define   GET32FCTX_RV9_BsU(r32)                           _BFGET_(r32,22,21)
    #define   SET32FCTX_RV9_BsU(r32,v)                         _BFSET_(r32,22,21,v)
    #define   GET16FCTX_RV9_BsU(r16)                           _BFGET_(r16, 6, 5)
    #define   SET16FCTX_RV9_BsU(r16,v)                         _BFSET_(r16, 6, 5,v)

    #define   GET32FCTX_RV9_BsV(r32)                           _BFGET_(r32,24,23)
    #define   SET32FCTX_RV9_BsV(r32,v)                         _BFSET_(r32,24,23,v)
    #define   GET16FCTX_RV9_BsV(r16)                           _BFGET_(r16, 8, 7)
    #define   SET16FCTX_RV9_BsV(r16,v)                         _BFSET_(r16, 8, 7,v)

    #define   GET32FCTX_RV9_Rsvd(r32)                          _BFGET_(r32,31,25)
    #define   SET32FCTX_RV9_Rsvd(r32,v)                        _BFSET_(r32,31,25,v)
    #define   GET16FCTX_RV9_Rsvd(r16)                          _BFGET_(r16,15, 9)
    #define   SET16FCTX_RV9_Rsvd(r16,v)                        _BFSET_(r16,15, 9,v)

            UNSG32 u_rBID                                      :  6;
            UNSG32 u_rIDX                                      :  5;
            UNSG32 u_FLD                                       :  1;
            UNSG32 u_equalpred                                 :  1;
            UNSG32 u_transform                                 :  1;
            UNSG32 u_NCBPY                                     :  1;
            UNSG32 u_MixFLG                                    :  1;
            UNSG32 u_CBPY                                      :  1;
            UNSG32 u_CBPU                                      :  1;
            UNSG32 u_CBPV                                      :  1;
            UNSG32 u_BsY                                       :  2;
            UNSG32 u_BsU                                       :  2;
            UNSG32 u_BsV                                       :  2;
            UNSG32 u_Rsvd                                      :  7;
    ///////////////////////////////////////////////////////////
              SIE_MV                                           ie_mv;
    ///////////////////////////////////////////////////////////
    } SIE_FCTX_RV9;

    ///////////////////////////////////////////////////////////
     SIGN32 FCTX_RV9_drvrd(SIE_FCTX_RV9 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 FCTX_RV9_drvwr(SIE_FCTX_RV9 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void FCTX_RV9_reset(SIE_FCTX_RV9 *p);
     SIGN32 FCTX_RV9_cmp  (SIE_FCTX_RV9 *p, SIE_FCTX_RV9 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define FCTX_RV9_check(p,pie,pfx,hLOG) FCTX_RV9_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define FCTX_RV9_print(p,    pfx,hLOG) FCTX_RV9_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: FCTX_RV9
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BCTX                    biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 6  rBID                      
///               %unsigned 5  rIDX                      
///               %unsigned 1  FLD                       
///               %unsigned 1  equalpred                 
///                                    ###
///                                    * BLK property for CABAC only:
///                                    * Using block category ACV,
///                                    * (Only at 4th 4x4 in each 8x8s):
///                                    * = !Intra && !skipped && (bi-pred || back-pred)
///                                    * NOTE: = 0 for direct mode
///                                    ###
///               %unsigned 3  RSVD                      
///                                    ###
///                                    * Reserved
///                                    ###
///               %unsigned 3  dctSel                    
///                                    : 8x8                       0x0
///                                    : 8x4                       0x1
///                                    : 4x8                       0x2
///                                    : 4x4                       0x3
///                                                 ###
///                                                 * VC-1 use only
///                                                 ###
///               %unsigned 6  ABSMVDX                   
///               %unsigned 7  ABSMVDY                   
///     @ 0x00004                      (P)
///     # 0x00004 mv                   
///               $MV                  mv                REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BCTX
#define h_BCTX (){}

    #define     BA_BCTX_rBID                                   0x0000
    #define     B16BCTX_rBID                                   0x0000
    #define   LSb32BCTX_rBID                                      0
    #define   LSb16BCTX_rBID                                      0
    #define       bBCTX_rBID                                   6
    #define   MSK32BCTX_rBID                                      0x0000003F

    #define     BA_BCTX_rIDX                                   0x0000
    #define     B16BCTX_rIDX                                   0x0000
    #define   LSb32BCTX_rIDX                                      6
    #define   LSb16BCTX_rIDX                                      6
    #define       bBCTX_rIDX                                   5
    #define   MSK32BCTX_rIDX                                      0x000007C0

    #define     BA_BCTX_FLD                                    0x0001
    #define     B16BCTX_FLD                                    0x0000
    #define   LSb32BCTX_FLD                                       11
    #define   LSb16BCTX_FLD                                       11
    #define       bBCTX_FLD                                    1
    #define   MSK32BCTX_FLD                                       0x00000800

    #define     BA_BCTX_equalpred                              0x0001
    #define     B16BCTX_equalpred                              0x0000
    #define   LSb32BCTX_equalpred                                 12
    #define   LSb16BCTX_equalpred                                 12
    #define       bBCTX_equalpred                              1
    #define   MSK32BCTX_equalpred                                 0x00001000

    #define     BA_BCTX_RSVD                                   0x0001
    #define     B16BCTX_RSVD                                   0x0000
    #define   LSb32BCTX_RSVD                                      13
    #define   LSb16BCTX_RSVD                                      13
    #define       bBCTX_RSVD                                   3
    #define   MSK32BCTX_RSVD                                      0x0000E000

    #define     BA_BCTX_dctSel                                 0x0002
    #define     B16BCTX_dctSel                                 0x0002
    #define   LSb32BCTX_dctSel                                    16
    #define   LSb16BCTX_dctSel                                    0
    #define       bBCTX_dctSel                                 3
    #define   MSK32BCTX_dctSel                                    0x00070000
    #define        BCTX_dctSel_8x8                                          0x0
    #define        BCTX_dctSel_8x4                                          0x1
    #define        BCTX_dctSel_4x8                                          0x2
    #define        BCTX_dctSel_4x4                                          0x3

    #define     BA_BCTX_ABSMVDX                                0x0002
    #define     B16BCTX_ABSMVDX                                0x0002
    #define   LSb32BCTX_ABSMVDX                                   19
    #define   LSb16BCTX_ABSMVDX                                   3
    #define       bBCTX_ABSMVDX                                6
    #define   MSK32BCTX_ABSMVDX                                   0x01F80000

    #define     BA_BCTX_ABSMVDY                                0x0003
    #define     B16BCTX_ABSMVDY                                0x0002
    #define   LSb32BCTX_ABSMVDY                                   25
    #define   LSb16BCTX_ABSMVDY                                   9
    #define       bBCTX_ABSMVDY                                7
    #define   MSK32BCTX_ABSMVDY                                   0xFE000000
    ///////////////////////////////////////////////////////////
    #define     RA_BCTX_mv                                     0x0004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BCTX {
    ///////////////////////////////////////////////////////////
    #define   GET32BCTX_rBID(r32)                              _BFGET_(r32, 5, 0)
    #define   SET32BCTX_rBID(r32,v)                            _BFSET_(r32, 5, 0,v)
    #define   GET16BCTX_rBID(r16)                              _BFGET_(r16, 5, 0)
    #define   SET16BCTX_rBID(r16,v)                            _BFSET_(r16, 5, 0,v)

    #define   GET32BCTX_rIDX(r32)                              _BFGET_(r32,10, 6)
    #define   SET32BCTX_rIDX(r32,v)                            _BFSET_(r32,10, 6,v)
    #define   GET16BCTX_rIDX(r16)                              _BFGET_(r16,10, 6)
    #define   SET16BCTX_rIDX(r16,v)                            _BFSET_(r16,10, 6,v)

    #define   GET32BCTX_FLD(r32)                               _BFGET_(r32,11,11)
    #define   SET32BCTX_FLD(r32,v)                             _BFSET_(r32,11,11,v)
    #define   GET16BCTX_FLD(r16)                               _BFGET_(r16,11,11)
    #define   SET16BCTX_FLD(r16,v)                             _BFSET_(r16,11,11,v)

    #define   GET32BCTX_equalpred(r32)                         _BFGET_(r32,12,12)
    #define   SET32BCTX_equalpred(r32,v)                       _BFSET_(r32,12,12,v)
    #define   GET16BCTX_equalpred(r16)                         _BFGET_(r16,12,12)
    #define   SET16BCTX_equalpred(r16,v)                       _BFSET_(r16,12,12,v)

    #define   GET32BCTX_RSVD(r32)                              _BFGET_(r32,15,13)
    #define   SET32BCTX_RSVD(r32,v)                            _BFSET_(r32,15,13,v)
    #define   GET16BCTX_RSVD(r16)                              _BFGET_(r16,15,13)
    #define   SET16BCTX_RSVD(r16,v)                            _BFSET_(r16,15,13,v)

    #define   GET32BCTX_dctSel(r32)                            _BFGET_(r32,18,16)
    #define   SET32BCTX_dctSel(r32,v)                          _BFSET_(r32,18,16,v)
    #define   GET16BCTX_dctSel(r16)                            _BFGET_(r16, 2, 0)
    #define   SET16BCTX_dctSel(r16,v)                          _BFSET_(r16, 2, 0,v)

    #define   GET32BCTX_ABSMVDX(r32)                           _BFGET_(r32,24,19)
    #define   SET32BCTX_ABSMVDX(r32,v)                         _BFSET_(r32,24,19,v)
    #define   GET16BCTX_ABSMVDX(r16)                           _BFGET_(r16, 8, 3)
    #define   SET16BCTX_ABSMVDX(r16,v)                         _BFSET_(r16, 8, 3,v)

    #define   GET32BCTX_ABSMVDY(r32)                           _BFGET_(r32,31,25)
    #define   SET32BCTX_ABSMVDY(r32,v)                         _BFSET_(r32,31,25,v)
    #define   GET16BCTX_ABSMVDY(r16)                           _BFGET_(r16,15, 9)
    #define   SET16BCTX_ABSMVDY(r16,v)                         _BFSET_(r16,15, 9,v)

            UNSG32 u_rBID                                      :  6;
            UNSG32 u_rIDX                                      :  5;
            UNSG32 u_FLD                                       :  1;
            UNSG32 u_equalpred                                 :  1;
            UNSG32 u_RSVD                                      :  3;
            UNSG32 u_dctSel                                    :  3;
            UNSG32 u_ABSMVDX                                   :  6;
            UNSG32 u_ABSMVDY                                   :  7;
    ///////////////////////////////////////////////////////////
              SIE_MV                                           ie_mv;
    ///////////////////////////////////////////////////////////
    } SIE_BCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 BCTX_drvrd(SIE_BCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BCTX_drvwr(SIE_BCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BCTX_reset(SIE_BCTX *p);
     SIGN32 BCTX_cmp  (SIE_BCTX *p, SIE_BCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BCTX_check(p,pie,pfx,hLOG) BCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BCTX_print(p,    pfx,hLOG) BCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BCTX_VC1                biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 6  rBID                      
///               %unsigned 5  rIDX                      
///               %unsigned 1  FLD                       
///               %unsigned 1  equalpred                 
///                                    ###
///                                    * BLK property for CABAC only:
///                                    * Using block category ACV,
///                                    * (Only at 4th 4x4 in each 8x8s):
///                                    * = !Intra && !skipped && (bi-pred || back-pred)
///                                    * NOTE: = 0 for direct mode
///                                    ###
///               %unsigned 3  RSVD                      
///                                    ###
///                                    * Reserved
///                                    ###
///               %unsigned 2  dctSelU                   
///                                    ###
///                                    * DCT transform type for U; used for VC-1 Fop
///                                    ###
///               %unsigned 2  dctSelV                   
///                                    ###
///                                    * DCT transform type for V; used for VC-1 Fop
///                                    ###
///               %unsigned 1  CBFU                      
///                                    ###
///                                    * coded block (4x4) flag for U; used for VC-1 Fop
///                                    ###
///               %unsigned 1  CBFV                      
///                                    ###
///                                    * coded block (4x4) flag for V; used for VC-1 Fop
///                                    ###
///               %unsigned 1  CBFU8x8                   
///                                    ###
///                                    * coded block (8x8) flag for U, used for VC-1 Fop
///                                    ###
///               %unsigned 1  CBFV8x8                   
///                                    ###
///                                    * coded block (8x8) flag for V, used for VC-1 Fop
///                                    ###
///               %unsigned 8  RSVD8                     
///     @ 0x00004                      (P)
///     # 0x00004 mv                   
///               $MV                  mv                REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BCTX_VC1
#define h_BCTX_VC1 (){}

    #define     BA_BCTX_VC1_rBID                               0x0000
    #define     B16BCTX_VC1_rBID                               0x0000
    #define   LSb32BCTX_VC1_rBID                                  0
    #define   LSb16BCTX_VC1_rBID                                  0
    #define       bBCTX_VC1_rBID                               6
    #define   MSK32BCTX_VC1_rBID                                  0x0000003F

    #define     BA_BCTX_VC1_rIDX                               0x0000
    #define     B16BCTX_VC1_rIDX                               0x0000
    #define   LSb32BCTX_VC1_rIDX                                  6
    #define   LSb16BCTX_VC1_rIDX                                  6
    #define       bBCTX_VC1_rIDX                               5
    #define   MSK32BCTX_VC1_rIDX                                  0x000007C0

    #define     BA_BCTX_VC1_FLD                                0x0001
    #define     B16BCTX_VC1_FLD                                0x0000
    #define   LSb32BCTX_VC1_FLD                                   11
    #define   LSb16BCTX_VC1_FLD                                   11
    #define       bBCTX_VC1_FLD                                1
    #define   MSK32BCTX_VC1_FLD                                   0x00000800

    #define     BA_BCTX_VC1_equalpred                          0x0001
    #define     B16BCTX_VC1_equalpred                          0x0000
    #define   LSb32BCTX_VC1_equalpred                             12
    #define   LSb16BCTX_VC1_equalpred                             12
    #define       bBCTX_VC1_equalpred                          1
    #define   MSK32BCTX_VC1_equalpred                             0x00001000

    #define     BA_BCTX_VC1_RSVD                               0x0001
    #define     B16BCTX_VC1_RSVD                               0x0000
    #define   LSb32BCTX_VC1_RSVD                                  13
    #define   LSb16BCTX_VC1_RSVD                                  13
    #define       bBCTX_VC1_RSVD                               3
    #define   MSK32BCTX_VC1_RSVD                                  0x0000E000

    #define     BA_BCTX_VC1_dctSelU                            0x0002
    #define     B16BCTX_VC1_dctSelU                            0x0002
    #define   LSb32BCTX_VC1_dctSelU                               16
    #define   LSb16BCTX_VC1_dctSelU                               0
    #define       bBCTX_VC1_dctSelU                            2
    #define   MSK32BCTX_VC1_dctSelU                               0x00030000

    #define     BA_BCTX_VC1_dctSelV                            0x0002
    #define     B16BCTX_VC1_dctSelV                            0x0002
    #define   LSb32BCTX_VC1_dctSelV                               18
    #define   LSb16BCTX_VC1_dctSelV                               2
    #define       bBCTX_VC1_dctSelV                            2
    #define   MSK32BCTX_VC1_dctSelV                               0x000C0000

    #define     BA_BCTX_VC1_CBFU                               0x0002
    #define     B16BCTX_VC1_CBFU                               0x0002
    #define   LSb32BCTX_VC1_CBFU                                  20
    #define   LSb16BCTX_VC1_CBFU                                  4
    #define       bBCTX_VC1_CBFU                               1
    #define   MSK32BCTX_VC1_CBFU                                  0x00100000

    #define     BA_BCTX_VC1_CBFV                               0x0002
    #define     B16BCTX_VC1_CBFV                               0x0002
    #define   LSb32BCTX_VC1_CBFV                                  21
    #define   LSb16BCTX_VC1_CBFV                                  5
    #define       bBCTX_VC1_CBFV                               1
    #define   MSK32BCTX_VC1_CBFV                                  0x00200000

    #define     BA_BCTX_VC1_CBFU8x8                            0x0002
    #define     B16BCTX_VC1_CBFU8x8                            0x0002
    #define   LSb32BCTX_VC1_CBFU8x8                               22
    #define   LSb16BCTX_VC1_CBFU8x8                               6
    #define       bBCTX_VC1_CBFU8x8                            1
    #define   MSK32BCTX_VC1_CBFU8x8                               0x00400000

    #define     BA_BCTX_VC1_CBFV8x8                            0x0002
    #define     B16BCTX_VC1_CBFV8x8                            0x0002
    #define   LSb32BCTX_VC1_CBFV8x8                               23
    #define   LSb16BCTX_VC1_CBFV8x8                               7
    #define       bBCTX_VC1_CBFV8x8                            1
    #define   MSK32BCTX_VC1_CBFV8x8                               0x00800000

    #define     BA_BCTX_VC1_RSVD8                              0x0003
    #define     B16BCTX_VC1_RSVD8                              0x0002
    #define   LSb32BCTX_VC1_RSVD8                                 24
    #define   LSb16BCTX_VC1_RSVD8                                 8
    #define       bBCTX_VC1_RSVD8                              8
    #define   MSK32BCTX_VC1_RSVD8                                 0xFF000000
    ///////////////////////////////////////////////////////////
    #define     RA_BCTX_VC1_mv                                 0x0004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BCTX_VC1 {
    ///////////////////////////////////////////////////////////
    #define   GET32BCTX_VC1_rBID(r32)                          _BFGET_(r32, 5, 0)
    #define   SET32BCTX_VC1_rBID(r32,v)                        _BFSET_(r32, 5, 0,v)
    #define   GET16BCTX_VC1_rBID(r16)                          _BFGET_(r16, 5, 0)
    #define   SET16BCTX_VC1_rBID(r16,v)                        _BFSET_(r16, 5, 0,v)

    #define   GET32BCTX_VC1_rIDX(r32)                          _BFGET_(r32,10, 6)
    #define   SET32BCTX_VC1_rIDX(r32,v)                        _BFSET_(r32,10, 6,v)
    #define   GET16BCTX_VC1_rIDX(r16)                          _BFGET_(r16,10, 6)
    #define   SET16BCTX_VC1_rIDX(r16,v)                        _BFSET_(r16,10, 6,v)

    #define   GET32BCTX_VC1_FLD(r32)                           _BFGET_(r32,11,11)
    #define   SET32BCTX_VC1_FLD(r32,v)                         _BFSET_(r32,11,11,v)
    #define   GET16BCTX_VC1_FLD(r16)                           _BFGET_(r16,11,11)
    #define   SET16BCTX_VC1_FLD(r16,v)                         _BFSET_(r16,11,11,v)

    #define   GET32BCTX_VC1_equalpred(r32)                     _BFGET_(r32,12,12)
    #define   SET32BCTX_VC1_equalpred(r32,v)                   _BFSET_(r32,12,12,v)
    #define   GET16BCTX_VC1_equalpred(r16)                     _BFGET_(r16,12,12)
    #define   SET16BCTX_VC1_equalpred(r16,v)                   _BFSET_(r16,12,12,v)

    #define   GET32BCTX_VC1_RSVD(r32)                          _BFGET_(r32,15,13)
    #define   SET32BCTX_VC1_RSVD(r32,v)                        _BFSET_(r32,15,13,v)
    #define   GET16BCTX_VC1_RSVD(r16)                          _BFGET_(r16,15,13)
    #define   SET16BCTX_VC1_RSVD(r16,v)                        _BFSET_(r16,15,13,v)

    #define   GET32BCTX_VC1_dctSelU(r32)                       _BFGET_(r32,17,16)
    #define   SET32BCTX_VC1_dctSelU(r32,v)                     _BFSET_(r32,17,16,v)
    #define   GET16BCTX_VC1_dctSelU(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16BCTX_VC1_dctSelU(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32BCTX_VC1_dctSelV(r32)                       _BFGET_(r32,19,18)
    #define   SET32BCTX_VC1_dctSelV(r32,v)                     _BFSET_(r32,19,18,v)
    #define   GET16BCTX_VC1_dctSelV(r16)                       _BFGET_(r16, 3, 2)
    #define   SET16BCTX_VC1_dctSelV(r16,v)                     _BFSET_(r16, 3, 2,v)

    #define   GET32BCTX_VC1_CBFU(r32)                          _BFGET_(r32,20,20)
    #define   SET32BCTX_VC1_CBFU(r32,v)                        _BFSET_(r32,20,20,v)
    #define   GET16BCTX_VC1_CBFU(r16)                          _BFGET_(r16, 4, 4)
    #define   SET16BCTX_VC1_CBFU(r16,v)                        _BFSET_(r16, 4, 4,v)

    #define   GET32BCTX_VC1_CBFV(r32)                          _BFGET_(r32,21,21)
    #define   SET32BCTX_VC1_CBFV(r32,v)                        _BFSET_(r32,21,21,v)
    #define   GET16BCTX_VC1_CBFV(r16)                          _BFGET_(r16, 5, 5)
    #define   SET16BCTX_VC1_CBFV(r16,v)                        _BFSET_(r16, 5, 5,v)

    #define   GET32BCTX_VC1_CBFU8x8(r32)                       _BFGET_(r32,22,22)
    #define   SET32BCTX_VC1_CBFU8x8(r32,v)                     _BFSET_(r32,22,22,v)
    #define   GET16BCTX_VC1_CBFU8x8(r16)                       _BFGET_(r16, 6, 6)
    #define   SET16BCTX_VC1_CBFU8x8(r16,v)                     _BFSET_(r16, 6, 6,v)

    #define   GET32BCTX_VC1_CBFV8x8(r32)                       _BFGET_(r32,23,23)
    #define   SET32BCTX_VC1_CBFV8x8(r32,v)                     _BFSET_(r32,23,23,v)
    #define   GET16BCTX_VC1_CBFV8x8(r16)                       _BFGET_(r16, 7, 7)
    #define   SET16BCTX_VC1_CBFV8x8(r16,v)                     _BFSET_(r16, 7, 7,v)

    #define   GET32BCTX_VC1_RSVD8(r32)                         _BFGET_(r32,31,24)
    #define   SET32BCTX_VC1_RSVD8(r32,v)                       _BFSET_(r32,31,24,v)
    #define   GET16BCTX_VC1_RSVD8(r16)                         _BFGET_(r16,15, 8)
    #define   SET16BCTX_VC1_RSVD8(r16,v)                       _BFSET_(r16,15, 8,v)

            UNSG32 u_rBID                                      :  6;
            UNSG32 u_rIDX                                      :  5;
            UNSG32 u_FLD                                       :  1;
            UNSG32 u_equalpred                                 :  1;
            UNSG32 u_RSVD                                      :  3;
            UNSG32 u_dctSelU                                   :  2;
            UNSG32 u_dctSelV                                   :  2;
            UNSG32 u_CBFU                                      :  1;
            UNSG32 u_CBFV                                      :  1;
            UNSG32 u_CBFU8x8                                   :  1;
            UNSG32 u_CBFV8x8                                   :  1;
            UNSG32 u_RSVD8                                     :  8;
    ///////////////////////////////////////////////////////////
              SIE_MV                                           ie_mv;
    ///////////////////////////////////////////////////////////
    } SIE_BCTX_VC1;

    ///////////////////////////////////////////////////////////
     SIGN32 BCTX_VC1_drvrd(SIE_BCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BCTX_VC1_drvwr(SIE_BCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BCTX_VC1_reset(SIE_BCTX_VC1 *p);
     SIGN32 BCTX_VC1_cmp  (SIE_BCTX_VC1 *p, SIE_BCTX_VC1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BCTX_VC1_check(p,pie,pfx,hLOG) BCTX_VC1_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BCTX_VC1_print(p,    pfx,hLOG) BCTX_VC1_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BCTX_VC1
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE FCTXI                   biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 22 RSVD                      
///               %unsigned 5  NCUV                      
///                                    ###
///                                    * CAVLC use only:
///                                    * Using block category ACU/ACV: 0~15
///                                    ###
///               %unsigned 5  NCY                       
///                                    ###
///                                    * CAVLC use only:
///                                    * Using block category ACY (every 4x4s): 0~16
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 20 RSVD20                    
///               %unsigned 4  intraChroma               
///                                    ###
///                                    * For encoder: Intra prediction mode for chormablocks, see IntraChroma.mode above. Only appears in DCI, one per MB.
///                                    ###
///               %unsigned 8  intraLuma                 
///                                    ###
///                                    * Intra 16x16/NxN prediction mode for luma blocks, see IntraLuma.mode above
///                                    * =0 between parser & syntax processor
///                                    * End of FCTXI
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_FCTXI
#define h_FCTXI (){}

    #define     BA_FCTXI_RSVD                                  0x0000
    #define     B16FCTXI_RSVD                                  0x0000
    #define   LSb32FCTXI_RSVD                                     0
    #define   LSb16FCTXI_RSVD                                     0
    #define       bFCTXI_RSVD                                  22
    #define   MSK32FCTXI_RSVD                                     0x003FFFFF

    #define     BA_FCTXI_NCUV                                  0x0002
    #define     B16FCTXI_NCUV                                  0x0002
    #define   LSb32FCTXI_NCUV                                     22
    #define   LSb16FCTXI_NCUV                                     6
    #define       bFCTXI_NCUV                                  5
    #define   MSK32FCTXI_NCUV                                     0x07C00000

    #define     BA_FCTXI_NCY                                   0x0003
    #define     B16FCTXI_NCY                                   0x0002
    #define   LSb32FCTXI_NCY                                      27
    #define   LSb16FCTXI_NCY                                      11
    #define       bFCTXI_NCY                                   5
    #define   MSK32FCTXI_NCY                                      0xF8000000
    ///////////////////////////////////////////////////////////

    #define     BA_FCTXI_RSVD20                                0x0004
    #define     B16FCTXI_RSVD20                                0x0004
    #define   LSb32FCTXI_RSVD20                                   0
    #define   LSb16FCTXI_RSVD20                                   0
    #define       bFCTXI_RSVD20                                20
    #define   MSK32FCTXI_RSVD20                                   0x000FFFFF

    #define     BA_FCTXI_intraChroma                           0x0006
    #define     B16FCTXI_intraChroma                           0x0006
    #define   LSb32FCTXI_intraChroma                              20
    #define   LSb16FCTXI_intraChroma                              4
    #define       bFCTXI_intraChroma                           4
    #define   MSK32FCTXI_intraChroma                              0x00F00000

    #define     BA_FCTXI_intraLuma                             0x0007
    #define     B16FCTXI_intraLuma                             0x0006
    #define   LSb32FCTXI_intraLuma                                24
    #define   LSb16FCTXI_intraLuma                                8
    #define       bFCTXI_intraLuma                             8
    #define   MSK32FCTXI_intraLuma                                0xFF000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_FCTXI {
    ///////////////////////////////////////////////////////////
    #define   GET32FCTXI_RSVD(r32)                             _BFGET_(r32,21, 0)
    #define   SET32FCTXI_RSVD(r32,v)                           _BFSET_(r32,21, 0,v)

    #define   GET32FCTXI_NCUV(r32)                             _BFGET_(r32,26,22)
    #define   SET32FCTXI_NCUV(r32,v)                           _BFSET_(r32,26,22,v)
    #define   GET16FCTXI_NCUV(r16)                             _BFGET_(r16,10, 6)
    #define   SET16FCTXI_NCUV(r16,v)                           _BFSET_(r16,10, 6,v)

    #define   GET32FCTXI_NCY(r32)                              _BFGET_(r32,31,27)
    #define   SET32FCTXI_NCY(r32,v)                            _BFSET_(r32,31,27,v)
    #define   GET16FCTXI_NCY(r16)                              _BFGET_(r16,15,11)
    #define   SET16FCTXI_NCY(r16,v)                            _BFSET_(r16,15,11,v)

            UNSG32 u_RSVD                                      : 22;
            UNSG32 u_NCUV                                      :  5;
            UNSG32 u_NCY                                       :  5;
    ///////////////////////////////////////////////////////////
    #define   GET32FCTXI_RSVD20(r32)                           _BFGET_(r32,19, 0)
    #define   SET32FCTXI_RSVD20(r32,v)                         _BFSET_(r32,19, 0,v)

    #define   GET32FCTXI_intraChroma(r32)                      _BFGET_(r32,23,20)
    #define   SET32FCTXI_intraChroma(r32,v)                    _BFSET_(r32,23,20,v)
    #define   GET16FCTXI_intraChroma(r16)                      _BFGET_(r16, 7, 4)
    #define   SET16FCTXI_intraChroma(r16,v)                    _BFSET_(r16, 7, 4,v)

    #define   GET32FCTXI_intraLuma(r32)                        _BFGET_(r32,31,24)
    #define   SET32FCTXI_intraLuma(r32,v)                      _BFSET_(r32,31,24,v)
    #define   GET16FCTXI_intraLuma(r16)                        _BFGET_(r16,15, 8)
    #define   SET16FCTXI_intraLuma(r16,v)                      _BFSET_(r16,15, 8,v)

            UNSG32 u_RSVD20                                    : 20;
            UNSG32 u_intraChroma                               :  4;
            UNSG32 u_intraLuma                                 :  8;
    ///////////////////////////////////////////////////////////
    } SIE_FCTXI;

    ///////////////////////////////////////////////////////////
     SIGN32 FCTXI_drvrd(SIE_FCTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 FCTXI_drvwr(SIE_FCTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void FCTXI_reset(SIE_FCTXI *p);
     SIGN32 FCTXI_cmp  (SIE_FCTXI *p, SIE_FCTXI *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define FCTXI_check(p,pie,pfx,hLOG) FCTXI_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define FCTXI_print(p,    pfx,hLOG) FCTXI_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: FCTXI
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE HCTX4x4                 biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 fore                 
///               $FCTX                fore              REG          
///                                    ###
///                                    * Forward prediction
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 back                 
///               $BCTX                back              REG          
///                                    ###
///                                    * Backward prediction
///                                    * End of HCTX4x4
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:     128b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_HCTX4x4
#define h_HCTX4x4 (){}

    #define     RA_HCTX4x4_fore                                0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_HCTX4x4_back                                0x0008
    ///////////////////////////////////////////////////////////

    typedef struct SIE_HCTX4x4 {
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_fore;
    ///////////////////////////////////////////////////////////
              SIE_BCTX                                         ie_back;
    ///////////////////////////////////////////////////////////
    } SIE_HCTX4x4;

    ///////////////////////////////////////////////////////////
     SIGN32 HCTX4x4_drvrd(SIE_HCTX4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 HCTX4x4_drvwr(SIE_HCTX4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void HCTX4x4_reset(SIE_HCTX4x4 *p);
     SIGN32 HCTX4x4_cmp  (SIE_HCTX4x4 *p, SIE_HCTX4x4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define HCTX4x4_check(p,pie,pfx,hLOG) HCTX4x4_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define HCTX4x4_print(p,    pfx,hLOG) HCTX4x4_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: HCTX4x4
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE CTXI                    biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %signed   16 AC0                       
///                                    ###
///                                    * DC or horizontal/vertical AC coefficient
///                                    ###
///               %signed   13 AC1                       
///                                    ###
///                                    * 2nd horizontal/vertical AC coefficient
///                                    ###
///               %unsigned 1  cbpcy                     
///                                    ###
///                                    * Flatten all 4x4s in a 8x8 block, coded or not
///                                    ###
///               %unsigned 2  mquantL                   
///                                    ###
///                                    * Low 2 bits of mquant, flatten all 4x4s in a macroblock
///                                    ###
///               %unsigned 3  mquantH                   
///                                    ###
///                                    * High 3 bits of mquant, flatten all 4x4s in a macroblock
///                                    ###
///               %signed   13 AC2                       
///                                    ###
///                                    * 3rd horizontal/vertical AC coefficient
///                                    ###
///               %unsigned 3  type                      
///                                    ###
///                                    * Sub-set of mb_type, see MBPROP.type above
///                                    * = intra16x16
///                                    ###
///               %signed   13 AC3                       
///                                    ###
///                                    * 4th horizontal/vertical AC coefficient
///                                    * End of CTXI
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CTXI
#define h_CTXI (){}

    #define     BA_CTXI_AC0                                    0x0000
    #define     B16CTXI_AC0                                    0x0000
    #define   LSb32CTXI_AC0                                       0
    #define   LSb16CTXI_AC0                                       0
    #define       bCTXI_AC0                                    16
    #define   MSK32CTXI_AC0                                       0x0000FFFF

    #define     BA_CTXI_AC1                                    0x0002
    #define     B16CTXI_AC1                                    0x0002
    #define   LSb32CTXI_AC1                                       16
    #define   LSb16CTXI_AC1                                       0
    #define       bCTXI_AC1                                    13
    #define   MSK32CTXI_AC1                                       0x1FFF0000

    #define     BA_CTXI_cbpcy                                  0x0003
    #define     B16CTXI_cbpcy                                  0x0002
    #define   LSb32CTXI_cbpcy                                     29
    #define   LSb16CTXI_cbpcy                                     13
    #define       bCTXI_cbpcy                                  1
    #define   MSK32CTXI_cbpcy                                     0x20000000

    #define     BA_CTXI_mquantL                                0x0003
    #define     B16CTXI_mquantL                                0x0002
    #define   LSb32CTXI_mquantL                                   30
    #define   LSb16CTXI_mquantL                                   14
    #define       bCTXI_mquantL                                2
    #define   MSK32CTXI_mquantL                                   0xC0000000

    #define     BA_CTXI_mquantH                                0x0004
    #define     B16CTXI_mquantH                                0x0004
    #define   LSb32CTXI_mquantH                                   0
    #define   LSb16CTXI_mquantH                                   0
    #define       bCTXI_mquantH                                3
    #define   MSK32CTXI_mquantH                                   0x00000007

    #define     BA_CTXI_AC2                                    0x0004
    #define     B16CTXI_AC2                                    0x0004
    #define   LSb32CTXI_AC2                                       3
    #define   LSb16CTXI_AC2                                       3
    #define       bCTXI_AC2                                    13
    #define   MSK32CTXI_AC2                                       0x0000FFF8

    #define     BA_CTXI_type                                   0x0006
    #define     B16CTXI_type                                   0x0006
    #define   LSb32CTXI_type                                      16
    #define   LSb16CTXI_type                                      0
    #define       bCTXI_type                                   3
    #define   MSK32CTXI_type                                      0x00070000

    #define     BA_CTXI_AC3                                    0x0006
    #define     B16CTXI_AC3                                    0x0006
    #define   LSb32CTXI_AC3                                       19
    #define   LSb16CTXI_AC3                                       3
    #define       bCTXI_AC3                                    13
    #define   MSK32CTXI_AC3                                       0xFFF80000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CTXI {
    ///////////////////////////////////////////////////////////
    #define   GET32CTXI_AC0(r32)                               _BFGET_(r32,15, 0)
    #define   SET32CTXI_AC0(r32,v)                             _BFSET_(r32,15, 0,v)
    #define   GET16CTXI_AC0(r16)                               _BFGET_(r16,15, 0)
    #define   SET16CTXI_AC0(r16,v)                             _BFSET_(r16,15, 0,v)

    #define   GET32CTXI_AC1(r32)                               _BFGET_(r32,28,16)
    #define   SET32CTXI_AC1(r32,v)                             _BFSET_(r32,28,16,v)
    #define   GET16CTXI_AC1(r16)                               _BFGET_(r16,12, 0)
    #define   SET16CTXI_AC1(r16,v)                             _BFSET_(r16,12, 0,v)

    #define   GET32CTXI_cbpcy(r32)                             _BFGET_(r32,29,29)
    #define   SET32CTXI_cbpcy(r32,v)                           _BFSET_(r32,29,29,v)
    #define   GET16CTXI_cbpcy(r16)                             _BFGET_(r16,13,13)
    #define   SET16CTXI_cbpcy(r16,v)                           _BFSET_(r16,13,13,v)

    #define   GET32CTXI_mquantL(r32)                           _BFGET_(r32,31,30)
    #define   SET32CTXI_mquantL(r32,v)                         _BFSET_(r32,31,30,v)
    #define   GET16CTXI_mquantL(r16)                           _BFGET_(r16,15,14)
    #define   SET16CTXI_mquantL(r16,v)                         _BFSET_(r16,15,14,v)

            UNSG32 s_AC0                                       : 16;
            UNSG32 s_AC1                                       : 13;
            UNSG32 u_cbpcy                                     :  1;
            UNSG32 u_mquantL                                   :  2;
    ///////////////////////////////////////////////////////////

    #define   GET32CTXI_mquantH(r32)                           _BFGET_(r32, 2, 0)
    #define   SET32CTXI_mquantH(r32,v)                         _BFSET_(r32, 2, 0,v)
    #define   GET16CTXI_mquantH(r16)                           _BFGET_(r16, 2, 0)
    #define   SET16CTXI_mquantH(r16,v)                         _BFSET_(r16, 2, 0,v)

    #define   GET32CTXI_AC2(r32)                               _BFGET_(r32,15, 3)
    #define   SET32CTXI_AC2(r32,v)                             _BFSET_(r32,15, 3,v)
    #define   GET16CTXI_AC2(r16)                               _BFGET_(r16,15, 3)
    #define   SET16CTXI_AC2(r16,v)                             _BFSET_(r16,15, 3,v)

    #define   GET32CTXI_type(r32)                              _BFGET_(r32,18,16)
    #define   SET32CTXI_type(r32,v)                            _BFSET_(r32,18,16,v)
    #define   GET16CTXI_type(r16)                              _BFGET_(r16, 2, 0)
    #define   SET16CTXI_type(r16,v)                            _BFSET_(r16, 2, 0,v)

    #define   GET32CTXI_AC3(r32)                               _BFGET_(r32,31,19)
    #define   SET32CTXI_AC3(r32,v)                             _BFSET_(r32,31,19,v)
    #define   GET16CTXI_AC3(r16)                               _BFGET_(r16,15, 3)
    #define   SET16CTXI_AC3(r16,v)                             _BFSET_(r16,15, 3,v)

            UNSG32 u_mquantH                                   :  3;
            UNSG32 s_AC2                                       : 13;
            UNSG32 u_type                                      :  3;
            UNSG32 s_AC3                                       : 13;
    ///////////////////////////////////////////////////////////
    } SIE_CTXI;

    ///////////////////////////////////////////////////////////
     SIGN32 CTXI_drvrd(SIE_CTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CTXI_drvwr(SIE_CTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CTXI_reset(SIE_CTXI *p);
     SIGN32 CTXI_cmp  (SIE_CTXI *p, SIE_CTXI *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CTXI_check(p,pie,pfx,hLOG) CTXI_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CTXI_print(p,    pfx,hLOG) CTXI_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CTXI
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE CTXI4x4                                  (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 luma                 
///               $CTXI                luma              REG          
///                                    ###
///                                    * DC/AC for Y
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 chroma               
///               $CTXI                chroma            REG          
///                                    ###
///                                    * DC/AC for UV
///                                    * End of CTXI4x4
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:     128b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CTXI4x4
#define h_CTXI4x4 (){}

    #define     RA_CTXI4x4_luma                                0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_CTXI4x4_chroma                              0x0008
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CTXI4x4 {
    ///////////////////////////////////////////////////////////
              SIE_CTXI                                         ie_luma;
    ///////////////////////////////////////////////////////////
              SIE_CTXI                                         ie_chroma;
    ///////////////////////////////////////////////////////////
    } SIE_CTXI4x4;

    ///////////////////////////////////////////////////////////
     SIGN32 CTXI4x4_drvrd(SIE_CTXI4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CTXI4x4_drvwr(SIE_CTXI4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CTXI4x4_reset(SIE_CTXI4x4 *p);
     SIGN32 CTXI4x4_cmp  (SIE_CTXI4x4 *p, SIE_CTXI4x4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CTXI4x4_check(p,pie,pfx,hLOG) CTXI4x4_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CTXI4x4_print(p,    pfx,hLOG) CTXI4x4_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CTXI4x4
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE IDX2BID                                  (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 frmIDX2BID           
///               $LUT8b               frmIDX2BID        REG      [16]
///                                    ###
///                                    * Cast to 8b rBID[32:rIDX][2:L0/L1]
///                                    * Note: field picture use this table (32 rIDX)!
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 topIDX2BID           
///               $LUT8b               topIDX2BID        REG      [16]
///                                    ###
///                                    * Cast to 8b rBID[32:rIDX][2:L0/L1]
///                                    ###
///     @ 0x00080                      (P)
///     # 0x00080 btmIDX2BID           
///               $LUT8b               btmIDX2BID        REG      [16]
///                                    ###
///                                    * Cast to 8b rBID[32:rIDX][2:L0/L1]
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     192B, bits:    1536b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_IDX2BID
#define h_IDX2BID (){}

    #define     RA_IDX2BID_frmIDX2BID                          0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_IDX2BID_topIDX2BID                          0x0040
    ///////////////////////////////////////////////////////////
    #define     RA_IDX2BID_btmIDX2BID                          0x0080
    ///////////////////////////////////////////////////////////

    typedef struct SIE_IDX2BID {
    ///////////////////////////////////////////////////////////
              SIE_LUT8b                                        ie_frmIDX2BID[16];
    ///////////////////////////////////////////////////////////
              SIE_LUT8b                                        ie_topIDX2BID[16];
    ///////////////////////////////////////////////////////////
              SIE_LUT8b                                        ie_btmIDX2BID[16];
    ///////////////////////////////////////////////////////////
    } SIE_IDX2BID;

    ///////////////////////////////////////////////////////////
     SIGN32 IDX2BID_drvrd(SIE_IDX2BID *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 IDX2BID_drvwr(SIE_IDX2BID *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void IDX2BID_reset(SIE_IDX2BID *p);
     SIGN32 IDX2BID_cmp  (SIE_IDX2BID *p, SIE_IDX2BID *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define IDX2BID_check(p,pie,pfx,hLOG) IDX2BID_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define IDX2BID_print(p,    pfx,hLOG) IDX2BID_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: IDX2BID
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BID2IDX                                  (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 frmBID2IDX           
///               $LUT8b               frmBID2IDX        REG      [10]
///                                    ###
///                                    * Cast to 8b L0.min.rIDX[34:rBID]
///                                    * Note: field picture use this table (32 rIDX)!
///                                    ###
///     @ 0x00028                      (P)
///     # 0x00028 topBID2IDX           
///               $LUT8b               topBID2IDX        REG      [10]
///                                    ###
///                                    * Cast to 8b L0.min.rIDX[34:rBID]
///                                    ###
///     @ 0x00050                      (P)
///     # 0x00050 btmBID2IDX           
///               $LUT8b               btmBID2IDX        REG      [10]
///                                    ###
///                                    * Cast to 8b L0.min.rIDX[34:rBID]
///                                    * Note: direct mode corner case
///                                    * Alternative method (not used) if not adjust rIDX:
///                                    * rBID = CoL.rBID | (CoL.Frm & Cur.Btm)
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     120B, bits:     960b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BID2IDX
#define h_BID2IDX (){}

    #define     RA_BID2IDX_frmBID2IDX                          0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_BID2IDX_topBID2IDX                          0x0028
    ///////////////////////////////////////////////////////////
    #define     RA_BID2IDX_btmBID2IDX                          0x0050
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BID2IDX {
    ///////////////////////////////////////////////////////////
              SIE_LUT8b                                        ie_frmBID2IDX[10];
    ///////////////////////////////////////////////////////////
              SIE_LUT8b                                        ie_topBID2IDX[10];
    ///////////////////////////////////////////////////////////
              SIE_LUT8b                                        ie_btmBID2IDX[10];
    ///////////////////////////////////////////////////////////
    } SIE_BID2IDX;

    ///////////////////////////////////////////////////////////
     SIGN32 BID2IDX_drvrd(SIE_BID2IDX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BID2IDX_drvwr(SIE_BID2IDX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BID2IDX_reset(SIE_BID2IDX *p);
     SIGN32 BID2IDX_cmp  (SIE_BID2IDX *p, SIE_BID2IDX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BID2IDX_check(p,pie,pfx,hLOG) BID2IDX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BID2IDX_print(p,    pfx,hLOG) BID2IDX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BID2IDX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ASPSET                  biu              (4,4)
///     ###
///     * [0:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 3  type                      
///                                    ###
///                                    * MB type
///                                    ###
///               %unsigned 2  chroma                    
///                                    ###
///                                    * Intra MB only: intra_chroma_pred
///                                    ###
///               %unsigned 1  t8x8                      
///                                    ###
///                                    * 8x8 transform; used by AspInit & residual.
///                                    * End of ASPSET
///                                    ###
///               %%        26         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ASPSET
#define h_ASPSET (){}

    #define     BA_ASPSET_type                                 0x0000
    #define     B16ASPSET_type                                 0x0000
    #define   LSb32ASPSET_type                                    0
    #define   LSb16ASPSET_type                                    0
    #define       bASPSET_type                                 3
    #define   MSK32ASPSET_type                                    0x00000007

    #define     BA_ASPSET_chroma                               0x0000
    #define     B16ASPSET_chroma                               0x0000
    #define   LSb32ASPSET_chroma                                  3
    #define   LSb16ASPSET_chroma                                  3
    #define       bASPSET_chroma                               2
    #define   MSK32ASPSET_chroma                                  0x00000018

    #define     BA_ASPSET_t8x8                                 0x0000
    #define     B16ASPSET_t8x8                                 0x0000
    #define   LSb32ASPSET_t8x8                                    5
    #define   LSb16ASPSET_t8x8                                    5
    #define       bASPSET_t8x8                                 1
    #define   MSK32ASPSET_t8x8                                    0x00000020
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ASPSET {
    ///////////////////////////////////////////////////////////
    #define   GET32ASPSET_type(r32)                            _BFGET_(r32, 2, 0)
    #define   SET32ASPSET_type(r32,v)                          _BFSET_(r32, 2, 0,v)
    #define   GET16ASPSET_type(r16)                            _BFGET_(r16, 2, 0)
    #define   SET16ASPSET_type(r16,v)                          _BFSET_(r16, 2, 0,v)

    #define   GET32ASPSET_chroma(r32)                          _BFGET_(r32, 4, 3)
    #define   SET32ASPSET_chroma(r32,v)                        _BFSET_(r32, 4, 3,v)
    #define   GET16ASPSET_chroma(r16)                          _BFGET_(r16, 4, 3)
    #define   SET16ASPSET_chroma(r16,v)                        _BFSET_(r16, 4, 3,v)

    #define   GET32ASPSET_t8x8(r32)                            _BFGET_(r32, 5, 5)
    #define   SET32ASPSET_t8x8(r32,v)                          _BFSET_(r32, 5, 5,v)
    #define   GET16ASPSET_t8x8(r16)                            _BFGET_(r16, 5, 5)
    #define   SET16ASPSET_t8x8(r16,v)                          _BFSET_(r16, 5, 5,v)

            UNSG32 u_type                                      :  3;
            UNSG32 u_chroma                                    :  2;
            UNSG32 u_t8x8                                      :  1;
            UNSG32 RSVDx0_b6                                   : 26;
    ///////////////////////////////////////////////////////////
    } SIE_ASPSET;

    ///////////////////////////////////////////////////////////
     SIGN32 ASPSET_drvrd(SIE_ASPSET *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ASPSET_drvwr(SIE_ASPSET *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ASPSET_reset(SIE_ASPSET *p);
     SIGN32 ASPSET_cmp  (SIE_ASPSET *p, SIE_ASPSET *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ASPSET_check(p,pie,pfx,hLOG) ASPSET_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ASPSET_print(p,    pfx,hLOG) ASPSET_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ASPSET
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE IntraPROP                                (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 3  type                      
///                                    ###
///                                    * See BLK.type above,
///                                    * LUT: IPCM or intraNxN or intra16x16
///                                    ###
///               %unsigned 1  8x8IDX0                   
///                                    ###
///                                    * LUT: 0 (P_8x8ref0)
///                                    ###
///               %unsigned 1  t8x8I                     
///                                    ###
///                                    * LUT: MB.transform8x8 & intraNxN
///                                    ###
///               %unsigned 1  t8x8PB                    
///                                    ###
///                                    * LUT: 0
///                                    ###
///               %unsigned 2  luma16x16                 
///                                    ###
///                                    * LUT: intra 16x16 prediction mode
///                                    ###
///               %unsigned 6  CBP                       
///                                    ###
///                                    * LUT: intra 16x16 coded block pattern
///                                    * MPEG4 LUT: Chroma cbp
///                                    * End of IntraPROP
///                                    ###
///               %%        18         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      14b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_IntraPROP
#define h_IntraPROP (){}

    #define     BA_IntraPROP_type                              0x0000
    #define     B16IntraPROP_type                              0x0000
    #define   LSb32IntraPROP_type                                 0
    #define   LSb16IntraPROP_type                                 0
    #define       bIntraPROP_type                              3
    #define   MSK32IntraPROP_type                                 0x00000007

    #define     BA_IntraPROP_8x8IDX0                           0x0000
    #define     B16IntraPROP_8x8IDX0                           0x0000
    #define   LSb32IntraPROP_8x8IDX0                              3
    #define   LSb16IntraPROP_8x8IDX0                              3
    #define       bIntraPROP_8x8IDX0                           1
    #define   MSK32IntraPROP_8x8IDX0                              0x00000008

    #define     BA_IntraPROP_t8x8I                             0x0000
    #define     B16IntraPROP_t8x8I                             0x0000
    #define   LSb32IntraPROP_t8x8I                                4
    #define   LSb16IntraPROP_t8x8I                                4
    #define       bIntraPROP_t8x8I                             1
    #define   MSK32IntraPROP_t8x8I                                0x00000010

    #define     BA_IntraPROP_t8x8PB                            0x0000
    #define     B16IntraPROP_t8x8PB                            0x0000
    #define   LSb32IntraPROP_t8x8PB                               5
    #define   LSb16IntraPROP_t8x8PB                               5
    #define       bIntraPROP_t8x8PB                            1
    #define   MSK32IntraPROP_t8x8PB                               0x00000020

    #define     BA_IntraPROP_luma16x16                         0x0000
    #define     B16IntraPROP_luma16x16                         0x0000
    #define   LSb32IntraPROP_luma16x16                            6
    #define   LSb16IntraPROP_luma16x16                            6
    #define       bIntraPROP_luma16x16                         2
    #define   MSK32IntraPROP_luma16x16                            0x000000C0

    #define     BA_IntraPROP_CBP                               0x0001
    #define     B16IntraPROP_CBP                               0x0000
    #define   LSb32IntraPROP_CBP                                  8
    #define   LSb16IntraPROP_CBP                                  8
    #define       bIntraPROP_CBP                               6
    #define   MSK32IntraPROP_CBP                                  0x00003F00
    ///////////////////////////////////////////////////////////

    typedef struct SIE_IntraPROP {
    ///////////////////////////////////////////////////////////
    #define   GET32IntraPROP_type(r32)                         _BFGET_(r32, 2, 0)
    #define   SET32IntraPROP_type(r32,v)                       _BFSET_(r32, 2, 0,v)
    #define   GET16IntraPROP_type(r16)                         _BFGET_(r16, 2, 0)
    #define   SET16IntraPROP_type(r16,v)                       _BFSET_(r16, 2, 0,v)

    #define   GET32IntraPROP_8x8IDX0(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32IntraPROP_8x8IDX0(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16IntraPROP_8x8IDX0(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16IntraPROP_8x8IDX0(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32IntraPROP_t8x8I(r32)                        _BFGET_(r32, 4, 4)
    #define   SET32IntraPROP_t8x8I(r32,v)                      _BFSET_(r32, 4, 4,v)
    #define   GET16IntraPROP_t8x8I(r16)                        _BFGET_(r16, 4, 4)
    #define   SET16IntraPROP_t8x8I(r16,v)                      _BFSET_(r16, 4, 4,v)

    #define   GET32IntraPROP_t8x8PB(r32)                       _BFGET_(r32, 5, 5)
    #define   SET32IntraPROP_t8x8PB(r32,v)                     _BFSET_(r32, 5, 5,v)
    #define   GET16IntraPROP_t8x8PB(r16)                       _BFGET_(r16, 5, 5)
    #define   SET16IntraPROP_t8x8PB(r16,v)                     _BFSET_(r16, 5, 5,v)

    #define   GET32IntraPROP_luma16x16(r32)                    _BFGET_(r32, 7, 6)
    #define   SET32IntraPROP_luma16x16(r32,v)                  _BFSET_(r32, 7, 6,v)
    #define   GET16IntraPROP_luma16x16(r16)                    _BFGET_(r16, 7, 6)
    #define   SET16IntraPROP_luma16x16(r16,v)                  _BFSET_(r16, 7, 6,v)

    #define   GET32IntraPROP_CBP(r32)                          _BFGET_(r32,13, 8)
    #define   SET32IntraPROP_CBP(r32,v)                        _BFSET_(r32,13, 8,v)
    #define   GET16IntraPROP_CBP(r16)                          _BFGET_(r16,13, 8)
    #define   SET16IntraPROP_CBP(r16,v)                        _BFSET_(r16,13, 8,v)

            UNSG32 u_type                                      :  3;
            UNSG32 u_8x8IDX0                                   :  1;
            UNSG32 u_t8x8I                                     :  1;
            UNSG32 u_t8x8PB                                    :  1;
            UNSG32 u_luma16x16                                 :  2;
            UNSG32 u_CBP                                       :  6;
            UNSG32 RSVDx0_b14                                  : 18;
    ///////////////////////////////////////////////////////////
    } SIE_IntraPROP;

    ///////////////////////////////////////////////////////////
     SIGN32 IntraPROP_drvrd(SIE_IntraPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 IntraPROP_drvwr(SIE_IntraPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void IntraPROP_reset(SIE_IntraPROP *p);
     SIGN32 IntraPROP_cmp  (SIE_IntraPROP *p, SIE_IntraPROP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define IntraPROP_check(p,pie,pfx,hLOG) IntraPROP_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define IntraPROP_print(p,    pfx,hLOG) IntraPROP_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: IntraPROP
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE InterPROP                                (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 3  type                      
///                                    ###
///                                    * See MBPROP.type above,
///                                    * LUT: inter or 8x8PB or 8x8IDX0 or direct16x16
///                                    ###
///               %unsigned 1  8x8IDX0                   
///                                    ###
///                                    * LUT: P_8x8ref0
///                                    ###
///               %unsigned 1  t8x8I                     
///                                    ###
///                                    * LUT: 0
///                                    ###
///               %unsigned 1  t8x8PB                    
///                                    ###
///                                    * LUT: MB.transform8x8 & inter &
///                                    * (MB.direct8x8 | !direct16x16)
///                                    ###
///               %unsigned 2  partition                 
///                                    ###
///                                    * See MBPROP.partition above
///                                    ###
///               %unsigned 2  motion_0i                 
///               %unsigned 2  motion_1i                 
///                                    ###
///                                    * LUT: intra/forward/backward/bi, see BLK.motion above
///                                    ###
///               %unsigned 2  mvs_0i                    
///               %unsigned 2  mvs_1i                    
///                                    ###
///                                    * Number of motion vectors for each directions
///                                    * End of InterPROP
///                                    ###
///               %%        16         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      16b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_InterPROP
#define h_InterPROP (){}

    #define     BA_InterPROP_type                              0x0000
    #define     B16InterPROP_type                              0x0000
    #define   LSb32InterPROP_type                                 0
    #define   LSb16InterPROP_type                                 0
    #define       bInterPROP_type                              3
    #define   MSK32InterPROP_type                                 0x00000007

    #define     BA_InterPROP_8x8IDX0                           0x0000
    #define     B16InterPROP_8x8IDX0                           0x0000
    #define   LSb32InterPROP_8x8IDX0                              3
    #define   LSb16InterPROP_8x8IDX0                              3
    #define       bInterPROP_8x8IDX0                           1
    #define   MSK32InterPROP_8x8IDX0                              0x00000008

    #define     BA_InterPROP_t8x8I                             0x0000
    #define     B16InterPROP_t8x8I                             0x0000
    #define   LSb32InterPROP_t8x8I                                4
    #define   LSb16InterPROP_t8x8I                                4
    #define       bInterPROP_t8x8I                             1
    #define   MSK32InterPROP_t8x8I                                0x00000010

    #define     BA_InterPROP_t8x8PB                            0x0000
    #define     B16InterPROP_t8x8PB                            0x0000
    #define   LSb32InterPROP_t8x8PB                               5
    #define   LSb16InterPROP_t8x8PB                               5
    #define       bInterPROP_t8x8PB                            1
    #define   MSK32InterPROP_t8x8PB                               0x00000020

    #define     BA_InterPROP_partition                         0x0000
    #define     B16InterPROP_partition                         0x0000
    #define   LSb32InterPROP_partition                            6
    #define   LSb16InterPROP_partition                            6
    #define       bInterPROP_partition                         2
    #define   MSK32InterPROP_partition                            0x000000C0

    #define     BA_InterPROP_motion_0i                         0x0001
    #define     B16InterPROP_motion_0i                         0x0000
    #define   LSb32InterPROP_motion_0i                            8
    #define   LSb16InterPROP_motion_0i                            8
    #define       bInterPROP_motion_0i                         2
    #define   MSK32InterPROP_motion_0i                            0x00000300

    #define     BA_InterPROP_motion_1i                         0x0001
    #define     B16InterPROP_motion_1i                         0x0000
    #define   LSb32InterPROP_motion_1i                            10
    #define   LSb16InterPROP_motion_1i                            10
    #define       bInterPROP_motion_1i                         2
    #define   MSK32InterPROP_motion_1i                            0x00000C00

    #define     BA_InterPROP_mvs_0i                            0x0001
    #define     B16InterPROP_mvs_0i                            0x0000
    #define   LSb32InterPROP_mvs_0i                               12
    #define   LSb16InterPROP_mvs_0i                               12
    #define       bInterPROP_mvs_0i                            2
    #define   MSK32InterPROP_mvs_0i                               0x00003000

    #define     BA_InterPROP_mvs_1i                            0x0001
    #define     B16InterPROP_mvs_1i                            0x0000
    #define   LSb32InterPROP_mvs_1i                               14
    #define   LSb16InterPROP_mvs_1i                               14
    #define       bInterPROP_mvs_1i                            2
    #define   MSK32InterPROP_mvs_1i                               0x0000C000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_InterPROP {
    ///////////////////////////////////////////////////////////
    #define   GET32InterPROP_type(r32)                         _BFGET_(r32, 2, 0)
    #define   SET32InterPROP_type(r32,v)                       _BFSET_(r32, 2, 0,v)
    #define   GET16InterPROP_type(r16)                         _BFGET_(r16, 2, 0)
    #define   SET16InterPROP_type(r16,v)                       _BFSET_(r16, 2, 0,v)

    #define   GET32InterPROP_8x8IDX0(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32InterPROP_8x8IDX0(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16InterPROP_8x8IDX0(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16InterPROP_8x8IDX0(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32InterPROP_t8x8I(r32)                        _BFGET_(r32, 4, 4)
    #define   SET32InterPROP_t8x8I(r32,v)                      _BFSET_(r32, 4, 4,v)
    #define   GET16InterPROP_t8x8I(r16)                        _BFGET_(r16, 4, 4)
    #define   SET16InterPROP_t8x8I(r16,v)                      _BFSET_(r16, 4, 4,v)

    #define   GET32InterPROP_t8x8PB(r32)                       _BFGET_(r32, 5, 5)
    #define   SET32InterPROP_t8x8PB(r32,v)                     _BFSET_(r32, 5, 5,v)
    #define   GET16InterPROP_t8x8PB(r16)                       _BFGET_(r16, 5, 5)
    #define   SET16InterPROP_t8x8PB(r16,v)                     _BFSET_(r16, 5, 5,v)

    #define   GET32InterPROP_partition(r32)                    _BFGET_(r32, 7, 6)
    #define   SET32InterPROP_partition(r32,v)                  _BFSET_(r32, 7, 6,v)
    #define   GET16InterPROP_partition(r16)                    _BFGET_(r16, 7, 6)
    #define   SET16InterPROP_partition(r16,v)                  _BFSET_(r16, 7, 6,v)

    #define   GET32InterPROP_motion_0i(r32)                    _BFGET_(r32, 9, 8)
    #define   SET32InterPROP_motion_0i(r32,v)                  _BFSET_(r32, 9, 8,v)
    #define   GET16InterPROP_motion_0i(r16)                    _BFGET_(r16, 9, 8)
    #define   SET16InterPROP_motion_0i(r16,v)                  _BFSET_(r16, 9, 8,v)

    #define   GET32InterPROP_motion_1i(r32)                    _BFGET_(r32,11,10)
    #define   SET32InterPROP_motion_1i(r32,v)                  _BFSET_(r32,11,10,v)
    #define   GET16InterPROP_motion_1i(r16)                    _BFGET_(r16,11,10)
    #define   SET16InterPROP_motion_1i(r16,v)                  _BFSET_(r16,11,10,v)

    #define   GET32InterPROP_mvs_0i(r32)                       _BFGET_(r32,13,12)
    #define   SET32InterPROP_mvs_0i(r32,v)                     _BFSET_(r32,13,12,v)
    #define   GET16InterPROP_mvs_0i(r16)                       _BFGET_(r16,13,12)
    #define   SET16InterPROP_mvs_0i(r16,v)                     _BFSET_(r16,13,12,v)

    #define   GET32InterPROP_mvs_1i(r32)                       _BFGET_(r32,15,14)
    #define   SET32InterPROP_mvs_1i(r32,v)                     _BFSET_(r32,15,14,v)
    #define   GET16InterPROP_mvs_1i(r16)                       _BFGET_(r16,15,14)
    #define   SET16InterPROP_mvs_1i(r16,v)                     _BFSET_(r16,15,14,v)

            UNSG32 u_type                                      :  3;
            UNSG32 u_8x8IDX0                                   :  1;
            UNSG32 u_t8x8I                                     :  1;
            UNSG32 u_t8x8PB                                    :  1;
            UNSG32 u_partition                                 :  2;
            UNSG32 u_motion_0i                                 :  2;
            UNSG32 u_motion_1i                                 :  2;
            UNSG32 u_mvs_0i                                    :  2;
            UNSG32 u_mvs_1i                                    :  2;
            UNSG32 RSVDx0_b16                                  : 16;
    ///////////////////////////////////////////////////////////
    } SIE_InterPROP;

    ///////////////////////////////////////////////////////////
     SIGN32 InterPROP_drvrd(SIE_InterPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 InterPROP_drvwr(SIE_InterPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void InterPROP_reset(SIE_InterPROP *p);
     SIGN32 InterPROP_cmp  (SIE_InterPROP *p, SIE_InterPROP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define InterPROP_check(p,pie,pfx,hLOG) InterPROP_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define InterPROP_print(p,    pfx,hLOG) InterPROP_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: InterPROP
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ResPROP_VC1                              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 8  MaxNumCoeff               
///                                    ###
///                                    * Maximal number of coefficients to decode,
///                                    * The valid number is: 16, 32, 63, and 64
///                                    ###
///               %unsigned 3  eBlk                      
///                                    ###
///                                    * 8x8 Block index. 0~3 for Y, 4 for Cb, 5 for Cr
///                                    ###
///               %unsigned 1  IsIntra                   
///                                    ###
///                                    * 1: intra block
///                                    * 0: inter block
///                                    ###
///               %unsigned 2  SubBlkIdx                 
///                                    ###
///                                    * Sub-block index in 8x8 block. Unit is 4x4 regardless of transform type.
///                                    ###
///               %unsigned 2  TransTypeOrIpMode         
///                                    ###
///                                    * For inter block, this field contain transform type information.
///                                    ###
///                                    : TRANS_4x4                 0x0
///                                    : TRANS_4x8                 0x1
///                                    : TRANS_8x4                 0x2
///                                    : TRANS_8x8                 0x3
///                                                 ###
///                                                 * For intra block, this field is intra prediction mode.
///                                                 ###
///                                    : IP_NORMAL                 0x0
///                                    : IP_HORIZONTAL             0x1
///                                    : IP_VERTICAL               0x2
///               %%        16         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      16b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ResPROP_VC1
#define h_ResPROP_VC1 (){}

    #define     BA_ResPROP_VC1_MaxNumCoeff                     0x0000
    #define     B16ResPROP_VC1_MaxNumCoeff                     0x0000
    #define   LSb32ResPROP_VC1_MaxNumCoeff                        0
    #define   LSb16ResPROP_VC1_MaxNumCoeff                        0
    #define       bResPROP_VC1_MaxNumCoeff                     8
    #define   MSK32ResPROP_VC1_MaxNumCoeff                        0x000000FF

    #define     BA_ResPROP_VC1_eBlk                            0x0001
    #define     B16ResPROP_VC1_eBlk                            0x0000
    #define   LSb32ResPROP_VC1_eBlk                               8
    #define   LSb16ResPROP_VC1_eBlk                               8
    #define       bResPROP_VC1_eBlk                            3
    #define   MSK32ResPROP_VC1_eBlk                               0x00000700

    #define     BA_ResPROP_VC1_IsIntra                         0x0001
    #define     B16ResPROP_VC1_IsIntra                         0x0000
    #define   LSb32ResPROP_VC1_IsIntra                            11
    #define   LSb16ResPROP_VC1_IsIntra                            11
    #define       bResPROP_VC1_IsIntra                         1
    #define   MSK32ResPROP_VC1_IsIntra                            0x00000800

    #define     BA_ResPROP_VC1_SubBlkIdx                       0x0001
    #define     B16ResPROP_VC1_SubBlkIdx                       0x0000
    #define   LSb32ResPROP_VC1_SubBlkIdx                          12
    #define   LSb16ResPROP_VC1_SubBlkIdx                          12
    #define       bResPROP_VC1_SubBlkIdx                       2
    #define   MSK32ResPROP_VC1_SubBlkIdx                          0x00003000

    #define     BA_ResPROP_VC1_TransTypeOrIpMode               0x0001
    #define     B16ResPROP_VC1_TransTypeOrIpMode               0x0000
    #define   LSb32ResPROP_VC1_TransTypeOrIpMode                  14
    #define   LSb16ResPROP_VC1_TransTypeOrIpMode                  14
    #define       bResPROP_VC1_TransTypeOrIpMode               2
    #define   MSK32ResPROP_VC1_TransTypeOrIpMode                  0x0000C000
    #define        ResPROP_VC1_TransTypeOrIpMode_TRANS_4x4                  0x0
    #define        ResPROP_VC1_TransTypeOrIpMode_TRANS_4x8                  0x1
    #define        ResPROP_VC1_TransTypeOrIpMode_TRANS_8x4                  0x2
    #define        ResPROP_VC1_TransTypeOrIpMode_TRANS_8x8                  0x3
    #define        ResPROP_VC1_TransTypeOrIpMode_IP_NORMAL                  0x0
    #define        ResPROP_VC1_TransTypeOrIpMode_IP_HORIZONTAL              0x1
    #define        ResPROP_VC1_TransTypeOrIpMode_IP_VERTICAL                0x2
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ResPROP_VC1 {
    ///////////////////////////////////////////////////////////
    #define   GET32ResPROP_VC1_MaxNumCoeff(r32)                _BFGET_(r32, 7, 0)
    #define   SET32ResPROP_VC1_MaxNumCoeff(r32,v)              _BFSET_(r32, 7, 0,v)
    #define   GET16ResPROP_VC1_MaxNumCoeff(r16)                _BFGET_(r16, 7, 0)
    #define   SET16ResPROP_VC1_MaxNumCoeff(r16,v)              _BFSET_(r16, 7, 0,v)

    #define   GET32ResPROP_VC1_eBlk(r32)                       _BFGET_(r32,10, 8)
    #define   SET32ResPROP_VC1_eBlk(r32,v)                     _BFSET_(r32,10, 8,v)
    #define   GET16ResPROP_VC1_eBlk(r16)                       _BFGET_(r16,10, 8)
    #define   SET16ResPROP_VC1_eBlk(r16,v)                     _BFSET_(r16,10, 8,v)

    #define   GET32ResPROP_VC1_IsIntra(r32)                    _BFGET_(r32,11,11)
    #define   SET32ResPROP_VC1_IsIntra(r32,v)                  _BFSET_(r32,11,11,v)
    #define   GET16ResPROP_VC1_IsIntra(r16)                    _BFGET_(r16,11,11)
    #define   SET16ResPROP_VC1_IsIntra(r16,v)                  _BFSET_(r16,11,11,v)

    #define   GET32ResPROP_VC1_SubBlkIdx(r32)                  _BFGET_(r32,13,12)
    #define   SET32ResPROP_VC1_SubBlkIdx(r32,v)                _BFSET_(r32,13,12,v)
    #define   GET16ResPROP_VC1_SubBlkIdx(r16)                  _BFGET_(r16,13,12)
    #define   SET16ResPROP_VC1_SubBlkIdx(r16,v)                _BFSET_(r16,13,12,v)

    #define   GET32ResPROP_VC1_TransTypeOrIpMode(r32)          _BFGET_(r32,15,14)
    #define   SET32ResPROP_VC1_TransTypeOrIpMode(r32,v)        _BFSET_(r32,15,14,v)
    #define   GET16ResPROP_VC1_TransTypeOrIpMode(r16)          _BFGET_(r16,15,14)
    #define   SET16ResPROP_VC1_TransTypeOrIpMode(r16,v)        _BFSET_(r16,15,14,v)

            UNSG32 u_MaxNumCoeff                               :  8;
            UNSG32 u_eBlk                                      :  3;
            UNSG32 u_IsIntra                                   :  1;
            UNSG32 u_SubBlkIdx                                 :  2;
            UNSG32 u_TransTypeOrIpMode                         :  2;
            UNSG32 RSVDx0_b16                                  : 16;
    ///////////////////////////////////////////////////////////
    } SIE_ResPROP_VC1;

    ///////////////////////////////////////////////////////////
     SIGN32 ResPROP_VC1_drvrd(SIE_ResPROP_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ResPROP_VC1_drvwr(SIE_ResPROP_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ResPROP_VC1_reset(SIE_ResPROP_VC1 *p);
     SIGN32 ResPROP_VC1_cmp  (SIE_ResPROP_VC1 *p, SIE_ResPROP_VC1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ResPROP_VC1_check(p,pie,pfx,hLOG) ResPROP_VC1_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ResPROP_VC1_print(p,    pfx,hLOG) ResPROP_VC1_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ResPROP_VC1
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ResPROP_MPEG2                            (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 1  Intra_MB                  
///                                    : inter                     0x0
///                                    : intra                     0x1
///                                                 ###
///                                                 * Indicate current MB is inter-coded or intra-coded
///                                                 ###
///               %unsigned 1  CC                        
///                                    : luma                      0x0
///                                    : chroma                    0x1
///                                                 ###
///                                                 * Color component (to select VLC table)
///                                                 ###
///               %unsigned 1  intra_vlc_format          
///                                    ###
///                                    * Whether to use intra VLC DC table or inter table
///                                    * End of ResProp_MPEG2
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       3b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ResPROP_MPEG2
#define h_ResPROP_MPEG2 (){}

    #define     BA_ResPROP_MPEG2_Intra_MB                      0x0000
    #define     B16ResPROP_MPEG2_Intra_MB                      0x0000
    #define   LSb32ResPROP_MPEG2_Intra_MB                         0
    #define   LSb16ResPROP_MPEG2_Intra_MB                         0
    #define       bResPROP_MPEG2_Intra_MB                      1
    #define   MSK32ResPROP_MPEG2_Intra_MB                         0x00000001
    #define        ResPROP_MPEG2_Intra_MB_inter                             0x0
    #define        ResPROP_MPEG2_Intra_MB_intra                             0x1

    #define     BA_ResPROP_MPEG2_CC                            0x0000
    #define     B16ResPROP_MPEG2_CC                            0x0000
    #define   LSb32ResPROP_MPEG2_CC                               1
    #define   LSb16ResPROP_MPEG2_CC                               1
    #define       bResPROP_MPEG2_CC                            1
    #define   MSK32ResPROP_MPEG2_CC                               0x00000002
    #define        ResPROP_MPEG2_CC_luma                                    0x0
    #define        ResPROP_MPEG2_CC_chroma                                  0x1

    #define     BA_ResPROP_MPEG2_intra_vlc_format              0x0000
    #define     B16ResPROP_MPEG2_intra_vlc_format              0x0000
    #define   LSb32ResPROP_MPEG2_intra_vlc_format                 2
    #define   LSb16ResPROP_MPEG2_intra_vlc_format                 2
    #define       bResPROP_MPEG2_intra_vlc_format              1
    #define   MSK32ResPROP_MPEG2_intra_vlc_format                 0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ResPROP_MPEG2 {
    ///////////////////////////////////////////////////////////
    #define   GET32ResPROP_MPEG2_Intra_MB(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32ResPROP_MPEG2_Intra_MB(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16ResPROP_MPEG2_Intra_MB(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16ResPROP_MPEG2_Intra_MB(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32ResPROP_MPEG2_CC(r32)                       _BFGET_(r32, 1, 1)
    #define   SET32ResPROP_MPEG2_CC(r32,v)                     _BFSET_(r32, 1, 1,v)
    #define   GET16ResPROP_MPEG2_CC(r16)                       _BFGET_(r16, 1, 1)
    #define   SET16ResPROP_MPEG2_CC(r16,v)                     _BFSET_(r16, 1, 1,v)

    #define   GET32ResPROP_MPEG2_intra_vlc_format(r32)         _BFGET_(r32, 2, 2)
    #define   SET32ResPROP_MPEG2_intra_vlc_format(r32,v)       _BFSET_(r32, 2, 2,v)
    #define   GET16ResPROP_MPEG2_intra_vlc_format(r16)         _BFGET_(r16, 2, 2)
    #define   SET16ResPROP_MPEG2_intra_vlc_format(r16,v)       _BFSET_(r16, 2, 2,v)

            UNSG32 u_Intra_MB                                  :  1;
            UNSG32 u_CC                                        :  1;
            UNSG32 u_intra_vlc_format                          :  1;
            UNSG32 RSVDx0_b3                                   : 29;
    ///////////////////////////////////////////////////////////
    } SIE_ResPROP_MPEG2;

    ///////////////////////////////////////////////////////////
     SIGN32 ResPROP_MPEG2_drvrd(SIE_ResPROP_MPEG2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ResPROP_MPEG2_drvwr(SIE_ResPROP_MPEG2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ResPROP_MPEG2_reset(SIE_ResPROP_MPEG2 *p);
     SIGN32 ResPROP_MPEG2_cmp  (SIE_ResPROP_MPEG2 *p, SIE_ResPROP_MPEG2 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ResPROP_MPEG2_check(p,pie,pfx,hLOG) ResPROP_MPEG2_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ResPROP_MPEG2_print(p,    pfx,hLOG) ResPROP_MPEG2_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ResPROP_MPEG2
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ResPROP_MPEG4                            (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 1  Intra_MB                  
///                                    : inter                     0x0
///                                    : intra                     0x1
///                                                 ###
///                                                 * Indicate current MB is inter-coded or intra-coded
///                                                 ###
///               %unsigned 1  CC                        
///                                    : luma                      0x0
///                                    : chroma                    0x1
///                                                 ###
///                                                 * Color component (to select VLC table)
///                                                 ###
///               %unsigned 1  use_intra_dc_vlc          
///                                    ###
///                                    * Whether to use intra VLC DC table or inter table
///                                    ###
///               %unsigned 1  pattern_code              
///                                    ###
///                                    * Indicate whether to encode AC coefficients
///                                    ###
///               %unsigned 2  scan_order                
///                                    : normal                    0x0
///                                    : horizontal                0x1
///                                    : vertical                  0x2
///                                                 ###
///                                                 * Indicate zigzag scan order of 8x8 coefficients
///                                                 * End of ResProp_MPEG4
///                                                 ###
///               %%        26         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ResPROP_MPEG4
#define h_ResPROP_MPEG4 (){}

    #define     BA_ResPROP_MPEG4_Intra_MB                      0x0000
    #define     B16ResPROP_MPEG4_Intra_MB                      0x0000
    #define   LSb32ResPROP_MPEG4_Intra_MB                         0
    #define   LSb16ResPROP_MPEG4_Intra_MB                         0
    #define       bResPROP_MPEG4_Intra_MB                      1
    #define   MSK32ResPROP_MPEG4_Intra_MB                         0x00000001
    #define        ResPROP_MPEG4_Intra_MB_inter                             0x0
    #define        ResPROP_MPEG4_Intra_MB_intra                             0x1

    #define     BA_ResPROP_MPEG4_CC                            0x0000
    #define     B16ResPROP_MPEG4_CC                            0x0000
    #define   LSb32ResPROP_MPEG4_CC                               1
    #define   LSb16ResPROP_MPEG4_CC                               1
    #define       bResPROP_MPEG4_CC                            1
    #define   MSK32ResPROP_MPEG4_CC                               0x00000002
    #define        ResPROP_MPEG4_CC_luma                                    0x0
    #define        ResPROP_MPEG4_CC_chroma                                  0x1

    #define     BA_ResPROP_MPEG4_use_intra_dc_vlc              0x0000
    #define     B16ResPROP_MPEG4_use_intra_dc_vlc              0x0000
    #define   LSb32ResPROP_MPEG4_use_intra_dc_vlc                 2
    #define   LSb16ResPROP_MPEG4_use_intra_dc_vlc                 2
    #define       bResPROP_MPEG4_use_intra_dc_vlc              1
    #define   MSK32ResPROP_MPEG4_use_intra_dc_vlc                 0x00000004

    #define     BA_ResPROP_MPEG4_pattern_code                  0x0000
    #define     B16ResPROP_MPEG4_pattern_code                  0x0000
    #define   LSb32ResPROP_MPEG4_pattern_code                     3
    #define   LSb16ResPROP_MPEG4_pattern_code                     3
    #define       bResPROP_MPEG4_pattern_code                  1
    #define   MSK32ResPROP_MPEG4_pattern_code                     0x00000008

    #define     BA_ResPROP_MPEG4_scan_order                    0x0000
    #define     B16ResPROP_MPEG4_scan_order                    0x0000
    #define   LSb32ResPROP_MPEG4_scan_order                       4
    #define   LSb16ResPROP_MPEG4_scan_order                       4
    #define       bResPROP_MPEG4_scan_order                    2
    #define   MSK32ResPROP_MPEG4_scan_order                       0x00000030
    #define        ResPROP_MPEG4_scan_order_normal                          0x0
    #define        ResPROP_MPEG4_scan_order_horizontal                      0x1
    #define        ResPROP_MPEG4_scan_order_vertical                        0x2
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ResPROP_MPEG4 {
    ///////////////////////////////////////////////////////////
    #define   GET32ResPROP_MPEG4_Intra_MB(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32ResPROP_MPEG4_Intra_MB(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16ResPROP_MPEG4_Intra_MB(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16ResPROP_MPEG4_Intra_MB(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32ResPROP_MPEG4_CC(r32)                       _BFGET_(r32, 1, 1)
    #define   SET32ResPROP_MPEG4_CC(r32,v)                     _BFSET_(r32, 1, 1,v)
    #define   GET16ResPROP_MPEG4_CC(r16)                       _BFGET_(r16, 1, 1)
    #define   SET16ResPROP_MPEG4_CC(r16,v)                     _BFSET_(r16, 1, 1,v)

    #define   GET32ResPROP_MPEG4_use_intra_dc_vlc(r32)         _BFGET_(r32, 2, 2)
    #define   SET32ResPROP_MPEG4_use_intra_dc_vlc(r32,v)       _BFSET_(r32, 2, 2,v)
    #define   GET16ResPROP_MPEG4_use_intra_dc_vlc(r16)         _BFGET_(r16, 2, 2)
    #define   SET16ResPROP_MPEG4_use_intra_dc_vlc(r16,v)       _BFSET_(r16, 2, 2,v)

    #define   GET32ResPROP_MPEG4_pattern_code(r32)             _BFGET_(r32, 3, 3)
    #define   SET32ResPROP_MPEG4_pattern_code(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16ResPROP_MPEG4_pattern_code(r16)             _BFGET_(r16, 3, 3)
    #define   SET16ResPROP_MPEG4_pattern_code(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32ResPROP_MPEG4_scan_order(r32)               _BFGET_(r32, 5, 4)
    #define   SET32ResPROP_MPEG4_scan_order(r32,v)             _BFSET_(r32, 5, 4,v)
    #define   GET16ResPROP_MPEG4_scan_order(r16)               _BFGET_(r16, 5, 4)
    #define   SET16ResPROP_MPEG4_scan_order(r16,v)             _BFSET_(r16, 5, 4,v)

            UNSG32 u_Intra_MB                                  :  1;
            UNSG32 u_CC                                        :  1;
            UNSG32 u_use_intra_dc_vlc                          :  1;
            UNSG32 u_pattern_code                              :  1;
            UNSG32 u_scan_order                                :  2;
            UNSG32 RSVDx0_b6                                   : 26;
    ///////////////////////////////////////////////////////////
    } SIE_ResPROP_MPEG4;

    ///////////////////////////////////////////////////////////
     SIGN32 ResPROP_MPEG4_drvrd(SIE_ResPROP_MPEG4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ResPROP_MPEG4_drvwr(SIE_ResPROP_MPEG4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ResPROP_MPEG4_reset(SIE_ResPROP_MPEG4 *p);
     SIGN32 ResPROP_MPEG4_cmp  (SIE_ResPROP_MPEG4 *p, SIE_ResPROP_MPEG4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ResPROP_MPEG4_check(p,pie,pfx,hLOG) ResPROP_MPEG4_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ResPROP_MPEG4_print(p,    pfx,hLOG) ResPROP_MPEG4_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ResPROP_MPEG4
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ResPROP_JPEG                             (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 1  DCTblId                   
///                                    : luma                      0x0
///                                    : chroma                    0x1
///                                                 ###
///                                                 * Selects Huffman table used to decode or encode DC coefficients
///                                                 ###
///               %unsigned 1  ACTblId                   
///                                    : luma                      0x0
///                                    : chroma                    0x1
///                                                 ###
///                                                 * Selects Huffman table used to decode or encode AC coefficients
///                                                 * End of ResPROP_JPEG
///                                                 ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       2b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ResPROP_JPEG
#define h_ResPROP_JPEG (){}

    #define     BA_ResPROP_JPEG_DCTblId                        0x0000
    #define     B16ResPROP_JPEG_DCTblId                        0x0000
    #define   LSb32ResPROP_JPEG_DCTblId                           0
    #define   LSb16ResPROP_JPEG_DCTblId                           0
    #define       bResPROP_JPEG_DCTblId                        1
    #define   MSK32ResPROP_JPEG_DCTblId                           0x00000001
    #define        ResPROP_JPEG_DCTblId_luma                                0x0
    #define        ResPROP_JPEG_DCTblId_chroma                              0x1

    #define     BA_ResPROP_JPEG_ACTblId                        0x0000
    #define     B16ResPROP_JPEG_ACTblId                        0x0000
    #define   LSb32ResPROP_JPEG_ACTblId                           1
    #define   LSb16ResPROP_JPEG_ACTblId                           1
    #define       bResPROP_JPEG_ACTblId                        1
    #define   MSK32ResPROP_JPEG_ACTblId                           0x00000002
    #define        ResPROP_JPEG_ACTblId_luma                                0x0
    #define        ResPROP_JPEG_ACTblId_chroma                              0x1
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ResPROP_JPEG {
    ///////////////////////////////////////////////////////////
    #define   GET32ResPROP_JPEG_DCTblId(r32)                   _BFGET_(r32, 0, 0)
    #define   SET32ResPROP_JPEG_DCTblId(r32,v)                 _BFSET_(r32, 0, 0,v)
    #define   GET16ResPROP_JPEG_DCTblId(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16ResPROP_JPEG_DCTblId(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define   GET32ResPROP_JPEG_ACTblId(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32ResPROP_JPEG_ACTblId(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16ResPROP_JPEG_ACTblId(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16ResPROP_JPEG_ACTblId(r16,v)                 _BFSET_(r16, 1, 1,v)

            UNSG32 u_DCTblId                                   :  1;
            UNSG32 u_ACTblId                                   :  1;
            UNSG32 RSVDx0_b2                                   : 30;
    ///////////////////////////////////////////////////////////
    } SIE_ResPROP_JPEG;

    ///////////////////////////////////////////////////////////
     SIGN32 ResPROP_JPEG_drvrd(SIE_ResPROP_JPEG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ResPROP_JPEG_drvwr(SIE_ResPROP_JPEG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ResPROP_JPEG_reset(SIE_ResPROP_JPEG *p);
     SIGN32 ResPROP_JPEG_cmp  (SIE_ResPROP_JPEG *p, SIE_ResPROP_JPEG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ResPROP_JPEG_check(p,pie,pfx,hLOG) ResPROP_JPEG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ResPROP_JPEG_print(p,    pfx,hLOG) ResPROP_JPEG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ResPROP_JPEG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TotalCoeff6                              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 5  nc_0i                     
///               %unsigned 5  nc_1i                     
///               %unsigned 5  nc_2i                     
///                                    ###
///                                    * The number of non-zero transform coefficients in a 4x4 Y or UV coefficient block. Totally 3 blocks are in order 0 ~ 2.
///                                    ###
///               %%        1          # Stuffing bits...
///               %unsigned 5  nc1_0i                    
///               %unsigned 5  nc1_1i                    
///               %unsigned 5  nc1_2i                    
///               %%        1          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      30b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TotalCoeff6
#define h_TotalCoeff6 (){}

    #define     BA_TotalCoeff6_nc_0i                           0x0000
    #define     B16TotalCoeff6_nc_0i                           0x0000
    #define   LSb32TotalCoeff6_nc_0i                              0
    #define   LSb16TotalCoeff6_nc_0i                              0
    #define       bTotalCoeff6_nc_0i                           5
    #define   MSK32TotalCoeff6_nc_0i                              0x0000001F

    #define     BA_TotalCoeff6_nc_1i                           0x0000
    #define     B16TotalCoeff6_nc_1i                           0x0000
    #define   LSb32TotalCoeff6_nc_1i                              5
    #define   LSb16TotalCoeff6_nc_1i                              5
    #define       bTotalCoeff6_nc_1i                           5
    #define   MSK32TotalCoeff6_nc_1i                              0x000003E0

    #define     BA_TotalCoeff6_nc_2i                           0x0001
    #define     B16TotalCoeff6_nc_2i                           0x0000
    #define   LSb32TotalCoeff6_nc_2i                              10
    #define   LSb16TotalCoeff6_nc_2i                              10
    #define       bTotalCoeff6_nc_2i                           5
    #define   MSK32TotalCoeff6_nc_2i                              0x00007C00

    #define     BA_TotalCoeff6_nc1_0i                          0x0002
    #define     B16TotalCoeff6_nc1_0i                          0x0002
    #define   LSb32TotalCoeff6_nc1_0i                             16
    #define   LSb16TotalCoeff6_nc1_0i                             0
    #define       bTotalCoeff6_nc1_0i                          5
    #define   MSK32TotalCoeff6_nc1_0i                             0x001F0000

    #define     BA_TotalCoeff6_nc1_1i                          0x0002
    #define     B16TotalCoeff6_nc1_1i                          0x0002
    #define   LSb32TotalCoeff6_nc1_1i                             21
    #define   LSb16TotalCoeff6_nc1_1i                             5
    #define       bTotalCoeff6_nc1_1i                          5
    #define   MSK32TotalCoeff6_nc1_1i                             0x03E00000

    #define     BA_TotalCoeff6_nc1_2i                          0x0003
    #define     B16TotalCoeff6_nc1_2i                          0x0002
    #define   LSb32TotalCoeff6_nc1_2i                             26
    #define   LSb16TotalCoeff6_nc1_2i                             10
    #define       bTotalCoeff6_nc1_2i                          5
    #define   MSK32TotalCoeff6_nc1_2i                             0x7C000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TotalCoeff6 {
    ///////////////////////////////////////////////////////////
    #define   GET32TotalCoeff6_nc_0i(r32)                      _BFGET_(r32, 4, 0)
    #define   SET32TotalCoeff6_nc_0i(r32,v)                    _BFSET_(r32, 4, 0,v)
    #define   GET16TotalCoeff6_nc_0i(r16)                      _BFGET_(r16, 4, 0)
    #define   SET16TotalCoeff6_nc_0i(r16,v)                    _BFSET_(r16, 4, 0,v)

    #define   GET32TotalCoeff6_nc_1i(r32)                      _BFGET_(r32, 9, 5)
    #define   SET32TotalCoeff6_nc_1i(r32,v)                    _BFSET_(r32, 9, 5,v)
    #define   GET16TotalCoeff6_nc_1i(r16)                      _BFGET_(r16, 9, 5)
    #define   SET16TotalCoeff6_nc_1i(r16,v)                    _BFSET_(r16, 9, 5,v)

    #define   GET32TotalCoeff6_nc_2i(r32)                      _BFGET_(r32,14,10)
    #define   SET32TotalCoeff6_nc_2i(r32,v)                    _BFSET_(r32,14,10,v)
    #define   GET16TotalCoeff6_nc_2i(r16)                      _BFGET_(r16,14,10)
    #define   SET16TotalCoeff6_nc_2i(r16,v)                    _BFSET_(r16,14,10,v)

    #define   GET32TotalCoeff6_nc1_0i(r32)                     _BFGET_(r32,20,16)
    #define   SET32TotalCoeff6_nc1_0i(r32,v)                   _BFSET_(r32,20,16,v)
    #define   GET16TotalCoeff6_nc1_0i(r16)                     _BFGET_(r16, 4, 0)
    #define   SET16TotalCoeff6_nc1_0i(r16,v)                   _BFSET_(r16, 4, 0,v)

    #define   GET32TotalCoeff6_nc1_1i(r32)                     _BFGET_(r32,25,21)
    #define   SET32TotalCoeff6_nc1_1i(r32,v)                   _BFSET_(r32,25,21,v)
    #define   GET16TotalCoeff6_nc1_1i(r16)                     _BFGET_(r16, 9, 5)
    #define   SET16TotalCoeff6_nc1_1i(r16,v)                   _BFSET_(r16, 9, 5,v)

    #define   GET32TotalCoeff6_nc1_2i(r32)                     _BFGET_(r32,30,26)
    #define   SET32TotalCoeff6_nc1_2i(r32,v)                   _BFSET_(r32,30,26,v)
    #define   GET16TotalCoeff6_nc1_2i(r16)                     _BFGET_(r16,14,10)
    #define   SET16TotalCoeff6_nc1_2i(r16,v)                   _BFSET_(r16,14,10,v)

            UNSG32 u_nc_0i                                     :  5;
            UNSG32 u_nc_1i                                     :  5;
            UNSG32 u_nc_2i                                     :  5;
            UNSG32 RSVDx0_b15                                  :  1;
            UNSG32 u_nc1_0i                                    :  5;
            UNSG32 u_nc1_1i                                    :  5;
            UNSG32 u_nc1_2i                                    :  5;
            UNSG32 RSVDx0_b31                                  :  1;
    ///////////////////////////////////////////////////////////
    } SIE_TotalCoeff6;

    ///////////////////////////////////////////////////////////
     SIGN32 TotalCoeff6_drvrd(SIE_TotalCoeff6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TotalCoeff6_drvwr(SIE_TotalCoeff6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TotalCoeff6_reset(SIE_TotalCoeff6 *p);
     SIGN32 TotalCoeff6_cmp  (SIE_TotalCoeff6 *p, SIE_TotalCoeff6 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TotalCoeff6_check(p,pie,pfx,hLOG) TotalCoeff6_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TotalCoeff6_print(p,    pfx,hLOG) TotalCoeff6_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TotalCoeff6
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ASEPopTotalCoeff                         (4,2)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 TotalCoeff           
///               $TotalCoeff6         TotalCoeff        REG       [2]
///                                    ###
///                                    * The number of non-zero transform coefficients in a 4x4 Y or UV coefficient block in 3 block group. Totally 12 blocks in 4 groups are in order 0 ~ 11.
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      60b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ASEPopTotalCoeff
#define h_ASEPopTotalCoeff (){}

    #define     RA_ASEPopTotalCoeff_TotalCoeff                 0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ASEPopTotalCoeff {
    ///////////////////////////////////////////////////////////
              SIE_TotalCoeff6                                  ie_TotalCoeff[2];
    ///////////////////////////////////////////////////////////
    } SIE_ASEPopTotalCoeff;

    ///////////////////////////////////////////////////////////
     SIGN32 ASEPopTotalCoeff_drvrd(SIE_ASEPopTotalCoeff *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ASEPopTotalCoeff_drvwr(SIE_ASEPopTotalCoeff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ASEPopTotalCoeff_reset(SIE_ASEPopTotalCoeff *p);
     SIGN32 ASEPopTotalCoeff_cmp  (SIE_ASEPopTotalCoeff *p, SIE_ASEPopTotalCoeff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ASEPopTotalCoeff_check(p,pie,pfx,hLOG) ASEPopTotalCoeff_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ASEPopTotalCoeff_print(p,    pfx,hLOG) ASEPopTotalCoeff_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ASEPopTotalCoeff
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE RF64PIC                 biu              (4,4)
///     ###
///     * RF64 picture-level information for ALU64 extensions; padded to 64b. Used in placed of BIU register for efficiency. Parameters in this interface should only be updated at the slice boundary.
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 3  format                    
///                                    : h264                      0x0
///                                    : wmv                       0x1
///                                                 ###
///                                                 * VC-1 Main Profile
///                                                 ###
///                                    : mpg2                      0x2
///                                    : other                     0x3
///                                    : mpg4                      0x4
///                                    : vc1ap                     0x5
///                                                 ###
///                                                 * VC-1 Advanced Profile
///                                                 ###
///                                    : h263                      0x6
///                                    : avs                       0x7
///                                                 ###
///                                                 * Format of the current video stream
///                                                 ###
///               %unsigned 1  cabac                     
///                                    ###
///                                    * Whether current slice is coded in CABAC
///                                    ###
///               %unsigned 2  picType                   
///                                    : I                         0x0
///                                    : P                         0x1
///                                    : B                         0x2
///                                                 ###
///                                                 * Used by PMV to qualify between P_skip & B_skip
///                                                 ###
///               %unsigned 5  maxL0                     
///                                    ###
///                                    * H264: num_ref_idx_l0_active_minus1
///                                    ###
///               %unsigned 5  maxL1                     
///                                    ###
///                                    * H264: num_ref_idx_l1_active_minus1
///                                    ###
///               %unsigned 1  MbaffPic                  
///                                    ###
///                                    * Whether current picture is Mbaff pic or not; for FOP
///                                    * For VC-1:
///                                    * (~Mbaffpic && ~fieldPic) -> progressive
///                                    * (Mbaffpic && ~fieldPic) -> interlace frame
///                                    ###
///               %unsigned 1  fieldPic                  
///                                    ###
///                                    * Whether current picture is field coded or not; for FOP
///                                    * For VC-1:
///                                    * (~MbaffPic && fieldPic) -> interlace field, one ref;
///                                    * (MbaffPic && fieldPic) -> interlace field, two ref
///                                    ###
///               %unsigned 1  spatialPred               
///                                    ###
///                                    * Spatial direct prediction modee; for dirMV.
///                                    ###
///               %unsigned 1  colPicMbaff               
///                                    ###
///                                    * Whether colocated pic is Mbaff pic or not; for dirMV
///                                    ###
///               %unsigned 1  colPicField               
///                                    ###
///                                    * Whether colocated picture is field pic or not; for dirMV
///                                    ###
///               %unsigned 1  colPicST                  
///                                    ###
///                                    * Co-located picture is a long-term (0) or short-term (1) reference picture; for dirMV.
///                                    ###
///               %signed   5  AC0Offset                 
///                                    ###
///                                    * = slice_alpha_c0_offset_div2<<1, -12 ~ +12, inclusive, even numbers only. For FOP only.
///                                    ###
///               %signed   5  BetaOffset                
///                                    ###
///                                    * = slice_beta_offset_div2<<1, -12 ~ +12, inclusive, even numbers only. For FOP only.
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 16 dqAcLimit                 
///                                    ###
///                                    * Saturation limit for AC dequantization
///                                    * Also apply for universal dequantization
///                                    ###
///               %unsigned 14 dqDcLimit                 
///                                    ###
///                                    * Saturation limit for DC dequantization
///                                    ###
///               %unsigned 2  mismatch                  
///                                    : none                      0x0
///                                    : mpeg1                     0x1
///                                    : mpeg2                     0x2
///                                                 ###
///                                                 * mismatch control, for AC dequant only
///                                                 ###
///     @ 0x00008                      (P)
///               %unsigned 16 picW                      
///                                    ###
///                                    * Width of current picture; up to 2047
///                                    ###
///               %unsigned 13 picH                      
///                                    ###
///                                    * Height of current picture; up to 2047. For vcMsg only
///                                    ###
///               %unsigned 1  btmFldPic                 
///                                    ###
///                                    * H.264: Current picture is bottom field; for vcMsg. Valid only when fieldPic==1.
///                                    ###
///               %unsigned 2  hint                      
///                                    ###
///                                    * Same as CacheMsg.hint; for vcMsg only
///                                    ###
///     @ 0x0000C                      (P)
///               %unsigned 8  shiftLumaX                
///                                    ###
///                                    * (For vcMsg only) Shift amount lookup table for Luma X direction. 4 entries, 2-bit per entry, indexed by mvx[1:0] in little-endian format
///                                    ###
///               %unsigned 8  shiftLumaY                
///                                    ###
///                                    * (For vcMsg only) Shift amount lookup table for Luma Y direction. 4 entries, 2-bit per entry, indexed by mvy[1:0] in little-endian format
///                                    ###
///               %unsigned 8  shiftChromaX              
///                                    ###
///                                    * (For vcMsg only) Shift amount lookup table for Chroma X direction. 4 entries, 2-bit per entry, indexed by mvx[1:0] in little-endian format
///                                    ###
///               %unsigned 8  shiftChromaY              
///                                    ###
///                                    * (For vcMsg only) Shift amount lookup table for Chroma Y direction. 4 entries, 2-bit per entry, indexed by mvy[1:0] in little-endian format
///                                    ###
///     @ 0x00010                      (P)
///               %unsigned 4  fracTapDiv2Y              
///                                    ###
///                                    * (Tap size / 2) for luma fractional MV interpolation
///                                    ###
///               %unsigned 4  fracTapDiv2C              
///                                    ###
///                                    * (Tap size / 2) for chroma fractional MV interpolation
///                                    ###
///               %unsigned 6  IPCM_QPU                  
///                                    ###
///                                    * QPU for IPCM coded MBs; for H.264 FOP
///                                    ###
///               %unsigned 6  IPCM_QPV                  
///                                    ###
///                                    * QPV for IPCM coded MBs; for H.264 FOP
///                                    ###
///               %unsigned 12 RSVD12                    
///                                    ###
///                                    * padding to 32 bits
///                                    ###
///     @ 0x00014                      (P)
///               %unsigned 5  PQUANT                    
///                                    ###
///                                    * picture-level quantization factor
///                                    ###
///               %unsigned 2  FRFD                      
///                                    ###
///                                    * Forward reference picture distance, 0~3.
///                                    * Used by VC1 for interlace P field PMV, or for interlace B field forward PMV
///                                    ###
///               %unsigned 2  BRFD                      
///                                    ###
///                                    * Backward reference picture distance, 0~3.
///                                    * Used by VC1 for interlace B field backward PMV
///                                    ###
///               %unsigned 1  secondFld                 
///                                    ###
///                                    * Used by PMV for interlace field picture: whether current field is 1st field or 2nd field of display picture
///                                    ###
///               %unsigned 2  mvRange                   
///                                    ###
///                                    * 0~3; used to lookup range_x & range_y for PMV; see VC-1 spec table 75.
///                                    ###
///               %unsigned 1  hybridMvThres             
///                                    ###
///                                    * 0: threshold = 16; 1: threshold = 32
///                                    ###
///               %unsigned 1  firstMbIntra              
///                                    ###
///                                    * 0: first MB or block is inter coded; 1: intra coded; used for VC-1 Fop
///                                    ###
///               %unsigned 1  halfPixel                 
///                                    ###
///                                    * Half pixel flag, for VC-1 PMV interlace field mode.
///                                    ###
///               %unsigned 1  forwRefInterlace          
///                                    ###
///                                    * For VC-1 interlace frame picture in VCMSG extension forward reference is 0: progressive coded; 1: interlace coded
///                                    ###
///               %unsigned 1  backRefInterlace          
///                                    ###
///                                    * For VC-1 interlace frame picture in VCMSG extension backward reference is 0: progressive coded; 1: interlace coded
///                                    ###
///               %unsigned 2  FrmTransACSet             
///                                    ###
///                                    * For VC-1 frame-level transform AC coding set selection (for Cb and Cr block; and inter Y block).
///                                    * Valid values are 0, 1, and 2
///                                    ###
///               %unsigned 2  FrmTransACSet2            
///                                    ###
///                                    * For VC-1 frame-level transform AC table-2 index selection (for I-frame Y block)
///                                    * Valid values are 0, 1, and 2
///                                    ###
///               %unsigned 1  PQIndexGT8                
///                                    ###
///                                    * Indicator to represent whether Picture Quantized Index (PQIndexG8, defined in Table 36 in VC-1 spec) is greater than 8.
///                                    * 0: value of PQIndex is less than or equal to 8
///                                    * 1: value of PQIndex is greater than 8
///                                    ###
///               %unsigned 1  EscapeTBL                 
///                                    ###
///                                    * For VC-1 to select escape table in residual decoding
///                                    ###
///               %unsigned 4  format1                   
///                                    : RV9                       0x0
///                                    : RV8                       0x1
///                                    : vp8                       0x2
///                                    : jpeg                      0x3
///               %unsigned 1  noReorder                 
///                                    ###
///                                    * For ASE, disable coefficient reorder.
///                                    ###
///               %unsigned 1  iplusModeOn               
///                                    ###
///                                    * For ASE, IPLUS mode is on or not.
///                                    ###
///               %unsigned 3  RSVD3                     
///                                    ###
///                                    * padding to 32 bits
///                                    ###
///     @ 0x00018                      (P)
///     # 0x00018 RSVD                 
///               $LUT64b              RSVD              REG       [5]
///                                    ###
///                                    * Reserved for alignment
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 rIDX2BID             
///               $IDX2BID             rIDX2BID          REG          
///                                    ###
///                                    * Defined in 'decHal_mbLvl.sxw.txt'
///                                    * End of RF64PIC
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     256B, bits:    2048b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_RF64PIC
#define h_RF64PIC (){}

    #define     BA_RF64PIC_format                              0x0000
    #define     B16RF64PIC_format                              0x0000
    #define   LSb32RF64PIC_format                                 0
    #define   LSb16RF64PIC_format                                 0
    #define       bRF64PIC_format                              3
    #define   MSK32RF64PIC_format                                 0x00000007
    #define        RF64PIC_format_h264                                      0x0
    #define        RF64PIC_format_wmv                                       0x1
    #define        RF64PIC_format_mpg2                                      0x2
    #define        RF64PIC_format_other                                     0x3
    #define        RF64PIC_format_mpg4                                      0x4
    #define        RF64PIC_format_vc1ap                                     0x5
    #define        RF64PIC_format_h263                                      0x6
    #define        RF64PIC_format_avs                                       0x7

    #define     BA_RF64PIC_cabac                               0x0000
    #define     B16RF64PIC_cabac                               0x0000
    #define   LSb32RF64PIC_cabac                                  3
    #define   LSb16RF64PIC_cabac                                  3
    #define       bRF64PIC_cabac                               1
    #define   MSK32RF64PIC_cabac                                  0x00000008

    #define     BA_RF64PIC_picType                             0x0000
    #define     B16RF64PIC_picType                             0x0000
    #define   LSb32RF64PIC_picType                                4
    #define   LSb16RF64PIC_picType                                4
    #define       bRF64PIC_picType                             2
    #define   MSK32RF64PIC_picType                                0x00000030
    #define        RF64PIC_picType_I                                        0x0
    #define        RF64PIC_picType_P                                        0x1
    #define        RF64PIC_picType_B                                        0x2

    #define     BA_RF64PIC_maxL0                               0x0000
    #define     B16RF64PIC_maxL0                               0x0000
    #define   LSb32RF64PIC_maxL0                                  6
    #define   LSb16RF64PIC_maxL0                                  6
    #define       bRF64PIC_maxL0                               5
    #define   MSK32RF64PIC_maxL0                                  0x000007C0

    #define     BA_RF64PIC_maxL1                               0x0001
    #define     B16RF64PIC_maxL1                               0x0000
    #define   LSb32RF64PIC_maxL1                                  11
    #define   LSb16RF64PIC_maxL1                                  11
    #define       bRF64PIC_maxL1                               5
    #define   MSK32RF64PIC_maxL1                                  0x0000F800

    #define     BA_RF64PIC_MbaffPic                            0x0002
    #define     B16RF64PIC_MbaffPic                            0x0002
    #define   LSb32RF64PIC_MbaffPic                               16
    #define   LSb16RF64PIC_MbaffPic                               0
    #define       bRF64PIC_MbaffPic                            1
    #define   MSK32RF64PIC_MbaffPic                               0x00010000

    #define     BA_RF64PIC_fieldPic                            0x0002
    #define     B16RF64PIC_fieldPic                            0x0002
    #define   LSb32RF64PIC_fieldPic                               17
    #define   LSb16RF64PIC_fieldPic                               1
    #define       bRF64PIC_fieldPic                            1
    #define   MSK32RF64PIC_fieldPic                               0x00020000

    #define     BA_RF64PIC_spatialPred                         0x0002
    #define     B16RF64PIC_spatialPred                         0x0002
    #define   LSb32RF64PIC_spatialPred                            18
    #define   LSb16RF64PIC_spatialPred                            2
    #define       bRF64PIC_spatialPred                         1
    #define   MSK32RF64PIC_spatialPred                            0x00040000

    #define     BA_RF64PIC_colPicMbaff                         0x0002
    #define     B16RF64PIC_colPicMbaff                         0x0002
    #define   LSb32RF64PIC_colPicMbaff                            19
    #define   LSb16RF64PIC_colPicMbaff                            3
    #define       bRF64PIC_colPicMbaff                         1
    #define   MSK32RF64PIC_colPicMbaff                            0x00080000

    #define     BA_RF64PIC_colPicField                         0x0002
    #define     B16RF64PIC_colPicField                         0x0002
    #define   LSb32RF64PIC_colPicField                            20
    #define   LSb16RF64PIC_colPicField                            4
    #define       bRF64PIC_colPicField                         1
    #define   MSK32RF64PIC_colPicField                            0x00100000

    #define     BA_RF64PIC_colPicST                            0x0002
    #define     B16RF64PIC_colPicST                            0x0002
    #define   LSb32RF64PIC_colPicST                               21
    #define   LSb16RF64PIC_colPicST                               5
    #define       bRF64PIC_colPicST                            1
    #define   MSK32RF64PIC_colPicST                               0x00200000

    #define     BA_RF64PIC_AC0Offset                           0x0002
    #define     B16RF64PIC_AC0Offset                           0x0002
    #define   LSb32RF64PIC_AC0Offset                              22
    #define   LSb16RF64PIC_AC0Offset                              6
    #define       bRF64PIC_AC0Offset                           5
    #define   MSK32RF64PIC_AC0Offset                              0x07C00000

    #define     BA_RF64PIC_BetaOffset                          0x0003
    #define     B16RF64PIC_BetaOffset                          0x0002
    #define   LSb32RF64PIC_BetaOffset                             27
    #define   LSb16RF64PIC_BetaOffset                             11
    #define       bRF64PIC_BetaOffset                          5
    #define   MSK32RF64PIC_BetaOffset                             0xF8000000
    ///////////////////////////////////////////////////////////

    #define     BA_RF64PIC_dqAcLimit                           0x0004
    #define     B16RF64PIC_dqAcLimit                           0x0004
    #define   LSb32RF64PIC_dqAcLimit                              0
    #define   LSb16RF64PIC_dqAcLimit                              0
    #define       bRF64PIC_dqAcLimit                           16
    #define   MSK32RF64PIC_dqAcLimit                              0x0000FFFF

    #define     BA_RF64PIC_dqDcLimit                           0x0006
    #define     B16RF64PIC_dqDcLimit                           0x0006
    #define   LSb32RF64PIC_dqDcLimit                              16
    #define   LSb16RF64PIC_dqDcLimit                              0
    #define       bRF64PIC_dqDcLimit                           14
    #define   MSK32RF64PIC_dqDcLimit                              0x3FFF0000

    #define     BA_RF64PIC_mismatch                            0x0007
    #define     B16RF64PIC_mismatch                            0x0006
    #define   LSb32RF64PIC_mismatch                               30
    #define   LSb16RF64PIC_mismatch                               14
    #define       bRF64PIC_mismatch                            2
    #define   MSK32RF64PIC_mismatch                               0xC0000000
    #define        RF64PIC_mismatch_none                                    0x0
    #define        RF64PIC_mismatch_mpeg1                                   0x1
    #define        RF64PIC_mismatch_mpeg2                                   0x2
    ///////////////////////////////////////////////////////////

    #define     BA_RF64PIC_picW                                0x0008
    #define     B16RF64PIC_picW                                0x0008
    #define   LSb32RF64PIC_picW                                   0
    #define   LSb16RF64PIC_picW                                   0
    #define       bRF64PIC_picW                                16
    #define   MSK32RF64PIC_picW                                   0x0000FFFF

    #define     BA_RF64PIC_picH                                0x000A
    #define     B16RF64PIC_picH                                0x000A
    #define   LSb32RF64PIC_picH                                   16
    #define   LSb16RF64PIC_picH                                   0
    #define       bRF64PIC_picH                                13
    #define   MSK32RF64PIC_picH                                   0x1FFF0000

    #define     BA_RF64PIC_btmFldPic                           0x000B
    #define     B16RF64PIC_btmFldPic                           0x000A
    #define   LSb32RF64PIC_btmFldPic                              29
    #define   LSb16RF64PIC_btmFldPic                              13
    #define       bRF64PIC_btmFldPic                           1
    #define   MSK32RF64PIC_btmFldPic                              0x20000000

    #define     BA_RF64PIC_hint                                0x000B
    #define     B16RF64PIC_hint                                0x000A
    #define   LSb32RF64PIC_hint                                   30
    #define   LSb16RF64PIC_hint                                   14
    #define       bRF64PIC_hint                                2
    #define   MSK32RF64PIC_hint                                   0xC0000000
    ///////////////////////////////////////////////////////////

    #define     BA_RF64PIC_shiftLumaX                          0x000C
    #define     B16RF64PIC_shiftLumaX                          0x000C
    #define   LSb32RF64PIC_shiftLumaX                             0
    #define   LSb16RF64PIC_shiftLumaX                             0
    #define       bRF64PIC_shiftLumaX                          8
    #define   MSK32RF64PIC_shiftLumaX                             0x000000FF

    #define     BA_RF64PIC_shiftLumaY                          0x000D
    #define     B16RF64PIC_shiftLumaY                          0x000C
    #define   LSb32RF64PIC_shiftLumaY                             8
    #define   LSb16RF64PIC_shiftLumaY                             8
    #define       bRF64PIC_shiftLumaY                          8
    #define   MSK32RF64PIC_shiftLumaY                             0x0000FF00

    #define     BA_RF64PIC_shiftChromaX                        0x000E
    #define     B16RF64PIC_shiftChromaX                        0x000E
    #define   LSb32RF64PIC_shiftChromaX                           16
    #define   LSb16RF64PIC_shiftChromaX                           0
    #define       bRF64PIC_shiftChromaX                        8
    #define   MSK32RF64PIC_shiftChromaX                           0x00FF0000

    #define     BA_RF64PIC_shiftChromaY                        0x000F
    #define     B16RF64PIC_shiftChromaY                        0x000E
    #define   LSb32RF64PIC_shiftChromaY                           24
    #define   LSb16RF64PIC_shiftChromaY                           8
    #define       bRF64PIC_shiftChromaY                        8
    #define   MSK32RF64PIC_shiftChromaY                           0xFF000000
    ///////////////////////////////////////////////////////////

    #define     BA_RF64PIC_fracTapDiv2Y                        0x0010
    #define     B16RF64PIC_fracTapDiv2Y                        0x0010
    #define   LSb32RF64PIC_fracTapDiv2Y                           0
    #define   LSb16RF64PIC_fracTapDiv2Y                           0
    #define       bRF64PIC_fracTapDiv2Y                        4
    #define   MSK32RF64PIC_fracTapDiv2Y                           0x0000000F

    #define     BA_RF64PIC_fracTapDiv2C                        0x0010
    #define     B16RF64PIC_fracTapDiv2C                        0x0010
    #define   LSb32RF64PIC_fracTapDiv2C                           4
    #define   LSb16RF64PIC_fracTapDiv2C                           4
    #define       bRF64PIC_fracTapDiv2C                        4
    #define   MSK32RF64PIC_fracTapDiv2C                           0x000000F0

    #define     BA_RF64PIC_IPCM_QPU                            0x0011
    #define     B16RF64PIC_IPCM_QPU                            0x0010
    #define   LSb32RF64PIC_IPCM_QPU                               8
    #define   LSb16RF64PIC_IPCM_QPU                               8
    #define       bRF64PIC_IPCM_QPU                            6
    #define   MSK32RF64PIC_IPCM_QPU                               0x00003F00

    #define     BA_RF64PIC_IPCM_QPV                            0x0011
    #define     B16RF64PIC_IPCM_QPV                            0x0010
    #define   LSb32RF64PIC_IPCM_QPV                               14
    #define   LSb16RF64PIC_IPCM_QPV                               14
    #define       bRF64PIC_IPCM_QPV                            6
    #define   MSK32RF64PIC_IPCM_QPV                               0x000FC000

    #define     BA_RF64PIC_RSVD12                              0x0012
    #define     B16RF64PIC_RSVD12                              0x0012
    #define   LSb32RF64PIC_RSVD12                                 20
    #define   LSb16RF64PIC_RSVD12                                 4
    #define       bRF64PIC_RSVD12                              12
    #define   MSK32RF64PIC_RSVD12                                 0xFFF00000
    ///////////////////////////////////////////////////////////

    #define     BA_RF64PIC_PQUANT                              0x0014
    #define     B16RF64PIC_PQUANT                              0x0014
    #define   LSb32RF64PIC_PQUANT                                 0
    #define   LSb16RF64PIC_PQUANT                                 0
    #define       bRF64PIC_PQUANT                              5
    #define   MSK32RF64PIC_PQUANT                                 0x0000001F

    #define     BA_RF64PIC_FRFD                                0x0014
    #define     B16RF64PIC_FRFD                                0x0014
    #define   LSb32RF64PIC_FRFD                                   5
    #define   LSb16RF64PIC_FRFD                                   5
    #define       bRF64PIC_FRFD                                2
    #define   MSK32RF64PIC_FRFD                                   0x00000060

    #define     BA_RF64PIC_BRFD                                0x0014
    #define     B16RF64PIC_BRFD                                0x0014
    #define   LSb32RF64PIC_BRFD                                   7
    #define   LSb16RF64PIC_BRFD                                   7
    #define       bRF64PIC_BRFD                                2
    #define   MSK32RF64PIC_BRFD                                   0x00000180

    #define     BA_RF64PIC_secondFld                           0x0015
    #define     B16RF64PIC_secondFld                           0x0014
    #define   LSb32RF64PIC_secondFld                              9
    #define   LSb16RF64PIC_secondFld                              9
    #define       bRF64PIC_secondFld                           1
    #define   MSK32RF64PIC_secondFld                              0x00000200

    #define     BA_RF64PIC_mvRange                             0x0015
    #define     B16RF64PIC_mvRange                             0x0014
    #define   LSb32RF64PIC_mvRange                                10
    #define   LSb16RF64PIC_mvRange                                10
    #define       bRF64PIC_mvRange                             2
    #define   MSK32RF64PIC_mvRange                                0x00000C00

    #define     BA_RF64PIC_hybridMvThres                       0x0015
    #define     B16RF64PIC_hybridMvThres                       0x0014
    #define   LSb32RF64PIC_hybridMvThres                          12
    #define   LSb16RF64PIC_hybridMvThres                          12
    #define       bRF64PIC_hybridMvThres                       1
    #define   MSK32RF64PIC_hybridMvThres                          0x00001000

    #define     BA_RF64PIC_firstMbIntra                        0x0015
    #define     B16RF64PIC_firstMbIntra                        0x0014
    #define   LSb32RF64PIC_firstMbIntra                           13
    #define   LSb16RF64PIC_firstMbIntra                           13
    #define       bRF64PIC_firstMbIntra                        1
    #define   MSK32RF64PIC_firstMbIntra                           0x00002000

    #define     BA_RF64PIC_halfPixel                           0x0015
    #define     B16RF64PIC_halfPixel                           0x0014
    #define   LSb32RF64PIC_halfPixel                              14
    #define   LSb16RF64PIC_halfPixel                              14
    #define       bRF64PIC_halfPixel                           1
    #define   MSK32RF64PIC_halfPixel                              0x00004000

    #define     BA_RF64PIC_forwRefInterlace                    0x0015
    #define     B16RF64PIC_forwRefInterlace                    0x0014
    #define   LSb32RF64PIC_forwRefInterlace                       15
    #define   LSb16RF64PIC_forwRefInterlace                       15
    #define       bRF64PIC_forwRefInterlace                    1
    #define   MSK32RF64PIC_forwRefInterlace                       0x00008000

    #define     BA_RF64PIC_backRefInterlace                    0x0016
    #define     B16RF64PIC_backRefInterlace                    0x0016
    #define   LSb32RF64PIC_backRefInterlace                       16
    #define   LSb16RF64PIC_backRefInterlace                       0
    #define       bRF64PIC_backRefInterlace                    1
    #define   MSK32RF64PIC_backRefInterlace                       0x00010000

    #define     BA_RF64PIC_FrmTransACSet                       0x0016
    #define     B16RF64PIC_FrmTransACSet                       0x0016
    #define   LSb32RF64PIC_FrmTransACSet                          17
    #define   LSb16RF64PIC_FrmTransACSet                          1
    #define       bRF64PIC_FrmTransACSet                       2
    #define   MSK32RF64PIC_FrmTransACSet                          0x00060000

    #define     BA_RF64PIC_FrmTransACSet2                      0x0016
    #define     B16RF64PIC_FrmTransACSet2                      0x0016
    #define   LSb32RF64PIC_FrmTransACSet2                         19
    #define   LSb16RF64PIC_FrmTransACSet2                         3
    #define       bRF64PIC_FrmTransACSet2                      2
    #define   MSK32RF64PIC_FrmTransACSet2                         0x00180000

    #define     BA_RF64PIC_PQIndexGT8                          0x0016
    #define     B16RF64PIC_PQIndexGT8                          0x0016
    #define   LSb32RF64PIC_PQIndexGT8                             21
    #define   LSb16RF64PIC_PQIndexGT8                             5
    #define       bRF64PIC_PQIndexGT8                          1
    #define   MSK32RF64PIC_PQIndexGT8                             0x00200000

    #define     BA_RF64PIC_EscapeTBL                           0x0016
    #define     B16RF64PIC_EscapeTBL                           0x0016
    #define   LSb32RF64PIC_EscapeTBL                              22
    #define   LSb16RF64PIC_EscapeTBL                              6
    #define       bRF64PIC_EscapeTBL                           1
    #define   MSK32RF64PIC_EscapeTBL                              0x00400000

    #define     BA_RF64PIC_format1                             0x0016
    #define     B16RF64PIC_format1                             0x0016
    #define   LSb32RF64PIC_format1                                23
    #define   LSb16RF64PIC_format1                                7
    #define       bRF64PIC_format1                             4
    #define   MSK32RF64PIC_format1                                0x07800000
    #define        RF64PIC_format1_RV9                                      0x0
    #define        RF64PIC_format1_RV8                                      0x1
    #define        RF64PIC_format1_vp8                                      0x2
    #define        RF64PIC_format1_jpeg                                     0x3

    #define     BA_RF64PIC_noReorder                           0x0017
    #define     B16RF64PIC_noReorder                           0x0016
    #define   LSb32RF64PIC_noReorder                              27
    #define   LSb16RF64PIC_noReorder                              11
    #define       bRF64PIC_noReorder                           1
    #define   MSK32RF64PIC_noReorder                              0x08000000

    #define     BA_RF64PIC_iplusModeOn                         0x0017
    #define     B16RF64PIC_iplusModeOn                         0x0016
    #define   LSb32RF64PIC_iplusModeOn                            28
    #define   LSb16RF64PIC_iplusModeOn                            12
    #define       bRF64PIC_iplusModeOn                         1
    #define   MSK32RF64PIC_iplusModeOn                            0x10000000

    #define     BA_RF64PIC_RSVD3                               0x0017
    #define     B16RF64PIC_RSVD3                               0x0016
    #define   LSb32RF64PIC_RSVD3                                  29
    #define   LSb16RF64PIC_RSVD3                                  13
    #define       bRF64PIC_RSVD3                               3
    #define   MSK32RF64PIC_RSVD3                                  0xE0000000
    ///////////////////////////////////////////////////////////
    #define     RA_RF64PIC_RSVD                                0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_RF64PIC_rIDX2BID                            0x0040
    ///////////////////////////////////////////////////////////

    typedef struct SIE_RF64PIC {
    ///////////////////////////////////////////////////////////
    #define   GET32RF64PIC_format(r32)                         _BFGET_(r32, 2, 0)
    #define   SET32RF64PIC_format(r32,v)                       _BFSET_(r32, 2, 0,v)
    #define   GET16RF64PIC_format(r16)                         _BFGET_(r16, 2, 0)
    #define   SET16RF64PIC_format(r16,v)                       _BFSET_(r16, 2, 0,v)

    #define   GET32RF64PIC_cabac(r32)                          _BFGET_(r32, 3, 3)
    #define   SET32RF64PIC_cabac(r32,v)                        _BFSET_(r32, 3, 3,v)
    #define   GET16RF64PIC_cabac(r16)                          _BFGET_(r16, 3, 3)
    #define   SET16RF64PIC_cabac(r16,v)                        _BFSET_(r16, 3, 3,v)

    #define   GET32RF64PIC_picType(r32)                        _BFGET_(r32, 5, 4)
    #define   SET32RF64PIC_picType(r32,v)                      _BFSET_(r32, 5, 4,v)
    #define   GET16RF64PIC_picType(r16)                        _BFGET_(r16, 5, 4)
    #define   SET16RF64PIC_picType(r16,v)                      _BFSET_(r16, 5, 4,v)

    #define   GET32RF64PIC_maxL0(r32)                          _BFGET_(r32,10, 6)
    #define   SET32RF64PIC_maxL0(r32,v)                        _BFSET_(r32,10, 6,v)
    #define   GET16RF64PIC_maxL0(r16)                          _BFGET_(r16,10, 6)
    #define   SET16RF64PIC_maxL0(r16,v)                        _BFSET_(r16,10, 6,v)

    #define   GET32RF64PIC_maxL1(r32)                          _BFGET_(r32,15,11)
    #define   SET32RF64PIC_maxL1(r32,v)                        _BFSET_(r32,15,11,v)
    #define   GET16RF64PIC_maxL1(r16)                          _BFGET_(r16,15,11)
    #define   SET16RF64PIC_maxL1(r16,v)                        _BFSET_(r16,15,11,v)

    #define   GET32RF64PIC_MbaffPic(r32)                       _BFGET_(r32,16,16)
    #define   SET32RF64PIC_MbaffPic(r32,v)                     _BFSET_(r32,16,16,v)
    #define   GET16RF64PIC_MbaffPic(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16RF64PIC_MbaffPic(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32RF64PIC_fieldPic(r32)                       _BFGET_(r32,17,17)
    #define   SET32RF64PIC_fieldPic(r32,v)                     _BFSET_(r32,17,17,v)
    #define   GET16RF64PIC_fieldPic(r16)                       _BFGET_(r16, 1, 1)
    #define   SET16RF64PIC_fieldPic(r16,v)                     _BFSET_(r16, 1, 1,v)

    #define   GET32RF64PIC_spatialPred(r32)                    _BFGET_(r32,18,18)
    #define   SET32RF64PIC_spatialPred(r32,v)                  _BFSET_(r32,18,18,v)
    #define   GET16RF64PIC_spatialPred(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16RF64PIC_spatialPred(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32RF64PIC_colPicMbaff(r32)                    _BFGET_(r32,19,19)
    #define   SET32RF64PIC_colPicMbaff(r32,v)                  _BFSET_(r32,19,19,v)
    #define   GET16RF64PIC_colPicMbaff(r16)                    _BFGET_(r16, 3, 3)
    #define   SET16RF64PIC_colPicMbaff(r16,v)                  _BFSET_(r16, 3, 3,v)

    #define   GET32RF64PIC_colPicField(r32)                    _BFGET_(r32,20,20)
    #define   SET32RF64PIC_colPicField(r32,v)                  _BFSET_(r32,20,20,v)
    #define   GET16RF64PIC_colPicField(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16RF64PIC_colPicField(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32RF64PIC_colPicST(r32)                       _BFGET_(r32,21,21)
    #define   SET32RF64PIC_colPicST(r32,v)                     _BFSET_(r32,21,21,v)
    #define   GET16RF64PIC_colPicST(r16)                       _BFGET_(r16, 5, 5)
    #define   SET16RF64PIC_colPicST(r16,v)                     _BFSET_(r16, 5, 5,v)

    #define   GET32RF64PIC_AC0Offset(r32)                      _BFGET_(r32,26,22)
    #define   SET32RF64PIC_AC0Offset(r32,v)                    _BFSET_(r32,26,22,v)
    #define   GET16RF64PIC_AC0Offset(r16)                      _BFGET_(r16,10, 6)
    #define   SET16RF64PIC_AC0Offset(r16,v)                    _BFSET_(r16,10, 6,v)

    #define   GET32RF64PIC_BetaOffset(r32)                     _BFGET_(r32,31,27)
    #define   SET32RF64PIC_BetaOffset(r32,v)                   _BFSET_(r32,31,27,v)
    #define   GET16RF64PIC_BetaOffset(r16)                     _BFGET_(r16,15,11)
    #define   SET16RF64PIC_BetaOffset(r16,v)                   _BFSET_(r16,15,11,v)

            UNSG32 u_format                                    :  3;
            UNSG32 u_cabac                                     :  1;
            UNSG32 u_picType                                   :  2;
            UNSG32 u_maxL0                                     :  5;
            UNSG32 u_maxL1                                     :  5;
            UNSG32 u_MbaffPic                                  :  1;
            UNSG32 u_fieldPic                                  :  1;
            UNSG32 u_spatialPred                               :  1;
            UNSG32 u_colPicMbaff                               :  1;
            UNSG32 u_colPicField                               :  1;
            UNSG32 u_colPicST                                  :  1;
            UNSG32 s_AC0Offset                                 :  5;
            UNSG32 s_BetaOffset                                :  5;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64PIC_dqAcLimit(r32)                      _BFGET_(r32,15, 0)
    #define   SET32RF64PIC_dqAcLimit(r32,v)                    _BFSET_(r32,15, 0,v)
    #define   GET16RF64PIC_dqAcLimit(r16)                      _BFGET_(r16,15, 0)
    #define   SET16RF64PIC_dqAcLimit(r16,v)                    _BFSET_(r16,15, 0,v)

    #define   GET32RF64PIC_dqDcLimit(r32)                      _BFGET_(r32,29,16)
    #define   SET32RF64PIC_dqDcLimit(r32,v)                    _BFSET_(r32,29,16,v)
    #define   GET16RF64PIC_dqDcLimit(r16)                      _BFGET_(r16,13, 0)
    #define   SET16RF64PIC_dqDcLimit(r16,v)                    _BFSET_(r16,13, 0,v)

    #define   GET32RF64PIC_mismatch(r32)                       _BFGET_(r32,31,30)
    #define   SET32RF64PIC_mismatch(r32,v)                     _BFSET_(r32,31,30,v)
    #define   GET16RF64PIC_mismatch(r16)                       _BFGET_(r16,15,14)
    #define   SET16RF64PIC_mismatch(r16,v)                     _BFSET_(r16,15,14,v)

            UNSG32 u_dqAcLimit                                 : 16;
            UNSG32 u_dqDcLimit                                 : 14;
            UNSG32 u_mismatch                                  :  2;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64PIC_picW(r32)                           _BFGET_(r32,15, 0)
    #define   SET32RF64PIC_picW(r32,v)                         _BFSET_(r32,15, 0,v)
    #define   GET16RF64PIC_picW(r16)                           _BFGET_(r16,15, 0)
    #define   SET16RF64PIC_picW(r16,v)                         _BFSET_(r16,15, 0,v)

    #define   GET32RF64PIC_picH(r32)                           _BFGET_(r32,28,16)
    #define   SET32RF64PIC_picH(r32,v)                         _BFSET_(r32,28,16,v)
    #define   GET16RF64PIC_picH(r16)                           _BFGET_(r16,12, 0)
    #define   SET16RF64PIC_picH(r16,v)                         _BFSET_(r16,12, 0,v)

    #define   GET32RF64PIC_btmFldPic(r32)                      _BFGET_(r32,29,29)
    #define   SET32RF64PIC_btmFldPic(r32,v)                    _BFSET_(r32,29,29,v)
    #define   GET16RF64PIC_btmFldPic(r16)                      _BFGET_(r16,13,13)
    #define   SET16RF64PIC_btmFldPic(r16,v)                    _BFSET_(r16,13,13,v)

    #define   GET32RF64PIC_hint(r32)                           _BFGET_(r32,31,30)
    #define   SET32RF64PIC_hint(r32,v)                         _BFSET_(r32,31,30,v)
    #define   GET16RF64PIC_hint(r16)                           _BFGET_(r16,15,14)
    #define   SET16RF64PIC_hint(r16,v)                         _BFSET_(r16,15,14,v)

            UNSG32 u_picW                                      : 16;
            UNSG32 u_picH                                      : 13;
            UNSG32 u_btmFldPic                                 :  1;
            UNSG32 u_hint                                      :  2;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64PIC_shiftLumaX(r32)                     _BFGET_(r32, 7, 0)
    #define   SET32RF64PIC_shiftLumaX(r32,v)                   _BFSET_(r32, 7, 0,v)
    #define   GET16RF64PIC_shiftLumaX(r16)                     _BFGET_(r16, 7, 0)
    #define   SET16RF64PIC_shiftLumaX(r16,v)                   _BFSET_(r16, 7, 0,v)

    #define   GET32RF64PIC_shiftLumaY(r32)                     _BFGET_(r32,15, 8)
    #define   SET32RF64PIC_shiftLumaY(r32,v)                   _BFSET_(r32,15, 8,v)
    #define   GET16RF64PIC_shiftLumaY(r16)                     _BFGET_(r16,15, 8)
    #define   SET16RF64PIC_shiftLumaY(r16,v)                   _BFSET_(r16,15, 8,v)

    #define   GET32RF64PIC_shiftChromaX(r32)                   _BFGET_(r32,23,16)
    #define   SET32RF64PIC_shiftChromaX(r32,v)                 _BFSET_(r32,23,16,v)
    #define   GET16RF64PIC_shiftChromaX(r16)                   _BFGET_(r16, 7, 0)
    #define   SET16RF64PIC_shiftChromaX(r16,v)                 _BFSET_(r16, 7, 0,v)

    #define   GET32RF64PIC_shiftChromaY(r32)                   _BFGET_(r32,31,24)
    #define   SET32RF64PIC_shiftChromaY(r32,v)                 _BFSET_(r32,31,24,v)
    #define   GET16RF64PIC_shiftChromaY(r16)                   _BFGET_(r16,15, 8)
    #define   SET16RF64PIC_shiftChromaY(r16,v)                 _BFSET_(r16,15, 8,v)

            UNSG32 u_shiftLumaX                                :  8;
            UNSG32 u_shiftLumaY                                :  8;
            UNSG32 u_shiftChromaX                              :  8;
            UNSG32 u_shiftChromaY                              :  8;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64PIC_fracTapDiv2Y(r32)                   _BFGET_(r32, 3, 0)
    #define   SET32RF64PIC_fracTapDiv2Y(r32,v)                 _BFSET_(r32, 3, 0,v)
    #define   GET16RF64PIC_fracTapDiv2Y(r16)                   _BFGET_(r16, 3, 0)
    #define   SET16RF64PIC_fracTapDiv2Y(r16,v)                 _BFSET_(r16, 3, 0,v)

    #define   GET32RF64PIC_fracTapDiv2C(r32)                   _BFGET_(r32, 7, 4)
    #define   SET32RF64PIC_fracTapDiv2C(r32,v)                 _BFSET_(r32, 7, 4,v)
    #define   GET16RF64PIC_fracTapDiv2C(r16)                   _BFGET_(r16, 7, 4)
    #define   SET16RF64PIC_fracTapDiv2C(r16,v)                 _BFSET_(r16, 7, 4,v)

    #define   GET32RF64PIC_IPCM_QPU(r32)                       _BFGET_(r32,13, 8)
    #define   SET32RF64PIC_IPCM_QPU(r32,v)                     _BFSET_(r32,13, 8,v)
    #define   GET16RF64PIC_IPCM_QPU(r16)                       _BFGET_(r16,13, 8)
    #define   SET16RF64PIC_IPCM_QPU(r16,v)                     _BFSET_(r16,13, 8,v)

    #define   GET32RF64PIC_IPCM_QPV(r32)                       _BFGET_(r32,19,14)
    #define   SET32RF64PIC_IPCM_QPV(r32,v)                     _BFSET_(r32,19,14,v)

    #define   GET32RF64PIC_RSVD12(r32)                         _BFGET_(r32,31,20)
    #define   SET32RF64PIC_RSVD12(r32,v)                       _BFSET_(r32,31,20,v)
    #define   GET16RF64PIC_RSVD12(r16)                         _BFGET_(r16,15, 4)
    #define   SET16RF64PIC_RSVD12(r16,v)                       _BFSET_(r16,15, 4,v)

            UNSG32 u_fracTapDiv2Y                              :  4;
            UNSG32 u_fracTapDiv2C                              :  4;
            UNSG32 u_IPCM_QPU                                  :  6;
            UNSG32 u_IPCM_QPV                                  :  6;
            UNSG32 u_RSVD12                                    : 12;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64PIC_PQUANT(r32)                         _BFGET_(r32, 4, 0)
    #define   SET32RF64PIC_PQUANT(r32,v)                       _BFSET_(r32, 4, 0,v)
    #define   GET16RF64PIC_PQUANT(r16)                         _BFGET_(r16, 4, 0)
    #define   SET16RF64PIC_PQUANT(r16,v)                       _BFSET_(r16, 4, 0,v)

    #define   GET32RF64PIC_FRFD(r32)                           _BFGET_(r32, 6, 5)
    #define   SET32RF64PIC_FRFD(r32,v)                         _BFSET_(r32, 6, 5,v)
    #define   GET16RF64PIC_FRFD(r16)                           _BFGET_(r16, 6, 5)
    #define   SET16RF64PIC_FRFD(r16,v)                         _BFSET_(r16, 6, 5,v)

    #define   GET32RF64PIC_BRFD(r32)                           _BFGET_(r32, 8, 7)
    #define   SET32RF64PIC_BRFD(r32,v)                         _BFSET_(r32, 8, 7,v)
    #define   GET16RF64PIC_BRFD(r16)                           _BFGET_(r16, 8, 7)
    #define   SET16RF64PIC_BRFD(r16,v)                         _BFSET_(r16, 8, 7,v)

    #define   GET32RF64PIC_secondFld(r32)                      _BFGET_(r32, 9, 9)
    #define   SET32RF64PIC_secondFld(r32,v)                    _BFSET_(r32, 9, 9,v)
    #define   GET16RF64PIC_secondFld(r16)                      _BFGET_(r16, 9, 9)
    #define   SET16RF64PIC_secondFld(r16,v)                    _BFSET_(r16, 9, 9,v)

    #define   GET32RF64PIC_mvRange(r32)                        _BFGET_(r32,11,10)
    #define   SET32RF64PIC_mvRange(r32,v)                      _BFSET_(r32,11,10,v)
    #define   GET16RF64PIC_mvRange(r16)                        _BFGET_(r16,11,10)
    #define   SET16RF64PIC_mvRange(r16,v)                      _BFSET_(r16,11,10,v)

    #define   GET32RF64PIC_hybridMvThres(r32)                  _BFGET_(r32,12,12)
    #define   SET32RF64PIC_hybridMvThres(r32,v)                _BFSET_(r32,12,12,v)
    #define   GET16RF64PIC_hybridMvThres(r16)                  _BFGET_(r16,12,12)
    #define   SET16RF64PIC_hybridMvThres(r16,v)                _BFSET_(r16,12,12,v)

    #define   GET32RF64PIC_firstMbIntra(r32)                   _BFGET_(r32,13,13)
    #define   SET32RF64PIC_firstMbIntra(r32,v)                 _BFSET_(r32,13,13,v)
    #define   GET16RF64PIC_firstMbIntra(r16)                   _BFGET_(r16,13,13)
    #define   SET16RF64PIC_firstMbIntra(r16,v)                 _BFSET_(r16,13,13,v)

    #define   GET32RF64PIC_halfPixel(r32)                      _BFGET_(r32,14,14)
    #define   SET32RF64PIC_halfPixel(r32,v)                    _BFSET_(r32,14,14,v)
    #define   GET16RF64PIC_halfPixel(r16)                      _BFGET_(r16,14,14)
    #define   SET16RF64PIC_halfPixel(r16,v)                    _BFSET_(r16,14,14,v)

    #define   GET32RF64PIC_forwRefInterlace(r32)               _BFGET_(r32,15,15)
    #define   SET32RF64PIC_forwRefInterlace(r32,v)             _BFSET_(r32,15,15,v)
    #define   GET16RF64PIC_forwRefInterlace(r16)               _BFGET_(r16,15,15)
    #define   SET16RF64PIC_forwRefInterlace(r16,v)             _BFSET_(r16,15,15,v)

    #define   GET32RF64PIC_backRefInterlace(r32)               _BFGET_(r32,16,16)
    #define   SET32RF64PIC_backRefInterlace(r32,v)             _BFSET_(r32,16,16,v)
    #define   GET16RF64PIC_backRefInterlace(r16)               _BFGET_(r16, 0, 0)
    #define   SET16RF64PIC_backRefInterlace(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32RF64PIC_FrmTransACSet(r32)                  _BFGET_(r32,18,17)
    #define   SET32RF64PIC_FrmTransACSet(r32,v)                _BFSET_(r32,18,17,v)
    #define   GET16RF64PIC_FrmTransACSet(r16)                  _BFGET_(r16, 2, 1)
    #define   SET16RF64PIC_FrmTransACSet(r16,v)                _BFSET_(r16, 2, 1,v)

    #define   GET32RF64PIC_FrmTransACSet2(r32)                 _BFGET_(r32,20,19)
    #define   SET32RF64PIC_FrmTransACSet2(r32,v)               _BFSET_(r32,20,19,v)
    #define   GET16RF64PIC_FrmTransACSet2(r16)                 _BFGET_(r16, 4, 3)
    #define   SET16RF64PIC_FrmTransACSet2(r16,v)               _BFSET_(r16, 4, 3,v)

    #define   GET32RF64PIC_PQIndexGT8(r32)                     _BFGET_(r32,21,21)
    #define   SET32RF64PIC_PQIndexGT8(r32,v)                   _BFSET_(r32,21,21,v)
    #define   GET16RF64PIC_PQIndexGT8(r16)                     _BFGET_(r16, 5, 5)
    #define   SET16RF64PIC_PQIndexGT8(r16,v)                   _BFSET_(r16, 5, 5,v)

    #define   GET32RF64PIC_EscapeTBL(r32)                      _BFGET_(r32,22,22)
    #define   SET32RF64PIC_EscapeTBL(r32,v)                    _BFSET_(r32,22,22,v)
    #define   GET16RF64PIC_EscapeTBL(r16)                      _BFGET_(r16, 6, 6)
    #define   SET16RF64PIC_EscapeTBL(r16,v)                    _BFSET_(r16, 6, 6,v)

    #define   GET32RF64PIC_format1(r32)                        _BFGET_(r32,26,23)
    #define   SET32RF64PIC_format1(r32,v)                      _BFSET_(r32,26,23,v)
    #define   GET16RF64PIC_format1(r16)                        _BFGET_(r16,10, 7)
    #define   SET16RF64PIC_format1(r16,v)                      _BFSET_(r16,10, 7,v)

    #define   GET32RF64PIC_noReorder(r32)                      _BFGET_(r32,27,27)
    #define   SET32RF64PIC_noReorder(r32,v)                    _BFSET_(r32,27,27,v)
    #define   GET16RF64PIC_noReorder(r16)                      _BFGET_(r16,11,11)
    #define   SET16RF64PIC_noReorder(r16,v)                    _BFSET_(r16,11,11,v)

    #define   GET32RF64PIC_iplusModeOn(r32)                    _BFGET_(r32,28,28)
    #define   SET32RF64PIC_iplusModeOn(r32,v)                  _BFSET_(r32,28,28,v)
    #define   GET16RF64PIC_iplusModeOn(r16)                    _BFGET_(r16,12,12)
    #define   SET16RF64PIC_iplusModeOn(r16,v)                  _BFSET_(r16,12,12,v)

    #define   GET32RF64PIC_RSVD3(r32)                          _BFGET_(r32,31,29)
    #define   SET32RF64PIC_RSVD3(r32,v)                        _BFSET_(r32,31,29,v)
    #define   GET16RF64PIC_RSVD3(r16)                          _BFGET_(r16,15,13)
    #define   SET16RF64PIC_RSVD3(r16,v)                        _BFSET_(r16,15,13,v)

            UNSG32 u_PQUANT                                    :  5;
            UNSG32 u_FRFD                                      :  2;
            UNSG32 u_BRFD                                      :  2;
            UNSG32 u_secondFld                                 :  1;
            UNSG32 u_mvRange                                   :  2;
            UNSG32 u_hybridMvThres                             :  1;
            UNSG32 u_firstMbIntra                              :  1;
            UNSG32 u_halfPixel                                 :  1;
            UNSG32 u_forwRefInterlace                          :  1;
            UNSG32 u_backRefInterlace                          :  1;
            UNSG32 u_FrmTransACSet                             :  2;
            UNSG32 u_FrmTransACSet2                            :  2;
            UNSG32 u_PQIndexGT8                                :  1;
            UNSG32 u_EscapeTBL                                 :  1;
            UNSG32 u_format1                                   :  4;
            UNSG32 u_noReorder                                 :  1;
            UNSG32 u_iplusModeOn                               :  1;
            UNSG32 u_RSVD3                                     :  3;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[5];
    ///////////////////////////////////////////////////////////
              SIE_IDX2BID                                      ie_rIDX2BID;
    ///////////////////////////////////////////////////////////
    } SIE_RF64PIC;

    ///////////////////////////////////////////////////////////
     SIGN32 RF64PIC_drvrd(SIE_RF64PIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 RF64PIC_drvwr(SIE_RF64PIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void RF64PIC_reset(SIE_RF64PIC *p);
     SIGN32 RF64PIC_cmp  (SIE_RF64PIC *p, SIE_RF64PIC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define RF64PIC_check(p,pie,pfx,hLOG) RF64PIC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define RF64PIC_print(p,    pfx,hLOG) RF64PIC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: RF64PIC
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE RF64MB                  biu              (4,4)
///     ###
///     * RF64 macroblock-level information for ALU64 extensions; padded to 64b
///     * [0:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               ###
///               * [0:15] casted from MBPROP[0:15] in decHal_mbLvl.sxw.txt
///               ###
///               %unsigned 3  BANK                      
///                                    ###
///                                    * Bank[0] indicates whether current MB is even or odd in an MB pair.
///                                    ###
///               %unsigned 1  Inter                     
///                                    ###
///                                    * Intra (0) or inter (1) macroblock, for DQmatrix selection in dQuant only
///                                    ###
///               %unsigned 1  lastMbRow                 
///                                    ###
///                                    * Current MB row is the last in slice; for VC-1 FOP
///                                    ###
///               %unsigned 1  lastMbRowPic              
///                                    ###
///                                    * Current MB row is the last in picture; for VC-1 FOP
///                                    ###
///               %unsigned 1  RSVD                      
///                                    ###
///                                    * reserved for bitfield alignment. Removed RF64MB.Mbaff.
///                                    ###
///               %unsigned 1  FLD                       
///                                    ###
///                                    * - if current MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1.
///                                    ###
///               %unsigned 1  FLDNeighborA              
///                                    ###
///                                    * - if left MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1.
///                                    ###
///               %unsigned 1  FLDNeighborB              
///                                    ###
///                                    * - if upper MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1.
///                                    ###
///               %unsigned 1  FLDNeighborC              
///                                    ###
///                                    * - if upper-right MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1.
///                                    ###
///               %unsigned 1  FLDNeighborD              
///                                    ###
///                                    * - if upper-left MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1.
///                                    ###
///               %unsigned 1  NeighborA                 
///                                    ###
///                                    * From stream-parser to syntax-processor:
///                                    * - if left MB is available
///                                    * From vScope to PCube:
///                                    * - if left MB is available as intra predictor
///                                    ###
///               %unsigned 1  NeighborB                 
///                                    ###
///                                    * From stream-parser to syntax-processor:
///                                    * - if upper MB is available
///                                    * From vScope to PCube:
///                                    * - if upper MB is available as intra predictor
///                                    ###
///               %unsigned 1  NeighborC                 
///                                    ###
///                                    * From stream-parser to syntax-processor:
///                                    * - if upper-right MB is available
///                                    * From vScope to PCube:
///                                    * - if upper-right MB is available as intra predictor
///                                    ###
///               %unsigned 1  NeighborD                 
///                                    ###
///                                    * From stream-parser to syntax-processor:
///                                    * - if upper-left MB is available
///                                    * From vScope to PCube:
///                                    * - if upper-left MB is available as intra predictor
///                                    ###
///               %unsigned 8  FopAddr2                  
///                                    ###
///                                    * VC-1: base addr 2 for FOP output, 16-byte based
///                                    ###
///               %unsigned 8  FopAddr3                  
///                                    ###
///                                    * VC-1: base addr 3 for FOP output, 16-byte based
///                                    * [32:63]
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 8  FopAddr                   
///                                    ###
///                                    * H.264: FOP output addr
///                                    * VC-1: base addr 0 for FOP output, 16-byte based
///                                    ###
///               %unsigned 8  FopAddr1                  
///                                    ###
///                                    * VC-1: base addr 1 for FOP output, 16-byte based
///                                    ###
///               %unsigned 8  MbX                       
///                                    ###
///                                    * Current MB index in X direction;
///                                    * from 0 up to ((picW+15)>>4) -1
///                                    ###
///               %unsigned 8  MbY                       
///                                    ###
///                                    * Current MB index in Y direction;
///                                    * from 0 up to ((picH+15)>>4) -1
///                                    * End of RF64MB
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_RF64MB
#define h_RF64MB (){}

    #define     BA_RF64MB_BANK                                 0x0000
    #define     B16RF64MB_BANK                                 0x0000
    #define   LSb32RF64MB_BANK                                    0
    #define   LSb16RF64MB_BANK                                    0
    #define       bRF64MB_BANK                                 3
    #define   MSK32RF64MB_BANK                                    0x00000007

    #define     BA_RF64MB_Inter                                0x0000
    #define     B16RF64MB_Inter                                0x0000
    #define   LSb32RF64MB_Inter                                   3
    #define   LSb16RF64MB_Inter                                   3
    #define       bRF64MB_Inter                                1
    #define   MSK32RF64MB_Inter                                   0x00000008

    #define     BA_RF64MB_lastMbRow                            0x0000
    #define     B16RF64MB_lastMbRow                            0x0000
    #define   LSb32RF64MB_lastMbRow                               4
    #define   LSb16RF64MB_lastMbRow                               4
    #define       bRF64MB_lastMbRow                            1
    #define   MSK32RF64MB_lastMbRow                               0x00000010

    #define     BA_RF64MB_lastMbRowPic                         0x0000
    #define     B16RF64MB_lastMbRowPic                         0x0000
    #define   LSb32RF64MB_lastMbRowPic                            5
    #define   LSb16RF64MB_lastMbRowPic                            5
    #define       bRF64MB_lastMbRowPic                         1
    #define   MSK32RF64MB_lastMbRowPic                            0x00000020

    #define     BA_RF64MB_RSVD                                 0x0000
    #define     B16RF64MB_RSVD                                 0x0000
    #define   LSb32RF64MB_RSVD                                    6
    #define   LSb16RF64MB_RSVD                                    6
    #define       bRF64MB_RSVD                                 1
    #define   MSK32RF64MB_RSVD                                    0x00000040

    #define     BA_RF64MB_FLD                                  0x0000
    #define     B16RF64MB_FLD                                  0x0000
    #define   LSb32RF64MB_FLD                                     7
    #define   LSb16RF64MB_FLD                                     7
    #define       bRF64MB_FLD                                  1
    #define   MSK32RF64MB_FLD                                     0x00000080

    #define     BA_RF64MB_FLDNeighborA                         0x0001
    #define     B16RF64MB_FLDNeighborA                         0x0000
    #define   LSb32RF64MB_FLDNeighborA                            8
    #define   LSb16RF64MB_FLDNeighborA                            8
    #define       bRF64MB_FLDNeighborA                         1
    #define   MSK32RF64MB_FLDNeighborA                            0x00000100

    #define     BA_RF64MB_FLDNeighborB                         0x0001
    #define     B16RF64MB_FLDNeighborB                         0x0000
    #define   LSb32RF64MB_FLDNeighborB                            9
    #define   LSb16RF64MB_FLDNeighborB                            9
    #define       bRF64MB_FLDNeighborB                         1
    #define   MSK32RF64MB_FLDNeighborB                            0x00000200

    #define     BA_RF64MB_FLDNeighborC                         0x0001
    #define     B16RF64MB_FLDNeighborC                         0x0000
    #define   LSb32RF64MB_FLDNeighborC                            10
    #define   LSb16RF64MB_FLDNeighborC                            10
    #define       bRF64MB_FLDNeighborC                         1
    #define   MSK32RF64MB_FLDNeighborC                            0x00000400

    #define     BA_RF64MB_FLDNeighborD                         0x0001
    #define     B16RF64MB_FLDNeighborD                         0x0000
    #define   LSb32RF64MB_FLDNeighborD                            11
    #define   LSb16RF64MB_FLDNeighborD                            11
    #define       bRF64MB_FLDNeighborD                         1
    #define   MSK32RF64MB_FLDNeighborD                            0x00000800

    #define     BA_RF64MB_NeighborA                            0x0001
    #define     B16RF64MB_NeighborA                            0x0000
    #define   LSb32RF64MB_NeighborA                               12
    #define   LSb16RF64MB_NeighborA                               12
    #define       bRF64MB_NeighborA                            1
    #define   MSK32RF64MB_NeighborA                               0x00001000

    #define     BA_RF64MB_NeighborB                            0x0001
    #define     B16RF64MB_NeighborB                            0x0000
    #define   LSb32RF64MB_NeighborB                               13
    #define   LSb16RF64MB_NeighborB                               13
    #define       bRF64MB_NeighborB                            1
    #define   MSK32RF64MB_NeighborB                               0x00002000

    #define     BA_RF64MB_NeighborC                            0x0001
    #define     B16RF64MB_NeighborC                            0x0000
    #define   LSb32RF64MB_NeighborC                               14
    #define   LSb16RF64MB_NeighborC                               14
    #define       bRF64MB_NeighborC                            1
    #define   MSK32RF64MB_NeighborC                               0x00004000

    #define     BA_RF64MB_NeighborD                            0x0001
    #define     B16RF64MB_NeighborD                            0x0000
    #define   LSb32RF64MB_NeighborD                               15
    #define   LSb16RF64MB_NeighborD                               15
    #define       bRF64MB_NeighborD                            1
    #define   MSK32RF64MB_NeighborD                               0x00008000

    #define     BA_RF64MB_FopAddr2                             0x0002
    #define     B16RF64MB_FopAddr2                             0x0002
    #define   LSb32RF64MB_FopAddr2                                16
    #define   LSb16RF64MB_FopAddr2                                0
    #define       bRF64MB_FopAddr2                             8
    #define   MSK32RF64MB_FopAddr2                                0x00FF0000

    #define     BA_RF64MB_FopAddr3                             0x0003
    #define     B16RF64MB_FopAddr3                             0x0002
    #define   LSb32RF64MB_FopAddr3                                24
    #define   LSb16RF64MB_FopAddr3                                8
    #define       bRF64MB_FopAddr3                             8
    #define   MSK32RF64MB_FopAddr3                                0xFF000000
    ///////////////////////////////////////////////////////////

    #define     BA_RF64MB_FopAddr                              0x0004
    #define     B16RF64MB_FopAddr                              0x0004
    #define   LSb32RF64MB_FopAddr                                 0
    #define   LSb16RF64MB_FopAddr                                 0
    #define       bRF64MB_FopAddr                              8
    #define   MSK32RF64MB_FopAddr                                 0x000000FF

    #define     BA_RF64MB_FopAddr1                             0x0005
    #define     B16RF64MB_FopAddr1                             0x0004
    #define   LSb32RF64MB_FopAddr1                                8
    #define   LSb16RF64MB_FopAddr1                                8
    #define       bRF64MB_FopAddr1                             8
    #define   MSK32RF64MB_FopAddr1                                0x0000FF00

    #define     BA_RF64MB_MbX                                  0x0006
    #define     B16RF64MB_MbX                                  0x0006
    #define   LSb32RF64MB_MbX                                     16
    #define   LSb16RF64MB_MbX                                     0
    #define       bRF64MB_MbX                                  8
    #define   MSK32RF64MB_MbX                                     0x00FF0000

    #define     BA_RF64MB_MbY                                  0x0007
    #define     B16RF64MB_MbY                                  0x0006
    #define   LSb32RF64MB_MbY                                     24
    #define   LSb16RF64MB_MbY                                     8
    #define       bRF64MB_MbY                                  8
    #define   MSK32RF64MB_MbY                                     0xFF000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_RF64MB {
    ///////////////////////////////////////////////////////////
    #define   GET32RF64MB_BANK(r32)                            _BFGET_(r32, 2, 0)
    #define   SET32RF64MB_BANK(r32,v)                          _BFSET_(r32, 2, 0,v)
    #define   GET16RF64MB_BANK(r16)                            _BFGET_(r16, 2, 0)
    #define   SET16RF64MB_BANK(r16,v)                          _BFSET_(r16, 2, 0,v)

    #define   GET32RF64MB_Inter(r32)                           _BFGET_(r32, 3, 3)
    #define   SET32RF64MB_Inter(r32,v)                         _BFSET_(r32, 3, 3,v)
    #define   GET16RF64MB_Inter(r16)                           _BFGET_(r16, 3, 3)
    #define   SET16RF64MB_Inter(r16,v)                         _BFSET_(r16, 3, 3,v)

    #define   GET32RF64MB_lastMbRow(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32RF64MB_lastMbRow(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16RF64MB_lastMbRow(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16RF64MB_lastMbRow(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32RF64MB_lastMbRowPic(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32RF64MB_lastMbRowPic(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16RF64MB_lastMbRowPic(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16RF64MB_lastMbRowPic(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32RF64MB_RSVD(r32)                            _BFGET_(r32, 6, 6)
    #define   SET32RF64MB_RSVD(r32,v)                          _BFSET_(r32, 6, 6,v)
    #define   GET16RF64MB_RSVD(r16)                            _BFGET_(r16, 6, 6)
    #define   SET16RF64MB_RSVD(r16,v)                          _BFSET_(r16, 6, 6,v)

    #define   GET32RF64MB_FLD(r32)                             _BFGET_(r32, 7, 7)
    #define   SET32RF64MB_FLD(r32,v)                           _BFSET_(r32, 7, 7,v)
    #define   GET16RF64MB_FLD(r16)                             _BFGET_(r16, 7, 7)
    #define   SET16RF64MB_FLD(r16,v)                           _BFSET_(r16, 7, 7,v)

    #define   GET32RF64MB_FLDNeighborA(r32)                    _BFGET_(r32, 8, 8)
    #define   SET32RF64MB_FLDNeighborA(r32,v)                  _BFSET_(r32, 8, 8,v)
    #define   GET16RF64MB_FLDNeighborA(r16)                    _BFGET_(r16, 8, 8)
    #define   SET16RF64MB_FLDNeighborA(r16,v)                  _BFSET_(r16, 8, 8,v)

    #define   GET32RF64MB_FLDNeighborB(r32)                    _BFGET_(r32, 9, 9)
    #define   SET32RF64MB_FLDNeighborB(r32,v)                  _BFSET_(r32, 9, 9,v)
    #define   GET16RF64MB_FLDNeighborB(r16)                    _BFGET_(r16, 9, 9)
    #define   SET16RF64MB_FLDNeighborB(r16,v)                  _BFSET_(r16, 9, 9,v)

    #define   GET32RF64MB_FLDNeighborC(r32)                    _BFGET_(r32,10,10)
    #define   SET32RF64MB_FLDNeighborC(r32,v)                  _BFSET_(r32,10,10,v)
    #define   GET16RF64MB_FLDNeighborC(r16)                    _BFGET_(r16,10,10)
    #define   SET16RF64MB_FLDNeighborC(r16,v)                  _BFSET_(r16,10,10,v)

    #define   GET32RF64MB_FLDNeighborD(r32)                    _BFGET_(r32,11,11)
    #define   SET32RF64MB_FLDNeighborD(r32,v)                  _BFSET_(r32,11,11,v)
    #define   GET16RF64MB_FLDNeighborD(r16)                    _BFGET_(r16,11,11)
    #define   SET16RF64MB_FLDNeighborD(r16,v)                  _BFSET_(r16,11,11,v)

    #define   GET32RF64MB_NeighborA(r32)                       _BFGET_(r32,12,12)
    #define   SET32RF64MB_NeighborA(r32,v)                     _BFSET_(r32,12,12,v)
    #define   GET16RF64MB_NeighborA(r16)                       _BFGET_(r16,12,12)
    #define   SET16RF64MB_NeighborA(r16,v)                     _BFSET_(r16,12,12,v)

    #define   GET32RF64MB_NeighborB(r32)                       _BFGET_(r32,13,13)
    #define   SET32RF64MB_NeighborB(r32,v)                     _BFSET_(r32,13,13,v)
    #define   GET16RF64MB_NeighborB(r16)                       _BFGET_(r16,13,13)
    #define   SET16RF64MB_NeighborB(r16,v)                     _BFSET_(r16,13,13,v)

    #define   GET32RF64MB_NeighborC(r32)                       _BFGET_(r32,14,14)
    #define   SET32RF64MB_NeighborC(r32,v)                     _BFSET_(r32,14,14,v)
    #define   GET16RF64MB_NeighborC(r16)                       _BFGET_(r16,14,14)
    #define   SET16RF64MB_NeighborC(r16,v)                     _BFSET_(r16,14,14,v)

    #define   GET32RF64MB_NeighborD(r32)                       _BFGET_(r32,15,15)
    #define   SET32RF64MB_NeighborD(r32,v)                     _BFSET_(r32,15,15,v)
    #define   GET16RF64MB_NeighborD(r16)                       _BFGET_(r16,15,15)
    #define   SET16RF64MB_NeighborD(r16,v)                     _BFSET_(r16,15,15,v)

    #define   GET32RF64MB_FopAddr2(r32)                        _BFGET_(r32,23,16)
    #define   SET32RF64MB_FopAddr2(r32,v)                      _BFSET_(r32,23,16,v)
    #define   GET16RF64MB_FopAddr2(r16)                        _BFGET_(r16, 7, 0)
    #define   SET16RF64MB_FopAddr2(r16,v)                      _BFSET_(r16, 7, 0,v)

    #define   GET32RF64MB_FopAddr3(r32)                        _BFGET_(r32,31,24)
    #define   SET32RF64MB_FopAddr3(r32,v)                      _BFSET_(r32,31,24,v)
    #define   GET16RF64MB_FopAddr3(r16)                        _BFGET_(r16,15, 8)
    #define   SET16RF64MB_FopAddr3(r16,v)                      _BFSET_(r16,15, 8,v)

            UNSG32 u_BANK                                      :  3;
            UNSG32 u_Inter                                     :  1;
            UNSG32 u_lastMbRow                                 :  1;
            UNSG32 u_lastMbRowPic                              :  1;
            UNSG32 u_RSVD                                      :  1;
            UNSG32 u_FLD                                       :  1;
            UNSG32 u_FLDNeighborA                              :  1;
            UNSG32 u_FLDNeighborB                              :  1;
            UNSG32 u_FLDNeighborC                              :  1;
            UNSG32 u_FLDNeighborD                              :  1;
            UNSG32 u_NeighborA                                 :  1;
            UNSG32 u_NeighborB                                 :  1;
            UNSG32 u_NeighborC                                 :  1;
            UNSG32 u_NeighborD                                 :  1;
            UNSG32 u_FopAddr2                                  :  8;
            UNSG32 u_FopAddr3                                  :  8;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64MB_FopAddr(r32)                         _BFGET_(r32, 7, 0)
    #define   SET32RF64MB_FopAddr(r32,v)                       _BFSET_(r32, 7, 0,v)
    #define   GET16RF64MB_FopAddr(r16)                         _BFGET_(r16, 7, 0)
    #define   SET16RF64MB_FopAddr(r16,v)                       _BFSET_(r16, 7, 0,v)

    #define   GET32RF64MB_FopAddr1(r32)                        _BFGET_(r32,15, 8)
    #define   SET32RF64MB_FopAddr1(r32,v)                      _BFSET_(r32,15, 8,v)
    #define   GET16RF64MB_FopAddr1(r16)                        _BFGET_(r16,15, 8)
    #define   SET16RF64MB_FopAddr1(r16,v)                      _BFSET_(r16,15, 8,v)

    #define   GET32RF64MB_MbX(r32)                             _BFGET_(r32,23,16)
    #define   SET32RF64MB_MbX(r32,v)                           _BFSET_(r32,23,16,v)
    #define   GET16RF64MB_MbX(r16)                             _BFGET_(r16, 7, 0)
    #define   SET16RF64MB_MbX(r16,v)                           _BFSET_(r16, 7, 0,v)

    #define   GET32RF64MB_MbY(r32)                             _BFGET_(r32,31,24)
    #define   SET32RF64MB_MbY(r32,v)                           _BFSET_(r32,31,24,v)
    #define   GET16RF64MB_MbY(r16)                             _BFGET_(r16,15, 8)
    #define   SET16RF64MB_MbY(r16,v)                           _BFSET_(r16,15, 8,v)

            UNSG32 u_FopAddr                                   :  8;
            UNSG32 u_FopAddr1                                  :  8;
            UNSG32 u_MbX                                       :  8;
            UNSG32 u_MbY                                       :  8;
    ///////////////////////////////////////////////////////////
    } SIE_RF64MB;

    ///////////////////////////////////////////////////////////
     SIGN32 RF64MB_drvrd(SIE_RF64MB *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 RF64MB_drvwr(SIE_RF64MB *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void RF64MB_reset(SIE_RF64MB *p);
     SIGN32 RF64MB_cmp  (SIE_RF64MB *p, SIE_RF64MB *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define RF64MB_check(p,pie,pfx,hLOG) RF64MB_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define RF64MB_print(p,    pfx,hLOG) RF64MB_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: RF64MB
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE RF64QP                  biu              (4,4)
///     ###
///     * QP for neighboring macroblocks; used by FOP only. Padded to 64b
///     * Same as {BLK,chroma,RSVD,QP,Qu,Qv} in MBPROP in decHal_mbLvl.sxw.txt
///     * Also added DC/ACstep_* for coefficient scaling for DC/AC prediction for MPEG-4/VC-1
///     * [0:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 8  DCstep_Y                  
///                                    ###
///                                    * VC-1: DCSTEP for coeff scaling in DC prediction (only 6 bits are used)
///                                    * MPEG-4: qstep luma coeff scaling in DC prediction
///                                    ###
///               %unsigned 8  ACstep_Y                  
///                                    ###
///                                    * VC-1: DCSTEP for coeff scaling in AC prediction (only 6 bits are used)
///                                    * MPEG-4: qstep luma coeff scaling in AC prediction
///                                    ###
///               %unsigned 8  DCstep_C                  
///                                    ###
///                                    * VC-1: not used
///                                    * MPEG-4: qstep chroma coeff scaling in DC prediction
///                                    ###
///               %unsigned 8  ACstep_C                  
///                                    ###
///                                    * VC-1: not used
///                                    * MPEG-4: qstep chroma coeff scaling in AC prediction
///                                    * [32:63]
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 8  RSVD8                     
///               %unsigned 8  QPY                       
///                                    ###
///                                    * H.264: QP for Luma; 0~51 inclusive
///                                    * MPEG-4: QP_AC (used to determine if coeff scaling is required for AC prediction)
///                                    ###
///               %unsigned 8  QPU                       
///                                    ###
///                                    * H.264: QP fo Cb; 0~51 inclusive
///                                    ###
///               %unsigned 8  QPV                       
///                                    ###
///                                    * H.264: QP for Cr; 0~51 inclusive
///                                    * End of RF64QP
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_RF64QP
#define h_RF64QP (){}

    #define     BA_RF64QP_DCstep_Y                             0x0000
    #define     B16RF64QP_DCstep_Y                             0x0000
    #define   LSb32RF64QP_DCstep_Y                                0
    #define   LSb16RF64QP_DCstep_Y                                0
    #define       bRF64QP_DCstep_Y                             8
    #define   MSK32RF64QP_DCstep_Y                                0x000000FF

    #define     BA_RF64QP_ACstep_Y                             0x0001
    #define     B16RF64QP_ACstep_Y                             0x0000
    #define   LSb32RF64QP_ACstep_Y                                8
    #define   LSb16RF64QP_ACstep_Y                                8
    #define       bRF64QP_ACstep_Y                             8
    #define   MSK32RF64QP_ACstep_Y                                0x0000FF00

    #define     BA_RF64QP_DCstep_C                             0x0002
    #define     B16RF64QP_DCstep_C                             0x0002
    #define   LSb32RF64QP_DCstep_C                                16
    #define   LSb16RF64QP_DCstep_C                                0
    #define       bRF64QP_DCstep_C                             8
    #define   MSK32RF64QP_DCstep_C                                0x00FF0000

    #define     BA_RF64QP_ACstep_C                             0x0003
    #define     B16RF64QP_ACstep_C                             0x0002
    #define   LSb32RF64QP_ACstep_C                                24
    #define   LSb16RF64QP_ACstep_C                                8
    #define       bRF64QP_ACstep_C                             8
    #define   MSK32RF64QP_ACstep_C                                0xFF000000
    ///////////////////////////////////////////////////////////

    #define     BA_RF64QP_RSVD8                                0x0004
    #define     B16RF64QP_RSVD8                                0x0004
    #define   LSb32RF64QP_RSVD8                                   0
    #define   LSb16RF64QP_RSVD8                                   0
    #define       bRF64QP_RSVD8                                8
    #define   MSK32RF64QP_RSVD8                                   0x000000FF

    #define     BA_RF64QP_QPY                                  0x0005
    #define     B16RF64QP_QPY                                  0x0004
    #define   LSb32RF64QP_QPY                                     8
    #define   LSb16RF64QP_QPY                                     8
    #define       bRF64QP_QPY                                  8
    #define   MSK32RF64QP_QPY                                     0x0000FF00

    #define     BA_RF64QP_QPU                                  0x0006
    #define     B16RF64QP_QPU                                  0x0006
    #define   LSb32RF64QP_QPU                                     16
    #define   LSb16RF64QP_QPU                                     0
    #define       bRF64QP_QPU                                  8
    #define   MSK32RF64QP_QPU                                     0x00FF0000

    #define     BA_RF64QP_QPV                                  0x0007
    #define     B16RF64QP_QPV                                  0x0006
    #define   LSb32RF64QP_QPV                                     24
    #define   LSb16RF64QP_QPV                                     8
    #define       bRF64QP_QPV                                  8
    #define   MSK32RF64QP_QPV                                     0xFF000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_RF64QP {
    ///////////////////////////////////////////////////////////
    #define   GET32RF64QP_DCstep_Y(r32)                        _BFGET_(r32, 7, 0)
    #define   SET32RF64QP_DCstep_Y(r32,v)                      _BFSET_(r32, 7, 0,v)
    #define   GET16RF64QP_DCstep_Y(r16)                        _BFGET_(r16, 7, 0)
    #define   SET16RF64QP_DCstep_Y(r16,v)                      _BFSET_(r16, 7, 0,v)

    #define   GET32RF64QP_ACstep_Y(r32)                        _BFGET_(r32,15, 8)
    #define   SET32RF64QP_ACstep_Y(r32,v)                      _BFSET_(r32,15, 8,v)
    #define   GET16RF64QP_ACstep_Y(r16)                        _BFGET_(r16,15, 8)
    #define   SET16RF64QP_ACstep_Y(r16,v)                      _BFSET_(r16,15, 8,v)

    #define   GET32RF64QP_DCstep_C(r32)                        _BFGET_(r32,23,16)
    #define   SET32RF64QP_DCstep_C(r32,v)                      _BFSET_(r32,23,16,v)
    #define   GET16RF64QP_DCstep_C(r16)                        _BFGET_(r16, 7, 0)
    #define   SET16RF64QP_DCstep_C(r16,v)                      _BFSET_(r16, 7, 0,v)

    #define   GET32RF64QP_ACstep_C(r32)                        _BFGET_(r32,31,24)
    #define   SET32RF64QP_ACstep_C(r32,v)                      _BFSET_(r32,31,24,v)
    #define   GET16RF64QP_ACstep_C(r16)                        _BFGET_(r16,15, 8)
    #define   SET16RF64QP_ACstep_C(r16,v)                      _BFSET_(r16,15, 8,v)

            UNSG32 u_DCstep_Y                                  :  8;
            UNSG32 u_ACstep_Y                                  :  8;
            UNSG32 u_DCstep_C                                  :  8;
            UNSG32 u_ACstep_C                                  :  8;
    ///////////////////////////////////////////////////////////
    #define   GET32RF64QP_RSVD8(r32)                           _BFGET_(r32, 7, 0)
    #define   SET32RF64QP_RSVD8(r32,v)                         _BFSET_(r32, 7, 0,v)
    #define   GET16RF64QP_RSVD8(r16)                           _BFGET_(r16, 7, 0)
    #define   SET16RF64QP_RSVD8(r16,v)                         _BFSET_(r16, 7, 0,v)

    #define   GET32RF64QP_QPY(r32)                             _BFGET_(r32,15, 8)
    #define   SET32RF64QP_QPY(r32,v)                           _BFSET_(r32,15, 8,v)
    #define   GET16RF64QP_QPY(r16)                             _BFGET_(r16,15, 8)
    #define   SET16RF64QP_QPY(r16,v)                           _BFSET_(r16,15, 8,v)

    #define   GET32RF64QP_QPU(r32)                             _BFGET_(r32,23,16)
    #define   SET32RF64QP_QPU(r32,v)                           _BFSET_(r32,23,16,v)
    #define   GET16RF64QP_QPU(r16)                             _BFGET_(r16, 7, 0)
    #define   SET16RF64QP_QPU(r16,v)                           _BFSET_(r16, 7, 0,v)

    #define   GET32RF64QP_QPV(r32)                             _BFGET_(r32,31,24)
    #define   SET32RF64QP_QPV(r32,v)                           _BFSET_(r32,31,24,v)
    #define   GET16RF64QP_QPV(r16)                             _BFGET_(r16,15, 8)
    #define   SET16RF64QP_QPV(r16,v)                           _BFSET_(r16,15, 8,v)

            UNSG32 u_RSVD8                                     :  8;
            UNSG32 u_QPY                                       :  8;
            UNSG32 u_QPU                                       :  8;
            UNSG32 u_QPV                                       :  8;
    ///////////////////////////////////////////////////////////
    } SIE_RF64QP;

    ///////////////////////////////////////////////////////////
     SIGN32 RF64QP_drvrd(SIE_RF64QP *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 RF64QP_drvwr(SIE_RF64QP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void RF64QP_reset(SIE_RF64QP *p);
     SIGN32 RF64QP_cmp  (SIE_RF64QP *p, SIE_RF64QP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define RF64QP_check(p,pie,pfx,hLOG) RF64QP_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define RF64QP_print(p,    pfx,hLOG) RF64QP_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: RF64QP
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE NLUTCTX                 biu              (4,4)
///     ###
///     * RF64 context for nLut
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock
///                                    * [64:2047]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD                 
///               $LUT64b              RSVD              REG      [31]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End NLUTCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_NLUTCTX
#define h_NLUTCTX (){}

    #define     RA_NLUTCTX_MB                                  0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_NLUTCTX_RSVD                                0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_NLUTCTX_PIC                                 0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_NLUTCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[31];
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_NLUTCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 NLUTCTX_drvrd(SIE_NLUTCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 NLUTCTX_drvwr(SIE_NLUTCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void NLUTCTX_reset(SIE_NLUTCTX *p);
     SIGN32 NLUTCTX_cmp  (SIE_NLUTCTX *p, SIE_NLUTCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define NLUTCTX_check(p,pie,pfx,hLOG) NLUTCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define NLUTCTX_print(p,    pfx,hLOG) NLUTCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: NLUTCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE BITOPCTX                biu              (4,4)
///     ###
///     * Operator format for BitOp extension
///     * [0:3583]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 RSVD                 
///               $LUT64b              RSVD              REG      [56]
///                                    ###
///                                    * padding to 3583
///                                    * [3584:3711]
///                                    ###
///     @ 0x001C0                      (P)
///     # 0x001C0 CTX                  
///               $BITOPRF64           CTX               REG          
///                                    ###
///                                    * Four BitOp commands, selected by extension ID
///                                    * End BitOpCtx
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITOPCTX
#define h_BITOPCTX (){}

    #define     RA_BITOPCTX_RSVD                               0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_BITOPCTX_CTX                                0x01C0
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITOPCTX {
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[56];
    ///////////////////////////////////////////////////////////
              SIE_BITOPRF64                                    ie_CTX;
    ///////////////////////////////////////////////////////////
    } SIE_BITOPCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 BITOPCTX_drvrd(SIE_BITOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITOPCTX_drvwr(SIE_BITOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITOPCTX_reset(SIE_BITOPCTX *p);
     SIGN32 BITOPCTX_cmp  (SIE_BITOPCTX *p, SIE_BITOPCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITOPCTX_check(p,pie,pfx,hLOG) BITOPCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITOPCTX_print(p,    pfx,hLOG) BITOPCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITOPCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE DQCTX                   biu              (4,4)
///     ###
///     * RF64 context for dQuant
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Reserved for RF64MB
///                                    * [64:191]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 QPX                  
///               $RF64QP              QPX               REG          
///                                    ###
///                                    * QP of current block
///                                    ###
///     @ 0x00010                      (P)
///     # 0x00010 QPN                  
///               $RF64QP              QPN               REG          
///                                    ###
///                                    * QP of neighboring block
///                                    * Used for VC-1/MPEG-4 DC/AC prediction
///                                    * [192:2047]
///                                    ###
///     @ 0x00018                      (P)
///     # 0x00018 RSVD                 
///               $LUT64b              RSVD              REG      [29]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End DQCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_DQCTX
#define h_DQCTX (){}

    #define     RA_DQCTX_MB                                    0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_DQCTX_QPX                                   0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_DQCTX_QPN                                   0x0010
    ///////////////////////////////////////////////////////////
    #define     RA_DQCTX_RSVD                                  0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_DQCTX_PIC                                   0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_DQCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPX;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPN;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[29];
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_DQCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 DQCTX_drvrd(SIE_DQCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 DQCTX_drvwr(SIE_DQCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void DQCTX_reset(SIE_DQCTX *p);
     SIGN32 DQCTX_cmp  (SIE_DQCTX *p, SIE_DQCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define DQCTX_check(p,pie,pfx,hLOG) DQCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define DQCTX_print(p,    pfx,hLOG) DQCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: DQCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ASPCTX                  biu              (4,4)
///     ###
///     * RF64 context for ASP
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Reserved for RF64MB
///                                    * [64:255]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD                 
///               $LUT64b              RSVD              REG       [3]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    ###
///     @ 0x00020                      (P)
///     # 0x00020 D33                  
///               $HCTX4x4             D33               REG          
///                                    ###
///                                    * Y(-1,-1)
///                                    ###
///     @ 0x00030                      (P)
///     # 0x00030 B30                  
///               $HCTX4x4             B30               REG          
///                                    ###
///                                    * Y(0,-1) or U(0,-1) or DCU(0,-1)
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 B31                  
///               $HCTX4x4             B31               REG          
///                                    ###
///                                    * Y(1,-1) or V(0,-1) or DCV(0,-1)
///                                    ###
///     @ 0x00050                      (P)
///     # 0x00050 B32                  
///               $HCTX4x4             B32               REG          
///                                    ###
///                                    * Y(2,-1) or U(1,-1)
///                                    ###
///     @ 0x00060                      (P)
///     # 0x00060 B33                  
///               $HCTX4x4             B33               REG          
///                                    ###
///                                    * Y(3,-1) or V(1,-1) or DCY(0,-1)
///                                    ###
///     @ 0x00070                      (P)
///     # 0x00070 C30                  
///               $HCTX4x4             C30               REG          
///                                    ###
///                                    * Y(4,-1)
///                                    ###
///     @ 0x00080                      (P)
///     # 0x00080 A03                  
///               $HCTX4x4             A03               REG          
///                                    ###
///                                    * Y(-1,0)
///                                    ###
///     @ 0x00090                      (P)
///     # 0x00090 A12                  
///               $HCTX4x4             A12               REG          
///                                    ###
///                                    * U(-1,0) & V(-1,0)
///                                    ###
///     @ 0x000A0                      (P)
///     # 0x000A0 A13                  
///               $HCTX4x4             A13               REG          
///                                    ###
///                                    * Y(-1,1)
///                                    ###
///     @ 0x000B0                      (P)
///     # 0x000B0 A23                  
///               $HCTX4x4             A23               REG          
///                                    ###
///                                    * Y(-1,2)
///                                    ###
///     @ 0x000C0                      (P)
///     # 0x000C0 A30                  
///               $HCTX4x4             A30               REG          
///                                    ###
///                                    * DCU(-1,0) & DCV(-1,0)
///                                    ###
///     @ 0x000D0                      (P)
///     # 0x000D0 A31                  
///               $HCTX4x4             A31               REG          
///                                    ###
///                                    * DCI(-1,0) & DCY(-1,0)
///                                    ###
///     @ 0x000E0                      (P)
///     # 0x000E0 A32                  
///               $HCTX4x4             A32               REG          
///                                    ###
///                                    * U(-1,1) & V(-1,1)
///                                    ###
///     @ 0x000F0                      (P)
///     # 0x000F0 A33                  
///               $HCTX4x4             A33               REG          
///                                    ###
///                                    * Y(-1,3)
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End ASPCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ASPCTX
#define h_ASPCTX (){}

    #define     RA_ASPCTX_MB                                   0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_RSVD                                 0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_D33                                  0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_B30                                  0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_B31                                  0x0040
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_B32                                  0x0050
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_B33                                  0x0060
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_C30                                  0x0070
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A03                                  0x0080
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A12                                  0x0090
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A13                                  0x00A0
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A23                                  0x00B0
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A30                                  0x00C0
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A31                                  0x00D0
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A32                                  0x00E0
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_A33                                  0x00F0
    ///////////////////////////////////////////////////////////
    #define     RA_ASPCTX_PIC                                  0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ASPCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[3];
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_D33;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B30;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B31;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B32;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B33;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_C30;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A03;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A12;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A13;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A23;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A30;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A31;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A32;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A33;
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_ASPCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 ASPCTX_drvrd(SIE_ASPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ASPCTX_drvwr(SIE_ASPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ASPCTX_reset(SIE_ASPCTX *p);
     SIGN32 ASPCTX_cmp  (SIE_ASPCTX *p, SIE_ASPCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ASPCTX_check(p,pie,pfx,hLOG) ASPCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ASPCTX_print(p,    pfx,hLOG) ASPCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ASPCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE HCTX_ARR                biu              (4,4)
///     ###
///     * 16 * HCTX4x4 for ASP
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 CTX                  
///               $HCTX4x4             CTX               REG      [16]
///                                    ###
///                                    * HCTX4x4
///                                    * End HCTX_ARR
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     256B, bits:    2048b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_HCTX_ARR
#define h_HCTX_ARR (){}

    #define     RA_HCTX_ARR_CTX                                0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_HCTX_ARR {
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_CTX[16];
    ///////////////////////////////////////////////////////////
    } SIE_HCTX_ARR;

    ///////////////////////////////////////////////////////////
     SIGN32 HCTX_ARR_drvrd(SIE_HCTX_ARR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 HCTX_ARR_drvwr(SIE_HCTX_ARR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void HCTX_ARR_reset(SIE_HCTX_ARR *p);
     SIGN32 HCTX_ARR_cmp  (SIE_HCTX_ARR *p, SIE_HCTX_ARR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define HCTX_ARR_check(p,pie,pfx,hLOG) HCTX_ARR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define HCTX_ARR_print(p,    pfx,hLOG) HCTX_ARR_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: HCTX_ARR
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ASECTX                  biu              (4,4)
///     ###
///     * RF64 context for ASE
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Reserved for RF64MB
///                                    * [64:255]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD                 
///               $LUT64b              RSVD              REG       [3]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    ###
///     @ 0x00020                      (P)
///     # 0x00020 D33                  
///               $HCTX4x4             D33               REG          
///                                    ###
///                                    * Y(-1,-1)
///                                    ###
///     @ 0x00030                      (P)
///     # 0x00030 B30                  
///               $HCTX4x4             B30               REG          
///                                    ###
///                                    * Y(0,-1) or U(0,-1) or DCU(0,-1)
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 B31                  
///               $HCTX4x4             B31               REG          
///                                    ###
///                                    * Y(1,-1) or V(0,-1) or DCV(0,-1)
///                                    ###
///     @ 0x00050                      (P)
///     # 0x00050 B32                  
///               $HCTX4x4             B32               REG          
///                                    ###
///                                    * Y(2,-1) or U(1,-1)
///                                    ###
///     @ 0x00060                      (P)
///     # 0x00060 B33                  
///               $HCTX4x4             B33               REG          
///                                    ###
///                                    * Y(3,-1) or V(1,-1) or DCY(0,-1)
///                                    ###
///     @ 0x00070                      (P)
///     # 0x00070 C30                  
///               $HCTX4x4             C30               REG          
///                                    ###
///                                    * Y(4,-1)
///                                    ###
///     @ 0x00080                      (P)
///     # 0x00080 A03                  
///               $HCTX4x4             A03               REG          
///                                    ###
///                                    * Y(-1,0)
///                                    ###
///     @ 0x00090                      (P)
///     # 0x00090 A12                  
///               $HCTX4x4             A12               REG          
///                                    ###
///                                    * U(-1,0) & V(-1,0)
///                                    ###
///     @ 0x000A0                      (P)
///     # 0x000A0 A13                  
///               $HCTX4x4             A13               REG          
///                                    ###
///                                    * Y(-1,1)
///                                    ###
///     @ 0x000B0                      (P)
///     # 0x000B0 A23                  
///               $HCTX4x4             A23               REG          
///                                    ###
///                                    * Y(-1,2)
///                                    ###
///     @ 0x000C0                      (P)
///     # 0x000C0 A30                  
///               $HCTX4x4             A30               REG          
///                                    ###
///                                    * DCU(-1,0) & DCV(-1,0)
///                                    ###
///     @ 0x000D0                      (P)
///     # 0x000D0 A31                  
///               $HCTX4x4             A31               REG          
///                                    ###
///                                    * DCI(-1,0) & DCY(-1,0)
///                                    ###
///     @ 0x000E0                      (P)
///     # 0x000E0 A32                  
///               $HCTX4x4             A32               REG          
///                                    ###
///                                    * U(-1,1) & V(-1,1)
///                                    ###
///     @ 0x000F0                      (P)
///     # 0x000F0 A33                  
///               $HCTX4x4             A33               REG          
///                                    ###
///                                    * Y(-1,3)
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End ASECTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ASECTX
#define h_ASECTX (){}

    #define     RA_ASECTX_MB                                   0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_RSVD                                 0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_D33                                  0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_B30                                  0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_B31                                  0x0040
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_B32                                  0x0050
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_B33                                  0x0060
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_C30                                  0x0070
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A03                                  0x0080
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A12                                  0x0090
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A13                                  0x00A0
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A23                                  0x00B0
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A30                                  0x00C0
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A31                                  0x00D0
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A32                                  0x00E0
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_A33                                  0x00F0
    ///////////////////////////////////////////////////////////
    #define     RA_ASECTX_PIC                                  0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ASECTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[3];
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_D33;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B30;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B31;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B32;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_B33;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_C30;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A03;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A12;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A13;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A23;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A30;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A31;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A32;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A33;
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_ASECTX;

    ///////////////////////////////////////////////////////////
     SIGN32 ASECTX_drvrd(SIE_ASECTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ASECTX_drvwr(SIE_ASECTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ASECTX_reset(SIE_ASECTX *p);
     SIGN32 ASECTX_cmp  (SIE_ASECTX *p, SIE_ASECTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ASECTX_check(p,pie,pfx,hLOG) ASECTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ASECTX_print(p,    pfx,hLOG) ASECTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ASECTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ASE_ND_CTX              biu              (4,4)
///     ###
///     * RF64 context for ASE (to store Neighbor D in MBAFF mode)
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 RSVD                 
///               $LUT64b              RSVD              REG          
///                                    ###
///                                    * Reserved for RF64MB
///                                    * [64:191]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 A03m                 
///               $HCTX4x4             A03m              REG          
///                                    ###
///                                    * Neighbor D for when locating at A03 in MBAFF mode
///                                    * [192:255]
///                                    ###
///     @ 0x00018                      (P)
///     # 0x00018 RSVD1                
///               $LUT64b              RSVD1             REG      [32]
///                                    ###
///                                    * [2240:2367]
///                                    ###
///     @ 0x00118                      (P)
///     # 0x00118 A13m                 
///               $HCTX4x4             A13m              REG          
///                                    ###
///                                    * Neighbor D for when locating at A13 in MBAFF mode
///                                    * [2368:2495]
///                                    ###
///     @ 0x00128                      (P)
///     # 0x00128 A23m                 
///               $HCTX4x4             A23m              REG          
///                                    ###
///                                    * Neighbor D for when locating at A23 in MBAFF mode
///                                    * [2496:4097]
///                                    ###
///     @ 0x00138                      (P)
///     # 0x00138 RSVD2                
///               $LUT64b              RSVD2             REG      [25]
///                                    ###
///                                    * Padding to the end
///                                    * End ASE_ND_CTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ASE_ND_CTX
#define h_ASE_ND_CTX (){}

    #define     RA_ASE_ND_CTX_RSVD                             0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_ASE_ND_CTX_A03m                             0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_ASE_ND_CTX_RSVD1                            0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_ASE_ND_CTX_A13m                             0x0118
    ///////////////////////////////////////////////////////////
    #define     RA_ASE_ND_CTX_A23m                             0x0128
    ///////////////////////////////////////////////////////////
    #define     RA_ASE_ND_CTX_RSVD2                            0x0138
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ASE_ND_CTX {
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A03m;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD1[32];
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A13m;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_A23m;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD2[25];
    ///////////////////////////////////////////////////////////
    } SIE_ASE_ND_CTX;

    ///////////////////////////////////////////////////////////
     SIGN32 ASE_ND_CTX_drvrd(SIE_ASE_ND_CTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ASE_ND_CTX_drvwr(SIE_ASE_ND_CTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ASE_ND_CTX_reset(SIE_ASE_ND_CTX *p);
     SIGN32 ASE_ND_CTX_cmp  (SIE_ASE_ND_CTX *p, SIE_ASE_ND_CTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ASE_ND_CTX_check(p,pie,pfx,hLOG) ASE_ND_CTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ASE_ND_CTX_print(p,    pfx,hLOG) ASE_ND_CTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ASE_ND_CTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE FOPCTX                  biu              (4,4)
///     ###
///     * RF64 context for FOP
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock
///                                    * [64:447]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 QPX0                 
///               $RF64QP              QPX0              REG          
///                                    ###
///                                    * QP of current MB
///                                    ###
///     @ 0x00010                      (P)
///     # 0x00010 QPX1                 
///               $RF64QP              QPX1              REG          
///                                    ###
///                                    * QP of current MB
///                                    ###
///     @ 0x00018                      (P)
///     # 0x00018 QPA0                 
///               $RF64QP              QPA0              REG          
///                                    ###
///                                    * QP of even MB of left MB pair
///                                    ###
///     @ 0x00020                      (P)
///     # 0x00020 QPA1                 
///               $RF64QP              QPA1              REG          
///                                    ###
///                                    * QP of odd MB of left MB pair
///                                    ###
///     @ 0x00028                      (P)
///     # 0x00028 QPB0                 
///               $RF64QP              QPB0              REG          
///                                    ###
///                                    * QP of even MB of top MB pair
///                                    ###
///     @ 0x00030                      (P)
///     # 0x00030 QPB1                 
///               $RF64QP              QPB1              REG          
///                                    ###
///                                    * QP of odd MB of top MB pair
///                                    * [448:831]
///                                    ###
///     @ 0x00038                      (P)
///     # 0x00038 BlkX                 
///               $HCTX4x4             BlkX              REG          
///                                    ###
///                                    * Context for current block
///                                    ###
///     @ 0x00048                      (P)
///     # 0x00048 BlkA                 
///               $HCTX4x4             BlkA              REG          
///                                    ###
///                                    * Context for left neighbor
///                                    ###
///     @ 0x00058                      (P)
///     # 0x00058 BlkB                 
///               $HCTX4x4             BlkB              REG          
///                                    ###
///                                    * Context for top block
///                                    ###
///     @ 0x00068                      (P)
///     # 0x00068 BlkC                 
///               $HCTX4x4             BlkC              REG          
///                                    ###
///                                    * Block context used in VC-1 main profile P exception 2.
///                                    * [960:2047]
///                                    ###
///     @ 0x00078                      (P)
///     # 0x00078 RSVD                 
///               $LUT64b              RSVD              REG      [17]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End RF64CTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_FOPCTX
#define h_FOPCTX (){}

    #define     RA_FOPCTX_MB                                   0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_QPX0                                 0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_QPX1                                 0x0010
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_QPA0                                 0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_QPA1                                 0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_QPB0                                 0x0028
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_QPB1                                 0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_BlkX                                 0x0038
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_BlkA                                 0x0048
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_BlkB                                 0x0058
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_BlkC                                 0x0068
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_RSVD                                 0x0078
    ///////////////////////////////////////////////////////////
    #define     RA_FOPCTX_PIC                                  0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_FOPCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPX0;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPX1;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPA0;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPA1;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPB0;
    ///////////////////////////////////////////////////////////
              SIE_RF64QP                                       ie_QPB1;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_BlkX;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_BlkA;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_BlkB;
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_BlkC;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[17];
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_FOPCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 FOPCTX_drvrd(SIE_FOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 FOPCTX_drvwr(SIE_FOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void FOPCTX_reset(SIE_FOPCTX *p);
     SIGN32 FOPCTX_cmp  (SIE_FOPCTX *p, SIE_FOPCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define FOPCTX_check(p,pie,pfx,hLOG) FOPCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define FOPCTX_print(p,    pfx,hLOG) FOPCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: FOPCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pmvScale                biu              (4,4)
///     ###
///     * Scaling factors for PMV calculation (for AVS)
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 32 scaleA                    
///                                    ###
///                                    * Scaling factor for MVs of block A
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 32 scaleB                    
///                                    ###
///                                    * Scaling factor for MVs of block B
///                                    * [64:127]
///                                    ###
///     @ 0x00008                      (P)
///               %unsigned 32 scaleC                    
///                                    ###
///                                    * Scaling factor for MVs of block C
///                                    ###
///     @ 0x0000C                      (P)
///               %unsigned 32 scaleD                    
///                                    ###
///                                    * Scaling factor for MVs of block D
///                                    * End pmvScale
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:     128b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pmvScale
#define h_pmvScale (){}

    #define     BA_pmvScale_scaleA                             0x0000
    #define     B16pmvScale_scaleA                             0x0000
    #define   LSb32pmvScale_scaleA                                0
    #define   LSb16pmvScale_scaleA                                0
    #define       bpmvScale_scaleA                             32
    #define   MSK32pmvScale_scaleA                                0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    #define     BA_pmvScale_scaleB                             0x0004
    #define     B16pmvScale_scaleB                             0x0004
    #define   LSb32pmvScale_scaleB                                0
    #define   LSb16pmvScale_scaleB                                0
    #define       bpmvScale_scaleB                             32
    #define   MSK32pmvScale_scaleB                                0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    #define     BA_pmvScale_scaleC                             0x0008
    #define     B16pmvScale_scaleC                             0x0008
    #define   LSb32pmvScale_scaleC                                0
    #define   LSb16pmvScale_scaleC                                0
    #define       bpmvScale_scaleC                             32
    #define   MSK32pmvScale_scaleC                                0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    #define     BA_pmvScale_scaleD                             0x000C
    #define     B16pmvScale_scaleD                             0x000C
    #define   LSb32pmvScale_scaleD                                0
    #define   LSb16pmvScale_scaleD                                0
    #define       bpmvScale_scaleD                             32
    #define   MSK32pmvScale_scaleD                                0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pmvScale {
    ///////////////////////////////////////////////////////////
    #define   GET32pmvScale_scaleA(r32)                        _BFGET_(r32,31, 0)
    #define   SET32pmvScale_scaleA(r32,v)                      _BFSET_(r32,31, 0,v)

            UNSG32 u_scaleA                                    : 32;
    ///////////////////////////////////////////////////////////
    #define   GET32pmvScale_scaleB(r32)                        _BFGET_(r32,31, 0)
    #define   SET32pmvScale_scaleB(r32,v)                      _BFSET_(r32,31, 0,v)

            UNSG32 u_scaleB                                    : 32;
    ///////////////////////////////////////////////////////////
    #define   GET32pmvScale_scaleC(r32)                        _BFGET_(r32,31, 0)
    #define   SET32pmvScale_scaleC(r32,v)                      _BFSET_(r32,31, 0,v)

            UNSG32 u_scaleC                                    : 32;
    ///////////////////////////////////////////////////////////
    #define   GET32pmvScale_scaleD(r32)                        _BFGET_(r32,31, 0)
    #define   SET32pmvScale_scaleD(r32,v)                      _BFSET_(r32,31, 0,v)

            UNSG32 u_scaleD                                    : 32;
    ///////////////////////////////////////////////////////////
    } SIE_pmvScale;

    ///////////////////////////////////////////////////////////
     SIGN32 pmvScale_drvrd(SIE_pmvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pmvScale_drvwr(SIE_pmvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pmvScale_reset(SIE_pmvScale *p);
     SIGN32 pmvScale_cmp  (SIE_pmvScale *p, SIE_pmvScale *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pmvScale_check(p,pie,pfx,hLOG) pmvScale_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pmvScale_print(p,    pfx,hLOG) pmvScale_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pmvScale
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE PMVCTX                  biu              (4,4)
///     ###
///     * RF64 context for PMV
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock
///                                    * [64:447]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD0                
///               $LUT64b              RSVD0             REG       [6]
///                                    ###
///                                    * padding to align block-level context
///                                    * [448:1087]
///                                    ###
///     @ 0x00038                      (P)
///     # 0x00038 BlkX                 
///               $FCTX                BlkX              REG          
///                                    ###
///                                    * Context for current block
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 ChromaMV             
///               $MV                  ChromaMV          REG          
///                                    ###
///                                    * MPEG-4 chroma MV
///                                    ###
///     @ 0x00044                      (P)
///               %unsigned 32 RSVDX                     
///                                    ###
///                                    * padding to 128-bit
///                                    ###
///     @ 0x00048                      (P)
///     # 0x00048 BlkA                 
///               $FCTX                BlkA              REG          
///                                    ###
///                                    * Context for left neighbor
///                                    ###
///     @ 0x00050                      (P)
///     # 0x00050 BlkD                 
///               $FCTX                BlkD              REG          
///                                    ###
///                                    * Context for upper-left neighbor
///                                    ###
///     @ 0x00058                      (P)
///     # 0x00058 BlkB                 
///               $FCTX                BlkB              REG          
///                                    ###
///                                    * Context for top neighbor
///                                    ###
///     @ 0x00060                      (P)
///     # 0x00060 BlkC                 
///               $FCTX                BlkC              REG          
///                                    ###
///                                    * Context for upper-right neighbor
///                                    ###
///     @ 0x00068                      (P)
///     # 0x00068 BlkA1                
///               $FCTX                BlkA1             REG          
///                                    ###
///                                    * Context for 2nd left neighbor, interlace frame
///                                    ###
///     @ 0x00070                      (P)
///     # 0x00070 BlkD1                
///               $FCTX                BlkD1             REG          
///                                    ###
///                                    * Context for 2nd upper-left neighbor, interlace frame
///                                    ###
///     @ 0x00078                      (P)
///     # 0x00078 BlkB1                
///               $FCTX                BlkB1             REG          
///                                    ###
///                                    * Context for 2nd top neighbor, interlace frame
///                                    ###
///     @ 0x00080                      (P)
///     # 0x00080 BlkC1                
///               $FCTX                BlkC1             REG          
///                                    ###
///                                    * Context for 2nd up-right neighbor, interlace frame only
///                                    * [1088:1727]
///                                    ###
///     @ 0x00088                      (P)
///               %unsigned 32 pmvScale_0i               
///               %unsigned 32 pmvScale_1i               
///               %unsigned 32 pmvScale_2i               
///               %unsigned 32 pmvScale_3i               
///               %unsigned 32 pmvScale_4i               
///               %unsigned 32 pmvScale_5i               
///               %unsigned 32 pmvScale_6i               
///               %unsigned 32 pmvScale_7i               
///               %unsigned 32 pmvScale_8i               
///               %unsigned 32 pmvScale_9i               
///               %unsigned 32 pmvScale_10i              
///               %unsigned 32 pmvScale_11i              
///               %unsigned 32 pmvScale_12i              
///               %unsigned 32 pmvScale_13i              
///               %unsigned 32 pmvScale_14i              
///               %unsigned 32 pmvScale_15i              
///               %unsigned 32 pmvScale_16i              
///               %unsigned 32 pmvScale_17i              
///               %unsigned 32 pmvScale_18i              
///               %unsigned 32 pmvScale_19i              
///                                    ###
///                                    * Scale candidates for PMV.
///                                    * [1727:2047]
///                                    ###
///     @ 0x000D8                      (P)
///     # 0x000D8 RSVD                 
///               $LUT64b              RSVD              REG       [5]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End PMVCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_PMVCTX
#define h_PMVCTX (){}

    #define     RA_PMVCTX_MB                                   0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_RSVD0                                0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkX                                 0x0038
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_ChromaMV                             0x0040
    ///////////////////////////////////////////////////////////

    #define     BA_PMVCTX_RSVDX                                0x0044
    #define     B16PMVCTX_RSVDX                                0x0044
    #define   LSb32PMVCTX_RSVDX                                   0
    #define   LSb16PMVCTX_RSVDX                                   0
    #define       bPMVCTX_RSVDX                                32
    #define   MSK32PMVCTX_RSVDX                                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkA                                 0x0048
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkD                                 0x0050
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkB                                 0x0058
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkC                                 0x0060
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkA1                                0x0068
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkD1                                0x0070
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkB1                                0x0078
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_BlkC1                                0x0080
    ///////////////////////////////////////////////////////////

    #define     BA_PMVCTX_pmvScale_0i                          0x0088
    #define     B16PMVCTX_pmvScale_0i                          0x0088
    #define   LSb32PMVCTX_pmvScale_0i                             0
    #define   LSb16PMVCTX_pmvScale_0i                             0
    #define       bPMVCTX_pmvScale_0i                          32
    #define   MSK32PMVCTX_pmvScale_0i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_1i                          0x008C
    #define     B16PMVCTX_pmvScale_1i                          0x008C
    #define   LSb32PMVCTX_pmvScale_1i                             0
    #define   LSb16PMVCTX_pmvScale_1i                             0
    #define       bPMVCTX_pmvScale_1i                          32
    #define   MSK32PMVCTX_pmvScale_1i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_2i                          0x0090
    #define     B16PMVCTX_pmvScale_2i                          0x0090
    #define   LSb32PMVCTX_pmvScale_2i                             0
    #define   LSb16PMVCTX_pmvScale_2i                             0
    #define       bPMVCTX_pmvScale_2i                          32
    #define   MSK32PMVCTX_pmvScale_2i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_3i                          0x0094
    #define     B16PMVCTX_pmvScale_3i                          0x0094
    #define   LSb32PMVCTX_pmvScale_3i                             0
    #define   LSb16PMVCTX_pmvScale_3i                             0
    #define       bPMVCTX_pmvScale_3i                          32
    #define   MSK32PMVCTX_pmvScale_3i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_4i                          0x0098
    #define     B16PMVCTX_pmvScale_4i                          0x0098
    #define   LSb32PMVCTX_pmvScale_4i                             0
    #define   LSb16PMVCTX_pmvScale_4i                             0
    #define       bPMVCTX_pmvScale_4i                          32
    #define   MSK32PMVCTX_pmvScale_4i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_5i                          0x009C
    #define     B16PMVCTX_pmvScale_5i                          0x009C
    #define   LSb32PMVCTX_pmvScale_5i                             0
    #define   LSb16PMVCTX_pmvScale_5i                             0
    #define       bPMVCTX_pmvScale_5i                          32
    #define   MSK32PMVCTX_pmvScale_5i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_6i                          0x00A0
    #define     B16PMVCTX_pmvScale_6i                          0x00A0
    #define   LSb32PMVCTX_pmvScale_6i                             0
    #define   LSb16PMVCTX_pmvScale_6i                             0
    #define       bPMVCTX_pmvScale_6i                          32
    #define   MSK32PMVCTX_pmvScale_6i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_7i                          0x00A4
    #define     B16PMVCTX_pmvScale_7i                          0x00A4
    #define   LSb32PMVCTX_pmvScale_7i                             0
    #define   LSb16PMVCTX_pmvScale_7i                             0
    #define       bPMVCTX_pmvScale_7i                          32
    #define   MSK32PMVCTX_pmvScale_7i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_8i                          0x00A8
    #define     B16PMVCTX_pmvScale_8i                          0x00A8
    #define   LSb32PMVCTX_pmvScale_8i                             0
    #define   LSb16PMVCTX_pmvScale_8i                             0
    #define       bPMVCTX_pmvScale_8i                          32
    #define   MSK32PMVCTX_pmvScale_8i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_9i                          0x00AC
    #define     B16PMVCTX_pmvScale_9i                          0x00AC
    #define   LSb32PMVCTX_pmvScale_9i                             0
    #define   LSb16PMVCTX_pmvScale_9i                             0
    #define       bPMVCTX_pmvScale_9i                          32
    #define   MSK32PMVCTX_pmvScale_9i                             0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_10i                         0x00B0
    #define     B16PMVCTX_pmvScale_10i                         0x00B0
    #define   LSb32PMVCTX_pmvScale_10i                            0
    #define   LSb16PMVCTX_pmvScale_10i                            0
    #define       bPMVCTX_pmvScale_10i                         32
    #define   MSK32PMVCTX_pmvScale_10i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_11i                         0x00B4
    #define     B16PMVCTX_pmvScale_11i                         0x00B4
    #define   LSb32PMVCTX_pmvScale_11i                            0
    #define   LSb16PMVCTX_pmvScale_11i                            0
    #define       bPMVCTX_pmvScale_11i                         32
    #define   MSK32PMVCTX_pmvScale_11i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_12i                         0x00B8
    #define     B16PMVCTX_pmvScale_12i                         0x00B8
    #define   LSb32PMVCTX_pmvScale_12i                            0
    #define   LSb16PMVCTX_pmvScale_12i                            0
    #define       bPMVCTX_pmvScale_12i                         32
    #define   MSK32PMVCTX_pmvScale_12i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_13i                         0x00BC
    #define     B16PMVCTX_pmvScale_13i                         0x00BC
    #define   LSb32PMVCTX_pmvScale_13i                            0
    #define   LSb16PMVCTX_pmvScale_13i                            0
    #define       bPMVCTX_pmvScale_13i                         32
    #define   MSK32PMVCTX_pmvScale_13i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_14i                         0x00C0
    #define     B16PMVCTX_pmvScale_14i                         0x00C0
    #define   LSb32PMVCTX_pmvScale_14i                            0
    #define   LSb16PMVCTX_pmvScale_14i                            0
    #define       bPMVCTX_pmvScale_14i                         32
    #define   MSK32PMVCTX_pmvScale_14i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_15i                         0x00C4
    #define     B16PMVCTX_pmvScale_15i                         0x00C4
    #define   LSb32PMVCTX_pmvScale_15i                            0
    #define   LSb16PMVCTX_pmvScale_15i                            0
    #define       bPMVCTX_pmvScale_15i                         32
    #define   MSK32PMVCTX_pmvScale_15i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_16i                         0x00C8
    #define     B16PMVCTX_pmvScale_16i                         0x00C8
    #define   LSb32PMVCTX_pmvScale_16i                            0
    #define   LSb16PMVCTX_pmvScale_16i                            0
    #define       bPMVCTX_pmvScale_16i                         32
    #define   MSK32PMVCTX_pmvScale_16i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_17i                         0x00CC
    #define     B16PMVCTX_pmvScale_17i                         0x00CC
    #define   LSb32PMVCTX_pmvScale_17i                            0
    #define   LSb16PMVCTX_pmvScale_17i                            0
    #define       bPMVCTX_pmvScale_17i                         32
    #define   MSK32PMVCTX_pmvScale_17i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_18i                         0x00D0
    #define     B16PMVCTX_pmvScale_18i                         0x00D0
    #define   LSb32PMVCTX_pmvScale_18i                            0
    #define   LSb16PMVCTX_pmvScale_18i                            0
    #define       bPMVCTX_pmvScale_18i                         32
    #define   MSK32PMVCTX_pmvScale_18i                            0xFFFFFFFF

    #define     BA_PMVCTX_pmvScale_19i                         0x00D4
    #define     B16PMVCTX_pmvScale_19i                         0x00D4
    #define   LSb32PMVCTX_pmvScale_19i                            0
    #define   LSb16PMVCTX_pmvScale_19i                            0
    #define       bPMVCTX_pmvScale_19i                         32
    #define   MSK32PMVCTX_pmvScale_19i                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_RSVD                                 0x00D8
    ///////////////////////////////////////////////////////////
    #define     RA_PMVCTX_PIC                                  0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_PMVCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD0[6];
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkX;
    ///////////////////////////////////////////////////////////
              SIE_MV                                           ie_ChromaMV;
    ///////////////////////////////////////////////////////////
    #define   GET32PMVCTX_RSVDX(r32)                           _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_RSVDX(r32,v)                         _BFSET_(r32,31, 0,v)

            UNSG32 u_RSVDX                                     : 32;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkA;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkD;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkB;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkC;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkA1;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkD1;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkB1;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkC1;
    ///////////////////////////////////////////////////////////
    #define   GET32PMVCTX_pmvScale_0i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_0i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_0i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_1i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_1i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_1i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_2i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_2i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_2i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_3i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_3i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_3i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_4i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_4i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_4i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_5i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_5i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_5i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_6i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_6i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_6i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_7i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_7i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_7i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_8i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_8i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_8i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_9i(r32)                     _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_9i(r32,v)                   _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_9i                               : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_10i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_10i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_10i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_11i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_11i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_11i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_12i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_12i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_12i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_13i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_13i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_13i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_14i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_14i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_14i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_15i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_15i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_15i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_16i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_16i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_16i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_17i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_17i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_17i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_18i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_18i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_18i                              : 32;
    ///////////////////////////////////////////////////////////

    #define   GET32PMVCTX_pmvScale_19i(r32)                    _BFGET_(r32,31, 0)
    #define   SET32PMVCTX_pmvScale_19i(r32,v)                  _BFSET_(r32,31, 0,v)

            UNSG32 u_pmvScale_19i                              : 32;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[5];
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_PMVCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 PMVCTX_drvrd(SIE_PMVCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 PMVCTX_drvwr(SIE_PMVCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void PMVCTX_reset(SIE_PMVCTX *p);
     SIGN32 PMVCTX_cmp  (SIE_PMVCTX *p, SIE_PMVCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define PMVCTX_check(p,pie,pfx,hLOG) PMVCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define PMVCTX_print(p,    pfx,hLOG) PMVCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: PMVCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE dirMvCTX                biu              (4,4)
///     ###
///     * RF64 context for direct mode MV calculation
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Reserved for RF64MB
///                                    * [64:447]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD0                
///               $LUT64b              RSVD0             REG       [6]
///                                    ###
///                                    * padding to align block-level context
///                                    * [448:575]
///                                    ###
///     @ 0x00038                      (P)
///     # 0x00038 BlkX                 
///               $HCTX4x4             BlkX              REG          
///                                    ###
///                                    * Context of the current block; 128-bit.
///                                    * [576:639]
///                                    ###
///     @ 0x00048                      (P)
///     # 0x00048 BlkCol               
///               $FCTX                BlkCol            REG          
///                                    ###
///                                    * Context of co-located block; 64-bit.
///                                    * [640:703]
///                                    ###
///     @ 0x00050                      (P)
///     # 0x00050 mvScale              
///               $dirMvScale          mvScale           REG          
///                                    ###
///                                    * MV scaling factor for temporal direct mode; 64 bits
///                                    * [704:1919]
///                                    ###
///     @ 0x00058                      (P)
///     # 0x00058 RSVD                 
///               $LUT64b              RSVD              REG      [19]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [1920:2047]
///                                    ###
///     @ 0x000F0                      (P)
///     # 0x000F0 MbPMV                
///               $HCTX4x4             MbPMV             REG          
///                                    ###
///                                    * Macroblock PMV, for spatial direct mode only
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End dirMvCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_dirMvCTX
#define h_dirMvCTX (){}

    #define     RA_dirMvCTX_MB                                 0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_RSVD0                              0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_BlkX                               0x0038
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_BlkCol                             0x0048
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_mvScale                            0x0050
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_RSVD                               0x0058
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_MbPMV                              0x00F0
    ///////////////////////////////////////////////////////////
    #define     RA_dirMvCTX_PIC                                0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_dirMvCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD0[6];
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_BlkX;
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_BlkCol;
    ///////////////////////////////////////////////////////////
              SIE_dirMvScale                                   ie_mvScale;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[19];
    ///////////////////////////////////////////////////////////
              SIE_HCTX4x4                                      ie_MbPMV;
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_dirMvCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 dirMvCTX_drvrd(SIE_dirMvCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 dirMvCTX_drvwr(SIE_dirMvCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void dirMvCTX_reset(SIE_dirMvCTX *p);
     SIGN32 dirMvCTX_cmp  (SIE_dirMvCTX *p, SIE_dirMvCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define dirMvCTX_check(p,pie,pfx,hLOG) dirMvCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define dirMvCTX_print(p,    pfx,hLOG) dirMvCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: dirMvCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE vcMsgCTX                biu              (4,4)
///     ###
///     * RF64 context for the vcMsg extension
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * 64b macroblock-level parameter
///                                    * [64:447]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD0                
///               $LUT64b              RSVD0             REG       [6]
///                                    ###
///                                    * padding to align block-level context
///                                    * [448:511]
///                                    ###
///     @ 0x00038                      (P)
///     # 0x00038 blkX                 
///               $FCTX                blkX              REG          
///                                    ###
///                                    * Motion information context of current partition
///                                    * [512:2047]
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 RSVD                 
///               $LUT64b              RSVD              REG      [24]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End vcMsgCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vcMsgCTX
#define h_vcMsgCTX (){}

    #define     RA_vcMsgCTX_MB                                 0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_vcMsgCTX_RSVD0                              0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_vcMsgCTX_blkX                               0x0038
    ///////////////////////////////////////////////////////////
    #define     RA_vcMsgCTX_RSVD                               0x0040
    ///////////////////////////////////////////////////////////
    #define     RA_vcMsgCTX_PIC                                0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vcMsgCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD0[6];
    ///////////////////////////////////////////////////////////
              SIE_FCTX                                         ie_blkX;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[24];
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_vcMsgCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 vcMsgCTX_drvrd(SIE_vcMsgCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vcMsgCTX_drvwr(SIE_vcMsgCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vcMsgCTX_reset(SIE_vcMsgCTX *p);
     SIGN32 vcMsgCTX_cmp  (SIE_vcMsgCTX *p, SIE_vcMsgCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vcMsgCTX_check(p,pie,pfx,hLOG) vcMsgCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vcMsgCTX_print(p,    pfx,hLOG) vcMsgCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vcMsgCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE vldCTX                  biu              (4,4)
///     ###
///     * RF64 context for vld
///     * [0:63]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 MB                   
///               $RF64MB              MB                REG          
///                                    ###
///                                    * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock
///                                    * [64:2047]
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 RSVD                 
///               $LUT64b              RSVD              REG      [31]
///                                    ###
///                                    * padding to 2048-bit boundary
///                                    * [2048:4095]
///                                    ###
///     @ 0x00100                      (P)
///     # 0x00100 PIC                  
///               $RF64PIC             PIC               REG          
///                                    ###
///                                    * Picture-level Parameters for ALU64 extensions.
///                                    * End vldCTX
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     512B, bits:    4096b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vldCTX
#define h_vldCTX (){}

    #define     RA_vldCTX_MB                                   0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_vldCTX_RSVD                                 0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_vldCTX_PIC                                  0x0100
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vldCTX {
    ///////////////////////////////////////////////////////////
              SIE_RF64MB                                       ie_MB;
    ///////////////////////////////////////////////////////////
              SIE_LUT64b                                       ie_RSVD[31];
    ///////////////////////////////////////////////////////////
              SIE_RF64PIC                                      ie_PIC;
    ///////////////////////////////////////////////////////////
    } SIE_vldCTX;

    ///////////////////////////////////////////////////////////
     SIGN32 vldCTX_drvrd(SIE_vldCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vldCTX_drvwr(SIE_vldCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vldCTX_reset(SIE_vldCTX *p);
     SIGN32 vldCTX_cmp  (SIE_vldCTX *p, SIE_vldCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vldCTX_check(p,pie,pfx,hLOG) vldCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vldCTX_print(p,    pfx,hLOG) vldCTX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vldCTX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ClkRstBiu               biu              (4,4)
///     ###
///     * Common Biu Unit used for block level reset and clock gating control
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CRCtl                (P)
///               ###
///               * Clock Reset Control Register
///               ###
///               %unsigned 1  rst                       0x1
///                                    ###
///                                    * Software reset. The reset signal is active low.
///                                    * 0 -> the block will be under reset.
///                                    * 1-> the block will be out of reset.
///                                    ###
///               %unsigned 1  swClk_en                  0x1
///                                    ###
///                                    * Software controlled clock enable.
///                                    * 0 -> The corresponding block will be disabled (gated)
///                                    * 1 -> The corresponding clock will be enabled (ungated)
///                                    ###
///               %unsigned 1  dyCG_en                   0x1
///                                    ###
///                                    * This is used to control (enalbe/disable) the HW self dynamic clock gating unit.
///                                    * 0 -> the dynamic clock gating will be disabled (the clock can not be turned off by dynamic clock gating unit).
///                                    * 1 -> the dynamic clock gating will be enabled (the clock can be dynamically turned on/off by the dynamic clock control unit).
///                                    * Here is the glue logic to generate the block level clock enable signal.
///                                    * ClkEn = swClk_en & (~dyCG_en | dyClk_en).
///                                    * swClk_en and dyCG_en are from this biu, and dyClk_en is the signal generated by the dynamic clock control unit.
///                                    * End of ClkRstBiu
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       3b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ClkRstBiu
#define h_ClkRstBiu (){}

    #define     RA_ClkRstBiu_CRCtl                             0x0000

    #define     BA_ClkRstBiu_CRCtl_rst                         0x0000
    #define     B16ClkRstBiu_CRCtl_rst                         0x0000
    #define   LSb32ClkRstBiu_CRCtl_rst                            0
    #define   LSb16ClkRstBiu_CRCtl_rst                            0
    #define       bClkRstBiu_CRCtl_rst                         1
    #define   MSK32ClkRstBiu_CRCtl_rst                            0x00000001

    #define     BA_ClkRstBiu_CRCtl_swClk_en                    0x0000
    #define     B16ClkRstBiu_CRCtl_swClk_en                    0x0000
    #define   LSb32ClkRstBiu_CRCtl_swClk_en                       1
    #define   LSb16ClkRstBiu_CRCtl_swClk_en                       1
    #define       bClkRstBiu_CRCtl_swClk_en                    1
    #define   MSK32ClkRstBiu_CRCtl_swClk_en                       0x00000002

    #define     BA_ClkRstBiu_CRCtl_dyCG_en                     0x0000
    #define     B16ClkRstBiu_CRCtl_dyCG_en                     0x0000
    #define   LSb32ClkRstBiu_CRCtl_dyCG_en                        2
    #define   LSb16ClkRstBiu_CRCtl_dyCG_en                        2
    #define       bClkRstBiu_CRCtl_dyCG_en                     1
    #define   MSK32ClkRstBiu_CRCtl_dyCG_en                        0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ClkRstBiu {
    ///////////////////////////////////////////////////////////
    #define   GET32ClkRstBiu_CRCtl_rst(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32ClkRstBiu_CRCtl_rst(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16ClkRstBiu_CRCtl_rst(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16ClkRstBiu_CRCtl_rst(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32ClkRstBiu_CRCtl_swClk_en(r32)               _BFGET_(r32, 1, 1)
    #define   SET32ClkRstBiu_CRCtl_swClk_en(r32,v)             _BFSET_(r32, 1, 1,v)
    #define   GET16ClkRstBiu_CRCtl_swClk_en(r16)               _BFGET_(r16, 1, 1)
    #define   SET16ClkRstBiu_CRCtl_swClk_en(r16,v)             _BFSET_(r16, 1, 1,v)

    #define   GET32ClkRstBiu_CRCtl_dyCG_en(r32)                _BFGET_(r32, 2, 2)
    #define   SET32ClkRstBiu_CRCtl_dyCG_en(r32,v)              _BFSET_(r32, 2, 2,v)
    #define   GET16ClkRstBiu_CRCtl_dyCG_en(r16)                _BFGET_(r16, 2, 2)
    #define   SET16ClkRstBiu_CRCtl_dyCG_en(r16,v)              _BFSET_(r16, 2, 2,v)

    #define     w32ClkRstBiu_CRCtl                             {\
            UNSG32 uCRCtl_rst                                  :  1;\
            UNSG32 uCRCtl_swClk_en                             :  1;\
            UNSG32 uCRCtl_dyCG_en                              :  1;\
            UNSG32 RSVDx0_b3                                   : 29;\
          }
    union { UNSG32 u32ClkRstBiu_CRCtl;
            struct w32ClkRstBiu_CRCtl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_ClkRstBiu;

    typedef union  T32ClkRstBiu_CRCtl
          { UNSG32 u32;
            struct w32ClkRstBiu_CRCtl;
                 } T32ClkRstBiu_CRCtl;
    ///////////////////////////////////////////////////////////

    typedef union  TClkRstBiu_CRCtl
          { UNSG32 u32[1];
            struct {
            struct w32ClkRstBiu_CRCtl;
                   };
                 } TClkRstBiu_CRCtl;

    ///////////////////////////////////////////////////////////
     SIGN32 ClkRstBiu_drvrd(SIE_ClkRstBiu *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ClkRstBiu_drvwr(SIE_ClkRstBiu *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ClkRstBiu_reset(SIE_ClkRstBiu *p);
     SIGN32 ClkRstBiu_cmp  (SIE_ClkRstBiu *p, SIE_ClkRstBiu *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ClkRstBiu_check(p,pie,pfx,hLOG) ClkRstBiu_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ClkRstBiu_print(p,    pfx,hLOG) ClkRstBiu_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ClkRstBiu
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE CacheCFG                                 (4,4)
///     ###
///     * On-the-fly messag to configure vCache.
///     * [00:31]
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///               %unsigned 32 val                       
///                                    ###
///                                    * 32b configuration data
///                                    * [32:63]
///                                    ###
///     @ 0x00004                      (P)
///               %unsigned 24 ptr                       
///                                    ###
///                                    * Configuration 32b word-address:
///                                    * equivalent as AHB programming byte address b[23:0]
///                                    ###
///               %unsigned 2  padding                   
///                                    ###
///                                    * Don't care for vCache configuration messages
///                                    ###
///               %unsigned 6  op                        
///                                    : CFG                      0x3F
///                                                 ###
///                                                 * vCache configuration mesage
///                                                 * End of CacheCFG
///                                                 ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CacheCFG
#define h_CacheCFG (){}

    #define     BA_CacheCFG_val                                0x0000
    #define     B16CacheCFG_val                                0x0000
    #define   LSb32CacheCFG_val                                   0
    #define   LSb16CacheCFG_val                                   0
    #define       bCacheCFG_val                                32
    #define   MSK32CacheCFG_val                                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    #define     BA_CacheCFG_ptr                                0x0004
    #define     B16CacheCFG_ptr                                0x0004
    #define   LSb32CacheCFG_ptr                                   0
    #define   LSb16CacheCFG_ptr                                   0
    #define       bCacheCFG_ptr                                24
    #define   MSK32CacheCFG_ptr                                   0x00FFFFFF

    #define     BA_CacheCFG_padding                            0x0007
    #define     B16CacheCFG_padding                            0x0006
    #define   LSb32CacheCFG_padding                               24
    #define   LSb16CacheCFG_padding                               8
    #define       bCacheCFG_padding                            2
    #define   MSK32CacheCFG_padding                               0x03000000

    #define     BA_CacheCFG_op                                 0x0007
    #define     B16CacheCFG_op                                 0x0006
    #define   LSb32CacheCFG_op                                    26
    #define   LSb16CacheCFG_op                                    10
    #define       bCacheCFG_op                                 6
    #define   MSK32CacheCFG_op                                    0xFC000000
    #define        CacheCFG_op_CFG                                          0x3F
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CacheCFG {
    ///////////////////////////////////////////////////////////
    #define   GET32CacheCFG_val(r32)                           _BFGET_(r32,31, 0)
    #define   SET32CacheCFG_val(r32,v)                         _BFSET_(r32,31, 0,v)

            UNSG32 u_val                                       : 32;
    ///////////////////////////////////////////////////////////
    #define   GET32CacheCFG_ptr(r32)                           _BFGET_(r32,23, 0)
    #define   SET32CacheCFG_ptr(r32,v)                         _BFSET_(r32,23, 0,v)

    #define   GET32CacheCFG_padding(r32)                       _BFGET_(r32,25,24)
    #define   SET32CacheCFG_padding(r32,v)                     _BFSET_(r32,25,24,v)
    #define   GET16CacheCFG_padding(r16)                       _BFGET_(r16, 9, 8)
    #define   SET16CacheCFG_padding(r16,v)                     _BFSET_(r16, 9, 8,v)

    #define   GET32CacheCFG_op(r32)                            _BFGET_(r32,31,26)
    #define   SET32CacheCFG_op(r32,v)                          _BFSET_(r32,31,26,v)
    #define   GET16CacheCFG_op(r16)                            _BFGET_(r16,15,10)
    #define   SET16CacheCFG_op(r16,v)                          _BFSET_(r16,15,10,v)

            UNSG32 u_ptr                                       : 24;
            UNSG32 u_padding                                   :  2;
            UNSG32 u_op                                        :  6;
    ///////////////////////////////////////////////////////////
    } SIE_CacheCFG;

    ///////////////////////////////////////////////////////////
     SIGN32 CacheCFG_drvrd(SIE_CacheCFG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CacheCFG_drvwr(SIE_CacheCFG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CacheCFG_reset(SIE_CacheCFG *p);
     SIGN32 CacheCFG_cmp  (SIE_CacheCFG *p, SIE_CacheCFG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CacheCFG_check(p,pie,pfx,hLOG) CacheCFG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CacheCFG_print(p,    pfx,hLOG) CacheCFG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CacheCFG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TAG_ADDR                                 (4,4)
///     ###
///     * Tag ram address format
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 val                  (RW)
///               %unsigned 2  way                       
///               %unsigned 2  xtile_l                   
///               %unsigned 3  ytile_l                   
///               %unsigned 1  uv                        
///               %%        24         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       8b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TAG_ADDR
#define h_TAG_ADDR (){}

    #define     RA_TAG_ADDR_val                                0x0000

    #define     BA_TAG_ADDR_val_way                            0x0000
    #define     B16TAG_ADDR_val_way                            0x0000
    #define   LSb32TAG_ADDR_val_way                               0
    #define   LSb16TAG_ADDR_val_way                               0
    #define       bTAG_ADDR_val_way                            2
    #define   MSK32TAG_ADDR_val_way                               0x00000003

    #define     BA_TAG_ADDR_val_xtile_l                        0x0000
    #define     B16TAG_ADDR_val_xtile_l                        0x0000
    #define   LSb32TAG_ADDR_val_xtile_l                           2
    #define   LSb16TAG_ADDR_val_xtile_l                           2
    #define       bTAG_ADDR_val_xtile_l                        2
    #define   MSK32TAG_ADDR_val_xtile_l                           0x0000000C

    #define     BA_TAG_ADDR_val_ytile_l                        0x0000
    #define     B16TAG_ADDR_val_ytile_l                        0x0000
    #define   LSb32TAG_ADDR_val_ytile_l                           4
    #define   LSb16TAG_ADDR_val_ytile_l                           4
    #define       bTAG_ADDR_val_ytile_l                        3
    #define   MSK32TAG_ADDR_val_ytile_l                           0x00000070

    #define     BA_TAG_ADDR_val_uv                             0x0000
    #define     B16TAG_ADDR_val_uv                             0x0000
    #define   LSb32TAG_ADDR_val_uv                                7
    #define   LSb16TAG_ADDR_val_uv                                7
    #define       bTAG_ADDR_val_uv                             1
    #define   MSK32TAG_ADDR_val_uv                                0x00000080
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TAG_ADDR {
    ///////////////////////////////////////////////////////////
    #define   GET32TAG_ADDR_val_way(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32TAG_ADDR_val_way(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16TAG_ADDR_val_way(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16TAG_ADDR_val_way(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32TAG_ADDR_val_xtile_l(r32)                   _BFGET_(r32, 3, 2)
    #define   SET32TAG_ADDR_val_xtile_l(r32,v)                 _BFSET_(r32, 3, 2,v)
    #define   GET16TAG_ADDR_val_xtile_l(r16)                   _BFGET_(r16, 3, 2)
    #define   SET16TAG_ADDR_val_xtile_l(r16,v)                 _BFSET_(r16, 3, 2,v)

    #define   GET32TAG_ADDR_val_ytile_l(r32)                   _BFGET_(r32, 6, 4)
    #define   SET32TAG_ADDR_val_ytile_l(r32,v)                 _BFSET_(r32, 6, 4,v)
    #define   GET16TAG_ADDR_val_ytile_l(r16)                   _BFGET_(r16, 6, 4)
    #define   SET16TAG_ADDR_val_ytile_l(r16,v)                 _BFSET_(r16, 6, 4,v)

    #define   GET32TAG_ADDR_val_uv(r32)                        _BFGET_(r32, 7, 7)
    #define   SET32TAG_ADDR_val_uv(r32,v)                      _BFSET_(r32, 7, 7,v)
    #define   GET16TAG_ADDR_val_uv(r16)                        _BFGET_(r16, 7, 7)
    #define   SET16TAG_ADDR_val_uv(r16,v)                      _BFSET_(r16, 7, 7,v)

    #define     w32TAG_ADDR_val                                {\
            UNSG32 uval_way                                    :  2;\
            UNSG32 uval_xtile_l                                :  2;\
            UNSG32 uval_ytile_l                                :  3;\
            UNSG32 uval_uv                                     :  1;\
            UNSG32 RSVDx0_b8                                   : 24;\
          }
    union { UNSG32 u32TAG_ADDR_val;
            struct w32TAG_ADDR_val;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TAG_ADDR;

    typedef union  T32TAG_ADDR_val
          { UNSG32 u32;
            struct w32TAG_ADDR_val;
                 } T32TAG_ADDR_val;
    ///////////////////////////////////////////////////////////

    typedef union  TTAG_ADDR_val
          { UNSG32 u32[1];
            struct {
            struct w32TAG_ADDR_val;
                   };
                 } TTAG_ADDR_val;

    ///////////////////////////////////////////////////////////
     SIGN32 TAG_ADDR_drvrd(SIE_TAG_ADDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TAG_ADDR_drvwr(SIE_TAG_ADDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TAG_ADDR_reset(SIE_TAG_ADDR *p);
     SIGN32 TAG_ADDR_cmp  (SIE_TAG_ADDR *p, SIE_TAG_ADDR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TAG_ADDR_check(p,pie,pfx,hLOG) TAG_ADDR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TAG_ADDR_print(p,    pfx,hLOG) TAG_ADDR_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TAG_ADDR
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TILE_CMD                                 (4,4)
///     ###
///     * TileCmdQ format
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 entry                (RW)
///               %unsigned 2  way                       
///               %unsigned 2  xtile_l                   
///               %unsigned 3  ytile_l                   
///               %unsigned 1  uv                        
///               %unsigned 1  xtile_h                   
///               %unsigned 3  ytile_h                   
///               %unsigned 1  cache_hit                 
///               %unsigned 1  out_region                
///                                    ###
///                                    * Extra tile padding for DRAM burst alignment
///                                    ###
///               %unsigned 1  last_cmd                  
///               %%        17         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      15b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TILE_CMD
#define h_TILE_CMD (){}

    #define     RA_TILE_CMD_entry                              0x0000

    #define     BA_TILE_CMD_entry_way                          0x0000
    #define     B16TILE_CMD_entry_way                          0x0000
    #define   LSb32TILE_CMD_entry_way                             0
    #define   LSb16TILE_CMD_entry_way                             0
    #define       bTILE_CMD_entry_way                          2
    #define   MSK32TILE_CMD_entry_way                             0x00000003

    #define     BA_TILE_CMD_entry_xtile_l                      0x0000
    #define     B16TILE_CMD_entry_xtile_l                      0x0000
    #define   LSb32TILE_CMD_entry_xtile_l                         2
    #define   LSb16TILE_CMD_entry_xtile_l                         2
    #define       bTILE_CMD_entry_xtile_l                      2
    #define   MSK32TILE_CMD_entry_xtile_l                         0x0000000C

    #define     BA_TILE_CMD_entry_ytile_l                      0x0000
    #define     B16TILE_CMD_entry_ytile_l                      0x0000
    #define   LSb32TILE_CMD_entry_ytile_l                         4
    #define   LSb16TILE_CMD_entry_ytile_l                         4
    #define       bTILE_CMD_entry_ytile_l                      3
    #define   MSK32TILE_CMD_entry_ytile_l                         0x00000070

    #define     BA_TILE_CMD_entry_uv                           0x0000
    #define     B16TILE_CMD_entry_uv                           0x0000
    #define   LSb32TILE_CMD_entry_uv                              7
    #define   LSb16TILE_CMD_entry_uv                              7
    #define       bTILE_CMD_entry_uv                           1
    #define   MSK32TILE_CMD_entry_uv                              0x00000080

    #define     BA_TILE_CMD_entry_xtile_h                      0x0001
    #define     B16TILE_CMD_entry_xtile_h                      0x0000
    #define   LSb32TILE_CMD_entry_xtile_h                         8
    #define   LSb16TILE_CMD_entry_xtile_h                         8
    #define       bTILE_CMD_entry_xtile_h                      1
    #define   MSK32TILE_CMD_entry_xtile_h                         0x00000100

    #define     BA_TILE_CMD_entry_ytile_h                      0x0001
    #define     B16TILE_CMD_entry_ytile_h                      0x0000
    #define   LSb32TILE_CMD_entry_ytile_h                         9
    #define   LSb16TILE_CMD_entry_ytile_h                         9
    #define       bTILE_CMD_entry_ytile_h                      3
    #define   MSK32TILE_CMD_entry_ytile_h                         0x00000E00

    #define     BA_TILE_CMD_entry_cache_hit                    0x0001
    #define     B16TILE_CMD_entry_cache_hit                    0x0000
    #define   LSb32TILE_CMD_entry_cache_hit                       12
    #define   LSb16TILE_CMD_entry_cache_hit                       12
    #define       bTILE_CMD_entry_cache_hit                    1
    #define   MSK32TILE_CMD_entry_cache_hit                       0x00001000

    #define     BA_TILE_CMD_entry_out_region                   0x0001
    #define     B16TILE_CMD_entry_out_region                   0x0000
    #define   LSb32TILE_CMD_entry_out_region                      13
    #define   LSb16TILE_CMD_entry_out_region                      13
    #define       bTILE_CMD_entry_out_region                   1
    #define   MSK32TILE_CMD_entry_out_region                      0x00002000

    #define     BA_TILE_CMD_entry_last_cmd                     0x0001
    #define     B16TILE_CMD_entry_last_cmd                     0x0000
    #define   LSb32TILE_CMD_entry_last_cmd                        14
    #define   LSb16TILE_CMD_entry_last_cmd                        14
    #define       bTILE_CMD_entry_last_cmd                     1
    #define   MSK32TILE_CMD_entry_last_cmd                        0x00004000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TILE_CMD {
    ///////////////////////////////////////////////////////////
    #define   GET32TILE_CMD_entry_way(r32)                     _BFGET_(r32, 1, 0)
    #define   SET32TILE_CMD_entry_way(r32,v)                   _BFSET_(r32, 1, 0,v)
    #define   GET16TILE_CMD_entry_way(r16)                     _BFGET_(r16, 1, 0)
    #define   SET16TILE_CMD_entry_way(r16,v)                   _BFSET_(r16, 1, 0,v)

    #define   GET32TILE_CMD_entry_xtile_l(r32)                 _BFGET_(r32, 3, 2)
    #define   SET32TILE_CMD_entry_xtile_l(r32,v)               _BFSET_(r32, 3, 2,v)
    #define   GET16TILE_CMD_entry_xtile_l(r16)                 _BFGET_(r16, 3, 2)
    #define   SET16TILE_CMD_entry_xtile_l(r16,v)               _BFSET_(r16, 3, 2,v)

    #define   GET32TILE_CMD_entry_ytile_l(r32)                 _BFGET_(r32, 6, 4)
    #define   SET32TILE_CMD_entry_ytile_l(r32,v)               _BFSET_(r32, 6, 4,v)
    #define   GET16TILE_CMD_entry_ytile_l(r16)                 _BFGET_(r16, 6, 4)
    #define   SET16TILE_CMD_entry_ytile_l(r16,v)               _BFSET_(r16, 6, 4,v)

    #define   GET32TILE_CMD_entry_uv(r32)                      _BFGET_(r32, 7, 7)
    #define   SET32TILE_CMD_entry_uv(r32,v)                    _BFSET_(r32, 7, 7,v)
    #define   GET16TILE_CMD_entry_uv(r16)                      _BFGET_(r16, 7, 7)
    #define   SET16TILE_CMD_entry_uv(r16,v)                    _BFSET_(r16, 7, 7,v)

    #define   GET32TILE_CMD_entry_xtile_h(r32)                 _BFGET_(r32, 8, 8)
    #define   SET32TILE_CMD_entry_xtile_h(r32,v)               _BFSET_(r32, 8, 8,v)
    #define   GET16TILE_CMD_entry_xtile_h(r16)                 _BFGET_(r16, 8, 8)
    #define   SET16TILE_CMD_entry_xtile_h(r16,v)               _BFSET_(r16, 8, 8,v)

    #define   GET32TILE_CMD_entry_ytile_h(r32)                 _BFGET_(r32,11, 9)
    #define   SET32TILE_CMD_entry_ytile_h(r32,v)               _BFSET_(r32,11, 9,v)
    #define   GET16TILE_CMD_entry_ytile_h(r16)                 _BFGET_(r16,11, 9)
    #define   SET16TILE_CMD_entry_ytile_h(r16,v)               _BFSET_(r16,11, 9,v)

    #define   GET32TILE_CMD_entry_cache_hit(r32)               _BFGET_(r32,12,12)
    #define   SET32TILE_CMD_entry_cache_hit(r32,v)             _BFSET_(r32,12,12,v)
    #define   GET16TILE_CMD_entry_cache_hit(r16)               _BFGET_(r16,12,12)
    #define   SET16TILE_CMD_entry_cache_hit(r16,v)             _BFSET_(r16,12,12,v)

    #define   GET32TILE_CMD_entry_out_region(r32)              _BFGET_(r32,13,13)
    #define   SET32TILE_CMD_entry_out_region(r32,v)            _BFSET_(r32,13,13,v)
    #define   GET16TILE_CMD_entry_out_region(r16)              _BFGET_(r16,13,13)
    #define   SET16TILE_CMD_entry_out_region(r16,v)            _BFSET_(r16,13,13,v)

    #define   GET32TILE_CMD_entry_last_cmd(r32)                _BFGET_(r32,14,14)
    #define   SET32TILE_CMD_entry_last_cmd(r32,v)              _BFSET_(r32,14,14,v)
    #define   GET16TILE_CMD_entry_last_cmd(r16)                _BFGET_(r16,14,14)
    #define   SET16TILE_CMD_entry_last_cmd(r16,v)              _BFSET_(r16,14,14,v)

    #define     w32TILE_CMD_entry                              {\
            UNSG32 uentry_way                                  :  2;\
            UNSG32 uentry_xtile_l                              :  2;\
            UNSG32 uentry_ytile_l                              :  3;\
            UNSG32 uentry_uv                                   :  1;\
            UNSG32 uentry_xtile_h                              :  1;\
            UNSG32 uentry_ytile_h                              :  3;\
            UNSG32 uentry_cache_hit                            :  1;\
            UNSG32 uentry_out_region                           :  1;\
            UNSG32 uentry_last_cmd                             :  1;\
            UNSG32 RSVDx0_b15                                  : 17;\
          }
    union { UNSG32 u32TILE_CMD_entry;
            struct w32TILE_CMD_entry;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TILE_CMD;

    typedef union  T32TILE_CMD_entry
          { UNSG32 u32;
            struct w32TILE_CMD_entry;
                 } T32TILE_CMD_entry;
    ///////////////////////////////////////////////////////////

    typedef union  TTILE_CMD_entry
          { UNSG32 u32[1];
            struct {
            struct w32TILE_CMD_entry;
                   };
                 } TTILE_CMD_entry;

    ///////////////////////////////////////////////////////////
     SIGN32 TILE_CMD_drvrd(SIE_TILE_CMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TILE_CMD_drvwr(SIE_TILE_CMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TILE_CMD_reset(SIE_TILE_CMD *p);
     SIGN32 TILE_CMD_cmp  (SIE_TILE_CMD *p, SIE_TILE_CMD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TILE_CMD_check(p,pie,pfx,hLOG) TILE_CMD_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TILE_CMD_print(p,    pfx,hLOG) TILE_CMD_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TILE_CMD
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TAG                                      (4,4)
///     ###
///     * TAG sram entry, 20-bit wide with msb as dirty bit, support pict size up to 4Kx4K
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 entry                (RW)
///               %unsigned 7  xtile                     0x0
///               %unsigned 7  ytile                     0x0
///               %unsigned 5  rbid                      0x0
///               %unsigned 1  valid                     0x0
///               %%        12         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      20b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TAG
#define h_TAG (){}

    #define     RA_TAG_entry                                   0x0000

    #define     BA_TAG_entry_xtile                             0x0000
    #define     B16TAG_entry_xtile                             0x0000
    #define   LSb32TAG_entry_xtile                                0
    #define   LSb16TAG_entry_xtile                                0
    #define       bTAG_entry_xtile                             7
    #define   MSK32TAG_entry_xtile                                0x0000007F

    #define     BA_TAG_entry_ytile                             0x0000
    #define     B16TAG_entry_ytile                             0x0000
    #define   LSb32TAG_entry_ytile                                7
    #define   LSb16TAG_entry_ytile                                7
    #define       bTAG_entry_ytile                             7
    #define   MSK32TAG_entry_ytile                                0x00003F80

    #define     BA_TAG_entry_rbid                              0x0001
    #define     B16TAG_entry_rbid                              0x0000
    #define   LSb32TAG_entry_rbid                                 14
    #define   LSb16TAG_entry_rbid                                 14
    #define       bTAG_entry_rbid                              5
    #define   MSK32TAG_entry_rbid                                 0x0007C000

    #define     BA_TAG_entry_valid                             0x0002
    #define     B16TAG_entry_valid                             0x0002
    #define   LSb32TAG_entry_valid                                19
    #define   LSb16TAG_entry_valid                                3
    #define       bTAG_entry_valid                             1
    #define   MSK32TAG_entry_valid                                0x00080000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TAG {
    ///////////////////////////////////////////////////////////
    #define   GET32TAG_entry_xtile(r32)                        _BFGET_(r32, 6, 0)
    #define   SET32TAG_entry_xtile(r32,v)                      _BFSET_(r32, 6, 0,v)
    #define   GET16TAG_entry_xtile(r16)                        _BFGET_(r16, 6, 0)
    #define   SET16TAG_entry_xtile(r16,v)                      _BFSET_(r16, 6, 0,v)

    #define   GET32TAG_entry_ytile(r32)                        _BFGET_(r32,13, 7)
    #define   SET32TAG_entry_ytile(r32,v)                      _BFSET_(r32,13, 7,v)
    #define   GET16TAG_entry_ytile(r16)                        _BFGET_(r16,13, 7)
    #define   SET16TAG_entry_ytile(r16,v)                      _BFSET_(r16,13, 7,v)

    #define   GET32TAG_entry_rbid(r32)                         _BFGET_(r32,18,14)
    #define   SET32TAG_entry_rbid(r32,v)                       _BFSET_(r32,18,14,v)

    #define   GET32TAG_entry_valid(r32)                        _BFGET_(r32,19,19)
    #define   SET32TAG_entry_valid(r32,v)                      _BFSET_(r32,19,19,v)
    #define   GET16TAG_entry_valid(r16)                        _BFGET_(r16, 3, 3)
    #define   SET16TAG_entry_valid(r16,v)                      _BFSET_(r16, 3, 3,v)

    #define     w32TAG_entry                                   {\
            UNSG32 uentry_xtile                                :  7;\
            UNSG32 uentry_ytile                                :  7;\
            UNSG32 uentry_rbid                                 :  5;\
            UNSG32 uentry_valid                                :  1;\
            UNSG32 RSVDx0_b20                                  : 12;\
          }
    union { UNSG32 u32TAG_entry;
            struct w32TAG_entry;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TAG;

    typedef union  T32TAG_entry
          { UNSG32 u32;
            struct w32TAG_entry;
                 } T32TAG_entry;
    ///////////////////////////////////////////////////////////

    typedef union  TTAG_entry
          { UNSG32 u32[1];
            struct {
            struct w32TAG_entry;
                   };
                 } TTAG_entry;

    ///////////////////////////////////////////////////////////
     SIGN32 TAG_drvrd(SIE_TAG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TAG_drvwr(SIE_TAG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TAG_reset(SIE_TAG *p);
     SIGN32 TAG_cmp  (SIE_TAG *p, SIE_TAG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TAG_check(p,pie,pfx,hLOG) TAG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TAG_print(p,    pfx,hLOG) TAG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TAG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TAG_SRAM                                 (4,4)
///     ###
///     * TAG sram array
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 word                 
///               $TAG                 word              REG     [192]
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     768B, bits:    3840b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TAG_SRAM
#define h_TAG_SRAM (){}

    #define     RA_TAG_SRAM_word                               0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TAG_SRAM {
    ///////////////////////////////////////////////////////////
              SIE_TAG                                          ie_word[192];
    ///////////////////////////////////////////////////////////
    } SIE_TAG_SRAM;

    ///////////////////////////////////////////////////////////
     SIGN32 TAG_SRAM_drvrd(SIE_TAG_SRAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TAG_SRAM_drvwr(SIE_TAG_SRAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TAG_SRAM_reset(SIE_TAG_SRAM *p);
     SIGN32 TAG_SRAM_cmp  (SIE_TAG_SRAM *p, SIE_TAG_SRAM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TAG_SRAM_check(p,pie,pfx,hLOG) TAG_SRAM_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TAG_SRAM_print(p,    pfx,hLOG) TAG_SRAM_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TAG_SRAM
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TRANS_DESC                               (4,4)
///     ###
///     * Transfer Descriptor Format Definition
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 entry                (P)
///               %unsigned 4  stride                    0x0
///                                    ###
///                                    * Address stride of the output refB; 4x4 block based
///                                    ###
///               %unsigned 1  sem_chk                   0x0
///                                    ###
///                                    * 0: bypass semaphore check; 1: semaphore check needed
///                                    ###
///               %unsigned 1  sem_upd                   0x0
///                                    ###
///                                    * 0: bypass semaphore update; 1: semaphore update needed
///                                    ###
///               %unsigned 16 addr                      0x0
///                                    ###
///                                    * Address offset of the output refB; 4x4 block based,
///                                    * supporting up to 2K of 128-bit words
///                                    ###
///               %unsigned 6  sem_id                    0x13
///                                    ###
///                                    * Semaphore ID for the specified semaphore operation
///                                    * So far only used for encoder
///                                    ###
///               %%        4          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      28b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TRANS_DESC
#define h_TRANS_DESC (){}

    #define     RA_TRANS_DESC_entry                            0x0000

    #define     BA_TRANS_DESC_entry_stride                     0x0000
    #define     B16TRANS_DESC_entry_stride                     0x0000
    #define   LSb32TRANS_DESC_entry_stride                        0
    #define   LSb16TRANS_DESC_entry_stride                        0
    #define       bTRANS_DESC_entry_stride                     4
    #define   MSK32TRANS_DESC_entry_stride                        0x0000000F

    #define     BA_TRANS_DESC_entry_sem_chk                    0x0000
    #define     B16TRANS_DESC_entry_sem_chk                    0x0000
    #define   LSb32TRANS_DESC_entry_sem_chk                       4
    #define   LSb16TRANS_DESC_entry_sem_chk                       4
    #define       bTRANS_DESC_entry_sem_chk                    1
    #define   MSK32TRANS_DESC_entry_sem_chk                       0x00000010

    #define     BA_TRANS_DESC_entry_sem_upd                    0x0000
    #define     B16TRANS_DESC_entry_sem_upd                    0x0000
    #define   LSb32TRANS_DESC_entry_sem_upd                       5
    #define   LSb16TRANS_DESC_entry_sem_upd                       5
    #define       bTRANS_DESC_entry_sem_upd                    1
    #define   MSK32TRANS_DESC_entry_sem_upd                       0x00000020

    #define     BA_TRANS_DESC_entry_addr                       0x0000
    #define     B16TRANS_DESC_entry_addr                       0x0000
    #define   LSb32TRANS_DESC_entry_addr                          6
    #define   LSb16TRANS_DESC_entry_addr                          6
    #define       bTRANS_DESC_entry_addr                       16
    #define   MSK32TRANS_DESC_entry_addr                          0x003FFFC0

    #define     BA_TRANS_DESC_entry_sem_id                     0x0002
    #define     B16TRANS_DESC_entry_sem_id                     0x0002
    #define   LSb32TRANS_DESC_entry_sem_id                        22
    #define   LSb16TRANS_DESC_entry_sem_id                        6
    #define       bTRANS_DESC_entry_sem_id                     6
    #define   MSK32TRANS_DESC_entry_sem_id                        0x0FC00000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TRANS_DESC {
    ///////////////////////////////////////////////////////////
    #define   GET32TRANS_DESC_entry_stride(r32)                _BFGET_(r32, 3, 0)
    #define   SET32TRANS_DESC_entry_stride(r32,v)              _BFSET_(r32, 3, 0,v)
    #define   GET16TRANS_DESC_entry_stride(r16)                _BFGET_(r16, 3, 0)
    #define   SET16TRANS_DESC_entry_stride(r16,v)              _BFSET_(r16, 3, 0,v)

    #define   GET32TRANS_DESC_entry_sem_chk(r32)               _BFGET_(r32, 4, 4)
    #define   SET32TRANS_DESC_entry_sem_chk(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16TRANS_DESC_entry_sem_chk(r16)               _BFGET_(r16, 4, 4)
    #define   SET16TRANS_DESC_entry_sem_chk(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32TRANS_DESC_entry_sem_upd(r32)               _BFGET_(r32, 5, 5)
    #define   SET32TRANS_DESC_entry_sem_upd(r32,v)             _BFSET_(r32, 5, 5,v)
    #define   GET16TRANS_DESC_entry_sem_upd(r16)               _BFGET_(r16, 5, 5)
    #define   SET16TRANS_DESC_entry_sem_upd(r16,v)             _BFSET_(r16, 5, 5,v)

    #define   GET32TRANS_DESC_entry_addr(r32)                  _BFGET_(r32,21, 6)
    #define   SET32TRANS_DESC_entry_addr(r32,v)                _BFSET_(r32,21, 6,v)

    #define   GET32TRANS_DESC_entry_sem_id(r32)                _BFGET_(r32,27,22)
    #define   SET32TRANS_DESC_entry_sem_id(r32,v)              _BFSET_(r32,27,22,v)
    #define   GET16TRANS_DESC_entry_sem_id(r16)                _BFGET_(r16,11, 6)
    #define   SET16TRANS_DESC_entry_sem_id(r16,v)              _BFSET_(r16,11, 6,v)

    #define     w32TRANS_DESC_entry                            {\
            UNSG32 uentry_stride                               :  4;\
            UNSG32 uentry_sem_chk                              :  1;\
            UNSG32 uentry_sem_upd                              :  1;\
            UNSG32 uentry_addr                                 : 16;\
            UNSG32 uentry_sem_id                               :  6;\
            UNSG32 RSVDx0_b28                                  :  4;\
          }
    union { UNSG32 u32TRANS_DESC_entry;
            struct w32TRANS_DESC_entry;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TRANS_DESC;

    typedef union  T32TRANS_DESC_entry
          { UNSG32 u32;
            struct w32TRANS_DESC_entry;
                 } T32TRANS_DESC_entry;
    ///////////////////////////////////////////////////////////

    typedef union  TTRANS_DESC_entry
          { UNSG32 u32[1];
            struct {
            struct w32TRANS_DESC_entry;
                   };
                 } TTRANS_DESC_entry;

    ///////////////////////////////////////////////////////////
     SIGN32 TRANS_DESC_drvrd(SIE_TRANS_DESC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TRANS_DESC_drvwr(SIE_TRANS_DESC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TRANS_DESC_reset(SIE_TRANS_DESC *p);
     SIGN32 TRANS_DESC_cmp  (SIE_TRANS_DESC *p, SIE_TRANS_DESC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TRANS_DESC_check(p,pie,pfx,hLOG) TRANS_DESC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TRANS_DESC_print(p,    pfx,hLOG) TRANS_DESC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TRANS_DESC
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE FRAME_DESC              biu              (4,4)
///     ###
///     * Reference frame descriptor format definition
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 entry                (P)
///               %unsigned 2  fid                       0x0
///                                    ###
///                                    * 0/1: cache-able; fid[0] to be used for way calculation
///                                    * 2: frame not cache-able
///                                    ###
///               %unsigned 1  intlRef                   0x0
///                                    ###
///                                    * 0: reference picture is progressive;
///                                    * 1: reference picture is interlaced
///                                    ###
///               %unsigned 1  weavedRef                 0x0
///                                    ###
///                                    * 0: raster scan reference picture
///                                    * 1: weaved reference picture
///                                    ###
///               %unsigned 1  rangeRed                  0x0
///                                    ###
///                                    * VC-1 range reduction setting for this reference picture
///                                    ###
///               %unsigned 5  rsvd                      0x0
///                                    ###
///                                    * Reserved for future use
///                                    ###
///               %unsigned 22 addr                      0x0
///                                    ###
///                                    * bits [31:10] of frame buffer base address.
///                                    * Note that bit [11:10] should be 0. (Frame buffer base address should be aligned to 4K bytes.)
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      32b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_FRAME_DESC
#define h_FRAME_DESC (){}

    #define     RA_FRAME_DESC_entry                            0x0000

    #define     BA_FRAME_DESC_entry_fid                        0x0000
    #define     B16FRAME_DESC_entry_fid                        0x0000
    #define   LSb32FRAME_DESC_entry_fid                           0
    #define   LSb16FRAME_DESC_entry_fid                           0
    #define       bFRAME_DESC_entry_fid                        2
    #define   MSK32FRAME_DESC_entry_fid                           0x00000003

    #define     BA_FRAME_DESC_entry_intlRef                    0x0000
    #define     B16FRAME_DESC_entry_intlRef                    0x0000
    #define   LSb32FRAME_DESC_entry_intlRef                       2
    #define   LSb16FRAME_DESC_entry_intlRef                       2
    #define       bFRAME_DESC_entry_intlRef                    1
    #define   MSK32FRAME_DESC_entry_intlRef                       0x00000004

    #define     BA_FRAME_DESC_entry_weavedRef                  0x0000
    #define     B16FRAME_DESC_entry_weavedRef                  0x0000
    #define   LSb32FRAME_DESC_entry_weavedRef                     3
    #define   LSb16FRAME_DESC_entry_weavedRef                     3
    #define       bFRAME_DESC_entry_weavedRef                  1
    #define   MSK32FRAME_DESC_entry_weavedRef                     0x00000008

    #define     BA_FRAME_DESC_entry_rangeRed                   0x0000
    #define     B16FRAME_DESC_entry_rangeRed                   0x0000
    #define   LSb32FRAME_DESC_entry_rangeRed                      4
    #define   LSb16FRAME_DESC_entry_rangeRed                      4
    #define       bFRAME_DESC_entry_rangeRed                   1
    #define   MSK32FRAME_DESC_entry_rangeRed                      0x00000010

    #define     BA_FRAME_DESC_entry_rsvd                       0x0000
    #define     B16FRAME_DESC_entry_rsvd                       0x0000
    #define   LSb32FRAME_DESC_entry_rsvd                          5
    #define   LSb16FRAME_DESC_entry_rsvd                          5
    #define       bFRAME_DESC_entry_rsvd                       5
    #define   MSK32FRAME_DESC_entry_rsvd                          0x000003E0

    #define     BA_FRAME_DESC_entry_addr                       0x0001
    #define     B16FRAME_DESC_entry_addr                       0x0000
    #define   LSb32FRAME_DESC_entry_addr                          10
    #define   LSb16FRAME_DESC_entry_addr                          10
    #define       bFRAME_DESC_entry_addr                       22
    #define   MSK32FRAME_DESC_entry_addr                          0xFFFFFC00
    ///////////////////////////////////////////////////////////

    typedef struct SIE_FRAME_DESC {
    ///////////////////////////////////////////////////////////
    #define   GET32FRAME_DESC_entry_fid(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32FRAME_DESC_entry_fid(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16FRAME_DESC_entry_fid(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16FRAME_DESC_entry_fid(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32FRAME_DESC_entry_intlRef(r32)               _BFGET_(r32, 2, 2)
    #define   SET32FRAME_DESC_entry_intlRef(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16FRAME_DESC_entry_intlRef(r16)               _BFGET_(r16, 2, 2)
    #define   SET16FRAME_DESC_entry_intlRef(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32FRAME_DESC_entry_weavedRef(r32)             _BFGET_(r32, 3, 3)
    #define   SET32FRAME_DESC_entry_weavedRef(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16FRAME_DESC_entry_weavedRef(r16)             _BFGET_(r16, 3, 3)
    #define   SET16FRAME_DESC_entry_weavedRef(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32FRAME_DESC_entry_rangeRed(r32)              _BFGET_(r32, 4, 4)
    #define   SET32FRAME_DESC_entry_rangeRed(r32,v)            _BFSET_(r32, 4, 4,v)
    #define   GET16FRAME_DESC_entry_rangeRed(r16)              _BFGET_(r16, 4, 4)
    #define   SET16FRAME_DESC_entry_rangeRed(r16,v)            _BFSET_(r16, 4, 4,v)

    #define   GET32FRAME_DESC_entry_rsvd(r32)                  _BFGET_(r32, 9, 5)
    #define   SET32FRAME_DESC_entry_rsvd(r32,v)                _BFSET_(r32, 9, 5,v)
    #define   GET16FRAME_DESC_entry_rsvd(r16)                  _BFGET_(r16, 9, 5)
    #define   SET16FRAME_DESC_entry_rsvd(r16,v)                _BFSET_(r16, 9, 5,v)

    #define   GET32FRAME_DESC_entry_addr(r32)                  _BFGET_(r32,31,10)
    #define   SET32FRAME_DESC_entry_addr(r32,v)                _BFSET_(r32,31,10,v)

    #define     w32FRAME_DESC_entry                            {\
            UNSG32 uentry_fid                                  :  2;\
            UNSG32 uentry_intlRef                              :  1;\
            UNSG32 uentry_weavedRef                            :  1;\
            UNSG32 uentry_rangeRed                             :  1;\
            UNSG32 uentry_rsvd                                 :  5;\
            UNSG32 uentry_addr                                 : 22;\
          }
    union { UNSG32 u32FRAME_DESC_entry;
            struct w32FRAME_DESC_entry;
          };
    ///////////////////////////////////////////////////////////
    } SIE_FRAME_DESC;

    typedef union  T32FRAME_DESC_entry
          { UNSG32 u32;
            struct w32FRAME_DESC_entry;
                 } T32FRAME_DESC_entry;
    ///////////////////////////////////////////////////////////

    typedef union  TFRAME_DESC_entry
          { UNSG32 u32[1];
            struct {
            struct w32FRAME_DESC_entry;
                   };
                 } TFRAME_DESC_entry;

    ///////////////////////////////////////////////////////////
     SIGN32 FRAME_DESC_drvrd(SIE_FRAME_DESC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 FRAME_DESC_drvwr(SIE_FRAME_DESC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void FRAME_DESC_reset(SIE_FRAME_DESC *p);
     SIGN32 FRAME_DESC_cmp  (SIE_FRAME_DESC *p, SIE_FRAME_DESC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define FRAME_DESC_check(p,pie,pfx,hLOG) FRAME_DESC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define FRAME_DESC_print(p,    pfx,hLOG) FRAME_DESC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: FRAME_DESC
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE PIX_LUT                                  (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 entry                (RW)
///               %unsigned 6  val                       0x0
///               %%        26         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_PIX_LUT
#define h_PIX_LUT (){}

    #define     RA_PIX_LUT_entry                               0x0000

    #define     BA_PIX_LUT_entry_val                           0x0000
    #define     B16PIX_LUT_entry_val                           0x0000
    #define   LSb32PIX_LUT_entry_val                              0
    #define   LSb16PIX_LUT_entry_val                              0
    #define       bPIX_LUT_entry_val                           6
    #define   MSK32PIX_LUT_entry_val                              0x0000003F
    ///////////////////////////////////////////////////////////

    typedef struct SIE_PIX_LUT {
    ///////////////////////////////////////////////////////////
    #define   GET32PIX_LUT_entry_val(r32)                      _BFGET_(r32, 5, 0)
    #define   SET32PIX_LUT_entry_val(r32,v)                    _BFSET_(r32, 5, 0,v)
    #define   GET16PIX_LUT_entry_val(r16)                      _BFGET_(r16, 5, 0)
    #define   SET16PIX_LUT_entry_val(r16,v)                    _BFSET_(r16, 5, 0,v)

    #define     w32PIX_LUT_entry                               {\
            UNSG32 uentry_val                                  :  6;\
            UNSG32 RSVDx0_b6                                   : 26;\
          }
    union { UNSG32 u32PIX_LUT_entry;
            struct w32PIX_LUT_entry;
          };
    ///////////////////////////////////////////////////////////
    } SIE_PIX_LUT;

    typedef union  T32PIX_LUT_entry
          { UNSG32 u32;
            struct w32PIX_LUT_entry;
                 } T32PIX_LUT_entry;
    ///////////////////////////////////////////////////////////

    typedef union  TPIX_LUT_entry
          { UNSG32 u32[1];
            struct {
            struct w32PIX_LUT_entry;
                   };
                 } TPIX_LUT_entry;

    ///////////////////////////////////////////////////////////
     SIGN32 PIX_LUT_drvrd(SIE_PIX_LUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 PIX_LUT_drvwr(SIE_PIX_LUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void PIX_LUT_reset(SIE_PIX_LUT *p);
     SIGN32 PIX_LUT_cmp  (SIE_PIX_LUT *p, SIE_PIX_LUT *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define PIX_LUT_check(p,pie,pfx,hLOG) PIX_LUT_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define PIX_LUT_print(p,    pfx,hLOG) PIX_LUT_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: PIX_LUT
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE INTEN_PARAM                              (4,4)
///     ###
///     * VC-1 intensity parameters
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 entry                (RW)
///               %unsigned 1  intensityOn               0x0
///               %signed   8  iScale                    0
///               %signed   10 iShift                    0
///               %%        13         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      19b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_INTEN_PARAM
#define h_INTEN_PARAM (){}

    #define     RA_INTEN_PARAM_entry                           0x0000

    #define     BA_INTEN_PARAM_entry_intensityOn               0x0000
    #define     B16INTEN_PARAM_entry_intensityOn               0x0000
    #define   LSb32INTEN_PARAM_entry_intensityOn                  0
    #define   LSb16INTEN_PARAM_entry_intensityOn                  0
    #define       bINTEN_PARAM_entry_intensityOn               1
    #define   MSK32INTEN_PARAM_entry_intensityOn                  0x00000001

    #define     BA_INTEN_PARAM_entry_iScale                    0x0000
    #define     B16INTEN_PARAM_entry_iScale                    0x0000
    #define   LSb32INTEN_PARAM_entry_iScale                       1
    #define   LSb16INTEN_PARAM_entry_iScale                       1
    #define       bINTEN_PARAM_entry_iScale                    8
    #define   MSK32INTEN_PARAM_entry_iScale                       0x000001FE

    #define     BA_INTEN_PARAM_entry_iShift                    0x0001
    #define     B16INTEN_PARAM_entry_iShift                    0x0000
    #define   LSb32INTEN_PARAM_entry_iShift                       9
    #define   LSb16INTEN_PARAM_entry_iShift                       9
    #define       bINTEN_PARAM_entry_iShift                    10
    #define   MSK32INTEN_PARAM_entry_iShift                       0x0007FE00
    ///////////////////////////////////////////////////////////

    typedef struct SIE_INTEN_PARAM {
    ///////////////////////////////////////////////////////////
    #define   GET32INTEN_PARAM_entry_intensityOn(r32)          _BFGET_(r32, 0, 0)
    #define   SET32INTEN_PARAM_entry_intensityOn(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16INTEN_PARAM_entry_intensityOn(r16)          _BFGET_(r16, 0, 0)
    #define   SET16INTEN_PARAM_entry_intensityOn(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32INTEN_PARAM_entry_iScale(r32)               _BFGET_(r32, 8, 1)
    #define   SET32INTEN_PARAM_entry_iScale(r32,v)             _BFSET_(r32, 8, 1,v)
    #define   GET16INTEN_PARAM_entry_iScale(r16)               _BFGET_(r16, 8, 1)
    #define   SET16INTEN_PARAM_entry_iScale(r16,v)             _BFSET_(r16, 8, 1,v)

    #define   GET32INTEN_PARAM_entry_iShift(r32)               _BFGET_(r32,18, 9)
    #define   SET32INTEN_PARAM_entry_iShift(r32,v)             _BFSET_(r32,18, 9,v)

    #define     w32INTEN_PARAM_entry                           {\
            UNSG32 uentry_intensityOn                          :  1;\
            UNSG32 sentry_iScale                               :  8;\
            UNSG32 sentry_iShift                               : 10;\
            UNSG32 RSVDx0_b19                                  : 13;\
          }
    union { UNSG32 u32INTEN_PARAM_entry;
            struct w32INTEN_PARAM_entry;
          };
    ///////////////////////////////////////////////////////////
    } SIE_INTEN_PARAM;

    typedef union  T32INTEN_PARAM_entry
          { UNSG32 u32;
            struct w32INTEN_PARAM_entry;
                 } T32INTEN_PARAM_entry;
    ///////////////////////////////////////////////////////////

    typedef union  TINTEN_PARAM_entry
          { UNSG32 u32[1];
            struct {
            struct w32INTEN_PARAM_entry;
                   };
                 } TINTEN_PARAM_entry;

    ///////////////////////////////////////////////////////////
     SIGN32 INTEN_PARAM_drvrd(SIE_INTEN_PARAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 INTEN_PARAM_drvwr(SIE_INTEN_PARAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void INTEN_PARAM_reset(SIE_INTEN_PARAM *p);
     SIGN32 INTEN_PARAM_cmp  (SIE_INTEN_PARAM *p, SIE_INTEN_PARAM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define INTEN_PARAM_check(p,pie,pfx,hLOG) INTEN_PARAM_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define INTEN_PARAM_print(p,    pfx,hLOG) INTEN_PARAM_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: INTEN_PARAM
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE VC                      biu              (4,4)
///     ###
///     * Register Specification of vCache
///     ###
///     # # ----------------------------------------------------------
///               : TagSramBase        0x0
///                            ###
///                            * TagSram address base
///                            ###
///               : RegBase            0x1000
///                            ###
///                            * vCache register address base
///                            ###
///     @ 0x00000 TAG_SRAM             (P)
///     # 0x00000 tags                 
///               $TAG_SRAM            tags              MEM          
///                                    ###
///                                    * TAG SRAM, array of 192
///                                    ###
///     @ 0x00400                      (W-)
///     #         # Stuffing bytes...
///               %% 24576
///     @ 0x01000 CTRL                 (RW-)
///               ###
///               * vCache flow control
///               ###
///               %unsigned 1  stop                      0x0
///                                    ###
///                                    * Write 1 for vCache to stop message loading and start waiting for internal pipeline to end. Auto clear after vCache becomes idle, when vc_session_done is set to 1
///                                    ###
///               %unsigned 1  auto_resume               0x0
///                                    ###
///                                    * Write 1 to indicate that new session should auto resume after vc_session_done
///                                    ###
///               %unsigned 1  kickoff                   0x0
///                                    ###
///                                    * Write 1 to kickoff a new session (i.e. for vCache to start reading messages); self clear the next cycle. Always reads 0.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x01004 FORMAT               (P)
///               ###
///               * Current picture format
///               ###
///               %unsigned 3  picMode                   0x0
///                                    : h264                      0x0
///                                    : wmv                       0x1
///                                                 ###
///                                                 * VC-1 main profile
///                                                 ###
///                                    : mpg2                      0x2
///                                    : mpg4                      0x4
///                                    : vc1ap                     0x5
///                                                 ###
///                                                 * VC-1 advanced profile
///                                                 ###
///               %unsigned 1  fldPic                    0x0
///                                    : frame                     0x0
///                                                 ###
///                                                 * current picture is frame
///                                                 ###
///                                    : field                     0x1
///                                                 ###
///                                                 * current picture is field
///                                                 ###
///               %unsigned 1  rangeRed                  0x0
///                                    ###
///                                    * Range reduction setting for current picture
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x01008 STATUS               (WOC-)
///               ###
///               * vCache status
///               ###
///               %unsigned 1  session_done              0x0
///                                    ###
///                                    * 0: session ongoing or idle
///                                    * 1: previous session is done
///                                    * sticky until CPU writes 1 to clear
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x0100C CHROMA_OFFSET        (P)
///               ###
///               * Chroma frame buffer address offset from the corresponding luma frame buffer
///               ###
///               %unsigned 32 val                       0x0
///                                    ###
///                                    * Chroma buffer address = frame_luma[*] + chroma_offset
///                                    ###
///     @ 0x01010 PAGE_STRIDE          (P)
///               ###
///               * Address differential from the 1st pixel of a page row to the 1st pixel of the next page row.
///               ###
///               %unsigned 32 stride                    0x0
///     @ 0x01014 FRAME_DESC           (P)
///     # 0x01014 frame                
///               $FRAME_DESC          frame             REG      [17]
///                                    ###
///                                    * Frame buffer descriptors, array of 17
///                                    ###
///     @ 0x01058 TRANS_DESC           (P)
///     # 0x01058 dscp                 
///               $TRANS_DESC          dscp              REG      [63]
///                                    ###
///                                    * Output transfer ID for the OCP connection between vCache and PCube, array of 63
///                                    ###
///     @ 0x01154 XPIX_MAP             (P)
///     # 0x01154 xpix_map             
///               $PIX_LUT             xpix_map          REG      [32]
///     @ 0x011D4 YPIX_MAP             (P)
///     # 0x011D4 ypix_map             
///               $PIX_LUT             ypix_map          REG      [32]
///     @ 0x01254 XLOCEXP_MAP          (P)
///     # 0x01254 xlocexp_map          
///               $PIX_LUT             xlocexp_map       REG      [32]
///     @ 0x012D4 XPIXEXP_MAP          (P)
///     # 0x012D4 xpixexp_map          
///               $PIX_LUT             xpixexp_map       REG       [8]
///     @ 0x012F4 YLOCEXP_MAP          (P)
///     # 0x012F4 ylocexp_map          
///               $PIX_LUT             ylocexp_map       REG      [32]
///     @ 0x01374 YPIXEXP_MAP          (P)
///     # 0x01374 ypixexp_map          
///               $PIX_LUT             ypixexp_map       REG       [8]
///                                    ###
///                                    * Look-up table for vcMsg xpix, ypix, xlocexp, xpixexp, ylocexp, and ypixexp. Note that for UV, only xpixexp and ypixexp are required to go through the look-up table.
///                                    ###
///     @ 0x01394 INT_RBID_MAP         (RW)
///               ###
///               * Map forward and backward VC-1 intensity compensation parameter sets to reference frames with specific rBid.
///               ###
///               %unsigned 5  forward_rbid              0x0
///                                    ###
///                                    * Specify the rBid of forward reference frame. The forward intensity compensation parameter sets are applied to this frame. forward_rbid doesn't have the lsb of rBid that indicate top or bottom field.
///                                    ###
///               %unsigned 5  current_rbid              0x0
///                                    ###
///                                    * Specify the rBid of current frame. The current intensity compensation parameter set is applied to this frame. current_rbid doesn't have the lsb of rBid that indicate top or bottom field.
///                                    ###
///               %unsigned 5  backward_rbid             0x0
///                                    ###
///                                    * Specify the rBid of backward reference frame that backward intensity compensation parameter sets are applied to. backward_rbid doesn't have the lsb of rBid that indicate top or bottom field.
///                                    ###
///               %%        17         # Stuffing bits...
///     @ 0x01398 INT_FORWARD_TOP0     (P)
///     # 0x01398 int_forward_top      
///               $INTEN_PARAM         int_forward_top   REG       [2]
///     @ 0x013A0 INT_FORWARD_BOT0     (P)
///     # 0x013A0 int_forward_bot      
///               $INTEN_PARAM         int_forward_bot   REG       [2]
///     @ 0x013A8 INT_CURRENT          (P)
///     # 0x013A8 int_current          
///               $INTEN_PARAM         int_current       REG          
///     @ 0x013AC INT_BACKWARD_TOP     (P)
///     # 0x013AC int_backward_top     
///               $INTEN_PARAM         int_backward_top  REG          
///     @ 0x013B0 INT_BACKWARD_BOT     (P)
///     # 0x013B0 int_backward_bot     
///               $INTEN_PARAM         int_backward_bot  REG          
///                                    ###
///                                    * Forward and backward VC-1 intensity compensation parameter sets.
///                                    ###
///     @ 0x013B4 REGION_LOC_BASE      (P)
///               ###
///               * xloc/yloc base, multiples of 2K (to support pict size larger than 2K)
///               * e.g. xloc_final = ((xloc_base << 11) + vCmsg_xloc)
///               ###
///               %unsigned 8  luma_xloc_base            0x0
///               %unsigned 8  luma_yloc_base            0x0
///               %unsigned 8  chroma_xloc_base          0x0
///               %unsigned 8  chroma_yloc_base          0x0
///     @ 0x013B8 FETCH_COLLECTION     (P)
///               ###
///               * DRAM data fetch collection control
///               ###
///               %unsigned 16 dram_burst_size           0x20
///                                    ###
///                                    * DRAM burst size in bytes
///                                    ###
///               %unsigned 1  collection_mode           0x0
///                                    : tile_exact                0x0
///                                    : burst_align               0x1
///                                                 ###
///                                                 * Fetch collection mode
///                                                 * end of VC interface
///                                                 ###
///               %%        15         # Stuffing bits...
///     @ 0x013BC                      (W-)
///     #         # Stuffing bytes...
///               %% 544
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    5120B, bits:    3474b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_VC
#define h_VC (){}

    #define        VC_TagSramBase                              0x0
    #define        VC_RegBase                                  0x1000
    ///////////////////////////////////////////////////////////
    #define     RA_VC_TAG_SRAM                                 0x0000
    #define     RA_VC_tags                                     0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_VC_CTRL                                     0x1000

    #define     BA_VC_CTRL_stop                                0x1000
    #define     B16VC_CTRL_stop                                0x1000
    #define   LSb32VC_CTRL_stop                                   0
    #define   LSb16VC_CTRL_stop                                   0
    #define       bVC_CTRL_stop                                1
    #define   MSK32VC_CTRL_stop                                   0x00000001

    #define     BA_VC_CTRL_auto_resume                         0x1000
    #define     B16VC_CTRL_auto_resume                         0x1000
    #define   LSb32VC_CTRL_auto_resume                            1
    #define   LSb16VC_CTRL_auto_resume                            1
    #define       bVC_CTRL_auto_resume                         1
    #define   MSK32VC_CTRL_auto_resume                            0x00000002

    #define     BA_VC_CTRL_kickoff                             0x1000
    #define     B16VC_CTRL_kickoff                             0x1000
    #define   LSb32VC_CTRL_kickoff                                2
    #define   LSb16VC_CTRL_kickoff                                2
    #define       bVC_CTRL_kickoff                             1
    #define   MSK32VC_CTRL_kickoff                                0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_VC_FORMAT                                   0x1004

    #define     BA_VC_FORMAT_picMode                           0x1004
    #define     B16VC_FORMAT_picMode                           0x1004
    #define   LSb32VC_FORMAT_picMode                              0
    #define   LSb16VC_FORMAT_picMode                              0
    #define       bVC_FORMAT_picMode                           3
    #define   MSK32VC_FORMAT_picMode                              0x00000007
    #define        VC_FORMAT_picMode_h264                                   0x0
    #define        VC_FORMAT_picMode_wmv                                    0x1
    #define        VC_FORMAT_picMode_mpg2                                   0x2
    #define        VC_FORMAT_picMode_mpg4                                   0x4
    #define        VC_FORMAT_picMode_vc1ap                                  0x5

    #define     BA_VC_FORMAT_fldPic                            0x1004
    #define     B16VC_FORMAT_fldPic                            0x1004
    #define   LSb32VC_FORMAT_fldPic                               3
    #define   LSb16VC_FORMAT_fldPic                               3
    #define       bVC_FORMAT_fldPic                            1
    #define   MSK32VC_FORMAT_fldPic                               0x00000008
    #define        VC_FORMAT_fldPic_frame                                   0x0
    #define        VC_FORMAT_fldPic_field                                   0x1

    #define     BA_VC_FORMAT_rangeRed                          0x1004
    #define     B16VC_FORMAT_rangeRed                          0x1004
    #define   LSb32VC_FORMAT_rangeRed                             4
    #define   LSb16VC_FORMAT_rangeRed                             4
    #define       bVC_FORMAT_rangeRed                          1
    #define   MSK32VC_FORMAT_rangeRed                             0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_VC_STATUS                                   0x1008

    #define     BA_VC_STATUS_session_done                      0x1008
    #define     B16VC_STATUS_session_done                      0x1008
    #define   LSb32VC_STATUS_session_done                         0
    #define   LSb16VC_STATUS_session_done                         0
    #define       bVC_STATUS_session_done                      1
    #define   MSK32VC_STATUS_session_done                         0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_VC_CHROMA_OFFSET                            0x100C

    #define     BA_VC_CHROMA_OFFSET_val                        0x100C
    #define     B16VC_CHROMA_OFFSET_val                        0x100C
    #define   LSb32VC_CHROMA_OFFSET_val                           0
    #define   LSb16VC_CHROMA_OFFSET_val                           0
    #define       bVC_CHROMA_OFFSET_val                        32
    #define   MSK32VC_CHROMA_OFFSET_val                           0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_VC_PAGE_STRIDE                              0x1010

    #define     BA_VC_PAGE_STRIDE_stride                       0x1010
    #define     B16VC_PAGE_STRIDE_stride                       0x1010
    #define   LSb32VC_PAGE_STRIDE_stride                          0
    #define   LSb16VC_PAGE_STRIDE_stride                          0
    #define       bVC_PAGE_STRIDE_stride                       32
    #define   MSK32VC_PAGE_STRIDE_stride                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_VC_FRAME_DESC                               0x1014
    #define     RA_VC_frame                                    0x1014
    ///////////////////////////////////////////////////////////
    #define     RA_VC_TRANS_DESC                               0x1058
    #define     RA_VC_dscp                                     0x1058
    ///////////////////////////////////////////////////////////
    #define     RA_VC_XPIX_MAP                                 0x1154
    #define     RA_VC_xpix_map                                 0x1154
    ///////////////////////////////////////////////////////////
    #define     RA_VC_YPIX_MAP                                 0x11D4
    #define     RA_VC_ypix_map                                 0x11D4
    ///////////////////////////////////////////////////////////
    #define     RA_VC_XLOCEXP_MAP                              0x1254
    #define     RA_VC_xlocexp_map                              0x1254
    ///////////////////////////////////////////////////////////
    #define     RA_VC_XPIXEXP_MAP                              0x12D4
    #define     RA_VC_xpixexp_map                              0x12D4
    ///////////////////////////////////////////////////////////
    #define     RA_VC_YLOCEXP_MAP                              0x12F4
    #define     RA_VC_ylocexp_map                              0x12F4
    ///////////////////////////////////////////////////////////
    #define     RA_VC_YPIXEXP_MAP                              0x1374
    #define     RA_VC_ypixexp_map                              0x1374
    ///////////////////////////////////////////////////////////
    #define     RA_VC_INT_RBID_MAP                             0x1394

    #define     BA_VC_INT_RBID_MAP_forward_rbid                0x1394
    #define     B16VC_INT_RBID_MAP_forward_rbid                0x1394
    #define   LSb32VC_INT_RBID_MAP_forward_rbid                   0
    #define   LSb16VC_INT_RBID_MAP_forward_rbid                   0
    #define       bVC_INT_RBID_MAP_forward_rbid                5
    #define   MSK32VC_INT_RBID_MAP_forward_rbid                   0x0000001F

    #define     BA_VC_INT_RBID_MAP_current_rbid                0x1394
    #define     B16VC_INT_RBID_MAP_current_rbid                0x1394
    #define   LSb32VC_INT_RBID_MAP_current_rbid                   5
    #define   LSb16VC_INT_RBID_MAP_current_rbid                   5
    #define       bVC_INT_RBID_MAP_current_rbid                5
    #define   MSK32VC_INT_RBID_MAP_current_rbid                   0x000003E0

    #define     BA_VC_INT_RBID_MAP_backward_rbid               0x1395
    #define     B16VC_INT_RBID_MAP_backward_rbid               0x1394
    #define   LSb32VC_INT_RBID_MAP_backward_rbid                  10
    #define   LSb16VC_INT_RBID_MAP_backward_rbid                  10
    #define       bVC_INT_RBID_MAP_backward_rbid               5
    #define   MSK32VC_INT_RBID_MAP_backward_rbid                  0x00007C00
    ///////////////////////////////////////////////////////////
    #define     RA_VC_INT_FORWARD_TOP0                         0x1398
    #define     RA_VC_int_forward_top                          0x1398
    ///////////////////////////////////////////////////////////
    #define     RA_VC_INT_FORWARD_BOT0                         0x13A0
    #define     RA_VC_int_forward_bot                          0x13A0
    ///////////////////////////////////////////////////////////
    #define     RA_VC_INT_CURRENT                              0x13A8
    #define     RA_VC_int_current                              0x13A8
    ///////////////////////////////////////////////////////////
    #define     RA_VC_INT_BACKWARD_TOP                         0x13AC
    #define     RA_VC_int_backward_top                         0x13AC
    ///////////////////////////////////////////////////////////
    #define     RA_VC_INT_BACKWARD_BOT                         0x13B0
    #define     RA_VC_int_backward_bot                         0x13B0
    ///////////////////////////////////////////////////////////
    #define     RA_VC_REGION_LOC_BASE                          0x13B4

    #define     BA_VC_REGION_LOC_BASE_luma_xloc_base           0x13B4
    #define     B16VC_REGION_LOC_BASE_luma_xloc_base           0x13B4
    #define   LSb32VC_REGION_LOC_BASE_luma_xloc_base              0
    #define   LSb16VC_REGION_LOC_BASE_luma_xloc_base              0
    #define       bVC_REGION_LOC_BASE_luma_xloc_base           8
    #define   MSK32VC_REGION_LOC_BASE_luma_xloc_base              0x000000FF

    #define     BA_VC_REGION_LOC_BASE_luma_yloc_base           0x13B5
    #define     B16VC_REGION_LOC_BASE_luma_yloc_base           0x13B4
    #define   LSb32VC_REGION_LOC_BASE_luma_yloc_base              8
    #define   LSb16VC_REGION_LOC_BASE_luma_yloc_base              8
    #define       bVC_REGION_LOC_BASE_luma_yloc_base           8
    #define   MSK32VC_REGION_LOC_BASE_luma_yloc_base              0x0000FF00

    #define     BA_VC_REGION_LOC_BASE_chroma_xloc_base         0x13B6
    #define     B16VC_REGION_LOC_BASE_chroma_xloc_base         0x13B6
    #define   LSb32VC_REGION_LOC_BASE_chroma_xloc_base            16
    #define   LSb16VC_REGION_LOC_BASE_chroma_xloc_base            0
    #define       bVC_REGION_LOC_BASE_chroma_xloc_base         8
    #define   MSK32VC_REGION_LOC_BASE_chroma_xloc_base            0x00FF0000

    #define     BA_VC_REGION_LOC_BASE_chroma_yloc_base         0x13B7
    #define     B16VC_REGION_LOC_BASE_chroma_yloc_base         0x13B6
    #define   LSb32VC_REGION_LOC_BASE_chroma_yloc_base            24
    #define   LSb16VC_REGION_LOC_BASE_chroma_yloc_base            8
    #define       bVC_REGION_LOC_BASE_chroma_yloc_base         8
    #define   MSK32VC_REGION_LOC_BASE_chroma_yloc_base            0xFF000000
    ///////////////////////////////////////////////////////////
    #define     RA_VC_FETCH_COLLECTION                         0x13B8

    #define     BA_VC_FETCH_COLLECTION_dram_burst_size         0x13B8
    #define     B16VC_FETCH_COLLECTION_dram_burst_size         0x13B8
    #define   LSb32VC_FETCH_COLLECTION_dram_burst_size            0
    #define   LSb16VC_FETCH_COLLECTION_dram_burst_size            0
    #define       bVC_FETCH_COLLECTION_dram_burst_size         16
    #define   MSK32VC_FETCH_COLLECTION_dram_burst_size            0x0000FFFF

    #define     BA_VC_FETCH_COLLECTION_collection_mode         0x13BA
    #define     B16VC_FETCH_COLLECTION_collection_mode         0x13BA
    #define   LSb32VC_FETCH_COLLECTION_collection_mode            16
    #define   LSb16VC_FETCH_COLLECTION_collection_mode            0
    #define       bVC_FETCH_COLLECTION_collection_mode         1
    #define   MSK32VC_FETCH_COLLECTION_collection_mode            0x00010000
    #define        VC_FETCH_COLLECTION_collection_mode_tile_exact              0x0
    #define        VC_FETCH_COLLECTION_collection_mode_burst_align              0x1
    ///////////////////////////////////////////////////////////

    typedef struct SIE_VC {
    ///////////////////////////////////////////////////////////
              SIE_TAG_SRAM                                     ie_tags;
             UNSG8 RSVD_tags                                   [256];
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx400                                    [3072];
    ///////////////////////////////////////////////////////////
    #define   GET32VC_CTRL_stop(r32)                           _BFGET_(r32, 0, 0)
    #define   SET32VC_CTRL_stop(r32,v)                         _BFSET_(r32, 0, 0,v)
    #define   GET16VC_CTRL_stop(r16)                           _BFGET_(r16, 0, 0)
    #define   SET16VC_CTRL_stop(r16,v)                         _BFSET_(r16, 0, 0,v)

    #define   GET32VC_CTRL_auto_resume(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32VC_CTRL_auto_resume(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16VC_CTRL_auto_resume(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16VC_CTRL_auto_resume(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define   GET32VC_CTRL_kickoff(r32)                        _BFGET_(r32, 2, 2)
    #define   SET32VC_CTRL_kickoff(r32,v)                      _BFSET_(r32, 2, 2,v)
    #define   GET16VC_CTRL_kickoff(r16)                        _BFGET_(r16, 2, 2)
    #define   SET16VC_CTRL_kickoff(r16,v)                      _BFSET_(r16, 2, 2,v)

    #define     w32VC_CTRL                                     {\
            UNSG32 uCTRL_stop                                  :  1;\
            UNSG32 uCTRL_auto_resume                           :  1;\
            UNSG32 uCTRL_kickoff                               :  1;\
            UNSG32 RSVDx1000_b3                                : 29;\
          }
    union { UNSG32 u32VC_CTRL;
            struct w32VC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32VC_FORMAT_picMode(r32)                      _BFGET_(r32, 2, 0)
    #define   SET32VC_FORMAT_picMode(r32,v)                    _BFSET_(r32, 2, 0,v)
    #define   GET16VC_FORMAT_picMode(r16)                      _BFGET_(r16, 2, 0)
    #define   SET16VC_FORMAT_picMode(r16,v)                    _BFSET_(r16, 2, 0,v)

    #define   GET32VC_FORMAT_fldPic(r32)                       _BFGET_(r32, 3, 3)
    #define   SET32VC_FORMAT_fldPic(r32,v)                     _BFSET_(r32, 3, 3,v)
    #define   GET16VC_FORMAT_fldPic(r16)                       _BFGET_(r16, 3, 3)
    #define   SET16VC_FORMAT_fldPic(r16,v)                     _BFSET_(r16, 3, 3,v)

    #define   GET32VC_FORMAT_rangeRed(r32)                     _BFGET_(r32, 4, 4)
    #define   SET32VC_FORMAT_rangeRed(r32,v)                   _BFSET_(r32, 4, 4,v)
    #define   GET16VC_FORMAT_rangeRed(r16)                     _BFGET_(r16, 4, 4)
    #define   SET16VC_FORMAT_rangeRed(r16,v)                   _BFSET_(r16, 4, 4,v)

    #define     w32VC_FORMAT                                   {\
            UNSG32 uFORMAT_picMode                             :  3;\
            UNSG32 uFORMAT_fldPic                              :  1;\
            UNSG32 uFORMAT_rangeRed                            :  1;\
            UNSG32 RSVDx1004_b5                                : 27;\
          }
    union { UNSG32 u32VC_FORMAT;
            struct w32VC_FORMAT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32VC_STATUS_session_done(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32VC_STATUS_session_done(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16VC_STATUS_session_done(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16VC_STATUS_session_done(r16,v)               _BFSET_(r16, 0, 0,v)

    #define     w32VC_STATUS                                   {\
            UNSG32 uSTATUS_session_done                        :  1;\
            UNSG32 RSVDx1008_b1                                : 31;\
          }
    union { UNSG32 u32VC_STATUS;
            struct w32VC_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32VC_CHROMA_OFFSET_val(r32)                   _BFGET_(r32,31, 0)
    #define   SET32VC_CHROMA_OFFSET_val(r32,v)                 _BFSET_(r32,31, 0,v)

    #define     w32VC_CHROMA_OFFSET                            {\
            UNSG32 uCHROMA_OFFSET_val                          : 32;\
          }
    union { UNSG32 u32VC_CHROMA_OFFSET;
            struct w32VC_CHROMA_OFFSET;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32VC_PAGE_STRIDE_stride(r32)                  _BFGET_(r32,31, 0)
    #define   SET32VC_PAGE_STRIDE_stride(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32VC_PAGE_STRIDE                              {\
            UNSG32 uPAGE_STRIDE_stride                         : 32;\
          }
    union { UNSG32 u32VC_PAGE_STRIDE;
            struct w32VC_PAGE_STRIDE;
          };
    ///////////////////////////////////////////////////////////
              SIE_FRAME_DESC                                   ie_frame[17];
    ///////////////////////////////////////////////////////////
              SIE_TRANS_DESC                                   ie_dscp[63];
    ///////////////////////////////////////////////////////////
              SIE_PIX_LUT                                      ie_xpix_map[32];
    ///////////////////////////////////////////////////////////
              SIE_PIX_LUT                                      ie_ypix_map[32];
    ///////////////////////////////////////////////////////////
              SIE_PIX_LUT                                      ie_xlocexp_map[32];
    ///////////////////////////////////////////////////////////
              SIE_PIX_LUT                                      ie_xpixexp_map[8];
    ///////////////////////////////////////////////////////////
              SIE_PIX_LUT                                      ie_ylocexp_map[32];
    ///////////////////////////////////////////////////////////
              SIE_PIX_LUT                                      ie_ypixexp_map[8];
    ///////////////////////////////////////////////////////////
    #define   GET32VC_INT_RBID_MAP_forward_rbid(r32)           _BFGET_(r32, 4, 0)
    #define   SET32VC_INT_RBID_MAP_forward_rbid(r32,v)         _BFSET_(r32, 4, 0,v)
    #define   GET16VC_INT_RBID_MAP_forward_rbid(r16)           _BFGET_(r16, 4, 0)
    #define   SET16VC_INT_RBID_MAP_forward_rbid(r16,v)         _BFSET_(r16, 4, 0,v)

    #define   GET32VC_INT_RBID_MAP_current_rbid(r32)           _BFGET_(r32, 9, 5)
    #define   SET32VC_INT_RBID_MAP_current_rbid(r32,v)         _BFSET_(r32, 9, 5,v)
    #define   GET16VC_INT_RBID_MAP_current_rbid(r16)           _BFGET_(r16, 9, 5)
    #define   SET16VC_INT_RBID_MAP_current_rbid(r16,v)         _BFSET_(r16, 9, 5,v)

    #define   GET32VC_INT_RBID_MAP_backward_rbid(r32)          _BFGET_(r32,14,10)
    #define   SET32VC_INT_RBID_MAP_backward_rbid(r32,v)        _BFSET_(r32,14,10,v)
    #define   GET16VC_INT_RBID_MAP_backward_rbid(r16)          _BFGET_(r16,14,10)
    #define   SET16VC_INT_RBID_MAP_backward_rbid(r16,v)        _BFSET_(r16,14,10,v)

    #define     w32VC_INT_RBID_MAP                             {\
            UNSG32 uINT_RBID_MAP_forward_rbid                  :  5;\
            UNSG32 uINT_RBID_MAP_current_rbid                  :  5;\
            UNSG32 uINT_RBID_MAP_backward_rbid                 :  5;\
            UNSG32 RSVDx1394_b15                               : 17;\
          }
    union { UNSG32 u32VC_INT_RBID_MAP;
            struct w32VC_INT_RBID_MAP;
          };
    ///////////////////////////////////////////////////////////
              SIE_INTEN_PARAM                                  ie_int_forward_top[2];
    ///////////////////////////////////////////////////////////
              SIE_INTEN_PARAM                                  ie_int_forward_bot[2];
    ///////////////////////////////////////////////////////////
              SIE_INTEN_PARAM                                  ie_int_current;
    ///////////////////////////////////////////////////////////
              SIE_INTEN_PARAM                                  ie_int_backward_top;
    ///////////////////////////////////////////////////////////
              SIE_INTEN_PARAM                                  ie_int_backward_bot;
    ///////////////////////////////////////////////////////////
    #define   GET32VC_REGION_LOC_BASE_luma_xloc_base(r32)      _BFGET_(r32, 7, 0)
    #define   SET32VC_REGION_LOC_BASE_luma_xloc_base(r32,v)    _BFSET_(r32, 7, 0,v)
    #define   GET16VC_REGION_LOC_BASE_luma_xloc_base(r16)      _BFGET_(r16, 7, 0)
    #define   SET16VC_REGION_LOC_BASE_luma_xloc_base(r16,v)    _BFSET_(r16, 7, 0,v)

    #define   GET32VC_REGION_LOC_BASE_luma_yloc_base(r32)      _BFGET_(r32,15, 8)
    #define   SET32VC_REGION_LOC_BASE_luma_yloc_base(r32,v)    _BFSET_(r32,15, 8,v)
    #define   GET16VC_REGION_LOC_BASE_luma_yloc_base(r16)      _BFGET_(r16,15, 8)
    #define   SET16VC_REGION_LOC_BASE_luma_yloc_base(r16,v)    _BFSET_(r16,15, 8,v)

    #define   GET32VC_REGION_LOC_BASE_chroma_xloc_base(r32)    _BFGET_(r32,23,16)
    #define   SET32VC_REGION_LOC_BASE_chroma_xloc_base(r32,v)  _BFSET_(r32,23,16,v)
    #define   GET16VC_REGION_LOC_BASE_chroma_xloc_base(r16)    _BFGET_(r16, 7, 0)
    #define   SET16VC_REGION_LOC_BASE_chroma_xloc_base(r16,v)  _BFSET_(r16, 7, 0,v)

    #define   GET32VC_REGION_LOC_BASE_chroma_yloc_base(r32)    _BFGET_(r32,31,24)
    #define   SET32VC_REGION_LOC_BASE_chroma_yloc_base(r32,v)  _BFSET_(r32,31,24,v)
    #define   GET16VC_REGION_LOC_BASE_chroma_yloc_base(r16)    _BFGET_(r16,15, 8)
    #define   SET16VC_REGION_LOC_BASE_chroma_yloc_base(r16,v)  _BFSET_(r16,15, 8,v)

    #define     w32VC_REGION_LOC_BASE                          {\
            UNSG32 uREGION_LOC_BASE_luma_xloc_base             :  8;\
            UNSG32 uREGION_LOC_BASE_luma_yloc_base             :  8;\
            UNSG32 uREGION_LOC_BASE_chroma_xloc_base           :  8;\
            UNSG32 uREGION_LOC_BASE_chroma_yloc_base           :  8;\
          }
    union { UNSG32 u32VC_REGION_LOC_BASE;
            struct w32VC_REGION_LOC_BASE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32VC_FETCH_COLLECTION_dram_burst_size(r32)    _BFGET_(r32,15, 0)
    #define   SET32VC_FETCH_COLLECTION_dram_burst_size(r32,v)  _BFSET_(r32,15, 0,v)
    #define   GET16VC_FETCH_COLLECTION_dram_burst_size(r16)    _BFGET_(r16,15, 0)
    #define   SET16VC_FETCH_COLLECTION_dram_burst_size(r16,v)  _BFSET_(r16,15, 0,v)

    #define   GET32VC_FETCH_COLLECTION_collection_mode(r32)    _BFGET_(r32,16,16)
    #define   SET32VC_FETCH_COLLECTION_collection_mode(r32,v)  _BFSET_(r32,16,16,v)
    #define   GET16VC_FETCH_COLLECTION_collection_mode(r16)    _BFGET_(r16, 0, 0)
    #define   SET16VC_FETCH_COLLECTION_collection_mode(r16,v)  _BFSET_(r16, 0, 0,v)

    #define     w32VC_FETCH_COLLECTION                         {\
            UNSG32 uFETCH_COLLECTION_dram_burst_size           : 16;\
            UNSG32 uFETCH_COLLECTION_collection_mode           :  1;\
            UNSG32 RSVDx13B8_b17                               : 15;\
          }
    union { UNSG32 u32VC_FETCH_COLLECTION;
            struct w32VC_FETCH_COLLECTION;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx13BC                                   [68];
    ///////////////////////////////////////////////////////////
    } SIE_VC;

    typedef union  T32VC_CTRL
          { UNSG32 u32;
            struct w32VC_CTRL;
                 } T32VC_CTRL;
    typedef union  T32VC_FORMAT
          { UNSG32 u32;
            struct w32VC_FORMAT;
                 } T32VC_FORMAT;
    typedef union  T32VC_STATUS
          { UNSG32 u32;
            struct w32VC_STATUS;
                 } T32VC_STATUS;
    typedef union  T32VC_CHROMA_OFFSET
          { UNSG32 u32;
            struct w32VC_CHROMA_OFFSET;
                 } T32VC_CHROMA_OFFSET;
    typedef union  T32VC_PAGE_STRIDE
          { UNSG32 u32;
            struct w32VC_PAGE_STRIDE;
                 } T32VC_PAGE_STRIDE;
    typedef union  T32VC_INT_RBID_MAP
          { UNSG32 u32;
            struct w32VC_INT_RBID_MAP;
                 } T32VC_INT_RBID_MAP;
    typedef union  T32VC_REGION_LOC_BASE
          { UNSG32 u32;
            struct w32VC_REGION_LOC_BASE;
                 } T32VC_REGION_LOC_BASE;
    typedef union  T32VC_FETCH_COLLECTION
          { UNSG32 u32;
            struct w32VC_FETCH_COLLECTION;
                 } T32VC_FETCH_COLLECTION;
    ///////////////////////////////////////////////////////////

    typedef union  TVC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32VC_CTRL;
                   };
                 } TVC_CTRL;
    typedef union  TVC_FORMAT
          { UNSG32 u32[1];
            struct {
            struct w32VC_FORMAT;
                   };
                 } TVC_FORMAT;
    typedef union  TVC_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32VC_STATUS;
                   };
                 } TVC_STATUS;
    typedef union  TVC_CHROMA_OFFSET
          { UNSG32 u32[1];
            struct {
            struct w32VC_CHROMA_OFFSET;
                   };
                 } TVC_CHROMA_OFFSET;
    typedef union  TVC_PAGE_STRIDE
          { UNSG32 u32[1];
            struct {
            struct w32VC_PAGE_STRIDE;
                   };
                 } TVC_PAGE_STRIDE;
    typedef union  TVC_INT_RBID_MAP
          { UNSG32 u32[1];
            struct {
            struct w32VC_INT_RBID_MAP;
                   };
                 } TVC_INT_RBID_MAP;
    typedef union  TVC_REGION_LOC_BASE
          { UNSG32 u32[1];
            struct {
            struct w32VC_REGION_LOC_BASE;
                   };
                 } TVC_REGION_LOC_BASE;
    typedef union  TVC_FETCH_COLLECTION
          { UNSG32 u32[1];
            struct {
            struct w32VC_FETCH_COLLECTION;
                   };
                 } TVC_FETCH_COLLECTION;

    ///////////////////////////////////////////////////////////
     SIGN32 VC_drvrd(SIE_VC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 VC_drvwr(SIE_VC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void VC_reset(SIE_VC *p);
     SIGN32 VC_cmp  (SIE_VC *p, SIE_VC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define VC_check(p,pie,pfx,hLOG) VC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define VC_print(p,    pfx,hLOG) VC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: VC
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE vcClkRst                biu              (4,4)
///     ###
///     * vCache level clock reset control unit
///     * For all reset control bit, 0-- reset, 1-- release. After chip power on reset, all these registers are 0 which means the vPro subsystem is in reset state and should be kicked-off by CPU.
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 global               
///               $ClkRstBiu           global            REG          
///     @ 0x00004                      (P)
///     # 0x00004 vcBiu                
///               $ClkRstBiu           vcBiu             REG          
///     @ 0x00008                      (P)
///     # 0x00008 BiuArb               
///               $ClkRstBiu           BiuArb            REG          
///     @ 0x0000C                      (P)
///     # 0x0000C misc                 
///               $ClkRstBiu           misc              REG          
///                                    ###
///                                    * For p3Figo0/1, only sw clock enable is used and dynamic clock control will not be applied.
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      12b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vcClkRst
#define h_vcClkRst (){}

    #define     RA_vcClkRst_global                             0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_vcClkRst_vcBiu                              0x0004
    ///////////////////////////////////////////////////////////
    #define     RA_vcClkRst_BiuArb                             0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_vcClkRst_misc                               0x000C
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vcClkRst {
    ///////////////////////////////////////////////////////////
              SIE_ClkRstBiu                                    ie_global;
    ///////////////////////////////////////////////////////////
              SIE_ClkRstBiu                                    ie_vcBiu;
    ///////////////////////////////////////////////////////////
              SIE_ClkRstBiu                                    ie_BiuArb;
    ///////////////////////////////////////////////////////////
              SIE_ClkRstBiu                                    ie_misc;
    ///////////////////////////////////////////////////////////
    } SIE_vcClkRst;

    ///////////////////////////////////////////////////////////
     SIGN32 vcClkRst_drvrd(SIE_vcClkRst *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vcClkRst_drvwr(SIE_vcClkRst *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vcClkRst_reset(SIE_vcClkRst *p);
     SIGN32 vcClkRst_cmp  (SIE_vcClkRst *p, SIE_vcClkRst *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vcClkRst_check(p,pie,pfx,hLOG) vcClkRst_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vcClkRst_print(p,    pfx,hLOG) vcClkRst_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vcClkRst
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE VcBIU                                    (4,4)
///     ###
///     * Constants for vCache submodule hSel decoding
///     ###
///     # # ----------------------------------------------------------
///               : SIZE               0x10000
///               : DEC_BIT            0x10
///                            ###
///                            * vCache
///                            ###
///               : Vc_OFST            0x0
///               : Vc_SIZE            0xF000
///               : Vc_DEC_BIT         0xC
///                            ###
///                            * VcCR
///                            ###
///               : VcCR_OFST          0xF000
///               : VcCR_SIZE          0x1000
///               : VcCR_DEC_BIT       0xC
///     @ 0x00000 Dummy                (P)
///               %unsigned 1  xxx                       0x0
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       1b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_VcBIU
#define h_VcBIU (){}

    #define        VcBIU_SIZE                                  0x10000
    #define        VcBIU_DEC_BIT                               0x10
    #define        VcBIU_Vc_OFST                               0x0
    #define        VcBIU_Vc_SIZE                               0xF000
    #define        VcBIU_Vc_DEC_BIT                            0xC
    #define        VcBIU_VcCR_OFST                             0xF000
    #define        VcBIU_VcCR_SIZE                             0x1000
    #define        VcBIU_VcCR_DEC_BIT                          0xC
    ///////////////////////////////////////////////////////////
    #define     RA_VcBIU_Dummy                                 0x0000

    #define     BA_VcBIU_Dummy_xxx                             0x0000
    #define     B16VcBIU_Dummy_xxx                             0x0000
    #define   LSb32VcBIU_Dummy_xxx                                0
    #define   LSb16VcBIU_Dummy_xxx                                0
    #define       bVcBIU_Dummy_xxx                             1
    #define   MSK32VcBIU_Dummy_xxx                                0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_VcBIU {
    ///////////////////////////////////////////////////////////
    #define   GET32VcBIU_Dummy_xxx(r32)                        _BFGET_(r32, 0, 0)
    #define   SET32VcBIU_Dummy_xxx(r32,v)                      _BFSET_(r32, 0, 0,v)
    #define   GET16VcBIU_Dummy_xxx(r16)                        _BFGET_(r16, 0, 0)
    #define   SET16VcBIU_Dummy_xxx(r16,v)                      _BFSET_(r16, 0, 0,v)

    #define     w32VcBIU_Dummy                                 {\
            UNSG32 uDummy_xxx                                  :  1;\
            UNSG32 RSVDx0_b1                                   : 31;\
          }
    union { UNSG32 u32VcBIU_Dummy;
            struct w32VcBIU_Dummy;
          };
    ///////////////////////////////////////////////////////////
    } SIE_VcBIU;

    typedef union  T32VcBIU_Dummy
          { UNSG32 u32;
            struct w32VcBIU_Dummy;
                 } T32VcBIU_Dummy;
    ///////////////////////////////////////////////////////////

    typedef union  TVcBIU_Dummy
          { UNSG32 u32[1];
            struct {
            struct w32VcBIU_Dummy;
                   };
                 } TVcBIU_Dummy;

    ///////////////////////////////////////////////////////////
     SIGN32 VcBIU_drvrd(SIE_VcBIU *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 VcBIU_drvwr(SIE_VcBIU *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void VcBIU_reset(SIE_VcBIU *p);
     SIGN32 VcBIU_cmp  (SIE_VcBIU *p, SIE_VcBIU *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define VcBIU_check(p,pie,pfx,hLOG) VcBIU_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define VcBIU_print(p,    pfx,hLOG) VcBIU_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: VcBIU
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: vcache_spec.h
////////////////////////////////////////////////////////////