/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//////
/// don't edit! auto-generated by docc: MctrlSS.h
////////////////////////////////////////////////////////////
#ifndef MctrlSS_h
#define MctrlSS_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE pll                                      (4,4)
///     ###
///     * SSPLL is a differential, wide range, and low power spread-spectrum PLL that is also capable of
///     * adding in a fixed frequency offset in about 1 ppm/step resolution.
///     * .. Input Frequency: Fref: 8 MHz ~ 2 GHz
///     * Output Frequency: Fout: 9 MHz ~ 3GHz for differential outputs CLKOUTP and CLKOUTN;
///     * 9 MHz ~ 2.1 GHz for single -ended output CLKOUT.
///     * .. Fout(CLKOUT) = Fref *(4*N/M) / CLKOUT_SE_DIV_SEL
///     * Fout(CLKOUTP, CLKOUTN) = Fref*(4*N/M) / CLKOUT_DIFF_DIV_SEL
///     * M: Reference Divider: 1 to 511.
///     * N: Feedback Divider: 1 to 511.
///     * VCODIV: VCO differential divider is controlled by CLKOUT_DIFF_DIV_SEL.
///     * VCO single-ended divider is controlled by CLKOUT_SE_DIV_SEL.
///     * Divider value = 1 1,2,3,4.128.
///     * Update Rate: Fref / M = 8 to 32 MHz (to maintain the PLL stability).
///     * NOTE: Although VCO can be operated between 12 ~ 3 GHz, the 1 ~ 1.5 GHz range is
///     * applicable only in the low power mode and cannot be used with the SSC function. In order to
///     * use the SSC function VCO must be operated above 1.5GHz.
///     * .. Cycle to Cycle Jitter (max): <30 ps.
///     * .. Programmable Reference and Feedback Divider.
///     * .. 1 ppm/step frequency offset resolution. Up to 50,000 ppm without changing the Feedback
///     * Divider setting.
///     * .. SSC frequency range: 30 KHz ~ 100 KHz
///     * .. SSC amplitude range: up to +/-5%. (SSC function is disabled by default.)
///     * .. Supporting both down-spread and center-spread modes.
///     * .. Current consumption( typical corner, AVDD=1.8 V, DVDD=1.05V): see sspll document
///     * .. Locking time: < 50 us
///     * .. Process Node: 28 nm LP
///     * .. Analog Power Supply: 1.8 V (+10%, -5%)
///     * .. Digital Power Supply: 1.05 V (±10%)
///     * Support Low DVDD Mode: Digtial Power Supply = 0.75V ~ 1.32V. See section 2.1 for detail.
///     * .. Output Duty Cycle: 45% - 55% for any post divider ratio
///     * .. Built-in Bandgap circuit.
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * PLL Control register
///               ###
///               %unsigned 1  PU                        0x1
///                                    ###
///                                    * PLL Power-Up
///                                    * 1: power up.
///                                    * 0: power down.
///                                    ###
///               %unsigned 1  RESET                     0x0
///                                    ###
///                                    * Power On Reset. Active high, reset PLL and all logic.
///                                    * 1: reset.
///                                    * 0: no reset.
///                                    ###
///               %unsigned 1  AVDD1815_SEL              0x1
///                                    ###
///                                    * AVDD Select.
///                                    * Selects whether AVDD is 1.8V
///                                    * or 1.5V.
///                                    * 1: 1.8V
///                                    * 0: 1.5V
///                                    ###
///               %unsigned 9  REFDIV                    0x2
///                                    ###
///                                    * Reference Clock Divider
///                                    * Select.
///                                    * Divider = REFDIV[8:0]
///                                    * 9’h000 = divide by 1
///                                    * 9’h001 = divide by 1
///                                    * 9’h002 = divide by 2
///                                    * 9’h003 = divide by 3
///                                    * ...
///                                    * 9’h1FF = divide by 511.
///                                    * REFDIV[8:0] range is 1~250
///                                    ###
///               %unsigned 9  FBDIV                     0x20
///                                    ###
///                                    * Feedback Clock Divider Select.
///                                    * Divider= FBDIV [8:0]
///                                    * 9’h000 = divide by 1
///                                    * 9’h001 = divide by 1
///                                    * 9’h002 = divide by 2
///                                    * 9’h003 = divide by 3
///                                    * ...
///                                    * 9’h1FF = divide by 511.
///                                    * FBDIV range is 9 to 94
///                                    ###
///               %unsigned 2  VDDM                      0x1
///                                    ###
///                                    * VCO Supply Control.
///                                    * 11: 1.3 V
///                                    * 10: 1.25 V
///                                    * 01: 1.2 V
///                                    * 00: 1.15 V.
///                                    ###
///               %unsigned 3  VDDL                      0x4
///                                    ###
///                                    * Internal VDD Supply
///                                    * Control.
///                                    * 000:0.9V
///                                    * 001:0.95V
///                                    * 010:1V
///                                    * 011:1.05V
///                                    * 100:1.1V
///                                    * 101:1.15V
///                                    * 110:1.2V
///                                    * 111:1.2V.
///                                    ###
///               %unsigned 4  ICP                       0x1
///                                    ###
///                                    * Charge-pump Current Control Bits.
///                                    * 0000: 3 uA
///                                    * 0001: 3.75 uA
///                                    * 0010: 4.5 uA
///                                    * 0011: 5.25 uA
///                                    * 0100: 6 uA
///                                    * 0101: 7.5 uA
///                                    * 0110: 9 uA
///                                    * 0111: 10.5 uA
///                                    * 1000: 12 uA
///                                    * 1001: 15 uA
///                                    * 1010: 18 uA
///                                    * 1011: 21 uA
///                                    * 1100: 24 uA
///                                    * 1101: 30 uA
///                                    * 1110: 36 uA
///                                    * 1111: 42 uA.
///                                    * Note : ICP[3:0] = (10 MHz / Update Rate) * Default.
///                                    * If PU_BW_SEL = 1, then increase ICP value by 2x
///                                    ###
///               %unsigned 1  PLL_BW_SEL                0x0
///                                    ###
///                                    * PLL Bandwidth Select.
///                                    * 1: BW x 2
///                                    * 0: Normal PLL bandwidth.
///                                    * Note: Use bandwidth x 2 only if update rate is between 16 - 32 MHz.
///                                    * NOTE: Bandwidth x 2 is for special cases only. If used, the update rate must be between 16 MHz - 32 MHz.
///                                    ###
///               %%        1          # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 4  KVCO                      0xA
///                                    ###
///                                    * KVCO Frequency Range
///                                    * Select.
///                                    * 0000~0111: Reserved.
///                                    * 1000:1.2GHz ~ 1.35GHz
///                                    * 1001:1.35GHz ~ 1.5GHz
///                                    * 1010:1.5GHz ~ 1.75GHz
///                                    * 1011:1.75GHz ~ 2.00GHz
///                                    * 1100: 2GHz ~ 2.2GHz
///                                    * 1101: 2.2GHz ~ 2.4GHz
///                                    * 1110: 2.4GHz ~ 2.6GHz
///                                    * 1111: 2.6GHz ~ 3GHz
///                                    * SSC mode is only supported for frequency >=2 GHz
///                                    * FVCO=((4*REFCLK/M)*N)/(1+OFFSET_PERCENT)
///                                    ###
///               %unsigned 2  CTUNE                     0x1
///                                    ###
///                                    * VCO Capacitor Select.
///                                    * 00: No Cap Loading
///                                    * 01: One Unit Cap Loading
///                                    * 10: Two Unit Cap Loading
///                                    * 11: Three Unit Cap Loading.
///                                    ###
///               %unsigned 3  CLKOUT_DIFF_DIV_SEL       0x2
///                                    ###
///                                    * Post Divider For Differential
///                                    * Output Clock.
///                                    * 000: 1
///                                    * 001: 2
///                                    * 010: 4
///                                    * 011: 8
///                                    * 100: 16
///                                    * 101: 32
///                                    * 110: 64
///                                    * 111:128
///                                    ###
///               %unsigned 3  CLKOUT_SE_DIV_SEL         0x2
///                                    ###
///                                    * Post Divider For
///                                    * Single-ended Output Clock.
///                                    * 000: 1
///                                    * 001: 2
///                                    * 010: 4
///                                    * 011: 8
///                                    * 100: 16
///                                    * 101: 32
///                                    * 110: 64
///                                    * 111:128
///                                    ###
///               %unsigned 1  CLKOUT_SOURCE_SEL         0x1
///                                    ###
///                                    * Differential Clock And
///                                    * Single-ended Clock Source Control.
///                                    * 0: from the phase interpolator.
///                                    * 1: from VCO directly.
///                                    * Note: This is used in test mode only. Select ‘1’ for normal operation.
///                                    ###
///               %unsigned 1  CLKOUT_DIFF_EN            0x1
///                                    ###
///                                    * Differential Clock Enable.
///                                    * 0:Disable differential clock
///                                    * 1:Enable differential clock
///                                    ###
///               %unsigned 1  BYPASS_EN                 0x0
///                                    ###
///                                    * PLL Clock Bypass Enable.
///                                    * 1: The PLL is bypassed. CLKOUT is derived from REFCLK.
///                                    * 0: CLKOUT is derived from the PLL clock.
///                                    * NOTE: Bypass only works for the single ended clock.
///                                    * If BYPASS_EN==1. CLKOUT= REFCLK.
///                                    * Make sure Fvco/CLKOUT_SE_DIV_SEL< 2.1 GHz, when using the bypass function.
///                                    ###
///               %unsigned 1  CLKOUT_SE_GATING_EN       0x0
///                                    ###
///                                    * Clock Output Gating Control.
///                                    * Selection for using the PLL lock signal to gate the output clock.
///                                    * 0: The PLL_LOCK signal won't affect the output clock, CLKOUT
///                                    * 1: Use PLL_LOCK signal to gate the output clock, CLKOUT.
///                                    ###
///               %unsigned 1  FBCLK_EXT_SEL             0x0
///                                    ###
///                                    * External Or Internal Feedback
///                                    * Clock Select.
///                                    * 0: select internal feedback clock
///                                    * 1: select external feedback clock.
///                                    * Note: For most applications the external feedback clock is not used. In these cases use the default selection "0".
///                                    ###
///               %unsigned 6  FBCDLY                    0x0
///                                    ###
///                                    * Fine Tune Delay Select
///                                    * Between REFCLK And FBCLK_EXT When FBCLK_EXT_SEL = 1.
///                                    * FBCDLY[5] is the sign bit.
///                                    * 1 = FBCLK_EXT will lag REFCLK.
///                                    * 0 = FBCLK_EXT will lead REFCLK.
///                                    * FBCDLY[4:0] decides the actual amount of delay.
///                                    * 00000: No delay.
///                                    * Each additional step has these
///                                    * delays:
///                                    * 00h = No delay
///                                    * 01h = 15 - 50 ps phase difference
///                                    * 02h = 30 - 100 ps phase difference
///                                    * 03h = 45 - 150 ps phase difference
///                                    * ...
///                                    * 3Fh = 945 ps - 3150 ps phase difference.
///                                    * Note: Used in DSPLL application, do not use in regular PLL application.
///                                    ###
///               %unsigned 3  FD                        0x4
///                                    ###
///                                    * Tune Frequency Detector Precision
///                                    * FD[0]: Reserved.
///                                    * FD[2:1] FD precision
///                                    * 00 +/- 0.1%
///                                    * 01 +/- 0.2%
///                                    * 10 +/- 0.4%
///                                    * 11 +/- 0.8%.
///                                    ###
///               %unsigned 4  INTPI                     0x6
///                                    ###
///                                    * Phase Interpolator Bias Current Select.
///                                    * 1.2 ~ 1.5 GHz NOT SUPPORTED
///                                    * 0101: (VCO:1.5 ~ 2 GHz)
///                                    * 0110: (VCO:2 ~ 2.5 GHz)
///                                    * 1000: (VCO:2.5 ~ 3GHz).
///                                    * NOTE: VCO running frequency below 1.5 GHz not supported.
///                                    ###
///               %%        2          # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 3  INTPR                     0x4
///                                    ###
///                                    * Phase Interpolator Resistor Select.
///                                    * NOTE: VCO running frequency below 1.5 GHz not supported.
///                                    ###
///               %unsigned 1  PI_EN                     0x0
///                                    ###
///                                    * Phase Interpolator Enable.
///                                    * 1: Enable phase interpolator
///                                    * 0: Disable phase interpolator.
///                                    ###
///               %unsigned 1  PI_LOOP_MODE              0x0
///                                    ###
///                                    * Phase Interpolator Loop Control.
///                                    * 1: PI is in the PLL loop.
///                                    * 0: PI is out of the PLL loop
///                                    ###
///               %unsigned 1  CLK_DET_EN                0x1
///                                    ###
///                                    * PI Output Clock Enable. This selection enables the PI output clock for the internal reset circuit
///                                    ###
///               %unsigned 1  RESET_PI                  0x0
///                                    ###
///                                    * External Interpolator Reset.
///                                    * 1: reset.
///                                    * 0: no reset.
///                                    ###
///               %unsigned 1  RESET_SSC                 0x0
///                                    ###
///                                    * SSC reset
///                                    * 0 : No reset
///                                    * 1 : Reset
///                                    ###
///               %unsigned 1  FREQ_OFFSET_EN            0x0
///                                    ###
///                                    * Frequency Offset Enable.
///                                    * 0: Disable
///                                    * 1: Enable.
///                                    ###
///               %unsigned 17 FREQ_OFFSET               0x0
///                                    ###
///                                    * Frequency Offset Value
///                                    * Control.
///                                    * [16]: Sign-Bit.
///                                    * 0: Frequency down
///                                    * 1: Frequency up
///                                    * [15:0] : 1 LSB 1 ppm, upto 5%
///                                    * 1LSB=10e6/(4*128 *2048) ppm
///                                    * [16]=0--->Sign= 1
///                                    * [16]=1--->Sign= -1
///                                    * Fout = Fvco/ (1 + Sign* FREQ_OFFSET[15:0] *1LSB)
///                                    ###
///               %unsigned 1  FREQ_OFFSET_MODE_SELECTION 0x0
///                                    ###
///                                    * Frequency Offset Mode Select.
///                                    * 0: FREQ_OFFSET[16:0] is updated by FREQ_OFFSET_VALID
///                                    * 1: FREQ_OFFSET[16:0] is sampled by CK_DIV64_OUT
///                                    * (It has to be valid at the rising edge of CK_DIV64_OUT).
///                                    * Note: For special application only. Use FREQ_OFFSET_VALID to update FREQ_OFFSET[16:0] by default.
///                                    ###
///               %unsigned 1  FREQ_OFFSET_VALID         0x0
///                                    ###
///                                    * Frequency Offset Value Valid.
///                                    * Indicates that frequency offset value (FREQ_OFFSET[16:0]) is valid.
///                                    * Note:
///                                    * 1) A rising edge will trigger the frequency offset generation circuit to read in the FREQ_OFFSET [16:0] value. The pulse width has to be no less than 50 ns.
///                                    * 2) This signal is only needed when FREQ_OFFSET_MODE_SELECTION=0.
///                                    ###
///               %unsigned 1  SSC_CLK_EN                0x0
///                                    ###
///                                    * SSC Clock Enable.
///                                    * This selection enables the PI output clock for SSC digital logic.
///                                    ###
///               %unsigned 1  SSC_MODE                  0x1
///                                    ###
///                                    * SSC Mode Select.
///                                    * 0: center spread
///                                    * 1: down spread.
///                                    ###
///               %%        2          # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 16 SSC_FREQ_DIV              0x0
///                                    ###
///                                    * SSC Frequency Select.
///                                    ###
///               %unsigned 11 SSC_RNGE                  0x0
///                                    ###
///                                    * SSC Range Select. SSC_RNGE[10:0] = Desired SSC amplitude /(SSC_FREQ_DIV[14:0]*2^(-28)).
///                                    * Rounding to integer required.
///                                    ###
///               %unsigned 4  TEST_ANA                  0x0
///                                    ###
///                                    * Analog test point
///                                    ###
///               %%        1          # Stuffing bits...
///     # 0x00010 ctrl4                
///               %unsigned 8  RESERVE_IN                0x0
///                                    ###
///                                    * Reserved input pins
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00014 status               (R-)
///               ###
///               * PLL status register
///               ###
///               %unsigned 1  PLL_LOCK                  
///                                    ###
///                                    * PLL Lock Detect.
///                                    * 1: PLL locked.
///                                    * 0: PLL not locked.
///                                    * Note:
///                                    * After PLL is powered up, wait for 50 us to check for the lock status.
///                                    * In normal operation, when PLL_LOCK signal is detected low, sample the signal again after 100 us to confirm the status.
///                                    * This signal is for testing purpose only, do not use it for any functional use.
///                                    ###
///               %unsigned 1  CLK_CFMOD                 
///                                    ###
///                                    * Clock Mode Output.
///                                    *  For down spread and
///                                    * PI_LOOP_MODE = 0, output
///                                    * is 0.
///                                    *  For down spread and
///                                    * PI_LOOP_MODE = 1, output
///                                    * is 1.
///                                    *  For center spread, output a
///                                    * clock with SSC modulation
///                                    * frequency.
///                                    ###
///               %unsigned 1  CLK_FMOD                  
///                                    ###
///                                    * Clock Output And Modulation
///                                    * Frequency.
///                                    * For down spread, output a clock
///                                    * with SSC modulation frequency.
///                                    * For center spread, output a clock
///                                    * with double SSC modulation
///                                    * frequency.
///                                    ###
///               %unsigned 8  RESERVE_OUT               
///                                    ###
///                                    * Reserve Output Register pins.
///                                    ###
///               %%        21         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:     141b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pll
#define h_pll (){}

    #define     RA_pll_ctrl                                    0x0000

    #define     BA_pll_ctrl_PU                                 0x0000
    #define     B16pll_ctrl_PU                                 0x0000
    #define   LSb32pll_ctrl_PU                                    0
    #define   LSb16pll_ctrl_PU                                    0
    #define       bpll_ctrl_PU                                 1
    #define   MSK32pll_ctrl_PU                                    0x00000001

    #define     BA_pll_ctrl_RESET                              0x0000
    #define     B16pll_ctrl_RESET                              0x0000
    #define   LSb32pll_ctrl_RESET                                 1
    #define   LSb16pll_ctrl_RESET                                 1
    #define       bpll_ctrl_RESET                              1
    #define   MSK32pll_ctrl_RESET                                 0x00000002

    #define     BA_pll_ctrl_AVDD1815_SEL                       0x0000
    #define     B16pll_ctrl_AVDD1815_SEL                       0x0000
    #define   LSb32pll_ctrl_AVDD1815_SEL                          2
    #define   LSb16pll_ctrl_AVDD1815_SEL                          2
    #define       bpll_ctrl_AVDD1815_SEL                       1
    #define   MSK32pll_ctrl_AVDD1815_SEL                          0x00000004

    #define     BA_pll_ctrl_REFDIV                             0x0000
    #define     B16pll_ctrl_REFDIV                             0x0000
    #define   LSb32pll_ctrl_REFDIV                                3
    #define   LSb16pll_ctrl_REFDIV                                3
    #define       bpll_ctrl_REFDIV                             9
    #define   MSK32pll_ctrl_REFDIV                                0x00000FF8

    #define     BA_pll_ctrl_FBDIV                              0x0001
    #define     B16pll_ctrl_FBDIV                              0x0000
    #define   LSb32pll_ctrl_FBDIV                                 12
    #define   LSb16pll_ctrl_FBDIV                                 12
    #define       bpll_ctrl_FBDIV                              9
    #define   MSK32pll_ctrl_FBDIV                                 0x001FF000

    #define     BA_pll_ctrl_VDDM                               0x0002
    #define     B16pll_ctrl_VDDM                               0x0002
    #define   LSb32pll_ctrl_VDDM                                  21
    #define   LSb16pll_ctrl_VDDM                                  5
    #define       bpll_ctrl_VDDM                               2
    #define   MSK32pll_ctrl_VDDM                                  0x00600000

    #define     BA_pll_ctrl_VDDL                               0x0002
    #define     B16pll_ctrl_VDDL                               0x0002
    #define   LSb32pll_ctrl_VDDL                                  23
    #define   LSb16pll_ctrl_VDDL                                  7
    #define       bpll_ctrl_VDDL                               3
    #define   MSK32pll_ctrl_VDDL                                  0x03800000

    #define     BA_pll_ctrl_ICP                                0x0003
    #define     B16pll_ctrl_ICP                                0x0002
    #define   LSb32pll_ctrl_ICP                                   26
    #define   LSb16pll_ctrl_ICP                                   10
    #define       bpll_ctrl_ICP                                4
    #define   MSK32pll_ctrl_ICP                                   0x3C000000

    #define     BA_pll_ctrl_PLL_BW_SEL                         0x0003
    #define     B16pll_ctrl_PLL_BW_SEL                         0x0002
    #define   LSb32pll_ctrl_PLL_BW_SEL                            30
    #define   LSb16pll_ctrl_PLL_BW_SEL                            14
    #define       bpll_ctrl_PLL_BW_SEL                         1
    #define   MSK32pll_ctrl_PLL_BW_SEL                            0x40000000

    #define     RA_pll_ctrl1                                   0x0004

    #define     BA_pll_ctrl_KVCO                               0x0004
    #define     B16pll_ctrl_KVCO                               0x0004
    #define   LSb32pll_ctrl_KVCO                                  0
    #define   LSb16pll_ctrl_KVCO                                  0
    #define       bpll_ctrl_KVCO                               4
    #define   MSK32pll_ctrl_KVCO                                  0x0000000F

    #define     BA_pll_ctrl_CTUNE                              0x0004
    #define     B16pll_ctrl_CTUNE                              0x0004
    #define   LSb32pll_ctrl_CTUNE                                 4
    #define   LSb16pll_ctrl_CTUNE                                 4
    #define       bpll_ctrl_CTUNE                              2
    #define   MSK32pll_ctrl_CTUNE                                 0x00000030

    #define     BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL                0x0004
    #define     B16pll_ctrl_CLKOUT_DIFF_DIV_SEL                0x0004
    #define   LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL                   6
    #define   LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL                   6
    #define       bpll_ctrl_CLKOUT_DIFF_DIV_SEL                3
    #define   MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL                   0x000001C0

    #define     BA_pll_ctrl_CLKOUT_SE_DIV_SEL                  0x0005
    #define     B16pll_ctrl_CLKOUT_SE_DIV_SEL                  0x0004
    #define   LSb32pll_ctrl_CLKOUT_SE_DIV_SEL                     9
    #define   LSb16pll_ctrl_CLKOUT_SE_DIV_SEL                     9
    #define       bpll_ctrl_CLKOUT_SE_DIV_SEL                  3
    #define   MSK32pll_ctrl_CLKOUT_SE_DIV_SEL                     0x00000E00

    #define     BA_pll_ctrl_CLKOUT_SOURCE_SEL                  0x0005
    #define     B16pll_ctrl_CLKOUT_SOURCE_SEL                  0x0004
    #define   LSb32pll_ctrl_CLKOUT_SOURCE_SEL                     12
    #define   LSb16pll_ctrl_CLKOUT_SOURCE_SEL                     12
    #define       bpll_ctrl_CLKOUT_SOURCE_SEL                  1
    #define   MSK32pll_ctrl_CLKOUT_SOURCE_SEL                     0x00001000

    #define     BA_pll_ctrl_CLKOUT_DIFF_EN                     0x0005
    #define     B16pll_ctrl_CLKOUT_DIFF_EN                     0x0004
    #define   LSb32pll_ctrl_CLKOUT_DIFF_EN                        13
    #define   LSb16pll_ctrl_CLKOUT_DIFF_EN                        13
    #define       bpll_ctrl_CLKOUT_DIFF_EN                     1
    #define   MSK32pll_ctrl_CLKOUT_DIFF_EN                        0x00002000

    #define     BA_pll_ctrl_BYPASS_EN                          0x0005
    #define     B16pll_ctrl_BYPASS_EN                          0x0004
    #define   LSb32pll_ctrl_BYPASS_EN                             14
    #define   LSb16pll_ctrl_BYPASS_EN                             14
    #define       bpll_ctrl_BYPASS_EN                          1
    #define   MSK32pll_ctrl_BYPASS_EN                             0x00004000

    #define     BA_pll_ctrl_CLKOUT_SE_GATING_EN                0x0005
    #define     B16pll_ctrl_CLKOUT_SE_GATING_EN                0x0004
    #define   LSb32pll_ctrl_CLKOUT_SE_GATING_EN                   15
    #define   LSb16pll_ctrl_CLKOUT_SE_GATING_EN                   15
    #define       bpll_ctrl_CLKOUT_SE_GATING_EN                1
    #define   MSK32pll_ctrl_CLKOUT_SE_GATING_EN                   0x00008000

    #define     BA_pll_ctrl_FBCLK_EXT_SEL                      0x0006
    #define     B16pll_ctrl_FBCLK_EXT_SEL                      0x0006
    #define   LSb32pll_ctrl_FBCLK_EXT_SEL                         16
    #define   LSb16pll_ctrl_FBCLK_EXT_SEL                         0
    #define       bpll_ctrl_FBCLK_EXT_SEL                      1
    #define   MSK32pll_ctrl_FBCLK_EXT_SEL                         0x00010000

    #define     BA_pll_ctrl_FBCDLY                             0x0006
    #define     B16pll_ctrl_FBCDLY                             0x0006
    #define   LSb32pll_ctrl_FBCDLY                                17
    #define   LSb16pll_ctrl_FBCDLY                                1
    #define       bpll_ctrl_FBCDLY                             6
    #define   MSK32pll_ctrl_FBCDLY                                0x007E0000

    #define     BA_pll_ctrl_FD                                 0x0006
    #define     B16pll_ctrl_FD                                 0x0006
    #define   LSb32pll_ctrl_FD                                    23
    #define   LSb16pll_ctrl_FD                                    7
    #define       bpll_ctrl_FD                                 3
    #define   MSK32pll_ctrl_FD                                    0x03800000

    #define     BA_pll_ctrl_INTPI                              0x0007
    #define     B16pll_ctrl_INTPI                              0x0006
    #define   LSb32pll_ctrl_INTPI                                 26
    #define   LSb16pll_ctrl_INTPI                                 10
    #define       bpll_ctrl_INTPI                              4
    #define   MSK32pll_ctrl_INTPI                                 0x3C000000

    #define     RA_pll_ctrl2                                   0x0008

    #define     BA_pll_ctrl_INTPR                              0x0008
    #define     B16pll_ctrl_INTPR                              0x0008
    #define   LSb32pll_ctrl_INTPR                                 0
    #define   LSb16pll_ctrl_INTPR                                 0
    #define       bpll_ctrl_INTPR                              3
    #define   MSK32pll_ctrl_INTPR                                 0x00000007

    #define     BA_pll_ctrl_PI_EN                              0x0008
    #define     B16pll_ctrl_PI_EN                              0x0008
    #define   LSb32pll_ctrl_PI_EN                                 3
    #define   LSb16pll_ctrl_PI_EN                                 3
    #define       bpll_ctrl_PI_EN                              1
    #define   MSK32pll_ctrl_PI_EN                                 0x00000008

    #define     BA_pll_ctrl_PI_LOOP_MODE                       0x0008
    #define     B16pll_ctrl_PI_LOOP_MODE                       0x0008
    #define   LSb32pll_ctrl_PI_LOOP_MODE                          4
    #define   LSb16pll_ctrl_PI_LOOP_MODE                          4
    #define       bpll_ctrl_PI_LOOP_MODE                       1
    #define   MSK32pll_ctrl_PI_LOOP_MODE                          0x00000010

    #define     BA_pll_ctrl_CLK_DET_EN                         0x0008
    #define     B16pll_ctrl_CLK_DET_EN                         0x0008
    #define   LSb32pll_ctrl_CLK_DET_EN                            5
    #define   LSb16pll_ctrl_CLK_DET_EN                            5
    #define       bpll_ctrl_CLK_DET_EN                         1
    #define   MSK32pll_ctrl_CLK_DET_EN                            0x00000020

    #define     BA_pll_ctrl_RESET_PI                           0x0008
    #define     B16pll_ctrl_RESET_PI                           0x0008
    #define   LSb32pll_ctrl_RESET_PI                              6
    #define   LSb16pll_ctrl_RESET_PI                              6
    #define       bpll_ctrl_RESET_PI                           1
    #define   MSK32pll_ctrl_RESET_PI                              0x00000040

    #define     BA_pll_ctrl_RESET_SSC                          0x0008
    #define     B16pll_ctrl_RESET_SSC                          0x0008
    #define   LSb32pll_ctrl_RESET_SSC                             7
    #define   LSb16pll_ctrl_RESET_SSC                             7
    #define       bpll_ctrl_RESET_SSC                          1
    #define   MSK32pll_ctrl_RESET_SSC                             0x00000080

    #define     BA_pll_ctrl_FREQ_OFFSET_EN                     0x0009
    #define     B16pll_ctrl_FREQ_OFFSET_EN                     0x0008
    #define   LSb32pll_ctrl_FREQ_OFFSET_EN                        8
    #define   LSb16pll_ctrl_FREQ_OFFSET_EN                        8
    #define       bpll_ctrl_FREQ_OFFSET_EN                     1
    #define   MSK32pll_ctrl_FREQ_OFFSET_EN                        0x00000100

    #define     BA_pll_ctrl_FREQ_OFFSET                        0x0009
    #define     B16pll_ctrl_FREQ_OFFSET                        0x0008
    #define   LSb32pll_ctrl_FREQ_OFFSET                           9
    #define   LSb16pll_ctrl_FREQ_OFFSET                           9
    #define       bpll_ctrl_FREQ_OFFSET                        17
    #define   MSK32pll_ctrl_FREQ_OFFSET                           0x03FFFE00

    #define     BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION         0x000B
    #define     B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION         0x000A
    #define   LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION            26
    #define   LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION            10
    #define       bpll_ctrl_FREQ_OFFSET_MODE_SELECTION         1
    #define   MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION            0x04000000

    #define     BA_pll_ctrl_FREQ_OFFSET_VALID                  0x000B
    #define     B16pll_ctrl_FREQ_OFFSET_VALID                  0x000A
    #define   LSb32pll_ctrl_FREQ_OFFSET_VALID                     27
    #define   LSb16pll_ctrl_FREQ_OFFSET_VALID                     11
    #define       bpll_ctrl_FREQ_OFFSET_VALID                  1
    #define   MSK32pll_ctrl_FREQ_OFFSET_VALID                     0x08000000

    #define     BA_pll_ctrl_SSC_CLK_EN                         0x000B
    #define     B16pll_ctrl_SSC_CLK_EN                         0x000A
    #define   LSb32pll_ctrl_SSC_CLK_EN                            28
    #define   LSb16pll_ctrl_SSC_CLK_EN                            12
    #define       bpll_ctrl_SSC_CLK_EN                         1
    #define   MSK32pll_ctrl_SSC_CLK_EN                            0x10000000

    #define     BA_pll_ctrl_SSC_MODE                           0x000B
    #define     B16pll_ctrl_SSC_MODE                           0x000A
    #define   LSb32pll_ctrl_SSC_MODE                              29
    #define   LSb16pll_ctrl_SSC_MODE                              13
    #define       bpll_ctrl_SSC_MODE                           1
    #define   MSK32pll_ctrl_SSC_MODE                              0x20000000

    #define     RA_pll_ctrl3                                   0x000C

    #define     BA_pll_ctrl_SSC_FREQ_DIV                       0x000C
    #define     B16pll_ctrl_SSC_FREQ_DIV                       0x000C
    #define   LSb32pll_ctrl_SSC_FREQ_DIV                          0
    #define   LSb16pll_ctrl_SSC_FREQ_DIV                          0
    #define       bpll_ctrl_SSC_FREQ_DIV                       16
    #define   MSK32pll_ctrl_SSC_FREQ_DIV                          0x0000FFFF

    #define     BA_pll_ctrl_SSC_RNGE                           0x000E
    #define     B16pll_ctrl_SSC_RNGE                           0x000E
    #define   LSb32pll_ctrl_SSC_RNGE                              16
    #define   LSb16pll_ctrl_SSC_RNGE                              0
    #define       bpll_ctrl_SSC_RNGE                           11
    #define   MSK32pll_ctrl_SSC_RNGE                              0x07FF0000

    #define     BA_pll_ctrl_TEST_ANA                           0x000F
    #define     B16pll_ctrl_TEST_ANA                           0x000E
    #define   LSb32pll_ctrl_TEST_ANA                              27
    #define   LSb16pll_ctrl_TEST_ANA                              11
    #define       bpll_ctrl_TEST_ANA                           4
    #define   MSK32pll_ctrl_TEST_ANA                              0x78000000

    #define     RA_pll_ctrl4                                   0x0010

    #define     BA_pll_ctrl_RESERVE_IN                         0x0010
    #define     B16pll_ctrl_RESERVE_IN                         0x0010
    #define   LSb32pll_ctrl_RESERVE_IN                            0
    #define   LSb16pll_ctrl_RESERVE_IN                            0
    #define       bpll_ctrl_RESERVE_IN                         8
    #define   MSK32pll_ctrl_RESERVE_IN                            0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_pll_status                                  0x0014

    #define     BA_pll_status_PLL_LOCK                         0x0014
    #define     B16pll_status_PLL_LOCK                         0x0014
    #define   LSb32pll_status_PLL_LOCK                            0
    #define   LSb16pll_status_PLL_LOCK                            0
    #define       bpll_status_PLL_LOCK                         1
    #define   MSK32pll_status_PLL_LOCK                            0x00000001

    #define     BA_pll_status_CLK_CFMOD                        0x0014
    #define     B16pll_status_CLK_CFMOD                        0x0014
    #define   LSb32pll_status_CLK_CFMOD                           1
    #define   LSb16pll_status_CLK_CFMOD                           1
    #define       bpll_status_CLK_CFMOD                        1
    #define   MSK32pll_status_CLK_CFMOD                           0x00000002

    #define     BA_pll_status_CLK_FMOD                         0x0014
    #define     B16pll_status_CLK_FMOD                         0x0014
    #define   LSb32pll_status_CLK_FMOD                            2
    #define   LSb16pll_status_CLK_FMOD                            2
    #define       bpll_status_CLK_FMOD                         1
    #define   MSK32pll_status_CLK_FMOD                            0x00000004

    #define     BA_pll_status_RESERVE_OUT                      0x0014
    #define     B16pll_status_RESERVE_OUT                      0x0014
    #define   LSb32pll_status_RESERVE_OUT                         3
    #define   LSb16pll_status_RESERVE_OUT                         3
    #define       bpll_status_RESERVE_OUT                      8
    #define   MSK32pll_status_RESERVE_OUT                         0x000007F8
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pll {
    ///////////////////////////////////////////////////////////
    #define   GET32pll_ctrl_PU(r32)                            _BFGET_(r32, 0, 0)
    #define   SET32pll_ctrl_PU(r32,v)                          _BFSET_(r32, 0, 0,v)
    #define   GET16pll_ctrl_PU(r16)                            _BFGET_(r16, 0, 0)
    #define   SET16pll_ctrl_PU(r16,v)                          _BFSET_(r16, 0, 0,v)

    #define   GET32pll_ctrl_RESET(r32)                         _BFGET_(r32, 1, 1)
    #define   SET32pll_ctrl_RESET(r32,v)                       _BFSET_(r32, 1, 1,v)
    #define   GET16pll_ctrl_RESET(r16)                         _BFGET_(r16, 1, 1)
    #define   SET16pll_ctrl_RESET(r16,v)                       _BFSET_(r16, 1, 1,v)

    #define   GET32pll_ctrl_AVDD1815_SEL(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32pll_ctrl_AVDD1815_SEL(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16pll_ctrl_AVDD1815_SEL(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16pll_ctrl_AVDD1815_SEL(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32pll_ctrl_REFDIV(r32)                        _BFGET_(r32,11, 3)
    #define   SET32pll_ctrl_REFDIV(r32,v)                      _BFSET_(r32,11, 3,v)
    #define   GET16pll_ctrl_REFDIV(r16)                        _BFGET_(r16,11, 3)
    #define   SET16pll_ctrl_REFDIV(r16,v)                      _BFSET_(r16,11, 3,v)

    #define   GET32pll_ctrl_FBDIV(r32)                         _BFGET_(r32,20,12)
    #define   SET32pll_ctrl_FBDIV(r32,v)                       _BFSET_(r32,20,12,v)

    #define   GET32pll_ctrl_VDDM(r32)                          _BFGET_(r32,22,21)
    #define   SET32pll_ctrl_VDDM(r32,v)                        _BFSET_(r32,22,21,v)
    #define   GET16pll_ctrl_VDDM(r16)                          _BFGET_(r16, 6, 5)
    #define   SET16pll_ctrl_VDDM(r16,v)                        _BFSET_(r16, 6, 5,v)

    #define   GET32pll_ctrl_VDDL(r32)                          _BFGET_(r32,25,23)
    #define   SET32pll_ctrl_VDDL(r32,v)                        _BFSET_(r32,25,23,v)
    #define   GET16pll_ctrl_VDDL(r16)                          _BFGET_(r16, 9, 7)
    #define   SET16pll_ctrl_VDDL(r16,v)                        _BFSET_(r16, 9, 7,v)

    #define   GET32pll_ctrl_ICP(r32)                           _BFGET_(r32,29,26)
    #define   SET32pll_ctrl_ICP(r32,v)                         _BFSET_(r32,29,26,v)
    #define   GET16pll_ctrl_ICP(r16)                           _BFGET_(r16,13,10)
    #define   SET16pll_ctrl_ICP(r16,v)                         _BFSET_(r16,13,10,v)

    #define   GET32pll_ctrl_PLL_BW_SEL(r32)                    _BFGET_(r32,30,30)
    #define   SET32pll_ctrl_PLL_BW_SEL(r32,v)                  _BFSET_(r32,30,30,v)
    #define   GET16pll_ctrl_PLL_BW_SEL(r16)                    _BFGET_(r16,14,14)
    #define   SET16pll_ctrl_PLL_BW_SEL(r16,v)                  _BFSET_(r16,14,14,v)

    #define     w32pll_ctrl                                    {\
            UNSG32 uctrl_PU                                    :  1;\
            UNSG32 uctrl_RESET                                 :  1;\
            UNSG32 uctrl_AVDD1815_SEL                          :  1;\
            UNSG32 uctrl_REFDIV                                :  9;\
            UNSG32 uctrl_FBDIV                                 :  9;\
            UNSG32 uctrl_VDDM                                  :  2;\
            UNSG32 uctrl_VDDL                                  :  3;\
            UNSG32 uctrl_ICP                                   :  4;\
            UNSG32 uctrl_PLL_BW_SEL                            :  1;\
            UNSG32 RSVDx0_b31                                  :  1;\
          }
    union { UNSG32 u32pll_ctrl;
            struct w32pll_ctrl;
          };
    #define   GET32pll_ctrl_KVCO(r32)                          _BFGET_(r32, 3, 0)
    #define   SET32pll_ctrl_KVCO(r32,v)                        _BFSET_(r32, 3, 0,v)
    #define   GET16pll_ctrl_KVCO(r16)                          _BFGET_(r16, 3, 0)
    #define   SET16pll_ctrl_KVCO(r16,v)                        _BFSET_(r16, 3, 0,v)

    #define   GET32pll_ctrl_CTUNE(r32)                         _BFGET_(r32, 5, 4)
    #define   SET32pll_ctrl_CTUNE(r32,v)                       _BFSET_(r32, 5, 4,v)
    #define   GET16pll_ctrl_CTUNE(r16)                         _BFGET_(r16, 5, 4)
    #define   SET16pll_ctrl_CTUNE(r16,v)                       _BFSET_(r16, 5, 4,v)

    #define   GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32)           _BFGET_(r32, 8, 6)
    #define   SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v)         _BFSET_(r32, 8, 6,v)
    #define   GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16)           _BFGET_(r16, 8, 6)
    #define   SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v)         _BFSET_(r16, 8, 6,v)

    #define   GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32)             _BFGET_(r32,11, 9)
    #define   SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v)           _BFSET_(r32,11, 9,v)
    #define   GET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16)             _BFGET_(r16,11, 9)
    #define   SET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16,v)           _BFSET_(r16,11, 9,v)

    #define   GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32)             _BFGET_(r32,12,12)
    #define   SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v)           _BFSET_(r32,12,12,v)
    #define   GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16)             _BFGET_(r16,12,12)
    #define   SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v)           _BFSET_(r16,12,12,v)

    #define   GET32pll_ctrl_CLKOUT_DIFF_EN(r32)                _BFGET_(r32,13,13)
    #define   SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v)              _BFSET_(r32,13,13,v)
    #define   GET16pll_ctrl_CLKOUT_DIFF_EN(r16)                _BFGET_(r16,13,13)
    #define   SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v)              _BFSET_(r16,13,13,v)

    #define   GET32pll_ctrl_BYPASS_EN(r32)                     _BFGET_(r32,14,14)
    #define   SET32pll_ctrl_BYPASS_EN(r32,v)                   _BFSET_(r32,14,14,v)
    #define   GET16pll_ctrl_BYPASS_EN(r16)                     _BFGET_(r16,14,14)
    #define   SET16pll_ctrl_BYPASS_EN(r16,v)                   _BFSET_(r16,14,14,v)

    #define   GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32)           _BFGET_(r32,15,15)
    #define   SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v)         _BFSET_(r32,15,15,v)
    #define   GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16)           _BFGET_(r16,15,15)
    #define   SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v)         _BFSET_(r16,15,15,v)

    #define   GET32pll_ctrl_FBCLK_EXT_SEL(r32)                 _BFGET_(r32,16,16)
    #define   SET32pll_ctrl_FBCLK_EXT_SEL(r32,v)               _BFSET_(r32,16,16,v)
    #define   GET16pll_ctrl_FBCLK_EXT_SEL(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16pll_ctrl_FBCLK_EXT_SEL(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32pll_ctrl_FBCDLY(r32)                        _BFGET_(r32,22,17)
    #define   SET32pll_ctrl_FBCDLY(r32,v)                      _BFSET_(r32,22,17,v)
    #define   GET16pll_ctrl_FBCDLY(r16)                        _BFGET_(r16, 6, 1)
    #define   SET16pll_ctrl_FBCDLY(r16,v)                      _BFSET_(r16, 6, 1,v)

    #define   GET32pll_ctrl_FD(r32)                            _BFGET_(r32,25,23)
    #define   SET32pll_ctrl_FD(r32,v)                          _BFSET_(r32,25,23,v)
    #define   GET16pll_ctrl_FD(r16)                            _BFGET_(r16, 9, 7)
    #define   SET16pll_ctrl_FD(r16,v)                          _BFSET_(r16, 9, 7,v)

    #define   GET32pll_ctrl_INTPI(r32)                         _BFGET_(r32,29,26)
    #define   SET32pll_ctrl_INTPI(r32,v)                       _BFSET_(r32,29,26,v)
    #define   GET16pll_ctrl_INTPI(r16)                         _BFGET_(r16,13,10)
    #define   SET16pll_ctrl_INTPI(r16,v)                       _BFSET_(r16,13,10,v)

    #define     w32pll_ctrl1                                   {\
            UNSG32 uctrl_KVCO                                  :  4;\
            UNSG32 uctrl_CTUNE                                 :  2;\
            UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL                   :  3;\
            UNSG32 uctrl_CLKOUT_SE_DIV_SEL                     :  3;\
            UNSG32 uctrl_CLKOUT_SOURCE_SEL                     :  1;\
            UNSG32 uctrl_CLKOUT_DIFF_EN                        :  1;\
            UNSG32 uctrl_BYPASS_EN                             :  1;\
            UNSG32 uctrl_CLKOUT_SE_GATING_EN                   :  1;\
            UNSG32 uctrl_FBCLK_EXT_SEL                         :  1;\
            UNSG32 uctrl_FBCDLY                                :  6;\
            UNSG32 uctrl_FD                                    :  3;\
            UNSG32 uctrl_INTPI                                 :  4;\
            UNSG32 RSVDx4_b30                                  :  2;\
          }
    union { UNSG32 u32pll_ctrl1;
            struct w32pll_ctrl1;
          };
    #define   GET32pll_ctrl_INTPR(r32)                         _BFGET_(r32, 2, 0)
    #define   SET32pll_ctrl_INTPR(r32,v)                       _BFSET_(r32, 2, 0,v)
    #define   GET16pll_ctrl_INTPR(r16)                         _BFGET_(r16, 2, 0)
    #define   SET16pll_ctrl_INTPR(r16,v)                       _BFSET_(r16, 2, 0,v)

    #define   GET32pll_ctrl_PI_EN(r32)                         _BFGET_(r32, 3, 3)
    #define   SET32pll_ctrl_PI_EN(r32,v)                       _BFSET_(r32, 3, 3,v)
    #define   GET16pll_ctrl_PI_EN(r16)                         _BFGET_(r16, 3, 3)
    #define   SET16pll_ctrl_PI_EN(r16,v)                       _BFSET_(r16, 3, 3,v)

    #define   GET32pll_ctrl_PI_LOOP_MODE(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32pll_ctrl_PI_LOOP_MODE(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16pll_ctrl_PI_LOOP_MODE(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16pll_ctrl_PI_LOOP_MODE(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32pll_ctrl_CLK_DET_EN(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32pll_ctrl_CLK_DET_EN(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16pll_ctrl_CLK_DET_EN(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16pll_ctrl_CLK_DET_EN(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32pll_ctrl_RESET_PI(r32)                      _BFGET_(r32, 6, 6)
    #define   SET32pll_ctrl_RESET_PI(r32,v)                    _BFSET_(r32, 6, 6,v)
    #define   GET16pll_ctrl_RESET_PI(r16)                      _BFGET_(r16, 6, 6)
    #define   SET16pll_ctrl_RESET_PI(r16,v)                    _BFSET_(r16, 6, 6,v)

    #define   GET32pll_ctrl_RESET_SSC(r32)                     _BFGET_(r32, 7, 7)
    #define   SET32pll_ctrl_RESET_SSC(r32,v)                   _BFSET_(r32, 7, 7,v)
    #define   GET16pll_ctrl_RESET_SSC(r16)                     _BFGET_(r16, 7, 7)
    #define   SET16pll_ctrl_RESET_SSC(r16,v)                   _BFSET_(r16, 7, 7,v)

    #define   GET32pll_ctrl_FREQ_OFFSET_EN(r32)                _BFGET_(r32, 8, 8)
    #define   SET32pll_ctrl_FREQ_OFFSET_EN(r32,v)              _BFSET_(r32, 8, 8,v)
    #define   GET16pll_ctrl_FREQ_OFFSET_EN(r16)                _BFGET_(r16, 8, 8)
    #define   SET16pll_ctrl_FREQ_OFFSET_EN(r16,v)              _BFSET_(r16, 8, 8,v)

    #define   GET32pll_ctrl_FREQ_OFFSET(r32)                   _BFGET_(r32,25, 9)
    #define   SET32pll_ctrl_FREQ_OFFSET(r32,v)                 _BFSET_(r32,25, 9,v)

    #define   GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32)    _BFGET_(r32,26,26)
    #define   SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v)  _BFSET_(r32,26,26,v)
    #define   GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16)    _BFGET_(r16,10,10)
    #define   SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v)  _BFSET_(r16,10,10,v)

    #define   GET32pll_ctrl_FREQ_OFFSET_VALID(r32)             _BFGET_(r32,27,27)
    #define   SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v)           _BFSET_(r32,27,27,v)
    #define   GET16pll_ctrl_FREQ_OFFSET_VALID(r16)             _BFGET_(r16,11,11)
    #define   SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v)           _BFSET_(r16,11,11,v)

    #define   GET32pll_ctrl_SSC_CLK_EN(r32)                    _BFGET_(r32,28,28)
    #define   SET32pll_ctrl_SSC_CLK_EN(r32,v)                  _BFSET_(r32,28,28,v)
    #define   GET16pll_ctrl_SSC_CLK_EN(r16)                    _BFGET_(r16,12,12)
    #define   SET16pll_ctrl_SSC_CLK_EN(r16,v)                  _BFSET_(r16,12,12,v)

    #define   GET32pll_ctrl_SSC_MODE(r32)                      _BFGET_(r32,29,29)
    #define   SET32pll_ctrl_SSC_MODE(r32,v)                    _BFSET_(r32,29,29,v)
    #define   GET16pll_ctrl_SSC_MODE(r16)                      _BFGET_(r16,13,13)
    #define   SET16pll_ctrl_SSC_MODE(r16,v)                    _BFSET_(r16,13,13,v)

    #define     w32pll_ctrl2                                   {\
            UNSG32 uctrl_INTPR                                 :  3;\
            UNSG32 uctrl_PI_EN                                 :  1;\
            UNSG32 uctrl_PI_LOOP_MODE                          :  1;\
            UNSG32 uctrl_CLK_DET_EN                            :  1;\
            UNSG32 uctrl_RESET_PI                              :  1;\
            UNSG32 uctrl_RESET_SSC                             :  1;\
            UNSG32 uctrl_FREQ_OFFSET_EN                        :  1;\
            UNSG32 uctrl_FREQ_OFFSET                           : 17;\
            UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION            :  1;\
            UNSG32 uctrl_FREQ_OFFSET_VALID                     :  1;\
            UNSG32 uctrl_SSC_CLK_EN                            :  1;\
            UNSG32 uctrl_SSC_MODE                              :  1;\
            UNSG32 RSVDx8_b30                                  :  2;\
          }
    union { UNSG32 u32pll_ctrl2;
            struct w32pll_ctrl2;
          };
    #define   GET32pll_ctrl_SSC_FREQ_DIV(r32)                  _BFGET_(r32,15, 0)
    #define   SET32pll_ctrl_SSC_FREQ_DIV(r32,v)                _BFSET_(r32,15, 0,v)
    #define   GET16pll_ctrl_SSC_FREQ_DIV(r16)                  _BFGET_(r16,15, 0)
    #define   SET16pll_ctrl_SSC_FREQ_DIV(r16,v)                _BFSET_(r16,15, 0,v)

    #define   GET32pll_ctrl_SSC_RNGE(r32)                      _BFGET_(r32,26,16)
    #define   SET32pll_ctrl_SSC_RNGE(r32,v)                    _BFSET_(r32,26,16,v)
    #define   GET16pll_ctrl_SSC_RNGE(r16)                      _BFGET_(r16,10, 0)
    #define   SET16pll_ctrl_SSC_RNGE(r16,v)                    _BFSET_(r16,10, 0,v)

    #define   GET32pll_ctrl_TEST_ANA(r32)                      _BFGET_(r32,30,27)
    #define   SET32pll_ctrl_TEST_ANA(r32,v)                    _BFSET_(r32,30,27,v)
    #define   GET16pll_ctrl_TEST_ANA(r16)                      _BFGET_(r16,14,11)
    #define   SET16pll_ctrl_TEST_ANA(r16,v)                    _BFSET_(r16,14,11,v)

    #define     w32pll_ctrl3                                   {\
            UNSG32 uctrl_SSC_FREQ_DIV                          : 16;\
            UNSG32 uctrl_SSC_RNGE                              : 11;\
            UNSG32 uctrl_TEST_ANA                              :  4;\
            UNSG32 RSVDxC_b31                                  :  1;\
          }
    union { UNSG32 u32pll_ctrl3;
            struct w32pll_ctrl3;
          };
    #define   GET32pll_ctrl_RESERVE_IN(r32)                    _BFGET_(r32, 7, 0)
    #define   SET32pll_ctrl_RESERVE_IN(r32,v)                  _BFSET_(r32, 7, 0,v)
    #define   GET16pll_ctrl_RESERVE_IN(r16)                    _BFGET_(r16, 7, 0)
    #define   SET16pll_ctrl_RESERVE_IN(r16,v)                  _BFSET_(r16, 7, 0,v)

    #define     w32pll_ctrl4                                   {\
            UNSG32 uctrl_RESERVE_IN                            :  8;\
            UNSG32 RSVDx10_b8                                  : 24;\
          }
    union { UNSG32 u32pll_ctrl4;
            struct w32pll_ctrl4;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pll_status_PLL_LOCK(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32pll_status_PLL_LOCK(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16pll_status_PLL_LOCK(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16pll_status_PLL_LOCK(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32pll_status_CLK_CFMOD(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32pll_status_CLK_CFMOD(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16pll_status_CLK_CFMOD(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16pll_status_CLK_CFMOD(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define   GET32pll_status_CLK_FMOD(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32pll_status_CLK_FMOD(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16pll_status_CLK_FMOD(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16pll_status_CLK_FMOD(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32pll_status_RESERVE_OUT(r32)                 _BFGET_(r32,10, 3)
    #define   SET32pll_status_RESERVE_OUT(r32,v)               _BFSET_(r32,10, 3,v)
    #define   GET16pll_status_RESERVE_OUT(r16)                 _BFGET_(r16,10, 3)
    #define   SET16pll_status_RESERVE_OUT(r16,v)               _BFSET_(r16,10, 3,v)

    #define     w32pll_status                                  {\
            UNSG32 ustatus_PLL_LOCK                            :  1;\
            UNSG32 ustatus_CLK_CFMOD                           :  1;\
            UNSG32 ustatus_CLK_FMOD                            :  1;\
            UNSG32 ustatus_RESERVE_OUT                         :  8;\
            UNSG32 RSVDx14_b11                                 : 21;\
          }
    union { UNSG32 u32pll_status;
            struct w32pll_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pll;

    typedef union  T32pll_ctrl
          { UNSG32 u32;
            struct w32pll_ctrl;
                 } T32pll_ctrl;
    typedef union  T32pll_ctrl1
          { UNSG32 u32;
            struct w32pll_ctrl1;
                 } T32pll_ctrl1;
    typedef union  T32pll_ctrl2
          { UNSG32 u32;
            struct w32pll_ctrl2;
                 } T32pll_ctrl2;
    typedef union  T32pll_ctrl3
          { UNSG32 u32;
            struct w32pll_ctrl3;
                 } T32pll_ctrl3;
    typedef union  T32pll_ctrl4
          { UNSG32 u32;
            struct w32pll_ctrl4;
                 } T32pll_ctrl4;
    typedef union  T32pll_status
          { UNSG32 u32;
            struct w32pll_status;
                 } T32pll_status;
    ///////////////////////////////////////////////////////////

    typedef union  Tpll_ctrl
          { UNSG32 u32[5];
            struct {
            struct w32pll_ctrl;
            struct w32pll_ctrl1;
            struct w32pll_ctrl2;
            struct w32pll_ctrl3;
            struct w32pll_ctrl4;
                   };
                 } Tpll_ctrl;
    typedef union  Tpll_status
          { UNSG32 u32[1];
            struct {
            struct w32pll_status;
                   };
                 } Tpll_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pll_reset(SIE_pll *p);
     SIGN32 pll_cmp  (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pll_print(p,    pfx,hLOG) pll_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pll
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE MctrlSS                 biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 MC5_4TO1             (P)
///               ###
///               * Registers that selects 4:1/ 2:1 operation for Memory Controller.
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 1  enable                    0x1
///                                    ###
///                                    * 1 : selects 4:1 operation. Memory Controller runs at 1/4th of PHY clock (or half of DDR interface clock)
///                                    * Recommended for data rates more than 1.6GHz DDR.
///                                    * 0 : selects 2:1 operation. Memory Controller runs at ½ the speed of PHY clock (or same as DDR interface clock).
///                                    * Recommended for data rates of up to 1.6GHz DDR.
///                                    * NOTE: Memory Controller is less efficient in 4:1 mode, so it is not recommended to enable 4:1 operation at less than or equal to 1.6GHz DDR rates.
///                                    * This register should only be written when MC is idle (preferably as part of the MC initialization sequence).
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00004 AVIO_PRIO            (P)
///               ###
///               * Registers that controls priority of AVIO DMA masters when QoS flag is low. For this register to take effect, per-master priority scheme should be selected inside MC4 for port-1 (vppDhub) and port-2 (agVipDhub).
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 4  vppDhub                   0x2
///                                    ###
///                                    * When QoS flag from vppDhub is asserted, critical priority request is sent to MC4. When QoS flag is low, this register decides the priority of the transaction sent to MC4.
///                                    ###
///               %unsigned 4  agVipDhub                 0x2
///                                    ###
///                                    * When QoS flag from agVipDhub is asserted, critical priority request is sent to MC4. When QoS flag is low, this register decides the priority of the transaction sent to MC4.
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00008 ddrPhyLoopBackSrc    (P)
///               ###
///               * Register to control source of DDR Phy Loopback config information (JTAG or CPU AHB)
///               ###
///               %unsigned 1  Control                   0x1
///                                    ###
///                                    * Control to select the source of DDR Phy Loopback configuration info
///                                    * 0 – through the CPU AHB bus
///                                    * 1 - via JTAG
///                                    * JTAG chosen by default
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x0000C ddrPhyLoopBackConfig1 (P)
///               ###
///               * Register for configuring ddrPhy Loopback
///               ###
///               %unsigned 1  TST_MODE                  0x0
///                                    ###
///                                    * Loopback Mode Enable.
///                                    * 0: under normal functional mode, DDR-PHY is fed with MC4 output.
///                                    * 1: Loopback test-mode is enabled, DDR-PHY is fed with PRBS test-patterns.
///                                    ###
///               %unsigned 1  TST_START                 0x0
///                                    ###
///                                    * Loopback Test Start.
///                                    * 0->1 transition will start the loopback test. S/W shall write 0 and then 1 to start the test. Once written as 0 and then 1, H/W will not look at this bit until loopback test is indicated done through the ddrPhyLoopBackStatus2 register.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00010 ddrPhyLoopBackConfig2 (P)
///               ###
///               * Register for controlling inputs to the PRBS test-pattern generator
///               ###
///               %unsigned 5  CFG_DATA_DLY              0x0
///                                    ###
///                                    * Adjust the value to sample the data from the data sub-phy for comparison.
///                                    ###
///               %unsigned 3  RSERVRED1                 0x0
///                                    ###
///                                    * Reserved. Not used.
///                                    * *INTERNAL_ONLY**
///                                    ###
///               %unsigned 5  CFG_ADC_DLY               0x0
///                                    ###
///                                    * Adjust the value to sample the data from the adcm sub-phy for comparison.
///                                    ###
///               %unsigned 2  RSERVRED2                 0x0
///                                    ###
///                                    * Reserved. Not used.
///                                    * *INTERNAL_ONLY**
///                                    ###
///               %unsigned 1  SKIP_CMD_SUBPHY           0x0
///                                    ###
///                                    * 0: Loopback test covers ADCM sub-PHYs
///                                    * 1: Loopback test skips ADCM sub-PHYs
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00014 ddrPhyLoopBackConfig3 (P)
///               ###
///               * Not used.
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 32 SEED                      0x0
///                                    ###
///                                    * Initial Seed
///                                    ###
///     @ 0x00018 ddrPhyLoopBackStatus1 (R-)
///               ###
///               * Register for DDR PHY Loop Back Status
///               ###
///               %unsigned 16 STATUS                    
///                                    ###
///                                    * Indicate which sub-PHY fail the test. Valid when “DONE” bit indicates loopback test is finished.
///                                    ###
///               %unsigned 16 RESERVED                  
///                                    ###
///                                    * Not used.
///                                    * *INTERNAL_ONLY**
///                                    ###
///     @ 0x0001C ddrPhyLoopBackStatus2 (R-)
///               %unsigned 1  DONE                      
///                                    ###
///                                    * 0: Loopback test is not finished.
///                                    * 1: Loopback test is finished and status is valid.
///                                    * This bit gets cleared automatically when S/W writes 1 to TST_START bit.
///                                    ###
///               %unsigned 1  FAIL                      
///                                    ###
///                                    * Valid when DONE bit is high.
///                                    * 0: Loopback test passed.
///                                    * 1: Loopback test failed, ddrPhyLoopBackStatus1 register indicates which sub-PHY has failed.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00020 mc_phy_pd_ctrl       (P)
///               ###
///               * DDR PHY QS/DQ/AC/CK pull-up/pull-down control
///               ###
///               %unsigned 1  normal_mode_ch0           0x0
///                                    ###
///                                    * 0 : DDR Phy DQ/QS/AC/CK pull-up/pull-down controlled by register bit
///                                    * 1 : pull-up/pull-down controlled by memory controller
///                                    ###
///               %unsigned 1  pd_en_ch0                 0x0
///                                    ###
///                                    * This bit is used to control DDR PHY DQ/QS/AC/CK pull-up/pull-down when normal_mode is '0'
///                                    * bit[1] (pd_en)
///                                    * bit[0] (normal_mode)
///                                    * X
///                                    * 1
///                                    * pull-up/pull-down controlled by memory controller register (MC_PHY_REG10)
///                                    * 0
///                                    * 0
///                                    * pull-up/pull-down controlled by pd_en bit, DQ/QS/AC/CK pull-up/pull-down disabled as pd_en is 0
///                                    * 1
///                                    * 0
///                                    * pull-up/pull-down controlled by pd_en bit, DQ/QS/AC/CK pull-up/pull-down enabled as pd_en is 1
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00024 mc_mstr0_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port – 0 (CPU) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x0
///                                    ###
///                                    * QoS control for Port – 0 (CPU) Read-Addr channel of memory controller
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00028 mc_mstr1_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port – 1 (AVIO0) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x3
///                                    ###
///                                    * QoS control for Port – 1 (AVIO0) Read-Addr channel of memory controller
///                                    * When QoS flag from vppDhub is asserted, this register is used to control the priority
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x0002C mc_mstr2_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port - 2 (AVIO1) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x3
///                                    ###
///                                    * QoS control for Mst0 (AVIO1) Read-Addr channel of memory controller
///                                    * When QoS flag from agVipDhub is asserted, this register is used to control the priority
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00030 mc_mstr3_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port – 3 (DXBAR S2) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x0
///                                    ###
///                                    * QoS control for Port – 3 (DXBAR S2) Read-Addr channel of memory controller
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00034 mc_mstr4_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port -4 (DXBAR S0) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x0
///                                    ###
///                                    * QoS control for Port – 4 (DXBAR S0) Read-Addr channel of memory controller
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00038 mc_mstr5_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port – 5 (GC1K) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x0
///                                    ###
///                                    * QoS control for Port – 5 (GC1K) Read-Addr channel of memory controller
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x0003C mc_mstr6_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port – 6 (HANTRO) Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x0
///                                    ###
///                                    * QoS control for Port – 6 (HANTRO) Read-Addr channel of memory controller
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00040 mc_mstr7_qos         (P)
///               %unsigned 4  awqos                     0x0
///                                    ###
///                                    * QoS control for Port – 7 Write-Addr channel of memory controller
///                                    ###
///               %unsigned 4  arqos                     0x0
///                                    ###
///                                    * QoS control for Port – 7 Read-Addr channel of memory controller
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00044 mc_hw_phy_dll_update_req (P)
///               %unsigned 1  en                        0x0
///                                    ###
///                                    * Held high for atleast 3 dClk cycle to trigger a DLL update in the PHY, can be useful for dynamic voltage changing
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00048 mc_hw_dfc_ctrl       (P)
///               %unsigned 1  reg_table_req             0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %unsigned 5  reg_table_type            0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %unsigned 1  reg_table_wait_ack        0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %unsigned 1  sleep_req                 0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %unsigned 3  sleep_type                0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %%        21         # Stuffing bits...
///     @ 0x0004C mc_hw_dfc_sts        (R-)
///               %unsigned 1  reg_table_req_ack         0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %unsigned 1  reg_table_wait_req        0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %unsigned 1  sleep_req_ack             0x0
///                                    ###
///                                    * HW Dynamic Freq. Change (DFC)handshake signal
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00050                      (P)
///     # 0x00050 memPll               
///               $pll                 memPll            REG          
///                                    ###
///                                    * Configuration registers for memPll
///                                    ###
///     @ 0x00068 RWTC_31to0           (P)
///               %unsigned 32 value                     0xAAAA99AA
///                                    ###
///                                    * RWTC[31:0] value for MC5
///                                    ###
///     @ 0x0006C RWTC_57to32          (P)
///               %unsigned 26 value                     0x2A95B5A
///                                    ###
///                                    * RWTC[57:32] value for MC5
///                                    ###
///               %%        6          # Stuffing bits...
///     @ 0x00070 DDRCLK_VREG_CTRL_0   (P)
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * '1' Power UP REGULATOR 0
///                                    * '0' Power down for minimum current consumption
///                                    ###
///               %unsigned 1  LP                        0x1
///                                    ###
///                                    * For hpm usage, set LP=0, for lp usage, set LP=1
///                                    ###
///               %unsigned 1  BYPASS                    0x1
///                                    ###
///                                    * Bypass DVDD to output, when set both BYPASS=1 and PU=1, VDDR=DVDD
///                                    ###
///               %unsigned 3  VSEL                      0x0
///                                    ###
///                                    * Choose regulator output voltage 20mV/step
///                                    * When LP=0   When LP=1
///                                    * 000:0.88V       0.94V
///                                    * 001:0.90V       0.96V
///                                    * 010:0.92V       0.98V
///                                    * 011:0.94V       1.00V
///                                    * 100:0.96V       1.02V
///                                    * 101:0.98V       1.04V
///                                    * 110:1.00V       1.06V
///                                    * 111:1.02V       1.08V
///                                    ###
///               %unsigned 1  TSTMON_EN                 0x0
///                                    ###
///                                    * TESTMON enable signal
///                                    * When TSTMON_EN=0, TP==Z; when TSTMON_EN=1, pass TESTMON[2:0] value
///                                    ###
///               %unsigned 3  TESTMON                   0x0
///                                    ###
///                                    * Analog Test Point
///                                    * If Testmon[2:0] = 000, high Z.
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00074 DDRCLK_VREG_CTRL_1   (P)
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * '1' Power UP REGULATOR 1
///                                    * '0' Power down for minimum current consumption
///                                    ###
///               %unsigned 1  LP                        0x1
///                                    ###
///                                    * For hpm usage, set LP=0, for lp usage, set LP=1
///                                    ###
///               %unsigned 1  BYPASS                    0x1
///                                    ###
///                                    * Bypass DVDD to output, when set both BYPASS=1 and PU=1, VDDR=DVDD
///                                    ###
///               %unsigned 3  VSEL                      0x0
///                                    ###
///                                    * Choose regulator output voltage 20mV/step
///                                    * When LP=0   When LP=1
///                                    * 000:0.88V       0.94V
///                                    * 001:0.90V       0.96V
///                                    * 010:0.92V       0.98V
///                                    * 011:0.94V       1.00V
///                                    * 100:0.96V       1.02V
///                                    * 101:0.98V       1.04V
///                                    * 110:1.00V       1.06V
///                                    * 111:1.02V       1.08V
///                                    ###
///               %unsigned 1  TSTMON_EN                 0x0
///                                    ###
///                                    * TESTMON enable signal
///                                    * When TSTMON_EN=0, TP==Z; when TSTMON_EN=1, pass TESTMON[2:0] value
///                                    ###
///               %unsigned 3  TESTMON                   0x0
///                                    ###
///                                    * Analog Test Point
///                                    * If Testmon[2:0] = 000, high Z.
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00078 DDRCLK_VREG_CTRL_2   (P)
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * '1' Power UP REGULATOR 2
///                                    * '0' Power down for minimum current consumption
///                                    ###
///               %unsigned 1  LP                        0x1
///                                    ###
///                                    * For hpm usage, set LP=0, for lp usage, set LP=1
///                                    ###
///               %unsigned 1  BYPASS                    0x1
///                                    ###
///                                    * Bypass DVDD to output, when set both BYPASS=1 and PU=1, VDDR=DVDD
///                                    ###
///               %unsigned 3  VSEL                      0x0
///                                    ###
///                                    * Choose regulator output voltage 20mV/step
///                                    * When LP=0   When LP=1
///                                    * 000:0.88V       0.94V
///                                    * 001:0.90V       0.96V
///                                    * 010:0.92V       0.98V
///                                    * 011:0.94V       1.00V
///                                    * 100:0.96V       1.02V
///                                    * 101:0.98V       1.04V
///                                    * 110:1.00V       1.06V
///                                    * 111:1.02V       1.08V
///                                    ###
///               %unsigned 1  TSTMON_EN                 0x0
///                                    ###
///                                    * TESTMON enable signal
///                                    * When TSTMON_EN=0, TP==Z; when TSTMON_EN=1, pass TESTMON[2:0] value
///                                    ###
///               %unsigned 3  TESTMON                   0x0
///                                    ###
///                                    * Analog Test Point
///                                    * If Testmon[2:0] = 000, high Z.
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x0007C DDRCLK_VREG_CTRL_3   (P)
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * '1' Power UP REGULATOR 3
///                                    * '0' Power down for minimum current consumption
///                                    ###
///               %unsigned 1  LP                        0x1
///                                    ###
///                                    * For hpm usage, set LP=0, for lp usage, set LP=1
///                                    ###
///               %unsigned 1  BYPASS                    0x1
///                                    ###
///                                    * Bypass DVDD to output, when set both BYPASS=1 and PU=1, VDDR=DVDD
///                                    ###
///               %unsigned 3  VSEL                      0x0
///                                    ###
///                                    * Choose regulator output voltage 20mV/step
///                                    * When LP=0   When LP=1
///                                    * 000:0.88V       0.94V
///                                    * 001:0.90V       0.96V
///                                    * 010:0.92V       0.98V
///                                    * 011:0.94V       1.00V
///                                    * 100:0.96V       1.02V
///                                    * 101:0.98V       1.04V
///                                    * 110:1.00V       1.06V
///                                    * 111:1.02V       1.08V
///                                    ###
///               %unsigned 1  TSTMON_EN                 0x0
///                                    ###
///                                    * TESTMON enable signal
///                                    * When TSTMON_EN=0, TP==Z; when TSTMON_EN=1, pass TESTMON[2:0] value
///                                    ###
///               %unsigned 3  TESTMON                   0x0
///                                    ###
///                                    * Analog Test Point
///                                    * If Testmon[2:0] = 000, high Z.
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00080                      (W-)
///     #         # Stuffing bytes...
///               %% 261120
///     @ 0x08000 DDRScramCtrl         (P)
///               %unsigned 1  Secure_Key                0x0
///                                    ###
///                                    * Scrambling Key Security filter enable
///                                    ###
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * 1: Enable scrambling
///                                    * 0: Disable scrambling
///                                    ###
///               %%        30         # Stuffing bits...
///     # 0x08004 DDRScramCtrl1        
///               %unsigned 32 Key0_word0                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 0 of key0
///                                    ###
///     # 0x08008 DDRScramCtrl2        
///               %unsigned 32 Key0_word1                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 1 of key0
///                                    ###
///     # 0x0800C DDRScramCtrl3        
///               %unsigned 32 Key0_word2                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 2 of key0
///                                    ###
///     # 0x08010 DDRScramCtrl4        
///               %unsigned 32 Key0_word3                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 3 of key0
///                                    ###
///     # 0x08014 DDRScramCtrl5        
///               %unsigned 32 Key0_addr                 0x0
///                                    ###
///                                    * Key0 Physical address
///                                    ###
///     # 0x08018 DDRScramCtrl6        
///               %unsigned 32 Key0_mask                 0x0
///                                    ###
///                                    * Key0 address mask
///                                    ###
///     # 0x0801C DDRScramCtrl7        
///               %unsigned 32 Key1_word0                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 0 of key1
///                                    ###
///     # 0x08020 DDRScramCtrl8        
///               %unsigned 32 Key1_word1                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 1 of key1
///                                    ###
///     # 0x08024 DDRScramCtrl9        
///               %unsigned 32 Key1_word2                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 2 of key1
///                                    ###
///     # 0x08028 DDRScramCtrl10       
///               %unsigned 32 Key1_word3                0x0
///                                    ###
///                                    * Key is 128 bits
///                                    * Word 3 of key1
///                                    ###
///     # 0x0802C DDRScramCtrl11       
///               %unsigned 32 Key1_addr                 0x0
///                                    ###
///                                    * Key1 Physical address
///                                    ###
///     # 0x08030 DDRScramCtrl12       
///               %unsigned 32 Key1_mask                 0x0
///                                    ###
///                                    * Key1 address mask
///                                    ###
///     # 0x08034 DDRScramCtrl13       
///               %unsigned 5  W_latency                 0x0
///                                    ###
///                                    * Used to adjust the write latency
///                                    ###
///               %unsigned 5  R_latency                 0x0
///                                    ###
///                                    * Used to adjust the read latency
///                                    ###
///               %unsigned 4  cal_latency               0x0
///                                    ###
///                                    * DDR4 CAL mode Latency setup
///                                    * Scrambler latency programming details are described after this table
///                                    ###
///               %%        18         # Stuffing bits...
///     @ 0x08038 rz_ctrl              (P)
///               %unsigned 8  arrz_pass                 0xFF
///                                    ###
///                                    * Read Restrict Zone control, 1-bit per master
///                                    ###
///               %unsigned 8  awrz_pass                 0x0
///                                    ###
///                                    * Write Restrict Zone Control, 1-bit per master
///                                    ###
///               %%        16         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:   32828B, bits:     830b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MctrlSS
#define h_MctrlSS (){}

    #define     RA_MctrlSS_MC5_4TO1                            0x0000

    #define     BA_MctrlSS_MC5_4TO1_enable                     0x0000
    #define     B16MctrlSS_MC5_4TO1_enable                     0x0000
    #define   LSb32MctrlSS_MC5_4TO1_enable                        0
    #define   LSb16MctrlSS_MC5_4TO1_enable                        0
    #define       bMctrlSS_MC5_4TO1_enable                     1
    #define   MSK32MctrlSS_MC5_4TO1_enable                        0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_AVIO_PRIO                           0x0004

    #define     BA_MctrlSS_AVIO_PRIO_vppDhub                   0x0004
    #define     B16MctrlSS_AVIO_PRIO_vppDhub                   0x0004
    #define   LSb32MctrlSS_AVIO_PRIO_vppDhub                      0
    #define   LSb16MctrlSS_AVIO_PRIO_vppDhub                      0
    #define       bMctrlSS_AVIO_PRIO_vppDhub                   4
    #define   MSK32MctrlSS_AVIO_PRIO_vppDhub                      0x0000000F

    #define     BA_MctrlSS_AVIO_PRIO_agVipDhub                 0x0004
    #define     B16MctrlSS_AVIO_PRIO_agVipDhub                 0x0004
    #define   LSb32MctrlSS_AVIO_PRIO_agVipDhub                    4
    #define   LSb16MctrlSS_AVIO_PRIO_agVipDhub                    4
    #define       bMctrlSS_AVIO_PRIO_agVipDhub                 4
    #define   MSK32MctrlSS_AVIO_PRIO_agVipDhub                    0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_ddrPhyLoopBackSrc                   0x0008

    #define     BA_MctrlSS_ddrPhyLoopBackSrc_Control           0x0008
    #define     B16MctrlSS_ddrPhyLoopBackSrc_Control           0x0008
    #define   LSb32MctrlSS_ddrPhyLoopBackSrc_Control              0
    #define   LSb16MctrlSS_ddrPhyLoopBackSrc_Control              0
    #define       bMctrlSS_ddrPhyLoopBackSrc_Control           1
    #define   MSK32MctrlSS_ddrPhyLoopBackSrc_Control              0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_ddrPhyLoopBackConfig1               0x000C

    #define     BA_MctrlSS_ddrPhyLoopBackConfig1_TST_MODE      0x000C
    #define     B16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE      0x000C
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE         0
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE         0
    #define       bMctrlSS_ddrPhyLoopBackConfig1_TST_MODE      1
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE         0x00000001

    #define     BA_MctrlSS_ddrPhyLoopBackConfig1_TST_START     0x000C
    #define     B16MctrlSS_ddrPhyLoopBackConfig1_TST_START     0x000C
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig1_TST_START        1
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig1_TST_START        1
    #define       bMctrlSS_ddrPhyLoopBackConfig1_TST_START     1
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig1_TST_START        0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_ddrPhyLoopBackConfig2               0x0010

    #define     BA_MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY  0x0010
    #define     B16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY  0x0010
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY     0
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY     0
    #define       bMctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY  5
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY     0x0000001F

    #define     BA_MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1     0x0010
    #define     B16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1     0x0010
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1        5
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1        5
    #define       bMctrlSS_ddrPhyLoopBackConfig2_RSERVRED1     3
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1        0x000000E0

    #define     BA_MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY   0x0011
    #define     B16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY   0x0010
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY      8
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY      8
    #define       bMctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY   5
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY      0x00001F00

    #define     BA_MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2     0x0011
    #define     B16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2     0x0010
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2        13
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2        13
    #define       bMctrlSS_ddrPhyLoopBackConfig2_RSERVRED2     2
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2        0x00006000

    #define     BA_MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 0x0011
    #define     B16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 0x0010
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY    15
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY    15
    #define       bMctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 1
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY    0x00008000
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_ddrPhyLoopBackConfig3               0x0014

    #define     BA_MctrlSS_ddrPhyLoopBackConfig3_SEED          0x0014
    #define     B16MctrlSS_ddrPhyLoopBackConfig3_SEED          0x0014
    #define   LSb32MctrlSS_ddrPhyLoopBackConfig3_SEED             0
    #define   LSb16MctrlSS_ddrPhyLoopBackConfig3_SEED             0
    #define       bMctrlSS_ddrPhyLoopBackConfig3_SEED          32
    #define   MSK32MctrlSS_ddrPhyLoopBackConfig3_SEED             0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_ddrPhyLoopBackStatus1               0x0018

    #define     BA_MctrlSS_ddrPhyLoopBackStatus1_STATUS        0x0018
    #define     B16MctrlSS_ddrPhyLoopBackStatus1_STATUS        0x0018
    #define   LSb32MctrlSS_ddrPhyLoopBackStatus1_STATUS           0
    #define   LSb16MctrlSS_ddrPhyLoopBackStatus1_STATUS           0
    #define       bMctrlSS_ddrPhyLoopBackStatus1_STATUS        16
    #define   MSK32MctrlSS_ddrPhyLoopBackStatus1_STATUS           0x0000FFFF

    #define     BA_MctrlSS_ddrPhyLoopBackStatus1_RESERVED      0x001A
    #define     B16MctrlSS_ddrPhyLoopBackStatus1_RESERVED      0x001A
    #define   LSb32MctrlSS_ddrPhyLoopBackStatus1_RESERVED         16
    #define   LSb16MctrlSS_ddrPhyLoopBackStatus1_RESERVED         0
    #define       bMctrlSS_ddrPhyLoopBackStatus1_RESERVED      16
    #define   MSK32MctrlSS_ddrPhyLoopBackStatus1_RESERVED         0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_ddrPhyLoopBackStatus2               0x001C

    #define     BA_MctrlSS_ddrPhyLoopBackStatus2_DONE          0x001C
    #define     B16MctrlSS_ddrPhyLoopBackStatus2_DONE          0x001C
    #define   LSb32MctrlSS_ddrPhyLoopBackStatus2_DONE             0
    #define   LSb16MctrlSS_ddrPhyLoopBackStatus2_DONE             0
    #define       bMctrlSS_ddrPhyLoopBackStatus2_DONE          1
    #define   MSK32MctrlSS_ddrPhyLoopBackStatus2_DONE             0x00000001

    #define     BA_MctrlSS_ddrPhyLoopBackStatus2_FAIL          0x001C
    #define     B16MctrlSS_ddrPhyLoopBackStatus2_FAIL          0x001C
    #define   LSb32MctrlSS_ddrPhyLoopBackStatus2_FAIL             1
    #define   LSb16MctrlSS_ddrPhyLoopBackStatus2_FAIL             1
    #define       bMctrlSS_ddrPhyLoopBackStatus2_FAIL          1
    #define   MSK32MctrlSS_ddrPhyLoopBackStatus2_FAIL             0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_phy_pd_ctrl                      0x0020

    #define     BA_MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0      0x0020
    #define     B16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0      0x0020
    #define   LSb32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0         0
    #define   LSb16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0         0
    #define       bMctrlSS_mc_phy_pd_ctrl_normal_mode_ch0      1
    #define   MSK32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0         0x00000001

    #define     BA_MctrlSS_mc_phy_pd_ctrl_pd_en_ch0            0x0020
    #define     B16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0            0x0020
    #define   LSb32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0               1
    #define   LSb16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0               1
    #define       bMctrlSS_mc_phy_pd_ctrl_pd_en_ch0            1
    #define   MSK32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0               0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr0_qos                        0x0024

    #define     BA_MctrlSS_mc_mstr0_qos_awqos                  0x0024
    #define     B16MctrlSS_mc_mstr0_qos_awqos                  0x0024
    #define   LSb32MctrlSS_mc_mstr0_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr0_qos_awqos                     0
    #define       bMctrlSS_mc_mstr0_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr0_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr0_qos_arqos                  0x0024
    #define     B16MctrlSS_mc_mstr0_qos_arqos                  0x0024
    #define   LSb32MctrlSS_mc_mstr0_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr0_qos_arqos                     4
    #define       bMctrlSS_mc_mstr0_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr0_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr1_qos                        0x0028

    #define     BA_MctrlSS_mc_mstr1_qos_awqos                  0x0028
    #define     B16MctrlSS_mc_mstr1_qos_awqos                  0x0028
    #define   LSb32MctrlSS_mc_mstr1_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr1_qos_awqos                     0
    #define       bMctrlSS_mc_mstr1_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr1_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr1_qos_arqos                  0x0028
    #define     B16MctrlSS_mc_mstr1_qos_arqos                  0x0028
    #define   LSb32MctrlSS_mc_mstr1_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr1_qos_arqos                     4
    #define       bMctrlSS_mc_mstr1_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr1_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr2_qos                        0x002C

    #define     BA_MctrlSS_mc_mstr2_qos_awqos                  0x002C
    #define     B16MctrlSS_mc_mstr2_qos_awqos                  0x002C
    #define   LSb32MctrlSS_mc_mstr2_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr2_qos_awqos                     0
    #define       bMctrlSS_mc_mstr2_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr2_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr2_qos_arqos                  0x002C
    #define     B16MctrlSS_mc_mstr2_qos_arqos                  0x002C
    #define   LSb32MctrlSS_mc_mstr2_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr2_qos_arqos                     4
    #define       bMctrlSS_mc_mstr2_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr2_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr3_qos                        0x0030

    #define     BA_MctrlSS_mc_mstr3_qos_awqos                  0x0030
    #define     B16MctrlSS_mc_mstr3_qos_awqos                  0x0030
    #define   LSb32MctrlSS_mc_mstr3_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr3_qos_awqos                     0
    #define       bMctrlSS_mc_mstr3_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr3_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr3_qos_arqos                  0x0030
    #define     B16MctrlSS_mc_mstr3_qos_arqos                  0x0030
    #define   LSb32MctrlSS_mc_mstr3_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr3_qos_arqos                     4
    #define       bMctrlSS_mc_mstr3_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr3_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr4_qos                        0x0034

    #define     BA_MctrlSS_mc_mstr4_qos_awqos                  0x0034
    #define     B16MctrlSS_mc_mstr4_qos_awqos                  0x0034
    #define   LSb32MctrlSS_mc_mstr4_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr4_qos_awqos                     0
    #define       bMctrlSS_mc_mstr4_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr4_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr4_qos_arqos                  0x0034
    #define     B16MctrlSS_mc_mstr4_qos_arqos                  0x0034
    #define   LSb32MctrlSS_mc_mstr4_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr4_qos_arqos                     4
    #define       bMctrlSS_mc_mstr4_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr4_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr5_qos                        0x0038

    #define     BA_MctrlSS_mc_mstr5_qos_awqos                  0x0038
    #define     B16MctrlSS_mc_mstr5_qos_awqos                  0x0038
    #define   LSb32MctrlSS_mc_mstr5_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr5_qos_awqos                     0
    #define       bMctrlSS_mc_mstr5_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr5_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr5_qos_arqos                  0x0038
    #define     B16MctrlSS_mc_mstr5_qos_arqos                  0x0038
    #define   LSb32MctrlSS_mc_mstr5_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr5_qos_arqos                     4
    #define       bMctrlSS_mc_mstr5_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr5_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr6_qos                        0x003C

    #define     BA_MctrlSS_mc_mstr6_qos_awqos                  0x003C
    #define     B16MctrlSS_mc_mstr6_qos_awqos                  0x003C
    #define   LSb32MctrlSS_mc_mstr6_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr6_qos_awqos                     0
    #define       bMctrlSS_mc_mstr6_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr6_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr6_qos_arqos                  0x003C
    #define     B16MctrlSS_mc_mstr6_qos_arqos                  0x003C
    #define   LSb32MctrlSS_mc_mstr6_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr6_qos_arqos                     4
    #define       bMctrlSS_mc_mstr6_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr6_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_mstr7_qos                        0x0040

    #define     BA_MctrlSS_mc_mstr7_qos_awqos                  0x0040
    #define     B16MctrlSS_mc_mstr7_qos_awqos                  0x0040
    #define   LSb32MctrlSS_mc_mstr7_qos_awqos                     0
    #define   LSb16MctrlSS_mc_mstr7_qos_awqos                     0
    #define       bMctrlSS_mc_mstr7_qos_awqos                  4
    #define   MSK32MctrlSS_mc_mstr7_qos_awqos                     0x0000000F

    #define     BA_MctrlSS_mc_mstr7_qos_arqos                  0x0040
    #define     B16MctrlSS_mc_mstr7_qos_arqos                  0x0040
    #define   LSb32MctrlSS_mc_mstr7_qos_arqos                     4
    #define   LSb16MctrlSS_mc_mstr7_qos_arqos                     4
    #define       bMctrlSS_mc_mstr7_qos_arqos                  4
    #define   MSK32MctrlSS_mc_mstr7_qos_arqos                     0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_hw_phy_dll_update_req            0x0044

    #define     BA_MctrlSS_mc_hw_phy_dll_update_req_en         0x0044
    #define     B16MctrlSS_mc_hw_phy_dll_update_req_en         0x0044
    #define   LSb32MctrlSS_mc_hw_phy_dll_update_req_en            0
    #define   LSb16MctrlSS_mc_hw_phy_dll_update_req_en            0
    #define       bMctrlSS_mc_hw_phy_dll_update_req_en         1
    #define   MSK32MctrlSS_mc_hw_phy_dll_update_req_en            0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_hw_dfc_ctrl                      0x0048

    #define     BA_MctrlSS_mc_hw_dfc_ctrl_reg_table_req        0x0048
    #define     B16MctrlSS_mc_hw_dfc_ctrl_reg_table_req        0x0048
    #define   LSb32MctrlSS_mc_hw_dfc_ctrl_reg_table_req           0
    #define   LSb16MctrlSS_mc_hw_dfc_ctrl_reg_table_req           0
    #define       bMctrlSS_mc_hw_dfc_ctrl_reg_table_req        1
    #define   MSK32MctrlSS_mc_hw_dfc_ctrl_reg_table_req           0x00000001

    #define     BA_MctrlSS_mc_hw_dfc_ctrl_reg_table_type       0x0048
    #define     B16MctrlSS_mc_hw_dfc_ctrl_reg_table_type       0x0048
    #define   LSb32MctrlSS_mc_hw_dfc_ctrl_reg_table_type          1
    #define   LSb16MctrlSS_mc_hw_dfc_ctrl_reg_table_type          1
    #define       bMctrlSS_mc_hw_dfc_ctrl_reg_table_type       5
    #define   MSK32MctrlSS_mc_hw_dfc_ctrl_reg_table_type          0x0000003E

    #define     BA_MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack   0x0048
    #define     B16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack   0x0048
    #define   LSb32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack      6
    #define   LSb16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack      6
    #define       bMctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack   1
    #define   MSK32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack      0x00000040

    #define     BA_MctrlSS_mc_hw_dfc_ctrl_sleep_req            0x0048
    #define     B16MctrlSS_mc_hw_dfc_ctrl_sleep_req            0x0048
    #define   LSb32MctrlSS_mc_hw_dfc_ctrl_sleep_req               7
    #define   LSb16MctrlSS_mc_hw_dfc_ctrl_sleep_req               7
    #define       bMctrlSS_mc_hw_dfc_ctrl_sleep_req            1
    #define   MSK32MctrlSS_mc_hw_dfc_ctrl_sleep_req               0x00000080

    #define     BA_MctrlSS_mc_hw_dfc_ctrl_sleep_type           0x0049
    #define     B16MctrlSS_mc_hw_dfc_ctrl_sleep_type           0x0048
    #define   LSb32MctrlSS_mc_hw_dfc_ctrl_sleep_type              8
    #define   LSb16MctrlSS_mc_hw_dfc_ctrl_sleep_type              8
    #define       bMctrlSS_mc_hw_dfc_ctrl_sleep_type           3
    #define   MSK32MctrlSS_mc_hw_dfc_ctrl_sleep_type              0x00000700
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_mc_hw_dfc_sts                       0x004C

    #define     BA_MctrlSS_mc_hw_dfc_sts_reg_table_req_ack     0x004C
    #define     B16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack     0x004C
    #define   LSb32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack        0
    #define   LSb16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack        0
    #define       bMctrlSS_mc_hw_dfc_sts_reg_table_req_ack     1
    #define   MSK32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack        0x00000001

    #define     BA_MctrlSS_mc_hw_dfc_sts_reg_table_wait_req    0x004C
    #define     B16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req    0x004C
    #define   LSb32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req       1
    #define   LSb16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req       1
    #define       bMctrlSS_mc_hw_dfc_sts_reg_table_wait_req    1
    #define   MSK32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req       0x00000002

    #define     BA_MctrlSS_mc_hw_dfc_sts_sleep_req_ack         0x004C
    #define     B16MctrlSS_mc_hw_dfc_sts_sleep_req_ack         0x004C
    #define   LSb32MctrlSS_mc_hw_dfc_sts_sleep_req_ack            2
    #define   LSb16MctrlSS_mc_hw_dfc_sts_sleep_req_ack            2
    #define       bMctrlSS_mc_hw_dfc_sts_sleep_req_ack         1
    #define   MSK32MctrlSS_mc_hw_dfc_sts_sleep_req_ack            0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_memPll                              0x0050
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_RWTC_31to0                          0x0068

    #define     BA_MctrlSS_RWTC_31to0_value                    0x0068
    #define     B16MctrlSS_RWTC_31to0_value                    0x0068
    #define   LSb32MctrlSS_RWTC_31to0_value                       0
    #define   LSb16MctrlSS_RWTC_31to0_value                       0
    #define       bMctrlSS_RWTC_31to0_value                    32
    #define   MSK32MctrlSS_RWTC_31to0_value                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_RWTC_57to32                         0x006C

    #define     BA_MctrlSS_RWTC_57to32_value                   0x006C
    #define     B16MctrlSS_RWTC_57to32_value                   0x006C
    #define   LSb32MctrlSS_RWTC_57to32_value                      0
    #define   LSb16MctrlSS_RWTC_57to32_value                      0
    #define       bMctrlSS_RWTC_57to32_value                   26
    #define   MSK32MctrlSS_RWTC_57to32_value                      0x03FFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_DDRCLK_VREG_CTRL_0                  0x0070

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_0_PU               0x0070
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_0_PU               0x0070
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_0_PU                  0
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_0_PU                  0
    #define       bMctrlSS_DDRCLK_VREG_CTRL_0_PU               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_0_PU                  0x00000001

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_0_LP               0x0070
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_0_LP               0x0070
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_0_LP                  1
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_0_LP                  1
    #define       bMctrlSS_DDRCLK_VREG_CTRL_0_LP               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_0_LP                  0x00000002

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS           0x0070
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS           0x0070
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS              2
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS              2
    #define       bMctrlSS_DDRCLK_VREG_CTRL_0_BYPASS           1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS              0x00000004

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_0_VSEL             0x0070
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL             0x0070
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL                3
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL                3
    #define       bMctrlSS_DDRCLK_VREG_CTRL_0_VSEL             3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL                0x00000038

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN        0x0070
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN        0x0070
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN           6
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN           6
    #define       bMctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN        1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN           0x00000040

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON          0x0070
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON          0x0070
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON             7
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON             7
    #define       bMctrlSS_DDRCLK_VREG_CTRL_0_TESTMON          3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON             0x00000380
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_DDRCLK_VREG_CTRL_1                  0x0074

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_1_PU               0x0074
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_1_PU               0x0074
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_1_PU                  0
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_1_PU                  0
    #define       bMctrlSS_DDRCLK_VREG_CTRL_1_PU               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_1_PU                  0x00000001

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_1_LP               0x0074
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_1_LP               0x0074
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_1_LP                  1
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_1_LP                  1
    #define       bMctrlSS_DDRCLK_VREG_CTRL_1_LP               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_1_LP                  0x00000002

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS           0x0074
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS           0x0074
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS              2
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS              2
    #define       bMctrlSS_DDRCLK_VREG_CTRL_1_BYPASS           1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS              0x00000004

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_1_VSEL             0x0074
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL             0x0074
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL                3
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL                3
    #define       bMctrlSS_DDRCLK_VREG_CTRL_1_VSEL             3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL                0x00000038

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN        0x0074
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN        0x0074
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN           6
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN           6
    #define       bMctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN        1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN           0x00000040

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON          0x0074
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON          0x0074
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON             7
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON             7
    #define       bMctrlSS_DDRCLK_VREG_CTRL_1_TESTMON          3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON             0x00000380
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_DDRCLK_VREG_CTRL_2                  0x0078

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_2_PU               0x0078
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_2_PU               0x0078
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_2_PU                  0
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_2_PU                  0
    #define       bMctrlSS_DDRCLK_VREG_CTRL_2_PU               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_2_PU                  0x00000001

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_2_LP               0x0078
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_2_LP               0x0078
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_2_LP                  1
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_2_LP                  1
    #define       bMctrlSS_DDRCLK_VREG_CTRL_2_LP               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_2_LP                  0x00000002

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS           0x0078
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS           0x0078
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS              2
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS              2
    #define       bMctrlSS_DDRCLK_VREG_CTRL_2_BYPASS           1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS              0x00000004

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_2_VSEL             0x0078
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL             0x0078
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL                3
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL                3
    #define       bMctrlSS_DDRCLK_VREG_CTRL_2_VSEL             3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL                0x00000038

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN        0x0078
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN        0x0078
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN           6
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN           6
    #define       bMctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN        1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN           0x00000040

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON          0x0078
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON          0x0078
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON             7
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON             7
    #define       bMctrlSS_DDRCLK_VREG_CTRL_2_TESTMON          3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON             0x00000380
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_DDRCLK_VREG_CTRL_3                  0x007C

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_3_PU               0x007C
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_3_PU               0x007C
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_3_PU                  0
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_3_PU                  0
    #define       bMctrlSS_DDRCLK_VREG_CTRL_3_PU               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_3_PU                  0x00000001

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_3_LP               0x007C
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_3_LP               0x007C
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_3_LP                  1
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_3_LP                  1
    #define       bMctrlSS_DDRCLK_VREG_CTRL_3_LP               1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_3_LP                  0x00000002

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS           0x007C
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS           0x007C
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS              2
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS              2
    #define       bMctrlSS_DDRCLK_VREG_CTRL_3_BYPASS           1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS              0x00000004

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_3_VSEL             0x007C
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL             0x007C
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL                3
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL                3
    #define       bMctrlSS_DDRCLK_VREG_CTRL_3_VSEL             3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL                0x00000038

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN        0x007C
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN        0x007C
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN           6
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN           6
    #define       bMctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN        1
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN           0x00000040

    #define     BA_MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON          0x007C
    #define     B16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON          0x007C
    #define   LSb32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON             7
    #define   LSb16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON             7
    #define       bMctrlSS_DDRCLK_VREG_CTRL_3_TESTMON          3
    #define   MSK32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON             0x00000380
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_DDRScramCtrl                        0x8000

    #define     BA_MctrlSS_DDRScramCtrl_Secure_Key             0x8000
    #define     B16MctrlSS_DDRScramCtrl_Secure_Key             0x8000
    #define   LSb32MctrlSS_DDRScramCtrl_Secure_Key                0
    #define   LSb16MctrlSS_DDRScramCtrl_Secure_Key                0
    #define       bMctrlSS_DDRScramCtrl_Secure_Key             1
    #define   MSK32MctrlSS_DDRScramCtrl_Secure_Key                0x00000001

    #define     BA_MctrlSS_DDRScramCtrl_En                     0x8000
    #define     B16MctrlSS_DDRScramCtrl_En                     0x8000
    #define   LSb32MctrlSS_DDRScramCtrl_En                        1
    #define   LSb16MctrlSS_DDRScramCtrl_En                        1
    #define       bMctrlSS_DDRScramCtrl_En                     1
    #define   MSK32MctrlSS_DDRScramCtrl_En                        0x00000002

    #define     RA_MctrlSS_DDRScramCtrl1                       0x8004

    #define     BA_MctrlSS_DDRScramCtrl_Key0_word0             0x8004
    #define     B16MctrlSS_DDRScramCtrl_Key0_word0             0x8004
    #define   LSb32MctrlSS_DDRScramCtrl_Key0_word0                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key0_word0                0
    #define       bMctrlSS_DDRScramCtrl_Key0_word0             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key0_word0                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl2                       0x8008

    #define     BA_MctrlSS_DDRScramCtrl_Key0_word1             0x8008
    #define     B16MctrlSS_DDRScramCtrl_Key0_word1             0x8008
    #define   LSb32MctrlSS_DDRScramCtrl_Key0_word1                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key0_word1                0
    #define       bMctrlSS_DDRScramCtrl_Key0_word1             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key0_word1                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl3                       0x800C

    #define     BA_MctrlSS_DDRScramCtrl_Key0_word2             0x800C
    #define     B16MctrlSS_DDRScramCtrl_Key0_word2             0x800C
    #define   LSb32MctrlSS_DDRScramCtrl_Key0_word2                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key0_word2                0
    #define       bMctrlSS_DDRScramCtrl_Key0_word2             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key0_word2                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl4                       0x8010

    #define     BA_MctrlSS_DDRScramCtrl_Key0_word3             0x8010
    #define     B16MctrlSS_DDRScramCtrl_Key0_word3             0x8010
    #define   LSb32MctrlSS_DDRScramCtrl_Key0_word3                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key0_word3                0
    #define       bMctrlSS_DDRScramCtrl_Key0_word3             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key0_word3                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl5                       0x8014

    #define     BA_MctrlSS_DDRScramCtrl_Key0_addr              0x8014
    #define     B16MctrlSS_DDRScramCtrl_Key0_addr              0x8014
    #define   LSb32MctrlSS_DDRScramCtrl_Key0_addr                 0
    #define   LSb16MctrlSS_DDRScramCtrl_Key0_addr                 0
    #define       bMctrlSS_DDRScramCtrl_Key0_addr              32
    #define   MSK32MctrlSS_DDRScramCtrl_Key0_addr                 0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl6                       0x8018

    #define     BA_MctrlSS_DDRScramCtrl_Key0_mask              0x8018
    #define     B16MctrlSS_DDRScramCtrl_Key0_mask              0x8018
    #define   LSb32MctrlSS_DDRScramCtrl_Key0_mask                 0
    #define   LSb16MctrlSS_DDRScramCtrl_Key0_mask                 0
    #define       bMctrlSS_DDRScramCtrl_Key0_mask              32
    #define   MSK32MctrlSS_DDRScramCtrl_Key0_mask                 0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl7                       0x801C

    #define     BA_MctrlSS_DDRScramCtrl_Key1_word0             0x801C
    #define     B16MctrlSS_DDRScramCtrl_Key1_word0             0x801C
    #define   LSb32MctrlSS_DDRScramCtrl_Key1_word0                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key1_word0                0
    #define       bMctrlSS_DDRScramCtrl_Key1_word0             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key1_word0                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl8                       0x8020

    #define     BA_MctrlSS_DDRScramCtrl_Key1_word1             0x8020
    #define     B16MctrlSS_DDRScramCtrl_Key1_word1             0x8020
    #define   LSb32MctrlSS_DDRScramCtrl_Key1_word1                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key1_word1                0
    #define       bMctrlSS_DDRScramCtrl_Key1_word1             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key1_word1                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl9                       0x8024

    #define     BA_MctrlSS_DDRScramCtrl_Key1_word2             0x8024
    #define     B16MctrlSS_DDRScramCtrl_Key1_word2             0x8024
    #define   LSb32MctrlSS_DDRScramCtrl_Key1_word2                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key1_word2                0
    #define       bMctrlSS_DDRScramCtrl_Key1_word2             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key1_word2                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl10                      0x8028

    #define     BA_MctrlSS_DDRScramCtrl_Key1_word3             0x8028
    #define     B16MctrlSS_DDRScramCtrl_Key1_word3             0x8028
    #define   LSb32MctrlSS_DDRScramCtrl_Key1_word3                0
    #define   LSb16MctrlSS_DDRScramCtrl_Key1_word3                0
    #define       bMctrlSS_DDRScramCtrl_Key1_word3             32
    #define   MSK32MctrlSS_DDRScramCtrl_Key1_word3                0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl11                      0x802C

    #define     BA_MctrlSS_DDRScramCtrl_Key1_addr              0x802C
    #define     B16MctrlSS_DDRScramCtrl_Key1_addr              0x802C
    #define   LSb32MctrlSS_DDRScramCtrl_Key1_addr                 0
    #define   LSb16MctrlSS_DDRScramCtrl_Key1_addr                 0
    #define       bMctrlSS_DDRScramCtrl_Key1_addr              32
    #define   MSK32MctrlSS_DDRScramCtrl_Key1_addr                 0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl12                      0x8030

    #define     BA_MctrlSS_DDRScramCtrl_Key1_mask              0x8030
    #define     B16MctrlSS_DDRScramCtrl_Key1_mask              0x8030
    #define   LSb32MctrlSS_DDRScramCtrl_Key1_mask                 0
    #define   LSb16MctrlSS_DDRScramCtrl_Key1_mask                 0
    #define       bMctrlSS_DDRScramCtrl_Key1_mask              32
    #define   MSK32MctrlSS_DDRScramCtrl_Key1_mask                 0xFFFFFFFF

    #define     RA_MctrlSS_DDRScramCtrl13                      0x8034

    #define     BA_MctrlSS_DDRScramCtrl_W_latency              0x8034
    #define     B16MctrlSS_DDRScramCtrl_W_latency              0x8034
    #define   LSb32MctrlSS_DDRScramCtrl_W_latency                 0
    #define   LSb16MctrlSS_DDRScramCtrl_W_latency                 0
    #define       bMctrlSS_DDRScramCtrl_W_latency              5
    #define   MSK32MctrlSS_DDRScramCtrl_W_latency                 0x0000001F

    #define     BA_MctrlSS_DDRScramCtrl_R_latency              0x8034
    #define     B16MctrlSS_DDRScramCtrl_R_latency              0x8034
    #define   LSb32MctrlSS_DDRScramCtrl_R_latency                 5
    #define   LSb16MctrlSS_DDRScramCtrl_R_latency                 5
    #define       bMctrlSS_DDRScramCtrl_R_latency              5
    #define   MSK32MctrlSS_DDRScramCtrl_R_latency                 0x000003E0

    #define     BA_MctrlSS_DDRScramCtrl_cal_latency            0x8035
    #define     B16MctrlSS_DDRScramCtrl_cal_latency            0x8034
    #define   LSb32MctrlSS_DDRScramCtrl_cal_latency               10
    #define   LSb16MctrlSS_DDRScramCtrl_cal_latency               10
    #define       bMctrlSS_DDRScramCtrl_cal_latency            4
    #define   MSK32MctrlSS_DDRScramCtrl_cal_latency               0x00003C00
    ///////////////////////////////////////////////////////////
    #define     RA_MctrlSS_rz_ctrl                             0x8038

    #define     BA_MctrlSS_rz_ctrl_arrz_pass                   0x8038
    #define     B16MctrlSS_rz_ctrl_arrz_pass                   0x8038
    #define   LSb32MctrlSS_rz_ctrl_arrz_pass                      0
    #define   LSb16MctrlSS_rz_ctrl_arrz_pass                      0
    #define       bMctrlSS_rz_ctrl_arrz_pass                   8
    #define   MSK32MctrlSS_rz_ctrl_arrz_pass                      0x000000FF

    #define     BA_MctrlSS_rz_ctrl_awrz_pass                   0x8039
    #define     B16MctrlSS_rz_ctrl_awrz_pass                   0x8038
    #define   LSb32MctrlSS_rz_ctrl_awrz_pass                      8
    #define   LSb16MctrlSS_rz_ctrl_awrz_pass                      8
    #define       bMctrlSS_rz_ctrl_awrz_pass                   8
    #define   MSK32MctrlSS_rz_ctrl_awrz_pass                      0x0000FF00
    ///////////////////////////////////////////////////////////

    typedef struct SIE_MctrlSS {
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_MC5_4TO1_enable(r32)                _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_MC5_4TO1_enable(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_MC5_4TO1_enable(r16)                _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_MC5_4TO1_enable(r16,v)              _BFSET_(r16, 0, 0,v)

    #define     w32MctrlSS_MC5_4TO1                            {\
            UNSG32 uMC5_4TO1_enable                            :  1;\
            UNSG32 RSVDx0_b1                                   : 31;\
          }
    union { UNSG32 u32MctrlSS_MC5_4TO1;
            struct w32MctrlSS_MC5_4TO1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_AVIO_PRIO_vppDhub(r32)              _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_AVIO_PRIO_vppDhub(r32,v)            _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_AVIO_PRIO_vppDhub(r16)              _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_AVIO_PRIO_vppDhub(r16,v)            _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_AVIO_PRIO_agVipDhub(r32)            _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_AVIO_PRIO_agVipDhub(r32,v)          _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_AVIO_PRIO_agVipDhub(r16)            _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_AVIO_PRIO_agVipDhub(r16,v)          _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_AVIO_PRIO                           {\
            UNSG32 uAVIO_PRIO_vppDhub                          :  4;\
            UNSG32 uAVIO_PRIO_agVipDhub                        :  4;\
            UNSG32 RSVDx4_b8                                   : 24;\
          }
    union { UNSG32 u32MctrlSS_AVIO_PRIO;
            struct w32MctrlSS_AVIO_PRIO;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_ddrPhyLoopBackSrc_Control(r32)      _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_ddrPhyLoopBackSrc_Control(r32,v)    _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_ddrPhyLoopBackSrc_Control(r16)      _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_ddrPhyLoopBackSrc_Control(r16,v)    _BFSET_(r16, 0, 0,v)

    #define     w32MctrlSS_ddrPhyLoopBackSrc                   {\
            UNSG32 uddrPhyLoopBackSrc_Control                  :  1;\
            UNSG32 RSVDx8_b1                                   : 31;\
          }
    union { UNSG32 u32MctrlSS_ddrPhyLoopBackSrc;
            struct w32MctrlSS_ddrPhyLoopBackSrc;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r32) _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r16) _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_ddrPhyLoopBackConfig1_TST_START(r32) _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig1_TST_START(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig1_TST_START(r16) _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig1_TST_START(r16,v) _BFSET_(r16, 1, 1,v)

    #define     w32MctrlSS_ddrPhyLoopBackConfig1               {\
            UNSG32 uddrPhyLoopBackConfig1_TST_MODE             :  1;\
            UNSG32 uddrPhyLoopBackConfig1_TST_START            :  1;\
            UNSG32 RSVDxC_b2                                   : 30;\
          }
    union { UNSG32 u32MctrlSS_ddrPhyLoopBackConfig1;
            struct w32MctrlSS_ddrPhyLoopBackConfig1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r32) _BFGET_(r32, 4, 0)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r32,v) _BFSET_(r32, 4, 0,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r16) _BFGET_(r16, 4, 0)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r16,v) _BFSET_(r16, 4, 0,v)

    #define   GET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r32) _BFGET_(r32, 7, 5)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r32,v) _BFSET_(r32, 7, 5,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r16) _BFGET_(r16, 7, 5)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r16,v) _BFSET_(r16, 7, 5,v)

    #define   GET32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r32) _BFGET_(r32,12, 8)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r32,v) _BFSET_(r32,12, 8,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r16) _BFGET_(r16,12, 8)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r16,v) _BFSET_(r16,12, 8,v)

    #define   GET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r32) _BFGET_(r32,14,13)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r32,v) _BFSET_(r32,14,13,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r16) _BFGET_(r16,14,13)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r16,v) _BFSET_(r16,14,13,v)

    #define   GET32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r32) _BFGET_(r32,15,15)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r32,v) _BFSET_(r32,15,15,v)
    #define   GET16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r16) _BFGET_(r16,15,15)
    #define   SET16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r16,v) _BFSET_(r16,15,15,v)

    #define     w32MctrlSS_ddrPhyLoopBackConfig2               {\
            UNSG32 uddrPhyLoopBackConfig2_CFG_DATA_DLY         :  5;\
            UNSG32 uddrPhyLoopBackConfig2_RSERVRED1            :  3;\
            UNSG32 uddrPhyLoopBackConfig2_CFG_ADC_DLY          :  5;\
            UNSG32 uddrPhyLoopBackConfig2_RSERVRED2            :  2;\
            UNSG32 uddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY      :  1;\
            UNSG32 RSVDx10_b16                                 : 16;\
          }
    union { UNSG32 u32MctrlSS_ddrPhyLoopBackConfig2;
            struct w32MctrlSS_ddrPhyLoopBackConfig2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_ddrPhyLoopBackConfig3_SEED(r32)     _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_ddrPhyLoopBackConfig3_SEED(r32,v)   _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_ddrPhyLoopBackConfig3               {\
            UNSG32 uddrPhyLoopBackConfig3_SEED                 : 32;\
          }
    union { UNSG32 u32MctrlSS_ddrPhyLoopBackConfig3;
            struct w32MctrlSS_ddrPhyLoopBackConfig3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_ddrPhyLoopBackStatus1_STATUS(r32)   _BFGET_(r32,15, 0)
    #define   SET32MctrlSS_ddrPhyLoopBackStatus1_STATUS(r32,v) _BFSET_(r32,15, 0,v)
    #define   GET16MctrlSS_ddrPhyLoopBackStatus1_STATUS(r16)   _BFGET_(r16,15, 0)
    #define   SET16MctrlSS_ddrPhyLoopBackStatus1_STATUS(r16,v) _BFSET_(r16,15, 0,v)

    #define   GET32MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r32) _BFGET_(r32,31,16)
    #define   SET32MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r32,v) _BFSET_(r32,31,16,v)
    #define   GET16MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r16) _BFGET_(r16,15, 0)
    #define   SET16MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r16,v) _BFSET_(r16,15, 0,v)

    #define     w32MctrlSS_ddrPhyLoopBackStatus1               {\
            UNSG32 uddrPhyLoopBackStatus1_STATUS               : 16;\
            UNSG32 uddrPhyLoopBackStatus1_RESERVED             : 16;\
          }
    union { UNSG32 u32MctrlSS_ddrPhyLoopBackStatus1;
            struct w32MctrlSS_ddrPhyLoopBackStatus1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_ddrPhyLoopBackStatus2_DONE(r32)     _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_ddrPhyLoopBackStatus2_DONE(r32,v)   _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_ddrPhyLoopBackStatus2_DONE(r16)     _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_ddrPhyLoopBackStatus2_DONE(r16,v)   _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_ddrPhyLoopBackStatus2_FAIL(r32)     _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_ddrPhyLoopBackStatus2_FAIL(r32,v)   _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_ddrPhyLoopBackStatus2_FAIL(r16)     _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_ddrPhyLoopBackStatus2_FAIL(r16,v)   _BFSET_(r16, 1, 1,v)

    #define     w32MctrlSS_ddrPhyLoopBackStatus2               {\
            UNSG32 uddrPhyLoopBackStatus2_DONE                 :  1;\
            UNSG32 uddrPhyLoopBackStatus2_FAIL                 :  1;\
            UNSG32 RSVDx1C_b2                                  : 30;\
          }
    union { UNSG32 u32MctrlSS_ddrPhyLoopBackStatus2;
            struct w32MctrlSS_ddrPhyLoopBackStatus2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r32) _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r16) _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r32)       _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r16)       _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r16,v)     _BFSET_(r16, 1, 1,v)

    #define     w32MctrlSS_mc_phy_pd_ctrl                      {\
            UNSG32 umc_phy_pd_ctrl_normal_mode_ch0             :  1;\
            UNSG32 umc_phy_pd_ctrl_pd_en_ch0                   :  1;\
            UNSG32 RSVDx20_b2                                  : 30;\
          }
    union { UNSG32 u32MctrlSS_mc_phy_pd_ctrl;
            struct w32MctrlSS_mc_phy_pd_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr0_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr0_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr0_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr0_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr0_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr0_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr0_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr0_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr0_qos                        {\
            UNSG32 umc_mstr0_qos_awqos                         :  4;\
            UNSG32 umc_mstr0_qos_arqos                         :  4;\
            UNSG32 RSVDx24_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr0_qos;
            struct w32MctrlSS_mc_mstr0_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr1_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr1_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr1_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr1_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr1_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr1_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr1_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr1_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr1_qos                        {\
            UNSG32 umc_mstr1_qos_awqos                         :  4;\
            UNSG32 umc_mstr1_qos_arqos                         :  4;\
            UNSG32 RSVDx28_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr1_qos;
            struct w32MctrlSS_mc_mstr1_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr2_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr2_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr2_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr2_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr2_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr2_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr2_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr2_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr2_qos                        {\
            UNSG32 umc_mstr2_qos_awqos                         :  4;\
            UNSG32 umc_mstr2_qos_arqos                         :  4;\
            UNSG32 RSVDx2C_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr2_qos;
            struct w32MctrlSS_mc_mstr2_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr3_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr3_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr3_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr3_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr3_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr3_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr3_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr3_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr3_qos                        {\
            UNSG32 umc_mstr3_qos_awqos                         :  4;\
            UNSG32 umc_mstr3_qos_arqos                         :  4;\
            UNSG32 RSVDx30_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr3_qos;
            struct w32MctrlSS_mc_mstr3_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr4_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr4_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr4_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr4_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr4_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr4_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr4_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr4_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr4_qos                        {\
            UNSG32 umc_mstr4_qos_awqos                         :  4;\
            UNSG32 umc_mstr4_qos_arqos                         :  4;\
            UNSG32 RSVDx34_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr4_qos;
            struct w32MctrlSS_mc_mstr4_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr5_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr5_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr5_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr5_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr5_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr5_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr5_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr5_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr5_qos                        {\
            UNSG32 umc_mstr5_qos_awqos                         :  4;\
            UNSG32 umc_mstr5_qos_arqos                         :  4;\
            UNSG32 RSVDx38_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr5_qos;
            struct w32MctrlSS_mc_mstr5_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr6_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr6_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr6_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr6_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr6_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr6_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr6_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr6_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr6_qos                        {\
            UNSG32 umc_mstr6_qos_awqos                         :  4;\
            UNSG32 umc_mstr6_qos_arqos                         :  4;\
            UNSG32 RSVDx3C_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr6_qos;
            struct w32MctrlSS_mc_mstr6_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_mstr7_qos_awqos(r32)             _BFGET_(r32, 3, 0)
    #define   SET32MctrlSS_mc_mstr7_qos_awqos(r32,v)           _BFSET_(r32, 3, 0,v)
    #define   GET16MctrlSS_mc_mstr7_qos_awqos(r16)             _BFGET_(r16, 3, 0)
    #define   SET16MctrlSS_mc_mstr7_qos_awqos(r16,v)           _BFSET_(r16, 3, 0,v)

    #define   GET32MctrlSS_mc_mstr7_qos_arqos(r32)             _BFGET_(r32, 7, 4)
    #define   SET32MctrlSS_mc_mstr7_qos_arqos(r32,v)           _BFSET_(r32, 7, 4,v)
    #define   GET16MctrlSS_mc_mstr7_qos_arqos(r16)             _BFGET_(r16, 7, 4)
    #define   SET16MctrlSS_mc_mstr7_qos_arqos(r16,v)           _BFSET_(r16, 7, 4,v)

    #define     w32MctrlSS_mc_mstr7_qos                        {\
            UNSG32 umc_mstr7_qos_awqos                         :  4;\
            UNSG32 umc_mstr7_qos_arqos                         :  4;\
            UNSG32 RSVDx40_b8                                  : 24;\
          }
    union { UNSG32 u32MctrlSS_mc_mstr7_qos;
            struct w32MctrlSS_mc_mstr7_qos;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_hw_phy_dll_update_req_en(r32)    _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_mc_hw_phy_dll_update_req_en(r32,v)  _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_mc_hw_phy_dll_update_req_en(r16)    _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_mc_hw_phy_dll_update_req_en(r16,v)  _BFSET_(r16, 0, 0,v)

    #define     w32MctrlSS_mc_hw_phy_dll_update_req            {\
            UNSG32 umc_hw_phy_dll_update_req_en                :  1;\
            UNSG32 RSVDx44_b1                                  : 31;\
          }
    union { UNSG32 u32MctrlSS_mc_hw_phy_dll_update_req;
            struct w32MctrlSS_mc_hw_phy_dll_update_req;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r32)   _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r16)   _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r32)  _BFGET_(r32, 5, 1)
    #define   SET32MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r32,v) _BFSET_(r32, 5, 1,v)
    #define   GET16MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r16)  _BFGET_(r16, 5, 1)
    #define   SET16MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r16,v) _BFSET_(r16, 5, 1,v)

    #define   GET32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r32) _BFGET_(r32, 6, 6)
    #define   SET32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r16) _BFGET_(r16, 6, 6)
    #define   SET16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32MctrlSS_mc_hw_dfc_ctrl_sleep_req(r32)       _BFGET_(r32, 7, 7)
    #define   SET32MctrlSS_mc_hw_dfc_ctrl_sleep_req(r32,v)     _BFSET_(r32, 7, 7,v)
    #define   GET16MctrlSS_mc_hw_dfc_ctrl_sleep_req(r16)       _BFGET_(r16, 7, 7)
    #define   SET16MctrlSS_mc_hw_dfc_ctrl_sleep_req(r16,v)     _BFSET_(r16, 7, 7,v)

    #define   GET32MctrlSS_mc_hw_dfc_ctrl_sleep_type(r32)      _BFGET_(r32,10, 8)
    #define   SET32MctrlSS_mc_hw_dfc_ctrl_sleep_type(r32,v)    _BFSET_(r32,10, 8,v)
    #define   GET16MctrlSS_mc_hw_dfc_ctrl_sleep_type(r16)      _BFGET_(r16,10, 8)
    #define   SET16MctrlSS_mc_hw_dfc_ctrl_sleep_type(r16,v)    _BFSET_(r16,10, 8,v)

    #define     w32MctrlSS_mc_hw_dfc_ctrl                      {\
            UNSG32 umc_hw_dfc_ctrl_reg_table_req               :  1;\
            UNSG32 umc_hw_dfc_ctrl_reg_table_type              :  5;\
            UNSG32 umc_hw_dfc_ctrl_reg_table_wait_ack          :  1;\
            UNSG32 umc_hw_dfc_ctrl_sleep_req                   :  1;\
            UNSG32 umc_hw_dfc_ctrl_sleep_type                  :  3;\
            UNSG32 RSVDx48_b11                                 : 21;\
          }
    union { UNSG32 u32MctrlSS_mc_hw_dfc_ctrl;
            struct w32MctrlSS_mc_hw_dfc_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r32) _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r16) _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r32) _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r16) _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r32)    _BFGET_(r32, 2, 2)
    #define   SET32MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r32,v)  _BFSET_(r32, 2, 2,v)
    #define   GET16MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r16)    _BFGET_(r16, 2, 2)
    #define   SET16MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r16,v)  _BFSET_(r16, 2, 2,v)

    #define     w32MctrlSS_mc_hw_dfc_sts                       {\
            UNSG32 umc_hw_dfc_sts_reg_table_req_ack            :  1;\
            UNSG32 umc_hw_dfc_sts_reg_table_wait_req           :  1;\
            UNSG32 umc_hw_dfc_sts_sleep_req_ack                :  1;\
            UNSG32 RSVDx4C_b3                                  : 29;\
          }
    union { UNSG32 u32MctrlSS_mc_hw_dfc_sts;
            struct w32MctrlSS_mc_hw_dfc_sts;
          };
    ///////////////////////////////////////////////////////////
              SIE_pll                                          ie_memPll;
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_RWTC_31to0_value(r32)               _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_RWTC_31to0_value(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_RWTC_31to0                          {\
            UNSG32 uRWTC_31to0_value                           : 32;\
          }
    union { UNSG32 u32MctrlSS_RWTC_31to0;
            struct w32MctrlSS_RWTC_31to0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_RWTC_57to32_value(r32)              _BFGET_(r32,25, 0)
    #define   SET32MctrlSS_RWTC_57to32_value(r32,v)            _BFSET_(r32,25, 0,v)

    #define     w32MctrlSS_RWTC_57to32                         {\
            UNSG32 uRWTC_57to32_value                          : 26;\
            UNSG32 RSVDx6C_b26                                 :  6;\
          }
    union { UNSG32 u32MctrlSS_RWTC_57to32;
            struct w32MctrlSS_RWTC_57to32;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_0_PU(r32)          _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_0_PU(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_0_PU(r16)          _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_0_PU(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_0_LP(r32)          _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_0_LP(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_0_LP(r16)          _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_0_LP(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r32)      _BFGET_(r32, 2, 2)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r16)      _BFGET_(r16, 2, 2)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r32)        _BFGET_(r32, 5, 3)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r32,v)      _BFSET_(r32, 5, 3,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r16)        _BFGET_(r16, 5, 3)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r16,v)      _BFSET_(r16, 5, 3,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r32)   _BFGET_(r32, 6, 6)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r16)   _BFGET_(r16, 6, 6)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r32)     _BFGET_(r32, 9, 7)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r32,v)   _BFSET_(r32, 9, 7,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r16)     _BFGET_(r16, 9, 7)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r16,v)   _BFSET_(r16, 9, 7,v)

    #define     w32MctrlSS_DDRCLK_VREG_CTRL_0                  {\
            UNSG32 uDDRCLK_VREG_CTRL_0_PU                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_0_LP                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_0_BYPASS                  :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_0_VSEL                    :  3;\
            UNSG32 uDDRCLK_VREG_CTRL_0_TSTMON_EN               :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_0_TESTMON                 :  3;\
            UNSG32 RSVDx70_b10                                 : 22;\
          }
    union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_0;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_1_PU(r32)          _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_1_PU(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_1_PU(r16)          _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_1_PU(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_1_LP(r32)          _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_1_LP(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_1_LP(r16)          _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_1_LP(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r32)      _BFGET_(r32, 2, 2)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r16)      _BFGET_(r16, 2, 2)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r32)        _BFGET_(r32, 5, 3)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r32,v)      _BFSET_(r32, 5, 3,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r16)        _BFGET_(r16, 5, 3)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r16,v)      _BFSET_(r16, 5, 3,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r32)   _BFGET_(r32, 6, 6)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r16)   _BFGET_(r16, 6, 6)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r32)     _BFGET_(r32, 9, 7)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r32,v)   _BFSET_(r32, 9, 7,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r16)     _BFGET_(r16, 9, 7)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r16,v)   _BFSET_(r16, 9, 7,v)

    #define     w32MctrlSS_DDRCLK_VREG_CTRL_1                  {\
            UNSG32 uDDRCLK_VREG_CTRL_1_PU                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_1_LP                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_1_BYPASS                  :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_1_VSEL                    :  3;\
            UNSG32 uDDRCLK_VREG_CTRL_1_TSTMON_EN               :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_1_TESTMON                 :  3;\
            UNSG32 RSVDx74_b10                                 : 22;\
          }
    union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_1;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_2_PU(r32)          _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_2_PU(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_2_PU(r16)          _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_2_PU(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_2_LP(r32)          _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_2_LP(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_2_LP(r16)          _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_2_LP(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r32)      _BFGET_(r32, 2, 2)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r16)      _BFGET_(r16, 2, 2)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r32)        _BFGET_(r32, 5, 3)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r32,v)      _BFSET_(r32, 5, 3,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r16)        _BFGET_(r16, 5, 3)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r16,v)      _BFSET_(r16, 5, 3,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r32)   _BFGET_(r32, 6, 6)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r16)   _BFGET_(r16, 6, 6)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r32)     _BFGET_(r32, 9, 7)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r32,v)   _BFSET_(r32, 9, 7,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r16)     _BFGET_(r16, 9, 7)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r16,v)   _BFSET_(r16, 9, 7,v)

    #define     w32MctrlSS_DDRCLK_VREG_CTRL_2                  {\
            UNSG32 uDDRCLK_VREG_CTRL_2_PU                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_2_LP                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_2_BYPASS                  :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_2_VSEL                    :  3;\
            UNSG32 uDDRCLK_VREG_CTRL_2_TSTMON_EN               :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_2_TESTMON                 :  3;\
            UNSG32 RSVDx78_b10                                 : 22;\
          }
    union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_2;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_3_PU(r32)          _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_3_PU(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_3_PU(r16)          _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_3_PU(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_3_LP(r32)          _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_3_LP(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_3_LP(r16)          _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_3_LP(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r32)      _BFGET_(r32, 2, 2)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r16)      _BFGET_(r16, 2, 2)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r32)        _BFGET_(r32, 5, 3)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r32,v)      _BFSET_(r32, 5, 3,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r16)        _BFGET_(r16, 5, 3)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r16,v)      _BFSET_(r16, 5, 3,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r32)   _BFGET_(r32, 6, 6)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r16)   _BFGET_(r16, 6, 6)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r32)     _BFGET_(r32, 9, 7)
    #define   SET32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r32,v)   _BFSET_(r32, 9, 7,v)
    #define   GET16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r16)     _BFGET_(r16, 9, 7)
    #define   SET16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r16,v)   _BFSET_(r16, 9, 7,v)

    #define     w32MctrlSS_DDRCLK_VREG_CTRL_3                  {\
            UNSG32 uDDRCLK_VREG_CTRL_3_PU                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_3_LP                      :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_3_BYPASS                  :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_3_VSEL                    :  3;\
            UNSG32 uDDRCLK_VREG_CTRL_3_TSTMON_EN               :  1;\
            UNSG32 uDDRCLK_VREG_CTRL_3_TESTMON                 :  3;\
            UNSG32 RSVDx7C_b10                                 : 22;\
          }
    union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_3;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_3;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx80                                     [32640];
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_DDRScramCtrl_Secure_Key(r32)        _BFGET_(r32, 0, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Secure_Key(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16MctrlSS_DDRScramCtrl_Secure_Key(r16)        _BFGET_(r16, 0, 0)
    #define   SET16MctrlSS_DDRScramCtrl_Secure_Key(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32MctrlSS_DDRScramCtrl_En(r32)                _BFGET_(r32, 1, 1)
    #define   SET32MctrlSS_DDRScramCtrl_En(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16MctrlSS_DDRScramCtrl_En(r16)                _BFGET_(r16, 1, 1)
    #define   SET16MctrlSS_DDRScramCtrl_En(r16,v)              _BFSET_(r16, 1, 1,v)

    #define     w32MctrlSS_DDRScramCtrl                        {\
            UNSG32 uDDRScramCtrl_Secure_Key                    :  1;\
            UNSG32 uDDRScramCtrl_En                            :  1;\
            UNSG32 RSVDx8000_b2                                : 30;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl;
            struct w32MctrlSS_DDRScramCtrl;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key0_word0(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key0_word0(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl1                       {\
            UNSG32 uDDRScramCtrl_Key0_word0                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl1;
            struct w32MctrlSS_DDRScramCtrl1;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key0_word1(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key0_word1(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl2                       {\
            UNSG32 uDDRScramCtrl_Key0_word1                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl2;
            struct w32MctrlSS_DDRScramCtrl2;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key0_word2(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key0_word2(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl3                       {\
            UNSG32 uDDRScramCtrl_Key0_word2                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl3;
            struct w32MctrlSS_DDRScramCtrl3;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key0_word3(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key0_word3(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl4                       {\
            UNSG32 uDDRScramCtrl_Key0_word3                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl4;
            struct w32MctrlSS_DDRScramCtrl4;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key0_addr(r32)         _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key0_addr(r32,v)       _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl5                       {\
            UNSG32 uDDRScramCtrl_Key0_addr                     : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl5;
            struct w32MctrlSS_DDRScramCtrl5;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key0_mask(r32)         _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key0_mask(r32,v)       _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl6                       {\
            UNSG32 uDDRScramCtrl_Key0_mask                     : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl6;
            struct w32MctrlSS_DDRScramCtrl6;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key1_word0(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key1_word0(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl7                       {\
            UNSG32 uDDRScramCtrl_Key1_word0                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl7;
            struct w32MctrlSS_DDRScramCtrl7;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key1_word1(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key1_word1(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl8                       {\
            UNSG32 uDDRScramCtrl_Key1_word1                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl8;
            struct w32MctrlSS_DDRScramCtrl8;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key1_word2(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key1_word2(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl9                       {\
            UNSG32 uDDRScramCtrl_Key1_word2                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl9;
            struct w32MctrlSS_DDRScramCtrl9;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key1_word3(r32)        _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key1_word3(r32,v)      _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl10                      {\
            UNSG32 uDDRScramCtrl_Key1_word3                    : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl10;
            struct w32MctrlSS_DDRScramCtrl10;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key1_addr(r32)         _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key1_addr(r32,v)       _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl11                      {\
            UNSG32 uDDRScramCtrl_Key1_addr                     : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl11;
            struct w32MctrlSS_DDRScramCtrl11;
          };
    #define   GET32MctrlSS_DDRScramCtrl_Key1_mask(r32)         _BFGET_(r32,31, 0)
    #define   SET32MctrlSS_DDRScramCtrl_Key1_mask(r32,v)       _BFSET_(r32,31, 0,v)

    #define     w32MctrlSS_DDRScramCtrl12                      {\
            UNSG32 uDDRScramCtrl_Key1_mask                     : 32;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl12;
            struct w32MctrlSS_DDRScramCtrl12;
          };
    #define   GET32MctrlSS_DDRScramCtrl_W_latency(r32)         _BFGET_(r32, 4, 0)
    #define   SET32MctrlSS_DDRScramCtrl_W_latency(r32,v)       _BFSET_(r32, 4, 0,v)
    #define   GET16MctrlSS_DDRScramCtrl_W_latency(r16)         _BFGET_(r16, 4, 0)
    #define   SET16MctrlSS_DDRScramCtrl_W_latency(r16,v)       _BFSET_(r16, 4, 0,v)

    #define   GET32MctrlSS_DDRScramCtrl_R_latency(r32)         _BFGET_(r32, 9, 5)
    #define   SET32MctrlSS_DDRScramCtrl_R_latency(r32,v)       _BFSET_(r32, 9, 5,v)
    #define   GET16MctrlSS_DDRScramCtrl_R_latency(r16)         _BFGET_(r16, 9, 5)
    #define   SET16MctrlSS_DDRScramCtrl_R_latency(r16,v)       _BFSET_(r16, 9, 5,v)

    #define   GET32MctrlSS_DDRScramCtrl_cal_latency(r32)       _BFGET_(r32,13,10)
    #define   SET32MctrlSS_DDRScramCtrl_cal_latency(r32,v)     _BFSET_(r32,13,10,v)
    #define   GET16MctrlSS_DDRScramCtrl_cal_latency(r16)       _BFGET_(r16,13,10)
    #define   SET16MctrlSS_DDRScramCtrl_cal_latency(r16,v)     _BFSET_(r16,13,10,v)

    #define     w32MctrlSS_DDRScramCtrl13                      {\
            UNSG32 uDDRScramCtrl_W_latency                     :  5;\
            UNSG32 uDDRScramCtrl_R_latency                     :  5;\
            UNSG32 uDDRScramCtrl_cal_latency                   :  4;\
            UNSG32 RSVDx8034_b14                               : 18;\
          }
    union { UNSG32 u32MctrlSS_DDRScramCtrl13;
            struct w32MctrlSS_DDRScramCtrl13;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MctrlSS_rz_ctrl_arrz_pass(r32)              _BFGET_(r32, 7, 0)
    #define   SET32MctrlSS_rz_ctrl_arrz_pass(r32,v)            _BFSET_(r32, 7, 0,v)
    #define   GET16MctrlSS_rz_ctrl_arrz_pass(r16)              _BFGET_(r16, 7, 0)
    #define   SET16MctrlSS_rz_ctrl_arrz_pass(r16,v)            _BFSET_(r16, 7, 0,v)

    #define   GET32MctrlSS_rz_ctrl_awrz_pass(r32)              _BFGET_(r32,15, 8)
    #define   SET32MctrlSS_rz_ctrl_awrz_pass(r32,v)            _BFSET_(r32,15, 8,v)
    #define   GET16MctrlSS_rz_ctrl_awrz_pass(r16)              _BFGET_(r16,15, 8)
    #define   SET16MctrlSS_rz_ctrl_awrz_pass(r16,v)            _BFSET_(r16,15, 8,v)

    #define     w32MctrlSS_rz_ctrl                             {\
            UNSG32 urz_ctrl_arrz_pass                          :  8;\
            UNSG32 urz_ctrl_awrz_pass                          :  8;\
            UNSG32 RSVDx8038_b16                               : 16;\
          }
    union { UNSG32 u32MctrlSS_rz_ctrl;
            struct w32MctrlSS_rz_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_MctrlSS;

    typedef union  T32MctrlSS_MC5_4TO1
          { UNSG32 u32;
            struct w32MctrlSS_MC5_4TO1;
                 } T32MctrlSS_MC5_4TO1;
    typedef union  T32MctrlSS_AVIO_PRIO
          { UNSG32 u32;
            struct w32MctrlSS_AVIO_PRIO;
                 } T32MctrlSS_AVIO_PRIO;
    typedef union  T32MctrlSS_ddrPhyLoopBackSrc
          { UNSG32 u32;
            struct w32MctrlSS_ddrPhyLoopBackSrc;
                 } T32MctrlSS_ddrPhyLoopBackSrc;
    typedef union  T32MctrlSS_ddrPhyLoopBackConfig1
          { UNSG32 u32;
            struct w32MctrlSS_ddrPhyLoopBackConfig1;
                 } T32MctrlSS_ddrPhyLoopBackConfig1;
    typedef union  T32MctrlSS_ddrPhyLoopBackConfig2
          { UNSG32 u32;
            struct w32MctrlSS_ddrPhyLoopBackConfig2;
                 } T32MctrlSS_ddrPhyLoopBackConfig2;
    typedef union  T32MctrlSS_ddrPhyLoopBackConfig3
          { UNSG32 u32;
            struct w32MctrlSS_ddrPhyLoopBackConfig3;
                 } T32MctrlSS_ddrPhyLoopBackConfig3;
    typedef union  T32MctrlSS_ddrPhyLoopBackStatus1
          { UNSG32 u32;
            struct w32MctrlSS_ddrPhyLoopBackStatus1;
                 } T32MctrlSS_ddrPhyLoopBackStatus1;
    typedef union  T32MctrlSS_ddrPhyLoopBackStatus2
          { UNSG32 u32;
            struct w32MctrlSS_ddrPhyLoopBackStatus2;
                 } T32MctrlSS_ddrPhyLoopBackStatus2;
    typedef union  T32MctrlSS_mc_phy_pd_ctrl
          { UNSG32 u32;
            struct w32MctrlSS_mc_phy_pd_ctrl;
                 } T32MctrlSS_mc_phy_pd_ctrl;
    typedef union  T32MctrlSS_mc_mstr0_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr0_qos;
                 } T32MctrlSS_mc_mstr0_qos;
    typedef union  T32MctrlSS_mc_mstr1_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr1_qos;
                 } T32MctrlSS_mc_mstr1_qos;
    typedef union  T32MctrlSS_mc_mstr2_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr2_qos;
                 } T32MctrlSS_mc_mstr2_qos;
    typedef union  T32MctrlSS_mc_mstr3_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr3_qos;
                 } T32MctrlSS_mc_mstr3_qos;
    typedef union  T32MctrlSS_mc_mstr4_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr4_qos;
                 } T32MctrlSS_mc_mstr4_qos;
    typedef union  T32MctrlSS_mc_mstr5_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr5_qos;
                 } T32MctrlSS_mc_mstr5_qos;
    typedef union  T32MctrlSS_mc_mstr6_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr6_qos;
                 } T32MctrlSS_mc_mstr6_qos;
    typedef union  T32MctrlSS_mc_mstr7_qos
          { UNSG32 u32;
            struct w32MctrlSS_mc_mstr7_qos;
                 } T32MctrlSS_mc_mstr7_qos;
    typedef union  T32MctrlSS_mc_hw_phy_dll_update_req
          { UNSG32 u32;
            struct w32MctrlSS_mc_hw_phy_dll_update_req;
                 } T32MctrlSS_mc_hw_phy_dll_update_req;
    typedef union  T32MctrlSS_mc_hw_dfc_ctrl
          { UNSG32 u32;
            struct w32MctrlSS_mc_hw_dfc_ctrl;
                 } T32MctrlSS_mc_hw_dfc_ctrl;
    typedef union  T32MctrlSS_mc_hw_dfc_sts
          { UNSG32 u32;
            struct w32MctrlSS_mc_hw_dfc_sts;
                 } T32MctrlSS_mc_hw_dfc_sts;
    typedef union  T32MctrlSS_RWTC_31to0
          { UNSG32 u32;
            struct w32MctrlSS_RWTC_31to0;
                 } T32MctrlSS_RWTC_31to0;
    typedef union  T32MctrlSS_RWTC_57to32
          { UNSG32 u32;
            struct w32MctrlSS_RWTC_57to32;
                 } T32MctrlSS_RWTC_57to32;
    typedef union  T32MctrlSS_DDRCLK_VREG_CTRL_0
          { UNSG32 u32;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_0;
                 } T32MctrlSS_DDRCLK_VREG_CTRL_0;
    typedef union  T32MctrlSS_DDRCLK_VREG_CTRL_1
          { UNSG32 u32;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_1;
                 } T32MctrlSS_DDRCLK_VREG_CTRL_1;
    typedef union  T32MctrlSS_DDRCLK_VREG_CTRL_2
          { UNSG32 u32;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_2;
                 } T32MctrlSS_DDRCLK_VREG_CTRL_2;
    typedef union  T32MctrlSS_DDRCLK_VREG_CTRL_3
          { UNSG32 u32;
            struct w32MctrlSS_DDRCLK_VREG_CTRL_3;
                 } T32MctrlSS_DDRCLK_VREG_CTRL_3;
    typedef union  T32MctrlSS_DDRScramCtrl
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl;
                 } T32MctrlSS_DDRScramCtrl;
    typedef union  T32MctrlSS_DDRScramCtrl1
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl1;
                 } T32MctrlSS_DDRScramCtrl1;
    typedef union  T32MctrlSS_DDRScramCtrl2
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl2;
                 } T32MctrlSS_DDRScramCtrl2;
    typedef union  T32MctrlSS_DDRScramCtrl3
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl3;
                 } T32MctrlSS_DDRScramCtrl3;
    typedef union  T32MctrlSS_DDRScramCtrl4
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl4;
                 } T32MctrlSS_DDRScramCtrl4;
    typedef union  T32MctrlSS_DDRScramCtrl5
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl5;
                 } T32MctrlSS_DDRScramCtrl5;
    typedef union  T32MctrlSS_DDRScramCtrl6
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl6;
                 } T32MctrlSS_DDRScramCtrl6;
    typedef union  T32MctrlSS_DDRScramCtrl7
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl7;
                 } T32MctrlSS_DDRScramCtrl7;
    typedef union  T32MctrlSS_DDRScramCtrl8
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl8;
                 } T32MctrlSS_DDRScramCtrl8;
    typedef union  T32MctrlSS_DDRScramCtrl9
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl9;
                 } T32MctrlSS_DDRScramCtrl9;
    typedef union  T32MctrlSS_DDRScramCtrl10
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl10;
                 } T32MctrlSS_DDRScramCtrl10;
    typedef union  T32MctrlSS_DDRScramCtrl11
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl11;
                 } T32MctrlSS_DDRScramCtrl11;
    typedef union  T32MctrlSS_DDRScramCtrl12
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl12;
                 } T32MctrlSS_DDRScramCtrl12;
    typedef union  T32MctrlSS_DDRScramCtrl13
          { UNSG32 u32;
            struct w32MctrlSS_DDRScramCtrl13;
                 } T32MctrlSS_DDRScramCtrl13;
    typedef union  T32MctrlSS_rz_ctrl
          { UNSG32 u32;
            struct w32MctrlSS_rz_ctrl;
                 } T32MctrlSS_rz_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TMctrlSS_MC5_4TO1
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_MC5_4TO1;
                   };
                 } TMctrlSS_MC5_4TO1;
    typedef union  TMctrlSS_AVIO_PRIO
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_AVIO_PRIO;
                   };
                 } TMctrlSS_AVIO_PRIO;
    typedef union  TMctrlSS_ddrPhyLoopBackSrc
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_ddrPhyLoopBackSrc;
                   };
                 } TMctrlSS_ddrPhyLoopBackSrc;
    typedef union  TMctrlSS_ddrPhyLoopBackConfig1
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_ddrPhyLoopBackConfig1;
                   };
                 } TMctrlSS_ddrPhyLoopBackConfig1;
    typedef union  TMctrlSS_ddrPhyLoopBackConfig2
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_ddrPhyLoopBackConfig2;
                   };
                 } TMctrlSS_ddrPhyLoopBackConfig2;
    typedef union  TMctrlSS_ddrPhyLoopBackConfig3
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_ddrPhyLoopBackConfig3;
                   };
                 } TMctrlSS_ddrPhyLoopBackConfig3;
    typedef union  TMctrlSS_ddrPhyLoopBackStatus1
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_ddrPhyLoopBackStatus1;
                   };
                 } TMctrlSS_ddrPhyLoopBackStatus1;
    typedef union  TMctrlSS_ddrPhyLoopBackStatus2
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_ddrPhyLoopBackStatus2;
                   };
                 } TMctrlSS_ddrPhyLoopBackStatus2;
    typedef union  TMctrlSS_mc_phy_pd_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_phy_pd_ctrl;
                   };
                 } TMctrlSS_mc_phy_pd_ctrl;
    typedef union  TMctrlSS_mc_mstr0_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr0_qos;
                   };
                 } TMctrlSS_mc_mstr0_qos;
    typedef union  TMctrlSS_mc_mstr1_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr1_qos;
                   };
                 } TMctrlSS_mc_mstr1_qos;
    typedef union  TMctrlSS_mc_mstr2_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr2_qos;
                   };
                 } TMctrlSS_mc_mstr2_qos;
    typedef union  TMctrlSS_mc_mstr3_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr3_qos;
                   };
                 } TMctrlSS_mc_mstr3_qos;
    typedef union  TMctrlSS_mc_mstr4_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr4_qos;
                   };
                 } TMctrlSS_mc_mstr4_qos;
    typedef union  TMctrlSS_mc_mstr5_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr5_qos;
                   };
                 } TMctrlSS_mc_mstr5_qos;
    typedef union  TMctrlSS_mc_mstr6_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr6_qos;
                   };
                 } TMctrlSS_mc_mstr6_qos;
    typedef union  TMctrlSS_mc_mstr7_qos
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_mstr7_qos;
                   };
                 } TMctrlSS_mc_mstr7_qos;
    typedef union  TMctrlSS_mc_hw_phy_dll_update_req
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_hw_phy_dll_update_req;
                   };
                 } TMctrlSS_mc_hw_phy_dll_update_req;
    typedef union  TMctrlSS_mc_hw_dfc_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_hw_dfc_ctrl;
                   };
                 } TMctrlSS_mc_hw_dfc_ctrl;
    typedef union  TMctrlSS_mc_hw_dfc_sts
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_mc_hw_dfc_sts;
                   };
                 } TMctrlSS_mc_hw_dfc_sts;
    typedef union  TMctrlSS_RWTC_31to0
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_RWTC_31to0;
                   };
                 } TMctrlSS_RWTC_31to0;
    typedef union  TMctrlSS_RWTC_57to32
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_RWTC_57to32;
                   };
                 } TMctrlSS_RWTC_57to32;
    typedef union  TMctrlSS_DDRCLK_VREG_CTRL_0
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_DDRCLK_VREG_CTRL_0;
                   };
                 } TMctrlSS_DDRCLK_VREG_CTRL_0;
    typedef union  TMctrlSS_DDRCLK_VREG_CTRL_1
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_DDRCLK_VREG_CTRL_1;
                   };
                 } TMctrlSS_DDRCLK_VREG_CTRL_1;
    typedef union  TMctrlSS_DDRCLK_VREG_CTRL_2
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_DDRCLK_VREG_CTRL_2;
                   };
                 } TMctrlSS_DDRCLK_VREG_CTRL_2;
    typedef union  TMctrlSS_DDRCLK_VREG_CTRL_3
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_DDRCLK_VREG_CTRL_3;
                   };
                 } TMctrlSS_DDRCLK_VREG_CTRL_3;
    typedef union  TMctrlSS_DDRScramCtrl
          { UNSG32 u32[14];
            struct {
            struct w32MctrlSS_DDRScramCtrl;
            struct w32MctrlSS_DDRScramCtrl1;
            struct w32MctrlSS_DDRScramCtrl2;
            struct w32MctrlSS_DDRScramCtrl3;
            struct w32MctrlSS_DDRScramCtrl4;
            struct w32MctrlSS_DDRScramCtrl5;
            struct w32MctrlSS_DDRScramCtrl6;
            struct w32MctrlSS_DDRScramCtrl7;
            struct w32MctrlSS_DDRScramCtrl8;
            struct w32MctrlSS_DDRScramCtrl9;
            struct w32MctrlSS_DDRScramCtrl10;
            struct w32MctrlSS_DDRScramCtrl11;
            struct w32MctrlSS_DDRScramCtrl12;
            struct w32MctrlSS_DDRScramCtrl13;
                   };
                 } TMctrlSS_DDRScramCtrl;
    typedef union  TMctrlSS_rz_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32MctrlSS_rz_ctrl;
                   };
                 } TMctrlSS_rz_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 MctrlSS_drvrd(SIE_MctrlSS *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 MctrlSS_drvwr(SIE_MctrlSS *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void MctrlSS_reset(SIE_MctrlSS *p);
     SIGN32 MctrlSS_cmp  (SIE_MctrlSS *p, SIE_MctrlSS *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define MctrlSS_check(p,pie,pfx,hLOG) MctrlSS_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define MctrlSS_print(p,    pfx,hLOG) MctrlSS_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: MctrlSS
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: MctrlSS.h
////////////////////////////////////////////////////////////