/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//////
/// don't edit! auto-generated by docc: cic.h
////////////////////////////////////////////////////////////
#ifndef cic_h
#define cic_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE CIC                     biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P)
///               ###
///               * S0_ and S1_ prefix used for CICAM0 slot/S-CARD Command-Data Channels and CICAM1 slot/S-CARD Extended Channel respectively.
///               ###
///               %unsigned 2  HOST_TYPE                 0x0
///                                    : CIP                       0x1
///                                    : S_HOST                    0x2
///                                    : M_HOST                    0x3
///                                                 ###
///                                                 * Host Type
///                                                 ###
///               %unsigned 1  RESET                     0x1
///                                    ###
///                                    * Reset for complete CIC
///                                    * 0: Reset state
///                                    * 1: Normal state
///                                    ###
///               %unsigned 1  S0_CARD_EN                0x0
///               %unsigned 1  S1_CARD_EN                0x0
///                                    ###
///                                    * Card Interface Enable
///                                    * 1 : Enable Card Interface
///                                    * 0: Disable Card Interface
///                                    ###
///               %unsigned 1  S0_HOT_SWAP_EN            0x0
///               %unsigned 1  S1_HOT_SWAP_EN            0x0
///                                    ###
///                                    * Card Insertion/Removal Hardware detection
///                                    * 0: Disable
///                                    * 1: Enable
///                                    ###
///               %unsigned 1  S0_OVERLOAD_EN            0x0
///               %unsigned 1  S1_OVERLOAD_EN            0x0
///                                    ###
///                                    * Current Overload Hardware Detection
///                                    * 0: Disable
///                                    * 1: Enable
///                                    ###
///               %unsigned 1  S0_CD_SINGLE_EN           0x0
///               %unsigned 1  S1_CD_SINGLE_EN           0x0
///                                    ###
///                                    * Used to enable Card Insertion on CD1==0 or CD2==0 (Detection of CD1 or CD2 to be 0)
///                                    ###
///               %unsigned 1  CAM_PHY_RESET             0x0
///                                    ###
///                                    * Writing 1 to this bit resets CAM_PHY , PCMCIA_SM and SIP state machines; Read and Write buffer pointers are reset.
///                                    * Write 0 has no effect.
///                                    ###
///               %unsigned 1  S0_CE1                    0x0
///                                    ###
///                                    * 1: Enable CE1/CE2 for CICAM Slot0/S-CARD Data Channel Byte Access
///                                    * 0: Disable CE1/CE2 for CICAM Slot0/S-CARD Data Channel Byte Access
///                                    ###
///               %unsigned 1  S1_CE1                    0x0
///                                    ###
///                                    * 1: Enable CE1/CE2 for CICAM Slot1/S-CARD Extended Channel Byte Access
///                                    * 0: Disable CE1/CE2 for CICAM Slot1/S-CARD Extended Channel Byte Access
///                                    ###
///               %unsigned 1  M_HOST_IQB_ER             0x0
///                                    ###
///                                    * Software driven M_HOST IQB Error
///                                    ###
///               %unsigned 1  S_MODE_MX_EN              0x0
///                                    ###
///                                    * Please refer to description of s_mode_mx_en output
///                                    ###
///               %unsigned 1  M_MODE_MX_EN              0x0
///                                    ###
///                                    * Please refer to description of m_mode_mx_en output
///                                    ###
///               %unsigned 1  S0_VPP1SW                 0x0
///                                    ###
///                                    * Control of VPP1SW output pin, in M-Mode
///                                    * 0: Disable external voltage pin
///                                    * 1: Enable external voltage pin
///                                    ###
///               %unsigned 1  S0_VPP1SEL                0x0
///                                    ###
///                                    * 3.3V or 5V Card Voltage Selection for Card in M-Mode
///                                    * 0: Select 3.3V
///                                    * 1: Select 5V
///                                    ###
///               %unsigned 1  S0_VPP2SW                 0x0
///                                    ###
///                                    * Control of VPP2SW output pin, in M-Mode
///                                    * 0: Disable external voltage pin
///                                    * 1: Enable external voltage pin
///                                    ###
///               %unsigned 1  S0_VPP2SEL                0x0
///                                    ###
///                                    * 3.3V or 5V Card Voltage Selection for Card in M-Mode
///                                    * 0: Select 3.3V
///                                    * 1: Select 5V
///                                    ###
///               %unsigned 1  S0_VS2                    0x0
///                                    ###
///                                    * Configurable bit for VS2-MDET connection check for M-Card detection
///                                    ###
///               %unsigned 1  S0_VCCSW                  0x0
///               %unsigned 1  S1_VCCSW                  0x0
///                                    ###
///                                    * Control of VCCSW output pin
///                                    * 0: Disable external voltage pin
///                                    * 1: Enable external voltage pin
///                                    ###
///               %unsigned 1  S0_CARD_RST               0x0
///               %unsigned 1  S1_CARD_RST               0x0
///                                    ###
///                                    * Software driven CARD RESET for Card
///                                    ###
///               %unsigned 2  S0_VCC_SUPPORTED          0x2
///               %unsigned 2  S1_VCC_SUPPORTED          0x2
///                                    ###
///                                    * VCC Selection Capabilities for Card
///                                    * 0x0: Hot-swap will be triggered by 3.3V cards only (VS1 = LOW)
///                                    * 0x1: Hot-swap will be triggered by 5V cards only (VS1 = HIGH)
///                                    * 0x2: Hot-swap will be triggered by 3.3V or 5V cards
///                                    ###
///               %unsigned 1  S0_VCC_SEL                0x0
///               %unsigned 1  S1_VCC_SEL                0x0
///                                    ###
///                                    * 3.3V or 5V Card Voltage Selection for Card
///                                    * 0: Select 3.3V
///                                    * 1: Select 5V
///                                    ###
///     @ 0x00004 CMD                  (P)
///               %unsigned 3  TYPE                      0x0
///                                    : DIRECT_READ               0x0
///                                    : DIRECT_WRITE              0x1
///                                    : SINGLE_READ               0x2
///                                    : SINGLE_WRITE              0x3
///                                    : BLOCK_READ                0x4
///                                    : BLOCK_WRITE               0x5
///                                    : CAM_START                 0x6
///                                    : CAM_STOP                  0x7
///                                                 ###
///                                                 * Please refer to detailed description of each of these Command Operations
///                                                 * Note: Newly issued command in presence of an outstanding request is ignored by CTRL_SM. CPU to check STATUS register for any pending commands.
///                                                 ###
///               %unsigned 1  SLOT_CH                   0x0
///                                    : SLOT_CH0                  0x0
///                                    : SLOT_CH1                  0x1
///                                                 ###
///                                                 * CICAM slot/S_HOST channel selection (Not Used for CAM_START, CAM_STOP commands)
///                                                 ###
///               %unsigned 1  PCMCIA_ADDR_INCR          0x0
///                                    ###
///                                    * PCMCIA Address increment value for BLOCK transaction
///                                    * 0: PCMCIA Address increment by 1
///                                    * 1: PCMCIA Address increment by 2
///                                    * Required as Attribute Memory to be accessed at even address only
///                                    ###
///               %unsigned 1  BUF_BYTE_PACK             0x0
///                                    ###
///                                    * Order of Byte Packing in Read/Write Buffer for BLOCK transaction
///                                    * 0: {EVEN3,EVEN2,EVEN1,EVEN0}
///                                    * 1: {EVEN2,INVALID,EVEN0,INVALID} Effective transfer BLOCK size will be BLOCK_SIZE/2
///                                    * Required as Attribute Memory to be accessed at even address only
///                                    ###
///               %unsigned 1  IOA                       0x0
///                                    ###
///                                    * 0: Enable IO_# for I/O Access
///                                    * 1: Disable IO_# for Memory Access
///                                    ###
///               %unsigned 1  REGA                      0x0
///                                    ###
///                                    * 0: Assert REG_# for Attribute Memory or I/O Access
///                                    * 1: De-assert REG_# for Common Memory Access
///                                    ###
///               %unsigned 15 ADDR                      0x0
///                                    ###
///                                    * TRANS_ADDR if TYPE==DIRECT_READ
///                                    * TRANS_ADDR if TYPE==DIRECT_WRITE
///                                    * TRANS_ADDR if TYPE==SIGNLE_READ
///                                    * TRANS_ADDR if TYPE==SIGNLE_WRITE
///                                    * START_ADDR if TYPE==BLOCK_READ
///                                    * START_ADDR if TYPE==BLOCK_WRITE
///                                    * S0_CAM_REG_OFFSET if TYPE==CAM_START
///                                    * Not Valid for TYPE==CAM_STOP
///                                    ###
///               %unsigned 8  BYTE_WR_DATA              0x0
///                                    ###
///                                    * Single Byte Write data.
///                                    * Valid for DIRECT_WRITE and SINGLE_WRITE
///                                    ###
///               %%        1          # Stuffing bits...
///     @ 0x00008 CTRL_OE0             (P)
///               %unsigned 32 S0_31_0                   0xFFE0FFFC
///                                    ###
///                                    * Output Enable for S0 [31:0] pins
///                                    ###
///     @ 0x0000C CTRL_OE1             (P)
///               %unsigned 32 S0_63_32                  0x24003401
///                                    ###
///                                    * Output Enable for S0 [63:32] pins
///                                    ###
///     @ 0x00010 CTRL_OE2             (P)
///               %unsigned 5  S0_68_64                  0x0
///                                    ###
///                                    * Output Enable for S0 [68_64] pins
///                                    ###
///               %unsigned 1  S1_07_CE1                 0x0
///                                    ###
///                                    * Output Enable for S1 #07 CE1 pin
///                                    ###
///               %unsigned 1  S1_42_CE2                 0x0
///                                    ###
///                                    * Output Enable for S1 #42 E2 pin
///                                    ###
///               %unsigned 1  S1_58_RESET               0x0
///                                    ###
///                                    * Output Enable for S1 #58 RESET pin
///                                    ###
///               %unsigned 1  S1_43_VS1                 0x0
///                                    ###
///                                    * Output Enable for S1 VS1 pin
///                                    ###
///               %unsigned 1  S1_16_IREQ_N              0x0
///                                    ###
///                                    * Output Enable for S1 IREQ_N pin
///                                    ###
///               %unsigned 1  S1_36_CD1_N               0x0
///                                    ###
///                                    * Output Enable for S1 CD1_N pin
///                                    ###
///               %unsigned 1  S1_67_CD2_N               0x0
///                                    ###
///                                    * Output Enable for S1 CD2_N pin
///                                    ###
///               %unsigned 1  S1_60_INPACK_N            0x0
///                                    ###
///                                    * Output Enable for S1 INPACK_N pin
///                                    ###
///               %unsigned 1  S1_59_WAIT_N              0x0
///                                    ###
///                                    * Output Enable for S1 WAIT_N pin
///                                    ###
///               %unsigned 1  VC_S0_VCC_SW              0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 VCC_SW pin
///                                    ###
///               %unsigned 1  VC_S0_VCC_SEL             0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 VCC_SEL pin
///                                    ###
///               %unsigned 1  VC_S0_VPP1_SW             0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 VPP1_SW pin
///                                    ###
///               %unsigned 1  VC_S0_VPP1_SEL            0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 VPP1_SEL pin
///                                    ###
///               %unsigned 1  VC_S0_VPP2_SW             0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 VPP2_SW pin
///                                    ###
///               %unsigned 1  VC_S0_VPP2_SEL            0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 VPP2_SEL pin
///                                    ###
///               %unsigned 1  VC_S1_VCC_SW              0x0
///                                    ###
///                                    * Output Enable for Voltage Control S1 VCC_SW pin
///                                    ###
///               %unsigned 1  VC_S1_VCC_SEL             0x0
///                                    ###
///                                    * Output Enable for Voltage Control S1 VCC_SEL pin
///                                    ###
///               %unsigned 1  VC_S0_OVERLOAD            0x0
///                                    ###
///                                    * Output Enable for Voltage Control S0 OVERLOAD pin
///                                    ###
///               %unsigned 1  VC_S1_OVERLOAD            0x0
///                                    ###
///                                    * Output Enable for Voltage Control S1 OVERLOAD pin
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x00014 S1_CAM_REG_OFFSET    (P)
///               %unsigned 15 VAL                       0x0
///                                    ###
///                                    * S1_CAM_REG_OFFSET Value
///                                    ###
///               %%        17         # Stuffing bits...
///     @ 0x00018 STATUS               (R-)
///               ###
///               * Status of outstanding command and Read/Write Buffer State
///               ###
///               %unsigned 1  DIRECT_READ_PEND          0x0
///                                    ###
///                                    * 1: DIRECT_READ pending transaction
///                                    ###
///               %unsigned 1  DIRECT_WRITE_PEND         0x0
///                                    ###
///                                    * 1: DIRECT_WRITE pending transaction
///                                    ###
///               %unsigned 1  SINGLE_READ_PEND          0x0
///                                    ###
///                                    * 1: SINGLE_READ pending transaction
///                                    ###
///               %unsigned 1  SINGLE_WRITE_PEND         0x0
///                                    ###
///                                    * 1: SINGLE_WRITE pending transaction
///                                    ###
///               %unsigned 1  BLOCK_READ_PEND           0x0
///                                    ###
///                                    * 1: BLOCK_READ pending transaction
///                                    ###
///               %unsigned 1  BLOCK_WRITE_PEND          0x0
///                                    ###
///                                    * 1: BLOCK_WRITE pending transaction
///                                    ###
///               %unsigned 1  CAM_START_PEND            0x0
///                                    ###
///                                    * 1: CAM_START pending Command
///                                    ###
///               %unsigned 1  CAM_STOP_PEND             0x0
///                                    ###
///                                    * 1: CAM_STOP pending Command
///                                    ###
///               %unsigned 1  RX_BUF0_BUSY              0x0
///                                    ###
///                                    * 1: Read/Receive Buffer0 Busy (with write from PCMCIA/SIP State Machine)
///                                    * Read Access to Read Buffer0 from CPU ignored by Hardware
///                                    ###
///               %unsigned 1  RX_BUF1_BUSY              0x0
///                                    ###
///                                    * 1: Read/Receive Buffer1 Busy (with write from PCMCIA/SIP State Machine)
///                                    * Read Access to Read Buffer1 from CPU ignored by Hardware
///                                    ###
///               %unsigned 1  TX_BUF0_BUSY              0x0
///                                    ###
///                                    * 1: Write/Transmit Buffer0 Busy (with read from PCMCIA/SIP State Machine)
///                                    * Write/Transmit Access to Write/Transmit Buffer0 from CPU ignored by Hardware
///                                    ###
///               %unsigned 1  TX_BUF1_BUSY              0x0
///                                    ###
///                                    * 1: Write/Transmit Buffer1 Busy (with read from PCMCIA/SIP State Machine)
///                                    * Write Access to Write Buffer1 from CPU ignored by Hardware
///                                    ###
///               %%        20         # Stuffing bits...
///     @ 0x0001C TX_BUF0_WIN          (P)
///               %unsigned 32 LOC                       0x0
///                                    ###
///                                    * Write/Transmit Buffer0 Window Location
///                                    ###
///     @ 0x00020 TX_BUF1_WIN          (P)
///               %unsigned 32 LOC                       0x0
///                                    ###
///                                    * Write/Transmit Buffer1 Window Location
///                                    ###
///     @ 0x00024 RX_BUF0_WIN          (R-)
///               %unsigned 32 LOC                       0x0
///                                    ###
///                                    * Read/Receive Buffer0 Window Location
///                                    ###
///     @ 0x00028 RX_BUF1_WIN          (R-)
///               %unsigned 32 LOC                       0x0
///                                    ###
///                                    * Read/Receive Buffer1 Window Location
///                                    ###
///     @ 0x0002C TX_BUF0_CFG          (P)
///               %unsigned 12 SIZE                      0x0
///                                    ###
///                                    * Write/Transmit Buffer0 Size (Valid range: 0-4095)
///                                    * 0 value indicates transmit block size of 4096
///                                    ###
///               %unsigned 1  PKT_F                     0x0
///                                    ###
///                                    * SIP Transmit packet IQB F indication for Command Channel
///                                    ###
///               %unsigned 1  PKT_L                     0x0
///                                    ###
///                                    * SIP Transmit packet IQB L indication for Command Channel
///                                    ###
///               %unsigned 1  BYTE_SWAP_EN              0x0
///                                    ###
///                                    * Active High Enable for Byte Order Reversal within a word
///                                    ###
///               %unsigned 1  BIT_SWAP_EN               0x0
///                                    ###
///                                    * Active High Enable for Bit Order Reversal for all bytes in a word
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00030 TX_BUF1_CFG          (P)
///               %unsigned 12 SIZE                      0x0
///                                    ###
///                                    * Write/Transmit Buffer1 Size (Valid range: 0-4095)
///                                    * 0 value indicates transmit block size of 4096
///                                    ###
///               %unsigned 1  PKT_F                     0x0
///                                    ###
///                                    * SIP Transmit packet IQB F indication for Command Channel
///                                    ###
///               %unsigned 1  PKT_L                     0x0
///                                    ###
///                                    * SIP Transmit packet IQB L indication for Command Channel
///                                    ###
///               %unsigned 1  BYTE_SWAP_EN              0x0
///                                    ###
///                                    * Active High Enable for Byte Order Reversal within a word
///                                    ###
///               %unsigned 1  BIT_SWAP_EN               0x0
///                                    ###
///                                    * Active High Enable for Bit Order Reversal for all bytes in a word
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00034 RX_BUF0_CFG          (RW)
///               %unsigned 12 SIZE                      0x0
///                                    ###
///                                    * Read/Receive Buffer0 Size (Valid range: 0-4095)
///                                    * 0 value indicates receive block size of 4096
///                                    ###
///               %unsigned 1  PKT_F                     0x0
///                                    ###
///                                    * SIP Receive packet IQB F indication for Command Channel
///                                    ###
///               %unsigned 1  PKT_L                     0x0
///                                    ###
///                                    * SIP Receive packet IQB L indication for Command Channel
///                                    ###
///               %unsigned 1  BYTE_SWAP_EN              0x0
///                                    ###
///                                    * Active High Enable for Byte Order Reversal within a word
///                                    ###
///               %unsigned 1  BIT_SWAP_EN               0x0
///                                    ###
///                                    * Active High Enable for Bit Order Reversal for all bytes in a word
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00038 RX_BUF1_CFG          (RW)
///               %unsigned 12 SIZE                      0x0
///                                    ###
///                                    * Read/Receive Buffer1 Size (Valid range: 0-4095)
///                                    * 0 value indicates receive block size of 4096
///                                    ###
///               %unsigned 1  PKT_F                     0x0
///                                    ###
///                                    * SIP Receive packet IQB F indication for Extended Channel
///                                    ###
///               %unsigned 1  PKT_L                     0x0
///                                    ###
///                                    * SIP Receive packet IQB L indication for Extended Channel
///                                    ###
///               %unsigned 1  BYTE_SWAP_EN              0x0
///                                    ###
///                                    * Active High Enable for Byte Order Reversal within a word
///                                    ###
///               %unsigned 1  BIT_SWAP_EN               0x0
///                                    ###
///                                    * Active High Enable for Bit Order Reversal for all bytes in a word
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x0003C S0_SB_RD_DATA        (R-)
///               %unsigned 8  WINDOW                    0x0
///                                    ###
///                                    * Single byte read data register for S0.
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00040 S1_SB_RD_DATA        (R-)
///               %unsigned 8  WINDOW                    0x0
///                                    ###
///                                    * Single byte read data register for S1.
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00044 INT_STATUS           (WOC-)
///               ###
///               * Interrupt status register. SW shall write 1 to clear the particular bit. Write 0 has no effect.
///               ###
///               %unsigned 1  S0_OVERLOAD               0x0
///                                    ###
///                                    * Interrupt from OVERLOAD input
///                                    ###
///               %unsigned 1  S0_CARD_INSERT            0x0
///                                    ###
///                                    * Card Insertion event
///                                    ###
///               %unsigned 1  S0_CARD_REMOVE            0x0
///                                    ###
///                                    * Card Removal event
///                                    ###
///               %unsigned 1  S0_CARD_RDY               0x0
///                                    ###
///                                    * Card Ready event (for HOT_SWAP_EN==0x1)
///                                    ###
///               %unsigned 1  S0_CARD_RDY_TO            0x0
///                                    ###
///                                    * Card Ready Time Out event (for HOT_SWAP_EN==0x1)
///                                    ###
///               %unsigned 1  S0_IREQ                   0x0
///                                    ###
///                                    * Interrupt from Card
///                                    ###
///               %unsigned 1  S0_BLOCK_WRITE            0x0
///                                    ###
///                                    * BLOCK_WRITE completion event.
///                                    ###
///               %unsigned 1  S0_BLOCK_READ             0x0
///                                    ###
///                                    * BLOCK_READ completion event.
///                                    ###
///               %unsigned 1  S0_SINGLE_WRITE           0x0
///                                    ###
///                                    * SINGLE_WRITE completion event.
///                                    ###
///               %unsigned 1  S0_SINGLE_READ            0x0
///                                    ###
///                                    * SINGLE_READ completion event.
///                                    ###
///               %unsigned 1  S0_CARD_ERR               0x0
///                                    ###
///                                    * Signals PCMCIA timeout has occurred
///                                    * M_CARD_IQB_ER is set
///                                    ###
///               %unsigned 1  S1_OVERLOAD               0x0
///               %unsigned 1  S1_CARD_INSERT            0x0
///               %unsigned 1  S1_CARD_REMOVE            0x0
///               %unsigned 1  S1_CARD_RDY               0x0
///               %unsigned 1  S1_CARD_RDY_TO            0x0
///               %unsigned 1  S1_IREQ                   0x0
///               %unsigned 1  S1_BLOCK_WRITE            0x0
///               %unsigned 1  S1_BLOCK_READ             0x0
///               %unsigned 1  S1_SINGLE_WRITE           0x0
///               %unsigned 1  S1_SINGLE_READ            0x0
///               %unsigned 1  S1_CARD_ERR               0x0
///                                    ###
///                                    * Interrupt events corresponding to slot1
///                                    ###
///               %%        10         # Stuffing bits...
///     @ 0x00048 INT_MASK             (P)
///               ###
///               * Interrupt mask register. SW writes 1 to particular bit to mask that interrupt event. 0 enables the interrupt from that event.
///               ###
///               %unsigned 1  S0_OVERLOAD               0x1
///               %unsigned 1  S0_CARD_INSERT            0x1
///               %unsigned 1  S0_CARD_REMOVE            0x1
///               %unsigned 1  S0_CARD_RDY               0x1
///               %unsigned 1  S0_CARD_RDY_TO            0x1
///               %unsigned 1  S0_IREQ                   0x1
///               %unsigned 1  S0_BLOCK_WRITE            0x1
///               %unsigned 1  S0_BLOCK_READ             0x1
///               %unsigned 1  S0_SINGLE_WRITE           0x1
///               %unsigned 1  S0_SINGLE_READ            0x1
///               %unsigned 1  S0_CARD_ERR               0x1
///               %unsigned 1  S1_OVERLOAD               0x1
///               %unsigned 1  S1_CARD_INSERT            0x1
///               %unsigned 1  S1_CARD_REMOVE            0x1
///               %unsigned 1  S1_CARD_RDY               0x1
///               %unsigned 1  S1_CARD_RDY_TO            0x1
///               %unsigned 1  S1_IREQ                   0x1
///               %unsigned 1  S1_BLOCK_WRITE            0x1
///               %unsigned 1  S1_BLOCK_READ             0x1
///               %unsigned 1  S1_SINGLE_WRITE           0x1
///               %unsigned 1  S1_SINGLE_READ            0x1
///               %unsigned 1  S1_CARD_ERR               0x1
///               %%        10         # Stuffing bits...
///     @ 0x0004C INT_TRIG_POL         (P)
///               %unsigned 1  S0_OVERLOAD               0x0
///               %unsigned 1  S1_OVERLOAD               0x0
///                                    ###
///                                    * Active Level of OVERLOAD
///                                    * 0: Interrupt when OVERLOAD is LOW
///                                    * 1: Interrupt when OVERLOAD is HIGH
///                                    ###
///               %unsigned 1  S0_CD                     0x0
///               %unsigned 1  S1_CD                     0x0
///                                    ###
///                                    * Active Level of CD
///                                    * 0: Interrupt when CD is LOW
///                                    * 1: Interrupt when CD is HIGH
///                                    ###
///               %unsigned 1  S0_IREQ                   0x0
///               %unsigned 1  S1_IREQ                   0x0
///                                    ###
///                                    * Active Level of IREQ
///                                    * 0: Interrupt when IREQ is LOW
///                                    * 1: Interrupt when IREQ is HIGH
///                                    ###
///               %%        26         # Stuffing bits...
///     @ 0x00050 DA                   (P)
///               %unsigned 8  REQ_CYC                   0x96
///                                    ###
///                                    * Number of “tick_us” for which periodic DA check request is generated.
///                                    * If PRI_EN==1,DA check is performed for every DA check request.
///                                    * If PRI_EN==0, pending FR check is given priority over DA check request alternatively.
///                                    * Valid in case of Physical CAM mode
///                                    ###
///               %unsigned 1  PRI_EN                    0x0
///                                    ###
///                                    * DA Priority Enable
///                                    * 0: DA and FR check are performed alternatively if both set active
///                                    * In case of Dual Slot support, following is order of priority in which pending (DA or FR) requests are processed-
///                                    * REQ_CYC0: S0_DA S1_DA S0_FR S1_FR
///                                    * REQ_CYC1: S0_FR S1_FR S0_DA S1_DA
///                                    * REQ_CYC2: S1_DA S0_DA S1_FR S0_FR
///                                    * REQ_CYC3: S1_FR S0_FR S1_DA S0_DA
///                                    * and so on ...
///                                    * 1: DA from CAM has priority
///                                    * In case of Dual Slot support, following is order of priority in which pending (DA or FR) requests are processed-
///                                    * REQ_CYC0: S0_DA S1_DA S0_FR S1_FR
///                                    * REQ_CYC1: S1_DA S0_DA S1_FR S0_FR
///                                    * REQ_CYC2: S0_DA S1_DA S0_FR S1_FR
///                                    * REQ_CYC3: S1_DA S0_DA S1_FR S0_FR
///                                    * and so on ...
///                                    * Note: In case of Single Slot support one of following condition exists for requests(S0_DA, S1_DA, S0_FR, S1_FR),
///                                    * S0_DA==0 and S0_FR==0
///                                    * S1_DA==0 and S1_FR==0
///                                    * Valid in case of Physical CAM mode
///                                    ###
///               %%        23         # Stuffing bits...
///     @ 0x00054 HC_DLY               (P)
///               %unsigned 12 CLR                       0xA
///                                    ###
///                                    * It defines the number of "tick_us" between last byte transmission and the clearing of HC bit. The delay can vary between 0 to 2.42ms
///                                    * Valid in case of PHY_CAM mode
///                                    ###
///               %unsigned 8  RETRY                     0x2
///                                    ###
///                                    * It defines the number of "tick_us" between last FR==0 attempt and setting HC bit to 1 for initiating next FR status check.
///                                    * Valid in case of PHY_CAM mode
///                                    * Note: CLR time to be lesser than REQ_CYC time.
///                                    ###
///               %%        12         # Stuffing bits...
///     @ 0x00058 PHY_MIRROR_STAT      (R-)
///               %unsigned 1  S0_OVERLOAD               0x0
///               %unsigned 1  S1_OVERLOAD               0x0
///                                    ###
///                                    * Mirror Value of OVERLOAD pin
///                                    ###
///               %unsigned 1  S0_CD1                    0x0
///               %unsigned 1  S1_CD1                    0x0
///                                    ###
///                                    * Mirror Value of CD1 pin
///                                    ###
///               %unsigned 1  S0_CD2                    0x0
///               %unsigned 1  S1_CD2                    0x0
///                                    ###
///                                    * Mirror Value of CD2 pin
///                                    ###
///               %unsigned 1  S0_IREQ                   0x0
///               %unsigned 1  S1_IREQ                   0x0
///                                    ###
///                                    * Mirror Value of IREQ pin
///                                    ###
///               %unsigned 1  S0_VS1                    0x0
///               %unsigned 1  S1_VS1                    0x0
///                                    ###
///                                    * Mirror Value of VS1 pin
///                                    ###
///               %unsigned 1  S0_VS2                    0x0
///                                    ###
///                                    * Mirror Value of VS2 pin
///                                    ###
///               %unsigned 1  S0_MDET                   0x0
///                                    ###
///                                    * Mirror Value of MDET pin
///                                    ###
///               %unsigned 1  S0_SDO                    0x0
///                                    ###
///                                    * Mirror Value of SDO pin
///                                    ###
///               %%        19         # Stuffing bits...
///     @ 0x0005C S0_PHY_PH_CYC        (P)
///               ###
///               * This register controls number of cycles in different phases of PCMCIA Transaction. Eventually also controls PCMCIA Read/Write Cycle Time from Host point of view.
///               ###
///               %unsigned 8  SU                        0x21
///                                    ###
///                                    * Number of cicCoreClk cycles in "Set-Up Phase". In this phase all the control signals driven by CI Controller on PCMCIA are activated using corresponding SU (Set-Up) timings.
///                                    ###
///               %unsigned 8  PRE_WAIT                  0x21
///                                    ###
///                                    * Number of cicCoreClk cycles in “Pre-Active WAIT Phase”. This phase follows “Set-Up Phase”. In this phase, PCMCIA_SM waits for WAIT to go active. If WAIT goes active before end of this phase, SM moves to next phase; otherwise it is considered that PCMCIA device is ready for transaction, SM moves to next phase.
///                                    ###
///               %unsigned 8  WAIT                      0xFF
///                                    ###
///                                    * Number of cicCoreClk cycles in “Active WAIT Phase”. This phase follows “Pre-Active WAIT Phase”. If WAIT remains active till the end of this phase, this phase gets extended and a timeout interrupt is triggered, according to PHY_WAIT_TIMEOUT and PHY_WAIT_PRI setting. After triggering interrupt SM moves to next phase.
///                                    * If WAIT goes inactive before end of this phase, SM moves to next phase.
///                                    ###
///               %unsigned 8  HO                        0x21
///                                    ###
///                                    * Number of cicCoreClk cycles in “Hold Phase”. This phase follows “Active WAIT Phase”. In this phase all the control signals driven by CI Controller on PCMCIA are de-activated using corresponding HO (Hold) timings.
///                                    ###
///     @ 0x00060 S1_PHY_PH_CYC        (P)
///               %unsigned 8  SU                        0x21
///               %unsigned 8  PRE_WAIT                  0x21
///               %unsigned 8  WAIT                      0xFF
///               %unsigned 8  HO                        0x21
///     @ 0x00064 S0_PHY_WAIT          (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * WAIT# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 1  SYNC                      0x1
///                                    ###
///                                    * WAIT# Synchronization Enable
///                                    * 0: Disable
///                                    * 1: Enable
///                                    ###
///               %unsigned 1  PRI                       0x0
///                                    ###
///                                    * 0: PCMCIA_ERR is triggered, if WAIT remains active till end of “Active WAIT Phase”.
///                                    * 1: PCMCIA_ERR is triggered, if WAIT remains active for TIMEOUT_PERIOD.
///                                    ###
///               %unsigned 2  TIMEOUT_UNIT              0x1
///                                    ###
///                                    * Selection of tick for TIMEOUT_PERIOD
///                                    ###
///                                    : cicCoreClk                0x1
///                                    : US                        0x2
///                                    : MS                        0x3
///               %unsigned 10 TIMEOUT_PERIOD            0xC
///                                    ###
///                                    * It defines time duration in terms of selected tick for which if WAIT# remains activated, a PCMCIA_ERR interrupt is triggered.
///                                    ###
///               %%        17         # Stuffing bits...
///     @ 0x00068 S1_PHY_WAIT          (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 1  SYNC                      0x1
///               %unsigned 1  PRI                       0x0
///               %unsigned 2  TIMEOUT_UNIT              0x1
///                                    : cicCoreClk                0x1
///                                    : US                        0x2
///                                    : MS                        0x3
///               %unsigned 10 TIMEOUT_PERIOD            0xC
///               %%        17         # Stuffing bits...
///     @ 0x0006C S0_PHY_REG           (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * REG# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 8  SU_TIM                    0x3
///                                    ###
///                                    * REG# is driven with active value after REG_SU_CNT number of Clock Cycles of cicCoreClk; from start of “Set-Up Phase”.
///                                    ###
///               %unsigned 8  HO_TIM                    0x1E
///                                    ###
///                                    * REG# is driven with inactive value after REG_HO_CNT number of Clock Cycles of cicCoreClk; from start of “Hold Phase”.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00070 S1_PHY_REG           (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 8  SU_TIM                    0x3
///               %unsigned 8  HO_TIM                    0x1E
///               %%        15         # Stuffing bits...
///     @ 0x00074 S0_PHY_CE            (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * CE# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 8  SU_TIM                    0x6
///                                    ###
///                                    * CE# is driven with active value after CE_SU_CNT number of Clock Cycles of cicCoreClk; from start of “Set-Up Phase”.
///                                    ###
///               %unsigned 8  HO_TIM                    0x1B
///                                    ###
///                                    * CE# is driven with inactive value after CE_HO_CNT number of Clock Cycles of cicCoreClk; from start of “Hold Phase”.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00078 S1_PHY_CE            (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 8  SU_TIM                    0x6
///               %unsigned 8  HO_TIM                    0x1B
///               %%        15         # Stuffing bits...
///     @ 0x0007C S0_PHY_OE            (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * OE# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 8  SU_TIM                    0x1E
///                                    ###
///                                    * OE# is driven with active value after OE_SU_CNT number of Clock Cycles of cicCoreClk; from start of “Set-Up Phase”.
///                                    ###
///               %unsigned 8  HO_TIM                    0xF
///                                    ###
///                                    * OE# is driven with inactive value after OE_HO_CNT number of Clock Cycles of cicCoreClk; from start of “Hold Phase”.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00080 S1_PHY_OE            (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 8  SU_TIM                    0x1E
///               %unsigned 8  HO_TIM                    0xF
///               %%        15         # Stuffing bits...
///     @ 0x00084 S0_PHY_WE            (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * WE# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 8  SU_TIM                    0x9
///                                    ###
///                                    * WE# is driven with active value after WE_SU_CNT number of Clock Cycles of cicCoreClk; from start of “Set-Up Phase”.
///                                    ###
///               %unsigned 8  HO_TIM                    0x12
///                                    ###
///                                    * WE# is driven with inactive value after WE_HO_CNT number of Clock Cycles of cicCoreClk; from start of “Hold Phase”.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00088 S1_PHY_WE            (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 8  SU_TIM                    0x9
///               %unsigned 8  HO_TIM                    0x12
///               %%        15         # Stuffing bits...
///     @ 0x0008C S0_PHY_IORD          (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * IORD# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 8  SU_TIM                    0x7
///                                    ###
///                                    * IORD# is driven with active value after IORD_SU_CNT number of Clock Cycles of cicCoreClk; from start of “Set-Up Phase”.
///                                    ###
///               %unsigned 8  HO_TIM                    0x6
///                                    ###
///                                    * IORD# is driven with inactive value after IORD_HO_CNT number of Clock Cycles of cicCoreClk; from start of “Hold Phase”.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00090 S1_PHY_IORD          (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 8  SU_TIM                    0x7
///               %unsigned 8  HO_TIM                    0x6
///               %%        15         # Stuffing bits...
///     @ 0x00094 S0_PHY_IOWR          (P)
///               %unsigned 1  POL                       0x0
///                                    ###
///                                    * IOWR# Polarity
///                                    * 0: Active LOW
///                                    * 1: Active HIGH
///                                    ###
///               %unsigned 8  SU_TIM                    0x15
///                                    ###
///                                    * IOWR# is driven with active value after IOWR_SU_CNT number of Clock Cycles of cicCoreClk; from start of “Set-Up Phase”.
///                                    ###
///               %unsigned 8  HO_TIM                    0x12
///                                    ###
///                                    * IOWR# is driven with inactive value after IOWR_HO_CNT number of Clock Cycles of cicCoreClk; from start of “Hold Phase”.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00098 S1_PHY_IOWR          (P)
///               %unsigned 1  POL                       0x0
///               %unsigned 8  SU_TIM                    0x15
///               %unsigned 8  HO_TIM                    0x12
///               %%        15         # Stuffing bits...
///     @ 0x0009C S0_PHY_RD_DLAT       (P)
///               %unsigned 8  PHASE                     0x4
///                                    ###
///                                    * Phase in which Read Data is Latched
///                                    ###
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x3
///                                    ###
///                                    * Cycle of selected PHASE in which Read Data is Latched
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x000A0 S1_PHY_RD_DLAT       (P)
///               %unsigned 8  PHASE                     0x4
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x3
///               %%        16         # Stuffing bits...
///     @ 0x000A4 S0_PHY_IOWR_DLAUNCH  (P)
///               %unsigned 8  PHASE                     0x1
///                                    ###
///                                    * Phase in which I/O Write Data is Latched
///                                    ###
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x3
///                                    ###
///                                    * Cycle of selected PHASE in which I/O Write Data is Launched. DataValid is activated along with this.
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x000A8 S1_PHY_IOWR_DLAUNCH  (P)
///               %unsigned 8  PHASE                     0x1
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x3
///               %%        16         # Stuffing bits...
///     @ 0x000AC S0_PHY_IOWR_DREMOVE  (P)
///               %unsigned 8  PHASE                     0x4
///                                    ###
///                                    * Phase in which I/O Write Data is Removed
///                                    ###
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x1E
///                                    ###
///                                    * Cycle of selected PHASE in which I/O Write Data is Removed. DataValid is de-activated along with this.
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x000B0 S1_PHY_IOWR_DREMOVE  (P)
///               %unsigned 8  PHASE                     0x4
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x1E
///               %%        16         # Stuffing bits...
///     @ 0x000B4 S0_PHY_MEMW_DLAUNCH  (P)
///               %unsigned 8  PHASE                     0x2
///                                    ###
///                                    * Phase in which Memory Write Data is Latched
///                                    ###
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x1B
///                                    ###
///                                    * Cycle of selected PHASE in which Memory Write Data is Launched. DataValid is activated along with this.
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x000B8 S1_PHY_MEMW_DLAUNCH  (P)
///               %unsigned 8  PHASE                     0x2
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x1B
///               %%        16         # Stuffing bits...
///     @ 0x000BC S0_PHY_MEM_DREMOVE   (P)
///               %unsigned 8  PHASE                     0x4
///                                    ###
///                                    * Phase in which Memory Write Data is Removed
///                                    ###
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x1B
///                                    ###
///                                    * Cycle of selected PHASE in which Memory Write Data is Removed. DataValid is de-activated along with this.
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x000C0 S1_PHY_MEM_DREMOVE   (P)
///               %unsigned 8  PHASE                     0x4
///                                    : SU                        0x1
///                                    : PRE_WAIT                  0x2
///                                    : WAIT                      0x3
///                                    : HO                        0x4
///               %unsigned 8  CYCLE                     0x1B
///               %%        16         # Stuffing bits...
///     @ 0x000C4 TICK                 (P)
///               %unsigned 10 US                        0x12C
///                                    ###
///                                    * Number of cicCoreClk cycles for which tick_us event (one cicCoreClk pulse) is generated.
///                                    ###
///               %unsigned 10 MS                        0x3E8
///                                    ###
///                                    * Number of “tick_us” cycles for which tick_ms event (one cicCoreClk pulse) is generated.
///                                    ###
///               %unsigned 10 SEC                       0x3E8
///                                    ###
///                                    * Number of “tick_ms” cycles for which tick_sec event (one cicCoreClk pulse) is generated.
///                                    ###
///               %%        2          # Stuffing bits...
///     @ 0x000C8 S0_HS0               (P)
///               %unsigned 2  VS1_MON_TICK_SEL          0x2
///                                    ###
///                                    * Selection of tick for VS1_MON_TIME
///                                    ###
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 VS1_MON_TICK_CNT          0x33
///                                    ###
///                                    * Time duration in terms of selected tick. Used to wait for this much time after Card Insertion
///                                    ###
///               %unsigned 2  VCC_STABLE_TICK_SEL       0x2
///                                    ###
///                                    * Selection of tick for VCC_STABLE_TIME
///                                    ###
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 VCC_STABLE_TICK_CNT       0x12D
///                                    ###
///                                    * Time duration in terms of selected tick. HOT_SWAP_SM waits for this time after driving VCCSW and VCCSEL with valid values. Used during Card Insertion
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x000CC S1_HS0               (P)
///               %unsigned 2  VS1_MON_TICK_SEL          0x2
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 VS1_MON_TICK_CNT          0x33
///               %unsigned 2  VCC_STABLE_TICK_SEL       0x2
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 VCC_STABLE_TICK_CNT       0x12D
///               %%        8          # Stuffing bits...
///     @ 0x000D0 S0_HS1               (P)
///               %unsigned 2  RST_HIGH_TICK_SEL         0x1
///                                    ###
///                                    * Selection of tick for RST_HIGH_TIME
///                                    ###
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 RST_HIGH_TICK_CNT         0xB
///                                    ###
///                                    * Time duration in terms of selected tick. HOT_SWAP_SM waits for this time after applying RESET. Used during Card Insertion.
///                                    ###
///               %unsigned 2  WAIT_READY_TICK_SEL       0x2
///                                    ###
///                                    * Selection of tick for RST_HIGH_TIME
///                                    ###
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 WAIT_READY_TICK_CNT       0x15
///                                    ###
///                                    * Time duration in terms of selected tick. HOT_SWAP_SM waits for this time before checking state of READY(IREQ) pin. Used during Card Insertion.
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x000D4 S1_HS1               (P)
///               %unsigned 2  RST_HIGH_TICK_SEL         0x1
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 RST_HIGH_TICK_CNT         0xB
///               %unsigned 2  WAIT_READY_TICK_SEL       0x2
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 WAIT_READY_TICK_CNT       0x15
///               %%        8          # Stuffing bits...
///     @ 0x000D8 S0_HS2               (P)
///               %unsigned 2  CE_HIGH_TICK_SEL          0x2
///                                    ###
///                                    * Selection of tick for CE_HIGH_TIME
///                                    ###
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 CE_HIGH_TICK_CNT          0x15
///                                    ###
///                                    * Time duration in terms of selected tick. HOT_SWAP_SM waits for this time after CD==1 and CE==1 event. Used during Card Removal.
///                                    ###
///               %unsigned 2  RST_Z_TICK_SEL            0x1
///                                    ###
///                                    * Selection of tick for RST_Z_TIME
///                                    ###
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 RST_Z_TICK_CNT            0x1
///                                    ###
///                                    * Time duration in terms of selected tick. HOT_SWAP_SM waits for this time before driving VCCSW=0. Used during Card Removal.
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x000DC S1_HS2               (P)
///               %unsigned 2  CE_HIGH_TICK_SEL          0x2
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 CE_HIGH_TICK_CNT          0x15
///               %unsigned 2  RST_Z_TICK_SEL            0x1
///                                    : US                        0x1
///                                    : MS                        0x2
///                                    : SEC                       0x3
///               %unsigned 10 RST_Z_TICK_CNT            0x1
///               %%        8          # Stuffing bits...
///     @ 0x000E0 CLK                  (P)
///               %unsigned 1  CLKSWITCH                 0x1
///                                    : SRCCLK                    0x0
///                                    : DIVCLK                    0x1
///                                                 ###
///                                                 * Selects between source clock & divider clock
///                                                 ###
///               %unsigned 1  CLKD3SWITCH               0x0
///                                    : NONDIV3CLK                0x0
///                                    : DIV3CLK                   0x1
///                                                 ###
///                                                 * Selects between non-divide by-3 vs divide by-3 clocks.
///                                                 ###
///               %unsigned 1  CLKEN                     0x1
///                                    : DISABLE                   0x0
///                                    : ENABLE                    0x1
///                                                 ###
///                                                 * disable/enable control.
///                                                 ###
///               %unsigned 3  CLKSEL                    0x1
///                                    : D2                        0x1
///                                    : D4                        0x2
///                                    : D6                        0x3
///                                    : D8                        0x4
///                                    : D12                       0x5
///                                                 ###
///                                                 * clock selection.
///                                                 ###
///               %%        26         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     228B, bits:    1116b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CIC
#define h_CIC (){}

    #define     RA_CIC_CTRL                                    0x0000

    #define     BA_CIC_CTRL_HOST_TYPE                          0x0000
    #define     B16CIC_CTRL_HOST_TYPE                          0x0000
    #define   LSb32CIC_CTRL_HOST_TYPE                             0
    #define   LSb16CIC_CTRL_HOST_TYPE                             0
    #define       bCIC_CTRL_HOST_TYPE                          2
    #define   MSK32CIC_CTRL_HOST_TYPE                             0x00000003
    #define        CIC_CTRL_HOST_TYPE_CIP                                   0x1
    #define        CIC_CTRL_HOST_TYPE_S_HOST                                0x2
    #define        CIC_CTRL_HOST_TYPE_M_HOST                                0x3

    #define     BA_CIC_CTRL_RESET                              0x0000
    #define     B16CIC_CTRL_RESET                              0x0000
    #define   LSb32CIC_CTRL_RESET                                 2
    #define   LSb16CIC_CTRL_RESET                                 2
    #define       bCIC_CTRL_RESET                              1
    #define   MSK32CIC_CTRL_RESET                                 0x00000004

    #define     BA_CIC_CTRL_S0_CARD_EN                         0x0000
    #define     B16CIC_CTRL_S0_CARD_EN                         0x0000
    #define   LSb32CIC_CTRL_S0_CARD_EN                            3
    #define   LSb16CIC_CTRL_S0_CARD_EN                            3
    #define       bCIC_CTRL_S0_CARD_EN                         1
    #define   MSK32CIC_CTRL_S0_CARD_EN                            0x00000008

    #define     BA_CIC_CTRL_S1_CARD_EN                         0x0000
    #define     B16CIC_CTRL_S1_CARD_EN                         0x0000
    #define   LSb32CIC_CTRL_S1_CARD_EN                            4
    #define   LSb16CIC_CTRL_S1_CARD_EN                            4
    #define       bCIC_CTRL_S1_CARD_EN                         1
    #define   MSK32CIC_CTRL_S1_CARD_EN                            0x00000010

    #define     BA_CIC_CTRL_S0_HOT_SWAP_EN                     0x0000
    #define     B16CIC_CTRL_S0_HOT_SWAP_EN                     0x0000
    #define   LSb32CIC_CTRL_S0_HOT_SWAP_EN                        5
    #define   LSb16CIC_CTRL_S0_HOT_SWAP_EN                        5
    #define       bCIC_CTRL_S0_HOT_SWAP_EN                     1
    #define   MSK32CIC_CTRL_S0_HOT_SWAP_EN                        0x00000020

    #define     BA_CIC_CTRL_S1_HOT_SWAP_EN                     0x0000
    #define     B16CIC_CTRL_S1_HOT_SWAP_EN                     0x0000
    #define   LSb32CIC_CTRL_S1_HOT_SWAP_EN                        6
    #define   LSb16CIC_CTRL_S1_HOT_SWAP_EN                        6
    #define       bCIC_CTRL_S1_HOT_SWAP_EN                     1
    #define   MSK32CIC_CTRL_S1_HOT_SWAP_EN                        0x00000040

    #define     BA_CIC_CTRL_S0_OVERLOAD_EN                     0x0000
    #define     B16CIC_CTRL_S0_OVERLOAD_EN                     0x0000
    #define   LSb32CIC_CTRL_S0_OVERLOAD_EN                        7
    #define   LSb16CIC_CTRL_S0_OVERLOAD_EN                        7
    #define       bCIC_CTRL_S0_OVERLOAD_EN                     1
    #define   MSK32CIC_CTRL_S0_OVERLOAD_EN                        0x00000080

    #define     BA_CIC_CTRL_S1_OVERLOAD_EN                     0x0001
    #define     B16CIC_CTRL_S1_OVERLOAD_EN                     0x0000
    #define   LSb32CIC_CTRL_S1_OVERLOAD_EN                        8
    #define   LSb16CIC_CTRL_S1_OVERLOAD_EN                        8
    #define       bCIC_CTRL_S1_OVERLOAD_EN                     1
    #define   MSK32CIC_CTRL_S1_OVERLOAD_EN                        0x00000100

    #define     BA_CIC_CTRL_S0_CD_SINGLE_EN                    0x0001
    #define     B16CIC_CTRL_S0_CD_SINGLE_EN                    0x0000
    #define   LSb32CIC_CTRL_S0_CD_SINGLE_EN                       9
    #define   LSb16CIC_CTRL_S0_CD_SINGLE_EN                       9
    #define       bCIC_CTRL_S0_CD_SINGLE_EN                    1
    #define   MSK32CIC_CTRL_S0_CD_SINGLE_EN                       0x00000200

    #define     BA_CIC_CTRL_S1_CD_SINGLE_EN                    0x0001
    #define     B16CIC_CTRL_S1_CD_SINGLE_EN                    0x0000
    #define   LSb32CIC_CTRL_S1_CD_SINGLE_EN                       10
    #define   LSb16CIC_CTRL_S1_CD_SINGLE_EN                       10
    #define       bCIC_CTRL_S1_CD_SINGLE_EN                    1
    #define   MSK32CIC_CTRL_S1_CD_SINGLE_EN                       0x00000400

    #define     BA_CIC_CTRL_CAM_PHY_RESET                      0x0001
    #define     B16CIC_CTRL_CAM_PHY_RESET                      0x0000
    #define   LSb32CIC_CTRL_CAM_PHY_RESET                         11
    #define   LSb16CIC_CTRL_CAM_PHY_RESET                         11
    #define       bCIC_CTRL_CAM_PHY_RESET                      1
    #define   MSK32CIC_CTRL_CAM_PHY_RESET                         0x00000800

    #define     BA_CIC_CTRL_S0_CE1                             0x0001
    #define     B16CIC_CTRL_S0_CE1                             0x0000
    #define   LSb32CIC_CTRL_S0_CE1                                12
    #define   LSb16CIC_CTRL_S0_CE1                                12
    #define       bCIC_CTRL_S0_CE1                             1
    #define   MSK32CIC_CTRL_S0_CE1                                0x00001000

    #define     BA_CIC_CTRL_S1_CE1                             0x0001
    #define     B16CIC_CTRL_S1_CE1                             0x0000
    #define   LSb32CIC_CTRL_S1_CE1                                13
    #define   LSb16CIC_CTRL_S1_CE1                                13
    #define       bCIC_CTRL_S1_CE1                             1
    #define   MSK32CIC_CTRL_S1_CE1                                0x00002000

    #define     BA_CIC_CTRL_M_HOST_IQB_ER                      0x0001
    #define     B16CIC_CTRL_M_HOST_IQB_ER                      0x0000
    #define   LSb32CIC_CTRL_M_HOST_IQB_ER                         14
    #define   LSb16CIC_CTRL_M_HOST_IQB_ER                         14
    #define       bCIC_CTRL_M_HOST_IQB_ER                      1
    #define   MSK32CIC_CTRL_M_HOST_IQB_ER                         0x00004000

    #define     BA_CIC_CTRL_S_MODE_MX_EN                       0x0001
    #define     B16CIC_CTRL_S_MODE_MX_EN                       0x0000
    #define   LSb32CIC_CTRL_S_MODE_MX_EN                          15
    #define   LSb16CIC_CTRL_S_MODE_MX_EN                          15
    #define       bCIC_CTRL_S_MODE_MX_EN                       1
    #define   MSK32CIC_CTRL_S_MODE_MX_EN                          0x00008000

    #define     BA_CIC_CTRL_M_MODE_MX_EN                       0x0002
    #define     B16CIC_CTRL_M_MODE_MX_EN                       0x0002
    #define   LSb32CIC_CTRL_M_MODE_MX_EN                          16
    #define   LSb16CIC_CTRL_M_MODE_MX_EN                          0
    #define       bCIC_CTRL_M_MODE_MX_EN                       1
    #define   MSK32CIC_CTRL_M_MODE_MX_EN                          0x00010000

    #define     BA_CIC_CTRL_S0_VPP1SW                          0x0002
    #define     B16CIC_CTRL_S0_VPP1SW                          0x0002
    #define   LSb32CIC_CTRL_S0_VPP1SW                             17
    #define   LSb16CIC_CTRL_S0_VPP1SW                             1
    #define       bCIC_CTRL_S0_VPP1SW                          1
    #define   MSK32CIC_CTRL_S0_VPP1SW                             0x00020000

    #define     BA_CIC_CTRL_S0_VPP1SEL                         0x0002
    #define     B16CIC_CTRL_S0_VPP1SEL                         0x0002
    #define   LSb32CIC_CTRL_S0_VPP1SEL                            18
    #define   LSb16CIC_CTRL_S0_VPP1SEL                            2
    #define       bCIC_CTRL_S0_VPP1SEL                         1
    #define   MSK32CIC_CTRL_S0_VPP1SEL                            0x00040000

    #define     BA_CIC_CTRL_S0_VPP2SW                          0x0002
    #define     B16CIC_CTRL_S0_VPP2SW                          0x0002
    #define   LSb32CIC_CTRL_S0_VPP2SW                             19
    #define   LSb16CIC_CTRL_S0_VPP2SW                             3
    #define       bCIC_CTRL_S0_VPP2SW                          1
    #define   MSK32CIC_CTRL_S0_VPP2SW                             0x00080000

    #define     BA_CIC_CTRL_S0_VPP2SEL                         0x0002
    #define     B16CIC_CTRL_S0_VPP2SEL                         0x0002
    #define   LSb32CIC_CTRL_S0_VPP2SEL                            20
    #define   LSb16CIC_CTRL_S0_VPP2SEL                            4
    #define       bCIC_CTRL_S0_VPP2SEL                         1
    #define   MSK32CIC_CTRL_S0_VPP2SEL                            0x00100000

    #define     BA_CIC_CTRL_S0_VS2                             0x0002
    #define     B16CIC_CTRL_S0_VS2                             0x0002
    #define   LSb32CIC_CTRL_S0_VS2                                21
    #define   LSb16CIC_CTRL_S0_VS2                                5
    #define       bCIC_CTRL_S0_VS2                             1
    #define   MSK32CIC_CTRL_S0_VS2                                0x00200000

    #define     BA_CIC_CTRL_S0_VCCSW                           0x0002
    #define     B16CIC_CTRL_S0_VCCSW                           0x0002
    #define   LSb32CIC_CTRL_S0_VCCSW                              22
    #define   LSb16CIC_CTRL_S0_VCCSW                              6
    #define       bCIC_CTRL_S0_VCCSW                           1
    #define   MSK32CIC_CTRL_S0_VCCSW                              0x00400000

    #define     BA_CIC_CTRL_S1_VCCSW                           0x0002
    #define     B16CIC_CTRL_S1_VCCSW                           0x0002
    #define   LSb32CIC_CTRL_S1_VCCSW                              23
    #define   LSb16CIC_CTRL_S1_VCCSW                              7
    #define       bCIC_CTRL_S1_VCCSW                           1
    #define   MSK32CIC_CTRL_S1_VCCSW                              0x00800000

    #define     BA_CIC_CTRL_S0_CARD_RST                        0x0003
    #define     B16CIC_CTRL_S0_CARD_RST                        0x0002
    #define   LSb32CIC_CTRL_S0_CARD_RST                           24
    #define   LSb16CIC_CTRL_S0_CARD_RST                           8
    #define       bCIC_CTRL_S0_CARD_RST                        1
    #define   MSK32CIC_CTRL_S0_CARD_RST                           0x01000000

    #define     BA_CIC_CTRL_S1_CARD_RST                        0x0003
    #define     B16CIC_CTRL_S1_CARD_RST                        0x0002
    #define   LSb32CIC_CTRL_S1_CARD_RST                           25
    #define   LSb16CIC_CTRL_S1_CARD_RST                           9
    #define       bCIC_CTRL_S1_CARD_RST                        1
    #define   MSK32CIC_CTRL_S1_CARD_RST                           0x02000000

    #define     BA_CIC_CTRL_S0_VCC_SUPPORTED                   0x0003
    #define     B16CIC_CTRL_S0_VCC_SUPPORTED                   0x0002
    #define   LSb32CIC_CTRL_S0_VCC_SUPPORTED                      26
    #define   LSb16CIC_CTRL_S0_VCC_SUPPORTED                      10
    #define       bCIC_CTRL_S0_VCC_SUPPORTED                   2
    #define   MSK32CIC_CTRL_S0_VCC_SUPPORTED                      0x0C000000

    #define     BA_CIC_CTRL_S1_VCC_SUPPORTED                   0x0003
    #define     B16CIC_CTRL_S1_VCC_SUPPORTED                   0x0002
    #define   LSb32CIC_CTRL_S1_VCC_SUPPORTED                      28
    #define   LSb16CIC_CTRL_S1_VCC_SUPPORTED                      12
    #define       bCIC_CTRL_S1_VCC_SUPPORTED                   2
    #define   MSK32CIC_CTRL_S1_VCC_SUPPORTED                      0x30000000

    #define     BA_CIC_CTRL_S0_VCC_SEL                         0x0003
    #define     B16CIC_CTRL_S0_VCC_SEL                         0x0002
    #define   LSb32CIC_CTRL_S0_VCC_SEL                            30
    #define   LSb16CIC_CTRL_S0_VCC_SEL                            14
    #define       bCIC_CTRL_S0_VCC_SEL                         1
    #define   MSK32CIC_CTRL_S0_VCC_SEL                            0x40000000

    #define     BA_CIC_CTRL_S1_VCC_SEL                         0x0003
    #define     B16CIC_CTRL_S1_VCC_SEL                         0x0002
    #define   LSb32CIC_CTRL_S1_VCC_SEL                            31
    #define   LSb16CIC_CTRL_S1_VCC_SEL                            15
    #define       bCIC_CTRL_S1_VCC_SEL                         1
    #define   MSK32CIC_CTRL_S1_VCC_SEL                            0x80000000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_CMD                                     0x0004

    #define     BA_CIC_CMD_TYPE                                0x0004
    #define     B16CIC_CMD_TYPE                                0x0004
    #define   LSb32CIC_CMD_TYPE                                   0
    #define   LSb16CIC_CMD_TYPE                                   0
    #define       bCIC_CMD_TYPE                                3
    #define   MSK32CIC_CMD_TYPE                                   0x00000007
    #define        CIC_CMD_TYPE_DIRECT_READ                                 0x0
    #define        CIC_CMD_TYPE_DIRECT_WRITE                                0x1
    #define        CIC_CMD_TYPE_SINGLE_READ                                 0x2
    #define        CIC_CMD_TYPE_SINGLE_WRITE                                0x3
    #define        CIC_CMD_TYPE_BLOCK_READ                                  0x4
    #define        CIC_CMD_TYPE_BLOCK_WRITE                                 0x5
    #define        CIC_CMD_TYPE_CAM_START                                   0x6
    #define        CIC_CMD_TYPE_CAM_STOP                                    0x7

    #define     BA_CIC_CMD_SLOT_CH                             0x0004
    #define     B16CIC_CMD_SLOT_CH                             0x0004
    #define   LSb32CIC_CMD_SLOT_CH                                3
    #define   LSb16CIC_CMD_SLOT_CH                                3
    #define       bCIC_CMD_SLOT_CH                             1
    #define   MSK32CIC_CMD_SLOT_CH                                0x00000008
    #define        CIC_CMD_SLOT_CH_SLOT_CH0                                 0x0
    #define        CIC_CMD_SLOT_CH_SLOT_CH1                                 0x1

    #define     BA_CIC_CMD_PCMCIA_ADDR_INCR                    0x0004
    #define     B16CIC_CMD_PCMCIA_ADDR_INCR                    0x0004
    #define   LSb32CIC_CMD_PCMCIA_ADDR_INCR                       4
    #define   LSb16CIC_CMD_PCMCIA_ADDR_INCR                       4
    #define       bCIC_CMD_PCMCIA_ADDR_INCR                    1
    #define   MSK32CIC_CMD_PCMCIA_ADDR_INCR                       0x00000010

    #define     BA_CIC_CMD_BUF_BYTE_PACK                       0x0004
    #define     B16CIC_CMD_BUF_BYTE_PACK                       0x0004
    #define   LSb32CIC_CMD_BUF_BYTE_PACK                          5
    #define   LSb16CIC_CMD_BUF_BYTE_PACK                          5
    #define       bCIC_CMD_BUF_BYTE_PACK                       1
    #define   MSK32CIC_CMD_BUF_BYTE_PACK                          0x00000020

    #define     BA_CIC_CMD_IOA                                 0x0004
    #define     B16CIC_CMD_IOA                                 0x0004
    #define   LSb32CIC_CMD_IOA                                    6
    #define   LSb16CIC_CMD_IOA                                    6
    #define       bCIC_CMD_IOA                                 1
    #define   MSK32CIC_CMD_IOA                                    0x00000040

    #define     BA_CIC_CMD_REGA                                0x0004
    #define     B16CIC_CMD_REGA                                0x0004
    #define   LSb32CIC_CMD_REGA                                   7
    #define   LSb16CIC_CMD_REGA                                   7
    #define       bCIC_CMD_REGA                                1
    #define   MSK32CIC_CMD_REGA                                   0x00000080

    #define     BA_CIC_CMD_ADDR                                0x0005
    #define     B16CIC_CMD_ADDR                                0x0004
    #define   LSb32CIC_CMD_ADDR                                   8
    #define   LSb16CIC_CMD_ADDR                                   8
    #define       bCIC_CMD_ADDR                                15
    #define   MSK32CIC_CMD_ADDR                                   0x007FFF00

    #define     BA_CIC_CMD_BYTE_WR_DATA                        0x0006
    #define     B16CIC_CMD_BYTE_WR_DATA                        0x0006
    #define   LSb32CIC_CMD_BYTE_WR_DATA                           23
    #define   LSb16CIC_CMD_BYTE_WR_DATA                           7
    #define       bCIC_CMD_BYTE_WR_DATA                        8
    #define   MSK32CIC_CMD_BYTE_WR_DATA                           0x7F800000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_CTRL_OE0                                0x0008

    #define     BA_CIC_CTRL_OE0_S0_31_0                        0x0008
    #define     B16CIC_CTRL_OE0_S0_31_0                        0x0008
    #define   LSb32CIC_CTRL_OE0_S0_31_0                           0
    #define   LSb16CIC_CTRL_OE0_S0_31_0                           0
    #define       bCIC_CTRL_OE0_S0_31_0                        32
    #define   MSK32CIC_CTRL_OE0_S0_31_0                           0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_CTRL_OE1                                0x000C

    #define     BA_CIC_CTRL_OE1_S0_63_32                       0x000C
    #define     B16CIC_CTRL_OE1_S0_63_32                       0x000C
    #define   LSb32CIC_CTRL_OE1_S0_63_32                          0
    #define   LSb16CIC_CTRL_OE1_S0_63_32                          0
    #define       bCIC_CTRL_OE1_S0_63_32                       32
    #define   MSK32CIC_CTRL_OE1_S0_63_32                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_CTRL_OE2                                0x0010

    #define     BA_CIC_CTRL_OE2_S0_68_64                       0x0010
    #define     B16CIC_CTRL_OE2_S0_68_64                       0x0010
    #define   LSb32CIC_CTRL_OE2_S0_68_64                          0
    #define   LSb16CIC_CTRL_OE2_S0_68_64                          0
    #define       bCIC_CTRL_OE2_S0_68_64                       5
    #define   MSK32CIC_CTRL_OE2_S0_68_64                          0x0000001F

    #define     BA_CIC_CTRL_OE2_S1_07_CE1                      0x0010
    #define     B16CIC_CTRL_OE2_S1_07_CE1                      0x0010
    #define   LSb32CIC_CTRL_OE2_S1_07_CE1                         5
    #define   LSb16CIC_CTRL_OE2_S1_07_CE1                         5
    #define       bCIC_CTRL_OE2_S1_07_CE1                      1
    #define   MSK32CIC_CTRL_OE2_S1_07_CE1                         0x00000020

    #define     BA_CIC_CTRL_OE2_S1_42_CE2                      0x0010
    #define     B16CIC_CTRL_OE2_S1_42_CE2                      0x0010
    #define   LSb32CIC_CTRL_OE2_S1_42_CE2                         6
    #define   LSb16CIC_CTRL_OE2_S1_42_CE2                         6
    #define       bCIC_CTRL_OE2_S1_42_CE2                      1
    #define   MSK32CIC_CTRL_OE2_S1_42_CE2                         0x00000040

    #define     BA_CIC_CTRL_OE2_S1_58_RESET                    0x0010
    #define     B16CIC_CTRL_OE2_S1_58_RESET                    0x0010
    #define   LSb32CIC_CTRL_OE2_S1_58_RESET                       7
    #define   LSb16CIC_CTRL_OE2_S1_58_RESET                       7
    #define       bCIC_CTRL_OE2_S1_58_RESET                    1
    #define   MSK32CIC_CTRL_OE2_S1_58_RESET                       0x00000080

    #define     BA_CIC_CTRL_OE2_S1_43_VS1                      0x0011
    #define     B16CIC_CTRL_OE2_S1_43_VS1                      0x0010
    #define   LSb32CIC_CTRL_OE2_S1_43_VS1                         8
    #define   LSb16CIC_CTRL_OE2_S1_43_VS1                         8
    #define       bCIC_CTRL_OE2_S1_43_VS1                      1
    #define   MSK32CIC_CTRL_OE2_S1_43_VS1                         0x00000100

    #define     BA_CIC_CTRL_OE2_S1_16_IREQ_N                   0x0011
    #define     B16CIC_CTRL_OE2_S1_16_IREQ_N                   0x0010
    #define   LSb32CIC_CTRL_OE2_S1_16_IREQ_N                      9
    #define   LSb16CIC_CTRL_OE2_S1_16_IREQ_N                      9
    #define       bCIC_CTRL_OE2_S1_16_IREQ_N                   1
    #define   MSK32CIC_CTRL_OE2_S1_16_IREQ_N                      0x00000200

    #define     BA_CIC_CTRL_OE2_S1_36_CD1_N                    0x0011
    #define     B16CIC_CTRL_OE2_S1_36_CD1_N                    0x0010
    #define   LSb32CIC_CTRL_OE2_S1_36_CD1_N                       10
    #define   LSb16CIC_CTRL_OE2_S1_36_CD1_N                       10
    #define       bCIC_CTRL_OE2_S1_36_CD1_N                    1
    #define   MSK32CIC_CTRL_OE2_S1_36_CD1_N                       0x00000400

    #define     BA_CIC_CTRL_OE2_S1_67_CD2_N                    0x0011
    #define     B16CIC_CTRL_OE2_S1_67_CD2_N                    0x0010
    #define   LSb32CIC_CTRL_OE2_S1_67_CD2_N                       11
    #define   LSb16CIC_CTRL_OE2_S1_67_CD2_N                       11
    #define       bCIC_CTRL_OE2_S1_67_CD2_N                    1
    #define   MSK32CIC_CTRL_OE2_S1_67_CD2_N                       0x00000800

    #define     BA_CIC_CTRL_OE2_S1_60_INPACK_N                 0x0011
    #define     B16CIC_CTRL_OE2_S1_60_INPACK_N                 0x0010
    #define   LSb32CIC_CTRL_OE2_S1_60_INPACK_N                    12
    #define   LSb16CIC_CTRL_OE2_S1_60_INPACK_N                    12
    #define       bCIC_CTRL_OE2_S1_60_INPACK_N                 1
    #define   MSK32CIC_CTRL_OE2_S1_60_INPACK_N                    0x00001000

    #define     BA_CIC_CTRL_OE2_S1_59_WAIT_N                   0x0011
    #define     B16CIC_CTRL_OE2_S1_59_WAIT_N                   0x0010
    #define   LSb32CIC_CTRL_OE2_S1_59_WAIT_N                      13
    #define   LSb16CIC_CTRL_OE2_S1_59_WAIT_N                      13
    #define       bCIC_CTRL_OE2_S1_59_WAIT_N                   1
    #define   MSK32CIC_CTRL_OE2_S1_59_WAIT_N                      0x00002000

    #define     BA_CIC_CTRL_OE2_VC_S0_VCC_SW                   0x0011
    #define     B16CIC_CTRL_OE2_VC_S0_VCC_SW                   0x0010
    #define   LSb32CIC_CTRL_OE2_VC_S0_VCC_SW                      14
    #define   LSb16CIC_CTRL_OE2_VC_S0_VCC_SW                      14
    #define       bCIC_CTRL_OE2_VC_S0_VCC_SW                   1
    #define   MSK32CIC_CTRL_OE2_VC_S0_VCC_SW                      0x00004000

    #define     BA_CIC_CTRL_OE2_VC_S0_VCC_SEL                  0x0011
    #define     B16CIC_CTRL_OE2_VC_S0_VCC_SEL                  0x0010
    #define   LSb32CIC_CTRL_OE2_VC_S0_VCC_SEL                     15
    #define   LSb16CIC_CTRL_OE2_VC_S0_VCC_SEL                     15
    #define       bCIC_CTRL_OE2_VC_S0_VCC_SEL                  1
    #define   MSK32CIC_CTRL_OE2_VC_S0_VCC_SEL                     0x00008000

    #define     BA_CIC_CTRL_OE2_VC_S0_VPP1_SW                  0x0012
    #define     B16CIC_CTRL_OE2_VC_S0_VPP1_SW                  0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S0_VPP1_SW                     16
    #define   LSb16CIC_CTRL_OE2_VC_S0_VPP1_SW                     0
    #define       bCIC_CTRL_OE2_VC_S0_VPP1_SW                  1
    #define   MSK32CIC_CTRL_OE2_VC_S0_VPP1_SW                     0x00010000

    #define     BA_CIC_CTRL_OE2_VC_S0_VPP1_SEL                 0x0012
    #define     B16CIC_CTRL_OE2_VC_S0_VPP1_SEL                 0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S0_VPP1_SEL                    17
    #define   LSb16CIC_CTRL_OE2_VC_S0_VPP1_SEL                    1
    #define       bCIC_CTRL_OE2_VC_S0_VPP1_SEL                 1
    #define   MSK32CIC_CTRL_OE2_VC_S0_VPP1_SEL                    0x00020000

    #define     BA_CIC_CTRL_OE2_VC_S0_VPP2_SW                  0x0012
    #define     B16CIC_CTRL_OE2_VC_S0_VPP2_SW                  0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S0_VPP2_SW                     18
    #define   LSb16CIC_CTRL_OE2_VC_S0_VPP2_SW                     2
    #define       bCIC_CTRL_OE2_VC_S0_VPP2_SW                  1
    #define   MSK32CIC_CTRL_OE2_VC_S0_VPP2_SW                     0x00040000

    #define     BA_CIC_CTRL_OE2_VC_S0_VPP2_SEL                 0x0012
    #define     B16CIC_CTRL_OE2_VC_S0_VPP2_SEL                 0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S0_VPP2_SEL                    19
    #define   LSb16CIC_CTRL_OE2_VC_S0_VPP2_SEL                    3
    #define       bCIC_CTRL_OE2_VC_S0_VPP2_SEL                 1
    #define   MSK32CIC_CTRL_OE2_VC_S0_VPP2_SEL                    0x00080000

    #define     BA_CIC_CTRL_OE2_VC_S1_VCC_SW                   0x0012
    #define     B16CIC_CTRL_OE2_VC_S1_VCC_SW                   0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S1_VCC_SW                      20
    #define   LSb16CIC_CTRL_OE2_VC_S1_VCC_SW                      4
    #define       bCIC_CTRL_OE2_VC_S1_VCC_SW                   1
    #define   MSK32CIC_CTRL_OE2_VC_S1_VCC_SW                      0x00100000

    #define     BA_CIC_CTRL_OE2_VC_S1_VCC_SEL                  0x0012
    #define     B16CIC_CTRL_OE2_VC_S1_VCC_SEL                  0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S1_VCC_SEL                     21
    #define   LSb16CIC_CTRL_OE2_VC_S1_VCC_SEL                     5
    #define       bCIC_CTRL_OE2_VC_S1_VCC_SEL                  1
    #define   MSK32CIC_CTRL_OE2_VC_S1_VCC_SEL                     0x00200000

    #define     BA_CIC_CTRL_OE2_VC_S0_OVERLOAD                 0x0012
    #define     B16CIC_CTRL_OE2_VC_S0_OVERLOAD                 0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S0_OVERLOAD                    22
    #define   LSb16CIC_CTRL_OE2_VC_S0_OVERLOAD                    6
    #define       bCIC_CTRL_OE2_VC_S0_OVERLOAD                 1
    #define   MSK32CIC_CTRL_OE2_VC_S0_OVERLOAD                    0x00400000

    #define     BA_CIC_CTRL_OE2_VC_S1_OVERLOAD                 0x0012
    #define     B16CIC_CTRL_OE2_VC_S1_OVERLOAD                 0x0012
    #define   LSb32CIC_CTRL_OE2_VC_S1_OVERLOAD                    23
    #define   LSb16CIC_CTRL_OE2_VC_S1_OVERLOAD                    7
    #define       bCIC_CTRL_OE2_VC_S1_OVERLOAD                 1
    #define   MSK32CIC_CTRL_OE2_VC_S1_OVERLOAD                    0x00800000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_CAM_REG_OFFSET                       0x0014

    #define     BA_CIC_S1_CAM_REG_OFFSET_VAL                   0x0014
    #define     B16CIC_S1_CAM_REG_OFFSET_VAL                   0x0014
    #define   LSb32CIC_S1_CAM_REG_OFFSET_VAL                      0
    #define   LSb16CIC_S1_CAM_REG_OFFSET_VAL                      0
    #define       bCIC_S1_CAM_REG_OFFSET_VAL                   15
    #define   MSK32CIC_S1_CAM_REG_OFFSET_VAL                      0x00007FFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_STATUS                                  0x0018

    #define     BA_CIC_STATUS_DIRECT_READ_PEND                 0x0018
    #define     B16CIC_STATUS_DIRECT_READ_PEND                 0x0018
    #define   LSb32CIC_STATUS_DIRECT_READ_PEND                    0
    #define   LSb16CIC_STATUS_DIRECT_READ_PEND                    0
    #define       bCIC_STATUS_DIRECT_READ_PEND                 1
    #define   MSK32CIC_STATUS_DIRECT_READ_PEND                    0x00000001

    #define     BA_CIC_STATUS_DIRECT_WRITE_PEND                0x0018
    #define     B16CIC_STATUS_DIRECT_WRITE_PEND                0x0018
    #define   LSb32CIC_STATUS_DIRECT_WRITE_PEND                   1
    #define   LSb16CIC_STATUS_DIRECT_WRITE_PEND                   1
    #define       bCIC_STATUS_DIRECT_WRITE_PEND                1
    #define   MSK32CIC_STATUS_DIRECT_WRITE_PEND                   0x00000002

    #define     BA_CIC_STATUS_SINGLE_READ_PEND                 0x0018
    #define     B16CIC_STATUS_SINGLE_READ_PEND                 0x0018
    #define   LSb32CIC_STATUS_SINGLE_READ_PEND                    2
    #define   LSb16CIC_STATUS_SINGLE_READ_PEND                    2
    #define       bCIC_STATUS_SINGLE_READ_PEND                 1
    #define   MSK32CIC_STATUS_SINGLE_READ_PEND                    0x00000004

    #define     BA_CIC_STATUS_SINGLE_WRITE_PEND                0x0018
    #define     B16CIC_STATUS_SINGLE_WRITE_PEND                0x0018
    #define   LSb32CIC_STATUS_SINGLE_WRITE_PEND                   3
    #define   LSb16CIC_STATUS_SINGLE_WRITE_PEND                   3
    #define       bCIC_STATUS_SINGLE_WRITE_PEND                1
    #define   MSK32CIC_STATUS_SINGLE_WRITE_PEND                   0x00000008

    #define     BA_CIC_STATUS_BLOCK_READ_PEND                  0x0018
    #define     B16CIC_STATUS_BLOCK_READ_PEND                  0x0018
    #define   LSb32CIC_STATUS_BLOCK_READ_PEND                     4
    #define   LSb16CIC_STATUS_BLOCK_READ_PEND                     4
    #define       bCIC_STATUS_BLOCK_READ_PEND                  1
    #define   MSK32CIC_STATUS_BLOCK_READ_PEND                     0x00000010

    #define     BA_CIC_STATUS_BLOCK_WRITE_PEND                 0x0018
    #define     B16CIC_STATUS_BLOCK_WRITE_PEND                 0x0018
    #define   LSb32CIC_STATUS_BLOCK_WRITE_PEND                    5
    #define   LSb16CIC_STATUS_BLOCK_WRITE_PEND                    5
    #define       bCIC_STATUS_BLOCK_WRITE_PEND                 1
    #define   MSK32CIC_STATUS_BLOCK_WRITE_PEND                    0x00000020

    #define     BA_CIC_STATUS_CAM_START_PEND                   0x0018
    #define     B16CIC_STATUS_CAM_START_PEND                   0x0018
    #define   LSb32CIC_STATUS_CAM_START_PEND                      6
    #define   LSb16CIC_STATUS_CAM_START_PEND                      6
    #define       bCIC_STATUS_CAM_START_PEND                   1
    #define   MSK32CIC_STATUS_CAM_START_PEND                      0x00000040

    #define     BA_CIC_STATUS_CAM_STOP_PEND                    0x0018
    #define     B16CIC_STATUS_CAM_STOP_PEND                    0x0018
    #define   LSb32CIC_STATUS_CAM_STOP_PEND                       7
    #define   LSb16CIC_STATUS_CAM_STOP_PEND                       7
    #define       bCIC_STATUS_CAM_STOP_PEND                    1
    #define   MSK32CIC_STATUS_CAM_STOP_PEND                       0x00000080

    #define     BA_CIC_STATUS_RX_BUF0_BUSY                     0x0019
    #define     B16CIC_STATUS_RX_BUF0_BUSY                     0x0018
    #define   LSb32CIC_STATUS_RX_BUF0_BUSY                        8
    #define   LSb16CIC_STATUS_RX_BUF0_BUSY                        8
    #define       bCIC_STATUS_RX_BUF0_BUSY                     1
    #define   MSK32CIC_STATUS_RX_BUF0_BUSY                        0x00000100

    #define     BA_CIC_STATUS_RX_BUF1_BUSY                     0x0019
    #define     B16CIC_STATUS_RX_BUF1_BUSY                     0x0018
    #define   LSb32CIC_STATUS_RX_BUF1_BUSY                        9
    #define   LSb16CIC_STATUS_RX_BUF1_BUSY                        9
    #define       bCIC_STATUS_RX_BUF1_BUSY                     1
    #define   MSK32CIC_STATUS_RX_BUF1_BUSY                        0x00000200

    #define     BA_CIC_STATUS_TX_BUF0_BUSY                     0x0019
    #define     B16CIC_STATUS_TX_BUF0_BUSY                     0x0018
    #define   LSb32CIC_STATUS_TX_BUF0_BUSY                        10
    #define   LSb16CIC_STATUS_TX_BUF0_BUSY                        10
    #define       bCIC_STATUS_TX_BUF0_BUSY                     1
    #define   MSK32CIC_STATUS_TX_BUF0_BUSY                        0x00000400

    #define     BA_CIC_STATUS_TX_BUF1_BUSY                     0x0019
    #define     B16CIC_STATUS_TX_BUF1_BUSY                     0x0018
    #define   LSb32CIC_STATUS_TX_BUF1_BUSY                        11
    #define   LSb16CIC_STATUS_TX_BUF1_BUSY                        11
    #define       bCIC_STATUS_TX_BUF1_BUSY                     1
    #define   MSK32CIC_STATUS_TX_BUF1_BUSY                        0x00000800
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_TX_BUF0_WIN                             0x001C

    #define     BA_CIC_TX_BUF0_WIN_LOC                         0x001C
    #define     B16CIC_TX_BUF0_WIN_LOC                         0x001C
    #define   LSb32CIC_TX_BUF0_WIN_LOC                            0
    #define   LSb16CIC_TX_BUF0_WIN_LOC                            0
    #define       bCIC_TX_BUF0_WIN_LOC                         32
    #define   MSK32CIC_TX_BUF0_WIN_LOC                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_TX_BUF1_WIN                             0x0020

    #define     BA_CIC_TX_BUF1_WIN_LOC                         0x0020
    #define     B16CIC_TX_BUF1_WIN_LOC                         0x0020
    #define   LSb32CIC_TX_BUF1_WIN_LOC                            0
    #define   LSb16CIC_TX_BUF1_WIN_LOC                            0
    #define       bCIC_TX_BUF1_WIN_LOC                         32
    #define   MSK32CIC_TX_BUF1_WIN_LOC                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_RX_BUF0_WIN                             0x0024

    #define     BA_CIC_RX_BUF0_WIN_LOC                         0x0024
    #define     B16CIC_RX_BUF0_WIN_LOC                         0x0024
    #define   LSb32CIC_RX_BUF0_WIN_LOC                            0
    #define   LSb16CIC_RX_BUF0_WIN_LOC                            0
    #define       bCIC_RX_BUF0_WIN_LOC                         32
    #define   MSK32CIC_RX_BUF0_WIN_LOC                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_RX_BUF1_WIN                             0x0028

    #define     BA_CIC_RX_BUF1_WIN_LOC                         0x0028
    #define     B16CIC_RX_BUF1_WIN_LOC                         0x0028
    #define   LSb32CIC_RX_BUF1_WIN_LOC                            0
    #define   LSb16CIC_RX_BUF1_WIN_LOC                            0
    #define       bCIC_RX_BUF1_WIN_LOC                         32
    #define   MSK32CIC_RX_BUF1_WIN_LOC                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_TX_BUF0_CFG                             0x002C

    #define     BA_CIC_TX_BUF0_CFG_SIZE                        0x002C
    #define     B16CIC_TX_BUF0_CFG_SIZE                        0x002C
    #define   LSb32CIC_TX_BUF0_CFG_SIZE                           0
    #define   LSb16CIC_TX_BUF0_CFG_SIZE                           0
    #define       bCIC_TX_BUF0_CFG_SIZE                        12
    #define   MSK32CIC_TX_BUF0_CFG_SIZE                           0x00000FFF

    #define     BA_CIC_TX_BUF0_CFG_PKT_F                       0x002D
    #define     B16CIC_TX_BUF0_CFG_PKT_F                       0x002C
    #define   LSb32CIC_TX_BUF0_CFG_PKT_F                          12
    #define   LSb16CIC_TX_BUF0_CFG_PKT_F                          12
    #define       bCIC_TX_BUF0_CFG_PKT_F                       1
    #define   MSK32CIC_TX_BUF0_CFG_PKT_F                          0x00001000

    #define     BA_CIC_TX_BUF0_CFG_PKT_L                       0x002D
    #define     B16CIC_TX_BUF0_CFG_PKT_L                       0x002C
    #define   LSb32CIC_TX_BUF0_CFG_PKT_L                          13
    #define   LSb16CIC_TX_BUF0_CFG_PKT_L                          13
    #define       bCIC_TX_BUF0_CFG_PKT_L                       1
    #define   MSK32CIC_TX_BUF0_CFG_PKT_L                          0x00002000

    #define     BA_CIC_TX_BUF0_CFG_BYTE_SWAP_EN                0x002D
    #define     B16CIC_TX_BUF0_CFG_BYTE_SWAP_EN                0x002C
    #define   LSb32CIC_TX_BUF0_CFG_BYTE_SWAP_EN                   14
    #define   LSb16CIC_TX_BUF0_CFG_BYTE_SWAP_EN                   14
    #define       bCIC_TX_BUF0_CFG_BYTE_SWAP_EN                1
    #define   MSK32CIC_TX_BUF0_CFG_BYTE_SWAP_EN                   0x00004000

    #define     BA_CIC_TX_BUF0_CFG_BIT_SWAP_EN                 0x002D
    #define     B16CIC_TX_BUF0_CFG_BIT_SWAP_EN                 0x002C
    #define   LSb32CIC_TX_BUF0_CFG_BIT_SWAP_EN                    15
    #define   LSb16CIC_TX_BUF0_CFG_BIT_SWAP_EN                    15
    #define       bCIC_TX_BUF0_CFG_BIT_SWAP_EN                 1
    #define   MSK32CIC_TX_BUF0_CFG_BIT_SWAP_EN                    0x00008000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_TX_BUF1_CFG                             0x0030

    #define     BA_CIC_TX_BUF1_CFG_SIZE                        0x0030
    #define     B16CIC_TX_BUF1_CFG_SIZE                        0x0030
    #define   LSb32CIC_TX_BUF1_CFG_SIZE                           0
    #define   LSb16CIC_TX_BUF1_CFG_SIZE                           0
    #define       bCIC_TX_BUF1_CFG_SIZE                        12
    #define   MSK32CIC_TX_BUF1_CFG_SIZE                           0x00000FFF

    #define     BA_CIC_TX_BUF1_CFG_PKT_F                       0x0031
    #define     B16CIC_TX_BUF1_CFG_PKT_F                       0x0030
    #define   LSb32CIC_TX_BUF1_CFG_PKT_F                          12
    #define   LSb16CIC_TX_BUF1_CFG_PKT_F                          12
    #define       bCIC_TX_BUF1_CFG_PKT_F                       1
    #define   MSK32CIC_TX_BUF1_CFG_PKT_F                          0x00001000

    #define     BA_CIC_TX_BUF1_CFG_PKT_L                       0x0031
    #define     B16CIC_TX_BUF1_CFG_PKT_L                       0x0030
    #define   LSb32CIC_TX_BUF1_CFG_PKT_L                          13
    #define   LSb16CIC_TX_BUF1_CFG_PKT_L                          13
    #define       bCIC_TX_BUF1_CFG_PKT_L                       1
    #define   MSK32CIC_TX_BUF1_CFG_PKT_L                          0x00002000

    #define     BA_CIC_TX_BUF1_CFG_BYTE_SWAP_EN                0x0031
    #define     B16CIC_TX_BUF1_CFG_BYTE_SWAP_EN                0x0030
    #define   LSb32CIC_TX_BUF1_CFG_BYTE_SWAP_EN                   14
    #define   LSb16CIC_TX_BUF1_CFG_BYTE_SWAP_EN                   14
    #define       bCIC_TX_BUF1_CFG_BYTE_SWAP_EN                1
    #define   MSK32CIC_TX_BUF1_CFG_BYTE_SWAP_EN                   0x00004000

    #define     BA_CIC_TX_BUF1_CFG_BIT_SWAP_EN                 0x0031
    #define     B16CIC_TX_BUF1_CFG_BIT_SWAP_EN                 0x0030
    #define   LSb32CIC_TX_BUF1_CFG_BIT_SWAP_EN                    15
    #define   LSb16CIC_TX_BUF1_CFG_BIT_SWAP_EN                    15
    #define       bCIC_TX_BUF1_CFG_BIT_SWAP_EN                 1
    #define   MSK32CIC_TX_BUF1_CFG_BIT_SWAP_EN                    0x00008000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_RX_BUF0_CFG                             0x0034

    #define     BA_CIC_RX_BUF0_CFG_SIZE                        0x0034
    #define     B16CIC_RX_BUF0_CFG_SIZE                        0x0034
    #define   LSb32CIC_RX_BUF0_CFG_SIZE                           0
    #define   LSb16CIC_RX_BUF0_CFG_SIZE                           0
    #define       bCIC_RX_BUF0_CFG_SIZE                        12
    #define   MSK32CIC_RX_BUF0_CFG_SIZE                           0x00000FFF

    #define     BA_CIC_RX_BUF0_CFG_PKT_F                       0x0035
    #define     B16CIC_RX_BUF0_CFG_PKT_F                       0x0034
    #define   LSb32CIC_RX_BUF0_CFG_PKT_F                          12
    #define   LSb16CIC_RX_BUF0_CFG_PKT_F                          12
    #define       bCIC_RX_BUF0_CFG_PKT_F                       1
    #define   MSK32CIC_RX_BUF0_CFG_PKT_F                          0x00001000

    #define     BA_CIC_RX_BUF0_CFG_PKT_L                       0x0035
    #define     B16CIC_RX_BUF0_CFG_PKT_L                       0x0034
    #define   LSb32CIC_RX_BUF0_CFG_PKT_L                          13
    #define   LSb16CIC_RX_BUF0_CFG_PKT_L                          13
    #define       bCIC_RX_BUF0_CFG_PKT_L                       1
    #define   MSK32CIC_RX_BUF0_CFG_PKT_L                          0x00002000

    #define     BA_CIC_RX_BUF0_CFG_BYTE_SWAP_EN                0x0035
    #define     B16CIC_RX_BUF0_CFG_BYTE_SWAP_EN                0x0034
    #define   LSb32CIC_RX_BUF0_CFG_BYTE_SWAP_EN                   14
    #define   LSb16CIC_RX_BUF0_CFG_BYTE_SWAP_EN                   14
    #define       bCIC_RX_BUF0_CFG_BYTE_SWAP_EN                1
    #define   MSK32CIC_RX_BUF0_CFG_BYTE_SWAP_EN                   0x00004000

    #define     BA_CIC_RX_BUF0_CFG_BIT_SWAP_EN                 0x0035
    #define     B16CIC_RX_BUF0_CFG_BIT_SWAP_EN                 0x0034
    #define   LSb32CIC_RX_BUF0_CFG_BIT_SWAP_EN                    15
    #define   LSb16CIC_RX_BUF0_CFG_BIT_SWAP_EN                    15
    #define       bCIC_RX_BUF0_CFG_BIT_SWAP_EN                 1
    #define   MSK32CIC_RX_BUF0_CFG_BIT_SWAP_EN                    0x00008000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_RX_BUF1_CFG                             0x0038

    #define     BA_CIC_RX_BUF1_CFG_SIZE                        0x0038
    #define     B16CIC_RX_BUF1_CFG_SIZE                        0x0038
    #define   LSb32CIC_RX_BUF1_CFG_SIZE                           0
    #define   LSb16CIC_RX_BUF1_CFG_SIZE                           0
    #define       bCIC_RX_BUF1_CFG_SIZE                        12
    #define   MSK32CIC_RX_BUF1_CFG_SIZE                           0x00000FFF

    #define     BA_CIC_RX_BUF1_CFG_PKT_F                       0x0039
    #define     B16CIC_RX_BUF1_CFG_PKT_F                       0x0038
    #define   LSb32CIC_RX_BUF1_CFG_PKT_F                          12
    #define   LSb16CIC_RX_BUF1_CFG_PKT_F                          12
    #define       bCIC_RX_BUF1_CFG_PKT_F                       1
    #define   MSK32CIC_RX_BUF1_CFG_PKT_F                          0x00001000

    #define     BA_CIC_RX_BUF1_CFG_PKT_L                       0x0039
    #define     B16CIC_RX_BUF1_CFG_PKT_L                       0x0038
    #define   LSb32CIC_RX_BUF1_CFG_PKT_L                          13
    #define   LSb16CIC_RX_BUF1_CFG_PKT_L                          13
    #define       bCIC_RX_BUF1_CFG_PKT_L                       1
    #define   MSK32CIC_RX_BUF1_CFG_PKT_L                          0x00002000

    #define     BA_CIC_RX_BUF1_CFG_BYTE_SWAP_EN                0x0039
    #define     B16CIC_RX_BUF1_CFG_BYTE_SWAP_EN                0x0038
    #define   LSb32CIC_RX_BUF1_CFG_BYTE_SWAP_EN                   14
    #define   LSb16CIC_RX_BUF1_CFG_BYTE_SWAP_EN                   14
    #define       bCIC_RX_BUF1_CFG_BYTE_SWAP_EN                1
    #define   MSK32CIC_RX_BUF1_CFG_BYTE_SWAP_EN                   0x00004000

    #define     BA_CIC_RX_BUF1_CFG_BIT_SWAP_EN                 0x0039
    #define     B16CIC_RX_BUF1_CFG_BIT_SWAP_EN                 0x0038
    #define   LSb32CIC_RX_BUF1_CFG_BIT_SWAP_EN                    15
    #define   LSb16CIC_RX_BUF1_CFG_BIT_SWAP_EN                    15
    #define       bCIC_RX_BUF1_CFG_BIT_SWAP_EN                 1
    #define   MSK32CIC_RX_BUF1_CFG_BIT_SWAP_EN                    0x00008000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_SB_RD_DATA                           0x003C

    #define     BA_CIC_S0_SB_RD_DATA_WINDOW                    0x003C
    #define     B16CIC_S0_SB_RD_DATA_WINDOW                    0x003C
    #define   LSb32CIC_S0_SB_RD_DATA_WINDOW                       0
    #define   LSb16CIC_S0_SB_RD_DATA_WINDOW                       0
    #define       bCIC_S0_SB_RD_DATA_WINDOW                    8
    #define   MSK32CIC_S0_SB_RD_DATA_WINDOW                       0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_SB_RD_DATA                           0x0040

    #define     BA_CIC_S1_SB_RD_DATA_WINDOW                    0x0040
    #define     B16CIC_S1_SB_RD_DATA_WINDOW                    0x0040
    #define   LSb32CIC_S1_SB_RD_DATA_WINDOW                       0
    #define   LSb16CIC_S1_SB_RD_DATA_WINDOW                       0
    #define       bCIC_S1_SB_RD_DATA_WINDOW                    8
    #define   MSK32CIC_S1_SB_RD_DATA_WINDOW                       0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_INT_STATUS                              0x0044

    #define     BA_CIC_INT_STATUS_S0_OVERLOAD                  0x0044
    #define     B16CIC_INT_STATUS_S0_OVERLOAD                  0x0044
    #define   LSb32CIC_INT_STATUS_S0_OVERLOAD                     0
    #define   LSb16CIC_INT_STATUS_S0_OVERLOAD                     0
    #define       bCIC_INT_STATUS_S0_OVERLOAD                  1
    #define   MSK32CIC_INT_STATUS_S0_OVERLOAD                     0x00000001

    #define     BA_CIC_INT_STATUS_S0_CARD_INSERT               0x0044
    #define     B16CIC_INT_STATUS_S0_CARD_INSERT               0x0044
    #define   LSb32CIC_INT_STATUS_S0_CARD_INSERT                  1
    #define   LSb16CIC_INT_STATUS_S0_CARD_INSERT                  1
    #define       bCIC_INT_STATUS_S0_CARD_INSERT               1
    #define   MSK32CIC_INT_STATUS_S0_CARD_INSERT                  0x00000002

    #define     BA_CIC_INT_STATUS_S0_CARD_REMOVE               0x0044
    #define     B16CIC_INT_STATUS_S0_CARD_REMOVE               0x0044
    #define   LSb32CIC_INT_STATUS_S0_CARD_REMOVE                  2
    #define   LSb16CIC_INT_STATUS_S0_CARD_REMOVE                  2
    #define       bCIC_INT_STATUS_S0_CARD_REMOVE               1
    #define   MSK32CIC_INT_STATUS_S0_CARD_REMOVE                  0x00000004

    #define     BA_CIC_INT_STATUS_S0_CARD_RDY                  0x0044
    #define     B16CIC_INT_STATUS_S0_CARD_RDY                  0x0044
    #define   LSb32CIC_INT_STATUS_S0_CARD_RDY                     3
    #define   LSb16CIC_INT_STATUS_S0_CARD_RDY                     3
    #define       bCIC_INT_STATUS_S0_CARD_RDY                  1
    #define   MSK32CIC_INT_STATUS_S0_CARD_RDY                     0x00000008

    #define     BA_CIC_INT_STATUS_S0_CARD_RDY_TO               0x0044
    #define     B16CIC_INT_STATUS_S0_CARD_RDY_TO               0x0044
    #define   LSb32CIC_INT_STATUS_S0_CARD_RDY_TO                  4
    #define   LSb16CIC_INT_STATUS_S0_CARD_RDY_TO                  4
    #define       bCIC_INT_STATUS_S0_CARD_RDY_TO               1
    #define   MSK32CIC_INT_STATUS_S0_CARD_RDY_TO                  0x00000010

    #define     BA_CIC_INT_STATUS_S0_IREQ                      0x0044
    #define     B16CIC_INT_STATUS_S0_IREQ                      0x0044
    #define   LSb32CIC_INT_STATUS_S0_IREQ                         5
    #define   LSb16CIC_INT_STATUS_S0_IREQ                         5
    #define       bCIC_INT_STATUS_S0_IREQ                      1
    #define   MSK32CIC_INT_STATUS_S0_IREQ                         0x00000020

    #define     BA_CIC_INT_STATUS_S0_BLOCK_WRITE               0x0044
    #define     B16CIC_INT_STATUS_S0_BLOCK_WRITE               0x0044
    #define   LSb32CIC_INT_STATUS_S0_BLOCK_WRITE                  6
    #define   LSb16CIC_INT_STATUS_S0_BLOCK_WRITE                  6
    #define       bCIC_INT_STATUS_S0_BLOCK_WRITE               1
    #define   MSK32CIC_INT_STATUS_S0_BLOCK_WRITE                  0x00000040

    #define     BA_CIC_INT_STATUS_S0_BLOCK_READ                0x0044
    #define     B16CIC_INT_STATUS_S0_BLOCK_READ                0x0044
    #define   LSb32CIC_INT_STATUS_S0_BLOCK_READ                   7
    #define   LSb16CIC_INT_STATUS_S0_BLOCK_READ                   7
    #define       bCIC_INT_STATUS_S0_BLOCK_READ                1
    #define   MSK32CIC_INT_STATUS_S0_BLOCK_READ                   0x00000080

    #define     BA_CIC_INT_STATUS_S0_SINGLE_WRITE              0x0045
    #define     B16CIC_INT_STATUS_S0_SINGLE_WRITE              0x0044
    #define   LSb32CIC_INT_STATUS_S0_SINGLE_WRITE                 8
    #define   LSb16CIC_INT_STATUS_S0_SINGLE_WRITE                 8
    #define       bCIC_INT_STATUS_S0_SINGLE_WRITE              1
    #define   MSK32CIC_INT_STATUS_S0_SINGLE_WRITE                 0x00000100

    #define     BA_CIC_INT_STATUS_S0_SINGLE_READ               0x0045
    #define     B16CIC_INT_STATUS_S0_SINGLE_READ               0x0044
    #define   LSb32CIC_INT_STATUS_S0_SINGLE_READ                  9
    #define   LSb16CIC_INT_STATUS_S0_SINGLE_READ                  9
    #define       bCIC_INT_STATUS_S0_SINGLE_READ               1
    #define   MSK32CIC_INT_STATUS_S0_SINGLE_READ                  0x00000200

    #define     BA_CIC_INT_STATUS_S0_CARD_ERR                  0x0045
    #define     B16CIC_INT_STATUS_S0_CARD_ERR                  0x0044
    #define   LSb32CIC_INT_STATUS_S0_CARD_ERR                     10
    #define   LSb16CIC_INT_STATUS_S0_CARD_ERR                     10
    #define       bCIC_INT_STATUS_S0_CARD_ERR                  1
    #define   MSK32CIC_INT_STATUS_S0_CARD_ERR                     0x00000400

    #define     BA_CIC_INT_STATUS_S1_OVERLOAD                  0x0045
    #define     B16CIC_INT_STATUS_S1_OVERLOAD                  0x0044
    #define   LSb32CIC_INT_STATUS_S1_OVERLOAD                     11
    #define   LSb16CIC_INT_STATUS_S1_OVERLOAD                     11
    #define       bCIC_INT_STATUS_S1_OVERLOAD                  1
    #define   MSK32CIC_INT_STATUS_S1_OVERLOAD                     0x00000800

    #define     BA_CIC_INT_STATUS_S1_CARD_INSERT               0x0045
    #define     B16CIC_INT_STATUS_S1_CARD_INSERT               0x0044
    #define   LSb32CIC_INT_STATUS_S1_CARD_INSERT                  12
    #define   LSb16CIC_INT_STATUS_S1_CARD_INSERT                  12
    #define       bCIC_INT_STATUS_S1_CARD_INSERT               1
    #define   MSK32CIC_INT_STATUS_S1_CARD_INSERT                  0x00001000

    #define     BA_CIC_INT_STATUS_S1_CARD_REMOVE               0x0045
    #define     B16CIC_INT_STATUS_S1_CARD_REMOVE               0x0044
    #define   LSb32CIC_INT_STATUS_S1_CARD_REMOVE                  13
    #define   LSb16CIC_INT_STATUS_S1_CARD_REMOVE                  13
    #define       bCIC_INT_STATUS_S1_CARD_REMOVE               1
    #define   MSK32CIC_INT_STATUS_S1_CARD_REMOVE                  0x00002000

    #define     BA_CIC_INT_STATUS_S1_CARD_RDY                  0x0045
    #define     B16CIC_INT_STATUS_S1_CARD_RDY                  0x0044
    #define   LSb32CIC_INT_STATUS_S1_CARD_RDY                     14
    #define   LSb16CIC_INT_STATUS_S1_CARD_RDY                     14
    #define       bCIC_INT_STATUS_S1_CARD_RDY                  1
    #define   MSK32CIC_INT_STATUS_S1_CARD_RDY                     0x00004000

    #define     BA_CIC_INT_STATUS_S1_CARD_RDY_TO               0x0045
    #define     B16CIC_INT_STATUS_S1_CARD_RDY_TO               0x0044
    #define   LSb32CIC_INT_STATUS_S1_CARD_RDY_TO                  15
    #define   LSb16CIC_INT_STATUS_S1_CARD_RDY_TO                  15
    #define       bCIC_INT_STATUS_S1_CARD_RDY_TO               1
    #define   MSK32CIC_INT_STATUS_S1_CARD_RDY_TO                  0x00008000

    #define     BA_CIC_INT_STATUS_S1_IREQ                      0x0046
    #define     B16CIC_INT_STATUS_S1_IREQ                      0x0046
    #define   LSb32CIC_INT_STATUS_S1_IREQ                         16
    #define   LSb16CIC_INT_STATUS_S1_IREQ                         0
    #define       bCIC_INT_STATUS_S1_IREQ                      1
    #define   MSK32CIC_INT_STATUS_S1_IREQ                         0x00010000

    #define     BA_CIC_INT_STATUS_S1_BLOCK_WRITE               0x0046
    #define     B16CIC_INT_STATUS_S1_BLOCK_WRITE               0x0046
    #define   LSb32CIC_INT_STATUS_S1_BLOCK_WRITE                  17
    #define   LSb16CIC_INT_STATUS_S1_BLOCK_WRITE                  1
    #define       bCIC_INT_STATUS_S1_BLOCK_WRITE               1
    #define   MSK32CIC_INT_STATUS_S1_BLOCK_WRITE                  0x00020000

    #define     BA_CIC_INT_STATUS_S1_BLOCK_READ                0x0046
    #define     B16CIC_INT_STATUS_S1_BLOCK_READ                0x0046
    #define   LSb32CIC_INT_STATUS_S1_BLOCK_READ                   18
    #define   LSb16CIC_INT_STATUS_S1_BLOCK_READ                   2
    #define       bCIC_INT_STATUS_S1_BLOCK_READ                1
    #define   MSK32CIC_INT_STATUS_S1_BLOCK_READ                   0x00040000

    #define     BA_CIC_INT_STATUS_S1_SINGLE_WRITE              0x0046
    #define     B16CIC_INT_STATUS_S1_SINGLE_WRITE              0x0046
    #define   LSb32CIC_INT_STATUS_S1_SINGLE_WRITE                 19
    #define   LSb16CIC_INT_STATUS_S1_SINGLE_WRITE                 3
    #define       bCIC_INT_STATUS_S1_SINGLE_WRITE              1
    #define   MSK32CIC_INT_STATUS_S1_SINGLE_WRITE                 0x00080000

    #define     BA_CIC_INT_STATUS_S1_SINGLE_READ               0x0046
    #define     B16CIC_INT_STATUS_S1_SINGLE_READ               0x0046
    #define   LSb32CIC_INT_STATUS_S1_SINGLE_READ                  20
    #define   LSb16CIC_INT_STATUS_S1_SINGLE_READ                  4
    #define       bCIC_INT_STATUS_S1_SINGLE_READ               1
    #define   MSK32CIC_INT_STATUS_S1_SINGLE_READ                  0x00100000

    #define     BA_CIC_INT_STATUS_S1_CARD_ERR                  0x0046
    #define     B16CIC_INT_STATUS_S1_CARD_ERR                  0x0046
    #define   LSb32CIC_INT_STATUS_S1_CARD_ERR                     21
    #define   LSb16CIC_INT_STATUS_S1_CARD_ERR                     5
    #define       bCIC_INT_STATUS_S1_CARD_ERR                  1
    #define   MSK32CIC_INT_STATUS_S1_CARD_ERR                     0x00200000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_INT_MASK                                0x0048

    #define     BA_CIC_INT_MASK_S0_OVERLOAD                    0x0048
    #define     B16CIC_INT_MASK_S0_OVERLOAD                    0x0048
    #define   LSb32CIC_INT_MASK_S0_OVERLOAD                       0
    #define   LSb16CIC_INT_MASK_S0_OVERLOAD                       0
    #define       bCIC_INT_MASK_S0_OVERLOAD                    1
    #define   MSK32CIC_INT_MASK_S0_OVERLOAD                       0x00000001

    #define     BA_CIC_INT_MASK_S0_CARD_INSERT                 0x0048
    #define     B16CIC_INT_MASK_S0_CARD_INSERT                 0x0048
    #define   LSb32CIC_INT_MASK_S0_CARD_INSERT                    1
    #define   LSb16CIC_INT_MASK_S0_CARD_INSERT                    1
    #define       bCIC_INT_MASK_S0_CARD_INSERT                 1
    #define   MSK32CIC_INT_MASK_S0_CARD_INSERT                    0x00000002

    #define     BA_CIC_INT_MASK_S0_CARD_REMOVE                 0x0048
    #define     B16CIC_INT_MASK_S0_CARD_REMOVE                 0x0048
    #define   LSb32CIC_INT_MASK_S0_CARD_REMOVE                    2
    #define   LSb16CIC_INT_MASK_S0_CARD_REMOVE                    2
    #define       bCIC_INT_MASK_S0_CARD_REMOVE                 1
    #define   MSK32CIC_INT_MASK_S0_CARD_REMOVE                    0x00000004

    #define     BA_CIC_INT_MASK_S0_CARD_RDY                    0x0048
    #define     B16CIC_INT_MASK_S0_CARD_RDY                    0x0048
    #define   LSb32CIC_INT_MASK_S0_CARD_RDY                       3
    #define   LSb16CIC_INT_MASK_S0_CARD_RDY                       3
    #define       bCIC_INT_MASK_S0_CARD_RDY                    1
    #define   MSK32CIC_INT_MASK_S0_CARD_RDY                       0x00000008

    #define     BA_CIC_INT_MASK_S0_CARD_RDY_TO                 0x0048
    #define     B16CIC_INT_MASK_S0_CARD_RDY_TO                 0x0048
    #define   LSb32CIC_INT_MASK_S0_CARD_RDY_TO                    4
    #define   LSb16CIC_INT_MASK_S0_CARD_RDY_TO                    4
    #define       bCIC_INT_MASK_S0_CARD_RDY_TO                 1
    #define   MSK32CIC_INT_MASK_S0_CARD_RDY_TO                    0x00000010

    #define     BA_CIC_INT_MASK_S0_IREQ                        0x0048
    #define     B16CIC_INT_MASK_S0_IREQ                        0x0048
    #define   LSb32CIC_INT_MASK_S0_IREQ                           5
    #define   LSb16CIC_INT_MASK_S0_IREQ                           5
    #define       bCIC_INT_MASK_S0_IREQ                        1
    #define   MSK32CIC_INT_MASK_S0_IREQ                           0x00000020

    #define     BA_CIC_INT_MASK_S0_BLOCK_WRITE                 0x0048
    #define     B16CIC_INT_MASK_S0_BLOCK_WRITE                 0x0048
    #define   LSb32CIC_INT_MASK_S0_BLOCK_WRITE                    6
    #define   LSb16CIC_INT_MASK_S0_BLOCK_WRITE                    6
    #define       bCIC_INT_MASK_S0_BLOCK_WRITE                 1
    #define   MSK32CIC_INT_MASK_S0_BLOCK_WRITE                    0x00000040

    #define     BA_CIC_INT_MASK_S0_BLOCK_READ                  0x0048
    #define     B16CIC_INT_MASK_S0_BLOCK_READ                  0x0048
    #define   LSb32CIC_INT_MASK_S0_BLOCK_READ                     7
    #define   LSb16CIC_INT_MASK_S0_BLOCK_READ                     7
    #define       bCIC_INT_MASK_S0_BLOCK_READ                  1
    #define   MSK32CIC_INT_MASK_S0_BLOCK_READ                     0x00000080

    #define     BA_CIC_INT_MASK_S0_SINGLE_WRITE                0x0049
    #define     B16CIC_INT_MASK_S0_SINGLE_WRITE                0x0048
    #define   LSb32CIC_INT_MASK_S0_SINGLE_WRITE                   8
    #define   LSb16CIC_INT_MASK_S0_SINGLE_WRITE                   8
    #define       bCIC_INT_MASK_S0_SINGLE_WRITE                1
    #define   MSK32CIC_INT_MASK_S0_SINGLE_WRITE                   0x00000100

    #define     BA_CIC_INT_MASK_S0_SINGLE_READ                 0x0049
    #define     B16CIC_INT_MASK_S0_SINGLE_READ                 0x0048
    #define   LSb32CIC_INT_MASK_S0_SINGLE_READ                    9
    #define   LSb16CIC_INT_MASK_S0_SINGLE_READ                    9
    #define       bCIC_INT_MASK_S0_SINGLE_READ                 1
    #define   MSK32CIC_INT_MASK_S0_SINGLE_READ                    0x00000200

    #define     BA_CIC_INT_MASK_S0_CARD_ERR                    0x0049
    #define     B16CIC_INT_MASK_S0_CARD_ERR                    0x0048
    #define   LSb32CIC_INT_MASK_S0_CARD_ERR                       10
    #define   LSb16CIC_INT_MASK_S0_CARD_ERR                       10
    #define       bCIC_INT_MASK_S0_CARD_ERR                    1
    #define   MSK32CIC_INT_MASK_S0_CARD_ERR                       0x00000400

    #define     BA_CIC_INT_MASK_S1_OVERLOAD                    0x0049
    #define     B16CIC_INT_MASK_S1_OVERLOAD                    0x0048
    #define   LSb32CIC_INT_MASK_S1_OVERLOAD                       11
    #define   LSb16CIC_INT_MASK_S1_OVERLOAD                       11
    #define       bCIC_INT_MASK_S1_OVERLOAD                    1
    #define   MSK32CIC_INT_MASK_S1_OVERLOAD                       0x00000800

    #define     BA_CIC_INT_MASK_S1_CARD_INSERT                 0x0049
    #define     B16CIC_INT_MASK_S1_CARD_INSERT                 0x0048
    #define   LSb32CIC_INT_MASK_S1_CARD_INSERT                    12
    #define   LSb16CIC_INT_MASK_S1_CARD_INSERT                    12
    #define       bCIC_INT_MASK_S1_CARD_INSERT                 1
    #define   MSK32CIC_INT_MASK_S1_CARD_INSERT                    0x00001000

    #define     BA_CIC_INT_MASK_S1_CARD_REMOVE                 0x0049
    #define     B16CIC_INT_MASK_S1_CARD_REMOVE                 0x0048
    #define   LSb32CIC_INT_MASK_S1_CARD_REMOVE                    13
    #define   LSb16CIC_INT_MASK_S1_CARD_REMOVE                    13
    #define       bCIC_INT_MASK_S1_CARD_REMOVE                 1
    #define   MSK32CIC_INT_MASK_S1_CARD_REMOVE                    0x00002000

    #define     BA_CIC_INT_MASK_S1_CARD_RDY                    0x0049
    #define     B16CIC_INT_MASK_S1_CARD_RDY                    0x0048
    #define   LSb32CIC_INT_MASK_S1_CARD_RDY                       14
    #define   LSb16CIC_INT_MASK_S1_CARD_RDY                       14
    #define       bCIC_INT_MASK_S1_CARD_RDY                    1
    #define   MSK32CIC_INT_MASK_S1_CARD_RDY                       0x00004000

    #define     BA_CIC_INT_MASK_S1_CARD_RDY_TO                 0x0049
    #define     B16CIC_INT_MASK_S1_CARD_RDY_TO                 0x0048
    #define   LSb32CIC_INT_MASK_S1_CARD_RDY_TO                    15
    #define   LSb16CIC_INT_MASK_S1_CARD_RDY_TO                    15
    #define       bCIC_INT_MASK_S1_CARD_RDY_TO                 1
    #define   MSK32CIC_INT_MASK_S1_CARD_RDY_TO                    0x00008000

    #define     BA_CIC_INT_MASK_S1_IREQ                        0x004A
    #define     B16CIC_INT_MASK_S1_IREQ                        0x004A
    #define   LSb32CIC_INT_MASK_S1_IREQ                           16
    #define   LSb16CIC_INT_MASK_S1_IREQ                           0
    #define       bCIC_INT_MASK_S1_IREQ                        1
    #define   MSK32CIC_INT_MASK_S1_IREQ                           0x00010000

    #define     BA_CIC_INT_MASK_S1_BLOCK_WRITE                 0x004A
    #define     B16CIC_INT_MASK_S1_BLOCK_WRITE                 0x004A
    #define   LSb32CIC_INT_MASK_S1_BLOCK_WRITE                    17
    #define   LSb16CIC_INT_MASK_S1_BLOCK_WRITE                    1
    #define       bCIC_INT_MASK_S1_BLOCK_WRITE                 1
    #define   MSK32CIC_INT_MASK_S1_BLOCK_WRITE                    0x00020000

    #define     BA_CIC_INT_MASK_S1_BLOCK_READ                  0x004A
    #define     B16CIC_INT_MASK_S1_BLOCK_READ                  0x004A
    #define   LSb32CIC_INT_MASK_S1_BLOCK_READ                     18
    #define   LSb16CIC_INT_MASK_S1_BLOCK_READ                     2
    #define       bCIC_INT_MASK_S1_BLOCK_READ                  1
    #define   MSK32CIC_INT_MASK_S1_BLOCK_READ                     0x00040000

    #define     BA_CIC_INT_MASK_S1_SINGLE_WRITE                0x004A
    #define     B16CIC_INT_MASK_S1_SINGLE_WRITE                0x004A
    #define   LSb32CIC_INT_MASK_S1_SINGLE_WRITE                   19
    #define   LSb16CIC_INT_MASK_S1_SINGLE_WRITE                   3
    #define       bCIC_INT_MASK_S1_SINGLE_WRITE                1
    #define   MSK32CIC_INT_MASK_S1_SINGLE_WRITE                   0x00080000

    #define     BA_CIC_INT_MASK_S1_SINGLE_READ                 0x004A
    #define     B16CIC_INT_MASK_S1_SINGLE_READ                 0x004A
    #define   LSb32CIC_INT_MASK_S1_SINGLE_READ                    20
    #define   LSb16CIC_INT_MASK_S1_SINGLE_READ                    4
    #define       bCIC_INT_MASK_S1_SINGLE_READ                 1
    #define   MSK32CIC_INT_MASK_S1_SINGLE_READ                    0x00100000

    #define     BA_CIC_INT_MASK_S1_CARD_ERR                    0x004A
    #define     B16CIC_INT_MASK_S1_CARD_ERR                    0x004A
    #define   LSb32CIC_INT_MASK_S1_CARD_ERR                       21
    #define   LSb16CIC_INT_MASK_S1_CARD_ERR                       5
    #define       bCIC_INT_MASK_S1_CARD_ERR                    1
    #define   MSK32CIC_INT_MASK_S1_CARD_ERR                       0x00200000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_INT_TRIG_POL                            0x004C

    #define     BA_CIC_INT_TRIG_POL_S0_OVERLOAD                0x004C
    #define     B16CIC_INT_TRIG_POL_S0_OVERLOAD                0x004C
    #define   LSb32CIC_INT_TRIG_POL_S0_OVERLOAD                   0
    #define   LSb16CIC_INT_TRIG_POL_S0_OVERLOAD                   0
    #define       bCIC_INT_TRIG_POL_S0_OVERLOAD                1
    #define   MSK32CIC_INT_TRIG_POL_S0_OVERLOAD                   0x00000001

    #define     BA_CIC_INT_TRIG_POL_S1_OVERLOAD                0x004C
    #define     B16CIC_INT_TRIG_POL_S1_OVERLOAD                0x004C
    #define   LSb32CIC_INT_TRIG_POL_S1_OVERLOAD                   1
    #define   LSb16CIC_INT_TRIG_POL_S1_OVERLOAD                   1
    #define       bCIC_INT_TRIG_POL_S1_OVERLOAD                1
    #define   MSK32CIC_INT_TRIG_POL_S1_OVERLOAD                   0x00000002

    #define     BA_CIC_INT_TRIG_POL_S0_CD                      0x004C
    #define     B16CIC_INT_TRIG_POL_S0_CD                      0x004C
    #define   LSb32CIC_INT_TRIG_POL_S0_CD                         2
    #define   LSb16CIC_INT_TRIG_POL_S0_CD                         2
    #define       bCIC_INT_TRIG_POL_S0_CD                      1
    #define   MSK32CIC_INT_TRIG_POL_S0_CD                         0x00000004

    #define     BA_CIC_INT_TRIG_POL_S1_CD                      0x004C
    #define     B16CIC_INT_TRIG_POL_S1_CD                      0x004C
    #define   LSb32CIC_INT_TRIG_POL_S1_CD                         3
    #define   LSb16CIC_INT_TRIG_POL_S1_CD                         3
    #define       bCIC_INT_TRIG_POL_S1_CD                      1
    #define   MSK32CIC_INT_TRIG_POL_S1_CD                         0x00000008

    #define     BA_CIC_INT_TRIG_POL_S0_IREQ                    0x004C
    #define     B16CIC_INT_TRIG_POL_S0_IREQ                    0x004C
    #define   LSb32CIC_INT_TRIG_POL_S0_IREQ                       4
    #define   LSb16CIC_INT_TRIG_POL_S0_IREQ                       4
    #define       bCIC_INT_TRIG_POL_S0_IREQ                    1
    #define   MSK32CIC_INT_TRIG_POL_S0_IREQ                       0x00000010

    #define     BA_CIC_INT_TRIG_POL_S1_IREQ                    0x004C
    #define     B16CIC_INT_TRIG_POL_S1_IREQ                    0x004C
    #define   LSb32CIC_INT_TRIG_POL_S1_IREQ                       5
    #define   LSb16CIC_INT_TRIG_POL_S1_IREQ                       5
    #define       bCIC_INT_TRIG_POL_S1_IREQ                    1
    #define   MSK32CIC_INT_TRIG_POL_S1_IREQ                       0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_DA                                      0x0050

    #define     BA_CIC_DA_REQ_CYC                              0x0050
    #define     B16CIC_DA_REQ_CYC                              0x0050
    #define   LSb32CIC_DA_REQ_CYC                                 0
    #define   LSb16CIC_DA_REQ_CYC                                 0
    #define       bCIC_DA_REQ_CYC                              8
    #define   MSK32CIC_DA_REQ_CYC                                 0x000000FF

    #define     BA_CIC_DA_PRI_EN                               0x0051
    #define     B16CIC_DA_PRI_EN                               0x0050
    #define   LSb32CIC_DA_PRI_EN                                  8
    #define   LSb16CIC_DA_PRI_EN                                  8
    #define       bCIC_DA_PRI_EN                               1
    #define   MSK32CIC_DA_PRI_EN                                  0x00000100
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_HC_DLY                                  0x0054

    #define     BA_CIC_HC_DLY_CLR                              0x0054
    #define     B16CIC_HC_DLY_CLR                              0x0054
    #define   LSb32CIC_HC_DLY_CLR                                 0
    #define   LSb16CIC_HC_DLY_CLR                                 0
    #define       bCIC_HC_DLY_CLR                              12
    #define   MSK32CIC_HC_DLY_CLR                                 0x00000FFF

    #define     BA_CIC_HC_DLY_RETRY                            0x0055
    #define     B16CIC_HC_DLY_RETRY                            0x0054
    #define   LSb32CIC_HC_DLY_RETRY                               12
    #define   LSb16CIC_HC_DLY_RETRY                               12
    #define       bCIC_HC_DLY_RETRY                            8
    #define   MSK32CIC_HC_DLY_RETRY                               0x000FF000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_PHY_MIRROR_STAT                         0x0058

    #define     BA_CIC_PHY_MIRROR_STAT_S0_OVERLOAD             0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S0_OVERLOAD             0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_OVERLOAD                0
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_OVERLOAD                0
    #define       bCIC_PHY_MIRROR_STAT_S0_OVERLOAD             1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_OVERLOAD                0x00000001

    #define     BA_CIC_PHY_MIRROR_STAT_S1_OVERLOAD             0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S1_OVERLOAD             0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S1_OVERLOAD                1
    #define   LSb16CIC_PHY_MIRROR_STAT_S1_OVERLOAD                1
    #define       bCIC_PHY_MIRROR_STAT_S1_OVERLOAD             1
    #define   MSK32CIC_PHY_MIRROR_STAT_S1_OVERLOAD                0x00000002

    #define     BA_CIC_PHY_MIRROR_STAT_S0_CD1                  0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S0_CD1                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_CD1                     2
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_CD1                     2
    #define       bCIC_PHY_MIRROR_STAT_S0_CD1                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_CD1                     0x00000004

    #define     BA_CIC_PHY_MIRROR_STAT_S1_CD1                  0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S1_CD1                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S1_CD1                     3
    #define   LSb16CIC_PHY_MIRROR_STAT_S1_CD1                     3
    #define       bCIC_PHY_MIRROR_STAT_S1_CD1                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S1_CD1                     0x00000008

    #define     BA_CIC_PHY_MIRROR_STAT_S0_CD2                  0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S0_CD2                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_CD2                     4
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_CD2                     4
    #define       bCIC_PHY_MIRROR_STAT_S0_CD2                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_CD2                     0x00000010

    #define     BA_CIC_PHY_MIRROR_STAT_S1_CD2                  0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S1_CD2                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S1_CD2                     5
    #define   LSb16CIC_PHY_MIRROR_STAT_S1_CD2                     5
    #define       bCIC_PHY_MIRROR_STAT_S1_CD2                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S1_CD2                     0x00000020

    #define     BA_CIC_PHY_MIRROR_STAT_S0_IREQ                 0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S0_IREQ                 0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_IREQ                    6
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_IREQ                    6
    #define       bCIC_PHY_MIRROR_STAT_S0_IREQ                 1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_IREQ                    0x00000040

    #define     BA_CIC_PHY_MIRROR_STAT_S1_IREQ                 0x0058
    #define     B16CIC_PHY_MIRROR_STAT_S1_IREQ                 0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S1_IREQ                    7
    #define   LSb16CIC_PHY_MIRROR_STAT_S1_IREQ                    7
    #define       bCIC_PHY_MIRROR_STAT_S1_IREQ                 1
    #define   MSK32CIC_PHY_MIRROR_STAT_S1_IREQ                    0x00000080

    #define     BA_CIC_PHY_MIRROR_STAT_S0_VS1                  0x0059
    #define     B16CIC_PHY_MIRROR_STAT_S0_VS1                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_VS1                     8
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_VS1                     8
    #define       bCIC_PHY_MIRROR_STAT_S0_VS1                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_VS1                     0x00000100

    #define     BA_CIC_PHY_MIRROR_STAT_S1_VS1                  0x0059
    #define     B16CIC_PHY_MIRROR_STAT_S1_VS1                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S1_VS1                     9
    #define   LSb16CIC_PHY_MIRROR_STAT_S1_VS1                     9
    #define       bCIC_PHY_MIRROR_STAT_S1_VS1                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S1_VS1                     0x00000200

    #define     BA_CIC_PHY_MIRROR_STAT_S0_VS2                  0x0059
    #define     B16CIC_PHY_MIRROR_STAT_S0_VS2                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_VS2                     10
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_VS2                     10
    #define       bCIC_PHY_MIRROR_STAT_S0_VS2                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_VS2                     0x00000400

    #define     BA_CIC_PHY_MIRROR_STAT_S0_MDET                 0x0059
    #define     B16CIC_PHY_MIRROR_STAT_S0_MDET                 0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_MDET                    11
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_MDET                    11
    #define       bCIC_PHY_MIRROR_STAT_S0_MDET                 1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_MDET                    0x00000800

    #define     BA_CIC_PHY_MIRROR_STAT_S0_SDO                  0x0059
    #define     B16CIC_PHY_MIRROR_STAT_S0_SDO                  0x0058
    #define   LSb32CIC_PHY_MIRROR_STAT_S0_SDO                     12
    #define   LSb16CIC_PHY_MIRROR_STAT_S0_SDO                     12
    #define       bCIC_PHY_MIRROR_STAT_S0_SDO                  1
    #define   MSK32CIC_PHY_MIRROR_STAT_S0_SDO                     0x00001000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_PH_CYC                           0x005C

    #define     BA_CIC_S0_PHY_PH_CYC_SU                        0x005C
    #define     B16CIC_S0_PHY_PH_CYC_SU                        0x005C
    #define   LSb32CIC_S0_PHY_PH_CYC_SU                           0
    #define   LSb16CIC_S0_PHY_PH_CYC_SU                           0
    #define       bCIC_S0_PHY_PH_CYC_SU                        8
    #define   MSK32CIC_S0_PHY_PH_CYC_SU                           0x000000FF

    #define     BA_CIC_S0_PHY_PH_CYC_PRE_WAIT                  0x005D
    #define     B16CIC_S0_PHY_PH_CYC_PRE_WAIT                  0x005C
    #define   LSb32CIC_S0_PHY_PH_CYC_PRE_WAIT                     8
    #define   LSb16CIC_S0_PHY_PH_CYC_PRE_WAIT                     8
    #define       bCIC_S0_PHY_PH_CYC_PRE_WAIT                  8
    #define   MSK32CIC_S0_PHY_PH_CYC_PRE_WAIT                     0x0000FF00

    #define     BA_CIC_S0_PHY_PH_CYC_WAIT                      0x005E
    #define     B16CIC_S0_PHY_PH_CYC_WAIT                      0x005E
    #define   LSb32CIC_S0_PHY_PH_CYC_WAIT                         16
    #define   LSb16CIC_S0_PHY_PH_CYC_WAIT                         0
    #define       bCIC_S0_PHY_PH_CYC_WAIT                      8
    #define   MSK32CIC_S0_PHY_PH_CYC_WAIT                         0x00FF0000

    #define     BA_CIC_S0_PHY_PH_CYC_HO                        0x005F
    #define     B16CIC_S0_PHY_PH_CYC_HO                        0x005E
    #define   LSb32CIC_S0_PHY_PH_CYC_HO                           24
    #define   LSb16CIC_S0_PHY_PH_CYC_HO                           8
    #define       bCIC_S0_PHY_PH_CYC_HO                        8
    #define   MSK32CIC_S0_PHY_PH_CYC_HO                           0xFF000000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_PH_CYC                           0x0060

    #define     BA_CIC_S1_PHY_PH_CYC_SU                        0x0060
    #define     B16CIC_S1_PHY_PH_CYC_SU                        0x0060
    #define   LSb32CIC_S1_PHY_PH_CYC_SU                           0
    #define   LSb16CIC_S1_PHY_PH_CYC_SU                           0
    #define       bCIC_S1_PHY_PH_CYC_SU                        8
    #define   MSK32CIC_S1_PHY_PH_CYC_SU                           0x000000FF

    #define     BA_CIC_S1_PHY_PH_CYC_PRE_WAIT                  0x0061
    #define     B16CIC_S1_PHY_PH_CYC_PRE_WAIT                  0x0060
    #define   LSb32CIC_S1_PHY_PH_CYC_PRE_WAIT                     8
    #define   LSb16CIC_S1_PHY_PH_CYC_PRE_WAIT                     8
    #define       bCIC_S1_PHY_PH_CYC_PRE_WAIT                  8
    #define   MSK32CIC_S1_PHY_PH_CYC_PRE_WAIT                     0x0000FF00

    #define     BA_CIC_S1_PHY_PH_CYC_WAIT                      0x0062
    #define     B16CIC_S1_PHY_PH_CYC_WAIT                      0x0062
    #define   LSb32CIC_S1_PHY_PH_CYC_WAIT                         16
    #define   LSb16CIC_S1_PHY_PH_CYC_WAIT                         0
    #define       bCIC_S1_PHY_PH_CYC_WAIT                      8
    #define   MSK32CIC_S1_PHY_PH_CYC_WAIT                         0x00FF0000

    #define     BA_CIC_S1_PHY_PH_CYC_HO                        0x0063
    #define     B16CIC_S1_PHY_PH_CYC_HO                        0x0062
    #define   LSb32CIC_S1_PHY_PH_CYC_HO                           24
    #define   LSb16CIC_S1_PHY_PH_CYC_HO                           8
    #define       bCIC_S1_PHY_PH_CYC_HO                        8
    #define   MSK32CIC_S1_PHY_PH_CYC_HO                           0xFF000000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_WAIT                             0x0064

    #define     BA_CIC_S0_PHY_WAIT_POL                         0x0064
    #define     B16CIC_S0_PHY_WAIT_POL                         0x0064
    #define   LSb32CIC_S0_PHY_WAIT_POL                            0
    #define   LSb16CIC_S0_PHY_WAIT_POL                            0
    #define       bCIC_S0_PHY_WAIT_POL                         1
    #define   MSK32CIC_S0_PHY_WAIT_POL                            0x00000001

    #define     BA_CIC_S0_PHY_WAIT_SYNC                        0x0064
    #define     B16CIC_S0_PHY_WAIT_SYNC                        0x0064
    #define   LSb32CIC_S0_PHY_WAIT_SYNC                           1
    #define   LSb16CIC_S0_PHY_WAIT_SYNC                           1
    #define       bCIC_S0_PHY_WAIT_SYNC                        1
    #define   MSK32CIC_S0_PHY_WAIT_SYNC                           0x00000002

    #define     BA_CIC_S0_PHY_WAIT_PRI                         0x0064
    #define     B16CIC_S0_PHY_WAIT_PRI                         0x0064
    #define   LSb32CIC_S0_PHY_WAIT_PRI                            2
    #define   LSb16CIC_S0_PHY_WAIT_PRI                            2
    #define       bCIC_S0_PHY_WAIT_PRI                         1
    #define   MSK32CIC_S0_PHY_WAIT_PRI                            0x00000004

    #define     BA_CIC_S0_PHY_WAIT_TIMEOUT_UNIT                0x0064
    #define     B16CIC_S0_PHY_WAIT_TIMEOUT_UNIT                0x0064
    #define   LSb32CIC_S0_PHY_WAIT_TIMEOUT_UNIT                   3
    #define   LSb16CIC_S0_PHY_WAIT_TIMEOUT_UNIT                   3
    #define       bCIC_S0_PHY_WAIT_TIMEOUT_UNIT                2
    #define   MSK32CIC_S0_PHY_WAIT_TIMEOUT_UNIT                   0x00000018
    #define        CIC_S0_PHY_WAIT_TIMEOUT_UNIT_cicCoreClk                  0x1
    #define        CIC_S0_PHY_WAIT_TIMEOUT_UNIT_US                          0x2
    #define        CIC_S0_PHY_WAIT_TIMEOUT_UNIT_MS                          0x3

    #define     BA_CIC_S0_PHY_WAIT_TIMEOUT_PERIOD              0x0064
    #define     B16CIC_S0_PHY_WAIT_TIMEOUT_PERIOD              0x0064
    #define   LSb32CIC_S0_PHY_WAIT_TIMEOUT_PERIOD                 5
    #define   LSb16CIC_S0_PHY_WAIT_TIMEOUT_PERIOD                 5
    #define       bCIC_S0_PHY_WAIT_TIMEOUT_PERIOD              10
    #define   MSK32CIC_S0_PHY_WAIT_TIMEOUT_PERIOD                 0x00007FE0
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_WAIT                             0x0068

    #define     BA_CIC_S1_PHY_WAIT_POL                         0x0068
    #define     B16CIC_S1_PHY_WAIT_POL                         0x0068
    #define   LSb32CIC_S1_PHY_WAIT_POL                            0
    #define   LSb16CIC_S1_PHY_WAIT_POL                            0
    #define       bCIC_S1_PHY_WAIT_POL                         1
    #define   MSK32CIC_S1_PHY_WAIT_POL                            0x00000001

    #define     BA_CIC_S1_PHY_WAIT_SYNC                        0x0068
    #define     B16CIC_S1_PHY_WAIT_SYNC                        0x0068
    #define   LSb32CIC_S1_PHY_WAIT_SYNC                           1
    #define   LSb16CIC_S1_PHY_WAIT_SYNC                           1
    #define       bCIC_S1_PHY_WAIT_SYNC                        1
    #define   MSK32CIC_S1_PHY_WAIT_SYNC                           0x00000002

    #define     BA_CIC_S1_PHY_WAIT_PRI                         0x0068
    #define     B16CIC_S1_PHY_WAIT_PRI                         0x0068
    #define   LSb32CIC_S1_PHY_WAIT_PRI                            2
    #define   LSb16CIC_S1_PHY_WAIT_PRI                            2
    #define       bCIC_S1_PHY_WAIT_PRI                         1
    #define   MSK32CIC_S1_PHY_WAIT_PRI                            0x00000004

    #define     BA_CIC_S1_PHY_WAIT_TIMEOUT_UNIT                0x0068
    #define     B16CIC_S1_PHY_WAIT_TIMEOUT_UNIT                0x0068
    #define   LSb32CIC_S1_PHY_WAIT_TIMEOUT_UNIT                   3
    #define   LSb16CIC_S1_PHY_WAIT_TIMEOUT_UNIT                   3
    #define       bCIC_S1_PHY_WAIT_TIMEOUT_UNIT                2
    #define   MSK32CIC_S1_PHY_WAIT_TIMEOUT_UNIT                   0x00000018
    #define        CIC_S1_PHY_WAIT_TIMEOUT_UNIT_cicCoreClk                  0x1
    #define        CIC_S1_PHY_WAIT_TIMEOUT_UNIT_US                          0x2
    #define        CIC_S1_PHY_WAIT_TIMEOUT_UNIT_MS                          0x3

    #define     BA_CIC_S1_PHY_WAIT_TIMEOUT_PERIOD              0x0068
    #define     B16CIC_S1_PHY_WAIT_TIMEOUT_PERIOD              0x0068
    #define   LSb32CIC_S1_PHY_WAIT_TIMEOUT_PERIOD                 5
    #define   LSb16CIC_S1_PHY_WAIT_TIMEOUT_PERIOD                 5
    #define       bCIC_S1_PHY_WAIT_TIMEOUT_PERIOD              10
    #define   MSK32CIC_S1_PHY_WAIT_TIMEOUT_PERIOD                 0x00007FE0
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_REG                              0x006C

    #define     BA_CIC_S0_PHY_REG_POL                          0x006C
    #define     B16CIC_S0_PHY_REG_POL                          0x006C
    #define   LSb32CIC_S0_PHY_REG_POL                             0
    #define   LSb16CIC_S0_PHY_REG_POL                             0
    #define       bCIC_S0_PHY_REG_POL                          1
    #define   MSK32CIC_S0_PHY_REG_POL                             0x00000001

    #define     BA_CIC_S0_PHY_REG_SU_TIM                       0x006C
    #define     B16CIC_S0_PHY_REG_SU_TIM                       0x006C
    #define   LSb32CIC_S0_PHY_REG_SU_TIM                          1
    #define   LSb16CIC_S0_PHY_REG_SU_TIM                          1
    #define       bCIC_S0_PHY_REG_SU_TIM                       8
    #define   MSK32CIC_S0_PHY_REG_SU_TIM                          0x000001FE

    #define     BA_CIC_S0_PHY_REG_HO_TIM                       0x006D
    #define     B16CIC_S0_PHY_REG_HO_TIM                       0x006C
    #define   LSb32CIC_S0_PHY_REG_HO_TIM                          9
    #define   LSb16CIC_S0_PHY_REG_HO_TIM                          9
    #define       bCIC_S0_PHY_REG_HO_TIM                       8
    #define   MSK32CIC_S0_PHY_REG_HO_TIM                          0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_REG                              0x0070

    #define     BA_CIC_S1_PHY_REG_POL                          0x0070
    #define     B16CIC_S1_PHY_REG_POL                          0x0070
    #define   LSb32CIC_S1_PHY_REG_POL                             0
    #define   LSb16CIC_S1_PHY_REG_POL                             0
    #define       bCIC_S1_PHY_REG_POL                          1
    #define   MSK32CIC_S1_PHY_REG_POL                             0x00000001

    #define     BA_CIC_S1_PHY_REG_SU_TIM                       0x0070
    #define     B16CIC_S1_PHY_REG_SU_TIM                       0x0070
    #define   LSb32CIC_S1_PHY_REG_SU_TIM                          1
    #define   LSb16CIC_S1_PHY_REG_SU_TIM                          1
    #define       bCIC_S1_PHY_REG_SU_TIM                       8
    #define   MSK32CIC_S1_PHY_REG_SU_TIM                          0x000001FE

    #define     BA_CIC_S1_PHY_REG_HO_TIM                       0x0071
    #define     B16CIC_S1_PHY_REG_HO_TIM                       0x0070
    #define   LSb32CIC_S1_PHY_REG_HO_TIM                          9
    #define   LSb16CIC_S1_PHY_REG_HO_TIM                          9
    #define       bCIC_S1_PHY_REG_HO_TIM                       8
    #define   MSK32CIC_S1_PHY_REG_HO_TIM                          0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_CE                               0x0074

    #define     BA_CIC_S0_PHY_CE_POL                           0x0074
    #define     B16CIC_S0_PHY_CE_POL                           0x0074
    #define   LSb32CIC_S0_PHY_CE_POL                              0
    #define   LSb16CIC_S0_PHY_CE_POL                              0
    #define       bCIC_S0_PHY_CE_POL                           1
    #define   MSK32CIC_S0_PHY_CE_POL                              0x00000001

    #define     BA_CIC_S0_PHY_CE_SU_TIM                        0x0074
    #define     B16CIC_S0_PHY_CE_SU_TIM                        0x0074
    #define   LSb32CIC_S0_PHY_CE_SU_TIM                           1
    #define   LSb16CIC_S0_PHY_CE_SU_TIM                           1
    #define       bCIC_S0_PHY_CE_SU_TIM                        8
    #define   MSK32CIC_S0_PHY_CE_SU_TIM                           0x000001FE

    #define     BA_CIC_S0_PHY_CE_HO_TIM                        0x0075
    #define     B16CIC_S0_PHY_CE_HO_TIM                        0x0074
    #define   LSb32CIC_S0_PHY_CE_HO_TIM                           9
    #define   LSb16CIC_S0_PHY_CE_HO_TIM                           9
    #define       bCIC_S0_PHY_CE_HO_TIM                        8
    #define   MSK32CIC_S0_PHY_CE_HO_TIM                           0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_CE                               0x0078

    #define     BA_CIC_S1_PHY_CE_POL                           0x0078
    #define     B16CIC_S1_PHY_CE_POL                           0x0078
    #define   LSb32CIC_S1_PHY_CE_POL                              0
    #define   LSb16CIC_S1_PHY_CE_POL                              0
    #define       bCIC_S1_PHY_CE_POL                           1
    #define   MSK32CIC_S1_PHY_CE_POL                              0x00000001

    #define     BA_CIC_S1_PHY_CE_SU_TIM                        0x0078
    #define     B16CIC_S1_PHY_CE_SU_TIM                        0x0078
    #define   LSb32CIC_S1_PHY_CE_SU_TIM                           1
    #define   LSb16CIC_S1_PHY_CE_SU_TIM                           1
    #define       bCIC_S1_PHY_CE_SU_TIM                        8
    #define   MSK32CIC_S1_PHY_CE_SU_TIM                           0x000001FE

    #define     BA_CIC_S1_PHY_CE_HO_TIM                        0x0079
    #define     B16CIC_S1_PHY_CE_HO_TIM                        0x0078
    #define   LSb32CIC_S1_PHY_CE_HO_TIM                           9
    #define   LSb16CIC_S1_PHY_CE_HO_TIM                           9
    #define       bCIC_S1_PHY_CE_HO_TIM                        8
    #define   MSK32CIC_S1_PHY_CE_HO_TIM                           0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_OE                               0x007C

    #define     BA_CIC_S0_PHY_OE_POL                           0x007C
    #define     B16CIC_S0_PHY_OE_POL                           0x007C
    #define   LSb32CIC_S0_PHY_OE_POL                              0
    #define   LSb16CIC_S0_PHY_OE_POL                              0
    #define       bCIC_S0_PHY_OE_POL                           1
    #define   MSK32CIC_S0_PHY_OE_POL                              0x00000001

    #define     BA_CIC_S0_PHY_OE_SU_TIM                        0x007C
    #define     B16CIC_S0_PHY_OE_SU_TIM                        0x007C
    #define   LSb32CIC_S0_PHY_OE_SU_TIM                           1
    #define   LSb16CIC_S0_PHY_OE_SU_TIM                           1
    #define       bCIC_S0_PHY_OE_SU_TIM                        8
    #define   MSK32CIC_S0_PHY_OE_SU_TIM                           0x000001FE

    #define     BA_CIC_S0_PHY_OE_HO_TIM                        0x007D
    #define     B16CIC_S0_PHY_OE_HO_TIM                        0x007C
    #define   LSb32CIC_S0_PHY_OE_HO_TIM                           9
    #define   LSb16CIC_S0_PHY_OE_HO_TIM                           9
    #define       bCIC_S0_PHY_OE_HO_TIM                        8
    #define   MSK32CIC_S0_PHY_OE_HO_TIM                           0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_OE                               0x0080

    #define     BA_CIC_S1_PHY_OE_POL                           0x0080
    #define     B16CIC_S1_PHY_OE_POL                           0x0080
    #define   LSb32CIC_S1_PHY_OE_POL                              0
    #define   LSb16CIC_S1_PHY_OE_POL                              0
    #define       bCIC_S1_PHY_OE_POL                           1
    #define   MSK32CIC_S1_PHY_OE_POL                              0x00000001

    #define     BA_CIC_S1_PHY_OE_SU_TIM                        0x0080
    #define     B16CIC_S1_PHY_OE_SU_TIM                        0x0080
    #define   LSb32CIC_S1_PHY_OE_SU_TIM                           1
    #define   LSb16CIC_S1_PHY_OE_SU_TIM                           1
    #define       bCIC_S1_PHY_OE_SU_TIM                        8
    #define   MSK32CIC_S1_PHY_OE_SU_TIM                           0x000001FE

    #define     BA_CIC_S1_PHY_OE_HO_TIM                        0x0081
    #define     B16CIC_S1_PHY_OE_HO_TIM                        0x0080
    #define   LSb32CIC_S1_PHY_OE_HO_TIM                           9
    #define   LSb16CIC_S1_PHY_OE_HO_TIM                           9
    #define       bCIC_S1_PHY_OE_HO_TIM                        8
    #define   MSK32CIC_S1_PHY_OE_HO_TIM                           0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_WE                               0x0084

    #define     BA_CIC_S0_PHY_WE_POL                           0x0084
    #define     B16CIC_S0_PHY_WE_POL                           0x0084
    #define   LSb32CIC_S0_PHY_WE_POL                              0
    #define   LSb16CIC_S0_PHY_WE_POL                              0
    #define       bCIC_S0_PHY_WE_POL                           1
    #define   MSK32CIC_S0_PHY_WE_POL                              0x00000001

    #define     BA_CIC_S0_PHY_WE_SU_TIM                        0x0084
    #define     B16CIC_S0_PHY_WE_SU_TIM                        0x0084
    #define   LSb32CIC_S0_PHY_WE_SU_TIM                           1
    #define   LSb16CIC_S0_PHY_WE_SU_TIM                           1
    #define       bCIC_S0_PHY_WE_SU_TIM                        8
    #define   MSK32CIC_S0_PHY_WE_SU_TIM                           0x000001FE

    #define     BA_CIC_S0_PHY_WE_HO_TIM                        0x0085
    #define     B16CIC_S0_PHY_WE_HO_TIM                        0x0084
    #define   LSb32CIC_S0_PHY_WE_HO_TIM                           9
    #define   LSb16CIC_S0_PHY_WE_HO_TIM                           9
    #define       bCIC_S0_PHY_WE_HO_TIM                        8
    #define   MSK32CIC_S0_PHY_WE_HO_TIM                           0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_WE                               0x0088

    #define     BA_CIC_S1_PHY_WE_POL                           0x0088
    #define     B16CIC_S1_PHY_WE_POL                           0x0088
    #define   LSb32CIC_S1_PHY_WE_POL                              0
    #define   LSb16CIC_S1_PHY_WE_POL                              0
    #define       bCIC_S1_PHY_WE_POL                           1
    #define   MSK32CIC_S1_PHY_WE_POL                              0x00000001

    #define     BA_CIC_S1_PHY_WE_SU_TIM                        0x0088
    #define     B16CIC_S1_PHY_WE_SU_TIM                        0x0088
    #define   LSb32CIC_S1_PHY_WE_SU_TIM                           1
    #define   LSb16CIC_S1_PHY_WE_SU_TIM                           1
    #define       bCIC_S1_PHY_WE_SU_TIM                        8
    #define   MSK32CIC_S1_PHY_WE_SU_TIM                           0x000001FE

    #define     BA_CIC_S1_PHY_WE_HO_TIM                        0x0089
    #define     B16CIC_S1_PHY_WE_HO_TIM                        0x0088
    #define   LSb32CIC_S1_PHY_WE_HO_TIM                           9
    #define   LSb16CIC_S1_PHY_WE_HO_TIM                           9
    #define       bCIC_S1_PHY_WE_HO_TIM                        8
    #define   MSK32CIC_S1_PHY_WE_HO_TIM                           0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_IORD                             0x008C

    #define     BA_CIC_S0_PHY_IORD_POL                         0x008C
    #define     B16CIC_S0_PHY_IORD_POL                         0x008C
    #define   LSb32CIC_S0_PHY_IORD_POL                            0
    #define   LSb16CIC_S0_PHY_IORD_POL                            0
    #define       bCIC_S0_PHY_IORD_POL                         1
    #define   MSK32CIC_S0_PHY_IORD_POL                            0x00000001

    #define     BA_CIC_S0_PHY_IORD_SU_TIM                      0x008C
    #define     B16CIC_S0_PHY_IORD_SU_TIM                      0x008C
    #define   LSb32CIC_S0_PHY_IORD_SU_TIM                         1
    #define   LSb16CIC_S0_PHY_IORD_SU_TIM                         1
    #define       bCIC_S0_PHY_IORD_SU_TIM                      8
    #define   MSK32CIC_S0_PHY_IORD_SU_TIM                         0x000001FE

    #define     BA_CIC_S0_PHY_IORD_HO_TIM                      0x008D
    #define     B16CIC_S0_PHY_IORD_HO_TIM                      0x008C
    #define   LSb32CIC_S0_PHY_IORD_HO_TIM                         9
    #define   LSb16CIC_S0_PHY_IORD_HO_TIM                         9
    #define       bCIC_S0_PHY_IORD_HO_TIM                      8
    #define   MSK32CIC_S0_PHY_IORD_HO_TIM                         0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_IORD                             0x0090

    #define     BA_CIC_S1_PHY_IORD_POL                         0x0090
    #define     B16CIC_S1_PHY_IORD_POL                         0x0090
    #define   LSb32CIC_S1_PHY_IORD_POL                            0
    #define   LSb16CIC_S1_PHY_IORD_POL                            0
    #define       bCIC_S1_PHY_IORD_POL                         1
    #define   MSK32CIC_S1_PHY_IORD_POL                            0x00000001

    #define     BA_CIC_S1_PHY_IORD_SU_TIM                      0x0090
    #define     B16CIC_S1_PHY_IORD_SU_TIM                      0x0090
    #define   LSb32CIC_S1_PHY_IORD_SU_TIM                         1
    #define   LSb16CIC_S1_PHY_IORD_SU_TIM                         1
    #define       bCIC_S1_PHY_IORD_SU_TIM                      8
    #define   MSK32CIC_S1_PHY_IORD_SU_TIM                         0x000001FE

    #define     BA_CIC_S1_PHY_IORD_HO_TIM                      0x0091
    #define     B16CIC_S1_PHY_IORD_HO_TIM                      0x0090
    #define   LSb32CIC_S1_PHY_IORD_HO_TIM                         9
    #define   LSb16CIC_S1_PHY_IORD_HO_TIM                         9
    #define       bCIC_S1_PHY_IORD_HO_TIM                      8
    #define   MSK32CIC_S1_PHY_IORD_HO_TIM                         0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_IOWR                             0x0094

    #define     BA_CIC_S0_PHY_IOWR_POL                         0x0094
    #define     B16CIC_S0_PHY_IOWR_POL                         0x0094
    #define   LSb32CIC_S0_PHY_IOWR_POL                            0
    #define   LSb16CIC_S0_PHY_IOWR_POL                            0
    #define       bCIC_S0_PHY_IOWR_POL                         1
    #define   MSK32CIC_S0_PHY_IOWR_POL                            0x00000001

    #define     BA_CIC_S0_PHY_IOWR_SU_TIM                      0x0094
    #define     B16CIC_S0_PHY_IOWR_SU_TIM                      0x0094
    #define   LSb32CIC_S0_PHY_IOWR_SU_TIM                         1
    #define   LSb16CIC_S0_PHY_IOWR_SU_TIM                         1
    #define       bCIC_S0_PHY_IOWR_SU_TIM                      8
    #define   MSK32CIC_S0_PHY_IOWR_SU_TIM                         0x000001FE

    #define     BA_CIC_S0_PHY_IOWR_HO_TIM                      0x0095
    #define     B16CIC_S0_PHY_IOWR_HO_TIM                      0x0094
    #define   LSb32CIC_S0_PHY_IOWR_HO_TIM                         9
    #define   LSb16CIC_S0_PHY_IOWR_HO_TIM                         9
    #define       bCIC_S0_PHY_IOWR_HO_TIM                      8
    #define   MSK32CIC_S0_PHY_IOWR_HO_TIM                         0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_IOWR                             0x0098

    #define     BA_CIC_S1_PHY_IOWR_POL                         0x0098
    #define     B16CIC_S1_PHY_IOWR_POL                         0x0098
    #define   LSb32CIC_S1_PHY_IOWR_POL                            0
    #define   LSb16CIC_S1_PHY_IOWR_POL                            0
    #define       bCIC_S1_PHY_IOWR_POL                         1
    #define   MSK32CIC_S1_PHY_IOWR_POL                            0x00000001

    #define     BA_CIC_S1_PHY_IOWR_SU_TIM                      0x0098
    #define     B16CIC_S1_PHY_IOWR_SU_TIM                      0x0098
    #define   LSb32CIC_S1_PHY_IOWR_SU_TIM                         1
    #define   LSb16CIC_S1_PHY_IOWR_SU_TIM                         1
    #define       bCIC_S1_PHY_IOWR_SU_TIM                      8
    #define   MSK32CIC_S1_PHY_IOWR_SU_TIM                         0x000001FE

    #define     BA_CIC_S1_PHY_IOWR_HO_TIM                      0x0099
    #define     B16CIC_S1_PHY_IOWR_HO_TIM                      0x0098
    #define   LSb32CIC_S1_PHY_IOWR_HO_TIM                         9
    #define   LSb16CIC_S1_PHY_IOWR_HO_TIM                         9
    #define       bCIC_S1_PHY_IOWR_HO_TIM                      8
    #define   MSK32CIC_S1_PHY_IOWR_HO_TIM                         0x0001FE00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_RD_DLAT                          0x009C

    #define     BA_CIC_S0_PHY_RD_DLAT_PHASE                    0x009C
    #define     B16CIC_S0_PHY_RD_DLAT_PHASE                    0x009C
    #define   LSb32CIC_S0_PHY_RD_DLAT_PHASE                       0
    #define   LSb16CIC_S0_PHY_RD_DLAT_PHASE                       0
    #define       bCIC_S0_PHY_RD_DLAT_PHASE                    8
    #define   MSK32CIC_S0_PHY_RD_DLAT_PHASE                       0x000000FF
    #define        CIC_S0_PHY_RD_DLAT_PHASE_SU                              0x1
    #define        CIC_S0_PHY_RD_DLAT_PHASE_PRE_WAIT                        0x2
    #define        CIC_S0_PHY_RD_DLAT_PHASE_WAIT                            0x3
    #define        CIC_S0_PHY_RD_DLAT_PHASE_HO                              0x4

    #define     BA_CIC_S0_PHY_RD_DLAT_CYCLE                    0x009D
    #define     B16CIC_S0_PHY_RD_DLAT_CYCLE                    0x009C
    #define   LSb32CIC_S0_PHY_RD_DLAT_CYCLE                       8
    #define   LSb16CIC_S0_PHY_RD_DLAT_CYCLE                       8
    #define       bCIC_S0_PHY_RD_DLAT_CYCLE                    8
    #define   MSK32CIC_S0_PHY_RD_DLAT_CYCLE                       0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_RD_DLAT                          0x00A0

    #define     BA_CIC_S1_PHY_RD_DLAT_PHASE                    0x00A0
    #define     B16CIC_S1_PHY_RD_DLAT_PHASE                    0x00A0
    #define   LSb32CIC_S1_PHY_RD_DLAT_PHASE                       0
    #define   LSb16CIC_S1_PHY_RD_DLAT_PHASE                       0
    #define       bCIC_S1_PHY_RD_DLAT_PHASE                    8
    #define   MSK32CIC_S1_PHY_RD_DLAT_PHASE                       0x000000FF
    #define        CIC_S1_PHY_RD_DLAT_PHASE_SU                              0x1
    #define        CIC_S1_PHY_RD_DLAT_PHASE_PRE_WAIT                        0x2
    #define        CIC_S1_PHY_RD_DLAT_PHASE_WAIT                            0x3
    #define        CIC_S1_PHY_RD_DLAT_PHASE_HO                              0x4

    #define     BA_CIC_S1_PHY_RD_DLAT_CYCLE                    0x00A1
    #define     B16CIC_S1_PHY_RD_DLAT_CYCLE                    0x00A0
    #define   LSb32CIC_S1_PHY_RD_DLAT_CYCLE                       8
    #define   LSb16CIC_S1_PHY_RD_DLAT_CYCLE                       8
    #define       bCIC_S1_PHY_RD_DLAT_CYCLE                    8
    #define   MSK32CIC_S1_PHY_RD_DLAT_CYCLE                       0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_IOWR_DLAUNCH                     0x00A4

    #define     BA_CIC_S0_PHY_IOWR_DLAUNCH_PHASE               0x00A4
    #define     B16CIC_S0_PHY_IOWR_DLAUNCH_PHASE               0x00A4
    #define   LSb32CIC_S0_PHY_IOWR_DLAUNCH_PHASE                  0
    #define   LSb16CIC_S0_PHY_IOWR_DLAUNCH_PHASE                  0
    #define       bCIC_S0_PHY_IOWR_DLAUNCH_PHASE               8
    #define   MSK32CIC_S0_PHY_IOWR_DLAUNCH_PHASE                  0x000000FF
    #define        CIC_S0_PHY_IOWR_DLAUNCH_PHASE_SU                         0x1
    #define        CIC_S0_PHY_IOWR_DLAUNCH_PHASE_PRE_WAIT                   0x2
    #define        CIC_S0_PHY_IOWR_DLAUNCH_PHASE_WAIT                       0x3
    #define        CIC_S0_PHY_IOWR_DLAUNCH_PHASE_HO                         0x4

    #define     BA_CIC_S0_PHY_IOWR_DLAUNCH_CYCLE               0x00A5
    #define     B16CIC_S0_PHY_IOWR_DLAUNCH_CYCLE               0x00A4
    #define   LSb32CIC_S0_PHY_IOWR_DLAUNCH_CYCLE                  8
    #define   LSb16CIC_S0_PHY_IOWR_DLAUNCH_CYCLE                  8
    #define       bCIC_S0_PHY_IOWR_DLAUNCH_CYCLE               8
    #define   MSK32CIC_S0_PHY_IOWR_DLAUNCH_CYCLE                  0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_IOWR_DLAUNCH                     0x00A8

    #define     BA_CIC_S1_PHY_IOWR_DLAUNCH_PHASE               0x00A8
    #define     B16CIC_S1_PHY_IOWR_DLAUNCH_PHASE               0x00A8
    #define   LSb32CIC_S1_PHY_IOWR_DLAUNCH_PHASE                  0
    #define   LSb16CIC_S1_PHY_IOWR_DLAUNCH_PHASE                  0
    #define       bCIC_S1_PHY_IOWR_DLAUNCH_PHASE               8
    #define   MSK32CIC_S1_PHY_IOWR_DLAUNCH_PHASE                  0x000000FF
    #define        CIC_S1_PHY_IOWR_DLAUNCH_PHASE_SU                         0x1
    #define        CIC_S1_PHY_IOWR_DLAUNCH_PHASE_PRE_WAIT                   0x2
    #define        CIC_S1_PHY_IOWR_DLAUNCH_PHASE_WAIT                       0x3
    #define        CIC_S1_PHY_IOWR_DLAUNCH_PHASE_HO                         0x4

    #define     BA_CIC_S1_PHY_IOWR_DLAUNCH_CYCLE               0x00A9
    #define     B16CIC_S1_PHY_IOWR_DLAUNCH_CYCLE               0x00A8
    #define   LSb32CIC_S1_PHY_IOWR_DLAUNCH_CYCLE                  8
    #define   LSb16CIC_S1_PHY_IOWR_DLAUNCH_CYCLE                  8
    #define       bCIC_S1_PHY_IOWR_DLAUNCH_CYCLE               8
    #define   MSK32CIC_S1_PHY_IOWR_DLAUNCH_CYCLE                  0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_IOWR_DREMOVE                     0x00AC

    #define     BA_CIC_S0_PHY_IOWR_DREMOVE_PHASE               0x00AC
    #define     B16CIC_S0_PHY_IOWR_DREMOVE_PHASE               0x00AC
    #define   LSb32CIC_S0_PHY_IOWR_DREMOVE_PHASE                  0
    #define   LSb16CIC_S0_PHY_IOWR_DREMOVE_PHASE                  0
    #define       bCIC_S0_PHY_IOWR_DREMOVE_PHASE               8
    #define   MSK32CIC_S0_PHY_IOWR_DREMOVE_PHASE                  0x000000FF
    #define        CIC_S0_PHY_IOWR_DREMOVE_PHASE_SU                         0x1
    #define        CIC_S0_PHY_IOWR_DREMOVE_PHASE_PRE_WAIT                   0x2
    #define        CIC_S0_PHY_IOWR_DREMOVE_PHASE_WAIT                       0x3
    #define        CIC_S0_PHY_IOWR_DREMOVE_PHASE_HO                         0x4

    #define     BA_CIC_S0_PHY_IOWR_DREMOVE_CYCLE               0x00AD
    #define     B16CIC_S0_PHY_IOWR_DREMOVE_CYCLE               0x00AC
    #define   LSb32CIC_S0_PHY_IOWR_DREMOVE_CYCLE                  8
    #define   LSb16CIC_S0_PHY_IOWR_DREMOVE_CYCLE                  8
    #define       bCIC_S0_PHY_IOWR_DREMOVE_CYCLE               8
    #define   MSK32CIC_S0_PHY_IOWR_DREMOVE_CYCLE                  0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_IOWR_DREMOVE                     0x00B0

    #define     BA_CIC_S1_PHY_IOWR_DREMOVE_PHASE               0x00B0
    #define     B16CIC_S1_PHY_IOWR_DREMOVE_PHASE               0x00B0
    #define   LSb32CIC_S1_PHY_IOWR_DREMOVE_PHASE                  0
    #define   LSb16CIC_S1_PHY_IOWR_DREMOVE_PHASE                  0
    #define       bCIC_S1_PHY_IOWR_DREMOVE_PHASE               8
    #define   MSK32CIC_S1_PHY_IOWR_DREMOVE_PHASE                  0x000000FF
    #define        CIC_S1_PHY_IOWR_DREMOVE_PHASE_SU                         0x1
    #define        CIC_S1_PHY_IOWR_DREMOVE_PHASE_PRE_WAIT                   0x2
    #define        CIC_S1_PHY_IOWR_DREMOVE_PHASE_WAIT                       0x3
    #define        CIC_S1_PHY_IOWR_DREMOVE_PHASE_HO                         0x4

    #define     BA_CIC_S1_PHY_IOWR_DREMOVE_CYCLE               0x00B1
    #define     B16CIC_S1_PHY_IOWR_DREMOVE_CYCLE               0x00B0
    #define   LSb32CIC_S1_PHY_IOWR_DREMOVE_CYCLE                  8
    #define   LSb16CIC_S1_PHY_IOWR_DREMOVE_CYCLE                  8
    #define       bCIC_S1_PHY_IOWR_DREMOVE_CYCLE               8
    #define   MSK32CIC_S1_PHY_IOWR_DREMOVE_CYCLE                  0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_MEMW_DLAUNCH                     0x00B4

    #define     BA_CIC_S0_PHY_MEMW_DLAUNCH_PHASE               0x00B4
    #define     B16CIC_S0_PHY_MEMW_DLAUNCH_PHASE               0x00B4
    #define   LSb32CIC_S0_PHY_MEMW_DLAUNCH_PHASE                  0
    #define   LSb16CIC_S0_PHY_MEMW_DLAUNCH_PHASE                  0
    #define       bCIC_S0_PHY_MEMW_DLAUNCH_PHASE               8
    #define   MSK32CIC_S0_PHY_MEMW_DLAUNCH_PHASE                  0x000000FF
    #define        CIC_S0_PHY_MEMW_DLAUNCH_PHASE_SU                         0x1
    #define        CIC_S0_PHY_MEMW_DLAUNCH_PHASE_PRE_WAIT                   0x2
    #define        CIC_S0_PHY_MEMW_DLAUNCH_PHASE_WAIT                       0x3
    #define        CIC_S0_PHY_MEMW_DLAUNCH_PHASE_HO                         0x4

    #define     BA_CIC_S0_PHY_MEMW_DLAUNCH_CYCLE               0x00B5
    #define     B16CIC_S0_PHY_MEMW_DLAUNCH_CYCLE               0x00B4
    #define   LSb32CIC_S0_PHY_MEMW_DLAUNCH_CYCLE                  8
    #define   LSb16CIC_S0_PHY_MEMW_DLAUNCH_CYCLE                  8
    #define       bCIC_S0_PHY_MEMW_DLAUNCH_CYCLE               8
    #define   MSK32CIC_S0_PHY_MEMW_DLAUNCH_CYCLE                  0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_MEMW_DLAUNCH                     0x00B8

    #define     BA_CIC_S1_PHY_MEMW_DLAUNCH_PHASE               0x00B8
    #define     B16CIC_S1_PHY_MEMW_DLAUNCH_PHASE               0x00B8
    #define   LSb32CIC_S1_PHY_MEMW_DLAUNCH_PHASE                  0
    #define   LSb16CIC_S1_PHY_MEMW_DLAUNCH_PHASE                  0
    #define       bCIC_S1_PHY_MEMW_DLAUNCH_PHASE               8
    #define   MSK32CIC_S1_PHY_MEMW_DLAUNCH_PHASE                  0x000000FF
    #define        CIC_S1_PHY_MEMW_DLAUNCH_PHASE_SU                         0x1
    #define        CIC_S1_PHY_MEMW_DLAUNCH_PHASE_PRE_WAIT                   0x2
    #define        CIC_S1_PHY_MEMW_DLAUNCH_PHASE_WAIT                       0x3
    #define        CIC_S1_PHY_MEMW_DLAUNCH_PHASE_HO                         0x4

    #define     BA_CIC_S1_PHY_MEMW_DLAUNCH_CYCLE               0x00B9
    #define     B16CIC_S1_PHY_MEMW_DLAUNCH_CYCLE               0x00B8
    #define   LSb32CIC_S1_PHY_MEMW_DLAUNCH_CYCLE                  8
    #define   LSb16CIC_S1_PHY_MEMW_DLAUNCH_CYCLE                  8
    #define       bCIC_S1_PHY_MEMW_DLAUNCH_CYCLE               8
    #define   MSK32CIC_S1_PHY_MEMW_DLAUNCH_CYCLE                  0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_PHY_MEM_DREMOVE                      0x00BC

    #define     BA_CIC_S0_PHY_MEM_DREMOVE_PHASE                0x00BC
    #define     B16CIC_S0_PHY_MEM_DREMOVE_PHASE                0x00BC
    #define   LSb32CIC_S0_PHY_MEM_DREMOVE_PHASE                   0
    #define   LSb16CIC_S0_PHY_MEM_DREMOVE_PHASE                   0
    #define       bCIC_S0_PHY_MEM_DREMOVE_PHASE                8
    #define   MSK32CIC_S0_PHY_MEM_DREMOVE_PHASE                   0x000000FF
    #define        CIC_S0_PHY_MEM_DREMOVE_PHASE_SU                          0x1
    #define        CIC_S0_PHY_MEM_DREMOVE_PHASE_PRE_WAIT                    0x2
    #define        CIC_S0_PHY_MEM_DREMOVE_PHASE_WAIT                        0x3
    #define        CIC_S0_PHY_MEM_DREMOVE_PHASE_HO                          0x4

    #define     BA_CIC_S0_PHY_MEM_DREMOVE_CYCLE                0x00BD
    #define     B16CIC_S0_PHY_MEM_DREMOVE_CYCLE                0x00BC
    #define   LSb32CIC_S0_PHY_MEM_DREMOVE_CYCLE                   8
    #define   LSb16CIC_S0_PHY_MEM_DREMOVE_CYCLE                   8
    #define       bCIC_S0_PHY_MEM_DREMOVE_CYCLE                8
    #define   MSK32CIC_S0_PHY_MEM_DREMOVE_CYCLE                   0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_PHY_MEM_DREMOVE                      0x00C0

    #define     BA_CIC_S1_PHY_MEM_DREMOVE_PHASE                0x00C0
    #define     B16CIC_S1_PHY_MEM_DREMOVE_PHASE                0x00C0
    #define   LSb32CIC_S1_PHY_MEM_DREMOVE_PHASE                   0
    #define   LSb16CIC_S1_PHY_MEM_DREMOVE_PHASE                   0
    #define       bCIC_S1_PHY_MEM_DREMOVE_PHASE                8
    #define   MSK32CIC_S1_PHY_MEM_DREMOVE_PHASE                   0x000000FF
    #define        CIC_S1_PHY_MEM_DREMOVE_PHASE_SU                          0x1
    #define        CIC_S1_PHY_MEM_DREMOVE_PHASE_PRE_WAIT                    0x2
    #define        CIC_S1_PHY_MEM_DREMOVE_PHASE_WAIT                        0x3
    #define        CIC_S1_PHY_MEM_DREMOVE_PHASE_HO                          0x4

    #define     BA_CIC_S1_PHY_MEM_DREMOVE_CYCLE                0x00C1
    #define     B16CIC_S1_PHY_MEM_DREMOVE_CYCLE                0x00C0
    #define   LSb32CIC_S1_PHY_MEM_DREMOVE_CYCLE                   8
    #define   LSb16CIC_S1_PHY_MEM_DREMOVE_CYCLE                   8
    #define       bCIC_S1_PHY_MEM_DREMOVE_CYCLE                8
    #define   MSK32CIC_S1_PHY_MEM_DREMOVE_CYCLE                   0x0000FF00
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_TICK                                    0x00C4

    #define     BA_CIC_TICK_US                                 0x00C4
    #define     B16CIC_TICK_US                                 0x00C4
    #define   LSb32CIC_TICK_US                                    0
    #define   LSb16CIC_TICK_US                                    0
    #define       bCIC_TICK_US                                 10
    #define   MSK32CIC_TICK_US                                    0x000003FF

    #define     BA_CIC_TICK_MS                                 0x00C5
    #define     B16CIC_TICK_MS                                 0x00C4
    #define   LSb32CIC_TICK_MS                                    10
    #define   LSb16CIC_TICK_MS                                    10
    #define       bCIC_TICK_MS                                 10
    #define   MSK32CIC_TICK_MS                                    0x000FFC00

    #define     BA_CIC_TICK_SEC                                0x00C6
    #define     B16CIC_TICK_SEC                                0x00C6
    #define   LSb32CIC_TICK_SEC                                   20
    #define   LSb16CIC_TICK_SEC                                   4
    #define       bCIC_TICK_SEC                                10
    #define   MSK32CIC_TICK_SEC                                   0x3FF00000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_HS0                                  0x00C8

    #define     BA_CIC_S0_HS0_VS1_MON_TICK_SEL                 0x00C8
    #define     B16CIC_S0_HS0_VS1_MON_TICK_SEL                 0x00C8
    #define   LSb32CIC_S0_HS0_VS1_MON_TICK_SEL                    0
    #define   LSb16CIC_S0_HS0_VS1_MON_TICK_SEL                    0
    #define       bCIC_S0_HS0_VS1_MON_TICK_SEL                 2
    #define   MSK32CIC_S0_HS0_VS1_MON_TICK_SEL                    0x00000003
    #define        CIC_S0_HS0_VS1_MON_TICK_SEL_US                           0x1
    #define        CIC_S0_HS0_VS1_MON_TICK_SEL_MS                           0x2
    #define        CIC_S0_HS0_VS1_MON_TICK_SEL_SEC                          0x3

    #define     BA_CIC_S0_HS0_VS1_MON_TICK_CNT                 0x00C8
    #define     B16CIC_S0_HS0_VS1_MON_TICK_CNT                 0x00C8
    #define   LSb32CIC_S0_HS0_VS1_MON_TICK_CNT                    2
    #define   LSb16CIC_S0_HS0_VS1_MON_TICK_CNT                    2
    #define       bCIC_S0_HS0_VS1_MON_TICK_CNT                 10
    #define   MSK32CIC_S0_HS0_VS1_MON_TICK_CNT                    0x00000FFC

    #define     BA_CIC_S0_HS0_VCC_STABLE_TICK_SEL              0x00C9
    #define     B16CIC_S0_HS0_VCC_STABLE_TICK_SEL              0x00C8
    #define   LSb32CIC_S0_HS0_VCC_STABLE_TICK_SEL                 12
    #define   LSb16CIC_S0_HS0_VCC_STABLE_TICK_SEL                 12
    #define       bCIC_S0_HS0_VCC_STABLE_TICK_SEL              2
    #define   MSK32CIC_S0_HS0_VCC_STABLE_TICK_SEL                 0x00003000
    #define        CIC_S0_HS0_VCC_STABLE_TICK_SEL_US                        0x1
    #define        CIC_S0_HS0_VCC_STABLE_TICK_SEL_MS                        0x2
    #define        CIC_S0_HS0_VCC_STABLE_TICK_SEL_SEC                       0x3

    #define     BA_CIC_S0_HS0_VCC_STABLE_TICK_CNT              0x00C9
    #define     B16CIC_S0_HS0_VCC_STABLE_TICK_CNT              0x00C8
    #define   LSb32CIC_S0_HS0_VCC_STABLE_TICK_CNT                 14
    #define   LSb16CIC_S0_HS0_VCC_STABLE_TICK_CNT                 14
    #define       bCIC_S0_HS0_VCC_STABLE_TICK_CNT              10
    #define   MSK32CIC_S0_HS0_VCC_STABLE_TICK_CNT                 0x00FFC000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_HS0                                  0x00CC

    #define     BA_CIC_S1_HS0_VS1_MON_TICK_SEL                 0x00CC
    #define     B16CIC_S1_HS0_VS1_MON_TICK_SEL                 0x00CC
    #define   LSb32CIC_S1_HS0_VS1_MON_TICK_SEL                    0
    #define   LSb16CIC_S1_HS0_VS1_MON_TICK_SEL                    0
    #define       bCIC_S1_HS0_VS1_MON_TICK_SEL                 2
    #define   MSK32CIC_S1_HS0_VS1_MON_TICK_SEL                    0x00000003
    #define        CIC_S1_HS0_VS1_MON_TICK_SEL_US                           0x1
    #define        CIC_S1_HS0_VS1_MON_TICK_SEL_MS                           0x2
    #define        CIC_S1_HS0_VS1_MON_TICK_SEL_SEC                          0x3

    #define     BA_CIC_S1_HS0_VS1_MON_TICK_CNT                 0x00CC
    #define     B16CIC_S1_HS0_VS1_MON_TICK_CNT                 0x00CC
    #define   LSb32CIC_S1_HS0_VS1_MON_TICK_CNT                    2
    #define   LSb16CIC_S1_HS0_VS1_MON_TICK_CNT                    2
    #define       bCIC_S1_HS0_VS1_MON_TICK_CNT                 10
    #define   MSK32CIC_S1_HS0_VS1_MON_TICK_CNT                    0x00000FFC

    #define     BA_CIC_S1_HS0_VCC_STABLE_TICK_SEL              0x00CD
    #define     B16CIC_S1_HS0_VCC_STABLE_TICK_SEL              0x00CC
    #define   LSb32CIC_S1_HS0_VCC_STABLE_TICK_SEL                 12
    #define   LSb16CIC_S1_HS0_VCC_STABLE_TICK_SEL                 12
    #define       bCIC_S1_HS0_VCC_STABLE_TICK_SEL              2
    #define   MSK32CIC_S1_HS0_VCC_STABLE_TICK_SEL                 0x00003000
    #define        CIC_S1_HS0_VCC_STABLE_TICK_SEL_US                        0x1
    #define        CIC_S1_HS0_VCC_STABLE_TICK_SEL_MS                        0x2
    #define        CIC_S1_HS0_VCC_STABLE_TICK_SEL_SEC                       0x3

    #define     BA_CIC_S1_HS0_VCC_STABLE_TICK_CNT              0x00CD
    #define     B16CIC_S1_HS0_VCC_STABLE_TICK_CNT              0x00CC
    #define   LSb32CIC_S1_HS0_VCC_STABLE_TICK_CNT                 14
    #define   LSb16CIC_S1_HS0_VCC_STABLE_TICK_CNT                 14
    #define       bCIC_S1_HS0_VCC_STABLE_TICK_CNT              10
    #define   MSK32CIC_S1_HS0_VCC_STABLE_TICK_CNT                 0x00FFC000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_HS1                                  0x00D0

    #define     BA_CIC_S0_HS1_RST_HIGH_TICK_SEL                0x00D0
    #define     B16CIC_S0_HS1_RST_HIGH_TICK_SEL                0x00D0
    #define   LSb32CIC_S0_HS1_RST_HIGH_TICK_SEL                   0
    #define   LSb16CIC_S0_HS1_RST_HIGH_TICK_SEL                   0
    #define       bCIC_S0_HS1_RST_HIGH_TICK_SEL                2
    #define   MSK32CIC_S0_HS1_RST_HIGH_TICK_SEL                   0x00000003
    #define        CIC_S0_HS1_RST_HIGH_TICK_SEL_US                          0x1
    #define        CIC_S0_HS1_RST_HIGH_TICK_SEL_MS                          0x2
    #define        CIC_S0_HS1_RST_HIGH_TICK_SEL_SEC                         0x3

    #define     BA_CIC_S0_HS1_RST_HIGH_TICK_CNT                0x00D0
    #define     B16CIC_S0_HS1_RST_HIGH_TICK_CNT                0x00D0
    #define   LSb32CIC_S0_HS1_RST_HIGH_TICK_CNT                   2
    #define   LSb16CIC_S0_HS1_RST_HIGH_TICK_CNT                   2
    #define       bCIC_S0_HS1_RST_HIGH_TICK_CNT                10
    #define   MSK32CIC_S0_HS1_RST_HIGH_TICK_CNT                   0x00000FFC

    #define     BA_CIC_S0_HS1_WAIT_READY_TICK_SEL              0x00D1
    #define     B16CIC_S0_HS1_WAIT_READY_TICK_SEL              0x00D0
    #define   LSb32CIC_S0_HS1_WAIT_READY_TICK_SEL                 12
    #define   LSb16CIC_S0_HS1_WAIT_READY_TICK_SEL                 12
    #define       bCIC_S0_HS1_WAIT_READY_TICK_SEL              2
    #define   MSK32CIC_S0_HS1_WAIT_READY_TICK_SEL                 0x00003000
    #define        CIC_S0_HS1_WAIT_READY_TICK_SEL_US                        0x1
    #define        CIC_S0_HS1_WAIT_READY_TICK_SEL_MS                        0x2
    #define        CIC_S0_HS1_WAIT_READY_TICK_SEL_SEC                       0x3

    #define     BA_CIC_S0_HS1_WAIT_READY_TICK_CNT              0x00D1
    #define     B16CIC_S0_HS1_WAIT_READY_TICK_CNT              0x00D0
    #define   LSb32CIC_S0_HS1_WAIT_READY_TICK_CNT                 14
    #define   LSb16CIC_S0_HS1_WAIT_READY_TICK_CNT                 14
    #define       bCIC_S0_HS1_WAIT_READY_TICK_CNT              10
    #define   MSK32CIC_S0_HS1_WAIT_READY_TICK_CNT                 0x00FFC000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_HS1                                  0x00D4

    #define     BA_CIC_S1_HS1_RST_HIGH_TICK_SEL                0x00D4
    #define     B16CIC_S1_HS1_RST_HIGH_TICK_SEL                0x00D4
    #define   LSb32CIC_S1_HS1_RST_HIGH_TICK_SEL                   0
    #define   LSb16CIC_S1_HS1_RST_HIGH_TICK_SEL                   0
    #define       bCIC_S1_HS1_RST_HIGH_TICK_SEL                2
    #define   MSK32CIC_S1_HS1_RST_HIGH_TICK_SEL                   0x00000003
    #define        CIC_S1_HS1_RST_HIGH_TICK_SEL_US                          0x1
    #define        CIC_S1_HS1_RST_HIGH_TICK_SEL_MS                          0x2
    #define        CIC_S1_HS1_RST_HIGH_TICK_SEL_SEC                         0x3

    #define     BA_CIC_S1_HS1_RST_HIGH_TICK_CNT                0x00D4
    #define     B16CIC_S1_HS1_RST_HIGH_TICK_CNT                0x00D4
    #define   LSb32CIC_S1_HS1_RST_HIGH_TICK_CNT                   2
    #define   LSb16CIC_S1_HS1_RST_HIGH_TICK_CNT                   2
    #define       bCIC_S1_HS1_RST_HIGH_TICK_CNT                10
    #define   MSK32CIC_S1_HS1_RST_HIGH_TICK_CNT                   0x00000FFC

    #define     BA_CIC_S1_HS1_WAIT_READY_TICK_SEL              0x00D5
    #define     B16CIC_S1_HS1_WAIT_READY_TICK_SEL              0x00D4
    #define   LSb32CIC_S1_HS1_WAIT_READY_TICK_SEL                 12
    #define   LSb16CIC_S1_HS1_WAIT_READY_TICK_SEL                 12
    #define       bCIC_S1_HS1_WAIT_READY_TICK_SEL              2
    #define   MSK32CIC_S1_HS1_WAIT_READY_TICK_SEL                 0x00003000
    #define        CIC_S1_HS1_WAIT_READY_TICK_SEL_US                        0x1
    #define        CIC_S1_HS1_WAIT_READY_TICK_SEL_MS                        0x2
    #define        CIC_S1_HS1_WAIT_READY_TICK_SEL_SEC                       0x3

    #define     BA_CIC_S1_HS1_WAIT_READY_TICK_CNT              0x00D5
    #define     B16CIC_S1_HS1_WAIT_READY_TICK_CNT              0x00D4
    #define   LSb32CIC_S1_HS1_WAIT_READY_TICK_CNT                 14
    #define   LSb16CIC_S1_HS1_WAIT_READY_TICK_CNT                 14
    #define       bCIC_S1_HS1_WAIT_READY_TICK_CNT              10
    #define   MSK32CIC_S1_HS1_WAIT_READY_TICK_CNT                 0x00FFC000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S0_HS2                                  0x00D8

    #define     BA_CIC_S0_HS2_CE_HIGH_TICK_SEL                 0x00D8
    #define     B16CIC_S0_HS2_CE_HIGH_TICK_SEL                 0x00D8
    #define   LSb32CIC_S0_HS2_CE_HIGH_TICK_SEL                    0
    #define   LSb16CIC_S0_HS2_CE_HIGH_TICK_SEL                    0
    #define       bCIC_S0_HS2_CE_HIGH_TICK_SEL                 2
    #define   MSK32CIC_S0_HS2_CE_HIGH_TICK_SEL                    0x00000003
    #define        CIC_S0_HS2_CE_HIGH_TICK_SEL_US                           0x1
    #define        CIC_S0_HS2_CE_HIGH_TICK_SEL_MS                           0x2
    #define        CIC_S0_HS2_CE_HIGH_TICK_SEL_SEC                          0x3

    #define     BA_CIC_S0_HS2_CE_HIGH_TICK_CNT                 0x00D8
    #define     B16CIC_S0_HS2_CE_HIGH_TICK_CNT                 0x00D8
    #define   LSb32CIC_S0_HS2_CE_HIGH_TICK_CNT                    2
    #define   LSb16CIC_S0_HS2_CE_HIGH_TICK_CNT                    2
    #define       bCIC_S0_HS2_CE_HIGH_TICK_CNT                 10
    #define   MSK32CIC_S0_HS2_CE_HIGH_TICK_CNT                    0x00000FFC

    #define     BA_CIC_S0_HS2_RST_Z_TICK_SEL                   0x00D9
    #define     B16CIC_S0_HS2_RST_Z_TICK_SEL                   0x00D8
    #define   LSb32CIC_S0_HS2_RST_Z_TICK_SEL                      12
    #define   LSb16CIC_S0_HS2_RST_Z_TICK_SEL                      12
    #define       bCIC_S0_HS2_RST_Z_TICK_SEL                   2
    #define   MSK32CIC_S0_HS2_RST_Z_TICK_SEL                      0x00003000
    #define        CIC_S0_HS2_RST_Z_TICK_SEL_US                             0x1
    #define        CIC_S0_HS2_RST_Z_TICK_SEL_MS                             0x2
    #define        CIC_S0_HS2_RST_Z_TICK_SEL_SEC                            0x3

    #define     BA_CIC_S0_HS2_RST_Z_TICK_CNT                   0x00D9
    #define     B16CIC_S0_HS2_RST_Z_TICK_CNT                   0x00D8
    #define   LSb32CIC_S0_HS2_RST_Z_TICK_CNT                      14
    #define   LSb16CIC_S0_HS2_RST_Z_TICK_CNT                      14
    #define       bCIC_S0_HS2_RST_Z_TICK_CNT                   10
    #define   MSK32CIC_S0_HS2_RST_Z_TICK_CNT                      0x00FFC000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_S1_HS2                                  0x00DC

    #define     BA_CIC_S1_HS2_CE_HIGH_TICK_SEL                 0x00DC
    #define     B16CIC_S1_HS2_CE_HIGH_TICK_SEL                 0x00DC
    #define   LSb32CIC_S1_HS2_CE_HIGH_TICK_SEL                    0
    #define   LSb16CIC_S1_HS2_CE_HIGH_TICK_SEL                    0
    #define       bCIC_S1_HS2_CE_HIGH_TICK_SEL                 2
    #define   MSK32CIC_S1_HS2_CE_HIGH_TICK_SEL                    0x00000003
    #define        CIC_S1_HS2_CE_HIGH_TICK_SEL_US                           0x1
    #define        CIC_S1_HS2_CE_HIGH_TICK_SEL_MS                           0x2
    #define        CIC_S1_HS2_CE_HIGH_TICK_SEL_SEC                          0x3

    #define     BA_CIC_S1_HS2_CE_HIGH_TICK_CNT                 0x00DC
    #define     B16CIC_S1_HS2_CE_HIGH_TICK_CNT                 0x00DC
    #define   LSb32CIC_S1_HS2_CE_HIGH_TICK_CNT                    2
    #define   LSb16CIC_S1_HS2_CE_HIGH_TICK_CNT                    2
    #define       bCIC_S1_HS2_CE_HIGH_TICK_CNT                 10
    #define   MSK32CIC_S1_HS2_CE_HIGH_TICK_CNT                    0x00000FFC

    #define     BA_CIC_S1_HS2_RST_Z_TICK_SEL                   0x00DD
    #define     B16CIC_S1_HS2_RST_Z_TICK_SEL                   0x00DC
    #define   LSb32CIC_S1_HS2_RST_Z_TICK_SEL                      12
    #define   LSb16CIC_S1_HS2_RST_Z_TICK_SEL                      12
    #define       bCIC_S1_HS2_RST_Z_TICK_SEL                   2
    #define   MSK32CIC_S1_HS2_RST_Z_TICK_SEL                      0x00003000
    #define        CIC_S1_HS2_RST_Z_TICK_SEL_US                             0x1
    #define        CIC_S1_HS2_RST_Z_TICK_SEL_MS                             0x2
    #define        CIC_S1_HS2_RST_Z_TICK_SEL_SEC                            0x3

    #define     BA_CIC_S1_HS2_RST_Z_TICK_CNT                   0x00DD
    #define     B16CIC_S1_HS2_RST_Z_TICK_CNT                   0x00DC
    #define   LSb32CIC_S1_HS2_RST_Z_TICK_CNT                      14
    #define   LSb16CIC_S1_HS2_RST_Z_TICK_CNT                      14
    #define       bCIC_S1_HS2_RST_Z_TICK_CNT                   10
    #define   MSK32CIC_S1_HS2_RST_Z_TICK_CNT                      0x00FFC000
    ///////////////////////////////////////////////////////////
    #define     RA_CIC_CLK                                     0x00E0

    #define     BA_CIC_CLK_CLKSWITCH                           0x00E0
    #define     B16CIC_CLK_CLKSWITCH                           0x00E0
    #define   LSb32CIC_CLK_CLKSWITCH                              0
    #define   LSb16CIC_CLK_CLKSWITCH                              0
    #define       bCIC_CLK_CLKSWITCH                           1
    #define   MSK32CIC_CLK_CLKSWITCH                              0x00000001
    #define        CIC_CLK_CLKSWITCH_SRCCLK                                 0x0
    #define        CIC_CLK_CLKSWITCH_DIVCLK                                 0x1

    #define     BA_CIC_CLK_CLKD3SWITCH                         0x00E0
    #define     B16CIC_CLK_CLKD3SWITCH                         0x00E0
    #define   LSb32CIC_CLK_CLKD3SWITCH                            1
    #define   LSb16CIC_CLK_CLKD3SWITCH                            1
    #define       bCIC_CLK_CLKD3SWITCH                         1
    #define   MSK32CIC_CLK_CLKD3SWITCH                            0x00000002
    #define        CIC_CLK_CLKD3SWITCH_NONDIV3CLK                           0x0
    #define        CIC_CLK_CLKD3SWITCH_DIV3CLK                              0x1

    #define     BA_CIC_CLK_CLKEN                               0x00E0
    #define     B16CIC_CLK_CLKEN                               0x00E0
    #define   LSb32CIC_CLK_CLKEN                                  2
    #define   LSb16CIC_CLK_CLKEN                                  2
    #define       bCIC_CLK_CLKEN                               1
    #define   MSK32CIC_CLK_CLKEN                                  0x00000004
    #define        CIC_CLK_CLKEN_DISABLE                                    0x0
    #define        CIC_CLK_CLKEN_ENABLE                                     0x1

    #define     BA_CIC_CLK_CLKSEL                              0x00E0
    #define     B16CIC_CLK_CLKSEL                              0x00E0
    #define   LSb32CIC_CLK_CLKSEL                                 3
    #define   LSb16CIC_CLK_CLKSEL                                 3
    #define       bCIC_CLK_CLKSEL                              3
    #define   MSK32CIC_CLK_CLKSEL                                 0x00000038
    #define        CIC_CLK_CLKSEL_D2                                        0x1
    #define        CIC_CLK_CLKSEL_D4                                        0x2
    #define        CIC_CLK_CLKSEL_D6                                        0x3
    #define        CIC_CLK_CLKSEL_D8                                        0x4
    #define        CIC_CLK_CLKSEL_D12                                       0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CIC {
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_CTRL_HOST_TYPE(r32)                     _BFGET_(r32, 1, 0)
    #define   SET32CIC_CTRL_HOST_TYPE(r32,v)                   _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_CTRL_HOST_TYPE(r16)                     _BFGET_(r16, 1, 0)
    #define   SET16CIC_CTRL_HOST_TYPE(r16,v)                   _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_CTRL_RESET(r32)                         _BFGET_(r32, 2, 2)
    #define   SET32CIC_CTRL_RESET(r32,v)                       _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_CTRL_RESET(r16)                         _BFGET_(r16, 2, 2)
    #define   SET16CIC_CTRL_RESET(r16,v)                       _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_CTRL_S0_CARD_EN(r32)                    _BFGET_(r32, 3, 3)
    #define   SET32CIC_CTRL_S0_CARD_EN(r32,v)                  _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_CTRL_S0_CARD_EN(r16)                    _BFGET_(r16, 3, 3)
    #define   SET16CIC_CTRL_S0_CARD_EN(r16,v)                  _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_CTRL_S1_CARD_EN(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32CIC_CTRL_S1_CARD_EN(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_CTRL_S1_CARD_EN(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16CIC_CTRL_S1_CARD_EN(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_CTRL_S0_HOT_SWAP_EN(r32)                _BFGET_(r32, 5, 5)
    #define   SET32CIC_CTRL_S0_HOT_SWAP_EN(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_CTRL_S0_HOT_SWAP_EN(r16)                _BFGET_(r16, 5, 5)
    #define   SET16CIC_CTRL_S0_HOT_SWAP_EN(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_CTRL_S1_HOT_SWAP_EN(r32)                _BFGET_(r32, 6, 6)
    #define   SET32CIC_CTRL_S1_HOT_SWAP_EN(r32,v)              _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_CTRL_S1_HOT_SWAP_EN(r16)                _BFGET_(r16, 6, 6)
    #define   SET16CIC_CTRL_S1_HOT_SWAP_EN(r16,v)              _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_CTRL_S0_OVERLOAD_EN(r32)                _BFGET_(r32, 7, 7)
    #define   SET32CIC_CTRL_S0_OVERLOAD_EN(r32,v)              _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_CTRL_S0_OVERLOAD_EN(r16)                _BFGET_(r16, 7, 7)
    #define   SET16CIC_CTRL_S0_OVERLOAD_EN(r16,v)              _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_CTRL_S1_OVERLOAD_EN(r32)                _BFGET_(r32, 8, 8)
    #define   SET32CIC_CTRL_S1_OVERLOAD_EN(r32,v)              _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_CTRL_S1_OVERLOAD_EN(r16)                _BFGET_(r16, 8, 8)
    #define   SET16CIC_CTRL_S1_OVERLOAD_EN(r16,v)              _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_CTRL_S0_CD_SINGLE_EN(r32)               _BFGET_(r32, 9, 9)
    #define   SET32CIC_CTRL_S0_CD_SINGLE_EN(r32,v)             _BFSET_(r32, 9, 9,v)
    #define   GET16CIC_CTRL_S0_CD_SINGLE_EN(r16)               _BFGET_(r16, 9, 9)
    #define   SET16CIC_CTRL_S0_CD_SINGLE_EN(r16,v)             _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_CTRL_S1_CD_SINGLE_EN(r32)               _BFGET_(r32,10,10)
    #define   SET32CIC_CTRL_S1_CD_SINGLE_EN(r32,v)             _BFSET_(r32,10,10,v)
    #define   GET16CIC_CTRL_S1_CD_SINGLE_EN(r16)               _BFGET_(r16,10,10)
    #define   SET16CIC_CTRL_S1_CD_SINGLE_EN(r16,v)             _BFSET_(r16,10,10,v)

    #define   GET32CIC_CTRL_CAM_PHY_RESET(r32)                 _BFGET_(r32,11,11)
    #define   SET32CIC_CTRL_CAM_PHY_RESET(r32,v)               _BFSET_(r32,11,11,v)
    #define   GET16CIC_CTRL_CAM_PHY_RESET(r16)                 _BFGET_(r16,11,11)
    #define   SET16CIC_CTRL_CAM_PHY_RESET(r16,v)               _BFSET_(r16,11,11,v)

    #define   GET32CIC_CTRL_S0_CE1(r32)                        _BFGET_(r32,12,12)
    #define   SET32CIC_CTRL_S0_CE1(r32,v)                      _BFSET_(r32,12,12,v)
    #define   GET16CIC_CTRL_S0_CE1(r16)                        _BFGET_(r16,12,12)
    #define   SET16CIC_CTRL_S0_CE1(r16,v)                      _BFSET_(r16,12,12,v)

    #define   GET32CIC_CTRL_S1_CE1(r32)                        _BFGET_(r32,13,13)
    #define   SET32CIC_CTRL_S1_CE1(r32,v)                      _BFSET_(r32,13,13,v)
    #define   GET16CIC_CTRL_S1_CE1(r16)                        _BFGET_(r16,13,13)
    #define   SET16CIC_CTRL_S1_CE1(r16,v)                      _BFSET_(r16,13,13,v)

    #define   GET32CIC_CTRL_M_HOST_IQB_ER(r32)                 _BFGET_(r32,14,14)
    #define   SET32CIC_CTRL_M_HOST_IQB_ER(r32,v)               _BFSET_(r32,14,14,v)
    #define   GET16CIC_CTRL_M_HOST_IQB_ER(r16)                 _BFGET_(r16,14,14)
    #define   SET16CIC_CTRL_M_HOST_IQB_ER(r16,v)               _BFSET_(r16,14,14,v)

    #define   GET32CIC_CTRL_S_MODE_MX_EN(r32)                  _BFGET_(r32,15,15)
    #define   SET32CIC_CTRL_S_MODE_MX_EN(r32,v)                _BFSET_(r32,15,15,v)
    #define   GET16CIC_CTRL_S_MODE_MX_EN(r16)                  _BFGET_(r16,15,15)
    #define   SET16CIC_CTRL_S_MODE_MX_EN(r16,v)                _BFSET_(r16,15,15,v)

    #define   GET32CIC_CTRL_M_MODE_MX_EN(r32)                  _BFGET_(r32,16,16)
    #define   SET32CIC_CTRL_M_MODE_MX_EN(r32,v)                _BFSET_(r32,16,16,v)
    #define   GET16CIC_CTRL_M_MODE_MX_EN(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16CIC_CTRL_M_MODE_MX_EN(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_CTRL_S0_VPP1SW(r32)                     _BFGET_(r32,17,17)
    #define   SET32CIC_CTRL_S0_VPP1SW(r32,v)                   _BFSET_(r32,17,17,v)
    #define   GET16CIC_CTRL_S0_VPP1SW(r16)                     _BFGET_(r16, 1, 1)
    #define   SET16CIC_CTRL_S0_VPP1SW(r16,v)                   _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_CTRL_S0_VPP1SEL(r32)                    _BFGET_(r32,18,18)
    #define   SET32CIC_CTRL_S0_VPP1SEL(r32,v)                  _BFSET_(r32,18,18,v)
    #define   GET16CIC_CTRL_S0_VPP1SEL(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16CIC_CTRL_S0_VPP1SEL(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_CTRL_S0_VPP2SW(r32)                     _BFGET_(r32,19,19)
    #define   SET32CIC_CTRL_S0_VPP2SW(r32,v)                   _BFSET_(r32,19,19,v)
    #define   GET16CIC_CTRL_S0_VPP2SW(r16)                     _BFGET_(r16, 3, 3)
    #define   SET16CIC_CTRL_S0_VPP2SW(r16,v)                   _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_CTRL_S0_VPP2SEL(r32)                    _BFGET_(r32,20,20)
    #define   SET32CIC_CTRL_S0_VPP2SEL(r32,v)                  _BFSET_(r32,20,20,v)
    #define   GET16CIC_CTRL_S0_VPP2SEL(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16CIC_CTRL_S0_VPP2SEL(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_CTRL_S0_VS2(r32)                        _BFGET_(r32,21,21)
    #define   SET32CIC_CTRL_S0_VS2(r32,v)                      _BFSET_(r32,21,21,v)
    #define   GET16CIC_CTRL_S0_VS2(r16)                        _BFGET_(r16, 5, 5)
    #define   SET16CIC_CTRL_S0_VS2(r16,v)                      _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_CTRL_S0_VCCSW(r32)                      _BFGET_(r32,22,22)
    #define   SET32CIC_CTRL_S0_VCCSW(r32,v)                    _BFSET_(r32,22,22,v)
    #define   GET16CIC_CTRL_S0_VCCSW(r16)                      _BFGET_(r16, 6, 6)
    #define   SET16CIC_CTRL_S0_VCCSW(r16,v)                    _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_CTRL_S1_VCCSW(r32)                      _BFGET_(r32,23,23)
    #define   SET32CIC_CTRL_S1_VCCSW(r32,v)                    _BFSET_(r32,23,23,v)
    #define   GET16CIC_CTRL_S1_VCCSW(r16)                      _BFGET_(r16, 7, 7)
    #define   SET16CIC_CTRL_S1_VCCSW(r16,v)                    _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_CTRL_S0_CARD_RST(r32)                   _BFGET_(r32,24,24)
    #define   SET32CIC_CTRL_S0_CARD_RST(r32,v)                 _BFSET_(r32,24,24,v)
    #define   GET16CIC_CTRL_S0_CARD_RST(r16)                   _BFGET_(r16, 8, 8)
    #define   SET16CIC_CTRL_S0_CARD_RST(r16,v)                 _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_CTRL_S1_CARD_RST(r32)                   _BFGET_(r32,25,25)
    #define   SET32CIC_CTRL_S1_CARD_RST(r32,v)                 _BFSET_(r32,25,25,v)
    #define   GET16CIC_CTRL_S1_CARD_RST(r16)                   _BFGET_(r16, 9, 9)
    #define   SET16CIC_CTRL_S1_CARD_RST(r16,v)                 _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_CTRL_S0_VCC_SUPPORTED(r32)              _BFGET_(r32,27,26)
    #define   SET32CIC_CTRL_S0_VCC_SUPPORTED(r32,v)            _BFSET_(r32,27,26,v)
    #define   GET16CIC_CTRL_S0_VCC_SUPPORTED(r16)              _BFGET_(r16,11,10)
    #define   SET16CIC_CTRL_S0_VCC_SUPPORTED(r16,v)            _BFSET_(r16,11,10,v)

    #define   GET32CIC_CTRL_S1_VCC_SUPPORTED(r32)              _BFGET_(r32,29,28)
    #define   SET32CIC_CTRL_S1_VCC_SUPPORTED(r32,v)            _BFSET_(r32,29,28,v)
    #define   GET16CIC_CTRL_S1_VCC_SUPPORTED(r16)              _BFGET_(r16,13,12)
    #define   SET16CIC_CTRL_S1_VCC_SUPPORTED(r16,v)            _BFSET_(r16,13,12,v)

    #define   GET32CIC_CTRL_S0_VCC_SEL(r32)                    _BFGET_(r32,30,30)
    #define   SET32CIC_CTRL_S0_VCC_SEL(r32,v)                  _BFSET_(r32,30,30,v)
    #define   GET16CIC_CTRL_S0_VCC_SEL(r16)                    _BFGET_(r16,14,14)
    #define   SET16CIC_CTRL_S0_VCC_SEL(r16,v)                  _BFSET_(r16,14,14,v)

    #define   GET32CIC_CTRL_S1_VCC_SEL(r32)                    _BFGET_(r32,31,31)
    #define   SET32CIC_CTRL_S1_VCC_SEL(r32,v)                  _BFSET_(r32,31,31,v)
    #define   GET16CIC_CTRL_S1_VCC_SEL(r16)                    _BFGET_(r16,15,15)
    #define   SET16CIC_CTRL_S1_VCC_SEL(r16,v)                  _BFSET_(r16,15,15,v)

    #define     w32CIC_CTRL                                    {\
            UNSG32 uCTRL_HOST_TYPE                             :  2;\
            UNSG32 uCTRL_RESET                                 :  1;\
            UNSG32 uCTRL_S0_CARD_EN                            :  1;\
            UNSG32 uCTRL_S1_CARD_EN                            :  1;\
            UNSG32 uCTRL_S0_HOT_SWAP_EN                        :  1;\
            UNSG32 uCTRL_S1_HOT_SWAP_EN                        :  1;\
            UNSG32 uCTRL_S0_OVERLOAD_EN                        :  1;\
            UNSG32 uCTRL_S1_OVERLOAD_EN                        :  1;\
            UNSG32 uCTRL_S0_CD_SINGLE_EN                       :  1;\
            UNSG32 uCTRL_S1_CD_SINGLE_EN                       :  1;\
            UNSG32 uCTRL_CAM_PHY_RESET                         :  1;\
            UNSG32 uCTRL_S0_CE1                                :  1;\
            UNSG32 uCTRL_S1_CE1                                :  1;\
            UNSG32 uCTRL_M_HOST_IQB_ER                         :  1;\
            UNSG32 uCTRL_S_MODE_MX_EN                          :  1;\
            UNSG32 uCTRL_M_MODE_MX_EN                          :  1;\
            UNSG32 uCTRL_S0_VPP1SW                             :  1;\
            UNSG32 uCTRL_S0_VPP1SEL                            :  1;\
            UNSG32 uCTRL_S0_VPP2SW                             :  1;\
            UNSG32 uCTRL_S0_VPP2SEL                            :  1;\
            UNSG32 uCTRL_S0_VS2                                :  1;\
            UNSG32 uCTRL_S0_VCCSW                              :  1;\
            UNSG32 uCTRL_S1_VCCSW                              :  1;\
            UNSG32 uCTRL_S0_CARD_RST                           :  1;\
            UNSG32 uCTRL_S1_CARD_RST                           :  1;\
            UNSG32 uCTRL_S0_VCC_SUPPORTED                      :  2;\
            UNSG32 uCTRL_S1_VCC_SUPPORTED                      :  2;\
            UNSG32 uCTRL_S0_VCC_SEL                            :  1;\
            UNSG32 uCTRL_S1_VCC_SEL                            :  1;\
          }
    union { UNSG32 u32CIC_CTRL;
            struct w32CIC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_CMD_TYPE(r32)                           _BFGET_(r32, 2, 0)
    #define   SET32CIC_CMD_TYPE(r32,v)                         _BFSET_(r32, 2, 0,v)
    #define   GET16CIC_CMD_TYPE(r16)                           _BFGET_(r16, 2, 0)
    #define   SET16CIC_CMD_TYPE(r16,v)                         _BFSET_(r16, 2, 0,v)

    #define   GET32CIC_CMD_SLOT_CH(r32)                        _BFGET_(r32, 3, 3)
    #define   SET32CIC_CMD_SLOT_CH(r32,v)                      _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_CMD_SLOT_CH(r16)                        _BFGET_(r16, 3, 3)
    #define   SET16CIC_CMD_SLOT_CH(r16,v)                      _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_CMD_PCMCIA_ADDR_INCR(r32)               _BFGET_(r32, 4, 4)
    #define   SET32CIC_CMD_PCMCIA_ADDR_INCR(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_CMD_PCMCIA_ADDR_INCR(r16)               _BFGET_(r16, 4, 4)
    #define   SET16CIC_CMD_PCMCIA_ADDR_INCR(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_CMD_BUF_BYTE_PACK(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32CIC_CMD_BUF_BYTE_PACK(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_CMD_BUF_BYTE_PACK(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16CIC_CMD_BUF_BYTE_PACK(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_CMD_IOA(r32)                            _BFGET_(r32, 6, 6)
    #define   SET32CIC_CMD_IOA(r32,v)                          _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_CMD_IOA(r16)                            _BFGET_(r16, 6, 6)
    #define   SET16CIC_CMD_IOA(r16,v)                          _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_CMD_REGA(r32)                           _BFGET_(r32, 7, 7)
    #define   SET32CIC_CMD_REGA(r32,v)                         _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_CMD_REGA(r16)                           _BFGET_(r16, 7, 7)
    #define   SET16CIC_CMD_REGA(r16,v)                         _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_CMD_ADDR(r32)                           _BFGET_(r32,22, 8)
    #define   SET32CIC_CMD_ADDR(r32,v)                         _BFSET_(r32,22, 8,v)

    #define   GET32CIC_CMD_BYTE_WR_DATA(r32)                   _BFGET_(r32,30,23)
    #define   SET32CIC_CMD_BYTE_WR_DATA(r32,v)                 _BFSET_(r32,30,23,v)
    #define   GET16CIC_CMD_BYTE_WR_DATA(r16)                   _BFGET_(r16,14, 7)
    #define   SET16CIC_CMD_BYTE_WR_DATA(r16,v)                 _BFSET_(r16,14, 7,v)

    #define     w32CIC_CMD                                     {\
            UNSG32 uCMD_TYPE                                   :  3;\
            UNSG32 uCMD_SLOT_CH                                :  1;\
            UNSG32 uCMD_PCMCIA_ADDR_INCR                       :  1;\
            UNSG32 uCMD_BUF_BYTE_PACK                          :  1;\
            UNSG32 uCMD_IOA                                    :  1;\
            UNSG32 uCMD_REGA                                   :  1;\
            UNSG32 uCMD_ADDR                                   : 15;\
            UNSG32 uCMD_BYTE_WR_DATA                           :  8;\
            UNSG32 RSVDx4_b31                                  :  1;\
          }
    union { UNSG32 u32CIC_CMD;
            struct w32CIC_CMD;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_CTRL_OE0_S0_31_0(r32)                   _BFGET_(r32,31, 0)
    #define   SET32CIC_CTRL_OE0_S0_31_0(r32,v)                 _BFSET_(r32,31, 0,v)

    #define     w32CIC_CTRL_OE0                                {\
            UNSG32 uCTRL_OE0_S0_31_0                           : 32;\
          }
    union { UNSG32 u32CIC_CTRL_OE0;
            struct w32CIC_CTRL_OE0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_CTRL_OE1_S0_63_32(r32)                  _BFGET_(r32,31, 0)
    #define   SET32CIC_CTRL_OE1_S0_63_32(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32CIC_CTRL_OE1                                {\
            UNSG32 uCTRL_OE1_S0_63_32                          : 32;\
          }
    union { UNSG32 u32CIC_CTRL_OE1;
            struct w32CIC_CTRL_OE1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_CTRL_OE2_S0_68_64(r32)                  _BFGET_(r32, 4, 0)
    #define   SET32CIC_CTRL_OE2_S0_68_64(r32,v)                _BFSET_(r32, 4, 0,v)
    #define   GET16CIC_CTRL_OE2_S0_68_64(r16)                  _BFGET_(r16, 4, 0)
    #define   SET16CIC_CTRL_OE2_S0_68_64(r16,v)                _BFSET_(r16, 4, 0,v)

    #define   GET32CIC_CTRL_OE2_S1_07_CE1(r32)                 _BFGET_(r32, 5, 5)
    #define   SET32CIC_CTRL_OE2_S1_07_CE1(r32,v)               _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_CTRL_OE2_S1_07_CE1(r16)                 _BFGET_(r16, 5, 5)
    #define   SET16CIC_CTRL_OE2_S1_07_CE1(r16,v)               _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_CTRL_OE2_S1_42_CE2(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32CIC_CTRL_OE2_S1_42_CE2(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_CTRL_OE2_S1_42_CE2(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16CIC_CTRL_OE2_S1_42_CE2(r16,v)               _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_CTRL_OE2_S1_58_RESET(r32)               _BFGET_(r32, 7, 7)
    #define   SET32CIC_CTRL_OE2_S1_58_RESET(r32,v)             _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_CTRL_OE2_S1_58_RESET(r16)               _BFGET_(r16, 7, 7)
    #define   SET16CIC_CTRL_OE2_S1_58_RESET(r16,v)             _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_CTRL_OE2_S1_43_VS1(r32)                 _BFGET_(r32, 8, 8)
    #define   SET32CIC_CTRL_OE2_S1_43_VS1(r32,v)               _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_CTRL_OE2_S1_43_VS1(r16)                 _BFGET_(r16, 8, 8)
    #define   SET16CIC_CTRL_OE2_S1_43_VS1(r16,v)               _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_CTRL_OE2_S1_16_IREQ_N(r32)              _BFGET_(r32, 9, 9)
    #define   SET32CIC_CTRL_OE2_S1_16_IREQ_N(r32,v)            _BFSET_(r32, 9, 9,v)
    #define   GET16CIC_CTRL_OE2_S1_16_IREQ_N(r16)              _BFGET_(r16, 9, 9)
    #define   SET16CIC_CTRL_OE2_S1_16_IREQ_N(r16,v)            _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_CTRL_OE2_S1_36_CD1_N(r32)               _BFGET_(r32,10,10)
    #define   SET32CIC_CTRL_OE2_S1_36_CD1_N(r32,v)             _BFSET_(r32,10,10,v)
    #define   GET16CIC_CTRL_OE2_S1_36_CD1_N(r16)               _BFGET_(r16,10,10)
    #define   SET16CIC_CTRL_OE2_S1_36_CD1_N(r16,v)             _BFSET_(r16,10,10,v)

    #define   GET32CIC_CTRL_OE2_S1_67_CD2_N(r32)               _BFGET_(r32,11,11)
    #define   SET32CIC_CTRL_OE2_S1_67_CD2_N(r32,v)             _BFSET_(r32,11,11,v)
    #define   GET16CIC_CTRL_OE2_S1_67_CD2_N(r16)               _BFGET_(r16,11,11)
    #define   SET16CIC_CTRL_OE2_S1_67_CD2_N(r16,v)             _BFSET_(r16,11,11,v)

    #define   GET32CIC_CTRL_OE2_S1_60_INPACK_N(r32)            _BFGET_(r32,12,12)
    #define   SET32CIC_CTRL_OE2_S1_60_INPACK_N(r32,v)          _BFSET_(r32,12,12,v)
    #define   GET16CIC_CTRL_OE2_S1_60_INPACK_N(r16)            _BFGET_(r16,12,12)
    #define   SET16CIC_CTRL_OE2_S1_60_INPACK_N(r16,v)          _BFSET_(r16,12,12,v)

    #define   GET32CIC_CTRL_OE2_S1_59_WAIT_N(r32)              _BFGET_(r32,13,13)
    #define   SET32CIC_CTRL_OE2_S1_59_WAIT_N(r32,v)            _BFSET_(r32,13,13,v)
    #define   GET16CIC_CTRL_OE2_S1_59_WAIT_N(r16)              _BFGET_(r16,13,13)
    #define   SET16CIC_CTRL_OE2_S1_59_WAIT_N(r16,v)            _BFSET_(r16,13,13,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_VCC_SW(r32)              _BFGET_(r32,14,14)
    #define   SET32CIC_CTRL_OE2_VC_S0_VCC_SW(r32,v)            _BFSET_(r32,14,14,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_VCC_SW(r16)              _BFGET_(r16,14,14)
    #define   SET16CIC_CTRL_OE2_VC_S0_VCC_SW(r16,v)            _BFSET_(r16,14,14,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_VCC_SEL(r32)             _BFGET_(r32,15,15)
    #define   SET32CIC_CTRL_OE2_VC_S0_VCC_SEL(r32,v)           _BFSET_(r32,15,15,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_VCC_SEL(r16)             _BFGET_(r16,15,15)
    #define   SET16CIC_CTRL_OE2_VC_S0_VCC_SEL(r16,v)           _BFSET_(r16,15,15,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_VPP1_SW(r32)             _BFGET_(r32,16,16)
    #define   SET32CIC_CTRL_OE2_VC_S0_VPP1_SW(r32,v)           _BFSET_(r32,16,16,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_VPP1_SW(r16)             _BFGET_(r16, 0, 0)
    #define   SET16CIC_CTRL_OE2_VC_S0_VPP1_SW(r16,v)           _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_VPP1_SEL(r32)            _BFGET_(r32,17,17)
    #define   SET32CIC_CTRL_OE2_VC_S0_VPP1_SEL(r32,v)          _BFSET_(r32,17,17,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_VPP1_SEL(r16)            _BFGET_(r16, 1, 1)
    #define   SET16CIC_CTRL_OE2_VC_S0_VPP1_SEL(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_VPP2_SW(r32)             _BFGET_(r32,18,18)
    #define   SET32CIC_CTRL_OE2_VC_S0_VPP2_SW(r32,v)           _BFSET_(r32,18,18,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_VPP2_SW(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CIC_CTRL_OE2_VC_S0_VPP2_SW(r16,v)           _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_VPP2_SEL(r32)            _BFGET_(r32,19,19)
    #define   SET32CIC_CTRL_OE2_VC_S0_VPP2_SEL(r32,v)          _BFSET_(r32,19,19,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_VPP2_SEL(r16)            _BFGET_(r16, 3, 3)
    #define   SET16CIC_CTRL_OE2_VC_S0_VPP2_SEL(r16,v)          _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_CTRL_OE2_VC_S1_VCC_SW(r32)              _BFGET_(r32,20,20)
    #define   SET32CIC_CTRL_OE2_VC_S1_VCC_SW(r32,v)            _BFSET_(r32,20,20,v)
    #define   GET16CIC_CTRL_OE2_VC_S1_VCC_SW(r16)              _BFGET_(r16, 4, 4)
    #define   SET16CIC_CTRL_OE2_VC_S1_VCC_SW(r16,v)            _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_CTRL_OE2_VC_S1_VCC_SEL(r32)             _BFGET_(r32,21,21)
    #define   SET32CIC_CTRL_OE2_VC_S1_VCC_SEL(r32,v)           _BFSET_(r32,21,21,v)
    #define   GET16CIC_CTRL_OE2_VC_S1_VCC_SEL(r16)             _BFGET_(r16, 5, 5)
    #define   SET16CIC_CTRL_OE2_VC_S1_VCC_SEL(r16,v)           _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_CTRL_OE2_VC_S0_OVERLOAD(r32)            _BFGET_(r32,22,22)
    #define   SET32CIC_CTRL_OE2_VC_S0_OVERLOAD(r32,v)          _BFSET_(r32,22,22,v)
    #define   GET16CIC_CTRL_OE2_VC_S0_OVERLOAD(r16)            _BFGET_(r16, 6, 6)
    #define   SET16CIC_CTRL_OE2_VC_S0_OVERLOAD(r16,v)          _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_CTRL_OE2_VC_S1_OVERLOAD(r32)            _BFGET_(r32,23,23)
    #define   SET32CIC_CTRL_OE2_VC_S1_OVERLOAD(r32,v)          _BFSET_(r32,23,23,v)
    #define   GET16CIC_CTRL_OE2_VC_S1_OVERLOAD(r16)            _BFGET_(r16, 7, 7)
    #define   SET16CIC_CTRL_OE2_VC_S1_OVERLOAD(r16,v)          _BFSET_(r16, 7, 7,v)

    #define     w32CIC_CTRL_OE2                                {\
            UNSG32 uCTRL_OE2_S0_68_64                          :  5;\
            UNSG32 uCTRL_OE2_S1_07_CE1                         :  1;\
            UNSG32 uCTRL_OE2_S1_42_CE2                         :  1;\
            UNSG32 uCTRL_OE2_S1_58_RESET                       :  1;\
            UNSG32 uCTRL_OE2_S1_43_VS1                         :  1;\
            UNSG32 uCTRL_OE2_S1_16_IREQ_N                      :  1;\
            UNSG32 uCTRL_OE2_S1_36_CD1_N                       :  1;\
            UNSG32 uCTRL_OE2_S1_67_CD2_N                       :  1;\
            UNSG32 uCTRL_OE2_S1_60_INPACK_N                    :  1;\
            UNSG32 uCTRL_OE2_S1_59_WAIT_N                      :  1;\
            UNSG32 uCTRL_OE2_VC_S0_VCC_SW                      :  1;\
            UNSG32 uCTRL_OE2_VC_S0_VCC_SEL                     :  1;\
            UNSG32 uCTRL_OE2_VC_S0_VPP1_SW                     :  1;\
            UNSG32 uCTRL_OE2_VC_S0_VPP1_SEL                    :  1;\
            UNSG32 uCTRL_OE2_VC_S0_VPP2_SW                     :  1;\
            UNSG32 uCTRL_OE2_VC_S0_VPP2_SEL                    :  1;\
            UNSG32 uCTRL_OE2_VC_S1_VCC_SW                      :  1;\
            UNSG32 uCTRL_OE2_VC_S1_VCC_SEL                     :  1;\
            UNSG32 uCTRL_OE2_VC_S0_OVERLOAD                    :  1;\
            UNSG32 uCTRL_OE2_VC_S1_OVERLOAD                    :  1;\
            UNSG32 RSVDx10_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_CTRL_OE2;
            struct w32CIC_CTRL_OE2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_CAM_REG_OFFSET_VAL(r32)              _BFGET_(r32,14, 0)
    #define   SET32CIC_S1_CAM_REG_OFFSET_VAL(r32,v)            _BFSET_(r32,14, 0,v)
    #define   GET16CIC_S1_CAM_REG_OFFSET_VAL(r16)              _BFGET_(r16,14, 0)
    #define   SET16CIC_S1_CAM_REG_OFFSET_VAL(r16,v)            _BFSET_(r16,14, 0,v)

    #define     w32CIC_S1_CAM_REG_OFFSET                       {\
            UNSG32 uS1_CAM_REG_OFFSET_VAL                      : 15;\
            UNSG32 RSVDx14_b15                                 : 17;\
          }
    union { UNSG32 u32CIC_S1_CAM_REG_OFFSET;
            struct w32CIC_S1_CAM_REG_OFFSET;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_STATUS_DIRECT_READ_PEND(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CIC_STATUS_DIRECT_READ_PEND(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_STATUS_DIRECT_READ_PEND(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CIC_STATUS_DIRECT_READ_PEND(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_STATUS_DIRECT_WRITE_PEND(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CIC_STATUS_DIRECT_WRITE_PEND(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_STATUS_DIRECT_WRITE_PEND(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CIC_STATUS_DIRECT_WRITE_PEND(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_STATUS_SINGLE_READ_PEND(r32)            _BFGET_(r32, 2, 2)
    #define   SET32CIC_STATUS_SINGLE_READ_PEND(r32,v)          _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_STATUS_SINGLE_READ_PEND(r16)            _BFGET_(r16, 2, 2)
    #define   SET16CIC_STATUS_SINGLE_READ_PEND(r16,v)          _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_STATUS_SINGLE_WRITE_PEND(r32)           _BFGET_(r32, 3, 3)
    #define   SET32CIC_STATUS_SINGLE_WRITE_PEND(r32,v)         _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_STATUS_SINGLE_WRITE_PEND(r16)           _BFGET_(r16, 3, 3)
    #define   SET16CIC_STATUS_SINGLE_WRITE_PEND(r16,v)         _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_STATUS_BLOCK_READ_PEND(r32)             _BFGET_(r32, 4, 4)
    #define   SET32CIC_STATUS_BLOCK_READ_PEND(r32,v)           _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_STATUS_BLOCK_READ_PEND(r16)             _BFGET_(r16, 4, 4)
    #define   SET16CIC_STATUS_BLOCK_READ_PEND(r16,v)           _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_STATUS_BLOCK_WRITE_PEND(r32)            _BFGET_(r32, 5, 5)
    #define   SET32CIC_STATUS_BLOCK_WRITE_PEND(r32,v)          _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_STATUS_BLOCK_WRITE_PEND(r16)            _BFGET_(r16, 5, 5)
    #define   SET16CIC_STATUS_BLOCK_WRITE_PEND(r16,v)          _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_STATUS_CAM_START_PEND(r32)              _BFGET_(r32, 6, 6)
    #define   SET32CIC_STATUS_CAM_START_PEND(r32,v)            _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_STATUS_CAM_START_PEND(r16)              _BFGET_(r16, 6, 6)
    #define   SET16CIC_STATUS_CAM_START_PEND(r16,v)            _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_STATUS_CAM_STOP_PEND(r32)               _BFGET_(r32, 7, 7)
    #define   SET32CIC_STATUS_CAM_STOP_PEND(r32,v)             _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_STATUS_CAM_STOP_PEND(r16)               _BFGET_(r16, 7, 7)
    #define   SET16CIC_STATUS_CAM_STOP_PEND(r16,v)             _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_STATUS_RX_BUF0_BUSY(r32)                _BFGET_(r32, 8, 8)
    #define   SET32CIC_STATUS_RX_BUF0_BUSY(r32,v)              _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_STATUS_RX_BUF0_BUSY(r16)                _BFGET_(r16, 8, 8)
    #define   SET16CIC_STATUS_RX_BUF0_BUSY(r16,v)              _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_STATUS_RX_BUF1_BUSY(r32)                _BFGET_(r32, 9, 9)
    #define   SET32CIC_STATUS_RX_BUF1_BUSY(r32,v)              _BFSET_(r32, 9, 9,v)
    #define   GET16CIC_STATUS_RX_BUF1_BUSY(r16)                _BFGET_(r16, 9, 9)
    #define   SET16CIC_STATUS_RX_BUF1_BUSY(r16,v)              _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_STATUS_TX_BUF0_BUSY(r32)                _BFGET_(r32,10,10)
    #define   SET32CIC_STATUS_TX_BUF0_BUSY(r32,v)              _BFSET_(r32,10,10,v)
    #define   GET16CIC_STATUS_TX_BUF0_BUSY(r16)                _BFGET_(r16,10,10)
    #define   SET16CIC_STATUS_TX_BUF0_BUSY(r16,v)              _BFSET_(r16,10,10,v)

    #define   GET32CIC_STATUS_TX_BUF1_BUSY(r32)                _BFGET_(r32,11,11)
    #define   SET32CIC_STATUS_TX_BUF1_BUSY(r32,v)              _BFSET_(r32,11,11,v)
    #define   GET16CIC_STATUS_TX_BUF1_BUSY(r16)                _BFGET_(r16,11,11)
    #define   SET16CIC_STATUS_TX_BUF1_BUSY(r16,v)              _BFSET_(r16,11,11,v)

    #define     w32CIC_STATUS                                  {\
            UNSG32 uSTATUS_DIRECT_READ_PEND                    :  1;\
            UNSG32 uSTATUS_DIRECT_WRITE_PEND                   :  1;\
            UNSG32 uSTATUS_SINGLE_READ_PEND                    :  1;\
            UNSG32 uSTATUS_SINGLE_WRITE_PEND                   :  1;\
            UNSG32 uSTATUS_BLOCK_READ_PEND                     :  1;\
            UNSG32 uSTATUS_BLOCK_WRITE_PEND                    :  1;\
            UNSG32 uSTATUS_CAM_START_PEND                      :  1;\
            UNSG32 uSTATUS_CAM_STOP_PEND                       :  1;\
            UNSG32 uSTATUS_RX_BUF0_BUSY                        :  1;\
            UNSG32 uSTATUS_RX_BUF1_BUSY                        :  1;\
            UNSG32 uSTATUS_TX_BUF0_BUSY                        :  1;\
            UNSG32 uSTATUS_TX_BUF1_BUSY                        :  1;\
            UNSG32 RSVDx18_b12                                 : 20;\
          }
    union { UNSG32 u32CIC_STATUS;
            struct w32CIC_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_TX_BUF0_WIN_LOC(r32)                    _BFGET_(r32,31, 0)
    #define   SET32CIC_TX_BUF0_WIN_LOC(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32CIC_TX_BUF0_WIN                             {\
            UNSG32 uTX_BUF0_WIN_LOC                            : 32;\
          }
    union { UNSG32 u32CIC_TX_BUF0_WIN;
            struct w32CIC_TX_BUF0_WIN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_TX_BUF1_WIN_LOC(r32)                    _BFGET_(r32,31, 0)
    #define   SET32CIC_TX_BUF1_WIN_LOC(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32CIC_TX_BUF1_WIN                             {\
            UNSG32 uTX_BUF1_WIN_LOC                            : 32;\
          }
    union { UNSG32 u32CIC_TX_BUF1_WIN;
            struct w32CIC_TX_BUF1_WIN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_RX_BUF0_WIN_LOC(r32)                    _BFGET_(r32,31, 0)
    #define   SET32CIC_RX_BUF0_WIN_LOC(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32CIC_RX_BUF0_WIN                             {\
            UNSG32 uRX_BUF0_WIN_LOC                            : 32;\
          }
    union { UNSG32 u32CIC_RX_BUF0_WIN;
            struct w32CIC_RX_BUF0_WIN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_RX_BUF1_WIN_LOC(r32)                    _BFGET_(r32,31, 0)
    #define   SET32CIC_RX_BUF1_WIN_LOC(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32CIC_RX_BUF1_WIN                             {\
            UNSG32 uRX_BUF1_WIN_LOC                            : 32;\
          }
    union { UNSG32 u32CIC_RX_BUF1_WIN;
            struct w32CIC_RX_BUF1_WIN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_TX_BUF0_CFG_SIZE(r32)                   _BFGET_(r32,11, 0)
    #define   SET32CIC_TX_BUF0_CFG_SIZE(r32,v)                 _BFSET_(r32,11, 0,v)
    #define   GET16CIC_TX_BUF0_CFG_SIZE(r16)                   _BFGET_(r16,11, 0)
    #define   SET16CIC_TX_BUF0_CFG_SIZE(r16,v)                 _BFSET_(r16,11, 0,v)

    #define   GET32CIC_TX_BUF0_CFG_PKT_F(r32)                  _BFGET_(r32,12,12)
    #define   SET32CIC_TX_BUF0_CFG_PKT_F(r32,v)                _BFSET_(r32,12,12,v)
    #define   GET16CIC_TX_BUF0_CFG_PKT_F(r16)                  _BFGET_(r16,12,12)
    #define   SET16CIC_TX_BUF0_CFG_PKT_F(r16,v)                _BFSET_(r16,12,12,v)

    #define   GET32CIC_TX_BUF0_CFG_PKT_L(r32)                  _BFGET_(r32,13,13)
    #define   SET32CIC_TX_BUF0_CFG_PKT_L(r32,v)                _BFSET_(r32,13,13,v)
    #define   GET16CIC_TX_BUF0_CFG_PKT_L(r16)                  _BFGET_(r16,13,13)
    #define   SET16CIC_TX_BUF0_CFG_PKT_L(r16,v)                _BFSET_(r16,13,13,v)

    #define   GET32CIC_TX_BUF0_CFG_BYTE_SWAP_EN(r32)           _BFGET_(r32,14,14)
    #define   SET32CIC_TX_BUF0_CFG_BYTE_SWAP_EN(r32,v)         _BFSET_(r32,14,14,v)
    #define   GET16CIC_TX_BUF0_CFG_BYTE_SWAP_EN(r16)           _BFGET_(r16,14,14)
    #define   SET16CIC_TX_BUF0_CFG_BYTE_SWAP_EN(r16,v)         _BFSET_(r16,14,14,v)

    #define   GET32CIC_TX_BUF0_CFG_BIT_SWAP_EN(r32)            _BFGET_(r32,15,15)
    #define   SET32CIC_TX_BUF0_CFG_BIT_SWAP_EN(r32,v)          _BFSET_(r32,15,15,v)
    #define   GET16CIC_TX_BUF0_CFG_BIT_SWAP_EN(r16)            _BFGET_(r16,15,15)
    #define   SET16CIC_TX_BUF0_CFG_BIT_SWAP_EN(r16,v)          _BFSET_(r16,15,15,v)

    #define     w32CIC_TX_BUF0_CFG                             {\
            UNSG32 uTX_BUF0_CFG_SIZE                           : 12;\
            UNSG32 uTX_BUF0_CFG_PKT_F                          :  1;\
            UNSG32 uTX_BUF0_CFG_PKT_L                          :  1;\
            UNSG32 uTX_BUF0_CFG_BYTE_SWAP_EN                   :  1;\
            UNSG32 uTX_BUF0_CFG_BIT_SWAP_EN                    :  1;\
            UNSG32 RSVDx2C_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_TX_BUF0_CFG;
            struct w32CIC_TX_BUF0_CFG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_TX_BUF1_CFG_SIZE(r32)                   _BFGET_(r32,11, 0)
    #define   SET32CIC_TX_BUF1_CFG_SIZE(r32,v)                 _BFSET_(r32,11, 0,v)
    #define   GET16CIC_TX_BUF1_CFG_SIZE(r16)                   _BFGET_(r16,11, 0)
    #define   SET16CIC_TX_BUF1_CFG_SIZE(r16,v)                 _BFSET_(r16,11, 0,v)

    #define   GET32CIC_TX_BUF1_CFG_PKT_F(r32)                  _BFGET_(r32,12,12)
    #define   SET32CIC_TX_BUF1_CFG_PKT_F(r32,v)                _BFSET_(r32,12,12,v)
    #define   GET16CIC_TX_BUF1_CFG_PKT_F(r16)                  _BFGET_(r16,12,12)
    #define   SET16CIC_TX_BUF1_CFG_PKT_F(r16,v)                _BFSET_(r16,12,12,v)

    #define   GET32CIC_TX_BUF1_CFG_PKT_L(r32)                  _BFGET_(r32,13,13)
    #define   SET32CIC_TX_BUF1_CFG_PKT_L(r32,v)                _BFSET_(r32,13,13,v)
    #define   GET16CIC_TX_BUF1_CFG_PKT_L(r16)                  _BFGET_(r16,13,13)
    #define   SET16CIC_TX_BUF1_CFG_PKT_L(r16,v)                _BFSET_(r16,13,13,v)

    #define   GET32CIC_TX_BUF1_CFG_BYTE_SWAP_EN(r32)           _BFGET_(r32,14,14)
    #define   SET32CIC_TX_BUF1_CFG_BYTE_SWAP_EN(r32,v)         _BFSET_(r32,14,14,v)
    #define   GET16CIC_TX_BUF1_CFG_BYTE_SWAP_EN(r16)           _BFGET_(r16,14,14)
    #define   SET16CIC_TX_BUF1_CFG_BYTE_SWAP_EN(r16,v)         _BFSET_(r16,14,14,v)

    #define   GET32CIC_TX_BUF1_CFG_BIT_SWAP_EN(r32)            _BFGET_(r32,15,15)
    #define   SET32CIC_TX_BUF1_CFG_BIT_SWAP_EN(r32,v)          _BFSET_(r32,15,15,v)
    #define   GET16CIC_TX_BUF1_CFG_BIT_SWAP_EN(r16)            _BFGET_(r16,15,15)
    #define   SET16CIC_TX_BUF1_CFG_BIT_SWAP_EN(r16,v)          _BFSET_(r16,15,15,v)

    #define     w32CIC_TX_BUF1_CFG                             {\
            UNSG32 uTX_BUF1_CFG_SIZE                           : 12;\
            UNSG32 uTX_BUF1_CFG_PKT_F                          :  1;\
            UNSG32 uTX_BUF1_CFG_PKT_L                          :  1;\
            UNSG32 uTX_BUF1_CFG_BYTE_SWAP_EN                   :  1;\
            UNSG32 uTX_BUF1_CFG_BIT_SWAP_EN                    :  1;\
            UNSG32 RSVDx30_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_TX_BUF1_CFG;
            struct w32CIC_TX_BUF1_CFG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_RX_BUF0_CFG_SIZE(r32)                   _BFGET_(r32,11, 0)
    #define   SET32CIC_RX_BUF0_CFG_SIZE(r32,v)                 _BFSET_(r32,11, 0,v)
    #define   GET16CIC_RX_BUF0_CFG_SIZE(r16)                   _BFGET_(r16,11, 0)
    #define   SET16CIC_RX_BUF0_CFG_SIZE(r16,v)                 _BFSET_(r16,11, 0,v)

    #define   GET32CIC_RX_BUF0_CFG_PKT_F(r32)                  _BFGET_(r32,12,12)
    #define   SET32CIC_RX_BUF0_CFG_PKT_F(r32,v)                _BFSET_(r32,12,12,v)
    #define   GET16CIC_RX_BUF0_CFG_PKT_F(r16)                  _BFGET_(r16,12,12)
    #define   SET16CIC_RX_BUF0_CFG_PKT_F(r16,v)                _BFSET_(r16,12,12,v)

    #define   GET32CIC_RX_BUF0_CFG_PKT_L(r32)                  _BFGET_(r32,13,13)
    #define   SET32CIC_RX_BUF0_CFG_PKT_L(r32,v)                _BFSET_(r32,13,13,v)
    #define   GET16CIC_RX_BUF0_CFG_PKT_L(r16)                  _BFGET_(r16,13,13)
    #define   SET16CIC_RX_BUF0_CFG_PKT_L(r16,v)                _BFSET_(r16,13,13,v)

    #define   GET32CIC_RX_BUF0_CFG_BYTE_SWAP_EN(r32)           _BFGET_(r32,14,14)
    #define   SET32CIC_RX_BUF0_CFG_BYTE_SWAP_EN(r32,v)         _BFSET_(r32,14,14,v)
    #define   GET16CIC_RX_BUF0_CFG_BYTE_SWAP_EN(r16)           _BFGET_(r16,14,14)
    #define   SET16CIC_RX_BUF0_CFG_BYTE_SWAP_EN(r16,v)         _BFSET_(r16,14,14,v)

    #define   GET32CIC_RX_BUF0_CFG_BIT_SWAP_EN(r32)            _BFGET_(r32,15,15)
    #define   SET32CIC_RX_BUF0_CFG_BIT_SWAP_EN(r32,v)          _BFSET_(r32,15,15,v)
    #define   GET16CIC_RX_BUF0_CFG_BIT_SWAP_EN(r16)            _BFGET_(r16,15,15)
    #define   SET16CIC_RX_BUF0_CFG_BIT_SWAP_EN(r16,v)          _BFSET_(r16,15,15,v)

    #define     w32CIC_RX_BUF0_CFG                             {\
            UNSG32 uRX_BUF0_CFG_SIZE                           : 12;\
            UNSG32 uRX_BUF0_CFG_PKT_F                          :  1;\
            UNSG32 uRX_BUF0_CFG_PKT_L                          :  1;\
            UNSG32 uRX_BUF0_CFG_BYTE_SWAP_EN                   :  1;\
            UNSG32 uRX_BUF0_CFG_BIT_SWAP_EN                    :  1;\
            UNSG32 RSVDx34_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_RX_BUF0_CFG;
            struct w32CIC_RX_BUF0_CFG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_RX_BUF1_CFG_SIZE(r32)                   _BFGET_(r32,11, 0)
    #define   SET32CIC_RX_BUF1_CFG_SIZE(r32,v)                 _BFSET_(r32,11, 0,v)
    #define   GET16CIC_RX_BUF1_CFG_SIZE(r16)                   _BFGET_(r16,11, 0)
    #define   SET16CIC_RX_BUF1_CFG_SIZE(r16,v)                 _BFSET_(r16,11, 0,v)

    #define   GET32CIC_RX_BUF1_CFG_PKT_F(r32)                  _BFGET_(r32,12,12)
    #define   SET32CIC_RX_BUF1_CFG_PKT_F(r32,v)                _BFSET_(r32,12,12,v)
    #define   GET16CIC_RX_BUF1_CFG_PKT_F(r16)                  _BFGET_(r16,12,12)
    #define   SET16CIC_RX_BUF1_CFG_PKT_F(r16,v)                _BFSET_(r16,12,12,v)

    #define   GET32CIC_RX_BUF1_CFG_PKT_L(r32)                  _BFGET_(r32,13,13)
    #define   SET32CIC_RX_BUF1_CFG_PKT_L(r32,v)                _BFSET_(r32,13,13,v)
    #define   GET16CIC_RX_BUF1_CFG_PKT_L(r16)                  _BFGET_(r16,13,13)
    #define   SET16CIC_RX_BUF1_CFG_PKT_L(r16,v)                _BFSET_(r16,13,13,v)

    #define   GET32CIC_RX_BUF1_CFG_BYTE_SWAP_EN(r32)           _BFGET_(r32,14,14)
    #define   SET32CIC_RX_BUF1_CFG_BYTE_SWAP_EN(r32,v)         _BFSET_(r32,14,14,v)
    #define   GET16CIC_RX_BUF1_CFG_BYTE_SWAP_EN(r16)           _BFGET_(r16,14,14)
    #define   SET16CIC_RX_BUF1_CFG_BYTE_SWAP_EN(r16,v)         _BFSET_(r16,14,14,v)

    #define   GET32CIC_RX_BUF1_CFG_BIT_SWAP_EN(r32)            _BFGET_(r32,15,15)
    #define   SET32CIC_RX_BUF1_CFG_BIT_SWAP_EN(r32,v)          _BFSET_(r32,15,15,v)
    #define   GET16CIC_RX_BUF1_CFG_BIT_SWAP_EN(r16)            _BFGET_(r16,15,15)
    #define   SET16CIC_RX_BUF1_CFG_BIT_SWAP_EN(r16,v)          _BFSET_(r16,15,15,v)

    #define     w32CIC_RX_BUF1_CFG                             {\
            UNSG32 uRX_BUF1_CFG_SIZE                           : 12;\
            UNSG32 uRX_BUF1_CFG_PKT_F                          :  1;\
            UNSG32 uRX_BUF1_CFG_PKT_L                          :  1;\
            UNSG32 uRX_BUF1_CFG_BYTE_SWAP_EN                   :  1;\
            UNSG32 uRX_BUF1_CFG_BIT_SWAP_EN                    :  1;\
            UNSG32 RSVDx38_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_RX_BUF1_CFG;
            struct w32CIC_RX_BUF1_CFG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_SB_RD_DATA_WINDOW(r32)               _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_SB_RD_DATA_WINDOW(r32,v)             _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_SB_RD_DATA_WINDOW(r16)               _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_SB_RD_DATA_WINDOW(r16,v)             _BFSET_(r16, 7, 0,v)

    #define     w32CIC_S0_SB_RD_DATA                           {\
            UNSG32 uS0_SB_RD_DATA_WINDOW                       :  8;\
            UNSG32 RSVDx3C_b8                                  : 24;\
          }
    union { UNSG32 u32CIC_S0_SB_RD_DATA;
            struct w32CIC_S0_SB_RD_DATA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_SB_RD_DATA_WINDOW(r32)               _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_SB_RD_DATA_WINDOW(r32,v)             _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_SB_RD_DATA_WINDOW(r16)               _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_SB_RD_DATA_WINDOW(r16,v)             _BFSET_(r16, 7, 0,v)

    #define     w32CIC_S1_SB_RD_DATA                           {\
            UNSG32 uS1_SB_RD_DATA_WINDOW                       :  8;\
            UNSG32 RSVDx40_b8                                  : 24;\
          }
    union { UNSG32 u32CIC_S1_SB_RD_DATA;
            struct w32CIC_S1_SB_RD_DATA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_INT_STATUS_S0_OVERLOAD(r32)             _BFGET_(r32, 0, 0)
    #define   SET32CIC_INT_STATUS_S0_OVERLOAD(r32,v)           _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_INT_STATUS_S0_OVERLOAD(r16)             _BFGET_(r16, 0, 0)
    #define   SET16CIC_INT_STATUS_S0_OVERLOAD(r16,v)           _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_INT_STATUS_S0_CARD_INSERT(r32)          _BFGET_(r32, 1, 1)
    #define   SET32CIC_INT_STATUS_S0_CARD_INSERT(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_INT_STATUS_S0_CARD_INSERT(r16)          _BFGET_(r16, 1, 1)
    #define   SET16CIC_INT_STATUS_S0_CARD_INSERT(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_INT_STATUS_S0_CARD_REMOVE(r32)          _BFGET_(r32, 2, 2)
    #define   SET32CIC_INT_STATUS_S0_CARD_REMOVE(r32,v)        _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_INT_STATUS_S0_CARD_REMOVE(r16)          _BFGET_(r16, 2, 2)
    #define   SET16CIC_INT_STATUS_S0_CARD_REMOVE(r16,v)        _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_INT_STATUS_S0_CARD_RDY(r32)             _BFGET_(r32, 3, 3)
    #define   SET32CIC_INT_STATUS_S0_CARD_RDY(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_INT_STATUS_S0_CARD_RDY(r16)             _BFGET_(r16, 3, 3)
    #define   SET16CIC_INT_STATUS_S0_CARD_RDY(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_INT_STATUS_S0_CARD_RDY_TO(r32)          _BFGET_(r32, 4, 4)
    #define   SET32CIC_INT_STATUS_S0_CARD_RDY_TO(r32,v)        _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_INT_STATUS_S0_CARD_RDY_TO(r16)          _BFGET_(r16, 4, 4)
    #define   SET16CIC_INT_STATUS_S0_CARD_RDY_TO(r16,v)        _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_INT_STATUS_S0_IREQ(r32)                 _BFGET_(r32, 5, 5)
    #define   SET32CIC_INT_STATUS_S0_IREQ(r32,v)               _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_INT_STATUS_S0_IREQ(r16)                 _BFGET_(r16, 5, 5)
    #define   SET16CIC_INT_STATUS_S0_IREQ(r16,v)               _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_INT_STATUS_S0_BLOCK_WRITE(r32)          _BFGET_(r32, 6, 6)
    #define   SET32CIC_INT_STATUS_S0_BLOCK_WRITE(r32,v)        _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_INT_STATUS_S0_BLOCK_WRITE(r16)          _BFGET_(r16, 6, 6)
    #define   SET16CIC_INT_STATUS_S0_BLOCK_WRITE(r16,v)        _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_INT_STATUS_S0_BLOCK_READ(r32)           _BFGET_(r32, 7, 7)
    #define   SET32CIC_INT_STATUS_S0_BLOCK_READ(r32,v)         _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_INT_STATUS_S0_BLOCK_READ(r16)           _BFGET_(r16, 7, 7)
    #define   SET16CIC_INT_STATUS_S0_BLOCK_READ(r16,v)         _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_INT_STATUS_S0_SINGLE_WRITE(r32)         _BFGET_(r32, 8, 8)
    #define   SET32CIC_INT_STATUS_S0_SINGLE_WRITE(r32,v)       _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_INT_STATUS_S0_SINGLE_WRITE(r16)         _BFGET_(r16, 8, 8)
    #define   SET16CIC_INT_STATUS_S0_SINGLE_WRITE(r16,v)       _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_INT_STATUS_S0_SINGLE_READ(r32)          _BFGET_(r32, 9, 9)
    #define   SET32CIC_INT_STATUS_S0_SINGLE_READ(r32,v)        _BFSET_(r32, 9, 9,v)
    #define   GET16CIC_INT_STATUS_S0_SINGLE_READ(r16)          _BFGET_(r16, 9, 9)
    #define   SET16CIC_INT_STATUS_S0_SINGLE_READ(r16,v)        _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_INT_STATUS_S0_CARD_ERR(r32)             _BFGET_(r32,10,10)
    #define   SET32CIC_INT_STATUS_S0_CARD_ERR(r32,v)           _BFSET_(r32,10,10,v)
    #define   GET16CIC_INT_STATUS_S0_CARD_ERR(r16)             _BFGET_(r16,10,10)
    #define   SET16CIC_INT_STATUS_S0_CARD_ERR(r16,v)           _BFSET_(r16,10,10,v)

    #define   GET32CIC_INT_STATUS_S1_OVERLOAD(r32)             _BFGET_(r32,11,11)
    #define   SET32CIC_INT_STATUS_S1_OVERLOAD(r32,v)           _BFSET_(r32,11,11,v)
    #define   GET16CIC_INT_STATUS_S1_OVERLOAD(r16)             _BFGET_(r16,11,11)
    #define   SET16CIC_INT_STATUS_S1_OVERLOAD(r16,v)           _BFSET_(r16,11,11,v)

    #define   GET32CIC_INT_STATUS_S1_CARD_INSERT(r32)          _BFGET_(r32,12,12)
    #define   SET32CIC_INT_STATUS_S1_CARD_INSERT(r32,v)        _BFSET_(r32,12,12,v)
    #define   GET16CIC_INT_STATUS_S1_CARD_INSERT(r16)          _BFGET_(r16,12,12)
    #define   SET16CIC_INT_STATUS_S1_CARD_INSERT(r16,v)        _BFSET_(r16,12,12,v)

    #define   GET32CIC_INT_STATUS_S1_CARD_REMOVE(r32)          _BFGET_(r32,13,13)
    #define   SET32CIC_INT_STATUS_S1_CARD_REMOVE(r32,v)        _BFSET_(r32,13,13,v)
    #define   GET16CIC_INT_STATUS_S1_CARD_REMOVE(r16)          _BFGET_(r16,13,13)
    #define   SET16CIC_INT_STATUS_S1_CARD_REMOVE(r16,v)        _BFSET_(r16,13,13,v)

    #define   GET32CIC_INT_STATUS_S1_CARD_RDY(r32)             _BFGET_(r32,14,14)
    #define   SET32CIC_INT_STATUS_S1_CARD_RDY(r32,v)           _BFSET_(r32,14,14,v)
    #define   GET16CIC_INT_STATUS_S1_CARD_RDY(r16)             _BFGET_(r16,14,14)
    #define   SET16CIC_INT_STATUS_S1_CARD_RDY(r16,v)           _BFSET_(r16,14,14,v)

    #define   GET32CIC_INT_STATUS_S1_CARD_RDY_TO(r32)          _BFGET_(r32,15,15)
    #define   SET32CIC_INT_STATUS_S1_CARD_RDY_TO(r32,v)        _BFSET_(r32,15,15,v)
    #define   GET16CIC_INT_STATUS_S1_CARD_RDY_TO(r16)          _BFGET_(r16,15,15)
    #define   SET16CIC_INT_STATUS_S1_CARD_RDY_TO(r16,v)        _BFSET_(r16,15,15,v)

    #define   GET32CIC_INT_STATUS_S1_IREQ(r32)                 _BFGET_(r32,16,16)
    #define   SET32CIC_INT_STATUS_S1_IREQ(r32,v)               _BFSET_(r32,16,16,v)
    #define   GET16CIC_INT_STATUS_S1_IREQ(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16CIC_INT_STATUS_S1_IREQ(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_INT_STATUS_S1_BLOCK_WRITE(r32)          _BFGET_(r32,17,17)
    #define   SET32CIC_INT_STATUS_S1_BLOCK_WRITE(r32,v)        _BFSET_(r32,17,17,v)
    #define   GET16CIC_INT_STATUS_S1_BLOCK_WRITE(r16)          _BFGET_(r16, 1, 1)
    #define   SET16CIC_INT_STATUS_S1_BLOCK_WRITE(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_INT_STATUS_S1_BLOCK_READ(r32)           _BFGET_(r32,18,18)
    #define   SET32CIC_INT_STATUS_S1_BLOCK_READ(r32,v)         _BFSET_(r32,18,18,v)
    #define   GET16CIC_INT_STATUS_S1_BLOCK_READ(r16)           _BFGET_(r16, 2, 2)
    #define   SET16CIC_INT_STATUS_S1_BLOCK_READ(r16,v)         _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_INT_STATUS_S1_SINGLE_WRITE(r32)         _BFGET_(r32,19,19)
    #define   SET32CIC_INT_STATUS_S1_SINGLE_WRITE(r32,v)       _BFSET_(r32,19,19,v)
    #define   GET16CIC_INT_STATUS_S1_SINGLE_WRITE(r16)         _BFGET_(r16, 3, 3)
    #define   SET16CIC_INT_STATUS_S1_SINGLE_WRITE(r16,v)       _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_INT_STATUS_S1_SINGLE_READ(r32)          _BFGET_(r32,20,20)
    #define   SET32CIC_INT_STATUS_S1_SINGLE_READ(r32,v)        _BFSET_(r32,20,20,v)
    #define   GET16CIC_INT_STATUS_S1_SINGLE_READ(r16)          _BFGET_(r16, 4, 4)
    #define   SET16CIC_INT_STATUS_S1_SINGLE_READ(r16,v)        _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_INT_STATUS_S1_CARD_ERR(r32)             _BFGET_(r32,21,21)
    #define   SET32CIC_INT_STATUS_S1_CARD_ERR(r32,v)           _BFSET_(r32,21,21,v)
    #define   GET16CIC_INT_STATUS_S1_CARD_ERR(r16)             _BFGET_(r16, 5, 5)
    #define   SET16CIC_INT_STATUS_S1_CARD_ERR(r16,v)           _BFSET_(r16, 5, 5,v)

    #define     w32CIC_INT_STATUS                              {\
            UNSG32 uINT_STATUS_S0_OVERLOAD                     :  1;\
            UNSG32 uINT_STATUS_S0_CARD_INSERT                  :  1;\
            UNSG32 uINT_STATUS_S0_CARD_REMOVE                  :  1;\
            UNSG32 uINT_STATUS_S0_CARD_RDY                     :  1;\
            UNSG32 uINT_STATUS_S0_CARD_RDY_TO                  :  1;\
            UNSG32 uINT_STATUS_S0_IREQ                         :  1;\
            UNSG32 uINT_STATUS_S0_BLOCK_WRITE                  :  1;\
            UNSG32 uINT_STATUS_S0_BLOCK_READ                   :  1;\
            UNSG32 uINT_STATUS_S0_SINGLE_WRITE                 :  1;\
            UNSG32 uINT_STATUS_S0_SINGLE_READ                  :  1;\
            UNSG32 uINT_STATUS_S0_CARD_ERR                     :  1;\
            UNSG32 uINT_STATUS_S1_OVERLOAD                     :  1;\
            UNSG32 uINT_STATUS_S1_CARD_INSERT                  :  1;\
            UNSG32 uINT_STATUS_S1_CARD_REMOVE                  :  1;\
            UNSG32 uINT_STATUS_S1_CARD_RDY                     :  1;\
            UNSG32 uINT_STATUS_S1_CARD_RDY_TO                  :  1;\
            UNSG32 uINT_STATUS_S1_IREQ                         :  1;\
            UNSG32 uINT_STATUS_S1_BLOCK_WRITE                  :  1;\
            UNSG32 uINT_STATUS_S1_BLOCK_READ                   :  1;\
            UNSG32 uINT_STATUS_S1_SINGLE_WRITE                 :  1;\
            UNSG32 uINT_STATUS_S1_SINGLE_READ                  :  1;\
            UNSG32 uINT_STATUS_S1_CARD_ERR                     :  1;\
            UNSG32 RSVDx44_b22                                 : 10;\
          }
    union { UNSG32 u32CIC_INT_STATUS;
            struct w32CIC_INT_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_INT_MASK_S0_OVERLOAD(r32)               _BFGET_(r32, 0, 0)
    #define   SET32CIC_INT_MASK_S0_OVERLOAD(r32,v)             _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_INT_MASK_S0_OVERLOAD(r16)               _BFGET_(r16, 0, 0)
    #define   SET16CIC_INT_MASK_S0_OVERLOAD(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_INT_MASK_S0_CARD_INSERT(r32)            _BFGET_(r32, 1, 1)
    #define   SET32CIC_INT_MASK_S0_CARD_INSERT(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_INT_MASK_S0_CARD_INSERT(r16)            _BFGET_(r16, 1, 1)
    #define   SET16CIC_INT_MASK_S0_CARD_INSERT(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_INT_MASK_S0_CARD_REMOVE(r32)            _BFGET_(r32, 2, 2)
    #define   SET32CIC_INT_MASK_S0_CARD_REMOVE(r32,v)          _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_INT_MASK_S0_CARD_REMOVE(r16)            _BFGET_(r16, 2, 2)
    #define   SET16CIC_INT_MASK_S0_CARD_REMOVE(r16,v)          _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_INT_MASK_S0_CARD_RDY(r32)               _BFGET_(r32, 3, 3)
    #define   SET32CIC_INT_MASK_S0_CARD_RDY(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_INT_MASK_S0_CARD_RDY(r16)               _BFGET_(r16, 3, 3)
    #define   SET16CIC_INT_MASK_S0_CARD_RDY(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_INT_MASK_S0_CARD_RDY_TO(r32)            _BFGET_(r32, 4, 4)
    #define   SET32CIC_INT_MASK_S0_CARD_RDY_TO(r32,v)          _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_INT_MASK_S0_CARD_RDY_TO(r16)            _BFGET_(r16, 4, 4)
    #define   SET16CIC_INT_MASK_S0_CARD_RDY_TO(r16,v)          _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_INT_MASK_S0_IREQ(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32CIC_INT_MASK_S0_IREQ(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_INT_MASK_S0_IREQ(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16CIC_INT_MASK_S0_IREQ(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_INT_MASK_S0_BLOCK_WRITE(r32)            _BFGET_(r32, 6, 6)
    #define   SET32CIC_INT_MASK_S0_BLOCK_WRITE(r32,v)          _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_INT_MASK_S0_BLOCK_WRITE(r16)            _BFGET_(r16, 6, 6)
    #define   SET16CIC_INT_MASK_S0_BLOCK_WRITE(r16,v)          _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_INT_MASK_S0_BLOCK_READ(r32)             _BFGET_(r32, 7, 7)
    #define   SET32CIC_INT_MASK_S0_BLOCK_READ(r32,v)           _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_INT_MASK_S0_BLOCK_READ(r16)             _BFGET_(r16, 7, 7)
    #define   SET16CIC_INT_MASK_S0_BLOCK_READ(r16,v)           _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_INT_MASK_S0_SINGLE_WRITE(r32)           _BFGET_(r32, 8, 8)
    #define   SET32CIC_INT_MASK_S0_SINGLE_WRITE(r32,v)         _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_INT_MASK_S0_SINGLE_WRITE(r16)           _BFGET_(r16, 8, 8)
    #define   SET16CIC_INT_MASK_S0_SINGLE_WRITE(r16,v)         _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_INT_MASK_S0_SINGLE_READ(r32)            _BFGET_(r32, 9, 9)
    #define   SET32CIC_INT_MASK_S0_SINGLE_READ(r32,v)          _BFSET_(r32, 9, 9,v)
    #define   GET16CIC_INT_MASK_S0_SINGLE_READ(r16)            _BFGET_(r16, 9, 9)
    #define   SET16CIC_INT_MASK_S0_SINGLE_READ(r16,v)          _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_INT_MASK_S0_CARD_ERR(r32)               _BFGET_(r32,10,10)
    #define   SET32CIC_INT_MASK_S0_CARD_ERR(r32,v)             _BFSET_(r32,10,10,v)
    #define   GET16CIC_INT_MASK_S0_CARD_ERR(r16)               _BFGET_(r16,10,10)
    #define   SET16CIC_INT_MASK_S0_CARD_ERR(r16,v)             _BFSET_(r16,10,10,v)

    #define   GET32CIC_INT_MASK_S1_OVERLOAD(r32)               _BFGET_(r32,11,11)
    #define   SET32CIC_INT_MASK_S1_OVERLOAD(r32,v)             _BFSET_(r32,11,11,v)
    #define   GET16CIC_INT_MASK_S1_OVERLOAD(r16)               _BFGET_(r16,11,11)
    #define   SET16CIC_INT_MASK_S1_OVERLOAD(r16,v)             _BFSET_(r16,11,11,v)

    #define   GET32CIC_INT_MASK_S1_CARD_INSERT(r32)            _BFGET_(r32,12,12)
    #define   SET32CIC_INT_MASK_S1_CARD_INSERT(r32,v)          _BFSET_(r32,12,12,v)
    #define   GET16CIC_INT_MASK_S1_CARD_INSERT(r16)            _BFGET_(r16,12,12)
    #define   SET16CIC_INT_MASK_S1_CARD_INSERT(r16,v)          _BFSET_(r16,12,12,v)

    #define   GET32CIC_INT_MASK_S1_CARD_REMOVE(r32)            _BFGET_(r32,13,13)
    #define   SET32CIC_INT_MASK_S1_CARD_REMOVE(r32,v)          _BFSET_(r32,13,13,v)
    #define   GET16CIC_INT_MASK_S1_CARD_REMOVE(r16)            _BFGET_(r16,13,13)
    #define   SET16CIC_INT_MASK_S1_CARD_REMOVE(r16,v)          _BFSET_(r16,13,13,v)

    #define   GET32CIC_INT_MASK_S1_CARD_RDY(r32)               _BFGET_(r32,14,14)
    #define   SET32CIC_INT_MASK_S1_CARD_RDY(r32,v)             _BFSET_(r32,14,14,v)
    #define   GET16CIC_INT_MASK_S1_CARD_RDY(r16)               _BFGET_(r16,14,14)
    #define   SET16CIC_INT_MASK_S1_CARD_RDY(r16,v)             _BFSET_(r16,14,14,v)

    #define   GET32CIC_INT_MASK_S1_CARD_RDY_TO(r32)            _BFGET_(r32,15,15)
    #define   SET32CIC_INT_MASK_S1_CARD_RDY_TO(r32,v)          _BFSET_(r32,15,15,v)
    #define   GET16CIC_INT_MASK_S1_CARD_RDY_TO(r16)            _BFGET_(r16,15,15)
    #define   SET16CIC_INT_MASK_S1_CARD_RDY_TO(r16,v)          _BFSET_(r16,15,15,v)

    #define   GET32CIC_INT_MASK_S1_IREQ(r32)                   _BFGET_(r32,16,16)
    #define   SET32CIC_INT_MASK_S1_IREQ(r32,v)                 _BFSET_(r32,16,16,v)
    #define   GET16CIC_INT_MASK_S1_IREQ(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16CIC_INT_MASK_S1_IREQ(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_INT_MASK_S1_BLOCK_WRITE(r32)            _BFGET_(r32,17,17)
    #define   SET32CIC_INT_MASK_S1_BLOCK_WRITE(r32,v)          _BFSET_(r32,17,17,v)
    #define   GET16CIC_INT_MASK_S1_BLOCK_WRITE(r16)            _BFGET_(r16, 1, 1)
    #define   SET16CIC_INT_MASK_S1_BLOCK_WRITE(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_INT_MASK_S1_BLOCK_READ(r32)             _BFGET_(r32,18,18)
    #define   SET32CIC_INT_MASK_S1_BLOCK_READ(r32,v)           _BFSET_(r32,18,18,v)
    #define   GET16CIC_INT_MASK_S1_BLOCK_READ(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CIC_INT_MASK_S1_BLOCK_READ(r16,v)           _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_INT_MASK_S1_SINGLE_WRITE(r32)           _BFGET_(r32,19,19)
    #define   SET32CIC_INT_MASK_S1_SINGLE_WRITE(r32,v)         _BFSET_(r32,19,19,v)
    #define   GET16CIC_INT_MASK_S1_SINGLE_WRITE(r16)           _BFGET_(r16, 3, 3)
    #define   SET16CIC_INT_MASK_S1_SINGLE_WRITE(r16,v)         _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_INT_MASK_S1_SINGLE_READ(r32)            _BFGET_(r32,20,20)
    #define   SET32CIC_INT_MASK_S1_SINGLE_READ(r32,v)          _BFSET_(r32,20,20,v)
    #define   GET16CIC_INT_MASK_S1_SINGLE_READ(r16)            _BFGET_(r16, 4, 4)
    #define   SET16CIC_INT_MASK_S1_SINGLE_READ(r16,v)          _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_INT_MASK_S1_CARD_ERR(r32)               _BFGET_(r32,21,21)
    #define   SET32CIC_INT_MASK_S1_CARD_ERR(r32,v)             _BFSET_(r32,21,21,v)
    #define   GET16CIC_INT_MASK_S1_CARD_ERR(r16)               _BFGET_(r16, 5, 5)
    #define   SET16CIC_INT_MASK_S1_CARD_ERR(r16,v)             _BFSET_(r16, 5, 5,v)

    #define     w32CIC_INT_MASK                                {\
            UNSG32 uINT_MASK_S0_OVERLOAD                       :  1;\
            UNSG32 uINT_MASK_S0_CARD_INSERT                    :  1;\
            UNSG32 uINT_MASK_S0_CARD_REMOVE                    :  1;\
            UNSG32 uINT_MASK_S0_CARD_RDY                       :  1;\
            UNSG32 uINT_MASK_S0_CARD_RDY_TO                    :  1;\
            UNSG32 uINT_MASK_S0_IREQ                           :  1;\
            UNSG32 uINT_MASK_S0_BLOCK_WRITE                    :  1;\
            UNSG32 uINT_MASK_S0_BLOCK_READ                     :  1;\
            UNSG32 uINT_MASK_S0_SINGLE_WRITE                   :  1;\
            UNSG32 uINT_MASK_S0_SINGLE_READ                    :  1;\
            UNSG32 uINT_MASK_S0_CARD_ERR                       :  1;\
            UNSG32 uINT_MASK_S1_OVERLOAD                       :  1;\
            UNSG32 uINT_MASK_S1_CARD_INSERT                    :  1;\
            UNSG32 uINT_MASK_S1_CARD_REMOVE                    :  1;\
            UNSG32 uINT_MASK_S1_CARD_RDY                       :  1;\
            UNSG32 uINT_MASK_S1_CARD_RDY_TO                    :  1;\
            UNSG32 uINT_MASK_S1_IREQ                           :  1;\
            UNSG32 uINT_MASK_S1_BLOCK_WRITE                    :  1;\
            UNSG32 uINT_MASK_S1_BLOCK_READ                     :  1;\
            UNSG32 uINT_MASK_S1_SINGLE_WRITE                   :  1;\
            UNSG32 uINT_MASK_S1_SINGLE_READ                    :  1;\
            UNSG32 uINT_MASK_S1_CARD_ERR                       :  1;\
            UNSG32 RSVDx48_b22                                 : 10;\
          }
    union { UNSG32 u32CIC_INT_MASK;
            struct w32CIC_INT_MASK;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_INT_TRIG_POL_S0_OVERLOAD(r32)           _BFGET_(r32, 0, 0)
    #define   SET32CIC_INT_TRIG_POL_S0_OVERLOAD(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_INT_TRIG_POL_S0_OVERLOAD(r16)           _BFGET_(r16, 0, 0)
    #define   SET16CIC_INT_TRIG_POL_S0_OVERLOAD(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_INT_TRIG_POL_S1_OVERLOAD(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CIC_INT_TRIG_POL_S1_OVERLOAD(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_INT_TRIG_POL_S1_OVERLOAD(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CIC_INT_TRIG_POL_S1_OVERLOAD(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_INT_TRIG_POL_S0_CD(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32CIC_INT_TRIG_POL_S0_CD(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_INT_TRIG_POL_S0_CD(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16CIC_INT_TRIG_POL_S0_CD(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_INT_TRIG_POL_S1_CD(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32CIC_INT_TRIG_POL_S1_CD(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_INT_TRIG_POL_S1_CD(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16CIC_INT_TRIG_POL_S1_CD(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_INT_TRIG_POL_S0_IREQ(r32)               _BFGET_(r32, 4, 4)
    #define   SET32CIC_INT_TRIG_POL_S0_IREQ(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_INT_TRIG_POL_S0_IREQ(r16)               _BFGET_(r16, 4, 4)
    #define   SET16CIC_INT_TRIG_POL_S0_IREQ(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_INT_TRIG_POL_S1_IREQ(r32)               _BFGET_(r32, 5, 5)
    #define   SET32CIC_INT_TRIG_POL_S1_IREQ(r32,v)             _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_INT_TRIG_POL_S1_IREQ(r16)               _BFGET_(r16, 5, 5)
    #define   SET16CIC_INT_TRIG_POL_S1_IREQ(r16,v)             _BFSET_(r16, 5, 5,v)

    #define     w32CIC_INT_TRIG_POL                            {\
            UNSG32 uINT_TRIG_POL_S0_OVERLOAD                   :  1;\
            UNSG32 uINT_TRIG_POL_S1_OVERLOAD                   :  1;\
            UNSG32 uINT_TRIG_POL_S0_CD                         :  1;\
            UNSG32 uINT_TRIG_POL_S1_CD                         :  1;\
            UNSG32 uINT_TRIG_POL_S0_IREQ                       :  1;\
            UNSG32 uINT_TRIG_POL_S1_IREQ                       :  1;\
            UNSG32 RSVDx4C_b6                                  : 26;\
          }
    union { UNSG32 u32CIC_INT_TRIG_POL;
            struct w32CIC_INT_TRIG_POL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_DA_REQ_CYC(r32)                         _BFGET_(r32, 7, 0)
    #define   SET32CIC_DA_REQ_CYC(r32,v)                       _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_DA_REQ_CYC(r16)                         _BFGET_(r16, 7, 0)
    #define   SET16CIC_DA_REQ_CYC(r16,v)                       _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_DA_PRI_EN(r32)                          _BFGET_(r32, 8, 8)
    #define   SET32CIC_DA_PRI_EN(r32,v)                        _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_DA_PRI_EN(r16)                          _BFGET_(r16, 8, 8)
    #define   SET16CIC_DA_PRI_EN(r16,v)                        _BFSET_(r16, 8, 8,v)

    #define     w32CIC_DA                                      {\
            UNSG32 uDA_REQ_CYC                                 :  8;\
            UNSG32 uDA_PRI_EN                                  :  1;\
            UNSG32 RSVDx50_b9                                  : 23;\
          }
    union { UNSG32 u32CIC_DA;
            struct w32CIC_DA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_HC_DLY_CLR(r32)                         _BFGET_(r32,11, 0)
    #define   SET32CIC_HC_DLY_CLR(r32,v)                       _BFSET_(r32,11, 0,v)
    #define   GET16CIC_HC_DLY_CLR(r16)                         _BFGET_(r16,11, 0)
    #define   SET16CIC_HC_DLY_CLR(r16,v)                       _BFSET_(r16,11, 0,v)

    #define   GET32CIC_HC_DLY_RETRY(r32)                       _BFGET_(r32,19,12)
    #define   SET32CIC_HC_DLY_RETRY(r32,v)                     _BFSET_(r32,19,12,v)

    #define     w32CIC_HC_DLY                                  {\
            UNSG32 uHC_DLY_CLR                                 : 12;\
            UNSG32 uHC_DLY_RETRY                               :  8;\
            UNSG32 RSVDx54_b20                                 : 12;\
          }
    union { UNSG32 u32CIC_HC_DLY;
            struct w32CIC_HC_DLY;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_PHY_MIRROR_STAT_S0_OVERLOAD(r32)        _BFGET_(r32, 0, 0)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_OVERLOAD(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_OVERLOAD(r16)        _BFGET_(r16, 0, 0)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_OVERLOAD(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S1_OVERLOAD(r32)        _BFGET_(r32, 1, 1)
    #define   SET32CIC_PHY_MIRROR_STAT_S1_OVERLOAD(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S1_OVERLOAD(r16)        _BFGET_(r16, 1, 1)
    #define   SET16CIC_PHY_MIRROR_STAT_S1_OVERLOAD(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_CD1(r32)             _BFGET_(r32, 2, 2)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_CD1(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_CD1(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_CD1(r16,v)           _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S1_CD1(r32)             _BFGET_(r32, 3, 3)
    #define   SET32CIC_PHY_MIRROR_STAT_S1_CD1(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S1_CD1(r16)             _BFGET_(r16, 3, 3)
    #define   SET16CIC_PHY_MIRROR_STAT_S1_CD1(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_CD2(r32)             _BFGET_(r32, 4, 4)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_CD2(r32,v)           _BFSET_(r32, 4, 4,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_CD2(r16)             _BFGET_(r16, 4, 4)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_CD2(r16,v)           _BFSET_(r16, 4, 4,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S1_CD2(r32)             _BFGET_(r32, 5, 5)
    #define   SET32CIC_PHY_MIRROR_STAT_S1_CD2(r32,v)           _BFSET_(r32, 5, 5,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S1_CD2(r16)             _BFGET_(r16, 5, 5)
    #define   SET16CIC_PHY_MIRROR_STAT_S1_CD2(r16,v)           _BFSET_(r16, 5, 5,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_IREQ(r32)            _BFGET_(r32, 6, 6)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_IREQ(r32,v)          _BFSET_(r32, 6, 6,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_IREQ(r16)            _BFGET_(r16, 6, 6)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_IREQ(r16,v)          _BFSET_(r16, 6, 6,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S1_IREQ(r32)            _BFGET_(r32, 7, 7)
    #define   SET32CIC_PHY_MIRROR_STAT_S1_IREQ(r32,v)          _BFSET_(r32, 7, 7,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S1_IREQ(r16)            _BFGET_(r16, 7, 7)
    #define   SET16CIC_PHY_MIRROR_STAT_S1_IREQ(r16,v)          _BFSET_(r16, 7, 7,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_VS1(r32)             _BFGET_(r32, 8, 8)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_VS1(r32,v)           _BFSET_(r32, 8, 8,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_VS1(r16)             _BFGET_(r16, 8, 8)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_VS1(r16,v)           _BFSET_(r16, 8, 8,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S1_VS1(r32)             _BFGET_(r32, 9, 9)
    #define   SET32CIC_PHY_MIRROR_STAT_S1_VS1(r32,v)           _BFSET_(r32, 9, 9,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S1_VS1(r16)             _BFGET_(r16, 9, 9)
    #define   SET16CIC_PHY_MIRROR_STAT_S1_VS1(r16,v)           _BFSET_(r16, 9, 9,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_VS2(r32)             _BFGET_(r32,10,10)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_VS2(r32,v)           _BFSET_(r32,10,10,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_VS2(r16)             _BFGET_(r16,10,10)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_VS2(r16,v)           _BFSET_(r16,10,10,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_MDET(r32)            _BFGET_(r32,11,11)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_MDET(r32,v)          _BFSET_(r32,11,11,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_MDET(r16)            _BFGET_(r16,11,11)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_MDET(r16,v)          _BFSET_(r16,11,11,v)

    #define   GET32CIC_PHY_MIRROR_STAT_S0_SDO(r32)             _BFGET_(r32,12,12)
    #define   SET32CIC_PHY_MIRROR_STAT_S0_SDO(r32,v)           _BFSET_(r32,12,12,v)
    #define   GET16CIC_PHY_MIRROR_STAT_S0_SDO(r16)             _BFGET_(r16,12,12)
    #define   SET16CIC_PHY_MIRROR_STAT_S0_SDO(r16,v)           _BFSET_(r16,12,12,v)

    #define     w32CIC_PHY_MIRROR_STAT                         {\
            UNSG32 uPHY_MIRROR_STAT_S0_OVERLOAD                :  1;\
            UNSG32 uPHY_MIRROR_STAT_S1_OVERLOAD                :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_CD1                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S1_CD1                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_CD2                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S1_CD2                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_IREQ                    :  1;\
            UNSG32 uPHY_MIRROR_STAT_S1_IREQ                    :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_VS1                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S1_VS1                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_VS2                     :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_MDET                    :  1;\
            UNSG32 uPHY_MIRROR_STAT_S0_SDO                     :  1;\
            UNSG32 RSVDx58_b13                                 : 19;\
          }
    union { UNSG32 u32CIC_PHY_MIRROR_STAT;
            struct w32CIC_PHY_MIRROR_STAT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_PH_CYC_SU(r32)                   _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_PHY_PH_CYC_SU(r32,v)                 _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_PHY_PH_CYC_SU(r16)                   _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_PH_CYC_SU(r16,v)                 _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_PH_CYC_PRE_WAIT(r32)             _BFGET_(r32,15, 8)
    #define   SET32CIC_S0_PHY_PH_CYC_PRE_WAIT(r32,v)           _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S0_PHY_PH_CYC_PRE_WAIT(r16)             _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_PH_CYC_PRE_WAIT(r16,v)           _BFSET_(r16,15, 8,v)

    #define   GET32CIC_S0_PHY_PH_CYC_WAIT(r32)                 _BFGET_(r32,23,16)
    #define   SET32CIC_S0_PHY_PH_CYC_WAIT(r32,v)               _BFSET_(r32,23,16,v)
    #define   GET16CIC_S0_PHY_PH_CYC_WAIT(r16)                 _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_PH_CYC_WAIT(r16,v)               _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_PH_CYC_HO(r32)                   _BFGET_(r32,31,24)
    #define   SET32CIC_S0_PHY_PH_CYC_HO(r32,v)                 _BFSET_(r32,31,24,v)
    #define   GET16CIC_S0_PHY_PH_CYC_HO(r16)                   _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_PH_CYC_HO(r16,v)                 _BFSET_(r16,15, 8,v)

    #define     w32CIC_S0_PHY_PH_CYC                           {\
            UNSG32 uS0_PHY_PH_CYC_SU                           :  8;\
            UNSG32 uS0_PHY_PH_CYC_PRE_WAIT                     :  8;\
            UNSG32 uS0_PHY_PH_CYC_WAIT                         :  8;\
            UNSG32 uS0_PHY_PH_CYC_HO                           :  8;\
          }
    union { UNSG32 u32CIC_S0_PHY_PH_CYC;
            struct w32CIC_S0_PHY_PH_CYC;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_PH_CYC_SU(r32)                   _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_PHY_PH_CYC_SU(r32,v)                 _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_PHY_PH_CYC_SU(r16)                   _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_PH_CYC_SU(r16,v)                 _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_PH_CYC_PRE_WAIT(r32)             _BFGET_(r32,15, 8)
    #define   SET32CIC_S1_PHY_PH_CYC_PRE_WAIT(r32,v)           _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S1_PHY_PH_CYC_PRE_WAIT(r16)             _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_PH_CYC_PRE_WAIT(r16,v)           _BFSET_(r16,15, 8,v)

    #define   GET32CIC_S1_PHY_PH_CYC_WAIT(r32)                 _BFGET_(r32,23,16)
    #define   SET32CIC_S1_PHY_PH_CYC_WAIT(r32,v)               _BFSET_(r32,23,16,v)
    #define   GET16CIC_S1_PHY_PH_CYC_WAIT(r16)                 _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_PH_CYC_WAIT(r16,v)               _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_PH_CYC_HO(r32)                   _BFGET_(r32,31,24)
    #define   SET32CIC_S1_PHY_PH_CYC_HO(r32,v)                 _BFSET_(r32,31,24,v)
    #define   GET16CIC_S1_PHY_PH_CYC_HO(r16)                   _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_PH_CYC_HO(r16,v)                 _BFSET_(r16,15, 8,v)

    #define     w32CIC_S1_PHY_PH_CYC                           {\
            UNSG32 uS1_PHY_PH_CYC_SU                           :  8;\
            UNSG32 uS1_PHY_PH_CYC_PRE_WAIT                     :  8;\
            UNSG32 uS1_PHY_PH_CYC_WAIT                         :  8;\
            UNSG32 uS1_PHY_PH_CYC_HO                           :  8;\
          }
    union { UNSG32 u32CIC_S1_PHY_PH_CYC;
            struct w32CIC_S1_PHY_PH_CYC;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_WAIT_POL(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_WAIT_POL(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_WAIT_POL(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_WAIT_POL(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_WAIT_SYNC(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32CIC_S0_PHY_WAIT_SYNC(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_S0_PHY_WAIT_SYNC(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16CIC_S0_PHY_WAIT_SYNC(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_S0_PHY_WAIT_PRI(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32CIC_S0_PHY_WAIT_PRI(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_S0_PHY_WAIT_PRI(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16CIC_S0_PHY_WAIT_PRI(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_S0_PHY_WAIT_TIMEOUT_UNIT(r32)           _BFGET_(r32, 4, 3)
    #define   SET32CIC_S0_PHY_WAIT_TIMEOUT_UNIT(r32,v)         _BFSET_(r32, 4, 3,v)
    #define   GET16CIC_S0_PHY_WAIT_TIMEOUT_UNIT(r16)           _BFGET_(r16, 4, 3)
    #define   SET16CIC_S0_PHY_WAIT_TIMEOUT_UNIT(r16,v)         _BFSET_(r16, 4, 3,v)

    #define   GET32CIC_S0_PHY_WAIT_TIMEOUT_PERIOD(r32)         _BFGET_(r32,14, 5)
    #define   SET32CIC_S0_PHY_WAIT_TIMEOUT_PERIOD(r32,v)       _BFSET_(r32,14, 5,v)
    #define   GET16CIC_S0_PHY_WAIT_TIMEOUT_PERIOD(r16)         _BFGET_(r16,14, 5)
    #define   SET16CIC_S0_PHY_WAIT_TIMEOUT_PERIOD(r16,v)       _BFSET_(r16,14, 5,v)

    #define     w32CIC_S0_PHY_WAIT                             {\
            UNSG32 uS0_PHY_WAIT_POL                            :  1;\
            UNSG32 uS0_PHY_WAIT_SYNC                           :  1;\
            UNSG32 uS0_PHY_WAIT_PRI                            :  1;\
            UNSG32 uS0_PHY_WAIT_TIMEOUT_UNIT                   :  2;\
            UNSG32 uS0_PHY_WAIT_TIMEOUT_PERIOD                 : 10;\
            UNSG32 RSVDx64_b15                                 : 17;\
          }
    union { UNSG32 u32CIC_S0_PHY_WAIT;
            struct w32CIC_S0_PHY_WAIT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_WAIT_POL(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_WAIT_POL(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_WAIT_POL(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_WAIT_POL(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_WAIT_SYNC(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32CIC_S1_PHY_WAIT_SYNC(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_S1_PHY_WAIT_SYNC(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16CIC_S1_PHY_WAIT_SYNC(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_S1_PHY_WAIT_PRI(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32CIC_S1_PHY_WAIT_PRI(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_S1_PHY_WAIT_PRI(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16CIC_S1_PHY_WAIT_PRI(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_S1_PHY_WAIT_TIMEOUT_UNIT(r32)           _BFGET_(r32, 4, 3)
    #define   SET32CIC_S1_PHY_WAIT_TIMEOUT_UNIT(r32,v)         _BFSET_(r32, 4, 3,v)
    #define   GET16CIC_S1_PHY_WAIT_TIMEOUT_UNIT(r16)           _BFGET_(r16, 4, 3)
    #define   SET16CIC_S1_PHY_WAIT_TIMEOUT_UNIT(r16,v)         _BFSET_(r16, 4, 3,v)

    #define   GET32CIC_S1_PHY_WAIT_TIMEOUT_PERIOD(r32)         _BFGET_(r32,14, 5)
    #define   SET32CIC_S1_PHY_WAIT_TIMEOUT_PERIOD(r32,v)       _BFSET_(r32,14, 5,v)
    #define   GET16CIC_S1_PHY_WAIT_TIMEOUT_PERIOD(r16)         _BFGET_(r16,14, 5)
    #define   SET16CIC_S1_PHY_WAIT_TIMEOUT_PERIOD(r16,v)       _BFSET_(r16,14, 5,v)

    #define     w32CIC_S1_PHY_WAIT                             {\
            UNSG32 uS1_PHY_WAIT_POL                            :  1;\
            UNSG32 uS1_PHY_WAIT_SYNC                           :  1;\
            UNSG32 uS1_PHY_WAIT_PRI                            :  1;\
            UNSG32 uS1_PHY_WAIT_TIMEOUT_UNIT                   :  2;\
            UNSG32 uS1_PHY_WAIT_TIMEOUT_PERIOD                 : 10;\
            UNSG32 RSVDx68_b15                                 : 17;\
          }
    union { UNSG32 u32CIC_S1_PHY_WAIT;
            struct w32CIC_S1_PHY_WAIT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_REG_POL(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_REG_POL(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_REG_POL(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_REG_POL(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_REG_SU_TIM(r32)                  _BFGET_(r32, 8, 1)
    #define   SET32CIC_S0_PHY_REG_SU_TIM(r32,v)                _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S0_PHY_REG_SU_TIM(r16)                  _BFGET_(r16, 8, 1)
    #define   SET16CIC_S0_PHY_REG_SU_TIM(r16,v)                _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S0_PHY_REG_HO_TIM(r32)                  _BFGET_(r32,16, 9)
    #define   SET32CIC_S0_PHY_REG_HO_TIM(r32,v)                _BFSET_(r32,16, 9,v)

    #define     w32CIC_S0_PHY_REG                              {\
            UNSG32 uS0_PHY_REG_POL                             :  1;\
            UNSG32 uS0_PHY_REG_SU_TIM                          :  8;\
            UNSG32 uS0_PHY_REG_HO_TIM                          :  8;\
            UNSG32 RSVDx6C_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S0_PHY_REG;
            struct w32CIC_S0_PHY_REG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_REG_POL(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_REG_POL(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_REG_POL(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_REG_POL(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_REG_SU_TIM(r32)                  _BFGET_(r32, 8, 1)
    #define   SET32CIC_S1_PHY_REG_SU_TIM(r32,v)                _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S1_PHY_REG_SU_TIM(r16)                  _BFGET_(r16, 8, 1)
    #define   SET16CIC_S1_PHY_REG_SU_TIM(r16,v)                _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S1_PHY_REG_HO_TIM(r32)                  _BFGET_(r32,16, 9)
    #define   SET32CIC_S1_PHY_REG_HO_TIM(r32,v)                _BFSET_(r32,16, 9,v)

    #define     w32CIC_S1_PHY_REG                              {\
            UNSG32 uS1_PHY_REG_POL                             :  1;\
            UNSG32 uS1_PHY_REG_SU_TIM                          :  8;\
            UNSG32 uS1_PHY_REG_HO_TIM                          :  8;\
            UNSG32 RSVDx70_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S1_PHY_REG;
            struct w32CIC_S1_PHY_REG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_CE_POL(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_CE_POL(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_CE_POL(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_CE_POL(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_CE_SU_TIM(r32)                   _BFGET_(r32, 8, 1)
    #define   SET32CIC_S0_PHY_CE_SU_TIM(r32,v)                 _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S0_PHY_CE_SU_TIM(r16)                   _BFGET_(r16, 8, 1)
    #define   SET16CIC_S0_PHY_CE_SU_TIM(r16,v)                 _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S0_PHY_CE_HO_TIM(r32)                   _BFGET_(r32,16, 9)
    #define   SET32CIC_S0_PHY_CE_HO_TIM(r32,v)                 _BFSET_(r32,16, 9,v)

    #define     w32CIC_S0_PHY_CE                               {\
            UNSG32 uS0_PHY_CE_POL                              :  1;\
            UNSG32 uS0_PHY_CE_SU_TIM                           :  8;\
            UNSG32 uS0_PHY_CE_HO_TIM                           :  8;\
            UNSG32 RSVDx74_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S0_PHY_CE;
            struct w32CIC_S0_PHY_CE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_CE_POL(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_CE_POL(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_CE_POL(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_CE_POL(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_CE_SU_TIM(r32)                   _BFGET_(r32, 8, 1)
    #define   SET32CIC_S1_PHY_CE_SU_TIM(r32,v)                 _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S1_PHY_CE_SU_TIM(r16)                   _BFGET_(r16, 8, 1)
    #define   SET16CIC_S1_PHY_CE_SU_TIM(r16,v)                 _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S1_PHY_CE_HO_TIM(r32)                   _BFGET_(r32,16, 9)
    #define   SET32CIC_S1_PHY_CE_HO_TIM(r32,v)                 _BFSET_(r32,16, 9,v)

    #define     w32CIC_S1_PHY_CE                               {\
            UNSG32 uS1_PHY_CE_POL                              :  1;\
            UNSG32 uS1_PHY_CE_SU_TIM                           :  8;\
            UNSG32 uS1_PHY_CE_HO_TIM                           :  8;\
            UNSG32 RSVDx78_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S1_PHY_CE;
            struct w32CIC_S1_PHY_CE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_OE_POL(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_OE_POL(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_OE_POL(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_OE_POL(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_OE_SU_TIM(r32)                   _BFGET_(r32, 8, 1)
    #define   SET32CIC_S0_PHY_OE_SU_TIM(r32,v)                 _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S0_PHY_OE_SU_TIM(r16)                   _BFGET_(r16, 8, 1)
    #define   SET16CIC_S0_PHY_OE_SU_TIM(r16,v)                 _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S0_PHY_OE_HO_TIM(r32)                   _BFGET_(r32,16, 9)
    #define   SET32CIC_S0_PHY_OE_HO_TIM(r32,v)                 _BFSET_(r32,16, 9,v)

    #define     w32CIC_S0_PHY_OE                               {\
            UNSG32 uS0_PHY_OE_POL                              :  1;\
            UNSG32 uS0_PHY_OE_SU_TIM                           :  8;\
            UNSG32 uS0_PHY_OE_HO_TIM                           :  8;\
            UNSG32 RSVDx7C_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S0_PHY_OE;
            struct w32CIC_S0_PHY_OE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_OE_POL(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_OE_POL(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_OE_POL(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_OE_POL(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_OE_SU_TIM(r32)                   _BFGET_(r32, 8, 1)
    #define   SET32CIC_S1_PHY_OE_SU_TIM(r32,v)                 _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S1_PHY_OE_SU_TIM(r16)                   _BFGET_(r16, 8, 1)
    #define   SET16CIC_S1_PHY_OE_SU_TIM(r16,v)                 _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S1_PHY_OE_HO_TIM(r32)                   _BFGET_(r32,16, 9)
    #define   SET32CIC_S1_PHY_OE_HO_TIM(r32,v)                 _BFSET_(r32,16, 9,v)

    #define     w32CIC_S1_PHY_OE                               {\
            UNSG32 uS1_PHY_OE_POL                              :  1;\
            UNSG32 uS1_PHY_OE_SU_TIM                           :  8;\
            UNSG32 uS1_PHY_OE_HO_TIM                           :  8;\
            UNSG32 RSVDx80_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S1_PHY_OE;
            struct w32CIC_S1_PHY_OE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_WE_POL(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_WE_POL(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_WE_POL(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_WE_POL(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_WE_SU_TIM(r32)                   _BFGET_(r32, 8, 1)
    #define   SET32CIC_S0_PHY_WE_SU_TIM(r32,v)                 _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S0_PHY_WE_SU_TIM(r16)                   _BFGET_(r16, 8, 1)
    #define   SET16CIC_S0_PHY_WE_SU_TIM(r16,v)                 _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S0_PHY_WE_HO_TIM(r32)                   _BFGET_(r32,16, 9)
    #define   SET32CIC_S0_PHY_WE_HO_TIM(r32,v)                 _BFSET_(r32,16, 9,v)

    #define     w32CIC_S0_PHY_WE                               {\
            UNSG32 uS0_PHY_WE_POL                              :  1;\
            UNSG32 uS0_PHY_WE_SU_TIM                           :  8;\
            UNSG32 uS0_PHY_WE_HO_TIM                           :  8;\
            UNSG32 RSVDx84_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S0_PHY_WE;
            struct w32CIC_S0_PHY_WE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_WE_POL(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_WE_POL(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_WE_POL(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_WE_POL(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_WE_SU_TIM(r32)                   _BFGET_(r32, 8, 1)
    #define   SET32CIC_S1_PHY_WE_SU_TIM(r32,v)                 _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S1_PHY_WE_SU_TIM(r16)                   _BFGET_(r16, 8, 1)
    #define   SET16CIC_S1_PHY_WE_SU_TIM(r16,v)                 _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S1_PHY_WE_HO_TIM(r32)                   _BFGET_(r32,16, 9)
    #define   SET32CIC_S1_PHY_WE_HO_TIM(r32,v)                 _BFSET_(r32,16, 9,v)

    #define     w32CIC_S1_PHY_WE                               {\
            UNSG32 uS1_PHY_WE_POL                              :  1;\
            UNSG32 uS1_PHY_WE_SU_TIM                           :  8;\
            UNSG32 uS1_PHY_WE_HO_TIM                           :  8;\
            UNSG32 RSVDx88_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S1_PHY_WE;
            struct w32CIC_S1_PHY_WE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_IORD_POL(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_IORD_POL(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_IORD_POL(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_IORD_POL(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_IORD_SU_TIM(r32)                 _BFGET_(r32, 8, 1)
    #define   SET32CIC_S0_PHY_IORD_SU_TIM(r32,v)               _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S0_PHY_IORD_SU_TIM(r16)                 _BFGET_(r16, 8, 1)
    #define   SET16CIC_S0_PHY_IORD_SU_TIM(r16,v)               _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S0_PHY_IORD_HO_TIM(r32)                 _BFGET_(r32,16, 9)
    #define   SET32CIC_S0_PHY_IORD_HO_TIM(r32,v)               _BFSET_(r32,16, 9,v)

    #define     w32CIC_S0_PHY_IORD                             {\
            UNSG32 uS0_PHY_IORD_POL                            :  1;\
            UNSG32 uS0_PHY_IORD_SU_TIM                         :  8;\
            UNSG32 uS0_PHY_IORD_HO_TIM                         :  8;\
            UNSG32 RSVDx8C_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S0_PHY_IORD;
            struct w32CIC_S0_PHY_IORD;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_IORD_POL(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_IORD_POL(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_IORD_POL(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_IORD_POL(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_IORD_SU_TIM(r32)                 _BFGET_(r32, 8, 1)
    #define   SET32CIC_S1_PHY_IORD_SU_TIM(r32,v)               _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S1_PHY_IORD_SU_TIM(r16)                 _BFGET_(r16, 8, 1)
    #define   SET16CIC_S1_PHY_IORD_SU_TIM(r16,v)               _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S1_PHY_IORD_HO_TIM(r32)                 _BFGET_(r32,16, 9)
    #define   SET32CIC_S1_PHY_IORD_HO_TIM(r32,v)               _BFSET_(r32,16, 9,v)

    #define     w32CIC_S1_PHY_IORD                             {\
            UNSG32 uS1_PHY_IORD_POL                            :  1;\
            UNSG32 uS1_PHY_IORD_SU_TIM                         :  8;\
            UNSG32 uS1_PHY_IORD_HO_TIM                         :  8;\
            UNSG32 RSVDx90_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S1_PHY_IORD;
            struct w32CIC_S1_PHY_IORD;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_IOWR_POL(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32CIC_S0_PHY_IOWR_POL(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S0_PHY_IOWR_POL(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16CIC_S0_PHY_IOWR_POL(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S0_PHY_IOWR_SU_TIM(r32)                 _BFGET_(r32, 8, 1)
    #define   SET32CIC_S0_PHY_IOWR_SU_TIM(r32,v)               _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S0_PHY_IOWR_SU_TIM(r16)                 _BFGET_(r16, 8, 1)
    #define   SET16CIC_S0_PHY_IOWR_SU_TIM(r16,v)               _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S0_PHY_IOWR_HO_TIM(r32)                 _BFGET_(r32,16, 9)
    #define   SET32CIC_S0_PHY_IOWR_HO_TIM(r32,v)               _BFSET_(r32,16, 9,v)

    #define     w32CIC_S0_PHY_IOWR                             {\
            UNSG32 uS0_PHY_IOWR_POL                            :  1;\
            UNSG32 uS0_PHY_IOWR_SU_TIM                         :  8;\
            UNSG32 uS0_PHY_IOWR_HO_TIM                         :  8;\
            UNSG32 RSVDx94_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S0_PHY_IOWR;
            struct w32CIC_S0_PHY_IOWR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_IOWR_POL(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32CIC_S1_PHY_IOWR_POL(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_S1_PHY_IOWR_POL(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16CIC_S1_PHY_IOWR_POL(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_S1_PHY_IOWR_SU_TIM(r32)                 _BFGET_(r32, 8, 1)
    #define   SET32CIC_S1_PHY_IOWR_SU_TIM(r32,v)               _BFSET_(r32, 8, 1,v)
    #define   GET16CIC_S1_PHY_IOWR_SU_TIM(r16)                 _BFGET_(r16, 8, 1)
    #define   SET16CIC_S1_PHY_IOWR_SU_TIM(r16,v)               _BFSET_(r16, 8, 1,v)

    #define   GET32CIC_S1_PHY_IOWR_HO_TIM(r32)                 _BFGET_(r32,16, 9)
    #define   SET32CIC_S1_PHY_IOWR_HO_TIM(r32,v)               _BFSET_(r32,16, 9,v)

    #define     w32CIC_S1_PHY_IOWR                             {\
            UNSG32 uS1_PHY_IOWR_POL                            :  1;\
            UNSG32 uS1_PHY_IOWR_SU_TIM                         :  8;\
            UNSG32 uS1_PHY_IOWR_HO_TIM                         :  8;\
            UNSG32 RSVDx98_b17                                 : 15;\
          }
    union { UNSG32 u32CIC_S1_PHY_IOWR;
            struct w32CIC_S1_PHY_IOWR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_RD_DLAT_PHASE(r32)               _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_PHY_RD_DLAT_PHASE(r32,v)             _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_PHY_RD_DLAT_PHASE(r16)               _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_RD_DLAT_PHASE(r16,v)             _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_RD_DLAT_CYCLE(r32)               _BFGET_(r32,15, 8)
    #define   SET32CIC_S0_PHY_RD_DLAT_CYCLE(r32,v)             _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S0_PHY_RD_DLAT_CYCLE(r16)               _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_RD_DLAT_CYCLE(r16,v)             _BFSET_(r16,15, 8,v)

    #define     w32CIC_S0_PHY_RD_DLAT                          {\
            UNSG32 uS0_PHY_RD_DLAT_PHASE                       :  8;\
            UNSG32 uS0_PHY_RD_DLAT_CYCLE                       :  8;\
            UNSG32 RSVDx9C_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S0_PHY_RD_DLAT;
            struct w32CIC_S0_PHY_RD_DLAT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_RD_DLAT_PHASE(r32)               _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_PHY_RD_DLAT_PHASE(r32,v)             _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_PHY_RD_DLAT_PHASE(r16)               _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_RD_DLAT_PHASE(r16,v)             _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_RD_DLAT_CYCLE(r32)               _BFGET_(r32,15, 8)
    #define   SET32CIC_S1_PHY_RD_DLAT_CYCLE(r32,v)             _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S1_PHY_RD_DLAT_CYCLE(r16)               _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_RD_DLAT_CYCLE(r16,v)             _BFSET_(r16,15, 8,v)

    #define     w32CIC_S1_PHY_RD_DLAT                          {\
            UNSG32 uS1_PHY_RD_DLAT_PHASE                       :  8;\
            UNSG32 uS1_PHY_RD_DLAT_CYCLE                       :  8;\
            UNSG32 RSVDxA0_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S1_PHY_RD_DLAT;
            struct w32CIC_S1_PHY_RD_DLAT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_IOWR_DLAUNCH_PHASE(r32)          _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_PHY_IOWR_DLAUNCH_PHASE(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_PHY_IOWR_DLAUNCH_PHASE(r16)          _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_IOWR_DLAUNCH_PHASE(r16,v)        _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_IOWR_DLAUNCH_CYCLE(r32)          _BFGET_(r32,15, 8)
    #define   SET32CIC_S0_PHY_IOWR_DLAUNCH_CYCLE(r32,v)        _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S0_PHY_IOWR_DLAUNCH_CYCLE(r16)          _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_IOWR_DLAUNCH_CYCLE(r16,v)        _BFSET_(r16,15, 8,v)

    #define     w32CIC_S0_PHY_IOWR_DLAUNCH                     {\
            UNSG32 uS0_PHY_IOWR_DLAUNCH_PHASE                  :  8;\
            UNSG32 uS0_PHY_IOWR_DLAUNCH_CYCLE                  :  8;\
            UNSG32 RSVDxA4_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S0_PHY_IOWR_DLAUNCH;
            struct w32CIC_S0_PHY_IOWR_DLAUNCH;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_IOWR_DLAUNCH_PHASE(r32)          _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_PHY_IOWR_DLAUNCH_PHASE(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_PHY_IOWR_DLAUNCH_PHASE(r16)          _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_IOWR_DLAUNCH_PHASE(r16,v)        _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_IOWR_DLAUNCH_CYCLE(r32)          _BFGET_(r32,15, 8)
    #define   SET32CIC_S1_PHY_IOWR_DLAUNCH_CYCLE(r32,v)        _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S1_PHY_IOWR_DLAUNCH_CYCLE(r16)          _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_IOWR_DLAUNCH_CYCLE(r16,v)        _BFSET_(r16,15, 8,v)

    #define     w32CIC_S1_PHY_IOWR_DLAUNCH                     {\
            UNSG32 uS1_PHY_IOWR_DLAUNCH_PHASE                  :  8;\
            UNSG32 uS1_PHY_IOWR_DLAUNCH_CYCLE                  :  8;\
            UNSG32 RSVDxA8_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S1_PHY_IOWR_DLAUNCH;
            struct w32CIC_S1_PHY_IOWR_DLAUNCH;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_IOWR_DREMOVE_PHASE(r32)          _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_PHY_IOWR_DREMOVE_PHASE(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_PHY_IOWR_DREMOVE_PHASE(r16)          _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_IOWR_DREMOVE_PHASE(r16,v)        _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_IOWR_DREMOVE_CYCLE(r32)          _BFGET_(r32,15, 8)
    #define   SET32CIC_S0_PHY_IOWR_DREMOVE_CYCLE(r32,v)        _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S0_PHY_IOWR_DREMOVE_CYCLE(r16)          _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_IOWR_DREMOVE_CYCLE(r16,v)        _BFSET_(r16,15, 8,v)

    #define     w32CIC_S0_PHY_IOWR_DREMOVE                     {\
            UNSG32 uS0_PHY_IOWR_DREMOVE_PHASE                  :  8;\
            UNSG32 uS0_PHY_IOWR_DREMOVE_CYCLE                  :  8;\
            UNSG32 RSVDxAC_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S0_PHY_IOWR_DREMOVE;
            struct w32CIC_S0_PHY_IOWR_DREMOVE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_IOWR_DREMOVE_PHASE(r32)          _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_PHY_IOWR_DREMOVE_PHASE(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_PHY_IOWR_DREMOVE_PHASE(r16)          _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_IOWR_DREMOVE_PHASE(r16,v)        _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_IOWR_DREMOVE_CYCLE(r32)          _BFGET_(r32,15, 8)
    #define   SET32CIC_S1_PHY_IOWR_DREMOVE_CYCLE(r32,v)        _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S1_PHY_IOWR_DREMOVE_CYCLE(r16)          _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_IOWR_DREMOVE_CYCLE(r16,v)        _BFSET_(r16,15, 8,v)

    #define     w32CIC_S1_PHY_IOWR_DREMOVE                     {\
            UNSG32 uS1_PHY_IOWR_DREMOVE_PHASE                  :  8;\
            UNSG32 uS1_PHY_IOWR_DREMOVE_CYCLE                  :  8;\
            UNSG32 RSVDxB0_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S1_PHY_IOWR_DREMOVE;
            struct w32CIC_S1_PHY_IOWR_DREMOVE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_MEMW_DLAUNCH_PHASE(r32)          _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_PHY_MEMW_DLAUNCH_PHASE(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_PHY_MEMW_DLAUNCH_PHASE(r16)          _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_MEMW_DLAUNCH_PHASE(r16,v)        _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_MEMW_DLAUNCH_CYCLE(r32)          _BFGET_(r32,15, 8)
    #define   SET32CIC_S0_PHY_MEMW_DLAUNCH_CYCLE(r32,v)        _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S0_PHY_MEMW_DLAUNCH_CYCLE(r16)          _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_MEMW_DLAUNCH_CYCLE(r16,v)        _BFSET_(r16,15, 8,v)

    #define     w32CIC_S0_PHY_MEMW_DLAUNCH                     {\
            UNSG32 uS0_PHY_MEMW_DLAUNCH_PHASE                  :  8;\
            UNSG32 uS0_PHY_MEMW_DLAUNCH_CYCLE                  :  8;\
            UNSG32 RSVDxB4_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S0_PHY_MEMW_DLAUNCH;
            struct w32CIC_S0_PHY_MEMW_DLAUNCH;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_MEMW_DLAUNCH_PHASE(r32)          _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_PHY_MEMW_DLAUNCH_PHASE(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_PHY_MEMW_DLAUNCH_PHASE(r16)          _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_MEMW_DLAUNCH_PHASE(r16,v)        _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_MEMW_DLAUNCH_CYCLE(r32)          _BFGET_(r32,15, 8)
    #define   SET32CIC_S1_PHY_MEMW_DLAUNCH_CYCLE(r32,v)        _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S1_PHY_MEMW_DLAUNCH_CYCLE(r16)          _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_MEMW_DLAUNCH_CYCLE(r16,v)        _BFSET_(r16,15, 8,v)

    #define     w32CIC_S1_PHY_MEMW_DLAUNCH                     {\
            UNSG32 uS1_PHY_MEMW_DLAUNCH_PHASE                  :  8;\
            UNSG32 uS1_PHY_MEMW_DLAUNCH_CYCLE                  :  8;\
            UNSG32 RSVDxB8_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S1_PHY_MEMW_DLAUNCH;
            struct w32CIC_S1_PHY_MEMW_DLAUNCH;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_PHY_MEM_DREMOVE_PHASE(r32)           _BFGET_(r32, 7, 0)
    #define   SET32CIC_S0_PHY_MEM_DREMOVE_PHASE(r32,v)         _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S0_PHY_MEM_DREMOVE_PHASE(r16)           _BFGET_(r16, 7, 0)
    #define   SET16CIC_S0_PHY_MEM_DREMOVE_PHASE(r16,v)         _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S0_PHY_MEM_DREMOVE_CYCLE(r32)           _BFGET_(r32,15, 8)
    #define   SET32CIC_S0_PHY_MEM_DREMOVE_CYCLE(r32,v)         _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S0_PHY_MEM_DREMOVE_CYCLE(r16)           _BFGET_(r16,15, 8)
    #define   SET16CIC_S0_PHY_MEM_DREMOVE_CYCLE(r16,v)         _BFSET_(r16,15, 8,v)

    #define     w32CIC_S0_PHY_MEM_DREMOVE                      {\
            UNSG32 uS0_PHY_MEM_DREMOVE_PHASE                   :  8;\
            UNSG32 uS0_PHY_MEM_DREMOVE_CYCLE                   :  8;\
            UNSG32 RSVDxBC_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S0_PHY_MEM_DREMOVE;
            struct w32CIC_S0_PHY_MEM_DREMOVE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_PHY_MEM_DREMOVE_PHASE(r32)           _BFGET_(r32, 7, 0)
    #define   SET32CIC_S1_PHY_MEM_DREMOVE_PHASE(r32,v)         _BFSET_(r32, 7, 0,v)
    #define   GET16CIC_S1_PHY_MEM_DREMOVE_PHASE(r16)           _BFGET_(r16, 7, 0)
    #define   SET16CIC_S1_PHY_MEM_DREMOVE_PHASE(r16,v)         _BFSET_(r16, 7, 0,v)

    #define   GET32CIC_S1_PHY_MEM_DREMOVE_CYCLE(r32)           _BFGET_(r32,15, 8)
    #define   SET32CIC_S1_PHY_MEM_DREMOVE_CYCLE(r32,v)         _BFSET_(r32,15, 8,v)
    #define   GET16CIC_S1_PHY_MEM_DREMOVE_CYCLE(r16)           _BFGET_(r16,15, 8)
    #define   SET16CIC_S1_PHY_MEM_DREMOVE_CYCLE(r16,v)         _BFSET_(r16,15, 8,v)

    #define     w32CIC_S1_PHY_MEM_DREMOVE                      {\
            UNSG32 uS1_PHY_MEM_DREMOVE_PHASE                   :  8;\
            UNSG32 uS1_PHY_MEM_DREMOVE_CYCLE                   :  8;\
            UNSG32 RSVDxC0_b16                                 : 16;\
          }
    union { UNSG32 u32CIC_S1_PHY_MEM_DREMOVE;
            struct w32CIC_S1_PHY_MEM_DREMOVE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_TICK_US(r32)                            _BFGET_(r32, 9, 0)
    #define   SET32CIC_TICK_US(r32,v)                          _BFSET_(r32, 9, 0,v)
    #define   GET16CIC_TICK_US(r16)                            _BFGET_(r16, 9, 0)
    #define   SET16CIC_TICK_US(r16,v)                          _BFSET_(r16, 9, 0,v)

    #define   GET32CIC_TICK_MS(r32)                            _BFGET_(r32,19,10)
    #define   SET32CIC_TICK_MS(r32,v)                          _BFSET_(r32,19,10,v)

    #define   GET32CIC_TICK_SEC(r32)                           _BFGET_(r32,29,20)
    #define   SET32CIC_TICK_SEC(r32,v)                         _BFSET_(r32,29,20,v)
    #define   GET16CIC_TICK_SEC(r16)                           _BFGET_(r16,13, 4)
    #define   SET16CIC_TICK_SEC(r16,v)                         _BFSET_(r16,13, 4,v)

    #define     w32CIC_TICK                                    {\
            UNSG32 uTICK_US                                    : 10;\
            UNSG32 uTICK_MS                                    : 10;\
            UNSG32 uTICK_SEC                                   : 10;\
            UNSG32 RSVDxC4_b30                                 :  2;\
          }
    union { UNSG32 u32CIC_TICK;
            struct w32CIC_TICK;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_HS0_VS1_MON_TICK_SEL(r32)            _BFGET_(r32, 1, 0)
    #define   SET32CIC_S0_HS0_VS1_MON_TICK_SEL(r32,v)          _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_S0_HS0_VS1_MON_TICK_SEL(r16)            _BFGET_(r16, 1, 0)
    #define   SET16CIC_S0_HS0_VS1_MON_TICK_SEL(r16,v)          _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_S0_HS0_VS1_MON_TICK_CNT(r32)            _BFGET_(r32,11, 2)
    #define   SET32CIC_S0_HS0_VS1_MON_TICK_CNT(r32,v)          _BFSET_(r32,11, 2,v)
    #define   GET16CIC_S0_HS0_VS1_MON_TICK_CNT(r16)            _BFGET_(r16,11, 2)
    #define   SET16CIC_S0_HS0_VS1_MON_TICK_CNT(r16,v)          _BFSET_(r16,11, 2,v)

    #define   GET32CIC_S0_HS0_VCC_STABLE_TICK_SEL(r32)         _BFGET_(r32,13,12)
    #define   SET32CIC_S0_HS0_VCC_STABLE_TICK_SEL(r32,v)       _BFSET_(r32,13,12,v)
    #define   GET16CIC_S0_HS0_VCC_STABLE_TICK_SEL(r16)         _BFGET_(r16,13,12)
    #define   SET16CIC_S0_HS0_VCC_STABLE_TICK_SEL(r16,v)       _BFSET_(r16,13,12,v)

    #define   GET32CIC_S0_HS0_VCC_STABLE_TICK_CNT(r32)         _BFGET_(r32,23,14)
    #define   SET32CIC_S0_HS0_VCC_STABLE_TICK_CNT(r32,v)       _BFSET_(r32,23,14,v)

    #define     w32CIC_S0_HS0                                  {\
            UNSG32 uS0_HS0_VS1_MON_TICK_SEL                    :  2;\
            UNSG32 uS0_HS0_VS1_MON_TICK_CNT                    : 10;\
            UNSG32 uS0_HS0_VCC_STABLE_TICK_SEL                 :  2;\
            UNSG32 uS0_HS0_VCC_STABLE_TICK_CNT                 : 10;\
            UNSG32 RSVDxC8_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_S0_HS0;
            struct w32CIC_S0_HS0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_HS0_VS1_MON_TICK_SEL(r32)            _BFGET_(r32, 1, 0)
    #define   SET32CIC_S1_HS0_VS1_MON_TICK_SEL(r32,v)          _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_S1_HS0_VS1_MON_TICK_SEL(r16)            _BFGET_(r16, 1, 0)
    #define   SET16CIC_S1_HS0_VS1_MON_TICK_SEL(r16,v)          _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_S1_HS0_VS1_MON_TICK_CNT(r32)            _BFGET_(r32,11, 2)
    #define   SET32CIC_S1_HS0_VS1_MON_TICK_CNT(r32,v)          _BFSET_(r32,11, 2,v)
    #define   GET16CIC_S1_HS0_VS1_MON_TICK_CNT(r16)            _BFGET_(r16,11, 2)
    #define   SET16CIC_S1_HS0_VS1_MON_TICK_CNT(r16,v)          _BFSET_(r16,11, 2,v)

    #define   GET32CIC_S1_HS0_VCC_STABLE_TICK_SEL(r32)         _BFGET_(r32,13,12)
    #define   SET32CIC_S1_HS0_VCC_STABLE_TICK_SEL(r32,v)       _BFSET_(r32,13,12,v)
    #define   GET16CIC_S1_HS0_VCC_STABLE_TICK_SEL(r16)         _BFGET_(r16,13,12)
    #define   SET16CIC_S1_HS0_VCC_STABLE_TICK_SEL(r16,v)       _BFSET_(r16,13,12,v)

    #define   GET32CIC_S1_HS0_VCC_STABLE_TICK_CNT(r32)         _BFGET_(r32,23,14)
    #define   SET32CIC_S1_HS0_VCC_STABLE_TICK_CNT(r32,v)       _BFSET_(r32,23,14,v)

    #define     w32CIC_S1_HS0                                  {\
            UNSG32 uS1_HS0_VS1_MON_TICK_SEL                    :  2;\
            UNSG32 uS1_HS0_VS1_MON_TICK_CNT                    : 10;\
            UNSG32 uS1_HS0_VCC_STABLE_TICK_SEL                 :  2;\
            UNSG32 uS1_HS0_VCC_STABLE_TICK_CNT                 : 10;\
            UNSG32 RSVDxCC_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_S1_HS0;
            struct w32CIC_S1_HS0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_HS1_RST_HIGH_TICK_SEL(r32)           _BFGET_(r32, 1, 0)
    #define   SET32CIC_S0_HS1_RST_HIGH_TICK_SEL(r32,v)         _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_S0_HS1_RST_HIGH_TICK_SEL(r16)           _BFGET_(r16, 1, 0)
    #define   SET16CIC_S0_HS1_RST_HIGH_TICK_SEL(r16,v)         _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_S0_HS1_RST_HIGH_TICK_CNT(r32)           _BFGET_(r32,11, 2)
    #define   SET32CIC_S0_HS1_RST_HIGH_TICK_CNT(r32,v)         _BFSET_(r32,11, 2,v)
    #define   GET16CIC_S0_HS1_RST_HIGH_TICK_CNT(r16)           _BFGET_(r16,11, 2)
    #define   SET16CIC_S0_HS1_RST_HIGH_TICK_CNT(r16,v)         _BFSET_(r16,11, 2,v)

    #define   GET32CIC_S0_HS1_WAIT_READY_TICK_SEL(r32)         _BFGET_(r32,13,12)
    #define   SET32CIC_S0_HS1_WAIT_READY_TICK_SEL(r32,v)       _BFSET_(r32,13,12,v)
    #define   GET16CIC_S0_HS1_WAIT_READY_TICK_SEL(r16)         _BFGET_(r16,13,12)
    #define   SET16CIC_S0_HS1_WAIT_READY_TICK_SEL(r16,v)       _BFSET_(r16,13,12,v)

    #define   GET32CIC_S0_HS1_WAIT_READY_TICK_CNT(r32)         _BFGET_(r32,23,14)
    #define   SET32CIC_S0_HS1_WAIT_READY_TICK_CNT(r32,v)       _BFSET_(r32,23,14,v)

    #define     w32CIC_S0_HS1                                  {\
            UNSG32 uS0_HS1_RST_HIGH_TICK_SEL                   :  2;\
            UNSG32 uS0_HS1_RST_HIGH_TICK_CNT                   : 10;\
            UNSG32 uS0_HS1_WAIT_READY_TICK_SEL                 :  2;\
            UNSG32 uS0_HS1_WAIT_READY_TICK_CNT                 : 10;\
            UNSG32 RSVDxD0_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_S0_HS1;
            struct w32CIC_S0_HS1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_HS1_RST_HIGH_TICK_SEL(r32)           _BFGET_(r32, 1, 0)
    #define   SET32CIC_S1_HS1_RST_HIGH_TICK_SEL(r32,v)         _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_S1_HS1_RST_HIGH_TICK_SEL(r16)           _BFGET_(r16, 1, 0)
    #define   SET16CIC_S1_HS1_RST_HIGH_TICK_SEL(r16,v)         _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_S1_HS1_RST_HIGH_TICK_CNT(r32)           _BFGET_(r32,11, 2)
    #define   SET32CIC_S1_HS1_RST_HIGH_TICK_CNT(r32,v)         _BFSET_(r32,11, 2,v)
    #define   GET16CIC_S1_HS1_RST_HIGH_TICK_CNT(r16)           _BFGET_(r16,11, 2)
    #define   SET16CIC_S1_HS1_RST_HIGH_TICK_CNT(r16,v)         _BFSET_(r16,11, 2,v)

    #define   GET32CIC_S1_HS1_WAIT_READY_TICK_SEL(r32)         _BFGET_(r32,13,12)
    #define   SET32CIC_S1_HS1_WAIT_READY_TICK_SEL(r32,v)       _BFSET_(r32,13,12,v)
    #define   GET16CIC_S1_HS1_WAIT_READY_TICK_SEL(r16)         _BFGET_(r16,13,12)
    #define   SET16CIC_S1_HS1_WAIT_READY_TICK_SEL(r16,v)       _BFSET_(r16,13,12,v)

    #define   GET32CIC_S1_HS1_WAIT_READY_TICK_CNT(r32)         _BFGET_(r32,23,14)
    #define   SET32CIC_S1_HS1_WAIT_READY_TICK_CNT(r32,v)       _BFSET_(r32,23,14,v)

    #define     w32CIC_S1_HS1                                  {\
            UNSG32 uS1_HS1_RST_HIGH_TICK_SEL                   :  2;\
            UNSG32 uS1_HS1_RST_HIGH_TICK_CNT                   : 10;\
            UNSG32 uS1_HS1_WAIT_READY_TICK_SEL                 :  2;\
            UNSG32 uS1_HS1_WAIT_READY_TICK_CNT                 : 10;\
            UNSG32 RSVDxD4_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_S1_HS1;
            struct w32CIC_S1_HS1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S0_HS2_CE_HIGH_TICK_SEL(r32)            _BFGET_(r32, 1, 0)
    #define   SET32CIC_S0_HS2_CE_HIGH_TICK_SEL(r32,v)          _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_S0_HS2_CE_HIGH_TICK_SEL(r16)            _BFGET_(r16, 1, 0)
    #define   SET16CIC_S0_HS2_CE_HIGH_TICK_SEL(r16,v)          _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_S0_HS2_CE_HIGH_TICK_CNT(r32)            _BFGET_(r32,11, 2)
    #define   SET32CIC_S0_HS2_CE_HIGH_TICK_CNT(r32,v)          _BFSET_(r32,11, 2,v)
    #define   GET16CIC_S0_HS2_CE_HIGH_TICK_CNT(r16)            _BFGET_(r16,11, 2)
    #define   SET16CIC_S0_HS2_CE_HIGH_TICK_CNT(r16,v)          _BFSET_(r16,11, 2,v)

    #define   GET32CIC_S0_HS2_RST_Z_TICK_SEL(r32)              _BFGET_(r32,13,12)
    #define   SET32CIC_S0_HS2_RST_Z_TICK_SEL(r32,v)            _BFSET_(r32,13,12,v)
    #define   GET16CIC_S0_HS2_RST_Z_TICK_SEL(r16)              _BFGET_(r16,13,12)
    #define   SET16CIC_S0_HS2_RST_Z_TICK_SEL(r16,v)            _BFSET_(r16,13,12,v)

    #define   GET32CIC_S0_HS2_RST_Z_TICK_CNT(r32)              _BFGET_(r32,23,14)
    #define   SET32CIC_S0_HS2_RST_Z_TICK_CNT(r32,v)            _BFSET_(r32,23,14,v)

    #define     w32CIC_S0_HS2                                  {\
            UNSG32 uS0_HS2_CE_HIGH_TICK_SEL                    :  2;\
            UNSG32 uS0_HS2_CE_HIGH_TICK_CNT                    : 10;\
            UNSG32 uS0_HS2_RST_Z_TICK_SEL                      :  2;\
            UNSG32 uS0_HS2_RST_Z_TICK_CNT                      : 10;\
            UNSG32 RSVDxD8_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_S0_HS2;
            struct w32CIC_S0_HS2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_S1_HS2_CE_HIGH_TICK_SEL(r32)            _BFGET_(r32, 1, 0)
    #define   SET32CIC_S1_HS2_CE_HIGH_TICK_SEL(r32,v)          _BFSET_(r32, 1, 0,v)
    #define   GET16CIC_S1_HS2_CE_HIGH_TICK_SEL(r16)            _BFGET_(r16, 1, 0)
    #define   SET16CIC_S1_HS2_CE_HIGH_TICK_SEL(r16,v)          _BFSET_(r16, 1, 0,v)

    #define   GET32CIC_S1_HS2_CE_HIGH_TICK_CNT(r32)            _BFGET_(r32,11, 2)
    #define   SET32CIC_S1_HS2_CE_HIGH_TICK_CNT(r32,v)          _BFSET_(r32,11, 2,v)
    #define   GET16CIC_S1_HS2_CE_HIGH_TICK_CNT(r16)            _BFGET_(r16,11, 2)
    #define   SET16CIC_S1_HS2_CE_HIGH_TICK_CNT(r16,v)          _BFSET_(r16,11, 2,v)

    #define   GET32CIC_S1_HS2_RST_Z_TICK_SEL(r32)              _BFGET_(r32,13,12)
    #define   SET32CIC_S1_HS2_RST_Z_TICK_SEL(r32,v)            _BFSET_(r32,13,12,v)
    #define   GET16CIC_S1_HS2_RST_Z_TICK_SEL(r16)              _BFGET_(r16,13,12)
    #define   SET16CIC_S1_HS2_RST_Z_TICK_SEL(r16,v)            _BFSET_(r16,13,12,v)

    #define   GET32CIC_S1_HS2_RST_Z_TICK_CNT(r32)              _BFGET_(r32,23,14)
    #define   SET32CIC_S1_HS2_RST_Z_TICK_CNT(r32,v)            _BFSET_(r32,23,14,v)

    #define     w32CIC_S1_HS2                                  {\
            UNSG32 uS1_HS2_CE_HIGH_TICK_SEL                    :  2;\
            UNSG32 uS1_HS2_CE_HIGH_TICK_CNT                    : 10;\
            UNSG32 uS1_HS2_RST_Z_TICK_SEL                      :  2;\
            UNSG32 uS1_HS2_RST_Z_TICK_CNT                      : 10;\
            UNSG32 RSVDxDC_b24                                 :  8;\
          }
    union { UNSG32 u32CIC_S1_HS2;
            struct w32CIC_S1_HS2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CIC_CLK_CLKSWITCH(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32CIC_CLK_CLKSWITCH(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16CIC_CLK_CLKSWITCH(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16CIC_CLK_CLKSWITCH(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32CIC_CLK_CLKD3SWITCH(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32CIC_CLK_CLKD3SWITCH(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16CIC_CLK_CLKD3SWITCH(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16CIC_CLK_CLKD3SWITCH(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define   GET32CIC_CLK_CLKEN(r32)                          _BFGET_(r32, 2, 2)
    #define   SET32CIC_CLK_CLKEN(r32,v)                        _BFSET_(r32, 2, 2,v)
    #define   GET16CIC_CLK_CLKEN(r16)                          _BFGET_(r16, 2, 2)
    #define   SET16CIC_CLK_CLKEN(r16,v)                        _BFSET_(r16, 2, 2,v)

    #define   GET32CIC_CLK_CLKSEL(r32)                         _BFGET_(r32, 5, 3)
    #define   SET32CIC_CLK_CLKSEL(r32,v)                       _BFSET_(r32, 5, 3,v)
    #define   GET16CIC_CLK_CLKSEL(r16)                         _BFGET_(r16, 5, 3)
    #define   SET16CIC_CLK_CLKSEL(r16,v)                       _BFSET_(r16, 5, 3,v)

    #define     w32CIC_CLK                                     {\
            UNSG32 uCLK_CLKSWITCH                              :  1;\
            UNSG32 uCLK_CLKD3SWITCH                            :  1;\
            UNSG32 uCLK_CLKEN                                  :  1;\
            UNSG32 uCLK_CLKSEL                                 :  3;\
            UNSG32 RSVDxE0_b6                                  : 26;\
          }
    union { UNSG32 u32CIC_CLK;
            struct w32CIC_CLK;
          };
    ///////////////////////////////////////////////////////////
    } SIE_CIC;

    typedef union  T32CIC_CTRL
          { UNSG32 u32;
            struct w32CIC_CTRL;
                 } T32CIC_CTRL;
    typedef union  T32CIC_CMD
          { UNSG32 u32;
            struct w32CIC_CMD;
                 } T32CIC_CMD;
    typedef union  T32CIC_CTRL_OE0
          { UNSG32 u32;
            struct w32CIC_CTRL_OE0;
                 } T32CIC_CTRL_OE0;
    typedef union  T32CIC_CTRL_OE1
          { UNSG32 u32;
            struct w32CIC_CTRL_OE1;
                 } T32CIC_CTRL_OE1;
    typedef union  T32CIC_CTRL_OE2
          { UNSG32 u32;
            struct w32CIC_CTRL_OE2;
                 } T32CIC_CTRL_OE2;
    typedef union  T32CIC_S1_CAM_REG_OFFSET
          { UNSG32 u32;
            struct w32CIC_S1_CAM_REG_OFFSET;
                 } T32CIC_S1_CAM_REG_OFFSET;
    typedef union  T32CIC_STATUS
          { UNSG32 u32;
            struct w32CIC_STATUS;
                 } T32CIC_STATUS;
    typedef union  T32CIC_TX_BUF0_WIN
          { UNSG32 u32;
            struct w32CIC_TX_BUF0_WIN;
                 } T32CIC_TX_BUF0_WIN;
    typedef union  T32CIC_TX_BUF1_WIN
          { UNSG32 u32;
            struct w32CIC_TX_BUF1_WIN;
                 } T32CIC_TX_BUF1_WIN;
    typedef union  T32CIC_RX_BUF0_WIN
          { UNSG32 u32;
            struct w32CIC_RX_BUF0_WIN;
                 } T32CIC_RX_BUF0_WIN;
    typedef union  T32CIC_RX_BUF1_WIN
          { UNSG32 u32;
            struct w32CIC_RX_BUF1_WIN;
                 } T32CIC_RX_BUF1_WIN;
    typedef union  T32CIC_TX_BUF0_CFG
          { UNSG32 u32;
            struct w32CIC_TX_BUF0_CFG;
                 } T32CIC_TX_BUF0_CFG;
    typedef union  T32CIC_TX_BUF1_CFG
          { UNSG32 u32;
            struct w32CIC_TX_BUF1_CFG;
                 } T32CIC_TX_BUF1_CFG;
    typedef union  T32CIC_RX_BUF0_CFG
          { UNSG32 u32;
            struct w32CIC_RX_BUF0_CFG;
                 } T32CIC_RX_BUF0_CFG;
    typedef union  T32CIC_RX_BUF1_CFG
          { UNSG32 u32;
            struct w32CIC_RX_BUF1_CFG;
                 } T32CIC_RX_BUF1_CFG;
    typedef union  T32CIC_S0_SB_RD_DATA
          { UNSG32 u32;
            struct w32CIC_S0_SB_RD_DATA;
                 } T32CIC_S0_SB_RD_DATA;
    typedef union  T32CIC_S1_SB_RD_DATA
          { UNSG32 u32;
            struct w32CIC_S1_SB_RD_DATA;
                 } T32CIC_S1_SB_RD_DATA;
    typedef union  T32CIC_INT_STATUS
          { UNSG32 u32;
            struct w32CIC_INT_STATUS;
                 } T32CIC_INT_STATUS;
    typedef union  T32CIC_INT_MASK
          { UNSG32 u32;
            struct w32CIC_INT_MASK;
                 } T32CIC_INT_MASK;
    typedef union  T32CIC_INT_TRIG_POL
          { UNSG32 u32;
            struct w32CIC_INT_TRIG_POL;
                 } T32CIC_INT_TRIG_POL;
    typedef union  T32CIC_DA
          { UNSG32 u32;
            struct w32CIC_DA;
                 } T32CIC_DA;
    typedef union  T32CIC_HC_DLY
          { UNSG32 u32;
            struct w32CIC_HC_DLY;
                 } T32CIC_HC_DLY;
    typedef union  T32CIC_PHY_MIRROR_STAT
          { UNSG32 u32;
            struct w32CIC_PHY_MIRROR_STAT;
                 } T32CIC_PHY_MIRROR_STAT;
    typedef union  T32CIC_S0_PHY_PH_CYC
          { UNSG32 u32;
            struct w32CIC_S0_PHY_PH_CYC;
                 } T32CIC_S0_PHY_PH_CYC;
    typedef union  T32CIC_S1_PHY_PH_CYC
          { UNSG32 u32;
            struct w32CIC_S1_PHY_PH_CYC;
                 } T32CIC_S1_PHY_PH_CYC;
    typedef union  T32CIC_S0_PHY_WAIT
          { UNSG32 u32;
            struct w32CIC_S0_PHY_WAIT;
                 } T32CIC_S0_PHY_WAIT;
    typedef union  T32CIC_S1_PHY_WAIT
          { UNSG32 u32;
            struct w32CIC_S1_PHY_WAIT;
                 } T32CIC_S1_PHY_WAIT;
    typedef union  T32CIC_S0_PHY_REG
          { UNSG32 u32;
            struct w32CIC_S0_PHY_REG;
                 } T32CIC_S0_PHY_REG;
    typedef union  T32CIC_S1_PHY_REG
          { UNSG32 u32;
            struct w32CIC_S1_PHY_REG;
                 } T32CIC_S1_PHY_REG;
    typedef union  T32CIC_S0_PHY_CE
          { UNSG32 u32;
            struct w32CIC_S0_PHY_CE;
                 } T32CIC_S0_PHY_CE;
    typedef union  T32CIC_S1_PHY_CE
          { UNSG32 u32;
            struct w32CIC_S1_PHY_CE;
                 } T32CIC_S1_PHY_CE;
    typedef union  T32CIC_S0_PHY_OE
          { UNSG32 u32;
            struct w32CIC_S0_PHY_OE;
                 } T32CIC_S0_PHY_OE;
    typedef union  T32CIC_S1_PHY_OE
          { UNSG32 u32;
            struct w32CIC_S1_PHY_OE;
                 } T32CIC_S1_PHY_OE;
    typedef union  T32CIC_S0_PHY_WE
          { UNSG32 u32;
            struct w32CIC_S0_PHY_WE;
                 } T32CIC_S0_PHY_WE;
    typedef union  T32CIC_S1_PHY_WE
          { UNSG32 u32;
            struct w32CIC_S1_PHY_WE;
                 } T32CIC_S1_PHY_WE;
    typedef union  T32CIC_S0_PHY_IORD
          { UNSG32 u32;
            struct w32CIC_S0_PHY_IORD;
                 } T32CIC_S0_PHY_IORD;
    typedef union  T32CIC_S1_PHY_IORD
          { UNSG32 u32;
            struct w32CIC_S1_PHY_IORD;
                 } T32CIC_S1_PHY_IORD;
    typedef union  T32CIC_S0_PHY_IOWR
          { UNSG32 u32;
            struct w32CIC_S0_PHY_IOWR;
                 } T32CIC_S0_PHY_IOWR;
    typedef union  T32CIC_S1_PHY_IOWR
          { UNSG32 u32;
            struct w32CIC_S1_PHY_IOWR;
                 } T32CIC_S1_PHY_IOWR;
    typedef union  T32CIC_S0_PHY_RD_DLAT
          { UNSG32 u32;
            struct w32CIC_S0_PHY_RD_DLAT;
                 } T32CIC_S0_PHY_RD_DLAT;
    typedef union  T32CIC_S1_PHY_RD_DLAT
          { UNSG32 u32;
            struct w32CIC_S1_PHY_RD_DLAT;
                 } T32CIC_S1_PHY_RD_DLAT;
    typedef union  T32CIC_S0_PHY_IOWR_DLAUNCH
          { UNSG32 u32;
            struct w32CIC_S0_PHY_IOWR_DLAUNCH;
                 } T32CIC_S0_PHY_IOWR_DLAUNCH;
    typedef union  T32CIC_S1_PHY_IOWR_DLAUNCH
          { UNSG32 u32;
            struct w32CIC_S1_PHY_IOWR_DLAUNCH;
                 } T32CIC_S1_PHY_IOWR_DLAUNCH;
    typedef union  T32CIC_S0_PHY_IOWR_DREMOVE
          { UNSG32 u32;
            struct w32CIC_S0_PHY_IOWR_DREMOVE;
                 } T32CIC_S0_PHY_IOWR_DREMOVE;
    typedef union  T32CIC_S1_PHY_IOWR_DREMOVE
          { UNSG32 u32;
            struct w32CIC_S1_PHY_IOWR_DREMOVE;
                 } T32CIC_S1_PHY_IOWR_DREMOVE;
    typedef union  T32CIC_S0_PHY_MEMW_DLAUNCH
          { UNSG32 u32;
            struct w32CIC_S0_PHY_MEMW_DLAUNCH;
                 } T32CIC_S0_PHY_MEMW_DLAUNCH;
    typedef union  T32CIC_S1_PHY_MEMW_DLAUNCH
          { UNSG32 u32;
            struct w32CIC_S1_PHY_MEMW_DLAUNCH;
                 } T32CIC_S1_PHY_MEMW_DLAUNCH;
    typedef union  T32CIC_S0_PHY_MEM_DREMOVE
          { UNSG32 u32;
            struct w32CIC_S0_PHY_MEM_DREMOVE;
                 } T32CIC_S0_PHY_MEM_DREMOVE;
    typedef union  T32CIC_S1_PHY_MEM_DREMOVE
          { UNSG32 u32;
            struct w32CIC_S1_PHY_MEM_DREMOVE;
                 } T32CIC_S1_PHY_MEM_DREMOVE;
    typedef union  T32CIC_TICK
          { UNSG32 u32;
            struct w32CIC_TICK;
                 } T32CIC_TICK;
    typedef union  T32CIC_S0_HS0
          { UNSG32 u32;
            struct w32CIC_S0_HS0;
                 } T32CIC_S0_HS0;
    typedef union  T32CIC_S1_HS0
          { UNSG32 u32;
            struct w32CIC_S1_HS0;
                 } T32CIC_S1_HS0;
    typedef union  T32CIC_S0_HS1
          { UNSG32 u32;
            struct w32CIC_S0_HS1;
                 } T32CIC_S0_HS1;
    typedef union  T32CIC_S1_HS1
          { UNSG32 u32;
            struct w32CIC_S1_HS1;
                 } T32CIC_S1_HS1;
    typedef union  T32CIC_S0_HS2
          { UNSG32 u32;
            struct w32CIC_S0_HS2;
                 } T32CIC_S0_HS2;
    typedef union  T32CIC_S1_HS2
          { UNSG32 u32;
            struct w32CIC_S1_HS2;
                 } T32CIC_S1_HS2;
    typedef union  T32CIC_CLK
          { UNSG32 u32;
            struct w32CIC_CLK;
                 } T32CIC_CLK;
    ///////////////////////////////////////////////////////////

    typedef union  TCIC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32CIC_CTRL;
                   };
                 } TCIC_CTRL;
    typedef union  TCIC_CMD
          { UNSG32 u32[1];
            struct {
            struct w32CIC_CMD;
                   };
                 } TCIC_CMD;
    typedef union  TCIC_CTRL_OE0
          { UNSG32 u32[1];
            struct {
            struct w32CIC_CTRL_OE0;
                   };
                 } TCIC_CTRL_OE0;
    typedef union  TCIC_CTRL_OE1
          { UNSG32 u32[1];
            struct {
            struct w32CIC_CTRL_OE1;
                   };
                 } TCIC_CTRL_OE1;
    typedef union  TCIC_CTRL_OE2
          { UNSG32 u32[1];
            struct {
            struct w32CIC_CTRL_OE2;
                   };
                 } TCIC_CTRL_OE2;
    typedef union  TCIC_S1_CAM_REG_OFFSET
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_CAM_REG_OFFSET;
                   };
                 } TCIC_S1_CAM_REG_OFFSET;
    typedef union  TCIC_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32CIC_STATUS;
                   };
                 } TCIC_STATUS;
    typedef union  TCIC_TX_BUF0_WIN
          { UNSG32 u32[1];
            struct {
            struct w32CIC_TX_BUF0_WIN;
                   };
                 } TCIC_TX_BUF0_WIN;
    typedef union  TCIC_TX_BUF1_WIN
          { UNSG32 u32[1];
            struct {
            struct w32CIC_TX_BUF1_WIN;
                   };
                 } TCIC_TX_BUF1_WIN;
    typedef union  TCIC_RX_BUF0_WIN
          { UNSG32 u32[1];
            struct {
            struct w32CIC_RX_BUF0_WIN;
                   };
                 } TCIC_RX_BUF0_WIN;
    typedef union  TCIC_RX_BUF1_WIN
          { UNSG32 u32[1];
            struct {
            struct w32CIC_RX_BUF1_WIN;
                   };
                 } TCIC_RX_BUF1_WIN;
    typedef union  TCIC_TX_BUF0_CFG
          { UNSG32 u32[1];
            struct {
            struct w32CIC_TX_BUF0_CFG;
                   };
                 } TCIC_TX_BUF0_CFG;
    typedef union  TCIC_TX_BUF1_CFG
          { UNSG32 u32[1];
            struct {
            struct w32CIC_TX_BUF1_CFG;
                   };
                 } TCIC_TX_BUF1_CFG;
    typedef union  TCIC_RX_BUF0_CFG
          { UNSG32 u32[1];
            struct {
            struct w32CIC_RX_BUF0_CFG;
                   };
                 } TCIC_RX_BUF0_CFG;
    typedef union  TCIC_RX_BUF1_CFG
          { UNSG32 u32[1];
            struct {
            struct w32CIC_RX_BUF1_CFG;
                   };
                 } TCIC_RX_BUF1_CFG;
    typedef union  TCIC_S0_SB_RD_DATA
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_SB_RD_DATA;
                   };
                 } TCIC_S0_SB_RD_DATA;
    typedef union  TCIC_S1_SB_RD_DATA
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_SB_RD_DATA;
                   };
                 } TCIC_S1_SB_RD_DATA;
    typedef union  TCIC_INT_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32CIC_INT_STATUS;
                   };
                 } TCIC_INT_STATUS;
    typedef union  TCIC_INT_MASK
          { UNSG32 u32[1];
            struct {
            struct w32CIC_INT_MASK;
                   };
                 } TCIC_INT_MASK;
    typedef union  TCIC_INT_TRIG_POL
          { UNSG32 u32[1];
            struct {
            struct w32CIC_INT_TRIG_POL;
                   };
                 } TCIC_INT_TRIG_POL;
    typedef union  TCIC_DA
          { UNSG32 u32[1];
            struct {
            struct w32CIC_DA;
                   };
                 } TCIC_DA;
    typedef union  TCIC_HC_DLY
          { UNSG32 u32[1];
            struct {
            struct w32CIC_HC_DLY;
                   };
                 } TCIC_HC_DLY;
    typedef union  TCIC_PHY_MIRROR_STAT
          { UNSG32 u32[1];
            struct {
            struct w32CIC_PHY_MIRROR_STAT;
                   };
                 } TCIC_PHY_MIRROR_STAT;
    typedef union  TCIC_S0_PHY_PH_CYC
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_PH_CYC;
                   };
                 } TCIC_S0_PHY_PH_CYC;
    typedef union  TCIC_S1_PHY_PH_CYC
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_PH_CYC;
                   };
                 } TCIC_S1_PHY_PH_CYC;
    typedef union  TCIC_S0_PHY_WAIT
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_WAIT;
                   };
                 } TCIC_S0_PHY_WAIT;
    typedef union  TCIC_S1_PHY_WAIT
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_WAIT;
                   };
                 } TCIC_S1_PHY_WAIT;
    typedef union  TCIC_S0_PHY_REG
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_REG;
                   };
                 } TCIC_S0_PHY_REG;
    typedef union  TCIC_S1_PHY_REG
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_REG;
                   };
                 } TCIC_S1_PHY_REG;
    typedef union  TCIC_S0_PHY_CE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_CE;
                   };
                 } TCIC_S0_PHY_CE;
    typedef union  TCIC_S1_PHY_CE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_CE;
                   };
                 } TCIC_S1_PHY_CE;
    typedef union  TCIC_S0_PHY_OE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_OE;
                   };
                 } TCIC_S0_PHY_OE;
    typedef union  TCIC_S1_PHY_OE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_OE;
                   };
                 } TCIC_S1_PHY_OE;
    typedef union  TCIC_S0_PHY_WE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_WE;
                   };
                 } TCIC_S0_PHY_WE;
    typedef union  TCIC_S1_PHY_WE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_WE;
                   };
                 } TCIC_S1_PHY_WE;
    typedef union  TCIC_S0_PHY_IORD
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_IORD;
                   };
                 } TCIC_S0_PHY_IORD;
    typedef union  TCIC_S1_PHY_IORD
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_IORD;
                   };
                 } TCIC_S1_PHY_IORD;
    typedef union  TCIC_S0_PHY_IOWR
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_IOWR;
                   };
                 } TCIC_S0_PHY_IOWR;
    typedef union  TCIC_S1_PHY_IOWR
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_IOWR;
                   };
                 } TCIC_S1_PHY_IOWR;
    typedef union  TCIC_S0_PHY_RD_DLAT
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_RD_DLAT;
                   };
                 } TCIC_S0_PHY_RD_DLAT;
    typedef union  TCIC_S1_PHY_RD_DLAT
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_RD_DLAT;
                   };
                 } TCIC_S1_PHY_RD_DLAT;
    typedef union  TCIC_S0_PHY_IOWR_DLAUNCH
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_IOWR_DLAUNCH;
                   };
                 } TCIC_S0_PHY_IOWR_DLAUNCH;
    typedef union  TCIC_S1_PHY_IOWR_DLAUNCH
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_IOWR_DLAUNCH;
                   };
                 } TCIC_S1_PHY_IOWR_DLAUNCH;
    typedef union  TCIC_S0_PHY_IOWR_DREMOVE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_IOWR_DREMOVE;
                   };
                 } TCIC_S0_PHY_IOWR_DREMOVE;
    typedef union  TCIC_S1_PHY_IOWR_DREMOVE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_IOWR_DREMOVE;
                   };
                 } TCIC_S1_PHY_IOWR_DREMOVE;
    typedef union  TCIC_S0_PHY_MEMW_DLAUNCH
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_MEMW_DLAUNCH;
                   };
                 } TCIC_S0_PHY_MEMW_DLAUNCH;
    typedef union  TCIC_S1_PHY_MEMW_DLAUNCH
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_MEMW_DLAUNCH;
                   };
                 } TCIC_S1_PHY_MEMW_DLAUNCH;
    typedef union  TCIC_S0_PHY_MEM_DREMOVE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_PHY_MEM_DREMOVE;
                   };
                 } TCIC_S0_PHY_MEM_DREMOVE;
    typedef union  TCIC_S1_PHY_MEM_DREMOVE
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_PHY_MEM_DREMOVE;
                   };
                 } TCIC_S1_PHY_MEM_DREMOVE;
    typedef union  TCIC_TICK
          { UNSG32 u32[1];
            struct {
            struct w32CIC_TICK;
                   };
                 } TCIC_TICK;
    typedef union  TCIC_S0_HS0
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_HS0;
                   };
                 } TCIC_S0_HS0;
    typedef union  TCIC_S1_HS0
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_HS0;
                   };
                 } TCIC_S1_HS0;
    typedef union  TCIC_S0_HS1
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_HS1;
                   };
                 } TCIC_S0_HS1;
    typedef union  TCIC_S1_HS1
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_HS1;
                   };
                 } TCIC_S1_HS1;
    typedef union  TCIC_S0_HS2
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S0_HS2;
                   };
                 } TCIC_S0_HS2;
    typedef union  TCIC_S1_HS2
          { UNSG32 u32[1];
            struct {
            struct w32CIC_S1_HS2;
                   };
                 } TCIC_S1_HS2;
    typedef union  TCIC_CLK
          { UNSG32 u32[1];
            struct {
            struct w32CIC_CLK;
                   };
                 } TCIC_CLK;

    ///////////////////////////////////////////////////////////
     SIGN32 CIC_drvrd(SIE_CIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CIC_drvwr(SIE_CIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CIC_reset(SIE_CIC *p);
     SIGN32 CIC_cmp  (SIE_CIC *p, SIE_CIC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CIC_check(p,pie,pfx,hLOG) CIC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CIC_print(p,    pfx,hLOG) CIC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CIC
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: cic.h
////////////////////////////////////////////////////////////