/*
 * Copyright (C) 2018 Synaptics Incorporated. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND
 * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES,
 * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY
 * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR
 * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND
 * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF
 * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT
 * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY
 * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS.
 */
#ifndef _DIAG_GIC_
#define _DIAG_GIC_

#include "soc.h"        // include for interrupt id


// MPCore GIC interrupt IDs
#define MP_BERLIN_INTR_ID(id)   (id + 32)   // berlin interrupts starts from ID 32

// name mapping
#define   IRQ_CTIIRQ0                         IRQ_cpu_wrap_U0__CTIIRQ0
#define   IRQ_CTIIRQ1                         IRQ_cpu_wrap_U0__CTIIRQ1
#define   IRQ_CTIIRQ2                         IRQ_cpu_wrap_U0__CTIIRQ2
#define   IRQ_CTIIRQ3                         IRQ_cpu_wrap_U0__CTIIRQ3
#define   IRQ_nPMUIRQ0                        IRQ_cpu_wrap_U0__nPMUIRQ0
#define   IRQ_nPMUIRQ1                        IRQ_cpu_wrap_U0__nPMUIRQ1
#define   IRQ_nPMUIRQ2                        IRQ_cpu_wrap_U0__nPMUIRQ2
#define   IRQ_nPMUIRQ3                        IRQ_cpu_wrap_U0__nPMUIRQ3
#define   IRQ_intrAhbTrc                      IRQ_u_AhbTrc__IntOut
#define   IRQ_AxiErrMonIntr                   IRQ_mc6_U0__MC6AxiErrMonIntr
#define   IRQ_nETRERRIRQ                      IRQ_cpu_wrap_U0__nEXTERRIRQ
#define   IRQ_dHubIntrAvio0                   IRQ_AIO_top_U0__dHubIntrAvio0
#define   IRQ_dHubIntrAvio1                   IRQ_AIO_top_U0__dHubIntrAvio1
#define   IRQ_dHubIntrAvio2                   IRQ_AIO_top_U0__dHubIntrAvio2
#define   IRQ_tsSSIntr                        IRQ_tsSS_BiuCfg_U0__tsSSIntr
#define   IRQ_bcmIntr                         IRQ_bcm_top_U0__bcm_hst_int_out
#define   IRQ_nocsIntr                        IRQ_CA_wrapper_U0__nocs3Intr
#define   IRQ_wdtIntr                         IRQ_tsSS__wdtIntr
#define   IRQ_kilopassIntr                    IRQ_KilopassOTP_wrapper_U0__KilopassIntr
#define   IRQ_usb0Intr                        IRQ_u_DWC_otg__interrupt
#define   IRQ_nanfIntr                        IRQ_cdns_hpnfc_U0__interrupt
#define   IRQ_emmc_int                        IRQ_u_emmcCore__intr
#define   IRQ_sdio_interrupt                  IRQ_u_sdioCore__intr
#define   IRQ_intrPb0                         IRQ_pBridge0__intrPb0
#define   IRQ_intrPb1                         IRQ_pBridge0__intrPb1
#define   IRQ_intrPb2                         IRQ_pBridge0__intrPb2
#define   IRQ_pexCfgAerRcErrIntr              IRQ_u_DWC_pcie_rc__cfg_aer_rc_err_int
#define   IRQ_pexCfgPmeIntr                   IRQ_u_DWC_pcie_rc__cfg_pme_int
#define   IRQ_pexMsiIntr                      IRQ_u_DWC_pcie_rc__msi_ctrl_int
#define   IRQ_pcie_l2_exit_intr               IRQ_pcie_top_U0__pcie_l2_exit_intr
#define   IRQ_pexHpIntr                       IRQ_u_DWC_pcie_rc__hp_int
#define   IRQ_pexMacIntr                      IRQ_pcie_top_U0__pexMacIntr
#define   IRQ_pcie_smlhreq_rst_intr           IRQ_pcie_top_U0__pcie_smlhreq_rst_intr
#define   IRQ_pexCfgAerRcErrIntr1             IRQ_u_DWC_pcie1_rc__cfg_aer_rc_err_int
#define   IRQ_pexCfgPmeIntr1                  IRQ_u_DWC_pcie1_rc__cfg_pme_int
#define   IRQ_pexMsiIntr1                     IRQ_u_DWC_pcie1_rc__msi_ctrl_int
#define   IRQ_pcie_l2_exit_intr1              IRQ_pcie_top_U1__pcie_l2_exit_intr
#define   IRQ_pexHpIntr1                      IRQ_u_DWC_pcie1_rc__hp_int
#define   IRQ_pexMacIntr1                     IRQ_pcie_top_U1__pexMacIntr
#define   IRQ_pcie_smlhreq_rst_intr1          IRQ_pcie_top_U1__pcie_smlhreq_rst_intr
#define   IRQ_apbPerif_gpio_0_Intr_irq        IRQ_u_apbPerif__ex_i_gpio_0_Intr_irq
#define   IRQ_apbPerif_gpio_1_Intr_irq        IRQ_u_apbPerif__ex_i_gpio_1_Intr_irq
#define   IRQ_apbPerif_i2c_0_Intr_irq         IRQ_u_apbPerif__ex_i_i2c_0_Intr_irq
#define   IRQ_apbPerif_i2c_1_Intr_irq         IRQ_u_apbPerif__ex_i_i2c_1_Intr_irq
#define   IRQ_apbPerif_ssi_Intr_irq           IRQ_u_apbPerif__ex_i_ssi_Intr_irq
#define   IRQ_apbPerif_wdt_0_Intr_irq         IRQ_u_apbPerif__ex_i_wdt_0_Intr_irq
#define   IRQ_apbPerif_wdt_1_Intr_irq         IRQ_u_apbPerif__ex_i_wdt_1_Intr_irq
#define   IRQ_apbPerif_wdt_2_Intr_irq         IRQ_u_apbPerif__ex_i_wdt_2_Intr_irq
#define   IRQ_apbPerif_timers_0_Intr0_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr0_irq
#define   IRQ_apbPerif_timers_0_Intr1_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr1_irq
#define   IRQ_apbPerif_timers_0_Intr2_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr2_irq
#define   IRQ_apbPerif_timers_0_Intr3_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr3_irq
#define   IRQ_apbPerif_timers_1_Intr0_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr0_irq
#define   IRQ_apbPerif_timers_1_Intr1_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr1_irq
#define   IRQ_apbPerif_timers_1_Intr2_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr2_irq
#define   IRQ_apbPerif_timers_1_Intr3_irq     IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr3_irq
#define   IRQ_apbPerif_uart_0_Intr_irq        IRQ_u_apbPerif__ex_i_apbPerif_uart_0_Intr_irq
#define   IRQ_apbPerif_uart_1_Intr_irq        IRQ_u_apbPerif__ex_i_apbPerif_uart_1_Intr_irq
#define   IRQ_dummy_sw_Intr0                  IRQ_soc_U0__dummySwIntr0
#define   IRQ_dummy_sw_Intr1                  IRQ_soc_U0__dummySwIntr1
#define   IRQ_dummy_sw_Intr2                  IRQ_soc_U0__dummySwIntr2
#define   IRQ_dummy_sw_Intr3                  IRQ_soc_U0__dummySwIntr3
#define   IRQ_dummy_sw_Intr4                  IRQ_soc_U0__dummySwIntr4
#define   IRQ_dummy_sw_Intr5                  IRQ_soc_U0__dummySwIntr5
#define   IRQ_dummy_sw_Intr6                  IRQ_soc_U0__dummySwIntr6
#define   IRQ_dummy_sw_Intr7                  IRQ_soc_U0__dummySwIntr7
#define   IRQ_nna_Intr                        IRQ_VIVANTE_GPU_U0__xaq2_intr
#define   IRQ_saradc_Intr                     IRQ_u_saradc_wrap__intr
#define   IRQ_ABBGEN_Intr                     IRQ_ABBGEN_U0__o_intr


#endif // _DIAG_GIC_