//////
/// don't edit! auto-generated by docc: MC6Ctrl.h
////////////////////////////////////////////////////////////
#ifndef MC6Ctrl_h
#define MC6Ctrl_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE vsipll                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * PLL Control register
///               ###
///               %unsigned 1  PD                        0x0
///                                    ###
///                                    * PLL Power Down Signal.
///                                    * 1: PLL power down;
///                                    * 0: normal operation
///                                    ###
///               %unsigned 1  RESETN                    0x1
///                                    ###
///                                    * Resets the SSC & Fraction Function When Low
///                                    ###
///               %unsigned 6  DM                        0x1
///                                    ###
///                                    * Reference Input Divider Control Pins. Set the reference divider factor from 1 to 63
///                                    ###
///               %unsigned 11 DN                        0x20
///                                    ###
///                                    * Feedback Divider Control Pins. Set the feedback divider factor from 16 to 2048
///                                    ###
///               %unsigned 2  MODE                      0x0
///                                    ###
///                                    * Operation Mode Select
///                                    * 00: integer mode;
///                                    * 01: fraction mode;
///                                    * 10: spread spectrum mode;
///                                    * 11: reserved.
///                                    ###
///               %unsigned 1  READY_BP                  0x0
///                                    ###
///                                    * READY_bypass signal
///                                    * 0:FRAC_READY work normal
///                                    * 1:directly bypass FRAC<23:0> to PLL
///                                    ###
///               %unsigned 1  FRAC_READY                0x1
///                                    ###
///                                    * FRAC value ready flag.
///                                    ###
///               %%        9          # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 24 FRAC                      0x0
///                                    ###
///                                    * Fractional Portion of DN Value
///                                    ###
///               %%        8          # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 11 SSRATE                    0x0
///                                    ###
///                                    * Spreading Frequency Control. Set the triangle modulation frequency.
///                                    ###
///               %%        21         # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 24 SLOPE                     0x0
///                                    ###
///                                    * Spreading Slope Control.
///                                    ###
///               %unsigned 1  PDDP                      0x0
///                                    ###
///                                    * DP Power Down Signal. (0.8V signal)
///                                    * 1: DP power down;
///                                    * 0: DP normal operation
///                                    ###
///               %unsigned 3  DP                        0x4
///                                    ###
///                                    * Output Divider1 Control Pins. Set the post divider factor from 1 to 7
///                                    ###
///               %unsigned 1  PDDP1                     0x0
///                                    ###
///                                    * DP1 Power Down Signal. (0.8V signal)
///                                    * 1: DP1 power down;
///                                    * 0: DP1 normal operation
///                                    ###
///               %unsigned 3  DP1                       0x4
///                                    ###
///                                    * Output Divider1 Control Pins. Set the post divider factor from 1 to 7
///                                    ###
///     # 0x00010 ctrl4                
///               %unsigned 1  BYPASS                    0x0
///                                    ###
///                                    * PLL BYPASS Signal
///                                    * 1: PLL bypass
///                                    * 0: normal operation
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00014 status               (R-)
///               ###
///               * PLL status register
///               ###
///               %unsigned 1  LOCK                      
///                                    ###
///                                    * Output. Lock detection
///                                    ###
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:      92b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vsipll
#define h_vsipll (){}

    #define     RA_vsipll_ctrl                                 0x0000

    #define     BA_vsipll_ctrl_PD                              0x0000
    #define     B16vsipll_ctrl_PD                              0x0000
    #define   LSb32vsipll_ctrl_PD                                 0
    #define   LSb16vsipll_ctrl_PD                                 0
    #define       bvsipll_ctrl_PD                              1
    #define   MSK32vsipll_ctrl_PD                                 0x00000001

    #define     BA_vsipll_ctrl_RESETN                          0x0000
    #define     B16vsipll_ctrl_RESETN                          0x0000
    #define   LSb32vsipll_ctrl_RESETN                             1
    #define   LSb16vsipll_ctrl_RESETN                             1
    #define       bvsipll_ctrl_RESETN                          1
    #define   MSK32vsipll_ctrl_RESETN                             0x00000002

    #define     BA_vsipll_ctrl_DM                              0x0000
    #define     B16vsipll_ctrl_DM                              0x0000
    #define   LSb32vsipll_ctrl_DM                                 2
    #define   LSb16vsipll_ctrl_DM                                 2
    #define       bvsipll_ctrl_DM                              6
    #define   MSK32vsipll_ctrl_DM                                 0x000000FC

    #define     BA_vsipll_ctrl_DN                              0x0001
    #define     B16vsipll_ctrl_DN                              0x0000
    #define   LSb32vsipll_ctrl_DN                                 8
    #define   LSb16vsipll_ctrl_DN                                 8
    #define       bvsipll_ctrl_DN                              11
    #define   MSK32vsipll_ctrl_DN                                 0x0007FF00

    #define     BA_vsipll_ctrl_MODE                            0x0002
    #define     B16vsipll_ctrl_MODE                            0x0002
    #define   LSb32vsipll_ctrl_MODE                               19
    #define   LSb16vsipll_ctrl_MODE                               3
    #define       bvsipll_ctrl_MODE                            2
    #define   MSK32vsipll_ctrl_MODE                               0x00180000

    #define     BA_vsipll_ctrl_READY_BP                        0x0002
    #define     B16vsipll_ctrl_READY_BP                        0x0002
    #define   LSb32vsipll_ctrl_READY_BP                           21
    #define   LSb16vsipll_ctrl_READY_BP                           5
    #define       bvsipll_ctrl_READY_BP                        1
    #define   MSK32vsipll_ctrl_READY_BP                           0x00200000

    #define     BA_vsipll_ctrl_FRAC_READY                      0x0002
    #define     B16vsipll_ctrl_FRAC_READY                      0x0002
    #define   LSb32vsipll_ctrl_FRAC_READY                         22
    #define   LSb16vsipll_ctrl_FRAC_READY                         6
    #define       bvsipll_ctrl_FRAC_READY                      1
    #define   MSK32vsipll_ctrl_FRAC_READY                         0x00400000

    #define     RA_vsipll_ctrl1                                0x0004

    #define     BA_vsipll_ctrl_FRAC                            0x0004
    #define     B16vsipll_ctrl_FRAC                            0x0004
    #define   LSb32vsipll_ctrl_FRAC                               0
    #define   LSb16vsipll_ctrl_FRAC                               0
    #define       bvsipll_ctrl_FRAC                            24
    #define   MSK32vsipll_ctrl_FRAC                               0x00FFFFFF

    #define     RA_vsipll_ctrl2                                0x0008

    #define     BA_vsipll_ctrl_SSRATE                          0x0008
    #define     B16vsipll_ctrl_SSRATE                          0x0008
    #define   LSb32vsipll_ctrl_SSRATE                             0
    #define   LSb16vsipll_ctrl_SSRATE                             0
    #define       bvsipll_ctrl_SSRATE                          11
    #define   MSK32vsipll_ctrl_SSRATE                             0x000007FF

    #define     RA_vsipll_ctrl3                                0x000C

    #define     BA_vsipll_ctrl_SLOPE                           0x000C
    #define     B16vsipll_ctrl_SLOPE                           0x000C
    #define   LSb32vsipll_ctrl_SLOPE                              0
    #define   LSb16vsipll_ctrl_SLOPE                              0
    #define       bvsipll_ctrl_SLOPE                           24
    #define   MSK32vsipll_ctrl_SLOPE                              0x00FFFFFF

    #define     BA_vsipll_ctrl_PDDP                            0x000F
    #define     B16vsipll_ctrl_PDDP                            0x000E
    #define   LSb32vsipll_ctrl_PDDP                               24
    #define   LSb16vsipll_ctrl_PDDP                               8
    #define       bvsipll_ctrl_PDDP                            1
    #define   MSK32vsipll_ctrl_PDDP                               0x01000000

    #define     BA_vsipll_ctrl_DP                              0x000F
    #define     B16vsipll_ctrl_DP                              0x000E
    #define   LSb32vsipll_ctrl_DP                                 25
    #define   LSb16vsipll_ctrl_DP                                 9
    #define       bvsipll_ctrl_DP                              3
    #define   MSK32vsipll_ctrl_DP                                 0x0E000000

    #define     BA_vsipll_ctrl_PDDP1                           0x000F
    #define     B16vsipll_ctrl_PDDP1                           0x000E
    #define   LSb32vsipll_ctrl_PDDP1                              28
    #define   LSb16vsipll_ctrl_PDDP1                              12
    #define       bvsipll_ctrl_PDDP1                           1
    #define   MSK32vsipll_ctrl_PDDP1                              0x10000000

    #define     BA_vsipll_ctrl_DP1                             0x000F
    #define     B16vsipll_ctrl_DP1                             0x000E
    #define   LSb32vsipll_ctrl_DP1                                29
    #define   LSb16vsipll_ctrl_DP1                                13
    #define       bvsipll_ctrl_DP1                             3
    #define   MSK32vsipll_ctrl_DP1                                0xE0000000

    #define     RA_vsipll_ctrl4                                0x0010

    #define     BA_vsipll_ctrl_BYPASS                          0x0010
    #define     B16vsipll_ctrl_BYPASS                          0x0010
    #define   LSb32vsipll_ctrl_BYPASS                             0
    #define   LSb16vsipll_ctrl_BYPASS                             0
    #define       bvsipll_ctrl_BYPASS                          1
    #define   MSK32vsipll_ctrl_BYPASS                             0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_vsipll_status                               0x0014

    #define     BA_vsipll_status_LOCK                          0x0014
    #define     B16vsipll_status_LOCK                          0x0014
    #define   LSb32vsipll_status_LOCK                             0
    #define   LSb16vsipll_status_LOCK                             0
    #define       bvsipll_status_LOCK                          1
    #define   MSK32vsipll_status_LOCK                             0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vsipll {
    ///////////////////////////////////////////////////////////
    #define   GET32vsipll_ctrl_PD(r32)                         _BFGET_(r32, 0, 0)
    #define   SET32vsipll_ctrl_PD(r32,v)                       _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_ctrl_PD(r16)                         _BFGET_(r16, 0, 0)
    #define   SET16vsipll_ctrl_PD(r16,v)                       _BFSET_(r16, 0, 0,v)

    #define   GET32vsipll_ctrl_RESETN(r32)                     _BFGET_(r32, 1, 1)
    #define   SET32vsipll_ctrl_RESETN(r32,v)                   _BFSET_(r32, 1, 1,v)
    #define   GET16vsipll_ctrl_RESETN(r16)                     _BFGET_(r16, 1, 1)
    #define   SET16vsipll_ctrl_RESETN(r16,v)                   _BFSET_(r16, 1, 1,v)

    #define   GET32vsipll_ctrl_DM(r32)                         _BFGET_(r32, 7, 2)
    #define   SET32vsipll_ctrl_DM(r32,v)                       _BFSET_(r32, 7, 2,v)
    #define   GET16vsipll_ctrl_DM(r16)                         _BFGET_(r16, 7, 2)
    #define   SET16vsipll_ctrl_DM(r16,v)                       _BFSET_(r16, 7, 2,v)

    #define   GET32vsipll_ctrl_DN(r32)                         _BFGET_(r32,18, 8)
    #define   SET32vsipll_ctrl_DN(r32,v)                       _BFSET_(r32,18, 8,v)

    #define   GET32vsipll_ctrl_MODE(r32)                       _BFGET_(r32,20,19)
    #define   SET32vsipll_ctrl_MODE(r32,v)                     _BFSET_(r32,20,19,v)
    #define   GET16vsipll_ctrl_MODE(r16)                       _BFGET_(r16, 4, 3)
    #define   SET16vsipll_ctrl_MODE(r16,v)                     _BFSET_(r16, 4, 3,v)

    #define   GET32vsipll_ctrl_READY_BP(r32)                   _BFGET_(r32,21,21)
    #define   SET32vsipll_ctrl_READY_BP(r32,v)                 _BFSET_(r32,21,21,v)
    #define   GET16vsipll_ctrl_READY_BP(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16vsipll_ctrl_READY_BP(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32vsipll_ctrl_FRAC_READY(r32)                 _BFGET_(r32,22,22)
    #define   SET32vsipll_ctrl_FRAC_READY(r32,v)               _BFSET_(r32,22,22,v)
    #define   GET16vsipll_ctrl_FRAC_READY(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16vsipll_ctrl_FRAC_READY(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32vsipll_ctrl                                 {\
            UNSG32 uctrl_PD                                    :  1;\
            UNSG32 uctrl_RESETN                                :  1;\
            UNSG32 uctrl_DM                                    :  6;\
            UNSG32 uctrl_DN                                    : 11;\
            UNSG32 uctrl_MODE                                  :  2;\
            UNSG32 uctrl_READY_BP                              :  1;\
            UNSG32 uctrl_FRAC_READY                            :  1;\
            UNSG32 RSVDx0_b23                                  :  9;\
          }
    union { UNSG32 u32vsipll_ctrl;
            struct w32vsipll_ctrl;
          };
    #define   GET32vsipll_ctrl_FRAC(r32)                       _BFGET_(r32,23, 0)
    #define   SET32vsipll_ctrl_FRAC(r32,v)                     _BFSET_(r32,23, 0,v)

    #define     w32vsipll_ctrl1                                {\
            UNSG32 uctrl_FRAC                                  : 24;\
            UNSG32 RSVDx4_b24                                  :  8;\
          }
    union { UNSG32 u32vsipll_ctrl1;
            struct w32vsipll_ctrl1;
          };
    #define   GET32vsipll_ctrl_SSRATE(r32)                     _BFGET_(r32,10, 0)
    #define   SET32vsipll_ctrl_SSRATE(r32,v)                   _BFSET_(r32,10, 0,v)
    #define   GET16vsipll_ctrl_SSRATE(r16)                     _BFGET_(r16,10, 0)
    #define   SET16vsipll_ctrl_SSRATE(r16,v)                   _BFSET_(r16,10, 0,v)

    #define     w32vsipll_ctrl2                                {\
            UNSG32 uctrl_SSRATE                                : 11;\
            UNSG32 RSVDx8_b11                                  : 21;\
          }
    union { UNSG32 u32vsipll_ctrl2;
            struct w32vsipll_ctrl2;
          };
    #define   GET32vsipll_ctrl_SLOPE(r32)                      _BFGET_(r32,23, 0)
    #define   SET32vsipll_ctrl_SLOPE(r32,v)                    _BFSET_(r32,23, 0,v)

    #define   GET32vsipll_ctrl_PDDP(r32)                       _BFGET_(r32,24,24)
    #define   SET32vsipll_ctrl_PDDP(r32,v)                     _BFSET_(r32,24,24,v)
    #define   GET16vsipll_ctrl_PDDP(r16)                       _BFGET_(r16, 8, 8)
    #define   SET16vsipll_ctrl_PDDP(r16,v)                     _BFSET_(r16, 8, 8,v)

    #define   GET32vsipll_ctrl_DP(r32)                         _BFGET_(r32,27,25)
    #define   SET32vsipll_ctrl_DP(r32,v)                       _BFSET_(r32,27,25,v)
    #define   GET16vsipll_ctrl_DP(r16)                         _BFGET_(r16,11, 9)
    #define   SET16vsipll_ctrl_DP(r16,v)                       _BFSET_(r16,11, 9,v)

    #define   GET32vsipll_ctrl_PDDP1(r32)                      _BFGET_(r32,28,28)
    #define   SET32vsipll_ctrl_PDDP1(r32,v)                    _BFSET_(r32,28,28,v)
    #define   GET16vsipll_ctrl_PDDP1(r16)                      _BFGET_(r16,12,12)
    #define   SET16vsipll_ctrl_PDDP1(r16,v)                    _BFSET_(r16,12,12,v)

    #define   GET32vsipll_ctrl_DP1(r32)                        _BFGET_(r32,31,29)
    #define   SET32vsipll_ctrl_DP1(r32,v)                      _BFSET_(r32,31,29,v)
    #define   GET16vsipll_ctrl_DP1(r16)                        _BFGET_(r16,15,13)
    #define   SET16vsipll_ctrl_DP1(r16,v)                      _BFSET_(r16,15,13,v)

    #define     w32vsipll_ctrl3                                {\
            UNSG32 uctrl_SLOPE                                 : 24;\
            UNSG32 uctrl_PDDP                                  :  1;\
            UNSG32 uctrl_DP                                    :  3;\
            UNSG32 uctrl_PDDP1                                 :  1;\
            UNSG32 uctrl_DP1                                   :  3;\
          }
    union { UNSG32 u32vsipll_ctrl3;
            struct w32vsipll_ctrl3;
          };
    #define   GET32vsipll_ctrl_BYPASS(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32vsipll_ctrl_BYPASS(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_ctrl_BYPASS(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16vsipll_ctrl_BYPASS(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32vsipll_ctrl4                                {\
            UNSG32 uctrl_BYPASS                                :  1;\
            UNSG32 RSVDx10_b1                                  : 31;\
          }
    union { UNSG32 u32vsipll_ctrl4;
            struct w32vsipll_ctrl4;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32vsipll_status_LOCK(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32vsipll_status_LOCK(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_status_LOCK(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16vsipll_status_LOCK(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32vsipll_status                               {\
            UNSG32 ustatus_LOCK                                :  1;\
            UNSG32 RSVDx14_b1                                  : 31;\
          }
    union { UNSG32 u32vsipll_status;
            struct w32vsipll_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_vsipll;

    typedef union  T32vsipll_ctrl
          { UNSG32 u32;
            struct w32vsipll_ctrl;
                 } T32vsipll_ctrl;
    typedef union  T32vsipll_ctrl1
          { UNSG32 u32;
            struct w32vsipll_ctrl1;
                 } T32vsipll_ctrl1;
    typedef union  T32vsipll_ctrl2
          { UNSG32 u32;
            struct w32vsipll_ctrl2;
                 } T32vsipll_ctrl2;
    typedef union  T32vsipll_ctrl3
          { UNSG32 u32;
            struct w32vsipll_ctrl3;
                 } T32vsipll_ctrl3;
    typedef union  T32vsipll_ctrl4
          { UNSG32 u32;
            struct w32vsipll_ctrl4;
                 } T32vsipll_ctrl4;
    typedef union  T32vsipll_status
          { UNSG32 u32;
            struct w32vsipll_status;
                 } T32vsipll_status;
    ///////////////////////////////////////////////////////////

    typedef union  Tvsipll_ctrl
          { UNSG32 u32[5];
            struct {
            struct w32vsipll_ctrl;
            struct w32vsipll_ctrl1;
            struct w32vsipll_ctrl2;
            struct w32vsipll_ctrl3;
            struct w32vsipll_ctrl4;
                   };
                 } Tvsipll_ctrl;
    typedef union  Tvsipll_status
          { UNSG32 u32[1];
            struct {
            struct w32vsipll_status;
                   };
                 } Tvsipll_status;

    ///////////////////////////////////////////////////////////
     SIGN32 vsipll_drvrd(SIE_vsipll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vsipll_drvwr(SIE_vsipll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vsipll_reset(SIE_vsipll *p);
     SIGN32 vsipll_cmp  (SIE_vsipll *p, SIE_vsipll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vsipll_check(p,pie,pfx,hLOG) vsipll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vsipll_print(p,    pfx,hLOG) vsipll_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vsipll
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOff                                   (4,4)
///     ###
///     * Register for the Power domain which is OFF by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x0
///                                    : PWROFF                    0x0
///                                    : PWRON                     0x3
///                                                 ###
///                                                 * Power Switch control
///                                                 * Bit 1 : SLP1B
///                                                 * Bit 0 : SLP2B
///                                                 * SLP1B SLP2B
///                                                 * 0               X               Switch is turned off
///                                                 * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                                 * 1               1               PMOS switch is fully turned on to reduce Ron
///                                                 ###
///               %unsigned 1  pwrDomainRstN             0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Power Domain Reset. Active low.
///                                                 * 0 : Reset the power domain
///                                                 * 1:   De-assert the reset for the power domain
///                                                 ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOff
#define h_pwrOff (){}

    #define     RA_pwrOff_ctrl                                 0x0000

    #define     BA_pwrOff_ctrl_iso_eN                          0x0000
    #define     B16pwrOff_ctrl_iso_eN                          0x0000
    #define   LSb32pwrOff_ctrl_iso_eN                             0
    #define   LSb16pwrOff_ctrl_iso_eN                             0
    #define       bpwrOff_ctrl_iso_eN                          1
    #define   MSK32pwrOff_ctrl_iso_eN                             0x00000001
    #define        pwrOff_ctrl_iso_eN_enable                                0x0
    #define        pwrOff_ctrl_iso_eN_disable                               0x1

    #define     BA_pwrOff_ctrl_pwrSwitchCtrl                   0x0000
    #define     B16pwrOff_ctrl_pwrSwitchCtrl                   0x0000
    #define   LSb32pwrOff_ctrl_pwrSwitchCtrl                      1
    #define   LSb16pwrOff_ctrl_pwrSwitchCtrl                      1
    #define       bpwrOff_ctrl_pwrSwitchCtrl                   2
    #define   MSK32pwrOff_ctrl_pwrSwitchCtrl                      0x00000006
    #define        pwrOff_ctrl_pwrSwitchCtrl_PWROFF                         0x0
    #define        pwrOff_ctrl_pwrSwitchCtrl_PWRON                          0x3

    #define     BA_pwrOff_ctrl_pwrDomainRstN                   0x0000
    #define     B16pwrOff_ctrl_pwrDomainRstN                   0x0000
    #define   LSb32pwrOff_ctrl_pwrDomainRstN                      3
    #define   LSb16pwrOff_ctrl_pwrDomainRstN                      3
    #define       bpwrOff_ctrl_pwrDomainRstN                   1
    #define   MSK32pwrOff_ctrl_pwrDomainRstN                      0x00000008
    #define        pwrOff_ctrl_pwrDomainRstN_enable                         0x0
    #define        pwrOff_ctrl_pwrDomainRstN_disable                        0x1
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOff_status                               0x0004

    #define     BA_pwrOff_status_pwrStatus                     0x0004
    #define     B16pwrOff_status_pwrStatus                     0x0004
    #define   LSb32pwrOff_status_pwrStatus                        0
    #define   LSb16pwrOff_status_pwrStatus                        0
    #define       bpwrOff_status_pwrStatus                     2
    #define   MSK32pwrOff_status_pwrStatus                        0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOff {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOff_ctrl_iso_eN(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32pwrOff_ctrl_iso_eN(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOff_ctrl_iso_eN(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16pwrOff_ctrl_iso_eN(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOff_ctrl_pwrSwitchCtrl(r32)              _BFGET_(r32, 2, 1)
    #define   SET32pwrOff_ctrl_pwrSwitchCtrl(r32,v)            _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOff_ctrl_pwrSwitchCtrl(r16)              _BFGET_(r16, 2, 1)
    #define   SET16pwrOff_ctrl_pwrSwitchCtrl(r16,v)            _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOff_ctrl_pwrDomainRstN(r32)              _BFGET_(r32, 3, 3)
    #define   SET32pwrOff_ctrl_pwrDomainRstN(r32,v)            _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOff_ctrl_pwrDomainRstN(r16)              _BFGET_(r16, 3, 3)
    #define   SET16pwrOff_ctrl_pwrDomainRstN(r16,v)            _BFSET_(r16, 3, 3,v)

    #define     w32pwrOff_ctrl                                 {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOff_ctrl;
            struct w32pwrOff_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOff_status_pwrStatus(r32)                _BFGET_(r32, 1, 0)
    #define   SET32pwrOff_status_pwrStatus(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOff_status_pwrStatus(r16)                _BFGET_(r16, 1, 0)
    #define   SET16pwrOff_status_pwrStatus(r16,v)              _BFSET_(r16, 1, 0,v)

    #define     w32pwrOff_status                               {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32pwrOff_status;
            struct w32pwrOff_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOff;

    typedef union  T32pwrOff_ctrl
          { UNSG32 u32;
            struct w32pwrOff_ctrl;
                 } T32pwrOff_ctrl;
    typedef union  T32pwrOff_status
          { UNSG32 u32;
            struct w32pwrOff_status;
                 } T32pwrOff_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOff_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOff_ctrl;
                   };
                 } TpwrOff_ctrl;
    typedef union  TpwrOff_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOff_status;
                   };
                 } TpwrOff_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOff_drvrd(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOff_drvwr(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOff_reset(SIE_pwrOff *p);
     SIGN32 pwrOff_cmp  (SIE_pwrOff *p, SIE_pwrOff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOff_check(p,pie,pfx,hLOG) pwrOff_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOff_print(p,    pfx,hLOG) pwrOff_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOff
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOn                                    (4,4)
///     ###
///     * Register for the Power domain which is ON by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x1
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x3
///                                    ###
///                                    * Power Switch control
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  pwrDomainRstN             0x1
///                                    ###
///                                    * Power Domain Reset. Active low.
///                                    * 0 : Reset the power domain
///                                    * 1:   De-assert the reset for the power domain
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn
#define h_pwrOn (){}

    #define     RA_pwrOn_ctrl                                  0x0000

    #define     BA_pwrOn_ctrl_iso_eN                           0x0000
    #define     B16pwrOn_ctrl_iso_eN                           0x0000
    #define   LSb32pwrOn_ctrl_iso_eN                              0
    #define   LSb16pwrOn_ctrl_iso_eN                              0
    #define       bpwrOn_ctrl_iso_eN                           1
    #define   MSK32pwrOn_ctrl_iso_eN                              0x00000001
    #define        pwrOn_ctrl_iso_eN_enable                                 0x0
    #define        pwrOn_ctrl_iso_eN_disable                                0x1

    #define     BA_pwrOn_ctrl_pwrSwitchCtrl                    0x0000
    #define     B16pwrOn_ctrl_pwrSwitchCtrl                    0x0000
    #define   LSb32pwrOn_ctrl_pwrSwitchCtrl                       1
    #define   LSb16pwrOn_ctrl_pwrSwitchCtrl                       1
    #define       bpwrOn_ctrl_pwrSwitchCtrl                    2
    #define   MSK32pwrOn_ctrl_pwrSwitchCtrl                       0x00000006

    #define     BA_pwrOn_ctrl_pwrDomainRstN                    0x0000
    #define     B16pwrOn_ctrl_pwrDomainRstN                    0x0000
    #define   LSb32pwrOn_ctrl_pwrDomainRstN                       3
    #define   LSb16pwrOn_ctrl_pwrDomainRstN                       3
    #define       bpwrOn_ctrl_pwrDomainRstN                    1
    #define   MSK32pwrOn_ctrl_pwrDomainRstN                       0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOn_status                                0x0004

    #define     BA_pwrOn_status_pwrStatus                      0x0004
    #define     B16pwrOn_status_pwrStatus                      0x0004
    #define   LSb32pwrOn_status_pwrStatus                         0
    #define   LSb16pwrOn_status_pwrStatus                         0
    #define       bpwrOn_status_pwrStatus                      2
    #define   MSK32pwrOn_status_pwrStatus                         0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOn {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_ctrl_iso_eN(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32pwrOn_ctrl_iso_eN(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOn_ctrl_iso_eN(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16pwrOn_ctrl_iso_eN(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOn_ctrl_pwrSwitchCtrl(r32)               _BFGET_(r32, 2, 1)
    #define   SET32pwrOn_ctrl_pwrSwitchCtrl(r32,v)             _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOn_ctrl_pwrSwitchCtrl(r16)               _BFGET_(r16, 2, 1)
    #define   SET16pwrOn_ctrl_pwrSwitchCtrl(r16,v)             _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOn_ctrl_pwrDomainRstN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32pwrOn_ctrl_pwrDomainRstN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOn_ctrl_pwrDomainRstN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16pwrOn_ctrl_pwrDomainRstN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define     w32pwrOn_ctrl                                  {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOn_ctrl;
            struct w32pwrOn_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_status_pwrStatus(r32)                 _BFGET_(r32, 1, 0)
    #define   SET32pwrOn_status_pwrStatus(r32,v)               _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOn_status_pwrStatus(r16)                 _BFGET_(r16, 1, 0)
    #define   SET16pwrOn_status_pwrStatus(r16,v)               _BFSET_(r16, 1, 0,v)

    #define     w32pwrOn_status                                {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32pwrOn_status;
            struct w32pwrOn_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOn;

    typedef union  T32pwrOn_ctrl
          { UNSG32 u32;
            struct w32pwrOn_ctrl;
                 } T32pwrOn_ctrl;
    typedef union  T32pwrOn_status
          { UNSG32 u32;
            struct w32pwrOn_status;
                 } T32pwrOn_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOn_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_ctrl;
                   };
                 } TpwrOn_ctrl;
    typedef union  TpwrOn_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_status;
                   };
                 } TpwrOn_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOn_drvrd(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOn_drvwr(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOn_reset(SIE_pwrOn *p);
     SIGN32 pwrOn_cmp  (SIE_pwrOn *p, SIE_pwrOn *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOn_check(p,pie,pfx,hLOG) pwrOn_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOn_print(p,    pfx,hLOG) pwrOn_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOn
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOn_iso                                (4,4)
///     ###
///     * Register for the Power domain which is ON by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x3
///                                    ###
///                                    * Power Switch control
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  pwrDomainRstN             0x0
///                                    ###
///                                    * Power Domain Reset. Active low.
///                                    * 0 : Reset the power domain
///                                    * 1:   De-assert the reset for the power domain
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  IP_IDLE                   
///                                    ###
///                                    * Indication from IP that it is idle and can be powered down.
///                                    * 1: Idle
///                                    * 0: Busy
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       7b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn_iso
#define h_pwrOn_iso (){}

    #define     RA_pwrOn_iso_ctrl                              0x0000

    #define     BA_pwrOn_iso_ctrl_iso_eN                       0x0000
    #define     B16pwrOn_iso_ctrl_iso_eN                       0x0000
    #define   LSb32pwrOn_iso_ctrl_iso_eN                          0
    #define   LSb16pwrOn_iso_ctrl_iso_eN                          0
    #define       bpwrOn_iso_ctrl_iso_eN                       1
    #define   MSK32pwrOn_iso_ctrl_iso_eN                          0x00000001
    #define        pwrOn_iso_ctrl_iso_eN_enable                             0x0
    #define        pwrOn_iso_ctrl_iso_eN_disable                            0x1

    #define     BA_pwrOn_iso_ctrl_pwrSwitchCtrl                0x0000
    #define     B16pwrOn_iso_ctrl_pwrSwitchCtrl                0x0000
    #define   LSb32pwrOn_iso_ctrl_pwrSwitchCtrl                   1
    #define   LSb16pwrOn_iso_ctrl_pwrSwitchCtrl                   1
    #define       bpwrOn_iso_ctrl_pwrSwitchCtrl                2
    #define   MSK32pwrOn_iso_ctrl_pwrSwitchCtrl                   0x00000006

    #define     BA_pwrOn_iso_ctrl_pwrDomainRstN                0x0000
    #define     B16pwrOn_iso_ctrl_pwrDomainRstN                0x0000
    #define   LSb32pwrOn_iso_ctrl_pwrDomainRstN                   3
    #define   LSb16pwrOn_iso_ctrl_pwrDomainRstN                   3
    #define       bpwrOn_iso_ctrl_pwrDomainRstN                1
    #define   MSK32pwrOn_iso_ctrl_pwrDomainRstN                   0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOn_iso_status                            0x0004

    #define     BA_pwrOn_iso_status_pwrStatus                  0x0004
    #define     B16pwrOn_iso_status_pwrStatus                  0x0004
    #define   LSb32pwrOn_iso_status_pwrStatus                     0
    #define   LSb16pwrOn_iso_status_pwrStatus                     0
    #define       bpwrOn_iso_status_pwrStatus                  2
    #define   MSK32pwrOn_iso_status_pwrStatus                     0x00000003

    #define     BA_pwrOn_iso_status_IP_IDLE                    0x0004
    #define     B16pwrOn_iso_status_IP_IDLE                    0x0004
    #define   LSb32pwrOn_iso_status_IP_IDLE                       2
    #define   LSb16pwrOn_iso_status_IP_IDLE                       2
    #define       bpwrOn_iso_status_IP_IDLE                    1
    #define   MSK32pwrOn_iso_status_IP_IDLE                       0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOn_iso {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_iso_ctrl_iso_eN(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32pwrOn_iso_ctrl_iso_eN(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOn_iso_ctrl_iso_eN(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16pwrOn_iso_ctrl_iso_eN(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOn_iso_ctrl_pwrSwitchCtrl(r32)           _BFGET_(r32, 2, 1)
    #define   SET32pwrOn_iso_ctrl_pwrSwitchCtrl(r32,v)         _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOn_iso_ctrl_pwrSwitchCtrl(r16)           _BFGET_(r16, 2, 1)
    #define   SET16pwrOn_iso_ctrl_pwrSwitchCtrl(r16,v)         _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOn_iso_ctrl_pwrDomainRstN(r32)           _BFGET_(r32, 3, 3)
    #define   SET32pwrOn_iso_ctrl_pwrDomainRstN(r32,v)         _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOn_iso_ctrl_pwrDomainRstN(r16)           _BFGET_(r16, 3, 3)
    #define   SET16pwrOn_iso_ctrl_pwrDomainRstN(r16,v)         _BFSET_(r16, 3, 3,v)

    #define     w32pwrOn_iso_ctrl                              {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOn_iso_ctrl;
            struct w32pwrOn_iso_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_iso_status_pwrStatus(r32)             _BFGET_(r32, 1, 0)
    #define   SET32pwrOn_iso_status_pwrStatus(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOn_iso_status_pwrStatus(r16)             _BFGET_(r16, 1, 0)
    #define   SET16pwrOn_iso_status_pwrStatus(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32pwrOn_iso_status_IP_IDLE(r32)               _BFGET_(r32, 2, 2)
    #define   SET32pwrOn_iso_status_IP_IDLE(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16pwrOn_iso_status_IP_IDLE(r16)               _BFGET_(r16, 2, 2)
    #define   SET16pwrOn_iso_status_IP_IDLE(r16,v)             _BFSET_(r16, 2, 2,v)

    #define     w32pwrOn_iso_status                            {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 ustatus_IP_IDLE                             :  1;\
            UNSG32 RSVDx4_b3                                   : 29;\
          }
    union { UNSG32 u32pwrOn_iso_status;
            struct w32pwrOn_iso_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOn_iso;

    typedef union  T32pwrOn_iso_ctrl
          { UNSG32 u32;
            struct w32pwrOn_iso_ctrl;
                 } T32pwrOn_iso_ctrl;
    typedef union  T32pwrOn_iso_status
          { UNSG32 u32;
            struct w32pwrOn_iso_status;
                 } T32pwrOn_iso_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOn_iso_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_iso_ctrl;
                   };
                 } TpwrOn_iso_ctrl;
    typedef union  TpwrOn_iso_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_iso_status;
                   };
                 } TpwrOn_iso_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOn_iso_drvrd(SIE_pwrOn_iso *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOn_iso_drvwr(SIE_pwrOn_iso *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOn_iso_reset(SIE_pwrOn_iso *p);
     SIGN32 pwrOn_iso_cmp  (SIE_pwrOn_iso *p, SIE_pwrOn_iso *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOn_iso_check(p,pie,pfx,hLOG) pwrOn_iso_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOn_iso_print(p,    pfx,hLOG) pwrOn_iso_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOn_iso
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxiPCntStat                              (4,4)
///     ###
///     * AXI Performance Counters
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 TOTAL_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Total no.of AXI clocks
///                                    ###
///     @ 0x00004 ARWAIT_CNT           (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks aRValid = 1 & aRReady = 0
///                                    ###
///     @ 0x00008 RWAIT_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks rValid = 1 & rReady = 0
///                                    ###
///     @ 0x0000C RIDLE_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks rValid = 0 & rReady = 1
///                                    ###
///     @ 0x00010 RDATA_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks rValid = 1 & rReady = 1
///                                    ###
///     @ 0x00014 AWWAIT_CNT           (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks aWValid = 1 & aWReady = 0
///                                    ###
///     @ 0x00018 WWAIT_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks wValid = 1 & wReady = 0
///                                    ###
///     @ 0x0001C WIDLE_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks wValid = 0 & wReady = 1
///                                    ###
///     @ 0x00020 WDATA_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks wValid = 1 & wReady = 1
///                                    ###
///     @ 0x00024 AWDATA_CNT           (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts no of clocks awValid & awReady
///                                    ###
///     @ 0x00028 ARDATA_CNT           (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts no of clocks awValid & awReady
///                                    ###
///     @ 0x0002C OF_STATUS            (RNB-)
///               %unsigned 1  total                     0x0
///               %unsigned 1  arwait                    0x0
///               %unsigned 1  rwait                     0x0
///               %unsigned 1  ridle                     0x0
///               %unsigned 1  rdata                     0x0
///               %unsigned 1  awwait                    0x0
///               %unsigned 1  wwait                     0x0
///               %unsigned 1  widle                     0x0
///               %unsigned 1  wdata                     0x0
///               %unsigned 1  awdata                    0x0
///               %unsigned 1  ardata                    0x0
///                                    ###
///                                    * Overflow status of total, wait and data counters. Clear will clear the overflow status as well.
///                                    ###
///               %%        21         # Stuffing bits...
///     @ 0x00030 READY                (R-)
///               %unsigned 1  cnt                       0x0
///                                    ###
///                                    * This bit is set by HW when counter values are latched and it's ok for SW to read the counter
///                                    ###
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      52B, bits:     364b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxiPCntStat
#define h_AxiPCntStat (){}

    #define     RA_AxiPCntStat_TOTAL_CNT                       0x0000

    #define     BA_AxiPCntStat_TOTAL_CNT_cnt                   0x0000
    #define     B16AxiPCntStat_TOTAL_CNT_cnt                   0x0000
    #define   LSb32AxiPCntStat_TOTAL_CNT_cnt                      0
    #define   LSb16AxiPCntStat_TOTAL_CNT_cnt                      0
    #define       bAxiPCntStat_TOTAL_CNT_cnt                   32
    #define   MSK32AxiPCntStat_TOTAL_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_ARWAIT_CNT                      0x0004

    #define     BA_AxiPCntStat_ARWAIT_CNT_cnt                  0x0004
    #define     B16AxiPCntStat_ARWAIT_CNT_cnt                  0x0004
    #define   LSb32AxiPCntStat_ARWAIT_CNT_cnt                     0
    #define   LSb16AxiPCntStat_ARWAIT_CNT_cnt                     0
    #define       bAxiPCntStat_ARWAIT_CNT_cnt                  32
    #define   MSK32AxiPCntStat_ARWAIT_CNT_cnt                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_RWAIT_CNT                       0x0008

    #define     BA_AxiPCntStat_RWAIT_CNT_cnt                   0x0008
    #define     B16AxiPCntStat_RWAIT_CNT_cnt                   0x0008
    #define   LSb32AxiPCntStat_RWAIT_CNT_cnt                      0
    #define   LSb16AxiPCntStat_RWAIT_CNT_cnt                      0
    #define       bAxiPCntStat_RWAIT_CNT_cnt                   32
    #define   MSK32AxiPCntStat_RWAIT_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_RIDLE_CNT                       0x000C

    #define     BA_AxiPCntStat_RIDLE_CNT_cnt                   0x000C
    #define     B16AxiPCntStat_RIDLE_CNT_cnt                   0x000C
    #define   LSb32AxiPCntStat_RIDLE_CNT_cnt                      0
    #define   LSb16AxiPCntStat_RIDLE_CNT_cnt                      0
    #define       bAxiPCntStat_RIDLE_CNT_cnt                   32
    #define   MSK32AxiPCntStat_RIDLE_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_RDATA_CNT                       0x0010

    #define     BA_AxiPCntStat_RDATA_CNT_cnt                   0x0010
    #define     B16AxiPCntStat_RDATA_CNT_cnt                   0x0010
    #define   LSb32AxiPCntStat_RDATA_CNT_cnt                      0
    #define   LSb16AxiPCntStat_RDATA_CNT_cnt                      0
    #define       bAxiPCntStat_RDATA_CNT_cnt                   32
    #define   MSK32AxiPCntStat_RDATA_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_AWWAIT_CNT                      0x0014

    #define     BA_AxiPCntStat_AWWAIT_CNT_cnt                  0x0014
    #define     B16AxiPCntStat_AWWAIT_CNT_cnt                  0x0014
    #define   LSb32AxiPCntStat_AWWAIT_CNT_cnt                     0
    #define   LSb16AxiPCntStat_AWWAIT_CNT_cnt                     0
    #define       bAxiPCntStat_AWWAIT_CNT_cnt                  32
    #define   MSK32AxiPCntStat_AWWAIT_CNT_cnt                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_WWAIT_CNT                       0x0018

    #define     BA_AxiPCntStat_WWAIT_CNT_cnt                   0x0018
    #define     B16AxiPCntStat_WWAIT_CNT_cnt                   0x0018
    #define   LSb32AxiPCntStat_WWAIT_CNT_cnt                      0
    #define   LSb16AxiPCntStat_WWAIT_CNT_cnt                      0
    #define       bAxiPCntStat_WWAIT_CNT_cnt                   32
    #define   MSK32AxiPCntStat_WWAIT_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_WIDLE_CNT                       0x001C

    #define     BA_AxiPCntStat_WIDLE_CNT_cnt                   0x001C
    #define     B16AxiPCntStat_WIDLE_CNT_cnt                   0x001C
    #define   LSb32AxiPCntStat_WIDLE_CNT_cnt                      0
    #define   LSb16AxiPCntStat_WIDLE_CNT_cnt                      0
    #define       bAxiPCntStat_WIDLE_CNT_cnt                   32
    #define   MSK32AxiPCntStat_WIDLE_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_WDATA_CNT                       0x0020

    #define     BA_AxiPCntStat_WDATA_CNT_cnt                   0x0020
    #define     B16AxiPCntStat_WDATA_CNT_cnt                   0x0020
    #define   LSb32AxiPCntStat_WDATA_CNT_cnt                      0
    #define   LSb16AxiPCntStat_WDATA_CNT_cnt                      0
    #define       bAxiPCntStat_WDATA_CNT_cnt                   32
    #define   MSK32AxiPCntStat_WDATA_CNT_cnt                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_AWDATA_CNT                      0x0024

    #define     BA_AxiPCntStat_AWDATA_CNT_cnt                  0x0024
    #define     B16AxiPCntStat_AWDATA_CNT_cnt                  0x0024
    #define   LSb32AxiPCntStat_AWDATA_CNT_cnt                     0
    #define   LSb16AxiPCntStat_AWDATA_CNT_cnt                     0
    #define       bAxiPCntStat_AWDATA_CNT_cnt                  32
    #define   MSK32AxiPCntStat_AWDATA_CNT_cnt                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_ARDATA_CNT                      0x0028

    #define     BA_AxiPCntStat_ARDATA_CNT_cnt                  0x0028
    #define     B16AxiPCntStat_ARDATA_CNT_cnt                  0x0028
    #define   LSb32AxiPCntStat_ARDATA_CNT_cnt                     0
    #define   LSb16AxiPCntStat_ARDATA_CNT_cnt                     0
    #define       bAxiPCntStat_ARDATA_CNT_cnt                  32
    #define   MSK32AxiPCntStat_ARDATA_CNT_cnt                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_OF_STATUS                       0x002C

    #define     BA_AxiPCntStat_OF_STATUS_total                 0x002C
    #define     B16AxiPCntStat_OF_STATUS_total                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_total                    0
    #define   LSb16AxiPCntStat_OF_STATUS_total                    0
    #define       bAxiPCntStat_OF_STATUS_total                 1
    #define   MSK32AxiPCntStat_OF_STATUS_total                    0x00000001

    #define     BA_AxiPCntStat_OF_STATUS_arwait                0x002C
    #define     B16AxiPCntStat_OF_STATUS_arwait                0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_arwait                   1
    #define   LSb16AxiPCntStat_OF_STATUS_arwait                   1
    #define       bAxiPCntStat_OF_STATUS_arwait                1
    #define   MSK32AxiPCntStat_OF_STATUS_arwait                   0x00000002

    #define     BA_AxiPCntStat_OF_STATUS_rwait                 0x002C
    #define     B16AxiPCntStat_OF_STATUS_rwait                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_rwait                    2
    #define   LSb16AxiPCntStat_OF_STATUS_rwait                    2
    #define       bAxiPCntStat_OF_STATUS_rwait                 1
    #define   MSK32AxiPCntStat_OF_STATUS_rwait                    0x00000004

    #define     BA_AxiPCntStat_OF_STATUS_ridle                 0x002C
    #define     B16AxiPCntStat_OF_STATUS_ridle                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_ridle                    3
    #define   LSb16AxiPCntStat_OF_STATUS_ridle                    3
    #define       bAxiPCntStat_OF_STATUS_ridle                 1
    #define   MSK32AxiPCntStat_OF_STATUS_ridle                    0x00000008

    #define     BA_AxiPCntStat_OF_STATUS_rdata                 0x002C
    #define     B16AxiPCntStat_OF_STATUS_rdata                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_rdata                    4
    #define   LSb16AxiPCntStat_OF_STATUS_rdata                    4
    #define       bAxiPCntStat_OF_STATUS_rdata                 1
    #define   MSK32AxiPCntStat_OF_STATUS_rdata                    0x00000010

    #define     BA_AxiPCntStat_OF_STATUS_awwait                0x002C
    #define     B16AxiPCntStat_OF_STATUS_awwait                0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_awwait                   5
    #define   LSb16AxiPCntStat_OF_STATUS_awwait                   5
    #define       bAxiPCntStat_OF_STATUS_awwait                1
    #define   MSK32AxiPCntStat_OF_STATUS_awwait                   0x00000020

    #define     BA_AxiPCntStat_OF_STATUS_wwait                 0x002C
    #define     B16AxiPCntStat_OF_STATUS_wwait                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_wwait                    6
    #define   LSb16AxiPCntStat_OF_STATUS_wwait                    6
    #define       bAxiPCntStat_OF_STATUS_wwait                 1
    #define   MSK32AxiPCntStat_OF_STATUS_wwait                    0x00000040

    #define     BA_AxiPCntStat_OF_STATUS_widle                 0x002C
    #define     B16AxiPCntStat_OF_STATUS_widle                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_widle                    7
    #define   LSb16AxiPCntStat_OF_STATUS_widle                    7
    #define       bAxiPCntStat_OF_STATUS_widle                 1
    #define   MSK32AxiPCntStat_OF_STATUS_widle                    0x00000080

    #define     BA_AxiPCntStat_OF_STATUS_wdata                 0x002D
    #define     B16AxiPCntStat_OF_STATUS_wdata                 0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_wdata                    8
    #define   LSb16AxiPCntStat_OF_STATUS_wdata                    8
    #define       bAxiPCntStat_OF_STATUS_wdata                 1
    #define   MSK32AxiPCntStat_OF_STATUS_wdata                    0x00000100

    #define     BA_AxiPCntStat_OF_STATUS_awdata                0x002D
    #define     B16AxiPCntStat_OF_STATUS_awdata                0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_awdata                   9
    #define   LSb16AxiPCntStat_OF_STATUS_awdata                   9
    #define       bAxiPCntStat_OF_STATUS_awdata                1
    #define   MSK32AxiPCntStat_OF_STATUS_awdata                   0x00000200

    #define     BA_AxiPCntStat_OF_STATUS_ardata                0x002D
    #define     B16AxiPCntStat_OF_STATUS_ardata                0x002C
    #define   LSb32AxiPCntStat_OF_STATUS_ardata                   10
    #define   LSb16AxiPCntStat_OF_STATUS_ardata                   10
    #define       bAxiPCntStat_OF_STATUS_ardata                1
    #define   MSK32AxiPCntStat_OF_STATUS_ardata                   0x00000400
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCntStat_READY                           0x0030

    #define     BA_AxiPCntStat_READY_cnt                       0x0030
    #define     B16AxiPCntStat_READY_cnt                       0x0030
    #define   LSb32AxiPCntStat_READY_cnt                          0
    #define   LSb16AxiPCntStat_READY_cnt                          0
    #define       bAxiPCntStat_READY_cnt                       1
    #define   MSK32AxiPCntStat_READY_cnt                          0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxiPCntStat {
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_TOTAL_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_TOTAL_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_TOTAL_CNT                       {\
            UNSG32 uTOTAL_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_TOTAL_CNT;
            struct w32AxiPCntStat_TOTAL_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_ARWAIT_CNT_cnt(r32)             _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_ARWAIT_CNT_cnt(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_ARWAIT_CNT                      {\
            UNSG32 uARWAIT_CNT_cnt                             : 32;\
          }
    union { UNSG32 u32AxiPCntStat_ARWAIT_CNT;
            struct w32AxiPCntStat_ARWAIT_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_RWAIT_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_RWAIT_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_RWAIT_CNT                       {\
            UNSG32 uRWAIT_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_RWAIT_CNT;
            struct w32AxiPCntStat_RWAIT_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_RIDLE_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_RIDLE_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_RIDLE_CNT                       {\
            UNSG32 uRIDLE_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_RIDLE_CNT;
            struct w32AxiPCntStat_RIDLE_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_RDATA_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_RDATA_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_RDATA_CNT                       {\
            UNSG32 uRDATA_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_RDATA_CNT;
            struct w32AxiPCntStat_RDATA_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_AWWAIT_CNT_cnt(r32)             _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_AWWAIT_CNT_cnt(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_AWWAIT_CNT                      {\
            UNSG32 uAWWAIT_CNT_cnt                             : 32;\
          }
    union { UNSG32 u32AxiPCntStat_AWWAIT_CNT;
            struct w32AxiPCntStat_AWWAIT_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_WWAIT_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_WWAIT_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_WWAIT_CNT                       {\
            UNSG32 uWWAIT_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_WWAIT_CNT;
            struct w32AxiPCntStat_WWAIT_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_WIDLE_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_WIDLE_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_WIDLE_CNT                       {\
            UNSG32 uWIDLE_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_WIDLE_CNT;
            struct w32AxiPCntStat_WIDLE_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_WDATA_CNT_cnt(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_WDATA_CNT_cnt(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_WDATA_CNT                       {\
            UNSG32 uWDATA_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCntStat_WDATA_CNT;
            struct w32AxiPCntStat_WDATA_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_AWDATA_CNT_cnt(r32)             _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_AWDATA_CNT_cnt(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_AWDATA_CNT                      {\
            UNSG32 uAWDATA_CNT_cnt                             : 32;\
          }
    union { UNSG32 u32AxiPCntStat_AWDATA_CNT;
            struct w32AxiPCntStat_AWDATA_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_ARDATA_CNT_cnt(r32)             _BFGET_(r32,31, 0)
    #define   SET32AxiPCntStat_ARDATA_CNT_cnt(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32AxiPCntStat_ARDATA_CNT                      {\
            UNSG32 uARDATA_CNT_cnt                             : 32;\
          }
    union { UNSG32 u32AxiPCntStat_ARDATA_CNT;
            struct w32AxiPCntStat_ARDATA_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_OF_STATUS_total(r32)            _BFGET_(r32, 0, 0)
    #define   SET32AxiPCntStat_OF_STATUS_total(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16AxiPCntStat_OF_STATUS_total(r16)            _BFGET_(r16, 0, 0)
    #define   SET16AxiPCntStat_OF_STATUS_total(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32AxiPCntStat_OF_STATUS_arwait(r32)           _BFGET_(r32, 1, 1)
    #define   SET32AxiPCntStat_OF_STATUS_arwait(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16AxiPCntStat_OF_STATUS_arwait(r16)           _BFGET_(r16, 1, 1)
    #define   SET16AxiPCntStat_OF_STATUS_arwait(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32AxiPCntStat_OF_STATUS_rwait(r32)            _BFGET_(r32, 2, 2)
    #define   SET32AxiPCntStat_OF_STATUS_rwait(r32,v)          _BFSET_(r32, 2, 2,v)
    #define   GET16AxiPCntStat_OF_STATUS_rwait(r16)            _BFGET_(r16, 2, 2)
    #define   SET16AxiPCntStat_OF_STATUS_rwait(r16,v)          _BFSET_(r16, 2, 2,v)

    #define   GET32AxiPCntStat_OF_STATUS_ridle(r32)            _BFGET_(r32, 3, 3)
    #define   SET32AxiPCntStat_OF_STATUS_ridle(r32,v)          _BFSET_(r32, 3, 3,v)
    #define   GET16AxiPCntStat_OF_STATUS_ridle(r16)            _BFGET_(r16, 3, 3)
    #define   SET16AxiPCntStat_OF_STATUS_ridle(r16,v)          _BFSET_(r16, 3, 3,v)

    #define   GET32AxiPCntStat_OF_STATUS_rdata(r32)            _BFGET_(r32, 4, 4)
    #define   SET32AxiPCntStat_OF_STATUS_rdata(r32,v)          _BFSET_(r32, 4, 4,v)
    #define   GET16AxiPCntStat_OF_STATUS_rdata(r16)            _BFGET_(r16, 4, 4)
    #define   SET16AxiPCntStat_OF_STATUS_rdata(r16,v)          _BFSET_(r16, 4, 4,v)

    #define   GET32AxiPCntStat_OF_STATUS_awwait(r32)           _BFGET_(r32, 5, 5)
    #define   SET32AxiPCntStat_OF_STATUS_awwait(r32,v)         _BFSET_(r32, 5, 5,v)
    #define   GET16AxiPCntStat_OF_STATUS_awwait(r16)           _BFGET_(r16, 5, 5)
    #define   SET16AxiPCntStat_OF_STATUS_awwait(r16,v)         _BFSET_(r16, 5, 5,v)

    #define   GET32AxiPCntStat_OF_STATUS_wwait(r32)            _BFGET_(r32, 6, 6)
    #define   SET32AxiPCntStat_OF_STATUS_wwait(r32,v)          _BFSET_(r32, 6, 6,v)
    #define   GET16AxiPCntStat_OF_STATUS_wwait(r16)            _BFGET_(r16, 6, 6)
    #define   SET16AxiPCntStat_OF_STATUS_wwait(r16,v)          _BFSET_(r16, 6, 6,v)

    #define   GET32AxiPCntStat_OF_STATUS_widle(r32)            _BFGET_(r32, 7, 7)
    #define   SET32AxiPCntStat_OF_STATUS_widle(r32,v)          _BFSET_(r32, 7, 7,v)
    #define   GET16AxiPCntStat_OF_STATUS_widle(r16)            _BFGET_(r16, 7, 7)
    #define   SET16AxiPCntStat_OF_STATUS_widle(r16,v)          _BFSET_(r16, 7, 7,v)

    #define   GET32AxiPCntStat_OF_STATUS_wdata(r32)            _BFGET_(r32, 8, 8)
    #define   SET32AxiPCntStat_OF_STATUS_wdata(r32,v)          _BFSET_(r32, 8, 8,v)
    #define   GET16AxiPCntStat_OF_STATUS_wdata(r16)            _BFGET_(r16, 8, 8)
    #define   SET16AxiPCntStat_OF_STATUS_wdata(r16,v)          _BFSET_(r16, 8, 8,v)

    #define   GET32AxiPCntStat_OF_STATUS_awdata(r32)           _BFGET_(r32, 9, 9)
    #define   SET32AxiPCntStat_OF_STATUS_awdata(r32,v)         _BFSET_(r32, 9, 9,v)
    #define   GET16AxiPCntStat_OF_STATUS_awdata(r16)           _BFGET_(r16, 9, 9)
    #define   SET16AxiPCntStat_OF_STATUS_awdata(r16,v)         _BFSET_(r16, 9, 9,v)

    #define   GET32AxiPCntStat_OF_STATUS_ardata(r32)           _BFGET_(r32,10,10)
    #define   SET32AxiPCntStat_OF_STATUS_ardata(r32,v)         _BFSET_(r32,10,10,v)
    #define   GET16AxiPCntStat_OF_STATUS_ardata(r16)           _BFGET_(r16,10,10)
    #define   SET16AxiPCntStat_OF_STATUS_ardata(r16,v)         _BFSET_(r16,10,10,v)

    #define     w32AxiPCntStat_OF_STATUS                       {\
            UNSG32 uOF_STATUS_total                            :  1;\
            UNSG32 uOF_STATUS_arwait                           :  1;\
            UNSG32 uOF_STATUS_rwait                            :  1;\
            UNSG32 uOF_STATUS_ridle                            :  1;\
            UNSG32 uOF_STATUS_rdata                            :  1;\
            UNSG32 uOF_STATUS_awwait                           :  1;\
            UNSG32 uOF_STATUS_wwait                            :  1;\
            UNSG32 uOF_STATUS_widle                            :  1;\
            UNSG32 uOF_STATUS_wdata                            :  1;\
            UNSG32 uOF_STATUS_awdata                           :  1;\
            UNSG32 uOF_STATUS_ardata                           :  1;\
            UNSG32 RSVDx2C_b11                                 : 21;\
          }
    union { UNSG32 u32AxiPCntStat_OF_STATUS;
            struct w32AxiPCntStat_OF_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCntStat_READY_cnt(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32AxiPCntStat_READY_cnt(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16AxiPCntStat_READY_cnt(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16AxiPCntStat_READY_cnt(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32AxiPCntStat_READY                           {\
            UNSG32 uREADY_cnt                                  :  1;\
            UNSG32 RSVDx30_b1                                  : 31;\
          }
    union { UNSG32 u32AxiPCntStat_READY;
            struct w32AxiPCntStat_READY;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxiPCntStat;

    typedef union  T32AxiPCntStat_TOTAL_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_TOTAL_CNT;
                 } T32AxiPCntStat_TOTAL_CNT;
    typedef union  T32AxiPCntStat_ARWAIT_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_ARWAIT_CNT;
                 } T32AxiPCntStat_ARWAIT_CNT;
    typedef union  T32AxiPCntStat_RWAIT_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_RWAIT_CNT;
                 } T32AxiPCntStat_RWAIT_CNT;
    typedef union  T32AxiPCntStat_RIDLE_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_RIDLE_CNT;
                 } T32AxiPCntStat_RIDLE_CNT;
    typedef union  T32AxiPCntStat_RDATA_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_RDATA_CNT;
                 } T32AxiPCntStat_RDATA_CNT;
    typedef union  T32AxiPCntStat_AWWAIT_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_AWWAIT_CNT;
                 } T32AxiPCntStat_AWWAIT_CNT;
    typedef union  T32AxiPCntStat_WWAIT_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_WWAIT_CNT;
                 } T32AxiPCntStat_WWAIT_CNT;
    typedef union  T32AxiPCntStat_WIDLE_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_WIDLE_CNT;
                 } T32AxiPCntStat_WIDLE_CNT;
    typedef union  T32AxiPCntStat_WDATA_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_WDATA_CNT;
                 } T32AxiPCntStat_WDATA_CNT;
    typedef union  T32AxiPCntStat_AWDATA_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_AWDATA_CNT;
                 } T32AxiPCntStat_AWDATA_CNT;
    typedef union  T32AxiPCntStat_ARDATA_CNT
          { UNSG32 u32;
            struct w32AxiPCntStat_ARDATA_CNT;
                 } T32AxiPCntStat_ARDATA_CNT;
    typedef union  T32AxiPCntStat_OF_STATUS
          { UNSG32 u32;
            struct w32AxiPCntStat_OF_STATUS;
                 } T32AxiPCntStat_OF_STATUS;
    typedef union  T32AxiPCntStat_READY
          { UNSG32 u32;
            struct w32AxiPCntStat_READY;
                 } T32AxiPCntStat_READY;
    ///////////////////////////////////////////////////////////

    typedef union  TAxiPCntStat_TOTAL_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_TOTAL_CNT;
                   };
                 } TAxiPCntStat_TOTAL_CNT;
    typedef union  TAxiPCntStat_ARWAIT_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_ARWAIT_CNT;
                   };
                 } TAxiPCntStat_ARWAIT_CNT;
    typedef union  TAxiPCntStat_RWAIT_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_RWAIT_CNT;
                   };
                 } TAxiPCntStat_RWAIT_CNT;
    typedef union  TAxiPCntStat_RIDLE_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_RIDLE_CNT;
                   };
                 } TAxiPCntStat_RIDLE_CNT;
    typedef union  TAxiPCntStat_RDATA_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_RDATA_CNT;
                   };
                 } TAxiPCntStat_RDATA_CNT;
    typedef union  TAxiPCntStat_AWWAIT_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_AWWAIT_CNT;
                   };
                 } TAxiPCntStat_AWWAIT_CNT;
    typedef union  TAxiPCntStat_WWAIT_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_WWAIT_CNT;
                   };
                 } TAxiPCntStat_WWAIT_CNT;
    typedef union  TAxiPCntStat_WIDLE_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_WIDLE_CNT;
                   };
                 } TAxiPCntStat_WIDLE_CNT;
    typedef union  TAxiPCntStat_WDATA_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_WDATA_CNT;
                   };
                 } TAxiPCntStat_WDATA_CNT;
    typedef union  TAxiPCntStat_AWDATA_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_AWDATA_CNT;
                   };
                 } TAxiPCntStat_AWDATA_CNT;
    typedef union  TAxiPCntStat_ARDATA_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_ARDATA_CNT;
                   };
                 } TAxiPCntStat_ARDATA_CNT;
    typedef union  TAxiPCntStat_OF_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_OF_STATUS;
                   };
                 } TAxiPCntStat_OF_STATUS;
    typedef union  TAxiPCntStat_READY
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCntStat_READY;
                   };
                 } TAxiPCntStat_READY;

    ///////////////////////////////////////////////////////////
     SIGN32 AxiPCntStat_drvrd(SIE_AxiPCntStat *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxiPCntStat_drvwr(SIE_AxiPCntStat *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxiPCntStat_reset(SIE_AxiPCntStat *p);
     SIGN32 AxiPCntStat_cmp  (SIE_AxiPCntStat *p, SIE_AxiPCntStat *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxiPCntStat_check(p,pie,pfx,hLOG) AxiPCntStat_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxiPCntStat_print(p,    pfx,hLOG) AxiPCntStat_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxiPCntStat
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxiErrorMon                              (4,4)
///     ###
///     * AXI Bus Error Response Monitor
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 WriteID              (R-)
///               %unsigned 32 berrID                    0x0
///                                    ###
///                                    * ID of AXI Write Transaction that caused an error response
///                                    ###
///     @ 0x00004 WriteStat            (R-)
///               %unsigned 1  berrType                  0x0
///                                    ###
///                                    * Error Response Type
///                                    * 0: SLVERR
///                                    * 1: DECERR
///                                    ###
///               %unsigned 1  berrValid                 0x0
///                                    ###
///                                    * When asserted, an error response is detected and the information is captured into berrID and berrType. Monitoring is stopped.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00008 WriteCtrl            (RW)
///               %unsigned 1  berrClear                 0x0
///                                    ###
///                                    * Writing 1 will clear berrValid and resume the monitoring. This bit self clears.
///                                    ###
///               %unsigned 1  berrIntrEn                0x0
///                                    ###
///                                    * 1: Monitor generates an active high interrupt when berrValid = 1
///                                    * 0: Interrupt is masked
///                                    * Note: To clear interrupt, write 1 to berrClear
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x0000C ReadID               (R-)
///               %unsigned 32 rerrID                    0x0
///                                    ###
///                                    * ID of AXI Read Transaction that caused an error response
///                                    ###
///     @ 0x00010 ReadStat             (R-)
///               %unsigned 1  rerrType                  0x0
///                                    ###
///                                    * Error Response Type
///                                    * 0: SLVERR
///                                    * 1: DECERR
///                                    ###
///               %unsigned 1  rerrValid                 0x0
///                                    ###
///                                    * When asserted, an error response is detected and the information is captured into rerrID and rerrType. Monitoring is stopped.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00014 ReadCtrl             (RW)
///               %unsigned 1  rerrClear                 0x0
///                                    ###
///                                    * Writing 1 will clear rerrValid and resume the monitoring. This bit self clears.
///                                    ###
///               %unsigned 1  rerrIntrEn                0x0
///                                    ###
///                                    * 1: Monitor generates an active high interrupt when berrValid = 1
///                                    * 0: Interrupt is masked.
///                                    * Note: To clear Interrupt, write 1 to berrClear
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:      72b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxiErrorMon
#define h_AxiErrorMon (){}

    #define     RA_AxiErrorMon_WriteID                         0x0000

    #define     BA_AxiErrorMon_WriteID_berrID                  0x0000
    #define     B16AxiErrorMon_WriteID_berrID                  0x0000
    #define   LSb32AxiErrorMon_WriteID_berrID                     0
    #define   LSb16AxiErrorMon_WriteID_berrID                     0
    #define       bAxiErrorMon_WriteID_berrID                  32
    #define   MSK32AxiErrorMon_WriteID_berrID                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_WriteStat                       0x0004

    #define     BA_AxiErrorMon_WriteStat_berrType              0x0004
    #define     B16AxiErrorMon_WriteStat_berrType              0x0004
    #define   LSb32AxiErrorMon_WriteStat_berrType                 0
    #define   LSb16AxiErrorMon_WriteStat_berrType                 0
    #define       bAxiErrorMon_WriteStat_berrType              1
    #define   MSK32AxiErrorMon_WriteStat_berrType                 0x00000001

    #define     BA_AxiErrorMon_WriteStat_berrValid             0x0004
    #define     B16AxiErrorMon_WriteStat_berrValid             0x0004
    #define   LSb32AxiErrorMon_WriteStat_berrValid                1
    #define   LSb16AxiErrorMon_WriteStat_berrValid                1
    #define       bAxiErrorMon_WriteStat_berrValid             1
    #define   MSK32AxiErrorMon_WriteStat_berrValid                0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_WriteCtrl                       0x0008

    #define     BA_AxiErrorMon_WriteCtrl_berrClear             0x0008
    #define     B16AxiErrorMon_WriteCtrl_berrClear             0x0008
    #define   LSb32AxiErrorMon_WriteCtrl_berrClear                0
    #define   LSb16AxiErrorMon_WriteCtrl_berrClear                0
    #define       bAxiErrorMon_WriteCtrl_berrClear             1
    #define   MSK32AxiErrorMon_WriteCtrl_berrClear                0x00000001

    #define     BA_AxiErrorMon_WriteCtrl_berrIntrEn            0x0008
    #define     B16AxiErrorMon_WriteCtrl_berrIntrEn            0x0008
    #define   LSb32AxiErrorMon_WriteCtrl_berrIntrEn               1
    #define   LSb16AxiErrorMon_WriteCtrl_berrIntrEn               1
    #define       bAxiErrorMon_WriteCtrl_berrIntrEn            1
    #define   MSK32AxiErrorMon_WriteCtrl_berrIntrEn               0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_ReadID                          0x000C

    #define     BA_AxiErrorMon_ReadID_rerrID                   0x000C
    #define     B16AxiErrorMon_ReadID_rerrID                   0x000C
    #define   LSb32AxiErrorMon_ReadID_rerrID                      0
    #define   LSb16AxiErrorMon_ReadID_rerrID                      0
    #define       bAxiErrorMon_ReadID_rerrID                   32
    #define   MSK32AxiErrorMon_ReadID_rerrID                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_ReadStat                        0x0010

    #define     BA_AxiErrorMon_ReadStat_rerrType               0x0010
    #define     B16AxiErrorMon_ReadStat_rerrType               0x0010
    #define   LSb32AxiErrorMon_ReadStat_rerrType                  0
    #define   LSb16AxiErrorMon_ReadStat_rerrType                  0
    #define       bAxiErrorMon_ReadStat_rerrType               1
    #define   MSK32AxiErrorMon_ReadStat_rerrType                  0x00000001

    #define     BA_AxiErrorMon_ReadStat_rerrValid              0x0010
    #define     B16AxiErrorMon_ReadStat_rerrValid              0x0010
    #define   LSb32AxiErrorMon_ReadStat_rerrValid                 1
    #define   LSb16AxiErrorMon_ReadStat_rerrValid                 1
    #define       bAxiErrorMon_ReadStat_rerrValid              1
    #define   MSK32AxiErrorMon_ReadStat_rerrValid                 0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_ReadCtrl                        0x0014

    #define     BA_AxiErrorMon_ReadCtrl_rerrClear              0x0014
    #define     B16AxiErrorMon_ReadCtrl_rerrClear              0x0014
    #define   LSb32AxiErrorMon_ReadCtrl_rerrClear                 0
    #define   LSb16AxiErrorMon_ReadCtrl_rerrClear                 0
    #define       bAxiErrorMon_ReadCtrl_rerrClear              1
    #define   MSK32AxiErrorMon_ReadCtrl_rerrClear                 0x00000001

    #define     BA_AxiErrorMon_ReadCtrl_rerrIntrEn             0x0014
    #define     B16AxiErrorMon_ReadCtrl_rerrIntrEn             0x0014
    #define   LSb32AxiErrorMon_ReadCtrl_rerrIntrEn                1
    #define   LSb16AxiErrorMon_ReadCtrl_rerrIntrEn                1
    #define       bAxiErrorMon_ReadCtrl_rerrIntrEn             1
    #define   MSK32AxiErrorMon_ReadCtrl_rerrIntrEn                0x00000002
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxiErrorMon {
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_WriteID_berrID(r32)             _BFGET_(r32,31, 0)
    #define   SET32AxiErrorMon_WriteID_berrID(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32AxiErrorMon_WriteID                         {\
            UNSG32 uWriteID_berrID                             : 32;\
          }
    union { UNSG32 u32AxiErrorMon_WriteID;
            struct w32AxiErrorMon_WriteID;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_WriteStat_berrType(r32)         _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_WriteStat_berrType(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_WriteStat_berrType(r16)         _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_WriteStat_berrType(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_WriteStat_berrValid(r32)        _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_WriteStat_berrValid(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_WriteStat_berrValid(r16)        _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_WriteStat_berrValid(r16,v)      _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_WriteStat                       {\
            UNSG32 uWriteStat_berrType                         :  1;\
            UNSG32 uWriteStat_berrValid                        :  1;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32AxiErrorMon_WriteStat;
            struct w32AxiErrorMon_WriteStat;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_WriteCtrl_berrClear(r32)        _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_WriteCtrl_berrClear(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_WriteCtrl_berrClear(r16)        _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_WriteCtrl_berrClear(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_WriteCtrl_berrIntrEn(r32)       _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_WriteCtrl_berrIntrEn(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_WriteCtrl_berrIntrEn(r16)       _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_WriteCtrl_berrIntrEn(r16,v)     _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_WriteCtrl                       {\
            UNSG32 uWriteCtrl_berrClear                        :  1;\
            UNSG32 uWriteCtrl_berrIntrEn                       :  1;\
            UNSG32 RSVDx8_b2                                   : 30;\
          }
    union { UNSG32 u32AxiErrorMon_WriteCtrl;
            struct w32AxiErrorMon_WriteCtrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_ReadID_rerrID(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiErrorMon_ReadID_rerrID(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiErrorMon_ReadID                          {\
            UNSG32 uReadID_rerrID                              : 32;\
          }
    union { UNSG32 u32AxiErrorMon_ReadID;
            struct w32AxiErrorMon_ReadID;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_ReadStat_rerrType(r32)          _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_ReadStat_rerrType(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_ReadStat_rerrType(r16)          _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_ReadStat_rerrType(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_ReadStat_rerrValid(r32)         _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_ReadStat_rerrValid(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_ReadStat_rerrValid(r16)         _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_ReadStat_rerrValid(r16,v)       _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_ReadStat                        {\
            UNSG32 uReadStat_rerrType                          :  1;\
            UNSG32 uReadStat_rerrValid                         :  1;\
            UNSG32 RSVDx10_b2                                  : 30;\
          }
    union { UNSG32 u32AxiErrorMon_ReadStat;
            struct w32AxiErrorMon_ReadStat;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_ReadCtrl_rerrClear(r32)         _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_ReadCtrl_rerrClear(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_ReadCtrl_rerrClear(r16)         _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_ReadCtrl_rerrClear(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_ReadCtrl_rerrIntrEn(r32)        _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_ReadCtrl_rerrIntrEn(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_ReadCtrl_rerrIntrEn(r16)        _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_ReadCtrl_rerrIntrEn(r16,v)      _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_ReadCtrl                        {\
            UNSG32 uReadCtrl_rerrClear                         :  1;\
            UNSG32 uReadCtrl_rerrIntrEn                        :  1;\
            UNSG32 RSVDx14_b2                                  : 30;\
          }
    union { UNSG32 u32AxiErrorMon_ReadCtrl;
            struct w32AxiErrorMon_ReadCtrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxiErrorMon;

    typedef union  T32AxiErrorMon_WriteID
          { UNSG32 u32;
            struct w32AxiErrorMon_WriteID;
                 } T32AxiErrorMon_WriteID;
    typedef union  T32AxiErrorMon_WriteStat
          { UNSG32 u32;
            struct w32AxiErrorMon_WriteStat;
                 } T32AxiErrorMon_WriteStat;
    typedef union  T32AxiErrorMon_WriteCtrl
          { UNSG32 u32;
            struct w32AxiErrorMon_WriteCtrl;
                 } T32AxiErrorMon_WriteCtrl;
    typedef union  T32AxiErrorMon_ReadID
          { UNSG32 u32;
            struct w32AxiErrorMon_ReadID;
                 } T32AxiErrorMon_ReadID;
    typedef union  T32AxiErrorMon_ReadStat
          { UNSG32 u32;
            struct w32AxiErrorMon_ReadStat;
                 } T32AxiErrorMon_ReadStat;
    typedef union  T32AxiErrorMon_ReadCtrl
          { UNSG32 u32;
            struct w32AxiErrorMon_ReadCtrl;
                 } T32AxiErrorMon_ReadCtrl;
    ///////////////////////////////////////////////////////////

    typedef union  TAxiErrorMon_WriteID
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_WriteID;
                   };
                 } TAxiErrorMon_WriteID;
    typedef union  TAxiErrorMon_WriteStat
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_WriteStat;
                   };
                 } TAxiErrorMon_WriteStat;
    typedef union  TAxiErrorMon_WriteCtrl
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_WriteCtrl;
                   };
                 } TAxiErrorMon_WriteCtrl;
    typedef union  TAxiErrorMon_ReadID
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_ReadID;
                   };
                 } TAxiErrorMon_ReadID;
    typedef union  TAxiErrorMon_ReadStat
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_ReadStat;
                   };
                 } TAxiErrorMon_ReadStat;
    typedef union  TAxiErrorMon_ReadCtrl
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_ReadCtrl;
                   };
                 } TAxiErrorMon_ReadCtrl;

    ///////////////////////////////////////////////////////////
     SIGN32 AxiErrorMon_drvrd(SIE_AxiErrorMon *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxiErrorMon_drvwr(SIE_AxiErrorMon *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxiErrorMon_reset(SIE_AxiErrorMon *p);
     SIGN32 AxiErrorMon_cmp  (SIE_AxiErrorMon *p, SIE_AxiErrorMon *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxiErrorMon_check(p,pie,pfx,hLOG) AxiErrorMon_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxiErrorMon_print(p,    pfx,hLOG) AxiErrorMon_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxiErrorMon
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxCacheOW                                (4,4)
///     ###
///     * AXI AxCache bit overwrite
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 AxCache              (P)
///               %unsigned 4  Write                     0xF
///                                    ###
///                                    * AWCache
///                                    ###
///               %unsigned 1  WrBypass                  0x0
///                                    ###
///                                    * Bypass AWCache
///                                    * 1: use Biu value
///                                    * 0: use master value
///                                    ###
///               %unsigned 4  Read                      0xF
///                                    ###
///                                    * ARCache
///                                    ###
///               %unsigned 1  RdBypass                  0x0
///                                    ###
///                                    * Bypass ARCache
///                                    * 1: use Biu value
///                                    * 0: use master value
///                                    * Only the lowest bit is used. The high 3 bits are reserved. Please keep them as all 0s.
///                                    ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxCacheOW
#define h_AxCacheOW (){}

    #define     RA_AxCacheOW_AxCache                           0x0000

    #define     BA_AxCacheOW_AxCache_Write                     0x0000
    #define     B16AxCacheOW_AxCache_Write                     0x0000
    #define   LSb32AxCacheOW_AxCache_Write                        0
    #define   LSb16AxCacheOW_AxCache_Write                        0
    #define       bAxCacheOW_AxCache_Write                     4
    #define   MSK32AxCacheOW_AxCache_Write                        0x0000000F

    #define     BA_AxCacheOW_AxCache_WrBypass                  0x0000
    #define     B16AxCacheOW_AxCache_WrBypass                  0x0000
    #define   LSb32AxCacheOW_AxCache_WrBypass                     4
    #define   LSb16AxCacheOW_AxCache_WrBypass                     4
    #define       bAxCacheOW_AxCache_WrBypass                  1
    #define   MSK32AxCacheOW_AxCache_WrBypass                     0x00000010

    #define     BA_AxCacheOW_AxCache_Read                      0x0000
    #define     B16AxCacheOW_AxCache_Read                      0x0000
    #define   LSb32AxCacheOW_AxCache_Read                         5
    #define   LSb16AxCacheOW_AxCache_Read                         5
    #define       bAxCacheOW_AxCache_Read                      4
    #define   MSK32AxCacheOW_AxCache_Read                         0x000001E0

    #define     BA_AxCacheOW_AxCache_RdBypass                  0x0001
    #define     B16AxCacheOW_AxCache_RdBypass                  0x0000
    #define   LSb32AxCacheOW_AxCache_RdBypass                     9
    #define   LSb16AxCacheOW_AxCache_RdBypass                     9
    #define       bAxCacheOW_AxCache_RdBypass                  1
    #define   MSK32AxCacheOW_AxCache_RdBypass                     0x00000200
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxCacheOW {
    ///////////////////////////////////////////////////////////
    #define   GET32AxCacheOW_AxCache_Write(r32)                _BFGET_(r32, 3, 0)
    #define   SET32AxCacheOW_AxCache_Write(r32,v)              _BFSET_(r32, 3, 0,v)
    #define   GET16AxCacheOW_AxCache_Write(r16)                _BFGET_(r16, 3, 0)
    #define   SET16AxCacheOW_AxCache_Write(r16,v)              _BFSET_(r16, 3, 0,v)

    #define   GET32AxCacheOW_AxCache_WrBypass(r32)             _BFGET_(r32, 4, 4)
    #define   SET32AxCacheOW_AxCache_WrBypass(r32,v)           _BFSET_(r32, 4, 4,v)
    #define   GET16AxCacheOW_AxCache_WrBypass(r16)             _BFGET_(r16, 4, 4)
    #define   SET16AxCacheOW_AxCache_WrBypass(r16,v)           _BFSET_(r16, 4, 4,v)

    #define   GET32AxCacheOW_AxCache_Read(r32)                 _BFGET_(r32, 8, 5)
    #define   SET32AxCacheOW_AxCache_Read(r32,v)               _BFSET_(r32, 8, 5,v)
    #define   GET16AxCacheOW_AxCache_Read(r16)                 _BFGET_(r16, 8, 5)
    #define   SET16AxCacheOW_AxCache_Read(r16,v)               _BFSET_(r16, 8, 5,v)

    #define   GET32AxCacheOW_AxCache_RdBypass(r32)             _BFGET_(r32, 9, 9)
    #define   SET32AxCacheOW_AxCache_RdBypass(r32,v)           _BFSET_(r32, 9, 9,v)
    #define   GET16AxCacheOW_AxCache_RdBypass(r16)             _BFGET_(r16, 9, 9)
    #define   SET16AxCacheOW_AxCache_RdBypass(r16,v)           _BFSET_(r16, 9, 9,v)

    #define     w32AxCacheOW_AxCache                           {\
            UNSG32 uAxCache_Write                              :  4;\
            UNSG32 uAxCache_WrBypass                           :  1;\
            UNSG32 uAxCache_Read                               :  4;\
            UNSG32 uAxCache_RdBypass                           :  1;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32AxCacheOW_AxCache;
            struct w32AxCacheOW_AxCache;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxCacheOW;

    typedef union  T32AxCacheOW_AxCache
          { UNSG32 u32;
            struct w32AxCacheOW_AxCache;
                 } T32AxCacheOW_AxCache;
    ///////////////////////////////////////////////////////////

    typedef union  TAxCacheOW_AxCache
          { UNSG32 u32[1];
            struct {
            struct w32AxCacheOW_AxCache;
                   };
                 } TAxCacheOW_AxCache;

    ///////////////////////////////////////////////////////////
     SIGN32 AxCacheOW_drvrd(SIE_AxCacheOW *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxCacheOW_drvwr(SIE_AxCacheOW *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxCacheOW_reset(SIE_AxCacheOW *p);
     SIGN32 AxCacheOW_cmp  (SIE_AxCacheOW *p, SIE_AxCacheOW *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxCacheOW_check(p,pie,pfx,hLOG) AxCacheOW_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxCacheOW_print(p,    pfx,hLOG) AxCacheOW_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxCacheOW
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxQoSOW                                  (4,4)
///     ###
///     * AXI AxQos bit overwrite control
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 AxQoS                (P)
///               %unsigned 4  Write                     0x0
///                                    ###
///                                    * AwQoS
///                                    ###
///               %unsigned 1  WrBypass                  0x0
///                                    ###
///                                    * Bypass AWQoS
///                                    * 1 : use Biu value
///                                    * 0 : use master value
///                                    ###
///               %unsigned 4  Read                      0x0
///                                    ###
///                                    * ArQoS
///                                    ###
///               %unsigned 1  RdBypass                  0x0
///                                    ###
///                                    * Bypass ARQoS
///                                    * 1 : use Biu value
///                                    * 0 : use master value
///                                    ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxQoSOW
#define h_AxQoSOW (){}

    #define     RA_AxQoSOW_AxQoS                               0x0000

    #define     BA_AxQoSOW_AxQoS_Write                         0x0000
    #define     B16AxQoSOW_AxQoS_Write                         0x0000
    #define   LSb32AxQoSOW_AxQoS_Write                            0
    #define   LSb16AxQoSOW_AxQoS_Write                            0
    #define       bAxQoSOW_AxQoS_Write                         4
    #define   MSK32AxQoSOW_AxQoS_Write                            0x0000000F

    #define     BA_AxQoSOW_AxQoS_WrBypass                      0x0000
    #define     B16AxQoSOW_AxQoS_WrBypass                      0x0000
    #define   LSb32AxQoSOW_AxQoS_WrBypass                         4
    #define   LSb16AxQoSOW_AxQoS_WrBypass                         4
    #define       bAxQoSOW_AxQoS_WrBypass                      1
    #define   MSK32AxQoSOW_AxQoS_WrBypass                         0x00000010

    #define     BA_AxQoSOW_AxQoS_Read                          0x0000
    #define     B16AxQoSOW_AxQoS_Read                          0x0000
    #define   LSb32AxQoSOW_AxQoS_Read                             5
    #define   LSb16AxQoSOW_AxQoS_Read                             5
    #define       bAxQoSOW_AxQoS_Read                          4
    #define   MSK32AxQoSOW_AxQoS_Read                             0x000001E0

    #define     BA_AxQoSOW_AxQoS_RdBypass                      0x0001
    #define     B16AxQoSOW_AxQoS_RdBypass                      0x0000
    #define   LSb32AxQoSOW_AxQoS_RdBypass                         9
    #define   LSb16AxQoSOW_AxQoS_RdBypass                         9
    #define       bAxQoSOW_AxQoS_RdBypass                      1
    #define   MSK32AxQoSOW_AxQoS_RdBypass                         0x00000200
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxQoSOW {
    ///////////////////////////////////////////////////////////
    #define   GET32AxQoSOW_AxQoS_Write(r32)                    _BFGET_(r32, 3, 0)
    #define   SET32AxQoSOW_AxQoS_Write(r32,v)                  _BFSET_(r32, 3, 0,v)
    #define   GET16AxQoSOW_AxQoS_Write(r16)                    _BFGET_(r16, 3, 0)
    #define   SET16AxQoSOW_AxQoS_Write(r16,v)                  _BFSET_(r16, 3, 0,v)

    #define   GET32AxQoSOW_AxQoS_WrBypass(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32AxQoSOW_AxQoS_WrBypass(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16AxQoSOW_AxQoS_WrBypass(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16AxQoSOW_AxQoS_WrBypass(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32AxQoSOW_AxQoS_Read(r32)                     _BFGET_(r32, 8, 5)
    #define   SET32AxQoSOW_AxQoS_Read(r32,v)                   _BFSET_(r32, 8, 5,v)
    #define   GET16AxQoSOW_AxQoS_Read(r16)                     _BFGET_(r16, 8, 5)
    #define   SET16AxQoSOW_AxQoS_Read(r16,v)                   _BFSET_(r16, 8, 5,v)

    #define   GET32AxQoSOW_AxQoS_RdBypass(r32)                 _BFGET_(r32, 9, 9)
    #define   SET32AxQoSOW_AxQoS_RdBypass(r32,v)               _BFSET_(r32, 9, 9,v)
    #define   GET16AxQoSOW_AxQoS_RdBypass(r16)                 _BFGET_(r16, 9, 9)
    #define   SET16AxQoSOW_AxQoS_RdBypass(r16,v)               _BFSET_(r16, 9, 9,v)

    #define     w32AxQoSOW_AxQoS                               {\
            UNSG32 uAxQoS_Write                                :  4;\
            UNSG32 uAxQoS_WrBypass                             :  1;\
            UNSG32 uAxQoS_Read                                 :  4;\
            UNSG32 uAxQoS_RdBypass                             :  1;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32AxQoSOW_AxQoS;
            struct w32AxQoSOW_AxQoS;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxQoSOW;

    typedef union  T32AxQoSOW_AxQoS
          { UNSG32 u32;
            struct w32AxQoSOW_AxQoS;
                 } T32AxQoSOW_AxQoS;
    ///////////////////////////////////////////////////////////

    typedef union  TAxQoSOW_AxQoS
          { UNSG32 u32[1];
            struct {
            struct w32AxQoSOW_AxQoS;
                   };
                 } TAxQoSOW_AxQoS;

    ///////////////////////////////////////////////////////////
     SIGN32 AxQoSOW_drvrd(SIE_AxQoSOW *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxQoSOW_drvwr(SIE_AxQoSOW *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxQoSOW_reset(SIE_AxQoSOW *p);
     SIGN32 AxQoSOW_cmp  (SIE_AxQoSOW *p, SIE_AxQoSOW *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxQoSOW_check(p,pie,pfx,hLOG) AxQoSOW_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxQoSOW_print(p,    pfx,hLOG) AxQoSOW_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxQoSOW
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxProtOW                                 (4,4)
///     ###
///     * AXI AxProt bit overwrite
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 AxProt               (P)
///               %unsigned 3  Write                     0x0
///                                    ###
///                                    * AWProt
///                                    ###
///               %unsigned 1  WrBypass                  0x0
///                                    ###
///                                    * Bypass AWProt
///                                    * 1: use Biu value
///                                    * 0: use master value
///                                    ###
///               %unsigned 3  Read                      0x0
///                                    ###
///                                    * ARProt
///                                    ###
///               %unsigned 1  RdBypass                  0x0
///                                    ###
///                                    * Bypass ARProt
///                                    * 1: use Biu value
///                                    * 0: use master value
///                                    * Only the lowest bit is used. The high 3 bits are reserved. Please keep them as all 0s.
///                                    ###
///               %%        24         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       8b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxProtOW
#define h_AxProtOW (){}

    #define     RA_AxProtOW_AxProt                             0x0000

    #define     BA_AxProtOW_AxProt_Write                       0x0000
    #define     B16AxProtOW_AxProt_Write                       0x0000
    #define   LSb32AxProtOW_AxProt_Write                          0
    #define   LSb16AxProtOW_AxProt_Write                          0
    #define       bAxProtOW_AxProt_Write                       3
    #define   MSK32AxProtOW_AxProt_Write                          0x00000007

    #define     BA_AxProtOW_AxProt_WrBypass                    0x0000
    #define     B16AxProtOW_AxProt_WrBypass                    0x0000
    #define   LSb32AxProtOW_AxProt_WrBypass                       3
    #define   LSb16AxProtOW_AxProt_WrBypass                       3
    #define       bAxProtOW_AxProt_WrBypass                    1
    #define   MSK32AxProtOW_AxProt_WrBypass                       0x00000008

    #define     BA_AxProtOW_AxProt_Read                        0x0000
    #define     B16AxProtOW_AxProt_Read                        0x0000
    #define   LSb32AxProtOW_AxProt_Read                           4
    #define   LSb16AxProtOW_AxProt_Read                           4
    #define       bAxProtOW_AxProt_Read                        3
    #define   MSK32AxProtOW_AxProt_Read                           0x00000070

    #define     BA_AxProtOW_AxProt_RdBypass                    0x0000
    #define     B16AxProtOW_AxProt_RdBypass                    0x0000
    #define   LSb32AxProtOW_AxProt_RdBypass                       7
    #define   LSb16AxProtOW_AxProt_RdBypass                       7
    #define       bAxProtOW_AxProt_RdBypass                    1
    #define   MSK32AxProtOW_AxProt_RdBypass                       0x00000080
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxProtOW {
    ///////////////////////////////////////////////////////////
    #define   GET32AxProtOW_AxProt_Write(r32)                  _BFGET_(r32, 2, 0)
    #define   SET32AxProtOW_AxProt_Write(r32,v)                _BFSET_(r32, 2, 0,v)
    #define   GET16AxProtOW_AxProt_Write(r16)                  _BFGET_(r16, 2, 0)
    #define   SET16AxProtOW_AxProt_Write(r16,v)                _BFSET_(r16, 2, 0,v)

    #define   GET32AxProtOW_AxProt_WrBypass(r32)               _BFGET_(r32, 3, 3)
    #define   SET32AxProtOW_AxProt_WrBypass(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16AxProtOW_AxProt_WrBypass(r16)               _BFGET_(r16, 3, 3)
    #define   SET16AxProtOW_AxProt_WrBypass(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32AxProtOW_AxProt_Read(r32)                   _BFGET_(r32, 6, 4)
    #define   SET32AxProtOW_AxProt_Read(r32,v)                 _BFSET_(r32, 6, 4,v)
    #define   GET16AxProtOW_AxProt_Read(r16)                   _BFGET_(r16, 6, 4)
    #define   SET16AxProtOW_AxProt_Read(r16,v)                 _BFSET_(r16, 6, 4,v)

    #define   GET32AxProtOW_AxProt_RdBypass(r32)               _BFGET_(r32, 7, 7)
    #define   SET32AxProtOW_AxProt_RdBypass(r32,v)             _BFSET_(r32, 7, 7,v)
    #define   GET16AxProtOW_AxProt_RdBypass(r16)               _BFGET_(r16, 7, 7)
    #define   SET16AxProtOW_AxProt_RdBypass(r16,v)             _BFSET_(r16, 7, 7,v)

    #define     w32AxProtOW_AxProt                             {\
            UNSG32 uAxProt_Write                               :  3;\
            UNSG32 uAxProt_WrBypass                            :  1;\
            UNSG32 uAxProt_Read                                :  3;\
            UNSG32 uAxProt_RdBypass                            :  1;\
            UNSG32 RSVDx0_b8                                   : 24;\
          }
    union { UNSG32 u32AxProtOW_AxProt;
            struct w32AxProtOW_AxProt;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxProtOW;

    typedef union  T32AxProtOW_AxProt
          { UNSG32 u32;
            struct w32AxProtOW_AxProt;
                 } T32AxProtOW_AxProt;
    ///////////////////////////////////////////////////////////

    typedef union  TAxProtOW_AxProt
          { UNSG32 u32[1];
            struct {
            struct w32AxProtOW_AxProt;
                   };
                 } TAxProtOW_AxProt;

    ///////////////////////////////////////////////////////////
     SIGN32 AxProtOW_drvrd(SIE_AxProtOW *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxProtOW_drvwr(SIE_AxProtOW *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxProtOW_reset(SIE_AxProtOW *p);
     SIGN32 AxProtOW_cmp  (SIE_AxProtOW *p, SIE_AxProtOW *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxProtOW_check(p,pie,pfx,hLOG) AxProtOW_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxProtOW_print(p,    pfx,hLOG) AxProtOW_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxProtOW
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE MC_Perf_CntStat                          (4,4)
///     ###
///     * MC performance logging signals counters
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 TOTAL_CNT            (RNB-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * count
///                                    ###
///     @ 0x00004 OF_STATUS            (RNB-)
///               %unsigned 1  total                     0x0
///                                    ###
///                                    * Overflow status
///                                    ###
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      33b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MC_Perf_CntStat
#define h_MC_Perf_CntStat (){}

    #define     RA_MC_Perf_CntStat_TOTAL_CNT                   0x0000

    #define     BA_MC_Perf_CntStat_TOTAL_CNT_cnt               0x0000
    #define     B16MC_Perf_CntStat_TOTAL_CNT_cnt               0x0000
    #define   LSb32MC_Perf_CntStat_TOTAL_CNT_cnt                  0
    #define   LSb16MC_Perf_CntStat_TOTAL_CNT_cnt                  0
    #define       bMC_Perf_CntStat_TOTAL_CNT_cnt               32
    #define   MSK32MC_Perf_CntStat_TOTAL_CNT_cnt                  0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_MC_Perf_CntStat_OF_STATUS                   0x0004

    #define     BA_MC_Perf_CntStat_OF_STATUS_total             0x0004
    #define     B16MC_Perf_CntStat_OF_STATUS_total             0x0004
    #define   LSb32MC_Perf_CntStat_OF_STATUS_total                0
    #define   LSb16MC_Perf_CntStat_OF_STATUS_total                0
    #define       bMC_Perf_CntStat_OF_STATUS_total             1
    #define   MSK32MC_Perf_CntStat_OF_STATUS_total                0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_MC_Perf_CntStat {
    ///////////////////////////////////////////////////////////
    #define   GET32MC_Perf_CntStat_TOTAL_CNT_cnt(r32)          _BFGET_(r32,31, 0)
    #define   SET32MC_Perf_CntStat_TOTAL_CNT_cnt(r32,v)        _BFSET_(r32,31, 0,v)

    #define     w32MC_Perf_CntStat_TOTAL_CNT                   {\
            UNSG32 uTOTAL_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32MC_Perf_CntStat_TOTAL_CNT;
            struct w32MC_Perf_CntStat_TOTAL_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC_Perf_CntStat_OF_STATUS_total(r32)        _BFGET_(r32, 0, 0)
    #define   SET32MC_Perf_CntStat_OF_STATUS_total(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16MC_Perf_CntStat_OF_STATUS_total(r16)        _BFGET_(r16, 0, 0)
    #define   SET16MC_Perf_CntStat_OF_STATUS_total(r16,v)      _BFSET_(r16, 0, 0,v)

    #define     w32MC_Perf_CntStat_OF_STATUS                   {\
            UNSG32 uOF_STATUS_total                            :  1;\
            UNSG32 RSVDx4_b1                                   : 31;\
          }
    union { UNSG32 u32MC_Perf_CntStat_OF_STATUS;
            struct w32MC_Perf_CntStat_OF_STATUS;
          };
    ///////////////////////////////////////////////////////////
    } SIE_MC_Perf_CntStat;

    typedef union  T32MC_Perf_CntStat_TOTAL_CNT
          { UNSG32 u32;
            struct w32MC_Perf_CntStat_TOTAL_CNT;
                 } T32MC_Perf_CntStat_TOTAL_CNT;
    typedef union  T32MC_Perf_CntStat_OF_STATUS
          { UNSG32 u32;
            struct w32MC_Perf_CntStat_OF_STATUS;
                 } T32MC_Perf_CntStat_OF_STATUS;
    ///////////////////////////////////////////////////////////

    typedef union  TMC_Perf_CntStat_TOTAL_CNT
          { UNSG32 u32[1];
            struct {
            struct w32MC_Perf_CntStat_TOTAL_CNT;
                   };
                 } TMC_Perf_CntStat_TOTAL_CNT;
    typedef union  TMC_Perf_CntStat_OF_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32MC_Perf_CntStat_OF_STATUS;
                   };
                 } TMC_Perf_CntStat_OF_STATUS;

    ///////////////////////////////////////////////////////////
     SIGN32 MC_Perf_CntStat_drvrd(SIE_MC_Perf_CntStat *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 MC_Perf_CntStat_drvwr(SIE_MC_Perf_CntStat *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void MC_Perf_CntStat_reset(SIE_MC_Perf_CntStat *p);
     SIGN32 MC_Perf_CntStat_cmp  (SIE_MC_Perf_CntStat *p, SIE_MC_Perf_CntStat *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define MC_Perf_CntStat_check(p,pie,pfx,hLOG) MC_Perf_CntStat_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define MC_Perf_CntStat_print(p,    pfx,hLOG) MC_Perf_CntStat_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: MC_Perf_CntStat
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE Secure_Zone                              (4,4)
///     ###
///     * Secure Zone settings
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 REGION_CTRL          (RW)
///               %unsigned 1  Enable                    0x0
///                                    ###
///                                    * When set, enables the region to be checked
///                                    * When clear, the region is not checked
///                                    ###
///               %unsigned 1  Lock                      0x0
///                                    ###
///                                    * When set, locks the registers associated with this region (REGION_MST_CFG, REGION_SADDR, REGION_EADDR, REGION_CTRL). Once set, may only be cleared by a reset
///                                    ###
///               %unsigned 1  NS                        0x0
///                                    ###
///                                    * Establishes the secure/non-secure attribute of the address region.
///                                    * 0: secure, 1: non-secure
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00004 REGION_MST_CFG       (RW)
///               ###
///               * 0 : M3
///               * 1 : A53
///               * 2 : NN, AIO
///               * 3 : Perif, JTAG_AHB, JTAG-CoreSight
///               ###
///               %unsigned 4  S_Read_En                 0xF
///                                    ###
///                                    * When set, each bit enables secure read access by the corresponding bus master (or master group) to the region
///                                    * 0: disable, 1: enable
///                                    ###
///               %unsigned 4  S_Write_En                0xF
///                                    ###
///                                    * When set, each bit enables secure write access by the corresponding bus master (or master group) to the region
///                                    * 0: disable, 1: enable
///                                    ###
///               %unsigned 4  NS_Read_En                0xF
///                                    ###
///                                    * When set, each bit enables non-secure read access by the corresponding bus master (or master group) to the region, if the region is also marked non-secure (NS) in the above control register
///                                    * 0: disable, 1: enable
///                                    ###
///               %unsigned 4  NS_Write_En               0xF
///                                    ###
///                                    * When set, each bit enables non-secure write access by the corresponding bus master (or master group) to the region, if the region is also marked non-secure (NS) in the above control register
///                                    * 0: disable, 1: enable
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00008 REGION_SADDR         (RW)
///               %unsigned 32 Start_Addr                0x0
///     @ 0x0000C REGION_EADDR         (RW)
///               %unsigned 32 End_Addr                  0x0
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      83b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_Secure_Zone
#define h_Secure_Zone (){}

    #define     RA_Secure_Zone_REGION_CTRL                     0x0000

    #define     BA_Secure_Zone_REGION_CTRL_Enable              0x0000
    #define     B16Secure_Zone_REGION_CTRL_Enable              0x0000
    #define   LSb32Secure_Zone_REGION_CTRL_Enable                 0
    #define   LSb16Secure_Zone_REGION_CTRL_Enable                 0
    #define       bSecure_Zone_REGION_CTRL_Enable              1
    #define   MSK32Secure_Zone_REGION_CTRL_Enable                 0x00000001

    #define     BA_Secure_Zone_REGION_CTRL_Lock                0x0000
    #define     B16Secure_Zone_REGION_CTRL_Lock                0x0000
    #define   LSb32Secure_Zone_REGION_CTRL_Lock                   1
    #define   LSb16Secure_Zone_REGION_CTRL_Lock                   1
    #define       bSecure_Zone_REGION_CTRL_Lock                1
    #define   MSK32Secure_Zone_REGION_CTRL_Lock                   0x00000002

    #define     BA_Secure_Zone_REGION_CTRL_NS                  0x0000
    #define     B16Secure_Zone_REGION_CTRL_NS                  0x0000
    #define   LSb32Secure_Zone_REGION_CTRL_NS                     2
    #define   LSb16Secure_Zone_REGION_CTRL_NS                     2
    #define       bSecure_Zone_REGION_CTRL_NS                  1
    #define   MSK32Secure_Zone_REGION_CTRL_NS                     0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_Secure_Zone_REGION_MST_CFG                  0x0004

    #define     BA_Secure_Zone_REGION_MST_CFG_S_Read_En        0x0004
    #define     B16Secure_Zone_REGION_MST_CFG_S_Read_En        0x0004
    #define   LSb32Secure_Zone_REGION_MST_CFG_S_Read_En           0
    #define   LSb16Secure_Zone_REGION_MST_CFG_S_Read_En           0
    #define       bSecure_Zone_REGION_MST_CFG_S_Read_En        4
    #define   MSK32Secure_Zone_REGION_MST_CFG_S_Read_En           0x0000000F

    #define     BA_Secure_Zone_REGION_MST_CFG_S_Write_En       0x0004
    #define     B16Secure_Zone_REGION_MST_CFG_S_Write_En       0x0004
    #define   LSb32Secure_Zone_REGION_MST_CFG_S_Write_En          4
    #define   LSb16Secure_Zone_REGION_MST_CFG_S_Write_En          4
    #define       bSecure_Zone_REGION_MST_CFG_S_Write_En       4
    #define   MSK32Secure_Zone_REGION_MST_CFG_S_Write_En          0x000000F0

    #define     BA_Secure_Zone_REGION_MST_CFG_NS_Read_En       0x0005
    #define     B16Secure_Zone_REGION_MST_CFG_NS_Read_En       0x0004
    #define   LSb32Secure_Zone_REGION_MST_CFG_NS_Read_En          8
    #define   LSb16Secure_Zone_REGION_MST_CFG_NS_Read_En          8
    #define       bSecure_Zone_REGION_MST_CFG_NS_Read_En       4
    #define   MSK32Secure_Zone_REGION_MST_CFG_NS_Read_En          0x00000F00

    #define     BA_Secure_Zone_REGION_MST_CFG_NS_Write_En      0x0005
    #define     B16Secure_Zone_REGION_MST_CFG_NS_Write_En      0x0004
    #define   LSb32Secure_Zone_REGION_MST_CFG_NS_Write_En         12
    #define   LSb16Secure_Zone_REGION_MST_CFG_NS_Write_En         12
    #define       bSecure_Zone_REGION_MST_CFG_NS_Write_En      4
    #define   MSK32Secure_Zone_REGION_MST_CFG_NS_Write_En         0x0000F000
    ///////////////////////////////////////////////////////////
    #define     RA_Secure_Zone_REGION_SADDR                    0x0008

    #define     BA_Secure_Zone_REGION_SADDR_Start_Addr         0x0008
    #define     B16Secure_Zone_REGION_SADDR_Start_Addr         0x0008
    #define   LSb32Secure_Zone_REGION_SADDR_Start_Addr            0
    #define   LSb16Secure_Zone_REGION_SADDR_Start_Addr            0
    #define       bSecure_Zone_REGION_SADDR_Start_Addr         32
    #define   MSK32Secure_Zone_REGION_SADDR_Start_Addr            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Secure_Zone_REGION_EADDR                    0x000C

    #define     BA_Secure_Zone_REGION_EADDR_End_Addr           0x000C
    #define     B16Secure_Zone_REGION_EADDR_End_Addr           0x000C
    #define   LSb32Secure_Zone_REGION_EADDR_End_Addr              0
    #define   LSb16Secure_Zone_REGION_EADDR_End_Addr              0
    #define       bSecure_Zone_REGION_EADDR_End_Addr           32
    #define   MSK32Secure_Zone_REGION_EADDR_End_Addr              0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_Secure_Zone {
    ///////////////////////////////////////////////////////////
    #define   GET32Secure_Zone_REGION_CTRL_Enable(r32)         _BFGET_(r32, 0, 0)
    #define   SET32Secure_Zone_REGION_CTRL_Enable(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16Secure_Zone_REGION_CTRL_Enable(r16)         _BFGET_(r16, 0, 0)
    #define   SET16Secure_Zone_REGION_CTRL_Enable(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32Secure_Zone_REGION_CTRL_Lock(r32)           _BFGET_(r32, 1, 1)
    #define   SET32Secure_Zone_REGION_CTRL_Lock(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16Secure_Zone_REGION_CTRL_Lock(r16)           _BFGET_(r16, 1, 1)
    #define   SET16Secure_Zone_REGION_CTRL_Lock(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32Secure_Zone_REGION_CTRL_NS(r32)             _BFGET_(r32, 2, 2)
    #define   SET32Secure_Zone_REGION_CTRL_NS(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16Secure_Zone_REGION_CTRL_NS(r16)             _BFGET_(r16, 2, 2)
    #define   SET16Secure_Zone_REGION_CTRL_NS(r16,v)           _BFSET_(r16, 2, 2,v)

    #define     w32Secure_Zone_REGION_CTRL                     {\
            UNSG32 uREGION_CTRL_Enable                         :  1;\
            UNSG32 uREGION_CTRL_Lock                           :  1;\
            UNSG32 uREGION_CTRL_NS                             :  1;\
            UNSG32 RSVDx0_b3                                   : 29;\
          }
    union { UNSG32 u32Secure_Zone_REGION_CTRL;
            struct w32Secure_Zone_REGION_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Secure_Zone_REGION_MST_CFG_S_Read_En(r32)   _BFGET_(r32, 3, 0)
    #define   SET32Secure_Zone_REGION_MST_CFG_S_Read_En(r32,v) _BFSET_(r32, 3, 0,v)
    #define   GET16Secure_Zone_REGION_MST_CFG_S_Read_En(r16)   _BFGET_(r16, 3, 0)
    #define   SET16Secure_Zone_REGION_MST_CFG_S_Read_En(r16,v) _BFSET_(r16, 3, 0,v)

    #define   GET32Secure_Zone_REGION_MST_CFG_S_Write_En(r32)  _BFGET_(r32, 7, 4)
    #define   SET32Secure_Zone_REGION_MST_CFG_S_Write_En(r32,v) _BFSET_(r32, 7, 4,v)
    #define   GET16Secure_Zone_REGION_MST_CFG_S_Write_En(r16)  _BFGET_(r16, 7, 4)
    #define   SET16Secure_Zone_REGION_MST_CFG_S_Write_En(r16,v) _BFSET_(r16, 7, 4,v)

    #define   GET32Secure_Zone_REGION_MST_CFG_NS_Read_En(r32)  _BFGET_(r32,11, 8)
    #define   SET32Secure_Zone_REGION_MST_CFG_NS_Read_En(r32,v) _BFSET_(r32,11, 8,v)
    #define   GET16Secure_Zone_REGION_MST_CFG_NS_Read_En(r16)  _BFGET_(r16,11, 8)
    #define   SET16Secure_Zone_REGION_MST_CFG_NS_Read_En(r16,v) _BFSET_(r16,11, 8,v)

    #define   GET32Secure_Zone_REGION_MST_CFG_NS_Write_En(r32) _BFGET_(r32,15,12)
    #define   SET32Secure_Zone_REGION_MST_CFG_NS_Write_En(r32,v) _BFSET_(r32,15,12,v)
    #define   GET16Secure_Zone_REGION_MST_CFG_NS_Write_En(r16) _BFGET_(r16,15,12)
    #define   SET16Secure_Zone_REGION_MST_CFG_NS_Write_En(r16,v) _BFSET_(r16,15,12,v)

    #define     w32Secure_Zone_REGION_MST_CFG                  {\
            UNSG32 uREGION_MST_CFG_S_Read_En                   :  4;\
            UNSG32 uREGION_MST_CFG_S_Write_En                  :  4;\
            UNSG32 uREGION_MST_CFG_NS_Read_En                  :  4;\
            UNSG32 uREGION_MST_CFG_NS_Write_En                 :  4;\
            UNSG32 RSVDx4_b16                                  : 16;\
          }
    union { UNSG32 u32Secure_Zone_REGION_MST_CFG;
            struct w32Secure_Zone_REGION_MST_CFG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Secure_Zone_REGION_SADDR_Start_Addr(r32)    _BFGET_(r32,31, 0)
    #define   SET32Secure_Zone_REGION_SADDR_Start_Addr(r32,v)  _BFSET_(r32,31, 0,v)

    #define     w32Secure_Zone_REGION_SADDR                    {\
            UNSG32 uREGION_SADDR_Start_Addr                    : 32;\
          }
    union { UNSG32 u32Secure_Zone_REGION_SADDR;
            struct w32Secure_Zone_REGION_SADDR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Secure_Zone_REGION_EADDR_End_Addr(r32)      _BFGET_(r32,31, 0)
    #define   SET32Secure_Zone_REGION_EADDR_End_Addr(r32,v)    _BFSET_(r32,31, 0,v)

    #define     w32Secure_Zone_REGION_EADDR                    {\
            UNSG32 uREGION_EADDR_End_Addr                      : 32;\
          }
    union { UNSG32 u32Secure_Zone_REGION_EADDR;
            struct w32Secure_Zone_REGION_EADDR;
          };
    ///////////////////////////////////////////////////////////
    } SIE_Secure_Zone;

    typedef union  T32Secure_Zone_REGION_CTRL
          { UNSG32 u32;
            struct w32Secure_Zone_REGION_CTRL;
                 } T32Secure_Zone_REGION_CTRL;
    typedef union  T32Secure_Zone_REGION_MST_CFG
          { UNSG32 u32;
            struct w32Secure_Zone_REGION_MST_CFG;
                 } T32Secure_Zone_REGION_MST_CFG;
    typedef union  T32Secure_Zone_REGION_SADDR
          { UNSG32 u32;
            struct w32Secure_Zone_REGION_SADDR;
                 } T32Secure_Zone_REGION_SADDR;
    typedef union  T32Secure_Zone_REGION_EADDR
          { UNSG32 u32;
            struct w32Secure_Zone_REGION_EADDR;
                 } T32Secure_Zone_REGION_EADDR;
    ///////////////////////////////////////////////////////////

    typedef union  TSecure_Zone_REGION_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32Secure_Zone_REGION_CTRL;
                   };
                 } TSecure_Zone_REGION_CTRL;
    typedef union  TSecure_Zone_REGION_MST_CFG
          { UNSG32 u32[1];
            struct {
            struct w32Secure_Zone_REGION_MST_CFG;
                   };
                 } TSecure_Zone_REGION_MST_CFG;
    typedef union  TSecure_Zone_REGION_SADDR
          { UNSG32 u32[1];
            struct {
            struct w32Secure_Zone_REGION_SADDR;
                   };
                 } TSecure_Zone_REGION_SADDR;
    typedef union  TSecure_Zone_REGION_EADDR
          { UNSG32 u32[1];
            struct {
            struct w32Secure_Zone_REGION_EADDR;
                   };
                 } TSecure_Zone_REGION_EADDR;

    ///////////////////////////////////////////////////////////
     SIGN32 Secure_Zone_drvrd(SIE_Secure_Zone *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 Secure_Zone_drvwr(SIE_Secure_Zone *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void Secure_Zone_reset(SIE_Secure_Zone *p);
     SIGN32 Secure_Zone_cmp  (SIE_Secure_Zone *p, SIE_Secure_Zone *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define Secure_Zone_check(p,pie,pfx,hLOG) Secure_Zone_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define Secure_Zone_print(p,    pfx,hLOG) Secure_Zone_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: Secure_Zone
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE MC6Ctrl                 biu              (4,4)
///     ###
///     * MC6
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 MC6_4TO1             (P)
///               ###
///               * Registers that selects 4:1/2:1 operation for Memory Controller
///               ###
///               %unsigned 1  enable                    0x1
///                                    ###
///                                    * Unused
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00004                      (P)
///     # 0x00004 memPll               
///               $vsipll              memPll            REG          
///                                    ###
///                                    * Configuration registers for memPll
///                                    ###
///     @ 0x0001C AxiPCntCTRL          (P)
///               ###
///               * 3 Performance counters are implemented.
///               * Bit 0: CA53 CPU
///               * Bit 1 : Shared between NNA and iMTEST
///               * Bit 7 : Shared by all other masters in chip
///               ###
///               %unsigned 8  clear                     0x0
///                                    ###
///                                    * Clear the counters
///                                    ###
///               %unsigned 8  enable                    0x0
///                                    ###
///                                    * Enable the counter increment, SW can make enable = 0 to temporarily disable counter increment
///                                    ###
///               %unsigned 8  latch                     0x0
///                                    ###
///                                    * Counter values are latched on rising edge of this signal
///                                    * Performance Counter support ID mask function. Each performance counter has one ID register and one Mask register.
///                                    * Only the transaction satisfies following equation would be counted:
///                                    * PID & Mask = TID & Mask
///                                    * PID is the programmed ID. TID is the transaction ID.
///                                    * ID mask function can be used for these counters:
///                                    * arwait, rwait, rdata, ridle, await and wdata
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x00020 AxiMst0              (P)
///               %unsigned 16 PID                       0x0
///               %unsigned 16 Mask                      0x0
///     @ 0x00024 AxiMst0DXBAR         (P)
///               %unsigned 16 PID                       0x0
///               %unsigned 16 Mask                      0x0
///     @ 0x00028 AxiMst1              (P)
///               %unsigned 16 PID                       0x0
///               %unsigned 16 Mask                      0x0
///     @ 0x0002C                      (P)
///     # 0x0002C Mstr0PCnt            
///               $AxiPCntStat         Mstr0PCnt         REG          
///                                    ###
///                                    * CA53 AXI interface performance counter
///                                    ###
///     @ 0x00060                      (P)
///     # 0x00060 Mstr0DXBARPCnt       
///               $AxiPCntStat         Mstr0DXBARPCnt    REG          
///                                    ###
///                                    * All masters coming from DXBAR AXI interface performance counter
///                                    ###
///     @ 0x00094                      (P)
///     # 0x00094 Mstr1PCnt            
///               $AxiPCntStat         Mstr1PCnt         REG          
///                                    ###
///                                    * NNA/iMTEST AXI interface performance counter
///                                    ###
///     @ 0x000C8                      (P)
///     # 0x000C8 Region0              
///               $Secure_Zone         Region0           REG          
///     @ 0x000D8                      (P)
///     # 0x000D8 Region1              
///               $Secure_Zone         Region1           REG          
///     @ 0x000E8                      (P)
///     # 0x000E8 Region2              
///               $Secure_Zone         Region2           REG          
///     @ 0x000F8                      (P)
///     # 0x000F8 Region3              
///               $Secure_Zone         Region3           REG          
///     @ 0x00108                      (P)
///     # 0x00108 Region4              
///               $Secure_Zone         Region4           REG          
///     @ 0x00118                      (P)
///     # 0x00118 Region5              
///               $Secure_Zone         Region5           REG          
///     @ 0x00128                      (P)
///     # 0x00128 Region6              
///               $Secure_Zone         Region6           REG          
///     @ 0x00138                      (P)
///     # 0x00138 Region7              
///               $Secure_Zone         Region7           REG          
///     @ 0x00148                      (P)
///     # 0x00148 AxiErrorMon_Mst0     
///               $AxiErrorMon         AxiErrorMon_Mst0  REG          
///                                    ###
///                                    * Memory Controller Axi Interface error detector.
///                                    ###
///     @ 0x00160                      (P)
///     # 0x00160 AxiErrorMon_Mst1     
///               $AxiErrorMon         AxiErrorMon_Mst1  REG          
///                                    ###
///                                    * Memory Controller Axi Interface error detector.
///                                    ###
///     @ 0x00178                      (P)
///     # 0x00178 CA53_Cache           
///               $AxCacheOW           CA53_Cache        REG          
///                                    ###
///                                    * CA53 AxCache control
///                                    ###
///     @ 0x0017C                      (P)
///     # 0x0017C CM3_Cache            
///               $AxCacheOW           CM3_Cache         REG          
///                                    ###
///                                    * CM53 AxCache control
///                                    ###
///     @ 0x00180                      (P)
///     # 0x00180 AIO_Cache            
///               $AxCacheOW           AIO_Cache         REG          
///                                    ###
///                                    * AIO AxCache control
///                                    ###
///     @ 0x00184                      (P)
///     # 0x00184 PXBAR_Cache          
///               $AxCacheOW           PXBAR_Cache       REG          
///                                    ###
///                                    * All Perif masters AxCache control
///                                    ###
///     @ 0x00188                      (P)
///     # 0x00188 NNA_Cache            
///               $AxCacheOW           NNA_Cache         REG          
///                                    ###
///                                    * NNA AxCache control
///                                    ###
///     @ 0x0018C                      (P)
///     # 0x0018C iMTEST_Cache         
///               $AxCacheOW           iMTEST_Cache      REG          
///                                    ###
///                                    * NNA AxCache control
///                                    ###
///     @ 0x00190                      (P)
///     # 0x00190 CA53_QoS             
///               $AxQoSOW             CA53_QoS          REG          
///                                    ###
///                                    * CA53 AXQoS OverWrite Control
///                                    ###
///     @ 0x00194                      (P)
///     # 0x00194 CM3_QoS              
///               $AxQoSOW             CM3_QoS           REG          
///                                    ###
///                                    * CM3 AXQoS OverWrite Control
///                                    ###
///     @ 0x00198                      (P)
///     # 0x00198 AIO_QoS              
///               $AxQoSOW             AIO_QoS           REG          
///                                    ###
///                                    * AIO AXQoS OverWrite Control
///                                    ###
///     @ 0x0019C                      (P)
///     # 0x0019C PCIE_QoS             
///               $AxQoSOW             PCIE_QoS          REG          
///                                    ###
///                                    * PCIE AXQoS OverWrite Control
///                                    ###
///     @ 0x001A0                      (P)
///     # 0x001A0 USB_QoS              
///               $AxQoSOW             USB_QoS           REG          
///                                    ###
///                                    * USB AXQoS OverWrite Control
///                                    ###
///     @ 0x001A4                      (P)
///     # 0x001A4 PXBAR_QoS            
///               $AxQoSOW             PXBAR_QoS         REG          
///                                    ###
///                                    * PXBAR AXQoS OverWrite Control
///                                    ###
///     @ 0x001A8                      (P)
///     # 0x001A8 NNA_QoS              
///               $AxQoSOW             NNA_QoS           REG          
///                                    ###
///                                    * NNA AXQoS OverWrite Control
///                                    ###
///     @ 0x001AC                      (P)
///     # 0x001AC iMTEST_QoS           
///               $AxQoSOW             iMTEST_QoS        REG          
///                                    ###
///                                    * IMTEST AXQoS OverWrite Control
///                                    ###
///     @ 0x001B0 DdrAsymCtrlCpu       (P)
///               %unsigned 8  Mode                      0x0
///                                    ###
///                                    * This register controls cpu asymmetric bridge in soc
///                                    * Operation Mode:
///                                    * 0: Symmetric
///                                    * 1: 512MB + 256MB
///                                    * 2: 1GB + 512MB
///                                    * 3: 512MB +128MB
///                                    * 4: 1GB + 256MB
///                                    * 5: 2GB + 512MB
///                                    * 6: 2GB + 1GB
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x001B4 DdrAsymCtrlNxbar     (P)
///               %unsigned 8  Mode                      0x0
///                                    ###
///                                    * This register controls NXBAR asymmetric bridge in soc
///                                    * Operation Mode:
///                                    * 0: Symmetric
///                                    * 1: 512MB + 256MB
///                                    * 2: 1GB + 512MB
///                                    * 3: 512MB +128MB
///                                    * 4: 1GB + 256MB
///                                    * 5: 2GB + 512MB
///                                    * 6: 2GB + 1GB
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x001B8 DdrAsymErrCpu        (R-)
///               %unsigned 32 Code                      0x0
///     @ 0x001BC DdrAsymErrNxbar      (R-)
///               %unsigned 32 Code                      0x0
///     @ 0x001C0 perf_log_cnt_ctrl    (P)
///               %unsigned 8  clear                     0x0
///                                    ###
///                                    * Clear the counters
///                                    ###
///               %unsigned 8  enable                    0x0
///                                    ###
///                                    * Enable the counter increment, SW can make enable = 0 to temporarily disable counter increment
///                                    ###
///               %unsigned 8  latch                     0x0
///                                    ###
///                                    * Counter values are latched on rising edge of this signal
///                                    ###
///               %unsigned 3  clk_div                   0x0
///                                    ###
///                                    * Clock divider for clock cycle counter
///                                    * 0x0	Divide clock by 1
///                                    * 0x1	Divide clock by 2
///                                    * 0x2	Divide clock by 4
///                                    * 0x3	Divide clock by 8
///                                    * 0x4	Divide clock by 16
///                                    * 0x5	Divide clock by 32
///                                    * 0x6	Divide clock by 64
///                                    * 0x7	Divide clock by 128
///                                    ###
///               %%        5          # Stuffing bits...
///     # 0x001C4 perf_log_cnt_ctrl1   
///               %unsigned 6  pc0_event_sel             0x0
///                                    ###
///                                    * 0x0 : Clock cycles
///                                    * 0x1 : perf_hif_rd_or_wr
///                                    * 0x2 : perf_hif_wr
///                                    * 0x3 : perf_hif_rd
///                                    * 0x4 : perf_hif_rmw
///                                    * 0x5 : perf_hif_hi_pri_rd
///                                    * 0x6 : perf_dfi_wr_data_cycles
///                                    * 0x7 : perf_dfi_rd_data_cycles
///                                    * 0x8 : perf_hpr_xact_when_critical
///                                    * 0x9 : perf_lpr_xact_when_critical
///                                    * 0xa : perf_wr_xact_when_critical
///                                    * 0xb : perf_op_is_activate
///                                    * 0xc : perf_op_is_rd_or_wr
///                                    * 0xd : perf_op_is_rd_activate
///                                    * 0xe : perf_op_is_rd
///                                    * 0xf : perf_op_is_wr
///                                    * 0x10 : perf_op_is_precharge
///                                    * 0x11 : perf_precharge_for_rdwr
///                                    * 0x12 : perf_precharge_for_other
///                                    * 0x13 : perf_rdwr_transitions
///                                    * 0x14 : perf_write_combine
///                                    * 0x15 : perf_war_hazard
///                                    * 0x16 : perf_raw_hazard
///                                    * 0x17 : perf_waw_hazard
///                                    * 0x18 : perf_op_is_enter_selfref
///                                    * 0x19 : perf_op_is_enter_powerdown
///                                    * 0x1a : perf_selfref_mode
///                                    * 0x1b : perf_op_is_refresh
///                                    * 0x1c : perf_op_is_crit_ref
///                                    * 0x1d : perf_op_is_spec_ref
///                                    * 0x1e : perf_op_is_load_mode
///                                    * 0x1f : perf_op_is_zqcl
///                                    * 0x20 : perf_op_is_zqcs
///                                    * 0x21 : perf_hpr_req_with_nocredit
///                                    * 0x22 : perf_lpr_req_with_nocredit
///                                    * 0x23 : PHY DSCL over threshold counter
///                                    * 0x24 : dfi_phymstr_req count
///                                    * 0x25 : dfi_phymstr_ack count
///                                    * 0x26 : dfi_ctrlupd_req count
///                                    * 0x27 : dfi_ctrlupd_ack count
///                                    * 0x28 : dfi_phymstr_req high duration count
///                                    * 0x29 : dfi_ctrlupd_req high duration count
///                                    ###
///               %unsigned 6  pc1_event_sel             0x0
///               %unsigned 6  pc2_event_sel             0x0
///               %unsigned 6  pc3_event_sel             0x0
///               %unsigned 6  pc4_event_sel             0x0
///               %%        2          # Stuffing bits...
///     # 0x001C8 perf_log_cnt_ctrl2   
///               %unsigned 6  pc5_event_sel             0x0
///               %unsigned 6  pc6_event_sel             0x0
///               %unsigned 6  pc7_event_sel             0x0
///               %%        14         # Stuffing bits...
///     @ 0x001CC perf_log_cnt_ready   (R-)
///               %unsigned 8  cnt                       0x0
///                                    ###
///                                    * This bit is set by HW when counter values are latched and it's ok for SW to read the counter
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x001D0                      (P)
///     # 0x001D0 pc0                  
///               $MC_Perf_CntStat     pc0               REG          
///                                    ###
///                                    * Performance counter0
///                                    ###
///     @ 0x001D8                      (P)
///     # 0x001D8 pc1                  
///               $MC_Perf_CntStat     pc1               REG          
///     @ 0x001E0                      (P)
///     # 0x001E0 pc2                  
///               $MC_Perf_CntStat     pc2               REG          
///     @ 0x001E8                      (P)
///     # 0x001E8 pc3                  
///               $MC_Perf_CntStat     pc3               REG          
///     @ 0x001F0                      (P)
///     # 0x001F0 pc4                  
///               $MC_Perf_CntStat     pc4               REG          
///     @ 0x001F8                      (P)
///     # 0x001F8 pc5                  
///               $MC_Perf_CntStat     pc5               REG          
///     @ 0x00200                      (P)
///     # 0x00200 pc6                  
///               $MC_Perf_CntStat     pc6               REG          
///     @ 0x00208                      (P)
///     # 0x00208 pc7                  
///               $MC_Perf_CntStat     pc7               REG          
///     @ 0x00210 phy_ctrl             (P)
///               %unsigned 1  turn_off_addrctrl_drivers 0x0
///               %unsigned 1  turn_on_ie                0x0
///               %%        30         # Stuffing bits...
///     @ 0x00214 AxUrgent_0           (P)
///               %unsigned 2  read                      0x0
///                                    ###
///                                    * AXI Read Urgent. Sideband signal to indicate a urgent transaction. When asserted, if rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. It can be asserted anytime, it's not associated to any particular command
///                                    * [0] : blue queue
///                                    * [1] : red queue
///                                    ###
///               %unsigned 1  write                     0x0
///                                    ###
///                                    * AXI Write Urgent. Sideband signal to indicate a write urgent transaction.
///                                    * When asserted, if wr_port_urgent_en register is set, causes the port
///                                    * arbiter to switch immediately to write. It can be asserted anytime, it's not
///                                    * associated to any particular command
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00218 AxUrgent_1           (P)
///               %unsigned 2  read                      0x0
///                                    ###
///                                    * AXI Read Urgent. Sideband signal to indicate a urgent transaction. When asserted, if rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. It can be asserted anytime, it's not associated to any particular command
///                                    * [0] : blue queue
///                                    * [1] : red queue
///                                    ###
///               %unsigned 1  write                     0x0
///                                    ###
///                                    * AXI Write Urgent. Sideband signal to indicate a write urgent transaction.
///                                    * When asserted, if wr_port_urgent_en register is set, causes the port
///                                    * arbiter to switch immediately to write. It can be asserted anytime, it's not
///                                    * associated to any particular command
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x0021C low_pwr_ifc          (RW)
///               %unsigned 1  axi0_lp_req               0x1
///               %unsigned 1  axi0_lp_ack               0x1
///               %unsigned 1  axi0_lp_active            0x1
///               %unsigned 1  axi1_lp_req               0x1
///               %unsigned 1  axi1_lp_ack               0x1
///               %unsigned 1  axi1_lp_active            0x1
///               %unsigned 1  hw_lp_req                 0x1
///               %unsigned 1  hw_lp_ack                 0x1
///               %unsigned 1  hw_lp_active              0x1
///               %unsigned 2  selfref_type              0x0
///               %%        21         # Stuffing bits...
///     @ 0x00220 port_arbiter         (P)
///               %unsigned 2  rmask_0                   0x0
///               %unsigned 2  rmask_1                   0x0
///               %unsigned 1  wmask_0                   0x0
///               %unsigned 1  wmask_1                   0x0
///               %%        26         # Stuffing bits...
///     @ 0x00224 unq_ddr_dfi_phymstr_ctrl (P)
///               %unsigned 1  phymstr_en                0x0
///                                    ###
///                                    * 1: will enable the unq_ddr_dfi_phymstr module
///                                    ###
///               %unsigned 1  srx_dscl_en               0x0
///                                    ###
///                                    * 1 : run DSCL after SRX
///                                    * 0 : don't run DSCL after SRX
///                                    ###
///               %%        30         # Stuffing bits...
///     # 0x00228 unq_ddr_dfi_phymstr_ctrl1 
///               %unsigned 32 dscl_interval             0x0
///                                    ###
///                                    * DSCL run interval in multiples of 1024 DFI clocks
///                                    ###
///     # 0x0022C unq_ddr_dfi_phymstr_ctrl2 
///               %unsigned 10 dfi_hsk_wait              0x0
///                                    ###
///                                    * DFI controller update handshake wait time. It equals DRAM tRFC timing parameter in DFI clock cycles
///                                    ###
///               %unsigned 16 ctrlupd_min_timeout       0x0
///                                    ###
///                                    * Max number of DFI clock cycles within which PHY should acknowledge dfi_ctrlupd_req
///                                    * 16'b0 : disable timeout check
///                                    * Other value : timeout value
///                                    * can be 20DFI cycles
///                                    ###
///               %%        6          # Stuffing bits...
///     # 0x00230 unq_ddr_dfi_phymstr_ctrl3 
///               %unsigned 16 ctrlupd_max_timeout       0x0
///                                    ###
///                                    * Max number of DFI clock cycles for which PHY may keep dfi_ctrlupd_ack asserted
///                                    * 16'b0:disable timeout check
///                                    * other value:timeout value
///                                    ###
///               %unsigned 16 phymstr_resp_timeout      0x0
///                                    ###
///                                    * Max number of DFI clock cycles within which controller should acknowledge dfi_phymstr_req
///                                    * 16'b0:disable timeout check
///                                    * other value:timeout value
///                                    ###
///     # 0x00234 unq_ddr_dfi_phymstr_ctrl4 
///               %unsigned 16 dscl_thres                0x0
///                                    ###
///                                    * PHY DSCL threshold setting. If the DSCL flow run time goes over the value, the overflow counter will increase by 1
///                                    ###
///               %unsigned 1  dscl_overflow_en          0x0
///                                    ###
///                                    * Enable PHY DSCL over threshold counter
///                                    * 1: Enable counter
///                                    * 0: Clear counter to 0
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00238 unq_ddr_dfi_phymstr_stat (R-)
///               %unsigned 2  current_state             0x0
///                                    ###
///                                    * State machine current state for debugging state machine hang.
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     572B, bits:    2816b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MC6Ctrl
#define h_MC6Ctrl (){}

    #define     RA_MC6Ctrl_MC6_4TO1                            0x0000

    #define     BA_MC6Ctrl_MC6_4TO1_enable                     0x0000
    #define     B16MC6Ctrl_MC6_4TO1_enable                     0x0000
    #define   LSb32MC6Ctrl_MC6_4TO1_enable                        0
    #define   LSb16MC6Ctrl_MC6_4TO1_enable                        0
    #define       bMC6Ctrl_MC6_4TO1_enable                     1
    #define   MSK32MC6Ctrl_MC6_4TO1_enable                        0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_memPll                              0x0004
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxiPCntCTRL                         0x001C

    #define     BA_MC6Ctrl_AxiPCntCTRL_clear                   0x001C
    #define     B16MC6Ctrl_AxiPCntCTRL_clear                   0x001C
    #define   LSb32MC6Ctrl_AxiPCntCTRL_clear                      0
    #define   LSb16MC6Ctrl_AxiPCntCTRL_clear                      0
    #define       bMC6Ctrl_AxiPCntCTRL_clear                   8
    #define   MSK32MC6Ctrl_AxiPCntCTRL_clear                      0x000000FF

    #define     BA_MC6Ctrl_AxiPCntCTRL_enable                  0x001D
    #define     B16MC6Ctrl_AxiPCntCTRL_enable                  0x001C
    #define   LSb32MC6Ctrl_AxiPCntCTRL_enable                     8
    #define   LSb16MC6Ctrl_AxiPCntCTRL_enable                     8
    #define       bMC6Ctrl_AxiPCntCTRL_enable                  8
    #define   MSK32MC6Ctrl_AxiPCntCTRL_enable                     0x0000FF00

    #define     BA_MC6Ctrl_AxiPCntCTRL_latch                   0x001E
    #define     B16MC6Ctrl_AxiPCntCTRL_latch                   0x001E
    #define   LSb32MC6Ctrl_AxiPCntCTRL_latch                      16
    #define   LSb16MC6Ctrl_AxiPCntCTRL_latch                      0
    #define       bMC6Ctrl_AxiPCntCTRL_latch                   8
    #define   MSK32MC6Ctrl_AxiPCntCTRL_latch                      0x00FF0000
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxiMst0                             0x0020

    #define     BA_MC6Ctrl_AxiMst0_PID                         0x0020
    #define     B16MC6Ctrl_AxiMst0_PID                         0x0020
    #define   LSb32MC6Ctrl_AxiMst0_PID                            0
    #define   LSb16MC6Ctrl_AxiMst0_PID                            0
    #define       bMC6Ctrl_AxiMst0_PID                         16
    #define   MSK32MC6Ctrl_AxiMst0_PID                            0x0000FFFF

    #define     BA_MC6Ctrl_AxiMst0_Mask                        0x0022
    #define     B16MC6Ctrl_AxiMst0_Mask                        0x0022
    #define   LSb32MC6Ctrl_AxiMst0_Mask                           16
    #define   LSb16MC6Ctrl_AxiMst0_Mask                           0
    #define       bMC6Ctrl_AxiMst0_Mask                        16
    #define   MSK32MC6Ctrl_AxiMst0_Mask                           0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxiMst0DXBAR                        0x0024

    #define     BA_MC6Ctrl_AxiMst0DXBAR_PID                    0x0024
    #define     B16MC6Ctrl_AxiMst0DXBAR_PID                    0x0024
    #define   LSb32MC6Ctrl_AxiMst0DXBAR_PID                       0
    #define   LSb16MC6Ctrl_AxiMst0DXBAR_PID                       0
    #define       bMC6Ctrl_AxiMst0DXBAR_PID                    16
    #define   MSK32MC6Ctrl_AxiMst0DXBAR_PID                       0x0000FFFF

    #define     BA_MC6Ctrl_AxiMst0DXBAR_Mask                   0x0026
    #define     B16MC6Ctrl_AxiMst0DXBAR_Mask                   0x0026
    #define   LSb32MC6Ctrl_AxiMst0DXBAR_Mask                      16
    #define   LSb16MC6Ctrl_AxiMst0DXBAR_Mask                      0
    #define       bMC6Ctrl_AxiMst0DXBAR_Mask                   16
    #define   MSK32MC6Ctrl_AxiMst0DXBAR_Mask                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxiMst1                             0x0028

    #define     BA_MC6Ctrl_AxiMst1_PID                         0x0028
    #define     B16MC6Ctrl_AxiMst1_PID                         0x0028
    #define   LSb32MC6Ctrl_AxiMst1_PID                            0
    #define   LSb16MC6Ctrl_AxiMst1_PID                            0
    #define       bMC6Ctrl_AxiMst1_PID                         16
    #define   MSK32MC6Ctrl_AxiMst1_PID                            0x0000FFFF

    #define     BA_MC6Ctrl_AxiMst1_Mask                        0x002A
    #define     B16MC6Ctrl_AxiMst1_Mask                        0x002A
    #define   LSb32MC6Ctrl_AxiMst1_Mask                           16
    #define   LSb16MC6Ctrl_AxiMst1_Mask                           0
    #define       bMC6Ctrl_AxiMst1_Mask                        16
    #define   MSK32MC6Ctrl_AxiMst1_Mask                           0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Mstr0PCnt                           0x002C
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Mstr0DXBARPCnt                      0x0060
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Mstr1PCnt                           0x0094
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region0                             0x00C8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region1                             0x00D8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region2                             0x00E8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region3                             0x00F8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region4                             0x0108
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region5                             0x0118
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region6                             0x0128
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_Region7                             0x0138
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxiErrorMon_Mst0                    0x0148
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxiErrorMon_Mst1                    0x0160
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_CA53_Cache                          0x0178
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_CM3_Cache                           0x017C
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AIO_Cache                           0x0180
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_PXBAR_Cache                         0x0184
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_NNA_Cache                           0x0188
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_iMTEST_Cache                        0x018C
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_CA53_QoS                            0x0190
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_CM3_QoS                             0x0194
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AIO_QoS                             0x0198
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_PCIE_QoS                            0x019C
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_USB_QoS                             0x01A0
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_PXBAR_QoS                           0x01A4
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_NNA_QoS                             0x01A8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_iMTEST_QoS                          0x01AC
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_DdrAsymCtrlCpu                      0x01B0

    #define     BA_MC6Ctrl_DdrAsymCtrlCpu_Mode                 0x01B0
    #define     B16MC6Ctrl_DdrAsymCtrlCpu_Mode                 0x01B0
    #define   LSb32MC6Ctrl_DdrAsymCtrlCpu_Mode                    0
    #define   LSb16MC6Ctrl_DdrAsymCtrlCpu_Mode                    0
    #define       bMC6Ctrl_DdrAsymCtrlCpu_Mode                 8
    #define   MSK32MC6Ctrl_DdrAsymCtrlCpu_Mode                    0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_DdrAsymCtrlNxbar                    0x01B4

    #define     BA_MC6Ctrl_DdrAsymCtrlNxbar_Mode               0x01B4
    #define     B16MC6Ctrl_DdrAsymCtrlNxbar_Mode               0x01B4
    #define   LSb32MC6Ctrl_DdrAsymCtrlNxbar_Mode                  0
    #define   LSb16MC6Ctrl_DdrAsymCtrlNxbar_Mode                  0
    #define       bMC6Ctrl_DdrAsymCtrlNxbar_Mode               8
    #define   MSK32MC6Ctrl_DdrAsymCtrlNxbar_Mode                  0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_DdrAsymErrCpu                       0x01B8

    #define     BA_MC6Ctrl_DdrAsymErrCpu_Code                  0x01B8
    #define     B16MC6Ctrl_DdrAsymErrCpu_Code                  0x01B8
    #define   LSb32MC6Ctrl_DdrAsymErrCpu_Code                     0
    #define   LSb16MC6Ctrl_DdrAsymErrCpu_Code                     0
    #define       bMC6Ctrl_DdrAsymErrCpu_Code                  32
    #define   MSK32MC6Ctrl_DdrAsymErrCpu_Code                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_DdrAsymErrNxbar                     0x01BC

    #define     BA_MC6Ctrl_DdrAsymErrNxbar_Code                0x01BC
    #define     B16MC6Ctrl_DdrAsymErrNxbar_Code                0x01BC
    #define   LSb32MC6Ctrl_DdrAsymErrNxbar_Code                   0
    #define   LSb16MC6Ctrl_DdrAsymErrNxbar_Code                   0
    #define       bMC6Ctrl_DdrAsymErrNxbar_Code                32
    #define   MSK32MC6Ctrl_DdrAsymErrNxbar_Code                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_perf_log_cnt_ctrl                   0x01C0

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_clear             0x01C0
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_clear             0x01C0
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_clear                0
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_clear                0
    #define       bMC6Ctrl_perf_log_cnt_ctrl_clear             8
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_clear                0x000000FF

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_enable            0x01C1
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_enable            0x01C0
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_enable               8
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_enable               8
    #define       bMC6Ctrl_perf_log_cnt_ctrl_enable            8
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_enable               0x0000FF00

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_latch             0x01C2
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_latch             0x01C2
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_latch                16
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_latch                0
    #define       bMC6Ctrl_perf_log_cnt_ctrl_latch             8
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_latch                0x00FF0000

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_clk_div           0x01C3
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_clk_div           0x01C2
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_clk_div              24
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_clk_div              8
    #define       bMC6Ctrl_perf_log_cnt_ctrl_clk_div           3
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_clk_div              0x07000000

    #define     RA_MC6Ctrl_perf_log_cnt_ctrl1                  0x01C4

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel     0x01C4
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel     0x01C4
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel        0
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel        0
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel        0x0000003F

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel     0x01C4
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel     0x01C4
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel        6
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel        6
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel        0x00000FC0

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel     0x01C5
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel     0x01C4
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel        12
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel        12
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel        0x0003F000

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel     0x01C6
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel     0x01C6
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel        18
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel        2
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel        0x00FC0000

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel     0x01C7
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel     0x01C6
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel        24
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel        8
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel        0x3F000000

    #define     RA_MC6Ctrl_perf_log_cnt_ctrl2                  0x01C8

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel     0x01C8
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel     0x01C8
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel        0
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel        0
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel        0x0000003F

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel     0x01C8
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel     0x01C8
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel        6
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel        6
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel        0x00000FC0

    #define     BA_MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel     0x01C9
    #define     B16MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel     0x01C8
    #define   LSb32MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel        12
    #define   LSb16MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel        12
    #define       bMC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel     6
    #define   MSK32MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel        0x0003F000
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_perf_log_cnt_ready                  0x01CC

    #define     BA_MC6Ctrl_perf_log_cnt_ready_cnt              0x01CC
    #define     B16MC6Ctrl_perf_log_cnt_ready_cnt              0x01CC
    #define   LSb32MC6Ctrl_perf_log_cnt_ready_cnt                 0
    #define   LSb16MC6Ctrl_perf_log_cnt_ready_cnt                 0
    #define       bMC6Ctrl_perf_log_cnt_ready_cnt              8
    #define   MSK32MC6Ctrl_perf_log_cnt_ready_cnt                 0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc0                                 0x01D0
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc1                                 0x01D8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc2                                 0x01E0
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc3                                 0x01E8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc4                                 0x01F0
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc5                                 0x01F8
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc6                                 0x0200
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_pc7                                 0x0208
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_phy_ctrl                            0x0210

    #define     BA_MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers  0x0210
    #define     B16MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers  0x0210
    #define   LSb32MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers     0
    #define   LSb16MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers     0
    #define       bMC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers  1
    #define   MSK32MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers     0x00000001

    #define     BA_MC6Ctrl_phy_ctrl_turn_on_ie                 0x0210
    #define     B16MC6Ctrl_phy_ctrl_turn_on_ie                 0x0210
    #define   LSb32MC6Ctrl_phy_ctrl_turn_on_ie                    1
    #define   LSb16MC6Ctrl_phy_ctrl_turn_on_ie                    1
    #define       bMC6Ctrl_phy_ctrl_turn_on_ie                 1
    #define   MSK32MC6Ctrl_phy_ctrl_turn_on_ie                    0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxUrgent_0                          0x0214

    #define     BA_MC6Ctrl_AxUrgent_0_read                     0x0214
    #define     B16MC6Ctrl_AxUrgent_0_read                     0x0214
    #define   LSb32MC6Ctrl_AxUrgent_0_read                        0
    #define   LSb16MC6Ctrl_AxUrgent_0_read                        0
    #define       bMC6Ctrl_AxUrgent_0_read                     2
    #define   MSK32MC6Ctrl_AxUrgent_0_read                        0x00000003

    #define     BA_MC6Ctrl_AxUrgent_0_write                    0x0214
    #define     B16MC6Ctrl_AxUrgent_0_write                    0x0214
    #define   LSb32MC6Ctrl_AxUrgent_0_write                       2
    #define   LSb16MC6Ctrl_AxUrgent_0_write                       2
    #define       bMC6Ctrl_AxUrgent_0_write                    1
    #define   MSK32MC6Ctrl_AxUrgent_0_write                       0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_AxUrgent_1                          0x0218

    #define     BA_MC6Ctrl_AxUrgent_1_read                     0x0218
    #define     B16MC6Ctrl_AxUrgent_1_read                     0x0218
    #define   LSb32MC6Ctrl_AxUrgent_1_read                        0
    #define   LSb16MC6Ctrl_AxUrgent_1_read                        0
    #define       bMC6Ctrl_AxUrgent_1_read                     2
    #define   MSK32MC6Ctrl_AxUrgent_1_read                        0x00000003

    #define     BA_MC6Ctrl_AxUrgent_1_write                    0x0218
    #define     B16MC6Ctrl_AxUrgent_1_write                    0x0218
    #define   LSb32MC6Ctrl_AxUrgent_1_write                       2
    #define   LSb16MC6Ctrl_AxUrgent_1_write                       2
    #define       bMC6Ctrl_AxUrgent_1_write                    1
    #define   MSK32MC6Ctrl_AxUrgent_1_write                       0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_low_pwr_ifc                         0x021C

    #define     BA_MC6Ctrl_low_pwr_ifc_axi0_lp_req             0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_axi0_lp_req             0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_axi0_lp_req                0
    #define   LSb16MC6Ctrl_low_pwr_ifc_axi0_lp_req                0
    #define       bMC6Ctrl_low_pwr_ifc_axi0_lp_req             1
    #define   MSK32MC6Ctrl_low_pwr_ifc_axi0_lp_req                0x00000001

    #define     BA_MC6Ctrl_low_pwr_ifc_axi0_lp_ack             0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_axi0_lp_ack             0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_axi0_lp_ack                1
    #define   LSb16MC6Ctrl_low_pwr_ifc_axi0_lp_ack                1
    #define       bMC6Ctrl_low_pwr_ifc_axi0_lp_ack             1
    #define   MSK32MC6Ctrl_low_pwr_ifc_axi0_lp_ack                0x00000002

    #define     BA_MC6Ctrl_low_pwr_ifc_axi0_lp_active          0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_axi0_lp_active          0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_axi0_lp_active             2
    #define   LSb16MC6Ctrl_low_pwr_ifc_axi0_lp_active             2
    #define       bMC6Ctrl_low_pwr_ifc_axi0_lp_active          1
    #define   MSK32MC6Ctrl_low_pwr_ifc_axi0_lp_active             0x00000004

    #define     BA_MC6Ctrl_low_pwr_ifc_axi1_lp_req             0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_axi1_lp_req             0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_axi1_lp_req                3
    #define   LSb16MC6Ctrl_low_pwr_ifc_axi1_lp_req                3
    #define       bMC6Ctrl_low_pwr_ifc_axi1_lp_req             1
    #define   MSK32MC6Ctrl_low_pwr_ifc_axi1_lp_req                0x00000008

    #define     BA_MC6Ctrl_low_pwr_ifc_axi1_lp_ack             0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_axi1_lp_ack             0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_axi1_lp_ack                4
    #define   LSb16MC6Ctrl_low_pwr_ifc_axi1_lp_ack                4
    #define       bMC6Ctrl_low_pwr_ifc_axi1_lp_ack             1
    #define   MSK32MC6Ctrl_low_pwr_ifc_axi1_lp_ack                0x00000010

    #define     BA_MC6Ctrl_low_pwr_ifc_axi1_lp_active          0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_axi1_lp_active          0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_axi1_lp_active             5
    #define   LSb16MC6Ctrl_low_pwr_ifc_axi1_lp_active             5
    #define       bMC6Ctrl_low_pwr_ifc_axi1_lp_active          1
    #define   MSK32MC6Ctrl_low_pwr_ifc_axi1_lp_active             0x00000020

    #define     BA_MC6Ctrl_low_pwr_ifc_hw_lp_req               0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_hw_lp_req               0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_hw_lp_req                  6
    #define   LSb16MC6Ctrl_low_pwr_ifc_hw_lp_req                  6
    #define       bMC6Ctrl_low_pwr_ifc_hw_lp_req               1
    #define   MSK32MC6Ctrl_low_pwr_ifc_hw_lp_req                  0x00000040

    #define     BA_MC6Ctrl_low_pwr_ifc_hw_lp_ack               0x021C
    #define     B16MC6Ctrl_low_pwr_ifc_hw_lp_ack               0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_hw_lp_ack                  7
    #define   LSb16MC6Ctrl_low_pwr_ifc_hw_lp_ack                  7
    #define       bMC6Ctrl_low_pwr_ifc_hw_lp_ack               1
    #define   MSK32MC6Ctrl_low_pwr_ifc_hw_lp_ack                  0x00000080

    #define     BA_MC6Ctrl_low_pwr_ifc_hw_lp_active            0x021D
    #define     B16MC6Ctrl_low_pwr_ifc_hw_lp_active            0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_hw_lp_active               8
    #define   LSb16MC6Ctrl_low_pwr_ifc_hw_lp_active               8
    #define       bMC6Ctrl_low_pwr_ifc_hw_lp_active            1
    #define   MSK32MC6Ctrl_low_pwr_ifc_hw_lp_active               0x00000100

    #define     BA_MC6Ctrl_low_pwr_ifc_selfref_type            0x021D
    #define     B16MC6Ctrl_low_pwr_ifc_selfref_type            0x021C
    #define   LSb32MC6Ctrl_low_pwr_ifc_selfref_type               9
    #define   LSb16MC6Ctrl_low_pwr_ifc_selfref_type               9
    #define       bMC6Ctrl_low_pwr_ifc_selfref_type            2
    #define   MSK32MC6Ctrl_low_pwr_ifc_selfref_type               0x00000600
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_port_arbiter                        0x0220

    #define     BA_MC6Ctrl_port_arbiter_rmask_0                0x0220
    #define     B16MC6Ctrl_port_arbiter_rmask_0                0x0220
    #define   LSb32MC6Ctrl_port_arbiter_rmask_0                   0
    #define   LSb16MC6Ctrl_port_arbiter_rmask_0                   0
    #define       bMC6Ctrl_port_arbiter_rmask_0                2
    #define   MSK32MC6Ctrl_port_arbiter_rmask_0                   0x00000003

    #define     BA_MC6Ctrl_port_arbiter_rmask_1                0x0220
    #define     B16MC6Ctrl_port_arbiter_rmask_1                0x0220
    #define   LSb32MC6Ctrl_port_arbiter_rmask_1                   2
    #define   LSb16MC6Ctrl_port_arbiter_rmask_1                   2
    #define       bMC6Ctrl_port_arbiter_rmask_1                2
    #define   MSK32MC6Ctrl_port_arbiter_rmask_1                   0x0000000C

    #define     BA_MC6Ctrl_port_arbiter_wmask_0                0x0220
    #define     B16MC6Ctrl_port_arbiter_wmask_0                0x0220
    #define   LSb32MC6Ctrl_port_arbiter_wmask_0                   4
    #define   LSb16MC6Ctrl_port_arbiter_wmask_0                   4
    #define       bMC6Ctrl_port_arbiter_wmask_0                1
    #define   MSK32MC6Ctrl_port_arbiter_wmask_0                   0x00000010

    #define     BA_MC6Ctrl_port_arbiter_wmask_1                0x0220
    #define     B16MC6Ctrl_port_arbiter_wmask_1                0x0220
    #define   LSb32MC6Ctrl_port_arbiter_wmask_1                   5
    #define   LSb16MC6Ctrl_port_arbiter_wmask_1                   5
    #define       bMC6Ctrl_port_arbiter_wmask_1                1
    #define   MSK32MC6Ctrl_port_arbiter_wmask_1                   0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl            0x0224

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en 0x0224
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en 0x0224
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en    0
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en 1
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en    0x00000001

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en 0x0224
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en 0x0224
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en    1
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en    1
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en 1
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en    0x00000002

    #define     RA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1           0x0228

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval 0x0228
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval 0x0228
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval    0
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval 32
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval    0xFFFFFFFF

    #define     RA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2           0x022C

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait 0x022C
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait 0x022C
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait    0
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait 10
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait    0x000003FF

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout 0x022D
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout 0x022C
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout    10
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout    10
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout 16
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout    0x03FFFC00

    #define     RA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3           0x0230

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout 0x0230
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout 0x0230
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout    0
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout 16
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout    0x0000FFFF

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout 0x0232
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout 0x0232
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout    16
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout 16
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout    0xFFFF0000

    #define     RA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4           0x0234

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres 0x0234
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres 0x0234
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres    0
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres 16
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres    0x0000FFFF

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en 0x0236
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en 0x0236
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en    16
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en 1
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en    0x00010000
    ///////////////////////////////////////////////////////////
    #define     RA_MC6Ctrl_unq_ddr_dfi_phymstr_stat            0x0238

    #define     BA_MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state 0x0238
    #define     B16MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state 0x0238
    #define   LSb32MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state    0
    #define   LSb16MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state    0
    #define       bMC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state 2
    #define   MSK32MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state    0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_MC6Ctrl {
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_MC6_4TO1_enable(r32)                _BFGET_(r32, 0, 0)
    #define   SET32MC6Ctrl_MC6_4TO1_enable(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16MC6Ctrl_MC6_4TO1_enable(r16)                _BFGET_(r16, 0, 0)
    #define   SET16MC6Ctrl_MC6_4TO1_enable(r16,v)              _BFSET_(r16, 0, 0,v)

    #define     w32MC6Ctrl_MC6_4TO1                            {\
            UNSG32 uMC6_4TO1_enable                            :  1;\
            UNSG32 RSVDx0_b1                                   : 31;\
          }
    union { UNSG32 u32MC6Ctrl_MC6_4TO1;
            struct w32MC6Ctrl_MC6_4TO1;
          };
    ///////////////////////////////////////////////////////////
              SIE_vsipll                                       ie_memPll;
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_AxiPCntCTRL_clear(r32)              _BFGET_(r32, 7, 0)
    #define   SET32MC6Ctrl_AxiPCntCTRL_clear(r32,v)            _BFSET_(r32, 7, 0,v)
    #define   GET16MC6Ctrl_AxiPCntCTRL_clear(r16)              _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_AxiPCntCTRL_clear(r16,v)            _BFSET_(r16, 7, 0,v)

    #define   GET32MC6Ctrl_AxiPCntCTRL_enable(r32)             _BFGET_(r32,15, 8)
    #define   SET32MC6Ctrl_AxiPCntCTRL_enable(r32,v)           _BFSET_(r32,15, 8,v)
    #define   GET16MC6Ctrl_AxiPCntCTRL_enable(r16)             _BFGET_(r16,15, 8)
    #define   SET16MC6Ctrl_AxiPCntCTRL_enable(r16,v)           _BFSET_(r16,15, 8,v)

    #define   GET32MC6Ctrl_AxiPCntCTRL_latch(r32)              _BFGET_(r32,23,16)
    #define   SET32MC6Ctrl_AxiPCntCTRL_latch(r32,v)            _BFSET_(r32,23,16,v)
    #define   GET16MC6Ctrl_AxiPCntCTRL_latch(r16)              _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_AxiPCntCTRL_latch(r16,v)            _BFSET_(r16, 7, 0,v)

    #define     w32MC6Ctrl_AxiPCntCTRL                         {\
            UNSG32 uAxiPCntCTRL_clear                          :  8;\
            UNSG32 uAxiPCntCTRL_enable                         :  8;\
            UNSG32 uAxiPCntCTRL_latch                          :  8;\
            UNSG32 RSVDx1C_b24                                 :  8;\
          }
    union { UNSG32 u32MC6Ctrl_AxiPCntCTRL;
            struct w32MC6Ctrl_AxiPCntCTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_AxiMst0_PID(r32)                    _BFGET_(r32,15, 0)
    #define   SET32MC6Ctrl_AxiMst0_PID(r32,v)                  _BFSET_(r32,15, 0,v)
    #define   GET16MC6Ctrl_AxiMst0_PID(r16)                    _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_AxiMst0_PID(r16,v)                  _BFSET_(r16,15, 0,v)

    #define   GET32MC6Ctrl_AxiMst0_Mask(r32)                   _BFGET_(r32,31,16)
    #define   SET32MC6Ctrl_AxiMst0_Mask(r32,v)                 _BFSET_(r32,31,16,v)
    #define   GET16MC6Ctrl_AxiMst0_Mask(r16)                   _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_AxiMst0_Mask(r16,v)                 _BFSET_(r16,15, 0,v)

    #define     w32MC6Ctrl_AxiMst0                             {\
            UNSG32 uAxiMst0_PID                                : 16;\
            UNSG32 uAxiMst0_Mask                               : 16;\
          }
    union { UNSG32 u32MC6Ctrl_AxiMst0;
            struct w32MC6Ctrl_AxiMst0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_AxiMst0DXBAR_PID(r32)               _BFGET_(r32,15, 0)
    #define   SET32MC6Ctrl_AxiMst0DXBAR_PID(r32,v)             _BFSET_(r32,15, 0,v)
    #define   GET16MC6Ctrl_AxiMst0DXBAR_PID(r16)               _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_AxiMst0DXBAR_PID(r16,v)             _BFSET_(r16,15, 0,v)

    #define   GET32MC6Ctrl_AxiMst0DXBAR_Mask(r32)              _BFGET_(r32,31,16)
    #define   SET32MC6Ctrl_AxiMst0DXBAR_Mask(r32,v)            _BFSET_(r32,31,16,v)
    #define   GET16MC6Ctrl_AxiMst0DXBAR_Mask(r16)              _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_AxiMst0DXBAR_Mask(r16,v)            _BFSET_(r16,15, 0,v)

    #define     w32MC6Ctrl_AxiMst0DXBAR                        {\
            UNSG32 uAxiMst0DXBAR_PID                           : 16;\
            UNSG32 uAxiMst0DXBAR_Mask                          : 16;\
          }
    union { UNSG32 u32MC6Ctrl_AxiMst0DXBAR;
            struct w32MC6Ctrl_AxiMst0DXBAR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_AxiMst1_PID(r32)                    _BFGET_(r32,15, 0)
    #define   SET32MC6Ctrl_AxiMst1_PID(r32,v)                  _BFSET_(r32,15, 0,v)
    #define   GET16MC6Ctrl_AxiMst1_PID(r16)                    _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_AxiMst1_PID(r16,v)                  _BFSET_(r16,15, 0,v)

    #define   GET32MC6Ctrl_AxiMst1_Mask(r32)                   _BFGET_(r32,31,16)
    #define   SET32MC6Ctrl_AxiMst1_Mask(r32,v)                 _BFSET_(r32,31,16,v)
    #define   GET16MC6Ctrl_AxiMst1_Mask(r16)                   _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_AxiMst1_Mask(r16,v)                 _BFSET_(r16,15, 0,v)

    #define     w32MC6Ctrl_AxiMst1                             {\
            UNSG32 uAxiMst1_PID                                : 16;\
            UNSG32 uAxiMst1_Mask                               : 16;\
          }
    union { UNSG32 u32MC6Ctrl_AxiMst1;
            struct w32MC6Ctrl_AxiMst1;
          };
    ///////////////////////////////////////////////////////////
              SIE_AxiPCntStat                                  ie_Mstr0PCnt;
    ///////////////////////////////////////////////////////////
              SIE_AxiPCntStat                                  ie_Mstr0DXBARPCnt;
    ///////////////////////////////////////////////////////////
              SIE_AxiPCntStat                                  ie_Mstr1PCnt;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region0;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region1;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region2;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region3;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region4;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region5;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region6;
    ///////////////////////////////////////////////////////////
              SIE_Secure_Zone                                  ie_Region7;
    ///////////////////////////////////////////////////////////
              SIE_AxiErrorMon                                  ie_AxiErrorMon_Mst0;
    ///////////////////////////////////////////////////////////
              SIE_AxiErrorMon                                  ie_AxiErrorMon_Mst1;
    ///////////////////////////////////////////////////////////
              SIE_AxCacheOW                                    ie_CA53_Cache;
    ///////////////////////////////////////////////////////////
              SIE_AxCacheOW                                    ie_CM3_Cache;
    ///////////////////////////////////////////////////////////
              SIE_AxCacheOW                                    ie_AIO_Cache;
    ///////////////////////////////////////////////////////////
              SIE_AxCacheOW                                    ie_PXBAR_Cache;
    ///////////////////////////////////////////////////////////
              SIE_AxCacheOW                                    ie_NNA_Cache;
    ///////////////////////////////////////////////////////////
              SIE_AxCacheOW                                    ie_iMTEST_Cache;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_CA53_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_CM3_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_AIO_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_PCIE_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_USB_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_PXBAR_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_NNA_QoS;
    ///////////////////////////////////////////////////////////
              SIE_AxQoSOW                                      ie_iMTEST_QoS;
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_DdrAsymCtrlCpu_Mode(r32)            _BFGET_(r32, 7, 0)
    #define   SET32MC6Ctrl_DdrAsymCtrlCpu_Mode(r32,v)          _BFSET_(r32, 7, 0,v)
    #define   GET16MC6Ctrl_DdrAsymCtrlCpu_Mode(r16)            _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_DdrAsymCtrlCpu_Mode(r16,v)          _BFSET_(r16, 7, 0,v)

    #define     w32MC6Ctrl_DdrAsymCtrlCpu                      {\
            UNSG32 uDdrAsymCtrlCpu_Mode                        :  8;\
            UNSG32 RSVDx1B0_b8                                 : 24;\
          }
    union { UNSG32 u32MC6Ctrl_DdrAsymCtrlCpu;
            struct w32MC6Ctrl_DdrAsymCtrlCpu;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_DdrAsymCtrlNxbar_Mode(r32)          _BFGET_(r32, 7, 0)
    #define   SET32MC6Ctrl_DdrAsymCtrlNxbar_Mode(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16MC6Ctrl_DdrAsymCtrlNxbar_Mode(r16)          _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_DdrAsymCtrlNxbar_Mode(r16,v)        _BFSET_(r16, 7, 0,v)

    #define     w32MC6Ctrl_DdrAsymCtrlNxbar                    {\
            UNSG32 uDdrAsymCtrlNxbar_Mode                      :  8;\
            UNSG32 RSVDx1B4_b8                                 : 24;\
          }
    union { UNSG32 u32MC6Ctrl_DdrAsymCtrlNxbar;
            struct w32MC6Ctrl_DdrAsymCtrlNxbar;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_DdrAsymErrCpu_Code(r32)             _BFGET_(r32,31, 0)
    #define   SET32MC6Ctrl_DdrAsymErrCpu_Code(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32MC6Ctrl_DdrAsymErrCpu                       {\
            UNSG32 uDdrAsymErrCpu_Code                         : 32;\
          }
    union { UNSG32 u32MC6Ctrl_DdrAsymErrCpu;
            struct w32MC6Ctrl_DdrAsymErrCpu;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_DdrAsymErrNxbar_Code(r32)           _BFGET_(r32,31, 0)
    #define   SET32MC6Ctrl_DdrAsymErrNxbar_Code(r32,v)         _BFSET_(r32,31, 0,v)

    #define     w32MC6Ctrl_DdrAsymErrNxbar                     {\
            UNSG32 uDdrAsymErrNxbar_Code                       : 32;\
          }
    union { UNSG32 u32MC6Ctrl_DdrAsymErrNxbar;
            struct w32MC6Ctrl_DdrAsymErrNxbar;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_clear(r32)        _BFGET_(r32, 7, 0)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_clear(r32,v)      _BFSET_(r32, 7, 0,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_clear(r16)        _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_clear(r16,v)      _BFSET_(r16, 7, 0,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_enable(r32)       _BFGET_(r32,15, 8)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_enable(r32,v)     _BFSET_(r32,15, 8,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_enable(r16)       _BFGET_(r16,15, 8)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_enable(r16,v)     _BFSET_(r16,15, 8,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_latch(r32)        _BFGET_(r32,23,16)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_latch(r32,v)      _BFSET_(r32,23,16,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_latch(r16)        _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_latch(r16,v)      _BFSET_(r16, 7, 0,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_clk_div(r32)      _BFGET_(r32,26,24)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_clk_div(r32,v)    _BFSET_(r32,26,24,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_clk_div(r16)      _BFGET_(r16,10, 8)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_clk_div(r16,v)    _BFSET_(r16,10, 8,v)

    #define     w32MC6Ctrl_perf_log_cnt_ctrl                   {\
            UNSG32 uperf_log_cnt_ctrl_clear                    :  8;\
            UNSG32 uperf_log_cnt_ctrl_enable                   :  8;\
            UNSG32 uperf_log_cnt_ctrl_latch                    :  8;\
            UNSG32 uperf_log_cnt_ctrl_clk_div                  :  3;\
            UNSG32 RSVDx1C0_b27                                :  5;\
          }
    union { UNSG32 u32MC6Ctrl_perf_log_cnt_ctrl;
            struct w32MC6Ctrl_perf_log_cnt_ctrl;
          };
    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel(r32) _BFGET_(r32, 5, 0)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel(r32,v) _BFSET_(r32, 5, 0,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel(r16) _BFGET_(r16, 5, 0)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_pc0_event_sel(r16,v) _BFSET_(r16, 5, 0,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel(r32) _BFGET_(r32,11, 6)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel(r32,v) _BFSET_(r32,11, 6,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel(r16) _BFGET_(r16,11, 6)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_pc1_event_sel(r16,v) _BFSET_(r16,11, 6,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel(r32) _BFGET_(r32,17,12)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc2_event_sel(r32,v) _BFSET_(r32,17,12,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel(r32) _BFGET_(r32,23,18)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel(r32,v) _BFSET_(r32,23,18,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel(r16) _BFGET_(r16, 7, 2)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_pc3_event_sel(r16,v) _BFSET_(r16, 7, 2,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel(r32) _BFGET_(r32,29,24)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel(r32,v) _BFSET_(r32,29,24,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel(r16) _BFGET_(r16,13, 8)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_pc4_event_sel(r16,v) _BFSET_(r16,13, 8,v)

    #define     w32MC6Ctrl_perf_log_cnt_ctrl1                  {\
            UNSG32 uperf_log_cnt_ctrl_pc0_event_sel            :  6;\
            UNSG32 uperf_log_cnt_ctrl_pc1_event_sel            :  6;\
            UNSG32 uperf_log_cnt_ctrl_pc2_event_sel            :  6;\
            UNSG32 uperf_log_cnt_ctrl_pc3_event_sel            :  6;\
            UNSG32 uperf_log_cnt_ctrl_pc4_event_sel            :  6;\
            UNSG32 RSVDx1C4_b30                                :  2;\
          }
    union { UNSG32 u32MC6Ctrl_perf_log_cnt_ctrl1;
            struct w32MC6Ctrl_perf_log_cnt_ctrl1;
          };
    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel(r32) _BFGET_(r32, 5, 0)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel(r32,v) _BFSET_(r32, 5, 0,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel(r16) _BFGET_(r16, 5, 0)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_pc5_event_sel(r16,v) _BFSET_(r16, 5, 0,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel(r32) _BFGET_(r32,11, 6)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel(r32,v) _BFSET_(r32,11, 6,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel(r16) _BFGET_(r16,11, 6)
    #define   SET16MC6Ctrl_perf_log_cnt_ctrl_pc6_event_sel(r16,v) _BFSET_(r16,11, 6,v)

    #define   GET32MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel(r32) _BFGET_(r32,17,12)
    #define   SET32MC6Ctrl_perf_log_cnt_ctrl_pc7_event_sel(r32,v) _BFSET_(r32,17,12,v)

    #define     w32MC6Ctrl_perf_log_cnt_ctrl2                  {\
            UNSG32 uperf_log_cnt_ctrl_pc5_event_sel            :  6;\
            UNSG32 uperf_log_cnt_ctrl_pc6_event_sel            :  6;\
            UNSG32 uperf_log_cnt_ctrl_pc7_event_sel            :  6;\
            UNSG32 RSVDx1C8_b18                                : 14;\
          }
    union { UNSG32 u32MC6Ctrl_perf_log_cnt_ctrl2;
            struct w32MC6Ctrl_perf_log_cnt_ctrl2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_perf_log_cnt_ready_cnt(r32)         _BFGET_(r32, 7, 0)
    #define   SET32MC6Ctrl_perf_log_cnt_ready_cnt(r32,v)       _BFSET_(r32, 7, 0,v)
    #define   GET16MC6Ctrl_perf_log_cnt_ready_cnt(r16)         _BFGET_(r16, 7, 0)
    #define   SET16MC6Ctrl_perf_log_cnt_ready_cnt(r16,v)       _BFSET_(r16, 7, 0,v)

    #define     w32MC6Ctrl_perf_log_cnt_ready                  {\
            UNSG32 uperf_log_cnt_ready_cnt                     :  8;\
            UNSG32 RSVDx1CC_b8                                 : 24;\
          }
    union { UNSG32 u32MC6Ctrl_perf_log_cnt_ready;
            struct w32MC6Ctrl_perf_log_cnt_ready;
          };
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc0;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc1;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc2;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc3;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc4;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc5;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc6;
    ///////////////////////////////////////////////////////////
              SIE_MC_Perf_CntStat                              ie_pc7;
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers(r32) _BFGET_(r32, 0, 0)
    #define   SET32MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers(r16) _BFGET_(r16, 0, 0)
    #define   SET16MC6Ctrl_phy_ctrl_turn_off_addrctrl_drivers(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32MC6Ctrl_phy_ctrl_turn_on_ie(r32)            _BFGET_(r32, 1, 1)
    #define   SET32MC6Ctrl_phy_ctrl_turn_on_ie(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16MC6Ctrl_phy_ctrl_turn_on_ie(r16)            _BFGET_(r16, 1, 1)
    #define   SET16MC6Ctrl_phy_ctrl_turn_on_ie(r16,v)          _BFSET_(r16, 1, 1,v)

    #define     w32MC6Ctrl_phy_ctrl                            {\
            UNSG32 uphy_ctrl_turn_off_addrctrl_drivers         :  1;\
            UNSG32 uphy_ctrl_turn_on_ie                        :  1;\
            UNSG32 RSVDx210_b2                                 : 30;\
          }
    union { UNSG32 u32MC6Ctrl_phy_ctrl;
            struct w32MC6Ctrl_phy_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_AxUrgent_0_read(r32)                _BFGET_(r32, 1, 0)
    #define   SET32MC6Ctrl_AxUrgent_0_read(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16MC6Ctrl_AxUrgent_0_read(r16)                _BFGET_(r16, 1, 0)
    #define   SET16MC6Ctrl_AxUrgent_0_read(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32MC6Ctrl_AxUrgent_0_write(r32)               _BFGET_(r32, 2, 2)
    #define   SET32MC6Ctrl_AxUrgent_0_write(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16MC6Ctrl_AxUrgent_0_write(r16)               _BFGET_(r16, 2, 2)
    #define   SET16MC6Ctrl_AxUrgent_0_write(r16,v)             _BFSET_(r16, 2, 2,v)

    #define     w32MC6Ctrl_AxUrgent_0                          {\
            UNSG32 uAxUrgent_0_read                            :  2;\
            UNSG32 uAxUrgent_0_write                           :  1;\
            UNSG32 RSVDx214_b3                                 : 29;\
          }
    union { UNSG32 u32MC6Ctrl_AxUrgent_0;
            struct w32MC6Ctrl_AxUrgent_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_AxUrgent_1_read(r32)                _BFGET_(r32, 1, 0)
    #define   SET32MC6Ctrl_AxUrgent_1_read(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16MC6Ctrl_AxUrgent_1_read(r16)                _BFGET_(r16, 1, 0)
    #define   SET16MC6Ctrl_AxUrgent_1_read(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32MC6Ctrl_AxUrgent_1_write(r32)               _BFGET_(r32, 2, 2)
    #define   SET32MC6Ctrl_AxUrgent_1_write(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16MC6Ctrl_AxUrgent_1_write(r16)               _BFGET_(r16, 2, 2)
    #define   SET16MC6Ctrl_AxUrgent_1_write(r16,v)             _BFSET_(r16, 2, 2,v)

    #define     w32MC6Ctrl_AxUrgent_1                          {\
            UNSG32 uAxUrgent_1_read                            :  2;\
            UNSG32 uAxUrgent_1_write                           :  1;\
            UNSG32 RSVDx218_b3                                 : 29;\
          }
    union { UNSG32 u32MC6Ctrl_AxUrgent_1;
            struct w32MC6Ctrl_AxUrgent_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_low_pwr_ifc_axi0_lp_req(r32)        _BFGET_(r32, 0, 0)
    #define   SET32MC6Ctrl_low_pwr_ifc_axi0_lp_req(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_axi0_lp_req(r16)        _BFGET_(r16, 0, 0)
    #define   SET16MC6Ctrl_low_pwr_ifc_axi0_lp_req(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_axi0_lp_ack(r32)        _BFGET_(r32, 1, 1)
    #define   SET32MC6Ctrl_low_pwr_ifc_axi0_lp_ack(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_axi0_lp_ack(r16)        _BFGET_(r16, 1, 1)
    #define   SET16MC6Ctrl_low_pwr_ifc_axi0_lp_ack(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_axi0_lp_active(r32)     _BFGET_(r32, 2, 2)
    #define   SET32MC6Ctrl_low_pwr_ifc_axi0_lp_active(r32,v)   _BFSET_(r32, 2, 2,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_axi0_lp_active(r16)     _BFGET_(r16, 2, 2)
    #define   SET16MC6Ctrl_low_pwr_ifc_axi0_lp_active(r16,v)   _BFSET_(r16, 2, 2,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_axi1_lp_req(r32)        _BFGET_(r32, 3, 3)
    #define   SET32MC6Ctrl_low_pwr_ifc_axi1_lp_req(r32,v)      _BFSET_(r32, 3, 3,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_axi1_lp_req(r16)        _BFGET_(r16, 3, 3)
    #define   SET16MC6Ctrl_low_pwr_ifc_axi1_lp_req(r16,v)      _BFSET_(r16, 3, 3,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_axi1_lp_ack(r32)        _BFGET_(r32, 4, 4)
    #define   SET32MC6Ctrl_low_pwr_ifc_axi1_lp_ack(r32,v)      _BFSET_(r32, 4, 4,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_axi1_lp_ack(r16)        _BFGET_(r16, 4, 4)
    #define   SET16MC6Ctrl_low_pwr_ifc_axi1_lp_ack(r16,v)      _BFSET_(r16, 4, 4,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_axi1_lp_active(r32)     _BFGET_(r32, 5, 5)
    #define   SET32MC6Ctrl_low_pwr_ifc_axi1_lp_active(r32,v)   _BFSET_(r32, 5, 5,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_axi1_lp_active(r16)     _BFGET_(r16, 5, 5)
    #define   SET16MC6Ctrl_low_pwr_ifc_axi1_lp_active(r16,v)   _BFSET_(r16, 5, 5,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_hw_lp_req(r32)          _BFGET_(r32, 6, 6)
    #define   SET32MC6Ctrl_low_pwr_ifc_hw_lp_req(r32,v)        _BFSET_(r32, 6, 6,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_hw_lp_req(r16)          _BFGET_(r16, 6, 6)
    #define   SET16MC6Ctrl_low_pwr_ifc_hw_lp_req(r16,v)        _BFSET_(r16, 6, 6,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_hw_lp_ack(r32)          _BFGET_(r32, 7, 7)
    #define   SET32MC6Ctrl_low_pwr_ifc_hw_lp_ack(r32,v)        _BFSET_(r32, 7, 7,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_hw_lp_ack(r16)          _BFGET_(r16, 7, 7)
    #define   SET16MC6Ctrl_low_pwr_ifc_hw_lp_ack(r16,v)        _BFSET_(r16, 7, 7,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_hw_lp_active(r32)       _BFGET_(r32, 8, 8)
    #define   SET32MC6Ctrl_low_pwr_ifc_hw_lp_active(r32,v)     _BFSET_(r32, 8, 8,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_hw_lp_active(r16)       _BFGET_(r16, 8, 8)
    #define   SET16MC6Ctrl_low_pwr_ifc_hw_lp_active(r16,v)     _BFSET_(r16, 8, 8,v)

    #define   GET32MC6Ctrl_low_pwr_ifc_selfref_type(r32)       _BFGET_(r32,10, 9)
    #define   SET32MC6Ctrl_low_pwr_ifc_selfref_type(r32,v)     _BFSET_(r32,10, 9,v)
    #define   GET16MC6Ctrl_low_pwr_ifc_selfref_type(r16)       _BFGET_(r16,10, 9)
    #define   SET16MC6Ctrl_low_pwr_ifc_selfref_type(r16,v)     _BFSET_(r16,10, 9,v)

    #define     w32MC6Ctrl_low_pwr_ifc                         {\
            UNSG32 ulow_pwr_ifc_axi0_lp_req                    :  1;\
            UNSG32 ulow_pwr_ifc_axi0_lp_ack                    :  1;\
            UNSG32 ulow_pwr_ifc_axi0_lp_active                 :  1;\
            UNSG32 ulow_pwr_ifc_axi1_lp_req                    :  1;\
            UNSG32 ulow_pwr_ifc_axi1_lp_ack                    :  1;\
            UNSG32 ulow_pwr_ifc_axi1_lp_active                 :  1;\
            UNSG32 ulow_pwr_ifc_hw_lp_req                      :  1;\
            UNSG32 ulow_pwr_ifc_hw_lp_ack                      :  1;\
            UNSG32 ulow_pwr_ifc_hw_lp_active                   :  1;\
            UNSG32 ulow_pwr_ifc_selfref_type                   :  2;\
            UNSG32 RSVDx21C_b11                                : 21;\
          }
    union { UNSG32 u32MC6Ctrl_low_pwr_ifc;
            struct w32MC6Ctrl_low_pwr_ifc;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_port_arbiter_rmask_0(r32)           _BFGET_(r32, 1, 0)
    #define   SET32MC6Ctrl_port_arbiter_rmask_0(r32,v)         _BFSET_(r32, 1, 0,v)
    #define   GET16MC6Ctrl_port_arbiter_rmask_0(r16)           _BFGET_(r16, 1, 0)
    #define   SET16MC6Ctrl_port_arbiter_rmask_0(r16,v)         _BFSET_(r16, 1, 0,v)

    #define   GET32MC6Ctrl_port_arbiter_rmask_1(r32)           _BFGET_(r32, 3, 2)
    #define   SET32MC6Ctrl_port_arbiter_rmask_1(r32,v)         _BFSET_(r32, 3, 2,v)
    #define   GET16MC6Ctrl_port_arbiter_rmask_1(r16)           _BFGET_(r16, 3, 2)
    #define   SET16MC6Ctrl_port_arbiter_rmask_1(r16,v)         _BFSET_(r16, 3, 2,v)

    #define   GET32MC6Ctrl_port_arbiter_wmask_0(r32)           _BFGET_(r32, 4, 4)
    #define   SET32MC6Ctrl_port_arbiter_wmask_0(r32,v)         _BFSET_(r32, 4, 4,v)
    #define   GET16MC6Ctrl_port_arbiter_wmask_0(r16)           _BFGET_(r16, 4, 4)
    #define   SET16MC6Ctrl_port_arbiter_wmask_0(r16,v)         _BFSET_(r16, 4, 4,v)

    #define   GET32MC6Ctrl_port_arbiter_wmask_1(r32)           _BFGET_(r32, 5, 5)
    #define   SET32MC6Ctrl_port_arbiter_wmask_1(r32,v)         _BFSET_(r32, 5, 5,v)
    #define   GET16MC6Ctrl_port_arbiter_wmask_1(r16)           _BFGET_(r16, 5, 5)
    #define   SET16MC6Ctrl_port_arbiter_wmask_1(r16,v)         _BFSET_(r16, 5, 5,v)

    #define     w32MC6Ctrl_port_arbiter                        {\
            UNSG32 uport_arbiter_rmask_0                       :  2;\
            UNSG32 uport_arbiter_rmask_1                       :  2;\
            UNSG32 uport_arbiter_wmask_0                       :  1;\
            UNSG32 uport_arbiter_wmask_1                       :  1;\
            UNSG32 RSVDx220_b6                                 : 26;\
          }
    union { UNSG32 u32MC6Ctrl_port_arbiter;
            struct w32MC6Ctrl_port_arbiter;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en(r32) _BFGET_(r32, 0, 0)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en(r16) _BFGET_(r16, 0, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_en(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en(r32) _BFGET_(r32, 1, 1)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en(r16) _BFGET_(r16, 1, 1)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_srx_dscl_en(r16,v) _BFSET_(r16, 1, 1,v)

    #define     w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl            {\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_phymstr_en        :  1;\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_srx_dscl_en       :  1;\
            UNSG32 RSVDx224_b2                                 : 30;\
          }
    union { UNSG32 u32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl;
          };
    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval(r32) _BFGET_(r32,31, 0)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_interval(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1           {\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_dscl_interval     : 32;\
          }
    union { UNSG32 u32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1;
          };
    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait(r32) _BFGET_(r32, 9, 0)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait(r32,v) _BFSET_(r32, 9, 0,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait(r16) _BFGET_(r16, 9, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait(r16,v) _BFSET_(r16, 9, 0,v)

    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout(r32) _BFGET_(r32,25,10)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout(r32,v) _BFSET_(r32,25,10,v)

    #define     w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2           {\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_dfi_hsk_wait      : 10;\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_ctrlupd_min_timeout : 16;\
            UNSG32 RSVDx22C_b26                                :  6;\
          }
    union { UNSG32 u32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2;
          };
    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout(r32) _BFGET_(r32,15, 0)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout(r32,v) _BFSET_(r32,15, 0,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout(r16) _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout(r16,v) _BFSET_(r16,15, 0,v)

    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout(r32) _BFGET_(r32,31,16)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout(r32,v) _BFSET_(r32,31,16,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout(r16) _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout(r16,v) _BFSET_(r16,15, 0,v)

    #define     w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3           {\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_ctrlupd_max_timeout : 16;\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_phymstr_resp_timeout : 16;\
          }
    union { UNSG32 u32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3;
          };
    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres(r32) _BFGET_(r32,15, 0)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres(r32,v) _BFSET_(r32,15, 0,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres(r16) _BFGET_(r16,15, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_thres(r16,v) _BFSET_(r16,15, 0,v)

    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en(r32) _BFGET_(r32,16,16)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en(r32,v) _BFSET_(r32,16,16,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en(r16) _BFGET_(r16, 0, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_ctrl_dscl_overflow_en(r16,v) _BFSET_(r16, 0, 0,v)

    #define     w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4           {\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_dscl_thres        : 16;\
            UNSG32 uunq_ddr_dfi_phymstr_ctrl_dscl_overflow_en  :  1;\
            UNSG32 RSVDx234_b17                                : 15;\
          }
    union { UNSG32 u32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state(r32) _BFGET_(r32, 1, 0)
    #define   SET32MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state(r32,v) _BFSET_(r32, 1, 0,v)
    #define   GET16MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state(r16) _BFGET_(r16, 1, 0)
    #define   SET16MC6Ctrl_unq_ddr_dfi_phymstr_stat_current_state(r16,v) _BFSET_(r16, 1, 0,v)

    #define     w32MC6Ctrl_unq_ddr_dfi_phymstr_stat            {\
            UNSG32 uunq_ddr_dfi_phymstr_stat_current_state     :  2;\
            UNSG32 RSVDx238_b2                                 : 30;\
          }
    union { UNSG32 u32MC6Ctrl_unq_ddr_dfi_phymstr_stat;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_stat;
          };
    ///////////////////////////////////////////////////////////
    } SIE_MC6Ctrl;

    typedef union  T32MC6Ctrl_MC6_4TO1
          { UNSG32 u32;
            struct w32MC6Ctrl_MC6_4TO1;
                 } T32MC6Ctrl_MC6_4TO1;
    typedef union  T32MC6Ctrl_AxiPCntCTRL
          { UNSG32 u32;
            struct w32MC6Ctrl_AxiPCntCTRL;
                 } T32MC6Ctrl_AxiPCntCTRL;
    typedef union  T32MC6Ctrl_AxiMst0
          { UNSG32 u32;
            struct w32MC6Ctrl_AxiMst0;
                 } T32MC6Ctrl_AxiMst0;
    typedef union  T32MC6Ctrl_AxiMst0DXBAR
          { UNSG32 u32;
            struct w32MC6Ctrl_AxiMst0DXBAR;
                 } T32MC6Ctrl_AxiMst0DXBAR;
    typedef union  T32MC6Ctrl_AxiMst1
          { UNSG32 u32;
            struct w32MC6Ctrl_AxiMst1;
                 } T32MC6Ctrl_AxiMst1;
    typedef union  T32MC6Ctrl_DdrAsymCtrlCpu
          { UNSG32 u32;
            struct w32MC6Ctrl_DdrAsymCtrlCpu;
                 } T32MC6Ctrl_DdrAsymCtrlCpu;
    typedef union  T32MC6Ctrl_DdrAsymCtrlNxbar
          { UNSG32 u32;
            struct w32MC6Ctrl_DdrAsymCtrlNxbar;
                 } T32MC6Ctrl_DdrAsymCtrlNxbar;
    typedef union  T32MC6Ctrl_DdrAsymErrCpu
          { UNSG32 u32;
            struct w32MC6Ctrl_DdrAsymErrCpu;
                 } T32MC6Ctrl_DdrAsymErrCpu;
    typedef union  T32MC6Ctrl_DdrAsymErrNxbar
          { UNSG32 u32;
            struct w32MC6Ctrl_DdrAsymErrNxbar;
                 } T32MC6Ctrl_DdrAsymErrNxbar;
    typedef union  T32MC6Ctrl_perf_log_cnt_ctrl
          { UNSG32 u32;
            struct w32MC6Ctrl_perf_log_cnt_ctrl;
                 } T32MC6Ctrl_perf_log_cnt_ctrl;
    typedef union  T32MC6Ctrl_perf_log_cnt_ctrl1
          { UNSG32 u32;
            struct w32MC6Ctrl_perf_log_cnt_ctrl1;
                 } T32MC6Ctrl_perf_log_cnt_ctrl1;
    typedef union  T32MC6Ctrl_perf_log_cnt_ctrl2
          { UNSG32 u32;
            struct w32MC6Ctrl_perf_log_cnt_ctrl2;
                 } T32MC6Ctrl_perf_log_cnt_ctrl2;
    typedef union  T32MC6Ctrl_perf_log_cnt_ready
          { UNSG32 u32;
            struct w32MC6Ctrl_perf_log_cnt_ready;
                 } T32MC6Ctrl_perf_log_cnt_ready;
    typedef union  T32MC6Ctrl_phy_ctrl
          { UNSG32 u32;
            struct w32MC6Ctrl_phy_ctrl;
                 } T32MC6Ctrl_phy_ctrl;
    typedef union  T32MC6Ctrl_AxUrgent_0
          { UNSG32 u32;
            struct w32MC6Ctrl_AxUrgent_0;
                 } T32MC6Ctrl_AxUrgent_0;
    typedef union  T32MC6Ctrl_AxUrgent_1
          { UNSG32 u32;
            struct w32MC6Ctrl_AxUrgent_1;
                 } T32MC6Ctrl_AxUrgent_1;
    typedef union  T32MC6Ctrl_low_pwr_ifc
          { UNSG32 u32;
            struct w32MC6Ctrl_low_pwr_ifc;
                 } T32MC6Ctrl_low_pwr_ifc;
    typedef union  T32MC6Ctrl_port_arbiter
          { UNSG32 u32;
            struct w32MC6Ctrl_port_arbiter;
                 } T32MC6Ctrl_port_arbiter;
    typedef union  T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl
          { UNSG32 u32;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl;
                 } T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl;
    typedef union  T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1
          { UNSG32 u32;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1;
                 } T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1;
    typedef union  T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2
          { UNSG32 u32;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2;
                 } T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2;
    typedef union  T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3
          { UNSG32 u32;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3;
                 } T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3;
    typedef union  T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4
          { UNSG32 u32;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4;
                 } T32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4;
    typedef union  T32MC6Ctrl_unq_ddr_dfi_phymstr_stat
          { UNSG32 u32;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_stat;
                 } T32MC6Ctrl_unq_ddr_dfi_phymstr_stat;
    ///////////////////////////////////////////////////////////

    typedef union  TMC6Ctrl_MC6_4TO1
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_MC6_4TO1;
                   };
                 } TMC6Ctrl_MC6_4TO1;
    typedef union  TMC6Ctrl_AxiPCntCTRL
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_AxiPCntCTRL;
                   };
                 } TMC6Ctrl_AxiPCntCTRL;
    typedef union  TMC6Ctrl_AxiMst0
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_AxiMst0;
                   };
                 } TMC6Ctrl_AxiMst0;
    typedef union  TMC6Ctrl_AxiMst0DXBAR
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_AxiMst0DXBAR;
                   };
                 } TMC6Ctrl_AxiMst0DXBAR;
    typedef union  TMC6Ctrl_AxiMst1
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_AxiMst1;
                   };
                 } TMC6Ctrl_AxiMst1;
    typedef union  TMC6Ctrl_DdrAsymCtrlCpu
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_DdrAsymCtrlCpu;
                   };
                 } TMC6Ctrl_DdrAsymCtrlCpu;
    typedef union  TMC6Ctrl_DdrAsymCtrlNxbar
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_DdrAsymCtrlNxbar;
                   };
                 } TMC6Ctrl_DdrAsymCtrlNxbar;
    typedef union  TMC6Ctrl_DdrAsymErrCpu
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_DdrAsymErrCpu;
                   };
                 } TMC6Ctrl_DdrAsymErrCpu;
    typedef union  TMC6Ctrl_DdrAsymErrNxbar
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_DdrAsymErrNxbar;
                   };
                 } TMC6Ctrl_DdrAsymErrNxbar;
    typedef union  TMC6Ctrl_perf_log_cnt_ctrl
          { UNSG32 u32[3];
            struct {
            struct w32MC6Ctrl_perf_log_cnt_ctrl;
            struct w32MC6Ctrl_perf_log_cnt_ctrl1;
            struct w32MC6Ctrl_perf_log_cnt_ctrl2;
                   };
                 } TMC6Ctrl_perf_log_cnt_ctrl;
    typedef union  TMC6Ctrl_perf_log_cnt_ready
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_perf_log_cnt_ready;
                   };
                 } TMC6Ctrl_perf_log_cnt_ready;
    typedef union  TMC6Ctrl_phy_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_phy_ctrl;
                   };
                 } TMC6Ctrl_phy_ctrl;
    typedef union  TMC6Ctrl_AxUrgent_0
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_AxUrgent_0;
                   };
                 } TMC6Ctrl_AxUrgent_0;
    typedef union  TMC6Ctrl_AxUrgent_1
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_AxUrgent_1;
                   };
                 } TMC6Ctrl_AxUrgent_1;
    typedef union  TMC6Ctrl_low_pwr_ifc
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_low_pwr_ifc;
                   };
                 } TMC6Ctrl_low_pwr_ifc;
    typedef union  TMC6Ctrl_port_arbiter
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_port_arbiter;
                   };
                 } TMC6Ctrl_port_arbiter;
    typedef union  TMC6Ctrl_unq_ddr_dfi_phymstr_ctrl
          { UNSG32 u32[5];
            struct {
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl1;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl2;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl3;
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_ctrl4;
                   };
                 } TMC6Ctrl_unq_ddr_dfi_phymstr_ctrl;
    typedef union  TMC6Ctrl_unq_ddr_dfi_phymstr_stat
          { UNSG32 u32[1];
            struct {
            struct w32MC6Ctrl_unq_ddr_dfi_phymstr_stat;
                   };
                 } TMC6Ctrl_unq_ddr_dfi_phymstr_stat;

    ///////////////////////////////////////////////////////////
     SIGN32 MC6Ctrl_drvrd(SIE_MC6Ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 MC6Ctrl_drvwr(SIE_MC6Ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void MC6Ctrl_reset(SIE_MC6Ctrl *p);
     SIGN32 MC6Ctrl_cmp  (SIE_MC6Ctrl *p, SIE_MC6Ctrl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define MC6Ctrl_check(p,pie,pfx,hLOG) MC6Ctrl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define MC6Ctrl_print(p,    pfx,hLOG) MC6Ctrl_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: MC6Ctrl
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: MC6Ctrl.h
////////////////////////////////////////////////////////////