//////
/// don't edit! auto-generated by docc: cpu_wrp.h
////////////////////////////////////////////////////////////
#ifndef cpu_wrp_h
#define cpu_wrp_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE CPU_REG                                  (4,4)
///     ###
///     * All the controls for CORTEXA53 system
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 SRRESET_MP           (RW-)
///               ###
///               * Reset and that can recover by itself
///               ###
///               %unsigned 1  nRESETALL                 0x1
///                                    ###
///                                    * RESET the whole CPU
///                                    * 0 Apply reset to CPU
///                                    * 1 Do not apply reset to CPU
///                                    ###
///               %unsigned 1  nL2RESET                  0x1
///                                    ###
///                                    * Input L2 memory system reset:
///                                    * 0 Apply reset to shared L2 memory system controller.
///                                    * 1 Do not apply reset to shared L2 memory system controller.
///                                    ###
///               %unsigned 1  nPRESETDBG                0x1
///                                    ###
///                                    * APB reset, active-LOW:
///                                    * 0 Apply reset to APB interface.
///                                    * 1 Do not apply reset to APB interface.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00004 SRRESET_0            (RW-)
///               ###
///               * Reset Core 0
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00008 SRRESET_1            (RW-)
///               ###
///               * Reset Core 1
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x0000C SRRESET_2            (RW-)
///               ###
///               * Reset Core 2
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00010 SRRESET_3            (RW-)
///               ###
///               * Reset Core 3
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00014 RESET_MP             (RW-)
///               ###
///               * Reset and reset control signals, reset in this group will not reset itself
///               ###
///               %unsigned 1  nRESETALL                 0x0
///                                    ###
///                                    * RESET the whole CPU
///                                    * 0 Apply reset to CPU
///                                    * 1 Do not apply reset to CPU
///                                    ###
///               %unsigned 1  nL2RESET                  0x1
///                                    ###
///                                    * Input L2 memory system reset:
///                                    * 0 Apply reset to shared L2 memory system controller.
///                                    * 1 Do not apply reset to shared L2 memory system controller.
///                                    ###
///               %unsigned 1  nPRESETDBG                0x1
///                                    ###
///                                    * APB reset, active-LOW:
///                                    * 0 Apply reset to APB interface.
///                                    * 1 Do not apply reset to APB interface.
///                                    ###
///               %unsigned 1  L2RSTDISABLE              0x0
///                                    ###
///                                    * Input Disable automatic L2 cache invalidate at reset:
///                                    * 0 Hardware resets L2 cache.
///                                    * 1 Hardware does not reset L2 cache.
///                                    ###
///               %unsigned 1  RESETCPUTIMER             0x1
///                                    ###
///                                    * Reset CPU timer
///                                    * 0 resets
///                                    * 1 does not reset
///                                    ###
///               %unsigned 1  RESETPTMTIMER             0x1
///                                    ###
///                                    * Reset PTM timer
///                                    * 0 resets
///                                    * 1 does not reset
///                                    ###
///               %unsigned 1  nMBISTRESET               0x1
///                                    ###
///                                    * Reset MBIST
///                                    * 0 resets
///                                    * 1 does not reset
///                                    ###
///               %unsigned 1  L2_FNRST                  0x1
///                                    ###
///                                    * Reset L2 FNRST
///                                    * 0 resets
///                                    * 1 does not reset
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00018 RESET_0              (RW-)
///               ###
///               * Reset and reset control signals, reset in this group will not reset itself
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %unsigned 1  WARMRSTREQ                0x1
///                                    ###
///                                    * Output Processor warm reset request
///                                    * 0 Apply warm reset.
///                                    * 1 Do not apply warm reset.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x0001C RESET_1              (RW-)
///               ###
///               * Reset and reset control signals, reset in this group will not reset itself
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %unsigned 1  WARMRSTREQ                0x1
///                                    ###
///                                    * Output Processor warm reset request
///                                    * 0 Apply warm reset.
///                                    * 1 Do not apply warm reset.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00020 RESET_2              (RW-)
///               ###
///               * Reset and reset control signals, reset in this group will not reset itself
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %unsigned 1  WARMRSTREQ                0x1
///                                    ###
///                                    * Output Processor warm reset request
///                                    * 0 Apply warm reset.
///                                    * 1 Do not apply warm reset.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00024 RESET_3              (RW-)
///               ###
///               * Reset and reset control signals, reset in this group will not reset itself
///               ###
///               %unsigned 1  nCPUPORESET               0x1
///                                    ###
///                                    * Input Processor powerup reset:
///                                    * 0 Apply reset to all processor logic.
///                                    * 1 Do not apply reset to all processor logic.
///                                    ###
///               %unsigned 1  nCORERESET                0x1
///                                    ###
///                                    * Input Individual processor resets excluding Debug and ETM trace unit:
///                                    * 0 Apply reset to processor logicb.
///                                    * 1 Do not apply reset to processor logic.
///                                    ###
///               %unsigned 1  WARMRSTREQ                0x1
///                                    ###
///                                    * Output Processor warm reset request
///                                    * 0 Apply warm reset.
///                                    * 1 Do not apply warm reset.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00028 CFG                  (RW-)
///               ###
///               * System controls of CPU. All the bits of this register are only sampled during reset of the CPU. Most of them should only be changed while the CPU is in reset.
///               ###
///               %unsigned 4  AA64nAA32                 0x0
///                                    ###
///                                    * Input Register width state:
///                                    * 0: AArch32.
///                                    * 1: AArch64.
///                                    * This pin is sampled only during reset of the processor.
///                                    * Bit0: core 0
///                                    * Bit1: core 1
///                                    * Bit2: core 2
///                                    * Bit3: core 3
///                                    ###
///               %unsigned 4  CFGEND                    0x0
///                                    ###
///                                    * Input Endianness configuration at reset. It sets the initial value of the EE bits in the CP15
///                                    * SCTLR_EL3 and SCTR_S registers:
///                                    * 0 EE bit is LOW.
///                                    * 1 EE bit is HIGH.
///                                    * This pin is sampled only during reset of the processor.
///                                    ###
///               %unsigned 4  CFGTE                     0x0
///                                    ###
///                                    * Input Enable T32 exceptions. It sets the initial value of the TE bit in the CP15 SCTLR register:
///                                    * 0 TE bit is LOW.
///                                    * 1 TE bit is HIGH.
///                                    * This pin is sampled only during reset of the processor.
///                                    ###
///               %unsigned 8  CLUSTERIDAFF1             0x0
///                                    ###
///                                    * Input Value read in the Cluster ID Affinity Level 1 field, MPIDR bits [15:8], of the CP15
///                                    * MPDIR register.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///               %unsigned 8  CLUSTERIDAFF2             0x0
///                                    ###
///                                    * Input Value read in the Cluster ID Affinity Level 2 field, MPIDR bits [23:16], of the CP15
///                                    * MPDIR register.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///               %unsigned 4  CP15SDISABLE              0x0
///                                    ###
///                                    * Input Disable write access to some secure CP15 registers
///                                    ###
///     # 0x0002C CFG1                 
///               %unsigned 4  CRYPTODISABLE             0x0
///                                    ###
///                                    * Input Disables the Cryptography Extensions.
///                                    * This pin is sampled only during reset of the processor.
///                                    ###
///               %unsigned 4  VINITHI                   0xF
///                                    ###
///                                    * Input Location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 SCTLR register:
///                                    * 0: Exception vectors start at address 0x00000000.
///                                    * 1: Exception vectors start at address 0xFFFF0000.
///                                    * This pin is sampled only during reset of the processor.
///                                    ###
///               %unsigned 8  RDMEMATTR                 0x0
///                                    ###
///                                    * Output Read request memory attributes.
///                                    ###
///               %unsigned 8  WRMEMATTR                 0x0
///                                    ###
///                                    * Output Write request memory attributes.
///                                    ###
///               %unsigned 1  ACINACTM                  0x0
///                                    ###
///                                    * Output Read request memory attributes.Input Snoop interface is inactive and not participating in coherency:
///                                    * 0 Snoop interface is active.
///                                    * 1 Snoop interface is inactive.
///                                    ###
///               %%        7          # Stuffing bits...
///     @ 0x00030 PWR_NO_RETENTION_MP  (RW-)
///               ###
///               * non-Retention power management signals
///               ###
///               %unsigned 1  CLREXMONREQ               0x0
///                                    ###
///                                    * Input Clearing of the external global exclusive monitor request. When this signal is asserted, it acts as a WFE wake-up event to all the processors in the MPCore device
///                                    ###
///               %unsigned 1  CLREXMONACK               0x0
///                                    ###
///                                    * Clearing of the external global exclusive monitor acknowledge
///                                    ###
///               %unsigned 1  EVENTI                    0x0
///                                    ###
///                                    * Input Event input for processor wake-up from WFE state
///                                    ###
///               %unsigned 1  EVENTO                    0x0
///                                    ###
///                                    * Output Event output. Active when a SEV instruction is executed
///                                    ###
///               %unsigned 1  STANDBYWFIL2              0x0
///               %unsigned 1  L2FLUSHREQ                0x0
///                                    ###
///                                    * Input L2 hardware flush request.
///                                    ###
///               %unsigned 1  L2FLUSHDONE               0x0
///                                    ###
///                                    * Output L2 hardware flush complete.
///                                    ###
///               %unsigned 1  SMPEN                     0x0
///               %%        24         # Stuffing bits...
///     @ 0x00034 PWR_NO_RETENTION_0   (RW-)
///               ###
///               * Core 0 non-Retention power management signals
///               ###
///               %unsigned 1  STANDBYWFI                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFI low-power state:
///                                    * 0 Processor not in WFI low-power state.
///                                    * 1 Processor in WFI low-power state. This is the reset condition.
///                                    ###
///               %unsigned 1  STANDBYWFE                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFE low-power state:
///                                    * 0 Processor not in WFE low-power state.
///                                    * 1 Processor in WFE low-power state.
///                                    ###
///               %unsigned 1  DBGNOPWRDWN               0x0
///                                    ###
///                                    * Output Processor no powerdown request
///                                    * 0 Do not request that the processor stays powered up.
///                                    * 1 Request that the processor stays powered up.
///                                    ###
///               %unsigned 1  DBGPWRUPREQ               0x0
///                                    ###
///                                    * Output Processor powerup request
///                                    * 0 Do not request processor to power up.
///                                    * 1 Request that the processor is not powered up.
///                                    ###
///               %unsigned 1  DBGPWRDUP                 0x1
///                                    ###
///                                    * Input Processor powered up
///                                    * 0 Processor is powered down.
///                                    * 1 Processor is powered up.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00038 PWR_NO_RETENTION_1   (RW-)
///               ###
///               * Core 1 non-Retention power management signals
///               ###
///               %unsigned 1  STANDBYWFI                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFI low-power state:
///                                    * 0 Processor not in WFI low-power state.
///                                    * 1 Processor in WFI low-power state. This is the reset condition.
///                                    ###
///               %unsigned 1  STANDBYWFE                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFE low-power state:
///                                    * 0 Processor not in WFE low-power state.
///                                    * 1 Processor in WFE low-power state.
///                                    ###
///               %unsigned 1  DBGNOPWRDWN               0x0
///                                    ###
///                                    * Output Processor no powerdown request
///                                    * 0 Do not request that the processor stays powered up.
///                                    * 1 Request that the processor stays powered up.
///                                    ###
///               %unsigned 1  DBGPWRUPREQ               0x0
///                                    ###
///                                    * Output Processor powerup request
///                                    * 0 Do not request processor to power up.
///                                    * 1 Request that the processor is not powered up.
///                                    ###
///               %unsigned 1  DBGPWRDUP                 0x1
///                                    ###
///                                    * Input Processor powered up
///                                    * 0 Processor is powered down.
///                                    * 1 Processor is powered up.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x0003C PWR_NO_RETENTION_2   (RW-)
///               ###
///               * Core 2 non-Retention power management signals
///               ###
///               %unsigned 1  STANDBYWFI                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFI low-power state:
///                                    * 0 Processor not in WFI low-power state.
///                                    * 1 Processor in WFI low-power state. This is the reset condition.
///                                    ###
///               %unsigned 1  STANDBYWFE                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFE low-power state:
///                                    * 0 Processor not in WFE low-power state.
///                                    * 1 Processor in WFE low-power state.
///                                    ###
///               %unsigned 1  DBGNOPWRDWN               0x0
///                                    ###
///                                    * Output Processor no powerdown request
///                                    * 0 Do not request that the processor stays powered up.
///                                    * 1 Request that the processor stays powered up.
///                                    ###
///               %unsigned 1  DBGPWRUPREQ               0x0
///                                    ###
///                                    * Output Processor powerup request
///                                    * 0 Do not request processor to power up.
///                                    * 1 Request that the processor is not powered up.
///                                    ###
///               %unsigned 1  DBGPWRDUP                 0x1
///                                    ###
///                                    * Input Processor powered up
///                                    * 0 Processor is powered down.
///                                    * 1 Processor is powered up.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00040 PWR_NO_RETENTION_3   (RW-)
///               ###
///               * Core 3 non-Retention power management signals
///               ###
///               %unsigned 1  STANDBYWFI                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFI low-power state:
///                                    * 0 Processor not in WFI low-power state.
///                                    * 1 Processor in WFI low-power state. This is the reset condition.
///                                    ###
///               %unsigned 1  STANDBYWFE                0x0
///                                    ###
///                                    * Output Indicates whether a processor is in WFE low-power state:
///                                    * 0 Processor not in WFE low-power state.
///                                    * 1 Processor in WFE low-power state.
///                                    ###
///               %unsigned 1  DBGNOPWRDWN               0x0
///                                    ###
///                                    * Output Processor no powerdown request
///                                    * 0 Do not request that the processor stays powered up.
///                                    * 1 Request that the processor stays powered up.
///                                    ###
///               %unsigned 1  DBGPWRUPREQ               0x0
///                                    ###
///                                    * Output Processor powerup request
///                                    * 0 Do not request processor to power up.
///                                    * 1 Request that the processor is not powered up.
///                                    ###
///               %unsigned 1  DBGPWRDUP                 0x1
///                                    ###
///                                    * Input Processor powered up
///                                    * 0 Processor is powered down.
///                                    * 1 Processor is powered up.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00044 PWR_RETENTION        (RW-)
///               ###
///               * Retention power management signals
///               ###
///               %unsigned 1  L2QACTIVE                 0x0
///                                    ###
///                                    * Output Indicates whether the L2 data RAMs are active
///                                    * L2QREQn Input Indicates that the power controller is ready to enter or exit retention for the L2 data
///                                    * RAMs
///                                    ###
///               %unsigned 1  L2QDENY                   0x0
///                                    ###
///                                    * Output Indicates that the L2 data RAMs deny the power controller retention request
///                                    ###
///               %unsigned 1  L2QACCEPTn                0x0
///                                    ###
///                                    * Output Indicates that the L2 data RAMs accept the power controller retention request
///                                    ###
///               %unsigned 1  L2QREQn                   0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the L2 data
///                                    * RAMs
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00048 PWR_RETENTION_0      (RW-)
///               ###
///               * Core 0 Retention power management signals
///               ###
///               %unsigned 1  CPUQACTIVE                0x0
///                                    ###
///                                    * Output Indicates whether the referenced processor is active
///                                    ###
///               %unsigned 1  CPUQREQn                  0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced processor
///                                    ###
///               %unsigned 1  CPUQDENY                  0x0
///                                    ###
///                                    * Output Indicates that the referenced processor denies the power controller retention request
///                                    ###
///               %unsigned 1  CPUQACCEPTn               0x0
///                                    ###
///                                    * Output Indicates that the referenced processor accepts the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACTIVE               0x0
///                                    ###
///                                    * Output Indicates whether the referenced Advanced SIMD and Floating-point block is active
///                                    ###
///               %unsigned 1  NEONQREQn                 0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced Advanced SIMD and Floating-point block
///                                    ###
///               %unsigned 1  NEONQDENY                 0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block denies the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACCEPTn              0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block accepts the power controller retention request
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x0004C PWR_RETENTION_1      (RW-)
///               ###
///               * Core 1 Retention power management signals
///               ###
///               %unsigned 1  CPUQACTIVE                0x0
///                                    ###
///                                    * Output Indicates whether the referenced processor is active
///                                    ###
///               %unsigned 1  CPUQREQn                  0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced processor
///                                    ###
///               %unsigned 1  CPUQDENY                  0x0
///                                    ###
///                                    * Output Indicates that the referenced processor denies the power controller retention request
///                                    ###
///               %unsigned 1  CPUQACCEPTn               0x0
///                                    ###
///                                    * Output Indicates that the referenced processor accepts the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACTIVE               0x0
///                                    ###
///                                    * Output Indicates whether the referenced Advanced SIMD and Floating-point block is active
///                                    ###
///               %unsigned 1  NEONQREQn                 0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced Advanced SIMD and Floating-point block
///                                    ###
///               %unsigned 1  NEONQDENY                 0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block denies the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACCEPTn              0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block accepts the power controller retention request
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00050 PWR_RETENTION_2      (RW-)
///               ###
///               * Core 2 Retention power management signals
///               ###
///               %unsigned 1  CPUQACTIVE                0x0
///                                    ###
///                                    * Output Indicates whether the referenced processor is active
///                                    ###
///               %unsigned 1  CPUQREQn                  0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced processor
///                                    ###
///               %unsigned 1  CPUQDENY                  0x0
///                                    ###
///                                    * Output Indicates that the referenced processor denies the power controller retention request
///                                    ###
///               %unsigned 1  CPUQACCEPTn               0x0
///                                    ###
///                                    * Output Indicates that the referenced processor accepts the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACTIVE               0x0
///                                    ###
///                                    * Output Indicates whether the referenced Advanced SIMD and Floating-point block is active
///                                    ###
///               %unsigned 1  NEONQREQn                 0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced Advanced SIMD and Floating-point block
///                                    ###
///               %unsigned 1  NEONQDENY                 0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block denies the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACCEPTn              0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block accepts the power controller retention request
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00054 PWR_RETENTION_3      (RW-)
///               ###
///               * Core 3 Retention power management signals
///               ###
///               %unsigned 1  CPUQACTIVE                0x0
///                                    ###
///                                    * Output Indicates whether the referenced processor is active
///                                    ###
///               %unsigned 1  CPUQREQn                  0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced processor
///                                    ###
///               %unsigned 1  CPUQDENY                  0x0
///                                    ###
///                                    * Output Indicates that the referenced processor denies the power controller retention request
///                                    ###
///               %unsigned 1  CPUQACCEPTn               0x0
///                                    ###
///                                    * Output Indicates that the referenced processor accepts the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACTIVE               0x0
///                                    ###
///                                    * Output Indicates whether the referenced Advanced SIMD and Floating-point block is active
///                                    ###
///               %unsigned 1  NEONQREQn                 0x1
///                                    ###
///                                    * Input Indicates that the power controller is ready to enter or exit retention for the referenced Advanced SIMD and Floating-point block
///                                    ###
///               %unsigned 1  NEONQDENY                 0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block denies the power controller retention request
///                                    ###
///               %unsigned 1  NEONQACCEPTn              0x0
///                                    ###
///                                    * Output Indicates that the referenced Advanced SIMD and Floating-point block accepts the power controller retention request
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00058 ACE_CHI              (RW-)
///               ###
///               * interface signals that both ACE and CHI use.
///               ###
///               %unsigned 1  BROADCASTCACHEMAINT       0x0
///                                    ###
///                                    * Input Enable broadcasting of cache maintenance operations to downstream caches:
///                                    * 0 Cache maintenance operations are not broadcast to downstream caches.
///                                    * 1 Cache maintenance operations are broadcast to downstream caches.
///                                    * This pin is sampled only during reset of the Cortex-A73 MPCore processor.
///                                    ###
///               %unsigned 1  BROADCASTCACHEMAINTPOU    0x0
///                                    ###
///                                    * Enable broadcasting of cache maintenance by Modified Virtual Address (MVA) to
///                                    * the Point of Unification (PoU) :
///                                    * 0 Cache maintenance operations by MVA to PoU are not broadcast to other
///                                    * clusters 	.
///                                    * 1 Cache maintenance operations by MVA to PoU are broadcast to other
///                                    * cluster .
///                                    * This pin is sampled only during reset of the Cortex-A73 MPCore processor.
///                                    ###
///               %unsigned 1  BROADCASTINNER            0x0
///                                    ###
///                                    * Input Enable broadcasting of Inner Shareable transactions:
///                                    * 0 Inner Shareable transactions are not broadcast externally.
///                                    * 1 Inner Shareable transactions are broadcast externally.
///                                    * If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER
///                                    * HIGH.
///                                    * This pin is sampled only during reset of the Cortex-A53 MPCore processor.
///                                    ###
///               %unsigned 1  BROADCASTOUTER            0x0
///                                    ###
///                                    * Input Enable broadcasting of outer shareable transactions:
///                                    * 0 Outer Shareable transactions are not broadcast externally.
///                                    * 1 Outer Shareable transactions are broadcast externally.
///                                    * This pin is sampled only during reset of the Cortex-A53 MPCore processor.
///                                    ###
///               %unsigned 1  SYSBARDISABLE             0x1
///                                    ###
///                                    * Disable broadcasting of barriers onto the system bus:
///                                    * 0 Barriers are broadcast onto the system bus. This requires an AMBA4 ACE, or
///                                    * AMBA5 CHI, interconnect.
///                                    * 1 Barriers are not broadcast onto the system bus. This is compatible with an
///                                    * AXI3 interconnect and most AMBA4 interconnects.a
///                                    * This pin is sampled only during reset of the Cortex-A53 MPCore processor
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x0005C DEBUG                (RW-)
///               ###
///               * miscellaneous Debug signals
///               ###
///               %unsigned 28 DBGROMADDR                0x0
///                                    ###
///                                    * Input Debug ROM base address.
///                                    * Specifies bits[39:12] of the ROM table physical address.
///                                    * If the address cannot be determined, tie this signal LOW.
///                                    * This pin is sampled only during reset of the processor.
///                                    * (Not Used)
///                                    ###
///               %unsigned 1  DBGROMADDRV               0x1
///                                    ###
///                                    * Input Debug ROM base address valid.
///                                    * If the debug ROM address cannot be determined, tie this signal LOW.
///                                    * This pin is sampled only during reset of the processor.
///                                    * DBGACK[CN:0] Output Debug acknowledge:
///                                    * 0 External debug request not acknowledged.
///                                    * 1 External debug request acknowledged.
///                                    ###
///               %%        3          # Stuffing bits...
///     # 0x00060 DEBUG1               
///               %unsigned 4  DBGACK                    0x0
///                                    ###
///                                    * Debug acknowledge:
///                                    * 0 External debug request not acknowledged.
///                                    * 1 External debug request acknowledged.
///                                    ###
///               %unsigned 4  nCOMMIRQ                  0x0
///                                    ###
///                                    * Output Communications channel receive or transmit interrupt request
///                                    * 0 Request interrupt.
///                                    * 1 No interrupt request.
///                                    ###
///               %unsigned 4  COMMRX                    0x0
///                                    ###
///                                    * Output Communications channel receive. Receive portion of Data Transfer Register full flag:
///                                    * 0 Empty.
///                                    * 1 Full.
///                                    ###
///               %unsigned 4  COMMTX                    0x0
///                                    ###
///                                    * Output Communication transmit channel. Transmit portion of Data Transfer Register empty
///                                    * flag:
///                                    * 0 Full.
///                                    * 1 Empty.
///                                    ###
///               %unsigned 4  EDBGRQ                    0x0
///                                    ###
///                                    * Input External debug request:
///                                    * 0 No external debug request.
///                                    * 1 External debug request.
///                                    * The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must
///                                    * be asserted until the processor asserts DBGACK.
///                                    ###
///               %unsigned 4  DBGEN                     0xF
///                                    ###
///                                    * Input Invasive debug enable:
///                                    * 0 Not enabled.
///                                    * 1 Enabled.
///                                    ###
///               %unsigned 4  NIDEN                     0xF
///                                    ###
///                                    * Input Non-invasive debug enable:
///                                    * 0 Not enabled.
///                                    * 1 Enabled.
///                                    * SPIDEN[CN:0] Input Secure privileged invasive debug enable:
///                                    * 0 Not enabled.
///                                    * 1 Enabled.
///                                    ###
///               %unsigned 4  SPIDEN                    0xF
///                                    ###
///                                    * Input Secure privileged invasive debug enable:
///                                    * 0 Not enabled.
///                                    * 1 Enabled.
///                                    ###
///     # 0x00064 DEBUG2               
///               %unsigned 4  SPNIDEN                   0xF
///                                    ###
///                                    * Input Secure privileged non-invasive debug enable:
///                                    * 0 Not enabled.
///                                    * 1 Enabled.
///                                    ###
///               %unsigned 4  DBGRSTREQ                 0x0
///                                    ###
///                                    * Output Warm reset request.
///                                    ###
///               %unsigned 4  DBGNOPWRDWN               0x0
///                                    ###
///                                    * Output No powerdown request:
///                                    * 0 On a powerdown request, the SoC power controller powers down the
///                                    * processor.
///                                    * 1 On a powerdown request, the SoC power controller does not power
///                                    * down the processor.
///                                    ###
///               %unsigned 4  DBGPWRUPREQ               0x0
///                                    ###
///                                    * Output Power up request:
///                                    * 0 Power down debug request to the power controller.
///                                    * 1 Power up request to the power controller.
///                                    ###
///               %unsigned 1  DBGL1RSTDISABLE           0x0
///                                    ###
///                                    * Input Disable L1 data cache automatic invalidate on reset functionality:
///                                    * 0 Enable automatic invalidation of L1 data cache on reset.
///                                    * 1 Disable automatic invalidation of L1 data cache on reset.
///                                    * This pin is sampled only during reset of the processor.
///                                    ###
///               %%        15         # Stuffing bits...
///     @ 0x00068 DFT                  (RW-)
///               ###
///               * CPU DFTControl
///               ###
///               %unsigned 1  DFTRAMHOLD                0x0
///                                    ###
///                                    * Disable the RAM chip select during scan testing
///                                    ###
///               %unsigned 1  DFTMCPHOLD                0x0
///                                    ###
///                                    * Disable Multicycle Paths on RAM interfaces
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x0006C GIC                  (RW-)
///               ###
///               * GIC signals that are not used
///               ###
///               %unsigned 4  nSEI                      0xF
///                                    ###
///                                    * System Error Interrupt request. Active-LOW, edge sensitive.
///                                    ###
///               %unsigned 4  nVSEI                     0xF
///                                    ###
///                                    * Virtual System Error Interrupt request. Active-LOW
///                                    ###
///               %unsigned 4  nREI                      0xF
///                                    ###
///                                    * RAM Error Interrupt request. Active-LOW
///                                    ###
///               %unsigned 4  nVCPUMNTIRQ               0x0
///                                    ###
///                                    * Output Virtual CPU interface maintenance interrupt PPI output.
///                                    ###
///               %unsigned 1  GICCDISABLE               0x1
///                                    ###
///                                    * Globally disables the CPU interface logic and routes the “External” signals directly to the
///                                    * processor.
///                                    * Required to enable use of non-ARM interrupt controllers.
///                                    ###
///               %unsigned 1  ICDTVALID                 0x0
///                                    ###
///                                    * Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TVALID
///                                    * indicates that the master is driving a valid transfer.
///                                    ###
///               %unsigned 1  ICDTREADY                 0x0
///                                    ###
///                                    * Output AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TREADY
///                                    * indicates that the slave can accept a transfer in the current cycle.
///                                    ###
///               %%        13         # Stuffing bits...
///     # 0x00070 GIC1                 
///               %unsigned 16 ICDTDATA                  0x0
///                                    ###
///                                    * Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TDATA is the
///                                    * primary payload that is used to provide the data that is passing across the interface.
///                                    ###
///               %unsigned 1  ICDTLAST                  0x0
///                                    ###
///                                    * Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TLAST
///                                    * indicates the boundary of a packet.
///                                    ###
///               %unsigned 2  ICDTDEST                  0x0
///                                    ###
///                                    * Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TDEST
///                                    * provides routing information for the data stream.
///                                    ###
///               %unsigned 1  ICCTVALID                 0x0
///                                    ###
///                                    * Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TVALID
///                                    * indicates that the master is driving a valid transfer.
///                                    ###
///               %unsigned 1  ICCTREADY                 0x0
///                                    ###
///                                    * Input AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TREADY
///                                    * indicates that the slave can accept a transfer in the current cycle.
///                                    ###
///               %%        11         # Stuffing bits...
///     # 0x00074 GIC2                 
///               %unsigned 16 ICCTDATA                  0x0
///                                    ###
///                                    * Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TDATA is the
///                                    * primary payload that is used to provide the data that is passing across the interface
///                                    ###
///               %unsigned 1  ICCTLAST                  0x0
///                                    ###
///                                    * Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TLAST
///                                    * indicates the boundary of a packet.
///                                    ###
///               %unsigned 2  ICCTID                    0x0
///                                    ###
///                                    * Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor. TID is the data stream
///                                    * identifier that indicates different streams of data.
///                                    ###
///               %%        13         # Stuffing bits...
///     @ 0x00078 CNT                  (RW-)
///               ###
///               * Generic Timer Signals
///               ###
///               %unsigned 1  CNTCLKEN                  0x1
///                                    ###
///                                    * Input Counter clock enable.
///                                    * This clock enable must be inserted one cycle before the CNTVALUEB bus.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x0007C ETM                  (RW-)
///               ###
///               * miscellaneous ETM trace unit signals
///               ###
///               %unsigned 1  SYNCREQM0                 0x0
///                                    ###
///                                    * Synchronization request from trace sink
///                                    ###
///               %unsigned 1  SYNCREQM1                 0x0
///                                    ###
///                                    * Synchronization request from trace sink
///                                    ###
///               %unsigned 1  SYNCREQM2                 0x0
///                                    ###
///                                    * Synchronization request from trace sink
///                                    ###
///               %unsigned 1  SYNCREQM3                 0x0
///                                    ###
///                                    * Synchronization request from trace sink
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00080 PMU                  (RW-)
///               ###
///               * PMU interfacet signals
///               ###
///               %unsigned 30 PMUEVENT0                 0x0
///                                    ###
///                                    * Output PMU event bus
///                                    ###
///               %%        2          # Stuffing bits...
///     # 0x00084 PMU1                 
///               %unsigned 30 PMUEVENT1                 0x0
///                                    ###
///                                    * Output PMU event bus
///                                    ###
///               %%        2          # Stuffing bits...
///     # 0x00088 PMU2                 
///               %unsigned 30 PMUEVENT2                 0x0
///                                    ###
///                                    * Output PMU event bus
///                                    ###
///               %%        2          # Stuffing bits...
///     # 0x0008C PMU3                 
///               %unsigned 30 PMUEVENT3                 0x0
///                                    ###
///                                    * Output PMU event bus
///                                    ###
///               %%        2          # Stuffing bits...
///     @ 0x00090 PWRSW_0              (RW-)
///               ###
///               * Core 0 PWRSW ctrl : by default pwrsw is on and isolation disabled
///               ###
///               %unsigned 1  PWRSW_CNTRL               0x1
///               %unsigned 1  PWRSW_CNTRL2              0x1
///               %unsigned 1  PWRSW_ACK                 0x0
///               %unsigned 1  PWRSW_ACK2                0x0
///               %unsigned 1  nCPU_ISO_MODE_EN_         0x1
///               %%        27         # Stuffing bits...
///     @ 0x00094 PWRSW_1              (RW-)
///               ###
///               * Core 1 PWRSW ctrl : by default pwrsw is on and isolation disabled
///               ###
///               %unsigned 1  PWRSW_CNTRL               0x1
///               %unsigned 1  PWRSW_CNTRL2              0x1
///               %unsigned 1  PWRSW_ACK                 0x0
///               %unsigned 1  PWRSW_ACK2                0x0
///               %unsigned 1  nCPU_ISO_MODE_EN_         0x1
///               %%        27         # Stuffing bits...
///     @ 0x00098 PWRSW_2              (RW-)
///               ###
///               * Core 2 PWRSW ctrl : by default pwrsw is on and isolation disabled
///               ###
///               %unsigned 1  PWRSW_CNTRL               0x1
///               %unsigned 1  PWRSW_CNTRL2              0x1
///               %unsigned 1  PWRSW_ACK                 0x0
///               %unsigned 1  PWRSW_ACK2                0x0
///               %unsigned 1  nCPU_ISO_MODE_EN_         0x1
///               %%        27         # Stuffing bits...
///     @ 0x0009C PWRSW_3              (RW-)
///               ###
///               * Core 3 PWRSW ctrl : by default pwrsw is on and isolation disabled
///               ###
///               %unsigned 1  PWRSW_CNTRL               0x1
///               %unsigned 1  PWRSW_CNTRL2              0x1
///               %unsigned 1  PWRSW_ACK                 0x0
///               %unsigned 1  PWRSW_ACK2                0x0
///               %unsigned 1  nCPU_ISO_MODE_EN_         0x1
///               %%        27         # Stuffing bits...
///     @ 0x000A0 CSSY_CTRL            (P)
///               ###
///               * CoreSight control
///               ###
///               %unsigned 1  dbgen                     0x1
///                                    ###
///                                    * Invasive Debug Enable
///                                    ###
///               %unsigned 1  spiden                    0x1
///                                    ###
///                                    * Secure Invasive Debug Enable
///                                    ###
///               %unsigned 1  niden                     0x1
///                                    ###
///                                    * Non Invasive Debug Enable
///                                    ###
///               %unsigned 1  spniden                   0x1
///                                    ###
///                                    * Secure Non Invasive Debug Enable
///                                    ###
///               %unsigned 1  DEVICEEN                  0x1
///                                    ###
///                                    * Enable APB-AP interface
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x000A4 Cpu0ExtPmu           (P)
///               ###
///               * CPU0 PMU Controls
///               ###
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables the CPU0 PMU Control of the power switch and reset signals.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000A8 Cpu1ExtPmu           (P)
///               ###
///               * CPU1 PMU Controls
///               ###
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables the CPU1 PMU Control of the power switch and reset signals.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000AC Cpu2ExtPmu           (P)
///               ###
///               * CPU2 PMU Controls
///               ###
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables the CPU2 PMU Control of the power switch and reset signals.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000B0 Cpu3ExtPmu           (P)
///               ###
///               * CPU3 PMU Controls
///               ###
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables the CPU3 PMU Control of the power switch and reset signals.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000B4 CpuPmuPwrSwDly       (P)
///               %unsigned 26 PwrSwDly                  0x0
///                                    ###
///                                    * Delay time from assertion of PwrSw1 to PwrSw2. Runs on a 25MHz clock.
///                                    ###
///               %%        6          # Stuffing bits...
///     @ 0x000B8 CpuPmuRstDly         (P)
///               %unsigned 26 PwrSwDly                  0x0
///                                    ###
///                                    * Delay time from PwrSw2 to ISO. RST is released 1 cycle after ISO. Runs on 25MHz clock.
///                                    ###
///               %%        6          # Stuffing bits...
///     @ 0x000BC Cpu0WarmRst          (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU0 Warm Reset by detecting WARMRSTREQ and WFI. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000C0 Cpu1WarmRst          (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU1 Warm Reset by detecting WARMRSTREQ and WFI. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000C4 Cpu2WarmRst          (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU2 Warm Reset by detecting WARMRSTREQ and WFI. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000C8 Cpu3WarmRst          (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU3 Warm Reset by detecting WARMRSTREQ and WFI. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000CC Cpu0DbgWarmRst       (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU0 DBG Warm Reset by detecting DBGRSTREQ. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000D0 Cpu1DbgWarmRst       (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU1 DBG Warm Reset by detecting DBGRSTREQ. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000D4 Cpu2DbgWarmRst       (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU2 DBG Warm Reset by detecting DBGRSTREQ. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000D8 Cpu3DbgWarmRst       (P)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Enables CPU3 DBG Warm Reset by detecting DBGRSTREQ. Once detected will reset the respective core.
///                                    ###
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     220B, bits:     510b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CPU_REG
#define h_CPU_REG (){}

    #define     RA_CPU_REG_SRRESET_MP                          0x0000

    #define     BA_CPU_REG_SRRESET_MP_nRESETALL                0x0000
    #define     B16CPU_REG_SRRESET_MP_nRESETALL                0x0000
    #define   LSb32CPU_REG_SRRESET_MP_nRESETALL                   0
    #define   LSb16CPU_REG_SRRESET_MP_nRESETALL                   0
    #define       bCPU_REG_SRRESET_MP_nRESETALL                1
    #define   MSK32CPU_REG_SRRESET_MP_nRESETALL                   0x00000001

    #define     BA_CPU_REG_SRRESET_MP_nL2RESET                 0x0000
    #define     B16CPU_REG_SRRESET_MP_nL2RESET                 0x0000
    #define   LSb32CPU_REG_SRRESET_MP_nL2RESET                    1
    #define   LSb16CPU_REG_SRRESET_MP_nL2RESET                    1
    #define       bCPU_REG_SRRESET_MP_nL2RESET                 1
    #define   MSK32CPU_REG_SRRESET_MP_nL2RESET                    0x00000002

    #define     BA_CPU_REG_SRRESET_MP_nPRESETDBG               0x0000
    #define     B16CPU_REG_SRRESET_MP_nPRESETDBG               0x0000
    #define   LSb32CPU_REG_SRRESET_MP_nPRESETDBG                  2
    #define   LSb16CPU_REG_SRRESET_MP_nPRESETDBG                  2
    #define       bCPU_REG_SRRESET_MP_nPRESETDBG               1
    #define   MSK32CPU_REG_SRRESET_MP_nPRESETDBG                  0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_SRRESET_0                           0x0004

    #define     BA_CPU_REG_SRRESET_0_nCPUPORESET               0x0004
    #define     B16CPU_REG_SRRESET_0_nCPUPORESET               0x0004
    #define   LSb32CPU_REG_SRRESET_0_nCPUPORESET                  0
    #define   LSb16CPU_REG_SRRESET_0_nCPUPORESET                  0
    #define       bCPU_REG_SRRESET_0_nCPUPORESET               1
    #define   MSK32CPU_REG_SRRESET_0_nCPUPORESET                  0x00000001

    #define     BA_CPU_REG_SRRESET_0_nCORERESET                0x0004
    #define     B16CPU_REG_SRRESET_0_nCORERESET                0x0004
    #define   LSb32CPU_REG_SRRESET_0_nCORERESET                   1
    #define   LSb16CPU_REG_SRRESET_0_nCORERESET                   1
    #define       bCPU_REG_SRRESET_0_nCORERESET                1
    #define   MSK32CPU_REG_SRRESET_0_nCORERESET                   0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_SRRESET_1                           0x0008

    #define     BA_CPU_REG_SRRESET_1_nCPUPORESET               0x0008
    #define     B16CPU_REG_SRRESET_1_nCPUPORESET               0x0008
    #define   LSb32CPU_REG_SRRESET_1_nCPUPORESET                  0
    #define   LSb16CPU_REG_SRRESET_1_nCPUPORESET                  0
    #define       bCPU_REG_SRRESET_1_nCPUPORESET               1
    #define   MSK32CPU_REG_SRRESET_1_nCPUPORESET                  0x00000001

    #define     BA_CPU_REG_SRRESET_1_nCORERESET                0x0008
    #define     B16CPU_REG_SRRESET_1_nCORERESET                0x0008
    #define   LSb32CPU_REG_SRRESET_1_nCORERESET                   1
    #define   LSb16CPU_REG_SRRESET_1_nCORERESET                   1
    #define       bCPU_REG_SRRESET_1_nCORERESET                1
    #define   MSK32CPU_REG_SRRESET_1_nCORERESET                   0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_SRRESET_2                           0x000C

    #define     BA_CPU_REG_SRRESET_2_nCPUPORESET               0x000C
    #define     B16CPU_REG_SRRESET_2_nCPUPORESET               0x000C
    #define   LSb32CPU_REG_SRRESET_2_nCPUPORESET                  0
    #define   LSb16CPU_REG_SRRESET_2_nCPUPORESET                  0
    #define       bCPU_REG_SRRESET_2_nCPUPORESET               1
    #define   MSK32CPU_REG_SRRESET_2_nCPUPORESET                  0x00000001

    #define     BA_CPU_REG_SRRESET_2_nCORERESET                0x000C
    #define     B16CPU_REG_SRRESET_2_nCORERESET                0x000C
    #define   LSb32CPU_REG_SRRESET_2_nCORERESET                   1
    #define   LSb16CPU_REG_SRRESET_2_nCORERESET                   1
    #define       bCPU_REG_SRRESET_2_nCORERESET                1
    #define   MSK32CPU_REG_SRRESET_2_nCORERESET                   0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_SRRESET_3                           0x0010

    #define     BA_CPU_REG_SRRESET_3_nCPUPORESET               0x0010
    #define     B16CPU_REG_SRRESET_3_nCPUPORESET               0x0010
    #define   LSb32CPU_REG_SRRESET_3_nCPUPORESET                  0
    #define   LSb16CPU_REG_SRRESET_3_nCPUPORESET                  0
    #define       bCPU_REG_SRRESET_3_nCPUPORESET               1
    #define   MSK32CPU_REG_SRRESET_3_nCPUPORESET                  0x00000001

    #define     BA_CPU_REG_SRRESET_3_nCORERESET                0x0010
    #define     B16CPU_REG_SRRESET_3_nCORERESET                0x0010
    #define   LSb32CPU_REG_SRRESET_3_nCORERESET                   1
    #define   LSb16CPU_REG_SRRESET_3_nCORERESET                   1
    #define       bCPU_REG_SRRESET_3_nCORERESET                1
    #define   MSK32CPU_REG_SRRESET_3_nCORERESET                   0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_RESET_MP                            0x0014

    #define     BA_CPU_REG_RESET_MP_nRESETALL                  0x0014
    #define     B16CPU_REG_RESET_MP_nRESETALL                  0x0014
    #define   LSb32CPU_REG_RESET_MP_nRESETALL                     0
    #define   LSb16CPU_REG_RESET_MP_nRESETALL                     0
    #define       bCPU_REG_RESET_MP_nRESETALL                  1
    #define   MSK32CPU_REG_RESET_MP_nRESETALL                     0x00000001

    #define     BA_CPU_REG_RESET_MP_nL2RESET                   0x0014
    #define     B16CPU_REG_RESET_MP_nL2RESET                   0x0014
    #define   LSb32CPU_REG_RESET_MP_nL2RESET                      1
    #define   LSb16CPU_REG_RESET_MP_nL2RESET                      1
    #define       bCPU_REG_RESET_MP_nL2RESET                   1
    #define   MSK32CPU_REG_RESET_MP_nL2RESET                      0x00000002

    #define     BA_CPU_REG_RESET_MP_nPRESETDBG                 0x0014
    #define     B16CPU_REG_RESET_MP_nPRESETDBG                 0x0014
    #define   LSb32CPU_REG_RESET_MP_nPRESETDBG                    2
    #define   LSb16CPU_REG_RESET_MP_nPRESETDBG                    2
    #define       bCPU_REG_RESET_MP_nPRESETDBG                 1
    #define   MSK32CPU_REG_RESET_MP_nPRESETDBG                    0x00000004

    #define     BA_CPU_REG_RESET_MP_L2RSTDISABLE               0x0014
    #define     B16CPU_REG_RESET_MP_L2RSTDISABLE               0x0014
    #define   LSb32CPU_REG_RESET_MP_L2RSTDISABLE                  3
    #define   LSb16CPU_REG_RESET_MP_L2RSTDISABLE                  3
    #define       bCPU_REG_RESET_MP_L2RSTDISABLE               1
    #define   MSK32CPU_REG_RESET_MP_L2RSTDISABLE                  0x00000008

    #define     BA_CPU_REG_RESET_MP_RESETCPUTIMER              0x0014
    #define     B16CPU_REG_RESET_MP_RESETCPUTIMER              0x0014
    #define   LSb32CPU_REG_RESET_MP_RESETCPUTIMER                 4
    #define   LSb16CPU_REG_RESET_MP_RESETCPUTIMER                 4
    #define       bCPU_REG_RESET_MP_RESETCPUTIMER              1
    #define   MSK32CPU_REG_RESET_MP_RESETCPUTIMER                 0x00000010

    #define     BA_CPU_REG_RESET_MP_RESETPTMTIMER              0x0014
    #define     B16CPU_REG_RESET_MP_RESETPTMTIMER              0x0014
    #define   LSb32CPU_REG_RESET_MP_RESETPTMTIMER                 5
    #define   LSb16CPU_REG_RESET_MP_RESETPTMTIMER                 5
    #define       bCPU_REG_RESET_MP_RESETPTMTIMER              1
    #define   MSK32CPU_REG_RESET_MP_RESETPTMTIMER                 0x00000020

    #define     BA_CPU_REG_RESET_MP_nMBISTRESET                0x0014
    #define     B16CPU_REG_RESET_MP_nMBISTRESET                0x0014
    #define   LSb32CPU_REG_RESET_MP_nMBISTRESET                   6
    #define   LSb16CPU_REG_RESET_MP_nMBISTRESET                   6
    #define       bCPU_REG_RESET_MP_nMBISTRESET                1
    #define   MSK32CPU_REG_RESET_MP_nMBISTRESET                   0x00000040

    #define     BA_CPU_REG_RESET_MP_L2_FNRST                   0x0014
    #define     B16CPU_REG_RESET_MP_L2_FNRST                   0x0014
    #define   LSb32CPU_REG_RESET_MP_L2_FNRST                      7
    #define   LSb16CPU_REG_RESET_MP_L2_FNRST                      7
    #define       bCPU_REG_RESET_MP_L2_FNRST                   1
    #define   MSK32CPU_REG_RESET_MP_L2_FNRST                      0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_RESET_0                             0x0018

    #define     BA_CPU_REG_RESET_0_nCPUPORESET                 0x0018
    #define     B16CPU_REG_RESET_0_nCPUPORESET                 0x0018
    #define   LSb32CPU_REG_RESET_0_nCPUPORESET                    0
    #define   LSb16CPU_REG_RESET_0_nCPUPORESET                    0
    #define       bCPU_REG_RESET_0_nCPUPORESET                 1
    #define   MSK32CPU_REG_RESET_0_nCPUPORESET                    0x00000001

    #define     BA_CPU_REG_RESET_0_nCORERESET                  0x0018
    #define     B16CPU_REG_RESET_0_nCORERESET                  0x0018
    #define   LSb32CPU_REG_RESET_0_nCORERESET                     1
    #define   LSb16CPU_REG_RESET_0_nCORERESET                     1
    #define       bCPU_REG_RESET_0_nCORERESET                  1
    #define   MSK32CPU_REG_RESET_0_nCORERESET                     0x00000002

    #define     BA_CPU_REG_RESET_0_WARMRSTREQ                  0x0018
    #define     B16CPU_REG_RESET_0_WARMRSTREQ                  0x0018
    #define   LSb32CPU_REG_RESET_0_WARMRSTREQ                     2
    #define   LSb16CPU_REG_RESET_0_WARMRSTREQ                     2
    #define       bCPU_REG_RESET_0_WARMRSTREQ                  1
    #define   MSK32CPU_REG_RESET_0_WARMRSTREQ                     0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_RESET_1                             0x001C

    #define     BA_CPU_REG_RESET_1_nCPUPORESET                 0x001C
    #define     B16CPU_REG_RESET_1_nCPUPORESET                 0x001C
    #define   LSb32CPU_REG_RESET_1_nCPUPORESET                    0
    #define   LSb16CPU_REG_RESET_1_nCPUPORESET                    0
    #define       bCPU_REG_RESET_1_nCPUPORESET                 1
    #define   MSK32CPU_REG_RESET_1_nCPUPORESET                    0x00000001

    #define     BA_CPU_REG_RESET_1_nCORERESET                  0x001C
    #define     B16CPU_REG_RESET_1_nCORERESET                  0x001C
    #define   LSb32CPU_REG_RESET_1_nCORERESET                     1
    #define   LSb16CPU_REG_RESET_1_nCORERESET                     1
    #define       bCPU_REG_RESET_1_nCORERESET                  1
    #define   MSK32CPU_REG_RESET_1_nCORERESET                     0x00000002

    #define     BA_CPU_REG_RESET_1_WARMRSTREQ                  0x001C
    #define     B16CPU_REG_RESET_1_WARMRSTREQ                  0x001C
    #define   LSb32CPU_REG_RESET_1_WARMRSTREQ                     2
    #define   LSb16CPU_REG_RESET_1_WARMRSTREQ                     2
    #define       bCPU_REG_RESET_1_WARMRSTREQ                  1
    #define   MSK32CPU_REG_RESET_1_WARMRSTREQ                     0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_RESET_2                             0x0020

    #define     BA_CPU_REG_RESET_2_nCPUPORESET                 0x0020
    #define     B16CPU_REG_RESET_2_nCPUPORESET                 0x0020
    #define   LSb32CPU_REG_RESET_2_nCPUPORESET                    0
    #define   LSb16CPU_REG_RESET_2_nCPUPORESET                    0
    #define       bCPU_REG_RESET_2_nCPUPORESET                 1
    #define   MSK32CPU_REG_RESET_2_nCPUPORESET                    0x00000001

    #define     BA_CPU_REG_RESET_2_nCORERESET                  0x0020
    #define     B16CPU_REG_RESET_2_nCORERESET                  0x0020
    #define   LSb32CPU_REG_RESET_2_nCORERESET                     1
    #define   LSb16CPU_REG_RESET_2_nCORERESET                     1
    #define       bCPU_REG_RESET_2_nCORERESET                  1
    #define   MSK32CPU_REG_RESET_2_nCORERESET                     0x00000002

    #define     BA_CPU_REG_RESET_2_WARMRSTREQ                  0x0020
    #define     B16CPU_REG_RESET_2_WARMRSTREQ                  0x0020
    #define   LSb32CPU_REG_RESET_2_WARMRSTREQ                     2
    #define   LSb16CPU_REG_RESET_2_WARMRSTREQ                     2
    #define       bCPU_REG_RESET_2_WARMRSTREQ                  1
    #define   MSK32CPU_REG_RESET_2_WARMRSTREQ                     0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_RESET_3                             0x0024

    #define     BA_CPU_REG_RESET_3_nCPUPORESET                 0x0024
    #define     B16CPU_REG_RESET_3_nCPUPORESET                 0x0024
    #define   LSb32CPU_REG_RESET_3_nCPUPORESET                    0
    #define   LSb16CPU_REG_RESET_3_nCPUPORESET                    0
    #define       bCPU_REG_RESET_3_nCPUPORESET                 1
    #define   MSK32CPU_REG_RESET_3_nCPUPORESET                    0x00000001

    #define     BA_CPU_REG_RESET_3_nCORERESET                  0x0024
    #define     B16CPU_REG_RESET_3_nCORERESET                  0x0024
    #define   LSb32CPU_REG_RESET_3_nCORERESET                     1
    #define   LSb16CPU_REG_RESET_3_nCORERESET                     1
    #define       bCPU_REG_RESET_3_nCORERESET                  1
    #define   MSK32CPU_REG_RESET_3_nCORERESET                     0x00000002

    #define     BA_CPU_REG_RESET_3_WARMRSTREQ                  0x0024
    #define     B16CPU_REG_RESET_3_WARMRSTREQ                  0x0024
    #define   LSb32CPU_REG_RESET_3_WARMRSTREQ                     2
    #define   LSb16CPU_REG_RESET_3_WARMRSTREQ                     2
    #define       bCPU_REG_RESET_3_WARMRSTREQ                  1
    #define   MSK32CPU_REG_RESET_3_WARMRSTREQ                     0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_CFG                                 0x0028

    #define     BA_CPU_REG_CFG_AA64nAA32                       0x0028
    #define     B16CPU_REG_CFG_AA64nAA32                       0x0028
    #define   LSb32CPU_REG_CFG_AA64nAA32                          0
    #define   LSb16CPU_REG_CFG_AA64nAA32                          0
    #define       bCPU_REG_CFG_AA64nAA32                       4
    #define   MSK32CPU_REG_CFG_AA64nAA32                          0x0000000F

    #define     BA_CPU_REG_CFG_CFGEND                          0x0028
    #define     B16CPU_REG_CFG_CFGEND                          0x0028
    #define   LSb32CPU_REG_CFG_CFGEND                             4
    #define   LSb16CPU_REG_CFG_CFGEND                             4
    #define       bCPU_REG_CFG_CFGEND                          4
    #define   MSK32CPU_REG_CFG_CFGEND                             0x000000F0

    #define     BA_CPU_REG_CFG_CFGTE                           0x0029
    #define     B16CPU_REG_CFG_CFGTE                           0x0028
    #define   LSb32CPU_REG_CFG_CFGTE                              8
    #define   LSb16CPU_REG_CFG_CFGTE                              8
    #define       bCPU_REG_CFG_CFGTE                           4
    #define   MSK32CPU_REG_CFG_CFGTE                              0x00000F00

    #define     BA_CPU_REG_CFG_CLUSTERIDAFF1                   0x0029
    #define     B16CPU_REG_CFG_CLUSTERIDAFF1                   0x0028
    #define   LSb32CPU_REG_CFG_CLUSTERIDAFF1                      12
    #define   LSb16CPU_REG_CFG_CLUSTERIDAFF1                      12
    #define       bCPU_REG_CFG_CLUSTERIDAFF1                   8
    #define   MSK32CPU_REG_CFG_CLUSTERIDAFF1                      0x000FF000

    #define     BA_CPU_REG_CFG_CLUSTERIDAFF2                   0x002A
    #define     B16CPU_REG_CFG_CLUSTERIDAFF2                   0x002A
    #define   LSb32CPU_REG_CFG_CLUSTERIDAFF2                      20
    #define   LSb16CPU_REG_CFG_CLUSTERIDAFF2                      4
    #define       bCPU_REG_CFG_CLUSTERIDAFF2                   8
    #define   MSK32CPU_REG_CFG_CLUSTERIDAFF2                      0x0FF00000

    #define     BA_CPU_REG_CFG_CP15SDISABLE                    0x002B
    #define     B16CPU_REG_CFG_CP15SDISABLE                    0x002A
    #define   LSb32CPU_REG_CFG_CP15SDISABLE                       28
    #define   LSb16CPU_REG_CFG_CP15SDISABLE                       12
    #define       bCPU_REG_CFG_CP15SDISABLE                    4
    #define   MSK32CPU_REG_CFG_CP15SDISABLE                       0xF0000000

    #define     RA_CPU_REG_CFG1                                0x002C

    #define     BA_CPU_REG_CFG_CRYPTODISABLE                   0x002C
    #define     B16CPU_REG_CFG_CRYPTODISABLE                   0x002C
    #define   LSb32CPU_REG_CFG_CRYPTODISABLE                      0
    #define   LSb16CPU_REG_CFG_CRYPTODISABLE                      0
    #define       bCPU_REG_CFG_CRYPTODISABLE                   4
    #define   MSK32CPU_REG_CFG_CRYPTODISABLE                      0x0000000F

    #define     BA_CPU_REG_CFG_VINITHI                         0x002C
    #define     B16CPU_REG_CFG_VINITHI                         0x002C
    #define   LSb32CPU_REG_CFG_VINITHI                            4
    #define   LSb16CPU_REG_CFG_VINITHI                            4
    #define       bCPU_REG_CFG_VINITHI                         4
    #define   MSK32CPU_REG_CFG_VINITHI                            0x000000F0

    #define     BA_CPU_REG_CFG_RDMEMATTR                       0x002D
    #define     B16CPU_REG_CFG_RDMEMATTR                       0x002C
    #define   LSb32CPU_REG_CFG_RDMEMATTR                          8
    #define   LSb16CPU_REG_CFG_RDMEMATTR                          8
    #define       bCPU_REG_CFG_RDMEMATTR                       8
    #define   MSK32CPU_REG_CFG_RDMEMATTR                          0x0000FF00

    #define     BA_CPU_REG_CFG_WRMEMATTR                       0x002E
    #define     B16CPU_REG_CFG_WRMEMATTR                       0x002E
    #define   LSb32CPU_REG_CFG_WRMEMATTR                          16
    #define   LSb16CPU_REG_CFG_WRMEMATTR                          0
    #define       bCPU_REG_CFG_WRMEMATTR                       8
    #define   MSK32CPU_REG_CFG_WRMEMATTR                          0x00FF0000

    #define     BA_CPU_REG_CFG_ACINACTM                        0x002F
    #define     B16CPU_REG_CFG_ACINACTM                        0x002E
    #define   LSb32CPU_REG_CFG_ACINACTM                           24
    #define   LSb16CPU_REG_CFG_ACINACTM                           8
    #define       bCPU_REG_CFG_ACINACTM                        1
    #define   MSK32CPU_REG_CFG_ACINACTM                           0x01000000
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_NO_RETENTION_MP                 0x0030

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ     0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ     0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ        0
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ        0
    #define       bCPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ     1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ        0x00000001

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK     0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK     0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK        1
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK        1
    #define       bCPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK     1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK        0x00000002

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_EVENTI          0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_EVENTI          0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_EVENTI             2
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_EVENTI             2
    #define       bCPU_REG_PWR_NO_RETENTION_MP_EVENTI          1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_EVENTI             0x00000004

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_EVENTO          0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_EVENTO          0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_EVENTO             3
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_EVENTO             3
    #define       bCPU_REG_PWR_NO_RETENTION_MP_EVENTO          1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_EVENTO             0x00000008

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2    0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2    0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2       4
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2       4
    #define       bCPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2    1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2       0x00000010

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ      0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ      0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ         5
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ         5
    #define       bCPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ         0x00000020

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE     0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE     0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE        6
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE        6
    #define       bCPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE     1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE        0x00000040

    #define     BA_CPU_REG_PWR_NO_RETENTION_MP_SMPEN           0x0030
    #define     B16CPU_REG_PWR_NO_RETENTION_MP_SMPEN           0x0030
    #define   LSb32CPU_REG_PWR_NO_RETENTION_MP_SMPEN              7
    #define   LSb16CPU_REG_PWR_NO_RETENTION_MP_SMPEN              7
    #define       bCPU_REG_PWR_NO_RETENTION_MP_SMPEN           1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_MP_SMPEN              0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_NO_RETENTION_0                  0x0034

    #define     BA_CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI       0x0034
    #define     B16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI       0x0034
    #define   LSb32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI          0
    #define   LSb16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI          0
    #define       bCPU_REG_PWR_NO_RETENTION_0_STANDBYWFI       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI          0x00000001

    #define     BA_CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE       0x0034
    #define     B16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE       0x0034
    #define   LSb32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE          1
    #define   LSb16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE          1
    #define       bCPU_REG_PWR_NO_RETENTION_0_STANDBYWFE       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE          0x00000002

    #define     BA_CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN      0x0034
    #define     B16CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN      0x0034
    #define   LSb32CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN         2
    #define   LSb16CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN         2
    #define       bCPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN         0x00000004

    #define     BA_CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ      0x0034
    #define     B16CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ      0x0034
    #define   LSb32CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ         3
    #define   LSb16CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ         3
    #define       bCPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ         0x00000008

    #define     BA_CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP        0x0034
    #define     B16CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP        0x0034
    #define   LSb32CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP           4
    #define   LSb16CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP           4
    #define       bCPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP        1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP           0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_NO_RETENTION_1                  0x0038

    #define     BA_CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI       0x0038
    #define     B16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI       0x0038
    #define   LSb32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI          0
    #define   LSb16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI          0
    #define       bCPU_REG_PWR_NO_RETENTION_1_STANDBYWFI       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI          0x00000001

    #define     BA_CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE       0x0038
    #define     B16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE       0x0038
    #define   LSb32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE          1
    #define   LSb16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE          1
    #define       bCPU_REG_PWR_NO_RETENTION_1_STANDBYWFE       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE          0x00000002

    #define     BA_CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN      0x0038
    #define     B16CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN      0x0038
    #define   LSb32CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN         2
    #define   LSb16CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN         2
    #define       bCPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN         0x00000004

    #define     BA_CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ      0x0038
    #define     B16CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ      0x0038
    #define   LSb32CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ         3
    #define   LSb16CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ         3
    #define       bCPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ         0x00000008

    #define     BA_CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP        0x0038
    #define     B16CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP        0x0038
    #define   LSb32CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP           4
    #define   LSb16CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP           4
    #define       bCPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP        1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP           0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_NO_RETENTION_2                  0x003C

    #define     BA_CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI       0x003C
    #define     B16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI       0x003C
    #define   LSb32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI          0
    #define   LSb16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI          0
    #define       bCPU_REG_PWR_NO_RETENTION_2_STANDBYWFI       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI          0x00000001

    #define     BA_CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE       0x003C
    #define     B16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE       0x003C
    #define   LSb32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE          1
    #define   LSb16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE          1
    #define       bCPU_REG_PWR_NO_RETENTION_2_STANDBYWFE       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE          0x00000002

    #define     BA_CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN      0x003C
    #define     B16CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN      0x003C
    #define   LSb32CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN         2
    #define   LSb16CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN         2
    #define       bCPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN         0x00000004

    #define     BA_CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ      0x003C
    #define     B16CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ      0x003C
    #define   LSb32CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ         3
    #define   LSb16CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ         3
    #define       bCPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ         0x00000008

    #define     BA_CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP        0x003C
    #define     B16CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP        0x003C
    #define   LSb32CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP           4
    #define   LSb16CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP           4
    #define       bCPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP        1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP           0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_NO_RETENTION_3                  0x0040

    #define     BA_CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI       0x0040
    #define     B16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI       0x0040
    #define   LSb32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI          0
    #define   LSb16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI          0
    #define       bCPU_REG_PWR_NO_RETENTION_3_STANDBYWFI       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI          0x00000001

    #define     BA_CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE       0x0040
    #define     B16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE       0x0040
    #define   LSb32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE          1
    #define   LSb16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE          1
    #define       bCPU_REG_PWR_NO_RETENTION_3_STANDBYWFE       1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE          0x00000002

    #define     BA_CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN      0x0040
    #define     B16CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN      0x0040
    #define   LSb32CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN         2
    #define   LSb16CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN         2
    #define       bCPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN         0x00000004

    #define     BA_CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ      0x0040
    #define     B16CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ      0x0040
    #define   LSb32CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ         3
    #define   LSb16CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ         3
    #define       bCPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ      1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ         0x00000008

    #define     BA_CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP        0x0040
    #define     B16CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP        0x0040
    #define   LSb32CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP           4
    #define   LSb16CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP           4
    #define       bCPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP        1
    #define   MSK32CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP           0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_RETENTION                       0x0044

    #define     BA_CPU_REG_PWR_RETENTION_L2QACTIVE             0x0044
    #define     B16CPU_REG_PWR_RETENTION_L2QACTIVE             0x0044
    #define   LSb32CPU_REG_PWR_RETENTION_L2QACTIVE                0
    #define   LSb16CPU_REG_PWR_RETENTION_L2QACTIVE                0
    #define       bCPU_REG_PWR_RETENTION_L2QACTIVE             1
    #define   MSK32CPU_REG_PWR_RETENTION_L2QACTIVE                0x00000001

    #define     BA_CPU_REG_PWR_RETENTION_L2QDENY               0x0044
    #define     B16CPU_REG_PWR_RETENTION_L2QDENY               0x0044
    #define   LSb32CPU_REG_PWR_RETENTION_L2QDENY                  1
    #define   LSb16CPU_REG_PWR_RETENTION_L2QDENY                  1
    #define       bCPU_REG_PWR_RETENTION_L2QDENY               1
    #define   MSK32CPU_REG_PWR_RETENTION_L2QDENY                  0x00000002

    #define     BA_CPU_REG_PWR_RETENTION_L2QACCEPTn            0x0044
    #define     B16CPU_REG_PWR_RETENTION_L2QACCEPTn            0x0044
    #define   LSb32CPU_REG_PWR_RETENTION_L2QACCEPTn               2
    #define   LSb16CPU_REG_PWR_RETENTION_L2QACCEPTn               2
    #define       bCPU_REG_PWR_RETENTION_L2QACCEPTn            1
    #define   MSK32CPU_REG_PWR_RETENTION_L2QACCEPTn               0x00000004

    #define     BA_CPU_REG_PWR_RETENTION_L2QREQn               0x0044
    #define     B16CPU_REG_PWR_RETENTION_L2QREQn               0x0044
    #define   LSb32CPU_REG_PWR_RETENTION_L2QREQn                  3
    #define   LSb16CPU_REG_PWR_RETENTION_L2QREQn                  3
    #define       bCPU_REG_PWR_RETENTION_L2QREQn               1
    #define   MSK32CPU_REG_PWR_RETENTION_L2QREQn                  0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_RETENTION_0                     0x0048

    #define     BA_CPU_REG_PWR_RETENTION_0_CPUQACTIVE          0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_CPUQACTIVE          0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_CPUQACTIVE             0
    #define   LSb16CPU_REG_PWR_RETENTION_0_CPUQACTIVE             0
    #define       bCPU_REG_PWR_RETENTION_0_CPUQACTIVE          1
    #define   MSK32CPU_REG_PWR_RETENTION_0_CPUQACTIVE             0x00000001

    #define     BA_CPU_REG_PWR_RETENTION_0_CPUQREQn            0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_CPUQREQn            0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_CPUQREQn               1
    #define   LSb16CPU_REG_PWR_RETENTION_0_CPUQREQn               1
    #define       bCPU_REG_PWR_RETENTION_0_CPUQREQn            1
    #define   MSK32CPU_REG_PWR_RETENTION_0_CPUQREQn               0x00000002

    #define     BA_CPU_REG_PWR_RETENTION_0_CPUQDENY            0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_CPUQDENY            0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_CPUQDENY               2
    #define   LSb16CPU_REG_PWR_RETENTION_0_CPUQDENY               2
    #define       bCPU_REG_PWR_RETENTION_0_CPUQDENY            1
    #define   MSK32CPU_REG_PWR_RETENTION_0_CPUQDENY               0x00000004

    #define     BA_CPU_REG_PWR_RETENTION_0_CPUQACCEPTn         0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_CPUQACCEPTn         0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_CPUQACCEPTn            3
    #define   LSb16CPU_REG_PWR_RETENTION_0_CPUQACCEPTn            3
    #define       bCPU_REG_PWR_RETENTION_0_CPUQACCEPTn         1
    #define   MSK32CPU_REG_PWR_RETENTION_0_CPUQACCEPTn            0x00000008

    #define     BA_CPU_REG_PWR_RETENTION_0_NEONQACTIVE         0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_NEONQACTIVE         0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_NEONQACTIVE            4
    #define   LSb16CPU_REG_PWR_RETENTION_0_NEONQACTIVE            4
    #define       bCPU_REG_PWR_RETENTION_0_NEONQACTIVE         1
    #define   MSK32CPU_REG_PWR_RETENTION_0_NEONQACTIVE            0x00000010

    #define     BA_CPU_REG_PWR_RETENTION_0_NEONQREQn           0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_NEONQREQn           0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_NEONQREQn              5
    #define   LSb16CPU_REG_PWR_RETENTION_0_NEONQREQn              5
    #define       bCPU_REG_PWR_RETENTION_0_NEONQREQn           1
    #define   MSK32CPU_REG_PWR_RETENTION_0_NEONQREQn              0x00000020

    #define     BA_CPU_REG_PWR_RETENTION_0_NEONQDENY           0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_NEONQDENY           0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_NEONQDENY              6
    #define   LSb16CPU_REG_PWR_RETENTION_0_NEONQDENY              6
    #define       bCPU_REG_PWR_RETENTION_0_NEONQDENY           1
    #define   MSK32CPU_REG_PWR_RETENTION_0_NEONQDENY              0x00000040

    #define     BA_CPU_REG_PWR_RETENTION_0_NEONQACCEPTn        0x0048
    #define     B16CPU_REG_PWR_RETENTION_0_NEONQACCEPTn        0x0048
    #define   LSb32CPU_REG_PWR_RETENTION_0_NEONQACCEPTn           7
    #define   LSb16CPU_REG_PWR_RETENTION_0_NEONQACCEPTn           7
    #define       bCPU_REG_PWR_RETENTION_0_NEONQACCEPTn        1
    #define   MSK32CPU_REG_PWR_RETENTION_0_NEONQACCEPTn           0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_RETENTION_1                     0x004C

    #define     BA_CPU_REG_PWR_RETENTION_1_CPUQACTIVE          0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_CPUQACTIVE          0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_CPUQACTIVE             0
    #define   LSb16CPU_REG_PWR_RETENTION_1_CPUQACTIVE             0
    #define       bCPU_REG_PWR_RETENTION_1_CPUQACTIVE          1
    #define   MSK32CPU_REG_PWR_RETENTION_1_CPUQACTIVE             0x00000001

    #define     BA_CPU_REG_PWR_RETENTION_1_CPUQREQn            0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_CPUQREQn            0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_CPUQREQn               1
    #define   LSb16CPU_REG_PWR_RETENTION_1_CPUQREQn               1
    #define       bCPU_REG_PWR_RETENTION_1_CPUQREQn            1
    #define   MSK32CPU_REG_PWR_RETENTION_1_CPUQREQn               0x00000002

    #define     BA_CPU_REG_PWR_RETENTION_1_CPUQDENY            0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_CPUQDENY            0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_CPUQDENY               2
    #define   LSb16CPU_REG_PWR_RETENTION_1_CPUQDENY               2
    #define       bCPU_REG_PWR_RETENTION_1_CPUQDENY            1
    #define   MSK32CPU_REG_PWR_RETENTION_1_CPUQDENY               0x00000004

    #define     BA_CPU_REG_PWR_RETENTION_1_CPUQACCEPTn         0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_CPUQACCEPTn         0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_CPUQACCEPTn            3
    #define   LSb16CPU_REG_PWR_RETENTION_1_CPUQACCEPTn            3
    #define       bCPU_REG_PWR_RETENTION_1_CPUQACCEPTn         1
    #define   MSK32CPU_REG_PWR_RETENTION_1_CPUQACCEPTn            0x00000008

    #define     BA_CPU_REG_PWR_RETENTION_1_NEONQACTIVE         0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_NEONQACTIVE         0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_NEONQACTIVE            4
    #define   LSb16CPU_REG_PWR_RETENTION_1_NEONQACTIVE            4
    #define       bCPU_REG_PWR_RETENTION_1_NEONQACTIVE         1
    #define   MSK32CPU_REG_PWR_RETENTION_1_NEONQACTIVE            0x00000010

    #define     BA_CPU_REG_PWR_RETENTION_1_NEONQREQn           0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_NEONQREQn           0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_NEONQREQn              5
    #define   LSb16CPU_REG_PWR_RETENTION_1_NEONQREQn              5
    #define       bCPU_REG_PWR_RETENTION_1_NEONQREQn           1
    #define   MSK32CPU_REG_PWR_RETENTION_1_NEONQREQn              0x00000020

    #define     BA_CPU_REG_PWR_RETENTION_1_NEONQDENY           0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_NEONQDENY           0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_NEONQDENY              6
    #define   LSb16CPU_REG_PWR_RETENTION_1_NEONQDENY              6
    #define       bCPU_REG_PWR_RETENTION_1_NEONQDENY           1
    #define   MSK32CPU_REG_PWR_RETENTION_1_NEONQDENY              0x00000040

    #define     BA_CPU_REG_PWR_RETENTION_1_NEONQACCEPTn        0x004C
    #define     B16CPU_REG_PWR_RETENTION_1_NEONQACCEPTn        0x004C
    #define   LSb32CPU_REG_PWR_RETENTION_1_NEONQACCEPTn           7
    #define   LSb16CPU_REG_PWR_RETENTION_1_NEONQACCEPTn           7
    #define       bCPU_REG_PWR_RETENTION_1_NEONQACCEPTn        1
    #define   MSK32CPU_REG_PWR_RETENTION_1_NEONQACCEPTn           0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_RETENTION_2                     0x0050

    #define     BA_CPU_REG_PWR_RETENTION_2_CPUQACTIVE          0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_CPUQACTIVE          0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_CPUQACTIVE             0
    #define   LSb16CPU_REG_PWR_RETENTION_2_CPUQACTIVE             0
    #define       bCPU_REG_PWR_RETENTION_2_CPUQACTIVE          1
    #define   MSK32CPU_REG_PWR_RETENTION_2_CPUQACTIVE             0x00000001

    #define     BA_CPU_REG_PWR_RETENTION_2_CPUQREQn            0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_CPUQREQn            0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_CPUQREQn               1
    #define   LSb16CPU_REG_PWR_RETENTION_2_CPUQREQn               1
    #define       bCPU_REG_PWR_RETENTION_2_CPUQREQn            1
    #define   MSK32CPU_REG_PWR_RETENTION_2_CPUQREQn               0x00000002

    #define     BA_CPU_REG_PWR_RETENTION_2_CPUQDENY            0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_CPUQDENY            0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_CPUQDENY               2
    #define   LSb16CPU_REG_PWR_RETENTION_2_CPUQDENY               2
    #define       bCPU_REG_PWR_RETENTION_2_CPUQDENY            1
    #define   MSK32CPU_REG_PWR_RETENTION_2_CPUQDENY               0x00000004

    #define     BA_CPU_REG_PWR_RETENTION_2_CPUQACCEPTn         0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_CPUQACCEPTn         0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_CPUQACCEPTn            3
    #define   LSb16CPU_REG_PWR_RETENTION_2_CPUQACCEPTn            3
    #define       bCPU_REG_PWR_RETENTION_2_CPUQACCEPTn         1
    #define   MSK32CPU_REG_PWR_RETENTION_2_CPUQACCEPTn            0x00000008

    #define     BA_CPU_REG_PWR_RETENTION_2_NEONQACTIVE         0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_NEONQACTIVE         0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_NEONQACTIVE            4
    #define   LSb16CPU_REG_PWR_RETENTION_2_NEONQACTIVE            4
    #define       bCPU_REG_PWR_RETENTION_2_NEONQACTIVE         1
    #define   MSK32CPU_REG_PWR_RETENTION_2_NEONQACTIVE            0x00000010

    #define     BA_CPU_REG_PWR_RETENTION_2_NEONQREQn           0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_NEONQREQn           0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_NEONQREQn              5
    #define   LSb16CPU_REG_PWR_RETENTION_2_NEONQREQn              5
    #define       bCPU_REG_PWR_RETENTION_2_NEONQREQn           1
    #define   MSK32CPU_REG_PWR_RETENTION_2_NEONQREQn              0x00000020

    #define     BA_CPU_REG_PWR_RETENTION_2_NEONQDENY           0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_NEONQDENY           0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_NEONQDENY              6
    #define   LSb16CPU_REG_PWR_RETENTION_2_NEONQDENY              6
    #define       bCPU_REG_PWR_RETENTION_2_NEONQDENY           1
    #define   MSK32CPU_REG_PWR_RETENTION_2_NEONQDENY              0x00000040

    #define     BA_CPU_REG_PWR_RETENTION_2_NEONQACCEPTn        0x0050
    #define     B16CPU_REG_PWR_RETENTION_2_NEONQACCEPTn        0x0050
    #define   LSb32CPU_REG_PWR_RETENTION_2_NEONQACCEPTn           7
    #define   LSb16CPU_REG_PWR_RETENTION_2_NEONQACCEPTn           7
    #define       bCPU_REG_PWR_RETENTION_2_NEONQACCEPTn        1
    #define   MSK32CPU_REG_PWR_RETENTION_2_NEONQACCEPTn           0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWR_RETENTION_3                     0x0054

    #define     BA_CPU_REG_PWR_RETENTION_3_CPUQACTIVE          0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_CPUQACTIVE          0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_CPUQACTIVE             0
    #define   LSb16CPU_REG_PWR_RETENTION_3_CPUQACTIVE             0
    #define       bCPU_REG_PWR_RETENTION_3_CPUQACTIVE          1
    #define   MSK32CPU_REG_PWR_RETENTION_3_CPUQACTIVE             0x00000001

    #define     BA_CPU_REG_PWR_RETENTION_3_CPUQREQn            0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_CPUQREQn            0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_CPUQREQn               1
    #define   LSb16CPU_REG_PWR_RETENTION_3_CPUQREQn               1
    #define       bCPU_REG_PWR_RETENTION_3_CPUQREQn            1
    #define   MSK32CPU_REG_PWR_RETENTION_3_CPUQREQn               0x00000002

    #define     BA_CPU_REG_PWR_RETENTION_3_CPUQDENY            0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_CPUQDENY            0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_CPUQDENY               2
    #define   LSb16CPU_REG_PWR_RETENTION_3_CPUQDENY               2
    #define       bCPU_REG_PWR_RETENTION_3_CPUQDENY            1
    #define   MSK32CPU_REG_PWR_RETENTION_3_CPUQDENY               0x00000004

    #define     BA_CPU_REG_PWR_RETENTION_3_CPUQACCEPTn         0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_CPUQACCEPTn         0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_CPUQACCEPTn            3
    #define   LSb16CPU_REG_PWR_RETENTION_3_CPUQACCEPTn            3
    #define       bCPU_REG_PWR_RETENTION_3_CPUQACCEPTn         1
    #define   MSK32CPU_REG_PWR_RETENTION_3_CPUQACCEPTn            0x00000008

    #define     BA_CPU_REG_PWR_RETENTION_3_NEONQACTIVE         0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_NEONQACTIVE         0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_NEONQACTIVE            4
    #define   LSb16CPU_REG_PWR_RETENTION_3_NEONQACTIVE            4
    #define       bCPU_REG_PWR_RETENTION_3_NEONQACTIVE         1
    #define   MSK32CPU_REG_PWR_RETENTION_3_NEONQACTIVE            0x00000010

    #define     BA_CPU_REG_PWR_RETENTION_3_NEONQREQn           0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_NEONQREQn           0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_NEONQREQn              5
    #define   LSb16CPU_REG_PWR_RETENTION_3_NEONQREQn              5
    #define       bCPU_REG_PWR_RETENTION_3_NEONQREQn           1
    #define   MSK32CPU_REG_PWR_RETENTION_3_NEONQREQn              0x00000020

    #define     BA_CPU_REG_PWR_RETENTION_3_NEONQDENY           0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_NEONQDENY           0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_NEONQDENY              6
    #define   LSb16CPU_REG_PWR_RETENTION_3_NEONQDENY              6
    #define       bCPU_REG_PWR_RETENTION_3_NEONQDENY           1
    #define   MSK32CPU_REG_PWR_RETENTION_3_NEONQDENY              0x00000040

    #define     BA_CPU_REG_PWR_RETENTION_3_NEONQACCEPTn        0x0054
    #define     B16CPU_REG_PWR_RETENTION_3_NEONQACCEPTn        0x0054
    #define   LSb32CPU_REG_PWR_RETENTION_3_NEONQACCEPTn           7
    #define   LSb16CPU_REG_PWR_RETENTION_3_NEONQACCEPTn           7
    #define       bCPU_REG_PWR_RETENTION_3_NEONQACCEPTn        1
    #define   MSK32CPU_REG_PWR_RETENTION_3_NEONQACCEPTn           0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_ACE_CHI                             0x0058

    #define     BA_CPU_REG_ACE_CHI_BROADCASTCACHEMAINT         0x0058
    #define     B16CPU_REG_ACE_CHI_BROADCASTCACHEMAINT         0x0058
    #define   LSb32CPU_REG_ACE_CHI_BROADCASTCACHEMAINT            0
    #define   LSb16CPU_REG_ACE_CHI_BROADCASTCACHEMAINT            0
    #define       bCPU_REG_ACE_CHI_BROADCASTCACHEMAINT         1
    #define   MSK32CPU_REG_ACE_CHI_BROADCASTCACHEMAINT            0x00000001

    #define     BA_CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU      0x0058
    #define     B16CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU      0x0058
    #define   LSb32CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU         1
    #define   LSb16CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU         1
    #define       bCPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU      1
    #define   MSK32CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU         0x00000002

    #define     BA_CPU_REG_ACE_CHI_BROADCASTINNER              0x0058
    #define     B16CPU_REG_ACE_CHI_BROADCASTINNER              0x0058
    #define   LSb32CPU_REG_ACE_CHI_BROADCASTINNER                 2
    #define   LSb16CPU_REG_ACE_CHI_BROADCASTINNER                 2
    #define       bCPU_REG_ACE_CHI_BROADCASTINNER              1
    #define   MSK32CPU_REG_ACE_CHI_BROADCASTINNER                 0x00000004

    #define     BA_CPU_REG_ACE_CHI_BROADCASTOUTER              0x0058
    #define     B16CPU_REG_ACE_CHI_BROADCASTOUTER              0x0058
    #define   LSb32CPU_REG_ACE_CHI_BROADCASTOUTER                 3
    #define   LSb16CPU_REG_ACE_CHI_BROADCASTOUTER                 3
    #define       bCPU_REG_ACE_CHI_BROADCASTOUTER              1
    #define   MSK32CPU_REG_ACE_CHI_BROADCASTOUTER                 0x00000008

    #define     BA_CPU_REG_ACE_CHI_SYSBARDISABLE               0x0058
    #define     B16CPU_REG_ACE_CHI_SYSBARDISABLE               0x0058
    #define   LSb32CPU_REG_ACE_CHI_SYSBARDISABLE                  4
    #define   LSb16CPU_REG_ACE_CHI_SYSBARDISABLE                  4
    #define       bCPU_REG_ACE_CHI_SYSBARDISABLE               1
    #define   MSK32CPU_REG_ACE_CHI_SYSBARDISABLE                  0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_DEBUG                               0x005C

    #define     BA_CPU_REG_DEBUG_DBGROMADDR                    0x005C
    #define     B16CPU_REG_DEBUG_DBGROMADDR                    0x005C
    #define   LSb32CPU_REG_DEBUG_DBGROMADDR                       0
    #define   LSb16CPU_REG_DEBUG_DBGROMADDR                       0
    #define       bCPU_REG_DEBUG_DBGROMADDR                    28
    #define   MSK32CPU_REG_DEBUG_DBGROMADDR                       0x0FFFFFFF

    #define     BA_CPU_REG_DEBUG_DBGROMADDRV                   0x005F
    #define     B16CPU_REG_DEBUG_DBGROMADDRV                   0x005E
    #define   LSb32CPU_REG_DEBUG_DBGROMADDRV                      28
    #define   LSb16CPU_REG_DEBUG_DBGROMADDRV                      12
    #define       bCPU_REG_DEBUG_DBGROMADDRV                   1
    #define   MSK32CPU_REG_DEBUG_DBGROMADDRV                      0x10000000

    #define     RA_CPU_REG_DEBUG1                              0x0060

    #define     BA_CPU_REG_DEBUG_DBGACK                        0x0060
    #define     B16CPU_REG_DEBUG_DBGACK                        0x0060
    #define   LSb32CPU_REG_DEBUG_DBGACK                           0
    #define   LSb16CPU_REG_DEBUG_DBGACK                           0
    #define       bCPU_REG_DEBUG_DBGACK                        4
    #define   MSK32CPU_REG_DEBUG_DBGACK                           0x0000000F

    #define     BA_CPU_REG_DEBUG_nCOMMIRQ                      0x0060
    #define     B16CPU_REG_DEBUG_nCOMMIRQ                      0x0060
    #define   LSb32CPU_REG_DEBUG_nCOMMIRQ                         4
    #define   LSb16CPU_REG_DEBUG_nCOMMIRQ                         4
    #define       bCPU_REG_DEBUG_nCOMMIRQ                      4
    #define   MSK32CPU_REG_DEBUG_nCOMMIRQ                         0x000000F0

    #define     BA_CPU_REG_DEBUG_COMMRX                        0x0061
    #define     B16CPU_REG_DEBUG_COMMRX                        0x0060
    #define   LSb32CPU_REG_DEBUG_COMMRX                           8
    #define   LSb16CPU_REG_DEBUG_COMMRX                           8
    #define       bCPU_REG_DEBUG_COMMRX                        4
    #define   MSK32CPU_REG_DEBUG_COMMRX                           0x00000F00

    #define     BA_CPU_REG_DEBUG_COMMTX                        0x0061
    #define     B16CPU_REG_DEBUG_COMMTX                        0x0060
    #define   LSb32CPU_REG_DEBUG_COMMTX                           12
    #define   LSb16CPU_REG_DEBUG_COMMTX                           12
    #define       bCPU_REG_DEBUG_COMMTX                        4
    #define   MSK32CPU_REG_DEBUG_COMMTX                           0x0000F000

    #define     BA_CPU_REG_DEBUG_EDBGRQ                        0x0062
    #define     B16CPU_REG_DEBUG_EDBGRQ                        0x0062
    #define   LSb32CPU_REG_DEBUG_EDBGRQ                           16
    #define   LSb16CPU_REG_DEBUG_EDBGRQ                           0
    #define       bCPU_REG_DEBUG_EDBGRQ                        4
    #define   MSK32CPU_REG_DEBUG_EDBGRQ                           0x000F0000

    #define     BA_CPU_REG_DEBUG_DBGEN                         0x0062
    #define     B16CPU_REG_DEBUG_DBGEN                         0x0062
    #define   LSb32CPU_REG_DEBUG_DBGEN                            20
    #define   LSb16CPU_REG_DEBUG_DBGEN                            4
    #define       bCPU_REG_DEBUG_DBGEN                         4
    #define   MSK32CPU_REG_DEBUG_DBGEN                            0x00F00000

    #define     BA_CPU_REG_DEBUG_NIDEN                         0x0063
    #define     B16CPU_REG_DEBUG_NIDEN                         0x0062
    #define   LSb32CPU_REG_DEBUG_NIDEN                            24
    #define   LSb16CPU_REG_DEBUG_NIDEN                            8
    #define       bCPU_REG_DEBUG_NIDEN                         4
    #define   MSK32CPU_REG_DEBUG_NIDEN                            0x0F000000

    #define     BA_CPU_REG_DEBUG_SPIDEN                        0x0063
    #define     B16CPU_REG_DEBUG_SPIDEN                        0x0062
    #define   LSb32CPU_REG_DEBUG_SPIDEN                           28
    #define   LSb16CPU_REG_DEBUG_SPIDEN                           12
    #define       bCPU_REG_DEBUG_SPIDEN                        4
    #define   MSK32CPU_REG_DEBUG_SPIDEN                           0xF0000000

    #define     RA_CPU_REG_DEBUG2                              0x0064

    #define     BA_CPU_REG_DEBUG_SPNIDEN                       0x0064
    #define     B16CPU_REG_DEBUG_SPNIDEN                       0x0064
    #define   LSb32CPU_REG_DEBUG_SPNIDEN                          0
    #define   LSb16CPU_REG_DEBUG_SPNIDEN                          0
    #define       bCPU_REG_DEBUG_SPNIDEN                       4
    #define   MSK32CPU_REG_DEBUG_SPNIDEN                          0x0000000F

    #define     BA_CPU_REG_DEBUG_DBGRSTREQ                     0x0064
    #define     B16CPU_REG_DEBUG_DBGRSTREQ                     0x0064
    #define   LSb32CPU_REG_DEBUG_DBGRSTREQ                        4
    #define   LSb16CPU_REG_DEBUG_DBGRSTREQ                        4
    #define       bCPU_REG_DEBUG_DBGRSTREQ                     4
    #define   MSK32CPU_REG_DEBUG_DBGRSTREQ                        0x000000F0

    #define     BA_CPU_REG_DEBUG_DBGNOPWRDWN                   0x0065
    #define     B16CPU_REG_DEBUG_DBGNOPWRDWN                   0x0064
    #define   LSb32CPU_REG_DEBUG_DBGNOPWRDWN                      8
    #define   LSb16CPU_REG_DEBUG_DBGNOPWRDWN                      8
    #define       bCPU_REG_DEBUG_DBGNOPWRDWN                   4
    #define   MSK32CPU_REG_DEBUG_DBGNOPWRDWN                      0x00000F00

    #define     BA_CPU_REG_DEBUG_DBGPWRUPREQ                   0x0065
    #define     B16CPU_REG_DEBUG_DBGPWRUPREQ                   0x0064
    #define   LSb32CPU_REG_DEBUG_DBGPWRUPREQ                      12
    #define   LSb16CPU_REG_DEBUG_DBGPWRUPREQ                      12
    #define       bCPU_REG_DEBUG_DBGPWRUPREQ                   4
    #define   MSK32CPU_REG_DEBUG_DBGPWRUPREQ                      0x0000F000

    #define     BA_CPU_REG_DEBUG_DBGL1RSTDISABLE               0x0066
    #define     B16CPU_REG_DEBUG_DBGL1RSTDISABLE               0x0066
    #define   LSb32CPU_REG_DEBUG_DBGL1RSTDISABLE                  16
    #define   LSb16CPU_REG_DEBUG_DBGL1RSTDISABLE                  0
    #define       bCPU_REG_DEBUG_DBGL1RSTDISABLE               1
    #define   MSK32CPU_REG_DEBUG_DBGL1RSTDISABLE                  0x00010000
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_DFT                                 0x0068

    #define     BA_CPU_REG_DFT_DFTRAMHOLD                      0x0068
    #define     B16CPU_REG_DFT_DFTRAMHOLD                      0x0068
    #define   LSb32CPU_REG_DFT_DFTRAMHOLD                         0
    #define   LSb16CPU_REG_DFT_DFTRAMHOLD                         0
    #define       bCPU_REG_DFT_DFTRAMHOLD                      1
    #define   MSK32CPU_REG_DFT_DFTRAMHOLD                         0x00000001

    #define     BA_CPU_REG_DFT_DFTMCPHOLD                      0x0068
    #define     B16CPU_REG_DFT_DFTMCPHOLD                      0x0068
    #define   LSb32CPU_REG_DFT_DFTMCPHOLD                         1
    #define   LSb16CPU_REG_DFT_DFTMCPHOLD                         1
    #define       bCPU_REG_DFT_DFTMCPHOLD                      1
    #define   MSK32CPU_REG_DFT_DFTMCPHOLD                         0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_GIC                                 0x006C

    #define     BA_CPU_REG_GIC_nSEI                            0x006C
    #define     B16CPU_REG_GIC_nSEI                            0x006C
    #define   LSb32CPU_REG_GIC_nSEI                               0
    #define   LSb16CPU_REG_GIC_nSEI                               0
    #define       bCPU_REG_GIC_nSEI                            4
    #define   MSK32CPU_REG_GIC_nSEI                               0x0000000F

    #define     BA_CPU_REG_GIC_nVSEI                           0x006C
    #define     B16CPU_REG_GIC_nVSEI                           0x006C
    #define   LSb32CPU_REG_GIC_nVSEI                              4
    #define   LSb16CPU_REG_GIC_nVSEI                              4
    #define       bCPU_REG_GIC_nVSEI                           4
    #define   MSK32CPU_REG_GIC_nVSEI                              0x000000F0

    #define     BA_CPU_REG_GIC_nREI                            0x006D
    #define     B16CPU_REG_GIC_nREI                            0x006C
    #define   LSb32CPU_REG_GIC_nREI                               8
    #define   LSb16CPU_REG_GIC_nREI                               8
    #define       bCPU_REG_GIC_nREI                            4
    #define   MSK32CPU_REG_GIC_nREI                               0x00000F00

    #define     BA_CPU_REG_GIC_nVCPUMNTIRQ                     0x006D
    #define     B16CPU_REG_GIC_nVCPUMNTIRQ                     0x006C
    #define   LSb32CPU_REG_GIC_nVCPUMNTIRQ                        12
    #define   LSb16CPU_REG_GIC_nVCPUMNTIRQ                        12
    #define       bCPU_REG_GIC_nVCPUMNTIRQ                     4
    #define   MSK32CPU_REG_GIC_nVCPUMNTIRQ                        0x0000F000

    #define     BA_CPU_REG_GIC_GICCDISABLE                     0x006E
    #define     B16CPU_REG_GIC_GICCDISABLE                     0x006E
    #define   LSb32CPU_REG_GIC_GICCDISABLE                        16
    #define   LSb16CPU_REG_GIC_GICCDISABLE                        0
    #define       bCPU_REG_GIC_GICCDISABLE                     1
    #define   MSK32CPU_REG_GIC_GICCDISABLE                        0x00010000

    #define     BA_CPU_REG_GIC_ICDTVALID                       0x006E
    #define     B16CPU_REG_GIC_ICDTVALID                       0x006E
    #define   LSb32CPU_REG_GIC_ICDTVALID                          17
    #define   LSb16CPU_REG_GIC_ICDTVALID                          1
    #define       bCPU_REG_GIC_ICDTVALID                       1
    #define   MSK32CPU_REG_GIC_ICDTVALID                          0x00020000

    #define     BA_CPU_REG_GIC_ICDTREADY                       0x006E
    #define     B16CPU_REG_GIC_ICDTREADY                       0x006E
    #define   LSb32CPU_REG_GIC_ICDTREADY                          18
    #define   LSb16CPU_REG_GIC_ICDTREADY                          2
    #define       bCPU_REG_GIC_ICDTREADY                       1
    #define   MSK32CPU_REG_GIC_ICDTREADY                          0x00040000

    #define     RA_CPU_REG_GIC1                                0x0070

    #define     BA_CPU_REG_GIC_ICDTDATA                        0x0070
    #define     B16CPU_REG_GIC_ICDTDATA                        0x0070
    #define   LSb32CPU_REG_GIC_ICDTDATA                           0
    #define   LSb16CPU_REG_GIC_ICDTDATA                           0
    #define       bCPU_REG_GIC_ICDTDATA                        16
    #define   MSK32CPU_REG_GIC_ICDTDATA                           0x0000FFFF

    #define     BA_CPU_REG_GIC_ICDTLAST                        0x0072
    #define     B16CPU_REG_GIC_ICDTLAST                        0x0072
    #define   LSb32CPU_REG_GIC_ICDTLAST                           16
    #define   LSb16CPU_REG_GIC_ICDTLAST                           0
    #define       bCPU_REG_GIC_ICDTLAST                        1
    #define   MSK32CPU_REG_GIC_ICDTLAST                           0x00010000

    #define     BA_CPU_REG_GIC_ICDTDEST                        0x0072
    #define     B16CPU_REG_GIC_ICDTDEST                        0x0072
    #define   LSb32CPU_REG_GIC_ICDTDEST                           17
    #define   LSb16CPU_REG_GIC_ICDTDEST                           1
    #define       bCPU_REG_GIC_ICDTDEST                        2
    #define   MSK32CPU_REG_GIC_ICDTDEST                           0x00060000

    #define     BA_CPU_REG_GIC_ICCTVALID                       0x0072
    #define     B16CPU_REG_GIC_ICCTVALID                       0x0072
    #define   LSb32CPU_REG_GIC_ICCTVALID                          19
    #define   LSb16CPU_REG_GIC_ICCTVALID                          3
    #define       bCPU_REG_GIC_ICCTVALID                       1
    #define   MSK32CPU_REG_GIC_ICCTVALID                          0x00080000

    #define     BA_CPU_REG_GIC_ICCTREADY                       0x0072
    #define     B16CPU_REG_GIC_ICCTREADY                       0x0072
    #define   LSb32CPU_REG_GIC_ICCTREADY                          20
    #define   LSb16CPU_REG_GIC_ICCTREADY                          4
    #define       bCPU_REG_GIC_ICCTREADY                       1
    #define   MSK32CPU_REG_GIC_ICCTREADY                          0x00100000

    #define     RA_CPU_REG_GIC2                                0x0074

    #define     BA_CPU_REG_GIC_ICCTDATA                        0x0074
    #define     B16CPU_REG_GIC_ICCTDATA                        0x0074
    #define   LSb32CPU_REG_GIC_ICCTDATA                           0
    #define   LSb16CPU_REG_GIC_ICCTDATA                           0
    #define       bCPU_REG_GIC_ICCTDATA                        16
    #define   MSK32CPU_REG_GIC_ICCTDATA                           0x0000FFFF

    #define     BA_CPU_REG_GIC_ICCTLAST                        0x0076
    #define     B16CPU_REG_GIC_ICCTLAST                        0x0076
    #define   LSb32CPU_REG_GIC_ICCTLAST                           16
    #define   LSb16CPU_REG_GIC_ICCTLAST                           0
    #define       bCPU_REG_GIC_ICCTLAST                        1
    #define   MSK32CPU_REG_GIC_ICCTLAST                           0x00010000

    #define     BA_CPU_REG_GIC_ICCTID                          0x0076
    #define     B16CPU_REG_GIC_ICCTID                          0x0076
    #define   LSb32CPU_REG_GIC_ICCTID                             17
    #define   LSb16CPU_REG_GIC_ICCTID                             1
    #define       bCPU_REG_GIC_ICCTID                          2
    #define   MSK32CPU_REG_GIC_ICCTID                             0x00060000
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_CNT                                 0x0078

    #define     BA_CPU_REG_CNT_CNTCLKEN                        0x0078
    #define     B16CPU_REG_CNT_CNTCLKEN                        0x0078
    #define   LSb32CPU_REG_CNT_CNTCLKEN                           0
    #define   LSb16CPU_REG_CNT_CNTCLKEN                           0
    #define       bCPU_REG_CNT_CNTCLKEN                        1
    #define   MSK32CPU_REG_CNT_CNTCLKEN                           0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_ETM                                 0x007C

    #define     BA_CPU_REG_ETM_SYNCREQM0                       0x007C
    #define     B16CPU_REG_ETM_SYNCREQM0                       0x007C
    #define   LSb32CPU_REG_ETM_SYNCREQM0                          0
    #define   LSb16CPU_REG_ETM_SYNCREQM0                          0
    #define       bCPU_REG_ETM_SYNCREQM0                       1
    #define   MSK32CPU_REG_ETM_SYNCREQM0                          0x00000001

    #define     BA_CPU_REG_ETM_SYNCREQM1                       0x007C
    #define     B16CPU_REG_ETM_SYNCREQM1                       0x007C
    #define   LSb32CPU_REG_ETM_SYNCREQM1                          1
    #define   LSb16CPU_REG_ETM_SYNCREQM1                          1
    #define       bCPU_REG_ETM_SYNCREQM1                       1
    #define   MSK32CPU_REG_ETM_SYNCREQM1                          0x00000002

    #define     BA_CPU_REG_ETM_SYNCREQM2                       0x007C
    #define     B16CPU_REG_ETM_SYNCREQM2                       0x007C
    #define   LSb32CPU_REG_ETM_SYNCREQM2                          2
    #define   LSb16CPU_REG_ETM_SYNCREQM2                          2
    #define       bCPU_REG_ETM_SYNCREQM2                       1
    #define   MSK32CPU_REG_ETM_SYNCREQM2                          0x00000004

    #define     BA_CPU_REG_ETM_SYNCREQM3                       0x007C
    #define     B16CPU_REG_ETM_SYNCREQM3                       0x007C
    #define   LSb32CPU_REG_ETM_SYNCREQM3                          3
    #define   LSb16CPU_REG_ETM_SYNCREQM3                          3
    #define       bCPU_REG_ETM_SYNCREQM3                       1
    #define   MSK32CPU_REG_ETM_SYNCREQM3                          0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PMU                                 0x0080

    #define     BA_CPU_REG_PMU_PMUEVENT0                       0x0080
    #define     B16CPU_REG_PMU_PMUEVENT0                       0x0080
    #define   LSb32CPU_REG_PMU_PMUEVENT0                          0
    #define   LSb16CPU_REG_PMU_PMUEVENT0                          0
    #define       bCPU_REG_PMU_PMUEVENT0                       30
    #define   MSK32CPU_REG_PMU_PMUEVENT0                          0x3FFFFFFF

    #define     RA_CPU_REG_PMU1                                0x0084

    #define     BA_CPU_REG_PMU_PMUEVENT1                       0x0084
    #define     B16CPU_REG_PMU_PMUEVENT1                       0x0084
    #define   LSb32CPU_REG_PMU_PMUEVENT1                          0
    #define   LSb16CPU_REG_PMU_PMUEVENT1                          0
    #define       bCPU_REG_PMU_PMUEVENT1                       30
    #define   MSK32CPU_REG_PMU_PMUEVENT1                          0x3FFFFFFF

    #define     RA_CPU_REG_PMU2                                0x0088

    #define     BA_CPU_REG_PMU_PMUEVENT2                       0x0088
    #define     B16CPU_REG_PMU_PMUEVENT2                       0x0088
    #define   LSb32CPU_REG_PMU_PMUEVENT2                          0
    #define   LSb16CPU_REG_PMU_PMUEVENT2                          0
    #define       bCPU_REG_PMU_PMUEVENT2                       30
    #define   MSK32CPU_REG_PMU_PMUEVENT2                          0x3FFFFFFF

    #define     RA_CPU_REG_PMU3                                0x008C

    #define     BA_CPU_REG_PMU_PMUEVENT3                       0x008C
    #define     B16CPU_REG_PMU_PMUEVENT3                       0x008C
    #define   LSb32CPU_REG_PMU_PMUEVENT3                          0
    #define   LSb16CPU_REG_PMU_PMUEVENT3                          0
    #define       bCPU_REG_PMU_PMUEVENT3                       30
    #define   MSK32CPU_REG_PMU_PMUEVENT3                          0x3FFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWRSW_0                             0x0090

    #define     BA_CPU_REG_PWRSW_0_PWRSW_CNTRL                 0x0090
    #define     B16CPU_REG_PWRSW_0_PWRSW_CNTRL                 0x0090
    #define   LSb32CPU_REG_PWRSW_0_PWRSW_CNTRL                    0
    #define   LSb16CPU_REG_PWRSW_0_PWRSW_CNTRL                    0
    #define       bCPU_REG_PWRSW_0_PWRSW_CNTRL                 1
    #define   MSK32CPU_REG_PWRSW_0_PWRSW_CNTRL                    0x00000001

    #define     BA_CPU_REG_PWRSW_0_PWRSW_CNTRL2                0x0090
    #define     B16CPU_REG_PWRSW_0_PWRSW_CNTRL2                0x0090
    #define   LSb32CPU_REG_PWRSW_0_PWRSW_CNTRL2                   1
    #define   LSb16CPU_REG_PWRSW_0_PWRSW_CNTRL2                   1
    #define       bCPU_REG_PWRSW_0_PWRSW_CNTRL2                1
    #define   MSK32CPU_REG_PWRSW_0_PWRSW_CNTRL2                   0x00000002

    #define     BA_CPU_REG_PWRSW_0_PWRSW_ACK                   0x0090
    #define     B16CPU_REG_PWRSW_0_PWRSW_ACK                   0x0090
    #define   LSb32CPU_REG_PWRSW_0_PWRSW_ACK                      2
    #define   LSb16CPU_REG_PWRSW_0_PWRSW_ACK                      2
    #define       bCPU_REG_PWRSW_0_PWRSW_ACK                   1
    #define   MSK32CPU_REG_PWRSW_0_PWRSW_ACK                      0x00000004

    #define     BA_CPU_REG_PWRSW_0_PWRSW_ACK2                  0x0090
    #define     B16CPU_REG_PWRSW_0_PWRSW_ACK2                  0x0090
    #define   LSb32CPU_REG_PWRSW_0_PWRSW_ACK2                     3
    #define   LSb16CPU_REG_PWRSW_0_PWRSW_ACK2                     3
    #define       bCPU_REG_PWRSW_0_PWRSW_ACK2                  1
    #define   MSK32CPU_REG_PWRSW_0_PWRSW_ACK2                     0x00000008

    #define     BA_CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_           0x0090
    #define     B16CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_           0x0090
    #define   LSb32CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_              4
    #define   LSb16CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_              4
    #define       bCPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_           1
    #define   MSK32CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_              0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWRSW_1                             0x0094

    #define     BA_CPU_REG_PWRSW_1_PWRSW_CNTRL                 0x0094
    #define     B16CPU_REG_PWRSW_1_PWRSW_CNTRL                 0x0094
    #define   LSb32CPU_REG_PWRSW_1_PWRSW_CNTRL                    0
    #define   LSb16CPU_REG_PWRSW_1_PWRSW_CNTRL                    0
    #define       bCPU_REG_PWRSW_1_PWRSW_CNTRL                 1
    #define   MSK32CPU_REG_PWRSW_1_PWRSW_CNTRL                    0x00000001

    #define     BA_CPU_REG_PWRSW_1_PWRSW_CNTRL2                0x0094
    #define     B16CPU_REG_PWRSW_1_PWRSW_CNTRL2                0x0094
    #define   LSb32CPU_REG_PWRSW_1_PWRSW_CNTRL2                   1
    #define   LSb16CPU_REG_PWRSW_1_PWRSW_CNTRL2                   1
    #define       bCPU_REG_PWRSW_1_PWRSW_CNTRL2                1
    #define   MSK32CPU_REG_PWRSW_1_PWRSW_CNTRL2                   0x00000002

    #define     BA_CPU_REG_PWRSW_1_PWRSW_ACK                   0x0094
    #define     B16CPU_REG_PWRSW_1_PWRSW_ACK                   0x0094
    #define   LSb32CPU_REG_PWRSW_1_PWRSW_ACK                      2
    #define   LSb16CPU_REG_PWRSW_1_PWRSW_ACK                      2
    #define       bCPU_REG_PWRSW_1_PWRSW_ACK                   1
    #define   MSK32CPU_REG_PWRSW_1_PWRSW_ACK                      0x00000004

    #define     BA_CPU_REG_PWRSW_1_PWRSW_ACK2                  0x0094
    #define     B16CPU_REG_PWRSW_1_PWRSW_ACK2                  0x0094
    #define   LSb32CPU_REG_PWRSW_1_PWRSW_ACK2                     3
    #define   LSb16CPU_REG_PWRSW_1_PWRSW_ACK2                     3
    #define       bCPU_REG_PWRSW_1_PWRSW_ACK2                  1
    #define   MSK32CPU_REG_PWRSW_1_PWRSW_ACK2                     0x00000008

    #define     BA_CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_           0x0094
    #define     B16CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_           0x0094
    #define   LSb32CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_              4
    #define   LSb16CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_              4
    #define       bCPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_           1
    #define   MSK32CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_              0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWRSW_2                             0x0098

    #define     BA_CPU_REG_PWRSW_2_PWRSW_CNTRL                 0x0098
    #define     B16CPU_REG_PWRSW_2_PWRSW_CNTRL                 0x0098
    #define   LSb32CPU_REG_PWRSW_2_PWRSW_CNTRL                    0
    #define   LSb16CPU_REG_PWRSW_2_PWRSW_CNTRL                    0
    #define       bCPU_REG_PWRSW_2_PWRSW_CNTRL                 1
    #define   MSK32CPU_REG_PWRSW_2_PWRSW_CNTRL                    0x00000001

    #define     BA_CPU_REG_PWRSW_2_PWRSW_CNTRL2                0x0098
    #define     B16CPU_REG_PWRSW_2_PWRSW_CNTRL2                0x0098
    #define   LSb32CPU_REG_PWRSW_2_PWRSW_CNTRL2                   1
    #define   LSb16CPU_REG_PWRSW_2_PWRSW_CNTRL2                   1
    #define       bCPU_REG_PWRSW_2_PWRSW_CNTRL2                1
    #define   MSK32CPU_REG_PWRSW_2_PWRSW_CNTRL2                   0x00000002

    #define     BA_CPU_REG_PWRSW_2_PWRSW_ACK                   0x0098
    #define     B16CPU_REG_PWRSW_2_PWRSW_ACK                   0x0098
    #define   LSb32CPU_REG_PWRSW_2_PWRSW_ACK                      2
    #define   LSb16CPU_REG_PWRSW_2_PWRSW_ACK                      2
    #define       bCPU_REG_PWRSW_2_PWRSW_ACK                   1
    #define   MSK32CPU_REG_PWRSW_2_PWRSW_ACK                      0x00000004

    #define     BA_CPU_REG_PWRSW_2_PWRSW_ACK2                  0x0098
    #define     B16CPU_REG_PWRSW_2_PWRSW_ACK2                  0x0098
    #define   LSb32CPU_REG_PWRSW_2_PWRSW_ACK2                     3
    #define   LSb16CPU_REG_PWRSW_2_PWRSW_ACK2                     3
    #define       bCPU_REG_PWRSW_2_PWRSW_ACK2                  1
    #define   MSK32CPU_REG_PWRSW_2_PWRSW_ACK2                     0x00000008

    #define     BA_CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_           0x0098
    #define     B16CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_           0x0098
    #define   LSb32CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_              4
    #define   LSb16CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_              4
    #define       bCPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_           1
    #define   MSK32CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_              0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_PWRSW_3                             0x009C

    #define     BA_CPU_REG_PWRSW_3_PWRSW_CNTRL                 0x009C
    #define     B16CPU_REG_PWRSW_3_PWRSW_CNTRL                 0x009C
    #define   LSb32CPU_REG_PWRSW_3_PWRSW_CNTRL                    0
    #define   LSb16CPU_REG_PWRSW_3_PWRSW_CNTRL                    0
    #define       bCPU_REG_PWRSW_3_PWRSW_CNTRL                 1
    #define   MSK32CPU_REG_PWRSW_3_PWRSW_CNTRL                    0x00000001

    #define     BA_CPU_REG_PWRSW_3_PWRSW_CNTRL2                0x009C
    #define     B16CPU_REG_PWRSW_3_PWRSW_CNTRL2                0x009C
    #define   LSb32CPU_REG_PWRSW_3_PWRSW_CNTRL2                   1
    #define   LSb16CPU_REG_PWRSW_3_PWRSW_CNTRL2                   1
    #define       bCPU_REG_PWRSW_3_PWRSW_CNTRL2                1
    #define   MSK32CPU_REG_PWRSW_3_PWRSW_CNTRL2                   0x00000002

    #define     BA_CPU_REG_PWRSW_3_PWRSW_ACK                   0x009C
    #define     B16CPU_REG_PWRSW_3_PWRSW_ACK                   0x009C
    #define   LSb32CPU_REG_PWRSW_3_PWRSW_ACK                      2
    #define   LSb16CPU_REG_PWRSW_3_PWRSW_ACK                      2
    #define       bCPU_REG_PWRSW_3_PWRSW_ACK                   1
    #define   MSK32CPU_REG_PWRSW_3_PWRSW_ACK                      0x00000004

    #define     BA_CPU_REG_PWRSW_3_PWRSW_ACK2                  0x009C
    #define     B16CPU_REG_PWRSW_3_PWRSW_ACK2                  0x009C
    #define   LSb32CPU_REG_PWRSW_3_PWRSW_ACK2                     3
    #define   LSb16CPU_REG_PWRSW_3_PWRSW_ACK2                     3
    #define       bCPU_REG_PWRSW_3_PWRSW_ACK2                  1
    #define   MSK32CPU_REG_PWRSW_3_PWRSW_ACK2                     0x00000008

    #define     BA_CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_           0x009C
    #define     B16CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_           0x009C
    #define   LSb32CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_              4
    #define   LSb16CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_              4
    #define       bCPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_           1
    #define   MSK32CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_              0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_CSSY_CTRL                           0x00A0

    #define     BA_CPU_REG_CSSY_CTRL_dbgen                     0x00A0
    #define     B16CPU_REG_CSSY_CTRL_dbgen                     0x00A0
    #define   LSb32CPU_REG_CSSY_CTRL_dbgen                        0
    #define   LSb16CPU_REG_CSSY_CTRL_dbgen                        0
    #define       bCPU_REG_CSSY_CTRL_dbgen                     1
    #define   MSK32CPU_REG_CSSY_CTRL_dbgen                        0x00000001

    #define     BA_CPU_REG_CSSY_CTRL_spiden                    0x00A0
    #define     B16CPU_REG_CSSY_CTRL_spiden                    0x00A0
    #define   LSb32CPU_REG_CSSY_CTRL_spiden                       1
    #define   LSb16CPU_REG_CSSY_CTRL_spiden                       1
    #define       bCPU_REG_CSSY_CTRL_spiden                    1
    #define   MSK32CPU_REG_CSSY_CTRL_spiden                       0x00000002

    #define     BA_CPU_REG_CSSY_CTRL_niden                     0x00A0
    #define     B16CPU_REG_CSSY_CTRL_niden                     0x00A0
    #define   LSb32CPU_REG_CSSY_CTRL_niden                        2
    #define   LSb16CPU_REG_CSSY_CTRL_niden                        2
    #define       bCPU_REG_CSSY_CTRL_niden                     1
    #define   MSK32CPU_REG_CSSY_CTRL_niden                        0x00000004

    #define     BA_CPU_REG_CSSY_CTRL_spniden                   0x00A0
    #define     B16CPU_REG_CSSY_CTRL_spniden                   0x00A0
    #define   LSb32CPU_REG_CSSY_CTRL_spniden                      3
    #define   LSb16CPU_REG_CSSY_CTRL_spniden                      3
    #define       bCPU_REG_CSSY_CTRL_spniden                   1
    #define   MSK32CPU_REG_CSSY_CTRL_spniden                      0x00000008

    #define     BA_CPU_REG_CSSY_CTRL_DEVICEEN                  0x00A0
    #define     B16CPU_REG_CSSY_CTRL_DEVICEEN                  0x00A0
    #define   LSb32CPU_REG_CSSY_CTRL_DEVICEEN                     4
    #define   LSb16CPU_REG_CSSY_CTRL_DEVICEEN                     4
    #define       bCPU_REG_CSSY_CTRL_DEVICEEN                  1
    #define   MSK32CPU_REG_CSSY_CTRL_DEVICEEN                     0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu0ExtPmu                          0x00A4

    #define     BA_CPU_REG_Cpu0ExtPmu_En                       0x00A4
    #define     B16CPU_REG_Cpu0ExtPmu_En                       0x00A4
    #define   LSb32CPU_REG_Cpu0ExtPmu_En                          0
    #define   LSb16CPU_REG_Cpu0ExtPmu_En                          0
    #define       bCPU_REG_Cpu0ExtPmu_En                       1
    #define   MSK32CPU_REG_Cpu0ExtPmu_En                          0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu1ExtPmu                          0x00A8

    #define     BA_CPU_REG_Cpu1ExtPmu_En                       0x00A8
    #define     B16CPU_REG_Cpu1ExtPmu_En                       0x00A8
    #define   LSb32CPU_REG_Cpu1ExtPmu_En                          0
    #define   LSb16CPU_REG_Cpu1ExtPmu_En                          0
    #define       bCPU_REG_Cpu1ExtPmu_En                       1
    #define   MSK32CPU_REG_Cpu1ExtPmu_En                          0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu2ExtPmu                          0x00AC

    #define     BA_CPU_REG_Cpu2ExtPmu_En                       0x00AC
    #define     B16CPU_REG_Cpu2ExtPmu_En                       0x00AC
    #define   LSb32CPU_REG_Cpu2ExtPmu_En                          0
    #define   LSb16CPU_REG_Cpu2ExtPmu_En                          0
    #define       bCPU_REG_Cpu2ExtPmu_En                       1
    #define   MSK32CPU_REG_Cpu2ExtPmu_En                          0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu3ExtPmu                          0x00B0

    #define     BA_CPU_REG_Cpu3ExtPmu_En                       0x00B0
    #define     B16CPU_REG_Cpu3ExtPmu_En                       0x00B0
    #define   LSb32CPU_REG_Cpu3ExtPmu_En                          0
    #define   LSb16CPU_REG_Cpu3ExtPmu_En                          0
    #define       bCPU_REG_Cpu3ExtPmu_En                       1
    #define   MSK32CPU_REG_Cpu3ExtPmu_En                          0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_CpuPmuPwrSwDly                      0x00B4

    #define     BA_CPU_REG_CpuPmuPwrSwDly_PwrSwDly             0x00B4
    #define     B16CPU_REG_CpuPmuPwrSwDly_PwrSwDly             0x00B4
    #define   LSb32CPU_REG_CpuPmuPwrSwDly_PwrSwDly                0
    #define   LSb16CPU_REG_CpuPmuPwrSwDly_PwrSwDly                0
    #define       bCPU_REG_CpuPmuPwrSwDly_PwrSwDly             26
    #define   MSK32CPU_REG_CpuPmuPwrSwDly_PwrSwDly                0x03FFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_CpuPmuRstDly                        0x00B8

    #define     BA_CPU_REG_CpuPmuRstDly_PwrSwDly               0x00B8
    #define     B16CPU_REG_CpuPmuRstDly_PwrSwDly               0x00B8
    #define   LSb32CPU_REG_CpuPmuRstDly_PwrSwDly                  0
    #define   LSb16CPU_REG_CpuPmuRstDly_PwrSwDly                  0
    #define       bCPU_REG_CpuPmuRstDly_PwrSwDly               26
    #define   MSK32CPU_REG_CpuPmuRstDly_PwrSwDly                  0x03FFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu0WarmRst                         0x00BC

    #define     BA_CPU_REG_Cpu0WarmRst_En                      0x00BC
    #define     B16CPU_REG_Cpu0WarmRst_En                      0x00BC
    #define   LSb32CPU_REG_Cpu0WarmRst_En                         0
    #define   LSb16CPU_REG_Cpu0WarmRst_En                         0
    #define       bCPU_REG_Cpu0WarmRst_En                      1
    #define   MSK32CPU_REG_Cpu0WarmRst_En                         0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu1WarmRst                         0x00C0

    #define     BA_CPU_REG_Cpu1WarmRst_En                      0x00C0
    #define     B16CPU_REG_Cpu1WarmRst_En                      0x00C0
    #define   LSb32CPU_REG_Cpu1WarmRst_En                         0
    #define   LSb16CPU_REG_Cpu1WarmRst_En                         0
    #define       bCPU_REG_Cpu1WarmRst_En                      1
    #define   MSK32CPU_REG_Cpu1WarmRst_En                         0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu2WarmRst                         0x00C4

    #define     BA_CPU_REG_Cpu2WarmRst_En                      0x00C4
    #define     B16CPU_REG_Cpu2WarmRst_En                      0x00C4
    #define   LSb32CPU_REG_Cpu2WarmRst_En                         0
    #define   LSb16CPU_REG_Cpu2WarmRst_En                         0
    #define       bCPU_REG_Cpu2WarmRst_En                      1
    #define   MSK32CPU_REG_Cpu2WarmRst_En                         0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu3WarmRst                         0x00C8

    #define     BA_CPU_REG_Cpu3WarmRst_En                      0x00C8
    #define     B16CPU_REG_Cpu3WarmRst_En                      0x00C8
    #define   LSb32CPU_REG_Cpu3WarmRst_En                         0
    #define   LSb16CPU_REG_Cpu3WarmRst_En                         0
    #define       bCPU_REG_Cpu3WarmRst_En                      1
    #define   MSK32CPU_REG_Cpu3WarmRst_En                         0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu0DbgWarmRst                      0x00CC

    #define     BA_CPU_REG_Cpu0DbgWarmRst_En                   0x00CC
    #define     B16CPU_REG_Cpu0DbgWarmRst_En                   0x00CC
    #define   LSb32CPU_REG_Cpu0DbgWarmRst_En                      0
    #define   LSb16CPU_REG_Cpu0DbgWarmRst_En                      0
    #define       bCPU_REG_Cpu0DbgWarmRst_En                   1
    #define   MSK32CPU_REG_Cpu0DbgWarmRst_En                      0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu1DbgWarmRst                      0x00D0

    #define     BA_CPU_REG_Cpu1DbgWarmRst_En                   0x00D0
    #define     B16CPU_REG_Cpu1DbgWarmRst_En                   0x00D0
    #define   LSb32CPU_REG_Cpu1DbgWarmRst_En                      0
    #define   LSb16CPU_REG_Cpu1DbgWarmRst_En                      0
    #define       bCPU_REG_Cpu1DbgWarmRst_En                   1
    #define   MSK32CPU_REG_Cpu1DbgWarmRst_En                      0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu2DbgWarmRst                      0x00D4

    #define     BA_CPU_REG_Cpu2DbgWarmRst_En                   0x00D4
    #define     B16CPU_REG_Cpu2DbgWarmRst_En                   0x00D4
    #define   LSb32CPU_REG_Cpu2DbgWarmRst_En                      0
    #define   LSb16CPU_REG_Cpu2DbgWarmRst_En                      0
    #define       bCPU_REG_Cpu2DbgWarmRst_En                   1
    #define   MSK32CPU_REG_Cpu2DbgWarmRst_En                      0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_REG_Cpu3DbgWarmRst                      0x00D8

    #define     BA_CPU_REG_Cpu3DbgWarmRst_En                   0x00D8
    #define     B16CPU_REG_Cpu3DbgWarmRst_En                   0x00D8
    #define   LSb32CPU_REG_Cpu3DbgWarmRst_En                      0
    #define   LSb16CPU_REG_Cpu3DbgWarmRst_En                      0
    #define       bCPU_REG_Cpu3DbgWarmRst_En                   1
    #define   MSK32CPU_REG_Cpu3DbgWarmRst_En                      0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CPU_REG {
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_SRRESET_MP_nRESETALL(r32)           _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_SRRESET_MP_nRESETALL(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_SRRESET_MP_nRESETALL(r16)           _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_SRRESET_MP_nRESETALL(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_SRRESET_MP_nL2RESET(r32)            _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_SRRESET_MP_nL2RESET(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_SRRESET_MP_nL2RESET(r16)            _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_SRRESET_MP_nL2RESET(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_SRRESET_MP_nPRESETDBG(r32)          _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_SRRESET_MP_nPRESETDBG(r32,v)        _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_SRRESET_MP_nPRESETDBG(r16)          _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_SRRESET_MP_nPRESETDBG(r16,v)        _BFSET_(r16, 2, 2,v)

    #define     w32CPU_REG_SRRESET_MP                          {\
            UNSG32 uSRRESET_MP_nRESETALL                       :  1;\
            UNSG32 uSRRESET_MP_nL2RESET                        :  1;\
            UNSG32 uSRRESET_MP_nPRESETDBG                      :  1;\
            UNSG32 RSVDx0_b3                                   : 29;\
          }
    union { UNSG32 u32CPU_REG_SRRESET_MP;
            struct w32CPU_REG_SRRESET_MP;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_SRRESET_0_nCPUPORESET(r32)          _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_SRRESET_0_nCPUPORESET(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_SRRESET_0_nCPUPORESET(r16)          _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_SRRESET_0_nCPUPORESET(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_SRRESET_0_nCORERESET(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_SRRESET_0_nCORERESET(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_SRRESET_0_nCORERESET(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_SRRESET_0_nCORERESET(r16,v)         _BFSET_(r16, 1, 1,v)

    #define     w32CPU_REG_SRRESET_0                           {\
            UNSG32 uSRRESET_0_nCPUPORESET                      :  1;\
            UNSG32 uSRRESET_0_nCORERESET                       :  1;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32CPU_REG_SRRESET_0;
            struct w32CPU_REG_SRRESET_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_SRRESET_1_nCPUPORESET(r32)          _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_SRRESET_1_nCPUPORESET(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_SRRESET_1_nCPUPORESET(r16)          _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_SRRESET_1_nCPUPORESET(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_SRRESET_1_nCORERESET(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_SRRESET_1_nCORERESET(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_SRRESET_1_nCORERESET(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_SRRESET_1_nCORERESET(r16,v)         _BFSET_(r16, 1, 1,v)

    #define     w32CPU_REG_SRRESET_1                           {\
            UNSG32 uSRRESET_1_nCPUPORESET                      :  1;\
            UNSG32 uSRRESET_1_nCORERESET                       :  1;\
            UNSG32 RSVDx8_b2                                   : 30;\
          }
    union { UNSG32 u32CPU_REG_SRRESET_1;
            struct w32CPU_REG_SRRESET_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_SRRESET_2_nCPUPORESET(r32)          _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_SRRESET_2_nCPUPORESET(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_SRRESET_2_nCPUPORESET(r16)          _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_SRRESET_2_nCPUPORESET(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_SRRESET_2_nCORERESET(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_SRRESET_2_nCORERESET(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_SRRESET_2_nCORERESET(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_SRRESET_2_nCORERESET(r16,v)         _BFSET_(r16, 1, 1,v)

    #define     w32CPU_REG_SRRESET_2                           {\
            UNSG32 uSRRESET_2_nCPUPORESET                      :  1;\
            UNSG32 uSRRESET_2_nCORERESET                       :  1;\
            UNSG32 RSVDxC_b2                                   : 30;\
          }
    union { UNSG32 u32CPU_REG_SRRESET_2;
            struct w32CPU_REG_SRRESET_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_SRRESET_3_nCPUPORESET(r32)          _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_SRRESET_3_nCPUPORESET(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_SRRESET_3_nCPUPORESET(r16)          _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_SRRESET_3_nCPUPORESET(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_SRRESET_3_nCORERESET(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_SRRESET_3_nCORERESET(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_SRRESET_3_nCORERESET(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_SRRESET_3_nCORERESET(r16,v)         _BFSET_(r16, 1, 1,v)

    #define     w32CPU_REG_SRRESET_3                           {\
            UNSG32 uSRRESET_3_nCPUPORESET                      :  1;\
            UNSG32 uSRRESET_3_nCORERESET                       :  1;\
            UNSG32 RSVDx10_b2                                  : 30;\
          }
    union { UNSG32 u32CPU_REG_SRRESET_3;
            struct w32CPU_REG_SRRESET_3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_RESET_MP_nRESETALL(r32)             _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_RESET_MP_nRESETALL(r32,v)           _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_RESET_MP_nRESETALL(r16)             _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_RESET_MP_nRESETALL(r16,v)           _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_RESET_MP_nL2RESET(r32)              _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_RESET_MP_nL2RESET(r32,v)            _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_RESET_MP_nL2RESET(r16)              _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_RESET_MP_nL2RESET(r16,v)            _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_RESET_MP_nPRESETDBG(r32)            _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_RESET_MP_nPRESETDBG(r32,v)          _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_RESET_MP_nPRESETDBG(r16)            _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_RESET_MP_nPRESETDBG(r16,v)          _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_RESET_MP_L2RSTDISABLE(r32)          _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_RESET_MP_L2RSTDISABLE(r32,v)        _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_RESET_MP_L2RSTDISABLE(r16)          _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_RESET_MP_L2RSTDISABLE(r16,v)        _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_RESET_MP_RESETCPUTIMER(r32)         _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_RESET_MP_RESETCPUTIMER(r32,v)       _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_RESET_MP_RESETCPUTIMER(r16)         _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_RESET_MP_RESETCPUTIMER(r16,v)       _BFSET_(r16, 4, 4,v)

    #define   GET32CPU_REG_RESET_MP_RESETPTMTIMER(r32)         _BFGET_(r32, 5, 5)
    #define   SET32CPU_REG_RESET_MP_RESETPTMTIMER(r32,v)       _BFSET_(r32, 5, 5,v)
    #define   GET16CPU_REG_RESET_MP_RESETPTMTIMER(r16)         _BFGET_(r16, 5, 5)
    #define   SET16CPU_REG_RESET_MP_RESETPTMTIMER(r16,v)       _BFSET_(r16, 5, 5,v)

    #define   GET32CPU_REG_RESET_MP_nMBISTRESET(r32)           _BFGET_(r32, 6, 6)
    #define   SET32CPU_REG_RESET_MP_nMBISTRESET(r32,v)         _BFSET_(r32, 6, 6,v)
    #define   GET16CPU_REG_RESET_MP_nMBISTRESET(r16)           _BFGET_(r16, 6, 6)
    #define   SET16CPU_REG_RESET_MP_nMBISTRESET(r16,v)         _BFSET_(r16, 6, 6,v)

    #define   GET32CPU_REG_RESET_MP_L2_FNRST(r32)              _BFGET_(r32, 7, 7)
    #define   SET32CPU_REG_RESET_MP_L2_FNRST(r32,v)            _BFSET_(r32, 7, 7,v)
    #define   GET16CPU_REG_RESET_MP_L2_FNRST(r16)              _BFGET_(r16, 7, 7)
    #define   SET16CPU_REG_RESET_MP_L2_FNRST(r16,v)            _BFSET_(r16, 7, 7,v)

    #define     w32CPU_REG_RESET_MP                            {\
            UNSG32 uRESET_MP_nRESETALL                         :  1;\
            UNSG32 uRESET_MP_nL2RESET                          :  1;\
            UNSG32 uRESET_MP_nPRESETDBG                        :  1;\
            UNSG32 uRESET_MP_L2RSTDISABLE                      :  1;\
            UNSG32 uRESET_MP_RESETCPUTIMER                     :  1;\
            UNSG32 uRESET_MP_RESETPTMTIMER                     :  1;\
            UNSG32 uRESET_MP_nMBISTRESET                       :  1;\
            UNSG32 uRESET_MP_L2_FNRST                          :  1;\
            UNSG32 RSVDx14_b8                                  : 24;\
          }
    union { UNSG32 u32CPU_REG_RESET_MP;
            struct w32CPU_REG_RESET_MP;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_RESET_0_nCPUPORESET(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_RESET_0_nCPUPORESET(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_RESET_0_nCPUPORESET(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_RESET_0_nCPUPORESET(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_RESET_0_nCORERESET(r32)             _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_RESET_0_nCORERESET(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_RESET_0_nCORERESET(r16)             _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_RESET_0_nCORERESET(r16,v)           _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_RESET_0_WARMRSTREQ(r32)             _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_RESET_0_WARMRSTREQ(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_RESET_0_WARMRSTREQ(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_RESET_0_WARMRSTREQ(r16,v)           _BFSET_(r16, 2, 2,v)

    #define     w32CPU_REG_RESET_0                             {\
            UNSG32 uRESET_0_nCPUPORESET                        :  1;\
            UNSG32 uRESET_0_nCORERESET                         :  1;\
            UNSG32 uRESET_0_WARMRSTREQ                         :  1;\
            UNSG32 RSVDx18_b3                                  : 29;\
          }
    union { UNSG32 u32CPU_REG_RESET_0;
            struct w32CPU_REG_RESET_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_RESET_1_nCPUPORESET(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_RESET_1_nCPUPORESET(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_RESET_1_nCPUPORESET(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_RESET_1_nCPUPORESET(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_RESET_1_nCORERESET(r32)             _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_RESET_1_nCORERESET(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_RESET_1_nCORERESET(r16)             _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_RESET_1_nCORERESET(r16,v)           _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_RESET_1_WARMRSTREQ(r32)             _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_RESET_1_WARMRSTREQ(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_RESET_1_WARMRSTREQ(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_RESET_1_WARMRSTREQ(r16,v)           _BFSET_(r16, 2, 2,v)

    #define     w32CPU_REG_RESET_1                             {\
            UNSG32 uRESET_1_nCPUPORESET                        :  1;\
            UNSG32 uRESET_1_nCORERESET                         :  1;\
            UNSG32 uRESET_1_WARMRSTREQ                         :  1;\
            UNSG32 RSVDx1C_b3                                  : 29;\
          }
    union { UNSG32 u32CPU_REG_RESET_1;
            struct w32CPU_REG_RESET_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_RESET_2_nCPUPORESET(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_RESET_2_nCPUPORESET(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_RESET_2_nCPUPORESET(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_RESET_2_nCPUPORESET(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_RESET_2_nCORERESET(r32)             _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_RESET_2_nCORERESET(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_RESET_2_nCORERESET(r16)             _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_RESET_2_nCORERESET(r16,v)           _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_RESET_2_WARMRSTREQ(r32)             _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_RESET_2_WARMRSTREQ(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_RESET_2_WARMRSTREQ(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_RESET_2_WARMRSTREQ(r16,v)           _BFSET_(r16, 2, 2,v)

    #define     w32CPU_REG_RESET_2                             {\
            UNSG32 uRESET_2_nCPUPORESET                        :  1;\
            UNSG32 uRESET_2_nCORERESET                         :  1;\
            UNSG32 uRESET_2_WARMRSTREQ                         :  1;\
            UNSG32 RSVDx20_b3                                  : 29;\
          }
    union { UNSG32 u32CPU_REG_RESET_2;
            struct w32CPU_REG_RESET_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_RESET_3_nCPUPORESET(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_RESET_3_nCPUPORESET(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_RESET_3_nCPUPORESET(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_RESET_3_nCPUPORESET(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_RESET_3_nCORERESET(r32)             _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_RESET_3_nCORERESET(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_RESET_3_nCORERESET(r16)             _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_RESET_3_nCORERESET(r16,v)           _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_RESET_3_WARMRSTREQ(r32)             _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_RESET_3_WARMRSTREQ(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_RESET_3_WARMRSTREQ(r16)             _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_RESET_3_WARMRSTREQ(r16,v)           _BFSET_(r16, 2, 2,v)

    #define     w32CPU_REG_RESET_3                             {\
            UNSG32 uRESET_3_nCPUPORESET                        :  1;\
            UNSG32 uRESET_3_nCORERESET                         :  1;\
            UNSG32 uRESET_3_WARMRSTREQ                         :  1;\
            UNSG32 RSVDx24_b3                                  : 29;\
          }
    union { UNSG32 u32CPU_REG_RESET_3;
            struct w32CPU_REG_RESET_3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_CFG_AA64nAA32(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32CPU_REG_CFG_AA64nAA32(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16CPU_REG_CFG_AA64nAA32(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16CPU_REG_CFG_AA64nAA32(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32CPU_REG_CFG_CFGEND(r32)                     _BFGET_(r32, 7, 4)
    #define   SET32CPU_REG_CFG_CFGEND(r32,v)                   _BFSET_(r32, 7, 4,v)
    #define   GET16CPU_REG_CFG_CFGEND(r16)                     _BFGET_(r16, 7, 4)
    #define   SET16CPU_REG_CFG_CFGEND(r16,v)                   _BFSET_(r16, 7, 4,v)

    #define   GET32CPU_REG_CFG_CFGTE(r32)                      _BFGET_(r32,11, 8)
    #define   SET32CPU_REG_CFG_CFGTE(r32,v)                    _BFSET_(r32,11, 8,v)
    #define   GET16CPU_REG_CFG_CFGTE(r16)                      _BFGET_(r16,11, 8)
    #define   SET16CPU_REG_CFG_CFGTE(r16,v)                    _BFSET_(r16,11, 8,v)

    #define   GET32CPU_REG_CFG_CLUSTERIDAFF1(r32)              _BFGET_(r32,19,12)
    #define   SET32CPU_REG_CFG_CLUSTERIDAFF1(r32,v)            _BFSET_(r32,19,12,v)

    #define   GET32CPU_REG_CFG_CLUSTERIDAFF2(r32)              _BFGET_(r32,27,20)
    #define   SET32CPU_REG_CFG_CLUSTERIDAFF2(r32,v)            _BFSET_(r32,27,20,v)
    #define   GET16CPU_REG_CFG_CLUSTERIDAFF2(r16)              _BFGET_(r16,11, 4)
    #define   SET16CPU_REG_CFG_CLUSTERIDAFF2(r16,v)            _BFSET_(r16,11, 4,v)

    #define   GET32CPU_REG_CFG_CP15SDISABLE(r32)               _BFGET_(r32,31,28)
    #define   SET32CPU_REG_CFG_CP15SDISABLE(r32,v)             _BFSET_(r32,31,28,v)
    #define   GET16CPU_REG_CFG_CP15SDISABLE(r16)               _BFGET_(r16,15,12)
    #define   SET16CPU_REG_CFG_CP15SDISABLE(r16,v)             _BFSET_(r16,15,12,v)

    #define     w32CPU_REG_CFG                                 {\
            UNSG32 uCFG_AA64nAA32                              :  4;\
            UNSG32 uCFG_CFGEND                                 :  4;\
            UNSG32 uCFG_CFGTE                                  :  4;\
            UNSG32 uCFG_CLUSTERIDAFF1                          :  8;\
            UNSG32 uCFG_CLUSTERIDAFF2                          :  8;\
            UNSG32 uCFG_CP15SDISABLE                           :  4;\
          }
    union { UNSG32 u32CPU_REG_CFG;
            struct w32CPU_REG_CFG;
          };
    #define   GET32CPU_REG_CFG_CRYPTODISABLE(r32)              _BFGET_(r32, 3, 0)
    #define   SET32CPU_REG_CFG_CRYPTODISABLE(r32,v)            _BFSET_(r32, 3, 0,v)
    #define   GET16CPU_REG_CFG_CRYPTODISABLE(r16)              _BFGET_(r16, 3, 0)
    #define   SET16CPU_REG_CFG_CRYPTODISABLE(r16,v)            _BFSET_(r16, 3, 0,v)

    #define   GET32CPU_REG_CFG_VINITHI(r32)                    _BFGET_(r32, 7, 4)
    #define   SET32CPU_REG_CFG_VINITHI(r32,v)                  _BFSET_(r32, 7, 4,v)
    #define   GET16CPU_REG_CFG_VINITHI(r16)                    _BFGET_(r16, 7, 4)
    #define   SET16CPU_REG_CFG_VINITHI(r16,v)                  _BFSET_(r16, 7, 4,v)

    #define   GET32CPU_REG_CFG_RDMEMATTR(r32)                  _BFGET_(r32,15, 8)
    #define   SET32CPU_REG_CFG_RDMEMATTR(r32,v)                _BFSET_(r32,15, 8,v)
    #define   GET16CPU_REG_CFG_RDMEMATTR(r16)                  _BFGET_(r16,15, 8)
    #define   SET16CPU_REG_CFG_RDMEMATTR(r16,v)                _BFSET_(r16,15, 8,v)

    #define   GET32CPU_REG_CFG_WRMEMATTR(r32)                  _BFGET_(r32,23,16)
    #define   SET32CPU_REG_CFG_WRMEMATTR(r32,v)                _BFSET_(r32,23,16,v)
    #define   GET16CPU_REG_CFG_WRMEMATTR(r16)                  _BFGET_(r16, 7, 0)
    #define   SET16CPU_REG_CFG_WRMEMATTR(r16,v)                _BFSET_(r16, 7, 0,v)

    #define   GET32CPU_REG_CFG_ACINACTM(r32)                   _BFGET_(r32,24,24)
    #define   SET32CPU_REG_CFG_ACINACTM(r32,v)                 _BFSET_(r32,24,24,v)
    #define   GET16CPU_REG_CFG_ACINACTM(r16)                   _BFGET_(r16, 8, 8)
    #define   SET16CPU_REG_CFG_ACINACTM(r16,v)                 _BFSET_(r16, 8, 8,v)

    #define     w32CPU_REG_CFG1                                {\
            UNSG32 uCFG_CRYPTODISABLE                          :  4;\
            UNSG32 uCFG_VINITHI                                :  4;\
            UNSG32 uCFG_RDMEMATTR                              :  8;\
            UNSG32 uCFG_WRMEMATTR                              :  8;\
            UNSG32 uCFG_ACINACTM                               :  1;\
            UNSG32 RSVDx2C_b25                                 :  7;\
          }
    union { UNSG32 u32CPU_REG_CFG1;
            struct w32CPU_REG_CFG1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ(r32) _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ(r16) _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONREQ(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK(r32) _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK(r16) _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_CLREXMONACK(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_EVENTI(r32)     _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_EVENTI(r32,v)   _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_EVENTI(r16)     _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_EVENTI(r16,v)   _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_EVENTO(r32)     _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_EVENTO(r32,v)   _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_EVENTO(r16)     _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_EVENTO(r16,v)   _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2(r32) _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2(r16) _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_STANDBYWFIL2(r16,v) _BFSET_(r16, 4, 4,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ(r32) _BFGET_(r32, 5, 5)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ(r32,v) _BFSET_(r32, 5, 5,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ(r16) _BFGET_(r16, 5, 5)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHREQ(r16,v) _BFSET_(r16, 5, 5,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE(r32) _BFGET_(r32, 6, 6)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE(r16) _BFGET_(r16, 6, 6)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_L2FLUSHDONE(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_MP_SMPEN(r32)      _BFGET_(r32, 7, 7)
    #define   SET32CPU_REG_PWR_NO_RETENTION_MP_SMPEN(r32,v)    _BFSET_(r32, 7, 7,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_MP_SMPEN(r16)      _BFGET_(r16, 7, 7)
    #define   SET16CPU_REG_PWR_NO_RETENTION_MP_SMPEN(r16,v)    _BFSET_(r16, 7, 7,v)

    #define     w32CPU_REG_PWR_NO_RETENTION_MP                 {\
            UNSG32 uPWR_NO_RETENTION_MP_CLREXMONREQ            :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_CLREXMONACK            :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_EVENTI                 :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_EVENTO                 :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_STANDBYWFIL2           :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_L2FLUSHREQ             :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_L2FLUSHDONE            :  1;\
            UNSG32 uPWR_NO_RETENTION_MP_SMPEN                  :  1;\
            UNSG32 RSVDx30_b8                                  : 24;\
          }
    union { UNSG32 u32CPU_REG_PWR_NO_RETENTION_MP;
            struct w32CPU_REG_PWR_NO_RETENTION_MP;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI(r32)  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI(r16)  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFI(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE(r32)  _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE(r16)  _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_NO_RETENTION_0_STANDBYWFE(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN(r32) _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN(r16) _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_NO_RETENTION_0_DBGNOPWRDWN(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ(r32) _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ(r16) _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_NO_RETENTION_0_DBGPWRUPREQ(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP(r32)   _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP(r16)   _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_NO_RETENTION_0_DBGPWRDUP(r16,v) _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWR_NO_RETENTION_0                  {\
            UNSG32 uPWR_NO_RETENTION_0_STANDBYWFI              :  1;\
            UNSG32 uPWR_NO_RETENTION_0_STANDBYWFE              :  1;\
            UNSG32 uPWR_NO_RETENTION_0_DBGNOPWRDWN             :  1;\
            UNSG32 uPWR_NO_RETENTION_0_DBGPWRUPREQ             :  1;\
            UNSG32 uPWR_NO_RETENTION_0_DBGPWRDUP               :  1;\
            UNSG32 RSVDx34_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWR_NO_RETENTION_0;
            struct w32CPU_REG_PWR_NO_RETENTION_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI(r32)  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI(r16)  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFI(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE(r32)  _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE(r16)  _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_NO_RETENTION_1_STANDBYWFE(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN(r32) _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN(r16) _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_NO_RETENTION_1_DBGNOPWRDWN(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ(r32) _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ(r16) _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_NO_RETENTION_1_DBGPWRUPREQ(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP(r32)   _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP(r16)   _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_NO_RETENTION_1_DBGPWRDUP(r16,v) _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWR_NO_RETENTION_1                  {\
            UNSG32 uPWR_NO_RETENTION_1_STANDBYWFI              :  1;\
            UNSG32 uPWR_NO_RETENTION_1_STANDBYWFE              :  1;\
            UNSG32 uPWR_NO_RETENTION_1_DBGNOPWRDWN             :  1;\
            UNSG32 uPWR_NO_RETENTION_1_DBGPWRUPREQ             :  1;\
            UNSG32 uPWR_NO_RETENTION_1_DBGPWRDUP               :  1;\
            UNSG32 RSVDx38_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWR_NO_RETENTION_1;
            struct w32CPU_REG_PWR_NO_RETENTION_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI(r32)  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI(r16)  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFI(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE(r32)  _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE(r16)  _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_NO_RETENTION_2_STANDBYWFE(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN(r32) _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN(r16) _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_NO_RETENTION_2_DBGNOPWRDWN(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ(r32) _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ(r16) _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_NO_RETENTION_2_DBGPWRUPREQ(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP(r32)   _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP(r16)   _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_NO_RETENTION_2_DBGPWRDUP(r16,v) _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWR_NO_RETENTION_2                  {\
            UNSG32 uPWR_NO_RETENTION_2_STANDBYWFI              :  1;\
            UNSG32 uPWR_NO_RETENTION_2_STANDBYWFE              :  1;\
            UNSG32 uPWR_NO_RETENTION_2_DBGNOPWRDWN             :  1;\
            UNSG32 uPWR_NO_RETENTION_2_DBGPWRUPREQ             :  1;\
            UNSG32 uPWR_NO_RETENTION_2_DBGPWRDUP               :  1;\
            UNSG32 RSVDx3C_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWR_NO_RETENTION_2;
            struct w32CPU_REG_PWR_NO_RETENTION_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI(r32)  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI(r16)  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFI(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE(r32)  _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE(r16)  _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_NO_RETENTION_3_STANDBYWFE(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN(r32) _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN(r16) _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_NO_RETENTION_3_DBGNOPWRDWN(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ(r32) _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ(r16) _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_NO_RETENTION_3_DBGPWRUPREQ(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP(r32)   _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP(r16)   _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_NO_RETENTION_3_DBGPWRDUP(r16,v) _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWR_NO_RETENTION_3                  {\
            UNSG32 uPWR_NO_RETENTION_3_STANDBYWFI              :  1;\
            UNSG32 uPWR_NO_RETENTION_3_STANDBYWFE              :  1;\
            UNSG32 uPWR_NO_RETENTION_3_DBGNOPWRDWN             :  1;\
            UNSG32 uPWR_NO_RETENTION_3_DBGPWRUPREQ             :  1;\
            UNSG32 uPWR_NO_RETENTION_3_DBGPWRDUP               :  1;\
            UNSG32 RSVDx40_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWR_NO_RETENTION_3;
            struct w32CPU_REG_PWR_NO_RETENTION_3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_RETENTION_L2QACTIVE(r32)        _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_RETENTION_L2QACTIVE(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_RETENTION_L2QACTIVE(r16)        _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_RETENTION_L2QACTIVE(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_RETENTION_L2QDENY(r32)          _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_RETENTION_L2QDENY(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_RETENTION_L2QDENY(r16)          _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_RETENTION_L2QDENY(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_RETENTION_L2QACCEPTn(r32)       _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_RETENTION_L2QACCEPTn(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_RETENTION_L2QACCEPTn(r16)       _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_RETENTION_L2QACCEPTn(r16,v)     _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_RETENTION_L2QREQn(r32)          _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_RETENTION_L2QREQn(r32,v)        _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_RETENTION_L2QREQn(r16)          _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_RETENTION_L2QREQn(r16,v)        _BFSET_(r16, 3, 3,v)

    #define     w32CPU_REG_PWR_RETENTION                       {\
            UNSG32 uPWR_RETENTION_L2QACTIVE                    :  1;\
            UNSG32 uPWR_RETENTION_L2QDENY                      :  1;\
            UNSG32 uPWR_RETENTION_L2QACCEPTn                   :  1;\
            UNSG32 uPWR_RETENTION_L2QREQn                      :  1;\
            UNSG32 RSVDx44_b4                                  : 28;\
          }
    union { UNSG32 u32CPU_REG_PWR_RETENTION;
            struct w32CPU_REG_PWR_RETENTION;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_RETENTION_0_CPUQACTIVE(r32)     _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_RETENTION_0_CPUQACTIVE(r32,v)   _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_CPUQACTIVE(r16)     _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_RETENTION_0_CPUQACTIVE(r16,v)   _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_CPUQREQn(r32)       _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_RETENTION_0_CPUQREQn(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_CPUQREQn(r16)       _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_RETENTION_0_CPUQREQn(r16,v)     _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_CPUQDENY(r32)       _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_RETENTION_0_CPUQDENY(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_CPUQDENY(r16)       _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_RETENTION_0_CPUQDENY(r16,v)     _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_CPUQACCEPTn(r32)    _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_RETENTION_0_CPUQACCEPTn(r32,v)  _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_CPUQACCEPTn(r16)    _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_RETENTION_0_CPUQACCEPTn(r16,v)  _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_NEONQACTIVE(r32)    _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_RETENTION_0_NEONQACTIVE(r32,v)  _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_NEONQACTIVE(r16)    _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_RETENTION_0_NEONQACTIVE(r16,v)  _BFSET_(r16, 4, 4,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_NEONQREQn(r32)      _BFGET_(r32, 5, 5)
    #define   SET32CPU_REG_PWR_RETENTION_0_NEONQREQn(r32,v)    _BFSET_(r32, 5, 5,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_NEONQREQn(r16)      _BFGET_(r16, 5, 5)
    #define   SET16CPU_REG_PWR_RETENTION_0_NEONQREQn(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_NEONQDENY(r32)      _BFGET_(r32, 6, 6)
    #define   SET32CPU_REG_PWR_RETENTION_0_NEONQDENY(r32,v)    _BFSET_(r32, 6, 6,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_NEONQDENY(r16)      _BFGET_(r16, 6, 6)
    #define   SET16CPU_REG_PWR_RETENTION_0_NEONQDENY(r16,v)    _BFSET_(r16, 6, 6,v)

    #define   GET32CPU_REG_PWR_RETENTION_0_NEONQACCEPTn(r32)   _BFGET_(r32, 7, 7)
    #define   SET32CPU_REG_PWR_RETENTION_0_NEONQACCEPTn(r32,v) _BFSET_(r32, 7, 7,v)
    #define   GET16CPU_REG_PWR_RETENTION_0_NEONQACCEPTn(r16)   _BFGET_(r16, 7, 7)
    #define   SET16CPU_REG_PWR_RETENTION_0_NEONQACCEPTn(r16,v) _BFSET_(r16, 7, 7,v)

    #define     w32CPU_REG_PWR_RETENTION_0                     {\
            UNSG32 uPWR_RETENTION_0_CPUQACTIVE                 :  1;\
            UNSG32 uPWR_RETENTION_0_CPUQREQn                   :  1;\
            UNSG32 uPWR_RETENTION_0_CPUQDENY                   :  1;\
            UNSG32 uPWR_RETENTION_0_CPUQACCEPTn                :  1;\
            UNSG32 uPWR_RETENTION_0_NEONQACTIVE                :  1;\
            UNSG32 uPWR_RETENTION_0_NEONQREQn                  :  1;\
            UNSG32 uPWR_RETENTION_0_NEONQDENY                  :  1;\
            UNSG32 uPWR_RETENTION_0_NEONQACCEPTn               :  1;\
            UNSG32 RSVDx48_b8                                  : 24;\
          }
    union { UNSG32 u32CPU_REG_PWR_RETENTION_0;
            struct w32CPU_REG_PWR_RETENTION_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_RETENTION_1_CPUQACTIVE(r32)     _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_RETENTION_1_CPUQACTIVE(r32,v)   _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_CPUQACTIVE(r16)     _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_RETENTION_1_CPUQACTIVE(r16,v)   _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_CPUQREQn(r32)       _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_RETENTION_1_CPUQREQn(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_CPUQREQn(r16)       _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_RETENTION_1_CPUQREQn(r16,v)     _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_CPUQDENY(r32)       _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_RETENTION_1_CPUQDENY(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_CPUQDENY(r16)       _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_RETENTION_1_CPUQDENY(r16,v)     _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_CPUQACCEPTn(r32)    _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_RETENTION_1_CPUQACCEPTn(r32,v)  _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_CPUQACCEPTn(r16)    _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_RETENTION_1_CPUQACCEPTn(r16,v)  _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_NEONQACTIVE(r32)    _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_RETENTION_1_NEONQACTIVE(r32,v)  _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_NEONQACTIVE(r16)    _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_RETENTION_1_NEONQACTIVE(r16,v)  _BFSET_(r16, 4, 4,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_NEONQREQn(r32)      _BFGET_(r32, 5, 5)
    #define   SET32CPU_REG_PWR_RETENTION_1_NEONQREQn(r32,v)    _BFSET_(r32, 5, 5,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_NEONQREQn(r16)      _BFGET_(r16, 5, 5)
    #define   SET16CPU_REG_PWR_RETENTION_1_NEONQREQn(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_NEONQDENY(r32)      _BFGET_(r32, 6, 6)
    #define   SET32CPU_REG_PWR_RETENTION_1_NEONQDENY(r32,v)    _BFSET_(r32, 6, 6,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_NEONQDENY(r16)      _BFGET_(r16, 6, 6)
    #define   SET16CPU_REG_PWR_RETENTION_1_NEONQDENY(r16,v)    _BFSET_(r16, 6, 6,v)

    #define   GET32CPU_REG_PWR_RETENTION_1_NEONQACCEPTn(r32)   _BFGET_(r32, 7, 7)
    #define   SET32CPU_REG_PWR_RETENTION_1_NEONQACCEPTn(r32,v) _BFSET_(r32, 7, 7,v)
    #define   GET16CPU_REG_PWR_RETENTION_1_NEONQACCEPTn(r16)   _BFGET_(r16, 7, 7)
    #define   SET16CPU_REG_PWR_RETENTION_1_NEONQACCEPTn(r16,v) _BFSET_(r16, 7, 7,v)

    #define     w32CPU_REG_PWR_RETENTION_1                     {\
            UNSG32 uPWR_RETENTION_1_CPUQACTIVE                 :  1;\
            UNSG32 uPWR_RETENTION_1_CPUQREQn                   :  1;\
            UNSG32 uPWR_RETENTION_1_CPUQDENY                   :  1;\
            UNSG32 uPWR_RETENTION_1_CPUQACCEPTn                :  1;\
            UNSG32 uPWR_RETENTION_1_NEONQACTIVE                :  1;\
            UNSG32 uPWR_RETENTION_1_NEONQREQn                  :  1;\
            UNSG32 uPWR_RETENTION_1_NEONQDENY                  :  1;\
            UNSG32 uPWR_RETENTION_1_NEONQACCEPTn               :  1;\
            UNSG32 RSVDx4C_b8                                  : 24;\
          }
    union { UNSG32 u32CPU_REG_PWR_RETENTION_1;
            struct w32CPU_REG_PWR_RETENTION_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_RETENTION_2_CPUQACTIVE(r32)     _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_RETENTION_2_CPUQACTIVE(r32,v)   _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_CPUQACTIVE(r16)     _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_RETENTION_2_CPUQACTIVE(r16,v)   _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_CPUQREQn(r32)       _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_RETENTION_2_CPUQREQn(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_CPUQREQn(r16)       _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_RETENTION_2_CPUQREQn(r16,v)     _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_CPUQDENY(r32)       _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_RETENTION_2_CPUQDENY(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_CPUQDENY(r16)       _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_RETENTION_2_CPUQDENY(r16,v)     _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_CPUQACCEPTn(r32)    _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_RETENTION_2_CPUQACCEPTn(r32,v)  _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_CPUQACCEPTn(r16)    _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_RETENTION_2_CPUQACCEPTn(r16,v)  _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_NEONQACTIVE(r32)    _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_RETENTION_2_NEONQACTIVE(r32,v)  _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_NEONQACTIVE(r16)    _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_RETENTION_2_NEONQACTIVE(r16,v)  _BFSET_(r16, 4, 4,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_NEONQREQn(r32)      _BFGET_(r32, 5, 5)
    #define   SET32CPU_REG_PWR_RETENTION_2_NEONQREQn(r32,v)    _BFSET_(r32, 5, 5,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_NEONQREQn(r16)      _BFGET_(r16, 5, 5)
    #define   SET16CPU_REG_PWR_RETENTION_2_NEONQREQn(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_NEONQDENY(r32)      _BFGET_(r32, 6, 6)
    #define   SET32CPU_REG_PWR_RETENTION_2_NEONQDENY(r32,v)    _BFSET_(r32, 6, 6,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_NEONQDENY(r16)      _BFGET_(r16, 6, 6)
    #define   SET16CPU_REG_PWR_RETENTION_2_NEONQDENY(r16,v)    _BFSET_(r16, 6, 6,v)

    #define   GET32CPU_REG_PWR_RETENTION_2_NEONQACCEPTn(r32)   _BFGET_(r32, 7, 7)
    #define   SET32CPU_REG_PWR_RETENTION_2_NEONQACCEPTn(r32,v) _BFSET_(r32, 7, 7,v)
    #define   GET16CPU_REG_PWR_RETENTION_2_NEONQACCEPTn(r16)   _BFGET_(r16, 7, 7)
    #define   SET16CPU_REG_PWR_RETENTION_2_NEONQACCEPTn(r16,v) _BFSET_(r16, 7, 7,v)

    #define     w32CPU_REG_PWR_RETENTION_2                     {\
            UNSG32 uPWR_RETENTION_2_CPUQACTIVE                 :  1;\
            UNSG32 uPWR_RETENTION_2_CPUQREQn                   :  1;\
            UNSG32 uPWR_RETENTION_2_CPUQDENY                   :  1;\
            UNSG32 uPWR_RETENTION_2_CPUQACCEPTn                :  1;\
            UNSG32 uPWR_RETENTION_2_NEONQACTIVE                :  1;\
            UNSG32 uPWR_RETENTION_2_NEONQREQn                  :  1;\
            UNSG32 uPWR_RETENTION_2_NEONQDENY                  :  1;\
            UNSG32 uPWR_RETENTION_2_NEONQACCEPTn               :  1;\
            UNSG32 RSVDx50_b8                                  : 24;\
          }
    union { UNSG32 u32CPU_REG_PWR_RETENTION_2;
            struct w32CPU_REG_PWR_RETENTION_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWR_RETENTION_3_CPUQACTIVE(r32)     _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWR_RETENTION_3_CPUQACTIVE(r32,v)   _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_CPUQACTIVE(r16)     _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWR_RETENTION_3_CPUQACTIVE(r16,v)   _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_CPUQREQn(r32)       _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWR_RETENTION_3_CPUQREQn(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_CPUQREQn(r16)       _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWR_RETENTION_3_CPUQREQn(r16,v)     _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_CPUQDENY(r32)       _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWR_RETENTION_3_CPUQDENY(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_CPUQDENY(r16)       _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWR_RETENTION_3_CPUQDENY(r16,v)     _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_CPUQACCEPTn(r32)    _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWR_RETENTION_3_CPUQACCEPTn(r32,v)  _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_CPUQACCEPTn(r16)    _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWR_RETENTION_3_CPUQACCEPTn(r16,v)  _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_NEONQACTIVE(r32)    _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWR_RETENTION_3_NEONQACTIVE(r32,v)  _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_NEONQACTIVE(r16)    _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWR_RETENTION_3_NEONQACTIVE(r16,v)  _BFSET_(r16, 4, 4,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_NEONQREQn(r32)      _BFGET_(r32, 5, 5)
    #define   SET32CPU_REG_PWR_RETENTION_3_NEONQREQn(r32,v)    _BFSET_(r32, 5, 5,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_NEONQREQn(r16)      _BFGET_(r16, 5, 5)
    #define   SET16CPU_REG_PWR_RETENTION_3_NEONQREQn(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_NEONQDENY(r32)      _BFGET_(r32, 6, 6)
    #define   SET32CPU_REG_PWR_RETENTION_3_NEONQDENY(r32,v)    _BFSET_(r32, 6, 6,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_NEONQDENY(r16)      _BFGET_(r16, 6, 6)
    #define   SET16CPU_REG_PWR_RETENTION_3_NEONQDENY(r16,v)    _BFSET_(r16, 6, 6,v)

    #define   GET32CPU_REG_PWR_RETENTION_3_NEONQACCEPTn(r32)   _BFGET_(r32, 7, 7)
    #define   SET32CPU_REG_PWR_RETENTION_3_NEONQACCEPTn(r32,v) _BFSET_(r32, 7, 7,v)
    #define   GET16CPU_REG_PWR_RETENTION_3_NEONQACCEPTn(r16)   _BFGET_(r16, 7, 7)
    #define   SET16CPU_REG_PWR_RETENTION_3_NEONQACCEPTn(r16,v) _BFSET_(r16, 7, 7,v)

    #define     w32CPU_REG_PWR_RETENTION_3                     {\
            UNSG32 uPWR_RETENTION_3_CPUQACTIVE                 :  1;\
            UNSG32 uPWR_RETENTION_3_CPUQREQn                   :  1;\
            UNSG32 uPWR_RETENTION_3_CPUQDENY                   :  1;\
            UNSG32 uPWR_RETENTION_3_CPUQACCEPTn                :  1;\
            UNSG32 uPWR_RETENTION_3_NEONQACTIVE                :  1;\
            UNSG32 uPWR_RETENTION_3_NEONQREQn                  :  1;\
            UNSG32 uPWR_RETENTION_3_NEONQDENY                  :  1;\
            UNSG32 uPWR_RETENTION_3_NEONQACCEPTn               :  1;\
            UNSG32 RSVDx54_b8                                  : 24;\
          }
    union { UNSG32 u32CPU_REG_PWR_RETENTION_3;
            struct w32CPU_REG_PWR_RETENTION_3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_ACE_CHI_BROADCASTCACHEMAINT(r32)    _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_ACE_CHI_BROADCASTCACHEMAINT(r32,v)  _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_ACE_CHI_BROADCASTCACHEMAINT(r16)    _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_ACE_CHI_BROADCASTCACHEMAINT(r16,v)  _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU(r32) _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU(r16) _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_ACE_CHI_BROADCASTCACHEMAINTPOU(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_ACE_CHI_BROADCASTINNER(r32)         _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_ACE_CHI_BROADCASTINNER(r32,v)       _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_ACE_CHI_BROADCASTINNER(r16)         _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_ACE_CHI_BROADCASTINNER(r16,v)       _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_ACE_CHI_BROADCASTOUTER(r32)         _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_ACE_CHI_BROADCASTOUTER(r32,v)       _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_ACE_CHI_BROADCASTOUTER(r16)         _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_ACE_CHI_BROADCASTOUTER(r16,v)       _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_ACE_CHI_SYSBARDISABLE(r32)          _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_ACE_CHI_SYSBARDISABLE(r32,v)        _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_ACE_CHI_SYSBARDISABLE(r16)          _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_ACE_CHI_SYSBARDISABLE(r16,v)        _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_ACE_CHI                             {\
            UNSG32 uACE_CHI_BROADCASTCACHEMAINT                :  1;\
            UNSG32 uACE_CHI_BROADCASTCACHEMAINTPOU             :  1;\
            UNSG32 uACE_CHI_BROADCASTINNER                     :  1;\
            UNSG32 uACE_CHI_BROADCASTOUTER                     :  1;\
            UNSG32 uACE_CHI_SYSBARDISABLE                      :  1;\
            UNSG32 RSVDx58_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_ACE_CHI;
            struct w32CPU_REG_ACE_CHI;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_DEBUG_DBGROMADDR(r32)               _BFGET_(r32,27, 0)
    #define   SET32CPU_REG_DEBUG_DBGROMADDR(r32,v)             _BFSET_(r32,27, 0,v)

    #define   GET32CPU_REG_DEBUG_DBGROMADDRV(r32)              _BFGET_(r32,28,28)
    #define   SET32CPU_REG_DEBUG_DBGROMADDRV(r32,v)            _BFSET_(r32,28,28,v)
    #define   GET16CPU_REG_DEBUG_DBGROMADDRV(r16)              _BFGET_(r16,12,12)
    #define   SET16CPU_REG_DEBUG_DBGROMADDRV(r16,v)            _BFSET_(r16,12,12,v)

    #define     w32CPU_REG_DEBUG                               {\
            UNSG32 uDEBUG_DBGROMADDR                           : 28;\
            UNSG32 uDEBUG_DBGROMADDRV                          :  1;\
            UNSG32 RSVDx5C_b29                                 :  3;\
          }
    union { UNSG32 u32CPU_REG_DEBUG;
            struct w32CPU_REG_DEBUG;
          };
    #define   GET32CPU_REG_DEBUG_DBGACK(r32)                   _BFGET_(r32, 3, 0)
    #define   SET32CPU_REG_DEBUG_DBGACK(r32,v)                 _BFSET_(r32, 3, 0,v)
    #define   GET16CPU_REG_DEBUG_DBGACK(r16)                   _BFGET_(r16, 3, 0)
    #define   SET16CPU_REG_DEBUG_DBGACK(r16,v)                 _BFSET_(r16, 3, 0,v)

    #define   GET32CPU_REG_DEBUG_nCOMMIRQ(r32)                 _BFGET_(r32, 7, 4)
    #define   SET32CPU_REG_DEBUG_nCOMMIRQ(r32,v)               _BFSET_(r32, 7, 4,v)
    #define   GET16CPU_REG_DEBUG_nCOMMIRQ(r16)                 _BFGET_(r16, 7, 4)
    #define   SET16CPU_REG_DEBUG_nCOMMIRQ(r16,v)               _BFSET_(r16, 7, 4,v)

    #define   GET32CPU_REG_DEBUG_COMMRX(r32)                   _BFGET_(r32,11, 8)
    #define   SET32CPU_REG_DEBUG_COMMRX(r32,v)                 _BFSET_(r32,11, 8,v)
    #define   GET16CPU_REG_DEBUG_COMMRX(r16)                   _BFGET_(r16,11, 8)
    #define   SET16CPU_REG_DEBUG_COMMRX(r16,v)                 _BFSET_(r16,11, 8,v)

    #define   GET32CPU_REG_DEBUG_COMMTX(r32)                   _BFGET_(r32,15,12)
    #define   SET32CPU_REG_DEBUG_COMMTX(r32,v)                 _BFSET_(r32,15,12,v)
    #define   GET16CPU_REG_DEBUG_COMMTX(r16)                   _BFGET_(r16,15,12)
    #define   SET16CPU_REG_DEBUG_COMMTX(r16,v)                 _BFSET_(r16,15,12,v)

    #define   GET32CPU_REG_DEBUG_EDBGRQ(r32)                   _BFGET_(r32,19,16)
    #define   SET32CPU_REG_DEBUG_EDBGRQ(r32,v)                 _BFSET_(r32,19,16,v)
    #define   GET16CPU_REG_DEBUG_EDBGRQ(r16)                   _BFGET_(r16, 3, 0)
    #define   SET16CPU_REG_DEBUG_EDBGRQ(r16,v)                 _BFSET_(r16, 3, 0,v)

    #define   GET32CPU_REG_DEBUG_DBGEN(r32)                    _BFGET_(r32,23,20)
    #define   SET32CPU_REG_DEBUG_DBGEN(r32,v)                  _BFSET_(r32,23,20,v)
    #define   GET16CPU_REG_DEBUG_DBGEN(r16)                    _BFGET_(r16, 7, 4)
    #define   SET16CPU_REG_DEBUG_DBGEN(r16,v)                  _BFSET_(r16, 7, 4,v)

    #define   GET32CPU_REG_DEBUG_NIDEN(r32)                    _BFGET_(r32,27,24)
    #define   SET32CPU_REG_DEBUG_NIDEN(r32,v)                  _BFSET_(r32,27,24,v)
    #define   GET16CPU_REG_DEBUG_NIDEN(r16)                    _BFGET_(r16,11, 8)
    #define   SET16CPU_REG_DEBUG_NIDEN(r16,v)                  _BFSET_(r16,11, 8,v)

    #define   GET32CPU_REG_DEBUG_SPIDEN(r32)                   _BFGET_(r32,31,28)
    #define   SET32CPU_REG_DEBUG_SPIDEN(r32,v)                 _BFSET_(r32,31,28,v)
    #define   GET16CPU_REG_DEBUG_SPIDEN(r16)                   _BFGET_(r16,15,12)
    #define   SET16CPU_REG_DEBUG_SPIDEN(r16,v)                 _BFSET_(r16,15,12,v)

    #define     w32CPU_REG_DEBUG1                              {\
            UNSG32 uDEBUG_DBGACK                               :  4;\
            UNSG32 uDEBUG_nCOMMIRQ                             :  4;\
            UNSG32 uDEBUG_COMMRX                               :  4;\
            UNSG32 uDEBUG_COMMTX                               :  4;\
            UNSG32 uDEBUG_EDBGRQ                               :  4;\
            UNSG32 uDEBUG_DBGEN                                :  4;\
            UNSG32 uDEBUG_NIDEN                                :  4;\
            UNSG32 uDEBUG_SPIDEN                               :  4;\
          }
    union { UNSG32 u32CPU_REG_DEBUG1;
            struct w32CPU_REG_DEBUG1;
          };
    #define   GET32CPU_REG_DEBUG_SPNIDEN(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32CPU_REG_DEBUG_SPNIDEN(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16CPU_REG_DEBUG_SPNIDEN(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16CPU_REG_DEBUG_SPNIDEN(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32CPU_REG_DEBUG_DBGRSTREQ(r32)                _BFGET_(r32, 7, 4)
    #define   SET32CPU_REG_DEBUG_DBGRSTREQ(r32,v)              _BFSET_(r32, 7, 4,v)
    #define   GET16CPU_REG_DEBUG_DBGRSTREQ(r16)                _BFGET_(r16, 7, 4)
    #define   SET16CPU_REG_DEBUG_DBGRSTREQ(r16,v)              _BFSET_(r16, 7, 4,v)

    #define   GET32CPU_REG_DEBUG_DBGNOPWRDWN(r32)              _BFGET_(r32,11, 8)
    #define   SET32CPU_REG_DEBUG_DBGNOPWRDWN(r32,v)            _BFSET_(r32,11, 8,v)
    #define   GET16CPU_REG_DEBUG_DBGNOPWRDWN(r16)              _BFGET_(r16,11, 8)
    #define   SET16CPU_REG_DEBUG_DBGNOPWRDWN(r16,v)            _BFSET_(r16,11, 8,v)

    #define   GET32CPU_REG_DEBUG_DBGPWRUPREQ(r32)              _BFGET_(r32,15,12)
    #define   SET32CPU_REG_DEBUG_DBGPWRUPREQ(r32,v)            _BFSET_(r32,15,12,v)
    #define   GET16CPU_REG_DEBUG_DBGPWRUPREQ(r16)              _BFGET_(r16,15,12)
    #define   SET16CPU_REG_DEBUG_DBGPWRUPREQ(r16,v)            _BFSET_(r16,15,12,v)

    #define   GET32CPU_REG_DEBUG_DBGL1RSTDISABLE(r32)          _BFGET_(r32,16,16)
    #define   SET32CPU_REG_DEBUG_DBGL1RSTDISABLE(r32,v)        _BFSET_(r32,16,16,v)
    #define   GET16CPU_REG_DEBUG_DBGL1RSTDISABLE(r16)          _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_DEBUG_DBGL1RSTDISABLE(r16,v)        _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_DEBUG2                              {\
            UNSG32 uDEBUG_SPNIDEN                              :  4;\
            UNSG32 uDEBUG_DBGRSTREQ                            :  4;\
            UNSG32 uDEBUG_DBGNOPWRDWN                          :  4;\
            UNSG32 uDEBUG_DBGPWRUPREQ                          :  4;\
            UNSG32 uDEBUG_DBGL1RSTDISABLE                      :  1;\
            UNSG32 RSVDx64_b17                                 : 15;\
          }
    union { UNSG32 u32CPU_REG_DEBUG2;
            struct w32CPU_REG_DEBUG2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_DFT_DFTRAMHOLD(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_DFT_DFTRAMHOLD(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_DFT_DFTRAMHOLD(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_DFT_DFTRAMHOLD(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_DFT_DFTMCPHOLD(r32)                 _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_DFT_DFTMCPHOLD(r32,v)               _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_DFT_DFTMCPHOLD(r16)                 _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_DFT_DFTMCPHOLD(r16,v)               _BFSET_(r16, 1, 1,v)

    #define     w32CPU_REG_DFT                                 {\
            UNSG32 uDFT_DFTRAMHOLD                             :  1;\
            UNSG32 uDFT_DFTMCPHOLD                             :  1;\
            UNSG32 RSVDx68_b2                                  : 30;\
          }
    union { UNSG32 u32CPU_REG_DFT;
            struct w32CPU_REG_DFT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_GIC_nSEI(r32)                       _BFGET_(r32, 3, 0)
    #define   SET32CPU_REG_GIC_nSEI(r32,v)                     _BFSET_(r32, 3, 0,v)
    #define   GET16CPU_REG_GIC_nSEI(r16)                       _BFGET_(r16, 3, 0)
    #define   SET16CPU_REG_GIC_nSEI(r16,v)                     _BFSET_(r16, 3, 0,v)

    #define   GET32CPU_REG_GIC_nVSEI(r32)                      _BFGET_(r32, 7, 4)
    #define   SET32CPU_REG_GIC_nVSEI(r32,v)                    _BFSET_(r32, 7, 4,v)
    #define   GET16CPU_REG_GIC_nVSEI(r16)                      _BFGET_(r16, 7, 4)
    #define   SET16CPU_REG_GIC_nVSEI(r16,v)                    _BFSET_(r16, 7, 4,v)

    #define   GET32CPU_REG_GIC_nREI(r32)                       _BFGET_(r32,11, 8)
    #define   SET32CPU_REG_GIC_nREI(r32,v)                     _BFSET_(r32,11, 8,v)
    #define   GET16CPU_REG_GIC_nREI(r16)                       _BFGET_(r16,11, 8)
    #define   SET16CPU_REG_GIC_nREI(r16,v)                     _BFSET_(r16,11, 8,v)

    #define   GET32CPU_REG_GIC_nVCPUMNTIRQ(r32)                _BFGET_(r32,15,12)
    #define   SET32CPU_REG_GIC_nVCPUMNTIRQ(r32,v)              _BFSET_(r32,15,12,v)
    #define   GET16CPU_REG_GIC_nVCPUMNTIRQ(r16)                _BFGET_(r16,15,12)
    #define   SET16CPU_REG_GIC_nVCPUMNTIRQ(r16,v)              _BFSET_(r16,15,12,v)

    #define   GET32CPU_REG_GIC_GICCDISABLE(r32)                _BFGET_(r32,16,16)
    #define   SET32CPU_REG_GIC_GICCDISABLE(r32,v)              _BFSET_(r32,16,16,v)
    #define   GET16CPU_REG_GIC_GICCDISABLE(r16)                _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_GIC_GICCDISABLE(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_GIC_ICDTVALID(r32)                  _BFGET_(r32,17,17)
    #define   SET32CPU_REG_GIC_ICDTVALID(r32,v)                _BFSET_(r32,17,17,v)
    #define   GET16CPU_REG_GIC_ICDTVALID(r16)                  _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_GIC_ICDTVALID(r16,v)                _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_GIC_ICDTREADY(r32)                  _BFGET_(r32,18,18)
    #define   SET32CPU_REG_GIC_ICDTREADY(r32,v)                _BFSET_(r32,18,18,v)
    #define   GET16CPU_REG_GIC_ICDTREADY(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_GIC_ICDTREADY(r16,v)                _BFSET_(r16, 2, 2,v)

    #define     w32CPU_REG_GIC                                 {\
            UNSG32 uGIC_nSEI                                   :  4;\
            UNSG32 uGIC_nVSEI                                  :  4;\
            UNSG32 uGIC_nREI                                   :  4;\
            UNSG32 uGIC_nVCPUMNTIRQ                            :  4;\
            UNSG32 uGIC_GICCDISABLE                            :  1;\
            UNSG32 uGIC_ICDTVALID                              :  1;\
            UNSG32 uGIC_ICDTREADY                              :  1;\
            UNSG32 RSVDx6C_b19                                 : 13;\
          }
    union { UNSG32 u32CPU_REG_GIC;
            struct w32CPU_REG_GIC;
          };
    #define   GET32CPU_REG_GIC_ICDTDATA(r32)                   _BFGET_(r32,15, 0)
    #define   SET32CPU_REG_GIC_ICDTDATA(r32,v)                 _BFSET_(r32,15, 0,v)
    #define   GET16CPU_REG_GIC_ICDTDATA(r16)                   _BFGET_(r16,15, 0)
    #define   SET16CPU_REG_GIC_ICDTDATA(r16,v)                 _BFSET_(r16,15, 0,v)

    #define   GET32CPU_REG_GIC_ICDTLAST(r32)                   _BFGET_(r32,16,16)
    #define   SET32CPU_REG_GIC_ICDTLAST(r32,v)                 _BFSET_(r32,16,16,v)
    #define   GET16CPU_REG_GIC_ICDTLAST(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_GIC_ICDTLAST(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_GIC_ICDTDEST(r32)                   _BFGET_(r32,18,17)
    #define   SET32CPU_REG_GIC_ICDTDEST(r32,v)                 _BFSET_(r32,18,17,v)
    #define   GET16CPU_REG_GIC_ICDTDEST(r16)                   _BFGET_(r16, 2, 1)
    #define   SET16CPU_REG_GIC_ICDTDEST(r16,v)                 _BFSET_(r16, 2, 1,v)

    #define   GET32CPU_REG_GIC_ICCTVALID(r32)                  _BFGET_(r32,19,19)
    #define   SET32CPU_REG_GIC_ICCTVALID(r32,v)                _BFSET_(r32,19,19,v)
    #define   GET16CPU_REG_GIC_ICCTVALID(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_GIC_ICCTVALID(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_GIC_ICCTREADY(r32)                  _BFGET_(r32,20,20)
    #define   SET32CPU_REG_GIC_ICCTREADY(r32,v)                _BFSET_(r32,20,20,v)
    #define   GET16CPU_REG_GIC_ICCTREADY(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_GIC_ICCTREADY(r16,v)                _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_GIC1                                {\
            UNSG32 uGIC_ICDTDATA                               : 16;\
            UNSG32 uGIC_ICDTLAST                               :  1;\
            UNSG32 uGIC_ICDTDEST                               :  2;\
            UNSG32 uGIC_ICCTVALID                              :  1;\
            UNSG32 uGIC_ICCTREADY                              :  1;\
            UNSG32 RSVDx70_b21                                 : 11;\
          }
    union { UNSG32 u32CPU_REG_GIC1;
            struct w32CPU_REG_GIC1;
          };
    #define   GET32CPU_REG_GIC_ICCTDATA(r32)                   _BFGET_(r32,15, 0)
    #define   SET32CPU_REG_GIC_ICCTDATA(r32,v)                 _BFSET_(r32,15, 0,v)
    #define   GET16CPU_REG_GIC_ICCTDATA(r16)                   _BFGET_(r16,15, 0)
    #define   SET16CPU_REG_GIC_ICCTDATA(r16,v)                 _BFSET_(r16,15, 0,v)

    #define   GET32CPU_REG_GIC_ICCTLAST(r32)                   _BFGET_(r32,16,16)
    #define   SET32CPU_REG_GIC_ICCTLAST(r32,v)                 _BFSET_(r32,16,16,v)
    #define   GET16CPU_REG_GIC_ICCTLAST(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_GIC_ICCTLAST(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_GIC_ICCTID(r32)                     _BFGET_(r32,18,17)
    #define   SET32CPU_REG_GIC_ICCTID(r32,v)                   _BFSET_(r32,18,17,v)
    #define   GET16CPU_REG_GIC_ICCTID(r16)                     _BFGET_(r16, 2, 1)
    #define   SET16CPU_REG_GIC_ICCTID(r16,v)                   _BFSET_(r16, 2, 1,v)

    #define     w32CPU_REG_GIC2                                {\
            UNSG32 uGIC_ICCTDATA                               : 16;\
            UNSG32 uGIC_ICCTLAST                               :  1;\
            UNSG32 uGIC_ICCTID                                 :  2;\
            UNSG32 RSVDx74_b19                                 : 13;\
          }
    union { UNSG32 u32CPU_REG_GIC2;
            struct w32CPU_REG_GIC2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_CNT_CNTCLKEN(r32)                   _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_CNT_CNTCLKEN(r32,v)                 _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_CNT_CNTCLKEN(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_CNT_CNTCLKEN(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_CNT                                 {\
            UNSG32 uCNT_CNTCLKEN                               :  1;\
            UNSG32 RSVDx78_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_CNT;
            struct w32CPU_REG_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_ETM_SYNCREQM0(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_ETM_SYNCREQM0(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_ETM_SYNCREQM0(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_ETM_SYNCREQM0(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_ETM_SYNCREQM1(r32)                  _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_ETM_SYNCREQM1(r32,v)                _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_ETM_SYNCREQM1(r16)                  _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_ETM_SYNCREQM1(r16,v)                _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_ETM_SYNCREQM2(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_ETM_SYNCREQM2(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_ETM_SYNCREQM2(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_ETM_SYNCREQM2(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_ETM_SYNCREQM3(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_ETM_SYNCREQM3(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_ETM_SYNCREQM3(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_ETM_SYNCREQM3(r16,v)                _BFSET_(r16, 3, 3,v)

    #define     w32CPU_REG_ETM                                 {\
            UNSG32 uETM_SYNCREQM0                              :  1;\
            UNSG32 uETM_SYNCREQM1                              :  1;\
            UNSG32 uETM_SYNCREQM2                              :  1;\
            UNSG32 uETM_SYNCREQM3                              :  1;\
            UNSG32 RSVDx7C_b4                                  : 28;\
          }
    union { UNSG32 u32CPU_REG_ETM;
            struct w32CPU_REG_ETM;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PMU_PMUEVENT0(r32)                  _BFGET_(r32,29, 0)
    #define   SET32CPU_REG_PMU_PMUEVENT0(r32,v)                _BFSET_(r32,29, 0,v)

    #define     w32CPU_REG_PMU                                 {\
            UNSG32 uPMU_PMUEVENT0                              : 30;\
            UNSG32 RSVDx80_b30                                 :  2;\
          }
    union { UNSG32 u32CPU_REG_PMU;
            struct w32CPU_REG_PMU;
          };
    #define   GET32CPU_REG_PMU_PMUEVENT1(r32)                  _BFGET_(r32,29, 0)
    #define   SET32CPU_REG_PMU_PMUEVENT1(r32,v)                _BFSET_(r32,29, 0,v)

    #define     w32CPU_REG_PMU1                                {\
            UNSG32 uPMU_PMUEVENT1                              : 30;\
            UNSG32 RSVDx84_b30                                 :  2;\
          }
    union { UNSG32 u32CPU_REG_PMU1;
            struct w32CPU_REG_PMU1;
          };
    #define   GET32CPU_REG_PMU_PMUEVENT2(r32)                  _BFGET_(r32,29, 0)
    #define   SET32CPU_REG_PMU_PMUEVENT2(r32,v)                _BFSET_(r32,29, 0,v)

    #define     w32CPU_REG_PMU2                                {\
            UNSG32 uPMU_PMUEVENT2                              : 30;\
            UNSG32 RSVDx88_b30                                 :  2;\
          }
    union { UNSG32 u32CPU_REG_PMU2;
            struct w32CPU_REG_PMU2;
          };
    #define   GET32CPU_REG_PMU_PMUEVENT3(r32)                  _BFGET_(r32,29, 0)
    #define   SET32CPU_REG_PMU_PMUEVENT3(r32,v)                _BFSET_(r32,29, 0,v)

    #define     w32CPU_REG_PMU3                                {\
            UNSG32 uPMU_PMUEVENT3                              : 30;\
            UNSG32 RSVDx8C_b30                                 :  2;\
          }
    union { UNSG32 u32CPU_REG_PMU3;
            struct w32CPU_REG_PMU3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWRSW_0_PWRSW_CNTRL(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWRSW_0_PWRSW_CNTRL(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWRSW_0_PWRSW_CNTRL(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWRSW_0_PWRSW_CNTRL(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWRSW_0_PWRSW_CNTRL2(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWRSW_0_PWRSW_CNTRL2(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWRSW_0_PWRSW_CNTRL2(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWRSW_0_PWRSW_CNTRL2(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWRSW_0_PWRSW_ACK(r32)              _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWRSW_0_PWRSW_ACK(r32,v)            _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWRSW_0_PWRSW_ACK(r16)              _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWRSW_0_PWRSW_ACK(r16,v)            _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWRSW_0_PWRSW_ACK2(r32)             _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWRSW_0_PWRSW_ACK2(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWRSW_0_PWRSW_ACK2(r16)             _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWRSW_0_PWRSW_ACK2(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_(r32)      _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_(r16)      _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWRSW_0_nCPU_ISO_MODE_EN_(r16,v)    _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWRSW_0                             {\
            UNSG32 uPWRSW_0_PWRSW_CNTRL                        :  1;\
            UNSG32 uPWRSW_0_PWRSW_CNTRL2                       :  1;\
            UNSG32 uPWRSW_0_PWRSW_ACK                          :  1;\
            UNSG32 uPWRSW_0_PWRSW_ACK2                         :  1;\
            UNSG32 uPWRSW_0_nCPU_ISO_MODE_EN_                  :  1;\
            UNSG32 RSVDx90_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWRSW_0;
            struct w32CPU_REG_PWRSW_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWRSW_1_PWRSW_CNTRL(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWRSW_1_PWRSW_CNTRL(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWRSW_1_PWRSW_CNTRL(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWRSW_1_PWRSW_CNTRL(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWRSW_1_PWRSW_CNTRL2(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWRSW_1_PWRSW_CNTRL2(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWRSW_1_PWRSW_CNTRL2(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWRSW_1_PWRSW_CNTRL2(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWRSW_1_PWRSW_ACK(r32)              _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWRSW_1_PWRSW_ACK(r32,v)            _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWRSW_1_PWRSW_ACK(r16)              _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWRSW_1_PWRSW_ACK(r16,v)            _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWRSW_1_PWRSW_ACK2(r32)             _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWRSW_1_PWRSW_ACK2(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWRSW_1_PWRSW_ACK2(r16)             _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWRSW_1_PWRSW_ACK2(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_(r32)      _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_(r16)      _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWRSW_1_nCPU_ISO_MODE_EN_(r16,v)    _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWRSW_1                             {\
            UNSG32 uPWRSW_1_PWRSW_CNTRL                        :  1;\
            UNSG32 uPWRSW_1_PWRSW_CNTRL2                       :  1;\
            UNSG32 uPWRSW_1_PWRSW_ACK                          :  1;\
            UNSG32 uPWRSW_1_PWRSW_ACK2                         :  1;\
            UNSG32 uPWRSW_1_nCPU_ISO_MODE_EN_                  :  1;\
            UNSG32 RSVDx94_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWRSW_1;
            struct w32CPU_REG_PWRSW_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWRSW_2_PWRSW_CNTRL(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWRSW_2_PWRSW_CNTRL(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWRSW_2_PWRSW_CNTRL(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWRSW_2_PWRSW_CNTRL(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWRSW_2_PWRSW_CNTRL2(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWRSW_2_PWRSW_CNTRL2(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWRSW_2_PWRSW_CNTRL2(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWRSW_2_PWRSW_CNTRL2(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWRSW_2_PWRSW_ACK(r32)              _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWRSW_2_PWRSW_ACK(r32,v)            _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWRSW_2_PWRSW_ACK(r16)              _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWRSW_2_PWRSW_ACK(r16,v)            _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWRSW_2_PWRSW_ACK2(r32)             _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWRSW_2_PWRSW_ACK2(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWRSW_2_PWRSW_ACK2(r16)             _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWRSW_2_PWRSW_ACK2(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_(r32)      _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_(r16)      _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWRSW_2_nCPU_ISO_MODE_EN_(r16,v)    _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWRSW_2                             {\
            UNSG32 uPWRSW_2_PWRSW_CNTRL                        :  1;\
            UNSG32 uPWRSW_2_PWRSW_CNTRL2                       :  1;\
            UNSG32 uPWRSW_2_PWRSW_ACK                          :  1;\
            UNSG32 uPWRSW_2_PWRSW_ACK2                         :  1;\
            UNSG32 uPWRSW_2_nCPU_ISO_MODE_EN_                  :  1;\
            UNSG32 RSVDx98_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWRSW_2;
            struct w32CPU_REG_PWRSW_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_PWRSW_3_PWRSW_CNTRL(r32)            _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_PWRSW_3_PWRSW_CNTRL(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_PWRSW_3_PWRSW_CNTRL(r16)            _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_PWRSW_3_PWRSW_CNTRL(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_PWRSW_3_PWRSW_CNTRL2(r32)           _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_PWRSW_3_PWRSW_CNTRL2(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_PWRSW_3_PWRSW_CNTRL2(r16)           _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_PWRSW_3_PWRSW_CNTRL2(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_PWRSW_3_PWRSW_ACK(r32)              _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_PWRSW_3_PWRSW_ACK(r32,v)            _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_PWRSW_3_PWRSW_ACK(r16)              _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_PWRSW_3_PWRSW_ACK(r16,v)            _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_PWRSW_3_PWRSW_ACK2(r32)             _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_PWRSW_3_PWRSW_ACK2(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_PWRSW_3_PWRSW_ACK2(r16)             _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_PWRSW_3_PWRSW_ACK2(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_(r32)      _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_(r16)      _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_PWRSW_3_nCPU_ISO_MODE_EN_(r16,v)    _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_PWRSW_3                             {\
            UNSG32 uPWRSW_3_PWRSW_CNTRL                        :  1;\
            UNSG32 uPWRSW_3_PWRSW_CNTRL2                       :  1;\
            UNSG32 uPWRSW_3_PWRSW_ACK                          :  1;\
            UNSG32 uPWRSW_3_PWRSW_ACK2                         :  1;\
            UNSG32 uPWRSW_3_nCPU_ISO_MODE_EN_                  :  1;\
            UNSG32 RSVDx9C_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_PWRSW_3;
            struct w32CPU_REG_PWRSW_3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_CSSY_CTRL_dbgen(r32)                _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_CSSY_CTRL_dbgen(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_CSSY_CTRL_dbgen(r16)                _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_CSSY_CTRL_dbgen(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32CPU_REG_CSSY_CTRL_spiden(r32)               _BFGET_(r32, 1, 1)
    #define   SET32CPU_REG_CSSY_CTRL_spiden(r32,v)             _BFSET_(r32, 1, 1,v)
    #define   GET16CPU_REG_CSSY_CTRL_spiden(r16)               _BFGET_(r16, 1, 1)
    #define   SET16CPU_REG_CSSY_CTRL_spiden(r16,v)             _BFSET_(r16, 1, 1,v)

    #define   GET32CPU_REG_CSSY_CTRL_niden(r32)                _BFGET_(r32, 2, 2)
    #define   SET32CPU_REG_CSSY_CTRL_niden(r32,v)              _BFSET_(r32, 2, 2,v)
    #define   GET16CPU_REG_CSSY_CTRL_niden(r16)                _BFGET_(r16, 2, 2)
    #define   SET16CPU_REG_CSSY_CTRL_niden(r16,v)              _BFSET_(r16, 2, 2,v)

    #define   GET32CPU_REG_CSSY_CTRL_spniden(r32)              _BFGET_(r32, 3, 3)
    #define   SET32CPU_REG_CSSY_CTRL_spniden(r32,v)            _BFSET_(r32, 3, 3,v)
    #define   GET16CPU_REG_CSSY_CTRL_spniden(r16)              _BFGET_(r16, 3, 3)
    #define   SET16CPU_REG_CSSY_CTRL_spniden(r16,v)            _BFSET_(r16, 3, 3,v)

    #define   GET32CPU_REG_CSSY_CTRL_DEVICEEN(r32)             _BFGET_(r32, 4, 4)
    #define   SET32CPU_REG_CSSY_CTRL_DEVICEEN(r32,v)           _BFSET_(r32, 4, 4,v)
    #define   GET16CPU_REG_CSSY_CTRL_DEVICEEN(r16)             _BFGET_(r16, 4, 4)
    #define   SET16CPU_REG_CSSY_CTRL_DEVICEEN(r16,v)           _BFSET_(r16, 4, 4,v)

    #define     w32CPU_REG_CSSY_CTRL                           {\
            UNSG32 uCSSY_CTRL_dbgen                            :  1;\
            UNSG32 uCSSY_CTRL_spiden                           :  1;\
            UNSG32 uCSSY_CTRL_niden                            :  1;\
            UNSG32 uCSSY_CTRL_spniden                          :  1;\
            UNSG32 uCSSY_CTRL_DEVICEEN                         :  1;\
            UNSG32 RSVDxA0_b5                                  : 27;\
          }
    union { UNSG32 u32CPU_REG_CSSY_CTRL;
            struct w32CPU_REG_CSSY_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu0ExtPmu_En(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu0ExtPmu_En(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu0ExtPmu_En(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu0ExtPmu_En(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu0ExtPmu                          {\
            UNSG32 uCpu0ExtPmu_En                              :  1;\
            UNSG32 RSVDxA4_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu0ExtPmu;
            struct w32CPU_REG_Cpu0ExtPmu;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu1ExtPmu_En(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu1ExtPmu_En(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu1ExtPmu_En(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu1ExtPmu_En(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu1ExtPmu                          {\
            UNSG32 uCpu1ExtPmu_En                              :  1;\
            UNSG32 RSVDxA8_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu1ExtPmu;
            struct w32CPU_REG_Cpu1ExtPmu;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu2ExtPmu_En(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu2ExtPmu_En(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu2ExtPmu_En(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu2ExtPmu_En(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu2ExtPmu                          {\
            UNSG32 uCpu2ExtPmu_En                              :  1;\
            UNSG32 RSVDxAC_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu2ExtPmu;
            struct w32CPU_REG_Cpu2ExtPmu;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu3ExtPmu_En(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu3ExtPmu_En(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu3ExtPmu_En(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu3ExtPmu_En(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu3ExtPmu                          {\
            UNSG32 uCpu3ExtPmu_En                              :  1;\
            UNSG32 RSVDxB0_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu3ExtPmu;
            struct w32CPU_REG_Cpu3ExtPmu;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_CpuPmuPwrSwDly_PwrSwDly(r32)        _BFGET_(r32,25, 0)
    #define   SET32CPU_REG_CpuPmuPwrSwDly_PwrSwDly(r32,v)      _BFSET_(r32,25, 0,v)

    #define     w32CPU_REG_CpuPmuPwrSwDly                      {\
            UNSG32 uCpuPmuPwrSwDly_PwrSwDly                    : 26;\
            UNSG32 RSVDxB4_b26                                 :  6;\
          }
    union { UNSG32 u32CPU_REG_CpuPmuPwrSwDly;
            struct w32CPU_REG_CpuPmuPwrSwDly;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_CpuPmuRstDly_PwrSwDly(r32)          _BFGET_(r32,25, 0)
    #define   SET32CPU_REG_CpuPmuRstDly_PwrSwDly(r32,v)        _BFSET_(r32,25, 0,v)

    #define     w32CPU_REG_CpuPmuRstDly                        {\
            UNSG32 uCpuPmuRstDly_PwrSwDly                      : 26;\
            UNSG32 RSVDxB8_b26                                 :  6;\
          }
    union { UNSG32 u32CPU_REG_CpuPmuRstDly;
            struct w32CPU_REG_CpuPmuRstDly;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu0WarmRst_En(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu0WarmRst_En(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu0WarmRst_En(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu0WarmRst_En(r16,v)               _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu0WarmRst                         {\
            UNSG32 uCpu0WarmRst_En                             :  1;\
            UNSG32 RSVDxBC_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu0WarmRst;
            struct w32CPU_REG_Cpu0WarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu1WarmRst_En(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu1WarmRst_En(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu1WarmRst_En(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu1WarmRst_En(r16,v)               _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu1WarmRst                         {\
            UNSG32 uCpu1WarmRst_En                             :  1;\
            UNSG32 RSVDxC0_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu1WarmRst;
            struct w32CPU_REG_Cpu1WarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu2WarmRst_En(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu2WarmRst_En(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu2WarmRst_En(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu2WarmRst_En(r16,v)               _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu2WarmRst                         {\
            UNSG32 uCpu2WarmRst_En                             :  1;\
            UNSG32 RSVDxC4_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu2WarmRst;
            struct w32CPU_REG_Cpu2WarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu3WarmRst_En(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu3WarmRst_En(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu3WarmRst_En(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu3WarmRst_En(r16,v)               _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu3WarmRst                         {\
            UNSG32 uCpu3WarmRst_En                             :  1;\
            UNSG32 RSVDxC8_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu3WarmRst;
            struct w32CPU_REG_Cpu3WarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu0DbgWarmRst_En(r32)              _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu0DbgWarmRst_En(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu0DbgWarmRst_En(r16)              _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu0DbgWarmRst_En(r16,v)            _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu0DbgWarmRst                      {\
            UNSG32 uCpu0DbgWarmRst_En                          :  1;\
            UNSG32 RSVDxCC_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu0DbgWarmRst;
            struct w32CPU_REG_Cpu0DbgWarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu1DbgWarmRst_En(r32)              _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu1DbgWarmRst_En(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu1DbgWarmRst_En(r16)              _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu1DbgWarmRst_En(r16,v)            _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu1DbgWarmRst                      {\
            UNSG32 uCpu1DbgWarmRst_En                          :  1;\
            UNSG32 RSVDxD0_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu1DbgWarmRst;
            struct w32CPU_REG_Cpu1DbgWarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu2DbgWarmRst_En(r32)              _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu2DbgWarmRst_En(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu2DbgWarmRst_En(r16)              _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu2DbgWarmRst_En(r16,v)            _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu2DbgWarmRst                      {\
            UNSG32 uCpu2DbgWarmRst_En                          :  1;\
            UNSG32 RSVDxD4_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu2DbgWarmRst;
            struct w32CPU_REG_Cpu2DbgWarmRst;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CPU_REG_Cpu3DbgWarmRst_En(r32)              _BFGET_(r32, 0, 0)
    #define   SET32CPU_REG_Cpu3DbgWarmRst_En(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16CPU_REG_Cpu3DbgWarmRst_En(r16)              _BFGET_(r16, 0, 0)
    #define   SET16CPU_REG_Cpu3DbgWarmRst_En(r16,v)            _BFSET_(r16, 0, 0,v)

    #define     w32CPU_REG_Cpu3DbgWarmRst                      {\
            UNSG32 uCpu3DbgWarmRst_En                          :  1;\
            UNSG32 RSVDxD8_b1                                  : 31;\
          }
    union { UNSG32 u32CPU_REG_Cpu3DbgWarmRst;
            struct w32CPU_REG_Cpu3DbgWarmRst;
          };
    ///////////////////////////////////////////////////////////
    } SIE_CPU_REG;

    typedef union  T32CPU_REG_SRRESET_MP
          { UNSG32 u32;
            struct w32CPU_REG_SRRESET_MP;
                 } T32CPU_REG_SRRESET_MP;
    typedef union  T32CPU_REG_SRRESET_0
          { UNSG32 u32;
            struct w32CPU_REG_SRRESET_0;
                 } T32CPU_REG_SRRESET_0;
    typedef union  T32CPU_REG_SRRESET_1
          { UNSG32 u32;
            struct w32CPU_REG_SRRESET_1;
                 } T32CPU_REG_SRRESET_1;
    typedef union  T32CPU_REG_SRRESET_2
          { UNSG32 u32;
            struct w32CPU_REG_SRRESET_2;
                 } T32CPU_REG_SRRESET_2;
    typedef union  T32CPU_REG_SRRESET_3
          { UNSG32 u32;
            struct w32CPU_REG_SRRESET_3;
                 } T32CPU_REG_SRRESET_3;
    typedef union  T32CPU_REG_RESET_MP
          { UNSG32 u32;
            struct w32CPU_REG_RESET_MP;
                 } T32CPU_REG_RESET_MP;
    typedef union  T32CPU_REG_RESET_0
          { UNSG32 u32;
            struct w32CPU_REG_RESET_0;
                 } T32CPU_REG_RESET_0;
    typedef union  T32CPU_REG_RESET_1
          { UNSG32 u32;
            struct w32CPU_REG_RESET_1;
                 } T32CPU_REG_RESET_1;
    typedef union  T32CPU_REG_RESET_2
          { UNSG32 u32;
            struct w32CPU_REG_RESET_2;
                 } T32CPU_REG_RESET_2;
    typedef union  T32CPU_REG_RESET_3
          { UNSG32 u32;
            struct w32CPU_REG_RESET_3;
                 } T32CPU_REG_RESET_3;
    typedef union  T32CPU_REG_CFG
          { UNSG32 u32;
            struct w32CPU_REG_CFG;
                 } T32CPU_REG_CFG;
    typedef union  T32CPU_REG_CFG1
          { UNSG32 u32;
            struct w32CPU_REG_CFG1;
                 } T32CPU_REG_CFG1;
    typedef union  T32CPU_REG_PWR_NO_RETENTION_MP
          { UNSG32 u32;
            struct w32CPU_REG_PWR_NO_RETENTION_MP;
                 } T32CPU_REG_PWR_NO_RETENTION_MP;
    typedef union  T32CPU_REG_PWR_NO_RETENTION_0
          { UNSG32 u32;
            struct w32CPU_REG_PWR_NO_RETENTION_0;
                 } T32CPU_REG_PWR_NO_RETENTION_0;
    typedef union  T32CPU_REG_PWR_NO_RETENTION_1
          { UNSG32 u32;
            struct w32CPU_REG_PWR_NO_RETENTION_1;
                 } T32CPU_REG_PWR_NO_RETENTION_1;
    typedef union  T32CPU_REG_PWR_NO_RETENTION_2
          { UNSG32 u32;
            struct w32CPU_REG_PWR_NO_RETENTION_2;
                 } T32CPU_REG_PWR_NO_RETENTION_2;
    typedef union  T32CPU_REG_PWR_NO_RETENTION_3
          { UNSG32 u32;
            struct w32CPU_REG_PWR_NO_RETENTION_3;
                 } T32CPU_REG_PWR_NO_RETENTION_3;
    typedef union  T32CPU_REG_PWR_RETENTION
          { UNSG32 u32;
            struct w32CPU_REG_PWR_RETENTION;
                 } T32CPU_REG_PWR_RETENTION;
    typedef union  T32CPU_REG_PWR_RETENTION_0
          { UNSG32 u32;
            struct w32CPU_REG_PWR_RETENTION_0;
                 } T32CPU_REG_PWR_RETENTION_0;
    typedef union  T32CPU_REG_PWR_RETENTION_1
          { UNSG32 u32;
            struct w32CPU_REG_PWR_RETENTION_1;
                 } T32CPU_REG_PWR_RETENTION_1;
    typedef union  T32CPU_REG_PWR_RETENTION_2
          { UNSG32 u32;
            struct w32CPU_REG_PWR_RETENTION_2;
                 } T32CPU_REG_PWR_RETENTION_2;
    typedef union  T32CPU_REG_PWR_RETENTION_3
          { UNSG32 u32;
            struct w32CPU_REG_PWR_RETENTION_3;
                 } T32CPU_REG_PWR_RETENTION_3;
    typedef union  T32CPU_REG_ACE_CHI
          { UNSG32 u32;
            struct w32CPU_REG_ACE_CHI;
                 } T32CPU_REG_ACE_CHI;
    typedef union  T32CPU_REG_DEBUG
          { UNSG32 u32;
            struct w32CPU_REG_DEBUG;
                 } T32CPU_REG_DEBUG;
    typedef union  T32CPU_REG_DEBUG1
          { UNSG32 u32;
            struct w32CPU_REG_DEBUG1;
                 } T32CPU_REG_DEBUG1;
    typedef union  T32CPU_REG_DEBUG2
          { UNSG32 u32;
            struct w32CPU_REG_DEBUG2;
                 } T32CPU_REG_DEBUG2;
    typedef union  T32CPU_REG_DFT
          { UNSG32 u32;
            struct w32CPU_REG_DFT;
                 } T32CPU_REG_DFT;
    typedef union  T32CPU_REG_GIC
          { UNSG32 u32;
            struct w32CPU_REG_GIC;
                 } T32CPU_REG_GIC;
    typedef union  T32CPU_REG_GIC1
          { UNSG32 u32;
            struct w32CPU_REG_GIC1;
                 } T32CPU_REG_GIC1;
    typedef union  T32CPU_REG_GIC2
          { UNSG32 u32;
            struct w32CPU_REG_GIC2;
                 } T32CPU_REG_GIC2;
    typedef union  T32CPU_REG_CNT
          { UNSG32 u32;
            struct w32CPU_REG_CNT;
                 } T32CPU_REG_CNT;
    typedef union  T32CPU_REG_ETM
          { UNSG32 u32;
            struct w32CPU_REG_ETM;
                 } T32CPU_REG_ETM;
    typedef union  T32CPU_REG_PMU
          { UNSG32 u32;
            struct w32CPU_REG_PMU;
                 } T32CPU_REG_PMU;
    typedef union  T32CPU_REG_PMU1
          { UNSG32 u32;
            struct w32CPU_REG_PMU1;
                 } T32CPU_REG_PMU1;
    typedef union  T32CPU_REG_PMU2
          { UNSG32 u32;
            struct w32CPU_REG_PMU2;
                 } T32CPU_REG_PMU2;
    typedef union  T32CPU_REG_PMU3
          { UNSG32 u32;
            struct w32CPU_REG_PMU3;
                 } T32CPU_REG_PMU3;
    typedef union  T32CPU_REG_PWRSW_0
          { UNSG32 u32;
            struct w32CPU_REG_PWRSW_0;
                 } T32CPU_REG_PWRSW_0;
    typedef union  T32CPU_REG_PWRSW_1
          { UNSG32 u32;
            struct w32CPU_REG_PWRSW_1;
                 } T32CPU_REG_PWRSW_1;
    typedef union  T32CPU_REG_PWRSW_2
          { UNSG32 u32;
            struct w32CPU_REG_PWRSW_2;
                 } T32CPU_REG_PWRSW_2;
    typedef union  T32CPU_REG_PWRSW_3
          { UNSG32 u32;
            struct w32CPU_REG_PWRSW_3;
                 } T32CPU_REG_PWRSW_3;
    typedef union  T32CPU_REG_CSSY_CTRL
          { UNSG32 u32;
            struct w32CPU_REG_CSSY_CTRL;
                 } T32CPU_REG_CSSY_CTRL;
    typedef union  T32CPU_REG_Cpu0ExtPmu
          { UNSG32 u32;
            struct w32CPU_REG_Cpu0ExtPmu;
                 } T32CPU_REG_Cpu0ExtPmu;
    typedef union  T32CPU_REG_Cpu1ExtPmu
          { UNSG32 u32;
            struct w32CPU_REG_Cpu1ExtPmu;
                 } T32CPU_REG_Cpu1ExtPmu;
    typedef union  T32CPU_REG_Cpu2ExtPmu
          { UNSG32 u32;
            struct w32CPU_REG_Cpu2ExtPmu;
                 } T32CPU_REG_Cpu2ExtPmu;
    typedef union  T32CPU_REG_Cpu3ExtPmu
          { UNSG32 u32;
            struct w32CPU_REG_Cpu3ExtPmu;
                 } T32CPU_REG_Cpu3ExtPmu;
    typedef union  T32CPU_REG_CpuPmuPwrSwDly
          { UNSG32 u32;
            struct w32CPU_REG_CpuPmuPwrSwDly;
                 } T32CPU_REG_CpuPmuPwrSwDly;
    typedef union  T32CPU_REG_CpuPmuRstDly
          { UNSG32 u32;
            struct w32CPU_REG_CpuPmuRstDly;
                 } T32CPU_REG_CpuPmuRstDly;
    typedef union  T32CPU_REG_Cpu0WarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu0WarmRst;
                 } T32CPU_REG_Cpu0WarmRst;
    typedef union  T32CPU_REG_Cpu1WarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu1WarmRst;
                 } T32CPU_REG_Cpu1WarmRst;
    typedef union  T32CPU_REG_Cpu2WarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu2WarmRst;
                 } T32CPU_REG_Cpu2WarmRst;
    typedef union  T32CPU_REG_Cpu3WarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu3WarmRst;
                 } T32CPU_REG_Cpu3WarmRst;
    typedef union  T32CPU_REG_Cpu0DbgWarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu0DbgWarmRst;
                 } T32CPU_REG_Cpu0DbgWarmRst;
    typedef union  T32CPU_REG_Cpu1DbgWarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu1DbgWarmRst;
                 } T32CPU_REG_Cpu1DbgWarmRst;
    typedef union  T32CPU_REG_Cpu2DbgWarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu2DbgWarmRst;
                 } T32CPU_REG_Cpu2DbgWarmRst;
    typedef union  T32CPU_REG_Cpu3DbgWarmRst
          { UNSG32 u32;
            struct w32CPU_REG_Cpu3DbgWarmRst;
                 } T32CPU_REG_Cpu3DbgWarmRst;
    ///////////////////////////////////////////////////////////

    typedef union  TCPU_REG_SRRESET_MP
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_SRRESET_MP;
                   };
                 } TCPU_REG_SRRESET_MP;
    typedef union  TCPU_REG_SRRESET_0
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_SRRESET_0;
                   };
                 } TCPU_REG_SRRESET_0;
    typedef union  TCPU_REG_SRRESET_1
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_SRRESET_1;
                   };
                 } TCPU_REG_SRRESET_1;
    typedef union  TCPU_REG_SRRESET_2
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_SRRESET_2;
                   };
                 } TCPU_REG_SRRESET_2;
    typedef union  TCPU_REG_SRRESET_3
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_SRRESET_3;
                   };
                 } TCPU_REG_SRRESET_3;
    typedef union  TCPU_REG_RESET_MP
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_RESET_MP;
                   };
                 } TCPU_REG_RESET_MP;
    typedef union  TCPU_REG_RESET_0
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_RESET_0;
                   };
                 } TCPU_REG_RESET_0;
    typedef union  TCPU_REG_RESET_1
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_RESET_1;
                   };
                 } TCPU_REG_RESET_1;
    typedef union  TCPU_REG_RESET_2
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_RESET_2;
                   };
                 } TCPU_REG_RESET_2;
    typedef union  TCPU_REG_RESET_3
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_RESET_3;
                   };
                 } TCPU_REG_RESET_3;
    typedef union  TCPU_REG_CFG
          { UNSG32 u32[2];
            struct {
            struct w32CPU_REG_CFG;
            struct w32CPU_REG_CFG1;
                   };
                 } TCPU_REG_CFG;
    typedef union  TCPU_REG_PWR_NO_RETENTION_MP
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_NO_RETENTION_MP;
                   };
                 } TCPU_REG_PWR_NO_RETENTION_MP;
    typedef union  TCPU_REG_PWR_NO_RETENTION_0
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_NO_RETENTION_0;
                   };
                 } TCPU_REG_PWR_NO_RETENTION_0;
    typedef union  TCPU_REG_PWR_NO_RETENTION_1
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_NO_RETENTION_1;
                   };
                 } TCPU_REG_PWR_NO_RETENTION_1;
    typedef union  TCPU_REG_PWR_NO_RETENTION_2
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_NO_RETENTION_2;
                   };
                 } TCPU_REG_PWR_NO_RETENTION_2;
    typedef union  TCPU_REG_PWR_NO_RETENTION_3
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_NO_RETENTION_3;
                   };
                 } TCPU_REG_PWR_NO_RETENTION_3;
    typedef union  TCPU_REG_PWR_RETENTION
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_RETENTION;
                   };
                 } TCPU_REG_PWR_RETENTION;
    typedef union  TCPU_REG_PWR_RETENTION_0
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_RETENTION_0;
                   };
                 } TCPU_REG_PWR_RETENTION_0;
    typedef union  TCPU_REG_PWR_RETENTION_1
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_RETENTION_1;
                   };
                 } TCPU_REG_PWR_RETENTION_1;
    typedef union  TCPU_REG_PWR_RETENTION_2
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_RETENTION_2;
                   };
                 } TCPU_REG_PWR_RETENTION_2;
    typedef union  TCPU_REG_PWR_RETENTION_3
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWR_RETENTION_3;
                   };
                 } TCPU_REG_PWR_RETENTION_3;
    typedef union  TCPU_REG_ACE_CHI
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_ACE_CHI;
                   };
                 } TCPU_REG_ACE_CHI;
    typedef union  TCPU_REG_DEBUG
          { UNSG32 u32[3];
            struct {
            struct w32CPU_REG_DEBUG;
            struct w32CPU_REG_DEBUG1;
            struct w32CPU_REG_DEBUG2;
                   };
                 } TCPU_REG_DEBUG;
    typedef union  TCPU_REG_DFT
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_DFT;
                   };
                 } TCPU_REG_DFT;
    typedef union  TCPU_REG_GIC
          { UNSG32 u32[3];
            struct {
            struct w32CPU_REG_GIC;
            struct w32CPU_REG_GIC1;
            struct w32CPU_REG_GIC2;
                   };
                 } TCPU_REG_GIC;
    typedef union  TCPU_REG_CNT
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_CNT;
                   };
                 } TCPU_REG_CNT;
    typedef union  TCPU_REG_ETM
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_ETM;
                   };
                 } TCPU_REG_ETM;
    typedef union  TCPU_REG_PMU
          { UNSG32 u32[4];
            struct {
            struct w32CPU_REG_PMU;
            struct w32CPU_REG_PMU1;
            struct w32CPU_REG_PMU2;
            struct w32CPU_REG_PMU3;
                   };
                 } TCPU_REG_PMU;
    typedef union  TCPU_REG_PWRSW_0
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWRSW_0;
                   };
                 } TCPU_REG_PWRSW_0;
    typedef union  TCPU_REG_PWRSW_1
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWRSW_1;
                   };
                 } TCPU_REG_PWRSW_1;
    typedef union  TCPU_REG_PWRSW_2
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWRSW_2;
                   };
                 } TCPU_REG_PWRSW_2;
    typedef union  TCPU_REG_PWRSW_3
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_PWRSW_3;
                   };
                 } TCPU_REG_PWRSW_3;
    typedef union  TCPU_REG_CSSY_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_CSSY_CTRL;
                   };
                 } TCPU_REG_CSSY_CTRL;
    typedef union  TCPU_REG_Cpu0ExtPmu
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu0ExtPmu;
                   };
                 } TCPU_REG_Cpu0ExtPmu;
    typedef union  TCPU_REG_Cpu1ExtPmu
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu1ExtPmu;
                   };
                 } TCPU_REG_Cpu1ExtPmu;
    typedef union  TCPU_REG_Cpu2ExtPmu
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu2ExtPmu;
                   };
                 } TCPU_REG_Cpu2ExtPmu;
    typedef union  TCPU_REG_Cpu3ExtPmu
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu3ExtPmu;
                   };
                 } TCPU_REG_Cpu3ExtPmu;
    typedef union  TCPU_REG_CpuPmuPwrSwDly
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_CpuPmuPwrSwDly;
                   };
                 } TCPU_REG_CpuPmuPwrSwDly;
    typedef union  TCPU_REG_CpuPmuRstDly
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_CpuPmuRstDly;
                   };
                 } TCPU_REG_CpuPmuRstDly;
    typedef union  TCPU_REG_Cpu0WarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu0WarmRst;
                   };
                 } TCPU_REG_Cpu0WarmRst;
    typedef union  TCPU_REG_Cpu1WarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu1WarmRst;
                   };
                 } TCPU_REG_Cpu1WarmRst;
    typedef union  TCPU_REG_Cpu2WarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu2WarmRst;
                   };
                 } TCPU_REG_Cpu2WarmRst;
    typedef union  TCPU_REG_Cpu3WarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu3WarmRst;
                   };
                 } TCPU_REG_Cpu3WarmRst;
    typedef union  TCPU_REG_Cpu0DbgWarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu0DbgWarmRst;
                   };
                 } TCPU_REG_Cpu0DbgWarmRst;
    typedef union  TCPU_REG_Cpu1DbgWarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu1DbgWarmRst;
                   };
                 } TCPU_REG_Cpu1DbgWarmRst;
    typedef union  TCPU_REG_Cpu2DbgWarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu2DbgWarmRst;
                   };
                 } TCPU_REG_Cpu2DbgWarmRst;
    typedef union  TCPU_REG_Cpu3DbgWarmRst
          { UNSG32 u32[1];
            struct {
            struct w32CPU_REG_Cpu3DbgWarmRst;
                   };
                 } TCPU_REG_Cpu3DbgWarmRst;

    ///////////////////////////////////////////////////////////
     SIGN32 CPU_REG_drvrd(SIE_CPU_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CPU_REG_drvwr(SIE_CPU_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CPU_REG_reset(SIE_CPU_REG *p);
     SIGN32 CPU_REG_cmp  (SIE_CPU_REG *p, SIE_CPU_REG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CPU_REG_check(p,pie,pfx,hLOG) CPU_REG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CPU_REG_print(p,    pfx,hLOG) CPU_REG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CPU_REG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE TIMER_REG                                (4,4)
///     ###
///     * CPU and PTM Timer control
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CPUTimerEn           (P)
///               %unsigned 1  CPUTimerEn                0x0
///                                    ###
///                                    * Cpu timer enable
///                                    * 1'b1: enable counter 1'b0: disable counter
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00004 CPUTimerLoad         (P)
///               %unsigned 1  CPUTimerLoad              0x0
///                                    ###
///                                    * Load CPU Timer Value from register
///                                    * This load is valid when CPUTimerEn is 1'b0
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00008 CPUTimerLoadValueHi  (P)
///               %unsigned 32 CPUTimerLoadValueHi       0x0
///                                    ###
///                                    * Cpu timer load value(High 32 bits)
///                                    ###
///     @ 0x0000C CPUTimerLoadValueLo  (P)
///               %unsigned 32 CPUTimerLoadValueLo       0x0
///                                    ###
///                                    * Cpu timer load value(Low 32 bits)
///                                    ###
///     @ 0x00010 PTMTimerEn           (P)
///               %unsigned 1  PTMTimerEn                0x0
///                                    ###
///                                    * PTM timer enable
///                                    * 1'b1: enable counter 1'b0: disable counter
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00014 PTMTimerLoad         (P)
///               %unsigned 1  PTMTimerLoad              0x0
///                                    ###
///                                    * Load PTMTimer Value from register
///                                    * This load is valid when CPUTimerEn is 1'b0
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00018 PTMTimerLoadValueHi  (P)
///               %unsigned 32 PTMTimerLoadValueHi       0x0
///                                    ###
///                                    * PTM timer load value(High 32 bits)
///                                    ###
///     @ 0x0001C PTMTimerLoadValueLo  (P)
///               %unsigned 32 PTMTimerLoadValueLo       0x0
///                                    ###
///                                    * PTM timer load value(Low 32 bits)
///                                    ###
///     @ 0x00020 CPUTimerValueHi      (R-)
///               %unsigned 32 CPUTimerValueHi           
///                                    ###
///                                    * Cpu timer value(High 32 bits)
///                                    ###
///     @ 0x00024 CPUTimerValueLo      (R-)
///               %unsigned 32 CPUTimerValueLo           
///                                    ###
///                                    * Cpu timer value(Low 32 bits)
///                                    ###
///     @ 0x00028 PTMTimerValueHi      (R-)
///               %unsigned 32 PTMTimerValueHi           
///                                    ###
///                                    * PTM timer value(High 32 bits)
///                                    ###
///     @ 0x0002C PTMTimerValueLo      (R-)
///               %unsigned 32 PTMTimerValueLo           
///                                    ###
///                                    * PTM timer value(Low 32 bits)
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      48B, bits:     260b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TIMER_REG
#define h_TIMER_REG (){}

    #define     RA_TIMER_REG_CPUTimerEn                        0x0000

    #define     BA_TIMER_REG_CPUTimerEn_CPUTimerEn             0x0000
    #define     B16TIMER_REG_CPUTimerEn_CPUTimerEn             0x0000
    #define   LSb32TIMER_REG_CPUTimerEn_CPUTimerEn                0
    #define   LSb16TIMER_REG_CPUTimerEn_CPUTimerEn                0
    #define       bTIMER_REG_CPUTimerEn_CPUTimerEn             1
    #define   MSK32TIMER_REG_CPUTimerEn_CPUTimerEn                0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_CPUTimerLoad                      0x0004

    #define     BA_TIMER_REG_CPUTimerLoad_CPUTimerLoad         0x0004
    #define     B16TIMER_REG_CPUTimerLoad_CPUTimerLoad         0x0004
    #define   LSb32TIMER_REG_CPUTimerLoad_CPUTimerLoad            0
    #define   LSb16TIMER_REG_CPUTimerLoad_CPUTimerLoad            0
    #define       bTIMER_REG_CPUTimerLoad_CPUTimerLoad         1
    #define   MSK32TIMER_REG_CPUTimerLoad_CPUTimerLoad            0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_CPUTimerLoadValueHi               0x0008

    #define     BA_TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi 0x0008
    #define     B16TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi 0x0008
    #define   LSb32TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi    0
    #define   LSb16TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi    0
    #define       bTIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi 32
    #define   MSK32TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi    0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_CPUTimerLoadValueLo               0x000C

    #define     BA_TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo 0x000C
    #define     B16TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo 0x000C
    #define   LSb32TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo    0
    #define   LSb16TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo    0
    #define       bTIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo 32
    #define   MSK32TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo    0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_PTMTimerEn                        0x0010

    #define     BA_TIMER_REG_PTMTimerEn_PTMTimerEn             0x0010
    #define     B16TIMER_REG_PTMTimerEn_PTMTimerEn             0x0010
    #define   LSb32TIMER_REG_PTMTimerEn_PTMTimerEn                0
    #define   LSb16TIMER_REG_PTMTimerEn_PTMTimerEn                0
    #define       bTIMER_REG_PTMTimerEn_PTMTimerEn             1
    #define   MSK32TIMER_REG_PTMTimerEn_PTMTimerEn                0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_PTMTimerLoad                      0x0014

    #define     BA_TIMER_REG_PTMTimerLoad_PTMTimerLoad         0x0014
    #define     B16TIMER_REG_PTMTimerLoad_PTMTimerLoad         0x0014
    #define   LSb32TIMER_REG_PTMTimerLoad_PTMTimerLoad            0
    #define   LSb16TIMER_REG_PTMTimerLoad_PTMTimerLoad            0
    #define       bTIMER_REG_PTMTimerLoad_PTMTimerLoad         1
    #define   MSK32TIMER_REG_PTMTimerLoad_PTMTimerLoad            0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_PTMTimerLoadValueHi               0x0018

    #define     BA_TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi 0x0018
    #define     B16TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi 0x0018
    #define   LSb32TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi    0
    #define   LSb16TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi    0
    #define       bTIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi 32
    #define   MSK32TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi    0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_PTMTimerLoadValueLo               0x001C

    #define     BA_TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo 0x001C
    #define     B16TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo 0x001C
    #define   LSb32TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo    0
    #define   LSb16TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo    0
    #define       bTIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo 32
    #define   MSK32TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo    0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_CPUTimerValueHi                   0x0020

    #define     BA_TIMER_REG_CPUTimerValueHi_CPUTimerValueHi   0x0020
    #define     B16TIMER_REG_CPUTimerValueHi_CPUTimerValueHi   0x0020
    #define   LSb32TIMER_REG_CPUTimerValueHi_CPUTimerValueHi      0
    #define   LSb16TIMER_REG_CPUTimerValueHi_CPUTimerValueHi      0
    #define       bTIMER_REG_CPUTimerValueHi_CPUTimerValueHi   32
    #define   MSK32TIMER_REG_CPUTimerValueHi_CPUTimerValueHi      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_CPUTimerValueLo                   0x0024

    #define     BA_TIMER_REG_CPUTimerValueLo_CPUTimerValueLo   0x0024
    #define     B16TIMER_REG_CPUTimerValueLo_CPUTimerValueLo   0x0024
    #define   LSb32TIMER_REG_CPUTimerValueLo_CPUTimerValueLo      0
    #define   LSb16TIMER_REG_CPUTimerValueLo_CPUTimerValueLo      0
    #define       bTIMER_REG_CPUTimerValueLo_CPUTimerValueLo   32
    #define   MSK32TIMER_REG_CPUTimerValueLo_CPUTimerValueLo      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_PTMTimerValueHi                   0x0028

    #define     BA_TIMER_REG_PTMTimerValueHi_PTMTimerValueHi   0x0028
    #define     B16TIMER_REG_PTMTimerValueHi_PTMTimerValueHi   0x0028
    #define   LSb32TIMER_REG_PTMTimerValueHi_PTMTimerValueHi      0
    #define   LSb16TIMER_REG_PTMTimerValueHi_PTMTimerValueHi      0
    #define       bTIMER_REG_PTMTimerValueHi_PTMTimerValueHi   32
    #define   MSK32TIMER_REG_PTMTimerValueHi_PTMTimerValueHi      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_TIMER_REG_PTMTimerValueLo                   0x002C

    #define     BA_TIMER_REG_PTMTimerValueLo_PTMTimerValueLo   0x002C
    #define     B16TIMER_REG_PTMTimerValueLo_PTMTimerValueLo   0x002C
    #define   LSb32TIMER_REG_PTMTimerValueLo_PTMTimerValueLo      0
    #define   LSb16TIMER_REG_PTMTimerValueLo_PTMTimerValueLo      0
    #define       bTIMER_REG_PTMTimerValueLo_PTMTimerValueLo   32
    #define   MSK32TIMER_REG_PTMTimerValueLo_PTMTimerValueLo      0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TIMER_REG {
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_CPUTimerEn_CPUTimerEn(r32)        _BFGET_(r32, 0, 0)
    #define   SET32TIMER_REG_CPUTimerEn_CPUTimerEn(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16TIMER_REG_CPUTimerEn_CPUTimerEn(r16)        _BFGET_(r16, 0, 0)
    #define   SET16TIMER_REG_CPUTimerEn_CPUTimerEn(r16,v)      _BFSET_(r16, 0, 0,v)

    #define     w32TIMER_REG_CPUTimerEn                        {\
            UNSG32 uCPUTimerEn_CPUTimerEn                      :  1;\
            UNSG32 RSVDx0_b1                                   : 31;\
          }
    union { UNSG32 u32TIMER_REG_CPUTimerEn;
            struct w32TIMER_REG_CPUTimerEn;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_CPUTimerLoad_CPUTimerLoad(r32)    _BFGET_(r32, 0, 0)
    #define   SET32TIMER_REG_CPUTimerLoad_CPUTimerLoad(r32,v)  _BFSET_(r32, 0, 0,v)
    #define   GET16TIMER_REG_CPUTimerLoad_CPUTimerLoad(r16)    _BFGET_(r16, 0, 0)
    #define   SET16TIMER_REG_CPUTimerLoad_CPUTimerLoad(r16,v)  _BFSET_(r16, 0, 0,v)

    #define     w32TIMER_REG_CPUTimerLoad                      {\
            UNSG32 uCPUTimerLoad_CPUTimerLoad                  :  1;\
            UNSG32 RSVDx4_b1                                   : 31;\
          }
    union { UNSG32 u32TIMER_REG_CPUTimerLoad;
            struct w32TIMER_REG_CPUTimerLoad;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_CPUTimerLoadValueHi_CPUTimerLoadValueHi(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_CPUTimerLoadValueHi               {\
            UNSG32 uCPUTimerLoadValueHi_CPUTimerLoadValueHi    : 32;\
          }
    union { UNSG32 u32TIMER_REG_CPUTimerLoadValueHi;
            struct w32TIMER_REG_CPUTimerLoadValueHi;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_CPUTimerLoadValueLo_CPUTimerLoadValueLo(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_CPUTimerLoadValueLo               {\
            UNSG32 uCPUTimerLoadValueLo_CPUTimerLoadValueLo    : 32;\
          }
    union { UNSG32 u32TIMER_REG_CPUTimerLoadValueLo;
            struct w32TIMER_REG_CPUTimerLoadValueLo;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_PTMTimerEn_PTMTimerEn(r32)        _BFGET_(r32, 0, 0)
    #define   SET32TIMER_REG_PTMTimerEn_PTMTimerEn(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16TIMER_REG_PTMTimerEn_PTMTimerEn(r16)        _BFGET_(r16, 0, 0)
    #define   SET16TIMER_REG_PTMTimerEn_PTMTimerEn(r16,v)      _BFSET_(r16, 0, 0,v)

    #define     w32TIMER_REG_PTMTimerEn                        {\
            UNSG32 uPTMTimerEn_PTMTimerEn                      :  1;\
            UNSG32 RSVDx10_b1                                  : 31;\
          }
    union { UNSG32 u32TIMER_REG_PTMTimerEn;
            struct w32TIMER_REG_PTMTimerEn;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_PTMTimerLoad_PTMTimerLoad(r32)    _BFGET_(r32, 0, 0)
    #define   SET32TIMER_REG_PTMTimerLoad_PTMTimerLoad(r32,v)  _BFSET_(r32, 0, 0,v)
    #define   GET16TIMER_REG_PTMTimerLoad_PTMTimerLoad(r16)    _BFGET_(r16, 0, 0)
    #define   SET16TIMER_REG_PTMTimerLoad_PTMTimerLoad(r16,v)  _BFSET_(r16, 0, 0,v)

    #define     w32TIMER_REG_PTMTimerLoad                      {\
            UNSG32 uPTMTimerLoad_PTMTimerLoad                  :  1;\
            UNSG32 RSVDx14_b1                                  : 31;\
          }
    union { UNSG32 u32TIMER_REG_PTMTimerLoad;
            struct w32TIMER_REG_PTMTimerLoad;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_PTMTimerLoadValueHi_PTMTimerLoadValueHi(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_PTMTimerLoadValueHi               {\
            UNSG32 uPTMTimerLoadValueHi_PTMTimerLoadValueHi    : 32;\
          }
    union { UNSG32 u32TIMER_REG_PTMTimerLoadValueHi;
            struct w32TIMER_REG_PTMTimerLoadValueHi;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_PTMTimerLoadValueLo_PTMTimerLoadValueLo(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_PTMTimerLoadValueLo               {\
            UNSG32 uPTMTimerLoadValueLo_PTMTimerLoadValueLo    : 32;\
          }
    union { UNSG32 u32TIMER_REG_PTMTimerLoadValueLo;
            struct w32TIMER_REG_PTMTimerLoadValueLo;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_CPUTimerValueHi_CPUTimerValueHi(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_CPUTimerValueHi_CPUTimerValueHi(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_CPUTimerValueHi                   {\
            UNSG32 uCPUTimerValueHi_CPUTimerValueHi            : 32;\
          }
    union { UNSG32 u32TIMER_REG_CPUTimerValueHi;
            struct w32TIMER_REG_CPUTimerValueHi;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_CPUTimerValueLo_CPUTimerValueLo(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_CPUTimerValueLo_CPUTimerValueLo(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_CPUTimerValueLo                   {\
            UNSG32 uCPUTimerValueLo_CPUTimerValueLo            : 32;\
          }
    union { UNSG32 u32TIMER_REG_CPUTimerValueLo;
            struct w32TIMER_REG_CPUTimerValueLo;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_PTMTimerValueHi_PTMTimerValueHi(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_PTMTimerValueHi_PTMTimerValueHi(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_PTMTimerValueHi                   {\
            UNSG32 uPTMTimerValueHi_PTMTimerValueHi            : 32;\
          }
    union { UNSG32 u32TIMER_REG_PTMTimerValueHi;
            struct w32TIMER_REG_PTMTimerValueHi;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TIMER_REG_PTMTimerValueLo_PTMTimerValueLo(r32) _BFGET_(r32,31, 0)
    #define   SET32TIMER_REG_PTMTimerValueLo_PTMTimerValueLo(r32,v) _BFSET_(r32,31, 0,v)

    #define     w32TIMER_REG_PTMTimerValueLo                   {\
            UNSG32 uPTMTimerValueLo_PTMTimerValueLo            : 32;\
          }
    union { UNSG32 u32TIMER_REG_PTMTimerValueLo;
            struct w32TIMER_REG_PTMTimerValueLo;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TIMER_REG;

    typedef union  T32TIMER_REG_CPUTimerEn
          { UNSG32 u32;
            struct w32TIMER_REG_CPUTimerEn;
                 } T32TIMER_REG_CPUTimerEn;
    typedef union  T32TIMER_REG_CPUTimerLoad
          { UNSG32 u32;
            struct w32TIMER_REG_CPUTimerLoad;
                 } T32TIMER_REG_CPUTimerLoad;
    typedef union  T32TIMER_REG_CPUTimerLoadValueHi
          { UNSG32 u32;
            struct w32TIMER_REG_CPUTimerLoadValueHi;
                 } T32TIMER_REG_CPUTimerLoadValueHi;
    typedef union  T32TIMER_REG_CPUTimerLoadValueLo
          { UNSG32 u32;
            struct w32TIMER_REG_CPUTimerLoadValueLo;
                 } T32TIMER_REG_CPUTimerLoadValueLo;
    typedef union  T32TIMER_REG_PTMTimerEn
          { UNSG32 u32;
            struct w32TIMER_REG_PTMTimerEn;
                 } T32TIMER_REG_PTMTimerEn;
    typedef union  T32TIMER_REG_PTMTimerLoad
          { UNSG32 u32;
            struct w32TIMER_REG_PTMTimerLoad;
                 } T32TIMER_REG_PTMTimerLoad;
    typedef union  T32TIMER_REG_PTMTimerLoadValueHi
          { UNSG32 u32;
            struct w32TIMER_REG_PTMTimerLoadValueHi;
                 } T32TIMER_REG_PTMTimerLoadValueHi;
    typedef union  T32TIMER_REG_PTMTimerLoadValueLo
          { UNSG32 u32;
            struct w32TIMER_REG_PTMTimerLoadValueLo;
                 } T32TIMER_REG_PTMTimerLoadValueLo;
    typedef union  T32TIMER_REG_CPUTimerValueHi
          { UNSG32 u32;
            struct w32TIMER_REG_CPUTimerValueHi;
                 } T32TIMER_REG_CPUTimerValueHi;
    typedef union  T32TIMER_REG_CPUTimerValueLo
          { UNSG32 u32;
            struct w32TIMER_REG_CPUTimerValueLo;
                 } T32TIMER_REG_CPUTimerValueLo;
    typedef union  T32TIMER_REG_PTMTimerValueHi
          { UNSG32 u32;
            struct w32TIMER_REG_PTMTimerValueHi;
                 } T32TIMER_REG_PTMTimerValueHi;
    typedef union  T32TIMER_REG_PTMTimerValueLo
          { UNSG32 u32;
            struct w32TIMER_REG_PTMTimerValueLo;
                 } T32TIMER_REG_PTMTimerValueLo;
    ///////////////////////////////////////////////////////////

    typedef union  TTIMER_REG_CPUTimerEn
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_CPUTimerEn;
                   };
                 } TTIMER_REG_CPUTimerEn;
    typedef union  TTIMER_REG_CPUTimerLoad
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_CPUTimerLoad;
                   };
                 } TTIMER_REG_CPUTimerLoad;
    typedef union  TTIMER_REG_CPUTimerLoadValueHi
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_CPUTimerLoadValueHi;
                   };
                 } TTIMER_REG_CPUTimerLoadValueHi;
    typedef union  TTIMER_REG_CPUTimerLoadValueLo
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_CPUTimerLoadValueLo;
                   };
                 } TTIMER_REG_CPUTimerLoadValueLo;
    typedef union  TTIMER_REG_PTMTimerEn
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_PTMTimerEn;
                   };
                 } TTIMER_REG_PTMTimerEn;
    typedef union  TTIMER_REG_PTMTimerLoad
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_PTMTimerLoad;
                   };
                 } TTIMER_REG_PTMTimerLoad;
    typedef union  TTIMER_REG_PTMTimerLoadValueHi
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_PTMTimerLoadValueHi;
                   };
                 } TTIMER_REG_PTMTimerLoadValueHi;
    typedef union  TTIMER_REG_PTMTimerLoadValueLo
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_PTMTimerLoadValueLo;
                   };
                 } TTIMER_REG_PTMTimerLoadValueLo;
    typedef union  TTIMER_REG_CPUTimerValueHi
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_CPUTimerValueHi;
                   };
                 } TTIMER_REG_CPUTimerValueHi;
    typedef union  TTIMER_REG_CPUTimerValueLo
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_CPUTimerValueLo;
                   };
                 } TTIMER_REG_CPUTimerValueLo;
    typedef union  TTIMER_REG_PTMTimerValueHi
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_PTMTimerValueHi;
                   };
                 } TTIMER_REG_PTMTimerValueHi;
    typedef union  TTIMER_REG_PTMTimerValueLo
          { UNSG32 u32[1];
            struct {
            struct w32TIMER_REG_PTMTimerValueLo;
                   };
                 } TTIMER_REG_PTMTimerValueLo;

    ///////////////////////////////////////////////////////////
     SIGN32 TIMER_REG_drvrd(SIE_TIMER_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TIMER_REG_drvwr(SIE_TIMER_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TIMER_REG_reset(SIE_TIMER_REG *p);
     SIGN32 TIMER_REG_cmp  (SIE_TIMER_REG *p, SIE_TIMER_REG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TIMER_REG_check(p,pie,pfx,hLOG) TIMER_REG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TIMER_REG_print(p,    pfx,hLOG) TIMER_REG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TIMER_REG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE CFG64_REG                                (4,4)
///     ###
///     * CPU 8-byte aligned registers
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CFG64_0              (RW-)
///               %unsigned 2  RESERVED                  0x0
///               %unsigned 30 RVBARADDR0_31_2           0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///     @ 0x00004 CFG64_1              (RW-)
///               %unsigned 8  RVBARADDR0_39_32          0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00008 CFG64_2              (RW-)
///               %unsigned 2  RESERVED                  0x0
///               %unsigned 30 RVBARADDR1_31_2           0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///     @ 0x0000C CFG64_3              (RW-)
///               %unsigned 8  RVBARADDR1_39_32          0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00010 CFG64_4              (RW-)
///               %unsigned 2  RESERVED                  0x0
///               %unsigned 30 RVBARADDR2_31_2           0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///     @ 0x00014 CFG64_5              (RW-)
///               %unsigned 8  RVBARADDR2_39_32          0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00018 CFG64_6              (RW-)
///               %unsigned 2  RESERVED                  0x0
///               %unsigned 30 RVBARADDR3_31_2           0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///     @ 0x0001C CFG64_7              (RW-)
///               %unsigned 8  RVBARADDR3_39_32          0x0
///                                    ###
///                                    * Input Reset Vector Base Address for executing in 64-bit state.
///                                    * These pins are sampled only during reset of the processor.
///                                    ###
///               %%        24         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      32B, bits:     160b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CFG64_REG
#define h_CFG64_REG (){}

    #define     RA_CFG64_REG_CFG64_0                           0x0000

    #define     BA_CFG64_REG_CFG64_0_RESERVED                  0x0000
    #define     B16CFG64_REG_CFG64_0_RESERVED                  0x0000
    #define   LSb32CFG64_REG_CFG64_0_RESERVED                     0
    #define   LSb16CFG64_REG_CFG64_0_RESERVED                     0
    #define       bCFG64_REG_CFG64_0_RESERVED                  2
    #define   MSK32CFG64_REG_CFG64_0_RESERVED                     0x00000003

    #define     BA_CFG64_REG_CFG64_0_RVBARADDR0_31_2           0x0000
    #define     B16CFG64_REG_CFG64_0_RVBARADDR0_31_2           0x0000
    #define   LSb32CFG64_REG_CFG64_0_RVBARADDR0_31_2              2
    #define   LSb16CFG64_REG_CFG64_0_RVBARADDR0_31_2              2
    #define       bCFG64_REG_CFG64_0_RVBARADDR0_31_2           30
    #define   MSK32CFG64_REG_CFG64_0_RVBARADDR0_31_2              0xFFFFFFFC
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_1                           0x0004

    #define     BA_CFG64_REG_CFG64_1_RVBARADDR0_39_32          0x0004
    #define     B16CFG64_REG_CFG64_1_RVBARADDR0_39_32          0x0004
    #define   LSb32CFG64_REG_CFG64_1_RVBARADDR0_39_32             0
    #define   LSb16CFG64_REG_CFG64_1_RVBARADDR0_39_32             0
    #define       bCFG64_REG_CFG64_1_RVBARADDR0_39_32          8
    #define   MSK32CFG64_REG_CFG64_1_RVBARADDR0_39_32             0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_2                           0x0008

    #define     BA_CFG64_REG_CFG64_2_RESERVED                  0x0008
    #define     B16CFG64_REG_CFG64_2_RESERVED                  0x0008
    #define   LSb32CFG64_REG_CFG64_2_RESERVED                     0
    #define   LSb16CFG64_REG_CFG64_2_RESERVED                     0
    #define       bCFG64_REG_CFG64_2_RESERVED                  2
    #define   MSK32CFG64_REG_CFG64_2_RESERVED                     0x00000003

    #define     BA_CFG64_REG_CFG64_2_RVBARADDR1_31_2           0x0008
    #define     B16CFG64_REG_CFG64_2_RVBARADDR1_31_2           0x0008
    #define   LSb32CFG64_REG_CFG64_2_RVBARADDR1_31_2              2
    #define   LSb16CFG64_REG_CFG64_2_RVBARADDR1_31_2              2
    #define       bCFG64_REG_CFG64_2_RVBARADDR1_31_2           30
    #define   MSK32CFG64_REG_CFG64_2_RVBARADDR1_31_2              0xFFFFFFFC
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_3                           0x000C

    #define     BA_CFG64_REG_CFG64_3_RVBARADDR1_39_32          0x000C
    #define     B16CFG64_REG_CFG64_3_RVBARADDR1_39_32          0x000C
    #define   LSb32CFG64_REG_CFG64_3_RVBARADDR1_39_32             0
    #define   LSb16CFG64_REG_CFG64_3_RVBARADDR1_39_32             0
    #define       bCFG64_REG_CFG64_3_RVBARADDR1_39_32          8
    #define   MSK32CFG64_REG_CFG64_3_RVBARADDR1_39_32             0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_4                           0x0010

    #define     BA_CFG64_REG_CFG64_4_RESERVED                  0x0010
    #define     B16CFG64_REG_CFG64_4_RESERVED                  0x0010
    #define   LSb32CFG64_REG_CFG64_4_RESERVED                     0
    #define   LSb16CFG64_REG_CFG64_4_RESERVED                     0
    #define       bCFG64_REG_CFG64_4_RESERVED                  2
    #define   MSK32CFG64_REG_CFG64_4_RESERVED                     0x00000003

    #define     BA_CFG64_REG_CFG64_4_RVBARADDR2_31_2           0x0010
    #define     B16CFG64_REG_CFG64_4_RVBARADDR2_31_2           0x0010
    #define   LSb32CFG64_REG_CFG64_4_RVBARADDR2_31_2              2
    #define   LSb16CFG64_REG_CFG64_4_RVBARADDR2_31_2              2
    #define       bCFG64_REG_CFG64_4_RVBARADDR2_31_2           30
    #define   MSK32CFG64_REG_CFG64_4_RVBARADDR2_31_2              0xFFFFFFFC
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_5                           0x0014

    #define     BA_CFG64_REG_CFG64_5_RVBARADDR2_39_32          0x0014
    #define     B16CFG64_REG_CFG64_5_RVBARADDR2_39_32          0x0014
    #define   LSb32CFG64_REG_CFG64_5_RVBARADDR2_39_32             0
    #define   LSb16CFG64_REG_CFG64_5_RVBARADDR2_39_32             0
    #define       bCFG64_REG_CFG64_5_RVBARADDR2_39_32          8
    #define   MSK32CFG64_REG_CFG64_5_RVBARADDR2_39_32             0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_6                           0x0018

    #define     BA_CFG64_REG_CFG64_6_RESERVED                  0x0018
    #define     B16CFG64_REG_CFG64_6_RESERVED                  0x0018
    #define   LSb32CFG64_REG_CFG64_6_RESERVED                     0
    #define   LSb16CFG64_REG_CFG64_6_RESERVED                     0
    #define       bCFG64_REG_CFG64_6_RESERVED                  2
    #define   MSK32CFG64_REG_CFG64_6_RESERVED                     0x00000003

    #define     BA_CFG64_REG_CFG64_6_RVBARADDR3_31_2           0x0018
    #define     B16CFG64_REG_CFG64_6_RVBARADDR3_31_2           0x0018
    #define   LSb32CFG64_REG_CFG64_6_RVBARADDR3_31_2              2
    #define   LSb16CFG64_REG_CFG64_6_RVBARADDR3_31_2              2
    #define       bCFG64_REG_CFG64_6_RVBARADDR3_31_2           30
    #define   MSK32CFG64_REG_CFG64_6_RVBARADDR3_31_2              0xFFFFFFFC
    ///////////////////////////////////////////////////////////
    #define     RA_CFG64_REG_CFG64_7                           0x001C

    #define     BA_CFG64_REG_CFG64_7_RVBARADDR3_39_32          0x001C
    #define     B16CFG64_REG_CFG64_7_RVBARADDR3_39_32          0x001C
    #define   LSb32CFG64_REG_CFG64_7_RVBARADDR3_39_32             0
    #define   LSb16CFG64_REG_CFG64_7_RVBARADDR3_39_32             0
    #define       bCFG64_REG_CFG64_7_RVBARADDR3_39_32          8
    #define   MSK32CFG64_REG_CFG64_7_RVBARADDR3_39_32             0x000000FF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CFG64_REG {
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_0_RESERVED(r32)             _BFGET_(r32, 1, 0)
    #define   SET32CFG64_REG_CFG64_0_RESERVED(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16CFG64_REG_CFG64_0_RESERVED(r16)             _BFGET_(r16, 1, 0)
    #define   SET16CFG64_REG_CFG64_0_RESERVED(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32CFG64_REG_CFG64_0_RVBARADDR0_31_2(r32)      _BFGET_(r32,31, 2)
    #define   SET32CFG64_REG_CFG64_0_RVBARADDR0_31_2(r32,v)    _BFSET_(r32,31, 2,v)

    #define     w32CFG64_REG_CFG64_0                           {\
            UNSG32 uCFG64_0_RESERVED                           :  2;\
            UNSG32 uCFG64_0_RVBARADDR0_31_2                    : 30;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_0;
            struct w32CFG64_REG_CFG64_0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_1_RVBARADDR0_39_32(r32)     _BFGET_(r32, 7, 0)
    #define   SET32CFG64_REG_CFG64_1_RVBARADDR0_39_32(r32,v)   _BFSET_(r32, 7, 0,v)
    #define   GET16CFG64_REG_CFG64_1_RVBARADDR0_39_32(r16)     _BFGET_(r16, 7, 0)
    #define   SET16CFG64_REG_CFG64_1_RVBARADDR0_39_32(r16,v)   _BFSET_(r16, 7, 0,v)

    #define     w32CFG64_REG_CFG64_1                           {\
            UNSG32 uCFG64_1_RVBARADDR0_39_32                   :  8;\
            UNSG32 RSVDx4_b8                                   : 24;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_1;
            struct w32CFG64_REG_CFG64_1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_2_RESERVED(r32)             _BFGET_(r32, 1, 0)
    #define   SET32CFG64_REG_CFG64_2_RESERVED(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16CFG64_REG_CFG64_2_RESERVED(r16)             _BFGET_(r16, 1, 0)
    #define   SET16CFG64_REG_CFG64_2_RESERVED(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32CFG64_REG_CFG64_2_RVBARADDR1_31_2(r32)      _BFGET_(r32,31, 2)
    #define   SET32CFG64_REG_CFG64_2_RVBARADDR1_31_2(r32,v)    _BFSET_(r32,31, 2,v)

    #define     w32CFG64_REG_CFG64_2                           {\
            UNSG32 uCFG64_2_RESERVED                           :  2;\
            UNSG32 uCFG64_2_RVBARADDR1_31_2                    : 30;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_2;
            struct w32CFG64_REG_CFG64_2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_3_RVBARADDR1_39_32(r32)     _BFGET_(r32, 7, 0)
    #define   SET32CFG64_REG_CFG64_3_RVBARADDR1_39_32(r32,v)   _BFSET_(r32, 7, 0,v)
    #define   GET16CFG64_REG_CFG64_3_RVBARADDR1_39_32(r16)     _BFGET_(r16, 7, 0)
    #define   SET16CFG64_REG_CFG64_3_RVBARADDR1_39_32(r16,v)   _BFSET_(r16, 7, 0,v)

    #define     w32CFG64_REG_CFG64_3                           {\
            UNSG32 uCFG64_3_RVBARADDR1_39_32                   :  8;\
            UNSG32 RSVDxC_b8                                   : 24;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_3;
            struct w32CFG64_REG_CFG64_3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_4_RESERVED(r32)             _BFGET_(r32, 1, 0)
    #define   SET32CFG64_REG_CFG64_4_RESERVED(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16CFG64_REG_CFG64_4_RESERVED(r16)             _BFGET_(r16, 1, 0)
    #define   SET16CFG64_REG_CFG64_4_RESERVED(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32CFG64_REG_CFG64_4_RVBARADDR2_31_2(r32)      _BFGET_(r32,31, 2)
    #define   SET32CFG64_REG_CFG64_4_RVBARADDR2_31_2(r32,v)    _BFSET_(r32,31, 2,v)

    #define     w32CFG64_REG_CFG64_4                           {\
            UNSG32 uCFG64_4_RESERVED                           :  2;\
            UNSG32 uCFG64_4_RVBARADDR2_31_2                    : 30;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_4;
            struct w32CFG64_REG_CFG64_4;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_5_RVBARADDR2_39_32(r32)     _BFGET_(r32, 7, 0)
    #define   SET32CFG64_REG_CFG64_5_RVBARADDR2_39_32(r32,v)   _BFSET_(r32, 7, 0,v)
    #define   GET16CFG64_REG_CFG64_5_RVBARADDR2_39_32(r16)     _BFGET_(r16, 7, 0)
    #define   SET16CFG64_REG_CFG64_5_RVBARADDR2_39_32(r16,v)   _BFSET_(r16, 7, 0,v)

    #define     w32CFG64_REG_CFG64_5                           {\
            UNSG32 uCFG64_5_RVBARADDR2_39_32                   :  8;\
            UNSG32 RSVDx14_b8                                  : 24;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_5;
            struct w32CFG64_REG_CFG64_5;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_6_RESERVED(r32)             _BFGET_(r32, 1, 0)
    #define   SET32CFG64_REG_CFG64_6_RESERVED(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16CFG64_REG_CFG64_6_RESERVED(r16)             _BFGET_(r16, 1, 0)
    #define   SET16CFG64_REG_CFG64_6_RESERVED(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32CFG64_REG_CFG64_6_RVBARADDR3_31_2(r32)      _BFGET_(r32,31, 2)
    #define   SET32CFG64_REG_CFG64_6_RVBARADDR3_31_2(r32,v)    _BFSET_(r32,31, 2,v)

    #define     w32CFG64_REG_CFG64_6                           {\
            UNSG32 uCFG64_6_RESERVED                           :  2;\
            UNSG32 uCFG64_6_RVBARADDR3_31_2                    : 30;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_6;
            struct w32CFG64_REG_CFG64_6;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32CFG64_REG_CFG64_7_RVBARADDR3_39_32(r32)     _BFGET_(r32, 7, 0)
    #define   SET32CFG64_REG_CFG64_7_RVBARADDR3_39_32(r32,v)   _BFSET_(r32, 7, 0,v)
    #define   GET16CFG64_REG_CFG64_7_RVBARADDR3_39_32(r16)     _BFGET_(r16, 7, 0)
    #define   SET16CFG64_REG_CFG64_7_RVBARADDR3_39_32(r16,v)   _BFSET_(r16, 7, 0,v)

    #define     w32CFG64_REG_CFG64_7                           {\
            UNSG32 uCFG64_7_RVBARADDR3_39_32                   :  8;\
            UNSG32 RSVDx1C_b8                                  : 24;\
          }
    union { UNSG32 u32CFG64_REG_CFG64_7;
            struct w32CFG64_REG_CFG64_7;
          };
    ///////////////////////////////////////////////////////////
    } SIE_CFG64_REG;

    typedef union  T32CFG64_REG_CFG64_0
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_0;
                 } T32CFG64_REG_CFG64_0;
    typedef union  T32CFG64_REG_CFG64_1
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_1;
                 } T32CFG64_REG_CFG64_1;
    typedef union  T32CFG64_REG_CFG64_2
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_2;
                 } T32CFG64_REG_CFG64_2;
    typedef union  T32CFG64_REG_CFG64_3
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_3;
                 } T32CFG64_REG_CFG64_3;
    typedef union  T32CFG64_REG_CFG64_4
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_4;
                 } T32CFG64_REG_CFG64_4;
    typedef union  T32CFG64_REG_CFG64_5
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_5;
                 } T32CFG64_REG_CFG64_5;
    typedef union  T32CFG64_REG_CFG64_6
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_6;
                 } T32CFG64_REG_CFG64_6;
    typedef union  T32CFG64_REG_CFG64_7
          { UNSG32 u32;
            struct w32CFG64_REG_CFG64_7;
                 } T32CFG64_REG_CFG64_7;
    ///////////////////////////////////////////////////////////

    typedef union  TCFG64_REG_CFG64_0
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_0;
                   };
                 } TCFG64_REG_CFG64_0;
    typedef union  TCFG64_REG_CFG64_1
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_1;
                   };
                 } TCFG64_REG_CFG64_1;
    typedef union  TCFG64_REG_CFG64_2
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_2;
                   };
                 } TCFG64_REG_CFG64_2;
    typedef union  TCFG64_REG_CFG64_3
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_3;
                   };
                 } TCFG64_REG_CFG64_3;
    typedef union  TCFG64_REG_CFG64_4
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_4;
                   };
                 } TCFG64_REG_CFG64_4;
    typedef union  TCFG64_REG_CFG64_5
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_5;
                   };
                 } TCFG64_REG_CFG64_5;
    typedef union  TCFG64_REG_CFG64_6
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_6;
                   };
                 } TCFG64_REG_CFG64_6;
    typedef union  TCFG64_REG_CFG64_7
          { UNSG32 u32[1];
            struct {
            struct w32CFG64_REG_CFG64_7;
                   };
                 } TCFG64_REG_CFG64_7;

    ///////////////////////////////////////////////////////////
     SIGN32 CFG64_REG_drvrd(SIE_CFG64_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CFG64_REG_drvwr(SIE_CFG64_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CFG64_REG_reset(SIE_CFG64_REG *p);
     SIGN32 CFG64_REG_cmp  (SIE_CFG64_REG *p, SIE_CFG64_REG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CFG64_REG_check(p,pie,pfx,hLOG) CFG64_REG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CFG64_REG_print(p,    pfx,hLOG) CFG64_REG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CFG64_REG
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE vsipll                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * PLL Control register
///               ###
///               %unsigned 1  PD                        0x0
///                                    ###
///                                    * PLL Power Down Signal.
///                                    * 1: PLL power down;
///                                    * 0: normal operation
///                                    ###
///               %unsigned 1  RESETN                    0x1
///                                    ###
///                                    * Resets the SSC & Fraction Function When Low
///                                    ###
///               %unsigned 6  DM                        0x1
///                                    ###
///                                    * Reference Input Divider Control Pins. Set the reference divider factor from 1 to 63
///                                    ###
///               %unsigned 11 DN                        0x20
///                                    ###
///                                    * Feedback Divider Control Pins. Set the feedback divider factor from 16 to 2048
///                                    ###
///               %unsigned 2  MODE                      0x0
///                                    ###
///                                    * Operation Mode Select
///                                    * 00: integer mode;
///                                    * 01: fraction mode;
///                                    * 10: spread spectrum mode;
///                                    * 11: reserved.
///                                    ###
///               %unsigned 1  READY_BP                  0x0
///                                    ###
///                                    * READY_bypass signal
///                                    * 0:FRAC_READY work normal
///                                    * 1:directly bypass FRAC<23:0> to PLL
///                                    ###
///               %unsigned 1  FRAC_READY                0x1
///                                    ###
///                                    * FRAC value ready flag.
///                                    ###
///               %%        9          # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 24 FRAC                      0x0
///                                    ###
///                                    * Fractional Portion of DN Value
///                                    ###
///               %%        8          # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 11 SSRATE                    0x0
///                                    ###
///                                    * Spreading Frequency Control. Set the triangle modulation frequency.
///                                    ###
///               %%        21         # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 24 SLOPE                     0x0
///                                    ###
///                                    * Spreading Slope Control.
///                                    ###
///               %unsigned 1  PDDP                      0x0
///                                    ###
///                                    * DP Power Down Signal. (0.8V signal)
///                                    * 1: DP power down;
///                                    * 0: DP normal operation
///                                    ###
///               %unsigned 3  DP                        0x4
///                                    ###
///                                    * Output Divider1 Control Pins. Set the post divider factor from 1 to 7
///                                    ###
///               %unsigned 1  PDDP1                     0x0
///                                    ###
///                                    * DP1 Power Down Signal. (0.8V signal)
///                                    * 1: DP1 power down;
///                                    * 0: DP1 normal operation
///                                    ###
///               %unsigned 3  DP1                       0x4
///                                    ###
///                                    * Output Divider1 Control Pins. Set the post divider factor from 1 to 7
///                                    ###
///     # 0x00010 ctrl4                
///               %unsigned 1  BYPASS                    0x0
///                                    ###
///                                    * PLL BYPASS Signal
///                                    * 1: PLL bypass
///                                    * 0: normal operation
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00014 status               (R-)
///               ###
///               * PLL status register
///               ###
///               %unsigned 1  LOCK                      
///                                    ###
///                                    * Output. Lock detection
///                                    ###
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:      92b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vsipll
#define h_vsipll (){}

    #define     RA_vsipll_ctrl                                 0x0000

    #define     BA_vsipll_ctrl_PD                              0x0000
    #define     B16vsipll_ctrl_PD                              0x0000
    #define   LSb32vsipll_ctrl_PD                                 0
    #define   LSb16vsipll_ctrl_PD                                 0
    #define       bvsipll_ctrl_PD                              1
    #define   MSK32vsipll_ctrl_PD                                 0x00000001

    #define     BA_vsipll_ctrl_RESETN                          0x0000
    #define     B16vsipll_ctrl_RESETN                          0x0000
    #define   LSb32vsipll_ctrl_RESETN                             1
    #define   LSb16vsipll_ctrl_RESETN                             1
    #define       bvsipll_ctrl_RESETN                          1
    #define   MSK32vsipll_ctrl_RESETN                             0x00000002

    #define     BA_vsipll_ctrl_DM                              0x0000
    #define     B16vsipll_ctrl_DM                              0x0000
    #define   LSb32vsipll_ctrl_DM                                 2
    #define   LSb16vsipll_ctrl_DM                                 2
    #define       bvsipll_ctrl_DM                              6
    #define   MSK32vsipll_ctrl_DM                                 0x000000FC

    #define     BA_vsipll_ctrl_DN                              0x0001
    #define     B16vsipll_ctrl_DN                              0x0000
    #define   LSb32vsipll_ctrl_DN                                 8
    #define   LSb16vsipll_ctrl_DN                                 8
    #define       bvsipll_ctrl_DN                              11
    #define   MSK32vsipll_ctrl_DN                                 0x0007FF00

    #define     BA_vsipll_ctrl_MODE                            0x0002
    #define     B16vsipll_ctrl_MODE                            0x0002
    #define   LSb32vsipll_ctrl_MODE                               19
    #define   LSb16vsipll_ctrl_MODE                               3
    #define       bvsipll_ctrl_MODE                            2
    #define   MSK32vsipll_ctrl_MODE                               0x00180000

    #define     BA_vsipll_ctrl_READY_BP                        0x0002
    #define     B16vsipll_ctrl_READY_BP                        0x0002
    #define   LSb32vsipll_ctrl_READY_BP                           21
    #define   LSb16vsipll_ctrl_READY_BP                           5
    #define       bvsipll_ctrl_READY_BP                        1
    #define   MSK32vsipll_ctrl_READY_BP                           0x00200000

    #define     BA_vsipll_ctrl_FRAC_READY                      0x0002
    #define     B16vsipll_ctrl_FRAC_READY                      0x0002
    #define   LSb32vsipll_ctrl_FRAC_READY                         22
    #define   LSb16vsipll_ctrl_FRAC_READY                         6
    #define       bvsipll_ctrl_FRAC_READY                      1
    #define   MSK32vsipll_ctrl_FRAC_READY                         0x00400000

    #define     RA_vsipll_ctrl1                                0x0004

    #define     BA_vsipll_ctrl_FRAC                            0x0004
    #define     B16vsipll_ctrl_FRAC                            0x0004
    #define   LSb32vsipll_ctrl_FRAC                               0
    #define   LSb16vsipll_ctrl_FRAC                               0
    #define       bvsipll_ctrl_FRAC                            24
    #define   MSK32vsipll_ctrl_FRAC                               0x00FFFFFF

    #define     RA_vsipll_ctrl2                                0x0008

    #define     BA_vsipll_ctrl_SSRATE                          0x0008
    #define     B16vsipll_ctrl_SSRATE                          0x0008
    #define   LSb32vsipll_ctrl_SSRATE                             0
    #define   LSb16vsipll_ctrl_SSRATE                             0
    #define       bvsipll_ctrl_SSRATE                          11
    #define   MSK32vsipll_ctrl_SSRATE                             0x000007FF

    #define     RA_vsipll_ctrl3                                0x000C

    #define     BA_vsipll_ctrl_SLOPE                           0x000C
    #define     B16vsipll_ctrl_SLOPE                           0x000C
    #define   LSb32vsipll_ctrl_SLOPE                              0
    #define   LSb16vsipll_ctrl_SLOPE                              0
    #define       bvsipll_ctrl_SLOPE                           24
    #define   MSK32vsipll_ctrl_SLOPE                              0x00FFFFFF

    #define     BA_vsipll_ctrl_PDDP                            0x000F
    #define     B16vsipll_ctrl_PDDP                            0x000E
    #define   LSb32vsipll_ctrl_PDDP                               24
    #define   LSb16vsipll_ctrl_PDDP                               8
    #define       bvsipll_ctrl_PDDP                            1
    #define   MSK32vsipll_ctrl_PDDP                               0x01000000

    #define     BA_vsipll_ctrl_DP                              0x000F
    #define     B16vsipll_ctrl_DP                              0x000E
    #define   LSb32vsipll_ctrl_DP                                 25
    #define   LSb16vsipll_ctrl_DP                                 9
    #define       bvsipll_ctrl_DP                              3
    #define   MSK32vsipll_ctrl_DP                                 0x0E000000

    #define     BA_vsipll_ctrl_PDDP1                           0x000F
    #define     B16vsipll_ctrl_PDDP1                           0x000E
    #define   LSb32vsipll_ctrl_PDDP1                              28
    #define   LSb16vsipll_ctrl_PDDP1                              12
    #define       bvsipll_ctrl_PDDP1                           1
    #define   MSK32vsipll_ctrl_PDDP1                              0x10000000

    #define     BA_vsipll_ctrl_DP1                             0x000F
    #define     B16vsipll_ctrl_DP1                             0x000E
    #define   LSb32vsipll_ctrl_DP1                                29
    #define   LSb16vsipll_ctrl_DP1                                13
    #define       bvsipll_ctrl_DP1                             3
    #define   MSK32vsipll_ctrl_DP1                                0xE0000000

    #define     RA_vsipll_ctrl4                                0x0010

    #define     BA_vsipll_ctrl_BYPASS                          0x0010
    #define     B16vsipll_ctrl_BYPASS                          0x0010
    #define   LSb32vsipll_ctrl_BYPASS                             0
    #define   LSb16vsipll_ctrl_BYPASS                             0
    #define       bvsipll_ctrl_BYPASS                          1
    #define   MSK32vsipll_ctrl_BYPASS                             0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_vsipll_status                               0x0014

    #define     BA_vsipll_status_LOCK                          0x0014
    #define     B16vsipll_status_LOCK                          0x0014
    #define   LSb32vsipll_status_LOCK                             0
    #define   LSb16vsipll_status_LOCK                             0
    #define       bvsipll_status_LOCK                          1
    #define   MSK32vsipll_status_LOCK                             0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vsipll {
    ///////////////////////////////////////////////////////////
    #define   GET32vsipll_ctrl_PD(r32)                         _BFGET_(r32, 0, 0)
    #define   SET32vsipll_ctrl_PD(r32,v)                       _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_ctrl_PD(r16)                         _BFGET_(r16, 0, 0)
    #define   SET16vsipll_ctrl_PD(r16,v)                       _BFSET_(r16, 0, 0,v)

    #define   GET32vsipll_ctrl_RESETN(r32)                     _BFGET_(r32, 1, 1)
    #define   SET32vsipll_ctrl_RESETN(r32,v)                   _BFSET_(r32, 1, 1,v)
    #define   GET16vsipll_ctrl_RESETN(r16)                     _BFGET_(r16, 1, 1)
    #define   SET16vsipll_ctrl_RESETN(r16,v)                   _BFSET_(r16, 1, 1,v)

    #define   GET32vsipll_ctrl_DM(r32)                         _BFGET_(r32, 7, 2)
    #define   SET32vsipll_ctrl_DM(r32,v)                       _BFSET_(r32, 7, 2,v)
    #define   GET16vsipll_ctrl_DM(r16)                         _BFGET_(r16, 7, 2)
    #define   SET16vsipll_ctrl_DM(r16,v)                       _BFSET_(r16, 7, 2,v)

    #define   GET32vsipll_ctrl_DN(r32)                         _BFGET_(r32,18, 8)
    #define   SET32vsipll_ctrl_DN(r32,v)                       _BFSET_(r32,18, 8,v)

    #define   GET32vsipll_ctrl_MODE(r32)                       _BFGET_(r32,20,19)
    #define   SET32vsipll_ctrl_MODE(r32,v)                     _BFSET_(r32,20,19,v)
    #define   GET16vsipll_ctrl_MODE(r16)                       _BFGET_(r16, 4, 3)
    #define   SET16vsipll_ctrl_MODE(r16,v)                     _BFSET_(r16, 4, 3,v)

    #define   GET32vsipll_ctrl_READY_BP(r32)                   _BFGET_(r32,21,21)
    #define   SET32vsipll_ctrl_READY_BP(r32,v)                 _BFSET_(r32,21,21,v)
    #define   GET16vsipll_ctrl_READY_BP(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16vsipll_ctrl_READY_BP(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32vsipll_ctrl_FRAC_READY(r32)                 _BFGET_(r32,22,22)
    #define   SET32vsipll_ctrl_FRAC_READY(r32,v)               _BFSET_(r32,22,22,v)
    #define   GET16vsipll_ctrl_FRAC_READY(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16vsipll_ctrl_FRAC_READY(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32vsipll_ctrl                                 {\
            UNSG32 uctrl_PD                                    :  1;\
            UNSG32 uctrl_RESETN                                :  1;\
            UNSG32 uctrl_DM                                    :  6;\
            UNSG32 uctrl_DN                                    : 11;\
            UNSG32 uctrl_MODE                                  :  2;\
            UNSG32 uctrl_READY_BP                              :  1;\
            UNSG32 uctrl_FRAC_READY                            :  1;\
            UNSG32 RSVDx0_b23                                  :  9;\
          }
    union { UNSG32 u32vsipll_ctrl;
            struct w32vsipll_ctrl;
          };
    #define   GET32vsipll_ctrl_FRAC(r32)                       _BFGET_(r32,23, 0)
    #define   SET32vsipll_ctrl_FRAC(r32,v)                     _BFSET_(r32,23, 0,v)

    #define     w32vsipll_ctrl1                                {\
            UNSG32 uctrl_FRAC                                  : 24;\
            UNSG32 RSVDx4_b24                                  :  8;\
          }
    union { UNSG32 u32vsipll_ctrl1;
            struct w32vsipll_ctrl1;
          };
    #define   GET32vsipll_ctrl_SSRATE(r32)                     _BFGET_(r32,10, 0)
    #define   SET32vsipll_ctrl_SSRATE(r32,v)                   _BFSET_(r32,10, 0,v)
    #define   GET16vsipll_ctrl_SSRATE(r16)                     _BFGET_(r16,10, 0)
    #define   SET16vsipll_ctrl_SSRATE(r16,v)                   _BFSET_(r16,10, 0,v)

    #define     w32vsipll_ctrl2                                {\
            UNSG32 uctrl_SSRATE                                : 11;\
            UNSG32 RSVDx8_b11                                  : 21;\
          }
    union { UNSG32 u32vsipll_ctrl2;
            struct w32vsipll_ctrl2;
          };
    #define   GET32vsipll_ctrl_SLOPE(r32)                      _BFGET_(r32,23, 0)
    #define   SET32vsipll_ctrl_SLOPE(r32,v)                    _BFSET_(r32,23, 0,v)

    #define   GET32vsipll_ctrl_PDDP(r32)                       _BFGET_(r32,24,24)
    #define   SET32vsipll_ctrl_PDDP(r32,v)                     _BFSET_(r32,24,24,v)
    #define   GET16vsipll_ctrl_PDDP(r16)                       _BFGET_(r16, 8, 8)
    #define   SET16vsipll_ctrl_PDDP(r16,v)                     _BFSET_(r16, 8, 8,v)

    #define   GET32vsipll_ctrl_DP(r32)                         _BFGET_(r32,27,25)
    #define   SET32vsipll_ctrl_DP(r32,v)                       _BFSET_(r32,27,25,v)
    #define   GET16vsipll_ctrl_DP(r16)                         _BFGET_(r16,11, 9)
    #define   SET16vsipll_ctrl_DP(r16,v)                       _BFSET_(r16,11, 9,v)

    #define   GET32vsipll_ctrl_PDDP1(r32)                      _BFGET_(r32,28,28)
    #define   SET32vsipll_ctrl_PDDP1(r32,v)                    _BFSET_(r32,28,28,v)
    #define   GET16vsipll_ctrl_PDDP1(r16)                      _BFGET_(r16,12,12)
    #define   SET16vsipll_ctrl_PDDP1(r16,v)                    _BFSET_(r16,12,12,v)

    #define   GET32vsipll_ctrl_DP1(r32)                        _BFGET_(r32,31,29)
    #define   SET32vsipll_ctrl_DP1(r32,v)                      _BFSET_(r32,31,29,v)
    #define   GET16vsipll_ctrl_DP1(r16)                        _BFGET_(r16,15,13)
    #define   SET16vsipll_ctrl_DP1(r16,v)                      _BFSET_(r16,15,13,v)

    #define     w32vsipll_ctrl3                                {\
            UNSG32 uctrl_SLOPE                                 : 24;\
            UNSG32 uctrl_PDDP                                  :  1;\
            UNSG32 uctrl_DP                                    :  3;\
            UNSG32 uctrl_PDDP1                                 :  1;\
            UNSG32 uctrl_DP1                                   :  3;\
          }
    union { UNSG32 u32vsipll_ctrl3;
            struct w32vsipll_ctrl3;
          };
    #define   GET32vsipll_ctrl_BYPASS(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32vsipll_ctrl_BYPASS(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_ctrl_BYPASS(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16vsipll_ctrl_BYPASS(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32vsipll_ctrl4                                {\
            UNSG32 uctrl_BYPASS                                :  1;\
            UNSG32 RSVDx10_b1                                  : 31;\
          }
    union { UNSG32 u32vsipll_ctrl4;
            struct w32vsipll_ctrl4;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32vsipll_status_LOCK(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32vsipll_status_LOCK(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_status_LOCK(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16vsipll_status_LOCK(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32vsipll_status                               {\
            UNSG32 ustatus_LOCK                                :  1;\
            UNSG32 RSVDx14_b1                                  : 31;\
          }
    union { UNSG32 u32vsipll_status;
            struct w32vsipll_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_vsipll;

    typedef union  T32vsipll_ctrl
          { UNSG32 u32;
            struct w32vsipll_ctrl;
                 } T32vsipll_ctrl;
    typedef union  T32vsipll_ctrl1
          { UNSG32 u32;
            struct w32vsipll_ctrl1;
                 } T32vsipll_ctrl1;
    typedef union  T32vsipll_ctrl2
          { UNSG32 u32;
            struct w32vsipll_ctrl2;
                 } T32vsipll_ctrl2;
    typedef union  T32vsipll_ctrl3
          { UNSG32 u32;
            struct w32vsipll_ctrl3;
                 } T32vsipll_ctrl3;
    typedef union  T32vsipll_ctrl4
          { UNSG32 u32;
            struct w32vsipll_ctrl4;
                 } T32vsipll_ctrl4;
    typedef union  T32vsipll_status
          { UNSG32 u32;
            struct w32vsipll_status;
                 } T32vsipll_status;
    ///////////////////////////////////////////////////////////

    typedef union  Tvsipll_ctrl
          { UNSG32 u32[5];
            struct {
            struct w32vsipll_ctrl;
            struct w32vsipll_ctrl1;
            struct w32vsipll_ctrl2;
            struct w32vsipll_ctrl3;
            struct w32vsipll_ctrl4;
                   };
                 } Tvsipll_ctrl;
    typedef union  Tvsipll_status
          { UNSG32 u32[1];
            struct {
            struct w32vsipll_status;
                   };
                 } Tvsipll_status;

    ///////////////////////////////////////////////////////////
     SIGN32 vsipll_drvrd(SIE_vsipll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vsipll_drvwr(SIE_vsipll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vsipll_reset(SIE_vsipll *p);
     SIGN32 vsipll_cmp  (SIE_vsipll *p, SIE_vsipll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vsipll_check(p,pie,pfx,hLOG) vsipll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vsipll_print(p,    pfx,hLOG) vsipll_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vsipll
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOff                                   (4,4)
///     ###
///     * Register for the Power domain which is OFF by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x0
///                                    : PWROFF                    0x0
///                                    : PWRON                     0x3
///                                                 ###
///                                                 * Power Switch control
///                                                 * Bit 1 : SLP1B
///                                                 * Bit 0 : SLP2B
///                                                 * SLP1B SLP2B
///                                                 * 0               X               Switch is turned off
///                                                 * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                                 * 1               1               PMOS switch is fully turned on to reduce Ron
///                                                 ###
///               %unsigned 1  pwrDomainRstN             0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Power Domain Reset. Active low.
///                                                 * 0 : Reset the power domain
///                                                 * 1:   De-assert the reset for the power domain
///                                                 ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOff
#define h_pwrOff (){}

    #define     RA_pwrOff_ctrl                                 0x0000

    #define     BA_pwrOff_ctrl_iso_eN                          0x0000
    #define     B16pwrOff_ctrl_iso_eN                          0x0000
    #define   LSb32pwrOff_ctrl_iso_eN                             0
    #define   LSb16pwrOff_ctrl_iso_eN                             0
    #define       bpwrOff_ctrl_iso_eN                          1
    #define   MSK32pwrOff_ctrl_iso_eN                             0x00000001
    #define        pwrOff_ctrl_iso_eN_enable                                0x0
    #define        pwrOff_ctrl_iso_eN_disable                               0x1

    #define     BA_pwrOff_ctrl_pwrSwitchCtrl                   0x0000
    #define     B16pwrOff_ctrl_pwrSwitchCtrl                   0x0000
    #define   LSb32pwrOff_ctrl_pwrSwitchCtrl                      1
    #define   LSb16pwrOff_ctrl_pwrSwitchCtrl                      1
    #define       bpwrOff_ctrl_pwrSwitchCtrl                   2
    #define   MSK32pwrOff_ctrl_pwrSwitchCtrl                      0x00000006
    #define        pwrOff_ctrl_pwrSwitchCtrl_PWROFF                         0x0
    #define        pwrOff_ctrl_pwrSwitchCtrl_PWRON                          0x3

    #define     BA_pwrOff_ctrl_pwrDomainRstN                   0x0000
    #define     B16pwrOff_ctrl_pwrDomainRstN                   0x0000
    #define   LSb32pwrOff_ctrl_pwrDomainRstN                      3
    #define   LSb16pwrOff_ctrl_pwrDomainRstN                      3
    #define       bpwrOff_ctrl_pwrDomainRstN                   1
    #define   MSK32pwrOff_ctrl_pwrDomainRstN                      0x00000008
    #define        pwrOff_ctrl_pwrDomainRstN_enable                         0x0
    #define        pwrOff_ctrl_pwrDomainRstN_disable                        0x1
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOff_status                               0x0004

    #define     BA_pwrOff_status_pwrStatus                     0x0004
    #define     B16pwrOff_status_pwrStatus                     0x0004
    #define   LSb32pwrOff_status_pwrStatus                        0
    #define   LSb16pwrOff_status_pwrStatus                        0
    #define       bpwrOff_status_pwrStatus                     2
    #define   MSK32pwrOff_status_pwrStatus                        0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOff {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOff_ctrl_iso_eN(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32pwrOff_ctrl_iso_eN(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOff_ctrl_iso_eN(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16pwrOff_ctrl_iso_eN(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOff_ctrl_pwrSwitchCtrl(r32)              _BFGET_(r32, 2, 1)
    #define   SET32pwrOff_ctrl_pwrSwitchCtrl(r32,v)            _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOff_ctrl_pwrSwitchCtrl(r16)              _BFGET_(r16, 2, 1)
    #define   SET16pwrOff_ctrl_pwrSwitchCtrl(r16,v)            _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOff_ctrl_pwrDomainRstN(r32)              _BFGET_(r32, 3, 3)
    #define   SET32pwrOff_ctrl_pwrDomainRstN(r32,v)            _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOff_ctrl_pwrDomainRstN(r16)              _BFGET_(r16, 3, 3)
    #define   SET16pwrOff_ctrl_pwrDomainRstN(r16,v)            _BFSET_(r16, 3, 3,v)

    #define     w32pwrOff_ctrl                                 {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOff_ctrl;
            struct w32pwrOff_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOff_status_pwrStatus(r32)                _BFGET_(r32, 1, 0)
    #define   SET32pwrOff_status_pwrStatus(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOff_status_pwrStatus(r16)                _BFGET_(r16, 1, 0)
    #define   SET16pwrOff_status_pwrStatus(r16,v)              _BFSET_(r16, 1, 0,v)

    #define     w32pwrOff_status                               {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32pwrOff_status;
            struct w32pwrOff_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOff;

    typedef union  T32pwrOff_ctrl
          { UNSG32 u32;
            struct w32pwrOff_ctrl;
                 } T32pwrOff_ctrl;
    typedef union  T32pwrOff_status
          { UNSG32 u32;
            struct w32pwrOff_status;
                 } T32pwrOff_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOff_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOff_ctrl;
                   };
                 } TpwrOff_ctrl;
    typedef union  TpwrOff_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOff_status;
                   };
                 } TpwrOff_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOff_drvrd(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOff_drvwr(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOff_reset(SIE_pwrOff *p);
     SIGN32 pwrOff_cmp  (SIE_pwrOff *p, SIE_pwrOff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOff_check(p,pie,pfx,hLOG) pwrOff_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOff_print(p,    pfx,hLOG) pwrOff_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOff
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOn                                    (4,4)
///     ###
///     * Register for the Power domain which is ON by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x1
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x3
///                                    ###
///                                    * Power Switch control
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  pwrDomainRstN             0x1
///                                    ###
///                                    * Power Domain Reset. Active low.
///                                    * 0 : Reset the power domain
///                                    * 1:   De-assert the reset for the power domain
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn
#define h_pwrOn (){}

    #define     RA_pwrOn_ctrl                                  0x0000

    #define     BA_pwrOn_ctrl_iso_eN                           0x0000
    #define     B16pwrOn_ctrl_iso_eN                           0x0000
    #define   LSb32pwrOn_ctrl_iso_eN                              0
    #define   LSb16pwrOn_ctrl_iso_eN                              0
    #define       bpwrOn_ctrl_iso_eN                           1
    #define   MSK32pwrOn_ctrl_iso_eN                              0x00000001
    #define        pwrOn_ctrl_iso_eN_enable                                 0x0
    #define        pwrOn_ctrl_iso_eN_disable                                0x1

    #define     BA_pwrOn_ctrl_pwrSwitchCtrl                    0x0000
    #define     B16pwrOn_ctrl_pwrSwitchCtrl                    0x0000
    #define   LSb32pwrOn_ctrl_pwrSwitchCtrl                       1
    #define   LSb16pwrOn_ctrl_pwrSwitchCtrl                       1
    #define       bpwrOn_ctrl_pwrSwitchCtrl                    2
    #define   MSK32pwrOn_ctrl_pwrSwitchCtrl                       0x00000006

    #define     BA_pwrOn_ctrl_pwrDomainRstN                    0x0000
    #define     B16pwrOn_ctrl_pwrDomainRstN                    0x0000
    #define   LSb32pwrOn_ctrl_pwrDomainRstN                       3
    #define   LSb16pwrOn_ctrl_pwrDomainRstN                       3
    #define       bpwrOn_ctrl_pwrDomainRstN                    1
    #define   MSK32pwrOn_ctrl_pwrDomainRstN                       0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOn_status                                0x0004

    #define     BA_pwrOn_status_pwrStatus                      0x0004
    #define     B16pwrOn_status_pwrStatus                      0x0004
    #define   LSb32pwrOn_status_pwrStatus                         0
    #define   LSb16pwrOn_status_pwrStatus                         0
    #define       bpwrOn_status_pwrStatus                      2
    #define   MSK32pwrOn_status_pwrStatus                         0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOn {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_ctrl_iso_eN(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32pwrOn_ctrl_iso_eN(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOn_ctrl_iso_eN(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16pwrOn_ctrl_iso_eN(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOn_ctrl_pwrSwitchCtrl(r32)               _BFGET_(r32, 2, 1)
    #define   SET32pwrOn_ctrl_pwrSwitchCtrl(r32,v)             _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOn_ctrl_pwrSwitchCtrl(r16)               _BFGET_(r16, 2, 1)
    #define   SET16pwrOn_ctrl_pwrSwitchCtrl(r16,v)             _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOn_ctrl_pwrDomainRstN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32pwrOn_ctrl_pwrDomainRstN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOn_ctrl_pwrDomainRstN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16pwrOn_ctrl_pwrDomainRstN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define     w32pwrOn_ctrl                                  {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOn_ctrl;
            struct w32pwrOn_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_status_pwrStatus(r32)                 _BFGET_(r32, 1, 0)
    #define   SET32pwrOn_status_pwrStatus(r32,v)               _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOn_status_pwrStatus(r16)                 _BFGET_(r16, 1, 0)
    #define   SET16pwrOn_status_pwrStatus(r16,v)               _BFSET_(r16, 1, 0,v)

    #define     w32pwrOn_status                                {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32pwrOn_status;
            struct w32pwrOn_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOn;

    typedef union  T32pwrOn_ctrl
          { UNSG32 u32;
            struct w32pwrOn_ctrl;
                 } T32pwrOn_ctrl;
    typedef union  T32pwrOn_status
          { UNSG32 u32;
            struct w32pwrOn_status;
                 } T32pwrOn_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOn_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_ctrl;
                   };
                 } TpwrOn_ctrl;
    typedef union  TpwrOn_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_status;
                   };
                 } TpwrOn_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOn_drvrd(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOn_drvwr(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOn_reset(SIE_pwrOn *p);
     SIGN32 pwrOn_cmp  (SIE_pwrOn *p, SIE_pwrOn *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOn_check(p,pie,pfx,hLOG) pwrOn_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOn_print(p,    pfx,hLOG) pwrOn_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOn
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOn_iso                                (4,4)
///     ###
///     * Register for the Power domain which is ON by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x3
///                                    ###
///                                    * Power Switch control
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  pwrDomainRstN             0x0
///                                    ###
///                                    * Power Domain Reset. Active low.
///                                    * 0 : Reset the power domain
///                                    * 1:   De-assert the reset for the power domain
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  IP_IDLE                   
///                                    ###
///                                    * Indication from IP that it is idle and can be powered down.
///                                    * 1: Idle
///                                    * 0: Busy
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       7b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn_iso
#define h_pwrOn_iso (){}

    #define     RA_pwrOn_iso_ctrl                              0x0000

    #define     BA_pwrOn_iso_ctrl_iso_eN                       0x0000
    #define     B16pwrOn_iso_ctrl_iso_eN                       0x0000
    #define   LSb32pwrOn_iso_ctrl_iso_eN                          0
    #define   LSb16pwrOn_iso_ctrl_iso_eN                          0
    #define       bpwrOn_iso_ctrl_iso_eN                       1
    #define   MSK32pwrOn_iso_ctrl_iso_eN                          0x00000001
    #define        pwrOn_iso_ctrl_iso_eN_enable                             0x0
    #define        pwrOn_iso_ctrl_iso_eN_disable                            0x1

    #define     BA_pwrOn_iso_ctrl_pwrSwitchCtrl                0x0000
    #define     B16pwrOn_iso_ctrl_pwrSwitchCtrl                0x0000
    #define   LSb32pwrOn_iso_ctrl_pwrSwitchCtrl                   1
    #define   LSb16pwrOn_iso_ctrl_pwrSwitchCtrl                   1
    #define       bpwrOn_iso_ctrl_pwrSwitchCtrl                2
    #define   MSK32pwrOn_iso_ctrl_pwrSwitchCtrl                   0x00000006

    #define     BA_pwrOn_iso_ctrl_pwrDomainRstN                0x0000
    #define     B16pwrOn_iso_ctrl_pwrDomainRstN                0x0000
    #define   LSb32pwrOn_iso_ctrl_pwrDomainRstN                   3
    #define   LSb16pwrOn_iso_ctrl_pwrDomainRstN                   3
    #define       bpwrOn_iso_ctrl_pwrDomainRstN                1
    #define   MSK32pwrOn_iso_ctrl_pwrDomainRstN                   0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOn_iso_status                            0x0004

    #define     BA_pwrOn_iso_status_pwrStatus                  0x0004
    #define     B16pwrOn_iso_status_pwrStatus                  0x0004
    #define   LSb32pwrOn_iso_status_pwrStatus                     0
    #define   LSb16pwrOn_iso_status_pwrStatus                     0
    #define       bpwrOn_iso_status_pwrStatus                  2
    #define   MSK32pwrOn_iso_status_pwrStatus                     0x00000003

    #define     BA_pwrOn_iso_status_IP_IDLE                    0x0004
    #define     B16pwrOn_iso_status_IP_IDLE                    0x0004
    #define   LSb32pwrOn_iso_status_IP_IDLE                       2
    #define   LSb16pwrOn_iso_status_IP_IDLE                       2
    #define       bpwrOn_iso_status_IP_IDLE                    1
    #define   MSK32pwrOn_iso_status_IP_IDLE                       0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOn_iso {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_iso_ctrl_iso_eN(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32pwrOn_iso_ctrl_iso_eN(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOn_iso_ctrl_iso_eN(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16pwrOn_iso_ctrl_iso_eN(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOn_iso_ctrl_pwrSwitchCtrl(r32)           _BFGET_(r32, 2, 1)
    #define   SET32pwrOn_iso_ctrl_pwrSwitchCtrl(r32,v)         _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOn_iso_ctrl_pwrSwitchCtrl(r16)           _BFGET_(r16, 2, 1)
    #define   SET16pwrOn_iso_ctrl_pwrSwitchCtrl(r16,v)         _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOn_iso_ctrl_pwrDomainRstN(r32)           _BFGET_(r32, 3, 3)
    #define   SET32pwrOn_iso_ctrl_pwrDomainRstN(r32,v)         _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOn_iso_ctrl_pwrDomainRstN(r16)           _BFGET_(r16, 3, 3)
    #define   SET16pwrOn_iso_ctrl_pwrDomainRstN(r16,v)         _BFSET_(r16, 3, 3,v)

    #define     w32pwrOn_iso_ctrl                              {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOn_iso_ctrl;
            struct w32pwrOn_iso_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_iso_status_pwrStatus(r32)             _BFGET_(r32, 1, 0)
    #define   SET32pwrOn_iso_status_pwrStatus(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOn_iso_status_pwrStatus(r16)             _BFGET_(r16, 1, 0)
    #define   SET16pwrOn_iso_status_pwrStatus(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32pwrOn_iso_status_IP_IDLE(r32)               _BFGET_(r32, 2, 2)
    #define   SET32pwrOn_iso_status_IP_IDLE(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16pwrOn_iso_status_IP_IDLE(r16)               _BFGET_(r16, 2, 2)
    #define   SET16pwrOn_iso_status_IP_IDLE(r16,v)             _BFSET_(r16, 2, 2,v)

    #define     w32pwrOn_iso_status                            {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 ustatus_IP_IDLE                             :  1;\
            UNSG32 RSVDx4_b3                                   : 29;\
          }
    union { UNSG32 u32pwrOn_iso_status;
            struct w32pwrOn_iso_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOn_iso;

    typedef union  T32pwrOn_iso_ctrl
          { UNSG32 u32;
            struct w32pwrOn_iso_ctrl;
                 } T32pwrOn_iso_ctrl;
    typedef union  T32pwrOn_iso_status
          { UNSG32 u32;
            struct w32pwrOn_iso_status;
                 } T32pwrOn_iso_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOn_iso_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_iso_ctrl;
                   };
                 } TpwrOn_iso_ctrl;
    typedef union  TpwrOn_iso_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_iso_status;
                   };
                 } TpwrOn_iso_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOn_iso_drvrd(SIE_pwrOn_iso *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOn_iso_drvwr(SIE_pwrOn_iso *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOn_iso_reset(SIE_pwrOn_iso *p);
     SIGN32 pwrOn_iso_cmp  (SIE_pwrOn_iso *p, SIE_pwrOn_iso *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOn_iso_check(p,pie,pfx,hLOG) pwrOn_iso_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOn_iso_print(p,    pfx,hLOG) pwrOn_iso_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOn_iso
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE CPU_WRP                 biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CPU_REG              (P)
///     # 0x00000 CPU_REG              
///               $CPU_REG             CPU_REG           REG          
///     @ 0x000DC                      (W-)
///     #         # Stuffing bytes...
///               %% 14624
///     @ 0x00800 CFG64_REG            (P)
///     # 0x00800 CFG64_REG            
///               $CFG64_REG           CFG64_REG         REG          
///     @ 0x00820                      (W-)
///     #         # Stuffing bytes...
///               %% 16128
///     @ 0x01000 TIMER_REG            (P)
///     # 0x01000 TIMER_REG            
///               $TIMER_REG           TIMER_REG         REG          
///     @ 0x01030                      (W-)
///     #         # Stuffing bytes...
///               %% 32384
///     @ 0x02000 PLL_REG              (P)
///     # 0x02000 PLL_REG              
///               $vsipll              PLL_REG           REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    8216B, bits:    1022b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_CPU_WRP
#define h_CPU_WRP (){}

    #define     RA_CPU_WRP_CPU_REG                             0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_WRP_CFG64_REG                           0x0800
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_WRP_TIMER_REG                           0x1000
    ///////////////////////////////////////////////////////////
    #define     RA_CPU_WRP_PLL_REG                             0x2000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_CPU_WRP {
    ///////////////////////////////////////////////////////////
              SIE_CPU_REG                                      ie_CPU_REG;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDxDC                                     [1828];
    ///////////////////////////////////////////////////////////
              SIE_CFG64_REG                                    ie_CFG64_REG;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx820                                    [2016];
    ///////////////////////////////////////////////////////////
              SIE_TIMER_REG                                    ie_TIMER_REG;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1030                                   [4048];
    ///////////////////////////////////////////////////////////
              SIE_vsipll                                       ie_PLL_REG;
    ///////////////////////////////////////////////////////////
    } SIE_CPU_WRP;

    ///////////////////////////////////////////////////////////
     SIGN32 CPU_WRP_drvrd(SIE_CPU_WRP *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 CPU_WRP_drvwr(SIE_CPU_WRP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void CPU_WRP_reset(SIE_CPU_WRP *p);
     SIGN32 CPU_WRP_cmp  (SIE_CPU_WRP *p, SIE_CPU_WRP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define CPU_WRP_check(p,pie,pfx,hLOG) CPU_WRP_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define CPU_WRP_print(p,    pfx,hLOG) CPU_WRP_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: CPU_WRP
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: cpu_wrp.h
////////////////////////////////////////////////////////////