//////
/// don't edit! auto-generated by docc: global.h
////////////////////////////////////////////////////////////
#ifndef global_h
#define global_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE vsipll                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * PLL Control register
///               ###
///               %unsigned 1  PD                        0x0
///                                    ###
///                                    * PLL Power Down Signal.
///                                    * 1: PLL power down;
///                                    * 0: normal operation
///                                    ###
///               %unsigned 1  RESETN                    0x1
///                                    ###
///                                    * Resets the SSC & Fraction Function When Low
///                                    ###
///               %unsigned 6  DM                        0x1
///                                    ###
///                                    * Reference Input Divider Control Pins. Set the reference divider factor from 1 to 63
///                                    ###
///               %unsigned 11 DN                        0x20
///                                    ###
///                                    * Feedback Divider Control Pins. Set the feedback divider factor from 16 to 2048
///                                    ###
///               %unsigned 2  MODE                      0x0
///                                    ###
///                                    * Operation Mode Select
///                                    * 00: integer mode;
///                                    * 01: fraction mode;
///                                    * 10: spread spectrum mode;
///                                    * 11: reserved.
///                                    ###
///               %unsigned 1  READY_BP                  0x0
///                                    ###
///                                    * READY_bypass signal
///                                    * 0:FRAC_READY work normal
///                                    * 1:directly bypass FRAC<23:0> to PLL
///                                    ###
///               %unsigned 1  FRAC_READY                0x1
///                                    ###
///                                    * FRAC value ready flag.
///                                    ###
///               %%        9          # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 24 FRAC                      0x0
///                                    ###
///                                    * Fractional Portion of DN Value
///                                    ###
///               %%        8          # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 11 SSRATE                    0x0
///                                    ###
///                                    * Spreading Frequency Control. Set the triangle modulation frequency.
///                                    ###
///               %%        21         # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 24 SLOPE                     0x0
///                                    ###
///                                    * Spreading Slope Control.
///                                    ###
///               %unsigned 1  PDDP                      0x0
///                                    ###
///                                    * DP Power Down Signal. (0.8V signal)
///                                    * 1: DP power down;
///                                    * 0: DP normal operation
///                                    ###
///               %unsigned 3  DP                        0x4
///                                    ###
///                                    * Output Divider1 Control Pins. Set the post divider factor from 1 to 7
///                                    ###
///               %unsigned 1  PDDP1                     0x0
///                                    ###
///                                    * DP1 Power Down Signal. (0.8V signal)
///                                    * 1: DP1 power down;
///                                    * 0: DP1 normal operation
///                                    ###
///               %unsigned 3  DP1                       0x4
///                                    ###
///                                    * Output Divider1 Control Pins. Set the post divider factor from 1 to 7
///                                    ###
///     # 0x00010 ctrl4                
///               %unsigned 1  BYPASS                    0x0
///                                    ###
///                                    * PLL BYPASS Signal
///                                    * 1: PLL bypass
///                                    * 0: normal operation
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00014 status               (R-)
///               ###
///               * PLL status register
///               ###
///               %unsigned 1  LOCK                      
///                                    ###
///                                    * Output. Lock detection
///                                    ###
///               %%        31         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:      92b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_vsipll
#define h_vsipll (){}

    #define     RA_vsipll_ctrl                                 0x0000

    #define     BA_vsipll_ctrl_PD                              0x0000
    #define     B16vsipll_ctrl_PD                              0x0000
    #define   LSb32vsipll_ctrl_PD                                 0
    #define   LSb16vsipll_ctrl_PD                                 0
    #define       bvsipll_ctrl_PD                              1
    #define   MSK32vsipll_ctrl_PD                                 0x00000001

    #define     BA_vsipll_ctrl_RESETN                          0x0000
    #define     B16vsipll_ctrl_RESETN                          0x0000
    #define   LSb32vsipll_ctrl_RESETN                             1
    #define   LSb16vsipll_ctrl_RESETN                             1
    #define       bvsipll_ctrl_RESETN                          1
    #define   MSK32vsipll_ctrl_RESETN                             0x00000002

    #define     BA_vsipll_ctrl_DM                              0x0000
    #define     B16vsipll_ctrl_DM                              0x0000
    #define   LSb32vsipll_ctrl_DM                                 2
    #define   LSb16vsipll_ctrl_DM                                 2
    #define       bvsipll_ctrl_DM                              6
    #define   MSK32vsipll_ctrl_DM                                 0x000000FC

    #define     BA_vsipll_ctrl_DN                              0x0001
    #define     B16vsipll_ctrl_DN                              0x0000
    #define   LSb32vsipll_ctrl_DN                                 8
    #define   LSb16vsipll_ctrl_DN                                 8
    #define       bvsipll_ctrl_DN                              11
    #define   MSK32vsipll_ctrl_DN                                 0x0007FF00

    #define     BA_vsipll_ctrl_MODE                            0x0002
    #define     B16vsipll_ctrl_MODE                            0x0002
    #define   LSb32vsipll_ctrl_MODE                               19
    #define   LSb16vsipll_ctrl_MODE                               3
    #define       bvsipll_ctrl_MODE                            2
    #define   MSK32vsipll_ctrl_MODE                               0x00180000

    #define     BA_vsipll_ctrl_READY_BP                        0x0002
    #define     B16vsipll_ctrl_READY_BP                        0x0002
    #define   LSb32vsipll_ctrl_READY_BP                           21
    #define   LSb16vsipll_ctrl_READY_BP                           5
    #define       bvsipll_ctrl_READY_BP                        1
    #define   MSK32vsipll_ctrl_READY_BP                           0x00200000

    #define     BA_vsipll_ctrl_FRAC_READY                      0x0002
    #define     B16vsipll_ctrl_FRAC_READY                      0x0002
    #define   LSb32vsipll_ctrl_FRAC_READY                         22
    #define   LSb16vsipll_ctrl_FRAC_READY                         6
    #define       bvsipll_ctrl_FRAC_READY                      1
    #define   MSK32vsipll_ctrl_FRAC_READY                         0x00400000

    #define     RA_vsipll_ctrl1                                0x0004

    #define     BA_vsipll_ctrl_FRAC                            0x0004
    #define     B16vsipll_ctrl_FRAC                            0x0004
    #define   LSb32vsipll_ctrl_FRAC                               0
    #define   LSb16vsipll_ctrl_FRAC                               0
    #define       bvsipll_ctrl_FRAC                            24
    #define   MSK32vsipll_ctrl_FRAC                               0x00FFFFFF

    #define     RA_vsipll_ctrl2                                0x0008

    #define     BA_vsipll_ctrl_SSRATE                          0x0008
    #define     B16vsipll_ctrl_SSRATE                          0x0008
    #define   LSb32vsipll_ctrl_SSRATE                             0
    #define   LSb16vsipll_ctrl_SSRATE                             0
    #define       bvsipll_ctrl_SSRATE                          11
    #define   MSK32vsipll_ctrl_SSRATE                             0x000007FF

    #define     RA_vsipll_ctrl3                                0x000C

    #define     BA_vsipll_ctrl_SLOPE                           0x000C
    #define     B16vsipll_ctrl_SLOPE                           0x000C
    #define   LSb32vsipll_ctrl_SLOPE                              0
    #define   LSb16vsipll_ctrl_SLOPE                              0
    #define       bvsipll_ctrl_SLOPE                           24
    #define   MSK32vsipll_ctrl_SLOPE                              0x00FFFFFF

    #define     BA_vsipll_ctrl_PDDP                            0x000F
    #define     B16vsipll_ctrl_PDDP                            0x000E
    #define   LSb32vsipll_ctrl_PDDP                               24
    #define   LSb16vsipll_ctrl_PDDP                               8
    #define       bvsipll_ctrl_PDDP                            1
    #define   MSK32vsipll_ctrl_PDDP                               0x01000000

    #define     BA_vsipll_ctrl_DP                              0x000F
    #define     B16vsipll_ctrl_DP                              0x000E
    #define   LSb32vsipll_ctrl_DP                                 25
    #define   LSb16vsipll_ctrl_DP                                 9
    #define       bvsipll_ctrl_DP                              3
    #define   MSK32vsipll_ctrl_DP                                 0x0E000000

    #define     BA_vsipll_ctrl_PDDP1                           0x000F
    #define     B16vsipll_ctrl_PDDP1                           0x000E
    #define   LSb32vsipll_ctrl_PDDP1                              28
    #define   LSb16vsipll_ctrl_PDDP1                              12
    #define       bvsipll_ctrl_PDDP1                           1
    #define   MSK32vsipll_ctrl_PDDP1                              0x10000000

    #define     BA_vsipll_ctrl_DP1                             0x000F
    #define     B16vsipll_ctrl_DP1                             0x000E
    #define   LSb32vsipll_ctrl_DP1                                29
    #define   LSb16vsipll_ctrl_DP1                                13
    #define       bvsipll_ctrl_DP1                             3
    #define   MSK32vsipll_ctrl_DP1                                0xE0000000

    #define     RA_vsipll_ctrl4                                0x0010

    #define     BA_vsipll_ctrl_BYPASS                          0x0010
    #define     B16vsipll_ctrl_BYPASS                          0x0010
    #define   LSb32vsipll_ctrl_BYPASS                             0
    #define   LSb16vsipll_ctrl_BYPASS                             0
    #define       bvsipll_ctrl_BYPASS                          1
    #define   MSK32vsipll_ctrl_BYPASS                             0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_vsipll_status                               0x0014

    #define     BA_vsipll_status_LOCK                          0x0014
    #define     B16vsipll_status_LOCK                          0x0014
    #define   LSb32vsipll_status_LOCK                             0
    #define   LSb16vsipll_status_LOCK                             0
    #define       bvsipll_status_LOCK                          1
    #define   MSK32vsipll_status_LOCK                             0x00000001
    ///////////////////////////////////////////////////////////

    typedef struct SIE_vsipll {
    ///////////////////////////////////////////////////////////
    #define   GET32vsipll_ctrl_PD(r32)                         _BFGET_(r32, 0, 0)
    #define   SET32vsipll_ctrl_PD(r32,v)                       _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_ctrl_PD(r16)                         _BFGET_(r16, 0, 0)
    #define   SET16vsipll_ctrl_PD(r16,v)                       _BFSET_(r16, 0, 0,v)

    #define   GET32vsipll_ctrl_RESETN(r32)                     _BFGET_(r32, 1, 1)
    #define   SET32vsipll_ctrl_RESETN(r32,v)                   _BFSET_(r32, 1, 1,v)
    #define   GET16vsipll_ctrl_RESETN(r16)                     _BFGET_(r16, 1, 1)
    #define   SET16vsipll_ctrl_RESETN(r16,v)                   _BFSET_(r16, 1, 1,v)

    #define   GET32vsipll_ctrl_DM(r32)                         _BFGET_(r32, 7, 2)
    #define   SET32vsipll_ctrl_DM(r32,v)                       _BFSET_(r32, 7, 2,v)
    #define   GET16vsipll_ctrl_DM(r16)                         _BFGET_(r16, 7, 2)
    #define   SET16vsipll_ctrl_DM(r16,v)                       _BFSET_(r16, 7, 2,v)

    #define   GET32vsipll_ctrl_DN(r32)                         _BFGET_(r32,18, 8)
    #define   SET32vsipll_ctrl_DN(r32,v)                       _BFSET_(r32,18, 8,v)

    #define   GET32vsipll_ctrl_MODE(r32)                       _BFGET_(r32,20,19)
    #define   SET32vsipll_ctrl_MODE(r32,v)                     _BFSET_(r32,20,19,v)
    #define   GET16vsipll_ctrl_MODE(r16)                       _BFGET_(r16, 4, 3)
    #define   SET16vsipll_ctrl_MODE(r16,v)                     _BFSET_(r16, 4, 3,v)

    #define   GET32vsipll_ctrl_READY_BP(r32)                   _BFGET_(r32,21,21)
    #define   SET32vsipll_ctrl_READY_BP(r32,v)                 _BFSET_(r32,21,21,v)
    #define   GET16vsipll_ctrl_READY_BP(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16vsipll_ctrl_READY_BP(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32vsipll_ctrl_FRAC_READY(r32)                 _BFGET_(r32,22,22)
    #define   SET32vsipll_ctrl_FRAC_READY(r32,v)               _BFSET_(r32,22,22,v)
    #define   GET16vsipll_ctrl_FRAC_READY(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16vsipll_ctrl_FRAC_READY(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32vsipll_ctrl                                 {\
            UNSG32 uctrl_PD                                    :  1;\
            UNSG32 uctrl_RESETN                                :  1;\
            UNSG32 uctrl_DM                                    :  6;\
            UNSG32 uctrl_DN                                    : 11;\
            UNSG32 uctrl_MODE                                  :  2;\
            UNSG32 uctrl_READY_BP                              :  1;\
            UNSG32 uctrl_FRAC_READY                            :  1;\
            UNSG32 RSVDx0_b23                                  :  9;\
          }
    union { UNSG32 u32vsipll_ctrl;
            struct w32vsipll_ctrl;
          };
    #define   GET32vsipll_ctrl_FRAC(r32)                       _BFGET_(r32,23, 0)
    #define   SET32vsipll_ctrl_FRAC(r32,v)                     _BFSET_(r32,23, 0,v)

    #define     w32vsipll_ctrl1                                {\
            UNSG32 uctrl_FRAC                                  : 24;\
            UNSG32 RSVDx4_b24                                  :  8;\
          }
    union { UNSG32 u32vsipll_ctrl1;
            struct w32vsipll_ctrl1;
          };
    #define   GET32vsipll_ctrl_SSRATE(r32)                     _BFGET_(r32,10, 0)
    #define   SET32vsipll_ctrl_SSRATE(r32,v)                   _BFSET_(r32,10, 0,v)
    #define   GET16vsipll_ctrl_SSRATE(r16)                     _BFGET_(r16,10, 0)
    #define   SET16vsipll_ctrl_SSRATE(r16,v)                   _BFSET_(r16,10, 0,v)

    #define     w32vsipll_ctrl2                                {\
            UNSG32 uctrl_SSRATE                                : 11;\
            UNSG32 RSVDx8_b11                                  : 21;\
          }
    union { UNSG32 u32vsipll_ctrl2;
            struct w32vsipll_ctrl2;
          };
    #define   GET32vsipll_ctrl_SLOPE(r32)                      _BFGET_(r32,23, 0)
    #define   SET32vsipll_ctrl_SLOPE(r32,v)                    _BFSET_(r32,23, 0,v)

    #define   GET32vsipll_ctrl_PDDP(r32)                       _BFGET_(r32,24,24)
    #define   SET32vsipll_ctrl_PDDP(r32,v)                     _BFSET_(r32,24,24,v)
    #define   GET16vsipll_ctrl_PDDP(r16)                       _BFGET_(r16, 8, 8)
    #define   SET16vsipll_ctrl_PDDP(r16,v)                     _BFSET_(r16, 8, 8,v)

    #define   GET32vsipll_ctrl_DP(r32)                         _BFGET_(r32,27,25)
    #define   SET32vsipll_ctrl_DP(r32,v)                       _BFSET_(r32,27,25,v)
    #define   GET16vsipll_ctrl_DP(r16)                         _BFGET_(r16,11, 9)
    #define   SET16vsipll_ctrl_DP(r16,v)                       _BFSET_(r16,11, 9,v)

    #define   GET32vsipll_ctrl_PDDP1(r32)                      _BFGET_(r32,28,28)
    #define   SET32vsipll_ctrl_PDDP1(r32,v)                    _BFSET_(r32,28,28,v)
    #define   GET16vsipll_ctrl_PDDP1(r16)                      _BFGET_(r16,12,12)
    #define   SET16vsipll_ctrl_PDDP1(r16,v)                    _BFSET_(r16,12,12,v)

    #define   GET32vsipll_ctrl_DP1(r32)                        _BFGET_(r32,31,29)
    #define   SET32vsipll_ctrl_DP1(r32,v)                      _BFSET_(r32,31,29,v)
    #define   GET16vsipll_ctrl_DP1(r16)                        _BFGET_(r16,15,13)
    #define   SET16vsipll_ctrl_DP1(r16,v)                      _BFSET_(r16,15,13,v)

    #define     w32vsipll_ctrl3                                {\
            UNSG32 uctrl_SLOPE                                 : 24;\
            UNSG32 uctrl_PDDP                                  :  1;\
            UNSG32 uctrl_DP                                    :  3;\
            UNSG32 uctrl_PDDP1                                 :  1;\
            UNSG32 uctrl_DP1                                   :  3;\
          }
    union { UNSG32 u32vsipll_ctrl3;
            struct w32vsipll_ctrl3;
          };
    #define   GET32vsipll_ctrl_BYPASS(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32vsipll_ctrl_BYPASS(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_ctrl_BYPASS(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16vsipll_ctrl_BYPASS(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32vsipll_ctrl4                                {\
            UNSG32 uctrl_BYPASS                                :  1;\
            UNSG32 RSVDx10_b1                                  : 31;\
          }
    union { UNSG32 u32vsipll_ctrl4;
            struct w32vsipll_ctrl4;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32vsipll_status_LOCK(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32vsipll_status_LOCK(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16vsipll_status_LOCK(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16vsipll_status_LOCK(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define     w32vsipll_status                               {\
            UNSG32 ustatus_LOCK                                :  1;\
            UNSG32 RSVDx14_b1                                  : 31;\
          }
    union { UNSG32 u32vsipll_status;
            struct w32vsipll_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_vsipll;

    typedef union  T32vsipll_ctrl
          { UNSG32 u32;
            struct w32vsipll_ctrl;
                 } T32vsipll_ctrl;
    typedef union  T32vsipll_ctrl1
          { UNSG32 u32;
            struct w32vsipll_ctrl1;
                 } T32vsipll_ctrl1;
    typedef union  T32vsipll_ctrl2
          { UNSG32 u32;
            struct w32vsipll_ctrl2;
                 } T32vsipll_ctrl2;
    typedef union  T32vsipll_ctrl3
          { UNSG32 u32;
            struct w32vsipll_ctrl3;
                 } T32vsipll_ctrl3;
    typedef union  T32vsipll_ctrl4
          { UNSG32 u32;
            struct w32vsipll_ctrl4;
                 } T32vsipll_ctrl4;
    typedef union  T32vsipll_status
          { UNSG32 u32;
            struct w32vsipll_status;
                 } T32vsipll_status;
    ///////////////////////////////////////////////////////////

    typedef union  Tvsipll_ctrl
          { UNSG32 u32[5];
            struct {
            struct w32vsipll_ctrl;
            struct w32vsipll_ctrl1;
            struct w32vsipll_ctrl2;
            struct w32vsipll_ctrl3;
            struct w32vsipll_ctrl4;
                   };
                 } Tvsipll_ctrl;
    typedef union  Tvsipll_status
          { UNSG32 u32[1];
            struct {
            struct w32vsipll_status;
                   };
                 } Tvsipll_status;

    ///////////////////////////////////////////////////////////
     SIGN32 vsipll_drvrd(SIE_vsipll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 vsipll_drvwr(SIE_vsipll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void vsipll_reset(SIE_vsipll *p);
     SIGN32 vsipll_cmp  (SIE_vsipll *p, SIE_vsipll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define vsipll_check(p,pie,pfx,hLOG) vsipll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define vsipll_print(p,    pfx,hLOG) vsipll_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: vsipll
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOff                                   (4,4)
///     ###
///     * Register for the Power domain which is OFF by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x0
///                                    : PWROFF                    0x0
///                                    : PWRON                     0x3
///                                                 ###
///                                                 * Power Switch control
///                                                 * Bit 1 : SLP1B
///                                                 * Bit 0 : SLP2B
///                                                 * SLP1B SLP2B
///                                                 * 0               X               Switch is turned off
///                                                 * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                                 * 1               1               PMOS switch is fully turned on to reduce Ron
///                                                 ###
///               %unsigned 1  pwrDomainRstN             0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Power Domain Reset. Active low.
///                                                 * 0 : Reset the power domain
///                                                 * 1:   De-assert the reset for the power domain
///                                                 ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOff
#define h_pwrOff (){}

    #define     RA_pwrOff_ctrl                                 0x0000

    #define     BA_pwrOff_ctrl_iso_eN                          0x0000
    #define     B16pwrOff_ctrl_iso_eN                          0x0000
    #define   LSb32pwrOff_ctrl_iso_eN                             0
    #define   LSb16pwrOff_ctrl_iso_eN                             0
    #define       bpwrOff_ctrl_iso_eN                          1
    #define   MSK32pwrOff_ctrl_iso_eN                             0x00000001
    #define        pwrOff_ctrl_iso_eN_enable                                0x0
    #define        pwrOff_ctrl_iso_eN_disable                               0x1

    #define     BA_pwrOff_ctrl_pwrSwitchCtrl                   0x0000
    #define     B16pwrOff_ctrl_pwrSwitchCtrl                   0x0000
    #define   LSb32pwrOff_ctrl_pwrSwitchCtrl                      1
    #define   LSb16pwrOff_ctrl_pwrSwitchCtrl                      1
    #define       bpwrOff_ctrl_pwrSwitchCtrl                   2
    #define   MSK32pwrOff_ctrl_pwrSwitchCtrl                      0x00000006
    #define        pwrOff_ctrl_pwrSwitchCtrl_PWROFF                         0x0
    #define        pwrOff_ctrl_pwrSwitchCtrl_PWRON                          0x3

    #define     BA_pwrOff_ctrl_pwrDomainRstN                   0x0000
    #define     B16pwrOff_ctrl_pwrDomainRstN                   0x0000
    #define   LSb32pwrOff_ctrl_pwrDomainRstN                      3
    #define   LSb16pwrOff_ctrl_pwrDomainRstN                      3
    #define       bpwrOff_ctrl_pwrDomainRstN                   1
    #define   MSK32pwrOff_ctrl_pwrDomainRstN                      0x00000008
    #define        pwrOff_ctrl_pwrDomainRstN_enable                         0x0
    #define        pwrOff_ctrl_pwrDomainRstN_disable                        0x1
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOff_status                               0x0004

    #define     BA_pwrOff_status_pwrStatus                     0x0004
    #define     B16pwrOff_status_pwrStatus                     0x0004
    #define   LSb32pwrOff_status_pwrStatus                        0
    #define   LSb16pwrOff_status_pwrStatus                        0
    #define       bpwrOff_status_pwrStatus                     2
    #define   MSK32pwrOff_status_pwrStatus                        0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOff {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOff_ctrl_iso_eN(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32pwrOff_ctrl_iso_eN(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOff_ctrl_iso_eN(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16pwrOff_ctrl_iso_eN(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOff_ctrl_pwrSwitchCtrl(r32)              _BFGET_(r32, 2, 1)
    #define   SET32pwrOff_ctrl_pwrSwitchCtrl(r32,v)            _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOff_ctrl_pwrSwitchCtrl(r16)              _BFGET_(r16, 2, 1)
    #define   SET16pwrOff_ctrl_pwrSwitchCtrl(r16,v)            _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOff_ctrl_pwrDomainRstN(r32)              _BFGET_(r32, 3, 3)
    #define   SET32pwrOff_ctrl_pwrDomainRstN(r32,v)            _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOff_ctrl_pwrDomainRstN(r16)              _BFGET_(r16, 3, 3)
    #define   SET16pwrOff_ctrl_pwrDomainRstN(r16,v)            _BFSET_(r16, 3, 3,v)

    #define     w32pwrOff_ctrl                                 {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOff_ctrl;
            struct w32pwrOff_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOff_status_pwrStatus(r32)                _BFGET_(r32, 1, 0)
    #define   SET32pwrOff_status_pwrStatus(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOff_status_pwrStatus(r16)                _BFGET_(r16, 1, 0)
    #define   SET16pwrOff_status_pwrStatus(r16,v)              _BFSET_(r16, 1, 0,v)

    #define     w32pwrOff_status                               {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32pwrOff_status;
            struct w32pwrOff_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOff;

    typedef union  T32pwrOff_ctrl
          { UNSG32 u32;
            struct w32pwrOff_ctrl;
                 } T32pwrOff_ctrl;
    typedef union  T32pwrOff_status
          { UNSG32 u32;
            struct w32pwrOff_status;
                 } T32pwrOff_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOff_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOff_ctrl;
                   };
                 } TpwrOff_ctrl;
    typedef union  TpwrOff_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOff_status;
                   };
                 } TpwrOff_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOff_drvrd(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOff_drvwr(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOff_reset(SIE_pwrOff *p);
     SIGN32 pwrOff_cmp  (SIE_pwrOff *p, SIE_pwrOff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOff_check(p,pie,pfx,hLOG) pwrOff_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOff_print(p,    pfx,hLOG) pwrOff_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOff
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOn                                    (4,4)
///     ###
///     * Register for the Power domain which is ON by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x1
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x3
///                                    ###
///                                    * Power Switch control
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  pwrDomainRstN             0x1
///                                    ###
///                                    * Power Domain Reset. Active low.
///                                    * 0 : Reset the power domain
///                                    * 1:   De-assert the reset for the power domain
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       6b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn
#define h_pwrOn (){}

    #define     RA_pwrOn_ctrl                                  0x0000

    #define     BA_pwrOn_ctrl_iso_eN                           0x0000
    #define     B16pwrOn_ctrl_iso_eN                           0x0000
    #define   LSb32pwrOn_ctrl_iso_eN                              0
    #define   LSb16pwrOn_ctrl_iso_eN                              0
    #define       bpwrOn_ctrl_iso_eN                           1
    #define   MSK32pwrOn_ctrl_iso_eN                              0x00000001
    #define        pwrOn_ctrl_iso_eN_enable                                 0x0
    #define        pwrOn_ctrl_iso_eN_disable                                0x1

    #define     BA_pwrOn_ctrl_pwrSwitchCtrl                    0x0000
    #define     B16pwrOn_ctrl_pwrSwitchCtrl                    0x0000
    #define   LSb32pwrOn_ctrl_pwrSwitchCtrl                       1
    #define   LSb16pwrOn_ctrl_pwrSwitchCtrl                       1
    #define       bpwrOn_ctrl_pwrSwitchCtrl                    2
    #define   MSK32pwrOn_ctrl_pwrSwitchCtrl                       0x00000006

    #define     BA_pwrOn_ctrl_pwrDomainRstN                    0x0000
    #define     B16pwrOn_ctrl_pwrDomainRstN                    0x0000
    #define   LSb32pwrOn_ctrl_pwrDomainRstN                       3
    #define   LSb16pwrOn_ctrl_pwrDomainRstN                       3
    #define       bpwrOn_ctrl_pwrDomainRstN                    1
    #define   MSK32pwrOn_ctrl_pwrDomainRstN                       0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOn_status                                0x0004

    #define     BA_pwrOn_status_pwrStatus                      0x0004
    #define     B16pwrOn_status_pwrStatus                      0x0004
    #define   LSb32pwrOn_status_pwrStatus                         0
    #define   LSb16pwrOn_status_pwrStatus                         0
    #define       bpwrOn_status_pwrStatus                      2
    #define   MSK32pwrOn_status_pwrStatus                         0x00000003
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOn {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_ctrl_iso_eN(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32pwrOn_ctrl_iso_eN(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOn_ctrl_iso_eN(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16pwrOn_ctrl_iso_eN(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOn_ctrl_pwrSwitchCtrl(r32)               _BFGET_(r32, 2, 1)
    #define   SET32pwrOn_ctrl_pwrSwitchCtrl(r32,v)             _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOn_ctrl_pwrSwitchCtrl(r16)               _BFGET_(r16, 2, 1)
    #define   SET16pwrOn_ctrl_pwrSwitchCtrl(r16,v)             _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOn_ctrl_pwrDomainRstN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32pwrOn_ctrl_pwrDomainRstN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOn_ctrl_pwrDomainRstN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16pwrOn_ctrl_pwrDomainRstN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define     w32pwrOn_ctrl                                  {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOn_ctrl;
            struct w32pwrOn_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_status_pwrStatus(r32)                 _BFGET_(r32, 1, 0)
    #define   SET32pwrOn_status_pwrStatus(r32,v)               _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOn_status_pwrStatus(r16)                 _BFGET_(r16, 1, 0)
    #define   SET16pwrOn_status_pwrStatus(r16,v)               _BFSET_(r16, 1, 0,v)

    #define     w32pwrOn_status                                {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32pwrOn_status;
            struct w32pwrOn_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOn;

    typedef union  T32pwrOn_ctrl
          { UNSG32 u32;
            struct w32pwrOn_ctrl;
                 } T32pwrOn_ctrl;
    typedef union  T32pwrOn_status
          { UNSG32 u32;
            struct w32pwrOn_status;
                 } T32pwrOn_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOn_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_ctrl;
                   };
                 } TpwrOn_ctrl;
    typedef union  TpwrOn_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_status;
                   };
                 } TpwrOn_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOn_drvrd(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOn_drvwr(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOn_reset(SIE_pwrOn *p);
     SIGN32 pwrOn_cmp  (SIE_pwrOn *p, SIE_pwrOn *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOn_check(p,pie,pfx,hLOG) pwrOn_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOn_print(p,    pfx,hLOG) pwrOn_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOn
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pwrOn_iso                                (4,4)
///     ###
///     * Register for the Power domain which is ON by default
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Power Domain Control Register
///               ###
///               %unsigned 1  iso_eN                    0x0
///                                    : enable                    0x0
///                                    : disable                   0x1
///                                                 ###
///                                                 * Isolation control bit. Active low
///                                                 * 0 : Isolation is enabled
///                                                 * 1 : Isolation is disabled (default)
///                                                 ###
///               %unsigned 2  pwrSwitchCtrl             0x3
///                                    ###
///                                    * Power Switch control
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  pwrDomainRstN             0x0
///                                    ###
///                                    * Power Domain Reset. Active low.
///                                    * 0 : Reset the power domain
///                                    * 1:   De-assert the reset for the power domain
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00004 status               (R-)
///               %unsigned 2  pwrStatus                 
///                                    ###
///                                    * Power domain Status output from the power domain module
///                                    * Bit 1 : SLP1B
///                                    * Bit 0 : SLP2B
///                                    * SLP1B SLP2B
///                                    * 0               X               Switch is turned off
///                                    * 1               0               PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
///                                    * 1               1               PMOS switch is fully turned on to reduce Ron
///                                    ###
///               %unsigned 1  IP_IDLE                   
///                                    ###
///                                    * Indication from IP that it is idle and can be powered down.
///                                    * 1: Idle
///                                    * 0: Busy
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:       7b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn_iso
#define h_pwrOn_iso (){}

    #define     RA_pwrOn_iso_ctrl                              0x0000

    #define     BA_pwrOn_iso_ctrl_iso_eN                       0x0000
    #define     B16pwrOn_iso_ctrl_iso_eN                       0x0000
    #define   LSb32pwrOn_iso_ctrl_iso_eN                          0
    #define   LSb16pwrOn_iso_ctrl_iso_eN                          0
    #define       bpwrOn_iso_ctrl_iso_eN                       1
    #define   MSK32pwrOn_iso_ctrl_iso_eN                          0x00000001
    #define        pwrOn_iso_ctrl_iso_eN_enable                             0x0
    #define        pwrOn_iso_ctrl_iso_eN_disable                            0x1

    #define     BA_pwrOn_iso_ctrl_pwrSwitchCtrl                0x0000
    #define     B16pwrOn_iso_ctrl_pwrSwitchCtrl                0x0000
    #define   LSb32pwrOn_iso_ctrl_pwrSwitchCtrl                   1
    #define   LSb16pwrOn_iso_ctrl_pwrSwitchCtrl                   1
    #define       bpwrOn_iso_ctrl_pwrSwitchCtrl                2
    #define   MSK32pwrOn_iso_ctrl_pwrSwitchCtrl                   0x00000006

    #define     BA_pwrOn_iso_ctrl_pwrDomainRstN                0x0000
    #define     B16pwrOn_iso_ctrl_pwrDomainRstN                0x0000
    #define   LSb32pwrOn_iso_ctrl_pwrDomainRstN                   3
    #define   LSb16pwrOn_iso_ctrl_pwrDomainRstN                   3
    #define       bpwrOn_iso_ctrl_pwrDomainRstN                1
    #define   MSK32pwrOn_iso_ctrl_pwrDomainRstN                   0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_pwrOn_iso_status                            0x0004

    #define     BA_pwrOn_iso_status_pwrStatus                  0x0004
    #define     B16pwrOn_iso_status_pwrStatus                  0x0004
    #define   LSb32pwrOn_iso_status_pwrStatus                     0
    #define   LSb16pwrOn_iso_status_pwrStatus                     0
    #define       bpwrOn_iso_status_pwrStatus                  2
    #define   MSK32pwrOn_iso_status_pwrStatus                     0x00000003

    #define     BA_pwrOn_iso_status_IP_IDLE                    0x0004
    #define     B16pwrOn_iso_status_IP_IDLE                    0x0004
    #define   LSb32pwrOn_iso_status_IP_IDLE                       2
    #define   LSb16pwrOn_iso_status_IP_IDLE                       2
    #define       bpwrOn_iso_status_IP_IDLE                    1
    #define   MSK32pwrOn_iso_status_IP_IDLE                       0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pwrOn_iso {
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_iso_ctrl_iso_eN(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32pwrOn_iso_ctrl_iso_eN(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16pwrOn_iso_ctrl_iso_eN(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16pwrOn_iso_ctrl_iso_eN(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32pwrOn_iso_ctrl_pwrSwitchCtrl(r32)           _BFGET_(r32, 2, 1)
    #define   SET32pwrOn_iso_ctrl_pwrSwitchCtrl(r32,v)         _BFSET_(r32, 2, 1,v)
    #define   GET16pwrOn_iso_ctrl_pwrSwitchCtrl(r16)           _BFGET_(r16, 2, 1)
    #define   SET16pwrOn_iso_ctrl_pwrSwitchCtrl(r16,v)         _BFSET_(r16, 2, 1,v)

    #define   GET32pwrOn_iso_ctrl_pwrDomainRstN(r32)           _BFGET_(r32, 3, 3)
    #define   SET32pwrOn_iso_ctrl_pwrDomainRstN(r32,v)         _BFSET_(r32, 3, 3,v)
    #define   GET16pwrOn_iso_ctrl_pwrDomainRstN(r16)           _BFGET_(r16, 3, 3)
    #define   SET16pwrOn_iso_ctrl_pwrDomainRstN(r16,v)         _BFSET_(r16, 3, 3,v)

    #define     w32pwrOn_iso_ctrl                              {\
            UNSG32 uctrl_iso_eN                                :  1;\
            UNSG32 uctrl_pwrSwitchCtrl                         :  2;\
            UNSG32 uctrl_pwrDomainRstN                         :  1;\
            UNSG32 RSVDx0_b4                                   : 28;\
          }
    union { UNSG32 u32pwrOn_iso_ctrl;
            struct w32pwrOn_iso_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pwrOn_iso_status_pwrStatus(r32)             _BFGET_(r32, 1, 0)
    #define   SET32pwrOn_iso_status_pwrStatus(r32,v)           _BFSET_(r32, 1, 0,v)
    #define   GET16pwrOn_iso_status_pwrStatus(r16)             _BFGET_(r16, 1, 0)
    #define   SET16pwrOn_iso_status_pwrStatus(r16,v)           _BFSET_(r16, 1, 0,v)

    #define   GET32pwrOn_iso_status_IP_IDLE(r32)               _BFGET_(r32, 2, 2)
    #define   SET32pwrOn_iso_status_IP_IDLE(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16pwrOn_iso_status_IP_IDLE(r16)               _BFGET_(r16, 2, 2)
    #define   SET16pwrOn_iso_status_IP_IDLE(r16,v)             _BFSET_(r16, 2, 2,v)

    #define     w32pwrOn_iso_status                            {\
            UNSG32 ustatus_pwrStatus                           :  2;\
            UNSG32 ustatus_IP_IDLE                             :  1;\
            UNSG32 RSVDx4_b3                                   : 29;\
          }
    union { UNSG32 u32pwrOn_iso_status;
            struct w32pwrOn_iso_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pwrOn_iso;

    typedef union  T32pwrOn_iso_ctrl
          { UNSG32 u32;
            struct w32pwrOn_iso_ctrl;
                 } T32pwrOn_iso_ctrl;
    typedef union  T32pwrOn_iso_status
          { UNSG32 u32;
            struct w32pwrOn_iso_status;
                 } T32pwrOn_iso_status;
    ///////////////////////////////////////////////////////////

    typedef union  TpwrOn_iso_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_iso_ctrl;
                   };
                 } TpwrOn_iso_ctrl;
    typedef union  TpwrOn_iso_status
          { UNSG32 u32[1];
            struct {
            struct w32pwrOn_iso_status;
                   };
                 } TpwrOn_iso_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pwrOn_iso_drvrd(SIE_pwrOn_iso *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pwrOn_iso_drvwr(SIE_pwrOn_iso *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pwrOn_iso_reset(SIE_pwrOn_iso *p);
     SIGN32 pwrOn_iso_cmp  (SIE_pwrOn_iso *p, SIE_pwrOn_iso *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pwrOn_iso_check(p,pie,pfx,hLOG) pwrOn_iso_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pwrOn_iso_print(p,    pfx,hLOG) pwrOn_iso_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pwrOn_iso
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE clkD1                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Control register
///               ###
///               %unsigned 1  ClkEn                     0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Clock enable register
///                                                 * 0: Disable
///                                                 * 1: Enable   (default)
///                                                 ###
///               %unsigned 3  ClkPllSel                 0x4
///                                    : APLL0_CLKO1               0x0
///                                    : APLL1_CLKO1               0x1
///                                    : MEMPLL_CLKO1              0x2
///                                    : CPUPLL_CLKO1              0x3
///                                    : SYSPLL_CLKO1              0x4
///                                                 ###
///                                                 * Clock source selection
///                                                 * 0: AVPLLB4 – AVPLL Channel 2
///                                                 * 1: AVPLLB5 – AVPLL Channel 5
///                                                 * 2: AVPLLB6 – AVPLL Channel 6
///                                                 * 3: AVPLLB7 - MEMPLL
///                                                 * 4: SYSPLL - SYSPLL DIV3 (default)
///                                                 * 5-7: Reserved
///                                                 ###
///               %unsigned 1  ClkPllSwitch              0x0
///                                    : SYSPLL                    0x0
///                                    : AVPLL                     0x1
///                                                 ###
///                                                 * Switch to select between SYSPLL or AVPLL as a clock source
///                                                 * 0: SYSPLL (default)
///                                                 * 1: AVPLL (selected output of ClkPllSel mux)
///                                                 ###
///               %unsigned 1  ClkSwitch                 0x0
///                                    : SrcClk                    0x0
///                                    : DivClk                    0x1
///                                                 ###
///                                                 * Clock divider switch select
///                                                 * 0:   No divider (default) for Divide by 1
///                                                 * 1:   Use Divider
///                                                 ###
///               %unsigned 1  ClkD3Switch               0x0
///                                    : NonDiv3Clk                0x0
///                                    : Div3Clk                   0x1
///                                                 ###
///                                                 * Divide by 3 clock switch
///                                                 * 0: No Divide by 3 (default)
///                                                 * 1: Use Divide by 3
///                                                 ###
///               %unsigned 3  ClkSel                    0x1
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///                                                 ###
///                                                 * Clock divider Selection
///                                                 * 0: Reserved
///                                                 * 1: Divide by 2 ( default)
///                                                 * 2: Divide by 4
///                                                 * 3: Divide by 6
///                                                 * 4: Divide by 8
///                                                 * 5: Divide by 12
///                                                 * 6-7: Reserved
///                                                 * Note: Not used for Divide by 1
///                                                 ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_clkD1
#define h_clkD1 (){}

    #define     RA_clkD1_ctrl                                  0x0000

    #define     BA_clkD1_ctrl_ClkEn                            0x0000
    #define     B16clkD1_ctrl_ClkEn                            0x0000
    #define   LSb32clkD1_ctrl_ClkEn                               0
    #define   LSb16clkD1_ctrl_ClkEn                               0
    #define       bclkD1_ctrl_ClkEn                            1
    #define   MSK32clkD1_ctrl_ClkEn                               0x00000001
    #define        clkD1_ctrl_ClkEn_enable                                  0x1
    #define        clkD1_ctrl_ClkEn_disable                                 0x0

    #define     BA_clkD1_ctrl_ClkPllSel                        0x0000
    #define     B16clkD1_ctrl_ClkPllSel                        0x0000
    #define   LSb32clkD1_ctrl_ClkPllSel                           1
    #define   LSb16clkD1_ctrl_ClkPllSel                           1
    #define       bclkD1_ctrl_ClkPllSel                        3
    #define   MSK32clkD1_ctrl_ClkPllSel                           0x0000000E
    #define        clkD1_ctrl_ClkPllSel_APLL0_CLKO1                         0x0
    #define        clkD1_ctrl_ClkPllSel_APLL1_CLKO1                         0x1
    #define        clkD1_ctrl_ClkPllSel_MEMPLL_CLKO1                        0x2
    #define        clkD1_ctrl_ClkPllSel_CPUPLL_CLKO1                        0x3
    #define        clkD1_ctrl_ClkPllSel_SYSPLL_CLKO1                        0x4

    #define     BA_clkD1_ctrl_ClkPllSwitch                     0x0000
    #define     B16clkD1_ctrl_ClkPllSwitch                     0x0000
    #define   LSb32clkD1_ctrl_ClkPllSwitch                        4
    #define   LSb16clkD1_ctrl_ClkPllSwitch                        4
    #define       bclkD1_ctrl_ClkPllSwitch                     1
    #define   MSK32clkD1_ctrl_ClkPllSwitch                        0x00000010
    #define        clkD1_ctrl_ClkPllSwitch_SYSPLL                           0x0
    #define        clkD1_ctrl_ClkPllSwitch_AVPLL                            0x1

    #define     BA_clkD1_ctrl_ClkSwitch                        0x0000
    #define     B16clkD1_ctrl_ClkSwitch                        0x0000
    #define   LSb32clkD1_ctrl_ClkSwitch                           5
    #define   LSb16clkD1_ctrl_ClkSwitch                           5
    #define       bclkD1_ctrl_ClkSwitch                        1
    #define   MSK32clkD1_ctrl_ClkSwitch                           0x00000020
    #define        clkD1_ctrl_ClkSwitch_SrcClk                              0x0
    #define        clkD1_ctrl_ClkSwitch_DivClk                              0x1

    #define     BA_clkD1_ctrl_ClkD3Switch                      0x0000
    #define     B16clkD1_ctrl_ClkD3Switch                      0x0000
    #define   LSb32clkD1_ctrl_ClkD3Switch                         6
    #define   LSb16clkD1_ctrl_ClkD3Switch                         6
    #define       bclkD1_ctrl_ClkD3Switch                      1
    #define   MSK32clkD1_ctrl_ClkD3Switch                         0x00000040
    #define        clkD1_ctrl_ClkD3Switch_NonDiv3Clk                        0x0
    #define        clkD1_ctrl_ClkD3Switch_Div3Clk                           0x1

    #define     BA_clkD1_ctrl_ClkSel                           0x0000
    #define     B16clkD1_ctrl_ClkSel                           0x0000
    #define   LSb32clkD1_ctrl_ClkSel                              7
    #define   LSb16clkD1_ctrl_ClkSel                              7
    #define       bclkD1_ctrl_ClkSel                           3
    #define   MSK32clkD1_ctrl_ClkSel                              0x00000380
    #define        clkD1_ctrl_ClkSel_d2                                     0x1
    #define        clkD1_ctrl_ClkSel_d4                                     0x2
    #define        clkD1_ctrl_ClkSel_d6                                     0x3
    #define        clkD1_ctrl_ClkSel_d8                                     0x4
    #define        clkD1_ctrl_ClkSel_d12                                    0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_clkD1 {
    ///////////////////////////////////////////////////////////
    #define   GET32clkD1_ctrl_ClkEn(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32clkD1_ctrl_ClkEn(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16clkD1_ctrl_ClkEn(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16clkD1_ctrl_ClkEn(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32clkD1_ctrl_ClkPllSel(r32)                   _BFGET_(r32, 3, 1)
    #define   SET32clkD1_ctrl_ClkPllSel(r32,v)                 _BFSET_(r32, 3, 1,v)
    #define   GET16clkD1_ctrl_ClkPllSel(r16)                   _BFGET_(r16, 3, 1)
    #define   SET16clkD1_ctrl_ClkPllSel(r16,v)                 _BFSET_(r16, 3, 1,v)

    #define   GET32clkD1_ctrl_ClkPllSwitch(r32)                _BFGET_(r32, 4, 4)
    #define   SET32clkD1_ctrl_ClkPllSwitch(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16clkD1_ctrl_ClkPllSwitch(r16)                _BFGET_(r16, 4, 4)
    #define   SET16clkD1_ctrl_ClkPllSwitch(r16,v)              _BFSET_(r16, 4, 4,v)

    #define   GET32clkD1_ctrl_ClkSwitch(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32clkD1_ctrl_ClkSwitch(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16clkD1_ctrl_ClkSwitch(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16clkD1_ctrl_ClkSwitch(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32clkD1_ctrl_ClkD3Switch(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32clkD1_ctrl_ClkD3Switch(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16clkD1_ctrl_ClkD3Switch(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16clkD1_ctrl_ClkD3Switch(r16,v)               _BFSET_(r16, 6, 6,v)

    #define   GET32clkD1_ctrl_ClkSel(r32)                      _BFGET_(r32, 9, 7)
    #define   SET32clkD1_ctrl_ClkSel(r32,v)                    _BFSET_(r32, 9, 7,v)
    #define   GET16clkD1_ctrl_ClkSel(r16)                      _BFGET_(r16, 9, 7)
    #define   SET16clkD1_ctrl_ClkSel(r16,v)                    _BFSET_(r16, 9, 7,v)

    #define     w32clkD1_ctrl                                  {\
            UNSG32 uctrl_ClkEn                                 :  1;\
            UNSG32 uctrl_ClkPllSel                             :  3;\
            UNSG32 uctrl_ClkPllSwitch                          :  1;\
            UNSG32 uctrl_ClkSwitch                             :  1;\
            UNSG32 uctrl_ClkD3Switch                           :  1;\
            UNSG32 uctrl_ClkSel                                :  3;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32clkD1_ctrl;
            struct w32clkD1_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_clkD1;

    typedef union  T32clkD1_ctrl
          { UNSG32 u32;
            struct w32clkD1_ctrl;
                 } T32clkD1_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TclkD1_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32clkD1_ctrl;
                   };
                 } TclkD1_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 clkD1_drvrd(SIE_clkD1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 clkD1_drvwr(SIE_clkD1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void clkD1_reset(SIE_clkD1 *p);
     SIGN32 clkD1_cmp  (SIE_clkD1 *p, SIE_clkD1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define clkD1_check(p,pie,pfx,hLOG) clkD1_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define clkD1_print(p,    pfx,hLOG) clkD1_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: clkD1
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE clkD2                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Control register
///               ###
///               %unsigned 1  ClkEn                     0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Clock enable register
///                                                 * 0: Disable
///                                                 * 1: Enable   (default)
///                                                 ###
///               %unsigned 3  ClkPllSel                 0x4
///                                    : APLL0_CLKO1               0x0
///                                    : APLL1_CLKO1               0x1
///                                    : MEMPLL_CLKO1              0x2
///                                    : CPUPLL_CLKO1              0x3
///                                    : SYSPLL_CLKO1              0x4
///                                                 ###
///                                                 * Clock source selection
///                                                 * 0: AVPLLB4 – AVPLL Channel 2
///                                                 * 1: AVPLLB5 – AVPLL Channel 5
///                                                 * 2: AVPLLB6 – AVPLL Channel 6
///                                                 * 3: AVPLLB7 - MEMPLL
///                                                 * 4: SYSPLL - SYSPLL DIV3 (default)
///                                                 * 5-7: Reserved
///                                                 ###
///               %unsigned 1  ClkPllSwitch              0x0
///                                    : SYSPLL                    0x0
///                                    : AVPLL                     0x1
///                                                 ###
///                                                 * Switch to select between SYSPLL or AVPLL as a clock source
///                                                 * 0: SYSPLL (default)
///                                                 * 1: AVPLL (selected output of ClkPllSel mux)
///                                                 ###
///               %unsigned 1  ClkSwitch                 0x1
///                                    : SrcClk                    0x0
///                                    : DivClk                    0x1
///                                                 ###
///                                                 * Clock divider switch select
///                                                 * 0:   No divider
///                                                 * 1:   Use Divider (default)
///                                                 ###
///               %unsigned 1  ClkD3Switch               0x0
///                                    : NonDiv3Clk                0x0
///                                    : Div3Clk                   0x1
///                                                 ###
///                                                 * Divide by 3 clock switch
///                                                 * 0: No Divide by 3 (default)
///                                                 * 1: Use Divide by 3
///                                                 ###
///               %unsigned 3  ClkSel                    0x1
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///                                                 ###
///                                                 * Clock divider Selection
///                                                 * 0: Reserved
///                                                 * 1: Divide by 2 ( default)
///                                                 * 2: Divide by 4
///                                                 * 3: Divide by 6
///                                                 * 4: Divide by 8
///                                                 * 5: Divide by 12
///                                                 * 6-7: Reserved
///                                                 ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_clkD2
#define h_clkD2 (){}

    #define     RA_clkD2_ctrl                                  0x0000

    #define     BA_clkD2_ctrl_ClkEn                            0x0000
    #define     B16clkD2_ctrl_ClkEn                            0x0000
    #define   LSb32clkD2_ctrl_ClkEn                               0
    #define   LSb16clkD2_ctrl_ClkEn                               0
    #define       bclkD2_ctrl_ClkEn                            1
    #define   MSK32clkD2_ctrl_ClkEn                               0x00000001
    #define        clkD2_ctrl_ClkEn_enable                                  0x1
    #define        clkD2_ctrl_ClkEn_disable                                 0x0

    #define     BA_clkD2_ctrl_ClkPllSel                        0x0000
    #define     B16clkD2_ctrl_ClkPllSel                        0x0000
    #define   LSb32clkD2_ctrl_ClkPllSel                           1
    #define   LSb16clkD2_ctrl_ClkPllSel                           1
    #define       bclkD2_ctrl_ClkPllSel                        3
    #define   MSK32clkD2_ctrl_ClkPllSel                           0x0000000E
    #define        clkD2_ctrl_ClkPllSel_APLL0_CLKO1                         0x0
    #define        clkD2_ctrl_ClkPllSel_APLL1_CLKO1                         0x1
    #define        clkD2_ctrl_ClkPllSel_MEMPLL_CLKO1                        0x2
    #define        clkD2_ctrl_ClkPllSel_CPUPLL_CLKO1                        0x3
    #define        clkD2_ctrl_ClkPllSel_SYSPLL_CLKO1                        0x4

    #define     BA_clkD2_ctrl_ClkPllSwitch                     0x0000
    #define     B16clkD2_ctrl_ClkPllSwitch                     0x0000
    #define   LSb32clkD2_ctrl_ClkPllSwitch                        4
    #define   LSb16clkD2_ctrl_ClkPllSwitch                        4
    #define       bclkD2_ctrl_ClkPllSwitch                     1
    #define   MSK32clkD2_ctrl_ClkPllSwitch                        0x00000010
    #define        clkD2_ctrl_ClkPllSwitch_SYSPLL                           0x0
    #define        clkD2_ctrl_ClkPllSwitch_AVPLL                            0x1

    #define     BA_clkD2_ctrl_ClkSwitch                        0x0000
    #define     B16clkD2_ctrl_ClkSwitch                        0x0000
    #define   LSb32clkD2_ctrl_ClkSwitch                           5
    #define   LSb16clkD2_ctrl_ClkSwitch                           5
    #define       bclkD2_ctrl_ClkSwitch                        1
    #define   MSK32clkD2_ctrl_ClkSwitch                           0x00000020
    #define        clkD2_ctrl_ClkSwitch_SrcClk                              0x0
    #define        clkD2_ctrl_ClkSwitch_DivClk                              0x1

    #define     BA_clkD2_ctrl_ClkD3Switch                      0x0000
    #define     B16clkD2_ctrl_ClkD3Switch                      0x0000
    #define   LSb32clkD2_ctrl_ClkD3Switch                         6
    #define   LSb16clkD2_ctrl_ClkD3Switch                         6
    #define       bclkD2_ctrl_ClkD3Switch                      1
    #define   MSK32clkD2_ctrl_ClkD3Switch                         0x00000040
    #define        clkD2_ctrl_ClkD3Switch_NonDiv3Clk                        0x0
    #define        clkD2_ctrl_ClkD3Switch_Div3Clk                           0x1

    #define     BA_clkD2_ctrl_ClkSel                           0x0000
    #define     B16clkD2_ctrl_ClkSel                           0x0000
    #define   LSb32clkD2_ctrl_ClkSel                              7
    #define   LSb16clkD2_ctrl_ClkSel                              7
    #define       bclkD2_ctrl_ClkSel                           3
    #define   MSK32clkD2_ctrl_ClkSel                              0x00000380
    #define        clkD2_ctrl_ClkSel_d2                                     0x1
    #define        clkD2_ctrl_ClkSel_d4                                     0x2
    #define        clkD2_ctrl_ClkSel_d6                                     0x3
    #define        clkD2_ctrl_ClkSel_d8                                     0x4
    #define        clkD2_ctrl_ClkSel_d12                                    0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_clkD2 {
    ///////////////////////////////////////////////////////////
    #define   GET32clkD2_ctrl_ClkEn(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32clkD2_ctrl_ClkEn(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16clkD2_ctrl_ClkEn(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16clkD2_ctrl_ClkEn(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32clkD2_ctrl_ClkPllSel(r32)                   _BFGET_(r32, 3, 1)
    #define   SET32clkD2_ctrl_ClkPllSel(r32,v)                 _BFSET_(r32, 3, 1,v)
    #define   GET16clkD2_ctrl_ClkPllSel(r16)                   _BFGET_(r16, 3, 1)
    #define   SET16clkD2_ctrl_ClkPllSel(r16,v)                 _BFSET_(r16, 3, 1,v)

    #define   GET32clkD2_ctrl_ClkPllSwitch(r32)                _BFGET_(r32, 4, 4)
    #define   SET32clkD2_ctrl_ClkPllSwitch(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16clkD2_ctrl_ClkPllSwitch(r16)                _BFGET_(r16, 4, 4)
    #define   SET16clkD2_ctrl_ClkPllSwitch(r16,v)              _BFSET_(r16, 4, 4,v)

    #define   GET32clkD2_ctrl_ClkSwitch(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32clkD2_ctrl_ClkSwitch(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16clkD2_ctrl_ClkSwitch(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16clkD2_ctrl_ClkSwitch(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32clkD2_ctrl_ClkD3Switch(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32clkD2_ctrl_ClkD3Switch(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16clkD2_ctrl_ClkD3Switch(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16clkD2_ctrl_ClkD3Switch(r16,v)               _BFSET_(r16, 6, 6,v)

    #define   GET32clkD2_ctrl_ClkSel(r32)                      _BFGET_(r32, 9, 7)
    #define   SET32clkD2_ctrl_ClkSel(r32,v)                    _BFSET_(r32, 9, 7,v)
    #define   GET16clkD2_ctrl_ClkSel(r16)                      _BFGET_(r16, 9, 7)
    #define   SET16clkD2_ctrl_ClkSel(r16,v)                    _BFSET_(r16, 9, 7,v)

    #define     w32clkD2_ctrl                                  {\
            UNSG32 uctrl_ClkEn                                 :  1;\
            UNSG32 uctrl_ClkPllSel                             :  3;\
            UNSG32 uctrl_ClkPllSwitch                          :  1;\
            UNSG32 uctrl_ClkSwitch                             :  1;\
            UNSG32 uctrl_ClkD3Switch                           :  1;\
            UNSG32 uctrl_ClkSel                                :  3;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32clkD2_ctrl;
            struct w32clkD2_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_clkD2;

    typedef union  T32clkD2_ctrl
          { UNSG32 u32;
            struct w32clkD2_ctrl;
                 } T32clkD2_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TclkD2_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32clkD2_ctrl;
                   };
                 } TclkD2_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 clkD2_drvrd(SIE_clkD2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 clkD2_drvwr(SIE_clkD2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void clkD2_reset(SIE_clkD2 *p);
     SIGN32 clkD2_cmp  (SIE_clkD2 *p, SIE_clkD2 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define clkD2_check(p,pie,pfx,hLOG) clkD2_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define clkD2_print(p,    pfx,hLOG) clkD2_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: clkD2
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE clkD4                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Control register
///               ###
///               %unsigned 1  ClkEn                     0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Clock enable register
///                                                 * 0: Disable
///                                                 * 1: Enable   (default)
///                                                 ###
///               %unsigned 3  ClkPllSel                 0x4
///                                    : APLL0_CLKO1               0x0
///                                    : APLL1_CLKO1               0x1
///                                    : MEMPLL_CLKO1              0x2
///                                    : CPUPLL_CLKO1              0x3
///                                    : SYSPLL_CLKO1              0x4
///                                                 ###
///                                                 * Clock source selection
///                                                 * 0: AVPLLB4 – AVPLL Channel 2
///                                                 * 1: AVPLLB5 – AVPLL Channel 5
///                                                 * 2: AVPLLB6 – AVPLL Channel 6
///                                                 * 3: AVPLLB7 - MEMPLL
///                                                 * 4: SYSPLL - SYSPLL DIV3 (default)
///                                                 * 5-7: Reserved
///                                                 ###
///               %unsigned 1  ClkPllSwitch              0x0
///                                    : SYSPLL                    0x0
///                                    : AVPLL                     0x1
///                                                 ###
///                                                 * Switch to select between SYSPLL or AVPLL as a clock source
///                                                 * 0: SYSPLL (default)
///                                                 * 1: AVPLL (selected output of ClkPllSel mux)
///                                                 ###
///               %unsigned 1  ClkSwitch                 0x1
///                                    : SrcClk                    0x0
///                                    : DivClk                    0x1
///                                                 ###
///                                                 * Clock divider switch select
///                                                 * 0:   No divider
///                                                 * 1:   Use Divider (default)
///                                                 ###
///               %unsigned 1  ClkD3Switch               0x0
///                                    : NonDiv3Clk                0x0
///                                    : Div3Clk                   0x1
///                                                 ###
///                                                 * Divide by 3 clock switch
///                                                 * 0: No Divide by 3 (default)
///                                                 * 1: Use Divide by 3
///                                                 ###
///               %unsigned 3  ClkSel                    0x2
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///                                                 ###
///                                                 * Clock divider Selection
///                                                 * 0: Reserved
///                                                 * 1: Divide by 2 ( default)
///                                                 * 2: Divide by 4
///                                                 * 3: Divide by 6
///                                                 * 4: Divide by 8
///                                                 * 5: Divide by 12
///                                                 * 6-7: Reserved
///                                                 ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_clkD4
#define h_clkD4 (){}

    #define     RA_clkD4_ctrl                                  0x0000

    #define     BA_clkD4_ctrl_ClkEn                            0x0000
    #define     B16clkD4_ctrl_ClkEn                            0x0000
    #define   LSb32clkD4_ctrl_ClkEn                               0
    #define   LSb16clkD4_ctrl_ClkEn                               0
    #define       bclkD4_ctrl_ClkEn                            1
    #define   MSK32clkD4_ctrl_ClkEn                               0x00000001
    #define        clkD4_ctrl_ClkEn_enable                                  0x1
    #define        clkD4_ctrl_ClkEn_disable                                 0x0

    #define     BA_clkD4_ctrl_ClkPllSel                        0x0000
    #define     B16clkD4_ctrl_ClkPllSel                        0x0000
    #define   LSb32clkD4_ctrl_ClkPllSel                           1
    #define   LSb16clkD4_ctrl_ClkPllSel                           1
    #define       bclkD4_ctrl_ClkPllSel                        3
    #define   MSK32clkD4_ctrl_ClkPllSel                           0x0000000E
    #define        clkD4_ctrl_ClkPllSel_APLL0_CLKO1                         0x0
    #define        clkD4_ctrl_ClkPllSel_APLL1_CLKO1                         0x1
    #define        clkD4_ctrl_ClkPllSel_MEMPLL_CLKO1                        0x2
    #define        clkD4_ctrl_ClkPllSel_CPUPLL_CLKO1                        0x3
    #define        clkD4_ctrl_ClkPllSel_SYSPLL_CLKO1                        0x4

    #define     BA_clkD4_ctrl_ClkPllSwitch                     0x0000
    #define     B16clkD4_ctrl_ClkPllSwitch                     0x0000
    #define   LSb32clkD4_ctrl_ClkPllSwitch                        4
    #define   LSb16clkD4_ctrl_ClkPllSwitch                        4
    #define       bclkD4_ctrl_ClkPllSwitch                     1
    #define   MSK32clkD4_ctrl_ClkPllSwitch                        0x00000010
    #define        clkD4_ctrl_ClkPllSwitch_SYSPLL                           0x0
    #define        clkD4_ctrl_ClkPllSwitch_AVPLL                            0x1

    #define     BA_clkD4_ctrl_ClkSwitch                        0x0000
    #define     B16clkD4_ctrl_ClkSwitch                        0x0000
    #define   LSb32clkD4_ctrl_ClkSwitch                           5
    #define   LSb16clkD4_ctrl_ClkSwitch                           5
    #define       bclkD4_ctrl_ClkSwitch                        1
    #define   MSK32clkD4_ctrl_ClkSwitch                           0x00000020
    #define        clkD4_ctrl_ClkSwitch_SrcClk                              0x0
    #define        clkD4_ctrl_ClkSwitch_DivClk                              0x1

    #define     BA_clkD4_ctrl_ClkD3Switch                      0x0000
    #define     B16clkD4_ctrl_ClkD3Switch                      0x0000
    #define   LSb32clkD4_ctrl_ClkD3Switch                         6
    #define   LSb16clkD4_ctrl_ClkD3Switch                         6
    #define       bclkD4_ctrl_ClkD3Switch                      1
    #define   MSK32clkD4_ctrl_ClkD3Switch                         0x00000040
    #define        clkD4_ctrl_ClkD3Switch_NonDiv3Clk                        0x0
    #define        clkD4_ctrl_ClkD3Switch_Div3Clk                           0x1

    #define     BA_clkD4_ctrl_ClkSel                           0x0000
    #define     B16clkD4_ctrl_ClkSel                           0x0000
    #define   LSb32clkD4_ctrl_ClkSel                              7
    #define   LSb16clkD4_ctrl_ClkSel                              7
    #define       bclkD4_ctrl_ClkSel                           3
    #define   MSK32clkD4_ctrl_ClkSel                              0x00000380
    #define        clkD4_ctrl_ClkSel_d2                                     0x1
    #define        clkD4_ctrl_ClkSel_d4                                     0x2
    #define        clkD4_ctrl_ClkSel_d6                                     0x3
    #define        clkD4_ctrl_ClkSel_d8                                     0x4
    #define        clkD4_ctrl_ClkSel_d12                                    0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_clkD4 {
    ///////////////////////////////////////////////////////////
    #define   GET32clkD4_ctrl_ClkEn(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32clkD4_ctrl_ClkEn(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16clkD4_ctrl_ClkEn(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16clkD4_ctrl_ClkEn(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32clkD4_ctrl_ClkPllSel(r32)                   _BFGET_(r32, 3, 1)
    #define   SET32clkD4_ctrl_ClkPllSel(r32,v)                 _BFSET_(r32, 3, 1,v)
    #define   GET16clkD4_ctrl_ClkPllSel(r16)                   _BFGET_(r16, 3, 1)
    #define   SET16clkD4_ctrl_ClkPllSel(r16,v)                 _BFSET_(r16, 3, 1,v)

    #define   GET32clkD4_ctrl_ClkPllSwitch(r32)                _BFGET_(r32, 4, 4)
    #define   SET32clkD4_ctrl_ClkPllSwitch(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16clkD4_ctrl_ClkPllSwitch(r16)                _BFGET_(r16, 4, 4)
    #define   SET16clkD4_ctrl_ClkPllSwitch(r16,v)              _BFSET_(r16, 4, 4,v)

    #define   GET32clkD4_ctrl_ClkSwitch(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32clkD4_ctrl_ClkSwitch(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16clkD4_ctrl_ClkSwitch(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16clkD4_ctrl_ClkSwitch(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32clkD4_ctrl_ClkD3Switch(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32clkD4_ctrl_ClkD3Switch(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16clkD4_ctrl_ClkD3Switch(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16clkD4_ctrl_ClkD3Switch(r16,v)               _BFSET_(r16, 6, 6,v)

    #define   GET32clkD4_ctrl_ClkSel(r32)                      _BFGET_(r32, 9, 7)
    #define   SET32clkD4_ctrl_ClkSel(r32,v)                    _BFSET_(r32, 9, 7,v)
    #define   GET16clkD4_ctrl_ClkSel(r16)                      _BFGET_(r16, 9, 7)
    #define   SET16clkD4_ctrl_ClkSel(r16,v)                    _BFSET_(r16, 9, 7,v)

    #define     w32clkD4_ctrl                                  {\
            UNSG32 uctrl_ClkEn                                 :  1;\
            UNSG32 uctrl_ClkPllSel                             :  3;\
            UNSG32 uctrl_ClkPllSwitch                          :  1;\
            UNSG32 uctrl_ClkSwitch                             :  1;\
            UNSG32 uctrl_ClkD3Switch                           :  1;\
            UNSG32 uctrl_ClkSel                                :  3;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32clkD4_ctrl;
            struct w32clkD4_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_clkD4;

    typedef union  T32clkD4_ctrl
          { UNSG32 u32;
            struct w32clkD4_ctrl;
                 } T32clkD4_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TclkD4_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32clkD4_ctrl;
                   };
                 } TclkD4_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 clkD4_drvrd(SIE_clkD4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 clkD4_drvwr(SIE_clkD4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void clkD4_reset(SIE_clkD4 *p);
     SIGN32 clkD4_cmp  (SIE_clkD4 *p, SIE_clkD4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define clkD4_check(p,pie,pfx,hLOG) clkD4_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define clkD4_print(p,    pfx,hLOG) clkD4_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: clkD4
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE clkD6                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Control register
///               ###
///               %unsigned 1  ClkEn                     0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Clock enable register
///                                                 * 0: Disable
///                                                 * 1: Enable   (default)
///                                                 ###
///               %unsigned 3  ClkPllSel                 0x4
///                                    : APLL0_CLKO1               0x0
///                                    : APLL1_CLKO1               0x1
///                                    : MEMPLL_CLKO1              0x2
///                                    : CPUPLL_CLKO1              0x3
///                                    : SYSPLL_CLKO1              0x4
///                                                 ###
///                                                 * Clock source selection
///                                                 * 0: AVPLLB4 – AVPLL Channel 2
///                                                 * 1: AVPLLB5 – AVPLL Channel 5
///                                                 * 2: AVPLLB6 – AVPLL Channel 6
///                                                 * 3: AVPLLB7 - MEMPLL
///                                                 * 4: SYSPLL - SYSPLL DIV3 (default)
///                                                 * 5-7: Reserved
///                                                 ###
///               %unsigned 1  ClkPllSwitch              0x0
///                                    : SYSPLL                    0x0
///                                    : AVPLL                     0x1
///                                                 ###
///                                                 * Switch to select between SYSPLL or AVPLL as a clock source
///                                                 * 0: SYSPLL (default)
///                                                 * 1: AVPLL (selected output of ClkPllSel mux)
///                                                 ###
///               %unsigned 1  ClkSwitch                 0x1
///                                    : SrcClk                    0x0
///                                    : DivClk                    0x1
///                                                 ###
///                                                 * Clock divider switch select
///                                                 * 0:   No divider
///                                                 * 1:   Use Divider (default)
///                                                 ###
///               %unsigned 1  ClkD3Switch               0x0
///                                    : NonDiv3Clk                0x0
///                                    : Div3Clk                   0x1
///                                                 ###
///                                                 * Divide by 3 clock switch
///                                                 * 0: No Divide by 3 (default)
///                                                 * 1: Use Divide by 3
///                                                 ###
///               %unsigned 3  ClkSel                    0x3
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///                                                 ###
///                                                 * Clock divider Selection
///                                                 * 0: Reserved
///                                                 * 1: Divide by 2 ( default)
///                                                 * 2: Divide by 4
///                                                 * 3: Divide by 6
///                                                 * 4: Divide by 8
///                                                 * 5: Divide by 12
///                                                 * 6-7: Reserved
///                                                 ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_clkD6
#define h_clkD6 (){}

    #define     RA_clkD6_ctrl                                  0x0000

    #define     BA_clkD6_ctrl_ClkEn                            0x0000
    #define     B16clkD6_ctrl_ClkEn                            0x0000
    #define   LSb32clkD6_ctrl_ClkEn                               0
    #define   LSb16clkD6_ctrl_ClkEn                               0
    #define       bclkD6_ctrl_ClkEn                            1
    #define   MSK32clkD6_ctrl_ClkEn                               0x00000001
    #define        clkD6_ctrl_ClkEn_enable                                  0x1
    #define        clkD6_ctrl_ClkEn_disable                                 0x0

    #define     BA_clkD6_ctrl_ClkPllSel                        0x0000
    #define     B16clkD6_ctrl_ClkPllSel                        0x0000
    #define   LSb32clkD6_ctrl_ClkPllSel                           1
    #define   LSb16clkD6_ctrl_ClkPllSel                           1
    #define       bclkD6_ctrl_ClkPllSel                        3
    #define   MSK32clkD6_ctrl_ClkPllSel                           0x0000000E
    #define        clkD6_ctrl_ClkPllSel_APLL0_CLKO1                         0x0
    #define        clkD6_ctrl_ClkPllSel_APLL1_CLKO1                         0x1
    #define        clkD6_ctrl_ClkPllSel_MEMPLL_CLKO1                        0x2
    #define        clkD6_ctrl_ClkPllSel_CPUPLL_CLKO1                        0x3
    #define        clkD6_ctrl_ClkPllSel_SYSPLL_CLKO1                        0x4

    #define     BA_clkD6_ctrl_ClkPllSwitch                     0x0000
    #define     B16clkD6_ctrl_ClkPllSwitch                     0x0000
    #define   LSb32clkD6_ctrl_ClkPllSwitch                        4
    #define   LSb16clkD6_ctrl_ClkPllSwitch                        4
    #define       bclkD6_ctrl_ClkPllSwitch                     1
    #define   MSK32clkD6_ctrl_ClkPllSwitch                        0x00000010
    #define        clkD6_ctrl_ClkPllSwitch_SYSPLL                           0x0
    #define        clkD6_ctrl_ClkPllSwitch_AVPLL                            0x1

    #define     BA_clkD6_ctrl_ClkSwitch                        0x0000
    #define     B16clkD6_ctrl_ClkSwitch                        0x0000
    #define   LSb32clkD6_ctrl_ClkSwitch                           5
    #define   LSb16clkD6_ctrl_ClkSwitch                           5
    #define       bclkD6_ctrl_ClkSwitch                        1
    #define   MSK32clkD6_ctrl_ClkSwitch                           0x00000020
    #define        clkD6_ctrl_ClkSwitch_SrcClk                              0x0
    #define        clkD6_ctrl_ClkSwitch_DivClk                              0x1

    #define     BA_clkD6_ctrl_ClkD3Switch                      0x0000
    #define     B16clkD6_ctrl_ClkD3Switch                      0x0000
    #define   LSb32clkD6_ctrl_ClkD3Switch                         6
    #define   LSb16clkD6_ctrl_ClkD3Switch                         6
    #define       bclkD6_ctrl_ClkD3Switch                      1
    #define   MSK32clkD6_ctrl_ClkD3Switch                         0x00000040
    #define        clkD6_ctrl_ClkD3Switch_NonDiv3Clk                        0x0
    #define        clkD6_ctrl_ClkD3Switch_Div3Clk                           0x1

    #define     BA_clkD6_ctrl_ClkSel                           0x0000
    #define     B16clkD6_ctrl_ClkSel                           0x0000
    #define   LSb32clkD6_ctrl_ClkSel                              7
    #define   LSb16clkD6_ctrl_ClkSel                              7
    #define       bclkD6_ctrl_ClkSel                           3
    #define   MSK32clkD6_ctrl_ClkSel                              0x00000380
    #define        clkD6_ctrl_ClkSel_d2                                     0x1
    #define        clkD6_ctrl_ClkSel_d4                                     0x2
    #define        clkD6_ctrl_ClkSel_d6                                     0x3
    #define        clkD6_ctrl_ClkSel_d8                                     0x4
    #define        clkD6_ctrl_ClkSel_d12                                    0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_clkD6 {
    ///////////////////////////////////////////////////////////
    #define   GET32clkD6_ctrl_ClkEn(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32clkD6_ctrl_ClkEn(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16clkD6_ctrl_ClkEn(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16clkD6_ctrl_ClkEn(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32clkD6_ctrl_ClkPllSel(r32)                   _BFGET_(r32, 3, 1)
    #define   SET32clkD6_ctrl_ClkPllSel(r32,v)                 _BFSET_(r32, 3, 1,v)
    #define   GET16clkD6_ctrl_ClkPllSel(r16)                   _BFGET_(r16, 3, 1)
    #define   SET16clkD6_ctrl_ClkPllSel(r16,v)                 _BFSET_(r16, 3, 1,v)

    #define   GET32clkD6_ctrl_ClkPllSwitch(r32)                _BFGET_(r32, 4, 4)
    #define   SET32clkD6_ctrl_ClkPllSwitch(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16clkD6_ctrl_ClkPllSwitch(r16)                _BFGET_(r16, 4, 4)
    #define   SET16clkD6_ctrl_ClkPllSwitch(r16,v)              _BFSET_(r16, 4, 4,v)

    #define   GET32clkD6_ctrl_ClkSwitch(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32clkD6_ctrl_ClkSwitch(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16clkD6_ctrl_ClkSwitch(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16clkD6_ctrl_ClkSwitch(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32clkD6_ctrl_ClkD3Switch(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32clkD6_ctrl_ClkD3Switch(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16clkD6_ctrl_ClkD3Switch(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16clkD6_ctrl_ClkD3Switch(r16,v)               _BFSET_(r16, 6, 6,v)

    #define   GET32clkD6_ctrl_ClkSel(r32)                      _BFGET_(r32, 9, 7)
    #define   SET32clkD6_ctrl_ClkSel(r32,v)                    _BFSET_(r32, 9, 7,v)
    #define   GET16clkD6_ctrl_ClkSel(r16)                      _BFGET_(r16, 9, 7)
    #define   SET16clkD6_ctrl_ClkSel(r16,v)                    _BFSET_(r16, 9, 7,v)

    #define     w32clkD6_ctrl                                  {\
            UNSG32 uctrl_ClkEn                                 :  1;\
            UNSG32 uctrl_ClkPllSel                             :  3;\
            UNSG32 uctrl_ClkPllSwitch                          :  1;\
            UNSG32 uctrl_ClkSwitch                             :  1;\
            UNSG32 uctrl_ClkD3Switch                           :  1;\
            UNSG32 uctrl_ClkSel                                :  3;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32clkD6_ctrl;
            struct w32clkD6_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_clkD6;

    typedef union  T32clkD6_ctrl
          { UNSG32 u32;
            struct w32clkD6_ctrl;
                 } T32clkD6_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TclkD6_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32clkD6_ctrl;
                   };
                 } TclkD6_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 clkD6_drvrd(SIE_clkD6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 clkD6_drvwr(SIE_clkD6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void clkD6_reset(SIE_clkD6 *p);
     SIGN32 clkD6_cmp  (SIE_clkD6 *p, SIE_clkD6 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define clkD6_check(p,pie,pfx,hLOG) clkD6_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define clkD6_print(p,    pfx,hLOG) clkD6_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: clkD6
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE clkD8                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Control register
///               ###
///               %unsigned 1  ClkEn                     0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Clock enable register
///                                                 * 0: Disable
///                                                 * 1: Enable   (default)
///                                                 ###
///               %unsigned 3  ClkPllSel                 0x4
///                                    : APLL0_CLKO1               0x0
///                                    : APLL1_CLKO1               0x1
///                                    : MEMPLL_CLKO1              0x2
///                                    : CPUPLL_CLKO1              0x3
///                                    : SYSPLL_CLKO1              0x4
///                                                 ###
///                                                 * Clock source selection
///                                                 * 0: AVPLLB4 – AVPLL Channel 2
///                                                 * 1: AVPLLB5 – AVPLL Channel 5
///                                                 * 2: AVPLLB6 – AVPLL Channel 6
///                                                 * 3: AVPLLB7 - MEMPLL
///                                                 * 4: SYSPLL - SYSPLL DIV3 (default)
///                                                 * 5-7: Reserved
///                                                 ###
///               %unsigned 1  ClkPllSwitch              0x0
///                                    : SYSPLL                    0x0
///                                    : AVPLL                     0x1
///                                                 ###
///                                                 * Switch to select between SYSPLL or AVPLL as a clock source
///                                                 * 0: SYSPLL (default)
///                                                 * 1: AVPLL (selected output of ClkPllSel mux)
///                                                 ###
///               %unsigned 1  ClkSwitch                 0x1
///                                    : SrcClk                    0x0
///                                    : DivClk                    0x1
///                                                 ###
///                                                 * Clock divider switch select
///                                                 * 0:   No divider
///                                                 * 1:   Use Divider (default)
///                                                 ###
///               %unsigned 1  ClkD3Switch               0x0
///                                    : NonDiv3Clk                0x0
///                                    : Div3Clk                   0x1
///                                                 ###
///                                                 * Divide by 3 clock switch
///                                                 * 0: No Divide by 3 (default)
///                                                 * 1: Use Divide by 3
///                                                 ###
///               %unsigned 3  ClkSel                    0x4
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///                                                 ###
///                                                 * Clock divider Selection
///                                                 * 0: Reserved
///                                                 * 1: Divide by 2 ( default)
///                                                 * 2: Divide by 4
///                                                 * 3: Divide by 6
///                                                 * 4: Divide by 8
///                                                 * 5: Divide by 12
///                                                 * 6-7: Reserved
///                                                 ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_clkD8
#define h_clkD8 (){}

    #define     RA_clkD8_ctrl                                  0x0000

    #define     BA_clkD8_ctrl_ClkEn                            0x0000
    #define     B16clkD8_ctrl_ClkEn                            0x0000
    #define   LSb32clkD8_ctrl_ClkEn                               0
    #define   LSb16clkD8_ctrl_ClkEn                               0
    #define       bclkD8_ctrl_ClkEn                            1
    #define   MSK32clkD8_ctrl_ClkEn                               0x00000001
    #define        clkD8_ctrl_ClkEn_enable                                  0x1
    #define        clkD8_ctrl_ClkEn_disable                                 0x0

    #define     BA_clkD8_ctrl_ClkPllSel                        0x0000
    #define     B16clkD8_ctrl_ClkPllSel                        0x0000
    #define   LSb32clkD8_ctrl_ClkPllSel                           1
    #define   LSb16clkD8_ctrl_ClkPllSel                           1
    #define       bclkD8_ctrl_ClkPllSel                        3
    #define   MSK32clkD8_ctrl_ClkPllSel                           0x0000000E
    #define        clkD8_ctrl_ClkPllSel_APLL0_CLKO1                         0x0
    #define        clkD8_ctrl_ClkPllSel_APLL1_CLKO1                         0x1
    #define        clkD8_ctrl_ClkPllSel_MEMPLL_CLKO1                        0x2
    #define        clkD8_ctrl_ClkPllSel_CPUPLL_CLKO1                        0x3
    #define        clkD8_ctrl_ClkPllSel_SYSPLL_CLKO1                        0x4

    #define     BA_clkD8_ctrl_ClkPllSwitch                     0x0000
    #define     B16clkD8_ctrl_ClkPllSwitch                     0x0000
    #define   LSb32clkD8_ctrl_ClkPllSwitch                        4
    #define   LSb16clkD8_ctrl_ClkPllSwitch                        4
    #define       bclkD8_ctrl_ClkPllSwitch                     1
    #define   MSK32clkD8_ctrl_ClkPllSwitch                        0x00000010
    #define        clkD8_ctrl_ClkPllSwitch_SYSPLL                           0x0
    #define        clkD8_ctrl_ClkPllSwitch_AVPLL                            0x1

    #define     BA_clkD8_ctrl_ClkSwitch                        0x0000
    #define     B16clkD8_ctrl_ClkSwitch                        0x0000
    #define   LSb32clkD8_ctrl_ClkSwitch                           5
    #define   LSb16clkD8_ctrl_ClkSwitch                           5
    #define       bclkD8_ctrl_ClkSwitch                        1
    #define   MSK32clkD8_ctrl_ClkSwitch                           0x00000020
    #define        clkD8_ctrl_ClkSwitch_SrcClk                              0x0
    #define        clkD8_ctrl_ClkSwitch_DivClk                              0x1

    #define     BA_clkD8_ctrl_ClkD3Switch                      0x0000
    #define     B16clkD8_ctrl_ClkD3Switch                      0x0000
    #define   LSb32clkD8_ctrl_ClkD3Switch                         6
    #define   LSb16clkD8_ctrl_ClkD3Switch                         6
    #define       bclkD8_ctrl_ClkD3Switch                      1
    #define   MSK32clkD8_ctrl_ClkD3Switch                         0x00000040
    #define        clkD8_ctrl_ClkD3Switch_NonDiv3Clk                        0x0
    #define        clkD8_ctrl_ClkD3Switch_Div3Clk                           0x1

    #define     BA_clkD8_ctrl_ClkSel                           0x0000
    #define     B16clkD8_ctrl_ClkSel                           0x0000
    #define   LSb32clkD8_ctrl_ClkSel                              7
    #define   LSb16clkD8_ctrl_ClkSel                              7
    #define       bclkD8_ctrl_ClkSel                           3
    #define   MSK32clkD8_ctrl_ClkSel                              0x00000380
    #define        clkD8_ctrl_ClkSel_d2                                     0x1
    #define        clkD8_ctrl_ClkSel_d4                                     0x2
    #define        clkD8_ctrl_ClkSel_d6                                     0x3
    #define        clkD8_ctrl_ClkSel_d8                                     0x4
    #define        clkD8_ctrl_ClkSel_d12                                    0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_clkD8 {
    ///////////////////////////////////////////////////////////
    #define   GET32clkD8_ctrl_ClkEn(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32clkD8_ctrl_ClkEn(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16clkD8_ctrl_ClkEn(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16clkD8_ctrl_ClkEn(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32clkD8_ctrl_ClkPllSel(r32)                   _BFGET_(r32, 3, 1)
    #define   SET32clkD8_ctrl_ClkPllSel(r32,v)                 _BFSET_(r32, 3, 1,v)
    #define   GET16clkD8_ctrl_ClkPllSel(r16)                   _BFGET_(r16, 3, 1)
    #define   SET16clkD8_ctrl_ClkPllSel(r16,v)                 _BFSET_(r16, 3, 1,v)

    #define   GET32clkD8_ctrl_ClkPllSwitch(r32)                _BFGET_(r32, 4, 4)
    #define   SET32clkD8_ctrl_ClkPllSwitch(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16clkD8_ctrl_ClkPllSwitch(r16)                _BFGET_(r16, 4, 4)
    #define   SET16clkD8_ctrl_ClkPllSwitch(r16,v)              _BFSET_(r16, 4, 4,v)

    #define   GET32clkD8_ctrl_ClkSwitch(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32clkD8_ctrl_ClkSwitch(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16clkD8_ctrl_ClkSwitch(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16clkD8_ctrl_ClkSwitch(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32clkD8_ctrl_ClkD3Switch(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32clkD8_ctrl_ClkD3Switch(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16clkD8_ctrl_ClkD3Switch(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16clkD8_ctrl_ClkD3Switch(r16,v)               _BFSET_(r16, 6, 6,v)

    #define   GET32clkD8_ctrl_ClkSel(r32)                      _BFGET_(r32, 9, 7)
    #define   SET32clkD8_ctrl_ClkSel(r32,v)                    _BFSET_(r32, 9, 7,v)
    #define   GET16clkD8_ctrl_ClkSel(r16)                      _BFGET_(r16, 9, 7)
    #define   SET16clkD8_ctrl_ClkSel(r16,v)                    _BFSET_(r16, 9, 7,v)

    #define     w32clkD8_ctrl                                  {\
            UNSG32 uctrl_ClkEn                                 :  1;\
            UNSG32 uctrl_ClkPllSel                             :  3;\
            UNSG32 uctrl_ClkPllSwitch                          :  1;\
            UNSG32 uctrl_ClkSwitch                             :  1;\
            UNSG32 uctrl_ClkD3Switch                           :  1;\
            UNSG32 uctrl_ClkSel                                :  3;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32clkD8_ctrl;
            struct w32clkD8_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_clkD8;

    typedef union  T32clkD8_ctrl
          { UNSG32 u32;
            struct w32clkD8_ctrl;
                 } T32clkD8_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TclkD8_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32clkD8_ctrl;
                   };
                 } TclkD8_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 clkD8_drvrd(SIE_clkD8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 clkD8_drvwr(SIE_clkD8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void clkD8_reset(SIE_clkD8 *p);
     SIGN32 clkD8_cmp  (SIE_clkD8 *p, SIE_clkD8 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define clkD8_check(p,pie,pfx,hLOG) clkD8_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define clkD8_print(p,    pfx,hLOG) clkD8_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: clkD8
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE clkD12                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * Control register
///               ###
///               %unsigned 1  ClkEn                     0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Clock enable register
///                                                 * 0: Disable
///                                                 * 1: Enable   (default)
///                                                 ###
///               %unsigned 3  ClkPllSel                 0x4
///                                    : APLL0_CLKO1               0x0
///                                    : APLL1_CLKO1               0x1
///                                    : MEMPLL_CLKO1              0x2
///                                    : CPUPLL_CLKO1              0x3
///                                    : SYSPLL_CLKO1              0x4
///                                                 ###
///                                                 * Clock source selection
///                                                 * 0: AVPLLB4 – AVPLL Channel 2
///                                                 * 1: AVPLLB5 – AVPLL Channel 5
///                                                 * 2: AVPLLB6 – AVPLL Channel 6
///                                                 * 3: AVPLLB7 - MEMPLL
///                                                 * 4: SYSPLL - SYSPLL DIV3 (default)
///                                                 * 5-7: Reserved
///                                                 ###
///               %unsigned 1  ClkPllSwitch              0x0
///                                    : SYSPLL                    0x0
///                                    : AVPLL                     0x1
///                                                 ###
///                                                 * Switch to select between SYSPLL or AVPLL as a clock source
///                                                 * 0: SYSPLL (default)
///                                                 * 1: AVPLL (selected output of ClkPllSel mux)
///                                                 ###
///               %unsigned 1  ClkSwitch                 0x1
///                                    : SrcClk                    0x0
///                                    : DivClk                    0x1
///                                                 ###
///                                                 * Clock divider switch select
///                                                 * 0:   No divider
///                                                 * 1:   Use Divider (default)
///                                                 ###
///               %unsigned 1  ClkD3Switch               0x0
///                                    : NonDiv3Clk                0x0
///                                    : Div3Clk                   0x1
///                                                 ###
///                                                 * Divide by 3 clock switch
///                                                 * 0: No Divide by 3 (default)
///                                                 * 1: Use Divide by 3
///                                                 ###
///               %unsigned 3  ClkSel                    0x5
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///                                                 ###
///                                                 * Clock divider Selection
///                                                 * 0: Reserved
///                                                 * 1: Divide by 2 ( default)
///                                                 * 2: Divide by 4
///                                                 * 3: Divide by 6
///                                                 * 4: Divide by 8
///                                                 * 5: Divide by 12
///                                                 * 6-7: Reserved
///                                                 ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_clkD12
#define h_clkD12 (){}

    #define     RA_clkD12_ctrl                                 0x0000

    #define     BA_clkD12_ctrl_ClkEn                           0x0000
    #define     B16clkD12_ctrl_ClkEn                           0x0000
    #define   LSb32clkD12_ctrl_ClkEn                              0
    #define   LSb16clkD12_ctrl_ClkEn                              0
    #define       bclkD12_ctrl_ClkEn                           1
    #define   MSK32clkD12_ctrl_ClkEn                              0x00000001
    #define        clkD12_ctrl_ClkEn_enable                                 0x1
    #define        clkD12_ctrl_ClkEn_disable                                0x0

    #define     BA_clkD12_ctrl_ClkPllSel                       0x0000
    #define     B16clkD12_ctrl_ClkPllSel                       0x0000
    #define   LSb32clkD12_ctrl_ClkPllSel                          1
    #define   LSb16clkD12_ctrl_ClkPllSel                          1
    #define       bclkD12_ctrl_ClkPllSel                       3
    #define   MSK32clkD12_ctrl_ClkPllSel                          0x0000000E
    #define        clkD12_ctrl_ClkPllSel_APLL0_CLKO1                        0x0
    #define        clkD12_ctrl_ClkPllSel_APLL1_CLKO1                        0x1
    #define        clkD12_ctrl_ClkPllSel_MEMPLL_CLKO1                       0x2
    #define        clkD12_ctrl_ClkPllSel_CPUPLL_CLKO1                       0x3
    #define        clkD12_ctrl_ClkPllSel_SYSPLL_CLKO1                       0x4

    #define     BA_clkD12_ctrl_ClkPllSwitch                    0x0000
    #define     B16clkD12_ctrl_ClkPllSwitch                    0x0000
    #define   LSb32clkD12_ctrl_ClkPllSwitch                       4
    #define   LSb16clkD12_ctrl_ClkPllSwitch                       4
    #define       bclkD12_ctrl_ClkPllSwitch                    1
    #define   MSK32clkD12_ctrl_ClkPllSwitch                       0x00000010
    #define        clkD12_ctrl_ClkPllSwitch_SYSPLL                          0x0
    #define        clkD12_ctrl_ClkPllSwitch_AVPLL                           0x1

    #define     BA_clkD12_ctrl_ClkSwitch                       0x0000
    #define     B16clkD12_ctrl_ClkSwitch                       0x0000
    #define   LSb32clkD12_ctrl_ClkSwitch                          5
    #define   LSb16clkD12_ctrl_ClkSwitch                          5
    #define       bclkD12_ctrl_ClkSwitch                       1
    #define   MSK32clkD12_ctrl_ClkSwitch                          0x00000020
    #define        clkD12_ctrl_ClkSwitch_SrcClk                             0x0
    #define        clkD12_ctrl_ClkSwitch_DivClk                             0x1

    #define     BA_clkD12_ctrl_ClkD3Switch                     0x0000
    #define     B16clkD12_ctrl_ClkD3Switch                     0x0000
    #define   LSb32clkD12_ctrl_ClkD3Switch                        6
    #define   LSb16clkD12_ctrl_ClkD3Switch                        6
    #define       bclkD12_ctrl_ClkD3Switch                     1
    #define   MSK32clkD12_ctrl_ClkD3Switch                        0x00000040
    #define        clkD12_ctrl_ClkD3Switch_NonDiv3Clk                       0x0
    #define        clkD12_ctrl_ClkD3Switch_Div3Clk                          0x1

    #define     BA_clkD12_ctrl_ClkSel                          0x0000
    #define     B16clkD12_ctrl_ClkSel                          0x0000
    #define   LSb32clkD12_ctrl_ClkSel                             7
    #define   LSb16clkD12_ctrl_ClkSel                             7
    #define       bclkD12_ctrl_ClkSel                          3
    #define   MSK32clkD12_ctrl_ClkSel                             0x00000380
    #define        clkD12_ctrl_ClkSel_d2                                    0x1
    #define        clkD12_ctrl_ClkSel_d4                                    0x2
    #define        clkD12_ctrl_ClkSel_d6                                    0x3
    #define        clkD12_ctrl_ClkSel_d8                                    0x4
    #define        clkD12_ctrl_ClkSel_d12                                   0x5
    ///////////////////////////////////////////////////////////

    typedef struct SIE_clkD12 {
    ///////////////////////////////////////////////////////////
    #define   GET32clkD12_ctrl_ClkEn(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32clkD12_ctrl_ClkEn(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16clkD12_ctrl_ClkEn(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16clkD12_ctrl_ClkEn(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32clkD12_ctrl_ClkPllSel(r32)                  _BFGET_(r32, 3, 1)
    #define   SET32clkD12_ctrl_ClkPllSel(r32,v)                _BFSET_(r32, 3, 1,v)
    #define   GET16clkD12_ctrl_ClkPllSel(r16)                  _BFGET_(r16, 3, 1)
    #define   SET16clkD12_ctrl_ClkPllSel(r16,v)                _BFSET_(r16, 3, 1,v)

    #define   GET32clkD12_ctrl_ClkPllSwitch(r32)               _BFGET_(r32, 4, 4)
    #define   SET32clkD12_ctrl_ClkPllSwitch(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16clkD12_ctrl_ClkPllSwitch(r16)               _BFGET_(r16, 4, 4)
    #define   SET16clkD12_ctrl_ClkPllSwitch(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32clkD12_ctrl_ClkSwitch(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32clkD12_ctrl_ClkSwitch(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16clkD12_ctrl_ClkSwitch(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16clkD12_ctrl_ClkSwitch(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32clkD12_ctrl_ClkD3Switch(r32)                _BFGET_(r32, 6, 6)
    #define   SET32clkD12_ctrl_ClkD3Switch(r32,v)              _BFSET_(r32, 6, 6,v)
    #define   GET16clkD12_ctrl_ClkD3Switch(r16)                _BFGET_(r16, 6, 6)
    #define   SET16clkD12_ctrl_ClkD3Switch(r16,v)              _BFSET_(r16, 6, 6,v)

    #define   GET32clkD12_ctrl_ClkSel(r32)                     _BFGET_(r32, 9, 7)
    #define   SET32clkD12_ctrl_ClkSel(r32,v)                   _BFSET_(r32, 9, 7,v)
    #define   GET16clkD12_ctrl_ClkSel(r16)                     _BFGET_(r16, 9, 7)
    #define   SET16clkD12_ctrl_ClkSel(r16,v)                   _BFSET_(r16, 9, 7,v)

    #define     w32clkD12_ctrl                                 {\
            UNSG32 uctrl_ClkEn                                 :  1;\
            UNSG32 uctrl_ClkPllSel                             :  3;\
            UNSG32 uctrl_ClkPllSwitch                          :  1;\
            UNSG32 uctrl_ClkSwitch                             :  1;\
            UNSG32 uctrl_ClkD3Switch                           :  1;\
            UNSG32 uctrl_ClkSel                                :  3;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32clkD12_ctrl;
            struct w32clkD12_ctrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_clkD12;

    typedef union  T32clkD12_ctrl
          { UNSG32 u32;
            struct w32clkD12_ctrl;
                 } T32clkD12_ctrl;
    ///////////////////////////////////////////////////////////

    typedef union  TclkD12_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32clkD12_ctrl;
                   };
                 } TclkD12_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 clkD12_drvrd(SIE_clkD12 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 clkD12_drvwr(SIE_clkD12 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void clkD12_reset(SIE_clkD12 *p);
     SIGN32 clkD12_cmp  (SIE_clkD12 *p, SIE_clkD12 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define clkD12_check(p,pie,pfx,hLOG) clkD12_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define clkD12_print(p,    pfx,hLOG) clkD12_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: clkD12
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE PERIF                   biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 PHY_DBG_CTRL         (P)
///               %unsigned 3  perif_dbg_sel             0x0
///                                    ###
///                                    * 3'b000 : usbOTG debug bus
///                                    * 3'b001 : pcie0 debug bus
///                                    * 3'b010: pcie1 debug bus
///                                    ###
///               %unsigned 2  SIF_MUX_SEL               0x0
///                                    ###
///                                    * 2'b00 : Reserved
///                                    * 2'b01 : SIF for SATA COMPHY
///                                    * 2'b10 : SIF for PCIE COMPHY
///                                    * 2'b11 : SIF for USB3 COMPHY
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00004 USB_CTRL             (P)
///               %unsigned 1  DISABLE_EL16              0x0
///                                    ###
///                                    * 0: Not disable EL16 compliance
///                                    * 1: Disable EL 16 compliance
///                                    ###
///               %unsigned 2  CTRL_MODE                 0x0
///                                    ###
///                                    * 00 : For OTG mode
///                                    ###
///               %unsigned 1  FORCE_PHYSTCKYRST         0x0
///                                    ###
///                                    * 0: Can use O_CLK_RDY from PHY to deassert prst_n
///                                    * 1: Desassertion of prst_n controlled through usbOtg sticky reset bit.
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00008 PXBAR_ASIB_SEL       (P)
///               %unsigned 1  NAND_EMMC                 0x0
///                                    ###
///                                    * 0: Pxbar asib connected to NAND
///                                    * 1: Pxbar asib connected to EMMC.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x0000C NAND_CTL0            (P)
///               ###
///               * NAND IP Control register0
///               ###
///               %unsigned 1  discovery_inhibit         0x1
///                                    ###
///                                    * Inhibit controller from discovery
///                                    ###
///               %unsigned 1  discovery_ignore_crc      0x1
///                                    ###
///                                    * Disable CRC during discovery
///                                    ###
///               %unsigned 16 rb_valid_time             0x3E8
///                                    ###
///                                    * RB valid time
///                                    ###
///               %%        14         # Stuffing bits...
///     @ 0x00010 NAND_CTL1            (P)
///               ###
///               * NAND IP Control register1
///               ###
///               %unsigned 16 dd_page_size              0x1000
///                                    ###
///                                    * DD page size
///                                    ###
///               %unsigned 16 dd_page_per_block         0x100
///                                    ###
///                                    * DD page size
///                                    ###
///     @ 0x00014 NAND_CTL2            (P)
///               ###
///               * NAND IP Control register2
///               ###
///               %unsigned 4  dd_lun_number             0x1
///                                    ###
///                                    * DD LUN number
///                                    ###
///               %unsigned 1  dd_four_addr_cycles       0x0
///                                    ###
///                                    * DD Four addr Cycles
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00018 NAND_DEVICE_IDL      (R-)
///               ###
///               * NAND Device ID Low
///               ###
///               %unsigned 32 id_low                    0x0
///                                    ###
///                                    * ID Low value
///                                    ###
///     @ 0x0001C NAND_DEVICE_IDH      (R-)
///               ###
///               * NAND Device ID High
///               ###
///               %unsigned 8  id_high                   0x0
///                                    ###
///                                    * ID High value
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00020 NAND_STATUS          (R-)
///               ###
///               * NAND Status
///               ###
///               %unsigned 1  init_comp                 0x0
///                                    ###
///                                    * Initialization Complete
///                                    ###
///               %unsigned 1  init_fail                 0x0
///                                    ###
///                                    * Initialization Fail
///                                    ###
///               %unsigned 1  ctrl_busy                 0x0
///                                    ###
///                                    * 1: NFC is busy
///                                    * 0 : NFC is Idle
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00024 RSERVED_CTRL0        (P)
///               ###
///               * Not used, may be used for ECOs
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 32 ctrl                      0x0
///                                    ###
///                                    * Not used.
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      40B, bits:     140b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_PERIF
#define h_PERIF (){}

    #define     RA_PERIF_PHY_DBG_CTRL                          0x0000

    #define     BA_PERIF_PHY_DBG_CTRL_perif_dbg_sel            0x0000
    #define     B16PERIF_PHY_DBG_CTRL_perif_dbg_sel            0x0000
    #define   LSb32PERIF_PHY_DBG_CTRL_perif_dbg_sel               0
    #define   LSb16PERIF_PHY_DBG_CTRL_perif_dbg_sel               0
    #define       bPERIF_PHY_DBG_CTRL_perif_dbg_sel            3
    #define   MSK32PERIF_PHY_DBG_CTRL_perif_dbg_sel               0x00000007

    #define     BA_PERIF_PHY_DBG_CTRL_SIF_MUX_SEL              0x0000
    #define     B16PERIF_PHY_DBG_CTRL_SIF_MUX_SEL              0x0000
    #define   LSb32PERIF_PHY_DBG_CTRL_SIF_MUX_SEL                 3
    #define   LSb16PERIF_PHY_DBG_CTRL_SIF_MUX_SEL                 3
    #define       bPERIF_PHY_DBG_CTRL_SIF_MUX_SEL              2
    #define   MSK32PERIF_PHY_DBG_CTRL_SIF_MUX_SEL                 0x00000018
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_USB_CTRL                              0x0004

    #define     BA_PERIF_USB_CTRL_DISABLE_EL16                 0x0004
    #define     B16PERIF_USB_CTRL_DISABLE_EL16                 0x0004
    #define   LSb32PERIF_USB_CTRL_DISABLE_EL16                    0
    #define   LSb16PERIF_USB_CTRL_DISABLE_EL16                    0
    #define       bPERIF_USB_CTRL_DISABLE_EL16                 1
    #define   MSK32PERIF_USB_CTRL_DISABLE_EL16                    0x00000001

    #define     BA_PERIF_USB_CTRL_CTRL_MODE                    0x0004
    #define     B16PERIF_USB_CTRL_CTRL_MODE                    0x0004
    #define   LSb32PERIF_USB_CTRL_CTRL_MODE                       1
    #define   LSb16PERIF_USB_CTRL_CTRL_MODE                       1
    #define       bPERIF_USB_CTRL_CTRL_MODE                    2
    #define   MSK32PERIF_USB_CTRL_CTRL_MODE                       0x00000006

    #define     BA_PERIF_USB_CTRL_FORCE_PHYSTCKYRST            0x0004
    #define     B16PERIF_USB_CTRL_FORCE_PHYSTCKYRST            0x0004
    #define   LSb32PERIF_USB_CTRL_FORCE_PHYSTCKYRST               3
    #define   LSb16PERIF_USB_CTRL_FORCE_PHYSTCKYRST               3
    #define       bPERIF_USB_CTRL_FORCE_PHYSTCKYRST            1
    #define   MSK32PERIF_USB_CTRL_FORCE_PHYSTCKYRST               0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_PXBAR_ASIB_SEL                        0x0008

    #define     BA_PERIF_PXBAR_ASIB_SEL_NAND_EMMC              0x0008
    #define     B16PERIF_PXBAR_ASIB_SEL_NAND_EMMC              0x0008
    #define   LSb32PERIF_PXBAR_ASIB_SEL_NAND_EMMC                 0
    #define   LSb16PERIF_PXBAR_ASIB_SEL_NAND_EMMC                 0
    #define       bPERIF_PXBAR_ASIB_SEL_NAND_EMMC              1
    #define   MSK32PERIF_PXBAR_ASIB_SEL_NAND_EMMC                 0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_NAND_CTL0                             0x000C

    #define     BA_PERIF_NAND_CTL0_discovery_inhibit           0x000C
    #define     B16PERIF_NAND_CTL0_discovery_inhibit           0x000C
    #define   LSb32PERIF_NAND_CTL0_discovery_inhibit              0
    #define   LSb16PERIF_NAND_CTL0_discovery_inhibit              0
    #define       bPERIF_NAND_CTL0_discovery_inhibit           1
    #define   MSK32PERIF_NAND_CTL0_discovery_inhibit              0x00000001

    #define     BA_PERIF_NAND_CTL0_discovery_ignore_crc        0x000C
    #define     B16PERIF_NAND_CTL0_discovery_ignore_crc        0x000C
    #define   LSb32PERIF_NAND_CTL0_discovery_ignore_crc           1
    #define   LSb16PERIF_NAND_CTL0_discovery_ignore_crc           1
    #define       bPERIF_NAND_CTL0_discovery_ignore_crc        1
    #define   MSK32PERIF_NAND_CTL0_discovery_ignore_crc           0x00000002

    #define     BA_PERIF_NAND_CTL0_rb_valid_time               0x000C
    #define     B16PERIF_NAND_CTL0_rb_valid_time               0x000C
    #define   LSb32PERIF_NAND_CTL0_rb_valid_time                  2
    #define   LSb16PERIF_NAND_CTL0_rb_valid_time                  2
    #define       bPERIF_NAND_CTL0_rb_valid_time               16
    #define   MSK32PERIF_NAND_CTL0_rb_valid_time                  0x0003FFFC
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_NAND_CTL1                             0x0010

    #define     BA_PERIF_NAND_CTL1_dd_page_size                0x0010
    #define     B16PERIF_NAND_CTL1_dd_page_size                0x0010
    #define   LSb32PERIF_NAND_CTL1_dd_page_size                   0
    #define   LSb16PERIF_NAND_CTL1_dd_page_size                   0
    #define       bPERIF_NAND_CTL1_dd_page_size                16
    #define   MSK32PERIF_NAND_CTL1_dd_page_size                   0x0000FFFF

    #define     BA_PERIF_NAND_CTL1_dd_page_per_block           0x0012
    #define     B16PERIF_NAND_CTL1_dd_page_per_block           0x0012
    #define   LSb32PERIF_NAND_CTL1_dd_page_per_block              16
    #define   LSb16PERIF_NAND_CTL1_dd_page_per_block              0
    #define       bPERIF_NAND_CTL1_dd_page_per_block           16
    #define   MSK32PERIF_NAND_CTL1_dd_page_per_block              0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_NAND_CTL2                             0x0014

    #define     BA_PERIF_NAND_CTL2_dd_lun_number               0x0014
    #define     B16PERIF_NAND_CTL2_dd_lun_number               0x0014
    #define   LSb32PERIF_NAND_CTL2_dd_lun_number                  0
    #define   LSb16PERIF_NAND_CTL2_dd_lun_number                  0
    #define       bPERIF_NAND_CTL2_dd_lun_number               4
    #define   MSK32PERIF_NAND_CTL2_dd_lun_number                  0x0000000F

    #define     BA_PERIF_NAND_CTL2_dd_four_addr_cycles         0x0014
    #define     B16PERIF_NAND_CTL2_dd_four_addr_cycles         0x0014
    #define   LSb32PERIF_NAND_CTL2_dd_four_addr_cycles            4
    #define   LSb16PERIF_NAND_CTL2_dd_four_addr_cycles            4
    #define       bPERIF_NAND_CTL2_dd_four_addr_cycles         1
    #define   MSK32PERIF_NAND_CTL2_dd_four_addr_cycles            0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_NAND_DEVICE_IDL                       0x0018

    #define     BA_PERIF_NAND_DEVICE_IDL_id_low                0x0018
    #define     B16PERIF_NAND_DEVICE_IDL_id_low                0x0018
    #define   LSb32PERIF_NAND_DEVICE_IDL_id_low                   0
    #define   LSb16PERIF_NAND_DEVICE_IDL_id_low                   0
    #define       bPERIF_NAND_DEVICE_IDL_id_low                32
    #define   MSK32PERIF_NAND_DEVICE_IDL_id_low                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_NAND_DEVICE_IDH                       0x001C

    #define     BA_PERIF_NAND_DEVICE_IDH_id_high               0x001C
    #define     B16PERIF_NAND_DEVICE_IDH_id_high               0x001C
    #define   LSb32PERIF_NAND_DEVICE_IDH_id_high                  0
    #define   LSb16PERIF_NAND_DEVICE_IDH_id_high                  0
    #define       bPERIF_NAND_DEVICE_IDH_id_high               8
    #define   MSK32PERIF_NAND_DEVICE_IDH_id_high                  0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_NAND_STATUS                           0x0020

    #define     BA_PERIF_NAND_STATUS_init_comp                 0x0020
    #define     B16PERIF_NAND_STATUS_init_comp                 0x0020
    #define   LSb32PERIF_NAND_STATUS_init_comp                    0
    #define   LSb16PERIF_NAND_STATUS_init_comp                    0
    #define       bPERIF_NAND_STATUS_init_comp                 1
    #define   MSK32PERIF_NAND_STATUS_init_comp                    0x00000001

    #define     BA_PERIF_NAND_STATUS_init_fail                 0x0020
    #define     B16PERIF_NAND_STATUS_init_fail                 0x0020
    #define   LSb32PERIF_NAND_STATUS_init_fail                    1
    #define   LSb16PERIF_NAND_STATUS_init_fail                    1
    #define       bPERIF_NAND_STATUS_init_fail                 1
    #define   MSK32PERIF_NAND_STATUS_init_fail                    0x00000002

    #define     BA_PERIF_NAND_STATUS_ctrl_busy                 0x0020
    #define     B16PERIF_NAND_STATUS_ctrl_busy                 0x0020
    #define   LSb32PERIF_NAND_STATUS_ctrl_busy                    2
    #define   LSb16PERIF_NAND_STATUS_ctrl_busy                    2
    #define       bPERIF_NAND_STATUS_ctrl_busy                 1
    #define   MSK32PERIF_NAND_STATUS_ctrl_busy                    0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_PERIF_RSERVED_CTRL0                         0x0024

    #define     BA_PERIF_RSERVED_CTRL0_ctrl                    0x0024
    #define     B16PERIF_RSERVED_CTRL0_ctrl                    0x0024
    #define   LSb32PERIF_RSERVED_CTRL0_ctrl                       0
    #define   LSb16PERIF_RSERVED_CTRL0_ctrl                       0
    #define       bPERIF_RSERVED_CTRL0_ctrl                    32
    #define   MSK32PERIF_RSERVED_CTRL0_ctrl                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_PERIF {
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_PHY_DBG_CTRL_perif_dbg_sel(r32)       _BFGET_(r32, 2, 0)
    #define   SET32PERIF_PHY_DBG_CTRL_perif_dbg_sel(r32,v)     _BFSET_(r32, 2, 0,v)
    #define   GET16PERIF_PHY_DBG_CTRL_perif_dbg_sel(r16)       _BFGET_(r16, 2, 0)
    #define   SET16PERIF_PHY_DBG_CTRL_perif_dbg_sel(r16,v)     _BFSET_(r16, 2, 0,v)

    #define   GET32PERIF_PHY_DBG_CTRL_SIF_MUX_SEL(r32)         _BFGET_(r32, 4, 3)
    #define   SET32PERIF_PHY_DBG_CTRL_SIF_MUX_SEL(r32,v)       _BFSET_(r32, 4, 3,v)
    #define   GET16PERIF_PHY_DBG_CTRL_SIF_MUX_SEL(r16)         _BFGET_(r16, 4, 3)
    #define   SET16PERIF_PHY_DBG_CTRL_SIF_MUX_SEL(r16,v)       _BFSET_(r16, 4, 3,v)

    #define     w32PERIF_PHY_DBG_CTRL                          {\
            UNSG32 uPHY_DBG_CTRL_perif_dbg_sel                 :  3;\
            UNSG32 uPHY_DBG_CTRL_SIF_MUX_SEL                   :  2;\
            UNSG32 RSVDx0_b5                                   : 27;\
          }
    union { UNSG32 u32PERIF_PHY_DBG_CTRL;
            struct w32PERIF_PHY_DBG_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_USB_CTRL_DISABLE_EL16(r32)            _BFGET_(r32, 0, 0)
    #define   SET32PERIF_USB_CTRL_DISABLE_EL16(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16PERIF_USB_CTRL_DISABLE_EL16(r16)            _BFGET_(r16, 0, 0)
    #define   SET16PERIF_USB_CTRL_DISABLE_EL16(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32PERIF_USB_CTRL_CTRL_MODE(r32)               _BFGET_(r32, 2, 1)
    #define   SET32PERIF_USB_CTRL_CTRL_MODE(r32,v)             _BFSET_(r32, 2, 1,v)
    #define   GET16PERIF_USB_CTRL_CTRL_MODE(r16)               _BFGET_(r16, 2, 1)
    #define   SET16PERIF_USB_CTRL_CTRL_MODE(r16,v)             _BFSET_(r16, 2, 1,v)

    #define   GET32PERIF_USB_CTRL_FORCE_PHYSTCKYRST(r32)       _BFGET_(r32, 3, 3)
    #define   SET32PERIF_USB_CTRL_FORCE_PHYSTCKYRST(r32,v)     _BFSET_(r32, 3, 3,v)
    #define   GET16PERIF_USB_CTRL_FORCE_PHYSTCKYRST(r16)       _BFGET_(r16, 3, 3)
    #define   SET16PERIF_USB_CTRL_FORCE_PHYSTCKYRST(r16,v)     _BFSET_(r16, 3, 3,v)

    #define     w32PERIF_USB_CTRL                              {\
            UNSG32 uUSB_CTRL_DISABLE_EL16                      :  1;\
            UNSG32 uUSB_CTRL_CTRL_MODE                         :  2;\
            UNSG32 uUSB_CTRL_FORCE_PHYSTCKYRST                 :  1;\
            UNSG32 RSVDx4_b4                                   : 28;\
          }
    union { UNSG32 u32PERIF_USB_CTRL;
            struct w32PERIF_USB_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_PXBAR_ASIB_SEL_NAND_EMMC(r32)         _BFGET_(r32, 0, 0)
    #define   SET32PERIF_PXBAR_ASIB_SEL_NAND_EMMC(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16PERIF_PXBAR_ASIB_SEL_NAND_EMMC(r16)         _BFGET_(r16, 0, 0)
    #define   SET16PERIF_PXBAR_ASIB_SEL_NAND_EMMC(r16,v)       _BFSET_(r16, 0, 0,v)

    #define     w32PERIF_PXBAR_ASIB_SEL                        {\
            UNSG32 uPXBAR_ASIB_SEL_NAND_EMMC                   :  1;\
            UNSG32 RSVDx8_b1                                   : 31;\
          }
    union { UNSG32 u32PERIF_PXBAR_ASIB_SEL;
            struct w32PERIF_PXBAR_ASIB_SEL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_NAND_CTL0_discovery_inhibit(r32)      _BFGET_(r32, 0, 0)
    #define   SET32PERIF_NAND_CTL0_discovery_inhibit(r32,v)    _BFSET_(r32, 0, 0,v)
    #define   GET16PERIF_NAND_CTL0_discovery_inhibit(r16)      _BFGET_(r16, 0, 0)
    #define   SET16PERIF_NAND_CTL0_discovery_inhibit(r16,v)    _BFSET_(r16, 0, 0,v)

    #define   GET32PERIF_NAND_CTL0_discovery_ignore_crc(r32)   _BFGET_(r32, 1, 1)
    #define   SET32PERIF_NAND_CTL0_discovery_ignore_crc(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16PERIF_NAND_CTL0_discovery_ignore_crc(r16)   _BFGET_(r16, 1, 1)
    #define   SET16PERIF_NAND_CTL0_discovery_ignore_crc(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32PERIF_NAND_CTL0_rb_valid_time(r32)          _BFGET_(r32,17, 2)
    #define   SET32PERIF_NAND_CTL0_rb_valid_time(r32,v)        _BFSET_(r32,17, 2,v)

    #define     w32PERIF_NAND_CTL0                             {\
            UNSG32 uNAND_CTL0_discovery_inhibit                :  1;\
            UNSG32 uNAND_CTL0_discovery_ignore_crc             :  1;\
            UNSG32 uNAND_CTL0_rb_valid_time                    : 16;\
            UNSG32 RSVDxC_b18                                  : 14;\
          }
    union { UNSG32 u32PERIF_NAND_CTL0;
            struct w32PERIF_NAND_CTL0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_NAND_CTL1_dd_page_size(r32)           _BFGET_(r32,15, 0)
    #define   SET32PERIF_NAND_CTL1_dd_page_size(r32,v)         _BFSET_(r32,15, 0,v)
    #define   GET16PERIF_NAND_CTL1_dd_page_size(r16)           _BFGET_(r16,15, 0)
    #define   SET16PERIF_NAND_CTL1_dd_page_size(r16,v)         _BFSET_(r16,15, 0,v)

    #define   GET32PERIF_NAND_CTL1_dd_page_per_block(r32)      _BFGET_(r32,31,16)
    #define   SET32PERIF_NAND_CTL1_dd_page_per_block(r32,v)    _BFSET_(r32,31,16,v)
    #define   GET16PERIF_NAND_CTL1_dd_page_per_block(r16)      _BFGET_(r16,15, 0)
    #define   SET16PERIF_NAND_CTL1_dd_page_per_block(r16,v)    _BFSET_(r16,15, 0,v)

    #define     w32PERIF_NAND_CTL1                             {\
            UNSG32 uNAND_CTL1_dd_page_size                     : 16;\
            UNSG32 uNAND_CTL1_dd_page_per_block                : 16;\
          }
    union { UNSG32 u32PERIF_NAND_CTL1;
            struct w32PERIF_NAND_CTL1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_NAND_CTL2_dd_lun_number(r32)          _BFGET_(r32, 3, 0)
    #define   SET32PERIF_NAND_CTL2_dd_lun_number(r32,v)        _BFSET_(r32, 3, 0,v)
    #define   GET16PERIF_NAND_CTL2_dd_lun_number(r16)          _BFGET_(r16, 3, 0)
    #define   SET16PERIF_NAND_CTL2_dd_lun_number(r16,v)        _BFSET_(r16, 3, 0,v)

    #define   GET32PERIF_NAND_CTL2_dd_four_addr_cycles(r32)    _BFGET_(r32, 4, 4)
    #define   SET32PERIF_NAND_CTL2_dd_four_addr_cycles(r32,v)  _BFSET_(r32, 4, 4,v)
    #define   GET16PERIF_NAND_CTL2_dd_four_addr_cycles(r16)    _BFGET_(r16, 4, 4)
    #define   SET16PERIF_NAND_CTL2_dd_four_addr_cycles(r16,v)  _BFSET_(r16, 4, 4,v)

    #define     w32PERIF_NAND_CTL2                             {\
            UNSG32 uNAND_CTL2_dd_lun_number                    :  4;\
            UNSG32 uNAND_CTL2_dd_four_addr_cycles              :  1;\
            UNSG32 RSVDx14_b5                                  : 27;\
          }
    union { UNSG32 u32PERIF_NAND_CTL2;
            struct w32PERIF_NAND_CTL2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_NAND_DEVICE_IDL_id_low(r32)           _BFGET_(r32,31, 0)
    #define   SET32PERIF_NAND_DEVICE_IDL_id_low(r32,v)         _BFSET_(r32,31, 0,v)

    #define     w32PERIF_NAND_DEVICE_IDL                       {\
            UNSG32 uNAND_DEVICE_IDL_id_low                     : 32;\
          }
    union { UNSG32 u32PERIF_NAND_DEVICE_IDL;
            struct w32PERIF_NAND_DEVICE_IDL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_NAND_DEVICE_IDH_id_high(r32)          _BFGET_(r32, 7, 0)
    #define   SET32PERIF_NAND_DEVICE_IDH_id_high(r32,v)        _BFSET_(r32, 7, 0,v)
    #define   GET16PERIF_NAND_DEVICE_IDH_id_high(r16)          _BFGET_(r16, 7, 0)
    #define   SET16PERIF_NAND_DEVICE_IDH_id_high(r16,v)        _BFSET_(r16, 7, 0,v)

    #define     w32PERIF_NAND_DEVICE_IDH                       {\
            UNSG32 uNAND_DEVICE_IDH_id_high                    :  8;\
            UNSG32 RSVDx1C_b8                                  : 24;\
          }
    union { UNSG32 u32PERIF_NAND_DEVICE_IDH;
            struct w32PERIF_NAND_DEVICE_IDH;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_NAND_STATUS_init_comp(r32)            _BFGET_(r32, 0, 0)
    #define   SET32PERIF_NAND_STATUS_init_comp(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16PERIF_NAND_STATUS_init_comp(r16)            _BFGET_(r16, 0, 0)
    #define   SET16PERIF_NAND_STATUS_init_comp(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32PERIF_NAND_STATUS_init_fail(r32)            _BFGET_(r32, 1, 1)
    #define   SET32PERIF_NAND_STATUS_init_fail(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16PERIF_NAND_STATUS_init_fail(r16)            _BFGET_(r16, 1, 1)
    #define   SET16PERIF_NAND_STATUS_init_fail(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32PERIF_NAND_STATUS_ctrl_busy(r32)            _BFGET_(r32, 2, 2)
    #define   SET32PERIF_NAND_STATUS_ctrl_busy(r32,v)          _BFSET_(r32, 2, 2,v)
    #define   GET16PERIF_NAND_STATUS_ctrl_busy(r16)            _BFGET_(r16, 2, 2)
    #define   SET16PERIF_NAND_STATUS_ctrl_busy(r16,v)          _BFSET_(r16, 2, 2,v)

    #define     w32PERIF_NAND_STATUS                           {\
            UNSG32 uNAND_STATUS_init_comp                      :  1;\
            UNSG32 uNAND_STATUS_init_fail                      :  1;\
            UNSG32 uNAND_STATUS_ctrl_busy                      :  1;\
            UNSG32 RSVDx20_b3                                  : 29;\
          }
    union { UNSG32 u32PERIF_NAND_STATUS;
            struct w32PERIF_NAND_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PERIF_RSERVED_CTRL0_ctrl(r32)               _BFGET_(r32,31, 0)
    #define   SET32PERIF_RSERVED_CTRL0_ctrl(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32PERIF_RSERVED_CTRL0                         {\
            UNSG32 uRSERVED_CTRL0_ctrl                         : 32;\
          }
    union { UNSG32 u32PERIF_RSERVED_CTRL0;
            struct w32PERIF_RSERVED_CTRL0;
          };
    ///////////////////////////////////////////////////////////
    } SIE_PERIF;

    typedef union  T32PERIF_PHY_DBG_CTRL
          { UNSG32 u32;
            struct w32PERIF_PHY_DBG_CTRL;
                 } T32PERIF_PHY_DBG_CTRL;
    typedef union  T32PERIF_USB_CTRL
          { UNSG32 u32;
            struct w32PERIF_USB_CTRL;
                 } T32PERIF_USB_CTRL;
    typedef union  T32PERIF_PXBAR_ASIB_SEL
          { UNSG32 u32;
            struct w32PERIF_PXBAR_ASIB_SEL;
                 } T32PERIF_PXBAR_ASIB_SEL;
    typedef union  T32PERIF_NAND_CTL0
          { UNSG32 u32;
            struct w32PERIF_NAND_CTL0;
                 } T32PERIF_NAND_CTL0;
    typedef union  T32PERIF_NAND_CTL1
          { UNSG32 u32;
            struct w32PERIF_NAND_CTL1;
                 } T32PERIF_NAND_CTL1;
    typedef union  T32PERIF_NAND_CTL2
          { UNSG32 u32;
            struct w32PERIF_NAND_CTL2;
                 } T32PERIF_NAND_CTL2;
    typedef union  T32PERIF_NAND_DEVICE_IDL
          { UNSG32 u32;
            struct w32PERIF_NAND_DEVICE_IDL;
                 } T32PERIF_NAND_DEVICE_IDL;
    typedef union  T32PERIF_NAND_DEVICE_IDH
          { UNSG32 u32;
            struct w32PERIF_NAND_DEVICE_IDH;
                 } T32PERIF_NAND_DEVICE_IDH;
    typedef union  T32PERIF_NAND_STATUS
          { UNSG32 u32;
            struct w32PERIF_NAND_STATUS;
                 } T32PERIF_NAND_STATUS;
    typedef union  T32PERIF_RSERVED_CTRL0
          { UNSG32 u32;
            struct w32PERIF_RSERVED_CTRL0;
                 } T32PERIF_RSERVED_CTRL0;
    ///////////////////////////////////////////////////////////

    typedef union  TPERIF_PHY_DBG_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_PHY_DBG_CTRL;
                   };
                 } TPERIF_PHY_DBG_CTRL;
    typedef union  TPERIF_USB_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_USB_CTRL;
                   };
                 } TPERIF_USB_CTRL;
    typedef union  TPERIF_PXBAR_ASIB_SEL
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_PXBAR_ASIB_SEL;
                   };
                 } TPERIF_PXBAR_ASIB_SEL;
    typedef union  TPERIF_NAND_CTL0
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_NAND_CTL0;
                   };
                 } TPERIF_NAND_CTL0;
    typedef union  TPERIF_NAND_CTL1
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_NAND_CTL1;
                   };
                 } TPERIF_NAND_CTL1;
    typedef union  TPERIF_NAND_CTL2
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_NAND_CTL2;
                   };
                 } TPERIF_NAND_CTL2;
    typedef union  TPERIF_NAND_DEVICE_IDL
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_NAND_DEVICE_IDL;
                   };
                 } TPERIF_NAND_DEVICE_IDL;
    typedef union  TPERIF_NAND_DEVICE_IDH
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_NAND_DEVICE_IDH;
                   };
                 } TPERIF_NAND_DEVICE_IDH;
    typedef union  TPERIF_NAND_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_NAND_STATUS;
                   };
                 } TPERIF_NAND_STATUS;
    typedef union  TPERIF_RSERVED_CTRL0
          { UNSG32 u32[1];
            struct {
            struct w32PERIF_RSERVED_CTRL0;
                   };
                 } TPERIF_RSERVED_CTRL0;

    ///////////////////////////////////////////////////////////
     SIGN32 PERIF_drvrd(SIE_PERIF *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 PERIF_drvwr(SIE_PERIF *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void PERIF_reset(SIE_PERIF *p);
     SIGN32 PERIF_cmp  (SIE_PERIF *p, SIE_PERIF *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define PERIF_check(p,pie,pfx,hLOG) PERIF_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define PERIF_print(p,    pfx,hLOG) PERIF_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: PERIF
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE ADC                                      (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P-)
///               %unsigned 3  SEL_CHA                   0x0
///                                    ###
///                                    * ADC analog input selection signals
///                                    * 0
///                                    ###
///               %unsigned 1  PD_ADC                    0x0
///                                    ###
///                                    * Power down ADC(Active H).
///                                    ###
///               %unsigned 2  MODE                      0x0
///                                    ###
///                                    * 00: Single conversion. Every time 1 to SOC_trigger register it will trigger soc cycle of ADC. At end of conversion interrupt is raised.
///                                    * Not used when either in freerun_mode or comp_mode
///                                    * 01: freerun_mode. ADC automatically triggered at every EOC. Updates DATA_OUT with successive adc output. No interrupt is generated.
///                                    * 10: comparison_mode. ADC is automatically triggered at every EOC until the adc out falls within the window set by DATA_LOW, DATA_HIGH and this adc value is latched to DATA_OUT register and interrupt is raised. No further conversions happen until interrupt is cleared.
///                                    * 11 : Rsvd
///                                    ###
///               %unsigned 1  SOC_trigger               0x0
///                                    ###
///                                    * Writing 1 to this register will trigger SOC of ADC. Used only in single conversion mode (MODE=00).
///                                    ###
///               %unsigned 1  EN_VCM                    0x0
///                                    ###
///                                    * Control Signal for ADC VCM Buffer Block
///                                    * EN_VCM=1, VCM Buffer Block Power ON;
///                                    * EN_VCM=0, VCM Buffer Block Power Down (Only in 1MSPS Differential Mode EN_VCM could be low; power down VCM Buffer will save power but decrease performance).
///                                    ###
///               %unsigned 1  SEL_CMP                   0x0
///                                    ###
///                                    * Control signal for ADC CMP selection:
///                                    * SEL_CMP=1, Conversional CMP is selected.
///                                    * SEL_CMP=0, Dynamic CMP is selected.
///                                    ###
///               %unsigned 1  SEL_SPEED                 0x1
///                                    ###
///                                    * Control signal for ADC conversion speed.
///                                    * SEL_SPEED=0: 1MSPS mode @ 16Mhz clock;
///                                    * SEL_SPEED=1: 5MSPS mode @ 80Mhz clock
///                                    * (please set SEL_CMP=0 and EN_VCM=1 ).
///                                    ###
///               %unsigned 1  SEL_DIFF                  0x0
///                                    ###
///                                    * Control signal for ADC MODE:
///                                    * SEL_DIFF=1, Differential Mode
///                                    * SEL_DIFF=0, Single-ended Mode
///                                    ###
///               %unsigned 1  EN_CAL                    0x0
///                                    ###
///                                    * Control signal for ADC offset calibration, the calibration is started by a low to high transition of EN_CAL.
///                                    ###
///               %unsigned 1  INTR_MSK                  0x0
///                                    ###
///                                    * When 1 interrupt is masked
///                                    ###
///               %unsigned 1  INTR_CLR                  0x0
///                                    ###
///                                    * When 1 is written interrupt is cleared.
///                                    ###
///               %unsigned 1  TEST_EN                   0x0
///                                    ###
///                                    * Functional test mode. Program the expected range in DATA_LOW, DATA_HIGH. Write 1 to SOC. Monitor FAIL status.
///                                    ###
///               %%        17         # Stuffing bits...
///     @ 0x00004 STS                  (R-)
///               %unsigned 12 DATA_OUT                  
///                                    ###
///                                    * 12bit digital output
///                                    ###
///               %unsigned 1  CAL_DONE                  
///                                    ###
///                                    * Flag for calibration:
///                                    * CAL_DONE=1, Calibration is finished
///                                    * CAL_DONE=0, Calibration is not done.
///                                    ###
///               %unsigned 1  EOC                       
///                                    ###
///                                    * Outputs data synchronization signal
///                                    ###
///               %%        18         # Stuffing bits...
///     @ 0x00008 FUNC_TEST_OUT        (RW)
///               %unsigned 1  FAIL                      0x0
///                                    ###
///                                    * 1 bit Indicates if ADC functional test failed.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x0000C COMP_MODE            (P)
///               %unsigned 12 DATA_HIGH                 0x0
///                                    ###
///                                    * High value of expected ADC output value during comparator mode of operation or during functional test.
///                                    ###
///               %unsigned 12 DATA_LOW                  0x0
///                                    ###
///                                    * Low value of expected ADC output value during comparator mode of operation or during functional test.
///                                    ###
///               %%        8          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      54b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ADC
#define h_ADC (){}

    #define     RA_ADC_CTRL                                    0x0000

    #define     BA_ADC_CTRL_SEL_CHA                            0x0000
    #define     B16ADC_CTRL_SEL_CHA                            0x0000
    #define   LSb32ADC_CTRL_SEL_CHA                               0
    #define   LSb16ADC_CTRL_SEL_CHA                               0
    #define       bADC_CTRL_SEL_CHA                            3
    #define   MSK32ADC_CTRL_SEL_CHA                               0x00000007

    #define     BA_ADC_CTRL_PD_ADC                             0x0000
    #define     B16ADC_CTRL_PD_ADC                             0x0000
    #define   LSb32ADC_CTRL_PD_ADC                                3
    #define   LSb16ADC_CTRL_PD_ADC                                3
    #define       bADC_CTRL_PD_ADC                             1
    #define   MSK32ADC_CTRL_PD_ADC                                0x00000008

    #define     BA_ADC_CTRL_MODE                               0x0000
    #define     B16ADC_CTRL_MODE                               0x0000
    #define   LSb32ADC_CTRL_MODE                                  4
    #define   LSb16ADC_CTRL_MODE                                  4
    #define       bADC_CTRL_MODE                               2
    #define   MSK32ADC_CTRL_MODE                                  0x00000030

    #define     BA_ADC_CTRL_SOC_trigger                        0x0000
    #define     B16ADC_CTRL_SOC_trigger                        0x0000
    #define   LSb32ADC_CTRL_SOC_trigger                           6
    #define   LSb16ADC_CTRL_SOC_trigger                           6
    #define       bADC_CTRL_SOC_trigger                        1
    #define   MSK32ADC_CTRL_SOC_trigger                           0x00000040

    #define     BA_ADC_CTRL_EN_VCM                             0x0000
    #define     B16ADC_CTRL_EN_VCM                             0x0000
    #define   LSb32ADC_CTRL_EN_VCM                                7
    #define   LSb16ADC_CTRL_EN_VCM                                7
    #define       bADC_CTRL_EN_VCM                             1
    #define   MSK32ADC_CTRL_EN_VCM                                0x00000080

    #define     BA_ADC_CTRL_SEL_CMP                            0x0001
    #define     B16ADC_CTRL_SEL_CMP                            0x0000
    #define   LSb32ADC_CTRL_SEL_CMP                               8
    #define   LSb16ADC_CTRL_SEL_CMP                               8
    #define       bADC_CTRL_SEL_CMP                            1
    #define   MSK32ADC_CTRL_SEL_CMP                               0x00000100

    #define     BA_ADC_CTRL_SEL_SPEED                          0x0001
    #define     B16ADC_CTRL_SEL_SPEED                          0x0000
    #define   LSb32ADC_CTRL_SEL_SPEED                             9
    #define   LSb16ADC_CTRL_SEL_SPEED                             9
    #define       bADC_CTRL_SEL_SPEED                          1
    #define   MSK32ADC_CTRL_SEL_SPEED                             0x00000200

    #define     BA_ADC_CTRL_SEL_DIFF                           0x0001
    #define     B16ADC_CTRL_SEL_DIFF                           0x0000
    #define   LSb32ADC_CTRL_SEL_DIFF                              10
    #define   LSb16ADC_CTRL_SEL_DIFF                              10
    #define       bADC_CTRL_SEL_DIFF                           1
    #define   MSK32ADC_CTRL_SEL_DIFF                              0x00000400

    #define     BA_ADC_CTRL_EN_CAL                             0x0001
    #define     B16ADC_CTRL_EN_CAL                             0x0000
    #define   LSb32ADC_CTRL_EN_CAL                                11
    #define   LSb16ADC_CTRL_EN_CAL                                11
    #define       bADC_CTRL_EN_CAL                             1
    #define   MSK32ADC_CTRL_EN_CAL                                0x00000800

    #define     BA_ADC_CTRL_INTR_MSK                           0x0001
    #define     B16ADC_CTRL_INTR_MSK                           0x0000
    #define   LSb32ADC_CTRL_INTR_MSK                              12
    #define   LSb16ADC_CTRL_INTR_MSK                              12
    #define       bADC_CTRL_INTR_MSK                           1
    #define   MSK32ADC_CTRL_INTR_MSK                              0x00001000

    #define     BA_ADC_CTRL_INTR_CLR                           0x0001
    #define     B16ADC_CTRL_INTR_CLR                           0x0000
    #define   LSb32ADC_CTRL_INTR_CLR                              13
    #define   LSb16ADC_CTRL_INTR_CLR                              13
    #define       bADC_CTRL_INTR_CLR                           1
    #define   MSK32ADC_CTRL_INTR_CLR                              0x00002000

    #define     BA_ADC_CTRL_TEST_EN                            0x0001
    #define     B16ADC_CTRL_TEST_EN                            0x0000
    #define   LSb32ADC_CTRL_TEST_EN                               14
    #define   LSb16ADC_CTRL_TEST_EN                               14
    #define       bADC_CTRL_TEST_EN                            1
    #define   MSK32ADC_CTRL_TEST_EN                               0x00004000
    ///////////////////////////////////////////////////////////
    #define     RA_ADC_STS                                     0x0004

    #define     BA_ADC_STS_DATA_OUT                            0x0004
    #define     B16ADC_STS_DATA_OUT                            0x0004
    #define   LSb32ADC_STS_DATA_OUT                               0
    #define   LSb16ADC_STS_DATA_OUT                               0
    #define       bADC_STS_DATA_OUT                            12
    #define   MSK32ADC_STS_DATA_OUT                               0x00000FFF

    #define     BA_ADC_STS_CAL_DONE                            0x0005
    #define     B16ADC_STS_CAL_DONE                            0x0004
    #define   LSb32ADC_STS_CAL_DONE                               12
    #define   LSb16ADC_STS_CAL_DONE                               12
    #define       bADC_STS_CAL_DONE                            1
    #define   MSK32ADC_STS_CAL_DONE                               0x00001000

    #define     BA_ADC_STS_EOC                                 0x0005
    #define     B16ADC_STS_EOC                                 0x0004
    #define   LSb32ADC_STS_EOC                                    13
    #define   LSb16ADC_STS_EOC                                    13
    #define       bADC_STS_EOC                                 1
    #define   MSK32ADC_STS_EOC                                    0x00002000
    ///////////////////////////////////////////////////////////
    #define     RA_ADC_FUNC_TEST_OUT                           0x0008

    #define     BA_ADC_FUNC_TEST_OUT_FAIL                      0x0008
    #define     B16ADC_FUNC_TEST_OUT_FAIL                      0x0008
    #define   LSb32ADC_FUNC_TEST_OUT_FAIL                         0
    #define   LSb16ADC_FUNC_TEST_OUT_FAIL                         0
    #define       bADC_FUNC_TEST_OUT_FAIL                      1
    #define   MSK32ADC_FUNC_TEST_OUT_FAIL                         0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_ADC_COMP_MODE                               0x000C

    #define     BA_ADC_COMP_MODE_DATA_HIGH                     0x000C
    #define     B16ADC_COMP_MODE_DATA_HIGH                     0x000C
    #define   LSb32ADC_COMP_MODE_DATA_HIGH                        0
    #define   LSb16ADC_COMP_MODE_DATA_HIGH                        0
    #define       bADC_COMP_MODE_DATA_HIGH                     12
    #define   MSK32ADC_COMP_MODE_DATA_HIGH                        0x00000FFF

    #define     BA_ADC_COMP_MODE_DATA_LOW                      0x000D
    #define     B16ADC_COMP_MODE_DATA_LOW                      0x000C
    #define   LSb32ADC_COMP_MODE_DATA_LOW                         12
    #define   LSb16ADC_COMP_MODE_DATA_LOW                         12
    #define       bADC_COMP_MODE_DATA_LOW                      12
    #define   MSK32ADC_COMP_MODE_DATA_LOW                         0x00FFF000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ADC {
    ///////////////////////////////////////////////////////////
    #define   GET32ADC_CTRL_SEL_CHA(r32)                       _BFGET_(r32, 2, 0)
    #define   SET32ADC_CTRL_SEL_CHA(r32,v)                     _BFSET_(r32, 2, 0,v)
    #define   GET16ADC_CTRL_SEL_CHA(r16)                       _BFGET_(r16, 2, 0)
    #define   SET16ADC_CTRL_SEL_CHA(r16,v)                     _BFSET_(r16, 2, 0,v)

    #define   GET32ADC_CTRL_PD_ADC(r32)                        _BFGET_(r32, 3, 3)
    #define   SET32ADC_CTRL_PD_ADC(r32,v)                      _BFSET_(r32, 3, 3,v)
    #define   GET16ADC_CTRL_PD_ADC(r16)                        _BFGET_(r16, 3, 3)
    #define   SET16ADC_CTRL_PD_ADC(r16,v)                      _BFSET_(r16, 3, 3,v)

    #define   GET32ADC_CTRL_MODE(r32)                          _BFGET_(r32, 5, 4)
    #define   SET32ADC_CTRL_MODE(r32,v)                        _BFSET_(r32, 5, 4,v)
    #define   GET16ADC_CTRL_MODE(r16)                          _BFGET_(r16, 5, 4)
    #define   SET16ADC_CTRL_MODE(r16,v)                        _BFSET_(r16, 5, 4,v)

    #define   GET32ADC_CTRL_SOC_trigger(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32ADC_CTRL_SOC_trigger(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16ADC_CTRL_SOC_trigger(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16ADC_CTRL_SOC_trigger(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define   GET32ADC_CTRL_EN_VCM(r32)                        _BFGET_(r32, 7, 7)
    #define   SET32ADC_CTRL_EN_VCM(r32,v)                      _BFSET_(r32, 7, 7,v)
    #define   GET16ADC_CTRL_EN_VCM(r16)                        _BFGET_(r16, 7, 7)
    #define   SET16ADC_CTRL_EN_VCM(r16,v)                      _BFSET_(r16, 7, 7,v)

    #define   GET32ADC_CTRL_SEL_CMP(r32)                       _BFGET_(r32, 8, 8)
    #define   SET32ADC_CTRL_SEL_CMP(r32,v)                     _BFSET_(r32, 8, 8,v)
    #define   GET16ADC_CTRL_SEL_CMP(r16)                       _BFGET_(r16, 8, 8)
    #define   SET16ADC_CTRL_SEL_CMP(r16,v)                     _BFSET_(r16, 8, 8,v)

    #define   GET32ADC_CTRL_SEL_SPEED(r32)                     _BFGET_(r32, 9, 9)
    #define   SET32ADC_CTRL_SEL_SPEED(r32,v)                   _BFSET_(r32, 9, 9,v)
    #define   GET16ADC_CTRL_SEL_SPEED(r16)                     _BFGET_(r16, 9, 9)
    #define   SET16ADC_CTRL_SEL_SPEED(r16,v)                   _BFSET_(r16, 9, 9,v)

    #define   GET32ADC_CTRL_SEL_DIFF(r32)                      _BFGET_(r32,10,10)
    #define   SET32ADC_CTRL_SEL_DIFF(r32,v)                    _BFSET_(r32,10,10,v)
    #define   GET16ADC_CTRL_SEL_DIFF(r16)                      _BFGET_(r16,10,10)
    #define   SET16ADC_CTRL_SEL_DIFF(r16,v)                    _BFSET_(r16,10,10,v)

    #define   GET32ADC_CTRL_EN_CAL(r32)                        _BFGET_(r32,11,11)
    #define   SET32ADC_CTRL_EN_CAL(r32,v)                      _BFSET_(r32,11,11,v)
    #define   GET16ADC_CTRL_EN_CAL(r16)                        _BFGET_(r16,11,11)
    #define   SET16ADC_CTRL_EN_CAL(r16,v)                      _BFSET_(r16,11,11,v)

    #define   GET32ADC_CTRL_INTR_MSK(r32)                      _BFGET_(r32,12,12)
    #define   SET32ADC_CTRL_INTR_MSK(r32,v)                    _BFSET_(r32,12,12,v)
    #define   GET16ADC_CTRL_INTR_MSK(r16)                      _BFGET_(r16,12,12)
    #define   SET16ADC_CTRL_INTR_MSK(r16,v)                    _BFSET_(r16,12,12,v)

    #define   GET32ADC_CTRL_INTR_CLR(r32)                      _BFGET_(r32,13,13)
    #define   SET32ADC_CTRL_INTR_CLR(r32,v)                    _BFSET_(r32,13,13,v)
    #define   GET16ADC_CTRL_INTR_CLR(r16)                      _BFGET_(r16,13,13)
    #define   SET16ADC_CTRL_INTR_CLR(r16,v)                    _BFSET_(r16,13,13,v)

    #define   GET32ADC_CTRL_TEST_EN(r32)                       _BFGET_(r32,14,14)
    #define   SET32ADC_CTRL_TEST_EN(r32,v)                     _BFSET_(r32,14,14,v)
    #define   GET16ADC_CTRL_TEST_EN(r16)                       _BFGET_(r16,14,14)
    #define   SET16ADC_CTRL_TEST_EN(r16,v)                     _BFSET_(r16,14,14,v)

    #define     w32ADC_CTRL                                    {\
            UNSG32 uCTRL_SEL_CHA                               :  3;\
            UNSG32 uCTRL_PD_ADC                                :  1;\
            UNSG32 uCTRL_MODE                                  :  2;\
            UNSG32 uCTRL_SOC_trigger                           :  1;\
            UNSG32 uCTRL_EN_VCM                                :  1;\
            UNSG32 uCTRL_SEL_CMP                               :  1;\
            UNSG32 uCTRL_SEL_SPEED                             :  1;\
            UNSG32 uCTRL_SEL_DIFF                              :  1;\
            UNSG32 uCTRL_EN_CAL                                :  1;\
            UNSG32 uCTRL_INTR_MSK                              :  1;\
            UNSG32 uCTRL_INTR_CLR                              :  1;\
            UNSG32 uCTRL_TEST_EN                               :  1;\
            UNSG32 RSVDx0_b15                                  : 17;\
          }
    union { UNSG32 u32ADC_CTRL;
            struct w32ADC_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32ADC_STS_DATA_OUT(r32)                       _BFGET_(r32,11, 0)
    #define   SET32ADC_STS_DATA_OUT(r32,v)                     _BFSET_(r32,11, 0,v)
    #define   GET16ADC_STS_DATA_OUT(r16)                       _BFGET_(r16,11, 0)
    #define   SET16ADC_STS_DATA_OUT(r16,v)                     _BFSET_(r16,11, 0,v)

    #define   GET32ADC_STS_CAL_DONE(r32)                       _BFGET_(r32,12,12)
    #define   SET32ADC_STS_CAL_DONE(r32,v)                     _BFSET_(r32,12,12,v)
    #define   GET16ADC_STS_CAL_DONE(r16)                       _BFGET_(r16,12,12)
    #define   SET16ADC_STS_CAL_DONE(r16,v)                     _BFSET_(r16,12,12,v)

    #define   GET32ADC_STS_EOC(r32)                            _BFGET_(r32,13,13)
    #define   SET32ADC_STS_EOC(r32,v)                          _BFSET_(r32,13,13,v)
    #define   GET16ADC_STS_EOC(r16)                            _BFGET_(r16,13,13)
    #define   SET16ADC_STS_EOC(r16,v)                          _BFSET_(r16,13,13,v)

    #define     w32ADC_STS                                     {\
            UNSG32 uSTS_DATA_OUT                               : 12;\
            UNSG32 uSTS_CAL_DONE                               :  1;\
            UNSG32 uSTS_EOC                                    :  1;\
            UNSG32 RSVDx4_b14                                  : 18;\
          }
    union { UNSG32 u32ADC_STS;
            struct w32ADC_STS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32ADC_FUNC_TEST_OUT_FAIL(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32ADC_FUNC_TEST_OUT_FAIL(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16ADC_FUNC_TEST_OUT_FAIL(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16ADC_FUNC_TEST_OUT_FAIL(r16,v)               _BFSET_(r16, 0, 0,v)

    #define     w32ADC_FUNC_TEST_OUT                           {\
            UNSG32 uFUNC_TEST_OUT_FAIL                         :  1;\
            UNSG32 RSVDx8_b1                                   : 31;\
          }
    union { UNSG32 u32ADC_FUNC_TEST_OUT;
            struct w32ADC_FUNC_TEST_OUT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32ADC_COMP_MODE_DATA_HIGH(r32)                _BFGET_(r32,11, 0)
    #define   SET32ADC_COMP_MODE_DATA_HIGH(r32,v)              _BFSET_(r32,11, 0,v)
    #define   GET16ADC_COMP_MODE_DATA_HIGH(r16)                _BFGET_(r16,11, 0)
    #define   SET16ADC_COMP_MODE_DATA_HIGH(r16,v)              _BFSET_(r16,11, 0,v)

    #define   GET32ADC_COMP_MODE_DATA_LOW(r32)                 _BFGET_(r32,23,12)
    #define   SET32ADC_COMP_MODE_DATA_LOW(r32,v)               _BFSET_(r32,23,12,v)

    #define     w32ADC_COMP_MODE                               {\
            UNSG32 uCOMP_MODE_DATA_HIGH                        : 12;\
            UNSG32 uCOMP_MODE_DATA_LOW                         : 12;\
            UNSG32 RSVDxC_b24                                  :  8;\
          }
    union { UNSG32 u32ADC_COMP_MODE;
            struct w32ADC_COMP_MODE;
          };
    ///////////////////////////////////////////////////////////
    } SIE_ADC;

    typedef union  T32ADC_CTRL
          { UNSG32 u32;
            struct w32ADC_CTRL;
                 } T32ADC_CTRL;
    typedef union  T32ADC_STS
          { UNSG32 u32;
            struct w32ADC_STS;
                 } T32ADC_STS;
    typedef union  T32ADC_FUNC_TEST_OUT
          { UNSG32 u32;
            struct w32ADC_FUNC_TEST_OUT;
                 } T32ADC_FUNC_TEST_OUT;
    typedef union  T32ADC_COMP_MODE
          { UNSG32 u32;
            struct w32ADC_COMP_MODE;
                 } T32ADC_COMP_MODE;
    ///////////////////////////////////////////////////////////

    typedef union  TADC_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32ADC_CTRL;
                   };
                 } TADC_CTRL;
    typedef union  TADC_STS
          { UNSG32 u32[1];
            struct {
            struct w32ADC_STS;
                   };
                 } TADC_STS;
    typedef union  TADC_FUNC_TEST_OUT
          { UNSG32 u32[1];
            struct {
            struct w32ADC_FUNC_TEST_OUT;
                   };
                 } TADC_FUNC_TEST_OUT;
    typedef union  TADC_COMP_MODE
          { UNSG32 u32[1];
            struct {
            struct w32ADC_COMP_MODE;
                   };
                 } TADC_COMP_MODE;

    ///////////////////////////////////////////////////////////
     SIGN32 ADC_drvrd(SIE_ADC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ADC_drvwr(SIE_ADC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ADC_reset(SIE_ADC *p);
     SIGN32 ADC_cmp  (SIE_ADC *p, SIE_ADC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ADC_check(p,pie,pfx,hLOG) ADC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ADC_print(p,    pfx,hLOG) ADC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ADC
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE PVT_Sens                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P-)
///               %unsigned 1  PD                        0x0
///                                    ###
///                                    * Sensor power down while PD=1.
///                                    ###
///               %unsigned 1  EN                        0x0
///                                    ###
///                                    * Enable clock to PVT Sensor when EN=1
///                                    ###
///               %unsigned 1  T_SEL                     0x0
///                                    ###
///                                    * Select temp. sensor. T_SEL=1 enable.
///                                    ###
///               %unsigned 1  V_SEL                     0x0
///                                    ###
///                                    * Select voltage sensor. V_SEL=1 enable.
///                                    ###
///               %unsigned 4  TRIM                      0x0
///                                    ###
///                                    * Trimming for internal reference voltage.
///                                    ###
///               %unsigned 1  NMOS_SEL                  0x0
///                                    ###
///                                    * Select process sensor for 0.8V core NMOS. NMOS_SEL=1 enable.
///                                    ###
///               %unsigned 1  PMOS_SEL                  0x0
///                                    ###
///                                    * Select process sensor for 0.8V core PMOS. PMOS_SEL=1 enable.
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00004 STS                  (R-)
///               %unsigned 12 BN                        
///                                    ###
///                                    * 12bit digital output.
///                                    ###
///               %unsigned 1  EOC                       
///                                    ###
///                                    * Digital output available indicator. EOC=1 available.
///                                    ###
///               %unsigned 3  NMOS                      
///                                    ###
///                                    * Bit [0] =1. 0.8V core NMOS typical corner indicator.
///                                    * Bit [1] = 1. 0.8V core NMOS fast corner indicator.
///                                    * Bit [2]=1. 0.8V core NMOS slow corner indicator.
///                                    ###
///               %unsigned 3  PMOS                      
///                                    ###
///                                    * Bit [0] =1. 0.8V core PMOS typical corner indicator.
///                                    * Bit [1] = 1. 0.8V core PMOS fast corner indicator.
///                                    * Bit [2]=1. 0.8V core PMOS slow corner indicator.
///                                    ###
///               %%        13         # Stuffing bits...
///     @ 0x00008 TEST                 (P)
///               %unsigned 1  ENABLE                    0x0
///                                    ###
///                                    * Connected to TSTCON input of PVT Sensor.
///                                    * 1= IP will enter into test mode.
///                                    ###
///               %unsigned 1  FAIL                      0x0
///                                    ###
///                                    * Reserved
///                                    ###
///               %unsigned 12 TEST_DATA_HIGH            0x0
///                                    ###
///                                    * Reserved
///                                    ###
///               %unsigned 12 TEST_DATA_LOW             0x0
///                                    ###
///                                    * Reserved
///                                    ###
///               %%        6          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      12B, bits:      55b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_PVT_Sens
#define h_PVT_Sens (){}

    #define     RA_PVT_Sens_CTRL                               0x0000

    #define     BA_PVT_Sens_CTRL_PD                            0x0000
    #define     B16PVT_Sens_CTRL_PD                            0x0000
    #define   LSb32PVT_Sens_CTRL_PD                               0
    #define   LSb16PVT_Sens_CTRL_PD                               0
    #define       bPVT_Sens_CTRL_PD                            1
    #define   MSK32PVT_Sens_CTRL_PD                               0x00000001

    #define     BA_PVT_Sens_CTRL_EN                            0x0000
    #define     B16PVT_Sens_CTRL_EN                            0x0000
    #define   LSb32PVT_Sens_CTRL_EN                               1
    #define   LSb16PVT_Sens_CTRL_EN                               1
    #define       bPVT_Sens_CTRL_EN                            1
    #define   MSK32PVT_Sens_CTRL_EN                               0x00000002

    #define     BA_PVT_Sens_CTRL_T_SEL                         0x0000
    #define     B16PVT_Sens_CTRL_T_SEL                         0x0000
    #define   LSb32PVT_Sens_CTRL_T_SEL                            2
    #define   LSb16PVT_Sens_CTRL_T_SEL                            2
    #define       bPVT_Sens_CTRL_T_SEL                         1
    #define   MSK32PVT_Sens_CTRL_T_SEL                            0x00000004

    #define     BA_PVT_Sens_CTRL_V_SEL                         0x0000
    #define     B16PVT_Sens_CTRL_V_SEL                         0x0000
    #define   LSb32PVT_Sens_CTRL_V_SEL                            3
    #define   LSb16PVT_Sens_CTRL_V_SEL                            3
    #define       bPVT_Sens_CTRL_V_SEL                         1
    #define   MSK32PVT_Sens_CTRL_V_SEL                            0x00000008

    #define     BA_PVT_Sens_CTRL_TRIM                          0x0000
    #define     B16PVT_Sens_CTRL_TRIM                          0x0000
    #define   LSb32PVT_Sens_CTRL_TRIM                             4
    #define   LSb16PVT_Sens_CTRL_TRIM                             4
    #define       bPVT_Sens_CTRL_TRIM                          4
    #define   MSK32PVT_Sens_CTRL_TRIM                             0x000000F0

    #define     BA_PVT_Sens_CTRL_NMOS_SEL                      0x0001
    #define     B16PVT_Sens_CTRL_NMOS_SEL                      0x0000
    #define   LSb32PVT_Sens_CTRL_NMOS_SEL                         8
    #define   LSb16PVT_Sens_CTRL_NMOS_SEL                         8
    #define       bPVT_Sens_CTRL_NMOS_SEL                      1
    #define   MSK32PVT_Sens_CTRL_NMOS_SEL                         0x00000100

    #define     BA_PVT_Sens_CTRL_PMOS_SEL                      0x0001
    #define     B16PVT_Sens_CTRL_PMOS_SEL                      0x0000
    #define   LSb32PVT_Sens_CTRL_PMOS_SEL                         9
    #define   LSb16PVT_Sens_CTRL_PMOS_SEL                         9
    #define       bPVT_Sens_CTRL_PMOS_SEL                      1
    #define   MSK32PVT_Sens_CTRL_PMOS_SEL                         0x00000200
    ///////////////////////////////////////////////////////////
    #define     RA_PVT_Sens_STS                                0x0004

    #define     BA_PVT_Sens_STS_BN                             0x0004
    #define     B16PVT_Sens_STS_BN                             0x0004
    #define   LSb32PVT_Sens_STS_BN                                0
    #define   LSb16PVT_Sens_STS_BN                                0
    #define       bPVT_Sens_STS_BN                             12
    #define   MSK32PVT_Sens_STS_BN                                0x00000FFF

    #define     BA_PVT_Sens_STS_EOC                            0x0005
    #define     B16PVT_Sens_STS_EOC                            0x0004
    #define   LSb32PVT_Sens_STS_EOC                               12
    #define   LSb16PVT_Sens_STS_EOC                               12
    #define       bPVT_Sens_STS_EOC                            1
    #define   MSK32PVT_Sens_STS_EOC                               0x00001000

    #define     BA_PVT_Sens_STS_NMOS                           0x0005
    #define     B16PVT_Sens_STS_NMOS                           0x0004
    #define   LSb32PVT_Sens_STS_NMOS                              13
    #define   LSb16PVT_Sens_STS_NMOS                              13
    #define       bPVT_Sens_STS_NMOS                           3
    #define   MSK32PVT_Sens_STS_NMOS                              0x0000E000

    #define     BA_PVT_Sens_STS_PMOS                           0x0006
    #define     B16PVT_Sens_STS_PMOS                           0x0006
    #define   LSb32PVT_Sens_STS_PMOS                              16
    #define   LSb16PVT_Sens_STS_PMOS                              0
    #define       bPVT_Sens_STS_PMOS                           3
    #define   MSK32PVT_Sens_STS_PMOS                              0x00070000
    ///////////////////////////////////////////////////////////
    #define     RA_PVT_Sens_TEST                               0x0008

    #define     BA_PVT_Sens_TEST_ENABLE                        0x0008
    #define     B16PVT_Sens_TEST_ENABLE                        0x0008
    #define   LSb32PVT_Sens_TEST_ENABLE                           0
    #define   LSb16PVT_Sens_TEST_ENABLE                           0
    #define       bPVT_Sens_TEST_ENABLE                        1
    #define   MSK32PVT_Sens_TEST_ENABLE                           0x00000001

    #define     BA_PVT_Sens_TEST_FAIL                          0x0008
    #define     B16PVT_Sens_TEST_FAIL                          0x0008
    #define   LSb32PVT_Sens_TEST_FAIL                             1
    #define   LSb16PVT_Sens_TEST_FAIL                             1
    #define       bPVT_Sens_TEST_FAIL                          1
    #define   MSK32PVT_Sens_TEST_FAIL                             0x00000002

    #define     BA_PVT_Sens_TEST_TEST_DATA_HIGH                0x0008
    #define     B16PVT_Sens_TEST_TEST_DATA_HIGH                0x0008
    #define   LSb32PVT_Sens_TEST_TEST_DATA_HIGH                   2
    #define   LSb16PVT_Sens_TEST_TEST_DATA_HIGH                   2
    #define       bPVT_Sens_TEST_TEST_DATA_HIGH                12
    #define   MSK32PVT_Sens_TEST_TEST_DATA_HIGH                   0x00003FFC

    #define     BA_PVT_Sens_TEST_TEST_DATA_LOW                 0x0009
    #define     B16PVT_Sens_TEST_TEST_DATA_LOW                 0x0008
    #define   LSb32PVT_Sens_TEST_TEST_DATA_LOW                    14
    #define   LSb16PVT_Sens_TEST_TEST_DATA_LOW                    14
    #define       bPVT_Sens_TEST_TEST_DATA_LOW                 12
    #define   MSK32PVT_Sens_TEST_TEST_DATA_LOW                    0x03FFC000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_PVT_Sens {
    ///////////////////////////////////////////////////////////
    #define   GET32PVT_Sens_CTRL_PD(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32PVT_Sens_CTRL_PD(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16PVT_Sens_CTRL_PD(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16PVT_Sens_CTRL_PD(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32PVT_Sens_CTRL_EN(r32)                       _BFGET_(r32, 1, 1)
    #define   SET32PVT_Sens_CTRL_EN(r32,v)                     _BFSET_(r32, 1, 1,v)
    #define   GET16PVT_Sens_CTRL_EN(r16)                       _BFGET_(r16, 1, 1)
    #define   SET16PVT_Sens_CTRL_EN(r16,v)                     _BFSET_(r16, 1, 1,v)

    #define   GET32PVT_Sens_CTRL_T_SEL(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32PVT_Sens_CTRL_T_SEL(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16PVT_Sens_CTRL_T_SEL(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16PVT_Sens_CTRL_T_SEL(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32PVT_Sens_CTRL_V_SEL(r32)                    _BFGET_(r32, 3, 3)
    #define   SET32PVT_Sens_CTRL_V_SEL(r32,v)                  _BFSET_(r32, 3, 3,v)
    #define   GET16PVT_Sens_CTRL_V_SEL(r16)                    _BFGET_(r16, 3, 3)
    #define   SET16PVT_Sens_CTRL_V_SEL(r16,v)                  _BFSET_(r16, 3, 3,v)

    #define   GET32PVT_Sens_CTRL_TRIM(r32)                     _BFGET_(r32, 7, 4)
    #define   SET32PVT_Sens_CTRL_TRIM(r32,v)                   _BFSET_(r32, 7, 4,v)
    #define   GET16PVT_Sens_CTRL_TRIM(r16)                     _BFGET_(r16, 7, 4)
    #define   SET16PVT_Sens_CTRL_TRIM(r16,v)                   _BFSET_(r16, 7, 4,v)

    #define   GET32PVT_Sens_CTRL_NMOS_SEL(r32)                 _BFGET_(r32, 8, 8)
    #define   SET32PVT_Sens_CTRL_NMOS_SEL(r32,v)               _BFSET_(r32, 8, 8,v)
    #define   GET16PVT_Sens_CTRL_NMOS_SEL(r16)                 _BFGET_(r16, 8, 8)
    #define   SET16PVT_Sens_CTRL_NMOS_SEL(r16,v)               _BFSET_(r16, 8, 8,v)

    #define   GET32PVT_Sens_CTRL_PMOS_SEL(r32)                 _BFGET_(r32, 9, 9)
    #define   SET32PVT_Sens_CTRL_PMOS_SEL(r32,v)               _BFSET_(r32, 9, 9,v)
    #define   GET16PVT_Sens_CTRL_PMOS_SEL(r16)                 _BFGET_(r16, 9, 9)
    #define   SET16PVT_Sens_CTRL_PMOS_SEL(r16,v)               _BFSET_(r16, 9, 9,v)

    #define     w32PVT_Sens_CTRL                               {\
            UNSG32 uCTRL_PD                                    :  1;\
            UNSG32 uCTRL_EN                                    :  1;\
            UNSG32 uCTRL_T_SEL                                 :  1;\
            UNSG32 uCTRL_V_SEL                                 :  1;\
            UNSG32 uCTRL_TRIM                                  :  4;\
            UNSG32 uCTRL_NMOS_SEL                              :  1;\
            UNSG32 uCTRL_PMOS_SEL                              :  1;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32PVT_Sens_CTRL;
            struct w32PVT_Sens_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PVT_Sens_STS_BN(r32)                        _BFGET_(r32,11, 0)
    #define   SET32PVT_Sens_STS_BN(r32,v)                      _BFSET_(r32,11, 0,v)
    #define   GET16PVT_Sens_STS_BN(r16)                        _BFGET_(r16,11, 0)
    #define   SET16PVT_Sens_STS_BN(r16,v)                      _BFSET_(r16,11, 0,v)

    #define   GET32PVT_Sens_STS_EOC(r32)                       _BFGET_(r32,12,12)
    #define   SET32PVT_Sens_STS_EOC(r32,v)                     _BFSET_(r32,12,12,v)
    #define   GET16PVT_Sens_STS_EOC(r16)                       _BFGET_(r16,12,12)
    #define   SET16PVT_Sens_STS_EOC(r16,v)                     _BFSET_(r16,12,12,v)

    #define   GET32PVT_Sens_STS_NMOS(r32)                      _BFGET_(r32,15,13)
    #define   SET32PVT_Sens_STS_NMOS(r32,v)                    _BFSET_(r32,15,13,v)
    #define   GET16PVT_Sens_STS_NMOS(r16)                      _BFGET_(r16,15,13)
    #define   SET16PVT_Sens_STS_NMOS(r16,v)                    _BFSET_(r16,15,13,v)

    #define   GET32PVT_Sens_STS_PMOS(r32)                      _BFGET_(r32,18,16)
    #define   SET32PVT_Sens_STS_PMOS(r32,v)                    _BFSET_(r32,18,16,v)
    #define   GET16PVT_Sens_STS_PMOS(r16)                      _BFGET_(r16, 2, 0)
    #define   SET16PVT_Sens_STS_PMOS(r16,v)                    _BFSET_(r16, 2, 0,v)

    #define     w32PVT_Sens_STS                                {\
            UNSG32 uSTS_BN                                     : 12;\
            UNSG32 uSTS_EOC                                    :  1;\
            UNSG32 uSTS_NMOS                                   :  3;\
            UNSG32 uSTS_PMOS                                   :  3;\
            UNSG32 RSVDx4_b19                                  : 13;\
          }
    union { UNSG32 u32PVT_Sens_STS;
            struct w32PVT_Sens_STS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PVT_Sens_TEST_ENABLE(r32)                   _BFGET_(r32, 0, 0)
    #define   SET32PVT_Sens_TEST_ENABLE(r32,v)                 _BFSET_(r32, 0, 0,v)
    #define   GET16PVT_Sens_TEST_ENABLE(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16PVT_Sens_TEST_ENABLE(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define   GET32PVT_Sens_TEST_FAIL(r32)                     _BFGET_(r32, 1, 1)
    #define   SET32PVT_Sens_TEST_FAIL(r32,v)                   _BFSET_(r32, 1, 1,v)
    #define   GET16PVT_Sens_TEST_FAIL(r16)                     _BFGET_(r16, 1, 1)
    #define   SET16PVT_Sens_TEST_FAIL(r16,v)                   _BFSET_(r16, 1, 1,v)

    #define   GET32PVT_Sens_TEST_TEST_DATA_HIGH(r32)           _BFGET_(r32,13, 2)
    #define   SET32PVT_Sens_TEST_TEST_DATA_HIGH(r32,v)         _BFSET_(r32,13, 2,v)
    #define   GET16PVT_Sens_TEST_TEST_DATA_HIGH(r16)           _BFGET_(r16,13, 2)
    #define   SET16PVT_Sens_TEST_TEST_DATA_HIGH(r16,v)         _BFSET_(r16,13, 2,v)

    #define   GET32PVT_Sens_TEST_TEST_DATA_LOW(r32)            _BFGET_(r32,25,14)
    #define   SET32PVT_Sens_TEST_TEST_DATA_LOW(r32,v)          _BFSET_(r32,25,14,v)

    #define     w32PVT_Sens_TEST                               {\
            UNSG32 uTEST_ENABLE                                :  1;\
            UNSG32 uTEST_FAIL                                  :  1;\
            UNSG32 uTEST_TEST_DATA_HIGH                        : 12;\
            UNSG32 uTEST_TEST_DATA_LOW                         : 12;\
            UNSG32 RSVDx8_b26                                  :  6;\
          }
    union { UNSG32 u32PVT_Sens_TEST;
            struct w32PVT_Sens_TEST;
          };
    ///////////////////////////////////////////////////////////
    } SIE_PVT_Sens;

    typedef union  T32PVT_Sens_CTRL
          { UNSG32 u32;
            struct w32PVT_Sens_CTRL;
                 } T32PVT_Sens_CTRL;
    typedef union  T32PVT_Sens_STS
          { UNSG32 u32;
            struct w32PVT_Sens_STS;
                 } T32PVT_Sens_STS;
    typedef union  T32PVT_Sens_TEST
          { UNSG32 u32;
            struct w32PVT_Sens_TEST;
                 } T32PVT_Sens_TEST;
    ///////////////////////////////////////////////////////////

    typedef union  TPVT_Sens_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PVT_Sens_CTRL;
                   };
                 } TPVT_Sens_CTRL;
    typedef union  TPVT_Sens_STS
          { UNSG32 u32[1];
            struct {
            struct w32PVT_Sens_STS;
                   };
                 } TPVT_Sens_STS;
    typedef union  TPVT_Sens_TEST
          { UNSG32 u32[1];
            struct {
            struct w32PVT_Sens_TEST;
                   };
                 } TPVT_Sens_TEST;

    ///////////////////////////////////////////////////////////
     SIGN32 PVT_Sens_drvrd(SIE_PVT_Sens *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 PVT_Sens_drvwr(SIE_PVT_Sens *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void PVT_Sens_reset(SIE_PVT_Sens *p);
     SIGN32 PVT_Sens_cmp  (SIE_PVT_Sens *p, SIE_PVT_Sens *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define PVT_Sens_check(p,pie,pfx,hLOG) PVT_Sens_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define PVT_Sens_print(p,    pfx,hLOG) PVT_Sens_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: PVT_Sens
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE Gbl                     biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ProductId            (RNB-)
///               ###
///               * Product ID register
///               ###
///               %unsigned 32 Id                        
///                                    ###
///                                    * Product ID:
///                                    * [31:28]     : Revision Id (0x0)/P
///                                    * [27:12]     : Part Number (0x3108)
///                                    * [11:1]       : Manufacture Id (0x588)
///                                    * [0]            : Reserved (0x1)
///                                    ###
///     @ 0x00004 ProductId_ext        (RNB-)
///               ###
///               * Product ID Extension
///               ###
///               %unsigned 8  ID_EXT                    
///                                    ###
///                                    * ID extension value
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00008 INT_ID               (RNB-)
///               ###
///               * **INTERNAL_ONLY**
///               * Internal ID register
///               ###
///               %unsigned 8  VALUE                     
///                                    ###
///                                    * Internal ID
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x0000C bootStrap            (R-)
///               ###
///               * Boot Strap Register (Read Only). Boot straps are latched on Power On and stored in this register.
///               * This register can be reset only by PAD reset.
///               * To provide software backward compatible,
///               * Please never remove register bits even if the clock gators are removed.
///               * Leave a 'not used' comment if the bit field is not used in current project.
///               * Please always add new bit field at the end.
///               ###
///               %unsigned 16 softwareStrap             
///                                    ###
///                                    * Straps for software usage
///                                    * BG4CT use the first 4 of them
///                                    ###
///               %unsigned 2  bootSrc                   
///                                    : ROM_SPI_BOOT              0x0
///                                    : ROM_NAND_BOOT             0x1
///                                    : ROM_EMMC_BOOT             0x2
///                                    : ROM_SPI_DIRECT_BOOT       0x3
///                                                 ###
///                                                 * CPU boot source
///                                                 * 00: ROM boot from SPI
///                                                 * 01: ROM boot from NAND
///                                                 * 10: ROM boot from EMMC
///                                                 * 11: Direct boot from SPI (Only available when ENG_EN=1)
///                                                 * Note: When direct boot from SPI (SPI clear boot), pwrCntlByps and cpuRstByps should be set to 1
///                                                 ###
///               %unsigned 1  cpuRstByps                
///                                    : CPU_INT_RST_BYPS          0x1
///                                    : CPU_INT_RST_EN            0x0
///                                                 ###
///                                                 * CPU reset bypass strap
///                                                 * 1: Bypass reset logic inside CPU partition
///                                                 * 0: Enable reset logic inside CPU partition
///                                                 ###
///               %unsigned 1  pllPwrDown                
///                                    : PWR_DOWN                  0x1
///                                    : PWR_UP                    0x0
///                                                 ###
///                                                 * PLL Power Down
///                                                 * SYS/MEM/CPU PLL Power Down
///                                                 * 1: Power Down
///                                                 * 0: Power UP
///                                                 ###
///               %unsigned 1  sysPllByps                
///                                    : PLL_OUT                   0x0
///                                    : BYPS                      0x1
///                                                 ###
///                                                 * SYSPLL Bypass
///                                                 * 0: No Bypass
///                                                 * 1: System PLL Bypassed
///                                                 ###
///               %unsigned 1  memPllByps                
///                                    : PLL_OUT                   0x0
///                                    : BYPS                      0x1
///                                                 ###
///                                                 * MEMPLL Bypass indicator
///                                                 * 0: No Bypass
///                                                 * 1: Memory PLL Bypassed
///                                                 ###
///               %unsigned 1  cpuPllByps                
///                                    : PLL_OUT                   0x0
///                                    : BYPS                      0x1
///                                                 ###
///                                                 * CPUPLL Bypass indicator
///                                                 * 0: No Bypass
///                                                 * 1: CPUPLL Bypassed
///                                                 ###
///               %unsigned 1  ENG_EN                    
///                                    : PRODUCTION_MODE           0x0
///                                    : DEVELOPE_MODE             0x1
///                                                 ###
///                                                 * Production or development mode. This is not a boot strap bit. It's a bonding option and only read by AHB.
///                                                 * *INTERNAL_ONLY**
///                                                 ###
///               %unsigned 1  LEGACY_BOOT               
///                                    : FAST_BOOT_MODE            0x0
///                                    : LEGACY_BOOT_MODE          0x1
///                                                 ###
///                                                 * Pll lock and reset wait time reduced from 20ms to 2ms.
///                                                 ###
///               %%        7          # Stuffing bits...
///     @ 0x00010 bootStrapEn          (P)
///               ###
///               * Boot Strap Enable register
///               * This register provides the option to over write the Bootstraps using CPU register write
///               ###
///               %unsigned 1  cpuRstBypsEn              0x1
///                                    : ENABLE                    0x1
///                                    : DISABLE                   0x0
///                                                 ###
///                                                 * CPU Reset Bypass Strap Enable
///                                                 * 1 : Allow bootstrap
///                                                 * 0 : Disable bootstrap
///                                                 ###
///               %unsigned 1  pllPwrDownEn              0x1
///                                    : ENABLE                    0x1
///                                    : DISABLE                   0x0
///                                                 ###
///                                                 * PLL Power Down Strap Enable
///                                                 * 1 : Allow bootstrap
///                                                 * 0 : Disable bootstrap
///                                                 ###
///               %unsigned 1  sysPLLBypsEn              0x1
///                                    : ENABLE                    0x1
///                                    : DISABLE                   0x0
///                                                 ###
///                                                 * System PLL Bypass Strap Enable
///                                                 * 1 : Allow bootstrap
///                                                 * 0 : Disable bootstrap
///                                                 ###
///               %unsigned 1  memPLLBypsEn              0x1
///                                    : ENABLE                    0x1
///                                    : DISABLE                   0x0
///                                                 ###
///                                                 * Memory PLL Bypass Strap Enable
///                                                 * 1 : Allow bootstrap
///                                                 * 0 : Disable bootstrap
///                                                 ###
///               %unsigned 1  cpuPLLBypsEn              0x1
///                                    : ENABLE                    0x1
///                                    : DISABLE                   0x0
///                                                 ###
///                                                 * CPU PLL Bypass Strap Enable
///                                                 * 1 : Allow bootstrap
///                                                 * 0 : Disable bootstrap
///                                                 ###
///               %unsigned 1  legacyBootEn              0x1
///                                    : ENABLE                    0x1
///                                    : DISABLE                   0x0
///                                                 ###
///                                                 * Legacy Boot Strap Enable
///                                                 * 1 : Allow bootstrap
///                                                 * 0 : Disable bootstrap
///                                                 ###
///               %%        26         # Stuffing bits...
///     @ 0x00014 pkgSel               (R-)
///               ###
///               * package select register (read only)
///               * identify different package
///               ###
///               %unsigned 1  DDR32bit                  
///                                    ###
///                                    * Form pad PKG_SEL_0
///                                    * 0: 64 bit DDR
///                                    * 1: 32 bit DDR
///                                    * bit 1 reserved
///                                    ###
///               %unsigned 1  reserved                  
///                                    ###
///                                    * Form pad PKG_SEL_1
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00018 chipCntl             (P-)
///               ###
///               * Misc Chip Control bits
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 1  SD0_CLK_LPBK_EN           0x1
///                                    ###
///                                    * SD0 CLK Loop Back enable bit
///                                    ###
///               %unsigned 1  SD0_CLK_LPBK_SEL          0x1
///                                    ###
///                                    * SD0 CLK Loop Back select
///                                    * 0: From pinMux
///                                    * 1: From loop back
///                                    ###
///               %unsigned 1  EMMC_CLK_LPBK_EN          0x1
///                                    ###
///                                    * EMMC CLK Loop Back enable bit
///                                    ###
///               %unsigned 1  EMMC_CLK_LPBK_SEL         0x1
///                                    ###
///                                    * EMMC CLK Loop Back select
///                                    * 0: From pinMux
///                                    * 1: From loop back
///                                    ###
///               %unsigned 10 I2S_FB_SEL                0x0
///                                    ###
///                                    * I2S_FB_SEL[1:0] Select I2S1_BCLKIO_DI feedback path
///                                    * 0: I2S1_BCLKIO_DI
///                                    * 1: I2S2_BCLKIO_DI
///                                    * 2: I2S2_BCLKIO_DO
///                                    * 3: 1'b0
///                                    * I2S_FB_SEL[3:2] Select I2S1_LRCKIO_DI feedback path
///                                    * 0: I2S1_LRCKIO_DI
///                                    * 1: I2S2_LRCKIO_DI
///                                    * 2: I2S2_LRCKIO_DO
///                                    * 3: 1'b0
///                                    * I2S_FB_SEL[5:4] Select I2S2_BCLKIO_DI feedback path
///                                    * 0: I2S2_BCLKIO_DI
///                                    * 1: I2S1_BCLKIO_DI
///                                    * 2: I2S1_BCLKIO_DO
///                                    * 3: I2S2_BCLKIO_DO
///                                    * I2S_FB_SEL[7:6] Select I2S2_LRCKIO_DI feedback path
///                                    * 0: I2S2_LRCKIO_DI
///                                    * 1: I2S1_LRCKIO_DI
///                                    * 2: I2S1_LRCKIO_DO
///                                    * 3: I2S2_LRCKIO_DO
///                                    * I2S_FB_SEL[8] Select I2S3_BCLKIO_DI feedback path
///                                    * 0: I2S3_BCLKIO_DI
///                                    * 1: I2S3_BCLKIO_DO
///                                    * I2S_FB_SEL[9] Select I2S3_LRCKIO_DI feedback path
///                                    * 0: I2S3_LRCKIO_DI
///                                    * 1: I2S3_LRCKIO_DO
///                                    ###
///               %unsigned 3  SPDIFI_SEL                0x0
///                                    ###
///                                    * Select for SPDIFI source
///                                    * 0: SPDIF mxued on PDM_DI[0]
///                                    * 1: SPDIFA muxed on I2S2_LRCKI
///                                    * 2: SPDIFB muxed on I2S1_DO[3]
///                                    * 3: SPDIFC muxed on I2S2_DI[2]
///                                    * 4: SPDIFD muxed on PDM_DI[2]
///                                    ###
///               %unsigned 1  TW1_SEL                   0x0
///                                    ###
///                                    * Select for TW1 source
///                                    * 0: TW1
///                                    * 1: TW1A muxed on URT1
///                                    ###
///               %unsigned 3  DBG_SEL                   0x0
///                                    ###
///                                    * Debug bus selection.
///                                    * 0: perifTop_dbg_bus
///                                    * 1: [15:0]
///                                    * 2: nna_debug[7:0]
///                                    ###
///               %unsigned 1  CLK_DBG_SEL               0x0
///                                    ###
///                                    * Clock debug bus selection
///                                    * 0: USBOTG_DBG_CLK
///                                    * 1: ABBGEN_ro_out
///                                    ###
///               %unsigned 1  SD0_CDn_SEL               0x0
///                                    ###
///                                    * SD0_CDn source selection
///                                    * 0: from IO: SD0_CDn
///                                    * 1: tie to 1'b0
///                                    ###
///               %unsigned 1  SD0_WP_SEL                0x0
///                                    ###
///                                    * SD0_WP source selection
///                                    * 0: from IO: SD0_WP
///                                    * 1: tie to 1'b1
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x0001C                      (W-)
///     #         # Stuffing bytes...
///               %% 32
///     @ 0x00020 sw_generic0          (P-)
///               ###
///               * Generic software register.
///               ###
///               %unsigned 32 swReg0                    0x0
///     @ 0x00024 sw_generic1          (P-)
///               ###
///               * Generic software register.
///               ###
///               %unsigned 32 swReg1                    0x0
///     @ 0x00028 sw_generic2          (P-)
///               ###
///               * Generic software register.
///               ###
///               %unsigned 32 swReg2                    0x0
///     @ 0x0002C sw_generic3          (P-)
///               ###
///               * Generic software register. This register can be reset only by PAD reset.
///               ###
///               %unsigned 32 swReg3                    0x0
///     @ 0x00030 RWTC_top31to0        (P-)
///               %unsigned 32 value                     0x100
///                                    ###
///                                    * RTWC [31:0] value for TOP level
///                                    * *INTERNAL_ONLY**
///                                    ###
///     @ 0x00034 RWTC_top63to32       (P-)
///               %unsigned 32 value                     0x0
///                                    ###
///                                    * RTWC [63:32] value for Top level
///                                    * *INTERNAL_ONLY**
///                                    ###
///     @ 0x00038 RWTC_top67to64       (P-)
///               %unsigned 4  value                     0x0
///                                    ###
///                                    * TWC [67:64] value for Top level
///                                    * *INTERNAL_ONLY**
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x0003C                      (W-)
///     #         # Stuffing bytes...
///               %% 128
///     @ 0x0004C SRAM_PWR_CTRL_USB2   (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00050 SRAM_PWR_CTRL_PCIE0  (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00054 SRAM_PWR_CTRL_PCIE1  (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00058                      (W-)
///     #         # Stuffing bytes...
///               %% 32
///     @ 0x0005C SRAM_PWR_CTRL_SISS   (P-)
///               %unsigned 3  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00060                      (W-)
///     #         # Stuffing bytes...
///               %% 96
///     @ 0x0006C SRAM_PWR_CTRL_NNA    (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00070 SRAM_PWR_CTRL_AIO    (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00074 SRAM_PWR_CTRL_CA53   (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00078 SRAM_PWR_CTRL_SCRATCH (P-)
///               %unsigned 2  value                     0x0
///                                    ###
///                                    * {POWERGATE,DEEPSLEEP} used to control memory leakage.
///                                    * 00: power gating disabled
///                                    * 01: deep sleep operation
///                                    * 10: power gating active
///                                    * 11: illegal operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x0007C                      (W-)
///     #         # Stuffing bytes...
///               %% 32
///     @ 0x00080 FPGAR                (R-)
///               ###
///               * FPGA Revision ID Read only register
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 32 FPGAR                     0xB3A9FA72
///                                    ###
///                                    * FPGA Revision ID register
///                                    ###
///     @ 0x00084 FPGARW               (P)
///               ###
///               * FPGA General Purpose RW register
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 32 FPGARW                    0x0
///                                    ###
///                                    * FPGA General purpose RW register
///                                    * PLL Control Region
///                                    ###
///     @ 0x00088                      (P)
///     # 0x00088 sysPll               
///               $vsipll              sysPll            REG          
///                                    ###
///                                    * Clock and Reset Control Region
///                                    ###
///     @ 0x000A0                      (W-)
///     #         # Stuffing bytes...
///               %% 7872
///     @ 0x00478 ResetTrigger         (P-)
///               ###
///               * Software reset trigger register. Using this register software can reset particular module of the chip. Writing 1 to this register will trigger 16 reference clock (640ns) reset to the corresponding module (except for PCIe for PCIe user has all the reset duration control so writing 1 will trigger the reset and writing 0 will de-assert the reset).
///               * In the following register:
///               * 0 : No Reset
///               * 1 : Reset
///               * To provide software backward compatible,
///               * Please never remove register bits even if the clock gators are removed.
///               * Leave a 'not used' comment if the bit field is not used in current project.
///               * Please always add new bit field at the end.
///               ###
///               %unsigned 1  chipReset                 0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset all registers in the chip.
///                                                 * Note: When this bit is set then there is no reset sequence followed to de-assert the reset to CPU in the end as done in case of boot-up. So using this bit is not suggested as CPU will come out of the reset earlier than modules which are running on slow clocks as compared to CPU.
///                                                 * *INTERNAL_ONLY**
///                                                 ###
///               %unsigned 1  socDdrSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset memory controller
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %%        30         # Stuffing bits...
///     @ 0x0047C ResetStatus          (RW-)
///               ###
///               * Reset Status register indicates whether reset is triggered or not to the corresponding module.
///               * 0 : Reset not issued
///               * 1 : Reset issued
///               * Note: Software need to write 0 to clear this register.
///               * To provide software backward compatible,
///               * Please never remove register bits even if the clock gators are removed.
///               * Leave a 'not used' comment if the bit field is not used in current project.
///               * Please always add new bit field at the end.
///               ###
///               %unsigned 1  ChipResetStatus           0x0
///                                    : asserted                  0x1
///                                    : deasserted                0x0
///                                                 ###
///                                                 * **INTERNAL_ONLY**
///                                                 ###
///               %unsigned 1  socDdrSyncResetStatus     0x0
///                                    : asserted                  0x1
///                                    : deasserted                0x0
///                                                 ###
///                                                 * Memory controller reset status
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %%        30         # Stuffing bits...
///     @ 0x00480 WDTResetStatus       (RW-)
///               %unsigned 1  wd0Status                 0x0
///                                    : asserted                  0x1
///                                    : deasserted                0x0
///                                                 ###
///                                                 * Watch dog timer 0 reset status
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  wd1Status                 0x0
///                                    : asserted                  0x1
///                                    : deasserted                0x0
///                                                 ###
///                                                 * Watch dog timer 1 reset status
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  wd2Status                 0x0
///                                    : asserted                  0x1
///                                    : deasserted                0x0
///                                                 ###
///                                                 * Watch dog timer 2 reset status
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %%        29         # Stuffing bits...
///     @ 0x00484 WDTSysRstMask        (RW)
///               ###
///               * Mask the sys rst from apbPerif wdt from triggering soc reset.
///               ###
///               %unsigned 1  wdt0Mask                  0x0
///                                    ###
///                                    * 1: Mask sys reset from wdt0
///                                    ###
///               %unsigned 1  wdt1Mask                  0x0
///                                    ###
///                                    * 1: Mask sys reset from wdt1
///                                    ###
///               %unsigned 1  wdt2Mask                  0x0
///                                    ###
///                                    * 1: Mask sys reset from wdt2
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00488 CHIP_RESET_TRACKER   (RW)
///               ###
///               * SW can perform read/write on this register to keep track of the chip reset.
///               * Note: A Shadow register is implemented for this register which stores the value that is written to this register. The Shadow Register gets reset only by the RSTIn Chip Pin.
///               ###
///               %unsigned 32 VALUE                     0x0
///     @ 0x0048C                      (W-)
///     #         # Stuffing bytes...
///               %% 64
///     @ 0x00494 avioReset            (P-)
///               ###
///               * AVIO 3D reset register
///               ###
///               %unsigned 1  SyncReset                 0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset all registers in AVIO
///                                                 * 0: No Reset
///                                                 * 1: Reset
///                                                 ###
///               %%        31         # Stuffing bits...
///     @ 0x00498 avioResetStatus      (RW-)
///               %unsigned 1  SyncReset                 0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of AVIO
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %%        31         # Stuffing bits...
///     @ 0x0049C perifReset           (P-)
///               ###
///               * perif reset register
///               * To provide software backward compatible,
///               * Please never remove register bits even if the clock gators are removed.
///               * Leave a 'not used' comment if the bit field is not used in current project.
///               * Please always add new bit field at the end.
///               ###
///               %unsigned 1  SyncReset                 0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset whole Peripheral unit
///                                                 * 0: No Reset
///                                                 * 1: Reset
///                                                 ###
///               %unsigned 1  ahbApbSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset Peripheral AHB-APB module (includes GPIO, Two wire Serial interface, Interrupt controller, Timers and SPI)
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  nfcSysSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset NAND Flash IP logic except registers
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  nfcRegSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset NAND Flash IP Configuration registers
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  sdioSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset peripheral SDIO module
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  tspSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset TSP module
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  tsSSSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset TSS module
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  nskSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset NSK module
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  nocsSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset nocs module
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  bcmSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset BCM
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  usb0SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset peripheral USB0 module
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  emmcSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset emmc
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %unsigned 1  pBridgeSyncReset          0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset pBridge
///                                                 * 0 : No Reset
///                                                 * 1 : Reset
///                                                 ###
///               %%        19         # Stuffing bits...
///     @ 0x004A0                      (W-)
///     #         # Stuffing bytes...
///               %% 768
///     @ 0x00500 perifResetStatus     (RW-)
///               ###
///               * To provide software backward compatible,
///               * Please never remove register bits even if the clock gators are removed.
///               * Leave a 'not used' comment if the bit field is not used in current project.
///               * Please always add new bit field at the end.
///               ###
///               %unsigned 1  SyncReset                 0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of whole Peripheral unit
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  ahbApbSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of Peripheral AHB-APB module (includes GPIO, Two wire Serial interface, Interrupt controller, Timers and SPI)
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  nfcSysSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * NAND Flash system reset status
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  nfcRegSyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * NAND Flash register reset status
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  sdioSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of peripheral SDIO module
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  tspSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of TSP module
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  tsSSSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of TSS module
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  nskSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of NSK module
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  nocsSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of nocs module
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  bcmSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of BCM
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  usb0SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status of peripheral USB0 module
///                                                 * 0 : Reset not issued
///                                                 * 1 : Reset issued
///                                                 ###
///               %unsigned 1  emmcSyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status for emmc
///                                                 * 0 : Reset not asserted
///                                                 * 1 : Reset asserted
///                                                 ###
///               %unsigned 1  pBridgeSyncReset          0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///                                                 ###
///                                                 * Reset status for pBridge
///                                                 * 0 : Reset not asserted
///                                                 * 1 : Reset asserted
///                                                 ###
///               %%        19         # Stuffing bits...
///     @ 0x00504 topStickyResetN      (P-)
///               %unsigned 1  nnaStickyRstn             0x0
///                                    ###
///                                    * NXBAR and IMTEST will be assert if nnaStickyRstn is asserted.
///                                    ###
///               %unsigned 1  ddrPHYStickyRstn          0x0
///                                    ###
///                                    * StickyRstn for ddrPHY
///                                    ###
///               %unsigned 1  mcStickyRstn              0x0
///                                    ###
///                                    * StickyRstn for memory controller
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00508 perifStickyResetN    (P-)
///               ###
///               * sticky reset bits. Active low.
///               * 0: Reset
///               * 1: No Reset
///               ###
///               %unsigned 1  pcie0Rstn                 0x0
///                                    : asserted                  0x0
///                                    : deasserted                0x1
///               %unsigned 1  pcie1Rstn                 0x0
///                                    : asserted                  0x0
///                                    : deasserted                0x1
///               %unsigned 1  usbOtgPrstn               0x0
///                                    : asserted                  0x0
///                                    : deasserted                0x1
///               %unsigned 1  usbOtgHresetn             0x0
///                                    : asserted                  0x0
///                                    : deasserted                0x1
///               %unsigned 1  usbOtgPhyreset            0x1
///                                    : asserted                  0x1
///                                    : deasserted                0x0
///               %unsigned 1  pcie0PhyRstn              0x0
///                                    : asserted                  0x0
///                                    : deasserted                0x1
///               %unsigned 1  pcie1PhyRstn              0x0
///                                    : asserted                  0x0
///                                    : deasserted                0x1
///                                                 ###
///                                                 * PCIE Module Reset
///                                                 * 0 : Reset
///                                                 * 1 : No Reset
///                                                 ###
///               %%        25         # Stuffing bits...
///     @ 0x0050C apbPerifResetTrigger (P-)
///               ###
///               * Software reset trigger register. Using this register software can reset particular apbPerif module.
///               * 0 : No Reset
///               * 1 : Reset
///               ###
///               %unsigned 1  uart0SyncReset            0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  uart1SyncReset            0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  i2c0SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  i2c1SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  spiSyncReset              0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  timer0SyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  timer1SyncReset           0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  wdt0SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  wdt1SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  wdt2SyncReset             0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %%        22         # Stuffing bits...
///     @ 0x00510 apbPerifResetStatus  (P-)
///               ###
///               * Reset Status register indicates whether reset is triggered or not to the corresponding module.
///               * 0 : Reset not issued
///               * 1 : Reset issued
///               * Note: Software need to write 0 to clear this register.
///               ###
///               %unsigned 1  uart0SyncResetStatus      0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  uart1SyncResetStatus      0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  i2c0SyncResetStatus       0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  i2c1SyncResetStatus       0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  i2c2SyncResetStatus       0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  spiSyncResetStatus        0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  timer0SyncResetStatus     0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  timer1SyncResetStatus     0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  wdt0SyncResetStatus       0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  wdt1SyncResetStatus       0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %unsigned 1  wdt2SyncResetStatus       0x0
///                                    : assert                    0x1
///                                    : deassert                  0x0
///               %%        21         # Stuffing bits...
///     @ 0x00514 clkEnable            (P-)
///               ###
///               * Clock enable register provides the option to switch clocks OFF for power saving.
///               * All these clocks are using perifSysClk as clock source.
///               * To provide software backward compatible,
///               * Please never remove register bits even if the clock gators are removed.
///               * Leave a 'not used' comment if the bit field is not used in current project.
///               * Please always add new register bit at the end.
///               ###
///               %unsigned 1  tspSysClkEn               0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * TSP Sys Clk
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  usb0CoreClkEn             0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * USB0 Core Clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  sdioSysClkEn              0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * SDIO AXI clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  pcie0SysClkEn             0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * pcie AXI clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  pcie1SysClkEn             0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Pcie1 AXI clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  nfcSysClkEn               0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Nand flash controller AXI clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  emmcSysClkEn              0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * EMMC AXI clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %unsigned 1  pBridgeCoreClkEn          0x1
///                                    : enable                    0x1
///                                    : disable                   0x0
///                                                 ###
///                                                 * Pbridge module clock enable register
///                                                 * 0 : disable
///                                                 * 1 : enable
///                                                 ###
///               %%        24         # Stuffing bits...
///     @ 0x00518 ClkSwitch            (P-)
///               ###
///               * Clock Switch register. This register is used to select clock between:
///               * PLL clock or reference clock (PLL Bypass option)
///               ###
///               %unsigned 1  sysPLLSWBypass            0x0
///                                    : refClk                    0x1
///                                    : pllClk                    0x0
///                                                 ###
///                                                 * System PLL Bypass switch
///                                                 * 0: Use PLL
///                                                 * 1: Bypass PLL
///                                                 ###
///               %unsigned 1  memPLLSWBypass            0x0
///                                    : refClk                    0x1
///                                    : pllClk                    0x0
///                                                 ###
///                                                 * Memory PLL Bypass switch
///                                                 * 0: Use PLL
///                                                 * 1: Bypass PLL
///                                                 ###
///               %unsigned 1  cpuPLLSWBypass            0x0
///                                    : refClk                    0x1
///                                    : pllClk                    0x0
///                                                 ###
///                                                 * CPU PLL Bypass switch
///                                                 * 0: Use PLL
///                                                 * 1: Bypass PLL
///                                                 * Following are control registers for clock generation logics in global.
///                                                 * They can select different pll source, set different diver and turn on/off the clocks
///                                                 * fast reference clock for cpu and ddr
///                                                 * Provide fast backup clock from syspll to cpu and ddr when cpupll or mempll is down for re-configuration
///                                                 ###
///               %%        29         # Stuffing bits...
///     @ 0x0051C                      (P)
///     # 0x0051C cpufastRefClk        
///               $clkD1               cpufastRefClk     REG          
///                                    ###
///                                    * Fast backup clock for cpu when cpupll is bypass
///                                    ###
///     @ 0x00520                      (P)
///     # 0x00520 memfastRefClk        
///               $clkD1               memfastRefClk     REG          
///                                    ###
///                                    * Fast backup clock for mc5 when mempll is bypass
///                                    * System bus clock
///                                    ###
///     @ 0x00524                      (P)
///     # 0x00524 cfgClk               
///               $clkD4               cfgClk            REG          
///                                    ###
///                                    * System AHB Clock
///                                    ###
///     @ 0x00528                      (P)
///     # 0x00528 perifSysClk          
///               $clkD2               perifSysClk       REG          
///                                    ###
///                                    * System AXI Clock
///                                    * used by perif zsp dxbar cxbar mcxbar
///                                    ###
///     @ 0x0052C                      (P)
///     # 0x0052C atbClk               
///               $clkD8               atbClk            REG          
///                                    ###
///                                    * ATB (CoreSight) Clock
///                                    * goes to v4g bcm and cpu_ss VPU clocks
///                                    * AVIO Clock
///                                    ###
///     @ 0x00530                      (P)
///     # 0x00530 avioSysClk           
///               $clkD2               avioSysClk        REG          
///                                    ###
///                                    * AVIO AXI Clock
///                                    * DSP Clock
///                                    * Perif Clock
///                                    * Tsp clock
///                                    ###
///     @ 0x00534                      (P)
///     # 0x00534 apbCoreClk           
///               $clkD4               apbCoreClk        REG          
///                                    ###
///                                    * APB perif clock for TWI, SPI, etc.
///                                    ###
///     @ 0x00538                      (P)
///     # 0x00538 nnaSysClk            
///               $clkD2               nnaSysClk         REG          
///                                    ###
///                                    * Nna AXI Clock
///                                    ###
///     @ 0x0053C                      (P)
///     # 0x0053C nnaCoreClk           
///               $clkD2               nnaCoreClk        REG          
///                                    ###
///                                    * Nna Core Clock
///                                    * SDIO and EMMC
///                                    ###
///     @ 0x00540                      (P)
///     # 0x00540 emmcClk              
///               $clkD4               emmcClk           REG          
///                                    ###
///                                    * emmc controller core Clock
///                                    ###
///     @ 0x00544                      (P)
///     # 0x00544 sd0Clk               
///               $clkD4               sd0Clk            REG          
///                                    ###
///                                    * SDIO0 controller core Clock
///                                    * PCIE
///                                    ###
///     @ 0x00548                      (P)
///     # 0x00548 pcie_500M_TxTestClk  
///               $clkD4               pcie_500M_TxTestClk REG          
///                                    ###
///                                    * PCIE test_clock[1]. Bypasses ser_pclk_out from serders.
///                                    ###
///     @ 0x0054C                      (P)
///     # 0x0054C pcie_250M_pipeTestClk1 
///               $clkD8               pcie_250M_pipeTestClk1 REG          
///                                    ###
///                                    * PCIE test_clock[2]. Bypasses pipe_clk/2, pipe_clk/4 in serders wrapper.
///                                    ###
///     @ 0x00550                      (P)
///     # 0x00550 pcie_250M_pipeTestClk2 
///               $clkD8               pcie_250M_pipeTestClk2 REG          
///                                    ###
///                                    * PCIE test clock[3]. Bypasses pipe_clk going to the MAC
///                                    ###
///     @ 0x00554                      (P)
///     # 0x00554 pcie_500M_RxTestClk  
///               $clkD4               pcie_500M_RxTestClk REG          
///                                    ###
///                                    * PCIE test_clock[4]. Bypasses rxwordclk from serders.
///                                    ###
///     @ 0x00558                      (P)
///     # 0x00558 pcie_serdesTestClk   
///               $clkD8               pcie_serdesTestClk REG          
///                                    ###
///                                    * Connects to i_scan_clk[5:0] port of serdes. All clock groups inside serdes bypassed by same test clock. Only target stuck-at coverage.
///                                    * NAND
///                                    ###
///     @ 0x0055C                      (P)
///     # 0x0055C nfcEccClk            
///               $clkD4               nfcEccClk         REG          
///                                    ###
///                                    * NFC ECC Clock.
///                                    ###
///     @ 0x00560                      (P)
///     # 0x00560 nfcCoreClk           
///               $clkD4               nfcCoreClk        REG          
///                                    ###
///                                    * NFC Core Clock.
///                                    * USBOTG
///                                    ###
///     @ 0x00564                      (P)
///     # 0x00564 usbOtg60MTestClk     
///               $clkD12              usbOtg60MTestClk  REG          
///                                    ###
///                                    * Usb otg test clock for 60Mhz domain, used by core and PHY.
///                                    ###
///     @ 0x00568                      (P)
///     # 0x00568 usbOtg50MTestClk     
///               $clkD12              usbOtg50MTestClk  REG          
///                                    ###
///                                    * Usb otg test clock for 50Mhz used byPHY.
///                                    ###
///     @ 0x0056C                      (P)
///     # 0x0056C usbOtg12MTestClk     
///               $clkD12              usbOtg12MTestClk  REG          
///                                    ###
///                                    * Usb otg test clock for 12Mhz used byPHY.
///                                    ###
///     @ 0x00570                      (P)
///     # 0x00570 usbOtg480MTestClk    
///               $clkD12              usbOtg480MTestClk REG          
///                                    ###
///                                    * Usb otg test clock for 480Mhz used byPHY.
///                                    * BCM
///                                    ###
///     @ 0x00574                      (P)
///     # 0x00574 bcmClk               
///               $clkD2               bcmClk            REG          
///                                    ###
///                                    * BCM Clock
///                                    * MISC Register Control Region
///                                    ###
///     @ 0x00578 NandCtrl             (P)
///               ###
///               * NAND Write Protect pin control register.
///               ###
///               %unsigned 1  NAND_WPn_Sel              0x1
///                                    ###
///                                    * 0 : Write protected
///                                    * 1: Not Write Protected
///                                    ###
///               %unsigned 1  NAND_CLE_OE               0x1
///                                    ###
///                                    * 0 : Output Disabled (drive Zero)
///                                    * 1: Output Enabled
///                                    ###
///               %unsigned 1  NAND_ALE_OE               0x1
///                                    ###
///                                    * 0 : Output Disabled (drive Zero)
///                                    * 1: Output Enabled
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x0057C                      (W-)
///     #         # Stuffing bytes...
///               %% 1280
///     @ 0x0061C gic400_ctrl          (P-)
///               %unsigned 1  cgfsdisable               0x0
///                                    ###
///                                    * GIC400 secure disable control
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00620 POR_1p8_3p3          (P-)
///               %unsigned 1  por_io_1p8v_pd            0x0
///                                    ###
///                                    * Power down 1.8V POR (active high)
///                                    ###
///               %unsigned 1  por_io_3p3v_pd            0x0
///                                    ###
///                                    * Power down 3.3V POR (active high)
///                                    ###
///               %unsigned 2  por_io_1p8v_threshold     0x0
///                                    ###
///                                    * Threshold voltage - only for high to low output trip point.
///                                    * 2'b00: 1.63V (default) 2'b01: TBD
///                                    * 2'b10: TBD
///                                    * 2'b11: TBD
///                                    ###
///               %unsigned 2  por_io_3p3v_threshold     0x0
///                                    ###
///                                    * Threshold voltage - only for high to low output trip point.
///                                    * 2'b00: 2.63V (default) 2'b01: 2.93V
///                                    * 2'b10: 3.08V
///                                    * 2'b11: TBD
///                                    ###
///               %unsigned 1  por_io_1p8v_bypass        0x0
///                                    ###
///                                    * Bypass por_io_1p8v reset
///                                    ###
///               %unsigned 1  por_io_3p3v_bypass        0x0
///                                    ###
///                                    * Bypass por_io_3p3v reset
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00624                      (W-)
///     #         # Stuffing bytes...
///               %% 480
///     @ 0x00660                      (P)
///     # 0x00660 PERIF                
///               $PERIF               PERIF             REG          
///     @ 0x00688                      (W-)
///     #         # Stuffing bytes...
///               %% 3008
///     @ 0x00800                      (P)
///     # 0x00800 ADC                  
///               $ADC                 ADC               REG          
///     @ 0x00810                      (P)
///     # 0x00810 PVT                  
///               $PVT_Sens            PVT               REG          
///                                    ###
///                                    * PAD Control Region
///                                    ###
///     @ 0x0081C Global_PADRING       (P-)
///               %unsigned 1  MODE_SEL                  0x0
///                                    ###
///                                    * 0: auto-selection independent of MODE18 bit
///                                    * 1: manual selection by MOD18 for power supply on rail VDDIO is switched from 1.8V to 3.3V.
///                                    ###
///               %unsigned 1  MODE_18                   0x0
///                                    ###
///                                    * 0: for other then 1.8V
///                                    * 1: for 1.8V(typical) mode operation
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00820 SPI_PADRING          (P-)
///               %unsigned 1  MODE_SEL                  0x0
///               %unsigned 1  MODE_18                   0x0
///               %%        30         # Stuffing bits...
///     @ 0x00824 NAND_PADRING         (P-)
///               %unsigned 1  MODE_SEL                  0x0
///               %unsigned 1  MODE_18                   0x0
///               %%        30         # Stuffing bits...
///     @ 0x00828 SD0_PADRING          (P-)
///               %unsigned 1  MODE_SEL                  0x0
///               %unsigned 1  MODE_18                   0x0
///               %%        30         # Stuffing bits...
///     @ 0x0082C I2S_PADRING          (P-)
///               %unsigned 1  MODE_SEL                  0x0
///               %unsigned 1  MODE_18                   0x0
///               %%        30         # Stuffing bits...
///     @ 0x00830 I2S3_PADRING         (P-)
///               %unsigned 1  MODE_SEL                  0x0
///               %unsigned 1  MODE_18                   0x0
///               %%        30         # Stuffing bits...
///     @ 0x00834 PWM_PADRING          (P-)
///               %unsigned 1  MODE_SEL                  0x0
///               %unsigned 1  MODE_18                   0x0
///               %%        30         # Stuffing bits...
///     @ 0x00838 XTL_CTL              (P-)
///               %unsigned 4  XTL_GM_SEL                0x8
///                                    ###
///                                    * Oscillator pad POSC_I gain control to generate negative resistance that compensates the basic architecture of the crystal oscillator pad.
///                                    * 0:2mS
///                                    * 1:4mS
///                                    * ….
///                                    * 15:32mS
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x0083C PADRING_MODE_OUT     (R-)
///               %unsigned 7  MODE_OUT                  
///                                    ###
///                                    * MODE = 1 for 1.8 V (Typical) mode operation MODE = 0 for 3.3 V
///                                    * (Typical) mode
///                                    * The below are the Pad Control Registers starting at 32KB boundary. Please do not change this offset and add any register that is needed before this.
///                                    ###
///               %%        25         # Stuffing bits...
///     @ 0x00840 pinMuxCntlBus        (P-)
///               %unsigned 3  I2S1_BCLKIO               0x0
///                                    ###
///                                    * pinMuxCntlBus[0*3+2:0*3]	 pinMux Control for I2S1_BCLKIO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S1_LRCKIO               0x0
///                                    ###
///                                    * pinMuxCntlBus[1*3+2:1*3]	 pinMux Control for I2S1_LRCKIO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S1_DO0                  0x0
///                                    ###
///                                    * pinMuxCntlBus[2*3+2:2*3]	 pinMux Control for I2S1_DO[0]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S1_DO1                  0x0
///                                    ###
///                                    * pinMuxCntlBus[3*3+2:3*3]	 pinMux Control for I2S1_DO[1]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S1_DO2                  0x0
///                                    ###
///                                    * pinMuxCntlBus[4*3+2:4*3]	 pinMux Control for I2S1_DO[2]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S1_DO3                  0x0
///                                    ###
///                                    * pinMuxCntlBus[5*3+2:5*3]	 pinMux Control for I2S1_DO[3]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S1_MCLK                 0x0
///                                    ###
///                                    * pinMuxCntlBus[6*3+2:6*3]	 pinMux Control for I2S1_MCLK
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S2_BCLKIO               0x0
///                                    ###
///                                    * pinMuxCntlBus[7*3+2:7*3]	 pinMux Control for I2S2_BCLKIO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S2_LRCKIO               0x0
///                                    ###
///                                    * pinMuxCntlBus[8*3+2:8*3]	 pinMux Control for I2S2_LRCKIO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S2_DI0                  0x0
///                                    ###
///                                    * pinMuxCntlBus[9*3+2:9*3]	 pinMux Control for I2S2_DI[0]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_5                    0x5
///               %%        2          # Stuffing bits...
///     # 0x00844 pinMuxCntlBus1       
///               %unsigned 3  I2S2_DI1                  0x0
///                                    ###
///                                    * pinMuxCntlBus[10*3+2:10*3]	 pinMux Control for I2S2_DI[1]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S2_DI2                  0x0
///                                    ###
///                                    * pinMuxCntlBus[11*3+2:11*3]	 pinMux Control for I2S2_DI[2]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S2_DI3                  0x0
///                                    ###
///                                    * pinMuxCntlBus[12*3+2:12*3]	 pinMux Control for I2S2_DI[3]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  PDM_CLKO                  0x0
///                                    ###
///                                    * pinMuxCntlBus[13*3+2:13*3]	 pinMux Control for PDM_CLKO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_5                    0x5
///               %unsigned 3  PDM_DI0                   0x0
///                                    ###
///                                    * pinMuxCntlBus[14*3+2:14*3]	 pinMux Control for PDM_DI[0]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  PDM_DI1                   0x0
///                                    ###
///                                    * pinMuxCntlBus[15*3+2:15*3]	 pinMux Control for PDM_DI[1]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  PDM_DI2                   0x0
///                                    ###
///                                    * pinMuxCntlBus[16*3+2:16*3]	 pinMux Control for PDM_DI[2]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  PDM_DI3                   0x0
///                                    ###
///                                    * pinMuxCntlBus[17*3+2:17*3]	 pinMux Control for PDM_DI[3]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  NAND_IO0                  0x0
///                                    ###
///                                    * pinMuxCntlBus[18*3+2:18*3]	 pinMux Control for NAND_IO[0]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %unsigned 3  NAND_IO1                  0x0
///                                    ###
///                                    * pinMuxCntlBus[19*3+2:19*3]	 pinMux Control for NAND_IO[1]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %%        2          # Stuffing bits...
///     # 0x00848 pinMuxCntlBus2       
///               %unsigned 3  NAND_IO2                  0x0
///                                    ###
///                                    * pinMuxCntlBus[20*3+2:20*3]	 pinMux Control for NAND_IO[2]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %unsigned 3  NAND_IO3                  0x0
///                                    ###
///                                    * pinMuxCntlBus[21*3+2:21*3]	 pinMux Control for NAND_IO[3]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %unsigned 3  NAND_IO4                  0x0
///                                    ###
///                                    * pinMuxCntlBus[22*3+2:22*3]	 pinMux Control for NAND_IO[4]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  NAND_IO5                  0x0
///                                    ###
///                                    * pinMuxCntlBus[23*3+2:23*3]	 pinMux Control for NAND_IO[5]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  NAND_IO6                  0x0
///                                    ###
///                                    * pinMuxCntlBus[24*3+2:24*3]	 pinMux Control for NAND_IO[6]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  NAND_IO7                  0x0
///                                    ###
///                                    * pinMuxCntlBus[25*3+2:25*3]	 pinMux Control for NAND_IO[7]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  NAND_ALE                  0x0
///                                    ###
///                                    * pinMuxCntlBus[26*3+2:26*3]	 pinMux Control for NAND_ALE
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///               %unsigned 3  NAND_CLE                  0x0
///                                    ###
///                                    * pinMuxCntlBus[27*3+2:27*3]	 pinMux Control for NAND_CLE
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///               %unsigned 3  NAND_WEn                  0x0
///                                    ###
///                                    * pinMuxCntlBus[28*3+2:28*3]	 pinMux Control for NAND_WEn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_3                    0x3
///               %unsigned 3  NAND_REn                  0x0
///                                    ###
///                                    * pinMuxCntlBus[29*3+2:29*3]	 pinMux Control for NAND_REn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_3                    0x3
///               %%        2          # Stuffing bits...
///     # 0x0084C pinMuxCntlBus3       
///               %unsigned 3  NAND_WPn                  0x0
///                                    ###
///                                    * pinMuxCntlBus[30*3+2:30*3]	 pinMux Control for NAND_WPn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  NAND_CEn                  0x0
///                                    ###
///                                    * pinMuxCntlBus[31*3+2:31*3]	 pinMux Control for NAND_CEn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  NAND_RDY                  0x0
///                                    ###
///                                    * pinMuxCntlBus[32*3+2:32*3]	 pinMux Control for NAND_RDY
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  SPI1_SS0n                 0x0
///                                    ###
///                                    * pinMuxCntlBus[33*3+2:33*3]	 pinMux Control for SPI1_SS0n
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  SPI1_SS1n                 0x0
///                                    ###
///                                    * pinMuxCntlBus[34*3+2:34*3]	 pinMux Control for SPI1_SS1n
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///               %unsigned 3  SPI1_SS2n                 0x0
///                                    ###
///                                    * pinMuxCntlBus[35*3+2:35*3]	 pinMux Control for SPI1_SS2n
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///               %unsigned 3  SPI1_SS3n                 0x0
///                                    ###
///                                    * pinMuxCntlBus[36*3+2:36*3]	 pinMux Control for SPI1_SS3n
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %unsigned 3  SPI1_SCLK                 0x0
///                                    ###
///                                    * pinMuxCntlBus[37*3+2:37*3]	 pinMux Control for SPI1_SCLK
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  SPI1_SDO                  0x0
///                                    ###
///                                    * pinMuxCntlBus[38*3+2:38*3]	 pinMux Control for SPI1_SDO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  SPI1_SDI                  0x0
///                                    ###
///                                    * pinMuxCntlBus[39*3+2:39*3]	 pinMux Control for SPI1_SDI
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %%        2          # Stuffing bits...
///     # 0x00850 pinMuxCntlBus4       
///               %unsigned 3  USB0_DRV_VBUS             0x0
///                                    ###
///                                    * pinMuxCntlBus[40*3+2:40*3]	 pinMux Control for USB0_DRV_VBUS
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  TW1_SCL                   0x0
///                                    ###
///                                    * pinMuxCntlBus[41*3+2:41*3]	 pinMux Control for TW1_SCL
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  TW1_SDA                   0x0
///                                    ###
///                                    * pinMuxCntlBus[42*3+2:42*3]	 pinMux Control for TW1_SDA
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  TW0_SCL                   0x0
///                                    ###
///                                    * pinMuxCntlBus[43*3+2:43*3]	 pinMux Control for TW0_SCL
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  TW0_SDA                   0x0
///                                    ###
///                                    * pinMuxCntlBus[44*3+2:44*3]	 pinMux Control for TW0_SDA
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  TMS                       0x0
///                                    ###
///                                    * pinMuxCntlBus[45*3+2:45*3]	 pinMux Control for TMS
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %unsigned 3  TDI                       0x0
///                                    ###
///                                    * pinMuxCntlBus[46*3+2:46*3]	 pinMux Control for TDI
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %unsigned 3  TDO                       0x0
///                                    ###
///                                    * pinMuxCntlBus[47*3+2:47*3]	 pinMux Control for TDO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///               %unsigned 3  PWM6                      0x0
///                                    ###
///                                    * pinMuxCntlBus[48*3+2:48*3]	 pinMux Control for PWM[6]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  PWM7                      0x0
///                                    ###
///                                    * pinMuxCntlBus[49*3+2:49*3]	 pinMux Control for PWM[7]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %%        2          # Stuffing bits...
///     # 0x00854 pinMuxCntlBus5       
///               %unsigned 3  PWM0                      0x0
///                                    ###
///                                    * pinMuxCntlBus[50*3+2:50*3]	 pinMux Control for PWM[0]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %unsigned 3  PWM1                      0x0
///                                    ###
///                                    * pinMuxCntlBus[51*3+2:51*3]	 pinMux Control for PWM[1]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  PWM2                      0x0
///                                    ###
///                                    * pinMuxCntlBus[52*3+2:52*3]	 pinMux Control for PWM[2]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  PWM3                      0x0
///                                    ###
///                                    * pinMuxCntlBus[53*3+2:53*3]	 pinMux Control for PWM[3]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  PWM4                      0x0
///                                    ###
///                                    * pinMuxCntlBus[54*3+2:54*3]	 pinMux Control for PWM[4]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  PWM5                      0x0
///                                    ###
///                                    * pinMuxCntlBus[55*3+2:55*3]	 pinMux Control for PWM[5]
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  URT1_RTSn                 0x0
///                                    ###
///                                    * pinMuxCntlBus[56*3+2:56*3]	 pinMux Control for URT1_RTSn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  URT1_CTSn                 0x0
///                                    ###
///                                    * pinMuxCntlBus[57*3+2:57*3]	 pinMux Control for URT1_CTSn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///                                    : MODE_3                    0x3
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  URT1_RXD                  0x0
///                                    ###
///                                    * pinMuxCntlBus[58*3+2:58*3]	 pinMux Control for URT1_RXD
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %unsigned 3  URT1_TXD                  0x0
///                                    ###
///                                    * pinMuxCntlBus[59*3+2:59*3]	 pinMux Control for URT1_TXD
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_4                    0x4
///                                    : MODE_5                    0x5
///               %%        2          # Stuffing bits...
///     # 0x00858 pinMuxCntlBus6       
///               %unsigned 3  I2S3_DI                   0x0
///                                    ###
///                                    * pinMuxCntlBus[60*3+2:60*3]	 pinMux Control for I2S3_DI
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S3_DO                   0x0
///                                    ###
///                                    * pinMuxCntlBus[61*3+2:61*3]	 pinMux Control for I2S3_DO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S3_BCLKIO               0x0
///                                    ###
///                                    * pinMuxCntlBus[62*3+2:62*3]	 pinMux Control for I2S3_BCLKIO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_5                    0x5
///               %unsigned 3  I2S3_LRCKIO               0x0
///                                    ###
///                                    * pinMuxCntlBus[63*3+2:63*3]	 pinMux Control for I2S3_LRCKIO
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  SD0_DAT0                  0x0
///                                    ###
///                                    * pinMuxCntlBus[64*3+2:64*3]	 pinMux Control for SD0_DAT0
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %unsigned 3  SD0_DAT1                  0x0
///                                    ###
///                                    * pinMuxCntlBus[65*3+2:65*3]	 pinMux Control for SD0_DAT1
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %unsigned 3  SD0_CLK                   0x0
///                                    ###
///                                    * pinMuxCntlBus[66*3+2:66*3]	 pinMux Control for SD0_CLK
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///               %unsigned 3  SD0_DAT2                  0x0
///                                    ###
///                                    * pinMuxCntlBus[67*3+2:67*3]	 pinMux Control for SD0_DAT2
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %unsigned 3  SD0_DAT3                  0x0
///                                    ###
///                                    * pinMuxCntlBus[68*3+2:68*3]	 pinMux Control for SD0_DAT3
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %unsigned 3  SD0_CMD                   0x0
///                                    ###
///                                    * pinMuxCntlBus[69*3+2:69*3]	 pinMux Control for SD0_CMD
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_2                    0x2
///               %%        2          # Stuffing bits...
///     # 0x0085C pinMuxCntlBus7       
///               %unsigned 3  SD0_CDn                   0x0
///                                    ###
///                                    * pinMuxCntlBus[70*3+2:70*3]	 pinMux Control for SD0_CDn
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %unsigned 3  SD0_WP                    0x0
///                                    ###
///                                    * pinMuxCntlBus[71*3+2:71*3]	 pinMux Control for SD0_WP
///                                    ###
///                                    : MODE_0                    0x0
///                                    : MODE_1                    0x1
///                                    : MODE_3                    0x3
///               %%        26         # Stuffing bits...
///     @ 0x00860 I2S1_BCLKIOCntl      (P-)
///               ###
///               * Pad Control for I2S1_BCLKIO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00864 I2S1_LRCKIOCntl      (P-)
///               ###
///               * Pad Control for I2S1_LRCKIO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00868 I2S1_DO0Cntl         (P-)
///               ###
///               * Pad Control for I2S1_DO[0]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x0086C I2S1_DO1Cntl         (P-)
///               ###
///               * Pad Control for I2S1_DO[1]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00870 I2S1_DO2Cntl         (P-)
///               ###
///               * Pad Control for I2S1_DO[2]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00874 I2S1_DO3Cntl         (P-)
///               ###
///               * Pad Control for I2S1_DO[3]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00878 I2S1_MCLKCntl        (P-)
///               ###
///               * Pad Control for I2S1_MCLK
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0087C I2S2_BCLKIOCntl      (P-)
///               ###
///               * Pad Control for I2S2_BCLKIO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00880 I2S2_LRCKIOCntl      (P-)
///               ###
///               * Pad Control for I2S2_LRCKIO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00884 I2S2_DI0Cntl         (P-)
///               ###
///               * Pad Control for I2S2_DI[0]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00888 I2S2_DI1Cntl         (P-)
///               ###
///               * Pad Control for I2S2_DI[1]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x0088C I2S2_DI2Cntl         (P-)
///               ###
///               * Pad Control for I2S2_DI[2]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00890 I2S2_DI3Cntl         (P-)
///               ###
///               * Pad Control for I2S2_DI[3]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00894 PDM_CLKOCntl         (P-)
///               ###
///               * Pad Control for PDM_CLKO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00898 PDM_DI0Cntl          (P-)
///               ###
///               * Pad Control for PDM_DI[0]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x0089C PDM_DI1Cntl          (P-)
///               ###
///               * Pad Control for PDM_DI[1]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008A0 PDM_DI2Cntl          (P-)
///               ###
///               * Pad Control for PDM_DI[2]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008A4 PDM_DI3Cntl          (P-)
///               ###
///               * Pad Control for PDM_DI[3]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008A8 NAND_IO0Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[0]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008AC NAND_IO1Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[1]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008B0 NAND_IO2Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[2]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008B4 NAND_IO3Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[3]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008B8 NAND_IO4Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[4]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008BC NAND_IO5Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[5]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008C0 NAND_IO6Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[6]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008C4 NAND_IO7Cntl         (P-)
///               ###
///               * Pad Control for NAND_IO[7]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008C8 NAND_ALECntl         (P-)
///               ###
///               * Pad Control for NAND_ALE
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x1
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008CC NAND_CLECntl         (P-)
///               ###
///               * Pad Control for NAND_CLE
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x1
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008D0 NAND_WEnCntl         (P-)
///               ###
///               * Pad Control for NAND_WEn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008D4 NAND_REnCntl         (P-)
///               ###
///               * Pad Control for NAND_REn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008D8 NAND_WPnCntl         (P-)
///               ###
///               * Pad Control for NAND_WPn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008DC NAND_CEnCntl         (P-)
///               ###
///               * Pad Control for NAND_CEn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008E0 NAND_RDYCntl         (P-)
///               ###
///               * Pad Control for NAND_RDY
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x008E4 SPI1_SS0nCntl        (P-)
///               ###
///               * Pad Control for SPI1_SS0n
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x1
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008E8 SPI1_SS1nCntl        (P-)
///               ###
///               * Pad Control for SPI1_SS1n
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008EC SPI1_SS2nCntl        (P-)
///               ###
///               * Pad Control for SPI1_SS2n
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008F0 SPI1_SS3nCntl        (P-)
///               ###
///               * Pad Control for SPI1_SS3n
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008F4 SPI1_SCLKCntl        (P-)
///               ###
///               * Pad Control for SPI1_SCLK
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008F8 SPI1_SDOCntl         (P-)
///               ###
///               * Pad Control for SPI1_SDO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x1
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x008FC SPI1_SDICntl         (P-)
///               ###
///               * Pad Control for SPI1_SDI
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00900 USB0_DRV_VBUSCntl    (P-)
///               ###
///               * Pad Control for USB0_DRV_VBUS
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00904 TW1_SCLCntl          (P-)
///               ###
///               * Pad Control for TW1_SCL
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00908 TW1_SDACntl          (P-)
///               ###
///               * Pad Control for TW1_SDA
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0090C TW0_SCLCntl          (P-)
///               ###
///               * Pad Control for TW0_SCL
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00910 TW0_SDACntl          (P-)
///               ###
///               * Pad Control for TW0_SDA
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00914 TMSCntl              (P-)
///               ###
///               * Pad Control for TMS
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x1
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00918 TDICntl              (P-)
///               ###
///               * Pad Control for TDI
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x1
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0091C TDOCntl              (P-)
///               ###
///               * Pad Control for TDO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x1
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00920 PWM6Cntl             (P-)
///               ###
///               * Pad Control for PWM[6]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00924 PWM7Cntl             (P-)
///               ###
///               * Pad Control for PWM[7]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00928 PWM0Cntl             (P-)
///               ###
///               * Pad Control for PWM[0]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x0092C PWM1Cntl             (P-)
///               ###
///               * Pad Control for PWM[1]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00930 PWM2Cntl             (P-)
///               ###
///               * Pad Control for PWM[2]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00934 PWM3Cntl             (P-)
///               ###
///               * Pad Control for PWM[3]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00938 PWM4Cntl             (P-)
///               ###
///               * Pad Control for PWM[4]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x0093C PWM5Cntl             (P-)
///               ###
///               * Pad Control for PWM[5]
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00940 URT1_RTSnCntl        (P-)
///               ###
///               * Pad Control for URT1_RTSn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00944 URT1_CTSnCntl        (P-)
///               ###
///               * Pad Control for URT1_CTSn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00948 URT1_RXDCntl         (P-)
///               ###
///               * Pad Control for URT1_RXD
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0094C URT1_TXDCntl         (P-)
///               ###
///               * Pad Control for URT1_TXD
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00950 I2S3_DICntl          (P-)
///               ###
///               * Pad Control for I2S3_DI
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00954 I2S3_DOCntl          (P-)
///               ###
///               * Pad Control for I2S3_DO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        26         # Stuffing bits...
///     @ 0x00958 I2S3_BCLKIOCntl      (P-)
///               ###
///               * Pad Control for I2S3_BCLKIO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0095C I2S3_LRCKIOCntl      (P-)
///               ###
///               * Pad Control for I2S3_LRCKIO
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00960 SD0_DAT0Cntl         (P-)
///               ###
///               * Pad Control for SD0_DAT0
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00964 SD0_DAT1Cntl         (P-)
///               ###
///               * Pad Control for SD0_DAT1
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00968 SD0_CLKCntl          (P-)
///               ###
///               * Pad Control for SD0_CLK
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x1
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0096C SD0_DAT2Cntl         (P-)
///               ###
///               * Pad Control for SD0_DAT2
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00970 SD0_DAT3Cntl         (P-)
///               ###
///               * Pad Control for SD0_DAT3
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00974 SD0_CMDCntl          (P-)
///               ###
///               * Pad Control for SD0_CMD
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x00978 SD0_CDnCntl          (P-)
///               ###
///               * Pad Control for SD0_CDn
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     @ 0x0097C SD0_WPCntl           (P-)
///               ###
///               * Pad Control for SD0_WP
///               ###
///               %unsigned 2  DRV                       0x0
///               %unsigned 1  PDEN                      0x0
///               %unsigned 1  PUEN                      0x0
///               %unsigned 1  RXEN                      0x1
///               %unsigned 1  SRC                       0x0
///               %unsigned 1  SMTC                      0x0
///               %%        25         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    2432B, bits:    1789b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_Gbl
#define h_Gbl (){}

    #define     RA_Gbl_ProductId                               0x0000

    #define     BA_Gbl_ProductId_Id                            0x0000
    #define     B16Gbl_ProductId_Id                            0x0000
    #define   LSb32Gbl_ProductId_Id                               0
    #define   LSb16Gbl_ProductId_Id                               0
    #define       bGbl_ProductId_Id                            32
    #define   MSK32Gbl_ProductId_Id                               0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_ProductId_ext                           0x0004

    #define     BA_Gbl_ProductId_ext_ID_EXT                    0x0004
    #define     B16Gbl_ProductId_ext_ID_EXT                    0x0004
    #define   LSb32Gbl_ProductId_ext_ID_EXT                       0
    #define   LSb16Gbl_ProductId_ext_ID_EXT                       0
    #define       bGbl_ProductId_ext_ID_EXT                    8
    #define   MSK32Gbl_ProductId_ext_ID_EXT                       0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_INT_ID                                  0x0008

    #define     BA_Gbl_INT_ID_VALUE                            0x0008
    #define     B16Gbl_INT_ID_VALUE                            0x0008
    #define   LSb32Gbl_INT_ID_VALUE                               0
    #define   LSb16Gbl_INT_ID_VALUE                               0
    #define       bGbl_INT_ID_VALUE                            8
    #define   MSK32Gbl_INT_ID_VALUE                               0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_bootStrap                               0x000C

    #define     BA_Gbl_bootStrap_softwareStrap                 0x000C
    #define     B16Gbl_bootStrap_softwareStrap                 0x000C
    #define   LSb32Gbl_bootStrap_softwareStrap                    0
    #define   LSb16Gbl_bootStrap_softwareStrap                    0
    #define       bGbl_bootStrap_softwareStrap                 16
    #define   MSK32Gbl_bootStrap_softwareStrap                    0x0000FFFF

    #define     BA_Gbl_bootStrap_bootSrc                       0x000E
    #define     B16Gbl_bootStrap_bootSrc                       0x000E
    #define   LSb32Gbl_bootStrap_bootSrc                          16
    #define   LSb16Gbl_bootStrap_bootSrc                          0
    #define       bGbl_bootStrap_bootSrc                       2
    #define   MSK32Gbl_bootStrap_bootSrc                          0x00030000
    #define        Gbl_bootStrap_bootSrc_ROM_SPI_BOOT                       0x0
    #define        Gbl_bootStrap_bootSrc_ROM_NAND_BOOT                      0x1
    #define        Gbl_bootStrap_bootSrc_ROM_EMMC_BOOT                      0x2
    #define        Gbl_bootStrap_bootSrc_ROM_SPI_DIRECT_BOOT                0x3

    #define     BA_Gbl_bootStrap_cpuRstByps                    0x000E
    #define     B16Gbl_bootStrap_cpuRstByps                    0x000E
    #define   LSb32Gbl_bootStrap_cpuRstByps                       18
    #define   LSb16Gbl_bootStrap_cpuRstByps                       2
    #define       bGbl_bootStrap_cpuRstByps                    1
    #define   MSK32Gbl_bootStrap_cpuRstByps                       0x00040000
    #define        Gbl_bootStrap_cpuRstByps_CPU_INT_RST_BYPS                0x1
    #define        Gbl_bootStrap_cpuRstByps_CPU_INT_RST_EN                  0x0

    #define     BA_Gbl_bootStrap_pllPwrDown                    0x000E
    #define     B16Gbl_bootStrap_pllPwrDown                    0x000E
    #define   LSb32Gbl_bootStrap_pllPwrDown                       19
    #define   LSb16Gbl_bootStrap_pllPwrDown                       3
    #define       bGbl_bootStrap_pllPwrDown                    1
    #define   MSK32Gbl_bootStrap_pllPwrDown                       0x00080000
    #define        Gbl_bootStrap_pllPwrDown_PWR_DOWN                        0x1
    #define        Gbl_bootStrap_pllPwrDown_PWR_UP                          0x0

    #define     BA_Gbl_bootStrap_sysPllByps                    0x000E
    #define     B16Gbl_bootStrap_sysPllByps                    0x000E
    #define   LSb32Gbl_bootStrap_sysPllByps                       20
    #define   LSb16Gbl_bootStrap_sysPllByps                       4
    #define       bGbl_bootStrap_sysPllByps                    1
    #define   MSK32Gbl_bootStrap_sysPllByps                       0x00100000
    #define        Gbl_bootStrap_sysPllByps_PLL_OUT                         0x0
    #define        Gbl_bootStrap_sysPllByps_BYPS                            0x1

    #define     BA_Gbl_bootStrap_memPllByps                    0x000E
    #define     B16Gbl_bootStrap_memPllByps                    0x000E
    #define   LSb32Gbl_bootStrap_memPllByps                       21
    #define   LSb16Gbl_bootStrap_memPllByps                       5
    #define       bGbl_bootStrap_memPllByps                    1
    #define   MSK32Gbl_bootStrap_memPllByps                       0x00200000
    #define        Gbl_bootStrap_memPllByps_PLL_OUT                         0x0
    #define        Gbl_bootStrap_memPllByps_BYPS                            0x1

    #define     BA_Gbl_bootStrap_cpuPllByps                    0x000E
    #define     B16Gbl_bootStrap_cpuPllByps                    0x000E
    #define   LSb32Gbl_bootStrap_cpuPllByps                       22
    #define   LSb16Gbl_bootStrap_cpuPllByps                       6
    #define       bGbl_bootStrap_cpuPllByps                    1
    #define   MSK32Gbl_bootStrap_cpuPllByps                       0x00400000
    #define        Gbl_bootStrap_cpuPllByps_PLL_OUT                         0x0
    #define        Gbl_bootStrap_cpuPllByps_BYPS                            0x1

    #define     BA_Gbl_bootStrap_ENG_EN                        0x000E
    #define     B16Gbl_bootStrap_ENG_EN                        0x000E
    #define   LSb32Gbl_bootStrap_ENG_EN                           23
    #define   LSb16Gbl_bootStrap_ENG_EN                           7
    #define       bGbl_bootStrap_ENG_EN                        1
    #define   MSK32Gbl_bootStrap_ENG_EN                           0x00800000
    #define        Gbl_bootStrap_ENG_EN_PRODUCTION_MODE                     0x0
    #define        Gbl_bootStrap_ENG_EN_DEVELOPE_MODE                       0x1

    #define     BA_Gbl_bootStrap_LEGACY_BOOT                   0x000F
    #define     B16Gbl_bootStrap_LEGACY_BOOT                   0x000E
    #define   LSb32Gbl_bootStrap_LEGACY_BOOT                      24
    #define   LSb16Gbl_bootStrap_LEGACY_BOOT                      8
    #define       bGbl_bootStrap_LEGACY_BOOT                   1
    #define   MSK32Gbl_bootStrap_LEGACY_BOOT                      0x01000000
    #define        Gbl_bootStrap_LEGACY_BOOT_FAST_BOOT_MODE                 0x0
    #define        Gbl_bootStrap_LEGACY_BOOT_LEGACY_BOOT_MODE               0x1
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_bootStrapEn                             0x0010

    #define     BA_Gbl_bootStrapEn_cpuRstBypsEn                0x0010
    #define     B16Gbl_bootStrapEn_cpuRstBypsEn                0x0010
    #define   LSb32Gbl_bootStrapEn_cpuRstBypsEn                   0
    #define   LSb16Gbl_bootStrapEn_cpuRstBypsEn                   0
    #define       bGbl_bootStrapEn_cpuRstBypsEn                1
    #define   MSK32Gbl_bootStrapEn_cpuRstBypsEn                   0x00000001
    #define        Gbl_bootStrapEn_cpuRstBypsEn_ENABLE                      0x1
    #define        Gbl_bootStrapEn_cpuRstBypsEn_DISABLE                     0x0

    #define     BA_Gbl_bootStrapEn_pllPwrDownEn                0x0010
    #define     B16Gbl_bootStrapEn_pllPwrDownEn                0x0010
    #define   LSb32Gbl_bootStrapEn_pllPwrDownEn                   1
    #define   LSb16Gbl_bootStrapEn_pllPwrDownEn                   1
    #define       bGbl_bootStrapEn_pllPwrDownEn                1
    #define   MSK32Gbl_bootStrapEn_pllPwrDownEn                   0x00000002
    #define        Gbl_bootStrapEn_pllPwrDownEn_ENABLE                      0x1
    #define        Gbl_bootStrapEn_pllPwrDownEn_DISABLE                     0x0

    #define     BA_Gbl_bootStrapEn_sysPLLBypsEn                0x0010
    #define     B16Gbl_bootStrapEn_sysPLLBypsEn                0x0010
    #define   LSb32Gbl_bootStrapEn_sysPLLBypsEn                   2
    #define   LSb16Gbl_bootStrapEn_sysPLLBypsEn                   2
    #define       bGbl_bootStrapEn_sysPLLBypsEn                1
    #define   MSK32Gbl_bootStrapEn_sysPLLBypsEn                   0x00000004
    #define        Gbl_bootStrapEn_sysPLLBypsEn_ENABLE                      0x1
    #define        Gbl_bootStrapEn_sysPLLBypsEn_DISABLE                     0x0

    #define     BA_Gbl_bootStrapEn_memPLLBypsEn                0x0010
    #define     B16Gbl_bootStrapEn_memPLLBypsEn                0x0010
    #define   LSb32Gbl_bootStrapEn_memPLLBypsEn                   3
    #define   LSb16Gbl_bootStrapEn_memPLLBypsEn                   3
    #define       bGbl_bootStrapEn_memPLLBypsEn                1
    #define   MSK32Gbl_bootStrapEn_memPLLBypsEn                   0x00000008
    #define        Gbl_bootStrapEn_memPLLBypsEn_ENABLE                      0x1
    #define        Gbl_bootStrapEn_memPLLBypsEn_DISABLE                     0x0

    #define     BA_Gbl_bootStrapEn_cpuPLLBypsEn                0x0010
    #define     B16Gbl_bootStrapEn_cpuPLLBypsEn                0x0010
    #define   LSb32Gbl_bootStrapEn_cpuPLLBypsEn                   4
    #define   LSb16Gbl_bootStrapEn_cpuPLLBypsEn                   4
    #define       bGbl_bootStrapEn_cpuPLLBypsEn                1
    #define   MSK32Gbl_bootStrapEn_cpuPLLBypsEn                   0x00000010
    #define        Gbl_bootStrapEn_cpuPLLBypsEn_ENABLE                      0x1
    #define        Gbl_bootStrapEn_cpuPLLBypsEn_DISABLE                     0x0

    #define     BA_Gbl_bootStrapEn_legacyBootEn                0x0010
    #define     B16Gbl_bootStrapEn_legacyBootEn                0x0010
    #define   LSb32Gbl_bootStrapEn_legacyBootEn                   5
    #define   LSb16Gbl_bootStrapEn_legacyBootEn                   5
    #define       bGbl_bootStrapEn_legacyBootEn                1
    #define   MSK32Gbl_bootStrapEn_legacyBootEn                   0x00000020
    #define        Gbl_bootStrapEn_legacyBootEn_ENABLE                      0x1
    #define        Gbl_bootStrapEn_legacyBootEn_DISABLE                     0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pkgSel                                  0x0014

    #define     BA_Gbl_pkgSel_DDR32bit                         0x0014
    #define     B16Gbl_pkgSel_DDR32bit                         0x0014
    #define   LSb32Gbl_pkgSel_DDR32bit                            0
    #define   LSb16Gbl_pkgSel_DDR32bit                            0
    #define       bGbl_pkgSel_DDR32bit                         1
    #define   MSK32Gbl_pkgSel_DDR32bit                            0x00000001

    #define     BA_Gbl_pkgSel_reserved                         0x0014
    #define     B16Gbl_pkgSel_reserved                         0x0014
    #define   LSb32Gbl_pkgSel_reserved                            1
    #define   LSb16Gbl_pkgSel_reserved                            1
    #define       bGbl_pkgSel_reserved                         1
    #define   MSK32Gbl_pkgSel_reserved                            0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_chipCntl                                0x0018

    #define     BA_Gbl_chipCntl_SD0_CLK_LPBK_EN                0x0018
    #define     B16Gbl_chipCntl_SD0_CLK_LPBK_EN                0x0018
    #define   LSb32Gbl_chipCntl_SD0_CLK_LPBK_EN                   0
    #define   LSb16Gbl_chipCntl_SD0_CLK_LPBK_EN                   0
    #define       bGbl_chipCntl_SD0_CLK_LPBK_EN                1
    #define   MSK32Gbl_chipCntl_SD0_CLK_LPBK_EN                   0x00000001

    #define     BA_Gbl_chipCntl_SD0_CLK_LPBK_SEL               0x0018
    #define     B16Gbl_chipCntl_SD0_CLK_LPBK_SEL               0x0018
    #define   LSb32Gbl_chipCntl_SD0_CLK_LPBK_SEL                  1
    #define   LSb16Gbl_chipCntl_SD0_CLK_LPBK_SEL                  1
    #define       bGbl_chipCntl_SD0_CLK_LPBK_SEL               1
    #define   MSK32Gbl_chipCntl_SD0_CLK_LPBK_SEL                  0x00000002

    #define     BA_Gbl_chipCntl_EMMC_CLK_LPBK_EN               0x0018
    #define     B16Gbl_chipCntl_EMMC_CLK_LPBK_EN               0x0018
    #define   LSb32Gbl_chipCntl_EMMC_CLK_LPBK_EN                  2
    #define   LSb16Gbl_chipCntl_EMMC_CLK_LPBK_EN                  2
    #define       bGbl_chipCntl_EMMC_CLK_LPBK_EN               1
    #define   MSK32Gbl_chipCntl_EMMC_CLK_LPBK_EN                  0x00000004

    #define     BA_Gbl_chipCntl_EMMC_CLK_LPBK_SEL              0x0018
    #define     B16Gbl_chipCntl_EMMC_CLK_LPBK_SEL              0x0018
    #define   LSb32Gbl_chipCntl_EMMC_CLK_LPBK_SEL                 3
    #define   LSb16Gbl_chipCntl_EMMC_CLK_LPBK_SEL                 3
    #define       bGbl_chipCntl_EMMC_CLK_LPBK_SEL              1
    #define   MSK32Gbl_chipCntl_EMMC_CLK_LPBK_SEL                 0x00000008

    #define     BA_Gbl_chipCntl_I2S_FB_SEL                     0x0018
    #define     B16Gbl_chipCntl_I2S_FB_SEL                     0x0018
    #define   LSb32Gbl_chipCntl_I2S_FB_SEL                        4
    #define   LSb16Gbl_chipCntl_I2S_FB_SEL                        4
    #define       bGbl_chipCntl_I2S_FB_SEL                     10
    #define   MSK32Gbl_chipCntl_I2S_FB_SEL                        0x00003FF0

    #define     BA_Gbl_chipCntl_SPDIFI_SEL                     0x0019
    #define     B16Gbl_chipCntl_SPDIFI_SEL                     0x0018
    #define   LSb32Gbl_chipCntl_SPDIFI_SEL                        14
    #define   LSb16Gbl_chipCntl_SPDIFI_SEL                        14
    #define       bGbl_chipCntl_SPDIFI_SEL                     3
    #define   MSK32Gbl_chipCntl_SPDIFI_SEL                        0x0001C000

    #define     BA_Gbl_chipCntl_TW1_SEL                        0x001A
    #define     B16Gbl_chipCntl_TW1_SEL                        0x001A
    #define   LSb32Gbl_chipCntl_TW1_SEL                           17
    #define   LSb16Gbl_chipCntl_TW1_SEL                           1
    #define       bGbl_chipCntl_TW1_SEL                        1
    #define   MSK32Gbl_chipCntl_TW1_SEL                           0x00020000

    #define     BA_Gbl_chipCntl_DBG_SEL                        0x001A
    #define     B16Gbl_chipCntl_DBG_SEL                        0x001A
    #define   LSb32Gbl_chipCntl_DBG_SEL                           18
    #define   LSb16Gbl_chipCntl_DBG_SEL                           2
    #define       bGbl_chipCntl_DBG_SEL                        3
    #define   MSK32Gbl_chipCntl_DBG_SEL                           0x001C0000

    #define     BA_Gbl_chipCntl_CLK_DBG_SEL                    0x001A
    #define     B16Gbl_chipCntl_CLK_DBG_SEL                    0x001A
    #define   LSb32Gbl_chipCntl_CLK_DBG_SEL                       21
    #define   LSb16Gbl_chipCntl_CLK_DBG_SEL                       5
    #define       bGbl_chipCntl_CLK_DBG_SEL                    1
    #define   MSK32Gbl_chipCntl_CLK_DBG_SEL                       0x00200000

    #define     BA_Gbl_chipCntl_SD0_CDn_SEL                    0x001A
    #define     B16Gbl_chipCntl_SD0_CDn_SEL                    0x001A
    #define   LSb32Gbl_chipCntl_SD0_CDn_SEL                       22
    #define   LSb16Gbl_chipCntl_SD0_CDn_SEL                       6
    #define       bGbl_chipCntl_SD0_CDn_SEL                    1
    #define   MSK32Gbl_chipCntl_SD0_CDn_SEL                       0x00400000

    #define     BA_Gbl_chipCntl_SD0_WP_SEL                     0x001A
    #define     B16Gbl_chipCntl_SD0_WP_SEL                     0x001A
    #define   LSb32Gbl_chipCntl_SD0_WP_SEL                        23
    #define   LSb16Gbl_chipCntl_SD0_WP_SEL                        7
    #define       bGbl_chipCntl_SD0_WP_SEL                     1
    #define   MSK32Gbl_chipCntl_SD0_WP_SEL                        0x00800000
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_sw_generic0                             0x0020

    #define     BA_Gbl_sw_generic0_swReg0                      0x0020
    #define     B16Gbl_sw_generic0_swReg0                      0x0020
    #define   LSb32Gbl_sw_generic0_swReg0                         0
    #define   LSb16Gbl_sw_generic0_swReg0                         0
    #define       bGbl_sw_generic0_swReg0                      32
    #define   MSK32Gbl_sw_generic0_swReg0                         0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_sw_generic1                             0x0024

    #define     BA_Gbl_sw_generic1_swReg1                      0x0024
    #define     B16Gbl_sw_generic1_swReg1                      0x0024
    #define   LSb32Gbl_sw_generic1_swReg1                         0
    #define   LSb16Gbl_sw_generic1_swReg1                         0
    #define       bGbl_sw_generic1_swReg1                      32
    #define   MSK32Gbl_sw_generic1_swReg1                         0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_sw_generic2                             0x0028

    #define     BA_Gbl_sw_generic2_swReg2                      0x0028
    #define     B16Gbl_sw_generic2_swReg2                      0x0028
    #define   LSb32Gbl_sw_generic2_swReg2                         0
    #define   LSb16Gbl_sw_generic2_swReg2                         0
    #define       bGbl_sw_generic2_swReg2                      32
    #define   MSK32Gbl_sw_generic2_swReg2                         0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_sw_generic3                             0x002C

    #define     BA_Gbl_sw_generic3_swReg3                      0x002C
    #define     B16Gbl_sw_generic3_swReg3                      0x002C
    #define   LSb32Gbl_sw_generic3_swReg3                         0
    #define   LSb16Gbl_sw_generic3_swReg3                         0
    #define       bGbl_sw_generic3_swReg3                      32
    #define   MSK32Gbl_sw_generic3_swReg3                         0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_RWTC_top31to0                           0x0030

    #define     BA_Gbl_RWTC_top31to0_value                     0x0030
    #define     B16Gbl_RWTC_top31to0_value                     0x0030
    #define   LSb32Gbl_RWTC_top31to0_value                        0
    #define   LSb16Gbl_RWTC_top31to0_value                        0
    #define       bGbl_RWTC_top31to0_value                     32
    #define   MSK32Gbl_RWTC_top31to0_value                        0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_RWTC_top63to32                          0x0034

    #define     BA_Gbl_RWTC_top63to32_value                    0x0034
    #define     B16Gbl_RWTC_top63to32_value                    0x0034
    #define   LSb32Gbl_RWTC_top63to32_value                       0
    #define   LSb16Gbl_RWTC_top63to32_value                       0
    #define       bGbl_RWTC_top63to32_value                    32
    #define   MSK32Gbl_RWTC_top63to32_value                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_RWTC_top67to64                          0x0038

    #define     BA_Gbl_RWTC_top67to64_value                    0x0038
    #define     B16Gbl_RWTC_top67to64_value                    0x0038
    #define   LSb32Gbl_RWTC_top67to64_value                       0
    #define   LSb16Gbl_RWTC_top67to64_value                       0
    #define       bGbl_RWTC_top67to64_value                    4
    #define   MSK32Gbl_RWTC_top67to64_value                       0x0000000F
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_USB2                      0x004C

    #define     BA_Gbl_SRAM_PWR_CTRL_USB2_value                0x004C
    #define     B16Gbl_SRAM_PWR_CTRL_USB2_value                0x004C
    #define   LSb32Gbl_SRAM_PWR_CTRL_USB2_value                   0
    #define   LSb16Gbl_SRAM_PWR_CTRL_USB2_value                   0
    #define       bGbl_SRAM_PWR_CTRL_USB2_value                2
    #define   MSK32Gbl_SRAM_PWR_CTRL_USB2_value                   0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_PCIE0                     0x0050

    #define     BA_Gbl_SRAM_PWR_CTRL_PCIE0_value               0x0050
    #define     B16Gbl_SRAM_PWR_CTRL_PCIE0_value               0x0050
    #define   LSb32Gbl_SRAM_PWR_CTRL_PCIE0_value                  0
    #define   LSb16Gbl_SRAM_PWR_CTRL_PCIE0_value                  0
    #define       bGbl_SRAM_PWR_CTRL_PCIE0_value               2
    #define   MSK32Gbl_SRAM_PWR_CTRL_PCIE0_value                  0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_PCIE1                     0x0054

    #define     BA_Gbl_SRAM_PWR_CTRL_PCIE1_value               0x0054
    #define     B16Gbl_SRAM_PWR_CTRL_PCIE1_value               0x0054
    #define   LSb32Gbl_SRAM_PWR_CTRL_PCIE1_value                  0
    #define   LSb16Gbl_SRAM_PWR_CTRL_PCIE1_value                  0
    #define       bGbl_SRAM_PWR_CTRL_PCIE1_value               2
    #define   MSK32Gbl_SRAM_PWR_CTRL_PCIE1_value                  0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_SISS                      0x005C

    #define     BA_Gbl_SRAM_PWR_CTRL_SISS_value                0x005C
    #define     B16Gbl_SRAM_PWR_CTRL_SISS_value                0x005C
    #define   LSb32Gbl_SRAM_PWR_CTRL_SISS_value                   0
    #define   LSb16Gbl_SRAM_PWR_CTRL_SISS_value                   0
    #define       bGbl_SRAM_PWR_CTRL_SISS_value                3
    #define   MSK32Gbl_SRAM_PWR_CTRL_SISS_value                   0x00000007
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_NNA                       0x006C

    #define     BA_Gbl_SRAM_PWR_CTRL_NNA_value                 0x006C
    #define     B16Gbl_SRAM_PWR_CTRL_NNA_value                 0x006C
    #define   LSb32Gbl_SRAM_PWR_CTRL_NNA_value                    0
    #define   LSb16Gbl_SRAM_PWR_CTRL_NNA_value                    0
    #define       bGbl_SRAM_PWR_CTRL_NNA_value                 2
    #define   MSK32Gbl_SRAM_PWR_CTRL_NNA_value                    0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_AIO                       0x0070

    #define     BA_Gbl_SRAM_PWR_CTRL_AIO_value                 0x0070
    #define     B16Gbl_SRAM_PWR_CTRL_AIO_value                 0x0070
    #define   LSb32Gbl_SRAM_PWR_CTRL_AIO_value                    0
    #define   LSb16Gbl_SRAM_PWR_CTRL_AIO_value                    0
    #define       bGbl_SRAM_PWR_CTRL_AIO_value                 2
    #define   MSK32Gbl_SRAM_PWR_CTRL_AIO_value                    0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_CA53                      0x0074

    #define     BA_Gbl_SRAM_PWR_CTRL_CA53_value                0x0074
    #define     B16Gbl_SRAM_PWR_CTRL_CA53_value                0x0074
    #define   LSb32Gbl_SRAM_PWR_CTRL_CA53_value                   0
    #define   LSb16Gbl_SRAM_PWR_CTRL_CA53_value                   0
    #define       bGbl_SRAM_PWR_CTRL_CA53_value                2
    #define   MSK32Gbl_SRAM_PWR_CTRL_CA53_value                   0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SRAM_PWR_CTRL_SCRATCH                   0x0078

    #define     BA_Gbl_SRAM_PWR_CTRL_SCRATCH_value             0x0078
    #define     B16Gbl_SRAM_PWR_CTRL_SCRATCH_value             0x0078
    #define   LSb32Gbl_SRAM_PWR_CTRL_SCRATCH_value                0
    #define   LSb16Gbl_SRAM_PWR_CTRL_SCRATCH_value                0
    #define       bGbl_SRAM_PWR_CTRL_SCRATCH_value             2
    #define   MSK32Gbl_SRAM_PWR_CTRL_SCRATCH_value                0x00000003
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_FPGAR                                   0x0080

    #define     BA_Gbl_FPGAR_FPGAR                             0x0080
    #define     B16Gbl_FPGAR_FPGAR                             0x0080
    #define   LSb32Gbl_FPGAR_FPGAR                                0
    #define   LSb16Gbl_FPGAR_FPGAR                                0
    #define       bGbl_FPGAR_FPGAR                             32
    #define   MSK32Gbl_FPGAR_FPGAR                                0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_FPGARW                                  0x0084

    #define     BA_Gbl_FPGARW_FPGARW                           0x0084
    #define     B16Gbl_FPGARW_FPGARW                           0x0084
    #define   LSb32Gbl_FPGARW_FPGARW                              0
    #define   LSb16Gbl_FPGARW_FPGARW                              0
    #define       bGbl_FPGARW_FPGARW                           32
    #define   MSK32Gbl_FPGARW_FPGARW                              0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_sysPll                                  0x0088
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_ResetTrigger                            0x0478

    #define     BA_Gbl_ResetTrigger_chipReset                  0x0478
    #define     B16Gbl_ResetTrigger_chipReset                  0x0478
    #define   LSb32Gbl_ResetTrigger_chipReset                     0
    #define   LSb16Gbl_ResetTrigger_chipReset                     0
    #define       bGbl_ResetTrigger_chipReset                  1
    #define   MSK32Gbl_ResetTrigger_chipReset                     0x00000001
    #define        Gbl_ResetTrigger_chipReset_assert                        0x1
    #define        Gbl_ResetTrigger_chipReset_deassert                      0x0

    #define     BA_Gbl_ResetTrigger_socDdrSyncReset            0x0478
    #define     B16Gbl_ResetTrigger_socDdrSyncReset            0x0478
    #define   LSb32Gbl_ResetTrigger_socDdrSyncReset               1
    #define   LSb16Gbl_ResetTrigger_socDdrSyncReset               1
    #define       bGbl_ResetTrigger_socDdrSyncReset            1
    #define   MSK32Gbl_ResetTrigger_socDdrSyncReset               0x00000002
    #define        Gbl_ResetTrigger_socDdrSyncReset_assert                  0x1
    #define        Gbl_ResetTrigger_socDdrSyncReset_deassert                0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_ResetStatus                             0x047C

    #define     BA_Gbl_ResetStatus_ChipResetStatus             0x047C
    #define     B16Gbl_ResetStatus_ChipResetStatus             0x047C
    #define   LSb32Gbl_ResetStatus_ChipResetStatus                0
    #define   LSb16Gbl_ResetStatus_ChipResetStatus                0
    #define       bGbl_ResetStatus_ChipResetStatus             1
    #define   MSK32Gbl_ResetStatus_ChipResetStatus                0x00000001
    #define        Gbl_ResetStatus_ChipResetStatus_asserted                 0x1
    #define        Gbl_ResetStatus_ChipResetStatus_deasserted               0x0

    #define     BA_Gbl_ResetStatus_socDdrSyncResetStatus       0x047C
    #define     B16Gbl_ResetStatus_socDdrSyncResetStatus       0x047C
    #define   LSb32Gbl_ResetStatus_socDdrSyncResetStatus          1
    #define   LSb16Gbl_ResetStatus_socDdrSyncResetStatus          1
    #define       bGbl_ResetStatus_socDdrSyncResetStatus       1
    #define   MSK32Gbl_ResetStatus_socDdrSyncResetStatus          0x00000002
    #define        Gbl_ResetStatus_socDdrSyncResetStatus_asserted              0x1
    #define        Gbl_ResetStatus_socDdrSyncResetStatus_deasserted              0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_WDTResetStatus                          0x0480

    #define     BA_Gbl_WDTResetStatus_wd0Status                0x0480
    #define     B16Gbl_WDTResetStatus_wd0Status                0x0480
    #define   LSb32Gbl_WDTResetStatus_wd0Status                   0
    #define   LSb16Gbl_WDTResetStatus_wd0Status                   0
    #define       bGbl_WDTResetStatus_wd0Status                1
    #define   MSK32Gbl_WDTResetStatus_wd0Status                   0x00000001
    #define        Gbl_WDTResetStatus_wd0Status_asserted                    0x1
    #define        Gbl_WDTResetStatus_wd0Status_deasserted                  0x0

    #define     BA_Gbl_WDTResetStatus_wd1Status                0x0480
    #define     B16Gbl_WDTResetStatus_wd1Status                0x0480
    #define   LSb32Gbl_WDTResetStatus_wd1Status                   1
    #define   LSb16Gbl_WDTResetStatus_wd1Status                   1
    #define       bGbl_WDTResetStatus_wd1Status                1
    #define   MSK32Gbl_WDTResetStatus_wd1Status                   0x00000002
    #define        Gbl_WDTResetStatus_wd1Status_asserted                    0x1
    #define        Gbl_WDTResetStatus_wd1Status_deasserted                  0x0

    #define     BA_Gbl_WDTResetStatus_wd2Status                0x0480
    #define     B16Gbl_WDTResetStatus_wd2Status                0x0480
    #define   LSb32Gbl_WDTResetStatus_wd2Status                   2
    #define   LSb16Gbl_WDTResetStatus_wd2Status                   2
    #define       bGbl_WDTResetStatus_wd2Status                1
    #define   MSK32Gbl_WDTResetStatus_wd2Status                   0x00000004
    #define        Gbl_WDTResetStatus_wd2Status_asserted                    0x1
    #define        Gbl_WDTResetStatus_wd2Status_deasserted                  0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_WDTSysRstMask                           0x0484

    #define     BA_Gbl_WDTSysRstMask_wdt0Mask                  0x0484
    #define     B16Gbl_WDTSysRstMask_wdt0Mask                  0x0484
    #define   LSb32Gbl_WDTSysRstMask_wdt0Mask                     0
    #define   LSb16Gbl_WDTSysRstMask_wdt0Mask                     0
    #define       bGbl_WDTSysRstMask_wdt0Mask                  1
    #define   MSK32Gbl_WDTSysRstMask_wdt0Mask                     0x00000001

    #define     BA_Gbl_WDTSysRstMask_wdt1Mask                  0x0484
    #define     B16Gbl_WDTSysRstMask_wdt1Mask                  0x0484
    #define   LSb32Gbl_WDTSysRstMask_wdt1Mask                     1
    #define   LSb16Gbl_WDTSysRstMask_wdt1Mask                     1
    #define       bGbl_WDTSysRstMask_wdt1Mask                  1
    #define   MSK32Gbl_WDTSysRstMask_wdt1Mask                     0x00000002

    #define     BA_Gbl_WDTSysRstMask_wdt2Mask                  0x0484
    #define     B16Gbl_WDTSysRstMask_wdt2Mask                  0x0484
    #define   LSb32Gbl_WDTSysRstMask_wdt2Mask                     2
    #define   LSb16Gbl_WDTSysRstMask_wdt2Mask                     2
    #define       bGbl_WDTSysRstMask_wdt2Mask                  1
    #define   MSK32Gbl_WDTSysRstMask_wdt2Mask                     0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_CHIP_RESET_TRACKER                      0x0488

    #define     BA_Gbl_CHIP_RESET_TRACKER_VALUE                0x0488
    #define     B16Gbl_CHIP_RESET_TRACKER_VALUE                0x0488
    #define   LSb32Gbl_CHIP_RESET_TRACKER_VALUE                   0
    #define   LSb16Gbl_CHIP_RESET_TRACKER_VALUE                   0
    #define       bGbl_CHIP_RESET_TRACKER_VALUE                32
    #define   MSK32Gbl_CHIP_RESET_TRACKER_VALUE                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_avioReset                               0x0494

    #define     BA_Gbl_avioReset_SyncReset                     0x0494
    #define     B16Gbl_avioReset_SyncReset                     0x0494
    #define   LSb32Gbl_avioReset_SyncReset                        0
    #define   LSb16Gbl_avioReset_SyncReset                        0
    #define       bGbl_avioReset_SyncReset                     1
    #define   MSK32Gbl_avioReset_SyncReset                        0x00000001
    #define        Gbl_avioReset_SyncReset_assert                           0x1
    #define        Gbl_avioReset_SyncReset_deassert                         0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_avioResetStatus                         0x0498

    #define     BA_Gbl_avioResetStatus_SyncReset               0x0498
    #define     B16Gbl_avioResetStatus_SyncReset               0x0498
    #define   LSb32Gbl_avioResetStatus_SyncReset                  0
    #define   LSb16Gbl_avioResetStatus_SyncReset                  0
    #define       bGbl_avioResetStatus_SyncReset               1
    #define   MSK32Gbl_avioResetStatus_SyncReset                  0x00000001
    #define        Gbl_avioResetStatus_SyncReset_assert                     0x1
    #define        Gbl_avioResetStatus_SyncReset_deassert                   0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_perifReset                              0x049C

    #define     BA_Gbl_perifReset_SyncReset                    0x049C
    #define     B16Gbl_perifReset_SyncReset                    0x049C
    #define   LSb32Gbl_perifReset_SyncReset                       0
    #define   LSb16Gbl_perifReset_SyncReset                       0
    #define       bGbl_perifReset_SyncReset                    1
    #define   MSK32Gbl_perifReset_SyncReset                       0x00000001
    #define        Gbl_perifReset_SyncReset_assert                          0x1
    #define        Gbl_perifReset_SyncReset_deassert                        0x0

    #define     BA_Gbl_perifReset_ahbApbSyncReset              0x049C
    #define     B16Gbl_perifReset_ahbApbSyncReset              0x049C
    #define   LSb32Gbl_perifReset_ahbApbSyncReset                 1
    #define   LSb16Gbl_perifReset_ahbApbSyncReset                 1
    #define       bGbl_perifReset_ahbApbSyncReset              1
    #define   MSK32Gbl_perifReset_ahbApbSyncReset                 0x00000002
    #define        Gbl_perifReset_ahbApbSyncReset_assert                    0x1
    #define        Gbl_perifReset_ahbApbSyncReset_deassert                  0x0

    #define     BA_Gbl_perifReset_nfcSysSyncReset              0x049C
    #define     B16Gbl_perifReset_nfcSysSyncReset              0x049C
    #define   LSb32Gbl_perifReset_nfcSysSyncReset                 2
    #define   LSb16Gbl_perifReset_nfcSysSyncReset                 2
    #define       bGbl_perifReset_nfcSysSyncReset              1
    #define   MSK32Gbl_perifReset_nfcSysSyncReset                 0x00000004
    #define        Gbl_perifReset_nfcSysSyncReset_assert                    0x1
    #define        Gbl_perifReset_nfcSysSyncReset_deassert                  0x0

    #define     BA_Gbl_perifReset_nfcRegSyncReset              0x049C
    #define     B16Gbl_perifReset_nfcRegSyncReset              0x049C
    #define   LSb32Gbl_perifReset_nfcRegSyncReset                 3
    #define   LSb16Gbl_perifReset_nfcRegSyncReset                 3
    #define       bGbl_perifReset_nfcRegSyncReset              1
    #define   MSK32Gbl_perifReset_nfcRegSyncReset                 0x00000008
    #define        Gbl_perifReset_nfcRegSyncReset_assert                    0x1
    #define        Gbl_perifReset_nfcRegSyncReset_deassert                  0x0

    #define     BA_Gbl_perifReset_sdioSyncReset                0x049C
    #define     B16Gbl_perifReset_sdioSyncReset                0x049C
    #define   LSb32Gbl_perifReset_sdioSyncReset                   4
    #define   LSb16Gbl_perifReset_sdioSyncReset                   4
    #define       bGbl_perifReset_sdioSyncReset                1
    #define   MSK32Gbl_perifReset_sdioSyncReset                   0x00000010
    #define        Gbl_perifReset_sdioSyncReset_assert                      0x1
    #define        Gbl_perifReset_sdioSyncReset_deassert                    0x0

    #define     BA_Gbl_perifReset_tspSyncReset                 0x049C
    #define     B16Gbl_perifReset_tspSyncReset                 0x049C
    #define   LSb32Gbl_perifReset_tspSyncReset                    5
    #define   LSb16Gbl_perifReset_tspSyncReset                    5
    #define       bGbl_perifReset_tspSyncReset                 1
    #define   MSK32Gbl_perifReset_tspSyncReset                    0x00000020
    #define        Gbl_perifReset_tspSyncReset_assert                       0x1
    #define        Gbl_perifReset_tspSyncReset_deassert                     0x0

    #define     BA_Gbl_perifReset_tsSSSyncReset                0x049C
    #define     B16Gbl_perifReset_tsSSSyncReset                0x049C
    #define   LSb32Gbl_perifReset_tsSSSyncReset                   6
    #define   LSb16Gbl_perifReset_tsSSSyncReset                   6
    #define       bGbl_perifReset_tsSSSyncReset                1
    #define   MSK32Gbl_perifReset_tsSSSyncReset                   0x00000040
    #define        Gbl_perifReset_tsSSSyncReset_assert                      0x1
    #define        Gbl_perifReset_tsSSSyncReset_deassert                    0x0

    #define     BA_Gbl_perifReset_nskSyncReset                 0x049C
    #define     B16Gbl_perifReset_nskSyncReset                 0x049C
    #define   LSb32Gbl_perifReset_nskSyncReset                    7
    #define   LSb16Gbl_perifReset_nskSyncReset                    7
    #define       bGbl_perifReset_nskSyncReset                 1
    #define   MSK32Gbl_perifReset_nskSyncReset                    0x00000080
    #define        Gbl_perifReset_nskSyncReset_assert                       0x1
    #define        Gbl_perifReset_nskSyncReset_deassert                     0x0

    #define     BA_Gbl_perifReset_nocsSyncReset                0x049D
    #define     B16Gbl_perifReset_nocsSyncReset                0x049C
    #define   LSb32Gbl_perifReset_nocsSyncReset                   8
    #define   LSb16Gbl_perifReset_nocsSyncReset                   8
    #define       bGbl_perifReset_nocsSyncReset                1
    #define   MSK32Gbl_perifReset_nocsSyncReset                   0x00000100
    #define        Gbl_perifReset_nocsSyncReset_assert                      0x1
    #define        Gbl_perifReset_nocsSyncReset_deassert                    0x0

    #define     BA_Gbl_perifReset_bcmSyncReset                 0x049D
    #define     B16Gbl_perifReset_bcmSyncReset                 0x049C
    #define   LSb32Gbl_perifReset_bcmSyncReset                    9
    #define   LSb16Gbl_perifReset_bcmSyncReset                    9
    #define       bGbl_perifReset_bcmSyncReset                 1
    #define   MSK32Gbl_perifReset_bcmSyncReset                    0x00000200
    #define        Gbl_perifReset_bcmSyncReset_assert                       0x1
    #define        Gbl_perifReset_bcmSyncReset_deassert                     0x0

    #define     BA_Gbl_perifReset_usb0SyncReset                0x049D
    #define     B16Gbl_perifReset_usb0SyncReset                0x049C
    #define   LSb32Gbl_perifReset_usb0SyncReset                   10
    #define   LSb16Gbl_perifReset_usb0SyncReset                   10
    #define       bGbl_perifReset_usb0SyncReset                1
    #define   MSK32Gbl_perifReset_usb0SyncReset                   0x00000400
    #define        Gbl_perifReset_usb0SyncReset_assert                      0x1
    #define        Gbl_perifReset_usb0SyncReset_deassert                    0x0

    #define     BA_Gbl_perifReset_emmcSyncReset                0x049D
    #define     B16Gbl_perifReset_emmcSyncReset                0x049C
    #define   LSb32Gbl_perifReset_emmcSyncReset                   11
    #define   LSb16Gbl_perifReset_emmcSyncReset                   11
    #define       bGbl_perifReset_emmcSyncReset                1
    #define   MSK32Gbl_perifReset_emmcSyncReset                   0x00000800
    #define        Gbl_perifReset_emmcSyncReset_assert                      0x1
    #define        Gbl_perifReset_emmcSyncReset_deassert                    0x0

    #define     BA_Gbl_perifReset_pBridgeSyncReset             0x049D
    #define     B16Gbl_perifReset_pBridgeSyncReset             0x049C
    #define   LSb32Gbl_perifReset_pBridgeSyncReset                12
    #define   LSb16Gbl_perifReset_pBridgeSyncReset                12
    #define       bGbl_perifReset_pBridgeSyncReset             1
    #define   MSK32Gbl_perifReset_pBridgeSyncReset                0x00001000
    #define        Gbl_perifReset_pBridgeSyncReset_assert                   0x1
    #define        Gbl_perifReset_pBridgeSyncReset_deassert                 0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_perifResetStatus                        0x0500

    #define     BA_Gbl_perifResetStatus_SyncReset              0x0500
    #define     B16Gbl_perifResetStatus_SyncReset              0x0500
    #define   LSb32Gbl_perifResetStatus_SyncReset                 0
    #define   LSb16Gbl_perifResetStatus_SyncReset                 0
    #define       bGbl_perifResetStatus_SyncReset              1
    #define   MSK32Gbl_perifResetStatus_SyncReset                 0x00000001
    #define        Gbl_perifResetStatus_SyncReset_assert                    0x1
    #define        Gbl_perifResetStatus_SyncReset_deassert                  0x0

    #define     BA_Gbl_perifResetStatus_ahbApbSyncReset        0x0500
    #define     B16Gbl_perifResetStatus_ahbApbSyncReset        0x0500
    #define   LSb32Gbl_perifResetStatus_ahbApbSyncReset           1
    #define   LSb16Gbl_perifResetStatus_ahbApbSyncReset           1
    #define       bGbl_perifResetStatus_ahbApbSyncReset        1
    #define   MSK32Gbl_perifResetStatus_ahbApbSyncReset           0x00000002
    #define        Gbl_perifResetStatus_ahbApbSyncReset_assert              0x1
    #define        Gbl_perifResetStatus_ahbApbSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_nfcSysSyncReset        0x0500
    #define     B16Gbl_perifResetStatus_nfcSysSyncReset        0x0500
    #define   LSb32Gbl_perifResetStatus_nfcSysSyncReset           2
    #define   LSb16Gbl_perifResetStatus_nfcSysSyncReset           2
    #define       bGbl_perifResetStatus_nfcSysSyncReset        1
    #define   MSK32Gbl_perifResetStatus_nfcSysSyncReset           0x00000004
    #define        Gbl_perifResetStatus_nfcSysSyncReset_assert              0x1
    #define        Gbl_perifResetStatus_nfcSysSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_nfcRegSyncReset        0x0500
    #define     B16Gbl_perifResetStatus_nfcRegSyncReset        0x0500
    #define   LSb32Gbl_perifResetStatus_nfcRegSyncReset           3
    #define   LSb16Gbl_perifResetStatus_nfcRegSyncReset           3
    #define       bGbl_perifResetStatus_nfcRegSyncReset        1
    #define   MSK32Gbl_perifResetStatus_nfcRegSyncReset           0x00000008
    #define        Gbl_perifResetStatus_nfcRegSyncReset_assert              0x1
    #define        Gbl_perifResetStatus_nfcRegSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_sdioSyncReset          0x0500
    #define     B16Gbl_perifResetStatus_sdioSyncReset          0x0500
    #define   LSb32Gbl_perifResetStatus_sdioSyncReset             4
    #define   LSb16Gbl_perifResetStatus_sdioSyncReset             4
    #define       bGbl_perifResetStatus_sdioSyncReset          1
    #define   MSK32Gbl_perifResetStatus_sdioSyncReset             0x00000010
    #define        Gbl_perifResetStatus_sdioSyncReset_assert                0x1
    #define        Gbl_perifResetStatus_sdioSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_tspSyncReset           0x0500
    #define     B16Gbl_perifResetStatus_tspSyncReset           0x0500
    #define   LSb32Gbl_perifResetStatus_tspSyncReset              5
    #define   LSb16Gbl_perifResetStatus_tspSyncReset              5
    #define       bGbl_perifResetStatus_tspSyncReset           1
    #define   MSK32Gbl_perifResetStatus_tspSyncReset              0x00000020
    #define        Gbl_perifResetStatus_tspSyncReset_assert                 0x1
    #define        Gbl_perifResetStatus_tspSyncReset_deassert               0x0

    #define     BA_Gbl_perifResetStatus_tsSSSyncReset          0x0500
    #define     B16Gbl_perifResetStatus_tsSSSyncReset          0x0500
    #define   LSb32Gbl_perifResetStatus_tsSSSyncReset             6
    #define   LSb16Gbl_perifResetStatus_tsSSSyncReset             6
    #define       bGbl_perifResetStatus_tsSSSyncReset          1
    #define   MSK32Gbl_perifResetStatus_tsSSSyncReset             0x00000040
    #define        Gbl_perifResetStatus_tsSSSyncReset_assert                0x1
    #define        Gbl_perifResetStatus_tsSSSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_nskSyncReset           0x0500
    #define     B16Gbl_perifResetStatus_nskSyncReset           0x0500
    #define   LSb32Gbl_perifResetStatus_nskSyncReset              7
    #define   LSb16Gbl_perifResetStatus_nskSyncReset              7
    #define       bGbl_perifResetStatus_nskSyncReset           1
    #define   MSK32Gbl_perifResetStatus_nskSyncReset              0x00000080
    #define        Gbl_perifResetStatus_nskSyncReset_assert                 0x1
    #define        Gbl_perifResetStatus_nskSyncReset_deassert               0x0

    #define     BA_Gbl_perifResetStatus_nocsSyncReset          0x0501
    #define     B16Gbl_perifResetStatus_nocsSyncReset          0x0500
    #define   LSb32Gbl_perifResetStatus_nocsSyncReset             8
    #define   LSb16Gbl_perifResetStatus_nocsSyncReset             8
    #define       bGbl_perifResetStatus_nocsSyncReset          1
    #define   MSK32Gbl_perifResetStatus_nocsSyncReset             0x00000100
    #define        Gbl_perifResetStatus_nocsSyncReset_assert                0x1
    #define        Gbl_perifResetStatus_nocsSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_bcmSyncReset           0x0501
    #define     B16Gbl_perifResetStatus_bcmSyncReset           0x0500
    #define   LSb32Gbl_perifResetStatus_bcmSyncReset              9
    #define   LSb16Gbl_perifResetStatus_bcmSyncReset              9
    #define       bGbl_perifResetStatus_bcmSyncReset           1
    #define   MSK32Gbl_perifResetStatus_bcmSyncReset              0x00000200
    #define        Gbl_perifResetStatus_bcmSyncReset_assert                 0x1
    #define        Gbl_perifResetStatus_bcmSyncReset_deassert               0x0

    #define     BA_Gbl_perifResetStatus_usb0SyncReset          0x0501
    #define     B16Gbl_perifResetStatus_usb0SyncReset          0x0500
    #define   LSb32Gbl_perifResetStatus_usb0SyncReset             10
    #define   LSb16Gbl_perifResetStatus_usb0SyncReset             10
    #define       bGbl_perifResetStatus_usb0SyncReset          1
    #define   MSK32Gbl_perifResetStatus_usb0SyncReset             0x00000400
    #define        Gbl_perifResetStatus_usb0SyncReset_assert                0x1
    #define        Gbl_perifResetStatus_usb0SyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_emmcSyncReset          0x0501
    #define     B16Gbl_perifResetStatus_emmcSyncReset          0x0500
    #define   LSb32Gbl_perifResetStatus_emmcSyncReset             11
    #define   LSb16Gbl_perifResetStatus_emmcSyncReset             11
    #define       bGbl_perifResetStatus_emmcSyncReset          1
    #define   MSK32Gbl_perifResetStatus_emmcSyncReset             0x00000800
    #define        Gbl_perifResetStatus_emmcSyncReset_assert                0x1
    #define        Gbl_perifResetStatus_emmcSyncReset_deassert              0x0

    #define     BA_Gbl_perifResetStatus_pBridgeSyncReset       0x0501
    #define     B16Gbl_perifResetStatus_pBridgeSyncReset       0x0500
    #define   LSb32Gbl_perifResetStatus_pBridgeSyncReset          12
    #define   LSb16Gbl_perifResetStatus_pBridgeSyncReset          12
    #define       bGbl_perifResetStatus_pBridgeSyncReset       1
    #define   MSK32Gbl_perifResetStatus_pBridgeSyncReset          0x00001000
    #define        Gbl_perifResetStatus_pBridgeSyncReset_assert              0x1
    #define        Gbl_perifResetStatus_pBridgeSyncReset_deassert              0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_topStickyResetN                         0x0504

    #define     BA_Gbl_topStickyResetN_nnaStickyRstn           0x0504
    #define     B16Gbl_topStickyResetN_nnaStickyRstn           0x0504
    #define   LSb32Gbl_topStickyResetN_nnaStickyRstn              0
    #define   LSb16Gbl_topStickyResetN_nnaStickyRstn              0
    #define       bGbl_topStickyResetN_nnaStickyRstn           1
    #define   MSK32Gbl_topStickyResetN_nnaStickyRstn              0x00000001

    #define     BA_Gbl_topStickyResetN_ddrPHYStickyRstn        0x0504
    #define     B16Gbl_topStickyResetN_ddrPHYStickyRstn        0x0504
    #define   LSb32Gbl_topStickyResetN_ddrPHYStickyRstn           1
    #define   LSb16Gbl_topStickyResetN_ddrPHYStickyRstn           1
    #define       bGbl_topStickyResetN_ddrPHYStickyRstn        1
    #define   MSK32Gbl_topStickyResetN_ddrPHYStickyRstn           0x00000002

    #define     BA_Gbl_topStickyResetN_mcStickyRstn            0x0504
    #define     B16Gbl_topStickyResetN_mcStickyRstn            0x0504
    #define   LSb32Gbl_topStickyResetN_mcStickyRstn               2
    #define   LSb16Gbl_topStickyResetN_mcStickyRstn               2
    #define       bGbl_topStickyResetN_mcStickyRstn            1
    #define   MSK32Gbl_topStickyResetN_mcStickyRstn               0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_perifStickyResetN                       0x0508

    #define     BA_Gbl_perifStickyResetN_pcie0Rstn             0x0508
    #define     B16Gbl_perifStickyResetN_pcie0Rstn             0x0508
    #define   LSb32Gbl_perifStickyResetN_pcie0Rstn                0
    #define   LSb16Gbl_perifStickyResetN_pcie0Rstn                0
    #define       bGbl_perifStickyResetN_pcie0Rstn             1
    #define   MSK32Gbl_perifStickyResetN_pcie0Rstn                0x00000001
    #define        Gbl_perifStickyResetN_pcie0Rstn_asserted                 0x0
    #define        Gbl_perifStickyResetN_pcie0Rstn_deasserted               0x1

    #define     BA_Gbl_perifStickyResetN_pcie1Rstn             0x0508
    #define     B16Gbl_perifStickyResetN_pcie1Rstn             0x0508
    #define   LSb32Gbl_perifStickyResetN_pcie1Rstn                1
    #define   LSb16Gbl_perifStickyResetN_pcie1Rstn                1
    #define       bGbl_perifStickyResetN_pcie1Rstn             1
    #define   MSK32Gbl_perifStickyResetN_pcie1Rstn                0x00000002
    #define        Gbl_perifStickyResetN_pcie1Rstn_asserted                 0x0
    #define        Gbl_perifStickyResetN_pcie1Rstn_deasserted               0x1

    #define     BA_Gbl_perifStickyResetN_usbOtgPrstn           0x0508
    #define     B16Gbl_perifStickyResetN_usbOtgPrstn           0x0508
    #define   LSb32Gbl_perifStickyResetN_usbOtgPrstn              2
    #define   LSb16Gbl_perifStickyResetN_usbOtgPrstn              2
    #define       bGbl_perifStickyResetN_usbOtgPrstn           1
    #define   MSK32Gbl_perifStickyResetN_usbOtgPrstn              0x00000004
    #define        Gbl_perifStickyResetN_usbOtgPrstn_asserted               0x0
    #define        Gbl_perifStickyResetN_usbOtgPrstn_deasserted              0x1

    #define     BA_Gbl_perifStickyResetN_usbOtgHresetn         0x0508
    #define     B16Gbl_perifStickyResetN_usbOtgHresetn         0x0508
    #define   LSb32Gbl_perifStickyResetN_usbOtgHresetn            3
    #define   LSb16Gbl_perifStickyResetN_usbOtgHresetn            3
    #define       bGbl_perifStickyResetN_usbOtgHresetn         1
    #define   MSK32Gbl_perifStickyResetN_usbOtgHresetn            0x00000008
    #define        Gbl_perifStickyResetN_usbOtgHresetn_asserted              0x0
    #define        Gbl_perifStickyResetN_usbOtgHresetn_deasserted              0x1

    #define     BA_Gbl_perifStickyResetN_usbOtgPhyreset        0x0508
    #define     B16Gbl_perifStickyResetN_usbOtgPhyreset        0x0508
    #define   LSb32Gbl_perifStickyResetN_usbOtgPhyreset           4
    #define   LSb16Gbl_perifStickyResetN_usbOtgPhyreset           4
    #define       bGbl_perifStickyResetN_usbOtgPhyreset        1
    #define   MSK32Gbl_perifStickyResetN_usbOtgPhyreset           0x00000010
    #define        Gbl_perifStickyResetN_usbOtgPhyreset_asserted              0x1
    #define        Gbl_perifStickyResetN_usbOtgPhyreset_deasserted              0x0

    #define     BA_Gbl_perifStickyResetN_pcie0PhyRstn          0x0508
    #define     B16Gbl_perifStickyResetN_pcie0PhyRstn          0x0508
    #define   LSb32Gbl_perifStickyResetN_pcie0PhyRstn             5
    #define   LSb16Gbl_perifStickyResetN_pcie0PhyRstn             5
    #define       bGbl_perifStickyResetN_pcie0PhyRstn          1
    #define   MSK32Gbl_perifStickyResetN_pcie0PhyRstn             0x00000020
    #define        Gbl_perifStickyResetN_pcie0PhyRstn_asserted              0x0
    #define        Gbl_perifStickyResetN_pcie0PhyRstn_deasserted              0x1

    #define     BA_Gbl_perifStickyResetN_pcie1PhyRstn          0x0508
    #define     B16Gbl_perifStickyResetN_pcie1PhyRstn          0x0508
    #define   LSb32Gbl_perifStickyResetN_pcie1PhyRstn             6
    #define   LSb16Gbl_perifStickyResetN_pcie1PhyRstn             6
    #define       bGbl_perifStickyResetN_pcie1PhyRstn          1
    #define   MSK32Gbl_perifStickyResetN_pcie1PhyRstn             0x00000040
    #define        Gbl_perifStickyResetN_pcie1PhyRstn_asserted              0x0
    #define        Gbl_perifStickyResetN_pcie1PhyRstn_deasserted              0x1
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_apbPerifResetTrigger                    0x050C

    #define     BA_Gbl_apbPerifResetTrigger_uart0SyncReset     0x050C
    #define     B16Gbl_apbPerifResetTrigger_uart0SyncReset     0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_uart0SyncReset        0
    #define   LSb16Gbl_apbPerifResetTrigger_uart0SyncReset        0
    #define       bGbl_apbPerifResetTrigger_uart0SyncReset     1
    #define   MSK32Gbl_apbPerifResetTrigger_uart0SyncReset        0x00000001
    #define        Gbl_apbPerifResetTrigger_uart0SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_uart0SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_uart1SyncReset     0x050C
    #define     B16Gbl_apbPerifResetTrigger_uart1SyncReset     0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_uart1SyncReset        1
    #define   LSb16Gbl_apbPerifResetTrigger_uart1SyncReset        1
    #define       bGbl_apbPerifResetTrigger_uart1SyncReset     1
    #define   MSK32Gbl_apbPerifResetTrigger_uart1SyncReset        0x00000002
    #define        Gbl_apbPerifResetTrigger_uart1SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_uart1SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_i2c0SyncReset      0x050C
    #define     B16Gbl_apbPerifResetTrigger_i2c0SyncReset      0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_i2c0SyncReset         2
    #define   LSb16Gbl_apbPerifResetTrigger_i2c0SyncReset         2
    #define       bGbl_apbPerifResetTrigger_i2c0SyncReset      1
    #define   MSK32Gbl_apbPerifResetTrigger_i2c0SyncReset         0x00000004
    #define        Gbl_apbPerifResetTrigger_i2c0SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_i2c0SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_i2c1SyncReset      0x050C
    #define     B16Gbl_apbPerifResetTrigger_i2c1SyncReset      0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_i2c1SyncReset         3
    #define   LSb16Gbl_apbPerifResetTrigger_i2c1SyncReset         3
    #define       bGbl_apbPerifResetTrigger_i2c1SyncReset      1
    #define   MSK32Gbl_apbPerifResetTrigger_i2c1SyncReset         0x00000008
    #define        Gbl_apbPerifResetTrigger_i2c1SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_i2c1SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_spiSyncReset       0x050C
    #define     B16Gbl_apbPerifResetTrigger_spiSyncReset       0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_spiSyncReset          4
    #define   LSb16Gbl_apbPerifResetTrigger_spiSyncReset          4
    #define       bGbl_apbPerifResetTrigger_spiSyncReset       1
    #define   MSK32Gbl_apbPerifResetTrigger_spiSyncReset          0x00000010
    #define        Gbl_apbPerifResetTrigger_spiSyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_spiSyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_timer0SyncReset    0x050C
    #define     B16Gbl_apbPerifResetTrigger_timer0SyncReset    0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_timer0SyncReset       5
    #define   LSb16Gbl_apbPerifResetTrigger_timer0SyncReset       5
    #define       bGbl_apbPerifResetTrigger_timer0SyncReset    1
    #define   MSK32Gbl_apbPerifResetTrigger_timer0SyncReset       0x00000020
    #define        Gbl_apbPerifResetTrigger_timer0SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_timer0SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_timer1SyncReset    0x050C
    #define     B16Gbl_apbPerifResetTrigger_timer1SyncReset    0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_timer1SyncReset       6
    #define   LSb16Gbl_apbPerifResetTrigger_timer1SyncReset       6
    #define       bGbl_apbPerifResetTrigger_timer1SyncReset    1
    #define   MSK32Gbl_apbPerifResetTrigger_timer1SyncReset       0x00000040
    #define        Gbl_apbPerifResetTrigger_timer1SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_timer1SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_wdt0SyncReset      0x050C
    #define     B16Gbl_apbPerifResetTrigger_wdt0SyncReset      0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_wdt0SyncReset         7
    #define   LSb16Gbl_apbPerifResetTrigger_wdt0SyncReset         7
    #define       bGbl_apbPerifResetTrigger_wdt0SyncReset      1
    #define   MSK32Gbl_apbPerifResetTrigger_wdt0SyncReset         0x00000080
    #define        Gbl_apbPerifResetTrigger_wdt0SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_wdt0SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_wdt1SyncReset      0x050D
    #define     B16Gbl_apbPerifResetTrigger_wdt1SyncReset      0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_wdt1SyncReset         8
    #define   LSb16Gbl_apbPerifResetTrigger_wdt1SyncReset         8
    #define       bGbl_apbPerifResetTrigger_wdt1SyncReset      1
    #define   MSK32Gbl_apbPerifResetTrigger_wdt1SyncReset         0x00000100
    #define        Gbl_apbPerifResetTrigger_wdt1SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_wdt1SyncReset_deassert              0x0

    #define     BA_Gbl_apbPerifResetTrigger_wdt2SyncReset      0x050D
    #define     B16Gbl_apbPerifResetTrigger_wdt2SyncReset      0x050C
    #define   LSb32Gbl_apbPerifResetTrigger_wdt2SyncReset         9
    #define   LSb16Gbl_apbPerifResetTrigger_wdt2SyncReset         9
    #define       bGbl_apbPerifResetTrigger_wdt2SyncReset      1
    #define   MSK32Gbl_apbPerifResetTrigger_wdt2SyncReset         0x00000200
    #define        Gbl_apbPerifResetTrigger_wdt2SyncReset_assert              0x1
    #define        Gbl_apbPerifResetTrigger_wdt2SyncReset_deassert              0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_apbPerifResetStatus                     0x0510

    #define     BA_Gbl_apbPerifResetStatus_uart0SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_uart0SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_uart0SyncResetStatus    0
    #define   LSb16Gbl_apbPerifResetStatus_uart0SyncResetStatus    0
    #define       bGbl_apbPerifResetStatus_uart0SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_uart0SyncResetStatus    0x00000001
    #define        Gbl_apbPerifResetStatus_uart0SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_uart0SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_uart1SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_uart1SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_uart1SyncResetStatus    1
    #define   LSb16Gbl_apbPerifResetStatus_uart1SyncResetStatus    1
    #define       bGbl_apbPerifResetStatus_uart1SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_uart1SyncResetStatus    0x00000002
    #define        Gbl_apbPerifResetStatus_uart1SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_uart1SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_i2c0SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_i2c0SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_i2c0SyncResetStatus    2
    #define   LSb16Gbl_apbPerifResetStatus_i2c0SyncResetStatus    2
    #define       bGbl_apbPerifResetStatus_i2c0SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_i2c0SyncResetStatus    0x00000004
    #define        Gbl_apbPerifResetStatus_i2c0SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_i2c0SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_i2c1SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_i2c1SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_i2c1SyncResetStatus    3
    #define   LSb16Gbl_apbPerifResetStatus_i2c1SyncResetStatus    3
    #define       bGbl_apbPerifResetStatus_i2c1SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_i2c1SyncResetStatus    0x00000008
    #define        Gbl_apbPerifResetStatus_i2c1SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_i2c1SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_i2c2SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_i2c2SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_i2c2SyncResetStatus    4
    #define   LSb16Gbl_apbPerifResetStatus_i2c2SyncResetStatus    4
    #define       bGbl_apbPerifResetStatus_i2c2SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_i2c2SyncResetStatus    0x00000010
    #define        Gbl_apbPerifResetStatus_i2c2SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_i2c2SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_spiSyncResetStatus  0x0510
    #define     B16Gbl_apbPerifResetStatus_spiSyncResetStatus  0x0510
    #define   LSb32Gbl_apbPerifResetStatus_spiSyncResetStatus     5
    #define   LSb16Gbl_apbPerifResetStatus_spiSyncResetStatus     5
    #define       bGbl_apbPerifResetStatus_spiSyncResetStatus  1
    #define   MSK32Gbl_apbPerifResetStatus_spiSyncResetStatus     0x00000020
    #define        Gbl_apbPerifResetStatus_spiSyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_spiSyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_timer0SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_timer0SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_timer0SyncResetStatus    6
    #define   LSb16Gbl_apbPerifResetStatus_timer0SyncResetStatus    6
    #define       bGbl_apbPerifResetStatus_timer0SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_timer0SyncResetStatus    0x00000040
    #define        Gbl_apbPerifResetStatus_timer0SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_timer0SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_timer1SyncResetStatus 0x0510
    #define     B16Gbl_apbPerifResetStatus_timer1SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_timer1SyncResetStatus    7
    #define   LSb16Gbl_apbPerifResetStatus_timer1SyncResetStatus    7
    #define       bGbl_apbPerifResetStatus_timer1SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_timer1SyncResetStatus    0x00000080
    #define        Gbl_apbPerifResetStatus_timer1SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_timer1SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_wdt0SyncResetStatus 0x0511
    #define     B16Gbl_apbPerifResetStatus_wdt0SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_wdt0SyncResetStatus    8
    #define   LSb16Gbl_apbPerifResetStatus_wdt0SyncResetStatus    8
    #define       bGbl_apbPerifResetStatus_wdt0SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_wdt0SyncResetStatus    0x00000100
    #define        Gbl_apbPerifResetStatus_wdt0SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_wdt0SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_wdt1SyncResetStatus 0x0511
    #define     B16Gbl_apbPerifResetStatus_wdt1SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_wdt1SyncResetStatus    9
    #define   LSb16Gbl_apbPerifResetStatus_wdt1SyncResetStatus    9
    #define       bGbl_apbPerifResetStatus_wdt1SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_wdt1SyncResetStatus    0x00000200
    #define        Gbl_apbPerifResetStatus_wdt1SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_wdt1SyncResetStatus_deassert              0x0

    #define     BA_Gbl_apbPerifResetStatus_wdt2SyncResetStatus 0x0511
    #define     B16Gbl_apbPerifResetStatus_wdt2SyncResetStatus 0x0510
    #define   LSb32Gbl_apbPerifResetStatus_wdt2SyncResetStatus    10
    #define   LSb16Gbl_apbPerifResetStatus_wdt2SyncResetStatus    10
    #define       bGbl_apbPerifResetStatus_wdt2SyncResetStatus 1
    #define   MSK32Gbl_apbPerifResetStatus_wdt2SyncResetStatus    0x00000400
    #define        Gbl_apbPerifResetStatus_wdt2SyncResetStatus_assert              0x1
    #define        Gbl_apbPerifResetStatus_wdt2SyncResetStatus_deassert              0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_clkEnable                               0x0514

    #define     BA_Gbl_clkEnable_tspSysClkEn                   0x0514
    #define     B16Gbl_clkEnable_tspSysClkEn                   0x0514
    #define   LSb32Gbl_clkEnable_tspSysClkEn                      0
    #define   LSb16Gbl_clkEnable_tspSysClkEn                      0
    #define       bGbl_clkEnable_tspSysClkEn                   1
    #define   MSK32Gbl_clkEnable_tspSysClkEn                      0x00000001
    #define        Gbl_clkEnable_tspSysClkEn_enable                         0x1
    #define        Gbl_clkEnable_tspSysClkEn_disable                        0x0

    #define     BA_Gbl_clkEnable_usb0CoreClkEn                 0x0514
    #define     B16Gbl_clkEnable_usb0CoreClkEn                 0x0514
    #define   LSb32Gbl_clkEnable_usb0CoreClkEn                    1
    #define   LSb16Gbl_clkEnable_usb0CoreClkEn                    1
    #define       bGbl_clkEnable_usb0CoreClkEn                 1
    #define   MSK32Gbl_clkEnable_usb0CoreClkEn                    0x00000002
    #define        Gbl_clkEnable_usb0CoreClkEn_enable                       0x1
    #define        Gbl_clkEnable_usb0CoreClkEn_disable                      0x0

    #define     BA_Gbl_clkEnable_sdioSysClkEn                  0x0514
    #define     B16Gbl_clkEnable_sdioSysClkEn                  0x0514
    #define   LSb32Gbl_clkEnable_sdioSysClkEn                     2
    #define   LSb16Gbl_clkEnable_sdioSysClkEn                     2
    #define       bGbl_clkEnable_sdioSysClkEn                  1
    #define   MSK32Gbl_clkEnable_sdioSysClkEn                     0x00000004
    #define        Gbl_clkEnable_sdioSysClkEn_enable                        0x1
    #define        Gbl_clkEnable_sdioSysClkEn_disable                       0x0

    #define     BA_Gbl_clkEnable_pcie0SysClkEn                 0x0514
    #define     B16Gbl_clkEnable_pcie0SysClkEn                 0x0514
    #define   LSb32Gbl_clkEnable_pcie0SysClkEn                    3
    #define   LSb16Gbl_clkEnable_pcie0SysClkEn                    3
    #define       bGbl_clkEnable_pcie0SysClkEn                 1
    #define   MSK32Gbl_clkEnable_pcie0SysClkEn                    0x00000008
    #define        Gbl_clkEnable_pcie0SysClkEn_enable                       0x1
    #define        Gbl_clkEnable_pcie0SysClkEn_disable                      0x0

    #define     BA_Gbl_clkEnable_pcie1SysClkEn                 0x0514
    #define     B16Gbl_clkEnable_pcie1SysClkEn                 0x0514
    #define   LSb32Gbl_clkEnable_pcie1SysClkEn                    4
    #define   LSb16Gbl_clkEnable_pcie1SysClkEn                    4
    #define       bGbl_clkEnable_pcie1SysClkEn                 1
    #define   MSK32Gbl_clkEnable_pcie1SysClkEn                    0x00000010
    #define        Gbl_clkEnable_pcie1SysClkEn_enable                       0x1
    #define        Gbl_clkEnable_pcie1SysClkEn_disable                      0x0

    #define     BA_Gbl_clkEnable_nfcSysClkEn                   0x0514
    #define     B16Gbl_clkEnable_nfcSysClkEn                   0x0514
    #define   LSb32Gbl_clkEnable_nfcSysClkEn                      5
    #define   LSb16Gbl_clkEnable_nfcSysClkEn                      5
    #define       bGbl_clkEnable_nfcSysClkEn                   1
    #define   MSK32Gbl_clkEnable_nfcSysClkEn                      0x00000020
    #define        Gbl_clkEnable_nfcSysClkEn_enable                         0x1
    #define        Gbl_clkEnable_nfcSysClkEn_disable                        0x0

    #define     BA_Gbl_clkEnable_emmcSysClkEn                  0x0514
    #define     B16Gbl_clkEnable_emmcSysClkEn                  0x0514
    #define   LSb32Gbl_clkEnable_emmcSysClkEn                     6
    #define   LSb16Gbl_clkEnable_emmcSysClkEn                     6
    #define       bGbl_clkEnable_emmcSysClkEn                  1
    #define   MSK32Gbl_clkEnable_emmcSysClkEn                     0x00000040
    #define        Gbl_clkEnable_emmcSysClkEn_enable                        0x1
    #define        Gbl_clkEnable_emmcSysClkEn_disable                       0x0

    #define     BA_Gbl_clkEnable_pBridgeCoreClkEn              0x0514
    #define     B16Gbl_clkEnable_pBridgeCoreClkEn              0x0514
    #define   LSb32Gbl_clkEnable_pBridgeCoreClkEn                 7
    #define   LSb16Gbl_clkEnable_pBridgeCoreClkEn                 7
    #define       bGbl_clkEnable_pBridgeCoreClkEn              1
    #define   MSK32Gbl_clkEnable_pBridgeCoreClkEn                 0x00000080
    #define        Gbl_clkEnable_pBridgeCoreClkEn_enable                    0x1
    #define        Gbl_clkEnable_pBridgeCoreClkEn_disable                   0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_ClkSwitch                               0x0518

    #define     BA_Gbl_ClkSwitch_sysPLLSWBypass                0x0518
    #define     B16Gbl_ClkSwitch_sysPLLSWBypass                0x0518
    #define   LSb32Gbl_ClkSwitch_sysPLLSWBypass                   0
    #define   LSb16Gbl_ClkSwitch_sysPLLSWBypass                   0
    #define       bGbl_ClkSwitch_sysPLLSWBypass                1
    #define   MSK32Gbl_ClkSwitch_sysPLLSWBypass                   0x00000001
    #define        Gbl_ClkSwitch_sysPLLSWBypass_refClk                      0x1
    #define        Gbl_ClkSwitch_sysPLLSWBypass_pllClk                      0x0

    #define     BA_Gbl_ClkSwitch_memPLLSWBypass                0x0518
    #define     B16Gbl_ClkSwitch_memPLLSWBypass                0x0518
    #define   LSb32Gbl_ClkSwitch_memPLLSWBypass                   1
    #define   LSb16Gbl_ClkSwitch_memPLLSWBypass                   1
    #define       bGbl_ClkSwitch_memPLLSWBypass                1
    #define   MSK32Gbl_ClkSwitch_memPLLSWBypass                   0x00000002
    #define        Gbl_ClkSwitch_memPLLSWBypass_refClk                      0x1
    #define        Gbl_ClkSwitch_memPLLSWBypass_pllClk                      0x0

    #define     BA_Gbl_ClkSwitch_cpuPLLSWBypass                0x0518
    #define     B16Gbl_ClkSwitch_cpuPLLSWBypass                0x0518
    #define   LSb32Gbl_ClkSwitch_cpuPLLSWBypass                   2
    #define   LSb16Gbl_ClkSwitch_cpuPLLSWBypass                   2
    #define       bGbl_ClkSwitch_cpuPLLSWBypass                1
    #define   MSK32Gbl_ClkSwitch_cpuPLLSWBypass                   0x00000004
    #define        Gbl_ClkSwitch_cpuPLLSWBypass_refClk                      0x1
    #define        Gbl_ClkSwitch_cpuPLLSWBypass_pllClk                      0x0
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_cpufastRefClk                           0x051C
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_memfastRefClk                           0x0520
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_cfgClk                                  0x0524
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_perifSysClk                             0x0528
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_atbClk                                  0x052C
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_avioSysClk                              0x0530
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_apbCoreClk                              0x0534
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_nnaSysClk                               0x0538
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_nnaCoreClk                              0x053C
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_emmcClk                                 0x0540
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_sd0Clk                                  0x0544
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pcie_500M_TxTestClk                     0x0548
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pcie_250M_pipeTestClk1                  0x054C
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pcie_250M_pipeTestClk2                  0x0550
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pcie_500M_RxTestClk                     0x0554
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pcie_serdesTestClk                      0x0558
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_nfcEccClk                               0x055C
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_nfcCoreClk                              0x0560
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_usbOtg60MTestClk                        0x0564
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_usbOtg50MTestClk                        0x0568
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_usbOtg12MTestClk                        0x056C
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_usbOtg480MTestClk                       0x0570
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_bcmClk                                  0x0574
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NandCtrl                                0x0578

    #define     BA_Gbl_NandCtrl_NAND_WPn_Sel                   0x0578
    #define     B16Gbl_NandCtrl_NAND_WPn_Sel                   0x0578
    #define   LSb32Gbl_NandCtrl_NAND_WPn_Sel                      0
    #define   LSb16Gbl_NandCtrl_NAND_WPn_Sel                      0
    #define       bGbl_NandCtrl_NAND_WPn_Sel                   1
    #define   MSK32Gbl_NandCtrl_NAND_WPn_Sel                      0x00000001

    #define     BA_Gbl_NandCtrl_NAND_CLE_OE                    0x0578
    #define     B16Gbl_NandCtrl_NAND_CLE_OE                    0x0578
    #define   LSb32Gbl_NandCtrl_NAND_CLE_OE                       1
    #define   LSb16Gbl_NandCtrl_NAND_CLE_OE                       1
    #define       bGbl_NandCtrl_NAND_CLE_OE                    1
    #define   MSK32Gbl_NandCtrl_NAND_CLE_OE                       0x00000002

    #define     BA_Gbl_NandCtrl_NAND_ALE_OE                    0x0578
    #define     B16Gbl_NandCtrl_NAND_ALE_OE                    0x0578
    #define   LSb32Gbl_NandCtrl_NAND_ALE_OE                       2
    #define   LSb16Gbl_NandCtrl_NAND_ALE_OE                       2
    #define       bGbl_NandCtrl_NAND_ALE_OE                    1
    #define   MSK32Gbl_NandCtrl_NAND_ALE_OE                       0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_gic400_ctrl                             0x061C

    #define     BA_Gbl_gic400_ctrl_cgfsdisable                 0x061C
    #define     B16Gbl_gic400_ctrl_cgfsdisable                 0x061C
    #define   LSb32Gbl_gic400_ctrl_cgfsdisable                    0
    #define   LSb16Gbl_gic400_ctrl_cgfsdisable                    0
    #define       bGbl_gic400_ctrl_cgfsdisable                 1
    #define   MSK32Gbl_gic400_ctrl_cgfsdisable                    0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_POR_1p8_3p3                             0x0620

    #define     BA_Gbl_POR_1p8_3p3_por_io_1p8v_pd              0x0620
    #define     B16Gbl_POR_1p8_3p3_por_io_1p8v_pd              0x0620
    #define   LSb32Gbl_POR_1p8_3p3_por_io_1p8v_pd                 0
    #define   LSb16Gbl_POR_1p8_3p3_por_io_1p8v_pd                 0
    #define       bGbl_POR_1p8_3p3_por_io_1p8v_pd              1
    #define   MSK32Gbl_POR_1p8_3p3_por_io_1p8v_pd                 0x00000001

    #define     BA_Gbl_POR_1p8_3p3_por_io_3p3v_pd              0x0620
    #define     B16Gbl_POR_1p8_3p3_por_io_3p3v_pd              0x0620
    #define   LSb32Gbl_POR_1p8_3p3_por_io_3p3v_pd                 1
    #define   LSb16Gbl_POR_1p8_3p3_por_io_3p3v_pd                 1
    #define       bGbl_POR_1p8_3p3_por_io_3p3v_pd              1
    #define   MSK32Gbl_POR_1p8_3p3_por_io_3p3v_pd                 0x00000002

    #define     BA_Gbl_POR_1p8_3p3_por_io_1p8v_threshold       0x0620
    #define     B16Gbl_POR_1p8_3p3_por_io_1p8v_threshold       0x0620
    #define   LSb32Gbl_POR_1p8_3p3_por_io_1p8v_threshold          2
    #define   LSb16Gbl_POR_1p8_3p3_por_io_1p8v_threshold          2
    #define       bGbl_POR_1p8_3p3_por_io_1p8v_threshold       2
    #define   MSK32Gbl_POR_1p8_3p3_por_io_1p8v_threshold          0x0000000C

    #define     BA_Gbl_POR_1p8_3p3_por_io_3p3v_threshold       0x0620
    #define     B16Gbl_POR_1p8_3p3_por_io_3p3v_threshold       0x0620
    #define   LSb32Gbl_POR_1p8_3p3_por_io_3p3v_threshold          4
    #define   LSb16Gbl_POR_1p8_3p3_por_io_3p3v_threshold          4
    #define       bGbl_POR_1p8_3p3_por_io_3p3v_threshold       2
    #define   MSK32Gbl_POR_1p8_3p3_por_io_3p3v_threshold          0x00000030

    #define     BA_Gbl_POR_1p8_3p3_por_io_1p8v_bypass          0x0620
    #define     B16Gbl_POR_1p8_3p3_por_io_1p8v_bypass          0x0620
    #define   LSb32Gbl_POR_1p8_3p3_por_io_1p8v_bypass             6
    #define   LSb16Gbl_POR_1p8_3p3_por_io_1p8v_bypass             6
    #define       bGbl_POR_1p8_3p3_por_io_1p8v_bypass          1
    #define   MSK32Gbl_POR_1p8_3p3_por_io_1p8v_bypass             0x00000040

    #define     BA_Gbl_POR_1p8_3p3_por_io_3p3v_bypass          0x0620
    #define     B16Gbl_POR_1p8_3p3_por_io_3p3v_bypass          0x0620
    #define   LSb32Gbl_POR_1p8_3p3_por_io_3p3v_bypass             7
    #define   LSb16Gbl_POR_1p8_3p3_por_io_3p3v_bypass             7
    #define       bGbl_POR_1p8_3p3_por_io_3p3v_bypass          1
    #define   MSK32Gbl_POR_1p8_3p3_por_io_3p3v_bypass             0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PERIF                                   0x0660
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_ADC                                     0x0800
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PVT                                     0x0810
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_Global_PADRING                          0x081C

    #define     BA_Gbl_Global_PADRING_MODE_SEL                 0x081C
    #define     B16Gbl_Global_PADRING_MODE_SEL                 0x081C
    #define   LSb32Gbl_Global_PADRING_MODE_SEL                    0
    #define   LSb16Gbl_Global_PADRING_MODE_SEL                    0
    #define       bGbl_Global_PADRING_MODE_SEL                 1
    #define   MSK32Gbl_Global_PADRING_MODE_SEL                    0x00000001

    #define     BA_Gbl_Global_PADRING_MODE_18                  0x081C
    #define     B16Gbl_Global_PADRING_MODE_18                  0x081C
    #define   LSb32Gbl_Global_PADRING_MODE_18                     1
    #define   LSb16Gbl_Global_PADRING_MODE_18                     1
    #define       bGbl_Global_PADRING_MODE_18                  1
    #define   MSK32Gbl_Global_PADRING_MODE_18                     0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI_PADRING                             0x0820

    #define     BA_Gbl_SPI_PADRING_MODE_SEL                    0x0820
    #define     B16Gbl_SPI_PADRING_MODE_SEL                    0x0820
    #define   LSb32Gbl_SPI_PADRING_MODE_SEL                       0
    #define   LSb16Gbl_SPI_PADRING_MODE_SEL                       0
    #define       bGbl_SPI_PADRING_MODE_SEL                    1
    #define   MSK32Gbl_SPI_PADRING_MODE_SEL                       0x00000001

    #define     BA_Gbl_SPI_PADRING_MODE_18                     0x0820
    #define     B16Gbl_SPI_PADRING_MODE_18                     0x0820
    #define   LSb32Gbl_SPI_PADRING_MODE_18                        1
    #define   LSb16Gbl_SPI_PADRING_MODE_18                        1
    #define       bGbl_SPI_PADRING_MODE_18                     1
    #define   MSK32Gbl_SPI_PADRING_MODE_18                        0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_PADRING                            0x0824

    #define     BA_Gbl_NAND_PADRING_MODE_SEL                   0x0824
    #define     B16Gbl_NAND_PADRING_MODE_SEL                   0x0824
    #define   LSb32Gbl_NAND_PADRING_MODE_SEL                      0
    #define   LSb16Gbl_NAND_PADRING_MODE_SEL                      0
    #define       bGbl_NAND_PADRING_MODE_SEL                   1
    #define   MSK32Gbl_NAND_PADRING_MODE_SEL                      0x00000001

    #define     BA_Gbl_NAND_PADRING_MODE_18                    0x0824
    #define     B16Gbl_NAND_PADRING_MODE_18                    0x0824
    #define   LSb32Gbl_NAND_PADRING_MODE_18                       1
    #define   LSb16Gbl_NAND_PADRING_MODE_18                       1
    #define       bGbl_NAND_PADRING_MODE_18                    1
    #define   MSK32Gbl_NAND_PADRING_MODE_18                       0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_PADRING                             0x0828

    #define     BA_Gbl_SD0_PADRING_MODE_SEL                    0x0828
    #define     B16Gbl_SD0_PADRING_MODE_SEL                    0x0828
    #define   LSb32Gbl_SD0_PADRING_MODE_SEL                       0
    #define   LSb16Gbl_SD0_PADRING_MODE_SEL                       0
    #define       bGbl_SD0_PADRING_MODE_SEL                    1
    #define   MSK32Gbl_SD0_PADRING_MODE_SEL                       0x00000001

    #define     BA_Gbl_SD0_PADRING_MODE_18                     0x0828
    #define     B16Gbl_SD0_PADRING_MODE_18                     0x0828
    #define   LSb32Gbl_SD0_PADRING_MODE_18                        1
    #define   LSb16Gbl_SD0_PADRING_MODE_18                        1
    #define       bGbl_SD0_PADRING_MODE_18                     1
    #define   MSK32Gbl_SD0_PADRING_MODE_18                        0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S_PADRING                             0x082C

    #define     BA_Gbl_I2S_PADRING_MODE_SEL                    0x082C
    #define     B16Gbl_I2S_PADRING_MODE_SEL                    0x082C
    #define   LSb32Gbl_I2S_PADRING_MODE_SEL                       0
    #define   LSb16Gbl_I2S_PADRING_MODE_SEL                       0
    #define       bGbl_I2S_PADRING_MODE_SEL                    1
    #define   MSK32Gbl_I2S_PADRING_MODE_SEL                       0x00000001

    #define     BA_Gbl_I2S_PADRING_MODE_18                     0x082C
    #define     B16Gbl_I2S_PADRING_MODE_18                     0x082C
    #define   LSb32Gbl_I2S_PADRING_MODE_18                        1
    #define   LSb16Gbl_I2S_PADRING_MODE_18                        1
    #define       bGbl_I2S_PADRING_MODE_18                     1
    #define   MSK32Gbl_I2S_PADRING_MODE_18                        0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S3_PADRING                            0x0830

    #define     BA_Gbl_I2S3_PADRING_MODE_SEL                   0x0830
    #define     B16Gbl_I2S3_PADRING_MODE_SEL                   0x0830
    #define   LSb32Gbl_I2S3_PADRING_MODE_SEL                      0
    #define   LSb16Gbl_I2S3_PADRING_MODE_SEL                      0
    #define       bGbl_I2S3_PADRING_MODE_SEL                   1
    #define   MSK32Gbl_I2S3_PADRING_MODE_SEL                      0x00000001

    #define     BA_Gbl_I2S3_PADRING_MODE_18                    0x0830
    #define     B16Gbl_I2S3_PADRING_MODE_18                    0x0830
    #define   LSb32Gbl_I2S3_PADRING_MODE_18                       1
    #define   LSb16Gbl_I2S3_PADRING_MODE_18                       1
    #define       bGbl_I2S3_PADRING_MODE_18                    1
    #define   MSK32Gbl_I2S3_PADRING_MODE_18                       0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM_PADRING                             0x0834

    #define     BA_Gbl_PWM_PADRING_MODE_SEL                    0x0834
    #define     B16Gbl_PWM_PADRING_MODE_SEL                    0x0834
    #define   LSb32Gbl_PWM_PADRING_MODE_SEL                       0
    #define   LSb16Gbl_PWM_PADRING_MODE_SEL                       0
    #define       bGbl_PWM_PADRING_MODE_SEL                    1
    #define   MSK32Gbl_PWM_PADRING_MODE_SEL                       0x00000001

    #define     BA_Gbl_PWM_PADRING_MODE_18                     0x0834
    #define     B16Gbl_PWM_PADRING_MODE_18                     0x0834
    #define   LSb32Gbl_PWM_PADRING_MODE_18                        1
    #define   LSb16Gbl_PWM_PADRING_MODE_18                        1
    #define       bGbl_PWM_PADRING_MODE_18                     1
    #define   MSK32Gbl_PWM_PADRING_MODE_18                        0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_XTL_CTL                                 0x0838

    #define     BA_Gbl_XTL_CTL_XTL_GM_SEL                      0x0838
    #define     B16Gbl_XTL_CTL_XTL_GM_SEL                      0x0838
    #define   LSb32Gbl_XTL_CTL_XTL_GM_SEL                         0
    #define   LSb16Gbl_XTL_CTL_XTL_GM_SEL                         0
    #define       bGbl_XTL_CTL_XTL_GM_SEL                      4
    #define   MSK32Gbl_XTL_CTL_XTL_GM_SEL                         0x0000000F
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PADRING_MODE_OUT                        0x083C

    #define     BA_Gbl_PADRING_MODE_OUT_MODE_OUT               0x083C
    #define     B16Gbl_PADRING_MODE_OUT_MODE_OUT               0x083C
    #define   LSb32Gbl_PADRING_MODE_OUT_MODE_OUT                  0
    #define   LSb16Gbl_PADRING_MODE_OUT_MODE_OUT                  0
    #define       bGbl_PADRING_MODE_OUT_MODE_OUT               7
    #define   MSK32Gbl_PADRING_MODE_OUT_MODE_OUT                  0x0000007F
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_pinMuxCntlBus                           0x0840

    #define     BA_Gbl_pinMuxCntlBus_I2S1_BCLKIO               0x0840
    #define     B16Gbl_pinMuxCntlBus_I2S1_BCLKIO               0x0840
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_BCLKIO                  0
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_BCLKIO                  0
    #define       bGbl_pinMuxCntlBus_I2S1_BCLKIO               3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_BCLKIO                  0x00000007
    #define        Gbl_pinMuxCntlBus_I2S1_BCLKIO_MODE_0                     0x0
    #define        Gbl_pinMuxCntlBus_I2S1_BCLKIO_MODE_1                     0x1
    #define        Gbl_pinMuxCntlBus_I2S1_BCLKIO_MODE_5                     0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S1_LRCKIO               0x0840
    #define     B16Gbl_pinMuxCntlBus_I2S1_LRCKIO               0x0840
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_LRCKIO                  3
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_LRCKIO                  3
    #define       bGbl_pinMuxCntlBus_I2S1_LRCKIO               3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_LRCKIO                  0x00000038
    #define        Gbl_pinMuxCntlBus_I2S1_LRCKIO_MODE_0                     0x0
    #define        Gbl_pinMuxCntlBus_I2S1_LRCKIO_MODE_1                     0x1
    #define        Gbl_pinMuxCntlBus_I2S1_LRCKIO_MODE_5                     0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S1_DO0                  0x0840
    #define     B16Gbl_pinMuxCntlBus_I2S1_DO0                  0x0840
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_DO0                     6
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_DO0                     6
    #define       bGbl_pinMuxCntlBus_I2S1_DO0                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_DO0                     0x000001C0
    #define        Gbl_pinMuxCntlBus_I2S1_DO0_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S1_DO0_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S1_DO0_MODE_3                        0x3
    #define        Gbl_pinMuxCntlBus_I2S1_DO0_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S1_DO1                  0x0841
    #define     B16Gbl_pinMuxCntlBus_I2S1_DO1                  0x0840
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_DO1                     9
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_DO1                     9
    #define       bGbl_pinMuxCntlBus_I2S1_DO1                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_DO1                     0x00000E00
    #define        Gbl_pinMuxCntlBus_I2S1_DO1_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S1_DO1_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S1_DO1_MODE_3                        0x3
    #define        Gbl_pinMuxCntlBus_I2S1_DO1_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S1_DO2                  0x0841
    #define     B16Gbl_pinMuxCntlBus_I2S1_DO2                  0x0840
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_DO2                     12
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_DO2                     12
    #define       bGbl_pinMuxCntlBus_I2S1_DO2                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_DO2                     0x00007000
    #define        Gbl_pinMuxCntlBus_I2S1_DO2_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S1_DO2_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S1_DO2_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_I2S1_DO2_MODE_3                        0x3
    #define        Gbl_pinMuxCntlBus_I2S1_DO2_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S1_DO3                  0x0841
    #define     B16Gbl_pinMuxCntlBus_I2S1_DO3                  0x0840
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_DO3                     15
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_DO3                     15
    #define       bGbl_pinMuxCntlBus_I2S1_DO3                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_DO3                     0x00038000
    #define        Gbl_pinMuxCntlBus_I2S1_DO3_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S1_DO3_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S1_DO3_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_I2S1_DO3_MODE_3                        0x3
    #define        Gbl_pinMuxCntlBus_I2S1_DO3_MODE_4                        0x4
    #define        Gbl_pinMuxCntlBus_I2S1_DO3_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S1_MCLK                 0x0842
    #define     B16Gbl_pinMuxCntlBus_I2S1_MCLK                 0x0842
    #define   LSb32Gbl_pinMuxCntlBus_I2S1_MCLK                    18
    #define   LSb16Gbl_pinMuxCntlBus_I2S1_MCLK                    2
    #define       bGbl_pinMuxCntlBus_I2S1_MCLK                 3
    #define   MSK32Gbl_pinMuxCntlBus_I2S1_MCLK                    0x001C0000
    #define        Gbl_pinMuxCntlBus_I2S1_MCLK_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_I2S1_MCLK_MODE_1                       0x1
    #define        Gbl_pinMuxCntlBus_I2S1_MCLK_MODE_5                       0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S2_BCLKIO               0x0842
    #define     B16Gbl_pinMuxCntlBus_I2S2_BCLKIO               0x0842
    #define   LSb32Gbl_pinMuxCntlBus_I2S2_BCLKIO                  21
    #define   LSb16Gbl_pinMuxCntlBus_I2S2_BCLKIO                  5
    #define       bGbl_pinMuxCntlBus_I2S2_BCLKIO               3
    #define   MSK32Gbl_pinMuxCntlBus_I2S2_BCLKIO                  0x00E00000
    #define        Gbl_pinMuxCntlBus_I2S2_BCLKIO_MODE_0                     0x0
    #define        Gbl_pinMuxCntlBus_I2S2_BCLKIO_MODE_1                     0x1
    #define        Gbl_pinMuxCntlBus_I2S2_BCLKIO_MODE_5                     0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S2_LRCKIO               0x0843
    #define     B16Gbl_pinMuxCntlBus_I2S2_LRCKIO               0x0842
    #define   LSb32Gbl_pinMuxCntlBus_I2S2_LRCKIO                  24
    #define   LSb16Gbl_pinMuxCntlBus_I2S2_LRCKIO                  8
    #define       bGbl_pinMuxCntlBus_I2S2_LRCKIO               3
    #define   MSK32Gbl_pinMuxCntlBus_I2S2_LRCKIO                  0x07000000
    #define        Gbl_pinMuxCntlBus_I2S2_LRCKIO_MODE_0                     0x0
    #define        Gbl_pinMuxCntlBus_I2S2_LRCKIO_MODE_1                     0x1
    #define        Gbl_pinMuxCntlBus_I2S2_LRCKIO_MODE_5                     0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S2_DI0                  0x0843
    #define     B16Gbl_pinMuxCntlBus_I2S2_DI0                  0x0842
    #define   LSb32Gbl_pinMuxCntlBus_I2S2_DI0                     27
    #define   LSb16Gbl_pinMuxCntlBus_I2S2_DI0                     11
    #define       bGbl_pinMuxCntlBus_I2S2_DI0                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S2_DI0                     0x38000000
    #define        Gbl_pinMuxCntlBus_I2S2_DI0_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S2_DI0_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S2_DI0_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_I2S2_DI0_MODE_5                        0x5

    #define     RA_Gbl_pinMuxCntlBus1                          0x0844

    #define     BA_Gbl_pinMuxCntlBus_I2S2_DI1                  0x0844
    #define     B16Gbl_pinMuxCntlBus_I2S2_DI1                  0x0844
    #define   LSb32Gbl_pinMuxCntlBus_I2S2_DI1                     0
    #define   LSb16Gbl_pinMuxCntlBus_I2S2_DI1                     0
    #define       bGbl_pinMuxCntlBus_I2S2_DI1                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S2_DI1                     0x00000007
    #define        Gbl_pinMuxCntlBus_I2S2_DI1_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S2_DI1_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S2_DI1_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_I2S2_DI1_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S2_DI2                  0x0844
    #define     B16Gbl_pinMuxCntlBus_I2S2_DI2                  0x0844
    #define   LSb32Gbl_pinMuxCntlBus_I2S2_DI2                     3
    #define   LSb16Gbl_pinMuxCntlBus_I2S2_DI2                     3
    #define       bGbl_pinMuxCntlBus_I2S2_DI2                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S2_DI2                     0x00000038
    #define        Gbl_pinMuxCntlBus_I2S2_DI2_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S2_DI2_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S2_DI2_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_I2S2_DI2_MODE_3                        0x3
    #define        Gbl_pinMuxCntlBus_I2S2_DI2_MODE_4                        0x4
    #define        Gbl_pinMuxCntlBus_I2S2_DI2_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S2_DI3                  0x0844
    #define     B16Gbl_pinMuxCntlBus_I2S2_DI3                  0x0844
    #define   LSb32Gbl_pinMuxCntlBus_I2S2_DI3                     6
    #define   LSb16Gbl_pinMuxCntlBus_I2S2_DI3                     6
    #define       bGbl_pinMuxCntlBus_I2S2_DI3                  3
    #define   MSK32Gbl_pinMuxCntlBus_I2S2_DI3                     0x000001C0
    #define        Gbl_pinMuxCntlBus_I2S2_DI3_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_I2S2_DI3_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_I2S2_DI3_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_I2S2_DI3_MODE_3                        0x3
    #define        Gbl_pinMuxCntlBus_I2S2_DI3_MODE_4                        0x4
    #define        Gbl_pinMuxCntlBus_I2S2_DI3_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_PDM_CLKO                  0x0845
    #define     B16Gbl_pinMuxCntlBus_PDM_CLKO                  0x0844
    #define   LSb32Gbl_pinMuxCntlBus_PDM_CLKO                     9
    #define   LSb16Gbl_pinMuxCntlBus_PDM_CLKO                     9
    #define       bGbl_pinMuxCntlBus_PDM_CLKO                  3
    #define   MSK32Gbl_pinMuxCntlBus_PDM_CLKO                     0x00000E00
    #define        Gbl_pinMuxCntlBus_PDM_CLKO_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_PDM_CLKO_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_PDM_CLKO_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_PDM_CLKO_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_PDM_DI0                   0x0845
    #define     B16Gbl_pinMuxCntlBus_PDM_DI0                   0x0844
    #define   LSb32Gbl_pinMuxCntlBus_PDM_DI0                      12
    #define   LSb16Gbl_pinMuxCntlBus_PDM_DI0                      12
    #define       bGbl_pinMuxCntlBus_PDM_DI0                   3
    #define   MSK32Gbl_pinMuxCntlBus_PDM_DI0                      0x00007000
    #define        Gbl_pinMuxCntlBus_PDM_DI0_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_PDM_DI0_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_PDM_DI0_MODE_5                         0x5

    #define     BA_Gbl_pinMuxCntlBus_PDM_DI1                   0x0845
    #define     B16Gbl_pinMuxCntlBus_PDM_DI1                   0x0844
    #define   LSb32Gbl_pinMuxCntlBus_PDM_DI1                      15
    #define   LSb16Gbl_pinMuxCntlBus_PDM_DI1                      15
    #define       bGbl_pinMuxCntlBus_PDM_DI1                   3
    #define   MSK32Gbl_pinMuxCntlBus_PDM_DI1                      0x00038000
    #define        Gbl_pinMuxCntlBus_PDM_DI1_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_PDM_DI1_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_PDM_DI1_MODE_5                         0x5

    #define     BA_Gbl_pinMuxCntlBus_PDM_DI2                   0x0846
    #define     B16Gbl_pinMuxCntlBus_PDM_DI2                   0x0846
    #define   LSb32Gbl_pinMuxCntlBus_PDM_DI2                      18
    #define   LSb16Gbl_pinMuxCntlBus_PDM_DI2                      2
    #define       bGbl_pinMuxCntlBus_PDM_DI2                   3
    #define   MSK32Gbl_pinMuxCntlBus_PDM_DI2                      0x001C0000
    #define        Gbl_pinMuxCntlBus_PDM_DI2_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_PDM_DI2_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_PDM_DI2_MODE_2                         0x2
    #define        Gbl_pinMuxCntlBus_PDM_DI2_MODE_3                         0x3
    #define        Gbl_pinMuxCntlBus_PDM_DI2_MODE_4                         0x4
    #define        Gbl_pinMuxCntlBus_PDM_DI2_MODE_5                         0x5

    #define     BA_Gbl_pinMuxCntlBus_PDM_DI3                   0x0846
    #define     B16Gbl_pinMuxCntlBus_PDM_DI3                   0x0846
    #define   LSb32Gbl_pinMuxCntlBus_PDM_DI3                      21
    #define   LSb16Gbl_pinMuxCntlBus_PDM_DI3                      5
    #define       bGbl_pinMuxCntlBus_PDM_DI3                   3
    #define   MSK32Gbl_pinMuxCntlBus_PDM_DI3                      0x00E00000
    #define        Gbl_pinMuxCntlBus_PDM_DI3_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_PDM_DI3_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_PDM_DI3_MODE_2                         0x2
    #define        Gbl_pinMuxCntlBus_PDM_DI3_MODE_3                         0x3
    #define        Gbl_pinMuxCntlBus_PDM_DI3_MODE_4                         0x4
    #define        Gbl_pinMuxCntlBus_PDM_DI3_MODE_5                         0x5

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO0                  0x0847
    #define     B16Gbl_pinMuxCntlBus_NAND_IO0                  0x0846
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO0                     24
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO0                     8
    #define       bGbl_pinMuxCntlBus_NAND_IO0                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO0                     0x07000000
    #define        Gbl_pinMuxCntlBus_NAND_IO0_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO0_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_IO0_MODE_4                        0x4

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO1                  0x0847
    #define     B16Gbl_pinMuxCntlBus_NAND_IO1                  0x0846
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO1                     27
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO1                     11
    #define       bGbl_pinMuxCntlBus_NAND_IO1                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO1                     0x38000000
    #define        Gbl_pinMuxCntlBus_NAND_IO1_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO1_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_IO1_MODE_4                        0x4

    #define     RA_Gbl_pinMuxCntlBus2                          0x0848

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO2                  0x0848
    #define     B16Gbl_pinMuxCntlBus_NAND_IO2                  0x0848
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO2                     0
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO2                     0
    #define       bGbl_pinMuxCntlBus_NAND_IO2                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO2                     0x00000007
    #define        Gbl_pinMuxCntlBus_NAND_IO2_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO2_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_IO2_MODE_4                        0x4

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO3                  0x0848
    #define     B16Gbl_pinMuxCntlBus_NAND_IO3                  0x0848
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO3                     3
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO3                     3
    #define       bGbl_pinMuxCntlBus_NAND_IO3                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO3                     0x00000038
    #define        Gbl_pinMuxCntlBus_NAND_IO3_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO3_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_IO3_MODE_4                        0x4

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO4                  0x0848
    #define     B16Gbl_pinMuxCntlBus_NAND_IO4                  0x0848
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO4                     6
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO4                     6
    #define       bGbl_pinMuxCntlBus_NAND_IO4                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO4                     0x000001C0
    #define        Gbl_pinMuxCntlBus_NAND_IO4_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO4_MODE_1                        0x1

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO5                  0x0849
    #define     B16Gbl_pinMuxCntlBus_NAND_IO5                  0x0848
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO5                     9
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO5                     9
    #define       bGbl_pinMuxCntlBus_NAND_IO5                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO5                     0x00000E00
    #define        Gbl_pinMuxCntlBus_NAND_IO5_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO5_MODE_1                        0x1

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO6                  0x0849
    #define     B16Gbl_pinMuxCntlBus_NAND_IO6                  0x0848
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO6                     12
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO6                     12
    #define       bGbl_pinMuxCntlBus_NAND_IO6                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO6                     0x00007000
    #define        Gbl_pinMuxCntlBus_NAND_IO6_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO6_MODE_1                        0x1

    #define     BA_Gbl_pinMuxCntlBus_NAND_IO7                  0x0849
    #define     B16Gbl_pinMuxCntlBus_NAND_IO7                  0x0848
    #define   LSb32Gbl_pinMuxCntlBus_NAND_IO7                     15
    #define   LSb16Gbl_pinMuxCntlBus_NAND_IO7                     15
    #define       bGbl_pinMuxCntlBus_NAND_IO7                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_IO7                     0x00038000
    #define        Gbl_pinMuxCntlBus_NAND_IO7_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_IO7_MODE_1                        0x1

    #define     BA_Gbl_pinMuxCntlBus_NAND_ALE                  0x084A
    #define     B16Gbl_pinMuxCntlBus_NAND_ALE                  0x084A
    #define   LSb32Gbl_pinMuxCntlBus_NAND_ALE                     18
    #define   LSb16Gbl_pinMuxCntlBus_NAND_ALE                     2
    #define       bGbl_pinMuxCntlBus_NAND_ALE                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_ALE                     0x001C0000
    #define        Gbl_pinMuxCntlBus_NAND_ALE_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_ALE_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_NAND_ALE_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_NAND_CLE                  0x084A
    #define     B16Gbl_pinMuxCntlBus_NAND_CLE                  0x084A
    #define   LSb32Gbl_pinMuxCntlBus_NAND_CLE                     21
    #define   LSb16Gbl_pinMuxCntlBus_NAND_CLE                     5
    #define       bGbl_pinMuxCntlBus_NAND_CLE                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_CLE                     0x00E00000
    #define        Gbl_pinMuxCntlBus_NAND_CLE_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_CLE_MODE_2                        0x2
    #define        Gbl_pinMuxCntlBus_NAND_CLE_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_NAND_WEn                  0x084B
    #define     B16Gbl_pinMuxCntlBus_NAND_WEn                  0x084A
    #define   LSb32Gbl_pinMuxCntlBus_NAND_WEn                     24
    #define   LSb16Gbl_pinMuxCntlBus_NAND_WEn                     8
    #define       bGbl_pinMuxCntlBus_NAND_WEn                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_WEn                     0x07000000
    #define        Gbl_pinMuxCntlBus_NAND_WEn_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_WEn_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_NAND_REn                  0x084B
    #define     B16Gbl_pinMuxCntlBus_NAND_REn                  0x084A
    #define   LSb32Gbl_pinMuxCntlBus_NAND_REn                     27
    #define   LSb16Gbl_pinMuxCntlBus_NAND_REn                     11
    #define       bGbl_pinMuxCntlBus_NAND_REn                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_REn                     0x38000000
    #define        Gbl_pinMuxCntlBus_NAND_REn_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_REn_MODE_3                        0x3

    #define     RA_Gbl_pinMuxCntlBus3                          0x084C

    #define     BA_Gbl_pinMuxCntlBus_NAND_WPn                  0x084C
    #define     B16Gbl_pinMuxCntlBus_NAND_WPn                  0x084C
    #define   LSb32Gbl_pinMuxCntlBus_NAND_WPn                     0
    #define   LSb16Gbl_pinMuxCntlBus_NAND_WPn                     0
    #define       bGbl_pinMuxCntlBus_NAND_WPn                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_WPn                     0x00000007
    #define        Gbl_pinMuxCntlBus_NAND_WPn_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_WPn_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_WPn_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_NAND_CEn                  0x084C
    #define     B16Gbl_pinMuxCntlBus_NAND_CEn                  0x084C
    #define   LSb32Gbl_pinMuxCntlBus_NAND_CEn                     3
    #define   LSb16Gbl_pinMuxCntlBus_NAND_CEn                     3
    #define       bGbl_pinMuxCntlBus_NAND_CEn                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_CEn                     0x00000038
    #define        Gbl_pinMuxCntlBus_NAND_CEn_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_CEn_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_CEn_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_NAND_RDY                  0x084C
    #define     B16Gbl_pinMuxCntlBus_NAND_RDY                  0x084C
    #define   LSb32Gbl_pinMuxCntlBus_NAND_RDY                     6
    #define   LSb16Gbl_pinMuxCntlBus_NAND_RDY                     6
    #define       bGbl_pinMuxCntlBus_NAND_RDY                  3
    #define   MSK32Gbl_pinMuxCntlBus_NAND_RDY                     0x000001C0
    #define        Gbl_pinMuxCntlBus_NAND_RDY_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_NAND_RDY_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_NAND_RDY_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SS0n                 0x084D
    #define     B16Gbl_pinMuxCntlBus_SPI1_SS0n                 0x084C
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SS0n                    9
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SS0n                    9
    #define       bGbl_pinMuxCntlBus_SPI1_SS0n                 3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SS0n                    0x00000E00
    #define        Gbl_pinMuxCntlBus_SPI1_SS0n_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SS0n_MODE_1                       0x1

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SS1n                 0x084D
    #define     B16Gbl_pinMuxCntlBus_SPI1_SS1n                 0x084C
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SS1n                    12
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SS1n                    12
    #define       bGbl_pinMuxCntlBus_SPI1_SS1n                 3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SS1n                    0x00007000
    #define        Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_2                       0x2
    #define        Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_3                       0x3

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SS2n                 0x084D
    #define     B16Gbl_pinMuxCntlBus_SPI1_SS2n                 0x084C
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SS2n                    15
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SS2n                    15
    #define       bGbl_pinMuxCntlBus_SPI1_SS2n                 3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SS2n                    0x00038000
    #define        Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_1                       0x1
    #define        Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_2                       0x2
    #define        Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_3                       0x3

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SS3n                 0x084E
    #define     B16Gbl_pinMuxCntlBus_SPI1_SS3n                 0x084E
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SS3n                    18
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SS3n                    2
    #define       bGbl_pinMuxCntlBus_SPI1_SS3n                 3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SS3n                    0x001C0000
    #define        Gbl_pinMuxCntlBus_SPI1_SS3n_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SS3n_MODE_1                       0x1
    #define        Gbl_pinMuxCntlBus_SPI1_SS3n_MODE_2                       0x2

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SCLK                 0x084E
    #define     B16Gbl_pinMuxCntlBus_SPI1_SCLK                 0x084E
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SCLK                    21
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SCLK                    5
    #define       bGbl_pinMuxCntlBus_SPI1_SCLK                 3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SCLK                    0x00E00000
    #define        Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_1                       0x1
    #define        Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_3                       0x3

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SDO                  0x084F
    #define     B16Gbl_pinMuxCntlBus_SPI1_SDO                  0x084E
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SDO                     24
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SDO                     8
    #define       bGbl_pinMuxCntlBus_SPI1_SDO                  3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SDO                     0x07000000
    #define        Gbl_pinMuxCntlBus_SPI1_SDO_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SDO_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_SPI1_SDO_MODE_3                        0x3

    #define     BA_Gbl_pinMuxCntlBus_SPI1_SDI                  0x084F
    #define     B16Gbl_pinMuxCntlBus_SPI1_SDI                  0x084E
    #define   LSb32Gbl_pinMuxCntlBus_SPI1_SDI                     27
    #define   LSb16Gbl_pinMuxCntlBus_SPI1_SDI                     11
    #define       bGbl_pinMuxCntlBus_SPI1_SDI                  3
    #define   MSK32Gbl_pinMuxCntlBus_SPI1_SDI                     0x38000000
    #define        Gbl_pinMuxCntlBus_SPI1_SDI_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_SPI1_SDI_MODE_1                        0x1

    #define     RA_Gbl_pinMuxCntlBus4                          0x0850

    #define     BA_Gbl_pinMuxCntlBus_USB0_DRV_VBUS             0x0850
    #define     B16Gbl_pinMuxCntlBus_USB0_DRV_VBUS             0x0850
    #define   LSb32Gbl_pinMuxCntlBus_USB0_DRV_VBUS                0
    #define   LSb16Gbl_pinMuxCntlBus_USB0_DRV_VBUS                0
    #define       bGbl_pinMuxCntlBus_USB0_DRV_VBUS             3
    #define   MSK32Gbl_pinMuxCntlBus_USB0_DRV_VBUS                0x00000007
    #define        Gbl_pinMuxCntlBus_USB0_DRV_VBUS_MODE_0                   0x0
    #define        Gbl_pinMuxCntlBus_USB0_DRV_VBUS_MODE_1                   0x1
    #define        Gbl_pinMuxCntlBus_USB0_DRV_VBUS_MODE_3                   0x3

    #define     BA_Gbl_pinMuxCntlBus_TW1_SCL                   0x0850
    #define     B16Gbl_pinMuxCntlBus_TW1_SCL                   0x0850
    #define   LSb32Gbl_pinMuxCntlBus_TW1_SCL                      3
    #define   LSb16Gbl_pinMuxCntlBus_TW1_SCL                      3
    #define       bGbl_pinMuxCntlBus_TW1_SCL                   3
    #define   MSK32Gbl_pinMuxCntlBus_TW1_SCL                      0x00000038
    #define        Gbl_pinMuxCntlBus_TW1_SCL_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_TW1_SCL_MODE_1                         0x1

    #define     BA_Gbl_pinMuxCntlBus_TW1_SDA                   0x0850
    #define     B16Gbl_pinMuxCntlBus_TW1_SDA                   0x0850
    #define   LSb32Gbl_pinMuxCntlBus_TW1_SDA                      6
    #define   LSb16Gbl_pinMuxCntlBus_TW1_SDA                      6
    #define       bGbl_pinMuxCntlBus_TW1_SDA                   3
    #define   MSK32Gbl_pinMuxCntlBus_TW1_SDA                      0x000001C0
    #define        Gbl_pinMuxCntlBus_TW1_SDA_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_TW1_SDA_MODE_1                         0x1

    #define     BA_Gbl_pinMuxCntlBus_TW0_SCL                   0x0851
    #define     B16Gbl_pinMuxCntlBus_TW0_SCL                   0x0850
    #define   LSb32Gbl_pinMuxCntlBus_TW0_SCL                      9
    #define   LSb16Gbl_pinMuxCntlBus_TW0_SCL                      9
    #define       bGbl_pinMuxCntlBus_TW0_SCL                   3
    #define   MSK32Gbl_pinMuxCntlBus_TW0_SCL                      0x00000E00
    #define        Gbl_pinMuxCntlBus_TW0_SCL_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_TW0_SCL_MODE_1                         0x1

    #define     BA_Gbl_pinMuxCntlBus_TW0_SDA                   0x0851
    #define     B16Gbl_pinMuxCntlBus_TW0_SDA                   0x0850
    #define   LSb32Gbl_pinMuxCntlBus_TW0_SDA                      12
    #define   LSb16Gbl_pinMuxCntlBus_TW0_SDA                      12
    #define       bGbl_pinMuxCntlBus_TW0_SDA                   3
    #define   MSK32Gbl_pinMuxCntlBus_TW0_SDA                      0x00007000
    #define        Gbl_pinMuxCntlBus_TW0_SDA_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_TW0_SDA_MODE_1                         0x1

    #define     BA_Gbl_pinMuxCntlBus_TMS                       0x0851
    #define     B16Gbl_pinMuxCntlBus_TMS                       0x0850
    #define   LSb32Gbl_pinMuxCntlBus_TMS                          15
    #define   LSb16Gbl_pinMuxCntlBus_TMS                          15
    #define       bGbl_pinMuxCntlBus_TMS                       3
    #define   MSK32Gbl_pinMuxCntlBus_TMS                          0x00038000
    #define        Gbl_pinMuxCntlBus_TMS_MODE_0                             0x0
    #define        Gbl_pinMuxCntlBus_TMS_MODE_1                             0x1
    #define        Gbl_pinMuxCntlBus_TMS_MODE_4                             0x4

    #define     BA_Gbl_pinMuxCntlBus_TDI                       0x0852
    #define     B16Gbl_pinMuxCntlBus_TDI                       0x0852
    #define   LSb32Gbl_pinMuxCntlBus_TDI                          18
    #define   LSb16Gbl_pinMuxCntlBus_TDI                          2
    #define       bGbl_pinMuxCntlBus_TDI                       3
    #define   MSK32Gbl_pinMuxCntlBus_TDI                          0x001C0000
    #define        Gbl_pinMuxCntlBus_TDI_MODE_0                             0x0
    #define        Gbl_pinMuxCntlBus_TDI_MODE_1                             0x1
    #define        Gbl_pinMuxCntlBus_TDI_MODE_4                             0x4

    #define     BA_Gbl_pinMuxCntlBus_TDO                       0x0852
    #define     B16Gbl_pinMuxCntlBus_TDO                       0x0852
    #define   LSb32Gbl_pinMuxCntlBus_TDO                          21
    #define   LSb16Gbl_pinMuxCntlBus_TDO                          5
    #define       bGbl_pinMuxCntlBus_TDO                       3
    #define   MSK32Gbl_pinMuxCntlBus_TDO                          0x00E00000
    #define        Gbl_pinMuxCntlBus_TDO_MODE_0                             0x0
    #define        Gbl_pinMuxCntlBus_TDO_MODE_1                             0x1
    #define        Gbl_pinMuxCntlBus_TDO_MODE_4                             0x4

    #define     BA_Gbl_pinMuxCntlBus_PWM6                      0x0853
    #define     B16Gbl_pinMuxCntlBus_PWM6                      0x0852
    #define   LSb32Gbl_pinMuxCntlBus_PWM6                         24
    #define   LSb16Gbl_pinMuxCntlBus_PWM6                         8
    #define       bGbl_pinMuxCntlBus_PWM6                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM6                         0x07000000
    #define        Gbl_pinMuxCntlBus_PWM6_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM6_MODE_1                            0x1

    #define     BA_Gbl_pinMuxCntlBus_PWM7                      0x0853
    #define     B16Gbl_pinMuxCntlBus_PWM7                      0x0852
    #define   LSb32Gbl_pinMuxCntlBus_PWM7                         27
    #define   LSb16Gbl_pinMuxCntlBus_PWM7                         11
    #define       bGbl_pinMuxCntlBus_PWM7                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM7                         0x38000000
    #define        Gbl_pinMuxCntlBus_PWM7_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM7_MODE_1                            0x1

    #define     RA_Gbl_pinMuxCntlBus5                          0x0854

    #define     BA_Gbl_pinMuxCntlBus_PWM0                      0x0854
    #define     B16Gbl_pinMuxCntlBus_PWM0                      0x0854
    #define   LSb32Gbl_pinMuxCntlBus_PWM0                         0
    #define   LSb16Gbl_pinMuxCntlBus_PWM0                         0
    #define       bGbl_pinMuxCntlBus_PWM0                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM0                         0x00000007
    #define        Gbl_pinMuxCntlBus_PWM0_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM0_MODE_1                            0x1
    #define        Gbl_pinMuxCntlBus_PWM0_MODE_2                            0x2

    #define     BA_Gbl_pinMuxCntlBus_PWM1                      0x0854
    #define     B16Gbl_pinMuxCntlBus_PWM1                      0x0854
    #define   LSb32Gbl_pinMuxCntlBus_PWM1                         3
    #define   LSb16Gbl_pinMuxCntlBus_PWM1                         3
    #define       bGbl_pinMuxCntlBus_PWM1                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM1                         0x00000038
    #define        Gbl_pinMuxCntlBus_PWM1_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM1_MODE_1                            0x1

    #define     BA_Gbl_pinMuxCntlBus_PWM2                      0x0854
    #define     B16Gbl_pinMuxCntlBus_PWM2                      0x0854
    #define   LSb32Gbl_pinMuxCntlBus_PWM2                         6
    #define   LSb16Gbl_pinMuxCntlBus_PWM2                         6
    #define       bGbl_pinMuxCntlBus_PWM2                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM2                         0x000001C0
    #define        Gbl_pinMuxCntlBus_PWM2_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM2_MODE_1                            0x1

    #define     BA_Gbl_pinMuxCntlBus_PWM3                      0x0855
    #define     B16Gbl_pinMuxCntlBus_PWM3                      0x0854
    #define   LSb32Gbl_pinMuxCntlBus_PWM3                         9
    #define   LSb16Gbl_pinMuxCntlBus_PWM3                         9
    #define       bGbl_pinMuxCntlBus_PWM3                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM3                         0x00000E00
    #define        Gbl_pinMuxCntlBus_PWM3_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM3_MODE_1                            0x1

    #define     BA_Gbl_pinMuxCntlBus_PWM4                      0x0855
    #define     B16Gbl_pinMuxCntlBus_PWM4                      0x0854
    #define   LSb32Gbl_pinMuxCntlBus_PWM4                         12
    #define   LSb16Gbl_pinMuxCntlBus_PWM4                         12
    #define       bGbl_pinMuxCntlBus_PWM4                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM4                         0x00007000
    #define        Gbl_pinMuxCntlBus_PWM4_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM4_MODE_1                            0x1

    #define     BA_Gbl_pinMuxCntlBus_PWM5                      0x0855
    #define     B16Gbl_pinMuxCntlBus_PWM5                      0x0854
    #define   LSb32Gbl_pinMuxCntlBus_PWM5                         15
    #define   LSb16Gbl_pinMuxCntlBus_PWM5                         15
    #define       bGbl_pinMuxCntlBus_PWM5                      3
    #define   MSK32Gbl_pinMuxCntlBus_PWM5                         0x00038000
    #define        Gbl_pinMuxCntlBus_PWM5_MODE_0                            0x0
    #define        Gbl_pinMuxCntlBus_PWM5_MODE_1                            0x1

    #define     BA_Gbl_pinMuxCntlBus_URT1_RTSn                 0x0856
    #define     B16Gbl_pinMuxCntlBus_URT1_RTSn                 0x0856
    #define   LSb32Gbl_pinMuxCntlBus_URT1_RTSn                    18
    #define   LSb16Gbl_pinMuxCntlBus_URT1_RTSn                    2
    #define       bGbl_pinMuxCntlBus_URT1_RTSn                 3
    #define   MSK32Gbl_pinMuxCntlBus_URT1_RTSn                    0x001C0000
    #define        Gbl_pinMuxCntlBus_URT1_RTSn_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_URT1_RTSn_MODE_1                       0x1
    #define        Gbl_pinMuxCntlBus_URT1_RTSn_MODE_2                       0x2
    #define        Gbl_pinMuxCntlBus_URT1_RTSn_MODE_3                       0x3
    #define        Gbl_pinMuxCntlBus_URT1_RTSn_MODE_4                       0x4
    #define        Gbl_pinMuxCntlBus_URT1_RTSn_MODE_5                       0x5

    #define     BA_Gbl_pinMuxCntlBus_URT1_CTSn                 0x0856
    #define     B16Gbl_pinMuxCntlBus_URT1_CTSn                 0x0856
    #define   LSb32Gbl_pinMuxCntlBus_URT1_CTSn                    21
    #define   LSb16Gbl_pinMuxCntlBus_URT1_CTSn                    5
    #define       bGbl_pinMuxCntlBus_URT1_CTSn                 3
    #define   MSK32Gbl_pinMuxCntlBus_URT1_CTSn                    0x00E00000
    #define        Gbl_pinMuxCntlBus_URT1_CTSn_MODE_0                       0x0
    #define        Gbl_pinMuxCntlBus_URT1_CTSn_MODE_1                       0x1
    #define        Gbl_pinMuxCntlBus_URT1_CTSn_MODE_2                       0x2
    #define        Gbl_pinMuxCntlBus_URT1_CTSn_MODE_3                       0x3
    #define        Gbl_pinMuxCntlBus_URT1_CTSn_MODE_4                       0x4
    #define        Gbl_pinMuxCntlBus_URT1_CTSn_MODE_5                       0x5

    #define     BA_Gbl_pinMuxCntlBus_URT1_RXD                  0x0857
    #define     B16Gbl_pinMuxCntlBus_URT1_RXD                  0x0856
    #define   LSb32Gbl_pinMuxCntlBus_URT1_RXD                     24
    #define   LSb16Gbl_pinMuxCntlBus_URT1_RXD                     8
    #define       bGbl_pinMuxCntlBus_URT1_RXD                  3
    #define   MSK32Gbl_pinMuxCntlBus_URT1_RXD                     0x07000000
    #define        Gbl_pinMuxCntlBus_URT1_RXD_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_URT1_RXD_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_URT1_RXD_MODE_4                        0x4
    #define        Gbl_pinMuxCntlBus_URT1_RXD_MODE_5                        0x5

    #define     BA_Gbl_pinMuxCntlBus_URT1_TXD                  0x0857
    #define     B16Gbl_pinMuxCntlBus_URT1_TXD                  0x0856
    #define   LSb32Gbl_pinMuxCntlBus_URT1_TXD                     27
    #define   LSb16Gbl_pinMuxCntlBus_URT1_TXD                     11
    #define       bGbl_pinMuxCntlBus_URT1_TXD                  3
    #define   MSK32Gbl_pinMuxCntlBus_URT1_TXD                     0x38000000
    #define        Gbl_pinMuxCntlBus_URT1_TXD_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_URT1_TXD_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_URT1_TXD_MODE_4                        0x4
    #define        Gbl_pinMuxCntlBus_URT1_TXD_MODE_5                        0x5

    #define     RA_Gbl_pinMuxCntlBus6                          0x0858

    #define     BA_Gbl_pinMuxCntlBus_I2S3_DI                   0x0858
    #define     B16Gbl_pinMuxCntlBus_I2S3_DI                   0x0858
    #define   LSb32Gbl_pinMuxCntlBus_I2S3_DI                      0
    #define   LSb16Gbl_pinMuxCntlBus_I2S3_DI                      0
    #define       bGbl_pinMuxCntlBus_I2S3_DI                   3
    #define   MSK32Gbl_pinMuxCntlBus_I2S3_DI                      0x00000007
    #define        Gbl_pinMuxCntlBus_I2S3_DI_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_I2S3_DI_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_I2S3_DI_MODE_5                         0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S3_DO                   0x0858
    #define     B16Gbl_pinMuxCntlBus_I2S3_DO                   0x0858
    #define   LSb32Gbl_pinMuxCntlBus_I2S3_DO                      3
    #define   LSb16Gbl_pinMuxCntlBus_I2S3_DO                      3
    #define       bGbl_pinMuxCntlBus_I2S3_DO                   3
    #define   MSK32Gbl_pinMuxCntlBus_I2S3_DO                      0x00000038
    #define        Gbl_pinMuxCntlBus_I2S3_DO_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_I2S3_DO_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_I2S3_DO_MODE_5                         0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S3_BCLKIO               0x0858
    #define     B16Gbl_pinMuxCntlBus_I2S3_BCLKIO               0x0858
    #define   LSb32Gbl_pinMuxCntlBus_I2S3_BCLKIO                  6
    #define   LSb16Gbl_pinMuxCntlBus_I2S3_BCLKIO                  6
    #define       bGbl_pinMuxCntlBus_I2S3_BCLKIO               3
    #define   MSK32Gbl_pinMuxCntlBus_I2S3_BCLKIO                  0x000001C0
    #define        Gbl_pinMuxCntlBus_I2S3_BCLKIO_MODE_0                     0x0
    #define        Gbl_pinMuxCntlBus_I2S3_BCLKIO_MODE_1                     0x1
    #define        Gbl_pinMuxCntlBus_I2S3_BCLKIO_MODE_5                     0x5

    #define     BA_Gbl_pinMuxCntlBus_I2S3_LRCKIO               0x0859
    #define     B16Gbl_pinMuxCntlBus_I2S3_LRCKIO               0x0858
    #define   LSb32Gbl_pinMuxCntlBus_I2S3_LRCKIO                  9
    #define   LSb16Gbl_pinMuxCntlBus_I2S3_LRCKIO                  9
    #define       bGbl_pinMuxCntlBus_I2S3_LRCKIO               3
    #define   MSK32Gbl_pinMuxCntlBus_I2S3_LRCKIO                  0x00000E00
    #define        Gbl_pinMuxCntlBus_I2S3_LRCKIO_MODE_0                     0x0
    #define        Gbl_pinMuxCntlBus_I2S3_LRCKIO_MODE_1                     0x1

    #define     BA_Gbl_pinMuxCntlBus_SD0_DAT0                  0x0859
    #define     B16Gbl_pinMuxCntlBus_SD0_DAT0                  0x0858
    #define   LSb32Gbl_pinMuxCntlBus_SD0_DAT0                     12
    #define   LSb16Gbl_pinMuxCntlBus_SD0_DAT0                     12
    #define       bGbl_pinMuxCntlBus_SD0_DAT0                  3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_DAT0                     0x00007000
    #define        Gbl_pinMuxCntlBus_SD0_DAT0_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_SD0_DAT0_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_SD0_DAT0_MODE_2                        0x2

    #define     BA_Gbl_pinMuxCntlBus_SD0_DAT1                  0x0859
    #define     B16Gbl_pinMuxCntlBus_SD0_DAT1                  0x0858
    #define   LSb32Gbl_pinMuxCntlBus_SD0_DAT1                     15
    #define   LSb16Gbl_pinMuxCntlBus_SD0_DAT1                     15
    #define       bGbl_pinMuxCntlBus_SD0_DAT1                  3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_DAT1                     0x00038000
    #define        Gbl_pinMuxCntlBus_SD0_DAT1_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_SD0_DAT1_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_SD0_DAT1_MODE_2                        0x2

    #define     BA_Gbl_pinMuxCntlBus_SD0_CLK                   0x085A
    #define     B16Gbl_pinMuxCntlBus_SD0_CLK                   0x085A
    #define   LSb32Gbl_pinMuxCntlBus_SD0_CLK                      18
    #define   LSb16Gbl_pinMuxCntlBus_SD0_CLK                      2
    #define       bGbl_pinMuxCntlBus_SD0_CLK                   3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_CLK                      0x001C0000
    #define        Gbl_pinMuxCntlBus_SD0_CLK_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_SD0_CLK_MODE_1                         0x1

    #define     BA_Gbl_pinMuxCntlBus_SD0_DAT2                  0x085A
    #define     B16Gbl_pinMuxCntlBus_SD0_DAT2                  0x085A
    #define   LSb32Gbl_pinMuxCntlBus_SD0_DAT2                     21
    #define   LSb16Gbl_pinMuxCntlBus_SD0_DAT2                     5
    #define       bGbl_pinMuxCntlBus_SD0_DAT2                  3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_DAT2                     0x00E00000
    #define        Gbl_pinMuxCntlBus_SD0_DAT2_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_SD0_DAT2_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_SD0_DAT2_MODE_2                        0x2

    #define     BA_Gbl_pinMuxCntlBus_SD0_DAT3                  0x085B
    #define     B16Gbl_pinMuxCntlBus_SD0_DAT3                  0x085A
    #define   LSb32Gbl_pinMuxCntlBus_SD0_DAT3                     24
    #define   LSb16Gbl_pinMuxCntlBus_SD0_DAT3                     8
    #define       bGbl_pinMuxCntlBus_SD0_DAT3                  3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_DAT3                     0x07000000
    #define        Gbl_pinMuxCntlBus_SD0_DAT3_MODE_0                        0x0
    #define        Gbl_pinMuxCntlBus_SD0_DAT3_MODE_1                        0x1
    #define        Gbl_pinMuxCntlBus_SD0_DAT3_MODE_2                        0x2

    #define     BA_Gbl_pinMuxCntlBus_SD0_CMD                   0x085B
    #define     B16Gbl_pinMuxCntlBus_SD0_CMD                   0x085A
    #define   LSb32Gbl_pinMuxCntlBus_SD0_CMD                      27
    #define   LSb16Gbl_pinMuxCntlBus_SD0_CMD                      11
    #define       bGbl_pinMuxCntlBus_SD0_CMD                   3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_CMD                      0x38000000
    #define        Gbl_pinMuxCntlBus_SD0_CMD_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_SD0_CMD_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_SD0_CMD_MODE_2                         0x2

    #define     RA_Gbl_pinMuxCntlBus7                          0x085C

    #define     BA_Gbl_pinMuxCntlBus_SD0_CDn                   0x085C
    #define     B16Gbl_pinMuxCntlBus_SD0_CDn                   0x085C
    #define   LSb32Gbl_pinMuxCntlBus_SD0_CDn                      0
    #define   LSb16Gbl_pinMuxCntlBus_SD0_CDn                      0
    #define       bGbl_pinMuxCntlBus_SD0_CDn                   3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_CDn                      0x00000007
    #define        Gbl_pinMuxCntlBus_SD0_CDn_MODE_0                         0x0
    #define        Gbl_pinMuxCntlBus_SD0_CDn_MODE_1                         0x1
    #define        Gbl_pinMuxCntlBus_SD0_CDn_MODE_3                         0x3

    #define     BA_Gbl_pinMuxCntlBus_SD0_WP                    0x085C
    #define     B16Gbl_pinMuxCntlBus_SD0_WP                    0x085C
    #define   LSb32Gbl_pinMuxCntlBus_SD0_WP                       3
    #define   LSb16Gbl_pinMuxCntlBus_SD0_WP                       3
    #define       bGbl_pinMuxCntlBus_SD0_WP                    3
    #define   MSK32Gbl_pinMuxCntlBus_SD0_WP                       0x00000038
    #define        Gbl_pinMuxCntlBus_SD0_WP_MODE_0                          0x0
    #define        Gbl_pinMuxCntlBus_SD0_WP_MODE_1                          0x1
    #define        Gbl_pinMuxCntlBus_SD0_WP_MODE_3                          0x3
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_BCLKIOCntl                         0x0860

    #define     BA_Gbl_I2S1_BCLKIOCntl_DRV                     0x0860
    #define     B16Gbl_I2S1_BCLKIOCntl_DRV                     0x0860
    #define   LSb32Gbl_I2S1_BCLKIOCntl_DRV                        0
    #define   LSb16Gbl_I2S1_BCLKIOCntl_DRV                        0
    #define       bGbl_I2S1_BCLKIOCntl_DRV                     2
    #define   MSK32Gbl_I2S1_BCLKIOCntl_DRV                        0x00000003

    #define     BA_Gbl_I2S1_BCLKIOCntl_PDEN                    0x0860
    #define     B16Gbl_I2S1_BCLKIOCntl_PDEN                    0x0860
    #define   LSb32Gbl_I2S1_BCLKIOCntl_PDEN                       2
    #define   LSb16Gbl_I2S1_BCLKIOCntl_PDEN                       2
    #define       bGbl_I2S1_BCLKIOCntl_PDEN                    1
    #define   MSK32Gbl_I2S1_BCLKIOCntl_PDEN                       0x00000004

    #define     BA_Gbl_I2S1_BCLKIOCntl_PUEN                    0x0860
    #define     B16Gbl_I2S1_BCLKIOCntl_PUEN                    0x0860
    #define   LSb32Gbl_I2S1_BCLKIOCntl_PUEN                       3
    #define   LSb16Gbl_I2S1_BCLKIOCntl_PUEN                       3
    #define       bGbl_I2S1_BCLKIOCntl_PUEN                    1
    #define   MSK32Gbl_I2S1_BCLKIOCntl_PUEN                       0x00000008

    #define     BA_Gbl_I2S1_BCLKIOCntl_RXEN                    0x0860
    #define     B16Gbl_I2S1_BCLKIOCntl_RXEN                    0x0860
    #define   LSb32Gbl_I2S1_BCLKIOCntl_RXEN                       4
    #define   LSb16Gbl_I2S1_BCLKIOCntl_RXEN                       4
    #define       bGbl_I2S1_BCLKIOCntl_RXEN                    1
    #define   MSK32Gbl_I2S1_BCLKIOCntl_RXEN                       0x00000010

    #define     BA_Gbl_I2S1_BCLKIOCntl_SRC                     0x0860
    #define     B16Gbl_I2S1_BCLKIOCntl_SRC                     0x0860
    #define   LSb32Gbl_I2S1_BCLKIOCntl_SRC                        5
    #define   LSb16Gbl_I2S1_BCLKIOCntl_SRC                        5
    #define       bGbl_I2S1_BCLKIOCntl_SRC                     1
    #define   MSK32Gbl_I2S1_BCLKIOCntl_SRC                        0x00000020

    #define     BA_Gbl_I2S1_BCLKIOCntl_SMTC                    0x0860
    #define     B16Gbl_I2S1_BCLKIOCntl_SMTC                    0x0860
    #define   LSb32Gbl_I2S1_BCLKIOCntl_SMTC                       6
    #define   LSb16Gbl_I2S1_BCLKIOCntl_SMTC                       6
    #define       bGbl_I2S1_BCLKIOCntl_SMTC                    1
    #define   MSK32Gbl_I2S1_BCLKIOCntl_SMTC                       0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_LRCKIOCntl                         0x0864

    #define     BA_Gbl_I2S1_LRCKIOCntl_DRV                     0x0864
    #define     B16Gbl_I2S1_LRCKIOCntl_DRV                     0x0864
    #define   LSb32Gbl_I2S1_LRCKIOCntl_DRV                        0
    #define   LSb16Gbl_I2S1_LRCKIOCntl_DRV                        0
    #define       bGbl_I2S1_LRCKIOCntl_DRV                     2
    #define   MSK32Gbl_I2S1_LRCKIOCntl_DRV                        0x00000003

    #define     BA_Gbl_I2S1_LRCKIOCntl_PDEN                    0x0864
    #define     B16Gbl_I2S1_LRCKIOCntl_PDEN                    0x0864
    #define   LSb32Gbl_I2S1_LRCKIOCntl_PDEN                       2
    #define   LSb16Gbl_I2S1_LRCKIOCntl_PDEN                       2
    #define       bGbl_I2S1_LRCKIOCntl_PDEN                    1
    #define   MSK32Gbl_I2S1_LRCKIOCntl_PDEN                       0x00000004

    #define     BA_Gbl_I2S1_LRCKIOCntl_PUEN                    0x0864
    #define     B16Gbl_I2S1_LRCKIOCntl_PUEN                    0x0864
    #define   LSb32Gbl_I2S1_LRCKIOCntl_PUEN                       3
    #define   LSb16Gbl_I2S1_LRCKIOCntl_PUEN                       3
    #define       bGbl_I2S1_LRCKIOCntl_PUEN                    1
    #define   MSK32Gbl_I2S1_LRCKIOCntl_PUEN                       0x00000008

    #define     BA_Gbl_I2S1_LRCKIOCntl_RXEN                    0x0864
    #define     B16Gbl_I2S1_LRCKIOCntl_RXEN                    0x0864
    #define   LSb32Gbl_I2S1_LRCKIOCntl_RXEN                       4
    #define   LSb16Gbl_I2S1_LRCKIOCntl_RXEN                       4
    #define       bGbl_I2S1_LRCKIOCntl_RXEN                    1
    #define   MSK32Gbl_I2S1_LRCKIOCntl_RXEN                       0x00000010

    #define     BA_Gbl_I2S1_LRCKIOCntl_SRC                     0x0864
    #define     B16Gbl_I2S1_LRCKIOCntl_SRC                     0x0864
    #define   LSb32Gbl_I2S1_LRCKIOCntl_SRC                        5
    #define   LSb16Gbl_I2S1_LRCKIOCntl_SRC                        5
    #define       bGbl_I2S1_LRCKIOCntl_SRC                     1
    #define   MSK32Gbl_I2S1_LRCKIOCntl_SRC                        0x00000020

    #define     BA_Gbl_I2S1_LRCKIOCntl_SMTC                    0x0864
    #define     B16Gbl_I2S1_LRCKIOCntl_SMTC                    0x0864
    #define   LSb32Gbl_I2S1_LRCKIOCntl_SMTC                       6
    #define   LSb16Gbl_I2S1_LRCKIOCntl_SMTC                       6
    #define       bGbl_I2S1_LRCKIOCntl_SMTC                    1
    #define   MSK32Gbl_I2S1_LRCKIOCntl_SMTC                       0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_DO0Cntl                            0x0868

    #define     BA_Gbl_I2S1_DO0Cntl_DRV                        0x0868
    #define     B16Gbl_I2S1_DO0Cntl_DRV                        0x0868
    #define   LSb32Gbl_I2S1_DO0Cntl_DRV                           0
    #define   LSb16Gbl_I2S1_DO0Cntl_DRV                           0
    #define       bGbl_I2S1_DO0Cntl_DRV                        2
    #define   MSK32Gbl_I2S1_DO0Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S1_DO0Cntl_PDEN                       0x0868
    #define     B16Gbl_I2S1_DO0Cntl_PDEN                       0x0868
    #define   LSb32Gbl_I2S1_DO0Cntl_PDEN                          2
    #define   LSb16Gbl_I2S1_DO0Cntl_PDEN                          2
    #define       bGbl_I2S1_DO0Cntl_PDEN                       1
    #define   MSK32Gbl_I2S1_DO0Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S1_DO0Cntl_PUEN                       0x0868
    #define     B16Gbl_I2S1_DO0Cntl_PUEN                       0x0868
    #define   LSb32Gbl_I2S1_DO0Cntl_PUEN                          3
    #define   LSb16Gbl_I2S1_DO0Cntl_PUEN                          3
    #define       bGbl_I2S1_DO0Cntl_PUEN                       1
    #define   MSK32Gbl_I2S1_DO0Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S1_DO0Cntl_SRC                        0x0868
    #define     B16Gbl_I2S1_DO0Cntl_SRC                        0x0868
    #define   LSb32Gbl_I2S1_DO0Cntl_SRC                           4
    #define   LSb16Gbl_I2S1_DO0Cntl_SRC                           4
    #define       bGbl_I2S1_DO0Cntl_SRC                        1
    #define   MSK32Gbl_I2S1_DO0Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S1_DO0Cntl_SMTC                       0x0868
    #define     B16Gbl_I2S1_DO0Cntl_SMTC                       0x0868
    #define   LSb32Gbl_I2S1_DO0Cntl_SMTC                          5
    #define   LSb16Gbl_I2S1_DO0Cntl_SMTC                          5
    #define       bGbl_I2S1_DO0Cntl_SMTC                       1
    #define   MSK32Gbl_I2S1_DO0Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_DO1Cntl                            0x086C

    #define     BA_Gbl_I2S1_DO1Cntl_DRV                        0x086C
    #define     B16Gbl_I2S1_DO1Cntl_DRV                        0x086C
    #define   LSb32Gbl_I2S1_DO1Cntl_DRV                           0
    #define   LSb16Gbl_I2S1_DO1Cntl_DRV                           0
    #define       bGbl_I2S1_DO1Cntl_DRV                        2
    #define   MSK32Gbl_I2S1_DO1Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S1_DO1Cntl_PDEN                       0x086C
    #define     B16Gbl_I2S1_DO1Cntl_PDEN                       0x086C
    #define   LSb32Gbl_I2S1_DO1Cntl_PDEN                          2
    #define   LSb16Gbl_I2S1_DO1Cntl_PDEN                          2
    #define       bGbl_I2S1_DO1Cntl_PDEN                       1
    #define   MSK32Gbl_I2S1_DO1Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S1_DO1Cntl_PUEN                       0x086C
    #define     B16Gbl_I2S1_DO1Cntl_PUEN                       0x086C
    #define   LSb32Gbl_I2S1_DO1Cntl_PUEN                          3
    #define   LSb16Gbl_I2S1_DO1Cntl_PUEN                          3
    #define       bGbl_I2S1_DO1Cntl_PUEN                       1
    #define   MSK32Gbl_I2S1_DO1Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S1_DO1Cntl_SRC                        0x086C
    #define     B16Gbl_I2S1_DO1Cntl_SRC                        0x086C
    #define   LSb32Gbl_I2S1_DO1Cntl_SRC                           4
    #define   LSb16Gbl_I2S1_DO1Cntl_SRC                           4
    #define       bGbl_I2S1_DO1Cntl_SRC                        1
    #define   MSK32Gbl_I2S1_DO1Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S1_DO1Cntl_SMTC                       0x086C
    #define     B16Gbl_I2S1_DO1Cntl_SMTC                       0x086C
    #define   LSb32Gbl_I2S1_DO1Cntl_SMTC                          5
    #define   LSb16Gbl_I2S1_DO1Cntl_SMTC                          5
    #define       bGbl_I2S1_DO1Cntl_SMTC                       1
    #define   MSK32Gbl_I2S1_DO1Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_DO2Cntl                            0x0870

    #define     BA_Gbl_I2S1_DO2Cntl_DRV                        0x0870
    #define     B16Gbl_I2S1_DO2Cntl_DRV                        0x0870
    #define   LSb32Gbl_I2S1_DO2Cntl_DRV                           0
    #define   LSb16Gbl_I2S1_DO2Cntl_DRV                           0
    #define       bGbl_I2S1_DO2Cntl_DRV                        2
    #define   MSK32Gbl_I2S1_DO2Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S1_DO2Cntl_PDEN                       0x0870
    #define     B16Gbl_I2S1_DO2Cntl_PDEN                       0x0870
    #define   LSb32Gbl_I2S1_DO2Cntl_PDEN                          2
    #define   LSb16Gbl_I2S1_DO2Cntl_PDEN                          2
    #define       bGbl_I2S1_DO2Cntl_PDEN                       1
    #define   MSK32Gbl_I2S1_DO2Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S1_DO2Cntl_PUEN                       0x0870
    #define     B16Gbl_I2S1_DO2Cntl_PUEN                       0x0870
    #define   LSb32Gbl_I2S1_DO2Cntl_PUEN                          3
    #define   LSb16Gbl_I2S1_DO2Cntl_PUEN                          3
    #define       bGbl_I2S1_DO2Cntl_PUEN                       1
    #define   MSK32Gbl_I2S1_DO2Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S1_DO2Cntl_SRC                        0x0870
    #define     B16Gbl_I2S1_DO2Cntl_SRC                        0x0870
    #define   LSb32Gbl_I2S1_DO2Cntl_SRC                           4
    #define   LSb16Gbl_I2S1_DO2Cntl_SRC                           4
    #define       bGbl_I2S1_DO2Cntl_SRC                        1
    #define   MSK32Gbl_I2S1_DO2Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S1_DO2Cntl_SMTC                       0x0870
    #define     B16Gbl_I2S1_DO2Cntl_SMTC                       0x0870
    #define   LSb32Gbl_I2S1_DO2Cntl_SMTC                          5
    #define   LSb16Gbl_I2S1_DO2Cntl_SMTC                          5
    #define       bGbl_I2S1_DO2Cntl_SMTC                       1
    #define   MSK32Gbl_I2S1_DO2Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_DO3Cntl                            0x0874

    #define     BA_Gbl_I2S1_DO3Cntl_DRV                        0x0874
    #define     B16Gbl_I2S1_DO3Cntl_DRV                        0x0874
    #define   LSb32Gbl_I2S1_DO3Cntl_DRV                           0
    #define   LSb16Gbl_I2S1_DO3Cntl_DRV                           0
    #define       bGbl_I2S1_DO3Cntl_DRV                        2
    #define   MSK32Gbl_I2S1_DO3Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S1_DO3Cntl_PDEN                       0x0874
    #define     B16Gbl_I2S1_DO3Cntl_PDEN                       0x0874
    #define   LSb32Gbl_I2S1_DO3Cntl_PDEN                          2
    #define   LSb16Gbl_I2S1_DO3Cntl_PDEN                          2
    #define       bGbl_I2S1_DO3Cntl_PDEN                       1
    #define   MSK32Gbl_I2S1_DO3Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S1_DO3Cntl_PUEN                       0x0874
    #define     B16Gbl_I2S1_DO3Cntl_PUEN                       0x0874
    #define   LSb32Gbl_I2S1_DO3Cntl_PUEN                          3
    #define   LSb16Gbl_I2S1_DO3Cntl_PUEN                          3
    #define       bGbl_I2S1_DO3Cntl_PUEN                       1
    #define   MSK32Gbl_I2S1_DO3Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S1_DO3Cntl_SRC                        0x0874
    #define     B16Gbl_I2S1_DO3Cntl_SRC                        0x0874
    #define   LSb32Gbl_I2S1_DO3Cntl_SRC                           4
    #define   LSb16Gbl_I2S1_DO3Cntl_SRC                           4
    #define       bGbl_I2S1_DO3Cntl_SRC                        1
    #define   MSK32Gbl_I2S1_DO3Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S1_DO3Cntl_SMTC                       0x0874
    #define     B16Gbl_I2S1_DO3Cntl_SMTC                       0x0874
    #define   LSb32Gbl_I2S1_DO3Cntl_SMTC                          5
    #define   LSb16Gbl_I2S1_DO3Cntl_SMTC                          5
    #define       bGbl_I2S1_DO3Cntl_SMTC                       1
    #define   MSK32Gbl_I2S1_DO3Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S1_MCLKCntl                           0x0878

    #define     BA_Gbl_I2S1_MCLKCntl_DRV                       0x0878
    #define     B16Gbl_I2S1_MCLKCntl_DRV                       0x0878
    #define   LSb32Gbl_I2S1_MCLKCntl_DRV                          0
    #define   LSb16Gbl_I2S1_MCLKCntl_DRV                          0
    #define       bGbl_I2S1_MCLKCntl_DRV                       2
    #define   MSK32Gbl_I2S1_MCLKCntl_DRV                          0x00000003

    #define     BA_Gbl_I2S1_MCLKCntl_PDEN                      0x0878
    #define     B16Gbl_I2S1_MCLKCntl_PDEN                      0x0878
    #define   LSb32Gbl_I2S1_MCLKCntl_PDEN                         2
    #define   LSb16Gbl_I2S1_MCLKCntl_PDEN                         2
    #define       bGbl_I2S1_MCLKCntl_PDEN                      1
    #define   MSK32Gbl_I2S1_MCLKCntl_PDEN                         0x00000004

    #define     BA_Gbl_I2S1_MCLKCntl_PUEN                      0x0878
    #define     B16Gbl_I2S1_MCLKCntl_PUEN                      0x0878
    #define   LSb32Gbl_I2S1_MCLKCntl_PUEN                         3
    #define   LSb16Gbl_I2S1_MCLKCntl_PUEN                         3
    #define       bGbl_I2S1_MCLKCntl_PUEN                      1
    #define   MSK32Gbl_I2S1_MCLKCntl_PUEN                         0x00000008

    #define     BA_Gbl_I2S1_MCLKCntl_RXEN                      0x0878
    #define     B16Gbl_I2S1_MCLKCntl_RXEN                      0x0878
    #define   LSb32Gbl_I2S1_MCLKCntl_RXEN                         4
    #define   LSb16Gbl_I2S1_MCLKCntl_RXEN                         4
    #define       bGbl_I2S1_MCLKCntl_RXEN                      1
    #define   MSK32Gbl_I2S1_MCLKCntl_RXEN                         0x00000010

    #define     BA_Gbl_I2S1_MCLKCntl_SRC                       0x0878
    #define     B16Gbl_I2S1_MCLKCntl_SRC                       0x0878
    #define   LSb32Gbl_I2S1_MCLKCntl_SRC                          5
    #define   LSb16Gbl_I2S1_MCLKCntl_SRC                          5
    #define       bGbl_I2S1_MCLKCntl_SRC                       1
    #define   MSK32Gbl_I2S1_MCLKCntl_SRC                          0x00000020

    #define     BA_Gbl_I2S1_MCLKCntl_SMTC                      0x0878
    #define     B16Gbl_I2S1_MCLKCntl_SMTC                      0x0878
    #define   LSb32Gbl_I2S1_MCLKCntl_SMTC                         6
    #define   LSb16Gbl_I2S1_MCLKCntl_SMTC                         6
    #define       bGbl_I2S1_MCLKCntl_SMTC                      1
    #define   MSK32Gbl_I2S1_MCLKCntl_SMTC                         0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S2_BCLKIOCntl                         0x087C

    #define     BA_Gbl_I2S2_BCLKIOCntl_DRV                     0x087C
    #define     B16Gbl_I2S2_BCLKIOCntl_DRV                     0x087C
    #define   LSb32Gbl_I2S2_BCLKIOCntl_DRV                        0
    #define   LSb16Gbl_I2S2_BCLKIOCntl_DRV                        0
    #define       bGbl_I2S2_BCLKIOCntl_DRV                     2
    #define   MSK32Gbl_I2S2_BCLKIOCntl_DRV                        0x00000003

    #define     BA_Gbl_I2S2_BCLKIOCntl_PDEN                    0x087C
    #define     B16Gbl_I2S2_BCLKIOCntl_PDEN                    0x087C
    #define   LSb32Gbl_I2S2_BCLKIOCntl_PDEN                       2
    #define   LSb16Gbl_I2S2_BCLKIOCntl_PDEN                       2
    #define       bGbl_I2S2_BCLKIOCntl_PDEN                    1
    #define   MSK32Gbl_I2S2_BCLKIOCntl_PDEN                       0x00000004

    #define     BA_Gbl_I2S2_BCLKIOCntl_PUEN                    0x087C
    #define     B16Gbl_I2S2_BCLKIOCntl_PUEN                    0x087C
    #define   LSb32Gbl_I2S2_BCLKIOCntl_PUEN                       3
    #define   LSb16Gbl_I2S2_BCLKIOCntl_PUEN                       3
    #define       bGbl_I2S2_BCLKIOCntl_PUEN                    1
    #define   MSK32Gbl_I2S2_BCLKIOCntl_PUEN                       0x00000008

    #define     BA_Gbl_I2S2_BCLKIOCntl_RXEN                    0x087C
    #define     B16Gbl_I2S2_BCLKIOCntl_RXEN                    0x087C
    #define   LSb32Gbl_I2S2_BCLKIOCntl_RXEN                       4
    #define   LSb16Gbl_I2S2_BCLKIOCntl_RXEN                       4
    #define       bGbl_I2S2_BCLKIOCntl_RXEN                    1
    #define   MSK32Gbl_I2S2_BCLKIOCntl_RXEN                       0x00000010

    #define     BA_Gbl_I2S2_BCLKIOCntl_SRC                     0x087C
    #define     B16Gbl_I2S2_BCLKIOCntl_SRC                     0x087C
    #define   LSb32Gbl_I2S2_BCLKIOCntl_SRC                        5
    #define   LSb16Gbl_I2S2_BCLKIOCntl_SRC                        5
    #define       bGbl_I2S2_BCLKIOCntl_SRC                     1
    #define   MSK32Gbl_I2S2_BCLKIOCntl_SRC                        0x00000020

    #define     BA_Gbl_I2S2_BCLKIOCntl_SMTC                    0x087C
    #define     B16Gbl_I2S2_BCLKIOCntl_SMTC                    0x087C
    #define   LSb32Gbl_I2S2_BCLKIOCntl_SMTC                       6
    #define   LSb16Gbl_I2S2_BCLKIOCntl_SMTC                       6
    #define       bGbl_I2S2_BCLKIOCntl_SMTC                    1
    #define   MSK32Gbl_I2S2_BCLKIOCntl_SMTC                       0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S2_LRCKIOCntl                         0x0880

    #define     BA_Gbl_I2S2_LRCKIOCntl_DRV                     0x0880
    #define     B16Gbl_I2S2_LRCKIOCntl_DRV                     0x0880
    #define   LSb32Gbl_I2S2_LRCKIOCntl_DRV                        0
    #define   LSb16Gbl_I2S2_LRCKIOCntl_DRV                        0
    #define       bGbl_I2S2_LRCKIOCntl_DRV                     2
    #define   MSK32Gbl_I2S2_LRCKIOCntl_DRV                        0x00000003

    #define     BA_Gbl_I2S2_LRCKIOCntl_PDEN                    0x0880
    #define     B16Gbl_I2S2_LRCKIOCntl_PDEN                    0x0880
    #define   LSb32Gbl_I2S2_LRCKIOCntl_PDEN                       2
    #define   LSb16Gbl_I2S2_LRCKIOCntl_PDEN                       2
    #define       bGbl_I2S2_LRCKIOCntl_PDEN                    1
    #define   MSK32Gbl_I2S2_LRCKIOCntl_PDEN                       0x00000004

    #define     BA_Gbl_I2S2_LRCKIOCntl_PUEN                    0x0880
    #define     B16Gbl_I2S2_LRCKIOCntl_PUEN                    0x0880
    #define   LSb32Gbl_I2S2_LRCKIOCntl_PUEN                       3
    #define   LSb16Gbl_I2S2_LRCKIOCntl_PUEN                       3
    #define       bGbl_I2S2_LRCKIOCntl_PUEN                    1
    #define   MSK32Gbl_I2S2_LRCKIOCntl_PUEN                       0x00000008

    #define     BA_Gbl_I2S2_LRCKIOCntl_RXEN                    0x0880
    #define     B16Gbl_I2S2_LRCKIOCntl_RXEN                    0x0880
    #define   LSb32Gbl_I2S2_LRCKIOCntl_RXEN                       4
    #define   LSb16Gbl_I2S2_LRCKIOCntl_RXEN                       4
    #define       bGbl_I2S2_LRCKIOCntl_RXEN                    1
    #define   MSK32Gbl_I2S2_LRCKIOCntl_RXEN                       0x00000010

    #define     BA_Gbl_I2S2_LRCKIOCntl_SRC                     0x0880
    #define     B16Gbl_I2S2_LRCKIOCntl_SRC                     0x0880
    #define   LSb32Gbl_I2S2_LRCKIOCntl_SRC                        5
    #define   LSb16Gbl_I2S2_LRCKIOCntl_SRC                        5
    #define       bGbl_I2S2_LRCKIOCntl_SRC                     1
    #define   MSK32Gbl_I2S2_LRCKIOCntl_SRC                        0x00000020

    #define     BA_Gbl_I2S2_LRCKIOCntl_SMTC                    0x0880
    #define     B16Gbl_I2S2_LRCKIOCntl_SMTC                    0x0880
    #define   LSb32Gbl_I2S2_LRCKIOCntl_SMTC                       6
    #define   LSb16Gbl_I2S2_LRCKIOCntl_SMTC                       6
    #define       bGbl_I2S2_LRCKIOCntl_SMTC                    1
    #define   MSK32Gbl_I2S2_LRCKIOCntl_SMTC                       0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S2_DI0Cntl                            0x0884

    #define     BA_Gbl_I2S2_DI0Cntl_DRV                        0x0884
    #define     B16Gbl_I2S2_DI0Cntl_DRV                        0x0884
    #define   LSb32Gbl_I2S2_DI0Cntl_DRV                           0
    #define   LSb16Gbl_I2S2_DI0Cntl_DRV                           0
    #define       bGbl_I2S2_DI0Cntl_DRV                        2
    #define   MSK32Gbl_I2S2_DI0Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S2_DI0Cntl_PDEN                       0x0884
    #define     B16Gbl_I2S2_DI0Cntl_PDEN                       0x0884
    #define   LSb32Gbl_I2S2_DI0Cntl_PDEN                          2
    #define   LSb16Gbl_I2S2_DI0Cntl_PDEN                          2
    #define       bGbl_I2S2_DI0Cntl_PDEN                       1
    #define   MSK32Gbl_I2S2_DI0Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S2_DI0Cntl_PUEN                       0x0884
    #define     B16Gbl_I2S2_DI0Cntl_PUEN                       0x0884
    #define   LSb32Gbl_I2S2_DI0Cntl_PUEN                          3
    #define   LSb16Gbl_I2S2_DI0Cntl_PUEN                          3
    #define       bGbl_I2S2_DI0Cntl_PUEN                       1
    #define   MSK32Gbl_I2S2_DI0Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S2_DI0Cntl_SRC                        0x0884
    #define     B16Gbl_I2S2_DI0Cntl_SRC                        0x0884
    #define   LSb32Gbl_I2S2_DI0Cntl_SRC                           4
    #define   LSb16Gbl_I2S2_DI0Cntl_SRC                           4
    #define       bGbl_I2S2_DI0Cntl_SRC                        1
    #define   MSK32Gbl_I2S2_DI0Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S2_DI0Cntl_SMTC                       0x0884
    #define     B16Gbl_I2S2_DI0Cntl_SMTC                       0x0884
    #define   LSb32Gbl_I2S2_DI0Cntl_SMTC                          5
    #define   LSb16Gbl_I2S2_DI0Cntl_SMTC                          5
    #define       bGbl_I2S2_DI0Cntl_SMTC                       1
    #define   MSK32Gbl_I2S2_DI0Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S2_DI1Cntl                            0x0888

    #define     BA_Gbl_I2S2_DI1Cntl_DRV                        0x0888
    #define     B16Gbl_I2S2_DI1Cntl_DRV                        0x0888
    #define   LSb32Gbl_I2S2_DI1Cntl_DRV                           0
    #define   LSb16Gbl_I2S2_DI1Cntl_DRV                           0
    #define       bGbl_I2S2_DI1Cntl_DRV                        2
    #define   MSK32Gbl_I2S2_DI1Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S2_DI1Cntl_PDEN                       0x0888
    #define     B16Gbl_I2S2_DI1Cntl_PDEN                       0x0888
    #define   LSb32Gbl_I2S2_DI1Cntl_PDEN                          2
    #define   LSb16Gbl_I2S2_DI1Cntl_PDEN                          2
    #define       bGbl_I2S2_DI1Cntl_PDEN                       1
    #define   MSK32Gbl_I2S2_DI1Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S2_DI1Cntl_PUEN                       0x0888
    #define     B16Gbl_I2S2_DI1Cntl_PUEN                       0x0888
    #define   LSb32Gbl_I2S2_DI1Cntl_PUEN                          3
    #define   LSb16Gbl_I2S2_DI1Cntl_PUEN                          3
    #define       bGbl_I2S2_DI1Cntl_PUEN                       1
    #define   MSK32Gbl_I2S2_DI1Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S2_DI1Cntl_SRC                        0x0888
    #define     B16Gbl_I2S2_DI1Cntl_SRC                        0x0888
    #define   LSb32Gbl_I2S2_DI1Cntl_SRC                           4
    #define   LSb16Gbl_I2S2_DI1Cntl_SRC                           4
    #define       bGbl_I2S2_DI1Cntl_SRC                        1
    #define   MSK32Gbl_I2S2_DI1Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S2_DI1Cntl_SMTC                       0x0888
    #define     B16Gbl_I2S2_DI1Cntl_SMTC                       0x0888
    #define   LSb32Gbl_I2S2_DI1Cntl_SMTC                          5
    #define   LSb16Gbl_I2S2_DI1Cntl_SMTC                          5
    #define       bGbl_I2S2_DI1Cntl_SMTC                       1
    #define   MSK32Gbl_I2S2_DI1Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S2_DI2Cntl                            0x088C

    #define     BA_Gbl_I2S2_DI2Cntl_DRV                        0x088C
    #define     B16Gbl_I2S2_DI2Cntl_DRV                        0x088C
    #define   LSb32Gbl_I2S2_DI2Cntl_DRV                           0
    #define   LSb16Gbl_I2S2_DI2Cntl_DRV                           0
    #define       bGbl_I2S2_DI2Cntl_DRV                        2
    #define   MSK32Gbl_I2S2_DI2Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S2_DI2Cntl_PDEN                       0x088C
    #define     B16Gbl_I2S2_DI2Cntl_PDEN                       0x088C
    #define   LSb32Gbl_I2S2_DI2Cntl_PDEN                          2
    #define   LSb16Gbl_I2S2_DI2Cntl_PDEN                          2
    #define       bGbl_I2S2_DI2Cntl_PDEN                       1
    #define   MSK32Gbl_I2S2_DI2Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S2_DI2Cntl_PUEN                       0x088C
    #define     B16Gbl_I2S2_DI2Cntl_PUEN                       0x088C
    #define   LSb32Gbl_I2S2_DI2Cntl_PUEN                          3
    #define   LSb16Gbl_I2S2_DI2Cntl_PUEN                          3
    #define       bGbl_I2S2_DI2Cntl_PUEN                       1
    #define   MSK32Gbl_I2S2_DI2Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S2_DI2Cntl_SRC                        0x088C
    #define     B16Gbl_I2S2_DI2Cntl_SRC                        0x088C
    #define   LSb32Gbl_I2S2_DI2Cntl_SRC                           4
    #define   LSb16Gbl_I2S2_DI2Cntl_SRC                           4
    #define       bGbl_I2S2_DI2Cntl_SRC                        1
    #define   MSK32Gbl_I2S2_DI2Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S2_DI2Cntl_SMTC                       0x088C
    #define     B16Gbl_I2S2_DI2Cntl_SMTC                       0x088C
    #define   LSb32Gbl_I2S2_DI2Cntl_SMTC                          5
    #define   LSb16Gbl_I2S2_DI2Cntl_SMTC                          5
    #define       bGbl_I2S2_DI2Cntl_SMTC                       1
    #define   MSK32Gbl_I2S2_DI2Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S2_DI3Cntl                            0x0890

    #define     BA_Gbl_I2S2_DI3Cntl_DRV                        0x0890
    #define     B16Gbl_I2S2_DI3Cntl_DRV                        0x0890
    #define   LSb32Gbl_I2S2_DI3Cntl_DRV                           0
    #define   LSb16Gbl_I2S2_DI3Cntl_DRV                           0
    #define       bGbl_I2S2_DI3Cntl_DRV                        2
    #define   MSK32Gbl_I2S2_DI3Cntl_DRV                           0x00000003

    #define     BA_Gbl_I2S2_DI3Cntl_PDEN                       0x0890
    #define     B16Gbl_I2S2_DI3Cntl_PDEN                       0x0890
    #define   LSb32Gbl_I2S2_DI3Cntl_PDEN                          2
    #define   LSb16Gbl_I2S2_DI3Cntl_PDEN                          2
    #define       bGbl_I2S2_DI3Cntl_PDEN                       1
    #define   MSK32Gbl_I2S2_DI3Cntl_PDEN                          0x00000004

    #define     BA_Gbl_I2S2_DI3Cntl_PUEN                       0x0890
    #define     B16Gbl_I2S2_DI3Cntl_PUEN                       0x0890
    #define   LSb32Gbl_I2S2_DI3Cntl_PUEN                          3
    #define   LSb16Gbl_I2S2_DI3Cntl_PUEN                          3
    #define       bGbl_I2S2_DI3Cntl_PUEN                       1
    #define   MSK32Gbl_I2S2_DI3Cntl_PUEN                          0x00000008

    #define     BA_Gbl_I2S2_DI3Cntl_SRC                        0x0890
    #define     B16Gbl_I2S2_DI3Cntl_SRC                        0x0890
    #define   LSb32Gbl_I2S2_DI3Cntl_SRC                           4
    #define   LSb16Gbl_I2S2_DI3Cntl_SRC                           4
    #define       bGbl_I2S2_DI3Cntl_SRC                        1
    #define   MSK32Gbl_I2S2_DI3Cntl_SRC                           0x00000010

    #define     BA_Gbl_I2S2_DI3Cntl_SMTC                       0x0890
    #define     B16Gbl_I2S2_DI3Cntl_SMTC                       0x0890
    #define   LSb32Gbl_I2S2_DI3Cntl_SMTC                          5
    #define   LSb16Gbl_I2S2_DI3Cntl_SMTC                          5
    #define       bGbl_I2S2_DI3Cntl_SMTC                       1
    #define   MSK32Gbl_I2S2_DI3Cntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PDM_CLKOCntl                            0x0894

    #define     BA_Gbl_PDM_CLKOCntl_DRV                        0x0894
    #define     B16Gbl_PDM_CLKOCntl_DRV                        0x0894
    #define   LSb32Gbl_PDM_CLKOCntl_DRV                           0
    #define   LSb16Gbl_PDM_CLKOCntl_DRV                           0
    #define       bGbl_PDM_CLKOCntl_DRV                        2
    #define   MSK32Gbl_PDM_CLKOCntl_DRV                           0x00000003

    #define     BA_Gbl_PDM_CLKOCntl_PDEN                       0x0894
    #define     B16Gbl_PDM_CLKOCntl_PDEN                       0x0894
    #define   LSb32Gbl_PDM_CLKOCntl_PDEN                          2
    #define   LSb16Gbl_PDM_CLKOCntl_PDEN                          2
    #define       bGbl_PDM_CLKOCntl_PDEN                       1
    #define   MSK32Gbl_PDM_CLKOCntl_PDEN                          0x00000004

    #define     BA_Gbl_PDM_CLKOCntl_PUEN                       0x0894
    #define     B16Gbl_PDM_CLKOCntl_PUEN                       0x0894
    #define   LSb32Gbl_PDM_CLKOCntl_PUEN                          3
    #define   LSb16Gbl_PDM_CLKOCntl_PUEN                          3
    #define       bGbl_PDM_CLKOCntl_PUEN                       1
    #define   MSK32Gbl_PDM_CLKOCntl_PUEN                          0x00000008

    #define     BA_Gbl_PDM_CLKOCntl_SRC                        0x0894
    #define     B16Gbl_PDM_CLKOCntl_SRC                        0x0894
    #define   LSb32Gbl_PDM_CLKOCntl_SRC                           4
    #define   LSb16Gbl_PDM_CLKOCntl_SRC                           4
    #define       bGbl_PDM_CLKOCntl_SRC                        1
    #define   MSK32Gbl_PDM_CLKOCntl_SRC                           0x00000010

    #define     BA_Gbl_PDM_CLKOCntl_SMTC                       0x0894
    #define     B16Gbl_PDM_CLKOCntl_SMTC                       0x0894
    #define   LSb32Gbl_PDM_CLKOCntl_SMTC                          5
    #define   LSb16Gbl_PDM_CLKOCntl_SMTC                          5
    #define       bGbl_PDM_CLKOCntl_SMTC                       1
    #define   MSK32Gbl_PDM_CLKOCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PDM_DI0Cntl                             0x0898

    #define     BA_Gbl_PDM_DI0Cntl_DRV                         0x0898
    #define     B16Gbl_PDM_DI0Cntl_DRV                         0x0898
    #define   LSb32Gbl_PDM_DI0Cntl_DRV                            0
    #define   LSb16Gbl_PDM_DI0Cntl_DRV                            0
    #define       bGbl_PDM_DI0Cntl_DRV                         2
    #define   MSK32Gbl_PDM_DI0Cntl_DRV                            0x00000003

    #define     BA_Gbl_PDM_DI0Cntl_PDEN                        0x0898
    #define     B16Gbl_PDM_DI0Cntl_PDEN                        0x0898
    #define   LSb32Gbl_PDM_DI0Cntl_PDEN                           2
    #define   LSb16Gbl_PDM_DI0Cntl_PDEN                           2
    #define       bGbl_PDM_DI0Cntl_PDEN                        1
    #define   MSK32Gbl_PDM_DI0Cntl_PDEN                           0x00000004

    #define     BA_Gbl_PDM_DI0Cntl_PUEN                        0x0898
    #define     B16Gbl_PDM_DI0Cntl_PUEN                        0x0898
    #define   LSb32Gbl_PDM_DI0Cntl_PUEN                           3
    #define   LSb16Gbl_PDM_DI0Cntl_PUEN                           3
    #define       bGbl_PDM_DI0Cntl_PUEN                        1
    #define   MSK32Gbl_PDM_DI0Cntl_PUEN                           0x00000008

    #define     BA_Gbl_PDM_DI0Cntl_SRC                         0x0898
    #define     B16Gbl_PDM_DI0Cntl_SRC                         0x0898
    #define   LSb32Gbl_PDM_DI0Cntl_SRC                            4
    #define   LSb16Gbl_PDM_DI0Cntl_SRC                            4
    #define       bGbl_PDM_DI0Cntl_SRC                         1
    #define   MSK32Gbl_PDM_DI0Cntl_SRC                            0x00000010

    #define     BA_Gbl_PDM_DI0Cntl_SMTC                        0x0898
    #define     B16Gbl_PDM_DI0Cntl_SMTC                        0x0898
    #define   LSb32Gbl_PDM_DI0Cntl_SMTC                           5
    #define   LSb16Gbl_PDM_DI0Cntl_SMTC                           5
    #define       bGbl_PDM_DI0Cntl_SMTC                        1
    #define   MSK32Gbl_PDM_DI0Cntl_SMTC                           0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PDM_DI1Cntl                             0x089C

    #define     BA_Gbl_PDM_DI1Cntl_DRV                         0x089C
    #define     B16Gbl_PDM_DI1Cntl_DRV                         0x089C
    #define   LSb32Gbl_PDM_DI1Cntl_DRV                            0
    #define   LSb16Gbl_PDM_DI1Cntl_DRV                            0
    #define       bGbl_PDM_DI1Cntl_DRV                         2
    #define   MSK32Gbl_PDM_DI1Cntl_DRV                            0x00000003

    #define     BA_Gbl_PDM_DI1Cntl_PDEN                        0x089C
    #define     B16Gbl_PDM_DI1Cntl_PDEN                        0x089C
    #define   LSb32Gbl_PDM_DI1Cntl_PDEN                           2
    #define   LSb16Gbl_PDM_DI1Cntl_PDEN                           2
    #define       bGbl_PDM_DI1Cntl_PDEN                        1
    #define   MSK32Gbl_PDM_DI1Cntl_PDEN                           0x00000004

    #define     BA_Gbl_PDM_DI1Cntl_PUEN                        0x089C
    #define     B16Gbl_PDM_DI1Cntl_PUEN                        0x089C
    #define   LSb32Gbl_PDM_DI1Cntl_PUEN                           3
    #define   LSb16Gbl_PDM_DI1Cntl_PUEN                           3
    #define       bGbl_PDM_DI1Cntl_PUEN                        1
    #define   MSK32Gbl_PDM_DI1Cntl_PUEN                           0x00000008

    #define     BA_Gbl_PDM_DI1Cntl_SRC                         0x089C
    #define     B16Gbl_PDM_DI1Cntl_SRC                         0x089C
    #define   LSb32Gbl_PDM_DI1Cntl_SRC                            4
    #define   LSb16Gbl_PDM_DI1Cntl_SRC                            4
    #define       bGbl_PDM_DI1Cntl_SRC                         1
    #define   MSK32Gbl_PDM_DI1Cntl_SRC                            0x00000010

    #define     BA_Gbl_PDM_DI1Cntl_SMTC                        0x089C
    #define     B16Gbl_PDM_DI1Cntl_SMTC                        0x089C
    #define   LSb32Gbl_PDM_DI1Cntl_SMTC                           5
    #define   LSb16Gbl_PDM_DI1Cntl_SMTC                           5
    #define       bGbl_PDM_DI1Cntl_SMTC                        1
    #define   MSK32Gbl_PDM_DI1Cntl_SMTC                           0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PDM_DI2Cntl                             0x08A0

    #define     BA_Gbl_PDM_DI2Cntl_DRV                         0x08A0
    #define     B16Gbl_PDM_DI2Cntl_DRV                         0x08A0
    #define   LSb32Gbl_PDM_DI2Cntl_DRV                            0
    #define   LSb16Gbl_PDM_DI2Cntl_DRV                            0
    #define       bGbl_PDM_DI2Cntl_DRV                         2
    #define   MSK32Gbl_PDM_DI2Cntl_DRV                            0x00000003

    #define     BA_Gbl_PDM_DI2Cntl_PDEN                        0x08A0
    #define     B16Gbl_PDM_DI2Cntl_PDEN                        0x08A0
    #define   LSb32Gbl_PDM_DI2Cntl_PDEN                           2
    #define   LSb16Gbl_PDM_DI2Cntl_PDEN                           2
    #define       bGbl_PDM_DI2Cntl_PDEN                        1
    #define   MSK32Gbl_PDM_DI2Cntl_PDEN                           0x00000004

    #define     BA_Gbl_PDM_DI2Cntl_PUEN                        0x08A0
    #define     B16Gbl_PDM_DI2Cntl_PUEN                        0x08A0
    #define   LSb32Gbl_PDM_DI2Cntl_PUEN                           3
    #define   LSb16Gbl_PDM_DI2Cntl_PUEN                           3
    #define       bGbl_PDM_DI2Cntl_PUEN                        1
    #define   MSK32Gbl_PDM_DI2Cntl_PUEN                           0x00000008

    #define     BA_Gbl_PDM_DI2Cntl_SRC                         0x08A0
    #define     B16Gbl_PDM_DI2Cntl_SRC                         0x08A0
    #define   LSb32Gbl_PDM_DI2Cntl_SRC                            4
    #define   LSb16Gbl_PDM_DI2Cntl_SRC                            4
    #define       bGbl_PDM_DI2Cntl_SRC                         1
    #define   MSK32Gbl_PDM_DI2Cntl_SRC                            0x00000010

    #define     BA_Gbl_PDM_DI2Cntl_SMTC                        0x08A0
    #define     B16Gbl_PDM_DI2Cntl_SMTC                        0x08A0
    #define   LSb32Gbl_PDM_DI2Cntl_SMTC                           5
    #define   LSb16Gbl_PDM_DI2Cntl_SMTC                           5
    #define       bGbl_PDM_DI2Cntl_SMTC                        1
    #define   MSK32Gbl_PDM_DI2Cntl_SMTC                           0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PDM_DI3Cntl                             0x08A4

    #define     BA_Gbl_PDM_DI3Cntl_DRV                         0x08A4
    #define     B16Gbl_PDM_DI3Cntl_DRV                         0x08A4
    #define   LSb32Gbl_PDM_DI3Cntl_DRV                            0
    #define   LSb16Gbl_PDM_DI3Cntl_DRV                            0
    #define       bGbl_PDM_DI3Cntl_DRV                         2
    #define   MSK32Gbl_PDM_DI3Cntl_DRV                            0x00000003

    #define     BA_Gbl_PDM_DI3Cntl_PDEN                        0x08A4
    #define     B16Gbl_PDM_DI3Cntl_PDEN                        0x08A4
    #define   LSb32Gbl_PDM_DI3Cntl_PDEN                           2
    #define   LSb16Gbl_PDM_DI3Cntl_PDEN                           2
    #define       bGbl_PDM_DI3Cntl_PDEN                        1
    #define   MSK32Gbl_PDM_DI3Cntl_PDEN                           0x00000004

    #define     BA_Gbl_PDM_DI3Cntl_PUEN                        0x08A4
    #define     B16Gbl_PDM_DI3Cntl_PUEN                        0x08A4
    #define   LSb32Gbl_PDM_DI3Cntl_PUEN                           3
    #define   LSb16Gbl_PDM_DI3Cntl_PUEN                           3
    #define       bGbl_PDM_DI3Cntl_PUEN                        1
    #define   MSK32Gbl_PDM_DI3Cntl_PUEN                           0x00000008

    #define     BA_Gbl_PDM_DI3Cntl_SRC                         0x08A4
    #define     B16Gbl_PDM_DI3Cntl_SRC                         0x08A4
    #define   LSb32Gbl_PDM_DI3Cntl_SRC                            4
    #define   LSb16Gbl_PDM_DI3Cntl_SRC                            4
    #define       bGbl_PDM_DI3Cntl_SRC                         1
    #define   MSK32Gbl_PDM_DI3Cntl_SRC                            0x00000010

    #define     BA_Gbl_PDM_DI3Cntl_SMTC                        0x08A4
    #define     B16Gbl_PDM_DI3Cntl_SMTC                        0x08A4
    #define   LSb32Gbl_PDM_DI3Cntl_SMTC                           5
    #define   LSb16Gbl_PDM_DI3Cntl_SMTC                           5
    #define       bGbl_PDM_DI3Cntl_SMTC                        1
    #define   MSK32Gbl_PDM_DI3Cntl_SMTC                           0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO0Cntl                            0x08A8

    #define     BA_Gbl_NAND_IO0Cntl_DRV                        0x08A8
    #define     B16Gbl_NAND_IO0Cntl_DRV                        0x08A8
    #define   LSb32Gbl_NAND_IO0Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO0Cntl_DRV                           0
    #define       bGbl_NAND_IO0Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO0Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO0Cntl_PDEN                       0x08A8
    #define     B16Gbl_NAND_IO0Cntl_PDEN                       0x08A8
    #define   LSb32Gbl_NAND_IO0Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO0Cntl_PDEN                          2
    #define       bGbl_NAND_IO0Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO0Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO0Cntl_PUEN                       0x08A8
    #define     B16Gbl_NAND_IO0Cntl_PUEN                       0x08A8
    #define   LSb32Gbl_NAND_IO0Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO0Cntl_PUEN                          3
    #define       bGbl_NAND_IO0Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO0Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO0Cntl_RXEN                       0x08A8
    #define     B16Gbl_NAND_IO0Cntl_RXEN                       0x08A8
    #define   LSb32Gbl_NAND_IO0Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO0Cntl_RXEN                          4
    #define       bGbl_NAND_IO0Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO0Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO0Cntl_SRC                        0x08A8
    #define     B16Gbl_NAND_IO0Cntl_SRC                        0x08A8
    #define   LSb32Gbl_NAND_IO0Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO0Cntl_SRC                           5
    #define       bGbl_NAND_IO0Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO0Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO0Cntl_SMTC                       0x08A8
    #define     B16Gbl_NAND_IO0Cntl_SMTC                       0x08A8
    #define   LSb32Gbl_NAND_IO0Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO0Cntl_SMTC                          6
    #define       bGbl_NAND_IO0Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO0Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO1Cntl                            0x08AC

    #define     BA_Gbl_NAND_IO1Cntl_DRV                        0x08AC
    #define     B16Gbl_NAND_IO1Cntl_DRV                        0x08AC
    #define   LSb32Gbl_NAND_IO1Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO1Cntl_DRV                           0
    #define       bGbl_NAND_IO1Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO1Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO1Cntl_PDEN                       0x08AC
    #define     B16Gbl_NAND_IO1Cntl_PDEN                       0x08AC
    #define   LSb32Gbl_NAND_IO1Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO1Cntl_PDEN                          2
    #define       bGbl_NAND_IO1Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO1Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO1Cntl_PUEN                       0x08AC
    #define     B16Gbl_NAND_IO1Cntl_PUEN                       0x08AC
    #define   LSb32Gbl_NAND_IO1Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO1Cntl_PUEN                          3
    #define       bGbl_NAND_IO1Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO1Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO1Cntl_RXEN                       0x08AC
    #define     B16Gbl_NAND_IO1Cntl_RXEN                       0x08AC
    #define   LSb32Gbl_NAND_IO1Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO1Cntl_RXEN                          4
    #define       bGbl_NAND_IO1Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO1Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO1Cntl_SRC                        0x08AC
    #define     B16Gbl_NAND_IO1Cntl_SRC                        0x08AC
    #define   LSb32Gbl_NAND_IO1Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO1Cntl_SRC                           5
    #define       bGbl_NAND_IO1Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO1Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO1Cntl_SMTC                       0x08AC
    #define     B16Gbl_NAND_IO1Cntl_SMTC                       0x08AC
    #define   LSb32Gbl_NAND_IO1Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO1Cntl_SMTC                          6
    #define       bGbl_NAND_IO1Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO1Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO2Cntl                            0x08B0

    #define     BA_Gbl_NAND_IO2Cntl_DRV                        0x08B0
    #define     B16Gbl_NAND_IO2Cntl_DRV                        0x08B0
    #define   LSb32Gbl_NAND_IO2Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO2Cntl_DRV                           0
    #define       bGbl_NAND_IO2Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO2Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO2Cntl_PDEN                       0x08B0
    #define     B16Gbl_NAND_IO2Cntl_PDEN                       0x08B0
    #define   LSb32Gbl_NAND_IO2Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO2Cntl_PDEN                          2
    #define       bGbl_NAND_IO2Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO2Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO2Cntl_PUEN                       0x08B0
    #define     B16Gbl_NAND_IO2Cntl_PUEN                       0x08B0
    #define   LSb32Gbl_NAND_IO2Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO2Cntl_PUEN                          3
    #define       bGbl_NAND_IO2Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO2Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO2Cntl_RXEN                       0x08B0
    #define     B16Gbl_NAND_IO2Cntl_RXEN                       0x08B0
    #define   LSb32Gbl_NAND_IO2Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO2Cntl_RXEN                          4
    #define       bGbl_NAND_IO2Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO2Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO2Cntl_SRC                        0x08B0
    #define     B16Gbl_NAND_IO2Cntl_SRC                        0x08B0
    #define   LSb32Gbl_NAND_IO2Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO2Cntl_SRC                           5
    #define       bGbl_NAND_IO2Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO2Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO2Cntl_SMTC                       0x08B0
    #define     B16Gbl_NAND_IO2Cntl_SMTC                       0x08B0
    #define   LSb32Gbl_NAND_IO2Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO2Cntl_SMTC                          6
    #define       bGbl_NAND_IO2Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO2Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO3Cntl                            0x08B4

    #define     BA_Gbl_NAND_IO3Cntl_DRV                        0x08B4
    #define     B16Gbl_NAND_IO3Cntl_DRV                        0x08B4
    #define   LSb32Gbl_NAND_IO3Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO3Cntl_DRV                           0
    #define       bGbl_NAND_IO3Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO3Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO3Cntl_PDEN                       0x08B4
    #define     B16Gbl_NAND_IO3Cntl_PDEN                       0x08B4
    #define   LSb32Gbl_NAND_IO3Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO3Cntl_PDEN                          2
    #define       bGbl_NAND_IO3Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO3Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO3Cntl_PUEN                       0x08B4
    #define     B16Gbl_NAND_IO3Cntl_PUEN                       0x08B4
    #define   LSb32Gbl_NAND_IO3Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO3Cntl_PUEN                          3
    #define       bGbl_NAND_IO3Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO3Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO3Cntl_RXEN                       0x08B4
    #define     B16Gbl_NAND_IO3Cntl_RXEN                       0x08B4
    #define   LSb32Gbl_NAND_IO3Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO3Cntl_RXEN                          4
    #define       bGbl_NAND_IO3Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO3Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO3Cntl_SRC                        0x08B4
    #define     B16Gbl_NAND_IO3Cntl_SRC                        0x08B4
    #define   LSb32Gbl_NAND_IO3Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO3Cntl_SRC                           5
    #define       bGbl_NAND_IO3Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO3Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO3Cntl_SMTC                       0x08B4
    #define     B16Gbl_NAND_IO3Cntl_SMTC                       0x08B4
    #define   LSb32Gbl_NAND_IO3Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO3Cntl_SMTC                          6
    #define       bGbl_NAND_IO3Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO3Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO4Cntl                            0x08B8

    #define     BA_Gbl_NAND_IO4Cntl_DRV                        0x08B8
    #define     B16Gbl_NAND_IO4Cntl_DRV                        0x08B8
    #define   LSb32Gbl_NAND_IO4Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO4Cntl_DRV                           0
    #define       bGbl_NAND_IO4Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO4Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO4Cntl_PDEN                       0x08B8
    #define     B16Gbl_NAND_IO4Cntl_PDEN                       0x08B8
    #define   LSb32Gbl_NAND_IO4Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO4Cntl_PDEN                          2
    #define       bGbl_NAND_IO4Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO4Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO4Cntl_PUEN                       0x08B8
    #define     B16Gbl_NAND_IO4Cntl_PUEN                       0x08B8
    #define   LSb32Gbl_NAND_IO4Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO4Cntl_PUEN                          3
    #define       bGbl_NAND_IO4Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO4Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO4Cntl_RXEN                       0x08B8
    #define     B16Gbl_NAND_IO4Cntl_RXEN                       0x08B8
    #define   LSb32Gbl_NAND_IO4Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO4Cntl_RXEN                          4
    #define       bGbl_NAND_IO4Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO4Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO4Cntl_SRC                        0x08B8
    #define     B16Gbl_NAND_IO4Cntl_SRC                        0x08B8
    #define   LSb32Gbl_NAND_IO4Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO4Cntl_SRC                           5
    #define       bGbl_NAND_IO4Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO4Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO4Cntl_SMTC                       0x08B8
    #define     B16Gbl_NAND_IO4Cntl_SMTC                       0x08B8
    #define   LSb32Gbl_NAND_IO4Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO4Cntl_SMTC                          6
    #define       bGbl_NAND_IO4Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO4Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO5Cntl                            0x08BC

    #define     BA_Gbl_NAND_IO5Cntl_DRV                        0x08BC
    #define     B16Gbl_NAND_IO5Cntl_DRV                        0x08BC
    #define   LSb32Gbl_NAND_IO5Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO5Cntl_DRV                           0
    #define       bGbl_NAND_IO5Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO5Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO5Cntl_PDEN                       0x08BC
    #define     B16Gbl_NAND_IO5Cntl_PDEN                       0x08BC
    #define   LSb32Gbl_NAND_IO5Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO5Cntl_PDEN                          2
    #define       bGbl_NAND_IO5Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO5Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO5Cntl_PUEN                       0x08BC
    #define     B16Gbl_NAND_IO5Cntl_PUEN                       0x08BC
    #define   LSb32Gbl_NAND_IO5Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO5Cntl_PUEN                          3
    #define       bGbl_NAND_IO5Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO5Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO5Cntl_RXEN                       0x08BC
    #define     B16Gbl_NAND_IO5Cntl_RXEN                       0x08BC
    #define   LSb32Gbl_NAND_IO5Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO5Cntl_RXEN                          4
    #define       bGbl_NAND_IO5Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO5Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO5Cntl_SRC                        0x08BC
    #define     B16Gbl_NAND_IO5Cntl_SRC                        0x08BC
    #define   LSb32Gbl_NAND_IO5Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO5Cntl_SRC                           5
    #define       bGbl_NAND_IO5Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO5Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO5Cntl_SMTC                       0x08BC
    #define     B16Gbl_NAND_IO5Cntl_SMTC                       0x08BC
    #define   LSb32Gbl_NAND_IO5Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO5Cntl_SMTC                          6
    #define       bGbl_NAND_IO5Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO5Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO6Cntl                            0x08C0

    #define     BA_Gbl_NAND_IO6Cntl_DRV                        0x08C0
    #define     B16Gbl_NAND_IO6Cntl_DRV                        0x08C0
    #define   LSb32Gbl_NAND_IO6Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO6Cntl_DRV                           0
    #define       bGbl_NAND_IO6Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO6Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO6Cntl_PDEN                       0x08C0
    #define     B16Gbl_NAND_IO6Cntl_PDEN                       0x08C0
    #define   LSb32Gbl_NAND_IO6Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO6Cntl_PDEN                          2
    #define       bGbl_NAND_IO6Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO6Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO6Cntl_PUEN                       0x08C0
    #define     B16Gbl_NAND_IO6Cntl_PUEN                       0x08C0
    #define   LSb32Gbl_NAND_IO6Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO6Cntl_PUEN                          3
    #define       bGbl_NAND_IO6Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO6Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO6Cntl_RXEN                       0x08C0
    #define     B16Gbl_NAND_IO6Cntl_RXEN                       0x08C0
    #define   LSb32Gbl_NAND_IO6Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO6Cntl_RXEN                          4
    #define       bGbl_NAND_IO6Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO6Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO6Cntl_SRC                        0x08C0
    #define     B16Gbl_NAND_IO6Cntl_SRC                        0x08C0
    #define   LSb32Gbl_NAND_IO6Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO6Cntl_SRC                           5
    #define       bGbl_NAND_IO6Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO6Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO6Cntl_SMTC                       0x08C0
    #define     B16Gbl_NAND_IO6Cntl_SMTC                       0x08C0
    #define   LSb32Gbl_NAND_IO6Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO6Cntl_SMTC                          6
    #define       bGbl_NAND_IO6Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO6Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_IO7Cntl                            0x08C4

    #define     BA_Gbl_NAND_IO7Cntl_DRV                        0x08C4
    #define     B16Gbl_NAND_IO7Cntl_DRV                        0x08C4
    #define   LSb32Gbl_NAND_IO7Cntl_DRV                           0
    #define   LSb16Gbl_NAND_IO7Cntl_DRV                           0
    #define       bGbl_NAND_IO7Cntl_DRV                        2
    #define   MSK32Gbl_NAND_IO7Cntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_IO7Cntl_PDEN                       0x08C4
    #define     B16Gbl_NAND_IO7Cntl_PDEN                       0x08C4
    #define   LSb32Gbl_NAND_IO7Cntl_PDEN                          2
    #define   LSb16Gbl_NAND_IO7Cntl_PDEN                          2
    #define       bGbl_NAND_IO7Cntl_PDEN                       1
    #define   MSK32Gbl_NAND_IO7Cntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_IO7Cntl_PUEN                       0x08C4
    #define     B16Gbl_NAND_IO7Cntl_PUEN                       0x08C4
    #define   LSb32Gbl_NAND_IO7Cntl_PUEN                          3
    #define   LSb16Gbl_NAND_IO7Cntl_PUEN                          3
    #define       bGbl_NAND_IO7Cntl_PUEN                       1
    #define   MSK32Gbl_NAND_IO7Cntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_IO7Cntl_RXEN                       0x08C4
    #define     B16Gbl_NAND_IO7Cntl_RXEN                       0x08C4
    #define   LSb32Gbl_NAND_IO7Cntl_RXEN                          4
    #define   LSb16Gbl_NAND_IO7Cntl_RXEN                          4
    #define       bGbl_NAND_IO7Cntl_RXEN                       1
    #define   MSK32Gbl_NAND_IO7Cntl_RXEN                          0x00000010

    #define     BA_Gbl_NAND_IO7Cntl_SRC                        0x08C4
    #define     B16Gbl_NAND_IO7Cntl_SRC                        0x08C4
    #define   LSb32Gbl_NAND_IO7Cntl_SRC                           5
    #define   LSb16Gbl_NAND_IO7Cntl_SRC                           5
    #define       bGbl_NAND_IO7Cntl_SRC                        1
    #define   MSK32Gbl_NAND_IO7Cntl_SRC                           0x00000020

    #define     BA_Gbl_NAND_IO7Cntl_SMTC                       0x08C4
    #define     B16Gbl_NAND_IO7Cntl_SMTC                       0x08C4
    #define   LSb32Gbl_NAND_IO7Cntl_SMTC                          6
    #define   LSb16Gbl_NAND_IO7Cntl_SMTC                          6
    #define       bGbl_NAND_IO7Cntl_SMTC                       1
    #define   MSK32Gbl_NAND_IO7Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_ALECntl                            0x08C8

    #define     BA_Gbl_NAND_ALECntl_DRV                        0x08C8
    #define     B16Gbl_NAND_ALECntl_DRV                        0x08C8
    #define   LSb32Gbl_NAND_ALECntl_DRV                           0
    #define   LSb16Gbl_NAND_ALECntl_DRV                           0
    #define       bGbl_NAND_ALECntl_DRV                        2
    #define   MSK32Gbl_NAND_ALECntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_ALECntl_PDEN                       0x08C8
    #define     B16Gbl_NAND_ALECntl_PDEN                       0x08C8
    #define   LSb32Gbl_NAND_ALECntl_PDEN                          2
    #define   LSb16Gbl_NAND_ALECntl_PDEN                          2
    #define       bGbl_NAND_ALECntl_PDEN                       1
    #define   MSK32Gbl_NAND_ALECntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_ALECntl_PUEN                       0x08C8
    #define     B16Gbl_NAND_ALECntl_PUEN                       0x08C8
    #define   LSb32Gbl_NAND_ALECntl_PUEN                          3
    #define   LSb16Gbl_NAND_ALECntl_PUEN                          3
    #define       bGbl_NAND_ALECntl_PUEN                       1
    #define   MSK32Gbl_NAND_ALECntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_ALECntl_SRC                        0x08C8
    #define     B16Gbl_NAND_ALECntl_SRC                        0x08C8
    #define   LSb32Gbl_NAND_ALECntl_SRC                           4
    #define   LSb16Gbl_NAND_ALECntl_SRC                           4
    #define       bGbl_NAND_ALECntl_SRC                        1
    #define   MSK32Gbl_NAND_ALECntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_ALECntl_SMTC                       0x08C8
    #define     B16Gbl_NAND_ALECntl_SMTC                       0x08C8
    #define   LSb32Gbl_NAND_ALECntl_SMTC                          5
    #define   LSb16Gbl_NAND_ALECntl_SMTC                          5
    #define       bGbl_NAND_ALECntl_SMTC                       1
    #define   MSK32Gbl_NAND_ALECntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_CLECntl                            0x08CC

    #define     BA_Gbl_NAND_CLECntl_DRV                        0x08CC
    #define     B16Gbl_NAND_CLECntl_DRV                        0x08CC
    #define   LSb32Gbl_NAND_CLECntl_DRV                           0
    #define   LSb16Gbl_NAND_CLECntl_DRV                           0
    #define       bGbl_NAND_CLECntl_DRV                        2
    #define   MSK32Gbl_NAND_CLECntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_CLECntl_PDEN                       0x08CC
    #define     B16Gbl_NAND_CLECntl_PDEN                       0x08CC
    #define   LSb32Gbl_NAND_CLECntl_PDEN                          2
    #define   LSb16Gbl_NAND_CLECntl_PDEN                          2
    #define       bGbl_NAND_CLECntl_PDEN                       1
    #define   MSK32Gbl_NAND_CLECntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_CLECntl_PUEN                       0x08CC
    #define     B16Gbl_NAND_CLECntl_PUEN                       0x08CC
    #define   LSb32Gbl_NAND_CLECntl_PUEN                          3
    #define   LSb16Gbl_NAND_CLECntl_PUEN                          3
    #define       bGbl_NAND_CLECntl_PUEN                       1
    #define   MSK32Gbl_NAND_CLECntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_CLECntl_SRC                        0x08CC
    #define     B16Gbl_NAND_CLECntl_SRC                        0x08CC
    #define   LSb32Gbl_NAND_CLECntl_SRC                           4
    #define   LSb16Gbl_NAND_CLECntl_SRC                           4
    #define       bGbl_NAND_CLECntl_SRC                        1
    #define   MSK32Gbl_NAND_CLECntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_CLECntl_SMTC                       0x08CC
    #define     B16Gbl_NAND_CLECntl_SMTC                       0x08CC
    #define   LSb32Gbl_NAND_CLECntl_SMTC                          5
    #define   LSb16Gbl_NAND_CLECntl_SMTC                          5
    #define       bGbl_NAND_CLECntl_SMTC                       1
    #define   MSK32Gbl_NAND_CLECntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_WEnCntl                            0x08D0

    #define     BA_Gbl_NAND_WEnCntl_DRV                        0x08D0
    #define     B16Gbl_NAND_WEnCntl_DRV                        0x08D0
    #define   LSb32Gbl_NAND_WEnCntl_DRV                           0
    #define   LSb16Gbl_NAND_WEnCntl_DRV                           0
    #define       bGbl_NAND_WEnCntl_DRV                        2
    #define   MSK32Gbl_NAND_WEnCntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_WEnCntl_PDEN                       0x08D0
    #define     B16Gbl_NAND_WEnCntl_PDEN                       0x08D0
    #define   LSb32Gbl_NAND_WEnCntl_PDEN                          2
    #define   LSb16Gbl_NAND_WEnCntl_PDEN                          2
    #define       bGbl_NAND_WEnCntl_PDEN                       1
    #define   MSK32Gbl_NAND_WEnCntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_WEnCntl_PUEN                       0x08D0
    #define     B16Gbl_NAND_WEnCntl_PUEN                       0x08D0
    #define   LSb32Gbl_NAND_WEnCntl_PUEN                          3
    #define   LSb16Gbl_NAND_WEnCntl_PUEN                          3
    #define       bGbl_NAND_WEnCntl_PUEN                       1
    #define   MSK32Gbl_NAND_WEnCntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_WEnCntl_SRC                        0x08D0
    #define     B16Gbl_NAND_WEnCntl_SRC                        0x08D0
    #define   LSb32Gbl_NAND_WEnCntl_SRC                           4
    #define   LSb16Gbl_NAND_WEnCntl_SRC                           4
    #define       bGbl_NAND_WEnCntl_SRC                        1
    #define   MSK32Gbl_NAND_WEnCntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_WEnCntl_SMTC                       0x08D0
    #define     B16Gbl_NAND_WEnCntl_SMTC                       0x08D0
    #define   LSb32Gbl_NAND_WEnCntl_SMTC                          5
    #define   LSb16Gbl_NAND_WEnCntl_SMTC                          5
    #define       bGbl_NAND_WEnCntl_SMTC                       1
    #define   MSK32Gbl_NAND_WEnCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_REnCntl                            0x08D4

    #define     BA_Gbl_NAND_REnCntl_DRV                        0x08D4
    #define     B16Gbl_NAND_REnCntl_DRV                        0x08D4
    #define   LSb32Gbl_NAND_REnCntl_DRV                           0
    #define   LSb16Gbl_NAND_REnCntl_DRV                           0
    #define       bGbl_NAND_REnCntl_DRV                        2
    #define   MSK32Gbl_NAND_REnCntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_REnCntl_PDEN                       0x08D4
    #define     B16Gbl_NAND_REnCntl_PDEN                       0x08D4
    #define   LSb32Gbl_NAND_REnCntl_PDEN                          2
    #define   LSb16Gbl_NAND_REnCntl_PDEN                          2
    #define       bGbl_NAND_REnCntl_PDEN                       1
    #define   MSK32Gbl_NAND_REnCntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_REnCntl_PUEN                       0x08D4
    #define     B16Gbl_NAND_REnCntl_PUEN                       0x08D4
    #define   LSb32Gbl_NAND_REnCntl_PUEN                          3
    #define   LSb16Gbl_NAND_REnCntl_PUEN                          3
    #define       bGbl_NAND_REnCntl_PUEN                       1
    #define   MSK32Gbl_NAND_REnCntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_REnCntl_SRC                        0x08D4
    #define     B16Gbl_NAND_REnCntl_SRC                        0x08D4
    #define   LSb32Gbl_NAND_REnCntl_SRC                           4
    #define   LSb16Gbl_NAND_REnCntl_SRC                           4
    #define       bGbl_NAND_REnCntl_SRC                        1
    #define   MSK32Gbl_NAND_REnCntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_REnCntl_SMTC                       0x08D4
    #define     B16Gbl_NAND_REnCntl_SMTC                       0x08D4
    #define   LSb32Gbl_NAND_REnCntl_SMTC                          5
    #define   LSb16Gbl_NAND_REnCntl_SMTC                          5
    #define       bGbl_NAND_REnCntl_SMTC                       1
    #define   MSK32Gbl_NAND_REnCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_WPnCntl                            0x08D8

    #define     BA_Gbl_NAND_WPnCntl_DRV                        0x08D8
    #define     B16Gbl_NAND_WPnCntl_DRV                        0x08D8
    #define   LSb32Gbl_NAND_WPnCntl_DRV                           0
    #define   LSb16Gbl_NAND_WPnCntl_DRV                           0
    #define       bGbl_NAND_WPnCntl_DRV                        2
    #define   MSK32Gbl_NAND_WPnCntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_WPnCntl_PDEN                       0x08D8
    #define     B16Gbl_NAND_WPnCntl_PDEN                       0x08D8
    #define   LSb32Gbl_NAND_WPnCntl_PDEN                          2
    #define   LSb16Gbl_NAND_WPnCntl_PDEN                          2
    #define       bGbl_NAND_WPnCntl_PDEN                       1
    #define   MSK32Gbl_NAND_WPnCntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_WPnCntl_PUEN                       0x08D8
    #define     B16Gbl_NAND_WPnCntl_PUEN                       0x08D8
    #define   LSb32Gbl_NAND_WPnCntl_PUEN                          3
    #define   LSb16Gbl_NAND_WPnCntl_PUEN                          3
    #define       bGbl_NAND_WPnCntl_PUEN                       1
    #define   MSK32Gbl_NAND_WPnCntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_WPnCntl_SRC                        0x08D8
    #define     B16Gbl_NAND_WPnCntl_SRC                        0x08D8
    #define   LSb32Gbl_NAND_WPnCntl_SRC                           4
    #define   LSb16Gbl_NAND_WPnCntl_SRC                           4
    #define       bGbl_NAND_WPnCntl_SRC                        1
    #define   MSK32Gbl_NAND_WPnCntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_WPnCntl_SMTC                       0x08D8
    #define     B16Gbl_NAND_WPnCntl_SMTC                       0x08D8
    #define   LSb32Gbl_NAND_WPnCntl_SMTC                          5
    #define   LSb16Gbl_NAND_WPnCntl_SMTC                          5
    #define       bGbl_NAND_WPnCntl_SMTC                       1
    #define   MSK32Gbl_NAND_WPnCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_CEnCntl                            0x08DC

    #define     BA_Gbl_NAND_CEnCntl_DRV                        0x08DC
    #define     B16Gbl_NAND_CEnCntl_DRV                        0x08DC
    #define   LSb32Gbl_NAND_CEnCntl_DRV                           0
    #define   LSb16Gbl_NAND_CEnCntl_DRV                           0
    #define       bGbl_NAND_CEnCntl_DRV                        2
    #define   MSK32Gbl_NAND_CEnCntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_CEnCntl_PDEN                       0x08DC
    #define     B16Gbl_NAND_CEnCntl_PDEN                       0x08DC
    #define   LSb32Gbl_NAND_CEnCntl_PDEN                          2
    #define   LSb16Gbl_NAND_CEnCntl_PDEN                          2
    #define       bGbl_NAND_CEnCntl_PDEN                       1
    #define   MSK32Gbl_NAND_CEnCntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_CEnCntl_PUEN                       0x08DC
    #define     B16Gbl_NAND_CEnCntl_PUEN                       0x08DC
    #define   LSb32Gbl_NAND_CEnCntl_PUEN                          3
    #define   LSb16Gbl_NAND_CEnCntl_PUEN                          3
    #define       bGbl_NAND_CEnCntl_PUEN                       1
    #define   MSK32Gbl_NAND_CEnCntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_CEnCntl_SRC                        0x08DC
    #define     B16Gbl_NAND_CEnCntl_SRC                        0x08DC
    #define   LSb32Gbl_NAND_CEnCntl_SRC                           4
    #define   LSb16Gbl_NAND_CEnCntl_SRC                           4
    #define       bGbl_NAND_CEnCntl_SRC                        1
    #define   MSK32Gbl_NAND_CEnCntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_CEnCntl_SMTC                       0x08DC
    #define     B16Gbl_NAND_CEnCntl_SMTC                       0x08DC
    #define   LSb32Gbl_NAND_CEnCntl_SMTC                          5
    #define   LSb16Gbl_NAND_CEnCntl_SMTC                          5
    #define       bGbl_NAND_CEnCntl_SMTC                       1
    #define   MSK32Gbl_NAND_CEnCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_NAND_RDYCntl                            0x08E0

    #define     BA_Gbl_NAND_RDYCntl_DRV                        0x08E0
    #define     B16Gbl_NAND_RDYCntl_DRV                        0x08E0
    #define   LSb32Gbl_NAND_RDYCntl_DRV                           0
    #define   LSb16Gbl_NAND_RDYCntl_DRV                           0
    #define       bGbl_NAND_RDYCntl_DRV                        2
    #define   MSK32Gbl_NAND_RDYCntl_DRV                           0x00000003

    #define     BA_Gbl_NAND_RDYCntl_PDEN                       0x08E0
    #define     B16Gbl_NAND_RDYCntl_PDEN                       0x08E0
    #define   LSb32Gbl_NAND_RDYCntl_PDEN                          2
    #define   LSb16Gbl_NAND_RDYCntl_PDEN                          2
    #define       bGbl_NAND_RDYCntl_PDEN                       1
    #define   MSK32Gbl_NAND_RDYCntl_PDEN                          0x00000004

    #define     BA_Gbl_NAND_RDYCntl_PUEN                       0x08E0
    #define     B16Gbl_NAND_RDYCntl_PUEN                       0x08E0
    #define   LSb32Gbl_NAND_RDYCntl_PUEN                          3
    #define   LSb16Gbl_NAND_RDYCntl_PUEN                          3
    #define       bGbl_NAND_RDYCntl_PUEN                       1
    #define   MSK32Gbl_NAND_RDYCntl_PUEN                          0x00000008

    #define     BA_Gbl_NAND_RDYCntl_SRC                        0x08E0
    #define     B16Gbl_NAND_RDYCntl_SRC                        0x08E0
    #define   LSb32Gbl_NAND_RDYCntl_SRC                           4
    #define   LSb16Gbl_NAND_RDYCntl_SRC                           4
    #define       bGbl_NAND_RDYCntl_SRC                        1
    #define   MSK32Gbl_NAND_RDYCntl_SRC                           0x00000010

    #define     BA_Gbl_NAND_RDYCntl_SMTC                       0x08E0
    #define     B16Gbl_NAND_RDYCntl_SMTC                       0x08E0
    #define   LSb32Gbl_NAND_RDYCntl_SMTC                          5
    #define   LSb16Gbl_NAND_RDYCntl_SMTC                          5
    #define       bGbl_NAND_RDYCntl_SMTC                       1
    #define   MSK32Gbl_NAND_RDYCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SS0nCntl                           0x08E4

    #define     BA_Gbl_SPI1_SS0nCntl_DRV                       0x08E4
    #define     B16Gbl_SPI1_SS0nCntl_DRV                       0x08E4
    #define   LSb32Gbl_SPI1_SS0nCntl_DRV                          0
    #define   LSb16Gbl_SPI1_SS0nCntl_DRV                          0
    #define       bGbl_SPI1_SS0nCntl_DRV                       2
    #define   MSK32Gbl_SPI1_SS0nCntl_DRV                          0x00000003

    #define     BA_Gbl_SPI1_SS0nCntl_PDEN                      0x08E4
    #define     B16Gbl_SPI1_SS0nCntl_PDEN                      0x08E4
    #define   LSb32Gbl_SPI1_SS0nCntl_PDEN                         2
    #define   LSb16Gbl_SPI1_SS0nCntl_PDEN                         2
    #define       bGbl_SPI1_SS0nCntl_PDEN                      1
    #define   MSK32Gbl_SPI1_SS0nCntl_PDEN                         0x00000004

    #define     BA_Gbl_SPI1_SS0nCntl_PUEN                      0x08E4
    #define     B16Gbl_SPI1_SS0nCntl_PUEN                      0x08E4
    #define   LSb32Gbl_SPI1_SS0nCntl_PUEN                         3
    #define   LSb16Gbl_SPI1_SS0nCntl_PUEN                         3
    #define       bGbl_SPI1_SS0nCntl_PUEN                      1
    #define   MSK32Gbl_SPI1_SS0nCntl_PUEN                         0x00000008

    #define     BA_Gbl_SPI1_SS0nCntl_RXEN                      0x08E4
    #define     B16Gbl_SPI1_SS0nCntl_RXEN                      0x08E4
    #define   LSb32Gbl_SPI1_SS0nCntl_RXEN                         4
    #define   LSb16Gbl_SPI1_SS0nCntl_RXEN                         4
    #define       bGbl_SPI1_SS0nCntl_RXEN                      1
    #define   MSK32Gbl_SPI1_SS0nCntl_RXEN                         0x00000010

    #define     BA_Gbl_SPI1_SS0nCntl_SRC                       0x08E4
    #define     B16Gbl_SPI1_SS0nCntl_SRC                       0x08E4
    #define   LSb32Gbl_SPI1_SS0nCntl_SRC                          5
    #define   LSb16Gbl_SPI1_SS0nCntl_SRC                          5
    #define       bGbl_SPI1_SS0nCntl_SRC                       1
    #define   MSK32Gbl_SPI1_SS0nCntl_SRC                          0x00000020

    #define     BA_Gbl_SPI1_SS0nCntl_SMTC                      0x08E4
    #define     B16Gbl_SPI1_SS0nCntl_SMTC                      0x08E4
    #define   LSb32Gbl_SPI1_SS0nCntl_SMTC                         6
    #define   LSb16Gbl_SPI1_SS0nCntl_SMTC                         6
    #define       bGbl_SPI1_SS0nCntl_SMTC                      1
    #define   MSK32Gbl_SPI1_SS0nCntl_SMTC                         0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SS1nCntl                           0x08E8

    #define     BA_Gbl_SPI1_SS1nCntl_DRV                       0x08E8
    #define     B16Gbl_SPI1_SS1nCntl_DRV                       0x08E8
    #define   LSb32Gbl_SPI1_SS1nCntl_DRV                          0
    #define   LSb16Gbl_SPI1_SS1nCntl_DRV                          0
    #define       bGbl_SPI1_SS1nCntl_DRV                       2
    #define   MSK32Gbl_SPI1_SS1nCntl_DRV                          0x00000003

    #define     BA_Gbl_SPI1_SS1nCntl_PDEN                      0x08E8
    #define     B16Gbl_SPI1_SS1nCntl_PDEN                      0x08E8
    #define   LSb32Gbl_SPI1_SS1nCntl_PDEN                         2
    #define   LSb16Gbl_SPI1_SS1nCntl_PDEN                         2
    #define       bGbl_SPI1_SS1nCntl_PDEN                      1
    #define   MSK32Gbl_SPI1_SS1nCntl_PDEN                         0x00000004

    #define     BA_Gbl_SPI1_SS1nCntl_PUEN                      0x08E8
    #define     B16Gbl_SPI1_SS1nCntl_PUEN                      0x08E8
    #define   LSb32Gbl_SPI1_SS1nCntl_PUEN                         3
    #define   LSb16Gbl_SPI1_SS1nCntl_PUEN                         3
    #define       bGbl_SPI1_SS1nCntl_PUEN                      1
    #define   MSK32Gbl_SPI1_SS1nCntl_PUEN                         0x00000008

    #define     BA_Gbl_SPI1_SS1nCntl_RXEN                      0x08E8
    #define     B16Gbl_SPI1_SS1nCntl_RXEN                      0x08E8
    #define   LSb32Gbl_SPI1_SS1nCntl_RXEN                         4
    #define   LSb16Gbl_SPI1_SS1nCntl_RXEN                         4
    #define       bGbl_SPI1_SS1nCntl_RXEN                      1
    #define   MSK32Gbl_SPI1_SS1nCntl_RXEN                         0x00000010

    #define     BA_Gbl_SPI1_SS1nCntl_SRC                       0x08E8
    #define     B16Gbl_SPI1_SS1nCntl_SRC                       0x08E8
    #define   LSb32Gbl_SPI1_SS1nCntl_SRC                          5
    #define   LSb16Gbl_SPI1_SS1nCntl_SRC                          5
    #define       bGbl_SPI1_SS1nCntl_SRC                       1
    #define   MSK32Gbl_SPI1_SS1nCntl_SRC                          0x00000020

    #define     BA_Gbl_SPI1_SS1nCntl_SMTC                      0x08E8
    #define     B16Gbl_SPI1_SS1nCntl_SMTC                      0x08E8
    #define   LSb32Gbl_SPI1_SS1nCntl_SMTC                         6
    #define   LSb16Gbl_SPI1_SS1nCntl_SMTC                         6
    #define       bGbl_SPI1_SS1nCntl_SMTC                      1
    #define   MSK32Gbl_SPI1_SS1nCntl_SMTC                         0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SS2nCntl                           0x08EC

    #define     BA_Gbl_SPI1_SS2nCntl_DRV                       0x08EC
    #define     B16Gbl_SPI1_SS2nCntl_DRV                       0x08EC
    #define   LSb32Gbl_SPI1_SS2nCntl_DRV                          0
    #define   LSb16Gbl_SPI1_SS2nCntl_DRV                          0
    #define       bGbl_SPI1_SS2nCntl_DRV                       2
    #define   MSK32Gbl_SPI1_SS2nCntl_DRV                          0x00000003

    #define     BA_Gbl_SPI1_SS2nCntl_PDEN                      0x08EC
    #define     B16Gbl_SPI1_SS2nCntl_PDEN                      0x08EC
    #define   LSb32Gbl_SPI1_SS2nCntl_PDEN                         2
    #define   LSb16Gbl_SPI1_SS2nCntl_PDEN                         2
    #define       bGbl_SPI1_SS2nCntl_PDEN                      1
    #define   MSK32Gbl_SPI1_SS2nCntl_PDEN                         0x00000004

    #define     BA_Gbl_SPI1_SS2nCntl_PUEN                      0x08EC
    #define     B16Gbl_SPI1_SS2nCntl_PUEN                      0x08EC
    #define   LSb32Gbl_SPI1_SS2nCntl_PUEN                         3
    #define   LSb16Gbl_SPI1_SS2nCntl_PUEN                         3
    #define       bGbl_SPI1_SS2nCntl_PUEN                      1
    #define   MSK32Gbl_SPI1_SS2nCntl_PUEN                         0x00000008

    #define     BA_Gbl_SPI1_SS2nCntl_RXEN                      0x08EC
    #define     B16Gbl_SPI1_SS2nCntl_RXEN                      0x08EC
    #define   LSb32Gbl_SPI1_SS2nCntl_RXEN                         4
    #define   LSb16Gbl_SPI1_SS2nCntl_RXEN                         4
    #define       bGbl_SPI1_SS2nCntl_RXEN                      1
    #define   MSK32Gbl_SPI1_SS2nCntl_RXEN                         0x00000010

    #define     BA_Gbl_SPI1_SS2nCntl_SRC                       0x08EC
    #define     B16Gbl_SPI1_SS2nCntl_SRC                       0x08EC
    #define   LSb32Gbl_SPI1_SS2nCntl_SRC                          5
    #define   LSb16Gbl_SPI1_SS2nCntl_SRC                          5
    #define       bGbl_SPI1_SS2nCntl_SRC                       1
    #define   MSK32Gbl_SPI1_SS2nCntl_SRC                          0x00000020

    #define     BA_Gbl_SPI1_SS2nCntl_SMTC                      0x08EC
    #define     B16Gbl_SPI1_SS2nCntl_SMTC                      0x08EC
    #define   LSb32Gbl_SPI1_SS2nCntl_SMTC                         6
    #define   LSb16Gbl_SPI1_SS2nCntl_SMTC                         6
    #define       bGbl_SPI1_SS2nCntl_SMTC                      1
    #define   MSK32Gbl_SPI1_SS2nCntl_SMTC                         0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SS3nCntl                           0x08F0

    #define     BA_Gbl_SPI1_SS3nCntl_DRV                       0x08F0
    #define     B16Gbl_SPI1_SS3nCntl_DRV                       0x08F0
    #define   LSb32Gbl_SPI1_SS3nCntl_DRV                          0
    #define   LSb16Gbl_SPI1_SS3nCntl_DRV                          0
    #define       bGbl_SPI1_SS3nCntl_DRV                       2
    #define   MSK32Gbl_SPI1_SS3nCntl_DRV                          0x00000003

    #define     BA_Gbl_SPI1_SS3nCntl_PDEN                      0x08F0
    #define     B16Gbl_SPI1_SS3nCntl_PDEN                      0x08F0
    #define   LSb32Gbl_SPI1_SS3nCntl_PDEN                         2
    #define   LSb16Gbl_SPI1_SS3nCntl_PDEN                         2
    #define       bGbl_SPI1_SS3nCntl_PDEN                      1
    #define   MSK32Gbl_SPI1_SS3nCntl_PDEN                         0x00000004

    #define     BA_Gbl_SPI1_SS3nCntl_PUEN                      0x08F0
    #define     B16Gbl_SPI1_SS3nCntl_PUEN                      0x08F0
    #define   LSb32Gbl_SPI1_SS3nCntl_PUEN                         3
    #define   LSb16Gbl_SPI1_SS3nCntl_PUEN                         3
    #define       bGbl_SPI1_SS3nCntl_PUEN                      1
    #define   MSK32Gbl_SPI1_SS3nCntl_PUEN                         0x00000008

    #define     BA_Gbl_SPI1_SS3nCntl_RXEN                      0x08F0
    #define     B16Gbl_SPI1_SS3nCntl_RXEN                      0x08F0
    #define   LSb32Gbl_SPI1_SS3nCntl_RXEN                         4
    #define   LSb16Gbl_SPI1_SS3nCntl_RXEN                         4
    #define       bGbl_SPI1_SS3nCntl_RXEN                      1
    #define   MSK32Gbl_SPI1_SS3nCntl_RXEN                         0x00000010

    #define     BA_Gbl_SPI1_SS3nCntl_SRC                       0x08F0
    #define     B16Gbl_SPI1_SS3nCntl_SRC                       0x08F0
    #define   LSb32Gbl_SPI1_SS3nCntl_SRC                          5
    #define   LSb16Gbl_SPI1_SS3nCntl_SRC                          5
    #define       bGbl_SPI1_SS3nCntl_SRC                       1
    #define   MSK32Gbl_SPI1_SS3nCntl_SRC                          0x00000020

    #define     BA_Gbl_SPI1_SS3nCntl_SMTC                      0x08F0
    #define     B16Gbl_SPI1_SS3nCntl_SMTC                      0x08F0
    #define   LSb32Gbl_SPI1_SS3nCntl_SMTC                         6
    #define   LSb16Gbl_SPI1_SS3nCntl_SMTC                         6
    #define       bGbl_SPI1_SS3nCntl_SMTC                      1
    #define   MSK32Gbl_SPI1_SS3nCntl_SMTC                         0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SCLKCntl                           0x08F4

    #define     BA_Gbl_SPI1_SCLKCntl_DRV                       0x08F4
    #define     B16Gbl_SPI1_SCLKCntl_DRV                       0x08F4
    #define   LSb32Gbl_SPI1_SCLKCntl_DRV                          0
    #define   LSb16Gbl_SPI1_SCLKCntl_DRV                          0
    #define       bGbl_SPI1_SCLKCntl_DRV                       2
    #define   MSK32Gbl_SPI1_SCLKCntl_DRV                          0x00000003

    #define     BA_Gbl_SPI1_SCLKCntl_PDEN                      0x08F4
    #define     B16Gbl_SPI1_SCLKCntl_PDEN                      0x08F4
    #define   LSb32Gbl_SPI1_SCLKCntl_PDEN                         2
    #define   LSb16Gbl_SPI1_SCLKCntl_PDEN                         2
    #define       bGbl_SPI1_SCLKCntl_PDEN                      1
    #define   MSK32Gbl_SPI1_SCLKCntl_PDEN                         0x00000004

    #define     BA_Gbl_SPI1_SCLKCntl_PUEN                      0x08F4
    #define     B16Gbl_SPI1_SCLKCntl_PUEN                      0x08F4
    #define   LSb32Gbl_SPI1_SCLKCntl_PUEN                         3
    #define   LSb16Gbl_SPI1_SCLKCntl_PUEN                         3
    #define       bGbl_SPI1_SCLKCntl_PUEN                      1
    #define   MSK32Gbl_SPI1_SCLKCntl_PUEN                         0x00000008

    #define     BA_Gbl_SPI1_SCLKCntl_RXEN                      0x08F4
    #define     B16Gbl_SPI1_SCLKCntl_RXEN                      0x08F4
    #define   LSb32Gbl_SPI1_SCLKCntl_RXEN                         4
    #define   LSb16Gbl_SPI1_SCLKCntl_RXEN                         4
    #define       bGbl_SPI1_SCLKCntl_RXEN                      1
    #define   MSK32Gbl_SPI1_SCLKCntl_RXEN                         0x00000010

    #define     BA_Gbl_SPI1_SCLKCntl_SRC                       0x08F4
    #define     B16Gbl_SPI1_SCLKCntl_SRC                       0x08F4
    #define   LSb32Gbl_SPI1_SCLKCntl_SRC                          5
    #define   LSb16Gbl_SPI1_SCLKCntl_SRC                          5
    #define       bGbl_SPI1_SCLKCntl_SRC                       1
    #define   MSK32Gbl_SPI1_SCLKCntl_SRC                          0x00000020

    #define     BA_Gbl_SPI1_SCLKCntl_SMTC                      0x08F4
    #define     B16Gbl_SPI1_SCLKCntl_SMTC                      0x08F4
    #define   LSb32Gbl_SPI1_SCLKCntl_SMTC                         6
    #define   LSb16Gbl_SPI1_SCLKCntl_SMTC                         6
    #define       bGbl_SPI1_SCLKCntl_SMTC                      1
    #define   MSK32Gbl_SPI1_SCLKCntl_SMTC                         0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SDOCntl                            0x08F8

    #define     BA_Gbl_SPI1_SDOCntl_DRV                        0x08F8
    #define     B16Gbl_SPI1_SDOCntl_DRV                        0x08F8
    #define   LSb32Gbl_SPI1_SDOCntl_DRV                           0
    #define   LSb16Gbl_SPI1_SDOCntl_DRV                           0
    #define       bGbl_SPI1_SDOCntl_DRV                        2
    #define   MSK32Gbl_SPI1_SDOCntl_DRV                           0x00000003

    #define     BA_Gbl_SPI1_SDOCntl_PDEN                       0x08F8
    #define     B16Gbl_SPI1_SDOCntl_PDEN                       0x08F8
    #define   LSb32Gbl_SPI1_SDOCntl_PDEN                          2
    #define   LSb16Gbl_SPI1_SDOCntl_PDEN                          2
    #define       bGbl_SPI1_SDOCntl_PDEN                       1
    #define   MSK32Gbl_SPI1_SDOCntl_PDEN                          0x00000004

    #define     BA_Gbl_SPI1_SDOCntl_PUEN                       0x08F8
    #define     B16Gbl_SPI1_SDOCntl_PUEN                       0x08F8
    #define   LSb32Gbl_SPI1_SDOCntl_PUEN                          3
    #define   LSb16Gbl_SPI1_SDOCntl_PUEN                          3
    #define       bGbl_SPI1_SDOCntl_PUEN                       1
    #define   MSK32Gbl_SPI1_SDOCntl_PUEN                          0x00000008

    #define     BA_Gbl_SPI1_SDOCntl_RXEN                       0x08F8
    #define     B16Gbl_SPI1_SDOCntl_RXEN                       0x08F8
    #define   LSb32Gbl_SPI1_SDOCntl_RXEN                          4
    #define   LSb16Gbl_SPI1_SDOCntl_RXEN                          4
    #define       bGbl_SPI1_SDOCntl_RXEN                       1
    #define   MSK32Gbl_SPI1_SDOCntl_RXEN                          0x00000010

    #define     BA_Gbl_SPI1_SDOCntl_SRC                        0x08F8
    #define     B16Gbl_SPI1_SDOCntl_SRC                        0x08F8
    #define   LSb32Gbl_SPI1_SDOCntl_SRC                           5
    #define   LSb16Gbl_SPI1_SDOCntl_SRC                           5
    #define       bGbl_SPI1_SDOCntl_SRC                        1
    #define   MSK32Gbl_SPI1_SDOCntl_SRC                           0x00000020

    #define     BA_Gbl_SPI1_SDOCntl_SMTC                       0x08F8
    #define     B16Gbl_SPI1_SDOCntl_SMTC                       0x08F8
    #define   LSb32Gbl_SPI1_SDOCntl_SMTC                          6
    #define   LSb16Gbl_SPI1_SDOCntl_SMTC                          6
    #define       bGbl_SPI1_SDOCntl_SMTC                       1
    #define   MSK32Gbl_SPI1_SDOCntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SPI1_SDICntl                            0x08FC

    #define     BA_Gbl_SPI1_SDICntl_DRV                        0x08FC
    #define     B16Gbl_SPI1_SDICntl_DRV                        0x08FC
    #define   LSb32Gbl_SPI1_SDICntl_DRV                           0
    #define   LSb16Gbl_SPI1_SDICntl_DRV                           0
    #define       bGbl_SPI1_SDICntl_DRV                        2
    #define   MSK32Gbl_SPI1_SDICntl_DRV                           0x00000003

    #define     BA_Gbl_SPI1_SDICntl_PDEN                       0x08FC
    #define     B16Gbl_SPI1_SDICntl_PDEN                       0x08FC
    #define   LSb32Gbl_SPI1_SDICntl_PDEN                          2
    #define   LSb16Gbl_SPI1_SDICntl_PDEN                          2
    #define       bGbl_SPI1_SDICntl_PDEN                       1
    #define   MSK32Gbl_SPI1_SDICntl_PDEN                          0x00000004

    #define     BA_Gbl_SPI1_SDICntl_PUEN                       0x08FC
    #define     B16Gbl_SPI1_SDICntl_PUEN                       0x08FC
    #define   LSb32Gbl_SPI1_SDICntl_PUEN                          3
    #define   LSb16Gbl_SPI1_SDICntl_PUEN                          3
    #define       bGbl_SPI1_SDICntl_PUEN                       1
    #define   MSK32Gbl_SPI1_SDICntl_PUEN                          0x00000008

    #define     BA_Gbl_SPI1_SDICntl_RXEN                       0x08FC
    #define     B16Gbl_SPI1_SDICntl_RXEN                       0x08FC
    #define   LSb32Gbl_SPI1_SDICntl_RXEN                          4
    #define   LSb16Gbl_SPI1_SDICntl_RXEN                          4
    #define       bGbl_SPI1_SDICntl_RXEN                       1
    #define   MSK32Gbl_SPI1_SDICntl_RXEN                          0x00000010

    #define     BA_Gbl_SPI1_SDICntl_SRC                        0x08FC
    #define     B16Gbl_SPI1_SDICntl_SRC                        0x08FC
    #define   LSb32Gbl_SPI1_SDICntl_SRC                           5
    #define   LSb16Gbl_SPI1_SDICntl_SRC                           5
    #define       bGbl_SPI1_SDICntl_SRC                        1
    #define   MSK32Gbl_SPI1_SDICntl_SRC                           0x00000020

    #define     BA_Gbl_SPI1_SDICntl_SMTC                       0x08FC
    #define     B16Gbl_SPI1_SDICntl_SMTC                       0x08FC
    #define   LSb32Gbl_SPI1_SDICntl_SMTC                          6
    #define   LSb16Gbl_SPI1_SDICntl_SMTC                          6
    #define       bGbl_SPI1_SDICntl_SMTC                       1
    #define   MSK32Gbl_SPI1_SDICntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_USB0_DRV_VBUSCntl                       0x0900

    #define     BA_Gbl_USB0_DRV_VBUSCntl_DRV                   0x0900
    #define     B16Gbl_USB0_DRV_VBUSCntl_DRV                   0x0900
    #define   LSb32Gbl_USB0_DRV_VBUSCntl_DRV                      0
    #define   LSb16Gbl_USB0_DRV_VBUSCntl_DRV                      0
    #define       bGbl_USB0_DRV_VBUSCntl_DRV                   2
    #define   MSK32Gbl_USB0_DRV_VBUSCntl_DRV                      0x00000003

    #define     BA_Gbl_USB0_DRV_VBUSCntl_PDEN                  0x0900
    #define     B16Gbl_USB0_DRV_VBUSCntl_PDEN                  0x0900
    #define   LSb32Gbl_USB0_DRV_VBUSCntl_PDEN                     2
    #define   LSb16Gbl_USB0_DRV_VBUSCntl_PDEN                     2
    #define       bGbl_USB0_DRV_VBUSCntl_PDEN                  1
    #define   MSK32Gbl_USB0_DRV_VBUSCntl_PDEN                     0x00000004

    #define     BA_Gbl_USB0_DRV_VBUSCntl_PUEN                  0x0900
    #define     B16Gbl_USB0_DRV_VBUSCntl_PUEN                  0x0900
    #define   LSb32Gbl_USB0_DRV_VBUSCntl_PUEN                     3
    #define   LSb16Gbl_USB0_DRV_VBUSCntl_PUEN                     3
    #define       bGbl_USB0_DRV_VBUSCntl_PUEN                  1
    #define   MSK32Gbl_USB0_DRV_VBUSCntl_PUEN                     0x00000008

    #define     BA_Gbl_USB0_DRV_VBUSCntl_RXEN                  0x0900
    #define     B16Gbl_USB0_DRV_VBUSCntl_RXEN                  0x0900
    #define   LSb32Gbl_USB0_DRV_VBUSCntl_RXEN                     4
    #define   LSb16Gbl_USB0_DRV_VBUSCntl_RXEN                     4
    #define       bGbl_USB0_DRV_VBUSCntl_RXEN                  1
    #define   MSK32Gbl_USB0_DRV_VBUSCntl_RXEN                     0x00000010

    #define     BA_Gbl_USB0_DRV_VBUSCntl_SRC                   0x0900
    #define     B16Gbl_USB0_DRV_VBUSCntl_SRC                   0x0900
    #define   LSb32Gbl_USB0_DRV_VBUSCntl_SRC                      5
    #define   LSb16Gbl_USB0_DRV_VBUSCntl_SRC                      5
    #define       bGbl_USB0_DRV_VBUSCntl_SRC                   1
    #define   MSK32Gbl_USB0_DRV_VBUSCntl_SRC                      0x00000020

    #define     BA_Gbl_USB0_DRV_VBUSCntl_SMTC                  0x0900
    #define     B16Gbl_USB0_DRV_VBUSCntl_SMTC                  0x0900
    #define   LSb32Gbl_USB0_DRV_VBUSCntl_SMTC                     6
    #define   LSb16Gbl_USB0_DRV_VBUSCntl_SMTC                     6
    #define       bGbl_USB0_DRV_VBUSCntl_SMTC                  1
    #define   MSK32Gbl_USB0_DRV_VBUSCntl_SMTC                     0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TW1_SCLCntl                             0x0904

    #define     BA_Gbl_TW1_SCLCntl_DRV                         0x0904
    #define     B16Gbl_TW1_SCLCntl_DRV                         0x0904
    #define   LSb32Gbl_TW1_SCLCntl_DRV                            0
    #define   LSb16Gbl_TW1_SCLCntl_DRV                            0
    #define       bGbl_TW1_SCLCntl_DRV                         2
    #define   MSK32Gbl_TW1_SCLCntl_DRV                            0x00000003

    #define     BA_Gbl_TW1_SCLCntl_PDEN                        0x0904
    #define     B16Gbl_TW1_SCLCntl_PDEN                        0x0904
    #define   LSb32Gbl_TW1_SCLCntl_PDEN                           2
    #define   LSb16Gbl_TW1_SCLCntl_PDEN                           2
    #define       bGbl_TW1_SCLCntl_PDEN                        1
    #define   MSK32Gbl_TW1_SCLCntl_PDEN                           0x00000004

    #define     BA_Gbl_TW1_SCLCntl_PUEN                        0x0904
    #define     B16Gbl_TW1_SCLCntl_PUEN                        0x0904
    #define   LSb32Gbl_TW1_SCLCntl_PUEN                           3
    #define   LSb16Gbl_TW1_SCLCntl_PUEN                           3
    #define       bGbl_TW1_SCLCntl_PUEN                        1
    #define   MSK32Gbl_TW1_SCLCntl_PUEN                           0x00000008

    #define     BA_Gbl_TW1_SCLCntl_RXEN                        0x0904
    #define     B16Gbl_TW1_SCLCntl_RXEN                        0x0904
    #define   LSb32Gbl_TW1_SCLCntl_RXEN                           4
    #define   LSb16Gbl_TW1_SCLCntl_RXEN                           4
    #define       bGbl_TW1_SCLCntl_RXEN                        1
    #define   MSK32Gbl_TW1_SCLCntl_RXEN                           0x00000010

    #define     BA_Gbl_TW1_SCLCntl_SRC                         0x0904
    #define     B16Gbl_TW1_SCLCntl_SRC                         0x0904
    #define   LSb32Gbl_TW1_SCLCntl_SRC                            5
    #define   LSb16Gbl_TW1_SCLCntl_SRC                            5
    #define       bGbl_TW1_SCLCntl_SRC                         1
    #define   MSK32Gbl_TW1_SCLCntl_SRC                            0x00000020

    #define     BA_Gbl_TW1_SCLCntl_SMTC                        0x0904
    #define     B16Gbl_TW1_SCLCntl_SMTC                        0x0904
    #define   LSb32Gbl_TW1_SCLCntl_SMTC                           6
    #define   LSb16Gbl_TW1_SCLCntl_SMTC                           6
    #define       bGbl_TW1_SCLCntl_SMTC                        1
    #define   MSK32Gbl_TW1_SCLCntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TW1_SDACntl                             0x0908

    #define     BA_Gbl_TW1_SDACntl_DRV                         0x0908
    #define     B16Gbl_TW1_SDACntl_DRV                         0x0908
    #define   LSb32Gbl_TW1_SDACntl_DRV                            0
    #define   LSb16Gbl_TW1_SDACntl_DRV                            0
    #define       bGbl_TW1_SDACntl_DRV                         2
    #define   MSK32Gbl_TW1_SDACntl_DRV                            0x00000003

    #define     BA_Gbl_TW1_SDACntl_PDEN                        0x0908
    #define     B16Gbl_TW1_SDACntl_PDEN                        0x0908
    #define   LSb32Gbl_TW1_SDACntl_PDEN                           2
    #define   LSb16Gbl_TW1_SDACntl_PDEN                           2
    #define       bGbl_TW1_SDACntl_PDEN                        1
    #define   MSK32Gbl_TW1_SDACntl_PDEN                           0x00000004

    #define     BA_Gbl_TW1_SDACntl_PUEN                        0x0908
    #define     B16Gbl_TW1_SDACntl_PUEN                        0x0908
    #define   LSb32Gbl_TW1_SDACntl_PUEN                           3
    #define   LSb16Gbl_TW1_SDACntl_PUEN                           3
    #define       bGbl_TW1_SDACntl_PUEN                        1
    #define   MSK32Gbl_TW1_SDACntl_PUEN                           0x00000008

    #define     BA_Gbl_TW1_SDACntl_RXEN                        0x0908
    #define     B16Gbl_TW1_SDACntl_RXEN                        0x0908
    #define   LSb32Gbl_TW1_SDACntl_RXEN                           4
    #define   LSb16Gbl_TW1_SDACntl_RXEN                           4
    #define       bGbl_TW1_SDACntl_RXEN                        1
    #define   MSK32Gbl_TW1_SDACntl_RXEN                           0x00000010

    #define     BA_Gbl_TW1_SDACntl_SRC                         0x0908
    #define     B16Gbl_TW1_SDACntl_SRC                         0x0908
    #define   LSb32Gbl_TW1_SDACntl_SRC                            5
    #define   LSb16Gbl_TW1_SDACntl_SRC                            5
    #define       bGbl_TW1_SDACntl_SRC                         1
    #define   MSK32Gbl_TW1_SDACntl_SRC                            0x00000020

    #define     BA_Gbl_TW1_SDACntl_SMTC                        0x0908
    #define     B16Gbl_TW1_SDACntl_SMTC                        0x0908
    #define   LSb32Gbl_TW1_SDACntl_SMTC                           6
    #define   LSb16Gbl_TW1_SDACntl_SMTC                           6
    #define       bGbl_TW1_SDACntl_SMTC                        1
    #define   MSK32Gbl_TW1_SDACntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TW0_SCLCntl                             0x090C

    #define     BA_Gbl_TW0_SCLCntl_DRV                         0x090C
    #define     B16Gbl_TW0_SCLCntl_DRV                         0x090C
    #define   LSb32Gbl_TW0_SCLCntl_DRV                            0
    #define   LSb16Gbl_TW0_SCLCntl_DRV                            0
    #define       bGbl_TW0_SCLCntl_DRV                         2
    #define   MSK32Gbl_TW0_SCLCntl_DRV                            0x00000003

    #define     BA_Gbl_TW0_SCLCntl_PDEN                        0x090C
    #define     B16Gbl_TW0_SCLCntl_PDEN                        0x090C
    #define   LSb32Gbl_TW0_SCLCntl_PDEN                           2
    #define   LSb16Gbl_TW0_SCLCntl_PDEN                           2
    #define       bGbl_TW0_SCLCntl_PDEN                        1
    #define   MSK32Gbl_TW0_SCLCntl_PDEN                           0x00000004

    #define     BA_Gbl_TW0_SCLCntl_PUEN                        0x090C
    #define     B16Gbl_TW0_SCLCntl_PUEN                        0x090C
    #define   LSb32Gbl_TW0_SCLCntl_PUEN                           3
    #define   LSb16Gbl_TW0_SCLCntl_PUEN                           3
    #define       bGbl_TW0_SCLCntl_PUEN                        1
    #define   MSK32Gbl_TW0_SCLCntl_PUEN                           0x00000008

    #define     BA_Gbl_TW0_SCLCntl_RXEN                        0x090C
    #define     B16Gbl_TW0_SCLCntl_RXEN                        0x090C
    #define   LSb32Gbl_TW0_SCLCntl_RXEN                           4
    #define   LSb16Gbl_TW0_SCLCntl_RXEN                           4
    #define       bGbl_TW0_SCLCntl_RXEN                        1
    #define   MSK32Gbl_TW0_SCLCntl_RXEN                           0x00000010

    #define     BA_Gbl_TW0_SCLCntl_SRC                         0x090C
    #define     B16Gbl_TW0_SCLCntl_SRC                         0x090C
    #define   LSb32Gbl_TW0_SCLCntl_SRC                            5
    #define   LSb16Gbl_TW0_SCLCntl_SRC                            5
    #define       bGbl_TW0_SCLCntl_SRC                         1
    #define   MSK32Gbl_TW0_SCLCntl_SRC                            0x00000020

    #define     BA_Gbl_TW0_SCLCntl_SMTC                        0x090C
    #define     B16Gbl_TW0_SCLCntl_SMTC                        0x090C
    #define   LSb32Gbl_TW0_SCLCntl_SMTC                           6
    #define   LSb16Gbl_TW0_SCLCntl_SMTC                           6
    #define       bGbl_TW0_SCLCntl_SMTC                        1
    #define   MSK32Gbl_TW0_SCLCntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TW0_SDACntl                             0x0910

    #define     BA_Gbl_TW0_SDACntl_DRV                         0x0910
    #define     B16Gbl_TW0_SDACntl_DRV                         0x0910
    #define   LSb32Gbl_TW0_SDACntl_DRV                            0
    #define   LSb16Gbl_TW0_SDACntl_DRV                            0
    #define       bGbl_TW0_SDACntl_DRV                         2
    #define   MSK32Gbl_TW0_SDACntl_DRV                            0x00000003

    #define     BA_Gbl_TW0_SDACntl_PDEN                        0x0910
    #define     B16Gbl_TW0_SDACntl_PDEN                        0x0910
    #define   LSb32Gbl_TW0_SDACntl_PDEN                           2
    #define   LSb16Gbl_TW0_SDACntl_PDEN                           2
    #define       bGbl_TW0_SDACntl_PDEN                        1
    #define   MSK32Gbl_TW0_SDACntl_PDEN                           0x00000004

    #define     BA_Gbl_TW0_SDACntl_PUEN                        0x0910
    #define     B16Gbl_TW0_SDACntl_PUEN                        0x0910
    #define   LSb32Gbl_TW0_SDACntl_PUEN                           3
    #define   LSb16Gbl_TW0_SDACntl_PUEN                           3
    #define       bGbl_TW0_SDACntl_PUEN                        1
    #define   MSK32Gbl_TW0_SDACntl_PUEN                           0x00000008

    #define     BA_Gbl_TW0_SDACntl_RXEN                        0x0910
    #define     B16Gbl_TW0_SDACntl_RXEN                        0x0910
    #define   LSb32Gbl_TW0_SDACntl_RXEN                           4
    #define   LSb16Gbl_TW0_SDACntl_RXEN                           4
    #define       bGbl_TW0_SDACntl_RXEN                        1
    #define   MSK32Gbl_TW0_SDACntl_RXEN                           0x00000010

    #define     BA_Gbl_TW0_SDACntl_SRC                         0x0910
    #define     B16Gbl_TW0_SDACntl_SRC                         0x0910
    #define   LSb32Gbl_TW0_SDACntl_SRC                            5
    #define   LSb16Gbl_TW0_SDACntl_SRC                            5
    #define       bGbl_TW0_SDACntl_SRC                         1
    #define   MSK32Gbl_TW0_SDACntl_SRC                            0x00000020

    #define     BA_Gbl_TW0_SDACntl_SMTC                        0x0910
    #define     B16Gbl_TW0_SDACntl_SMTC                        0x0910
    #define   LSb32Gbl_TW0_SDACntl_SMTC                           6
    #define   LSb16Gbl_TW0_SDACntl_SMTC                           6
    #define       bGbl_TW0_SDACntl_SMTC                        1
    #define   MSK32Gbl_TW0_SDACntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TMSCntl                                 0x0914

    #define     BA_Gbl_TMSCntl_DRV                             0x0914
    #define     B16Gbl_TMSCntl_DRV                             0x0914
    #define   LSb32Gbl_TMSCntl_DRV                                0
    #define   LSb16Gbl_TMSCntl_DRV                                0
    #define       bGbl_TMSCntl_DRV                             2
    #define   MSK32Gbl_TMSCntl_DRV                                0x00000003

    #define     BA_Gbl_TMSCntl_PDEN                            0x0914
    #define     B16Gbl_TMSCntl_PDEN                            0x0914
    #define   LSb32Gbl_TMSCntl_PDEN                               2
    #define   LSb16Gbl_TMSCntl_PDEN                               2
    #define       bGbl_TMSCntl_PDEN                            1
    #define   MSK32Gbl_TMSCntl_PDEN                               0x00000004

    #define     BA_Gbl_TMSCntl_PUEN                            0x0914
    #define     B16Gbl_TMSCntl_PUEN                            0x0914
    #define   LSb32Gbl_TMSCntl_PUEN                               3
    #define   LSb16Gbl_TMSCntl_PUEN                               3
    #define       bGbl_TMSCntl_PUEN                            1
    #define   MSK32Gbl_TMSCntl_PUEN                               0x00000008

    #define     BA_Gbl_TMSCntl_RXEN                            0x0914
    #define     B16Gbl_TMSCntl_RXEN                            0x0914
    #define   LSb32Gbl_TMSCntl_RXEN                               4
    #define   LSb16Gbl_TMSCntl_RXEN                               4
    #define       bGbl_TMSCntl_RXEN                            1
    #define   MSK32Gbl_TMSCntl_RXEN                               0x00000010

    #define     BA_Gbl_TMSCntl_SRC                             0x0914
    #define     B16Gbl_TMSCntl_SRC                             0x0914
    #define   LSb32Gbl_TMSCntl_SRC                                5
    #define   LSb16Gbl_TMSCntl_SRC                                5
    #define       bGbl_TMSCntl_SRC                             1
    #define   MSK32Gbl_TMSCntl_SRC                                0x00000020

    #define     BA_Gbl_TMSCntl_SMTC                            0x0914
    #define     B16Gbl_TMSCntl_SMTC                            0x0914
    #define   LSb32Gbl_TMSCntl_SMTC                               6
    #define   LSb16Gbl_TMSCntl_SMTC                               6
    #define       bGbl_TMSCntl_SMTC                            1
    #define   MSK32Gbl_TMSCntl_SMTC                               0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TDICntl                                 0x0918

    #define     BA_Gbl_TDICntl_DRV                             0x0918
    #define     B16Gbl_TDICntl_DRV                             0x0918
    #define   LSb32Gbl_TDICntl_DRV                                0
    #define   LSb16Gbl_TDICntl_DRV                                0
    #define       bGbl_TDICntl_DRV                             2
    #define   MSK32Gbl_TDICntl_DRV                                0x00000003

    #define     BA_Gbl_TDICntl_PDEN                            0x0918
    #define     B16Gbl_TDICntl_PDEN                            0x0918
    #define   LSb32Gbl_TDICntl_PDEN                               2
    #define   LSb16Gbl_TDICntl_PDEN                               2
    #define       bGbl_TDICntl_PDEN                            1
    #define   MSK32Gbl_TDICntl_PDEN                               0x00000004

    #define     BA_Gbl_TDICntl_PUEN                            0x0918
    #define     B16Gbl_TDICntl_PUEN                            0x0918
    #define   LSb32Gbl_TDICntl_PUEN                               3
    #define   LSb16Gbl_TDICntl_PUEN                               3
    #define       bGbl_TDICntl_PUEN                            1
    #define   MSK32Gbl_TDICntl_PUEN                               0x00000008

    #define     BA_Gbl_TDICntl_RXEN                            0x0918
    #define     B16Gbl_TDICntl_RXEN                            0x0918
    #define   LSb32Gbl_TDICntl_RXEN                               4
    #define   LSb16Gbl_TDICntl_RXEN                               4
    #define       bGbl_TDICntl_RXEN                            1
    #define   MSK32Gbl_TDICntl_RXEN                               0x00000010

    #define     BA_Gbl_TDICntl_SRC                             0x0918
    #define     B16Gbl_TDICntl_SRC                             0x0918
    #define   LSb32Gbl_TDICntl_SRC                                5
    #define   LSb16Gbl_TDICntl_SRC                                5
    #define       bGbl_TDICntl_SRC                             1
    #define   MSK32Gbl_TDICntl_SRC                                0x00000020

    #define     BA_Gbl_TDICntl_SMTC                            0x0918
    #define     B16Gbl_TDICntl_SMTC                            0x0918
    #define   LSb32Gbl_TDICntl_SMTC                               6
    #define   LSb16Gbl_TDICntl_SMTC                               6
    #define       bGbl_TDICntl_SMTC                            1
    #define   MSK32Gbl_TDICntl_SMTC                               0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_TDOCntl                                 0x091C

    #define     BA_Gbl_TDOCntl_DRV                             0x091C
    #define     B16Gbl_TDOCntl_DRV                             0x091C
    #define   LSb32Gbl_TDOCntl_DRV                                0
    #define   LSb16Gbl_TDOCntl_DRV                                0
    #define       bGbl_TDOCntl_DRV                             2
    #define   MSK32Gbl_TDOCntl_DRV                                0x00000003

    #define     BA_Gbl_TDOCntl_PDEN                            0x091C
    #define     B16Gbl_TDOCntl_PDEN                            0x091C
    #define   LSb32Gbl_TDOCntl_PDEN                               2
    #define   LSb16Gbl_TDOCntl_PDEN                               2
    #define       bGbl_TDOCntl_PDEN                            1
    #define   MSK32Gbl_TDOCntl_PDEN                               0x00000004

    #define     BA_Gbl_TDOCntl_PUEN                            0x091C
    #define     B16Gbl_TDOCntl_PUEN                            0x091C
    #define   LSb32Gbl_TDOCntl_PUEN                               3
    #define   LSb16Gbl_TDOCntl_PUEN                               3
    #define       bGbl_TDOCntl_PUEN                            1
    #define   MSK32Gbl_TDOCntl_PUEN                               0x00000008

    #define     BA_Gbl_TDOCntl_RXEN                            0x091C
    #define     B16Gbl_TDOCntl_RXEN                            0x091C
    #define   LSb32Gbl_TDOCntl_RXEN                               4
    #define   LSb16Gbl_TDOCntl_RXEN                               4
    #define       bGbl_TDOCntl_RXEN                            1
    #define   MSK32Gbl_TDOCntl_RXEN                               0x00000010

    #define     BA_Gbl_TDOCntl_SRC                             0x091C
    #define     B16Gbl_TDOCntl_SRC                             0x091C
    #define   LSb32Gbl_TDOCntl_SRC                                5
    #define   LSb16Gbl_TDOCntl_SRC                                5
    #define       bGbl_TDOCntl_SRC                             1
    #define   MSK32Gbl_TDOCntl_SRC                                0x00000020

    #define     BA_Gbl_TDOCntl_SMTC                            0x091C
    #define     B16Gbl_TDOCntl_SMTC                            0x091C
    #define   LSb32Gbl_TDOCntl_SMTC                               6
    #define   LSb16Gbl_TDOCntl_SMTC                               6
    #define       bGbl_TDOCntl_SMTC                            1
    #define   MSK32Gbl_TDOCntl_SMTC                               0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM6Cntl                                0x0920

    #define     BA_Gbl_PWM6Cntl_DRV                            0x0920
    #define     B16Gbl_PWM6Cntl_DRV                            0x0920
    #define   LSb32Gbl_PWM6Cntl_DRV                               0
    #define   LSb16Gbl_PWM6Cntl_DRV                               0
    #define       bGbl_PWM6Cntl_DRV                            2
    #define   MSK32Gbl_PWM6Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM6Cntl_PDEN                           0x0920
    #define     B16Gbl_PWM6Cntl_PDEN                           0x0920
    #define   LSb32Gbl_PWM6Cntl_PDEN                              2
    #define   LSb16Gbl_PWM6Cntl_PDEN                              2
    #define       bGbl_PWM6Cntl_PDEN                           1
    #define   MSK32Gbl_PWM6Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM6Cntl_PUEN                           0x0920
    #define     B16Gbl_PWM6Cntl_PUEN                           0x0920
    #define   LSb32Gbl_PWM6Cntl_PUEN                              3
    #define   LSb16Gbl_PWM6Cntl_PUEN                              3
    #define       bGbl_PWM6Cntl_PUEN                           1
    #define   MSK32Gbl_PWM6Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM6Cntl_SRC                            0x0920
    #define     B16Gbl_PWM6Cntl_SRC                            0x0920
    #define   LSb32Gbl_PWM6Cntl_SRC                               4
    #define   LSb16Gbl_PWM6Cntl_SRC                               4
    #define       bGbl_PWM6Cntl_SRC                            1
    #define   MSK32Gbl_PWM6Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM6Cntl_SMTC                           0x0920
    #define     B16Gbl_PWM6Cntl_SMTC                           0x0920
    #define   LSb32Gbl_PWM6Cntl_SMTC                              5
    #define   LSb16Gbl_PWM6Cntl_SMTC                              5
    #define       bGbl_PWM6Cntl_SMTC                           1
    #define   MSK32Gbl_PWM6Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM7Cntl                                0x0924

    #define     BA_Gbl_PWM7Cntl_DRV                            0x0924
    #define     B16Gbl_PWM7Cntl_DRV                            0x0924
    #define   LSb32Gbl_PWM7Cntl_DRV                               0
    #define   LSb16Gbl_PWM7Cntl_DRV                               0
    #define       bGbl_PWM7Cntl_DRV                            2
    #define   MSK32Gbl_PWM7Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM7Cntl_PDEN                           0x0924
    #define     B16Gbl_PWM7Cntl_PDEN                           0x0924
    #define   LSb32Gbl_PWM7Cntl_PDEN                              2
    #define   LSb16Gbl_PWM7Cntl_PDEN                              2
    #define       bGbl_PWM7Cntl_PDEN                           1
    #define   MSK32Gbl_PWM7Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM7Cntl_PUEN                           0x0924
    #define     B16Gbl_PWM7Cntl_PUEN                           0x0924
    #define   LSb32Gbl_PWM7Cntl_PUEN                              3
    #define   LSb16Gbl_PWM7Cntl_PUEN                              3
    #define       bGbl_PWM7Cntl_PUEN                           1
    #define   MSK32Gbl_PWM7Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM7Cntl_SRC                            0x0924
    #define     B16Gbl_PWM7Cntl_SRC                            0x0924
    #define   LSb32Gbl_PWM7Cntl_SRC                               4
    #define   LSb16Gbl_PWM7Cntl_SRC                               4
    #define       bGbl_PWM7Cntl_SRC                            1
    #define   MSK32Gbl_PWM7Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM7Cntl_SMTC                           0x0924
    #define     B16Gbl_PWM7Cntl_SMTC                           0x0924
    #define   LSb32Gbl_PWM7Cntl_SMTC                              5
    #define   LSb16Gbl_PWM7Cntl_SMTC                              5
    #define       bGbl_PWM7Cntl_SMTC                           1
    #define   MSK32Gbl_PWM7Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM0Cntl                                0x0928

    #define     BA_Gbl_PWM0Cntl_DRV                            0x0928
    #define     B16Gbl_PWM0Cntl_DRV                            0x0928
    #define   LSb32Gbl_PWM0Cntl_DRV                               0
    #define   LSb16Gbl_PWM0Cntl_DRV                               0
    #define       bGbl_PWM0Cntl_DRV                            2
    #define   MSK32Gbl_PWM0Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM0Cntl_PDEN                           0x0928
    #define     B16Gbl_PWM0Cntl_PDEN                           0x0928
    #define   LSb32Gbl_PWM0Cntl_PDEN                              2
    #define   LSb16Gbl_PWM0Cntl_PDEN                              2
    #define       bGbl_PWM0Cntl_PDEN                           1
    #define   MSK32Gbl_PWM0Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM0Cntl_PUEN                           0x0928
    #define     B16Gbl_PWM0Cntl_PUEN                           0x0928
    #define   LSb32Gbl_PWM0Cntl_PUEN                              3
    #define   LSb16Gbl_PWM0Cntl_PUEN                              3
    #define       bGbl_PWM0Cntl_PUEN                           1
    #define   MSK32Gbl_PWM0Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM0Cntl_SRC                            0x0928
    #define     B16Gbl_PWM0Cntl_SRC                            0x0928
    #define   LSb32Gbl_PWM0Cntl_SRC                               4
    #define   LSb16Gbl_PWM0Cntl_SRC                               4
    #define       bGbl_PWM0Cntl_SRC                            1
    #define   MSK32Gbl_PWM0Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM0Cntl_SMTC                           0x0928
    #define     B16Gbl_PWM0Cntl_SMTC                           0x0928
    #define   LSb32Gbl_PWM0Cntl_SMTC                              5
    #define   LSb16Gbl_PWM0Cntl_SMTC                              5
    #define       bGbl_PWM0Cntl_SMTC                           1
    #define   MSK32Gbl_PWM0Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM1Cntl                                0x092C

    #define     BA_Gbl_PWM1Cntl_DRV                            0x092C
    #define     B16Gbl_PWM1Cntl_DRV                            0x092C
    #define   LSb32Gbl_PWM1Cntl_DRV                               0
    #define   LSb16Gbl_PWM1Cntl_DRV                               0
    #define       bGbl_PWM1Cntl_DRV                            2
    #define   MSK32Gbl_PWM1Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM1Cntl_PDEN                           0x092C
    #define     B16Gbl_PWM1Cntl_PDEN                           0x092C
    #define   LSb32Gbl_PWM1Cntl_PDEN                              2
    #define   LSb16Gbl_PWM1Cntl_PDEN                              2
    #define       bGbl_PWM1Cntl_PDEN                           1
    #define   MSK32Gbl_PWM1Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM1Cntl_PUEN                           0x092C
    #define     B16Gbl_PWM1Cntl_PUEN                           0x092C
    #define   LSb32Gbl_PWM1Cntl_PUEN                              3
    #define   LSb16Gbl_PWM1Cntl_PUEN                              3
    #define       bGbl_PWM1Cntl_PUEN                           1
    #define   MSK32Gbl_PWM1Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM1Cntl_SRC                            0x092C
    #define     B16Gbl_PWM1Cntl_SRC                            0x092C
    #define   LSb32Gbl_PWM1Cntl_SRC                               4
    #define   LSb16Gbl_PWM1Cntl_SRC                               4
    #define       bGbl_PWM1Cntl_SRC                            1
    #define   MSK32Gbl_PWM1Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM1Cntl_SMTC                           0x092C
    #define     B16Gbl_PWM1Cntl_SMTC                           0x092C
    #define   LSb32Gbl_PWM1Cntl_SMTC                              5
    #define   LSb16Gbl_PWM1Cntl_SMTC                              5
    #define       bGbl_PWM1Cntl_SMTC                           1
    #define   MSK32Gbl_PWM1Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM2Cntl                                0x0930

    #define     BA_Gbl_PWM2Cntl_DRV                            0x0930
    #define     B16Gbl_PWM2Cntl_DRV                            0x0930
    #define   LSb32Gbl_PWM2Cntl_DRV                               0
    #define   LSb16Gbl_PWM2Cntl_DRV                               0
    #define       bGbl_PWM2Cntl_DRV                            2
    #define   MSK32Gbl_PWM2Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM2Cntl_PDEN                           0x0930
    #define     B16Gbl_PWM2Cntl_PDEN                           0x0930
    #define   LSb32Gbl_PWM2Cntl_PDEN                              2
    #define   LSb16Gbl_PWM2Cntl_PDEN                              2
    #define       bGbl_PWM2Cntl_PDEN                           1
    #define   MSK32Gbl_PWM2Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM2Cntl_PUEN                           0x0930
    #define     B16Gbl_PWM2Cntl_PUEN                           0x0930
    #define   LSb32Gbl_PWM2Cntl_PUEN                              3
    #define   LSb16Gbl_PWM2Cntl_PUEN                              3
    #define       bGbl_PWM2Cntl_PUEN                           1
    #define   MSK32Gbl_PWM2Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM2Cntl_SRC                            0x0930
    #define     B16Gbl_PWM2Cntl_SRC                            0x0930
    #define   LSb32Gbl_PWM2Cntl_SRC                               4
    #define   LSb16Gbl_PWM2Cntl_SRC                               4
    #define       bGbl_PWM2Cntl_SRC                            1
    #define   MSK32Gbl_PWM2Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM2Cntl_SMTC                           0x0930
    #define     B16Gbl_PWM2Cntl_SMTC                           0x0930
    #define   LSb32Gbl_PWM2Cntl_SMTC                              5
    #define   LSb16Gbl_PWM2Cntl_SMTC                              5
    #define       bGbl_PWM2Cntl_SMTC                           1
    #define   MSK32Gbl_PWM2Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM3Cntl                                0x0934

    #define     BA_Gbl_PWM3Cntl_DRV                            0x0934
    #define     B16Gbl_PWM3Cntl_DRV                            0x0934
    #define   LSb32Gbl_PWM3Cntl_DRV                               0
    #define   LSb16Gbl_PWM3Cntl_DRV                               0
    #define       bGbl_PWM3Cntl_DRV                            2
    #define   MSK32Gbl_PWM3Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM3Cntl_PDEN                           0x0934
    #define     B16Gbl_PWM3Cntl_PDEN                           0x0934
    #define   LSb32Gbl_PWM3Cntl_PDEN                              2
    #define   LSb16Gbl_PWM3Cntl_PDEN                              2
    #define       bGbl_PWM3Cntl_PDEN                           1
    #define   MSK32Gbl_PWM3Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM3Cntl_PUEN                           0x0934
    #define     B16Gbl_PWM3Cntl_PUEN                           0x0934
    #define   LSb32Gbl_PWM3Cntl_PUEN                              3
    #define   LSb16Gbl_PWM3Cntl_PUEN                              3
    #define       bGbl_PWM3Cntl_PUEN                           1
    #define   MSK32Gbl_PWM3Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM3Cntl_SRC                            0x0934
    #define     B16Gbl_PWM3Cntl_SRC                            0x0934
    #define   LSb32Gbl_PWM3Cntl_SRC                               4
    #define   LSb16Gbl_PWM3Cntl_SRC                               4
    #define       bGbl_PWM3Cntl_SRC                            1
    #define   MSK32Gbl_PWM3Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM3Cntl_SMTC                           0x0934
    #define     B16Gbl_PWM3Cntl_SMTC                           0x0934
    #define   LSb32Gbl_PWM3Cntl_SMTC                              5
    #define   LSb16Gbl_PWM3Cntl_SMTC                              5
    #define       bGbl_PWM3Cntl_SMTC                           1
    #define   MSK32Gbl_PWM3Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM4Cntl                                0x0938

    #define     BA_Gbl_PWM4Cntl_DRV                            0x0938
    #define     B16Gbl_PWM4Cntl_DRV                            0x0938
    #define   LSb32Gbl_PWM4Cntl_DRV                               0
    #define   LSb16Gbl_PWM4Cntl_DRV                               0
    #define       bGbl_PWM4Cntl_DRV                            2
    #define   MSK32Gbl_PWM4Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM4Cntl_PDEN                           0x0938
    #define     B16Gbl_PWM4Cntl_PDEN                           0x0938
    #define   LSb32Gbl_PWM4Cntl_PDEN                              2
    #define   LSb16Gbl_PWM4Cntl_PDEN                              2
    #define       bGbl_PWM4Cntl_PDEN                           1
    #define   MSK32Gbl_PWM4Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM4Cntl_PUEN                           0x0938
    #define     B16Gbl_PWM4Cntl_PUEN                           0x0938
    #define   LSb32Gbl_PWM4Cntl_PUEN                              3
    #define   LSb16Gbl_PWM4Cntl_PUEN                              3
    #define       bGbl_PWM4Cntl_PUEN                           1
    #define   MSK32Gbl_PWM4Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM4Cntl_SRC                            0x0938
    #define     B16Gbl_PWM4Cntl_SRC                            0x0938
    #define   LSb32Gbl_PWM4Cntl_SRC                               4
    #define   LSb16Gbl_PWM4Cntl_SRC                               4
    #define       bGbl_PWM4Cntl_SRC                            1
    #define   MSK32Gbl_PWM4Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM4Cntl_SMTC                           0x0938
    #define     B16Gbl_PWM4Cntl_SMTC                           0x0938
    #define   LSb32Gbl_PWM4Cntl_SMTC                              5
    #define   LSb16Gbl_PWM4Cntl_SMTC                              5
    #define       bGbl_PWM4Cntl_SMTC                           1
    #define   MSK32Gbl_PWM4Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_PWM5Cntl                                0x093C

    #define     BA_Gbl_PWM5Cntl_DRV                            0x093C
    #define     B16Gbl_PWM5Cntl_DRV                            0x093C
    #define   LSb32Gbl_PWM5Cntl_DRV                               0
    #define   LSb16Gbl_PWM5Cntl_DRV                               0
    #define       bGbl_PWM5Cntl_DRV                            2
    #define   MSK32Gbl_PWM5Cntl_DRV                               0x00000003

    #define     BA_Gbl_PWM5Cntl_PDEN                           0x093C
    #define     B16Gbl_PWM5Cntl_PDEN                           0x093C
    #define   LSb32Gbl_PWM5Cntl_PDEN                              2
    #define   LSb16Gbl_PWM5Cntl_PDEN                              2
    #define       bGbl_PWM5Cntl_PDEN                           1
    #define   MSK32Gbl_PWM5Cntl_PDEN                              0x00000004

    #define     BA_Gbl_PWM5Cntl_PUEN                           0x093C
    #define     B16Gbl_PWM5Cntl_PUEN                           0x093C
    #define   LSb32Gbl_PWM5Cntl_PUEN                              3
    #define   LSb16Gbl_PWM5Cntl_PUEN                              3
    #define       bGbl_PWM5Cntl_PUEN                           1
    #define   MSK32Gbl_PWM5Cntl_PUEN                              0x00000008

    #define     BA_Gbl_PWM5Cntl_SRC                            0x093C
    #define     B16Gbl_PWM5Cntl_SRC                            0x093C
    #define   LSb32Gbl_PWM5Cntl_SRC                               4
    #define   LSb16Gbl_PWM5Cntl_SRC                               4
    #define       bGbl_PWM5Cntl_SRC                            1
    #define   MSK32Gbl_PWM5Cntl_SRC                               0x00000010

    #define     BA_Gbl_PWM5Cntl_SMTC                           0x093C
    #define     B16Gbl_PWM5Cntl_SMTC                           0x093C
    #define   LSb32Gbl_PWM5Cntl_SMTC                              5
    #define   LSb16Gbl_PWM5Cntl_SMTC                              5
    #define       bGbl_PWM5Cntl_SMTC                           1
    #define   MSK32Gbl_PWM5Cntl_SMTC                              0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_URT1_RTSnCntl                           0x0940

    #define     BA_Gbl_URT1_RTSnCntl_DRV                       0x0940
    #define     B16Gbl_URT1_RTSnCntl_DRV                       0x0940
    #define   LSb32Gbl_URT1_RTSnCntl_DRV                          0
    #define   LSb16Gbl_URT1_RTSnCntl_DRV                          0
    #define       bGbl_URT1_RTSnCntl_DRV                       2
    #define   MSK32Gbl_URT1_RTSnCntl_DRV                          0x00000003

    #define     BA_Gbl_URT1_RTSnCntl_PDEN                      0x0940
    #define     B16Gbl_URT1_RTSnCntl_PDEN                      0x0940
    #define   LSb32Gbl_URT1_RTSnCntl_PDEN                         2
    #define   LSb16Gbl_URT1_RTSnCntl_PDEN                         2
    #define       bGbl_URT1_RTSnCntl_PDEN                      1
    #define   MSK32Gbl_URT1_RTSnCntl_PDEN                         0x00000004

    #define     BA_Gbl_URT1_RTSnCntl_PUEN                      0x0940
    #define     B16Gbl_URT1_RTSnCntl_PUEN                      0x0940
    #define   LSb32Gbl_URT1_RTSnCntl_PUEN                         3
    #define   LSb16Gbl_URT1_RTSnCntl_PUEN                         3
    #define       bGbl_URT1_RTSnCntl_PUEN                      1
    #define   MSK32Gbl_URT1_RTSnCntl_PUEN                         0x00000008

    #define     BA_Gbl_URT1_RTSnCntl_SRC                       0x0940
    #define     B16Gbl_URT1_RTSnCntl_SRC                       0x0940
    #define   LSb32Gbl_URT1_RTSnCntl_SRC                          4
    #define   LSb16Gbl_URT1_RTSnCntl_SRC                          4
    #define       bGbl_URT1_RTSnCntl_SRC                       1
    #define   MSK32Gbl_URT1_RTSnCntl_SRC                          0x00000010

    #define     BA_Gbl_URT1_RTSnCntl_SMTC                      0x0940
    #define     B16Gbl_URT1_RTSnCntl_SMTC                      0x0940
    #define   LSb32Gbl_URT1_RTSnCntl_SMTC                         5
    #define   LSb16Gbl_URT1_RTSnCntl_SMTC                         5
    #define       bGbl_URT1_RTSnCntl_SMTC                      1
    #define   MSK32Gbl_URT1_RTSnCntl_SMTC                         0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_URT1_CTSnCntl                           0x0944

    #define     BA_Gbl_URT1_CTSnCntl_DRV                       0x0944
    #define     B16Gbl_URT1_CTSnCntl_DRV                       0x0944
    #define   LSb32Gbl_URT1_CTSnCntl_DRV                          0
    #define   LSb16Gbl_URT1_CTSnCntl_DRV                          0
    #define       bGbl_URT1_CTSnCntl_DRV                       2
    #define   MSK32Gbl_URT1_CTSnCntl_DRV                          0x00000003

    #define     BA_Gbl_URT1_CTSnCntl_PDEN                      0x0944
    #define     B16Gbl_URT1_CTSnCntl_PDEN                      0x0944
    #define   LSb32Gbl_URT1_CTSnCntl_PDEN                         2
    #define   LSb16Gbl_URT1_CTSnCntl_PDEN                         2
    #define       bGbl_URT1_CTSnCntl_PDEN                      1
    #define   MSK32Gbl_URT1_CTSnCntl_PDEN                         0x00000004

    #define     BA_Gbl_URT1_CTSnCntl_PUEN                      0x0944
    #define     B16Gbl_URT1_CTSnCntl_PUEN                      0x0944
    #define   LSb32Gbl_URT1_CTSnCntl_PUEN                         3
    #define   LSb16Gbl_URT1_CTSnCntl_PUEN                         3
    #define       bGbl_URT1_CTSnCntl_PUEN                      1
    #define   MSK32Gbl_URT1_CTSnCntl_PUEN                         0x00000008

    #define     BA_Gbl_URT1_CTSnCntl_SRC                       0x0944
    #define     B16Gbl_URT1_CTSnCntl_SRC                       0x0944
    #define   LSb32Gbl_URT1_CTSnCntl_SRC                          4
    #define   LSb16Gbl_URT1_CTSnCntl_SRC                          4
    #define       bGbl_URT1_CTSnCntl_SRC                       1
    #define   MSK32Gbl_URT1_CTSnCntl_SRC                          0x00000010

    #define     BA_Gbl_URT1_CTSnCntl_SMTC                      0x0944
    #define     B16Gbl_URT1_CTSnCntl_SMTC                      0x0944
    #define   LSb32Gbl_URT1_CTSnCntl_SMTC                         5
    #define   LSb16Gbl_URT1_CTSnCntl_SMTC                         5
    #define       bGbl_URT1_CTSnCntl_SMTC                      1
    #define   MSK32Gbl_URT1_CTSnCntl_SMTC                         0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_URT1_RXDCntl                            0x0948

    #define     BA_Gbl_URT1_RXDCntl_DRV                        0x0948
    #define     B16Gbl_URT1_RXDCntl_DRV                        0x0948
    #define   LSb32Gbl_URT1_RXDCntl_DRV                           0
    #define   LSb16Gbl_URT1_RXDCntl_DRV                           0
    #define       bGbl_URT1_RXDCntl_DRV                        2
    #define   MSK32Gbl_URT1_RXDCntl_DRV                           0x00000003

    #define     BA_Gbl_URT1_RXDCntl_PDEN                       0x0948
    #define     B16Gbl_URT1_RXDCntl_PDEN                       0x0948
    #define   LSb32Gbl_URT1_RXDCntl_PDEN                          2
    #define   LSb16Gbl_URT1_RXDCntl_PDEN                          2
    #define       bGbl_URT1_RXDCntl_PDEN                       1
    #define   MSK32Gbl_URT1_RXDCntl_PDEN                          0x00000004

    #define     BA_Gbl_URT1_RXDCntl_PUEN                       0x0948
    #define     B16Gbl_URT1_RXDCntl_PUEN                       0x0948
    #define   LSb32Gbl_URT1_RXDCntl_PUEN                          3
    #define   LSb16Gbl_URT1_RXDCntl_PUEN                          3
    #define       bGbl_URT1_RXDCntl_PUEN                       1
    #define   MSK32Gbl_URT1_RXDCntl_PUEN                          0x00000008

    #define     BA_Gbl_URT1_RXDCntl_RXEN                       0x0948
    #define     B16Gbl_URT1_RXDCntl_RXEN                       0x0948
    #define   LSb32Gbl_URT1_RXDCntl_RXEN                          4
    #define   LSb16Gbl_URT1_RXDCntl_RXEN                          4
    #define       bGbl_URT1_RXDCntl_RXEN                       1
    #define   MSK32Gbl_URT1_RXDCntl_RXEN                          0x00000010

    #define     BA_Gbl_URT1_RXDCntl_SRC                        0x0948
    #define     B16Gbl_URT1_RXDCntl_SRC                        0x0948
    #define   LSb32Gbl_URT1_RXDCntl_SRC                           5
    #define   LSb16Gbl_URT1_RXDCntl_SRC                           5
    #define       bGbl_URT1_RXDCntl_SRC                        1
    #define   MSK32Gbl_URT1_RXDCntl_SRC                           0x00000020

    #define     BA_Gbl_URT1_RXDCntl_SMTC                       0x0948
    #define     B16Gbl_URT1_RXDCntl_SMTC                       0x0948
    #define   LSb32Gbl_URT1_RXDCntl_SMTC                          6
    #define   LSb16Gbl_URT1_RXDCntl_SMTC                          6
    #define       bGbl_URT1_RXDCntl_SMTC                       1
    #define   MSK32Gbl_URT1_RXDCntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_URT1_TXDCntl                            0x094C

    #define     BA_Gbl_URT1_TXDCntl_DRV                        0x094C
    #define     B16Gbl_URT1_TXDCntl_DRV                        0x094C
    #define   LSb32Gbl_URT1_TXDCntl_DRV                           0
    #define   LSb16Gbl_URT1_TXDCntl_DRV                           0
    #define       bGbl_URT1_TXDCntl_DRV                        2
    #define   MSK32Gbl_URT1_TXDCntl_DRV                           0x00000003

    #define     BA_Gbl_URT1_TXDCntl_PDEN                       0x094C
    #define     B16Gbl_URT1_TXDCntl_PDEN                       0x094C
    #define   LSb32Gbl_URT1_TXDCntl_PDEN                          2
    #define   LSb16Gbl_URT1_TXDCntl_PDEN                          2
    #define       bGbl_URT1_TXDCntl_PDEN                       1
    #define   MSK32Gbl_URT1_TXDCntl_PDEN                          0x00000004

    #define     BA_Gbl_URT1_TXDCntl_PUEN                       0x094C
    #define     B16Gbl_URT1_TXDCntl_PUEN                       0x094C
    #define   LSb32Gbl_URT1_TXDCntl_PUEN                          3
    #define   LSb16Gbl_URT1_TXDCntl_PUEN                          3
    #define       bGbl_URT1_TXDCntl_PUEN                       1
    #define   MSK32Gbl_URT1_TXDCntl_PUEN                          0x00000008

    #define     BA_Gbl_URT1_TXDCntl_SRC                        0x094C
    #define     B16Gbl_URT1_TXDCntl_SRC                        0x094C
    #define   LSb32Gbl_URT1_TXDCntl_SRC                           4
    #define   LSb16Gbl_URT1_TXDCntl_SRC                           4
    #define       bGbl_URT1_TXDCntl_SRC                        1
    #define   MSK32Gbl_URT1_TXDCntl_SRC                           0x00000010

    #define     BA_Gbl_URT1_TXDCntl_SMTC                       0x094C
    #define     B16Gbl_URT1_TXDCntl_SMTC                       0x094C
    #define   LSb32Gbl_URT1_TXDCntl_SMTC                          5
    #define   LSb16Gbl_URT1_TXDCntl_SMTC                          5
    #define       bGbl_URT1_TXDCntl_SMTC                       1
    #define   MSK32Gbl_URT1_TXDCntl_SMTC                          0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S3_DICntl                             0x0950

    #define     BA_Gbl_I2S3_DICntl_DRV                         0x0950
    #define     B16Gbl_I2S3_DICntl_DRV                         0x0950
    #define   LSb32Gbl_I2S3_DICntl_DRV                            0
    #define   LSb16Gbl_I2S3_DICntl_DRV                            0
    #define       bGbl_I2S3_DICntl_DRV                         2
    #define   MSK32Gbl_I2S3_DICntl_DRV                            0x00000003

    #define     BA_Gbl_I2S3_DICntl_PDEN                        0x0950
    #define     B16Gbl_I2S3_DICntl_PDEN                        0x0950
    #define   LSb32Gbl_I2S3_DICntl_PDEN                           2
    #define   LSb16Gbl_I2S3_DICntl_PDEN                           2
    #define       bGbl_I2S3_DICntl_PDEN                        1
    #define   MSK32Gbl_I2S3_DICntl_PDEN                           0x00000004

    #define     BA_Gbl_I2S3_DICntl_PUEN                        0x0950
    #define     B16Gbl_I2S3_DICntl_PUEN                        0x0950
    #define   LSb32Gbl_I2S3_DICntl_PUEN                           3
    #define   LSb16Gbl_I2S3_DICntl_PUEN                           3
    #define       bGbl_I2S3_DICntl_PUEN                        1
    #define   MSK32Gbl_I2S3_DICntl_PUEN                           0x00000008

    #define     BA_Gbl_I2S3_DICntl_SRC                         0x0950
    #define     B16Gbl_I2S3_DICntl_SRC                         0x0950
    #define   LSb32Gbl_I2S3_DICntl_SRC                            4
    #define   LSb16Gbl_I2S3_DICntl_SRC                            4
    #define       bGbl_I2S3_DICntl_SRC                         1
    #define   MSK32Gbl_I2S3_DICntl_SRC                            0x00000010

    #define     BA_Gbl_I2S3_DICntl_SMTC                        0x0950
    #define     B16Gbl_I2S3_DICntl_SMTC                        0x0950
    #define   LSb32Gbl_I2S3_DICntl_SMTC                           5
    #define   LSb16Gbl_I2S3_DICntl_SMTC                           5
    #define       bGbl_I2S3_DICntl_SMTC                        1
    #define   MSK32Gbl_I2S3_DICntl_SMTC                           0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S3_DOCntl                             0x0954

    #define     BA_Gbl_I2S3_DOCntl_DRV                         0x0954
    #define     B16Gbl_I2S3_DOCntl_DRV                         0x0954
    #define   LSb32Gbl_I2S3_DOCntl_DRV                            0
    #define   LSb16Gbl_I2S3_DOCntl_DRV                            0
    #define       bGbl_I2S3_DOCntl_DRV                         2
    #define   MSK32Gbl_I2S3_DOCntl_DRV                            0x00000003

    #define     BA_Gbl_I2S3_DOCntl_PDEN                        0x0954
    #define     B16Gbl_I2S3_DOCntl_PDEN                        0x0954
    #define   LSb32Gbl_I2S3_DOCntl_PDEN                           2
    #define   LSb16Gbl_I2S3_DOCntl_PDEN                           2
    #define       bGbl_I2S3_DOCntl_PDEN                        1
    #define   MSK32Gbl_I2S3_DOCntl_PDEN                           0x00000004

    #define     BA_Gbl_I2S3_DOCntl_PUEN                        0x0954
    #define     B16Gbl_I2S3_DOCntl_PUEN                        0x0954
    #define   LSb32Gbl_I2S3_DOCntl_PUEN                           3
    #define   LSb16Gbl_I2S3_DOCntl_PUEN                           3
    #define       bGbl_I2S3_DOCntl_PUEN                        1
    #define   MSK32Gbl_I2S3_DOCntl_PUEN                           0x00000008

    #define     BA_Gbl_I2S3_DOCntl_SRC                         0x0954
    #define     B16Gbl_I2S3_DOCntl_SRC                         0x0954
    #define   LSb32Gbl_I2S3_DOCntl_SRC                            4
    #define   LSb16Gbl_I2S3_DOCntl_SRC                            4
    #define       bGbl_I2S3_DOCntl_SRC                         1
    #define   MSK32Gbl_I2S3_DOCntl_SRC                            0x00000010

    #define     BA_Gbl_I2S3_DOCntl_SMTC                        0x0954
    #define     B16Gbl_I2S3_DOCntl_SMTC                        0x0954
    #define   LSb32Gbl_I2S3_DOCntl_SMTC                           5
    #define   LSb16Gbl_I2S3_DOCntl_SMTC                           5
    #define       bGbl_I2S3_DOCntl_SMTC                        1
    #define   MSK32Gbl_I2S3_DOCntl_SMTC                           0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S3_BCLKIOCntl                         0x0958

    #define     BA_Gbl_I2S3_BCLKIOCntl_DRV                     0x0958
    #define     B16Gbl_I2S3_BCLKIOCntl_DRV                     0x0958
    #define   LSb32Gbl_I2S3_BCLKIOCntl_DRV                        0
    #define   LSb16Gbl_I2S3_BCLKIOCntl_DRV                        0
    #define       bGbl_I2S3_BCLKIOCntl_DRV                     2
    #define   MSK32Gbl_I2S3_BCLKIOCntl_DRV                        0x00000003

    #define     BA_Gbl_I2S3_BCLKIOCntl_PDEN                    0x0958
    #define     B16Gbl_I2S3_BCLKIOCntl_PDEN                    0x0958
    #define   LSb32Gbl_I2S3_BCLKIOCntl_PDEN                       2
    #define   LSb16Gbl_I2S3_BCLKIOCntl_PDEN                       2
    #define       bGbl_I2S3_BCLKIOCntl_PDEN                    1
    #define   MSK32Gbl_I2S3_BCLKIOCntl_PDEN                       0x00000004

    #define     BA_Gbl_I2S3_BCLKIOCntl_PUEN                    0x0958
    #define     B16Gbl_I2S3_BCLKIOCntl_PUEN                    0x0958
    #define   LSb32Gbl_I2S3_BCLKIOCntl_PUEN                       3
    #define   LSb16Gbl_I2S3_BCLKIOCntl_PUEN                       3
    #define       bGbl_I2S3_BCLKIOCntl_PUEN                    1
    #define   MSK32Gbl_I2S3_BCLKIOCntl_PUEN                       0x00000008

    #define     BA_Gbl_I2S3_BCLKIOCntl_RXEN                    0x0958
    #define     B16Gbl_I2S3_BCLKIOCntl_RXEN                    0x0958
    #define   LSb32Gbl_I2S3_BCLKIOCntl_RXEN                       4
    #define   LSb16Gbl_I2S3_BCLKIOCntl_RXEN                       4
    #define       bGbl_I2S3_BCLKIOCntl_RXEN                    1
    #define   MSK32Gbl_I2S3_BCLKIOCntl_RXEN                       0x00000010

    #define     BA_Gbl_I2S3_BCLKIOCntl_SRC                     0x0958
    #define     B16Gbl_I2S3_BCLKIOCntl_SRC                     0x0958
    #define   LSb32Gbl_I2S3_BCLKIOCntl_SRC                        5
    #define   LSb16Gbl_I2S3_BCLKIOCntl_SRC                        5
    #define       bGbl_I2S3_BCLKIOCntl_SRC                     1
    #define   MSK32Gbl_I2S3_BCLKIOCntl_SRC                        0x00000020

    #define     BA_Gbl_I2S3_BCLKIOCntl_SMTC                    0x0958
    #define     B16Gbl_I2S3_BCLKIOCntl_SMTC                    0x0958
    #define   LSb32Gbl_I2S3_BCLKIOCntl_SMTC                       6
    #define   LSb16Gbl_I2S3_BCLKIOCntl_SMTC                       6
    #define       bGbl_I2S3_BCLKIOCntl_SMTC                    1
    #define   MSK32Gbl_I2S3_BCLKIOCntl_SMTC                       0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_I2S3_LRCKIOCntl                         0x095C

    #define     BA_Gbl_I2S3_LRCKIOCntl_DRV                     0x095C
    #define     B16Gbl_I2S3_LRCKIOCntl_DRV                     0x095C
    #define   LSb32Gbl_I2S3_LRCKIOCntl_DRV                        0
    #define   LSb16Gbl_I2S3_LRCKIOCntl_DRV                        0
    #define       bGbl_I2S3_LRCKIOCntl_DRV                     2
    #define   MSK32Gbl_I2S3_LRCKIOCntl_DRV                        0x00000003

    #define     BA_Gbl_I2S3_LRCKIOCntl_PDEN                    0x095C
    #define     B16Gbl_I2S3_LRCKIOCntl_PDEN                    0x095C
    #define   LSb32Gbl_I2S3_LRCKIOCntl_PDEN                       2
    #define   LSb16Gbl_I2S3_LRCKIOCntl_PDEN                       2
    #define       bGbl_I2S3_LRCKIOCntl_PDEN                    1
    #define   MSK32Gbl_I2S3_LRCKIOCntl_PDEN                       0x00000004

    #define     BA_Gbl_I2S3_LRCKIOCntl_PUEN                    0x095C
    #define     B16Gbl_I2S3_LRCKIOCntl_PUEN                    0x095C
    #define   LSb32Gbl_I2S3_LRCKIOCntl_PUEN                       3
    #define   LSb16Gbl_I2S3_LRCKIOCntl_PUEN                       3
    #define       bGbl_I2S3_LRCKIOCntl_PUEN                    1
    #define   MSK32Gbl_I2S3_LRCKIOCntl_PUEN                       0x00000008

    #define     BA_Gbl_I2S3_LRCKIOCntl_RXEN                    0x095C
    #define     B16Gbl_I2S3_LRCKIOCntl_RXEN                    0x095C
    #define   LSb32Gbl_I2S3_LRCKIOCntl_RXEN                       4
    #define   LSb16Gbl_I2S3_LRCKIOCntl_RXEN                       4
    #define       bGbl_I2S3_LRCKIOCntl_RXEN                    1
    #define   MSK32Gbl_I2S3_LRCKIOCntl_RXEN                       0x00000010

    #define     BA_Gbl_I2S3_LRCKIOCntl_SRC                     0x095C
    #define     B16Gbl_I2S3_LRCKIOCntl_SRC                     0x095C
    #define   LSb32Gbl_I2S3_LRCKIOCntl_SRC                        5
    #define   LSb16Gbl_I2S3_LRCKIOCntl_SRC                        5
    #define       bGbl_I2S3_LRCKIOCntl_SRC                     1
    #define   MSK32Gbl_I2S3_LRCKIOCntl_SRC                        0x00000020

    #define     BA_Gbl_I2S3_LRCKIOCntl_SMTC                    0x095C
    #define     B16Gbl_I2S3_LRCKIOCntl_SMTC                    0x095C
    #define   LSb32Gbl_I2S3_LRCKIOCntl_SMTC                       6
    #define   LSb16Gbl_I2S3_LRCKIOCntl_SMTC                       6
    #define       bGbl_I2S3_LRCKIOCntl_SMTC                    1
    #define   MSK32Gbl_I2S3_LRCKIOCntl_SMTC                       0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_DAT0Cntl                            0x0960

    #define     BA_Gbl_SD0_DAT0Cntl_DRV                        0x0960
    #define     B16Gbl_SD0_DAT0Cntl_DRV                        0x0960
    #define   LSb32Gbl_SD0_DAT0Cntl_DRV                           0
    #define   LSb16Gbl_SD0_DAT0Cntl_DRV                           0
    #define       bGbl_SD0_DAT0Cntl_DRV                        2
    #define   MSK32Gbl_SD0_DAT0Cntl_DRV                           0x00000003

    #define     BA_Gbl_SD0_DAT0Cntl_PDEN                       0x0960
    #define     B16Gbl_SD0_DAT0Cntl_PDEN                       0x0960
    #define   LSb32Gbl_SD0_DAT0Cntl_PDEN                          2
    #define   LSb16Gbl_SD0_DAT0Cntl_PDEN                          2
    #define       bGbl_SD0_DAT0Cntl_PDEN                       1
    #define   MSK32Gbl_SD0_DAT0Cntl_PDEN                          0x00000004

    #define     BA_Gbl_SD0_DAT0Cntl_PUEN                       0x0960
    #define     B16Gbl_SD0_DAT0Cntl_PUEN                       0x0960
    #define   LSb32Gbl_SD0_DAT0Cntl_PUEN                          3
    #define   LSb16Gbl_SD0_DAT0Cntl_PUEN                          3
    #define       bGbl_SD0_DAT0Cntl_PUEN                       1
    #define   MSK32Gbl_SD0_DAT0Cntl_PUEN                          0x00000008

    #define     BA_Gbl_SD0_DAT0Cntl_RXEN                       0x0960
    #define     B16Gbl_SD0_DAT0Cntl_RXEN                       0x0960
    #define   LSb32Gbl_SD0_DAT0Cntl_RXEN                          4
    #define   LSb16Gbl_SD0_DAT0Cntl_RXEN                          4
    #define       bGbl_SD0_DAT0Cntl_RXEN                       1
    #define   MSK32Gbl_SD0_DAT0Cntl_RXEN                          0x00000010

    #define     BA_Gbl_SD0_DAT0Cntl_SRC                        0x0960
    #define     B16Gbl_SD0_DAT0Cntl_SRC                        0x0960
    #define   LSb32Gbl_SD0_DAT0Cntl_SRC                           5
    #define   LSb16Gbl_SD0_DAT0Cntl_SRC                           5
    #define       bGbl_SD0_DAT0Cntl_SRC                        1
    #define   MSK32Gbl_SD0_DAT0Cntl_SRC                           0x00000020

    #define     BA_Gbl_SD0_DAT0Cntl_SMTC                       0x0960
    #define     B16Gbl_SD0_DAT0Cntl_SMTC                       0x0960
    #define   LSb32Gbl_SD0_DAT0Cntl_SMTC                          6
    #define   LSb16Gbl_SD0_DAT0Cntl_SMTC                          6
    #define       bGbl_SD0_DAT0Cntl_SMTC                       1
    #define   MSK32Gbl_SD0_DAT0Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_DAT1Cntl                            0x0964

    #define     BA_Gbl_SD0_DAT1Cntl_DRV                        0x0964
    #define     B16Gbl_SD0_DAT1Cntl_DRV                        0x0964
    #define   LSb32Gbl_SD0_DAT1Cntl_DRV                           0
    #define   LSb16Gbl_SD0_DAT1Cntl_DRV                           0
    #define       bGbl_SD0_DAT1Cntl_DRV                        2
    #define   MSK32Gbl_SD0_DAT1Cntl_DRV                           0x00000003

    #define     BA_Gbl_SD0_DAT1Cntl_PDEN                       0x0964
    #define     B16Gbl_SD0_DAT1Cntl_PDEN                       0x0964
    #define   LSb32Gbl_SD0_DAT1Cntl_PDEN                          2
    #define   LSb16Gbl_SD0_DAT1Cntl_PDEN                          2
    #define       bGbl_SD0_DAT1Cntl_PDEN                       1
    #define   MSK32Gbl_SD0_DAT1Cntl_PDEN                          0x00000004

    #define     BA_Gbl_SD0_DAT1Cntl_PUEN                       0x0964
    #define     B16Gbl_SD0_DAT1Cntl_PUEN                       0x0964
    #define   LSb32Gbl_SD0_DAT1Cntl_PUEN                          3
    #define   LSb16Gbl_SD0_DAT1Cntl_PUEN                          3
    #define       bGbl_SD0_DAT1Cntl_PUEN                       1
    #define   MSK32Gbl_SD0_DAT1Cntl_PUEN                          0x00000008

    #define     BA_Gbl_SD0_DAT1Cntl_RXEN                       0x0964
    #define     B16Gbl_SD0_DAT1Cntl_RXEN                       0x0964
    #define   LSb32Gbl_SD0_DAT1Cntl_RXEN                          4
    #define   LSb16Gbl_SD0_DAT1Cntl_RXEN                          4
    #define       bGbl_SD0_DAT1Cntl_RXEN                       1
    #define   MSK32Gbl_SD0_DAT1Cntl_RXEN                          0x00000010

    #define     BA_Gbl_SD0_DAT1Cntl_SRC                        0x0964
    #define     B16Gbl_SD0_DAT1Cntl_SRC                        0x0964
    #define   LSb32Gbl_SD0_DAT1Cntl_SRC                           5
    #define   LSb16Gbl_SD0_DAT1Cntl_SRC                           5
    #define       bGbl_SD0_DAT1Cntl_SRC                        1
    #define   MSK32Gbl_SD0_DAT1Cntl_SRC                           0x00000020

    #define     BA_Gbl_SD0_DAT1Cntl_SMTC                       0x0964
    #define     B16Gbl_SD0_DAT1Cntl_SMTC                       0x0964
    #define   LSb32Gbl_SD0_DAT1Cntl_SMTC                          6
    #define   LSb16Gbl_SD0_DAT1Cntl_SMTC                          6
    #define       bGbl_SD0_DAT1Cntl_SMTC                       1
    #define   MSK32Gbl_SD0_DAT1Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_CLKCntl                             0x0968

    #define     BA_Gbl_SD0_CLKCntl_DRV                         0x0968
    #define     B16Gbl_SD0_CLKCntl_DRV                         0x0968
    #define   LSb32Gbl_SD0_CLKCntl_DRV                            0
    #define   LSb16Gbl_SD0_CLKCntl_DRV                            0
    #define       bGbl_SD0_CLKCntl_DRV                         2
    #define   MSK32Gbl_SD0_CLKCntl_DRV                            0x00000003

    #define     BA_Gbl_SD0_CLKCntl_PDEN                        0x0968
    #define     B16Gbl_SD0_CLKCntl_PDEN                        0x0968
    #define   LSb32Gbl_SD0_CLKCntl_PDEN                           2
    #define   LSb16Gbl_SD0_CLKCntl_PDEN                           2
    #define       bGbl_SD0_CLKCntl_PDEN                        1
    #define   MSK32Gbl_SD0_CLKCntl_PDEN                           0x00000004

    #define     BA_Gbl_SD0_CLKCntl_PUEN                        0x0968
    #define     B16Gbl_SD0_CLKCntl_PUEN                        0x0968
    #define   LSb32Gbl_SD0_CLKCntl_PUEN                           3
    #define   LSb16Gbl_SD0_CLKCntl_PUEN                           3
    #define       bGbl_SD0_CLKCntl_PUEN                        1
    #define   MSK32Gbl_SD0_CLKCntl_PUEN                           0x00000008

    #define     BA_Gbl_SD0_CLKCntl_RXEN                        0x0968
    #define     B16Gbl_SD0_CLKCntl_RXEN                        0x0968
    #define   LSb32Gbl_SD0_CLKCntl_RXEN                           4
    #define   LSb16Gbl_SD0_CLKCntl_RXEN                           4
    #define       bGbl_SD0_CLKCntl_RXEN                        1
    #define   MSK32Gbl_SD0_CLKCntl_RXEN                           0x00000010

    #define     BA_Gbl_SD0_CLKCntl_SRC                         0x0968
    #define     B16Gbl_SD0_CLKCntl_SRC                         0x0968
    #define   LSb32Gbl_SD0_CLKCntl_SRC                            5
    #define   LSb16Gbl_SD0_CLKCntl_SRC                            5
    #define       bGbl_SD0_CLKCntl_SRC                         1
    #define   MSK32Gbl_SD0_CLKCntl_SRC                            0x00000020

    #define     BA_Gbl_SD0_CLKCntl_SMTC                        0x0968
    #define     B16Gbl_SD0_CLKCntl_SMTC                        0x0968
    #define   LSb32Gbl_SD0_CLKCntl_SMTC                           6
    #define   LSb16Gbl_SD0_CLKCntl_SMTC                           6
    #define       bGbl_SD0_CLKCntl_SMTC                        1
    #define   MSK32Gbl_SD0_CLKCntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_DAT2Cntl                            0x096C

    #define     BA_Gbl_SD0_DAT2Cntl_DRV                        0x096C
    #define     B16Gbl_SD0_DAT2Cntl_DRV                        0x096C
    #define   LSb32Gbl_SD0_DAT2Cntl_DRV                           0
    #define   LSb16Gbl_SD0_DAT2Cntl_DRV                           0
    #define       bGbl_SD0_DAT2Cntl_DRV                        2
    #define   MSK32Gbl_SD0_DAT2Cntl_DRV                           0x00000003

    #define     BA_Gbl_SD0_DAT2Cntl_PDEN                       0x096C
    #define     B16Gbl_SD0_DAT2Cntl_PDEN                       0x096C
    #define   LSb32Gbl_SD0_DAT2Cntl_PDEN                          2
    #define   LSb16Gbl_SD0_DAT2Cntl_PDEN                          2
    #define       bGbl_SD0_DAT2Cntl_PDEN                       1
    #define   MSK32Gbl_SD0_DAT2Cntl_PDEN                          0x00000004

    #define     BA_Gbl_SD0_DAT2Cntl_PUEN                       0x096C
    #define     B16Gbl_SD0_DAT2Cntl_PUEN                       0x096C
    #define   LSb32Gbl_SD0_DAT2Cntl_PUEN                          3
    #define   LSb16Gbl_SD0_DAT2Cntl_PUEN                          3
    #define       bGbl_SD0_DAT2Cntl_PUEN                       1
    #define   MSK32Gbl_SD0_DAT2Cntl_PUEN                          0x00000008

    #define     BA_Gbl_SD0_DAT2Cntl_RXEN                       0x096C
    #define     B16Gbl_SD0_DAT2Cntl_RXEN                       0x096C
    #define   LSb32Gbl_SD0_DAT2Cntl_RXEN                          4
    #define   LSb16Gbl_SD0_DAT2Cntl_RXEN                          4
    #define       bGbl_SD0_DAT2Cntl_RXEN                       1
    #define   MSK32Gbl_SD0_DAT2Cntl_RXEN                          0x00000010

    #define     BA_Gbl_SD0_DAT2Cntl_SRC                        0x096C
    #define     B16Gbl_SD0_DAT2Cntl_SRC                        0x096C
    #define   LSb32Gbl_SD0_DAT2Cntl_SRC                           5
    #define   LSb16Gbl_SD0_DAT2Cntl_SRC                           5
    #define       bGbl_SD0_DAT2Cntl_SRC                        1
    #define   MSK32Gbl_SD0_DAT2Cntl_SRC                           0x00000020

    #define     BA_Gbl_SD0_DAT2Cntl_SMTC                       0x096C
    #define     B16Gbl_SD0_DAT2Cntl_SMTC                       0x096C
    #define   LSb32Gbl_SD0_DAT2Cntl_SMTC                          6
    #define   LSb16Gbl_SD0_DAT2Cntl_SMTC                          6
    #define       bGbl_SD0_DAT2Cntl_SMTC                       1
    #define   MSK32Gbl_SD0_DAT2Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_DAT3Cntl                            0x0970

    #define     BA_Gbl_SD0_DAT3Cntl_DRV                        0x0970
    #define     B16Gbl_SD0_DAT3Cntl_DRV                        0x0970
    #define   LSb32Gbl_SD0_DAT3Cntl_DRV                           0
    #define   LSb16Gbl_SD0_DAT3Cntl_DRV                           0
    #define       bGbl_SD0_DAT3Cntl_DRV                        2
    #define   MSK32Gbl_SD0_DAT3Cntl_DRV                           0x00000003

    #define     BA_Gbl_SD0_DAT3Cntl_PDEN                       0x0970
    #define     B16Gbl_SD0_DAT3Cntl_PDEN                       0x0970
    #define   LSb32Gbl_SD0_DAT3Cntl_PDEN                          2
    #define   LSb16Gbl_SD0_DAT3Cntl_PDEN                          2
    #define       bGbl_SD0_DAT3Cntl_PDEN                       1
    #define   MSK32Gbl_SD0_DAT3Cntl_PDEN                          0x00000004

    #define     BA_Gbl_SD0_DAT3Cntl_PUEN                       0x0970
    #define     B16Gbl_SD0_DAT3Cntl_PUEN                       0x0970
    #define   LSb32Gbl_SD0_DAT3Cntl_PUEN                          3
    #define   LSb16Gbl_SD0_DAT3Cntl_PUEN                          3
    #define       bGbl_SD0_DAT3Cntl_PUEN                       1
    #define   MSK32Gbl_SD0_DAT3Cntl_PUEN                          0x00000008

    #define     BA_Gbl_SD0_DAT3Cntl_RXEN                       0x0970
    #define     B16Gbl_SD0_DAT3Cntl_RXEN                       0x0970
    #define   LSb32Gbl_SD0_DAT3Cntl_RXEN                          4
    #define   LSb16Gbl_SD0_DAT3Cntl_RXEN                          4
    #define       bGbl_SD0_DAT3Cntl_RXEN                       1
    #define   MSK32Gbl_SD0_DAT3Cntl_RXEN                          0x00000010

    #define     BA_Gbl_SD0_DAT3Cntl_SRC                        0x0970
    #define     B16Gbl_SD0_DAT3Cntl_SRC                        0x0970
    #define   LSb32Gbl_SD0_DAT3Cntl_SRC                           5
    #define   LSb16Gbl_SD0_DAT3Cntl_SRC                           5
    #define       bGbl_SD0_DAT3Cntl_SRC                        1
    #define   MSK32Gbl_SD0_DAT3Cntl_SRC                           0x00000020

    #define     BA_Gbl_SD0_DAT3Cntl_SMTC                       0x0970
    #define     B16Gbl_SD0_DAT3Cntl_SMTC                       0x0970
    #define   LSb32Gbl_SD0_DAT3Cntl_SMTC                          6
    #define   LSb16Gbl_SD0_DAT3Cntl_SMTC                          6
    #define       bGbl_SD0_DAT3Cntl_SMTC                       1
    #define   MSK32Gbl_SD0_DAT3Cntl_SMTC                          0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_CMDCntl                             0x0974

    #define     BA_Gbl_SD0_CMDCntl_DRV                         0x0974
    #define     B16Gbl_SD0_CMDCntl_DRV                         0x0974
    #define   LSb32Gbl_SD0_CMDCntl_DRV                            0
    #define   LSb16Gbl_SD0_CMDCntl_DRV                            0
    #define       bGbl_SD0_CMDCntl_DRV                         2
    #define   MSK32Gbl_SD0_CMDCntl_DRV                            0x00000003

    #define     BA_Gbl_SD0_CMDCntl_PDEN                        0x0974
    #define     B16Gbl_SD0_CMDCntl_PDEN                        0x0974
    #define   LSb32Gbl_SD0_CMDCntl_PDEN                           2
    #define   LSb16Gbl_SD0_CMDCntl_PDEN                           2
    #define       bGbl_SD0_CMDCntl_PDEN                        1
    #define   MSK32Gbl_SD0_CMDCntl_PDEN                           0x00000004

    #define     BA_Gbl_SD0_CMDCntl_PUEN                        0x0974
    #define     B16Gbl_SD0_CMDCntl_PUEN                        0x0974
    #define   LSb32Gbl_SD0_CMDCntl_PUEN                           3
    #define   LSb16Gbl_SD0_CMDCntl_PUEN                           3
    #define       bGbl_SD0_CMDCntl_PUEN                        1
    #define   MSK32Gbl_SD0_CMDCntl_PUEN                           0x00000008

    #define     BA_Gbl_SD0_CMDCntl_RXEN                        0x0974
    #define     B16Gbl_SD0_CMDCntl_RXEN                        0x0974
    #define   LSb32Gbl_SD0_CMDCntl_RXEN                           4
    #define   LSb16Gbl_SD0_CMDCntl_RXEN                           4
    #define       bGbl_SD0_CMDCntl_RXEN                        1
    #define   MSK32Gbl_SD0_CMDCntl_RXEN                           0x00000010

    #define     BA_Gbl_SD0_CMDCntl_SRC                         0x0974
    #define     B16Gbl_SD0_CMDCntl_SRC                         0x0974
    #define   LSb32Gbl_SD0_CMDCntl_SRC                            5
    #define   LSb16Gbl_SD0_CMDCntl_SRC                            5
    #define       bGbl_SD0_CMDCntl_SRC                         1
    #define   MSK32Gbl_SD0_CMDCntl_SRC                            0x00000020

    #define     BA_Gbl_SD0_CMDCntl_SMTC                        0x0974
    #define     B16Gbl_SD0_CMDCntl_SMTC                        0x0974
    #define   LSb32Gbl_SD0_CMDCntl_SMTC                           6
    #define   LSb16Gbl_SD0_CMDCntl_SMTC                           6
    #define       bGbl_SD0_CMDCntl_SMTC                        1
    #define   MSK32Gbl_SD0_CMDCntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_CDnCntl                             0x0978

    #define     BA_Gbl_SD0_CDnCntl_DRV                         0x0978
    #define     B16Gbl_SD0_CDnCntl_DRV                         0x0978
    #define   LSb32Gbl_SD0_CDnCntl_DRV                            0
    #define   LSb16Gbl_SD0_CDnCntl_DRV                            0
    #define       bGbl_SD0_CDnCntl_DRV                         2
    #define   MSK32Gbl_SD0_CDnCntl_DRV                            0x00000003

    #define     BA_Gbl_SD0_CDnCntl_PDEN                        0x0978
    #define     B16Gbl_SD0_CDnCntl_PDEN                        0x0978
    #define   LSb32Gbl_SD0_CDnCntl_PDEN                           2
    #define   LSb16Gbl_SD0_CDnCntl_PDEN                           2
    #define       bGbl_SD0_CDnCntl_PDEN                        1
    #define   MSK32Gbl_SD0_CDnCntl_PDEN                           0x00000004

    #define     BA_Gbl_SD0_CDnCntl_PUEN                        0x0978
    #define     B16Gbl_SD0_CDnCntl_PUEN                        0x0978
    #define   LSb32Gbl_SD0_CDnCntl_PUEN                           3
    #define   LSb16Gbl_SD0_CDnCntl_PUEN                           3
    #define       bGbl_SD0_CDnCntl_PUEN                        1
    #define   MSK32Gbl_SD0_CDnCntl_PUEN                           0x00000008

    #define     BA_Gbl_SD0_CDnCntl_RXEN                        0x0978
    #define     B16Gbl_SD0_CDnCntl_RXEN                        0x0978
    #define   LSb32Gbl_SD0_CDnCntl_RXEN                           4
    #define   LSb16Gbl_SD0_CDnCntl_RXEN                           4
    #define       bGbl_SD0_CDnCntl_RXEN                        1
    #define   MSK32Gbl_SD0_CDnCntl_RXEN                           0x00000010

    #define     BA_Gbl_SD0_CDnCntl_SRC                         0x0978
    #define     B16Gbl_SD0_CDnCntl_SRC                         0x0978
    #define   LSb32Gbl_SD0_CDnCntl_SRC                            5
    #define   LSb16Gbl_SD0_CDnCntl_SRC                            5
    #define       bGbl_SD0_CDnCntl_SRC                         1
    #define   MSK32Gbl_SD0_CDnCntl_SRC                            0x00000020

    #define     BA_Gbl_SD0_CDnCntl_SMTC                        0x0978
    #define     B16Gbl_SD0_CDnCntl_SMTC                        0x0978
    #define   LSb32Gbl_SD0_CDnCntl_SMTC                           6
    #define   LSb16Gbl_SD0_CDnCntl_SMTC                           6
    #define       bGbl_SD0_CDnCntl_SMTC                        1
    #define   MSK32Gbl_SD0_CDnCntl_SMTC                           0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_Gbl_SD0_WPCntl                              0x097C

    #define     BA_Gbl_SD0_WPCntl_DRV                          0x097C
    #define     B16Gbl_SD0_WPCntl_DRV                          0x097C
    #define   LSb32Gbl_SD0_WPCntl_DRV                             0
    #define   LSb16Gbl_SD0_WPCntl_DRV                             0
    #define       bGbl_SD0_WPCntl_DRV                          2
    #define   MSK32Gbl_SD0_WPCntl_DRV                             0x00000003

    #define     BA_Gbl_SD0_WPCntl_PDEN                         0x097C
    #define     B16Gbl_SD0_WPCntl_PDEN                         0x097C
    #define   LSb32Gbl_SD0_WPCntl_PDEN                            2
    #define   LSb16Gbl_SD0_WPCntl_PDEN                            2
    #define       bGbl_SD0_WPCntl_PDEN                         1
    #define   MSK32Gbl_SD0_WPCntl_PDEN                            0x00000004

    #define     BA_Gbl_SD0_WPCntl_PUEN                         0x097C
    #define     B16Gbl_SD0_WPCntl_PUEN                         0x097C
    #define   LSb32Gbl_SD0_WPCntl_PUEN                            3
    #define   LSb16Gbl_SD0_WPCntl_PUEN                            3
    #define       bGbl_SD0_WPCntl_PUEN                         1
    #define   MSK32Gbl_SD0_WPCntl_PUEN                            0x00000008

    #define     BA_Gbl_SD0_WPCntl_RXEN                         0x097C
    #define     B16Gbl_SD0_WPCntl_RXEN                         0x097C
    #define   LSb32Gbl_SD0_WPCntl_RXEN                            4
    #define   LSb16Gbl_SD0_WPCntl_RXEN                            4
    #define       bGbl_SD0_WPCntl_RXEN                         1
    #define   MSK32Gbl_SD0_WPCntl_RXEN                            0x00000010

    #define     BA_Gbl_SD0_WPCntl_SRC                          0x097C
    #define     B16Gbl_SD0_WPCntl_SRC                          0x097C
    #define   LSb32Gbl_SD0_WPCntl_SRC                             5
    #define   LSb16Gbl_SD0_WPCntl_SRC                             5
    #define       bGbl_SD0_WPCntl_SRC                          1
    #define   MSK32Gbl_SD0_WPCntl_SRC                             0x00000020

    #define     BA_Gbl_SD0_WPCntl_SMTC                         0x097C
    #define     B16Gbl_SD0_WPCntl_SMTC                         0x097C
    #define   LSb32Gbl_SD0_WPCntl_SMTC                            6
    #define   LSb16Gbl_SD0_WPCntl_SMTC                            6
    #define       bGbl_SD0_WPCntl_SMTC                         1
    #define   MSK32Gbl_SD0_WPCntl_SMTC                            0x00000040
    ///////////////////////////////////////////////////////////

    typedef struct SIE_Gbl {
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_ProductId_Id(r32)                       _BFGET_(r32,31, 0)
    #define   SET32Gbl_ProductId_Id(r32,v)                     _BFSET_(r32,31, 0,v)

    #define     w32Gbl_ProductId                               {\
            UNSG32 uProductId_Id                               : 32;\
          }
    union { UNSG32 u32Gbl_ProductId;
            struct w32Gbl_ProductId;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_ProductId_ext_ID_EXT(r32)               _BFGET_(r32, 7, 0)
    #define   SET32Gbl_ProductId_ext_ID_EXT(r32,v)             _BFSET_(r32, 7, 0,v)
    #define   GET16Gbl_ProductId_ext_ID_EXT(r16)               _BFGET_(r16, 7, 0)
    #define   SET16Gbl_ProductId_ext_ID_EXT(r16,v)             _BFSET_(r16, 7, 0,v)

    #define     w32Gbl_ProductId_ext                           {\
            UNSG32 uProductId_ext_ID_EXT                       :  8;\
            UNSG32 RSVDx4_b8                                   : 24;\
          }
    union { UNSG32 u32Gbl_ProductId_ext;
            struct w32Gbl_ProductId_ext;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_INT_ID_VALUE(r32)                       _BFGET_(r32, 7, 0)
    #define   SET32Gbl_INT_ID_VALUE(r32,v)                     _BFSET_(r32, 7, 0,v)
    #define   GET16Gbl_INT_ID_VALUE(r16)                       _BFGET_(r16, 7, 0)
    #define   SET16Gbl_INT_ID_VALUE(r16,v)                     _BFSET_(r16, 7, 0,v)

    #define     w32Gbl_INT_ID                                  {\
            UNSG32 uINT_ID_VALUE                               :  8;\
            UNSG32 RSVDx8_b8                                   : 24;\
          }
    union { UNSG32 u32Gbl_INT_ID;
            struct w32Gbl_INT_ID;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_bootStrap_softwareStrap(r32)            _BFGET_(r32,15, 0)
    #define   SET32Gbl_bootStrap_softwareStrap(r32,v)          _BFSET_(r32,15, 0,v)
    #define   GET16Gbl_bootStrap_softwareStrap(r16)            _BFGET_(r16,15, 0)
    #define   SET16Gbl_bootStrap_softwareStrap(r16,v)          _BFSET_(r16,15, 0,v)

    #define   GET32Gbl_bootStrap_bootSrc(r32)                  _BFGET_(r32,17,16)
    #define   SET32Gbl_bootStrap_bootSrc(r32,v)                _BFSET_(r32,17,16,v)
    #define   GET16Gbl_bootStrap_bootSrc(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_bootStrap_bootSrc(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_bootStrap_cpuRstByps(r32)               _BFGET_(r32,18,18)
    #define   SET32Gbl_bootStrap_cpuRstByps(r32,v)             _BFSET_(r32,18,18,v)
    #define   GET16Gbl_bootStrap_cpuRstByps(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_bootStrap_cpuRstByps(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_bootStrap_pllPwrDown(r32)               _BFGET_(r32,19,19)
    #define   SET32Gbl_bootStrap_pllPwrDown(r32,v)             _BFSET_(r32,19,19,v)
    #define   GET16Gbl_bootStrap_pllPwrDown(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_bootStrap_pllPwrDown(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_bootStrap_sysPllByps(r32)               _BFGET_(r32,20,20)
    #define   SET32Gbl_bootStrap_sysPllByps(r32,v)             _BFSET_(r32,20,20,v)
    #define   GET16Gbl_bootStrap_sysPllByps(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_bootStrap_sysPllByps(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_bootStrap_memPllByps(r32)               _BFGET_(r32,21,21)
    #define   SET32Gbl_bootStrap_memPllByps(r32,v)             _BFSET_(r32,21,21,v)
    #define   GET16Gbl_bootStrap_memPllByps(r16)               _BFGET_(r16, 5, 5)
    #define   SET16Gbl_bootStrap_memPllByps(r16,v)             _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_bootStrap_cpuPllByps(r32)               _BFGET_(r32,22,22)
    #define   SET32Gbl_bootStrap_cpuPllByps(r32,v)             _BFSET_(r32,22,22,v)
    #define   GET16Gbl_bootStrap_cpuPllByps(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_bootStrap_cpuPllByps(r16,v)             _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_bootStrap_ENG_EN(r32)                   _BFGET_(r32,23,23)
    #define   SET32Gbl_bootStrap_ENG_EN(r32,v)                 _BFSET_(r32,23,23,v)
    #define   GET16Gbl_bootStrap_ENG_EN(r16)                   _BFGET_(r16, 7, 7)
    #define   SET16Gbl_bootStrap_ENG_EN(r16,v)                 _BFSET_(r16, 7, 7,v)

    #define   GET32Gbl_bootStrap_LEGACY_BOOT(r32)              _BFGET_(r32,24,24)
    #define   SET32Gbl_bootStrap_LEGACY_BOOT(r32,v)            _BFSET_(r32,24,24,v)
    #define   GET16Gbl_bootStrap_LEGACY_BOOT(r16)              _BFGET_(r16, 8, 8)
    #define   SET16Gbl_bootStrap_LEGACY_BOOT(r16,v)            _BFSET_(r16, 8, 8,v)

    #define     w32Gbl_bootStrap                               {\
            UNSG32 ubootStrap_softwareStrap                    : 16;\
            UNSG32 ubootStrap_bootSrc                          :  2;\
            UNSG32 ubootStrap_cpuRstByps                       :  1;\
            UNSG32 ubootStrap_pllPwrDown                       :  1;\
            UNSG32 ubootStrap_sysPllByps                       :  1;\
            UNSG32 ubootStrap_memPllByps                       :  1;\
            UNSG32 ubootStrap_cpuPllByps                       :  1;\
            UNSG32 ubootStrap_ENG_EN                           :  1;\
            UNSG32 ubootStrap_LEGACY_BOOT                      :  1;\
            UNSG32 RSVDxC_b25                                  :  7;\
          }
    union { UNSG32 u32Gbl_bootStrap;
            struct w32Gbl_bootStrap;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_bootStrapEn_cpuRstBypsEn(r32)           _BFGET_(r32, 0, 0)
    #define   SET32Gbl_bootStrapEn_cpuRstBypsEn(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_bootStrapEn_cpuRstBypsEn(r16)           _BFGET_(r16, 0, 0)
    #define   SET16Gbl_bootStrapEn_cpuRstBypsEn(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_bootStrapEn_pllPwrDownEn(r32)           _BFGET_(r32, 1, 1)
    #define   SET32Gbl_bootStrapEn_pllPwrDownEn(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_bootStrapEn_pllPwrDownEn(r16)           _BFGET_(r16, 1, 1)
    #define   SET16Gbl_bootStrapEn_pllPwrDownEn(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_bootStrapEn_sysPLLBypsEn(r32)           _BFGET_(r32, 2, 2)
    #define   SET32Gbl_bootStrapEn_sysPLLBypsEn(r32,v)         _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_bootStrapEn_sysPLLBypsEn(r16)           _BFGET_(r16, 2, 2)
    #define   SET16Gbl_bootStrapEn_sysPLLBypsEn(r16,v)         _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_bootStrapEn_memPLLBypsEn(r32)           _BFGET_(r32, 3, 3)
    #define   SET32Gbl_bootStrapEn_memPLLBypsEn(r32,v)         _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_bootStrapEn_memPLLBypsEn(r16)           _BFGET_(r16, 3, 3)
    #define   SET16Gbl_bootStrapEn_memPLLBypsEn(r16,v)         _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_bootStrapEn_cpuPLLBypsEn(r32)           _BFGET_(r32, 4, 4)
    #define   SET32Gbl_bootStrapEn_cpuPLLBypsEn(r32,v)         _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_bootStrapEn_cpuPLLBypsEn(r16)           _BFGET_(r16, 4, 4)
    #define   SET16Gbl_bootStrapEn_cpuPLLBypsEn(r16,v)         _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_bootStrapEn_legacyBootEn(r32)           _BFGET_(r32, 5, 5)
    #define   SET32Gbl_bootStrapEn_legacyBootEn(r32,v)         _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_bootStrapEn_legacyBootEn(r16)           _BFGET_(r16, 5, 5)
    #define   SET16Gbl_bootStrapEn_legacyBootEn(r16,v)         _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_bootStrapEn                             {\
            UNSG32 ubootStrapEn_cpuRstBypsEn                   :  1;\
            UNSG32 ubootStrapEn_pllPwrDownEn                   :  1;\
            UNSG32 ubootStrapEn_sysPLLBypsEn                   :  1;\
            UNSG32 ubootStrapEn_memPLLBypsEn                   :  1;\
            UNSG32 ubootStrapEn_cpuPLLBypsEn                   :  1;\
            UNSG32 ubootStrapEn_legacyBootEn                   :  1;\
            UNSG32 RSVDx10_b6                                  : 26;\
          }
    union { UNSG32 u32Gbl_bootStrapEn;
            struct w32Gbl_bootStrapEn;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_pkgSel_DDR32bit(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32Gbl_pkgSel_DDR32bit(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_pkgSel_DDR32bit(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16Gbl_pkgSel_DDR32bit(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_pkgSel_reserved(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32Gbl_pkgSel_reserved(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_pkgSel_reserved(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16Gbl_pkgSel_reserved(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_pkgSel                                  {\
            UNSG32 upkgSel_DDR32bit                            :  1;\
            UNSG32 upkgSel_reserved                            :  1;\
            UNSG32 RSVDx14_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_pkgSel;
            struct w32Gbl_pkgSel;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_chipCntl_SD0_CLK_LPBK_EN(r32)           _BFGET_(r32, 0, 0)
    #define   SET32Gbl_chipCntl_SD0_CLK_LPBK_EN(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_chipCntl_SD0_CLK_LPBK_EN(r16)           _BFGET_(r16, 0, 0)
    #define   SET16Gbl_chipCntl_SD0_CLK_LPBK_EN(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_chipCntl_SD0_CLK_LPBK_SEL(r32)          _BFGET_(r32, 1, 1)
    #define   SET32Gbl_chipCntl_SD0_CLK_LPBK_SEL(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_chipCntl_SD0_CLK_LPBK_SEL(r16)          _BFGET_(r16, 1, 1)
    #define   SET16Gbl_chipCntl_SD0_CLK_LPBK_SEL(r16,v)        _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_chipCntl_EMMC_CLK_LPBK_EN(r32)          _BFGET_(r32, 2, 2)
    #define   SET32Gbl_chipCntl_EMMC_CLK_LPBK_EN(r32,v)        _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_chipCntl_EMMC_CLK_LPBK_EN(r16)          _BFGET_(r16, 2, 2)
    #define   SET16Gbl_chipCntl_EMMC_CLK_LPBK_EN(r16,v)        _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_chipCntl_EMMC_CLK_LPBK_SEL(r32)         _BFGET_(r32, 3, 3)
    #define   SET32Gbl_chipCntl_EMMC_CLK_LPBK_SEL(r32,v)       _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_chipCntl_EMMC_CLK_LPBK_SEL(r16)         _BFGET_(r16, 3, 3)
    #define   SET16Gbl_chipCntl_EMMC_CLK_LPBK_SEL(r16,v)       _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_chipCntl_I2S_FB_SEL(r32)                _BFGET_(r32,13, 4)
    #define   SET32Gbl_chipCntl_I2S_FB_SEL(r32,v)              _BFSET_(r32,13, 4,v)
    #define   GET16Gbl_chipCntl_I2S_FB_SEL(r16)                _BFGET_(r16,13, 4)
    #define   SET16Gbl_chipCntl_I2S_FB_SEL(r16,v)              _BFSET_(r16,13, 4,v)

    #define   GET32Gbl_chipCntl_SPDIFI_SEL(r32)                _BFGET_(r32,16,14)
    #define   SET32Gbl_chipCntl_SPDIFI_SEL(r32,v)              _BFSET_(r32,16,14,v)

    #define   GET32Gbl_chipCntl_TW1_SEL(r32)                   _BFGET_(r32,17,17)
    #define   SET32Gbl_chipCntl_TW1_SEL(r32,v)                 _BFSET_(r32,17,17,v)
    #define   GET16Gbl_chipCntl_TW1_SEL(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16Gbl_chipCntl_TW1_SEL(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_chipCntl_DBG_SEL(r32)                   _BFGET_(r32,20,18)
    #define   SET32Gbl_chipCntl_DBG_SEL(r32,v)                 _BFSET_(r32,20,18,v)
    #define   GET16Gbl_chipCntl_DBG_SEL(r16)                   _BFGET_(r16, 4, 2)
    #define   SET16Gbl_chipCntl_DBG_SEL(r16,v)                 _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_chipCntl_CLK_DBG_SEL(r32)               _BFGET_(r32,21,21)
    #define   SET32Gbl_chipCntl_CLK_DBG_SEL(r32,v)             _BFSET_(r32,21,21,v)
    #define   GET16Gbl_chipCntl_CLK_DBG_SEL(r16)               _BFGET_(r16, 5, 5)
    #define   SET16Gbl_chipCntl_CLK_DBG_SEL(r16,v)             _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_chipCntl_SD0_CDn_SEL(r32)               _BFGET_(r32,22,22)
    #define   SET32Gbl_chipCntl_SD0_CDn_SEL(r32,v)             _BFSET_(r32,22,22,v)
    #define   GET16Gbl_chipCntl_SD0_CDn_SEL(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_chipCntl_SD0_CDn_SEL(r16,v)             _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_chipCntl_SD0_WP_SEL(r32)                _BFGET_(r32,23,23)
    #define   SET32Gbl_chipCntl_SD0_WP_SEL(r32,v)              _BFSET_(r32,23,23,v)
    #define   GET16Gbl_chipCntl_SD0_WP_SEL(r16)                _BFGET_(r16, 7, 7)
    #define   SET16Gbl_chipCntl_SD0_WP_SEL(r16,v)              _BFSET_(r16, 7, 7,v)

    #define     w32Gbl_chipCntl                                {\
            UNSG32 uchipCntl_SD0_CLK_LPBK_EN                   :  1;\
            UNSG32 uchipCntl_SD0_CLK_LPBK_SEL                  :  1;\
            UNSG32 uchipCntl_EMMC_CLK_LPBK_EN                  :  1;\
            UNSG32 uchipCntl_EMMC_CLK_LPBK_SEL                 :  1;\
            UNSG32 uchipCntl_I2S_FB_SEL                        : 10;\
            UNSG32 uchipCntl_SPDIFI_SEL                        :  3;\
            UNSG32 uchipCntl_TW1_SEL                           :  1;\
            UNSG32 uchipCntl_DBG_SEL                           :  3;\
            UNSG32 uchipCntl_CLK_DBG_SEL                       :  1;\
            UNSG32 uchipCntl_SD0_CDn_SEL                       :  1;\
            UNSG32 uchipCntl_SD0_WP_SEL                        :  1;\
            UNSG32 RSVDx18_b24                                 :  8;\
          }
    union { UNSG32 u32Gbl_chipCntl;
            struct w32Gbl_chipCntl;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1C                                     [4];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_sw_generic0_swReg0(r32)                 _BFGET_(r32,31, 0)
    #define   SET32Gbl_sw_generic0_swReg0(r32,v)               _BFSET_(r32,31, 0,v)

    #define     w32Gbl_sw_generic0                             {\
            UNSG32 usw_generic0_swReg0                         : 32;\
          }
    union { UNSG32 u32Gbl_sw_generic0;
            struct w32Gbl_sw_generic0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_sw_generic1_swReg1(r32)                 _BFGET_(r32,31, 0)
    #define   SET32Gbl_sw_generic1_swReg1(r32,v)               _BFSET_(r32,31, 0,v)

    #define     w32Gbl_sw_generic1                             {\
            UNSG32 usw_generic1_swReg1                         : 32;\
          }
    union { UNSG32 u32Gbl_sw_generic1;
            struct w32Gbl_sw_generic1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_sw_generic2_swReg2(r32)                 _BFGET_(r32,31, 0)
    #define   SET32Gbl_sw_generic2_swReg2(r32,v)               _BFSET_(r32,31, 0,v)

    #define     w32Gbl_sw_generic2                             {\
            UNSG32 usw_generic2_swReg2                         : 32;\
          }
    union { UNSG32 u32Gbl_sw_generic2;
            struct w32Gbl_sw_generic2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_sw_generic3_swReg3(r32)                 _BFGET_(r32,31, 0)
    #define   SET32Gbl_sw_generic3_swReg3(r32,v)               _BFSET_(r32,31, 0,v)

    #define     w32Gbl_sw_generic3                             {\
            UNSG32 usw_generic3_swReg3                         : 32;\
          }
    union { UNSG32 u32Gbl_sw_generic3;
            struct w32Gbl_sw_generic3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_RWTC_top31to0_value(r32)                _BFGET_(r32,31, 0)
    #define   SET32Gbl_RWTC_top31to0_value(r32,v)              _BFSET_(r32,31, 0,v)

    #define     w32Gbl_RWTC_top31to0                           {\
            UNSG32 uRWTC_top31to0_value                        : 32;\
          }
    union { UNSG32 u32Gbl_RWTC_top31to0;
            struct w32Gbl_RWTC_top31to0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_RWTC_top63to32_value(r32)               _BFGET_(r32,31, 0)
    #define   SET32Gbl_RWTC_top63to32_value(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32Gbl_RWTC_top63to32                          {\
            UNSG32 uRWTC_top63to32_value                       : 32;\
          }
    union { UNSG32 u32Gbl_RWTC_top63to32;
            struct w32Gbl_RWTC_top63to32;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_RWTC_top67to64_value(r32)               _BFGET_(r32, 3, 0)
    #define   SET32Gbl_RWTC_top67to64_value(r32,v)             _BFSET_(r32, 3, 0,v)
    #define   GET16Gbl_RWTC_top67to64_value(r16)               _BFGET_(r16, 3, 0)
    #define   SET16Gbl_RWTC_top67to64_value(r16,v)             _BFSET_(r16, 3, 0,v)

    #define     w32Gbl_RWTC_top67to64                          {\
            UNSG32 uRWTC_top67to64_value                       :  4;\
            UNSG32 RSVDx38_b4                                  : 28;\
          }
    union { UNSG32 u32Gbl_RWTC_top67to64;
            struct w32Gbl_RWTC_top67to64;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx3C                                     [16];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_USB2_value(r32)           _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_USB2_value(r32,v)         _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_USB2_value(r16)           _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_USB2_value(r16,v)         _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_USB2                      {\
            UNSG32 uSRAM_PWR_CTRL_USB2_value                   :  2;\
            UNSG32 RSVDx4C_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_USB2;
            struct w32Gbl_SRAM_PWR_CTRL_USB2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_PCIE0_value(r32)          _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_PCIE0_value(r32,v)        _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_PCIE0_value(r16)          _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_PCIE0_value(r16,v)        _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_PCIE0                     {\
            UNSG32 uSRAM_PWR_CTRL_PCIE0_value                  :  2;\
            UNSG32 RSVDx50_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_PCIE0;
            struct w32Gbl_SRAM_PWR_CTRL_PCIE0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_PCIE1_value(r32)          _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_PCIE1_value(r32,v)        _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_PCIE1_value(r16)          _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_PCIE1_value(r16,v)        _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_PCIE1                     {\
            UNSG32 uSRAM_PWR_CTRL_PCIE1_value                  :  2;\
            UNSG32 RSVDx54_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_PCIE1;
            struct w32Gbl_SRAM_PWR_CTRL_PCIE1;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx58                                     [4];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_SISS_value(r32)           _BFGET_(r32, 2, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_SISS_value(r32,v)         _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_SISS_value(r16)           _BFGET_(r16, 2, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_SISS_value(r16,v)         _BFSET_(r16, 2, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_SISS                      {\
            UNSG32 uSRAM_PWR_CTRL_SISS_value                   :  3;\
            UNSG32 RSVDx5C_b3                                  : 29;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_SISS;
            struct w32Gbl_SRAM_PWR_CTRL_SISS;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx60                                     [12];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_NNA_value(r32)            _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_NNA_value(r32,v)          _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_NNA_value(r16)            _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_NNA_value(r16,v)          _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_NNA                       {\
            UNSG32 uSRAM_PWR_CTRL_NNA_value                    :  2;\
            UNSG32 RSVDx6C_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_NNA;
            struct w32Gbl_SRAM_PWR_CTRL_NNA;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_AIO_value(r32)            _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_AIO_value(r32,v)          _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_AIO_value(r16)            _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_AIO_value(r16,v)          _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_AIO                       {\
            UNSG32 uSRAM_PWR_CTRL_AIO_value                    :  2;\
            UNSG32 RSVDx70_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_AIO;
            struct w32Gbl_SRAM_PWR_CTRL_AIO;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_CA53_value(r32)           _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_CA53_value(r32,v)         _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_CA53_value(r16)           _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_CA53_value(r16,v)         _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_CA53                      {\
            UNSG32 uSRAM_PWR_CTRL_CA53_value                   :  2;\
            UNSG32 RSVDx74_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_CA53;
            struct w32Gbl_SRAM_PWR_CTRL_CA53;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SRAM_PWR_CTRL_SCRATCH_value(r32)        _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SRAM_PWR_CTRL_SCRATCH_value(r32,v)      _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SRAM_PWR_CTRL_SCRATCH_value(r16)        _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SRAM_PWR_CTRL_SCRATCH_value(r16,v)      _BFSET_(r16, 1, 0,v)

    #define     w32Gbl_SRAM_PWR_CTRL_SCRATCH                   {\
            UNSG32 uSRAM_PWR_CTRL_SCRATCH_value                :  2;\
            UNSG32 RSVDx78_b2                                  : 30;\
          }
    union { UNSG32 u32Gbl_SRAM_PWR_CTRL_SCRATCH;
            struct w32Gbl_SRAM_PWR_CTRL_SCRATCH;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx7C                                     [4];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_FPGAR_FPGAR(r32)                        _BFGET_(r32,31, 0)
    #define   SET32Gbl_FPGAR_FPGAR(r32,v)                      _BFSET_(r32,31, 0,v)

    #define     w32Gbl_FPGAR                                   {\
            UNSG32 uFPGAR_FPGAR                                : 32;\
          }
    union { UNSG32 u32Gbl_FPGAR;
            struct w32Gbl_FPGAR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_FPGARW_FPGARW(r32)                      _BFGET_(r32,31, 0)
    #define   SET32Gbl_FPGARW_FPGARW(r32,v)                    _BFSET_(r32,31, 0,v)

    #define     w32Gbl_FPGARW                                  {\
            UNSG32 uFPGARW_FPGARW                              : 32;\
          }
    union { UNSG32 u32Gbl_FPGARW;
            struct w32Gbl_FPGARW;
          };
    ///////////////////////////////////////////////////////////
              SIE_vsipll                                       ie_sysPll;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDxA0                                     [984];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_ResetTrigger_chipReset(r32)             _BFGET_(r32, 0, 0)
    #define   SET32Gbl_ResetTrigger_chipReset(r32,v)           _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_ResetTrigger_chipReset(r16)             _BFGET_(r16, 0, 0)
    #define   SET16Gbl_ResetTrigger_chipReset(r16,v)           _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_ResetTrigger_socDdrSyncReset(r32)       _BFGET_(r32, 1, 1)
    #define   SET32Gbl_ResetTrigger_socDdrSyncReset(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_ResetTrigger_socDdrSyncReset(r16)       _BFGET_(r16, 1, 1)
    #define   SET16Gbl_ResetTrigger_socDdrSyncReset(r16,v)     _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_ResetTrigger                            {\
            UNSG32 uResetTrigger_chipReset                     :  1;\
            UNSG32 uResetTrigger_socDdrSyncReset               :  1;\
            UNSG32 RSVDx478_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_ResetTrigger;
            struct w32Gbl_ResetTrigger;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_ResetStatus_ChipResetStatus(r32)        _BFGET_(r32, 0, 0)
    #define   SET32Gbl_ResetStatus_ChipResetStatus(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_ResetStatus_ChipResetStatus(r16)        _BFGET_(r16, 0, 0)
    #define   SET16Gbl_ResetStatus_ChipResetStatus(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_ResetStatus_socDdrSyncResetStatus(r32)  _BFGET_(r32, 1, 1)
    #define   SET32Gbl_ResetStatus_socDdrSyncResetStatus(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_ResetStatus_socDdrSyncResetStatus(r16)  _BFGET_(r16, 1, 1)
    #define   SET16Gbl_ResetStatus_socDdrSyncResetStatus(r16,v) _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_ResetStatus                             {\
            UNSG32 uResetStatus_ChipResetStatus                :  1;\
            UNSG32 uResetStatus_socDdrSyncResetStatus          :  1;\
            UNSG32 RSVDx47C_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_ResetStatus;
            struct w32Gbl_ResetStatus;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_WDTResetStatus_wd0Status(r32)           _BFGET_(r32, 0, 0)
    #define   SET32Gbl_WDTResetStatus_wd0Status(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_WDTResetStatus_wd0Status(r16)           _BFGET_(r16, 0, 0)
    #define   SET16Gbl_WDTResetStatus_wd0Status(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_WDTResetStatus_wd1Status(r32)           _BFGET_(r32, 1, 1)
    #define   SET32Gbl_WDTResetStatus_wd1Status(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_WDTResetStatus_wd1Status(r16)           _BFGET_(r16, 1, 1)
    #define   SET16Gbl_WDTResetStatus_wd1Status(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_WDTResetStatus_wd2Status(r32)           _BFGET_(r32, 2, 2)
    #define   SET32Gbl_WDTResetStatus_wd2Status(r32,v)         _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_WDTResetStatus_wd2Status(r16)           _BFGET_(r16, 2, 2)
    #define   SET16Gbl_WDTResetStatus_wd2Status(r16,v)         _BFSET_(r16, 2, 2,v)

    #define     w32Gbl_WDTResetStatus                          {\
            UNSG32 uWDTResetStatus_wd0Status                   :  1;\
            UNSG32 uWDTResetStatus_wd1Status                   :  1;\
            UNSG32 uWDTResetStatus_wd2Status                   :  1;\
            UNSG32 RSVDx480_b3                                 : 29;\
          }
    union { UNSG32 u32Gbl_WDTResetStatus;
            struct w32Gbl_WDTResetStatus;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_WDTSysRstMask_wdt0Mask(r32)             _BFGET_(r32, 0, 0)
    #define   SET32Gbl_WDTSysRstMask_wdt0Mask(r32,v)           _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_WDTSysRstMask_wdt0Mask(r16)             _BFGET_(r16, 0, 0)
    #define   SET16Gbl_WDTSysRstMask_wdt0Mask(r16,v)           _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_WDTSysRstMask_wdt1Mask(r32)             _BFGET_(r32, 1, 1)
    #define   SET32Gbl_WDTSysRstMask_wdt1Mask(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_WDTSysRstMask_wdt1Mask(r16)             _BFGET_(r16, 1, 1)
    #define   SET16Gbl_WDTSysRstMask_wdt1Mask(r16,v)           _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_WDTSysRstMask_wdt2Mask(r32)             _BFGET_(r32, 2, 2)
    #define   SET32Gbl_WDTSysRstMask_wdt2Mask(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_WDTSysRstMask_wdt2Mask(r16)             _BFGET_(r16, 2, 2)
    #define   SET16Gbl_WDTSysRstMask_wdt2Mask(r16,v)           _BFSET_(r16, 2, 2,v)

    #define     w32Gbl_WDTSysRstMask                           {\
            UNSG32 uWDTSysRstMask_wdt0Mask                     :  1;\
            UNSG32 uWDTSysRstMask_wdt1Mask                     :  1;\
            UNSG32 uWDTSysRstMask_wdt2Mask                     :  1;\
            UNSG32 RSVDx484_b3                                 : 29;\
          }
    union { UNSG32 u32Gbl_WDTSysRstMask;
            struct w32Gbl_WDTSysRstMask;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_CHIP_RESET_TRACKER_VALUE(r32)           _BFGET_(r32,31, 0)
    #define   SET32Gbl_CHIP_RESET_TRACKER_VALUE(r32,v)         _BFSET_(r32,31, 0,v)

    #define     w32Gbl_CHIP_RESET_TRACKER                      {\
            UNSG32 uCHIP_RESET_TRACKER_VALUE                   : 32;\
          }
    union { UNSG32 u32Gbl_CHIP_RESET_TRACKER;
            struct w32Gbl_CHIP_RESET_TRACKER;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx48C                                    [8];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_avioReset_SyncReset(r32)                _BFGET_(r32, 0, 0)
    #define   SET32Gbl_avioReset_SyncReset(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_avioReset_SyncReset(r16)                _BFGET_(r16, 0, 0)
    #define   SET16Gbl_avioReset_SyncReset(r16,v)              _BFSET_(r16, 0, 0,v)

    #define     w32Gbl_avioReset                               {\
            UNSG32 uavioReset_SyncReset                        :  1;\
            UNSG32 RSVDx494_b1                                 : 31;\
          }
    union { UNSG32 u32Gbl_avioReset;
            struct w32Gbl_avioReset;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_avioResetStatus_SyncReset(r32)          _BFGET_(r32, 0, 0)
    #define   SET32Gbl_avioResetStatus_SyncReset(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_avioResetStatus_SyncReset(r16)          _BFGET_(r16, 0, 0)
    #define   SET16Gbl_avioResetStatus_SyncReset(r16,v)        _BFSET_(r16, 0, 0,v)

    #define     w32Gbl_avioResetStatus                         {\
            UNSG32 uavioResetStatus_SyncReset                  :  1;\
            UNSG32 RSVDx498_b1                                 : 31;\
          }
    union { UNSG32 u32Gbl_avioResetStatus;
            struct w32Gbl_avioResetStatus;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_perifReset_SyncReset(r32)               _BFGET_(r32, 0, 0)
    #define   SET32Gbl_perifReset_SyncReset(r32,v)             _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_perifReset_SyncReset(r16)               _BFGET_(r16, 0, 0)
    #define   SET16Gbl_perifReset_SyncReset(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_perifReset_ahbApbSyncReset(r32)         _BFGET_(r32, 1, 1)
    #define   SET32Gbl_perifReset_ahbApbSyncReset(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_perifReset_ahbApbSyncReset(r16)         _BFGET_(r16, 1, 1)
    #define   SET16Gbl_perifReset_ahbApbSyncReset(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_perifReset_nfcSysSyncReset(r32)         _BFGET_(r32, 2, 2)
    #define   SET32Gbl_perifReset_nfcSysSyncReset(r32,v)       _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_perifReset_nfcSysSyncReset(r16)         _BFGET_(r16, 2, 2)
    #define   SET16Gbl_perifReset_nfcSysSyncReset(r16,v)       _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_perifReset_nfcRegSyncReset(r32)         _BFGET_(r32, 3, 3)
    #define   SET32Gbl_perifReset_nfcRegSyncReset(r32,v)       _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_perifReset_nfcRegSyncReset(r16)         _BFGET_(r16, 3, 3)
    #define   SET16Gbl_perifReset_nfcRegSyncReset(r16,v)       _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_perifReset_sdioSyncReset(r32)           _BFGET_(r32, 4, 4)
    #define   SET32Gbl_perifReset_sdioSyncReset(r32,v)         _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_perifReset_sdioSyncReset(r16)           _BFGET_(r16, 4, 4)
    #define   SET16Gbl_perifReset_sdioSyncReset(r16,v)         _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_perifReset_tspSyncReset(r32)            _BFGET_(r32, 5, 5)
    #define   SET32Gbl_perifReset_tspSyncReset(r32,v)          _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_perifReset_tspSyncReset(r16)            _BFGET_(r16, 5, 5)
    #define   SET16Gbl_perifReset_tspSyncReset(r16,v)          _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_perifReset_tsSSSyncReset(r32)           _BFGET_(r32, 6, 6)
    #define   SET32Gbl_perifReset_tsSSSyncReset(r32,v)         _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_perifReset_tsSSSyncReset(r16)           _BFGET_(r16, 6, 6)
    #define   SET16Gbl_perifReset_tsSSSyncReset(r16,v)         _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_perifReset_nskSyncReset(r32)            _BFGET_(r32, 7, 7)
    #define   SET32Gbl_perifReset_nskSyncReset(r32,v)          _BFSET_(r32, 7, 7,v)
    #define   GET16Gbl_perifReset_nskSyncReset(r16)            _BFGET_(r16, 7, 7)
    #define   SET16Gbl_perifReset_nskSyncReset(r16,v)          _BFSET_(r16, 7, 7,v)

    #define   GET32Gbl_perifReset_nocsSyncReset(r32)           _BFGET_(r32, 8, 8)
    #define   SET32Gbl_perifReset_nocsSyncReset(r32,v)         _BFSET_(r32, 8, 8,v)
    #define   GET16Gbl_perifReset_nocsSyncReset(r16)           _BFGET_(r16, 8, 8)
    #define   SET16Gbl_perifReset_nocsSyncReset(r16,v)         _BFSET_(r16, 8, 8,v)

    #define   GET32Gbl_perifReset_bcmSyncReset(r32)            _BFGET_(r32, 9, 9)
    #define   SET32Gbl_perifReset_bcmSyncReset(r32,v)          _BFSET_(r32, 9, 9,v)
    #define   GET16Gbl_perifReset_bcmSyncReset(r16)            _BFGET_(r16, 9, 9)
    #define   SET16Gbl_perifReset_bcmSyncReset(r16,v)          _BFSET_(r16, 9, 9,v)

    #define   GET32Gbl_perifReset_usb0SyncReset(r32)           _BFGET_(r32,10,10)
    #define   SET32Gbl_perifReset_usb0SyncReset(r32,v)         _BFSET_(r32,10,10,v)
    #define   GET16Gbl_perifReset_usb0SyncReset(r16)           _BFGET_(r16,10,10)
    #define   SET16Gbl_perifReset_usb0SyncReset(r16,v)         _BFSET_(r16,10,10,v)

    #define   GET32Gbl_perifReset_emmcSyncReset(r32)           _BFGET_(r32,11,11)
    #define   SET32Gbl_perifReset_emmcSyncReset(r32,v)         _BFSET_(r32,11,11,v)
    #define   GET16Gbl_perifReset_emmcSyncReset(r16)           _BFGET_(r16,11,11)
    #define   SET16Gbl_perifReset_emmcSyncReset(r16,v)         _BFSET_(r16,11,11,v)

    #define   GET32Gbl_perifReset_pBridgeSyncReset(r32)        _BFGET_(r32,12,12)
    #define   SET32Gbl_perifReset_pBridgeSyncReset(r32,v)      _BFSET_(r32,12,12,v)
    #define   GET16Gbl_perifReset_pBridgeSyncReset(r16)        _BFGET_(r16,12,12)
    #define   SET16Gbl_perifReset_pBridgeSyncReset(r16,v)      _BFSET_(r16,12,12,v)

    #define     w32Gbl_perifReset                              {\
            UNSG32 uperifReset_SyncReset                       :  1;\
            UNSG32 uperifReset_ahbApbSyncReset                 :  1;\
            UNSG32 uperifReset_nfcSysSyncReset                 :  1;\
            UNSG32 uperifReset_nfcRegSyncReset                 :  1;\
            UNSG32 uperifReset_sdioSyncReset                   :  1;\
            UNSG32 uperifReset_tspSyncReset                    :  1;\
            UNSG32 uperifReset_tsSSSyncReset                   :  1;\
            UNSG32 uperifReset_nskSyncReset                    :  1;\
            UNSG32 uperifReset_nocsSyncReset                   :  1;\
            UNSG32 uperifReset_bcmSyncReset                    :  1;\
            UNSG32 uperifReset_usb0SyncReset                   :  1;\
            UNSG32 uperifReset_emmcSyncReset                   :  1;\
            UNSG32 uperifReset_pBridgeSyncReset                :  1;\
            UNSG32 RSVDx49C_b13                                : 19;\
          }
    union { UNSG32 u32Gbl_perifReset;
            struct w32Gbl_perifReset;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx4A0                                    [96];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_perifResetStatus_SyncReset(r32)         _BFGET_(r32, 0, 0)
    #define   SET32Gbl_perifResetStatus_SyncReset(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_perifResetStatus_SyncReset(r16)         _BFGET_(r16, 0, 0)
    #define   SET16Gbl_perifResetStatus_SyncReset(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_perifResetStatus_ahbApbSyncReset(r32)   _BFGET_(r32, 1, 1)
    #define   SET32Gbl_perifResetStatus_ahbApbSyncReset(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_perifResetStatus_ahbApbSyncReset(r16)   _BFGET_(r16, 1, 1)
    #define   SET16Gbl_perifResetStatus_ahbApbSyncReset(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_perifResetStatus_nfcSysSyncReset(r32)   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_perifResetStatus_nfcSysSyncReset(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_perifResetStatus_nfcSysSyncReset(r16)   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_perifResetStatus_nfcSysSyncReset(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_perifResetStatus_nfcRegSyncReset(r32)   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_perifResetStatus_nfcRegSyncReset(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_perifResetStatus_nfcRegSyncReset(r16)   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_perifResetStatus_nfcRegSyncReset(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_perifResetStatus_sdioSyncReset(r32)     _BFGET_(r32, 4, 4)
    #define   SET32Gbl_perifResetStatus_sdioSyncReset(r32,v)   _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_perifResetStatus_sdioSyncReset(r16)     _BFGET_(r16, 4, 4)
    #define   SET16Gbl_perifResetStatus_sdioSyncReset(r16,v)   _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_perifResetStatus_tspSyncReset(r32)      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_perifResetStatus_tspSyncReset(r32,v)    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_perifResetStatus_tspSyncReset(r16)      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_perifResetStatus_tspSyncReset(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_perifResetStatus_tsSSSyncReset(r32)     _BFGET_(r32, 6, 6)
    #define   SET32Gbl_perifResetStatus_tsSSSyncReset(r32,v)   _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_perifResetStatus_tsSSSyncReset(r16)     _BFGET_(r16, 6, 6)
    #define   SET16Gbl_perifResetStatus_tsSSSyncReset(r16,v)   _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_perifResetStatus_nskSyncReset(r32)      _BFGET_(r32, 7, 7)
    #define   SET32Gbl_perifResetStatus_nskSyncReset(r32,v)    _BFSET_(r32, 7, 7,v)
    #define   GET16Gbl_perifResetStatus_nskSyncReset(r16)      _BFGET_(r16, 7, 7)
    #define   SET16Gbl_perifResetStatus_nskSyncReset(r16,v)    _BFSET_(r16, 7, 7,v)

    #define   GET32Gbl_perifResetStatus_nocsSyncReset(r32)     _BFGET_(r32, 8, 8)
    #define   SET32Gbl_perifResetStatus_nocsSyncReset(r32,v)   _BFSET_(r32, 8, 8,v)
    #define   GET16Gbl_perifResetStatus_nocsSyncReset(r16)     _BFGET_(r16, 8, 8)
    #define   SET16Gbl_perifResetStatus_nocsSyncReset(r16,v)   _BFSET_(r16, 8, 8,v)

    #define   GET32Gbl_perifResetStatus_bcmSyncReset(r32)      _BFGET_(r32, 9, 9)
    #define   SET32Gbl_perifResetStatus_bcmSyncReset(r32,v)    _BFSET_(r32, 9, 9,v)
    #define   GET16Gbl_perifResetStatus_bcmSyncReset(r16)      _BFGET_(r16, 9, 9)
    #define   SET16Gbl_perifResetStatus_bcmSyncReset(r16,v)    _BFSET_(r16, 9, 9,v)

    #define   GET32Gbl_perifResetStatus_usb0SyncReset(r32)     _BFGET_(r32,10,10)
    #define   SET32Gbl_perifResetStatus_usb0SyncReset(r32,v)   _BFSET_(r32,10,10,v)
    #define   GET16Gbl_perifResetStatus_usb0SyncReset(r16)     _BFGET_(r16,10,10)
    #define   SET16Gbl_perifResetStatus_usb0SyncReset(r16,v)   _BFSET_(r16,10,10,v)

    #define   GET32Gbl_perifResetStatus_emmcSyncReset(r32)     _BFGET_(r32,11,11)
    #define   SET32Gbl_perifResetStatus_emmcSyncReset(r32,v)   _BFSET_(r32,11,11,v)
    #define   GET16Gbl_perifResetStatus_emmcSyncReset(r16)     _BFGET_(r16,11,11)
    #define   SET16Gbl_perifResetStatus_emmcSyncReset(r16,v)   _BFSET_(r16,11,11,v)

    #define   GET32Gbl_perifResetStatus_pBridgeSyncReset(r32)  _BFGET_(r32,12,12)
    #define   SET32Gbl_perifResetStatus_pBridgeSyncReset(r32,v) _BFSET_(r32,12,12,v)
    #define   GET16Gbl_perifResetStatus_pBridgeSyncReset(r16)  _BFGET_(r16,12,12)
    #define   SET16Gbl_perifResetStatus_pBridgeSyncReset(r16,v) _BFSET_(r16,12,12,v)

    #define     w32Gbl_perifResetStatus                        {\
            UNSG32 uperifResetStatus_SyncReset                 :  1;\
            UNSG32 uperifResetStatus_ahbApbSyncReset           :  1;\
            UNSG32 uperifResetStatus_nfcSysSyncReset           :  1;\
            UNSG32 uperifResetStatus_nfcRegSyncReset           :  1;\
            UNSG32 uperifResetStatus_sdioSyncReset             :  1;\
            UNSG32 uperifResetStatus_tspSyncReset              :  1;\
            UNSG32 uperifResetStatus_tsSSSyncReset             :  1;\
            UNSG32 uperifResetStatus_nskSyncReset              :  1;\
            UNSG32 uperifResetStatus_nocsSyncReset             :  1;\
            UNSG32 uperifResetStatus_bcmSyncReset              :  1;\
            UNSG32 uperifResetStatus_usb0SyncReset             :  1;\
            UNSG32 uperifResetStatus_emmcSyncReset             :  1;\
            UNSG32 uperifResetStatus_pBridgeSyncReset          :  1;\
            UNSG32 RSVDx500_b13                                : 19;\
          }
    union { UNSG32 u32Gbl_perifResetStatus;
            struct w32Gbl_perifResetStatus;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_topStickyResetN_nnaStickyRstn(r32)      _BFGET_(r32, 0, 0)
    #define   SET32Gbl_topStickyResetN_nnaStickyRstn(r32,v)    _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_topStickyResetN_nnaStickyRstn(r16)      _BFGET_(r16, 0, 0)
    #define   SET16Gbl_topStickyResetN_nnaStickyRstn(r16,v)    _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_topStickyResetN_ddrPHYStickyRstn(r32)   _BFGET_(r32, 1, 1)
    #define   SET32Gbl_topStickyResetN_ddrPHYStickyRstn(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_topStickyResetN_ddrPHYStickyRstn(r16)   _BFGET_(r16, 1, 1)
    #define   SET16Gbl_topStickyResetN_ddrPHYStickyRstn(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_topStickyResetN_mcStickyRstn(r32)       _BFGET_(r32, 2, 2)
    #define   SET32Gbl_topStickyResetN_mcStickyRstn(r32,v)     _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_topStickyResetN_mcStickyRstn(r16)       _BFGET_(r16, 2, 2)
    #define   SET16Gbl_topStickyResetN_mcStickyRstn(r16,v)     _BFSET_(r16, 2, 2,v)

    #define     w32Gbl_topStickyResetN                         {\
            UNSG32 utopStickyResetN_nnaStickyRstn              :  1;\
            UNSG32 utopStickyResetN_ddrPHYStickyRstn           :  1;\
            UNSG32 utopStickyResetN_mcStickyRstn               :  1;\
            UNSG32 RSVDx504_b3                                 : 29;\
          }
    union { UNSG32 u32Gbl_topStickyResetN;
            struct w32Gbl_topStickyResetN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_perifStickyResetN_pcie0Rstn(r32)        _BFGET_(r32, 0, 0)
    #define   SET32Gbl_perifStickyResetN_pcie0Rstn(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_perifStickyResetN_pcie0Rstn(r16)        _BFGET_(r16, 0, 0)
    #define   SET16Gbl_perifStickyResetN_pcie0Rstn(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_perifStickyResetN_pcie1Rstn(r32)        _BFGET_(r32, 1, 1)
    #define   SET32Gbl_perifStickyResetN_pcie1Rstn(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_perifStickyResetN_pcie1Rstn(r16)        _BFGET_(r16, 1, 1)
    #define   SET16Gbl_perifStickyResetN_pcie1Rstn(r16,v)      _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_perifStickyResetN_usbOtgPrstn(r32)      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_perifStickyResetN_usbOtgPrstn(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_perifStickyResetN_usbOtgPrstn(r16)      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_perifStickyResetN_usbOtgPrstn(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_perifStickyResetN_usbOtgHresetn(r32)    _BFGET_(r32, 3, 3)
    #define   SET32Gbl_perifStickyResetN_usbOtgHresetn(r32,v)  _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_perifStickyResetN_usbOtgHresetn(r16)    _BFGET_(r16, 3, 3)
    #define   SET16Gbl_perifStickyResetN_usbOtgHresetn(r16,v)  _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_perifStickyResetN_usbOtgPhyreset(r32)   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_perifStickyResetN_usbOtgPhyreset(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_perifStickyResetN_usbOtgPhyreset(r16)   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_perifStickyResetN_usbOtgPhyreset(r16,v) _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_perifStickyResetN_pcie0PhyRstn(r32)     _BFGET_(r32, 5, 5)
    #define   SET32Gbl_perifStickyResetN_pcie0PhyRstn(r32,v)   _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_perifStickyResetN_pcie0PhyRstn(r16)     _BFGET_(r16, 5, 5)
    #define   SET16Gbl_perifStickyResetN_pcie0PhyRstn(r16,v)   _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_perifStickyResetN_pcie1PhyRstn(r32)     _BFGET_(r32, 6, 6)
    #define   SET32Gbl_perifStickyResetN_pcie1PhyRstn(r32,v)   _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_perifStickyResetN_pcie1PhyRstn(r16)     _BFGET_(r16, 6, 6)
    #define   SET16Gbl_perifStickyResetN_pcie1PhyRstn(r16,v)   _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_perifStickyResetN                       {\
            UNSG32 uperifStickyResetN_pcie0Rstn                :  1;\
            UNSG32 uperifStickyResetN_pcie1Rstn                :  1;\
            UNSG32 uperifStickyResetN_usbOtgPrstn              :  1;\
            UNSG32 uperifStickyResetN_usbOtgHresetn            :  1;\
            UNSG32 uperifStickyResetN_usbOtgPhyreset           :  1;\
            UNSG32 uperifStickyResetN_pcie0PhyRstn             :  1;\
            UNSG32 uperifStickyResetN_pcie1PhyRstn             :  1;\
            UNSG32 RSVDx508_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_perifStickyResetN;
            struct w32Gbl_perifStickyResetN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_apbPerifResetTrigger_uart0SyncReset(r32) _BFGET_(r32, 0, 0)
    #define   SET32Gbl_apbPerifResetTrigger_uart0SyncReset(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_apbPerifResetTrigger_uart0SyncReset(r16) _BFGET_(r16, 0, 0)
    #define   SET16Gbl_apbPerifResetTrigger_uart0SyncReset(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_apbPerifResetTrigger_uart1SyncReset(r32) _BFGET_(r32, 1, 1)
    #define   SET32Gbl_apbPerifResetTrigger_uart1SyncReset(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_apbPerifResetTrigger_uart1SyncReset(r16) _BFGET_(r16, 1, 1)
    #define   SET16Gbl_apbPerifResetTrigger_uart1SyncReset(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_apbPerifResetTrigger_i2c0SyncReset(r32) _BFGET_(r32, 2, 2)
    #define   SET32Gbl_apbPerifResetTrigger_i2c0SyncReset(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_apbPerifResetTrigger_i2c0SyncReset(r16) _BFGET_(r16, 2, 2)
    #define   SET16Gbl_apbPerifResetTrigger_i2c0SyncReset(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_apbPerifResetTrigger_i2c1SyncReset(r32) _BFGET_(r32, 3, 3)
    #define   SET32Gbl_apbPerifResetTrigger_i2c1SyncReset(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_apbPerifResetTrigger_i2c1SyncReset(r16) _BFGET_(r16, 3, 3)
    #define   SET16Gbl_apbPerifResetTrigger_i2c1SyncReset(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_apbPerifResetTrigger_spiSyncReset(r32)  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_apbPerifResetTrigger_spiSyncReset(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_apbPerifResetTrigger_spiSyncReset(r16)  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_apbPerifResetTrigger_spiSyncReset(r16,v) _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_apbPerifResetTrigger_timer0SyncReset(r32) _BFGET_(r32, 5, 5)
    #define   SET32Gbl_apbPerifResetTrigger_timer0SyncReset(r32,v) _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_apbPerifResetTrigger_timer0SyncReset(r16) _BFGET_(r16, 5, 5)
    #define   SET16Gbl_apbPerifResetTrigger_timer0SyncReset(r16,v) _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_apbPerifResetTrigger_timer1SyncReset(r32) _BFGET_(r32, 6, 6)
    #define   SET32Gbl_apbPerifResetTrigger_timer1SyncReset(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_apbPerifResetTrigger_timer1SyncReset(r16) _BFGET_(r16, 6, 6)
    #define   SET16Gbl_apbPerifResetTrigger_timer1SyncReset(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_apbPerifResetTrigger_wdt0SyncReset(r32) _BFGET_(r32, 7, 7)
    #define   SET32Gbl_apbPerifResetTrigger_wdt0SyncReset(r32,v) _BFSET_(r32, 7, 7,v)
    #define   GET16Gbl_apbPerifResetTrigger_wdt0SyncReset(r16) _BFGET_(r16, 7, 7)
    #define   SET16Gbl_apbPerifResetTrigger_wdt0SyncReset(r16,v) _BFSET_(r16, 7, 7,v)

    #define   GET32Gbl_apbPerifResetTrigger_wdt1SyncReset(r32) _BFGET_(r32, 8, 8)
    #define   SET32Gbl_apbPerifResetTrigger_wdt1SyncReset(r32,v) _BFSET_(r32, 8, 8,v)
    #define   GET16Gbl_apbPerifResetTrigger_wdt1SyncReset(r16) _BFGET_(r16, 8, 8)
    #define   SET16Gbl_apbPerifResetTrigger_wdt1SyncReset(r16,v) _BFSET_(r16, 8, 8,v)

    #define   GET32Gbl_apbPerifResetTrigger_wdt2SyncReset(r32) _BFGET_(r32, 9, 9)
    #define   SET32Gbl_apbPerifResetTrigger_wdt2SyncReset(r32,v) _BFSET_(r32, 9, 9,v)
    #define   GET16Gbl_apbPerifResetTrigger_wdt2SyncReset(r16) _BFGET_(r16, 9, 9)
    #define   SET16Gbl_apbPerifResetTrigger_wdt2SyncReset(r16,v) _BFSET_(r16, 9, 9,v)

    #define     w32Gbl_apbPerifResetTrigger                    {\
            UNSG32 uapbPerifResetTrigger_uart0SyncReset        :  1;\
            UNSG32 uapbPerifResetTrigger_uart1SyncReset        :  1;\
            UNSG32 uapbPerifResetTrigger_i2c0SyncReset         :  1;\
            UNSG32 uapbPerifResetTrigger_i2c1SyncReset         :  1;\
            UNSG32 uapbPerifResetTrigger_spiSyncReset          :  1;\
            UNSG32 uapbPerifResetTrigger_timer0SyncReset       :  1;\
            UNSG32 uapbPerifResetTrigger_timer1SyncReset       :  1;\
            UNSG32 uapbPerifResetTrigger_wdt0SyncReset         :  1;\
            UNSG32 uapbPerifResetTrigger_wdt1SyncReset         :  1;\
            UNSG32 uapbPerifResetTrigger_wdt2SyncReset         :  1;\
            UNSG32 RSVDx50C_b10                                : 22;\
          }
    union { UNSG32 u32Gbl_apbPerifResetTrigger;
            struct w32Gbl_apbPerifResetTrigger;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_apbPerifResetStatus_uart0SyncResetStatus(r32) _BFGET_(r32, 0, 0)
    #define   SET32Gbl_apbPerifResetStatus_uart0SyncResetStatus(r32,v) _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_apbPerifResetStatus_uart0SyncResetStatus(r16) _BFGET_(r16, 0, 0)
    #define   SET16Gbl_apbPerifResetStatus_uart0SyncResetStatus(r16,v) _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_apbPerifResetStatus_uart1SyncResetStatus(r32) _BFGET_(r32, 1, 1)
    #define   SET32Gbl_apbPerifResetStatus_uart1SyncResetStatus(r32,v) _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_apbPerifResetStatus_uart1SyncResetStatus(r16) _BFGET_(r16, 1, 1)
    #define   SET16Gbl_apbPerifResetStatus_uart1SyncResetStatus(r16,v) _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_apbPerifResetStatus_i2c0SyncResetStatus(r32) _BFGET_(r32, 2, 2)
    #define   SET32Gbl_apbPerifResetStatus_i2c0SyncResetStatus(r32,v) _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_apbPerifResetStatus_i2c0SyncResetStatus(r16) _BFGET_(r16, 2, 2)
    #define   SET16Gbl_apbPerifResetStatus_i2c0SyncResetStatus(r16,v) _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_apbPerifResetStatus_i2c1SyncResetStatus(r32) _BFGET_(r32, 3, 3)
    #define   SET32Gbl_apbPerifResetStatus_i2c1SyncResetStatus(r32,v) _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_apbPerifResetStatus_i2c1SyncResetStatus(r16) _BFGET_(r16, 3, 3)
    #define   SET16Gbl_apbPerifResetStatus_i2c1SyncResetStatus(r16,v) _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_apbPerifResetStatus_i2c2SyncResetStatus(r32) _BFGET_(r32, 4, 4)
    #define   SET32Gbl_apbPerifResetStatus_i2c2SyncResetStatus(r32,v) _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_apbPerifResetStatus_i2c2SyncResetStatus(r16) _BFGET_(r16, 4, 4)
    #define   SET16Gbl_apbPerifResetStatus_i2c2SyncResetStatus(r16,v) _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_apbPerifResetStatus_spiSyncResetStatus(r32) _BFGET_(r32, 5, 5)
    #define   SET32Gbl_apbPerifResetStatus_spiSyncResetStatus(r32,v) _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_apbPerifResetStatus_spiSyncResetStatus(r16) _BFGET_(r16, 5, 5)
    #define   SET16Gbl_apbPerifResetStatus_spiSyncResetStatus(r16,v) _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_apbPerifResetStatus_timer0SyncResetStatus(r32) _BFGET_(r32, 6, 6)
    #define   SET32Gbl_apbPerifResetStatus_timer0SyncResetStatus(r32,v) _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_apbPerifResetStatus_timer0SyncResetStatus(r16) _BFGET_(r16, 6, 6)
    #define   SET16Gbl_apbPerifResetStatus_timer0SyncResetStatus(r16,v) _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_apbPerifResetStatus_timer1SyncResetStatus(r32) _BFGET_(r32, 7, 7)
    #define   SET32Gbl_apbPerifResetStatus_timer1SyncResetStatus(r32,v) _BFSET_(r32, 7, 7,v)
    #define   GET16Gbl_apbPerifResetStatus_timer1SyncResetStatus(r16) _BFGET_(r16, 7, 7)
    #define   SET16Gbl_apbPerifResetStatus_timer1SyncResetStatus(r16,v) _BFSET_(r16, 7, 7,v)

    #define   GET32Gbl_apbPerifResetStatus_wdt0SyncResetStatus(r32) _BFGET_(r32, 8, 8)
    #define   SET32Gbl_apbPerifResetStatus_wdt0SyncResetStatus(r32,v) _BFSET_(r32, 8, 8,v)
    #define   GET16Gbl_apbPerifResetStatus_wdt0SyncResetStatus(r16) _BFGET_(r16, 8, 8)
    #define   SET16Gbl_apbPerifResetStatus_wdt0SyncResetStatus(r16,v) _BFSET_(r16, 8, 8,v)

    #define   GET32Gbl_apbPerifResetStatus_wdt1SyncResetStatus(r32) _BFGET_(r32, 9, 9)
    #define   SET32Gbl_apbPerifResetStatus_wdt1SyncResetStatus(r32,v) _BFSET_(r32, 9, 9,v)
    #define   GET16Gbl_apbPerifResetStatus_wdt1SyncResetStatus(r16) _BFGET_(r16, 9, 9)
    #define   SET16Gbl_apbPerifResetStatus_wdt1SyncResetStatus(r16,v) _BFSET_(r16, 9, 9,v)

    #define   GET32Gbl_apbPerifResetStatus_wdt2SyncResetStatus(r32) _BFGET_(r32,10,10)
    #define   SET32Gbl_apbPerifResetStatus_wdt2SyncResetStatus(r32,v) _BFSET_(r32,10,10,v)
    #define   GET16Gbl_apbPerifResetStatus_wdt2SyncResetStatus(r16) _BFGET_(r16,10,10)
    #define   SET16Gbl_apbPerifResetStatus_wdt2SyncResetStatus(r16,v) _BFSET_(r16,10,10,v)

    #define     w32Gbl_apbPerifResetStatus                     {\
            UNSG32 uapbPerifResetStatus_uart0SyncResetStatus   :  1;\
            UNSG32 uapbPerifResetStatus_uart1SyncResetStatus   :  1;\
            UNSG32 uapbPerifResetStatus_i2c0SyncResetStatus    :  1;\
            UNSG32 uapbPerifResetStatus_i2c1SyncResetStatus    :  1;\
            UNSG32 uapbPerifResetStatus_i2c2SyncResetStatus    :  1;\
            UNSG32 uapbPerifResetStatus_spiSyncResetStatus     :  1;\
            UNSG32 uapbPerifResetStatus_timer0SyncResetStatus  :  1;\
            UNSG32 uapbPerifResetStatus_timer1SyncResetStatus  :  1;\
            UNSG32 uapbPerifResetStatus_wdt0SyncResetStatus    :  1;\
            UNSG32 uapbPerifResetStatus_wdt1SyncResetStatus    :  1;\
            UNSG32 uapbPerifResetStatus_wdt2SyncResetStatus    :  1;\
            UNSG32 RSVDx510_b11                                : 21;\
          }
    union { UNSG32 u32Gbl_apbPerifResetStatus;
            struct w32Gbl_apbPerifResetStatus;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_clkEnable_tspSysClkEn(r32)              _BFGET_(r32, 0, 0)
    #define   SET32Gbl_clkEnable_tspSysClkEn(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_clkEnable_tspSysClkEn(r16)              _BFGET_(r16, 0, 0)
    #define   SET16Gbl_clkEnable_tspSysClkEn(r16,v)            _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_clkEnable_usb0CoreClkEn(r32)            _BFGET_(r32, 1, 1)
    #define   SET32Gbl_clkEnable_usb0CoreClkEn(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_clkEnable_usb0CoreClkEn(r16)            _BFGET_(r16, 1, 1)
    #define   SET16Gbl_clkEnable_usb0CoreClkEn(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_clkEnable_sdioSysClkEn(r32)             _BFGET_(r32, 2, 2)
    #define   SET32Gbl_clkEnable_sdioSysClkEn(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_clkEnable_sdioSysClkEn(r16)             _BFGET_(r16, 2, 2)
    #define   SET16Gbl_clkEnable_sdioSysClkEn(r16,v)           _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_clkEnable_pcie0SysClkEn(r32)            _BFGET_(r32, 3, 3)
    #define   SET32Gbl_clkEnable_pcie0SysClkEn(r32,v)          _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_clkEnable_pcie0SysClkEn(r16)            _BFGET_(r16, 3, 3)
    #define   SET16Gbl_clkEnable_pcie0SysClkEn(r16,v)          _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_clkEnable_pcie1SysClkEn(r32)            _BFGET_(r32, 4, 4)
    #define   SET32Gbl_clkEnable_pcie1SysClkEn(r32,v)          _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_clkEnable_pcie1SysClkEn(r16)            _BFGET_(r16, 4, 4)
    #define   SET16Gbl_clkEnable_pcie1SysClkEn(r16,v)          _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_clkEnable_nfcSysClkEn(r32)              _BFGET_(r32, 5, 5)
    #define   SET32Gbl_clkEnable_nfcSysClkEn(r32,v)            _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_clkEnable_nfcSysClkEn(r16)              _BFGET_(r16, 5, 5)
    #define   SET16Gbl_clkEnable_nfcSysClkEn(r16,v)            _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_clkEnable_emmcSysClkEn(r32)             _BFGET_(r32, 6, 6)
    #define   SET32Gbl_clkEnable_emmcSysClkEn(r32,v)           _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_clkEnable_emmcSysClkEn(r16)             _BFGET_(r16, 6, 6)
    #define   SET16Gbl_clkEnable_emmcSysClkEn(r16,v)           _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_clkEnable_pBridgeCoreClkEn(r32)         _BFGET_(r32, 7, 7)
    #define   SET32Gbl_clkEnable_pBridgeCoreClkEn(r32,v)       _BFSET_(r32, 7, 7,v)
    #define   GET16Gbl_clkEnable_pBridgeCoreClkEn(r16)         _BFGET_(r16, 7, 7)
    #define   SET16Gbl_clkEnable_pBridgeCoreClkEn(r16,v)       _BFSET_(r16, 7, 7,v)

    #define     w32Gbl_clkEnable                               {\
            UNSG32 uclkEnable_tspSysClkEn                      :  1;\
            UNSG32 uclkEnable_usb0CoreClkEn                    :  1;\
            UNSG32 uclkEnable_sdioSysClkEn                     :  1;\
            UNSG32 uclkEnable_pcie0SysClkEn                    :  1;\
            UNSG32 uclkEnable_pcie1SysClkEn                    :  1;\
            UNSG32 uclkEnable_nfcSysClkEn                      :  1;\
            UNSG32 uclkEnable_emmcSysClkEn                     :  1;\
            UNSG32 uclkEnable_pBridgeCoreClkEn                 :  1;\
            UNSG32 RSVDx514_b8                                 : 24;\
          }
    union { UNSG32 u32Gbl_clkEnable;
            struct w32Gbl_clkEnable;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_ClkSwitch_sysPLLSWBypass(r32)           _BFGET_(r32, 0, 0)
    #define   SET32Gbl_ClkSwitch_sysPLLSWBypass(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_ClkSwitch_sysPLLSWBypass(r16)           _BFGET_(r16, 0, 0)
    #define   SET16Gbl_ClkSwitch_sysPLLSWBypass(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_ClkSwitch_memPLLSWBypass(r32)           _BFGET_(r32, 1, 1)
    #define   SET32Gbl_ClkSwitch_memPLLSWBypass(r32,v)         _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_ClkSwitch_memPLLSWBypass(r16)           _BFGET_(r16, 1, 1)
    #define   SET16Gbl_ClkSwitch_memPLLSWBypass(r16,v)         _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_ClkSwitch_cpuPLLSWBypass(r32)           _BFGET_(r32, 2, 2)
    #define   SET32Gbl_ClkSwitch_cpuPLLSWBypass(r32,v)         _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_ClkSwitch_cpuPLLSWBypass(r16)           _BFGET_(r16, 2, 2)
    #define   SET16Gbl_ClkSwitch_cpuPLLSWBypass(r16,v)         _BFSET_(r16, 2, 2,v)

    #define     w32Gbl_ClkSwitch                               {\
            UNSG32 uClkSwitch_sysPLLSWBypass                   :  1;\
            UNSG32 uClkSwitch_memPLLSWBypass                   :  1;\
            UNSG32 uClkSwitch_cpuPLLSWBypass                   :  1;\
            UNSG32 RSVDx518_b3                                 : 29;\
          }
    union { UNSG32 u32Gbl_ClkSwitch;
            struct w32Gbl_ClkSwitch;
          };
    ///////////////////////////////////////////////////////////
              SIE_clkD1                                        ie_cpufastRefClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD1                                        ie_memfastRefClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_cfgClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD2                                        ie_perifSysClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD8                                        ie_atbClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD2                                        ie_avioSysClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_apbCoreClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD2                                        ie_nnaSysClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD2                                        ie_nnaCoreClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_emmcClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_sd0Clk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_pcie_500M_TxTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD8                                        ie_pcie_250M_pipeTestClk1;
    ///////////////////////////////////////////////////////////
              SIE_clkD8                                        ie_pcie_250M_pipeTestClk2;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_pcie_500M_RxTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD8                                        ie_pcie_serdesTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_nfcEccClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD4                                        ie_nfcCoreClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD12                                       ie_usbOtg60MTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD12                                       ie_usbOtg50MTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD12                                       ie_usbOtg12MTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD12                                       ie_usbOtg480MTestClk;
    ///////////////////////////////////////////////////////////
              SIE_clkD2                                        ie_bcmClk;
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NandCtrl_NAND_WPn_Sel(r32)              _BFGET_(r32, 0, 0)
    #define   SET32Gbl_NandCtrl_NAND_WPn_Sel(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_NandCtrl_NAND_WPn_Sel(r16)              _BFGET_(r16, 0, 0)
    #define   SET16Gbl_NandCtrl_NAND_WPn_Sel(r16,v)            _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_NandCtrl_NAND_CLE_OE(r32)               _BFGET_(r32, 1, 1)
    #define   SET32Gbl_NandCtrl_NAND_CLE_OE(r32,v)             _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_NandCtrl_NAND_CLE_OE(r16)               _BFGET_(r16, 1, 1)
    #define   SET16Gbl_NandCtrl_NAND_CLE_OE(r16,v)             _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_NandCtrl_NAND_ALE_OE(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NandCtrl_NAND_ALE_OE(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NandCtrl_NAND_ALE_OE(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NandCtrl_NAND_ALE_OE(r16,v)             _BFSET_(r16, 2, 2,v)

    #define     w32Gbl_NandCtrl                                {\
            UNSG32 uNandCtrl_NAND_WPn_Sel                      :  1;\
            UNSG32 uNandCtrl_NAND_CLE_OE                       :  1;\
            UNSG32 uNandCtrl_NAND_ALE_OE                       :  1;\
            UNSG32 RSVDx578_b3                                 : 29;\
          }
    union { UNSG32 u32Gbl_NandCtrl;
            struct w32Gbl_NandCtrl;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx57C                                    [160];
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_gic400_ctrl_cgfsdisable(r32)            _BFGET_(r32, 0, 0)
    #define   SET32Gbl_gic400_ctrl_cgfsdisable(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_gic400_ctrl_cgfsdisable(r16)            _BFGET_(r16, 0, 0)
    #define   SET16Gbl_gic400_ctrl_cgfsdisable(r16,v)          _BFSET_(r16, 0, 0,v)

    #define     w32Gbl_gic400_ctrl                             {\
            UNSG32 ugic400_ctrl_cgfsdisable                    :  1;\
            UNSG32 RSVDx61C_b1                                 : 31;\
          }
    union { UNSG32 u32Gbl_gic400_ctrl;
            struct w32Gbl_gic400_ctrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_POR_1p8_3p3_por_io_1p8v_pd(r32)         _BFGET_(r32, 0, 0)
    #define   SET32Gbl_POR_1p8_3p3_por_io_1p8v_pd(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_POR_1p8_3p3_por_io_1p8v_pd(r16)         _BFGET_(r16, 0, 0)
    #define   SET16Gbl_POR_1p8_3p3_por_io_1p8v_pd(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_POR_1p8_3p3_por_io_3p3v_pd(r32)         _BFGET_(r32, 1, 1)
    #define   SET32Gbl_POR_1p8_3p3_por_io_3p3v_pd(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_POR_1p8_3p3_por_io_3p3v_pd(r16)         _BFGET_(r16, 1, 1)
    #define   SET16Gbl_POR_1p8_3p3_por_io_3p3v_pd(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32Gbl_POR_1p8_3p3_por_io_1p8v_threshold(r32)  _BFGET_(r32, 3, 2)
    #define   SET32Gbl_POR_1p8_3p3_por_io_1p8v_threshold(r32,v) _BFSET_(r32, 3, 2,v)
    #define   GET16Gbl_POR_1p8_3p3_por_io_1p8v_threshold(r16)  _BFGET_(r16, 3, 2)
    #define   SET16Gbl_POR_1p8_3p3_por_io_1p8v_threshold(r16,v) _BFSET_(r16, 3, 2,v)

    #define   GET32Gbl_POR_1p8_3p3_por_io_3p3v_threshold(r32)  _BFGET_(r32, 5, 4)
    #define   SET32Gbl_POR_1p8_3p3_por_io_3p3v_threshold(r32,v) _BFSET_(r32, 5, 4,v)
    #define   GET16Gbl_POR_1p8_3p3_por_io_3p3v_threshold(r16)  _BFGET_(r16, 5, 4)
    #define   SET16Gbl_POR_1p8_3p3_por_io_3p3v_threshold(r16,v) _BFSET_(r16, 5, 4,v)

    #define   GET32Gbl_POR_1p8_3p3_por_io_1p8v_bypass(r32)     _BFGET_(r32, 6, 6)
    #define   SET32Gbl_POR_1p8_3p3_por_io_1p8v_bypass(r32,v)   _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_POR_1p8_3p3_por_io_1p8v_bypass(r16)     _BFGET_(r16, 6, 6)
    #define   SET16Gbl_POR_1p8_3p3_por_io_1p8v_bypass(r16,v)   _BFSET_(r16, 6, 6,v)

    #define   GET32Gbl_POR_1p8_3p3_por_io_3p3v_bypass(r32)     _BFGET_(r32, 7, 7)
    #define   SET32Gbl_POR_1p8_3p3_por_io_3p3v_bypass(r32,v)   _BFSET_(r32, 7, 7,v)
    #define   GET16Gbl_POR_1p8_3p3_por_io_3p3v_bypass(r16)     _BFGET_(r16, 7, 7)
    #define   SET16Gbl_POR_1p8_3p3_por_io_3p3v_bypass(r16,v)   _BFSET_(r16, 7, 7,v)

    #define     w32Gbl_POR_1p8_3p3                             {\
            UNSG32 uPOR_1p8_3p3_por_io_1p8v_pd                 :  1;\
            UNSG32 uPOR_1p8_3p3_por_io_3p3v_pd                 :  1;\
            UNSG32 uPOR_1p8_3p3_por_io_1p8v_threshold          :  2;\
            UNSG32 uPOR_1p8_3p3_por_io_3p3v_threshold          :  2;\
            UNSG32 uPOR_1p8_3p3_por_io_1p8v_bypass             :  1;\
            UNSG32 uPOR_1p8_3p3_por_io_3p3v_bypass             :  1;\
            UNSG32 RSVDx620_b8                                 : 24;\
          }
    union { UNSG32 u32Gbl_POR_1p8_3p3;
            struct w32Gbl_POR_1p8_3p3;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx624                                    [60];
    ///////////////////////////////////////////////////////////
              SIE_PERIF                                        ie_PERIF;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx688                                    [376];
    ///////////////////////////////////////////////////////////
              SIE_ADC                                          ie_ADC;
    ///////////////////////////////////////////////////////////
              SIE_PVT_Sens                                     ie_PVT;
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_Global_PADRING_MODE_SEL(r32)            _BFGET_(r32, 0, 0)
    #define   SET32Gbl_Global_PADRING_MODE_SEL(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_Global_PADRING_MODE_SEL(r16)            _BFGET_(r16, 0, 0)
    #define   SET16Gbl_Global_PADRING_MODE_SEL(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_Global_PADRING_MODE_18(r32)             _BFGET_(r32, 1, 1)
    #define   SET32Gbl_Global_PADRING_MODE_18(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_Global_PADRING_MODE_18(r16)             _BFGET_(r16, 1, 1)
    #define   SET16Gbl_Global_PADRING_MODE_18(r16,v)           _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_Global_PADRING                          {\
            UNSG32 uGlobal_PADRING_MODE_SEL                    :  1;\
            UNSG32 uGlobal_PADRING_MODE_18                     :  1;\
            UNSG32 RSVDx81C_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_Global_PADRING;
            struct w32Gbl_Global_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI_PADRING_MODE_SEL(r32)               _BFGET_(r32, 0, 0)
    #define   SET32Gbl_SPI_PADRING_MODE_SEL(r32,v)             _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_SPI_PADRING_MODE_SEL(r16)               _BFGET_(r16, 0, 0)
    #define   SET16Gbl_SPI_PADRING_MODE_SEL(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_SPI_PADRING_MODE_18(r32)                _BFGET_(r32, 1, 1)
    #define   SET32Gbl_SPI_PADRING_MODE_18(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_SPI_PADRING_MODE_18(r16)                _BFGET_(r16, 1, 1)
    #define   SET16Gbl_SPI_PADRING_MODE_18(r16,v)              _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_SPI_PADRING                             {\
            UNSG32 uSPI_PADRING_MODE_SEL                       :  1;\
            UNSG32 uSPI_PADRING_MODE_18                        :  1;\
            UNSG32 RSVDx820_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_SPI_PADRING;
            struct w32Gbl_SPI_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_PADRING_MODE_SEL(r32)              _BFGET_(r32, 0, 0)
    #define   SET32Gbl_NAND_PADRING_MODE_SEL(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_NAND_PADRING_MODE_SEL(r16)              _BFGET_(r16, 0, 0)
    #define   SET16Gbl_NAND_PADRING_MODE_SEL(r16,v)            _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_NAND_PADRING_MODE_18(r32)               _BFGET_(r32, 1, 1)
    #define   SET32Gbl_NAND_PADRING_MODE_18(r32,v)             _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_NAND_PADRING_MODE_18(r16)               _BFGET_(r16, 1, 1)
    #define   SET16Gbl_NAND_PADRING_MODE_18(r16,v)             _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_NAND_PADRING                            {\
            UNSG32 uNAND_PADRING_MODE_SEL                      :  1;\
            UNSG32 uNAND_PADRING_MODE_18                       :  1;\
            UNSG32 RSVDx824_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_NAND_PADRING;
            struct w32Gbl_NAND_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_PADRING_MODE_SEL(r32)               _BFGET_(r32, 0, 0)
    #define   SET32Gbl_SD0_PADRING_MODE_SEL(r32,v)             _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_SD0_PADRING_MODE_SEL(r16)               _BFGET_(r16, 0, 0)
    #define   SET16Gbl_SD0_PADRING_MODE_SEL(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_SD0_PADRING_MODE_18(r32)                _BFGET_(r32, 1, 1)
    #define   SET32Gbl_SD0_PADRING_MODE_18(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_SD0_PADRING_MODE_18(r16)                _BFGET_(r16, 1, 1)
    #define   SET16Gbl_SD0_PADRING_MODE_18(r16,v)              _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_SD0_PADRING                             {\
            UNSG32 uSD0_PADRING_MODE_SEL                       :  1;\
            UNSG32 uSD0_PADRING_MODE_18                        :  1;\
            UNSG32 RSVDx828_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_SD0_PADRING;
            struct w32Gbl_SD0_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S_PADRING_MODE_SEL(r32)               _BFGET_(r32, 0, 0)
    #define   SET32Gbl_I2S_PADRING_MODE_SEL(r32,v)             _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_I2S_PADRING_MODE_SEL(r16)               _BFGET_(r16, 0, 0)
    #define   SET16Gbl_I2S_PADRING_MODE_SEL(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_I2S_PADRING_MODE_18(r32)                _BFGET_(r32, 1, 1)
    #define   SET32Gbl_I2S_PADRING_MODE_18(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_I2S_PADRING_MODE_18(r16)                _BFGET_(r16, 1, 1)
    #define   SET16Gbl_I2S_PADRING_MODE_18(r16,v)              _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_I2S_PADRING                             {\
            UNSG32 uI2S_PADRING_MODE_SEL                       :  1;\
            UNSG32 uI2S_PADRING_MODE_18                        :  1;\
            UNSG32 RSVDx82C_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_I2S_PADRING;
            struct w32Gbl_I2S_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S3_PADRING_MODE_SEL(r32)              _BFGET_(r32, 0, 0)
    #define   SET32Gbl_I2S3_PADRING_MODE_SEL(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_I2S3_PADRING_MODE_SEL(r16)              _BFGET_(r16, 0, 0)
    #define   SET16Gbl_I2S3_PADRING_MODE_SEL(r16,v)            _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_I2S3_PADRING_MODE_18(r32)               _BFGET_(r32, 1, 1)
    #define   SET32Gbl_I2S3_PADRING_MODE_18(r32,v)             _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_I2S3_PADRING_MODE_18(r16)               _BFGET_(r16, 1, 1)
    #define   SET16Gbl_I2S3_PADRING_MODE_18(r16,v)             _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_I2S3_PADRING                            {\
            UNSG32 uI2S3_PADRING_MODE_SEL                      :  1;\
            UNSG32 uI2S3_PADRING_MODE_18                       :  1;\
            UNSG32 RSVDx830_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_I2S3_PADRING;
            struct w32Gbl_I2S3_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM_PADRING_MODE_SEL(r32)               _BFGET_(r32, 0, 0)
    #define   SET32Gbl_PWM_PADRING_MODE_SEL(r32,v)             _BFSET_(r32, 0, 0,v)
    #define   GET16Gbl_PWM_PADRING_MODE_SEL(r16)               _BFGET_(r16, 0, 0)
    #define   SET16Gbl_PWM_PADRING_MODE_SEL(r16,v)             _BFSET_(r16, 0, 0,v)

    #define   GET32Gbl_PWM_PADRING_MODE_18(r32)                _BFGET_(r32, 1, 1)
    #define   SET32Gbl_PWM_PADRING_MODE_18(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16Gbl_PWM_PADRING_MODE_18(r16)                _BFGET_(r16, 1, 1)
    #define   SET16Gbl_PWM_PADRING_MODE_18(r16,v)              _BFSET_(r16, 1, 1,v)

    #define     w32Gbl_PWM_PADRING                             {\
            UNSG32 uPWM_PADRING_MODE_SEL                       :  1;\
            UNSG32 uPWM_PADRING_MODE_18                        :  1;\
            UNSG32 RSVDx834_b2                                 : 30;\
          }
    union { UNSG32 u32Gbl_PWM_PADRING;
            struct w32Gbl_PWM_PADRING;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_XTL_CTL_XTL_GM_SEL(r32)                 _BFGET_(r32, 3, 0)
    #define   SET32Gbl_XTL_CTL_XTL_GM_SEL(r32,v)               _BFSET_(r32, 3, 0,v)
    #define   GET16Gbl_XTL_CTL_XTL_GM_SEL(r16)                 _BFGET_(r16, 3, 0)
    #define   SET16Gbl_XTL_CTL_XTL_GM_SEL(r16,v)               _BFSET_(r16, 3, 0,v)

    #define     w32Gbl_XTL_CTL                                 {\
            UNSG32 uXTL_CTL_XTL_GM_SEL                         :  4;\
            UNSG32 RSVDx838_b4                                 : 28;\
          }
    union { UNSG32 u32Gbl_XTL_CTL;
            struct w32Gbl_XTL_CTL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PADRING_MODE_OUT_MODE_OUT(r32)          _BFGET_(r32, 6, 0)
    #define   SET32Gbl_PADRING_MODE_OUT_MODE_OUT(r32,v)        _BFSET_(r32, 6, 0,v)
    #define   GET16Gbl_PADRING_MODE_OUT_MODE_OUT(r16)          _BFGET_(r16, 6, 0)
    #define   SET16Gbl_PADRING_MODE_OUT_MODE_OUT(r16,v)        _BFSET_(r16, 6, 0,v)

    #define     w32Gbl_PADRING_MODE_OUT                        {\
            UNSG32 uPADRING_MODE_OUT_MODE_OUT                  :  7;\
            UNSG32 RSVDx83C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_PADRING_MODE_OUT;
            struct w32Gbl_PADRING_MODE_OUT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_pinMuxCntlBus_I2S1_BCLKIO(r32)          _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_BCLKIO(r32,v)        _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S1_BCLKIO(r16)          _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_I2S1_BCLKIO(r16,v)        _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S1_LRCKIO(r32)          _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_LRCKIO(r32,v)        _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S1_LRCKIO(r16)          _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_I2S1_LRCKIO(r16,v)        _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S1_DO0(r32)             _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_DO0(r32,v)           _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S1_DO0(r16)             _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_I2S1_DO0(r16,v)           _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S1_DO1(r32)             _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_DO1(r32,v)           _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S1_DO1(r16)             _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_I2S1_DO1(r16,v)           _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S1_DO2(r32)             _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_DO2(r32,v)           _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S1_DO2(r16)             _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_I2S1_DO2(r16,v)           _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S1_DO3(r32)             _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_DO3(r32,v)           _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S1_MCLK(r32)            _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_I2S1_MCLK(r32,v)          _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S1_MCLK(r16)            _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_I2S1_MCLK(r16,v)          _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S2_BCLKIO(r32)          _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_I2S2_BCLKIO(r32,v)        _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S2_BCLKIO(r16)          _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_I2S2_BCLKIO(r16,v)        _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S2_LRCKIO(r32)          _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_I2S2_LRCKIO(r32,v)        _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S2_LRCKIO(r16)          _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_I2S2_LRCKIO(r16,v)        _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S2_DI0(r32)             _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_I2S2_DI0(r32,v)           _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S2_DI0(r16)             _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_I2S2_DI0(r16,v)           _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus                           {\
            UNSG32 upinMuxCntlBus_I2S1_BCLKIO                  :  3;\
            UNSG32 upinMuxCntlBus_I2S1_LRCKIO                  :  3;\
            UNSG32 upinMuxCntlBus_I2S1_DO0                     :  3;\
            UNSG32 upinMuxCntlBus_I2S1_DO1                     :  3;\
            UNSG32 upinMuxCntlBus_I2S1_DO2                     :  3;\
            UNSG32 upinMuxCntlBus_I2S1_DO3                     :  3;\
            UNSG32 upinMuxCntlBus_I2S1_MCLK                    :  3;\
            UNSG32 upinMuxCntlBus_I2S2_BCLKIO                  :  3;\
            UNSG32 upinMuxCntlBus_I2S2_LRCKIO                  :  3;\
            UNSG32 upinMuxCntlBus_I2S2_DI0                     :  3;\
            UNSG32 RSVDx840_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus;
            struct w32Gbl_pinMuxCntlBus;
          };
    #define   GET32Gbl_pinMuxCntlBus_I2S2_DI1(r32)             _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_I2S2_DI1(r32,v)           _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S2_DI1(r16)             _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_I2S2_DI1(r16,v)           _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S2_DI2(r32)             _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_I2S2_DI2(r32,v)           _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S2_DI2(r16)             _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_I2S2_DI2(r16,v)           _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S2_DI3(r32)             _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_I2S2_DI3(r32,v)           _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S2_DI3(r16)             _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_I2S2_DI3(r16,v)           _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_PDM_CLKO(r32)             _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_PDM_CLKO(r32,v)           _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_PDM_CLKO(r16)             _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_PDM_CLKO(r16,v)           _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_PDM_DI0(r32)              _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_PDM_DI0(r32,v)            _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_PDM_DI0(r16)              _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_PDM_DI0(r16,v)            _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_PDM_DI1(r32)              _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_PDM_DI1(r32,v)            _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_PDM_DI2(r32)              _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_PDM_DI2(r32,v)            _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_PDM_DI2(r16)              _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_PDM_DI2(r16,v)            _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_PDM_DI3(r32)              _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_PDM_DI3(r32,v)            _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_PDM_DI3(r16)              _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_PDM_DI3(r16,v)            _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO0(r32)             _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO0(r32,v)           _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO0(r16)             _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO0(r16,v)           _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO1(r32)             _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO1(r32,v)           _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO1(r16)             _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO1(r16,v)           _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus1                          {\
            UNSG32 upinMuxCntlBus_I2S2_DI1                     :  3;\
            UNSG32 upinMuxCntlBus_I2S2_DI2                     :  3;\
            UNSG32 upinMuxCntlBus_I2S2_DI3                     :  3;\
            UNSG32 upinMuxCntlBus_PDM_CLKO                     :  3;\
            UNSG32 upinMuxCntlBus_PDM_DI0                      :  3;\
            UNSG32 upinMuxCntlBus_PDM_DI1                      :  3;\
            UNSG32 upinMuxCntlBus_PDM_DI2                      :  3;\
            UNSG32 upinMuxCntlBus_PDM_DI3                      :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO0                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO1                     :  3;\
            UNSG32 RSVDx844_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus1;
            struct w32Gbl_pinMuxCntlBus1;
          };
    #define   GET32Gbl_pinMuxCntlBus_NAND_IO2(r32)             _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO2(r32,v)           _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO2(r16)             _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO2(r16,v)           _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO3(r32)             _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO3(r32,v)           _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO3(r16)             _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO3(r16,v)           _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO4(r32)             _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO4(r32,v)           _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO4(r16)             _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO4(r16,v)           _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO5(r32)             _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO5(r32,v)           _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO5(r16)             _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO5(r16,v)           _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO6(r32)             _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO6(r32,v)           _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_IO6(r16)             _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_NAND_IO6(r16,v)           _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_IO7(r32)             _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_NAND_IO7(r32,v)           _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_ALE(r32)             _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_NAND_ALE(r32,v)           _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_ALE(r16)             _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_NAND_ALE(r16,v)           _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_CLE(r32)             _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_NAND_CLE(r32,v)           _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_CLE(r16)             _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_NAND_CLE(r16,v)           _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_WEn(r32)             _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_NAND_WEn(r32,v)           _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_WEn(r16)             _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_NAND_WEn(r16,v)           _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_REn(r32)             _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_NAND_REn(r32,v)           _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_REn(r16)             _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_NAND_REn(r16,v)           _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus2                          {\
            UNSG32 upinMuxCntlBus_NAND_IO2                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO3                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO4                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO5                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO6                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_IO7                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_ALE                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_CLE                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_WEn                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_REn                     :  3;\
            UNSG32 RSVDx848_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus2;
            struct w32Gbl_pinMuxCntlBus2;
          };
    #define   GET32Gbl_pinMuxCntlBus_NAND_WPn(r32)             _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_NAND_WPn(r32,v)           _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_WPn(r16)             _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_NAND_WPn(r16,v)           _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_CEn(r32)             _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_NAND_CEn(r32,v)           _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_CEn(r16)             _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_NAND_CEn(r16,v)           _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_NAND_RDY(r32)             _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_NAND_RDY(r32,v)           _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_NAND_RDY(r16)             _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_NAND_RDY(r16,v)           _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SS0n(r32)            _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SS0n(r32,v)          _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_SPI1_SS0n(r16)            _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_SPI1_SS0n(r16,v)          _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SS1n(r32)            _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SS1n(r32,v)          _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_SPI1_SS1n(r16)            _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_SPI1_SS1n(r16,v)          _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SS2n(r32)            _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SS2n(r32,v)          _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SS3n(r32)            _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SS3n(r32,v)          _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_SPI1_SS3n(r16)            _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_SPI1_SS3n(r16,v)          _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SCLK(r32)            _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SCLK(r32,v)          _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_SPI1_SCLK(r16)            _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_SPI1_SCLK(r16,v)          _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SDO(r32)             _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SDO(r32,v)           _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_SPI1_SDO(r16)             _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_SPI1_SDO(r16,v)           _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_SPI1_SDI(r32)             _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_SPI1_SDI(r32,v)           _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_SPI1_SDI(r16)             _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_SPI1_SDI(r16,v)           _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus3                          {\
            UNSG32 upinMuxCntlBus_NAND_WPn                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_CEn                     :  3;\
            UNSG32 upinMuxCntlBus_NAND_RDY                     :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SS0n                    :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SS1n                    :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SS2n                    :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SS3n                    :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SCLK                    :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SDO                     :  3;\
            UNSG32 upinMuxCntlBus_SPI1_SDI                     :  3;\
            UNSG32 RSVDx84C_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus3;
            struct w32Gbl_pinMuxCntlBus3;
          };
    #define   GET32Gbl_pinMuxCntlBus_USB0_DRV_VBUS(r32)        _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_USB0_DRV_VBUS(r32,v)      _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_USB0_DRV_VBUS(r16)        _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_USB0_DRV_VBUS(r16,v)      _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_TW1_SCL(r32)              _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_TW1_SCL(r32,v)            _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_TW1_SCL(r16)              _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_TW1_SCL(r16,v)            _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_TW1_SDA(r32)              _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_TW1_SDA(r32,v)            _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_TW1_SDA(r16)              _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_TW1_SDA(r16,v)            _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_TW0_SCL(r32)              _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_TW0_SCL(r32,v)            _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_TW0_SCL(r16)              _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_TW0_SCL(r16,v)            _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_TW0_SDA(r32)              _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_TW0_SDA(r32,v)            _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_TW0_SDA(r16)              _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_TW0_SDA(r16,v)            _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_TMS(r32)                  _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_TMS(r32,v)                _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_TDI(r32)                  _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_TDI(r32,v)                _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_TDI(r16)                  _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_TDI(r16,v)                _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_TDO(r32)                  _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_TDO(r32,v)                _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_TDO(r16)                  _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_TDO(r16,v)                _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM6(r32)                 _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_PWM6(r32,v)               _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM6(r16)                 _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_PWM6(r16,v)               _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM7(r32)                 _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_PWM7(r32,v)               _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM7(r16)                 _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_PWM7(r16,v)               _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus4                          {\
            UNSG32 upinMuxCntlBus_USB0_DRV_VBUS                :  3;\
            UNSG32 upinMuxCntlBus_TW1_SCL                      :  3;\
            UNSG32 upinMuxCntlBus_TW1_SDA                      :  3;\
            UNSG32 upinMuxCntlBus_TW0_SCL                      :  3;\
            UNSG32 upinMuxCntlBus_TW0_SDA                      :  3;\
            UNSG32 upinMuxCntlBus_TMS                          :  3;\
            UNSG32 upinMuxCntlBus_TDI                          :  3;\
            UNSG32 upinMuxCntlBus_TDO                          :  3;\
            UNSG32 upinMuxCntlBus_PWM6                         :  3;\
            UNSG32 upinMuxCntlBus_PWM7                         :  3;\
            UNSG32 RSVDx850_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus4;
            struct w32Gbl_pinMuxCntlBus4;
          };
    #define   GET32Gbl_pinMuxCntlBus_PWM0(r32)                 _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_PWM0(r32,v)               _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM0(r16)                 _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_PWM0(r16,v)               _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM1(r32)                 _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_PWM1(r32,v)               _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM1(r16)                 _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_PWM1(r16,v)               _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM2(r32)                 _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_PWM2(r32,v)               _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM2(r16)                 _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_PWM2(r16,v)               _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM3(r32)                 _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_PWM3(r32,v)               _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM3(r16)                 _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_PWM3(r16,v)               _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM4(r32)                 _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_PWM4(r32,v)               _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_PWM4(r16)                 _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_PWM4(r16,v)               _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_PWM5(r32)                 _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_PWM5(r32,v)               _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_URT1_RTSn(r32)            _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_URT1_RTSn(r32,v)          _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_URT1_RTSn(r16)            _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_URT1_RTSn(r16,v)          _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_URT1_CTSn(r32)            _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_URT1_CTSn(r32,v)          _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_URT1_CTSn(r16)            _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_URT1_CTSn(r16,v)          _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_URT1_RXD(r32)             _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_URT1_RXD(r32,v)           _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_URT1_RXD(r16)             _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_URT1_RXD(r16,v)           _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_URT1_TXD(r32)             _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_URT1_TXD(r32,v)           _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_URT1_TXD(r16)             _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_URT1_TXD(r16,v)           _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus5                          {\
            UNSG32 upinMuxCntlBus_PWM0                         :  3;\
            UNSG32 upinMuxCntlBus_PWM1                         :  3;\
            UNSG32 upinMuxCntlBus_PWM2                         :  3;\
            UNSG32 upinMuxCntlBus_PWM3                         :  3;\
            UNSG32 upinMuxCntlBus_PWM4                         :  3;\
            UNSG32 upinMuxCntlBus_PWM5                         :  3;\
            UNSG32 upinMuxCntlBus_URT1_RTSn                    :  3;\
            UNSG32 upinMuxCntlBus_URT1_CTSn                    :  3;\
            UNSG32 upinMuxCntlBus_URT1_RXD                     :  3;\
            UNSG32 upinMuxCntlBus_URT1_TXD                     :  3;\
            UNSG32 RSVDx854_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus5;
            struct w32Gbl_pinMuxCntlBus5;
          };
    #define   GET32Gbl_pinMuxCntlBus_I2S3_DI(r32)              _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_I2S3_DI(r32,v)            _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S3_DI(r16)              _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_I2S3_DI(r16,v)            _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S3_DO(r32)              _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_I2S3_DO(r32,v)            _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S3_DO(r16)              _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_I2S3_DO(r16,v)            _BFSET_(r16, 5, 3,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S3_BCLKIO(r32)          _BFGET_(r32, 8, 6)
    #define   SET32Gbl_pinMuxCntlBus_I2S3_BCLKIO(r32,v)        _BFSET_(r32, 8, 6,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S3_BCLKIO(r16)          _BFGET_(r16, 8, 6)
    #define   SET16Gbl_pinMuxCntlBus_I2S3_BCLKIO(r16,v)        _BFSET_(r16, 8, 6,v)

    #define   GET32Gbl_pinMuxCntlBus_I2S3_LRCKIO(r32)          _BFGET_(r32,11, 9)
    #define   SET32Gbl_pinMuxCntlBus_I2S3_LRCKIO(r32,v)        _BFSET_(r32,11, 9,v)
    #define   GET16Gbl_pinMuxCntlBus_I2S3_LRCKIO(r16)          _BFGET_(r16,11, 9)
    #define   SET16Gbl_pinMuxCntlBus_I2S3_LRCKIO(r16,v)        _BFSET_(r16,11, 9,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_DAT0(r32)             _BFGET_(r32,14,12)
    #define   SET32Gbl_pinMuxCntlBus_SD0_DAT0(r32,v)           _BFSET_(r32,14,12,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_DAT0(r16)             _BFGET_(r16,14,12)
    #define   SET16Gbl_pinMuxCntlBus_SD0_DAT0(r16,v)           _BFSET_(r16,14,12,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_DAT1(r32)             _BFGET_(r32,17,15)
    #define   SET32Gbl_pinMuxCntlBus_SD0_DAT1(r32,v)           _BFSET_(r32,17,15,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_CLK(r32)              _BFGET_(r32,20,18)
    #define   SET32Gbl_pinMuxCntlBus_SD0_CLK(r32,v)            _BFSET_(r32,20,18,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_CLK(r16)              _BFGET_(r16, 4, 2)
    #define   SET16Gbl_pinMuxCntlBus_SD0_CLK(r16,v)            _BFSET_(r16, 4, 2,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_DAT2(r32)             _BFGET_(r32,23,21)
    #define   SET32Gbl_pinMuxCntlBus_SD0_DAT2(r32,v)           _BFSET_(r32,23,21,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_DAT2(r16)             _BFGET_(r16, 7, 5)
    #define   SET16Gbl_pinMuxCntlBus_SD0_DAT2(r16,v)           _BFSET_(r16, 7, 5,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_DAT3(r32)             _BFGET_(r32,26,24)
    #define   SET32Gbl_pinMuxCntlBus_SD0_DAT3(r32,v)           _BFSET_(r32,26,24,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_DAT3(r16)             _BFGET_(r16,10, 8)
    #define   SET16Gbl_pinMuxCntlBus_SD0_DAT3(r16,v)           _BFSET_(r16,10, 8,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_CMD(r32)              _BFGET_(r32,29,27)
    #define   SET32Gbl_pinMuxCntlBus_SD0_CMD(r32,v)            _BFSET_(r32,29,27,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_CMD(r16)              _BFGET_(r16,13,11)
    #define   SET16Gbl_pinMuxCntlBus_SD0_CMD(r16,v)            _BFSET_(r16,13,11,v)

    #define     w32Gbl_pinMuxCntlBus6                          {\
            UNSG32 upinMuxCntlBus_I2S3_DI                      :  3;\
            UNSG32 upinMuxCntlBus_I2S3_DO                      :  3;\
            UNSG32 upinMuxCntlBus_I2S3_BCLKIO                  :  3;\
            UNSG32 upinMuxCntlBus_I2S3_LRCKIO                  :  3;\
            UNSG32 upinMuxCntlBus_SD0_DAT0                     :  3;\
            UNSG32 upinMuxCntlBus_SD0_DAT1                     :  3;\
            UNSG32 upinMuxCntlBus_SD0_CLK                      :  3;\
            UNSG32 upinMuxCntlBus_SD0_DAT2                     :  3;\
            UNSG32 upinMuxCntlBus_SD0_DAT3                     :  3;\
            UNSG32 upinMuxCntlBus_SD0_CMD                      :  3;\
            UNSG32 RSVDx858_b30                                :  2;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus6;
            struct w32Gbl_pinMuxCntlBus6;
          };
    #define   GET32Gbl_pinMuxCntlBus_SD0_CDn(r32)              _BFGET_(r32, 2, 0)
    #define   SET32Gbl_pinMuxCntlBus_SD0_CDn(r32,v)            _BFSET_(r32, 2, 0,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_CDn(r16)              _BFGET_(r16, 2, 0)
    #define   SET16Gbl_pinMuxCntlBus_SD0_CDn(r16,v)            _BFSET_(r16, 2, 0,v)

    #define   GET32Gbl_pinMuxCntlBus_SD0_WP(r32)               _BFGET_(r32, 5, 3)
    #define   SET32Gbl_pinMuxCntlBus_SD0_WP(r32,v)             _BFSET_(r32, 5, 3,v)
    #define   GET16Gbl_pinMuxCntlBus_SD0_WP(r16)               _BFGET_(r16, 5, 3)
    #define   SET16Gbl_pinMuxCntlBus_SD0_WP(r16,v)             _BFSET_(r16, 5, 3,v)

    #define     w32Gbl_pinMuxCntlBus7                          {\
            UNSG32 upinMuxCntlBus_SD0_CDn                      :  3;\
            UNSG32 upinMuxCntlBus_SD0_WP                       :  3;\
            UNSG32 RSVDx85C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_pinMuxCntlBus7;
            struct w32Gbl_pinMuxCntlBus7;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_BCLKIOCntl_DRV(r32)                _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_BCLKIOCntl_DRV(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_BCLKIOCntl_DRV(r16)                _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_BCLKIOCntl_DRV(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_BCLKIOCntl_PDEN(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_BCLKIOCntl_PDEN(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_BCLKIOCntl_PDEN(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_BCLKIOCntl_PDEN(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_BCLKIOCntl_PUEN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_BCLKIOCntl_PUEN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_BCLKIOCntl_PUEN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_BCLKIOCntl_PUEN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_BCLKIOCntl_RXEN(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_BCLKIOCntl_RXEN(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_BCLKIOCntl_RXEN(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_BCLKIOCntl_RXEN(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_BCLKIOCntl_SRC(r32)                _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_BCLKIOCntl_SRC(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_BCLKIOCntl_SRC(r16)                _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_BCLKIOCntl_SRC(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S1_BCLKIOCntl_SMTC(r32)               _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S1_BCLKIOCntl_SMTC(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S1_BCLKIOCntl_SMTC(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S1_BCLKIOCntl_SMTC(r16,v)             _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S1_BCLKIOCntl                         {\
            UNSG32 uI2S1_BCLKIOCntl_DRV                        :  2;\
            UNSG32 uI2S1_BCLKIOCntl_PDEN                       :  1;\
            UNSG32 uI2S1_BCLKIOCntl_PUEN                       :  1;\
            UNSG32 uI2S1_BCLKIOCntl_RXEN                       :  1;\
            UNSG32 uI2S1_BCLKIOCntl_SRC                        :  1;\
            UNSG32 uI2S1_BCLKIOCntl_SMTC                       :  1;\
            UNSG32 RSVDx860_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S1_BCLKIOCntl;
            struct w32Gbl_I2S1_BCLKIOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_LRCKIOCntl_DRV(r32)                _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_LRCKIOCntl_DRV(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_LRCKIOCntl_DRV(r16)                _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_LRCKIOCntl_DRV(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_LRCKIOCntl_PDEN(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_LRCKIOCntl_PDEN(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_LRCKIOCntl_PDEN(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_LRCKIOCntl_PDEN(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_LRCKIOCntl_PUEN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_LRCKIOCntl_PUEN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_LRCKIOCntl_PUEN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_LRCKIOCntl_PUEN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_LRCKIOCntl_RXEN(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_LRCKIOCntl_RXEN(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_LRCKIOCntl_RXEN(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_LRCKIOCntl_RXEN(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_LRCKIOCntl_SRC(r32)                _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_LRCKIOCntl_SRC(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_LRCKIOCntl_SRC(r16)                _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_LRCKIOCntl_SRC(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S1_LRCKIOCntl_SMTC(r32)               _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S1_LRCKIOCntl_SMTC(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S1_LRCKIOCntl_SMTC(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S1_LRCKIOCntl_SMTC(r16,v)             _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S1_LRCKIOCntl                         {\
            UNSG32 uI2S1_LRCKIOCntl_DRV                        :  2;\
            UNSG32 uI2S1_LRCKIOCntl_PDEN                       :  1;\
            UNSG32 uI2S1_LRCKIOCntl_PUEN                       :  1;\
            UNSG32 uI2S1_LRCKIOCntl_RXEN                       :  1;\
            UNSG32 uI2S1_LRCKIOCntl_SRC                        :  1;\
            UNSG32 uI2S1_LRCKIOCntl_SMTC                       :  1;\
            UNSG32 RSVDx864_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S1_LRCKIOCntl;
            struct w32Gbl_I2S1_LRCKIOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_DO0Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_DO0Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_DO0Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_DO0Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_DO0Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_DO0Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_DO0Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_DO0Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_DO0Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_DO0Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_DO0Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_DO0Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_DO0Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_DO0Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_DO0Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_DO0Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_DO0Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_DO0Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_DO0Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_DO0Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S1_DO0Cntl                            {\
            UNSG32 uI2S1_DO0Cntl_DRV                           :  2;\
            UNSG32 uI2S1_DO0Cntl_PDEN                          :  1;\
            UNSG32 uI2S1_DO0Cntl_PUEN                          :  1;\
            UNSG32 uI2S1_DO0Cntl_SRC                           :  1;\
            UNSG32 uI2S1_DO0Cntl_SMTC                          :  1;\
            UNSG32 RSVDx868_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S1_DO0Cntl;
            struct w32Gbl_I2S1_DO0Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_DO1Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_DO1Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_DO1Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_DO1Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_DO1Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_DO1Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_DO1Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_DO1Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_DO1Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_DO1Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_DO1Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_DO1Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_DO1Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_DO1Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_DO1Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_DO1Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_DO1Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_DO1Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_DO1Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_DO1Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S1_DO1Cntl                            {\
            UNSG32 uI2S1_DO1Cntl_DRV                           :  2;\
            UNSG32 uI2S1_DO1Cntl_PDEN                          :  1;\
            UNSG32 uI2S1_DO1Cntl_PUEN                          :  1;\
            UNSG32 uI2S1_DO1Cntl_SRC                           :  1;\
            UNSG32 uI2S1_DO1Cntl_SMTC                          :  1;\
            UNSG32 RSVDx86C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S1_DO1Cntl;
            struct w32Gbl_I2S1_DO1Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_DO2Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_DO2Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_DO2Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_DO2Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_DO2Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_DO2Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_DO2Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_DO2Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_DO2Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_DO2Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_DO2Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_DO2Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_DO2Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_DO2Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_DO2Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_DO2Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_DO2Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_DO2Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_DO2Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_DO2Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S1_DO2Cntl                            {\
            UNSG32 uI2S1_DO2Cntl_DRV                           :  2;\
            UNSG32 uI2S1_DO2Cntl_PDEN                          :  1;\
            UNSG32 uI2S1_DO2Cntl_PUEN                          :  1;\
            UNSG32 uI2S1_DO2Cntl_SRC                           :  1;\
            UNSG32 uI2S1_DO2Cntl_SMTC                          :  1;\
            UNSG32 RSVDx870_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S1_DO2Cntl;
            struct w32Gbl_I2S1_DO2Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_DO3Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_DO3Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_DO3Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_DO3Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_DO3Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_DO3Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_DO3Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_DO3Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_DO3Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_DO3Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_DO3Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_DO3Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_DO3Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_DO3Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_DO3Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_DO3Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_DO3Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_DO3Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_DO3Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_DO3Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S1_DO3Cntl                            {\
            UNSG32 uI2S1_DO3Cntl_DRV                           :  2;\
            UNSG32 uI2S1_DO3Cntl_PDEN                          :  1;\
            UNSG32 uI2S1_DO3Cntl_PUEN                          :  1;\
            UNSG32 uI2S1_DO3Cntl_SRC                           :  1;\
            UNSG32 uI2S1_DO3Cntl_SMTC                          :  1;\
            UNSG32 RSVDx874_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S1_DO3Cntl;
            struct w32Gbl_I2S1_DO3Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S1_MCLKCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S1_MCLKCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S1_MCLKCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S1_MCLKCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S1_MCLKCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S1_MCLKCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S1_MCLKCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S1_MCLKCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S1_MCLKCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S1_MCLKCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S1_MCLKCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S1_MCLKCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S1_MCLKCntl_RXEN(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S1_MCLKCntl_RXEN(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S1_MCLKCntl_RXEN(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S1_MCLKCntl_RXEN(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S1_MCLKCntl_SRC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S1_MCLKCntl_SRC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S1_MCLKCntl_SRC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S1_MCLKCntl_SRC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S1_MCLKCntl_SMTC(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S1_MCLKCntl_SMTC(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S1_MCLKCntl_SMTC(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S1_MCLKCntl_SMTC(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S1_MCLKCntl                           {\
            UNSG32 uI2S1_MCLKCntl_DRV                          :  2;\
            UNSG32 uI2S1_MCLKCntl_PDEN                         :  1;\
            UNSG32 uI2S1_MCLKCntl_PUEN                         :  1;\
            UNSG32 uI2S1_MCLKCntl_RXEN                         :  1;\
            UNSG32 uI2S1_MCLKCntl_SRC                          :  1;\
            UNSG32 uI2S1_MCLKCntl_SMTC                         :  1;\
            UNSG32 RSVDx878_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S1_MCLKCntl;
            struct w32Gbl_I2S1_MCLKCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S2_BCLKIOCntl_DRV(r32)                _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S2_BCLKIOCntl_DRV(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S2_BCLKIOCntl_DRV(r16)                _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S2_BCLKIOCntl_DRV(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S2_BCLKIOCntl_PDEN(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S2_BCLKIOCntl_PDEN(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S2_BCLKIOCntl_PDEN(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S2_BCLKIOCntl_PDEN(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S2_BCLKIOCntl_PUEN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S2_BCLKIOCntl_PUEN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S2_BCLKIOCntl_PUEN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S2_BCLKIOCntl_PUEN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S2_BCLKIOCntl_RXEN(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S2_BCLKIOCntl_RXEN(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S2_BCLKIOCntl_RXEN(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S2_BCLKIOCntl_RXEN(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S2_BCLKIOCntl_SRC(r32)                _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S2_BCLKIOCntl_SRC(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S2_BCLKIOCntl_SRC(r16)                _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S2_BCLKIOCntl_SRC(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S2_BCLKIOCntl_SMTC(r32)               _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S2_BCLKIOCntl_SMTC(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S2_BCLKIOCntl_SMTC(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S2_BCLKIOCntl_SMTC(r16,v)             _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S2_BCLKIOCntl                         {\
            UNSG32 uI2S2_BCLKIOCntl_DRV                        :  2;\
            UNSG32 uI2S2_BCLKIOCntl_PDEN                       :  1;\
            UNSG32 uI2S2_BCLKIOCntl_PUEN                       :  1;\
            UNSG32 uI2S2_BCLKIOCntl_RXEN                       :  1;\
            UNSG32 uI2S2_BCLKIOCntl_SRC                        :  1;\
            UNSG32 uI2S2_BCLKIOCntl_SMTC                       :  1;\
            UNSG32 RSVDx87C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S2_BCLKIOCntl;
            struct w32Gbl_I2S2_BCLKIOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S2_LRCKIOCntl_DRV(r32)                _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S2_LRCKIOCntl_DRV(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S2_LRCKIOCntl_DRV(r16)                _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S2_LRCKIOCntl_DRV(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S2_LRCKIOCntl_PDEN(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S2_LRCKIOCntl_PDEN(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S2_LRCKIOCntl_PDEN(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S2_LRCKIOCntl_PDEN(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S2_LRCKIOCntl_PUEN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S2_LRCKIOCntl_PUEN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S2_LRCKIOCntl_PUEN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S2_LRCKIOCntl_PUEN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S2_LRCKIOCntl_RXEN(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S2_LRCKIOCntl_RXEN(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S2_LRCKIOCntl_RXEN(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S2_LRCKIOCntl_RXEN(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S2_LRCKIOCntl_SRC(r32)                _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S2_LRCKIOCntl_SRC(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S2_LRCKIOCntl_SRC(r16)                _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S2_LRCKIOCntl_SRC(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S2_LRCKIOCntl_SMTC(r32)               _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S2_LRCKIOCntl_SMTC(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S2_LRCKIOCntl_SMTC(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S2_LRCKIOCntl_SMTC(r16,v)             _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S2_LRCKIOCntl                         {\
            UNSG32 uI2S2_LRCKIOCntl_DRV                        :  2;\
            UNSG32 uI2S2_LRCKIOCntl_PDEN                       :  1;\
            UNSG32 uI2S2_LRCKIOCntl_PUEN                       :  1;\
            UNSG32 uI2S2_LRCKIOCntl_RXEN                       :  1;\
            UNSG32 uI2S2_LRCKIOCntl_SRC                        :  1;\
            UNSG32 uI2S2_LRCKIOCntl_SMTC                       :  1;\
            UNSG32 RSVDx880_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S2_LRCKIOCntl;
            struct w32Gbl_I2S2_LRCKIOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S2_DI0Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S2_DI0Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S2_DI0Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S2_DI0Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S2_DI0Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S2_DI0Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S2_DI0Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S2_DI0Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S2_DI0Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S2_DI0Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S2_DI0Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S2_DI0Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S2_DI0Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S2_DI0Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S2_DI0Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S2_DI0Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S2_DI0Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S2_DI0Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S2_DI0Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S2_DI0Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S2_DI0Cntl                            {\
            UNSG32 uI2S2_DI0Cntl_DRV                           :  2;\
            UNSG32 uI2S2_DI0Cntl_PDEN                          :  1;\
            UNSG32 uI2S2_DI0Cntl_PUEN                          :  1;\
            UNSG32 uI2S2_DI0Cntl_SRC                           :  1;\
            UNSG32 uI2S2_DI0Cntl_SMTC                          :  1;\
            UNSG32 RSVDx884_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S2_DI0Cntl;
            struct w32Gbl_I2S2_DI0Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S2_DI1Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S2_DI1Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S2_DI1Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S2_DI1Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S2_DI1Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S2_DI1Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S2_DI1Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S2_DI1Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S2_DI1Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S2_DI1Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S2_DI1Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S2_DI1Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S2_DI1Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S2_DI1Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S2_DI1Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S2_DI1Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S2_DI1Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S2_DI1Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S2_DI1Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S2_DI1Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S2_DI1Cntl                            {\
            UNSG32 uI2S2_DI1Cntl_DRV                           :  2;\
            UNSG32 uI2S2_DI1Cntl_PDEN                          :  1;\
            UNSG32 uI2S2_DI1Cntl_PUEN                          :  1;\
            UNSG32 uI2S2_DI1Cntl_SRC                           :  1;\
            UNSG32 uI2S2_DI1Cntl_SMTC                          :  1;\
            UNSG32 RSVDx888_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S2_DI1Cntl;
            struct w32Gbl_I2S2_DI1Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S2_DI2Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S2_DI2Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S2_DI2Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S2_DI2Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S2_DI2Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S2_DI2Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S2_DI2Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S2_DI2Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S2_DI2Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S2_DI2Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S2_DI2Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S2_DI2Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S2_DI2Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S2_DI2Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S2_DI2Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S2_DI2Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S2_DI2Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S2_DI2Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S2_DI2Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S2_DI2Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S2_DI2Cntl                            {\
            UNSG32 uI2S2_DI2Cntl_DRV                           :  2;\
            UNSG32 uI2S2_DI2Cntl_PDEN                          :  1;\
            UNSG32 uI2S2_DI2Cntl_PUEN                          :  1;\
            UNSG32 uI2S2_DI2Cntl_SRC                           :  1;\
            UNSG32 uI2S2_DI2Cntl_SMTC                          :  1;\
            UNSG32 RSVDx88C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S2_DI2Cntl;
            struct w32Gbl_I2S2_DI2Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S2_DI3Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S2_DI3Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S2_DI3Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S2_DI3Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S2_DI3Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S2_DI3Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S2_DI3Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S2_DI3Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S2_DI3Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S2_DI3Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S2_DI3Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S2_DI3Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S2_DI3Cntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S2_DI3Cntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S2_DI3Cntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S2_DI3Cntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S2_DI3Cntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S2_DI3Cntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S2_DI3Cntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S2_DI3Cntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S2_DI3Cntl                            {\
            UNSG32 uI2S2_DI3Cntl_DRV                           :  2;\
            UNSG32 uI2S2_DI3Cntl_PDEN                          :  1;\
            UNSG32 uI2S2_DI3Cntl_PUEN                          :  1;\
            UNSG32 uI2S2_DI3Cntl_SRC                           :  1;\
            UNSG32 uI2S2_DI3Cntl_SMTC                          :  1;\
            UNSG32 RSVDx890_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S2_DI3Cntl;
            struct w32Gbl_I2S2_DI3Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PDM_CLKOCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PDM_CLKOCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PDM_CLKOCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PDM_CLKOCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PDM_CLKOCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PDM_CLKOCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PDM_CLKOCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PDM_CLKOCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PDM_CLKOCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PDM_CLKOCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PDM_CLKOCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PDM_CLKOCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PDM_CLKOCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PDM_CLKOCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PDM_CLKOCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PDM_CLKOCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PDM_CLKOCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PDM_CLKOCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PDM_CLKOCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PDM_CLKOCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PDM_CLKOCntl                            {\
            UNSG32 uPDM_CLKOCntl_DRV                           :  2;\
            UNSG32 uPDM_CLKOCntl_PDEN                          :  1;\
            UNSG32 uPDM_CLKOCntl_PUEN                          :  1;\
            UNSG32 uPDM_CLKOCntl_SRC                           :  1;\
            UNSG32 uPDM_CLKOCntl_SMTC                          :  1;\
            UNSG32 RSVDx894_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PDM_CLKOCntl;
            struct w32Gbl_PDM_CLKOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PDM_DI0Cntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PDM_DI0Cntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PDM_DI0Cntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PDM_DI0Cntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PDM_DI0Cntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PDM_DI0Cntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PDM_DI0Cntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PDM_DI0Cntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PDM_DI0Cntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PDM_DI0Cntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PDM_DI0Cntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PDM_DI0Cntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PDM_DI0Cntl_SRC(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PDM_DI0Cntl_SRC(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PDM_DI0Cntl_SRC(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PDM_DI0Cntl_SRC(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PDM_DI0Cntl_SMTC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PDM_DI0Cntl_SMTC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PDM_DI0Cntl_SMTC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PDM_DI0Cntl_SMTC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PDM_DI0Cntl                             {\
            UNSG32 uPDM_DI0Cntl_DRV                            :  2;\
            UNSG32 uPDM_DI0Cntl_PDEN                           :  1;\
            UNSG32 uPDM_DI0Cntl_PUEN                           :  1;\
            UNSG32 uPDM_DI0Cntl_SRC                            :  1;\
            UNSG32 uPDM_DI0Cntl_SMTC                           :  1;\
            UNSG32 RSVDx898_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PDM_DI0Cntl;
            struct w32Gbl_PDM_DI0Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PDM_DI1Cntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PDM_DI1Cntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PDM_DI1Cntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PDM_DI1Cntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PDM_DI1Cntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PDM_DI1Cntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PDM_DI1Cntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PDM_DI1Cntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PDM_DI1Cntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PDM_DI1Cntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PDM_DI1Cntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PDM_DI1Cntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PDM_DI1Cntl_SRC(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PDM_DI1Cntl_SRC(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PDM_DI1Cntl_SRC(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PDM_DI1Cntl_SRC(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PDM_DI1Cntl_SMTC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PDM_DI1Cntl_SMTC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PDM_DI1Cntl_SMTC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PDM_DI1Cntl_SMTC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PDM_DI1Cntl                             {\
            UNSG32 uPDM_DI1Cntl_DRV                            :  2;\
            UNSG32 uPDM_DI1Cntl_PDEN                           :  1;\
            UNSG32 uPDM_DI1Cntl_PUEN                           :  1;\
            UNSG32 uPDM_DI1Cntl_SRC                            :  1;\
            UNSG32 uPDM_DI1Cntl_SMTC                           :  1;\
            UNSG32 RSVDx89C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PDM_DI1Cntl;
            struct w32Gbl_PDM_DI1Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PDM_DI2Cntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PDM_DI2Cntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PDM_DI2Cntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PDM_DI2Cntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PDM_DI2Cntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PDM_DI2Cntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PDM_DI2Cntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PDM_DI2Cntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PDM_DI2Cntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PDM_DI2Cntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PDM_DI2Cntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PDM_DI2Cntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PDM_DI2Cntl_SRC(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PDM_DI2Cntl_SRC(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PDM_DI2Cntl_SRC(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PDM_DI2Cntl_SRC(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PDM_DI2Cntl_SMTC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PDM_DI2Cntl_SMTC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PDM_DI2Cntl_SMTC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PDM_DI2Cntl_SMTC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PDM_DI2Cntl                             {\
            UNSG32 uPDM_DI2Cntl_DRV                            :  2;\
            UNSG32 uPDM_DI2Cntl_PDEN                           :  1;\
            UNSG32 uPDM_DI2Cntl_PUEN                           :  1;\
            UNSG32 uPDM_DI2Cntl_SRC                            :  1;\
            UNSG32 uPDM_DI2Cntl_SMTC                           :  1;\
            UNSG32 RSVDx8A0_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PDM_DI2Cntl;
            struct w32Gbl_PDM_DI2Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PDM_DI3Cntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PDM_DI3Cntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PDM_DI3Cntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PDM_DI3Cntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PDM_DI3Cntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PDM_DI3Cntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PDM_DI3Cntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PDM_DI3Cntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PDM_DI3Cntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PDM_DI3Cntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PDM_DI3Cntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PDM_DI3Cntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PDM_DI3Cntl_SRC(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PDM_DI3Cntl_SRC(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PDM_DI3Cntl_SRC(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PDM_DI3Cntl_SRC(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PDM_DI3Cntl_SMTC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PDM_DI3Cntl_SMTC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PDM_DI3Cntl_SMTC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PDM_DI3Cntl_SMTC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PDM_DI3Cntl                             {\
            UNSG32 uPDM_DI3Cntl_DRV                            :  2;\
            UNSG32 uPDM_DI3Cntl_PDEN                           :  1;\
            UNSG32 uPDM_DI3Cntl_PUEN                           :  1;\
            UNSG32 uPDM_DI3Cntl_SRC                            :  1;\
            UNSG32 uPDM_DI3Cntl_SMTC                           :  1;\
            UNSG32 RSVDx8A4_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PDM_DI3Cntl;
            struct w32Gbl_PDM_DI3Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO0Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO0Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO0Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO0Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO0Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO0Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO0Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO0Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO0Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO0Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO0Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO0Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO0Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO0Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO0Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO0Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO0Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO0Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO0Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO0Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO0Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO0Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO0Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO0Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO0Cntl                            {\
            UNSG32 uNAND_IO0Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO0Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO0Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO0Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO0Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO0Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8A8_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO0Cntl;
            struct w32Gbl_NAND_IO0Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO1Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO1Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO1Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO1Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO1Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO1Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO1Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO1Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO1Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO1Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO1Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO1Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO1Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO1Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO1Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO1Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO1Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO1Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO1Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO1Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO1Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO1Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO1Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO1Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO1Cntl                            {\
            UNSG32 uNAND_IO1Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO1Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO1Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO1Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO1Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO1Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8AC_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO1Cntl;
            struct w32Gbl_NAND_IO1Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO2Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO2Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO2Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO2Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO2Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO2Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO2Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO2Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO2Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO2Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO2Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO2Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO2Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO2Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO2Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO2Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO2Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO2Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO2Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO2Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO2Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO2Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO2Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO2Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO2Cntl                            {\
            UNSG32 uNAND_IO2Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO2Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO2Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO2Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO2Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO2Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8B0_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO2Cntl;
            struct w32Gbl_NAND_IO2Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO3Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO3Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO3Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO3Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO3Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO3Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO3Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO3Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO3Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO3Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO3Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO3Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO3Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO3Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO3Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO3Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO3Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO3Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO3Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO3Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO3Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO3Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO3Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO3Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO3Cntl                            {\
            UNSG32 uNAND_IO3Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO3Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO3Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO3Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO3Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO3Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8B4_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO3Cntl;
            struct w32Gbl_NAND_IO3Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO4Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO4Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO4Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO4Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO4Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO4Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO4Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO4Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO4Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO4Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO4Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO4Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO4Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO4Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO4Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO4Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO4Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO4Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO4Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO4Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO4Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO4Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO4Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO4Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO4Cntl                            {\
            UNSG32 uNAND_IO4Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO4Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO4Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO4Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO4Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO4Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8B8_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO4Cntl;
            struct w32Gbl_NAND_IO4Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO5Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO5Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO5Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO5Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO5Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO5Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO5Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO5Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO5Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO5Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO5Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO5Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO5Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO5Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO5Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO5Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO5Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO5Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO5Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO5Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO5Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO5Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO5Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO5Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO5Cntl                            {\
            UNSG32 uNAND_IO5Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO5Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO5Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO5Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO5Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO5Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8BC_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO5Cntl;
            struct w32Gbl_NAND_IO5Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO6Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO6Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO6Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO6Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO6Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO6Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO6Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO6Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO6Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO6Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO6Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO6Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO6Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO6Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO6Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO6Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO6Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO6Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO6Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO6Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO6Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO6Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO6Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO6Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO6Cntl                            {\
            UNSG32 uNAND_IO6Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO6Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO6Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO6Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO6Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO6Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8C0_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO6Cntl;
            struct w32Gbl_NAND_IO6Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_IO7Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_IO7Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_IO7Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_IO7Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_IO7Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_IO7Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_IO7Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_IO7Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_IO7Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_IO7Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_IO7Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_IO7Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_IO7Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_IO7Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_IO7Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_IO7Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_IO7Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_IO7Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_IO7Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_IO7Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_NAND_IO7Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_NAND_IO7Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_NAND_IO7Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_NAND_IO7Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_NAND_IO7Cntl                            {\
            UNSG32 uNAND_IO7Cntl_DRV                           :  2;\
            UNSG32 uNAND_IO7Cntl_PDEN                          :  1;\
            UNSG32 uNAND_IO7Cntl_PUEN                          :  1;\
            UNSG32 uNAND_IO7Cntl_RXEN                          :  1;\
            UNSG32 uNAND_IO7Cntl_SRC                           :  1;\
            UNSG32 uNAND_IO7Cntl_SMTC                          :  1;\
            UNSG32 RSVDx8C4_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_NAND_IO7Cntl;
            struct w32Gbl_NAND_IO7Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_ALECntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_ALECntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_ALECntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_ALECntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_ALECntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_ALECntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_ALECntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_ALECntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_ALECntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_ALECntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_ALECntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_ALECntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_ALECntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_ALECntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_ALECntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_ALECntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_ALECntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_ALECntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_ALECntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_ALECntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_ALECntl                            {\
            UNSG32 uNAND_ALECntl_DRV                           :  2;\
            UNSG32 uNAND_ALECntl_PDEN                          :  1;\
            UNSG32 uNAND_ALECntl_PUEN                          :  1;\
            UNSG32 uNAND_ALECntl_SRC                           :  1;\
            UNSG32 uNAND_ALECntl_SMTC                          :  1;\
            UNSG32 RSVDx8C8_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_ALECntl;
            struct w32Gbl_NAND_ALECntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_CLECntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_CLECntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_CLECntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_CLECntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_CLECntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_CLECntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_CLECntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_CLECntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_CLECntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_CLECntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_CLECntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_CLECntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_CLECntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_CLECntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_CLECntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_CLECntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_CLECntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_CLECntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_CLECntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_CLECntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_CLECntl                            {\
            UNSG32 uNAND_CLECntl_DRV                           :  2;\
            UNSG32 uNAND_CLECntl_PDEN                          :  1;\
            UNSG32 uNAND_CLECntl_PUEN                          :  1;\
            UNSG32 uNAND_CLECntl_SRC                           :  1;\
            UNSG32 uNAND_CLECntl_SMTC                          :  1;\
            UNSG32 RSVDx8CC_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_CLECntl;
            struct w32Gbl_NAND_CLECntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_WEnCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_WEnCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_WEnCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_WEnCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_WEnCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_WEnCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_WEnCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_WEnCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_WEnCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_WEnCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_WEnCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_WEnCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_WEnCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_WEnCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_WEnCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_WEnCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_WEnCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_WEnCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_WEnCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_WEnCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_WEnCntl                            {\
            UNSG32 uNAND_WEnCntl_DRV                           :  2;\
            UNSG32 uNAND_WEnCntl_PDEN                          :  1;\
            UNSG32 uNAND_WEnCntl_PUEN                          :  1;\
            UNSG32 uNAND_WEnCntl_SRC                           :  1;\
            UNSG32 uNAND_WEnCntl_SMTC                          :  1;\
            UNSG32 RSVDx8D0_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_WEnCntl;
            struct w32Gbl_NAND_WEnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_REnCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_REnCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_REnCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_REnCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_REnCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_REnCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_REnCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_REnCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_REnCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_REnCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_REnCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_REnCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_REnCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_REnCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_REnCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_REnCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_REnCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_REnCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_REnCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_REnCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_REnCntl                            {\
            UNSG32 uNAND_REnCntl_DRV                           :  2;\
            UNSG32 uNAND_REnCntl_PDEN                          :  1;\
            UNSG32 uNAND_REnCntl_PUEN                          :  1;\
            UNSG32 uNAND_REnCntl_SRC                           :  1;\
            UNSG32 uNAND_REnCntl_SMTC                          :  1;\
            UNSG32 RSVDx8D4_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_REnCntl;
            struct w32Gbl_NAND_REnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_WPnCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_WPnCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_WPnCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_WPnCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_WPnCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_WPnCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_WPnCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_WPnCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_WPnCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_WPnCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_WPnCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_WPnCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_WPnCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_WPnCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_WPnCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_WPnCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_WPnCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_WPnCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_WPnCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_WPnCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_WPnCntl                            {\
            UNSG32 uNAND_WPnCntl_DRV                           :  2;\
            UNSG32 uNAND_WPnCntl_PDEN                          :  1;\
            UNSG32 uNAND_WPnCntl_PUEN                          :  1;\
            UNSG32 uNAND_WPnCntl_SRC                           :  1;\
            UNSG32 uNAND_WPnCntl_SMTC                          :  1;\
            UNSG32 RSVDx8D8_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_WPnCntl;
            struct w32Gbl_NAND_WPnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_CEnCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_CEnCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_CEnCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_CEnCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_CEnCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_CEnCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_CEnCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_CEnCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_CEnCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_CEnCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_CEnCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_CEnCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_CEnCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_CEnCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_CEnCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_CEnCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_CEnCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_CEnCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_CEnCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_CEnCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_CEnCntl                            {\
            UNSG32 uNAND_CEnCntl_DRV                           :  2;\
            UNSG32 uNAND_CEnCntl_PDEN                          :  1;\
            UNSG32 uNAND_CEnCntl_PUEN                          :  1;\
            UNSG32 uNAND_CEnCntl_SRC                           :  1;\
            UNSG32 uNAND_CEnCntl_SMTC                          :  1;\
            UNSG32 RSVDx8DC_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_CEnCntl;
            struct w32Gbl_NAND_CEnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_NAND_RDYCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_NAND_RDYCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_NAND_RDYCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_NAND_RDYCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_NAND_RDYCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_NAND_RDYCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_NAND_RDYCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_NAND_RDYCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_NAND_RDYCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_NAND_RDYCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_NAND_RDYCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_NAND_RDYCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_NAND_RDYCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_NAND_RDYCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_NAND_RDYCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_NAND_RDYCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_NAND_RDYCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_NAND_RDYCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_NAND_RDYCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_NAND_RDYCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_NAND_RDYCntl                            {\
            UNSG32 uNAND_RDYCntl_DRV                           :  2;\
            UNSG32 uNAND_RDYCntl_PDEN                          :  1;\
            UNSG32 uNAND_RDYCntl_PUEN                          :  1;\
            UNSG32 uNAND_RDYCntl_SRC                           :  1;\
            UNSG32 uNAND_RDYCntl_SMTC                          :  1;\
            UNSG32 RSVDx8E0_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_NAND_RDYCntl;
            struct w32Gbl_NAND_RDYCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SS0nCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SS0nCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SS0nCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SS0nCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SS0nCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SS0nCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SS0nCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SS0nCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SS0nCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SS0nCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SS0nCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SS0nCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SS0nCntl_RXEN(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SS0nCntl_RXEN(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SS0nCntl_RXEN(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SS0nCntl_RXEN(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SS0nCntl_SRC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SS0nCntl_SRC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SS0nCntl_SRC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SS0nCntl_SRC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SS0nCntl_SMTC(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SS0nCntl_SMTC(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SS0nCntl_SMTC(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SS0nCntl_SMTC(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SS0nCntl                           {\
            UNSG32 uSPI1_SS0nCntl_DRV                          :  2;\
            UNSG32 uSPI1_SS0nCntl_PDEN                         :  1;\
            UNSG32 uSPI1_SS0nCntl_PUEN                         :  1;\
            UNSG32 uSPI1_SS0nCntl_RXEN                         :  1;\
            UNSG32 uSPI1_SS0nCntl_SRC                          :  1;\
            UNSG32 uSPI1_SS0nCntl_SMTC                         :  1;\
            UNSG32 RSVDx8E4_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SS0nCntl;
            struct w32Gbl_SPI1_SS0nCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SS1nCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SS1nCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SS1nCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SS1nCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SS1nCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SS1nCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SS1nCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SS1nCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SS1nCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SS1nCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SS1nCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SS1nCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SS1nCntl_RXEN(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SS1nCntl_RXEN(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SS1nCntl_RXEN(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SS1nCntl_RXEN(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SS1nCntl_SRC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SS1nCntl_SRC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SS1nCntl_SRC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SS1nCntl_SRC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SS1nCntl_SMTC(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SS1nCntl_SMTC(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SS1nCntl_SMTC(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SS1nCntl_SMTC(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SS1nCntl                           {\
            UNSG32 uSPI1_SS1nCntl_DRV                          :  2;\
            UNSG32 uSPI1_SS1nCntl_PDEN                         :  1;\
            UNSG32 uSPI1_SS1nCntl_PUEN                         :  1;\
            UNSG32 uSPI1_SS1nCntl_RXEN                         :  1;\
            UNSG32 uSPI1_SS1nCntl_SRC                          :  1;\
            UNSG32 uSPI1_SS1nCntl_SMTC                         :  1;\
            UNSG32 RSVDx8E8_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SS1nCntl;
            struct w32Gbl_SPI1_SS1nCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SS2nCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SS2nCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SS2nCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SS2nCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SS2nCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SS2nCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SS2nCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SS2nCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SS2nCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SS2nCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SS2nCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SS2nCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SS2nCntl_RXEN(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SS2nCntl_RXEN(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SS2nCntl_RXEN(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SS2nCntl_RXEN(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SS2nCntl_SRC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SS2nCntl_SRC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SS2nCntl_SRC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SS2nCntl_SRC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SS2nCntl_SMTC(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SS2nCntl_SMTC(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SS2nCntl_SMTC(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SS2nCntl_SMTC(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SS2nCntl                           {\
            UNSG32 uSPI1_SS2nCntl_DRV                          :  2;\
            UNSG32 uSPI1_SS2nCntl_PDEN                         :  1;\
            UNSG32 uSPI1_SS2nCntl_PUEN                         :  1;\
            UNSG32 uSPI1_SS2nCntl_RXEN                         :  1;\
            UNSG32 uSPI1_SS2nCntl_SRC                          :  1;\
            UNSG32 uSPI1_SS2nCntl_SMTC                         :  1;\
            UNSG32 RSVDx8EC_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SS2nCntl;
            struct w32Gbl_SPI1_SS2nCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SS3nCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SS3nCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SS3nCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SS3nCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SS3nCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SS3nCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SS3nCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SS3nCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SS3nCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SS3nCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SS3nCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SS3nCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SS3nCntl_RXEN(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SS3nCntl_RXEN(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SS3nCntl_RXEN(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SS3nCntl_RXEN(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SS3nCntl_SRC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SS3nCntl_SRC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SS3nCntl_SRC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SS3nCntl_SRC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SS3nCntl_SMTC(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SS3nCntl_SMTC(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SS3nCntl_SMTC(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SS3nCntl_SMTC(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SS3nCntl                           {\
            UNSG32 uSPI1_SS3nCntl_DRV                          :  2;\
            UNSG32 uSPI1_SS3nCntl_PDEN                         :  1;\
            UNSG32 uSPI1_SS3nCntl_PUEN                         :  1;\
            UNSG32 uSPI1_SS3nCntl_RXEN                         :  1;\
            UNSG32 uSPI1_SS3nCntl_SRC                          :  1;\
            UNSG32 uSPI1_SS3nCntl_SMTC                         :  1;\
            UNSG32 RSVDx8F0_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SS3nCntl;
            struct w32Gbl_SPI1_SS3nCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SCLKCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SCLKCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SCLKCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SCLKCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SCLKCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SCLKCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SCLKCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SCLKCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SCLKCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SCLKCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SCLKCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SCLKCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SCLKCntl_RXEN(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SCLKCntl_RXEN(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SCLKCntl_RXEN(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SCLKCntl_RXEN(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SCLKCntl_SRC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SCLKCntl_SRC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SCLKCntl_SRC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SCLKCntl_SRC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SCLKCntl_SMTC(r32)                 _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SCLKCntl_SMTC(r32,v)               _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SCLKCntl_SMTC(r16)                 _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SCLKCntl_SMTC(r16,v)               _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SCLKCntl                           {\
            UNSG32 uSPI1_SCLKCntl_DRV                          :  2;\
            UNSG32 uSPI1_SCLKCntl_PDEN                         :  1;\
            UNSG32 uSPI1_SCLKCntl_PUEN                         :  1;\
            UNSG32 uSPI1_SCLKCntl_RXEN                         :  1;\
            UNSG32 uSPI1_SCLKCntl_SRC                          :  1;\
            UNSG32 uSPI1_SCLKCntl_SMTC                         :  1;\
            UNSG32 RSVDx8F4_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SCLKCntl;
            struct w32Gbl_SPI1_SCLKCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SDOCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SDOCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SDOCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SDOCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SDOCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SDOCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SDOCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SDOCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SDOCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SDOCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SDOCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SDOCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SDOCntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SDOCntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SDOCntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SDOCntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SDOCntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SDOCntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SDOCntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SDOCntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SDOCntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SDOCntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SDOCntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SDOCntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SDOCntl                            {\
            UNSG32 uSPI1_SDOCntl_DRV                           :  2;\
            UNSG32 uSPI1_SDOCntl_PDEN                          :  1;\
            UNSG32 uSPI1_SDOCntl_PUEN                          :  1;\
            UNSG32 uSPI1_SDOCntl_RXEN                          :  1;\
            UNSG32 uSPI1_SDOCntl_SRC                           :  1;\
            UNSG32 uSPI1_SDOCntl_SMTC                          :  1;\
            UNSG32 RSVDx8F8_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SDOCntl;
            struct w32Gbl_SPI1_SDOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SPI1_SDICntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SPI1_SDICntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SPI1_SDICntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SPI1_SDICntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SPI1_SDICntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SPI1_SDICntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SPI1_SDICntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SPI1_SDICntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SPI1_SDICntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SPI1_SDICntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SPI1_SDICntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SPI1_SDICntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SPI1_SDICntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SPI1_SDICntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SPI1_SDICntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SPI1_SDICntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SPI1_SDICntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SPI1_SDICntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SPI1_SDICntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SPI1_SDICntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SPI1_SDICntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SPI1_SDICntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SPI1_SDICntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SPI1_SDICntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SPI1_SDICntl                            {\
            UNSG32 uSPI1_SDICntl_DRV                           :  2;\
            UNSG32 uSPI1_SDICntl_PDEN                          :  1;\
            UNSG32 uSPI1_SDICntl_PUEN                          :  1;\
            UNSG32 uSPI1_SDICntl_RXEN                          :  1;\
            UNSG32 uSPI1_SDICntl_SRC                           :  1;\
            UNSG32 uSPI1_SDICntl_SMTC                          :  1;\
            UNSG32 RSVDx8FC_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SPI1_SDICntl;
            struct w32Gbl_SPI1_SDICntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_USB0_DRV_VBUSCntl_DRV(r32)              _BFGET_(r32, 1, 0)
    #define   SET32Gbl_USB0_DRV_VBUSCntl_DRV(r32,v)            _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_USB0_DRV_VBUSCntl_DRV(r16)              _BFGET_(r16, 1, 0)
    #define   SET16Gbl_USB0_DRV_VBUSCntl_DRV(r16,v)            _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_USB0_DRV_VBUSCntl_PDEN(r32)             _BFGET_(r32, 2, 2)
    #define   SET32Gbl_USB0_DRV_VBUSCntl_PDEN(r32,v)           _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_USB0_DRV_VBUSCntl_PDEN(r16)             _BFGET_(r16, 2, 2)
    #define   SET16Gbl_USB0_DRV_VBUSCntl_PDEN(r16,v)           _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_USB0_DRV_VBUSCntl_PUEN(r32)             _BFGET_(r32, 3, 3)
    #define   SET32Gbl_USB0_DRV_VBUSCntl_PUEN(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_USB0_DRV_VBUSCntl_PUEN(r16)             _BFGET_(r16, 3, 3)
    #define   SET16Gbl_USB0_DRV_VBUSCntl_PUEN(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_USB0_DRV_VBUSCntl_RXEN(r32)             _BFGET_(r32, 4, 4)
    #define   SET32Gbl_USB0_DRV_VBUSCntl_RXEN(r32,v)           _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_USB0_DRV_VBUSCntl_RXEN(r16)             _BFGET_(r16, 4, 4)
    #define   SET16Gbl_USB0_DRV_VBUSCntl_RXEN(r16,v)           _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_USB0_DRV_VBUSCntl_SRC(r32)              _BFGET_(r32, 5, 5)
    #define   SET32Gbl_USB0_DRV_VBUSCntl_SRC(r32,v)            _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_USB0_DRV_VBUSCntl_SRC(r16)              _BFGET_(r16, 5, 5)
    #define   SET16Gbl_USB0_DRV_VBUSCntl_SRC(r16,v)            _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_USB0_DRV_VBUSCntl_SMTC(r32)             _BFGET_(r32, 6, 6)
    #define   SET32Gbl_USB0_DRV_VBUSCntl_SMTC(r32,v)           _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_USB0_DRV_VBUSCntl_SMTC(r16)             _BFGET_(r16, 6, 6)
    #define   SET16Gbl_USB0_DRV_VBUSCntl_SMTC(r16,v)           _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_USB0_DRV_VBUSCntl                       {\
            UNSG32 uUSB0_DRV_VBUSCntl_DRV                      :  2;\
            UNSG32 uUSB0_DRV_VBUSCntl_PDEN                     :  1;\
            UNSG32 uUSB0_DRV_VBUSCntl_PUEN                     :  1;\
            UNSG32 uUSB0_DRV_VBUSCntl_RXEN                     :  1;\
            UNSG32 uUSB0_DRV_VBUSCntl_SRC                      :  1;\
            UNSG32 uUSB0_DRV_VBUSCntl_SMTC                     :  1;\
            UNSG32 RSVDx900_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_USB0_DRV_VBUSCntl;
            struct w32Gbl_USB0_DRV_VBUSCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TW1_SCLCntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TW1_SCLCntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TW1_SCLCntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TW1_SCLCntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TW1_SCLCntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TW1_SCLCntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TW1_SCLCntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TW1_SCLCntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TW1_SCLCntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TW1_SCLCntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TW1_SCLCntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TW1_SCLCntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TW1_SCLCntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TW1_SCLCntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TW1_SCLCntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TW1_SCLCntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TW1_SCLCntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TW1_SCLCntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TW1_SCLCntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TW1_SCLCntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TW1_SCLCntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TW1_SCLCntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TW1_SCLCntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TW1_SCLCntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TW1_SCLCntl                             {\
            UNSG32 uTW1_SCLCntl_DRV                            :  2;\
            UNSG32 uTW1_SCLCntl_PDEN                           :  1;\
            UNSG32 uTW1_SCLCntl_PUEN                           :  1;\
            UNSG32 uTW1_SCLCntl_RXEN                           :  1;\
            UNSG32 uTW1_SCLCntl_SRC                            :  1;\
            UNSG32 uTW1_SCLCntl_SMTC                           :  1;\
            UNSG32 RSVDx904_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TW1_SCLCntl;
            struct w32Gbl_TW1_SCLCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TW1_SDACntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TW1_SDACntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TW1_SDACntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TW1_SDACntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TW1_SDACntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TW1_SDACntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TW1_SDACntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TW1_SDACntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TW1_SDACntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TW1_SDACntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TW1_SDACntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TW1_SDACntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TW1_SDACntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TW1_SDACntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TW1_SDACntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TW1_SDACntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TW1_SDACntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TW1_SDACntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TW1_SDACntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TW1_SDACntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TW1_SDACntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TW1_SDACntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TW1_SDACntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TW1_SDACntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TW1_SDACntl                             {\
            UNSG32 uTW1_SDACntl_DRV                            :  2;\
            UNSG32 uTW1_SDACntl_PDEN                           :  1;\
            UNSG32 uTW1_SDACntl_PUEN                           :  1;\
            UNSG32 uTW1_SDACntl_RXEN                           :  1;\
            UNSG32 uTW1_SDACntl_SRC                            :  1;\
            UNSG32 uTW1_SDACntl_SMTC                           :  1;\
            UNSG32 RSVDx908_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TW1_SDACntl;
            struct w32Gbl_TW1_SDACntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TW0_SCLCntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TW0_SCLCntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TW0_SCLCntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TW0_SCLCntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TW0_SCLCntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TW0_SCLCntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TW0_SCLCntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TW0_SCLCntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TW0_SCLCntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TW0_SCLCntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TW0_SCLCntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TW0_SCLCntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TW0_SCLCntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TW0_SCLCntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TW0_SCLCntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TW0_SCLCntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TW0_SCLCntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TW0_SCLCntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TW0_SCLCntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TW0_SCLCntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TW0_SCLCntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TW0_SCLCntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TW0_SCLCntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TW0_SCLCntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TW0_SCLCntl                             {\
            UNSG32 uTW0_SCLCntl_DRV                            :  2;\
            UNSG32 uTW0_SCLCntl_PDEN                           :  1;\
            UNSG32 uTW0_SCLCntl_PUEN                           :  1;\
            UNSG32 uTW0_SCLCntl_RXEN                           :  1;\
            UNSG32 uTW0_SCLCntl_SRC                            :  1;\
            UNSG32 uTW0_SCLCntl_SMTC                           :  1;\
            UNSG32 RSVDx90C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TW0_SCLCntl;
            struct w32Gbl_TW0_SCLCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TW0_SDACntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TW0_SDACntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TW0_SDACntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TW0_SDACntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TW0_SDACntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TW0_SDACntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TW0_SDACntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TW0_SDACntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TW0_SDACntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TW0_SDACntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TW0_SDACntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TW0_SDACntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TW0_SDACntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TW0_SDACntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TW0_SDACntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TW0_SDACntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TW0_SDACntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TW0_SDACntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TW0_SDACntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TW0_SDACntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TW0_SDACntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TW0_SDACntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TW0_SDACntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TW0_SDACntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TW0_SDACntl                             {\
            UNSG32 uTW0_SDACntl_DRV                            :  2;\
            UNSG32 uTW0_SDACntl_PDEN                           :  1;\
            UNSG32 uTW0_SDACntl_PUEN                           :  1;\
            UNSG32 uTW0_SDACntl_RXEN                           :  1;\
            UNSG32 uTW0_SDACntl_SRC                            :  1;\
            UNSG32 uTW0_SDACntl_SMTC                           :  1;\
            UNSG32 RSVDx910_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TW0_SDACntl;
            struct w32Gbl_TW0_SDACntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TMSCntl_DRV(r32)                        _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TMSCntl_DRV(r32,v)                      _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TMSCntl_DRV(r16)                        _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TMSCntl_DRV(r16,v)                      _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TMSCntl_PDEN(r32)                       _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TMSCntl_PDEN(r32,v)                     _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TMSCntl_PDEN(r16)                       _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TMSCntl_PDEN(r16,v)                     _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TMSCntl_PUEN(r32)                       _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TMSCntl_PUEN(r32,v)                     _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TMSCntl_PUEN(r16)                       _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TMSCntl_PUEN(r16,v)                     _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TMSCntl_RXEN(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TMSCntl_RXEN(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TMSCntl_RXEN(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TMSCntl_RXEN(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TMSCntl_SRC(r32)                        _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TMSCntl_SRC(r32,v)                      _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TMSCntl_SRC(r16)                        _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TMSCntl_SRC(r16,v)                      _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TMSCntl_SMTC(r32)                       _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TMSCntl_SMTC(r32,v)                     _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TMSCntl_SMTC(r16)                       _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TMSCntl_SMTC(r16,v)                     _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TMSCntl                                 {\
            UNSG32 uTMSCntl_DRV                                :  2;\
            UNSG32 uTMSCntl_PDEN                               :  1;\
            UNSG32 uTMSCntl_PUEN                               :  1;\
            UNSG32 uTMSCntl_RXEN                               :  1;\
            UNSG32 uTMSCntl_SRC                                :  1;\
            UNSG32 uTMSCntl_SMTC                               :  1;\
            UNSG32 RSVDx914_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TMSCntl;
            struct w32Gbl_TMSCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TDICntl_DRV(r32)                        _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TDICntl_DRV(r32,v)                      _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TDICntl_DRV(r16)                        _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TDICntl_DRV(r16,v)                      _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TDICntl_PDEN(r32)                       _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TDICntl_PDEN(r32,v)                     _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TDICntl_PDEN(r16)                       _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TDICntl_PDEN(r16,v)                     _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TDICntl_PUEN(r32)                       _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TDICntl_PUEN(r32,v)                     _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TDICntl_PUEN(r16)                       _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TDICntl_PUEN(r16,v)                     _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TDICntl_RXEN(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TDICntl_RXEN(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TDICntl_RXEN(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TDICntl_RXEN(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TDICntl_SRC(r32)                        _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TDICntl_SRC(r32,v)                      _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TDICntl_SRC(r16)                        _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TDICntl_SRC(r16,v)                      _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TDICntl_SMTC(r32)                       _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TDICntl_SMTC(r32,v)                     _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TDICntl_SMTC(r16)                       _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TDICntl_SMTC(r16,v)                     _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TDICntl                                 {\
            UNSG32 uTDICntl_DRV                                :  2;\
            UNSG32 uTDICntl_PDEN                               :  1;\
            UNSG32 uTDICntl_PUEN                               :  1;\
            UNSG32 uTDICntl_RXEN                               :  1;\
            UNSG32 uTDICntl_SRC                                :  1;\
            UNSG32 uTDICntl_SMTC                               :  1;\
            UNSG32 RSVDx918_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TDICntl;
            struct w32Gbl_TDICntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_TDOCntl_DRV(r32)                        _BFGET_(r32, 1, 0)
    #define   SET32Gbl_TDOCntl_DRV(r32,v)                      _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_TDOCntl_DRV(r16)                        _BFGET_(r16, 1, 0)
    #define   SET16Gbl_TDOCntl_DRV(r16,v)                      _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_TDOCntl_PDEN(r32)                       _BFGET_(r32, 2, 2)
    #define   SET32Gbl_TDOCntl_PDEN(r32,v)                     _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_TDOCntl_PDEN(r16)                       _BFGET_(r16, 2, 2)
    #define   SET16Gbl_TDOCntl_PDEN(r16,v)                     _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_TDOCntl_PUEN(r32)                       _BFGET_(r32, 3, 3)
    #define   SET32Gbl_TDOCntl_PUEN(r32,v)                     _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_TDOCntl_PUEN(r16)                       _BFGET_(r16, 3, 3)
    #define   SET16Gbl_TDOCntl_PUEN(r16,v)                     _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_TDOCntl_RXEN(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_TDOCntl_RXEN(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_TDOCntl_RXEN(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_TDOCntl_RXEN(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_TDOCntl_SRC(r32)                        _BFGET_(r32, 5, 5)
    #define   SET32Gbl_TDOCntl_SRC(r32,v)                      _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_TDOCntl_SRC(r16)                        _BFGET_(r16, 5, 5)
    #define   SET16Gbl_TDOCntl_SRC(r16,v)                      _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_TDOCntl_SMTC(r32)                       _BFGET_(r32, 6, 6)
    #define   SET32Gbl_TDOCntl_SMTC(r32,v)                     _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_TDOCntl_SMTC(r16)                       _BFGET_(r16, 6, 6)
    #define   SET16Gbl_TDOCntl_SMTC(r16,v)                     _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_TDOCntl                                 {\
            UNSG32 uTDOCntl_DRV                                :  2;\
            UNSG32 uTDOCntl_PDEN                               :  1;\
            UNSG32 uTDOCntl_PUEN                               :  1;\
            UNSG32 uTDOCntl_RXEN                               :  1;\
            UNSG32 uTDOCntl_SRC                                :  1;\
            UNSG32 uTDOCntl_SMTC                               :  1;\
            UNSG32 RSVDx91C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_TDOCntl;
            struct w32Gbl_TDOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM6Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM6Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM6Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM6Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM6Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM6Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM6Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM6Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM6Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM6Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM6Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM6Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM6Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM6Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM6Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM6Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM6Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM6Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM6Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM6Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM6Cntl                                {\
            UNSG32 uPWM6Cntl_DRV                               :  2;\
            UNSG32 uPWM6Cntl_PDEN                              :  1;\
            UNSG32 uPWM6Cntl_PUEN                              :  1;\
            UNSG32 uPWM6Cntl_SRC                               :  1;\
            UNSG32 uPWM6Cntl_SMTC                              :  1;\
            UNSG32 RSVDx920_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM6Cntl;
            struct w32Gbl_PWM6Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM7Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM7Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM7Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM7Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM7Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM7Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM7Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM7Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM7Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM7Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM7Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM7Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM7Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM7Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM7Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM7Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM7Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM7Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM7Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM7Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM7Cntl                                {\
            UNSG32 uPWM7Cntl_DRV                               :  2;\
            UNSG32 uPWM7Cntl_PDEN                              :  1;\
            UNSG32 uPWM7Cntl_PUEN                              :  1;\
            UNSG32 uPWM7Cntl_SRC                               :  1;\
            UNSG32 uPWM7Cntl_SMTC                              :  1;\
            UNSG32 RSVDx924_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM7Cntl;
            struct w32Gbl_PWM7Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM0Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM0Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM0Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM0Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM0Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM0Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM0Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM0Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM0Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM0Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM0Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM0Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM0Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM0Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM0Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM0Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM0Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM0Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM0Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM0Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM0Cntl                                {\
            UNSG32 uPWM0Cntl_DRV                               :  2;\
            UNSG32 uPWM0Cntl_PDEN                              :  1;\
            UNSG32 uPWM0Cntl_PUEN                              :  1;\
            UNSG32 uPWM0Cntl_SRC                               :  1;\
            UNSG32 uPWM0Cntl_SMTC                              :  1;\
            UNSG32 RSVDx928_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM0Cntl;
            struct w32Gbl_PWM0Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM1Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM1Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM1Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM1Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM1Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM1Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM1Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM1Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM1Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM1Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM1Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM1Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM1Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM1Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM1Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM1Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM1Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM1Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM1Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM1Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM1Cntl                                {\
            UNSG32 uPWM1Cntl_DRV                               :  2;\
            UNSG32 uPWM1Cntl_PDEN                              :  1;\
            UNSG32 uPWM1Cntl_PUEN                              :  1;\
            UNSG32 uPWM1Cntl_SRC                               :  1;\
            UNSG32 uPWM1Cntl_SMTC                              :  1;\
            UNSG32 RSVDx92C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM1Cntl;
            struct w32Gbl_PWM1Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM2Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM2Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM2Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM2Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM2Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM2Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM2Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM2Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM2Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM2Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM2Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM2Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM2Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM2Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM2Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM2Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM2Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM2Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM2Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM2Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM2Cntl                                {\
            UNSG32 uPWM2Cntl_DRV                               :  2;\
            UNSG32 uPWM2Cntl_PDEN                              :  1;\
            UNSG32 uPWM2Cntl_PUEN                              :  1;\
            UNSG32 uPWM2Cntl_SRC                               :  1;\
            UNSG32 uPWM2Cntl_SMTC                              :  1;\
            UNSG32 RSVDx930_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM2Cntl;
            struct w32Gbl_PWM2Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM3Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM3Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM3Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM3Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM3Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM3Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM3Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM3Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM3Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM3Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM3Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM3Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM3Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM3Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM3Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM3Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM3Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM3Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM3Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM3Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM3Cntl                                {\
            UNSG32 uPWM3Cntl_DRV                               :  2;\
            UNSG32 uPWM3Cntl_PDEN                              :  1;\
            UNSG32 uPWM3Cntl_PUEN                              :  1;\
            UNSG32 uPWM3Cntl_SRC                               :  1;\
            UNSG32 uPWM3Cntl_SMTC                              :  1;\
            UNSG32 RSVDx934_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM3Cntl;
            struct w32Gbl_PWM3Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM4Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM4Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM4Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM4Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM4Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM4Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM4Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM4Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM4Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM4Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM4Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM4Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM4Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM4Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM4Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM4Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM4Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM4Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM4Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM4Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM4Cntl                                {\
            UNSG32 uPWM4Cntl_DRV                               :  2;\
            UNSG32 uPWM4Cntl_PDEN                              :  1;\
            UNSG32 uPWM4Cntl_PUEN                              :  1;\
            UNSG32 uPWM4Cntl_SRC                               :  1;\
            UNSG32 uPWM4Cntl_SMTC                              :  1;\
            UNSG32 RSVDx938_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM4Cntl;
            struct w32Gbl_PWM4Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_PWM5Cntl_DRV(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32Gbl_PWM5Cntl_DRV(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_PWM5Cntl_DRV(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16Gbl_PWM5Cntl_DRV(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_PWM5Cntl_PDEN(r32)                      _BFGET_(r32, 2, 2)
    #define   SET32Gbl_PWM5Cntl_PDEN(r32,v)                    _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_PWM5Cntl_PDEN(r16)                      _BFGET_(r16, 2, 2)
    #define   SET16Gbl_PWM5Cntl_PDEN(r16,v)                    _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_PWM5Cntl_PUEN(r32)                      _BFGET_(r32, 3, 3)
    #define   SET32Gbl_PWM5Cntl_PUEN(r32,v)                    _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_PWM5Cntl_PUEN(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16Gbl_PWM5Cntl_PUEN(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_PWM5Cntl_SRC(r32)                       _BFGET_(r32, 4, 4)
    #define   SET32Gbl_PWM5Cntl_SRC(r32,v)                     _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_PWM5Cntl_SRC(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16Gbl_PWM5Cntl_SRC(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_PWM5Cntl_SMTC(r32)                      _BFGET_(r32, 5, 5)
    #define   SET32Gbl_PWM5Cntl_SMTC(r32,v)                    _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_PWM5Cntl_SMTC(r16)                      _BFGET_(r16, 5, 5)
    #define   SET16Gbl_PWM5Cntl_SMTC(r16,v)                    _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_PWM5Cntl                                {\
            UNSG32 uPWM5Cntl_DRV                               :  2;\
            UNSG32 uPWM5Cntl_PDEN                              :  1;\
            UNSG32 uPWM5Cntl_PUEN                              :  1;\
            UNSG32 uPWM5Cntl_SRC                               :  1;\
            UNSG32 uPWM5Cntl_SMTC                              :  1;\
            UNSG32 RSVDx93C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_PWM5Cntl;
            struct w32Gbl_PWM5Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_URT1_RTSnCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_URT1_RTSnCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_URT1_RTSnCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_URT1_RTSnCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_URT1_RTSnCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_URT1_RTSnCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_URT1_RTSnCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_URT1_RTSnCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_URT1_RTSnCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_URT1_RTSnCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_URT1_RTSnCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_URT1_RTSnCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_URT1_RTSnCntl_SRC(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_URT1_RTSnCntl_SRC(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_URT1_RTSnCntl_SRC(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_URT1_RTSnCntl_SRC(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_URT1_RTSnCntl_SMTC(r32)                 _BFGET_(r32, 5, 5)
    #define   SET32Gbl_URT1_RTSnCntl_SMTC(r32,v)               _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_URT1_RTSnCntl_SMTC(r16)                 _BFGET_(r16, 5, 5)
    #define   SET16Gbl_URT1_RTSnCntl_SMTC(r16,v)               _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_URT1_RTSnCntl                           {\
            UNSG32 uURT1_RTSnCntl_DRV                          :  2;\
            UNSG32 uURT1_RTSnCntl_PDEN                         :  1;\
            UNSG32 uURT1_RTSnCntl_PUEN                         :  1;\
            UNSG32 uURT1_RTSnCntl_SRC                          :  1;\
            UNSG32 uURT1_RTSnCntl_SMTC                         :  1;\
            UNSG32 RSVDx940_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_URT1_RTSnCntl;
            struct w32Gbl_URT1_RTSnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_URT1_CTSnCntl_DRV(r32)                  _BFGET_(r32, 1, 0)
    #define   SET32Gbl_URT1_CTSnCntl_DRV(r32,v)                _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_URT1_CTSnCntl_DRV(r16)                  _BFGET_(r16, 1, 0)
    #define   SET16Gbl_URT1_CTSnCntl_DRV(r16,v)                _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_URT1_CTSnCntl_PDEN(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32Gbl_URT1_CTSnCntl_PDEN(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_URT1_CTSnCntl_PDEN(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16Gbl_URT1_CTSnCntl_PDEN(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_URT1_CTSnCntl_PUEN(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32Gbl_URT1_CTSnCntl_PUEN(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_URT1_CTSnCntl_PUEN(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16Gbl_URT1_CTSnCntl_PUEN(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_URT1_CTSnCntl_SRC(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_URT1_CTSnCntl_SRC(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_URT1_CTSnCntl_SRC(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_URT1_CTSnCntl_SRC(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_URT1_CTSnCntl_SMTC(r32)                 _BFGET_(r32, 5, 5)
    #define   SET32Gbl_URT1_CTSnCntl_SMTC(r32,v)               _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_URT1_CTSnCntl_SMTC(r16)                 _BFGET_(r16, 5, 5)
    #define   SET16Gbl_URT1_CTSnCntl_SMTC(r16,v)               _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_URT1_CTSnCntl                           {\
            UNSG32 uURT1_CTSnCntl_DRV                          :  2;\
            UNSG32 uURT1_CTSnCntl_PDEN                         :  1;\
            UNSG32 uURT1_CTSnCntl_PUEN                         :  1;\
            UNSG32 uURT1_CTSnCntl_SRC                          :  1;\
            UNSG32 uURT1_CTSnCntl_SMTC                         :  1;\
            UNSG32 RSVDx944_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_URT1_CTSnCntl;
            struct w32Gbl_URT1_CTSnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_URT1_RXDCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_URT1_RXDCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_URT1_RXDCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_URT1_RXDCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_URT1_RXDCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_URT1_RXDCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_URT1_RXDCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_URT1_RXDCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_URT1_RXDCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_URT1_RXDCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_URT1_RXDCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_URT1_RXDCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_URT1_RXDCntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_URT1_RXDCntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_URT1_RXDCntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_URT1_RXDCntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_URT1_RXDCntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_URT1_RXDCntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_URT1_RXDCntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_URT1_RXDCntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_URT1_RXDCntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_URT1_RXDCntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_URT1_RXDCntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_URT1_RXDCntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_URT1_RXDCntl                            {\
            UNSG32 uURT1_RXDCntl_DRV                           :  2;\
            UNSG32 uURT1_RXDCntl_PDEN                          :  1;\
            UNSG32 uURT1_RXDCntl_PUEN                          :  1;\
            UNSG32 uURT1_RXDCntl_RXEN                          :  1;\
            UNSG32 uURT1_RXDCntl_SRC                           :  1;\
            UNSG32 uURT1_RXDCntl_SMTC                          :  1;\
            UNSG32 RSVDx948_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_URT1_RXDCntl;
            struct w32Gbl_URT1_RXDCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_URT1_TXDCntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_URT1_TXDCntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_URT1_TXDCntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_URT1_TXDCntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_URT1_TXDCntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_URT1_TXDCntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_URT1_TXDCntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_URT1_TXDCntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_URT1_TXDCntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_URT1_TXDCntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_URT1_TXDCntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_URT1_TXDCntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_URT1_TXDCntl_SRC(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_URT1_TXDCntl_SRC(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_URT1_TXDCntl_SRC(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_URT1_TXDCntl_SRC(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_URT1_TXDCntl_SMTC(r32)                  _BFGET_(r32, 5, 5)
    #define   SET32Gbl_URT1_TXDCntl_SMTC(r32,v)                _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_URT1_TXDCntl_SMTC(r16)                  _BFGET_(r16, 5, 5)
    #define   SET16Gbl_URT1_TXDCntl_SMTC(r16,v)                _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_URT1_TXDCntl                            {\
            UNSG32 uURT1_TXDCntl_DRV                           :  2;\
            UNSG32 uURT1_TXDCntl_PDEN                          :  1;\
            UNSG32 uURT1_TXDCntl_PUEN                          :  1;\
            UNSG32 uURT1_TXDCntl_SRC                           :  1;\
            UNSG32 uURT1_TXDCntl_SMTC                          :  1;\
            UNSG32 RSVDx94C_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_URT1_TXDCntl;
            struct w32Gbl_URT1_TXDCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S3_DICntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S3_DICntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S3_DICntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S3_DICntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S3_DICntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S3_DICntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S3_DICntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S3_DICntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S3_DICntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S3_DICntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S3_DICntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S3_DICntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S3_DICntl_SRC(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S3_DICntl_SRC(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S3_DICntl_SRC(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S3_DICntl_SRC(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S3_DICntl_SMTC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S3_DICntl_SMTC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S3_DICntl_SMTC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S3_DICntl_SMTC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S3_DICntl                             {\
            UNSG32 uI2S3_DICntl_DRV                            :  2;\
            UNSG32 uI2S3_DICntl_PDEN                           :  1;\
            UNSG32 uI2S3_DICntl_PUEN                           :  1;\
            UNSG32 uI2S3_DICntl_SRC                            :  1;\
            UNSG32 uI2S3_DICntl_SMTC                           :  1;\
            UNSG32 RSVDx950_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S3_DICntl;
            struct w32Gbl_I2S3_DICntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S3_DOCntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S3_DOCntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S3_DOCntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S3_DOCntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S3_DOCntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S3_DOCntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S3_DOCntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S3_DOCntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S3_DOCntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S3_DOCntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S3_DOCntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S3_DOCntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S3_DOCntl_SRC(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S3_DOCntl_SRC(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S3_DOCntl_SRC(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S3_DOCntl_SRC(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S3_DOCntl_SMTC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S3_DOCntl_SMTC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S3_DOCntl_SMTC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S3_DOCntl_SMTC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define     w32Gbl_I2S3_DOCntl                             {\
            UNSG32 uI2S3_DOCntl_DRV                            :  2;\
            UNSG32 uI2S3_DOCntl_PDEN                           :  1;\
            UNSG32 uI2S3_DOCntl_PUEN                           :  1;\
            UNSG32 uI2S3_DOCntl_SRC                            :  1;\
            UNSG32 uI2S3_DOCntl_SMTC                           :  1;\
            UNSG32 RSVDx954_b6                                 : 26;\
          }
    union { UNSG32 u32Gbl_I2S3_DOCntl;
            struct w32Gbl_I2S3_DOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S3_BCLKIOCntl_DRV(r32)                _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S3_BCLKIOCntl_DRV(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S3_BCLKIOCntl_DRV(r16)                _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S3_BCLKIOCntl_DRV(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S3_BCLKIOCntl_PDEN(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S3_BCLKIOCntl_PDEN(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S3_BCLKIOCntl_PDEN(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S3_BCLKIOCntl_PDEN(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S3_BCLKIOCntl_PUEN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S3_BCLKIOCntl_PUEN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S3_BCLKIOCntl_PUEN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S3_BCLKIOCntl_PUEN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S3_BCLKIOCntl_RXEN(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S3_BCLKIOCntl_RXEN(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S3_BCLKIOCntl_RXEN(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S3_BCLKIOCntl_RXEN(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S3_BCLKIOCntl_SRC(r32)                _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S3_BCLKIOCntl_SRC(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S3_BCLKIOCntl_SRC(r16)                _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S3_BCLKIOCntl_SRC(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S3_BCLKIOCntl_SMTC(r32)               _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S3_BCLKIOCntl_SMTC(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S3_BCLKIOCntl_SMTC(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S3_BCLKIOCntl_SMTC(r16,v)             _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S3_BCLKIOCntl                         {\
            UNSG32 uI2S3_BCLKIOCntl_DRV                        :  2;\
            UNSG32 uI2S3_BCLKIOCntl_PDEN                       :  1;\
            UNSG32 uI2S3_BCLKIOCntl_PUEN                       :  1;\
            UNSG32 uI2S3_BCLKIOCntl_RXEN                       :  1;\
            UNSG32 uI2S3_BCLKIOCntl_SRC                        :  1;\
            UNSG32 uI2S3_BCLKIOCntl_SMTC                       :  1;\
            UNSG32 RSVDx958_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S3_BCLKIOCntl;
            struct w32Gbl_I2S3_BCLKIOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_I2S3_LRCKIOCntl_DRV(r32)                _BFGET_(r32, 1, 0)
    #define   SET32Gbl_I2S3_LRCKIOCntl_DRV(r32,v)              _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_I2S3_LRCKIOCntl_DRV(r16)                _BFGET_(r16, 1, 0)
    #define   SET16Gbl_I2S3_LRCKIOCntl_DRV(r16,v)              _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_I2S3_LRCKIOCntl_PDEN(r32)               _BFGET_(r32, 2, 2)
    #define   SET32Gbl_I2S3_LRCKIOCntl_PDEN(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_I2S3_LRCKIOCntl_PDEN(r16)               _BFGET_(r16, 2, 2)
    #define   SET16Gbl_I2S3_LRCKIOCntl_PDEN(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_I2S3_LRCKIOCntl_PUEN(r32)               _BFGET_(r32, 3, 3)
    #define   SET32Gbl_I2S3_LRCKIOCntl_PUEN(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_I2S3_LRCKIOCntl_PUEN(r16)               _BFGET_(r16, 3, 3)
    #define   SET16Gbl_I2S3_LRCKIOCntl_PUEN(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_I2S3_LRCKIOCntl_RXEN(r32)               _BFGET_(r32, 4, 4)
    #define   SET32Gbl_I2S3_LRCKIOCntl_RXEN(r32,v)             _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_I2S3_LRCKIOCntl_RXEN(r16)               _BFGET_(r16, 4, 4)
    #define   SET16Gbl_I2S3_LRCKIOCntl_RXEN(r16,v)             _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_I2S3_LRCKIOCntl_SRC(r32)                _BFGET_(r32, 5, 5)
    #define   SET32Gbl_I2S3_LRCKIOCntl_SRC(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_I2S3_LRCKIOCntl_SRC(r16)                _BFGET_(r16, 5, 5)
    #define   SET16Gbl_I2S3_LRCKIOCntl_SRC(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_I2S3_LRCKIOCntl_SMTC(r32)               _BFGET_(r32, 6, 6)
    #define   SET32Gbl_I2S3_LRCKIOCntl_SMTC(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_I2S3_LRCKIOCntl_SMTC(r16)               _BFGET_(r16, 6, 6)
    #define   SET16Gbl_I2S3_LRCKIOCntl_SMTC(r16,v)             _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_I2S3_LRCKIOCntl                         {\
            UNSG32 uI2S3_LRCKIOCntl_DRV                        :  2;\
            UNSG32 uI2S3_LRCKIOCntl_PDEN                       :  1;\
            UNSG32 uI2S3_LRCKIOCntl_PUEN                       :  1;\
            UNSG32 uI2S3_LRCKIOCntl_RXEN                       :  1;\
            UNSG32 uI2S3_LRCKIOCntl_SRC                        :  1;\
            UNSG32 uI2S3_LRCKIOCntl_SMTC                       :  1;\
            UNSG32 RSVDx95C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_I2S3_LRCKIOCntl;
            struct w32Gbl_I2S3_LRCKIOCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_DAT0Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_DAT0Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_DAT0Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_DAT0Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_DAT0Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_DAT0Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_DAT0Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_DAT0Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_DAT0Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_DAT0Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_DAT0Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_DAT0Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_DAT0Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_DAT0Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_DAT0Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_DAT0Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_DAT0Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_DAT0Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_DAT0Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_DAT0Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_DAT0Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_DAT0Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_DAT0Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_DAT0Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_DAT0Cntl                            {\
            UNSG32 uSD0_DAT0Cntl_DRV                           :  2;\
            UNSG32 uSD0_DAT0Cntl_PDEN                          :  1;\
            UNSG32 uSD0_DAT0Cntl_PUEN                          :  1;\
            UNSG32 uSD0_DAT0Cntl_RXEN                          :  1;\
            UNSG32 uSD0_DAT0Cntl_SRC                           :  1;\
            UNSG32 uSD0_DAT0Cntl_SMTC                          :  1;\
            UNSG32 RSVDx960_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_DAT0Cntl;
            struct w32Gbl_SD0_DAT0Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_DAT1Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_DAT1Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_DAT1Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_DAT1Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_DAT1Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_DAT1Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_DAT1Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_DAT1Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_DAT1Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_DAT1Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_DAT1Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_DAT1Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_DAT1Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_DAT1Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_DAT1Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_DAT1Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_DAT1Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_DAT1Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_DAT1Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_DAT1Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_DAT1Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_DAT1Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_DAT1Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_DAT1Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_DAT1Cntl                            {\
            UNSG32 uSD0_DAT1Cntl_DRV                           :  2;\
            UNSG32 uSD0_DAT1Cntl_PDEN                          :  1;\
            UNSG32 uSD0_DAT1Cntl_PUEN                          :  1;\
            UNSG32 uSD0_DAT1Cntl_RXEN                          :  1;\
            UNSG32 uSD0_DAT1Cntl_SRC                           :  1;\
            UNSG32 uSD0_DAT1Cntl_SMTC                          :  1;\
            UNSG32 RSVDx964_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_DAT1Cntl;
            struct w32Gbl_SD0_DAT1Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_CLKCntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_CLKCntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_CLKCntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_CLKCntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_CLKCntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_CLKCntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_CLKCntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_CLKCntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_CLKCntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_CLKCntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_CLKCntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_CLKCntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_CLKCntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_CLKCntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_CLKCntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_CLKCntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_CLKCntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_CLKCntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_CLKCntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_CLKCntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_CLKCntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_CLKCntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_CLKCntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_CLKCntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_CLKCntl                             {\
            UNSG32 uSD0_CLKCntl_DRV                            :  2;\
            UNSG32 uSD0_CLKCntl_PDEN                           :  1;\
            UNSG32 uSD0_CLKCntl_PUEN                           :  1;\
            UNSG32 uSD0_CLKCntl_RXEN                           :  1;\
            UNSG32 uSD0_CLKCntl_SRC                            :  1;\
            UNSG32 uSD0_CLKCntl_SMTC                           :  1;\
            UNSG32 RSVDx968_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_CLKCntl;
            struct w32Gbl_SD0_CLKCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_DAT2Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_DAT2Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_DAT2Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_DAT2Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_DAT2Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_DAT2Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_DAT2Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_DAT2Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_DAT2Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_DAT2Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_DAT2Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_DAT2Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_DAT2Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_DAT2Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_DAT2Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_DAT2Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_DAT2Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_DAT2Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_DAT2Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_DAT2Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_DAT2Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_DAT2Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_DAT2Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_DAT2Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_DAT2Cntl                            {\
            UNSG32 uSD0_DAT2Cntl_DRV                           :  2;\
            UNSG32 uSD0_DAT2Cntl_PDEN                          :  1;\
            UNSG32 uSD0_DAT2Cntl_PUEN                          :  1;\
            UNSG32 uSD0_DAT2Cntl_RXEN                          :  1;\
            UNSG32 uSD0_DAT2Cntl_SRC                           :  1;\
            UNSG32 uSD0_DAT2Cntl_SMTC                          :  1;\
            UNSG32 RSVDx96C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_DAT2Cntl;
            struct w32Gbl_SD0_DAT2Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_DAT3Cntl_DRV(r32)                   _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_DAT3Cntl_DRV(r32,v)                 _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_DAT3Cntl_DRV(r16)                   _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_DAT3Cntl_DRV(r16,v)                 _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_DAT3Cntl_PDEN(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_DAT3Cntl_PDEN(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_DAT3Cntl_PDEN(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_DAT3Cntl_PDEN(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_DAT3Cntl_PUEN(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_DAT3Cntl_PUEN(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_DAT3Cntl_PUEN(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_DAT3Cntl_PUEN(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_DAT3Cntl_RXEN(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_DAT3Cntl_RXEN(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_DAT3Cntl_RXEN(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_DAT3Cntl_RXEN(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_DAT3Cntl_SRC(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_DAT3Cntl_SRC(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_DAT3Cntl_SRC(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_DAT3Cntl_SRC(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_DAT3Cntl_SMTC(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_DAT3Cntl_SMTC(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_DAT3Cntl_SMTC(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_DAT3Cntl_SMTC(r16,v)                _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_DAT3Cntl                            {\
            UNSG32 uSD0_DAT3Cntl_DRV                           :  2;\
            UNSG32 uSD0_DAT3Cntl_PDEN                          :  1;\
            UNSG32 uSD0_DAT3Cntl_PUEN                          :  1;\
            UNSG32 uSD0_DAT3Cntl_RXEN                          :  1;\
            UNSG32 uSD0_DAT3Cntl_SRC                           :  1;\
            UNSG32 uSD0_DAT3Cntl_SMTC                          :  1;\
            UNSG32 RSVDx970_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_DAT3Cntl;
            struct w32Gbl_SD0_DAT3Cntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_CMDCntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_CMDCntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_CMDCntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_CMDCntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_CMDCntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_CMDCntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_CMDCntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_CMDCntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_CMDCntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_CMDCntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_CMDCntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_CMDCntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_CMDCntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_CMDCntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_CMDCntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_CMDCntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_CMDCntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_CMDCntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_CMDCntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_CMDCntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_CMDCntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_CMDCntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_CMDCntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_CMDCntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_CMDCntl                             {\
            UNSG32 uSD0_CMDCntl_DRV                            :  2;\
            UNSG32 uSD0_CMDCntl_PDEN                           :  1;\
            UNSG32 uSD0_CMDCntl_PUEN                           :  1;\
            UNSG32 uSD0_CMDCntl_RXEN                           :  1;\
            UNSG32 uSD0_CMDCntl_SRC                            :  1;\
            UNSG32 uSD0_CMDCntl_SMTC                           :  1;\
            UNSG32 RSVDx974_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_CMDCntl;
            struct w32Gbl_SD0_CMDCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_CDnCntl_DRV(r32)                    _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_CDnCntl_DRV(r32,v)                  _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_CDnCntl_DRV(r16)                    _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_CDnCntl_DRV(r16,v)                  _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_CDnCntl_PDEN(r32)                   _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_CDnCntl_PDEN(r32,v)                 _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_CDnCntl_PDEN(r16)                   _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_CDnCntl_PDEN(r16,v)                 _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_CDnCntl_PUEN(r32)                   _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_CDnCntl_PUEN(r32,v)                 _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_CDnCntl_PUEN(r16)                   _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_CDnCntl_PUEN(r16,v)                 _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_CDnCntl_RXEN(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_CDnCntl_RXEN(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_CDnCntl_RXEN(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_CDnCntl_RXEN(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_CDnCntl_SRC(r32)                    _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_CDnCntl_SRC(r32,v)                  _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_CDnCntl_SRC(r16)                    _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_CDnCntl_SRC(r16,v)                  _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_CDnCntl_SMTC(r32)                   _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_CDnCntl_SMTC(r32,v)                 _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_CDnCntl_SMTC(r16)                   _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_CDnCntl_SMTC(r16,v)                 _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_CDnCntl                             {\
            UNSG32 uSD0_CDnCntl_DRV                            :  2;\
            UNSG32 uSD0_CDnCntl_PDEN                           :  1;\
            UNSG32 uSD0_CDnCntl_PUEN                           :  1;\
            UNSG32 uSD0_CDnCntl_RXEN                           :  1;\
            UNSG32 uSD0_CDnCntl_SRC                            :  1;\
            UNSG32 uSD0_CDnCntl_SMTC                           :  1;\
            UNSG32 RSVDx978_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_CDnCntl;
            struct w32Gbl_SD0_CDnCntl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32Gbl_SD0_WPCntl_DRV(r32)                     _BFGET_(r32, 1, 0)
    #define   SET32Gbl_SD0_WPCntl_DRV(r32,v)                   _BFSET_(r32, 1, 0,v)
    #define   GET16Gbl_SD0_WPCntl_DRV(r16)                     _BFGET_(r16, 1, 0)
    #define   SET16Gbl_SD0_WPCntl_DRV(r16,v)                   _BFSET_(r16, 1, 0,v)

    #define   GET32Gbl_SD0_WPCntl_PDEN(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32Gbl_SD0_WPCntl_PDEN(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16Gbl_SD0_WPCntl_PDEN(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16Gbl_SD0_WPCntl_PDEN(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32Gbl_SD0_WPCntl_PUEN(r32)                    _BFGET_(r32, 3, 3)
    #define   SET32Gbl_SD0_WPCntl_PUEN(r32,v)                  _BFSET_(r32, 3, 3,v)
    #define   GET16Gbl_SD0_WPCntl_PUEN(r16)                    _BFGET_(r16, 3, 3)
    #define   SET16Gbl_SD0_WPCntl_PUEN(r16,v)                  _BFSET_(r16, 3, 3,v)

    #define   GET32Gbl_SD0_WPCntl_RXEN(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32Gbl_SD0_WPCntl_RXEN(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16Gbl_SD0_WPCntl_RXEN(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16Gbl_SD0_WPCntl_RXEN(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32Gbl_SD0_WPCntl_SRC(r32)                     _BFGET_(r32, 5, 5)
    #define   SET32Gbl_SD0_WPCntl_SRC(r32,v)                   _BFSET_(r32, 5, 5,v)
    #define   GET16Gbl_SD0_WPCntl_SRC(r16)                     _BFGET_(r16, 5, 5)
    #define   SET16Gbl_SD0_WPCntl_SRC(r16,v)                   _BFSET_(r16, 5, 5,v)

    #define   GET32Gbl_SD0_WPCntl_SMTC(r32)                    _BFGET_(r32, 6, 6)
    #define   SET32Gbl_SD0_WPCntl_SMTC(r32,v)                  _BFSET_(r32, 6, 6,v)
    #define   GET16Gbl_SD0_WPCntl_SMTC(r16)                    _BFGET_(r16, 6, 6)
    #define   SET16Gbl_SD0_WPCntl_SMTC(r16,v)                  _BFSET_(r16, 6, 6,v)

    #define     w32Gbl_SD0_WPCntl                              {\
            UNSG32 uSD0_WPCntl_DRV                             :  2;\
            UNSG32 uSD0_WPCntl_PDEN                            :  1;\
            UNSG32 uSD0_WPCntl_PUEN                            :  1;\
            UNSG32 uSD0_WPCntl_RXEN                            :  1;\
            UNSG32 uSD0_WPCntl_SRC                             :  1;\
            UNSG32 uSD0_WPCntl_SMTC                            :  1;\
            UNSG32 RSVDx97C_b7                                 : 25;\
          }
    union { UNSG32 u32Gbl_SD0_WPCntl;
            struct w32Gbl_SD0_WPCntl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_Gbl;

    typedef union  T32Gbl_ProductId
          { UNSG32 u32;
            struct w32Gbl_ProductId;
                 } T32Gbl_ProductId;
    typedef union  T32Gbl_ProductId_ext
          { UNSG32 u32;
            struct w32Gbl_ProductId_ext;
                 } T32Gbl_ProductId_ext;
    typedef union  T32Gbl_INT_ID
          { UNSG32 u32;
            struct w32Gbl_INT_ID;
                 } T32Gbl_INT_ID;
    typedef union  T32Gbl_bootStrap
          { UNSG32 u32;
            struct w32Gbl_bootStrap;
                 } T32Gbl_bootStrap;
    typedef union  T32Gbl_bootStrapEn
          { UNSG32 u32;
            struct w32Gbl_bootStrapEn;
                 } T32Gbl_bootStrapEn;
    typedef union  T32Gbl_pkgSel
          { UNSG32 u32;
            struct w32Gbl_pkgSel;
                 } T32Gbl_pkgSel;
    typedef union  T32Gbl_chipCntl
          { UNSG32 u32;
            struct w32Gbl_chipCntl;
                 } T32Gbl_chipCntl;
    typedef union  T32Gbl_sw_generic0
          { UNSG32 u32;
            struct w32Gbl_sw_generic0;
                 } T32Gbl_sw_generic0;
    typedef union  T32Gbl_sw_generic1
          { UNSG32 u32;
            struct w32Gbl_sw_generic1;
                 } T32Gbl_sw_generic1;
    typedef union  T32Gbl_sw_generic2
          { UNSG32 u32;
            struct w32Gbl_sw_generic2;
                 } T32Gbl_sw_generic2;
    typedef union  T32Gbl_sw_generic3
          { UNSG32 u32;
            struct w32Gbl_sw_generic3;
                 } T32Gbl_sw_generic3;
    typedef union  T32Gbl_RWTC_top31to0
          { UNSG32 u32;
            struct w32Gbl_RWTC_top31to0;
                 } T32Gbl_RWTC_top31to0;
    typedef union  T32Gbl_RWTC_top63to32
          { UNSG32 u32;
            struct w32Gbl_RWTC_top63to32;
                 } T32Gbl_RWTC_top63to32;
    typedef union  T32Gbl_RWTC_top67to64
          { UNSG32 u32;
            struct w32Gbl_RWTC_top67to64;
                 } T32Gbl_RWTC_top67to64;
    typedef union  T32Gbl_SRAM_PWR_CTRL_USB2
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_USB2;
                 } T32Gbl_SRAM_PWR_CTRL_USB2;
    typedef union  T32Gbl_SRAM_PWR_CTRL_PCIE0
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_PCIE0;
                 } T32Gbl_SRAM_PWR_CTRL_PCIE0;
    typedef union  T32Gbl_SRAM_PWR_CTRL_PCIE1
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_PCIE1;
                 } T32Gbl_SRAM_PWR_CTRL_PCIE1;
    typedef union  T32Gbl_SRAM_PWR_CTRL_SISS
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_SISS;
                 } T32Gbl_SRAM_PWR_CTRL_SISS;
    typedef union  T32Gbl_SRAM_PWR_CTRL_NNA
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_NNA;
                 } T32Gbl_SRAM_PWR_CTRL_NNA;
    typedef union  T32Gbl_SRAM_PWR_CTRL_AIO
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_AIO;
                 } T32Gbl_SRAM_PWR_CTRL_AIO;
    typedef union  T32Gbl_SRAM_PWR_CTRL_CA53
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_CA53;
                 } T32Gbl_SRAM_PWR_CTRL_CA53;
    typedef union  T32Gbl_SRAM_PWR_CTRL_SCRATCH
          { UNSG32 u32;
            struct w32Gbl_SRAM_PWR_CTRL_SCRATCH;
                 } T32Gbl_SRAM_PWR_CTRL_SCRATCH;
    typedef union  T32Gbl_FPGAR
          { UNSG32 u32;
            struct w32Gbl_FPGAR;
                 } T32Gbl_FPGAR;
    typedef union  T32Gbl_FPGARW
          { UNSG32 u32;
            struct w32Gbl_FPGARW;
                 } T32Gbl_FPGARW;
    typedef union  T32Gbl_ResetTrigger
          { UNSG32 u32;
            struct w32Gbl_ResetTrigger;
                 } T32Gbl_ResetTrigger;
    typedef union  T32Gbl_ResetStatus
          { UNSG32 u32;
            struct w32Gbl_ResetStatus;
                 } T32Gbl_ResetStatus;
    typedef union  T32Gbl_WDTResetStatus
          { UNSG32 u32;
            struct w32Gbl_WDTResetStatus;
                 } T32Gbl_WDTResetStatus;
    typedef union  T32Gbl_WDTSysRstMask
          { UNSG32 u32;
            struct w32Gbl_WDTSysRstMask;
                 } T32Gbl_WDTSysRstMask;
    typedef union  T32Gbl_CHIP_RESET_TRACKER
          { UNSG32 u32;
            struct w32Gbl_CHIP_RESET_TRACKER;
                 } T32Gbl_CHIP_RESET_TRACKER;
    typedef union  T32Gbl_avioReset
          { UNSG32 u32;
            struct w32Gbl_avioReset;
                 } T32Gbl_avioReset;
    typedef union  T32Gbl_avioResetStatus
          { UNSG32 u32;
            struct w32Gbl_avioResetStatus;
                 } T32Gbl_avioResetStatus;
    typedef union  T32Gbl_perifReset
          { UNSG32 u32;
            struct w32Gbl_perifReset;
                 } T32Gbl_perifReset;
    typedef union  T32Gbl_perifResetStatus
          { UNSG32 u32;
            struct w32Gbl_perifResetStatus;
                 } T32Gbl_perifResetStatus;
    typedef union  T32Gbl_topStickyResetN
          { UNSG32 u32;
            struct w32Gbl_topStickyResetN;
                 } T32Gbl_topStickyResetN;
    typedef union  T32Gbl_perifStickyResetN
          { UNSG32 u32;
            struct w32Gbl_perifStickyResetN;
                 } T32Gbl_perifStickyResetN;
    typedef union  T32Gbl_apbPerifResetTrigger
          { UNSG32 u32;
            struct w32Gbl_apbPerifResetTrigger;
                 } T32Gbl_apbPerifResetTrigger;
    typedef union  T32Gbl_apbPerifResetStatus
          { UNSG32 u32;
            struct w32Gbl_apbPerifResetStatus;
                 } T32Gbl_apbPerifResetStatus;
    typedef union  T32Gbl_clkEnable
          { UNSG32 u32;
            struct w32Gbl_clkEnable;
                 } T32Gbl_clkEnable;
    typedef union  T32Gbl_ClkSwitch
          { UNSG32 u32;
            struct w32Gbl_ClkSwitch;
                 } T32Gbl_ClkSwitch;
    typedef union  T32Gbl_NandCtrl
          { UNSG32 u32;
            struct w32Gbl_NandCtrl;
                 } T32Gbl_NandCtrl;
    typedef union  T32Gbl_gic400_ctrl
          { UNSG32 u32;
            struct w32Gbl_gic400_ctrl;
                 } T32Gbl_gic400_ctrl;
    typedef union  T32Gbl_POR_1p8_3p3
          { UNSG32 u32;
            struct w32Gbl_POR_1p8_3p3;
                 } T32Gbl_POR_1p8_3p3;
    typedef union  T32Gbl_Global_PADRING
          { UNSG32 u32;
            struct w32Gbl_Global_PADRING;
                 } T32Gbl_Global_PADRING;
    typedef union  T32Gbl_SPI_PADRING
          { UNSG32 u32;
            struct w32Gbl_SPI_PADRING;
                 } T32Gbl_SPI_PADRING;
    typedef union  T32Gbl_NAND_PADRING
          { UNSG32 u32;
            struct w32Gbl_NAND_PADRING;
                 } T32Gbl_NAND_PADRING;
    typedef union  T32Gbl_SD0_PADRING
          { UNSG32 u32;
            struct w32Gbl_SD0_PADRING;
                 } T32Gbl_SD0_PADRING;
    typedef union  T32Gbl_I2S_PADRING
          { UNSG32 u32;
            struct w32Gbl_I2S_PADRING;
                 } T32Gbl_I2S_PADRING;
    typedef union  T32Gbl_I2S3_PADRING
          { UNSG32 u32;
            struct w32Gbl_I2S3_PADRING;
                 } T32Gbl_I2S3_PADRING;
    typedef union  T32Gbl_PWM_PADRING
          { UNSG32 u32;
            struct w32Gbl_PWM_PADRING;
                 } T32Gbl_PWM_PADRING;
    typedef union  T32Gbl_XTL_CTL
          { UNSG32 u32;
            struct w32Gbl_XTL_CTL;
                 } T32Gbl_XTL_CTL;
    typedef union  T32Gbl_PADRING_MODE_OUT
          { UNSG32 u32;
            struct w32Gbl_PADRING_MODE_OUT;
                 } T32Gbl_PADRING_MODE_OUT;
    typedef union  T32Gbl_pinMuxCntlBus
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus;
                 } T32Gbl_pinMuxCntlBus;
    typedef union  T32Gbl_pinMuxCntlBus1
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus1;
                 } T32Gbl_pinMuxCntlBus1;
    typedef union  T32Gbl_pinMuxCntlBus2
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus2;
                 } T32Gbl_pinMuxCntlBus2;
    typedef union  T32Gbl_pinMuxCntlBus3
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus3;
                 } T32Gbl_pinMuxCntlBus3;
    typedef union  T32Gbl_pinMuxCntlBus4
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus4;
                 } T32Gbl_pinMuxCntlBus4;
    typedef union  T32Gbl_pinMuxCntlBus5
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus5;
                 } T32Gbl_pinMuxCntlBus5;
    typedef union  T32Gbl_pinMuxCntlBus6
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus6;
                 } T32Gbl_pinMuxCntlBus6;
    typedef union  T32Gbl_pinMuxCntlBus7
          { UNSG32 u32;
            struct w32Gbl_pinMuxCntlBus7;
                 } T32Gbl_pinMuxCntlBus7;
    typedef union  T32Gbl_I2S1_BCLKIOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_BCLKIOCntl;
                 } T32Gbl_I2S1_BCLKIOCntl;
    typedef union  T32Gbl_I2S1_LRCKIOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_LRCKIOCntl;
                 } T32Gbl_I2S1_LRCKIOCntl;
    typedef union  T32Gbl_I2S1_DO0Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_DO0Cntl;
                 } T32Gbl_I2S1_DO0Cntl;
    typedef union  T32Gbl_I2S1_DO1Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_DO1Cntl;
                 } T32Gbl_I2S1_DO1Cntl;
    typedef union  T32Gbl_I2S1_DO2Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_DO2Cntl;
                 } T32Gbl_I2S1_DO2Cntl;
    typedef union  T32Gbl_I2S1_DO3Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_DO3Cntl;
                 } T32Gbl_I2S1_DO3Cntl;
    typedef union  T32Gbl_I2S1_MCLKCntl
          { UNSG32 u32;
            struct w32Gbl_I2S1_MCLKCntl;
                 } T32Gbl_I2S1_MCLKCntl;
    typedef union  T32Gbl_I2S2_BCLKIOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S2_BCLKIOCntl;
                 } T32Gbl_I2S2_BCLKIOCntl;
    typedef union  T32Gbl_I2S2_LRCKIOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S2_LRCKIOCntl;
                 } T32Gbl_I2S2_LRCKIOCntl;
    typedef union  T32Gbl_I2S2_DI0Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S2_DI0Cntl;
                 } T32Gbl_I2S2_DI0Cntl;
    typedef union  T32Gbl_I2S2_DI1Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S2_DI1Cntl;
                 } T32Gbl_I2S2_DI1Cntl;
    typedef union  T32Gbl_I2S2_DI2Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S2_DI2Cntl;
                 } T32Gbl_I2S2_DI2Cntl;
    typedef union  T32Gbl_I2S2_DI3Cntl
          { UNSG32 u32;
            struct w32Gbl_I2S2_DI3Cntl;
                 } T32Gbl_I2S2_DI3Cntl;
    typedef union  T32Gbl_PDM_CLKOCntl
          { UNSG32 u32;
            struct w32Gbl_PDM_CLKOCntl;
                 } T32Gbl_PDM_CLKOCntl;
    typedef union  T32Gbl_PDM_DI0Cntl
          { UNSG32 u32;
            struct w32Gbl_PDM_DI0Cntl;
                 } T32Gbl_PDM_DI0Cntl;
    typedef union  T32Gbl_PDM_DI1Cntl
          { UNSG32 u32;
            struct w32Gbl_PDM_DI1Cntl;
                 } T32Gbl_PDM_DI1Cntl;
    typedef union  T32Gbl_PDM_DI2Cntl
          { UNSG32 u32;
            struct w32Gbl_PDM_DI2Cntl;
                 } T32Gbl_PDM_DI2Cntl;
    typedef union  T32Gbl_PDM_DI3Cntl
          { UNSG32 u32;
            struct w32Gbl_PDM_DI3Cntl;
                 } T32Gbl_PDM_DI3Cntl;
    typedef union  T32Gbl_NAND_IO0Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO0Cntl;
                 } T32Gbl_NAND_IO0Cntl;
    typedef union  T32Gbl_NAND_IO1Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO1Cntl;
                 } T32Gbl_NAND_IO1Cntl;
    typedef union  T32Gbl_NAND_IO2Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO2Cntl;
                 } T32Gbl_NAND_IO2Cntl;
    typedef union  T32Gbl_NAND_IO3Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO3Cntl;
                 } T32Gbl_NAND_IO3Cntl;
    typedef union  T32Gbl_NAND_IO4Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO4Cntl;
                 } T32Gbl_NAND_IO4Cntl;
    typedef union  T32Gbl_NAND_IO5Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO5Cntl;
                 } T32Gbl_NAND_IO5Cntl;
    typedef union  T32Gbl_NAND_IO6Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO6Cntl;
                 } T32Gbl_NAND_IO6Cntl;
    typedef union  T32Gbl_NAND_IO7Cntl
          { UNSG32 u32;
            struct w32Gbl_NAND_IO7Cntl;
                 } T32Gbl_NAND_IO7Cntl;
    typedef union  T32Gbl_NAND_ALECntl
          { UNSG32 u32;
            struct w32Gbl_NAND_ALECntl;
                 } T32Gbl_NAND_ALECntl;
    typedef union  T32Gbl_NAND_CLECntl
          { UNSG32 u32;
            struct w32Gbl_NAND_CLECntl;
                 } T32Gbl_NAND_CLECntl;
    typedef union  T32Gbl_NAND_WEnCntl
          { UNSG32 u32;
            struct w32Gbl_NAND_WEnCntl;
                 } T32Gbl_NAND_WEnCntl;
    typedef union  T32Gbl_NAND_REnCntl
          { UNSG32 u32;
            struct w32Gbl_NAND_REnCntl;
                 } T32Gbl_NAND_REnCntl;
    typedef union  T32Gbl_NAND_WPnCntl
          { UNSG32 u32;
            struct w32Gbl_NAND_WPnCntl;
                 } T32Gbl_NAND_WPnCntl;
    typedef union  T32Gbl_NAND_CEnCntl
          { UNSG32 u32;
            struct w32Gbl_NAND_CEnCntl;
                 } T32Gbl_NAND_CEnCntl;
    typedef union  T32Gbl_NAND_RDYCntl
          { UNSG32 u32;
            struct w32Gbl_NAND_RDYCntl;
                 } T32Gbl_NAND_RDYCntl;
    typedef union  T32Gbl_SPI1_SS0nCntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SS0nCntl;
                 } T32Gbl_SPI1_SS0nCntl;
    typedef union  T32Gbl_SPI1_SS1nCntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SS1nCntl;
                 } T32Gbl_SPI1_SS1nCntl;
    typedef union  T32Gbl_SPI1_SS2nCntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SS2nCntl;
                 } T32Gbl_SPI1_SS2nCntl;
    typedef union  T32Gbl_SPI1_SS3nCntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SS3nCntl;
                 } T32Gbl_SPI1_SS3nCntl;
    typedef union  T32Gbl_SPI1_SCLKCntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SCLKCntl;
                 } T32Gbl_SPI1_SCLKCntl;
    typedef union  T32Gbl_SPI1_SDOCntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SDOCntl;
                 } T32Gbl_SPI1_SDOCntl;
    typedef union  T32Gbl_SPI1_SDICntl
          { UNSG32 u32;
            struct w32Gbl_SPI1_SDICntl;
                 } T32Gbl_SPI1_SDICntl;
    typedef union  T32Gbl_USB0_DRV_VBUSCntl
          { UNSG32 u32;
            struct w32Gbl_USB0_DRV_VBUSCntl;
                 } T32Gbl_USB0_DRV_VBUSCntl;
    typedef union  T32Gbl_TW1_SCLCntl
          { UNSG32 u32;
            struct w32Gbl_TW1_SCLCntl;
                 } T32Gbl_TW1_SCLCntl;
    typedef union  T32Gbl_TW1_SDACntl
          { UNSG32 u32;
            struct w32Gbl_TW1_SDACntl;
                 } T32Gbl_TW1_SDACntl;
    typedef union  T32Gbl_TW0_SCLCntl
          { UNSG32 u32;
            struct w32Gbl_TW0_SCLCntl;
                 } T32Gbl_TW0_SCLCntl;
    typedef union  T32Gbl_TW0_SDACntl
          { UNSG32 u32;
            struct w32Gbl_TW0_SDACntl;
                 } T32Gbl_TW0_SDACntl;
    typedef union  T32Gbl_TMSCntl
          { UNSG32 u32;
            struct w32Gbl_TMSCntl;
                 } T32Gbl_TMSCntl;
    typedef union  T32Gbl_TDICntl
          { UNSG32 u32;
            struct w32Gbl_TDICntl;
                 } T32Gbl_TDICntl;
    typedef union  T32Gbl_TDOCntl
          { UNSG32 u32;
            struct w32Gbl_TDOCntl;
                 } T32Gbl_TDOCntl;
    typedef union  T32Gbl_PWM6Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM6Cntl;
                 } T32Gbl_PWM6Cntl;
    typedef union  T32Gbl_PWM7Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM7Cntl;
                 } T32Gbl_PWM7Cntl;
    typedef union  T32Gbl_PWM0Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM0Cntl;
                 } T32Gbl_PWM0Cntl;
    typedef union  T32Gbl_PWM1Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM1Cntl;
                 } T32Gbl_PWM1Cntl;
    typedef union  T32Gbl_PWM2Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM2Cntl;
                 } T32Gbl_PWM2Cntl;
    typedef union  T32Gbl_PWM3Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM3Cntl;
                 } T32Gbl_PWM3Cntl;
    typedef union  T32Gbl_PWM4Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM4Cntl;
                 } T32Gbl_PWM4Cntl;
    typedef union  T32Gbl_PWM5Cntl
          { UNSG32 u32;
            struct w32Gbl_PWM5Cntl;
                 } T32Gbl_PWM5Cntl;
    typedef union  T32Gbl_URT1_RTSnCntl
          { UNSG32 u32;
            struct w32Gbl_URT1_RTSnCntl;
                 } T32Gbl_URT1_RTSnCntl;
    typedef union  T32Gbl_URT1_CTSnCntl
          { UNSG32 u32;
            struct w32Gbl_URT1_CTSnCntl;
                 } T32Gbl_URT1_CTSnCntl;
    typedef union  T32Gbl_URT1_RXDCntl
          { UNSG32 u32;
            struct w32Gbl_URT1_RXDCntl;
                 } T32Gbl_URT1_RXDCntl;
    typedef union  T32Gbl_URT1_TXDCntl
          { UNSG32 u32;
            struct w32Gbl_URT1_TXDCntl;
                 } T32Gbl_URT1_TXDCntl;
    typedef union  T32Gbl_I2S3_DICntl
          { UNSG32 u32;
            struct w32Gbl_I2S3_DICntl;
                 } T32Gbl_I2S3_DICntl;
    typedef union  T32Gbl_I2S3_DOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S3_DOCntl;
                 } T32Gbl_I2S3_DOCntl;
    typedef union  T32Gbl_I2S3_BCLKIOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S3_BCLKIOCntl;
                 } T32Gbl_I2S3_BCLKIOCntl;
    typedef union  T32Gbl_I2S3_LRCKIOCntl
          { UNSG32 u32;
            struct w32Gbl_I2S3_LRCKIOCntl;
                 } T32Gbl_I2S3_LRCKIOCntl;
    typedef union  T32Gbl_SD0_DAT0Cntl
          { UNSG32 u32;
            struct w32Gbl_SD0_DAT0Cntl;
                 } T32Gbl_SD0_DAT0Cntl;
    typedef union  T32Gbl_SD0_DAT1Cntl
          { UNSG32 u32;
            struct w32Gbl_SD0_DAT1Cntl;
                 } T32Gbl_SD0_DAT1Cntl;
    typedef union  T32Gbl_SD0_CLKCntl
          { UNSG32 u32;
            struct w32Gbl_SD0_CLKCntl;
                 } T32Gbl_SD0_CLKCntl;
    typedef union  T32Gbl_SD0_DAT2Cntl
          { UNSG32 u32;
            struct w32Gbl_SD0_DAT2Cntl;
                 } T32Gbl_SD0_DAT2Cntl;
    typedef union  T32Gbl_SD0_DAT3Cntl
          { UNSG32 u32;
            struct w32Gbl_SD0_DAT3Cntl;
                 } T32Gbl_SD0_DAT3Cntl;
    typedef union  T32Gbl_SD0_CMDCntl
          { UNSG32 u32;
            struct w32Gbl_SD0_CMDCntl;
                 } T32Gbl_SD0_CMDCntl;
    typedef union  T32Gbl_SD0_CDnCntl
          { UNSG32 u32;
            struct w32Gbl_SD0_CDnCntl;
                 } T32Gbl_SD0_CDnCntl;
    typedef union  T32Gbl_SD0_WPCntl
          { UNSG32 u32;
            struct w32Gbl_SD0_WPCntl;
                 } T32Gbl_SD0_WPCntl;
    ///////////////////////////////////////////////////////////

    typedef union  TGbl_ProductId
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_ProductId;
                   };
                 } TGbl_ProductId;
    typedef union  TGbl_ProductId_ext
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_ProductId_ext;
                   };
                 } TGbl_ProductId_ext;
    typedef union  TGbl_INT_ID
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_INT_ID;
                   };
                 } TGbl_INT_ID;
    typedef union  TGbl_bootStrap
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_bootStrap;
                   };
                 } TGbl_bootStrap;
    typedef union  TGbl_bootStrapEn
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_bootStrapEn;
                   };
                 } TGbl_bootStrapEn;
    typedef union  TGbl_pkgSel
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_pkgSel;
                   };
                 } TGbl_pkgSel;
    typedef union  TGbl_chipCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_chipCntl;
                   };
                 } TGbl_chipCntl;
    typedef union  TGbl_sw_generic0
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_sw_generic0;
                   };
                 } TGbl_sw_generic0;
    typedef union  TGbl_sw_generic1
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_sw_generic1;
                   };
                 } TGbl_sw_generic1;
    typedef union  TGbl_sw_generic2
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_sw_generic2;
                   };
                 } TGbl_sw_generic2;
    typedef union  TGbl_sw_generic3
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_sw_generic3;
                   };
                 } TGbl_sw_generic3;
    typedef union  TGbl_RWTC_top31to0
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_RWTC_top31to0;
                   };
                 } TGbl_RWTC_top31to0;
    typedef union  TGbl_RWTC_top63to32
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_RWTC_top63to32;
                   };
                 } TGbl_RWTC_top63to32;
    typedef union  TGbl_RWTC_top67to64
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_RWTC_top67to64;
                   };
                 } TGbl_RWTC_top67to64;
    typedef union  TGbl_SRAM_PWR_CTRL_USB2
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_USB2;
                   };
                 } TGbl_SRAM_PWR_CTRL_USB2;
    typedef union  TGbl_SRAM_PWR_CTRL_PCIE0
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_PCIE0;
                   };
                 } TGbl_SRAM_PWR_CTRL_PCIE0;
    typedef union  TGbl_SRAM_PWR_CTRL_PCIE1
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_PCIE1;
                   };
                 } TGbl_SRAM_PWR_CTRL_PCIE1;
    typedef union  TGbl_SRAM_PWR_CTRL_SISS
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_SISS;
                   };
                 } TGbl_SRAM_PWR_CTRL_SISS;
    typedef union  TGbl_SRAM_PWR_CTRL_NNA
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_NNA;
                   };
                 } TGbl_SRAM_PWR_CTRL_NNA;
    typedef union  TGbl_SRAM_PWR_CTRL_AIO
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_AIO;
                   };
                 } TGbl_SRAM_PWR_CTRL_AIO;
    typedef union  TGbl_SRAM_PWR_CTRL_CA53
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_CA53;
                   };
                 } TGbl_SRAM_PWR_CTRL_CA53;
    typedef union  TGbl_SRAM_PWR_CTRL_SCRATCH
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SRAM_PWR_CTRL_SCRATCH;
                   };
                 } TGbl_SRAM_PWR_CTRL_SCRATCH;
    typedef union  TGbl_FPGAR
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_FPGAR;
                   };
                 } TGbl_FPGAR;
    typedef union  TGbl_FPGARW
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_FPGARW;
                   };
                 } TGbl_FPGARW;
    typedef union  TGbl_ResetTrigger
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_ResetTrigger;
                   };
                 } TGbl_ResetTrigger;
    typedef union  TGbl_ResetStatus
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_ResetStatus;
                   };
                 } TGbl_ResetStatus;
    typedef union  TGbl_WDTResetStatus
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_WDTResetStatus;
                   };
                 } TGbl_WDTResetStatus;
    typedef union  TGbl_WDTSysRstMask
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_WDTSysRstMask;
                   };
                 } TGbl_WDTSysRstMask;
    typedef union  TGbl_CHIP_RESET_TRACKER
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_CHIP_RESET_TRACKER;
                   };
                 } TGbl_CHIP_RESET_TRACKER;
    typedef union  TGbl_avioReset
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_avioReset;
                   };
                 } TGbl_avioReset;
    typedef union  TGbl_avioResetStatus
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_avioResetStatus;
                   };
                 } TGbl_avioResetStatus;
    typedef union  TGbl_perifReset
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_perifReset;
                   };
                 } TGbl_perifReset;
    typedef union  TGbl_perifResetStatus
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_perifResetStatus;
                   };
                 } TGbl_perifResetStatus;
    typedef union  TGbl_topStickyResetN
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_topStickyResetN;
                   };
                 } TGbl_topStickyResetN;
    typedef union  TGbl_perifStickyResetN
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_perifStickyResetN;
                   };
                 } TGbl_perifStickyResetN;
    typedef union  TGbl_apbPerifResetTrigger
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_apbPerifResetTrigger;
                   };
                 } TGbl_apbPerifResetTrigger;
    typedef union  TGbl_apbPerifResetStatus
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_apbPerifResetStatus;
                   };
                 } TGbl_apbPerifResetStatus;
    typedef union  TGbl_clkEnable
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_clkEnable;
                   };
                 } TGbl_clkEnable;
    typedef union  TGbl_ClkSwitch
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_ClkSwitch;
                   };
                 } TGbl_ClkSwitch;
    typedef union  TGbl_NandCtrl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NandCtrl;
                   };
                 } TGbl_NandCtrl;
    typedef union  TGbl_gic400_ctrl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_gic400_ctrl;
                   };
                 } TGbl_gic400_ctrl;
    typedef union  TGbl_POR_1p8_3p3
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_POR_1p8_3p3;
                   };
                 } TGbl_POR_1p8_3p3;
    typedef union  TGbl_Global_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_Global_PADRING;
                   };
                 } TGbl_Global_PADRING;
    typedef union  TGbl_SPI_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI_PADRING;
                   };
                 } TGbl_SPI_PADRING;
    typedef union  TGbl_NAND_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_PADRING;
                   };
                 } TGbl_NAND_PADRING;
    typedef union  TGbl_SD0_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_PADRING;
                   };
                 } TGbl_SD0_PADRING;
    typedef union  TGbl_I2S_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S_PADRING;
                   };
                 } TGbl_I2S_PADRING;
    typedef union  TGbl_I2S3_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S3_PADRING;
                   };
                 } TGbl_I2S3_PADRING;
    typedef union  TGbl_PWM_PADRING
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM_PADRING;
                   };
                 } TGbl_PWM_PADRING;
    typedef union  TGbl_XTL_CTL
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_XTL_CTL;
                   };
                 } TGbl_XTL_CTL;
    typedef union  TGbl_PADRING_MODE_OUT
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PADRING_MODE_OUT;
                   };
                 } TGbl_PADRING_MODE_OUT;
    typedef union  TGbl_pinMuxCntlBus
          { UNSG32 u32[8];
            struct {
            struct w32Gbl_pinMuxCntlBus;
            struct w32Gbl_pinMuxCntlBus1;
            struct w32Gbl_pinMuxCntlBus2;
            struct w32Gbl_pinMuxCntlBus3;
            struct w32Gbl_pinMuxCntlBus4;
            struct w32Gbl_pinMuxCntlBus5;
            struct w32Gbl_pinMuxCntlBus6;
            struct w32Gbl_pinMuxCntlBus7;
                   };
                 } TGbl_pinMuxCntlBus;
    typedef union  TGbl_I2S1_BCLKIOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_BCLKIOCntl;
                   };
                 } TGbl_I2S1_BCLKIOCntl;
    typedef union  TGbl_I2S1_LRCKIOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_LRCKIOCntl;
                   };
                 } TGbl_I2S1_LRCKIOCntl;
    typedef union  TGbl_I2S1_DO0Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_DO0Cntl;
                   };
                 } TGbl_I2S1_DO0Cntl;
    typedef union  TGbl_I2S1_DO1Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_DO1Cntl;
                   };
                 } TGbl_I2S1_DO1Cntl;
    typedef union  TGbl_I2S1_DO2Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_DO2Cntl;
                   };
                 } TGbl_I2S1_DO2Cntl;
    typedef union  TGbl_I2S1_DO3Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_DO3Cntl;
                   };
                 } TGbl_I2S1_DO3Cntl;
    typedef union  TGbl_I2S1_MCLKCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S1_MCLKCntl;
                   };
                 } TGbl_I2S1_MCLKCntl;
    typedef union  TGbl_I2S2_BCLKIOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S2_BCLKIOCntl;
                   };
                 } TGbl_I2S2_BCLKIOCntl;
    typedef union  TGbl_I2S2_LRCKIOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S2_LRCKIOCntl;
                   };
                 } TGbl_I2S2_LRCKIOCntl;
    typedef union  TGbl_I2S2_DI0Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S2_DI0Cntl;
                   };
                 } TGbl_I2S2_DI0Cntl;
    typedef union  TGbl_I2S2_DI1Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S2_DI1Cntl;
                   };
                 } TGbl_I2S2_DI1Cntl;
    typedef union  TGbl_I2S2_DI2Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S2_DI2Cntl;
                   };
                 } TGbl_I2S2_DI2Cntl;
    typedef union  TGbl_I2S2_DI3Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S2_DI3Cntl;
                   };
                 } TGbl_I2S2_DI3Cntl;
    typedef union  TGbl_PDM_CLKOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PDM_CLKOCntl;
                   };
                 } TGbl_PDM_CLKOCntl;
    typedef union  TGbl_PDM_DI0Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PDM_DI0Cntl;
                   };
                 } TGbl_PDM_DI0Cntl;
    typedef union  TGbl_PDM_DI1Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PDM_DI1Cntl;
                   };
                 } TGbl_PDM_DI1Cntl;
    typedef union  TGbl_PDM_DI2Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PDM_DI2Cntl;
                   };
                 } TGbl_PDM_DI2Cntl;
    typedef union  TGbl_PDM_DI3Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PDM_DI3Cntl;
                   };
                 } TGbl_PDM_DI3Cntl;
    typedef union  TGbl_NAND_IO0Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO0Cntl;
                   };
                 } TGbl_NAND_IO0Cntl;
    typedef union  TGbl_NAND_IO1Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO1Cntl;
                   };
                 } TGbl_NAND_IO1Cntl;
    typedef union  TGbl_NAND_IO2Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO2Cntl;
                   };
                 } TGbl_NAND_IO2Cntl;
    typedef union  TGbl_NAND_IO3Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO3Cntl;
                   };
                 } TGbl_NAND_IO3Cntl;
    typedef union  TGbl_NAND_IO4Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO4Cntl;
                   };
                 } TGbl_NAND_IO4Cntl;
    typedef union  TGbl_NAND_IO5Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO5Cntl;
                   };
                 } TGbl_NAND_IO5Cntl;
    typedef union  TGbl_NAND_IO6Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO6Cntl;
                   };
                 } TGbl_NAND_IO6Cntl;
    typedef union  TGbl_NAND_IO7Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_IO7Cntl;
                   };
                 } TGbl_NAND_IO7Cntl;
    typedef union  TGbl_NAND_ALECntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_ALECntl;
                   };
                 } TGbl_NAND_ALECntl;
    typedef union  TGbl_NAND_CLECntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_CLECntl;
                   };
                 } TGbl_NAND_CLECntl;
    typedef union  TGbl_NAND_WEnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_WEnCntl;
                   };
                 } TGbl_NAND_WEnCntl;
    typedef union  TGbl_NAND_REnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_REnCntl;
                   };
                 } TGbl_NAND_REnCntl;
    typedef union  TGbl_NAND_WPnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_WPnCntl;
                   };
                 } TGbl_NAND_WPnCntl;
    typedef union  TGbl_NAND_CEnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_CEnCntl;
                   };
                 } TGbl_NAND_CEnCntl;
    typedef union  TGbl_NAND_RDYCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_NAND_RDYCntl;
                   };
                 } TGbl_NAND_RDYCntl;
    typedef union  TGbl_SPI1_SS0nCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SS0nCntl;
                   };
                 } TGbl_SPI1_SS0nCntl;
    typedef union  TGbl_SPI1_SS1nCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SS1nCntl;
                   };
                 } TGbl_SPI1_SS1nCntl;
    typedef union  TGbl_SPI1_SS2nCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SS2nCntl;
                   };
                 } TGbl_SPI1_SS2nCntl;
    typedef union  TGbl_SPI1_SS3nCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SS3nCntl;
                   };
                 } TGbl_SPI1_SS3nCntl;
    typedef union  TGbl_SPI1_SCLKCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SCLKCntl;
                   };
                 } TGbl_SPI1_SCLKCntl;
    typedef union  TGbl_SPI1_SDOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SDOCntl;
                   };
                 } TGbl_SPI1_SDOCntl;
    typedef union  TGbl_SPI1_SDICntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SPI1_SDICntl;
                   };
                 } TGbl_SPI1_SDICntl;
    typedef union  TGbl_USB0_DRV_VBUSCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_USB0_DRV_VBUSCntl;
                   };
                 } TGbl_USB0_DRV_VBUSCntl;
    typedef union  TGbl_TW1_SCLCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TW1_SCLCntl;
                   };
                 } TGbl_TW1_SCLCntl;
    typedef union  TGbl_TW1_SDACntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TW1_SDACntl;
                   };
                 } TGbl_TW1_SDACntl;
    typedef union  TGbl_TW0_SCLCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TW0_SCLCntl;
                   };
                 } TGbl_TW0_SCLCntl;
    typedef union  TGbl_TW0_SDACntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TW0_SDACntl;
                   };
                 } TGbl_TW0_SDACntl;
    typedef union  TGbl_TMSCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TMSCntl;
                   };
                 } TGbl_TMSCntl;
    typedef union  TGbl_TDICntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TDICntl;
                   };
                 } TGbl_TDICntl;
    typedef union  TGbl_TDOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_TDOCntl;
                   };
                 } TGbl_TDOCntl;
    typedef union  TGbl_PWM6Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM6Cntl;
                   };
                 } TGbl_PWM6Cntl;
    typedef union  TGbl_PWM7Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM7Cntl;
                   };
                 } TGbl_PWM7Cntl;
    typedef union  TGbl_PWM0Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM0Cntl;
                   };
                 } TGbl_PWM0Cntl;
    typedef union  TGbl_PWM1Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM1Cntl;
                   };
                 } TGbl_PWM1Cntl;
    typedef union  TGbl_PWM2Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM2Cntl;
                   };
                 } TGbl_PWM2Cntl;
    typedef union  TGbl_PWM3Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM3Cntl;
                   };
                 } TGbl_PWM3Cntl;
    typedef union  TGbl_PWM4Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM4Cntl;
                   };
                 } TGbl_PWM4Cntl;
    typedef union  TGbl_PWM5Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_PWM5Cntl;
                   };
                 } TGbl_PWM5Cntl;
    typedef union  TGbl_URT1_RTSnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_URT1_RTSnCntl;
                   };
                 } TGbl_URT1_RTSnCntl;
    typedef union  TGbl_URT1_CTSnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_URT1_CTSnCntl;
                   };
                 } TGbl_URT1_CTSnCntl;
    typedef union  TGbl_URT1_RXDCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_URT1_RXDCntl;
                   };
                 } TGbl_URT1_RXDCntl;
    typedef union  TGbl_URT1_TXDCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_URT1_TXDCntl;
                   };
                 } TGbl_URT1_TXDCntl;
    typedef union  TGbl_I2S3_DICntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S3_DICntl;
                   };
                 } TGbl_I2S3_DICntl;
    typedef union  TGbl_I2S3_DOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S3_DOCntl;
                   };
                 } TGbl_I2S3_DOCntl;
    typedef union  TGbl_I2S3_BCLKIOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S3_BCLKIOCntl;
                   };
                 } TGbl_I2S3_BCLKIOCntl;
    typedef union  TGbl_I2S3_LRCKIOCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_I2S3_LRCKIOCntl;
                   };
                 } TGbl_I2S3_LRCKIOCntl;
    typedef union  TGbl_SD0_DAT0Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_DAT0Cntl;
                   };
                 } TGbl_SD0_DAT0Cntl;
    typedef union  TGbl_SD0_DAT1Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_DAT1Cntl;
                   };
                 } TGbl_SD0_DAT1Cntl;
    typedef union  TGbl_SD0_CLKCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_CLKCntl;
                   };
                 } TGbl_SD0_CLKCntl;
    typedef union  TGbl_SD0_DAT2Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_DAT2Cntl;
                   };
                 } TGbl_SD0_DAT2Cntl;
    typedef union  TGbl_SD0_DAT3Cntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_DAT3Cntl;
                   };
                 } TGbl_SD0_DAT3Cntl;
    typedef union  TGbl_SD0_CMDCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_CMDCntl;
                   };
                 } TGbl_SD0_CMDCntl;
    typedef union  TGbl_SD0_CDnCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_CDnCntl;
                   };
                 } TGbl_SD0_CDnCntl;
    typedef union  TGbl_SD0_WPCntl
          { UNSG32 u32[1];
            struct {
            struct w32Gbl_SD0_WPCntl;
                   };
                 } TGbl_SD0_WPCntl;

    ///////////////////////////////////////////////////////////
     SIGN32 Gbl_drvrd(SIE_Gbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 Gbl_drvwr(SIE_Gbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void Gbl_reset(SIE_Gbl *p);
     SIGN32 Gbl_cmp  (SIE_Gbl *p, SIE_Gbl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define Gbl_check(p,pie,pfx,hLOG) Gbl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define Gbl_print(p,    pfx,hLOG) Gbl_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: Gbl
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: global.h
////////////////////////////////////////////////////////////