//////
/// don't edit! auto-generated by docc: soc.h
////////////////////////////////////////////////////////////
#ifndef soc_h
#define soc_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE IRQ                                      (4,4)
///     # # ----------------------------------------------------------
///               : cpu_wrap_U0__CTIIRQ0 0x0
///               : cpu_wrap_U0__CTIIRQ1 0x1
///               : cpu_wrap_U0__CTIIRQ2 0x2
///               : cpu_wrap_U0__CTIIRQ3 0x3
///               : cpu_wrap_U0__nPMUIRQ0 0x4
///               : cpu_wrap_U0__nPMUIRQ1 0x5
///               : cpu_wrap_U0__nPMUIRQ2 0x6
///               : cpu_wrap_U0__nPMUIRQ3 0x7
///               : u_AhbTrc__IntOut   0x8
///               : mc6_U0__MC6AxiErrMonIntr 0x9
///               : cpu_wrap_U0__nEXTERRIRQ 0xA
///               : AIO_top_U0__dHubIntrAvio0 0xB
///               : AIO_top_U0__dHubIntrAvio1 0xC
///               : AIO_top_U0__dHubIntrAvio2 0xD
///               : tsSS_BiuCfg_U0__tsSSIntr 0xE
///               : bcm_top_U0__bcm_hst_int_out 0xF
///               : CA_wrapper_U0__nocs3Intr 0x10
///               : tsSS__wdtIntr      0x11
///               : KilopassOTP_wrapper_U0__KilopassIntr 0x12
///               : u_DWC_otg__interrupt 0x13
///               : cdns_hpnfc_U0__interrupt 0x14
///               : u_emmcCore__intr   0x15
///               : u_sdioCore__intr   0x16
///               : pBridge0__intrPb0  0x17
///               : pBridge0__intrPb1  0x18
///               : pBridge0__intrPb2  0x19
///               : u_DWC_pcie_rc__cfg_aer_rc_err_int 0x1A
///               : u_DWC_pcie_rc__cfg_pme_int 0x1B
///               : u_DWC_pcie_rc__msi_ctrl_int 0x1C
///               : pcie_top_U0__pcie_l2_exit_intr 0x1D
///               : u_DWC_pcie_rc__hp_int 0x1E
///               : pcie_top_U0__pexMacIntr 0x1F
///               : pcie_top_U0__pcie_smlhreq_rst_intr 0x20
///               : u_DWC_pcie1_rc__cfg_aer_rc_err_int 0x21
///               : u_DWC_pcie1_rc__cfg_pme_int 0x22
///               : u_DWC_pcie1_rc__msi_ctrl_int 0x23
///               : pcie_top_U1__pcie_l2_exit_intr 0x24
///               : u_DWC_pcie1_rc__hp_int 0x25
///               : pcie_top_U1__pexMacIntr 0x26
///               : pcie_top_U1__pcie_smlhreq_rst_intr 0x27
///               : u_apbPerif__ex_i_gpio_0_Intr_irq 0x28
///               : u_apbPerif__ex_i_gpio_1_Intr_irq 0x29
///               : u_apbPerif__ex_i_i2c_0_Intr_irq 0x2A
///               : u_apbPerif__ex_i_i2c_1_Intr_irq 0x2B
///               : u_apbPerif__ex_i_ssi_Intr_irq 0x2C
///               : u_apbPerif__ex_i_wdt_0_Intr_irq 0x2D
///               : u_apbPerif__ex_i_wdt_1_Intr_irq 0x2E
///               : u_apbPerif__ex_i_wdt_2_Intr_irq 0x2F
///               : u_apbPerif__ex_i_apbPerif_timers_0_Intr0_irq 0x30
///               : u_apbPerif__ex_i_apbPerif_timers_0_Intr1_irq 0x31
///               : u_apbPerif__ex_i_apbPerif_timers_0_Intr2_irq 0x32
///               : u_apbPerif__ex_i_apbPerif_timers_0_Intr3_irq 0x33
///               : u_apbPerif__ex_i_apbPerif_timers_1_Intr0_irq 0x34
///               : u_apbPerif__ex_i_apbPerif_timers_1_Intr1_irq 0x35
///               : u_apbPerif__ex_i_apbPerif_timers_1_Intr2_irq 0x36
///               : u_apbPerif__ex_i_apbPerif_timers_1_Intr3_irq 0x37
///               : u_apbPerif__ex_i_apbPerif_uart_0_Intr_irq 0x38
///               : u_apbPerif__ex_i_apbPerif_uart_1_Intr_irq 0x39
///               : soc_U0__dummySwIntr0 0x3A
///               : soc_U0__dummySwIntr1 0x3B
///               : soc_U0__dummySwIntr2 0x3C
///               : soc_U0__dummySwIntr3 0x3D
///               : soc_U0__dummySwIntr4 0x3E
///               : soc_U0__dummySwIntr5 0x3F
///               : soc_U0__dummySwIntr6 0x40
///               : soc_U0__dummySwIntr7 0x41
///               : VIVANTE_GPU_U0__xaq2_intr 0x42
///               : u_saradc_wrap__intr 0x43
///               : ABBGEN_U0__o_intr  0x44
///               : TOTAL_IRQ          0x45
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       0B, bits:       0b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_IRQ
#define h_IRQ (){}

    #define        IRQ_cpu_wrap_U0__CTIIRQ0                    0x0
    #define        IRQ_cpu_wrap_U0__CTIIRQ1                    0x1
    #define        IRQ_cpu_wrap_U0__CTIIRQ2                    0x2
    #define        IRQ_cpu_wrap_U0__CTIIRQ3                    0x3
    #define        IRQ_cpu_wrap_U0__nPMUIRQ0                   0x4
    #define        IRQ_cpu_wrap_U0__nPMUIRQ1                   0x5
    #define        IRQ_cpu_wrap_U0__nPMUIRQ2                   0x6
    #define        IRQ_cpu_wrap_U0__nPMUIRQ3                   0x7
    #define        IRQ_u_AhbTrc__IntOut                        0x8
    #define        IRQ_mc6_U0__MC6AxiErrMonIntr                0x9
    #define        IRQ_cpu_wrap_U0__nEXTERRIRQ                 0xA
    #define        IRQ_AIO_top_U0__dHubIntrAvio0               0xB
    #define        IRQ_AIO_top_U0__dHubIntrAvio1               0xC
    #define        IRQ_AIO_top_U0__dHubIntrAvio2               0xD
    #define        IRQ_tsSS_BiuCfg_U0__tsSSIntr                0xE
    #define        IRQ_bcm_top_U0__bcm_hst_int_out             0xF
    #define        IRQ_CA_wrapper_U0__nocs3Intr                0x10
    #define        IRQ_tsSS__wdtIntr                           0x11
    #define        IRQ_KilopassOTP_wrapper_U0__KilopassIntr    0x12
    #define        IRQ_u_DWC_otg__interrupt                    0x13
    #define        IRQ_cdns_hpnfc_U0__interrupt                0x14
    #define        IRQ_u_emmcCore__intr                        0x15
    #define        IRQ_u_sdioCore__intr                        0x16
    #define        IRQ_pBridge0__intrPb0                       0x17
    #define        IRQ_pBridge0__intrPb1                       0x18
    #define        IRQ_pBridge0__intrPb2                       0x19
    #define        IRQ_u_DWC_pcie_rc__cfg_aer_rc_err_int       0x1A
    #define        IRQ_u_DWC_pcie_rc__cfg_pme_int              0x1B
    #define        IRQ_u_DWC_pcie_rc__msi_ctrl_int             0x1C
    #define        IRQ_pcie_top_U0__pcie_l2_exit_intr          0x1D
    #define        IRQ_u_DWC_pcie_rc__hp_int                   0x1E
    #define        IRQ_pcie_top_U0__pexMacIntr                 0x1F
    #define        IRQ_pcie_top_U0__pcie_smlhreq_rst_intr      0x20
    #define        IRQ_u_DWC_pcie1_rc__cfg_aer_rc_err_int      0x21
    #define        IRQ_u_DWC_pcie1_rc__cfg_pme_int             0x22
    #define        IRQ_u_DWC_pcie1_rc__msi_ctrl_int            0x23
    #define        IRQ_pcie_top_U1__pcie_l2_exit_intr          0x24
    #define        IRQ_u_DWC_pcie1_rc__hp_int                  0x25
    #define        IRQ_pcie_top_U1__pexMacIntr                 0x26
    #define        IRQ_pcie_top_U1__pcie_smlhreq_rst_intr      0x27
    #define        IRQ_u_apbPerif__ex_i_gpio_0_Intr_irq        0x28
    #define        IRQ_u_apbPerif__ex_i_gpio_1_Intr_irq        0x29
    #define        IRQ_u_apbPerif__ex_i_i2c_0_Intr_irq         0x2A
    #define        IRQ_u_apbPerif__ex_i_i2c_1_Intr_irq         0x2B
    #define        IRQ_u_apbPerif__ex_i_ssi_Intr_irq           0x2C
    #define        IRQ_u_apbPerif__ex_i_wdt_0_Intr_irq         0x2D
    #define        IRQ_u_apbPerif__ex_i_wdt_1_Intr_irq         0x2E
    #define        IRQ_u_apbPerif__ex_i_wdt_2_Intr_irq         0x2F
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr0_irq 0x30
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr1_irq 0x31
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr2_irq 0x32
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_0_Intr3_irq 0x33
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr0_irq 0x34
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr1_irq 0x35
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr2_irq 0x36
    #define        IRQ_u_apbPerif__ex_i_apbPerif_timers_1_Intr3_irq 0x37
    #define        IRQ_u_apbPerif__ex_i_apbPerif_uart_0_Intr_irq 0x38
    #define        IRQ_u_apbPerif__ex_i_apbPerif_uart_1_Intr_irq 0x39
    #define        IRQ_soc_U0__dummySwIntr0                    0x3A
    #define        IRQ_soc_U0__dummySwIntr1                    0x3B
    #define        IRQ_soc_U0__dummySwIntr2                    0x3C
    #define        IRQ_soc_U0__dummySwIntr3                    0x3D
    #define        IRQ_soc_U0__dummySwIntr4                    0x3E
    #define        IRQ_soc_U0__dummySwIntr5                    0x3F
    #define        IRQ_soc_U0__dummySwIntr6                    0x40
    #define        IRQ_soc_U0__dummySwIntr7                    0x41
    #define        IRQ_VIVANTE_GPU_U0__xaq2_intr               0x42
    #define        IRQ_u_saradc_wrap__intr                     0x43
    #define        IRQ_ABBGEN_U0__o_intr                       0x44
    #define        IRQ_TOTAL_IRQ                               0x45
    ///////////////////////////////////////////////////////////

#endif
//////
/// ENDOFINTERFACE: IRQ
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE pll                                      (4,4)
///     ###
///     * SSPLL is a differential, wide range, and low power spread-spectrum PLL that is also capable of
///     * adding in a fixed frequency offset in about 1 ppm/step resolution.
///     * .. Input Frequency: Fref: 8 MHz ~ 2 GHz
///     * Output Frequency: Fout: 9 MHz ~ 3GHz for differential outputs CLKOUTP and CLKOUTN;
///     * 9 MHz ~ 2.1 GHz for single -ended output CLKOUT.
///     * .. Fout(CLKOUT) = Fref *(4*N/M) / CLKOUT_SE_DIV_SEL
///     * Fout(CLKOUTP, CLKOUTN) = Fref*(4*N/M) / CLKOUT_DIFF_DIV_SEL
///     * M: Reference Divider: 1 to 511.
///     * N: Feedback Divider: 1 to 511.
///     * VCODIV: VCO differential divider is controlled by CLKOUT_DIFF_DIV_SEL.
///     * VCO single-ended divider is controlled by CLKOUT_SE_DIV_SEL.
///     * Divider value = 1 1,2,3,4.128.
///     * Update Rate: Fref / M = 8 to 32 MHz (to maintain the PLL stability).
///     * NOTE: Although VCO can be operated between 12 ~ 3 GHz, the 1 ~ 1.5 GHz range is
///     * applicable only in the low power mode and cannot be used with the SSC function. In order to
///     * use the SSC function VCO must be operated above 1.5GHz.
///     * .. Cycle to Cycle Jitter (max): <30 ps.
///     * .. Programmable Reference and Feedback Divider.
///     * .. 1 ppm/step frequency offset resolution. Up to 50,000 ppm without changing the Feedback
///     * Divider setting.
///     * .. SSC frequency range: 30 KHz ~ 100 KHz
///     * .. SSC amplitude range: up to +/-5%. (SSC function is disabled by default.)
///     * .. Supporting both down-spread and center-spread modes.
///     * .. Current consumption( typical corner, AVDD=1.8 V, DVDD=1.05V): see sspll document
///     * .. Locking time: < 50 us
///     * .. Process Node: 28 nm LP
///     * .. Analog Power Supply: 1.8 V (+10%, -5%)
///     * .. Digital Power Supply: 1.05 V (±10%)
///     * Support Low DVDD Mode: Digtial Power Supply = 0.75V ~ 1.32V. See section 2.1 for detail.
///     * .. Output Duty Cycle: 45% - 55% for any post divider ratio
///     * .. Built-in Bandgap circuit.
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               ###
///               * PLL Control register
///               ###
///               %unsigned 1  PU                        0x1
///                                    ###
///                                    * PLL Power-Up
///                                    * 1: power up.
///                                    * 0: power down.
///                                    ###
///               %unsigned 1  RESET                     0x0
///                                    ###
///                                    * Power On Reset. Active high, reset PLL and all logic.
///                                    * 1: reset.
///                                    * 0: no reset.
///                                    ###
///               %unsigned 1  AVDD1815_SEL              0x1
///                                    ###
///                                    * AVDD Select.
///                                    * Selects whether AVDD is 1.8V
///                                    * or 1.5V.
///                                    * 1: 1.8V
///                                    * 0: 1.5V
///                                    ###
///               %unsigned 9  REFDIV                    0x2
///                                    ###
///                                    * Reference Clock Divider
///                                    * Select.
///                                    * Divider = REFDIV[8:0]
///                                    * 9’h000 = divide by 1
///                                    * 9’h001 = divide by 1
///                                    * 9’h002 = divide by 2
///                                    * 9’h003 = divide by 3
///                                    * ...
///                                    * 9’h1FF = divide by 511.
///                                    * REFDIV[8:0] range is 1~250
///                                    ###
///               %unsigned 9  FBDIV                     0x20
///                                    ###
///                                    * Feedback Clock Divider Select.
///                                    * Divider= FBDIV [8:0]
///                                    * 9’h000 = divide by 1
///                                    * 9’h001 = divide by 1
///                                    * 9’h002 = divide by 2
///                                    * 9’h003 = divide by 3
///                                    * ...
///                                    * 9’h1FF = divide by 511.
///                                    * FBDIV range is 9 to 94
///                                    ###
///               %unsigned 2  VDDM                      0x1
///                                    ###
///                                    * VCO Supply Control.
///                                    * The bit enumerations for this
///                                    * signal is used to select a
///                                    * particular supply voltage.
///                                    * Except the default all other
///                                    * bits are for internal use.
///                                    * 11: 1.3V
///                                    * 10: 1.25V
///                                    * 01: 1.2V
///                                    * 00: 1.15V.
///                                    ###
///               %unsigned 3  VDDL                      0x4
///                                    ###
///                                    * Internal VDD Supply
///                                    * Control.
///                                    * The bit enumerations for this
///                                    * signal is used to select a
///                                    * particular supply voltage.
///                                    * Except the default all other
///                                    * bits are for internal use.
///                                    * 000: 0.7V.
///                                    * 001: 0.75V
///                                    * 010: 0.8V
///                                    * 011: 0.85V
///                                    * 100: 0.9V
///                                    * 101: 0.95V
///                                    * 110: 1.0V
///                                    * 111: 1.05V
///                                    ###
///               %unsigned 4  ICP                       0x4
///                                    ###
///                                    * Charge-pump Current Control Bits.
///                                    * 0000: 3 uA
///                                    * 0001: 3.75 uA
///                                    * 0010: 4.5 uA
///                                    * 0011: 5.25 uA
///                                    * 0100: 6 uA
///                                    * 0101: 7.5 uA
///                                    * 0110: 9 uA
///                                    * 0111: 10.5 uA
///                                    * 1000: 12 uA
///                                    * 1001: 15 uA
///                                    * 1010: 18 uA
///                                    * 1011: 21 uA
///                                    * 1100: 24 uA
///                                    * 1101: 30 uA
///                                    * 1110: 36 uA
///                                    * 1111: 42 uA.
///                                    * Note : ICP[3:0] = (10 MHz / Update Rate) * Default.
///                                    * If PU_BW_SEL = 1, then increase ICP value by 2x
///                                    ###
///               %unsigned 1  PLL_BW_SEL                0x0
///                                    ###
///                                    * PLL Bandwidth Select.
///                                    * 1: BW x 2
///                                    * 0: Normal PLL bandwidth.
///                                    * Note: Use bandwidth x 2 only if update rate is between 16 - 32 MHz.
///                                    * NOTE: Bandwidth x 2 is for special cases only. If used, the update rate must be between 16 MHz - 32 MHz.
///                                    ###
///               %%        1          # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 4  KVCO                      0x5
///                                    ###
///                                    * KVCO Frequency Range
///                                    * Select.
///                                    * 0000: Reserved
///                                    * 0001: 1.0G ~ 1.15G
///                                    * 0010: 1.15G ~ 1.25G
///                                    * 0011: 1.25G ~ 1.40G
///                                    * 0100: 1.40G ~ 1.55G
///                                    * 0101: 1.55G ~ 1.65G
///                                    * 0110: 1.65G ~ 1.80G
///                                    * 0111: 1.80G ~ 1.95G
///                                    * 1000: 1.95G ~ 2.17G
///                                    * 1001: 2.17G ~ 2.50G
///                                    * 1010: 2.50G ~ 2.80G
///                                    * 1011: 2.80G ~ 3.10G
///                                    * 1100: 3.10G ~ 3.45G
///                                    * 1101: 3.45G ~ 3.75G
///                                    * 1110: 3.75G ~ 4.0G
///                                    * 1111: Reserved.
///                                    * SSC mode is only supported for frequency >=2 GHz
///                                    * FVCO=((4*REFCLK/M)*N)/(1+OFFSET_PERCENT)
///                                    ###
///               %unsigned 2  CTUNE                     0x2
///                                    ###
///                                    * VCO Capacitor Select.
///                                    * 00: No Cap Loading
///                                    * 01: One Unit Cap Loading
///                                    * 10: Two Unit Cap Loading
///                                    * 11: Three Unit Cap Loading.
///                                    * Besides the default other bit
///                                    * enumerations are for internal
///                                    * use.
///                                    ###
///               %unsigned 9  CLKOUT_DIFF_DIV_SEL       0x4
///                                    ###
///                                    * Post Divider For Differential
///                                    * Output Clock.
///                                    * 9’h000 = 1
///                                    * 9’h001 = 1
///                                    * 9’h002 = 2
///                                    * 9’h003 = 3
///                                    * 9’h004 = 4
///                                    * ...
///                                    * 9’h1FF = 511.
///                                    ###
///               %unsigned 9  CLKOUT_SE_DIV_SEL         0x4
///                                    ###
///                                    * Post Divider For
///                                    * Single-ended Output Clock.
///                                    * 9’h000 = 1
///                                    * 9’h001 = 1
///                                    * 9’h002 = 2
///                                    * 9’h003 = 3
///                                    * 9’h004 = 4
///                                    * ...
///                                    * 9’h1FF = 511.
///                                    ###
///               %unsigned 1  CLKOUT_SOURCE_SEL         0x1
///                                    ###
///                                    * Differential Clock And
///                                    * Single-ended Clock Source Control.
///                                    * 0: from the phase interpolator.
///                                    * 1: from VCO directly.
///                                    * Note: This is used in test mode only. Select ‘1’ for normal operation.
///                                    ###
///               %unsigned 1  CLKOUT_DIFF_EN            0x1
///                                    ###
///                                    * Differential Clock Enable.
///                                    * 0:Disable differential clock
///                                    * 1:Enable differential clock
///                                    ###
///               %unsigned 1  BYPASS_EN                 0x0
///                                    ###
///                                    * PLL Clock Bypass Enable.
///                                    * 1: The PLL is bypassed. CLKOUT is derived from REFCLK.
///                                    * 0: CLKOUT is derived from the PLL clock.
///                                    * NOTE: Bypass only works for the single ended clock.
///                                    * If BYPASS_EN==1. CLKOUT= REFCLK.
///                                    * Make sure Fvco/CLKOUT_SE_DIV_SEL< 2.1 GHz, when using the bypass function.
///                                    ###
///               %unsigned 1  CLKOUT_SE_GATING_EN       0x1
///                                    ###
///                                    * Clock Output Gating Control.
///                                    * Selection for using the PLL lock signal to gate the output clock.
///                                    * 0: The PLL_LOCK signal won't affect the output clock, CLKOUT
///                                    * 1: Use PLL_LOCK signal to gate the output clock, CLKOUT.
///                                    ###
///               %unsigned 1  FBCLK_EXT_SEL             0x0
///                                    ###
///                                    * External Or Internal Feedback
///                                    * Clock Select.
///                                    * 0: select internal feedback clock
///                                    * 1: select external feedback clock.
///                                    * Note: For most applications the external feedback clock is not used. In these cases use the default selection "0".
///                                    ###
///               %%        3          # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 6  FBCDLY                    0x0
///                                    ###
///                                    * Fine Tune Delay Select
///                                    * Between REFCLK And FBCLK_EXT When FBCLK_EXT_SEL = 1.
///                                    * FBCDLY[5] is the sign bit.
///                                    * 1 = FBCLK_EXT will lag REFCLK.
///                                    * 0 = FBCLK_EXT will lead REFCLK.
///                                    * FBCDLY[4:0] decides the actual amount of delay.
///                                    * 00000: No delay.
///                                    * Each additional step has these
///                                    * delays:
///                                    * 00h = No delay
///                                    * 01h = 15 - 50 ps phase difference
///                                    * 02h = 30 - 100 ps phase difference
///                                    * 03h = 45 - 150 ps phase difference
///                                    * ...
///                                    * 3Fh = 945 ps - 3150 ps phase difference.
///                                    * Note: Used in DSPLL application, do not use in regular PLL application.
///                                    ###
///               %unsigned 3  FD                        0x4
///                                    ###
///                                    * Tune Frequency Detector Precision
///                                    * FD[0]: Reserved.
///                                    * FD[2:1] FD precision
///                                    * 00 +/- 0.1%
///                                    * 01 +/- 0.2%
///                                    * 10 +/- 0.4%
///                                    * 11 +/- 0.8%.
///                                    ###
///               %unsigned 4  INTPI                     0x6
///                                    ###
///                                    * Phase Interpolator Bias Current Select.
///                                    * 1~2 GHz Not SUPPORTED
///                                    * 0011 = 10 μA (2 ~ 2.75 GHz)
///                                    * 0101 = 15 μA (2.75 ~ 3.25 GHz).
///                                    * 0111 = 20 μA (3.25 ~ 4 GHz).
///                                    * VCO running frequency below
///                                    * 2 GHz not supported.
///                                    ###
///               %unsigned 3  INTPR                     0x4
///                                    ###
///                                    * Phase Interpolator Resistor Select.
///                                    * NOTE: VCO running frequency below 2 GHz not supported.
///                                    ###
///               %unsigned 1  PI_EN                     0x0
///                                    ###
///                                    * Phase Interpolator Enable.
///                                    * 1: Enable phase interpolator
///                                    * 0: Disable phase interpolator.
///                                    ###
///               %unsigned 1  PI_LOOP_MODE              0x0
///                                    ###
///                                    * Phase Interpolator Loop Control.
///                                    * 1: PI is in the PLL loop.
///                                    * 0: PI is out of the PLL loop
///                                    ###
///               %unsigned 1  CLK_DET_EN                0x1
///                                    ###
///                                    * PI Output Clock Enable. This selection enables the PI output clock for the internal reset circuit
///                                    ###
///               %unsigned 1  RESET_PI                  0x0
///                                    ###
///                                    * External Interpolator Reset.
///                                    * 1: reset.
///                                    * 0: no reset.
///                                    ###
///               %unsigned 1  RESET_SSC                 0x0
///                                    ###
///                                    * SSC reset
///                                    * 0 : No reset
///                                    * 1 : Reset
///                                    ###
///               %unsigned 1  FREQ_OFFSET_EN            0x0
///                                    ###
///                                    * Frequency Offset Enable.
///                                    * 0: Disable
///                                    * 1: Enable.
///                                    ###
///               %%        10         # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 17 FREQ_OFFSET               0x0
///                                    ###
///                                    * Frequency Offset Value
///                                    * Control.
///                                    * [16]: Sign-Bit.
///                                    * 0: Frequency down
///                                    * 1: Frequency up
///                                    * [15:0] : 1 LSB 1 ppm, upto 5%
///                                    * 1LSB=10e6/(4*128 *2048) ppm
///                                    * [16]=0--->Sign= 1
///                                    * [16]=1--->Sign= -1
///                                    * Fout = Fvco/ (1 + Sign* FREQ_OFFSET[15:0] *1LSB)
///                                    ###
///               %unsigned 1  FREQ_OFFSET_MODE_SELECTION 0x0
///                                    ###
///                                    * Frequency Offset Mode Select.
///                                    * 0: FREQ_OFFSET[16:0] is updated by FREQ_OFFSET_VALID
///                                    * 1: FREQ_OFFSET[16:0] is sampled by CK_DIV64_OUT
///                                    * (It has to be valid at the rising edge of CK_DIV64_OUT).
///                                    * Note: For special application only. Use FREQ_OFFSET_VALID to update FREQ_OFFSET[16:0] by default.
///                                    ###
///               %unsigned 1  FREQ_OFFSET_VALID         0x0
///                                    ###
///                                    * Frequency Offset Value Valid.
///                                    * Indicates that frequency offset value (FREQ_OFFSET[16:0]) is valid.
///                                    * Note:
///                                    * 1) A rising edge will trigger the frequency offset generation circuit to read in the FREQ_OFFSET [16:0] value. The pulse width has to be no less than 50 ns.
///                                    * 2) This signal is only needed when FREQ_OFFSET_MODE_SELECTION=0.
///                                    ###
///               %unsigned 1  SSC_CLK_EN                0x0
///                                    ###
///                                    * SSC Clock Enable.
///                                    * This selection enables the PI output clock for SSC digital logic.
///                                    ###
///               %unsigned 1  SSC_MODE                  0x1
///                                    ###
///                                    * SSC Mode Select.
///                                    * 0: center spread
///                                    * 1: down spread.
///                                    ###
///               %%        11         # Stuffing bits...
///     # 0x00010 ctrl4                
///               %unsigned 16 SSC_FREQ_DIV              0x0
///                                    ###
///                                    * SSC Frequency Select.
///                                    ###
///               %unsigned 11 SSC_RNGE                  0x0
///                                    ###
///                                    * SSC Range Select. SSC_RNGE[10:0] = Desired SSC amplitude /(SSC_FREQ_DIV[14:0]*2^(-28)).
///                                    * Rounding to integer required.
///                                    ###
///               %unsigned 4  TEST_ANA                  0x0
///                                    ###
///                                    * Analog test point
///                                    ###
///               %%        1          # Stuffing bits...
///     # 0x00014 ctrl5                
///               %unsigned 8  RESERVE_IN                0x0
///                                    ###
///                                    * Reserved input pins
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00018 status               (R-)
///               ###
///               * PLL status register
///               ###
///               %unsigned 1  PLL_LOCK                  
///                                    ###
///                                    * PLL Lock Detect.
///                                    * 1: PLL locked.
///                                    * 0: PLL not locked.
///                                    * Note:
///                                    * After PLL is powered up, wait for 50 us to check for the lock status.
///                                    * In normal operation, when PLL_LOCK signal is detected low, sample the signal again after 100 us to confirm the status.
///                                    * This signal is for testing purpose only, do not use it for any functional use.
///                                    ###
///               %unsigned 1  CLK_CFMOD                 
///                                    ###
///                                    * Clock Mode Output.
///                                    *  For down spread and
///                                    * PI_LOOP_MODE = 0, output
///                                    * is 0.
///                                    *  For down spread and
///                                    * PI_LOOP_MODE = 1, output
///                                    * is 1.
///                                    *  For center spread, output a
///                                    * clock with SSC modulation
///                                    * frequency.
///                                    ###
///               %unsigned 1  CLK_FMOD                  
///                                    ###
///                                    * Clock Output And Modulation
///                                    * Frequency.
///                                    * For down spread, output a clock
///                                    * with SSC modulation frequency.
///                                    * For center spread, output a clock
///                                    * with double SSC modulation
///                                    * frequency.
///                                    ###
///               %unsigned 8  RESERVE_OUT               
///                                    ###
///                                    * Reserve Output Register pins.
///                                    ###
///               %%        21         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      28B, bits:     153b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_pll
#define h_pll (){}

    #define     RA_pll_ctrl                                    0x0000

    #define     BA_pll_ctrl_PU                                 0x0000
    #define     B16pll_ctrl_PU                                 0x0000
    #define   LSb32pll_ctrl_PU                                    0
    #define   LSb16pll_ctrl_PU                                    0
    #define       bpll_ctrl_PU                                 1
    #define   MSK32pll_ctrl_PU                                    0x00000001

    #define     BA_pll_ctrl_RESET                              0x0000
    #define     B16pll_ctrl_RESET                              0x0000
    #define   LSb32pll_ctrl_RESET                                 1
    #define   LSb16pll_ctrl_RESET                                 1
    #define       bpll_ctrl_RESET                              1
    #define   MSK32pll_ctrl_RESET                                 0x00000002

    #define     BA_pll_ctrl_AVDD1815_SEL                       0x0000
    #define     B16pll_ctrl_AVDD1815_SEL                       0x0000
    #define   LSb32pll_ctrl_AVDD1815_SEL                          2
    #define   LSb16pll_ctrl_AVDD1815_SEL                          2
    #define       bpll_ctrl_AVDD1815_SEL                       1
    #define   MSK32pll_ctrl_AVDD1815_SEL                          0x00000004

    #define     BA_pll_ctrl_REFDIV                             0x0000
    #define     B16pll_ctrl_REFDIV                             0x0000
    #define   LSb32pll_ctrl_REFDIV                                3
    #define   LSb16pll_ctrl_REFDIV                                3
    #define       bpll_ctrl_REFDIV                             9
    #define   MSK32pll_ctrl_REFDIV                                0x00000FF8

    #define     BA_pll_ctrl_FBDIV                              0x0001
    #define     B16pll_ctrl_FBDIV                              0x0000
    #define   LSb32pll_ctrl_FBDIV                                 12
    #define   LSb16pll_ctrl_FBDIV                                 12
    #define       bpll_ctrl_FBDIV                              9
    #define   MSK32pll_ctrl_FBDIV                                 0x001FF000

    #define     BA_pll_ctrl_VDDM                               0x0002
    #define     B16pll_ctrl_VDDM                               0x0002
    #define   LSb32pll_ctrl_VDDM                                  21
    #define   LSb16pll_ctrl_VDDM                                  5
    #define       bpll_ctrl_VDDM                               2
    #define   MSK32pll_ctrl_VDDM                                  0x00600000

    #define     BA_pll_ctrl_VDDL                               0x0002
    #define     B16pll_ctrl_VDDL                               0x0002
    #define   LSb32pll_ctrl_VDDL                                  23
    #define   LSb16pll_ctrl_VDDL                                  7
    #define       bpll_ctrl_VDDL                               3
    #define   MSK32pll_ctrl_VDDL                                  0x03800000

    #define     BA_pll_ctrl_ICP                                0x0003
    #define     B16pll_ctrl_ICP                                0x0002
    #define   LSb32pll_ctrl_ICP                                   26
    #define   LSb16pll_ctrl_ICP                                   10
    #define       bpll_ctrl_ICP                                4
    #define   MSK32pll_ctrl_ICP                                   0x3C000000

    #define     BA_pll_ctrl_PLL_BW_SEL                         0x0003
    #define     B16pll_ctrl_PLL_BW_SEL                         0x0002
    #define   LSb32pll_ctrl_PLL_BW_SEL                            30
    #define   LSb16pll_ctrl_PLL_BW_SEL                            14
    #define       bpll_ctrl_PLL_BW_SEL                         1
    #define   MSK32pll_ctrl_PLL_BW_SEL                            0x40000000

    #define     RA_pll_ctrl1                                   0x0004

    #define     BA_pll_ctrl_KVCO                               0x0004
    #define     B16pll_ctrl_KVCO                               0x0004
    #define   LSb32pll_ctrl_KVCO                                  0
    #define   LSb16pll_ctrl_KVCO                                  0
    #define       bpll_ctrl_KVCO                               4
    #define   MSK32pll_ctrl_KVCO                                  0x0000000F

    #define     BA_pll_ctrl_CTUNE                              0x0004
    #define     B16pll_ctrl_CTUNE                              0x0004
    #define   LSb32pll_ctrl_CTUNE                                 4
    #define   LSb16pll_ctrl_CTUNE                                 4
    #define       bpll_ctrl_CTUNE                              2
    #define   MSK32pll_ctrl_CTUNE                                 0x00000030

    #define     BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL                0x0004
    #define     B16pll_ctrl_CLKOUT_DIFF_DIV_SEL                0x0004
    #define   LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL                   6
    #define   LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL                   6
    #define       bpll_ctrl_CLKOUT_DIFF_DIV_SEL                9
    #define   MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL                   0x00007FC0

    #define     BA_pll_ctrl_CLKOUT_SE_DIV_SEL                  0x0005
    #define     B16pll_ctrl_CLKOUT_SE_DIV_SEL                  0x0004
    #define   LSb32pll_ctrl_CLKOUT_SE_DIV_SEL                     15
    #define   LSb16pll_ctrl_CLKOUT_SE_DIV_SEL                     15
    #define       bpll_ctrl_CLKOUT_SE_DIV_SEL                  9
    #define   MSK32pll_ctrl_CLKOUT_SE_DIV_SEL                     0x00FF8000

    #define     BA_pll_ctrl_CLKOUT_SOURCE_SEL                  0x0007
    #define     B16pll_ctrl_CLKOUT_SOURCE_SEL                  0x0006
    #define   LSb32pll_ctrl_CLKOUT_SOURCE_SEL                     24
    #define   LSb16pll_ctrl_CLKOUT_SOURCE_SEL                     8
    #define       bpll_ctrl_CLKOUT_SOURCE_SEL                  1
    #define   MSK32pll_ctrl_CLKOUT_SOURCE_SEL                     0x01000000

    #define     BA_pll_ctrl_CLKOUT_DIFF_EN                     0x0007
    #define     B16pll_ctrl_CLKOUT_DIFF_EN                     0x0006
    #define   LSb32pll_ctrl_CLKOUT_DIFF_EN                        25
    #define   LSb16pll_ctrl_CLKOUT_DIFF_EN                        9
    #define       bpll_ctrl_CLKOUT_DIFF_EN                     1
    #define   MSK32pll_ctrl_CLKOUT_DIFF_EN                        0x02000000

    #define     BA_pll_ctrl_BYPASS_EN                          0x0007
    #define     B16pll_ctrl_BYPASS_EN                          0x0006
    #define   LSb32pll_ctrl_BYPASS_EN                             26
    #define   LSb16pll_ctrl_BYPASS_EN                             10
    #define       bpll_ctrl_BYPASS_EN                          1
    #define   MSK32pll_ctrl_BYPASS_EN                             0x04000000

    #define     BA_pll_ctrl_CLKOUT_SE_GATING_EN                0x0007
    #define     B16pll_ctrl_CLKOUT_SE_GATING_EN                0x0006
    #define   LSb32pll_ctrl_CLKOUT_SE_GATING_EN                   27
    #define   LSb16pll_ctrl_CLKOUT_SE_GATING_EN                   11
    #define       bpll_ctrl_CLKOUT_SE_GATING_EN                1
    #define   MSK32pll_ctrl_CLKOUT_SE_GATING_EN                   0x08000000

    #define     BA_pll_ctrl_FBCLK_EXT_SEL                      0x0007
    #define     B16pll_ctrl_FBCLK_EXT_SEL                      0x0006
    #define   LSb32pll_ctrl_FBCLK_EXT_SEL                         28
    #define   LSb16pll_ctrl_FBCLK_EXT_SEL                         12
    #define       bpll_ctrl_FBCLK_EXT_SEL                      1
    #define   MSK32pll_ctrl_FBCLK_EXT_SEL                         0x10000000

    #define     RA_pll_ctrl2                                   0x0008

    #define     BA_pll_ctrl_FBCDLY                             0x0008
    #define     B16pll_ctrl_FBCDLY                             0x0008
    #define   LSb32pll_ctrl_FBCDLY                                0
    #define   LSb16pll_ctrl_FBCDLY                                0
    #define       bpll_ctrl_FBCDLY                             6
    #define   MSK32pll_ctrl_FBCDLY                                0x0000003F

    #define     BA_pll_ctrl_FD                                 0x0008
    #define     B16pll_ctrl_FD                                 0x0008
    #define   LSb32pll_ctrl_FD                                    6
    #define   LSb16pll_ctrl_FD                                    6
    #define       bpll_ctrl_FD                                 3
    #define   MSK32pll_ctrl_FD                                    0x000001C0

    #define     BA_pll_ctrl_INTPI                              0x0009
    #define     B16pll_ctrl_INTPI                              0x0008
    #define   LSb32pll_ctrl_INTPI                                 9
    #define   LSb16pll_ctrl_INTPI                                 9
    #define       bpll_ctrl_INTPI                              4
    #define   MSK32pll_ctrl_INTPI                                 0x00001E00

    #define     BA_pll_ctrl_INTPR                              0x0009
    #define     B16pll_ctrl_INTPR                              0x0008
    #define   LSb32pll_ctrl_INTPR                                 13
    #define   LSb16pll_ctrl_INTPR                                 13
    #define       bpll_ctrl_INTPR                              3
    #define   MSK32pll_ctrl_INTPR                                 0x0000E000

    #define     BA_pll_ctrl_PI_EN                              0x000A
    #define     B16pll_ctrl_PI_EN                              0x000A
    #define   LSb32pll_ctrl_PI_EN                                 16
    #define   LSb16pll_ctrl_PI_EN                                 0
    #define       bpll_ctrl_PI_EN                              1
    #define   MSK32pll_ctrl_PI_EN                                 0x00010000

    #define     BA_pll_ctrl_PI_LOOP_MODE                       0x000A
    #define     B16pll_ctrl_PI_LOOP_MODE                       0x000A
    #define   LSb32pll_ctrl_PI_LOOP_MODE                          17
    #define   LSb16pll_ctrl_PI_LOOP_MODE                          1
    #define       bpll_ctrl_PI_LOOP_MODE                       1
    #define   MSK32pll_ctrl_PI_LOOP_MODE                          0x00020000

    #define     BA_pll_ctrl_CLK_DET_EN                         0x000A
    #define     B16pll_ctrl_CLK_DET_EN                         0x000A
    #define   LSb32pll_ctrl_CLK_DET_EN                            18
    #define   LSb16pll_ctrl_CLK_DET_EN                            2
    #define       bpll_ctrl_CLK_DET_EN                         1
    #define   MSK32pll_ctrl_CLK_DET_EN                            0x00040000

    #define     BA_pll_ctrl_RESET_PI                           0x000A
    #define     B16pll_ctrl_RESET_PI                           0x000A
    #define   LSb32pll_ctrl_RESET_PI                              19
    #define   LSb16pll_ctrl_RESET_PI                              3
    #define       bpll_ctrl_RESET_PI                           1
    #define   MSK32pll_ctrl_RESET_PI                              0x00080000

    #define     BA_pll_ctrl_RESET_SSC                          0x000A
    #define     B16pll_ctrl_RESET_SSC                          0x000A
    #define   LSb32pll_ctrl_RESET_SSC                             20
    #define   LSb16pll_ctrl_RESET_SSC                             4
    #define       bpll_ctrl_RESET_SSC                          1
    #define   MSK32pll_ctrl_RESET_SSC                             0x00100000

    #define     BA_pll_ctrl_FREQ_OFFSET_EN                     0x000A
    #define     B16pll_ctrl_FREQ_OFFSET_EN                     0x000A
    #define   LSb32pll_ctrl_FREQ_OFFSET_EN                        21
    #define   LSb16pll_ctrl_FREQ_OFFSET_EN                        5
    #define       bpll_ctrl_FREQ_OFFSET_EN                     1
    #define   MSK32pll_ctrl_FREQ_OFFSET_EN                        0x00200000

    #define     RA_pll_ctrl3                                   0x000C

    #define     BA_pll_ctrl_FREQ_OFFSET                        0x000C
    #define     B16pll_ctrl_FREQ_OFFSET                        0x000C
    #define   LSb32pll_ctrl_FREQ_OFFSET                           0
    #define   LSb16pll_ctrl_FREQ_OFFSET                           0
    #define       bpll_ctrl_FREQ_OFFSET                        17
    #define   MSK32pll_ctrl_FREQ_OFFSET                           0x0001FFFF

    #define     BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION         0x000E
    #define     B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION         0x000E
    #define   LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION            17
    #define   LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION            1
    #define       bpll_ctrl_FREQ_OFFSET_MODE_SELECTION         1
    #define   MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION            0x00020000

    #define     BA_pll_ctrl_FREQ_OFFSET_VALID                  0x000E
    #define     B16pll_ctrl_FREQ_OFFSET_VALID                  0x000E
    #define   LSb32pll_ctrl_FREQ_OFFSET_VALID                     18
    #define   LSb16pll_ctrl_FREQ_OFFSET_VALID                     2
    #define       bpll_ctrl_FREQ_OFFSET_VALID                  1
    #define   MSK32pll_ctrl_FREQ_OFFSET_VALID                     0x00040000

    #define     BA_pll_ctrl_SSC_CLK_EN                         0x000E
    #define     B16pll_ctrl_SSC_CLK_EN                         0x000E
    #define   LSb32pll_ctrl_SSC_CLK_EN                            19
    #define   LSb16pll_ctrl_SSC_CLK_EN                            3
    #define       bpll_ctrl_SSC_CLK_EN                         1
    #define   MSK32pll_ctrl_SSC_CLK_EN                            0x00080000

    #define     BA_pll_ctrl_SSC_MODE                           0x000E
    #define     B16pll_ctrl_SSC_MODE                           0x000E
    #define   LSb32pll_ctrl_SSC_MODE                              20
    #define   LSb16pll_ctrl_SSC_MODE                              4
    #define       bpll_ctrl_SSC_MODE                           1
    #define   MSK32pll_ctrl_SSC_MODE                              0x00100000

    #define     RA_pll_ctrl4                                   0x0010

    #define     BA_pll_ctrl_SSC_FREQ_DIV                       0x0010
    #define     B16pll_ctrl_SSC_FREQ_DIV                       0x0010
    #define   LSb32pll_ctrl_SSC_FREQ_DIV                          0
    #define   LSb16pll_ctrl_SSC_FREQ_DIV                          0
    #define       bpll_ctrl_SSC_FREQ_DIV                       16
    #define   MSK32pll_ctrl_SSC_FREQ_DIV                          0x0000FFFF

    #define     BA_pll_ctrl_SSC_RNGE                           0x0012
    #define     B16pll_ctrl_SSC_RNGE                           0x0012
    #define   LSb32pll_ctrl_SSC_RNGE                              16
    #define   LSb16pll_ctrl_SSC_RNGE                              0
    #define       bpll_ctrl_SSC_RNGE                           11
    #define   MSK32pll_ctrl_SSC_RNGE                              0x07FF0000

    #define     BA_pll_ctrl_TEST_ANA                           0x0013
    #define     B16pll_ctrl_TEST_ANA                           0x0012
    #define   LSb32pll_ctrl_TEST_ANA                              27
    #define   LSb16pll_ctrl_TEST_ANA                              11
    #define       bpll_ctrl_TEST_ANA                           4
    #define   MSK32pll_ctrl_TEST_ANA                              0x78000000

    #define     RA_pll_ctrl5                                   0x0014

    #define     BA_pll_ctrl_RESERVE_IN                         0x0014
    #define     B16pll_ctrl_RESERVE_IN                         0x0014
    #define   LSb32pll_ctrl_RESERVE_IN                            0
    #define   LSb16pll_ctrl_RESERVE_IN                            0
    #define       bpll_ctrl_RESERVE_IN                         8
    #define   MSK32pll_ctrl_RESERVE_IN                            0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_pll_status                                  0x0018

    #define     BA_pll_status_PLL_LOCK                         0x0018
    #define     B16pll_status_PLL_LOCK                         0x0018
    #define   LSb32pll_status_PLL_LOCK                            0
    #define   LSb16pll_status_PLL_LOCK                            0
    #define       bpll_status_PLL_LOCK                         1
    #define   MSK32pll_status_PLL_LOCK                            0x00000001

    #define     BA_pll_status_CLK_CFMOD                        0x0018
    #define     B16pll_status_CLK_CFMOD                        0x0018
    #define   LSb32pll_status_CLK_CFMOD                           1
    #define   LSb16pll_status_CLK_CFMOD                           1
    #define       bpll_status_CLK_CFMOD                        1
    #define   MSK32pll_status_CLK_CFMOD                           0x00000002

    #define     BA_pll_status_CLK_FMOD                         0x0018
    #define     B16pll_status_CLK_FMOD                         0x0018
    #define   LSb32pll_status_CLK_FMOD                            2
    #define   LSb16pll_status_CLK_FMOD                            2
    #define       bpll_status_CLK_FMOD                         1
    #define   MSK32pll_status_CLK_FMOD                            0x00000004

    #define     BA_pll_status_RESERVE_OUT                      0x0018
    #define     B16pll_status_RESERVE_OUT                      0x0018
    #define   LSb32pll_status_RESERVE_OUT                         3
    #define   LSb16pll_status_RESERVE_OUT                         3
    #define       bpll_status_RESERVE_OUT                      8
    #define   MSK32pll_status_RESERVE_OUT                         0x000007F8
    ///////////////////////////////////////////////////////////

    typedef struct SIE_pll {
    ///////////////////////////////////////////////////////////
    #define   GET32pll_ctrl_PU(r32)                            _BFGET_(r32, 0, 0)
    #define   SET32pll_ctrl_PU(r32,v)                          _BFSET_(r32, 0, 0,v)
    #define   GET16pll_ctrl_PU(r16)                            _BFGET_(r16, 0, 0)
    #define   SET16pll_ctrl_PU(r16,v)                          _BFSET_(r16, 0, 0,v)

    #define   GET32pll_ctrl_RESET(r32)                         _BFGET_(r32, 1, 1)
    #define   SET32pll_ctrl_RESET(r32,v)                       _BFSET_(r32, 1, 1,v)
    #define   GET16pll_ctrl_RESET(r16)                         _BFGET_(r16, 1, 1)
    #define   SET16pll_ctrl_RESET(r16,v)                       _BFSET_(r16, 1, 1,v)

    #define   GET32pll_ctrl_AVDD1815_SEL(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32pll_ctrl_AVDD1815_SEL(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16pll_ctrl_AVDD1815_SEL(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16pll_ctrl_AVDD1815_SEL(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32pll_ctrl_REFDIV(r32)                        _BFGET_(r32,11, 3)
    #define   SET32pll_ctrl_REFDIV(r32,v)                      _BFSET_(r32,11, 3,v)
    #define   GET16pll_ctrl_REFDIV(r16)                        _BFGET_(r16,11, 3)
    #define   SET16pll_ctrl_REFDIV(r16,v)                      _BFSET_(r16,11, 3,v)

    #define   GET32pll_ctrl_FBDIV(r32)                         _BFGET_(r32,20,12)
    #define   SET32pll_ctrl_FBDIV(r32,v)                       _BFSET_(r32,20,12,v)

    #define   GET32pll_ctrl_VDDM(r32)                          _BFGET_(r32,22,21)
    #define   SET32pll_ctrl_VDDM(r32,v)                        _BFSET_(r32,22,21,v)
    #define   GET16pll_ctrl_VDDM(r16)                          _BFGET_(r16, 6, 5)
    #define   SET16pll_ctrl_VDDM(r16,v)                        _BFSET_(r16, 6, 5,v)

    #define   GET32pll_ctrl_VDDL(r32)                          _BFGET_(r32,25,23)
    #define   SET32pll_ctrl_VDDL(r32,v)                        _BFSET_(r32,25,23,v)
    #define   GET16pll_ctrl_VDDL(r16)                          _BFGET_(r16, 9, 7)
    #define   SET16pll_ctrl_VDDL(r16,v)                        _BFSET_(r16, 9, 7,v)

    #define   GET32pll_ctrl_ICP(r32)                           _BFGET_(r32,29,26)
    #define   SET32pll_ctrl_ICP(r32,v)                         _BFSET_(r32,29,26,v)
    #define   GET16pll_ctrl_ICP(r16)                           _BFGET_(r16,13,10)
    #define   SET16pll_ctrl_ICP(r16,v)                         _BFSET_(r16,13,10,v)

    #define   GET32pll_ctrl_PLL_BW_SEL(r32)                    _BFGET_(r32,30,30)
    #define   SET32pll_ctrl_PLL_BW_SEL(r32,v)                  _BFSET_(r32,30,30,v)
    #define   GET16pll_ctrl_PLL_BW_SEL(r16)                    _BFGET_(r16,14,14)
    #define   SET16pll_ctrl_PLL_BW_SEL(r16,v)                  _BFSET_(r16,14,14,v)

    #define     w32pll_ctrl                                    {\
            UNSG32 uctrl_PU                                    :  1;\
            UNSG32 uctrl_RESET                                 :  1;\
            UNSG32 uctrl_AVDD1815_SEL                          :  1;\
            UNSG32 uctrl_REFDIV                                :  9;\
            UNSG32 uctrl_FBDIV                                 :  9;\
            UNSG32 uctrl_VDDM                                  :  2;\
            UNSG32 uctrl_VDDL                                  :  3;\
            UNSG32 uctrl_ICP                                   :  4;\
            UNSG32 uctrl_PLL_BW_SEL                            :  1;\
            UNSG32 RSVDx0_b31                                  :  1;\
          }
    union { UNSG32 u32pll_ctrl;
            struct w32pll_ctrl;
          };
    #define   GET32pll_ctrl_KVCO(r32)                          _BFGET_(r32, 3, 0)
    #define   SET32pll_ctrl_KVCO(r32,v)                        _BFSET_(r32, 3, 0,v)
    #define   GET16pll_ctrl_KVCO(r16)                          _BFGET_(r16, 3, 0)
    #define   SET16pll_ctrl_KVCO(r16,v)                        _BFSET_(r16, 3, 0,v)

    #define   GET32pll_ctrl_CTUNE(r32)                         _BFGET_(r32, 5, 4)
    #define   SET32pll_ctrl_CTUNE(r32,v)                       _BFSET_(r32, 5, 4,v)
    #define   GET16pll_ctrl_CTUNE(r16)                         _BFGET_(r16, 5, 4)
    #define   SET16pll_ctrl_CTUNE(r16,v)                       _BFSET_(r16, 5, 4,v)

    #define   GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32)           _BFGET_(r32,14, 6)
    #define   SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v)         _BFSET_(r32,14, 6,v)
    #define   GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16)           _BFGET_(r16,14, 6)
    #define   SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v)         _BFSET_(r16,14, 6,v)

    #define   GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32)             _BFGET_(r32,23,15)
    #define   SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v)           _BFSET_(r32,23,15,v)

    #define   GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32)             _BFGET_(r32,24,24)
    #define   SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v)           _BFSET_(r32,24,24,v)
    #define   GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16)             _BFGET_(r16, 8, 8)
    #define   SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v)           _BFSET_(r16, 8, 8,v)

    #define   GET32pll_ctrl_CLKOUT_DIFF_EN(r32)                _BFGET_(r32,25,25)
    #define   SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v)              _BFSET_(r32,25,25,v)
    #define   GET16pll_ctrl_CLKOUT_DIFF_EN(r16)                _BFGET_(r16, 9, 9)
    #define   SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v)              _BFSET_(r16, 9, 9,v)

    #define   GET32pll_ctrl_BYPASS_EN(r32)                     _BFGET_(r32,26,26)
    #define   SET32pll_ctrl_BYPASS_EN(r32,v)                   _BFSET_(r32,26,26,v)
    #define   GET16pll_ctrl_BYPASS_EN(r16)                     _BFGET_(r16,10,10)
    #define   SET16pll_ctrl_BYPASS_EN(r16,v)                   _BFSET_(r16,10,10,v)

    #define   GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32)           _BFGET_(r32,27,27)
    #define   SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v)         _BFSET_(r32,27,27,v)
    #define   GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16)           _BFGET_(r16,11,11)
    #define   SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v)         _BFSET_(r16,11,11,v)

    #define   GET32pll_ctrl_FBCLK_EXT_SEL(r32)                 _BFGET_(r32,28,28)
    #define   SET32pll_ctrl_FBCLK_EXT_SEL(r32,v)               _BFSET_(r32,28,28,v)
    #define   GET16pll_ctrl_FBCLK_EXT_SEL(r16)                 _BFGET_(r16,12,12)
    #define   SET16pll_ctrl_FBCLK_EXT_SEL(r16,v)               _BFSET_(r16,12,12,v)

    #define     w32pll_ctrl1                                   {\
            UNSG32 uctrl_KVCO                                  :  4;\
            UNSG32 uctrl_CTUNE                                 :  2;\
            UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL                   :  9;\
            UNSG32 uctrl_CLKOUT_SE_DIV_SEL                     :  9;\
            UNSG32 uctrl_CLKOUT_SOURCE_SEL                     :  1;\
            UNSG32 uctrl_CLKOUT_DIFF_EN                        :  1;\
            UNSG32 uctrl_BYPASS_EN                             :  1;\
            UNSG32 uctrl_CLKOUT_SE_GATING_EN                   :  1;\
            UNSG32 uctrl_FBCLK_EXT_SEL                         :  1;\
            UNSG32 RSVDx4_b29                                  :  3;\
          }
    union { UNSG32 u32pll_ctrl1;
            struct w32pll_ctrl1;
          };
    #define   GET32pll_ctrl_FBCDLY(r32)                        _BFGET_(r32, 5, 0)
    #define   SET32pll_ctrl_FBCDLY(r32,v)                      _BFSET_(r32, 5, 0,v)
    #define   GET16pll_ctrl_FBCDLY(r16)                        _BFGET_(r16, 5, 0)
    #define   SET16pll_ctrl_FBCDLY(r16,v)                      _BFSET_(r16, 5, 0,v)

    #define   GET32pll_ctrl_FD(r32)                            _BFGET_(r32, 8, 6)
    #define   SET32pll_ctrl_FD(r32,v)                          _BFSET_(r32, 8, 6,v)
    #define   GET16pll_ctrl_FD(r16)                            _BFGET_(r16, 8, 6)
    #define   SET16pll_ctrl_FD(r16,v)                          _BFSET_(r16, 8, 6,v)

    #define   GET32pll_ctrl_INTPI(r32)                         _BFGET_(r32,12, 9)
    #define   SET32pll_ctrl_INTPI(r32,v)                       _BFSET_(r32,12, 9,v)
    #define   GET16pll_ctrl_INTPI(r16)                         _BFGET_(r16,12, 9)
    #define   SET16pll_ctrl_INTPI(r16,v)                       _BFSET_(r16,12, 9,v)

    #define   GET32pll_ctrl_INTPR(r32)                         _BFGET_(r32,15,13)
    #define   SET32pll_ctrl_INTPR(r32,v)                       _BFSET_(r32,15,13,v)
    #define   GET16pll_ctrl_INTPR(r16)                         _BFGET_(r16,15,13)
    #define   SET16pll_ctrl_INTPR(r16,v)                       _BFSET_(r16,15,13,v)

    #define   GET32pll_ctrl_PI_EN(r32)                         _BFGET_(r32,16,16)
    #define   SET32pll_ctrl_PI_EN(r32,v)                       _BFSET_(r32,16,16,v)
    #define   GET16pll_ctrl_PI_EN(r16)                         _BFGET_(r16, 0, 0)
    #define   SET16pll_ctrl_PI_EN(r16,v)                       _BFSET_(r16, 0, 0,v)

    #define   GET32pll_ctrl_PI_LOOP_MODE(r32)                  _BFGET_(r32,17,17)
    #define   SET32pll_ctrl_PI_LOOP_MODE(r32,v)                _BFSET_(r32,17,17,v)
    #define   GET16pll_ctrl_PI_LOOP_MODE(r16)                  _BFGET_(r16, 1, 1)
    #define   SET16pll_ctrl_PI_LOOP_MODE(r16,v)                _BFSET_(r16, 1, 1,v)

    #define   GET32pll_ctrl_CLK_DET_EN(r32)                    _BFGET_(r32,18,18)
    #define   SET32pll_ctrl_CLK_DET_EN(r32,v)                  _BFSET_(r32,18,18,v)
    #define   GET16pll_ctrl_CLK_DET_EN(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16pll_ctrl_CLK_DET_EN(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32pll_ctrl_RESET_PI(r32)                      _BFGET_(r32,19,19)
    #define   SET32pll_ctrl_RESET_PI(r32,v)                    _BFSET_(r32,19,19,v)
    #define   GET16pll_ctrl_RESET_PI(r16)                      _BFGET_(r16, 3, 3)
    #define   SET16pll_ctrl_RESET_PI(r16,v)                    _BFSET_(r16, 3, 3,v)

    #define   GET32pll_ctrl_RESET_SSC(r32)                     _BFGET_(r32,20,20)
    #define   SET32pll_ctrl_RESET_SSC(r32,v)                   _BFSET_(r32,20,20,v)
    #define   GET16pll_ctrl_RESET_SSC(r16)                     _BFGET_(r16, 4, 4)
    #define   SET16pll_ctrl_RESET_SSC(r16,v)                   _BFSET_(r16, 4, 4,v)

    #define   GET32pll_ctrl_FREQ_OFFSET_EN(r32)                _BFGET_(r32,21,21)
    #define   SET32pll_ctrl_FREQ_OFFSET_EN(r32,v)              _BFSET_(r32,21,21,v)
    #define   GET16pll_ctrl_FREQ_OFFSET_EN(r16)                _BFGET_(r16, 5, 5)
    #define   SET16pll_ctrl_FREQ_OFFSET_EN(r16,v)              _BFSET_(r16, 5, 5,v)

    #define     w32pll_ctrl2                                   {\
            UNSG32 uctrl_FBCDLY                                :  6;\
            UNSG32 uctrl_FD                                    :  3;\
            UNSG32 uctrl_INTPI                                 :  4;\
            UNSG32 uctrl_INTPR                                 :  3;\
            UNSG32 uctrl_PI_EN                                 :  1;\
            UNSG32 uctrl_PI_LOOP_MODE                          :  1;\
            UNSG32 uctrl_CLK_DET_EN                            :  1;\
            UNSG32 uctrl_RESET_PI                              :  1;\
            UNSG32 uctrl_RESET_SSC                             :  1;\
            UNSG32 uctrl_FREQ_OFFSET_EN                        :  1;\
            UNSG32 RSVDx8_b22                                  : 10;\
          }
    union { UNSG32 u32pll_ctrl2;
            struct w32pll_ctrl2;
          };
    #define   GET32pll_ctrl_FREQ_OFFSET(r32)                   _BFGET_(r32,16, 0)
    #define   SET32pll_ctrl_FREQ_OFFSET(r32,v)                 _BFSET_(r32,16, 0,v)

    #define   GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32)    _BFGET_(r32,17,17)
    #define   SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v)  _BFSET_(r32,17,17,v)
    #define   GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16)    _BFGET_(r16, 1, 1)
    #define   SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v)  _BFSET_(r16, 1, 1,v)

    #define   GET32pll_ctrl_FREQ_OFFSET_VALID(r32)             _BFGET_(r32,18,18)
    #define   SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v)           _BFSET_(r32,18,18,v)
    #define   GET16pll_ctrl_FREQ_OFFSET_VALID(r16)             _BFGET_(r16, 2, 2)
    #define   SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v)           _BFSET_(r16, 2, 2,v)

    #define   GET32pll_ctrl_SSC_CLK_EN(r32)                    _BFGET_(r32,19,19)
    #define   SET32pll_ctrl_SSC_CLK_EN(r32,v)                  _BFSET_(r32,19,19,v)
    #define   GET16pll_ctrl_SSC_CLK_EN(r16)                    _BFGET_(r16, 3, 3)
    #define   SET16pll_ctrl_SSC_CLK_EN(r16,v)                  _BFSET_(r16, 3, 3,v)

    #define   GET32pll_ctrl_SSC_MODE(r32)                      _BFGET_(r32,20,20)
    #define   SET32pll_ctrl_SSC_MODE(r32,v)                    _BFSET_(r32,20,20,v)
    #define   GET16pll_ctrl_SSC_MODE(r16)                      _BFGET_(r16, 4, 4)
    #define   SET16pll_ctrl_SSC_MODE(r16,v)                    _BFSET_(r16, 4, 4,v)

    #define     w32pll_ctrl3                                   {\
            UNSG32 uctrl_FREQ_OFFSET                           : 17;\
            UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION            :  1;\
            UNSG32 uctrl_FREQ_OFFSET_VALID                     :  1;\
            UNSG32 uctrl_SSC_CLK_EN                            :  1;\
            UNSG32 uctrl_SSC_MODE                              :  1;\
            UNSG32 RSVDxC_b21                                  : 11;\
          }
    union { UNSG32 u32pll_ctrl3;
            struct w32pll_ctrl3;
          };
    #define   GET32pll_ctrl_SSC_FREQ_DIV(r32)                  _BFGET_(r32,15, 0)
    #define   SET32pll_ctrl_SSC_FREQ_DIV(r32,v)                _BFSET_(r32,15, 0,v)
    #define   GET16pll_ctrl_SSC_FREQ_DIV(r16)                  _BFGET_(r16,15, 0)
    #define   SET16pll_ctrl_SSC_FREQ_DIV(r16,v)                _BFSET_(r16,15, 0,v)

    #define   GET32pll_ctrl_SSC_RNGE(r32)                      _BFGET_(r32,26,16)
    #define   SET32pll_ctrl_SSC_RNGE(r32,v)                    _BFSET_(r32,26,16,v)
    #define   GET16pll_ctrl_SSC_RNGE(r16)                      _BFGET_(r16,10, 0)
    #define   SET16pll_ctrl_SSC_RNGE(r16,v)                    _BFSET_(r16,10, 0,v)

    #define   GET32pll_ctrl_TEST_ANA(r32)                      _BFGET_(r32,30,27)
    #define   SET32pll_ctrl_TEST_ANA(r32,v)                    _BFSET_(r32,30,27,v)
    #define   GET16pll_ctrl_TEST_ANA(r16)                      _BFGET_(r16,14,11)
    #define   SET16pll_ctrl_TEST_ANA(r16,v)                    _BFSET_(r16,14,11,v)

    #define     w32pll_ctrl4                                   {\
            UNSG32 uctrl_SSC_FREQ_DIV                          : 16;\
            UNSG32 uctrl_SSC_RNGE                              : 11;\
            UNSG32 uctrl_TEST_ANA                              :  4;\
            UNSG32 RSVDx10_b31                                 :  1;\
          }
    union { UNSG32 u32pll_ctrl4;
            struct w32pll_ctrl4;
          };
    #define   GET32pll_ctrl_RESERVE_IN(r32)                    _BFGET_(r32, 7, 0)
    #define   SET32pll_ctrl_RESERVE_IN(r32,v)                  _BFSET_(r32, 7, 0,v)
    #define   GET16pll_ctrl_RESERVE_IN(r16)                    _BFGET_(r16, 7, 0)
    #define   SET16pll_ctrl_RESERVE_IN(r16,v)                  _BFSET_(r16, 7, 0,v)

    #define     w32pll_ctrl5                                   {\
            UNSG32 uctrl_RESERVE_IN                            :  8;\
            UNSG32 RSVDx14_b8                                  : 24;\
          }
    union { UNSG32 u32pll_ctrl5;
            struct w32pll_ctrl5;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32pll_status_PLL_LOCK(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32pll_status_PLL_LOCK(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16pll_status_PLL_LOCK(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16pll_status_PLL_LOCK(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32pll_status_CLK_CFMOD(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32pll_status_CLK_CFMOD(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16pll_status_CLK_CFMOD(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16pll_status_CLK_CFMOD(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define   GET32pll_status_CLK_FMOD(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32pll_status_CLK_FMOD(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16pll_status_CLK_FMOD(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16pll_status_CLK_FMOD(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32pll_status_RESERVE_OUT(r32)                 _BFGET_(r32,10, 3)
    #define   SET32pll_status_RESERVE_OUT(r32,v)               _BFSET_(r32,10, 3,v)
    #define   GET16pll_status_RESERVE_OUT(r16)                 _BFGET_(r16,10, 3)
    #define   SET16pll_status_RESERVE_OUT(r16,v)               _BFSET_(r16,10, 3,v)

    #define     w32pll_status                                  {\
            UNSG32 ustatus_PLL_LOCK                            :  1;\
            UNSG32 ustatus_CLK_CFMOD                           :  1;\
            UNSG32 ustatus_CLK_FMOD                            :  1;\
            UNSG32 ustatus_RESERVE_OUT                         :  8;\
            UNSG32 RSVDx18_b11                                 : 21;\
          }
    union { UNSG32 u32pll_status;
            struct w32pll_status;
          };
    ///////////////////////////////////////////////////////////
    } SIE_pll;

    typedef union  T32pll_ctrl
          { UNSG32 u32;
            struct w32pll_ctrl;
                 } T32pll_ctrl;
    typedef union  T32pll_ctrl1
          { UNSG32 u32;
            struct w32pll_ctrl1;
                 } T32pll_ctrl1;
    typedef union  T32pll_ctrl2
          { UNSG32 u32;
            struct w32pll_ctrl2;
                 } T32pll_ctrl2;
    typedef union  T32pll_ctrl3
          { UNSG32 u32;
            struct w32pll_ctrl3;
                 } T32pll_ctrl3;
    typedef union  T32pll_ctrl4
          { UNSG32 u32;
            struct w32pll_ctrl4;
                 } T32pll_ctrl4;
    typedef union  T32pll_ctrl5
          { UNSG32 u32;
            struct w32pll_ctrl5;
                 } T32pll_ctrl5;
    typedef union  T32pll_status
          { UNSG32 u32;
            struct w32pll_status;
                 } T32pll_status;
    ///////////////////////////////////////////////////////////

    typedef union  Tpll_ctrl
          { UNSG32 u32[6];
            struct {
            struct w32pll_ctrl;
            struct w32pll_ctrl1;
            struct w32pll_ctrl2;
            struct w32pll_ctrl3;
            struct w32pll_ctrl4;
            struct w32pll_ctrl5;
                   };
                 } Tpll_ctrl;
    typedef union  Tpll_status
          { UNSG32 u32[1];
            struct {
            struct w32pll_status;
                   };
                 } Tpll_status;

    ///////////////////////////////////////////////////////////
     SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void pll_reset(SIE_pll *p);
     SIGN32 pll_cmp  (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define pll_print(p,    pfx,hLOG) pll_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: pll
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE MoltresReg              biu              (4,4)
///     ###
///     * All the controls for Moltres (PJ4-MP) sub-system (moltres_mp_ip).
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL5                (RW-)
///               ###
///               * CoreSight related controls
///               ###
///               %unsigned 1  dbgen                     0x1
///                                    ###
///                                    * Invasive Debug Enable.
///                                    ###
///               %unsigned 1  spiden                    0x1
///                                    ###
///                                    * Secure Invasive Debug Enable
///                                    ###
///               %unsigned 1  niden                     0x1
///                                    ###
///                                    * Non Invasive Debug Enable
///                                    ###
///               %unsigned 1  spniden                   0x1
///                                    ###
///                                    * Secure Non Invasive Debug Enable
///                                    ###
///               %unsigned 1  dbgrq                     0x0
///                                    ###
///                                    * Always write as 0.
///                                    ###
///               %unsigned 1  TPCTL                     0x0
///                                    ###
///                                    * report the presence of TRACECTL pin.
///                                    ###
///               %unsigned 5  TPMAXDATASIZE             0x0
///                                    ###
///                                    * indicates the maximum TRACEDATA width.
///                                    ###
///               %unsigned 1  DEVICEEN                  0x1
///                                    ###
///                                    * Enables APB-AP interface
///                                    ###
///               %%        20         # Stuffing bits...
///     @ 0x00004 SoftResetn           (P)
///               ###
///               * Controls various reset inputs of moltres_mp_ip
///               ###
///               %unsigned 1  CPUAxi                    0x1
///                                    ###
///                                    * Active low reset for CPU's AXI bus. Connected to HRESETn input of moltres_mp_ip.
///                                    ###
///               %unsigned 1  MpSubSys                  0x1
///                                    ###
///                                    * Active low reset for MP sub-system (peripherals, timers, watchdogs, AXI, ATB).
///                                    * Controls subsys_awake_nreset input of moltres_mp_ip
///                                    ###
///               %unsigned 1  CoreSight                 0x1
///                                    ###
///                                    * Active low reset for CoreSight module. Resets APB , ATB & CTM interfaces.
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x00008 sysIntPol            (P)
///               %unsigned 32 invert                    0x0
///                                    ###
///                                    * one bit per each interrupt source, interrupt position follow IRQ table defined in pic.sxw.txt
///                                    * 0 : Don't invert before sending to GIC inside PJ4-MP
///                                    * 1 : Invert before sending to GIC inside PJ4B-MP
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      12B, bits:      47b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MoltresReg
#define h_MoltresReg (){}

    #define     RA_MoltresReg_CTRL5                            0x0000

    #define     BA_MoltresReg_CTRL5_dbgen                      0x0000
    #define     B16MoltresReg_CTRL5_dbgen                      0x0000
    #define   LSb32MoltresReg_CTRL5_dbgen                         0
    #define   LSb16MoltresReg_CTRL5_dbgen                         0
    #define       bMoltresReg_CTRL5_dbgen                      1
    #define   MSK32MoltresReg_CTRL5_dbgen                         0x00000001

    #define     BA_MoltresReg_CTRL5_spiden                     0x0000
    #define     B16MoltresReg_CTRL5_spiden                     0x0000
    #define   LSb32MoltresReg_CTRL5_spiden                        1
    #define   LSb16MoltresReg_CTRL5_spiden                        1
    #define       bMoltresReg_CTRL5_spiden                     1
    #define   MSK32MoltresReg_CTRL5_spiden                        0x00000002

    #define     BA_MoltresReg_CTRL5_niden                      0x0000
    #define     B16MoltresReg_CTRL5_niden                      0x0000
    #define   LSb32MoltresReg_CTRL5_niden                         2
    #define   LSb16MoltresReg_CTRL5_niden                         2
    #define       bMoltresReg_CTRL5_niden                      1
    #define   MSK32MoltresReg_CTRL5_niden                         0x00000004

    #define     BA_MoltresReg_CTRL5_spniden                    0x0000
    #define     B16MoltresReg_CTRL5_spniden                    0x0000
    #define   LSb32MoltresReg_CTRL5_spniden                       3
    #define   LSb16MoltresReg_CTRL5_spniden                       3
    #define       bMoltresReg_CTRL5_spniden                    1
    #define   MSK32MoltresReg_CTRL5_spniden                       0x00000008

    #define     BA_MoltresReg_CTRL5_dbgrq                      0x0000
    #define     B16MoltresReg_CTRL5_dbgrq                      0x0000
    #define   LSb32MoltresReg_CTRL5_dbgrq                         4
    #define   LSb16MoltresReg_CTRL5_dbgrq                         4
    #define       bMoltresReg_CTRL5_dbgrq                      1
    #define   MSK32MoltresReg_CTRL5_dbgrq                         0x00000010

    #define     BA_MoltresReg_CTRL5_TPCTL                      0x0000
    #define     B16MoltresReg_CTRL5_TPCTL                      0x0000
    #define   LSb32MoltresReg_CTRL5_TPCTL                         5
    #define   LSb16MoltresReg_CTRL5_TPCTL                         5
    #define       bMoltresReg_CTRL5_TPCTL                      1
    #define   MSK32MoltresReg_CTRL5_TPCTL                         0x00000020

    #define     BA_MoltresReg_CTRL5_TPMAXDATASIZE              0x0000
    #define     B16MoltresReg_CTRL5_TPMAXDATASIZE              0x0000
    #define   LSb32MoltresReg_CTRL5_TPMAXDATASIZE                 6
    #define   LSb16MoltresReg_CTRL5_TPMAXDATASIZE                 6
    #define       bMoltresReg_CTRL5_TPMAXDATASIZE              5
    #define   MSK32MoltresReg_CTRL5_TPMAXDATASIZE                 0x000007C0

    #define     BA_MoltresReg_CTRL5_DEVICEEN                   0x0001
    #define     B16MoltresReg_CTRL5_DEVICEEN                   0x0000
    #define   LSb32MoltresReg_CTRL5_DEVICEEN                      11
    #define   LSb16MoltresReg_CTRL5_DEVICEEN                      11
    #define       bMoltresReg_CTRL5_DEVICEEN                   1
    #define   MSK32MoltresReg_CTRL5_DEVICEEN                      0x00000800
    ///////////////////////////////////////////////////////////
    #define     RA_MoltresReg_SoftResetn                       0x0004

    #define     BA_MoltresReg_SoftResetn_CPUAxi                0x0004
    #define     B16MoltresReg_SoftResetn_CPUAxi                0x0004
    #define   LSb32MoltresReg_SoftResetn_CPUAxi                   0
    #define   LSb16MoltresReg_SoftResetn_CPUAxi                   0
    #define       bMoltresReg_SoftResetn_CPUAxi                1
    #define   MSK32MoltresReg_SoftResetn_CPUAxi                   0x00000001

    #define     BA_MoltresReg_SoftResetn_MpSubSys              0x0004
    #define     B16MoltresReg_SoftResetn_MpSubSys              0x0004
    #define   LSb32MoltresReg_SoftResetn_MpSubSys                 1
    #define   LSb16MoltresReg_SoftResetn_MpSubSys                 1
    #define       bMoltresReg_SoftResetn_MpSubSys              1
    #define   MSK32MoltresReg_SoftResetn_MpSubSys                 0x00000002

    #define     BA_MoltresReg_SoftResetn_CoreSight             0x0004
    #define     B16MoltresReg_SoftResetn_CoreSight             0x0004
    #define   LSb32MoltresReg_SoftResetn_CoreSight                2
    #define   LSb16MoltresReg_SoftResetn_CoreSight                2
    #define       bMoltresReg_SoftResetn_CoreSight             1
    #define   MSK32MoltresReg_SoftResetn_CoreSight                0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_MoltresReg_sysIntPol                        0x0008

    #define     BA_MoltresReg_sysIntPol_invert                 0x0008
    #define     B16MoltresReg_sysIntPol_invert                 0x0008
    #define   LSb32MoltresReg_sysIntPol_invert                    0
    #define   LSb16MoltresReg_sysIntPol_invert                    0
    #define       bMoltresReg_sysIntPol_invert                 32
    #define   MSK32MoltresReg_sysIntPol_invert                    0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_MoltresReg {
    ///////////////////////////////////////////////////////////
    #define   GET32MoltresReg_CTRL5_dbgen(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32MoltresReg_CTRL5_dbgen(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16MoltresReg_CTRL5_dbgen(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16MoltresReg_CTRL5_dbgen(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32MoltresReg_CTRL5_spiden(r32)                _BFGET_(r32, 1, 1)
    #define   SET32MoltresReg_CTRL5_spiden(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16MoltresReg_CTRL5_spiden(r16)                _BFGET_(r16, 1, 1)
    #define   SET16MoltresReg_CTRL5_spiden(r16,v)              _BFSET_(r16, 1, 1,v)

    #define   GET32MoltresReg_CTRL5_niden(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32MoltresReg_CTRL5_niden(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16MoltresReg_CTRL5_niden(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16MoltresReg_CTRL5_niden(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32MoltresReg_CTRL5_spniden(r32)               _BFGET_(r32, 3, 3)
    #define   SET32MoltresReg_CTRL5_spniden(r32,v)             _BFSET_(r32, 3, 3,v)
    #define   GET16MoltresReg_CTRL5_spniden(r16)               _BFGET_(r16, 3, 3)
    #define   SET16MoltresReg_CTRL5_spniden(r16,v)             _BFSET_(r16, 3, 3,v)

    #define   GET32MoltresReg_CTRL5_dbgrq(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32MoltresReg_CTRL5_dbgrq(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16MoltresReg_CTRL5_dbgrq(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16MoltresReg_CTRL5_dbgrq(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32MoltresReg_CTRL5_TPCTL(r32)                 _BFGET_(r32, 5, 5)
    #define   SET32MoltresReg_CTRL5_TPCTL(r32,v)               _BFSET_(r32, 5, 5,v)
    #define   GET16MoltresReg_CTRL5_TPCTL(r16)                 _BFGET_(r16, 5, 5)
    #define   SET16MoltresReg_CTRL5_TPCTL(r16,v)               _BFSET_(r16, 5, 5,v)

    #define   GET32MoltresReg_CTRL5_TPMAXDATASIZE(r32)         _BFGET_(r32,10, 6)
    #define   SET32MoltresReg_CTRL5_TPMAXDATASIZE(r32,v)       _BFSET_(r32,10, 6,v)
    #define   GET16MoltresReg_CTRL5_TPMAXDATASIZE(r16)         _BFGET_(r16,10, 6)
    #define   SET16MoltresReg_CTRL5_TPMAXDATASIZE(r16,v)       _BFSET_(r16,10, 6,v)

    #define   GET32MoltresReg_CTRL5_DEVICEEN(r32)              _BFGET_(r32,11,11)
    #define   SET32MoltresReg_CTRL5_DEVICEEN(r32,v)            _BFSET_(r32,11,11,v)
    #define   GET16MoltresReg_CTRL5_DEVICEEN(r16)              _BFGET_(r16,11,11)
    #define   SET16MoltresReg_CTRL5_DEVICEEN(r16,v)            _BFSET_(r16,11,11,v)

    #define     w32MoltresReg_CTRL5                            {\
            UNSG32 uCTRL5_dbgen                                :  1;\
            UNSG32 uCTRL5_spiden                               :  1;\
            UNSG32 uCTRL5_niden                                :  1;\
            UNSG32 uCTRL5_spniden                              :  1;\
            UNSG32 uCTRL5_dbgrq                                :  1;\
            UNSG32 uCTRL5_TPCTL                                :  1;\
            UNSG32 uCTRL5_TPMAXDATASIZE                        :  5;\
            UNSG32 uCTRL5_DEVICEEN                             :  1;\
            UNSG32 RSVDx0_b12                                  : 20;\
          }
    union { UNSG32 u32MoltresReg_CTRL5;
            struct w32MoltresReg_CTRL5;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MoltresReg_SoftResetn_CPUAxi(r32)           _BFGET_(r32, 0, 0)
    #define   SET32MoltresReg_SoftResetn_CPUAxi(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16MoltresReg_SoftResetn_CPUAxi(r16)           _BFGET_(r16, 0, 0)
    #define   SET16MoltresReg_SoftResetn_CPUAxi(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32MoltresReg_SoftResetn_MpSubSys(r32)         _BFGET_(r32, 1, 1)
    #define   SET32MoltresReg_SoftResetn_MpSubSys(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16MoltresReg_SoftResetn_MpSubSys(r16)         _BFGET_(r16, 1, 1)
    #define   SET16MoltresReg_SoftResetn_MpSubSys(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32MoltresReg_SoftResetn_CoreSight(r32)        _BFGET_(r32, 2, 2)
    #define   SET32MoltresReg_SoftResetn_CoreSight(r32,v)      _BFSET_(r32, 2, 2,v)
    #define   GET16MoltresReg_SoftResetn_CoreSight(r16)        _BFGET_(r16, 2, 2)
    #define   SET16MoltresReg_SoftResetn_CoreSight(r16,v)      _BFSET_(r16, 2, 2,v)

    #define     w32MoltresReg_SoftResetn                       {\
            UNSG32 uSoftResetn_CPUAxi                          :  1;\
            UNSG32 uSoftResetn_MpSubSys                        :  1;\
            UNSG32 uSoftResetn_CoreSight                       :  1;\
            UNSG32 RSVDx4_b3                                   : 29;\
          }
    union { UNSG32 u32MoltresReg_SoftResetn;
            struct w32MoltresReg_SoftResetn;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32MoltresReg_sysIntPol_invert(r32)            _BFGET_(r32,31, 0)
    #define   SET32MoltresReg_sysIntPol_invert(r32,v)          _BFSET_(r32,31, 0,v)

    #define     w32MoltresReg_sysIntPol                        {\
            UNSG32 usysIntPol_invert                           : 32;\
          }
    union { UNSG32 u32MoltresReg_sysIntPol;
            struct w32MoltresReg_sysIntPol;
          };
    ///////////////////////////////////////////////////////////
    } SIE_MoltresReg;

    typedef union  T32MoltresReg_CTRL5
          { UNSG32 u32;
            struct w32MoltresReg_CTRL5;
                 } T32MoltresReg_CTRL5;
    typedef union  T32MoltresReg_SoftResetn
          { UNSG32 u32;
            struct w32MoltresReg_SoftResetn;
                 } T32MoltresReg_SoftResetn;
    typedef union  T32MoltresReg_sysIntPol
          { UNSG32 u32;
            struct w32MoltresReg_sysIntPol;
                 } T32MoltresReg_sysIntPol;
    ///////////////////////////////////////////////////////////

    typedef union  TMoltresReg_CTRL5
          { UNSG32 u32[1];
            struct {
            struct w32MoltresReg_CTRL5;
                   };
                 } TMoltresReg_CTRL5;
    typedef union  TMoltresReg_SoftResetn
          { UNSG32 u32[1];
            struct {
            struct w32MoltresReg_SoftResetn;
                   };
                 } TMoltresReg_SoftResetn;
    typedef union  TMoltresReg_sysIntPol
          { UNSG32 u32[1];
            struct {
            struct w32MoltresReg_sysIntPol;
                   };
                 } TMoltresReg_sysIntPol;

    ///////////////////////////////////////////////////////////
     SIGN32 MoltresReg_drvrd(SIE_MoltresReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 MoltresReg_drvwr(SIE_MoltresReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void MoltresReg_reset(SIE_MoltresReg *p);
     SIGN32 MoltresReg_cmp  (SIE_MoltresReg *p, SIE_MoltresReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define MoltresReg_check(p,pie,pfx,hLOG) MoltresReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define MoltresReg_print(p,    pfx,hLOG) MoltresReg_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: MoltresReg
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE IDReg                   biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P)
///               ###
///               * ID to {AxUSER, AxCACHE} mapping. Transaction is routed to IOB if (AxUSER | AxCACHE[1]) is true.
///               ###
///               %unsigned 4  AWCAHE                    0x0
///                                    ###
///                                    * AWCAHE corresponding to this ID.
///                                    ###
///               %unsigned 1  AWUSER                    0x0
///                                    ###
///                                    * AWUSER corresponding to this ID.
///                                    ###
///               %unsigned 4  ARCAHE                    0x0
///                                    ###
///                                    * ARCAHE corresponding to this ID.
///                                    ###
///               %unsigned 1  ARUSER                    0x0
///                                    ###
///                                    * ARUSER corresponding to this ID.
///                                    ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      10b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_IDReg
#define h_IDReg (){}

    #define     RA_IDReg_CTRL                                  0x0000

    #define     BA_IDReg_CTRL_AWCAHE                           0x0000
    #define     B16IDReg_CTRL_AWCAHE                           0x0000
    #define   LSb32IDReg_CTRL_AWCAHE                              0
    #define   LSb16IDReg_CTRL_AWCAHE                              0
    #define       bIDReg_CTRL_AWCAHE                           4
    #define   MSK32IDReg_CTRL_AWCAHE                              0x0000000F

    #define     BA_IDReg_CTRL_AWUSER                           0x0000
    #define     B16IDReg_CTRL_AWUSER                           0x0000
    #define   LSb32IDReg_CTRL_AWUSER                              4
    #define   LSb16IDReg_CTRL_AWUSER                              4
    #define       bIDReg_CTRL_AWUSER                           1
    #define   MSK32IDReg_CTRL_AWUSER                              0x00000010

    #define     BA_IDReg_CTRL_ARCAHE                           0x0000
    #define     B16IDReg_CTRL_ARCAHE                           0x0000
    #define   LSb32IDReg_CTRL_ARCAHE                              5
    #define   LSb16IDReg_CTRL_ARCAHE                              5
    #define       bIDReg_CTRL_ARCAHE                           4
    #define   MSK32IDReg_CTRL_ARCAHE                              0x000001E0

    #define     BA_IDReg_CTRL_ARUSER                           0x0001
    #define     B16IDReg_CTRL_ARUSER                           0x0000
    #define   LSb32IDReg_CTRL_ARUSER                              9
    #define   LSb16IDReg_CTRL_ARUSER                              9
    #define       bIDReg_CTRL_ARUSER                           1
    #define   MSK32IDReg_CTRL_ARUSER                              0x00000200
    ///////////////////////////////////////////////////////////

    typedef struct SIE_IDReg {
    ///////////////////////////////////////////////////////////
    #define   GET32IDReg_CTRL_AWCAHE(r32)                      _BFGET_(r32, 3, 0)
    #define   SET32IDReg_CTRL_AWCAHE(r32,v)                    _BFSET_(r32, 3, 0,v)
    #define   GET16IDReg_CTRL_AWCAHE(r16)                      _BFGET_(r16, 3, 0)
    #define   SET16IDReg_CTRL_AWCAHE(r16,v)                    _BFSET_(r16, 3, 0,v)

    #define   GET32IDReg_CTRL_AWUSER(r32)                      _BFGET_(r32, 4, 4)
    #define   SET32IDReg_CTRL_AWUSER(r32,v)                    _BFSET_(r32, 4, 4,v)
    #define   GET16IDReg_CTRL_AWUSER(r16)                      _BFGET_(r16, 4, 4)
    #define   SET16IDReg_CTRL_AWUSER(r16,v)                    _BFSET_(r16, 4, 4,v)

    #define   GET32IDReg_CTRL_ARCAHE(r32)                      _BFGET_(r32, 8, 5)
    #define   SET32IDReg_CTRL_ARCAHE(r32,v)                    _BFSET_(r32, 8, 5,v)
    #define   GET16IDReg_CTRL_ARCAHE(r16)                      _BFGET_(r16, 8, 5)
    #define   SET16IDReg_CTRL_ARCAHE(r16,v)                    _BFSET_(r16, 8, 5,v)

    #define   GET32IDReg_CTRL_ARUSER(r32)                      _BFGET_(r32, 9, 9)
    #define   SET32IDReg_CTRL_ARUSER(r32,v)                    _BFSET_(r32, 9, 9,v)
    #define   GET16IDReg_CTRL_ARUSER(r16)                      _BFGET_(r16, 9, 9)
    #define   SET16IDReg_CTRL_ARUSER(r16,v)                    _BFSET_(r16, 9, 9,v)

    #define     w32IDReg_CTRL                                  {\
            UNSG32 uCTRL_AWCAHE                                :  4;\
            UNSG32 uCTRL_AWUSER                                :  1;\
            UNSG32 uCTRL_ARCAHE                                :  4;\
            UNSG32 uCTRL_ARUSER                                :  1;\
            UNSG32 RSVDx0_b10                                  : 22;\
          }
    union { UNSG32 u32IDReg_CTRL;
            struct w32IDReg_CTRL;
          };
    ///////////////////////////////////////////////////////////
    } SIE_IDReg;

    typedef union  T32IDReg_CTRL
          { UNSG32 u32;
            struct w32IDReg_CTRL;
                 } T32IDReg_CTRL;
    ///////////////////////////////////////////////////////////

    typedef union  TIDReg_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32IDReg_CTRL;
                   };
                 } TIDReg_CTRL;

    ///////////////////////////////////////////////////////////
     SIGN32 IDReg_drvrd(SIE_IDReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 IDReg_drvwr(SIE_IDReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void IDReg_reset(SIE_IDReg *p);
     SIGN32 IDReg_cmp  (SIE_IDReg *p, SIE_IDReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define IDReg_check(p,pie,pfx,hLOG) IDReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define IDReg_print(p,    pfx,hLOG) IDReg_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: IDReg
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxiErrorMon                              (4,4)
///     ###
///     * AXI Bus Error Response Monitor
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 WriteID              (R-)
///               %unsigned 32 berrID                    0x0
///                                    ###
///                                    * ID of AXI Write Transaction that caused an error response
///                                    ###
///     @ 0x00004 WriteStat            (R-)
///               %unsigned 1  berrType                  0x0
///                                    ###
///                                    * Error Response Type
///                                    * 0: SLVERR
///                                    * 1: DECERR
///                                    ###
///               %unsigned 1  berrValid                 0x0
///                                    ###
///                                    * When asserted, an error response is detected and the information are captured into berrID and berrType.
///                                    * Monitoring is stopped
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00008 WriteCtrl            (RW)
///               %unsigned 1  berrClear                 0x0
///                                    ###
///                                    * Writing 1 will clear berrValid and resume the monitoring.
///                                    * This bit self clears.
///                                    ###
///               %unsigned 1  berrIntrEn                0x0
///                                    ###
///                                    * 1: Monitor generates an active high interrupt when berrValid = 1
///                                    * 0: Interrupt is masked.
///                                    * Note: To clear interrupt, write 1 to berrClear
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x0000C ReadID               (R-)
///               %unsigned 32 rerrID                    0x0
///                                    ###
///                                    * ID of AXI Read Transaction that caused an error response
///                                    ###
///     @ 0x00010 ReadStat             (R-)
///               %unsigned 1  rerrType                  0x0
///                                    ###
///                                    * Error Response Type
///                                    * 0: SLVERR
///                                    * 1: DECERR
///                                    ###
///               %unsigned 1  rerrValid                 0x0
///                                    ###
///                                    * When asserted, an error response is detected and the information are captured into rerrID and rerrType.
///                                    * Monitoring is stopped
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00014 ReadCtrl             (RW)
///               %unsigned 1  rerrClear                 0x0
///                                    ###
///                                    * Writing 1 will clear rerrValid and resume the monitoring.
///                                    * This bit self clears.
///                                    ###
///               %unsigned 1  rerrIntrEn                0x0
///                                    ###
///                                    * 1: Monitor generates an active high interrupt when berrValid = 1
///                                    * 0: Interrupt is masked.
///                                    * Note: To clear interrupt, write 1 to berrClear
///                                    ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:      72b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxiErrorMon
#define h_AxiErrorMon (){}

    #define     RA_AxiErrorMon_WriteID                         0x0000

    #define     BA_AxiErrorMon_WriteID_berrID                  0x0000
    #define     B16AxiErrorMon_WriteID_berrID                  0x0000
    #define   LSb32AxiErrorMon_WriteID_berrID                     0
    #define   LSb16AxiErrorMon_WriteID_berrID                     0
    #define       bAxiErrorMon_WriteID_berrID                  32
    #define   MSK32AxiErrorMon_WriteID_berrID                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_WriteStat                       0x0004

    #define     BA_AxiErrorMon_WriteStat_berrType              0x0004
    #define     B16AxiErrorMon_WriteStat_berrType              0x0004
    #define   LSb32AxiErrorMon_WriteStat_berrType                 0
    #define   LSb16AxiErrorMon_WriteStat_berrType                 0
    #define       bAxiErrorMon_WriteStat_berrType              1
    #define   MSK32AxiErrorMon_WriteStat_berrType                 0x00000001

    #define     BA_AxiErrorMon_WriteStat_berrValid             0x0004
    #define     B16AxiErrorMon_WriteStat_berrValid             0x0004
    #define   LSb32AxiErrorMon_WriteStat_berrValid                1
    #define   LSb16AxiErrorMon_WriteStat_berrValid                1
    #define       bAxiErrorMon_WriteStat_berrValid             1
    #define   MSK32AxiErrorMon_WriteStat_berrValid                0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_WriteCtrl                       0x0008

    #define     BA_AxiErrorMon_WriteCtrl_berrClear             0x0008
    #define     B16AxiErrorMon_WriteCtrl_berrClear             0x0008
    #define   LSb32AxiErrorMon_WriteCtrl_berrClear                0
    #define   LSb16AxiErrorMon_WriteCtrl_berrClear                0
    #define       bAxiErrorMon_WriteCtrl_berrClear             1
    #define   MSK32AxiErrorMon_WriteCtrl_berrClear                0x00000001

    #define     BA_AxiErrorMon_WriteCtrl_berrIntrEn            0x0008
    #define     B16AxiErrorMon_WriteCtrl_berrIntrEn            0x0008
    #define   LSb32AxiErrorMon_WriteCtrl_berrIntrEn               1
    #define   LSb16AxiErrorMon_WriteCtrl_berrIntrEn               1
    #define       bAxiErrorMon_WriteCtrl_berrIntrEn            1
    #define   MSK32AxiErrorMon_WriteCtrl_berrIntrEn               0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_ReadID                          0x000C

    #define     BA_AxiErrorMon_ReadID_rerrID                   0x000C
    #define     B16AxiErrorMon_ReadID_rerrID                   0x000C
    #define   LSb32AxiErrorMon_ReadID_rerrID                      0
    #define   LSb16AxiErrorMon_ReadID_rerrID                      0
    #define       bAxiErrorMon_ReadID_rerrID                   32
    #define   MSK32AxiErrorMon_ReadID_rerrID                      0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_ReadStat                        0x0010

    #define     BA_AxiErrorMon_ReadStat_rerrType               0x0010
    #define     B16AxiErrorMon_ReadStat_rerrType               0x0010
    #define   LSb32AxiErrorMon_ReadStat_rerrType                  0
    #define   LSb16AxiErrorMon_ReadStat_rerrType                  0
    #define       bAxiErrorMon_ReadStat_rerrType               1
    #define   MSK32AxiErrorMon_ReadStat_rerrType                  0x00000001

    #define     BA_AxiErrorMon_ReadStat_rerrValid              0x0010
    #define     B16AxiErrorMon_ReadStat_rerrValid              0x0010
    #define   LSb32AxiErrorMon_ReadStat_rerrValid                 1
    #define   LSb16AxiErrorMon_ReadStat_rerrValid                 1
    #define       bAxiErrorMon_ReadStat_rerrValid              1
    #define   MSK32AxiErrorMon_ReadStat_rerrValid                 0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiErrorMon_ReadCtrl                        0x0014

    #define     BA_AxiErrorMon_ReadCtrl_rerrClear              0x0014
    #define     B16AxiErrorMon_ReadCtrl_rerrClear              0x0014
    #define   LSb32AxiErrorMon_ReadCtrl_rerrClear                 0
    #define   LSb16AxiErrorMon_ReadCtrl_rerrClear                 0
    #define       bAxiErrorMon_ReadCtrl_rerrClear              1
    #define   MSK32AxiErrorMon_ReadCtrl_rerrClear                 0x00000001

    #define     BA_AxiErrorMon_ReadCtrl_rerrIntrEn             0x0014
    #define     B16AxiErrorMon_ReadCtrl_rerrIntrEn             0x0014
    #define   LSb32AxiErrorMon_ReadCtrl_rerrIntrEn                1
    #define   LSb16AxiErrorMon_ReadCtrl_rerrIntrEn                1
    #define       bAxiErrorMon_ReadCtrl_rerrIntrEn             1
    #define   MSK32AxiErrorMon_ReadCtrl_rerrIntrEn                0x00000002
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxiErrorMon {
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_WriteID_berrID(r32)             _BFGET_(r32,31, 0)
    #define   SET32AxiErrorMon_WriteID_berrID(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32AxiErrorMon_WriteID                         {\
            UNSG32 uWriteID_berrID                             : 32;\
          }
    union { UNSG32 u32AxiErrorMon_WriteID;
            struct w32AxiErrorMon_WriteID;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_WriteStat_berrType(r32)         _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_WriteStat_berrType(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_WriteStat_berrType(r16)         _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_WriteStat_berrType(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_WriteStat_berrValid(r32)        _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_WriteStat_berrValid(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_WriteStat_berrValid(r16)        _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_WriteStat_berrValid(r16,v)      _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_WriteStat                       {\
            UNSG32 uWriteStat_berrType                         :  1;\
            UNSG32 uWriteStat_berrValid                        :  1;\
            UNSG32 RSVDx4_b2                                   : 30;\
          }
    union { UNSG32 u32AxiErrorMon_WriteStat;
            struct w32AxiErrorMon_WriteStat;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_WriteCtrl_berrClear(r32)        _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_WriteCtrl_berrClear(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_WriteCtrl_berrClear(r16)        _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_WriteCtrl_berrClear(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_WriteCtrl_berrIntrEn(r32)       _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_WriteCtrl_berrIntrEn(r32,v)     _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_WriteCtrl_berrIntrEn(r16)       _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_WriteCtrl_berrIntrEn(r16,v)     _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_WriteCtrl                       {\
            UNSG32 uWriteCtrl_berrClear                        :  1;\
            UNSG32 uWriteCtrl_berrIntrEn                       :  1;\
            UNSG32 RSVDx8_b2                                   : 30;\
          }
    union { UNSG32 u32AxiErrorMon_WriteCtrl;
            struct w32AxiErrorMon_WriteCtrl;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_ReadID_rerrID(r32)              _BFGET_(r32,31, 0)
    #define   SET32AxiErrorMon_ReadID_rerrID(r32,v)            _BFSET_(r32,31, 0,v)

    #define     w32AxiErrorMon_ReadID                          {\
            UNSG32 uReadID_rerrID                              : 32;\
          }
    union { UNSG32 u32AxiErrorMon_ReadID;
            struct w32AxiErrorMon_ReadID;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_ReadStat_rerrType(r32)          _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_ReadStat_rerrType(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_ReadStat_rerrType(r16)          _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_ReadStat_rerrType(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_ReadStat_rerrValid(r32)         _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_ReadStat_rerrValid(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_ReadStat_rerrValid(r16)         _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_ReadStat_rerrValid(r16,v)       _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_ReadStat                        {\
            UNSG32 uReadStat_rerrType                          :  1;\
            UNSG32 uReadStat_rerrValid                         :  1;\
            UNSG32 RSVDx10_b2                                  : 30;\
          }
    union { UNSG32 u32AxiErrorMon_ReadStat;
            struct w32AxiErrorMon_ReadStat;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiErrorMon_ReadCtrl_rerrClear(r32)         _BFGET_(r32, 0, 0)
    #define   SET32AxiErrorMon_ReadCtrl_rerrClear(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16AxiErrorMon_ReadCtrl_rerrClear(r16)         _BFGET_(r16, 0, 0)
    #define   SET16AxiErrorMon_ReadCtrl_rerrClear(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32AxiErrorMon_ReadCtrl_rerrIntrEn(r32)        _BFGET_(r32, 1, 1)
    #define   SET32AxiErrorMon_ReadCtrl_rerrIntrEn(r32,v)      _BFSET_(r32, 1, 1,v)
    #define   GET16AxiErrorMon_ReadCtrl_rerrIntrEn(r16)        _BFGET_(r16, 1, 1)
    #define   SET16AxiErrorMon_ReadCtrl_rerrIntrEn(r16,v)      _BFSET_(r16, 1, 1,v)

    #define     w32AxiErrorMon_ReadCtrl                        {\
            UNSG32 uReadCtrl_rerrClear                         :  1;\
            UNSG32 uReadCtrl_rerrIntrEn                        :  1;\
            UNSG32 RSVDx14_b2                                  : 30;\
          }
    union { UNSG32 u32AxiErrorMon_ReadCtrl;
            struct w32AxiErrorMon_ReadCtrl;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxiErrorMon;

    typedef union  T32AxiErrorMon_WriteID
          { UNSG32 u32;
            struct w32AxiErrorMon_WriteID;
                 } T32AxiErrorMon_WriteID;
    typedef union  T32AxiErrorMon_WriteStat
          { UNSG32 u32;
            struct w32AxiErrorMon_WriteStat;
                 } T32AxiErrorMon_WriteStat;
    typedef union  T32AxiErrorMon_WriteCtrl
          { UNSG32 u32;
            struct w32AxiErrorMon_WriteCtrl;
                 } T32AxiErrorMon_WriteCtrl;
    typedef union  T32AxiErrorMon_ReadID
          { UNSG32 u32;
            struct w32AxiErrorMon_ReadID;
                 } T32AxiErrorMon_ReadID;
    typedef union  T32AxiErrorMon_ReadStat
          { UNSG32 u32;
            struct w32AxiErrorMon_ReadStat;
                 } T32AxiErrorMon_ReadStat;
    typedef union  T32AxiErrorMon_ReadCtrl
          { UNSG32 u32;
            struct w32AxiErrorMon_ReadCtrl;
                 } T32AxiErrorMon_ReadCtrl;
    ///////////////////////////////////////////////////////////

    typedef union  TAxiErrorMon_WriteID
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_WriteID;
                   };
                 } TAxiErrorMon_WriteID;
    typedef union  TAxiErrorMon_WriteStat
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_WriteStat;
                   };
                 } TAxiErrorMon_WriteStat;
    typedef union  TAxiErrorMon_WriteCtrl
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_WriteCtrl;
                   };
                 } TAxiErrorMon_WriteCtrl;
    typedef union  TAxiErrorMon_ReadID
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_ReadID;
                   };
                 } TAxiErrorMon_ReadID;
    typedef union  TAxiErrorMon_ReadStat
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_ReadStat;
                   };
                 } TAxiErrorMon_ReadStat;
    typedef union  TAxiErrorMon_ReadCtrl
          { UNSG32 u32[1];
            struct {
            struct w32AxiErrorMon_ReadCtrl;
                   };
                 } TAxiErrorMon_ReadCtrl;

    ///////////////////////////////////////////////////////////
     SIGN32 AxiErrorMon_drvrd(SIE_AxiErrorMon *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxiErrorMon_drvwr(SIE_AxiErrorMon *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxiErrorMon_reset(SIE_AxiErrorMon *p);
     SIGN32 AxiErrorMon_cmp  (SIE_AxiErrorMon *p, SIE_AxiErrorMon *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxiErrorMon_check(p,pie,pfx,hLOG) AxiErrorMon_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxiErrorMon_print(p,    pfx,hLOG) AxiErrorMon_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxiErrorMon
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE seSettingX                               (4,4)
///     ###
///     * Config Space Secure Region Registers
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P-)
///               %unsigned 1  seW                       0x0
///                                    ###
///                                    * 1: Only Secure Masters can write to this region
///                                    * 0: Any masters can write to this region
///                                    * (P)
///                                    ###
///               %unsigned 1  seR                       0x0
///                                    ###
///                                    * 1: Only Secure Masters can read from this region
///                                    * 0: Any masters can read from this region
///                                    * In combination with seW the access to the region is fully secure if seW and seR are 1 and non-secure when seW and seR are 0
///                                    * (P)
///                                    ###
///               %unsigned 1  rzW                       0x0
///                                    ###
///                                    * 1: Only RZ Masters can write to this region
///                                    * 0: Perform seW check
///                                    * (P)
///                                    ###
///               %unsigned 1  rzR                       0x0
///                                    ###
///                                    * 1: Only RZ Masters can write to this region
///                                    * 0: Perform seR check
///                                    * (P)
///                                    ###
///               %unsigned 1  Lock                      0x0
///                                    ###
///                                    * When Lock=1 it blocks writes to secure region registers. Once set it cannot be changed until reset.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00004 seStart              (P)
///               %unsigned 32 seStart                   0x0
///                                    ###
///                                    * Base or Start address of the region
///                                    * Bits [1:0] unused.
///                                    ###
///     @ 0x00008 seEnd                (P)
///               %unsigned 32 seEnd                     0x0
///                                    ###
///                                    * Used in conjunction with seBase to define region size
///                                    * Bits [1:0] unused
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      12B, bits:      69b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_seSettingX
#define h_seSettingX (){}

    #define     RA_seSettingX_CTRL                             0x0000

    #define     BA_seSettingX_CTRL_seW                         0x0000
    #define     B16seSettingX_CTRL_seW                         0x0000
    #define   LSb32seSettingX_CTRL_seW                            0
    #define   LSb16seSettingX_CTRL_seW                            0
    #define       bseSettingX_CTRL_seW                         1
    #define   MSK32seSettingX_CTRL_seW                            0x00000001

    #define     BA_seSettingX_CTRL_seR                         0x0000
    #define     B16seSettingX_CTRL_seR                         0x0000
    #define   LSb32seSettingX_CTRL_seR                            1
    #define   LSb16seSettingX_CTRL_seR                            1
    #define       bseSettingX_CTRL_seR                         1
    #define   MSK32seSettingX_CTRL_seR                            0x00000002

    #define     BA_seSettingX_CTRL_rzW                         0x0000
    #define     B16seSettingX_CTRL_rzW                         0x0000
    #define   LSb32seSettingX_CTRL_rzW                            2
    #define   LSb16seSettingX_CTRL_rzW                            2
    #define       bseSettingX_CTRL_rzW                         1
    #define   MSK32seSettingX_CTRL_rzW                            0x00000004

    #define     BA_seSettingX_CTRL_rzR                         0x0000
    #define     B16seSettingX_CTRL_rzR                         0x0000
    #define   LSb32seSettingX_CTRL_rzR                            3
    #define   LSb16seSettingX_CTRL_rzR                            3
    #define       bseSettingX_CTRL_rzR                         1
    #define   MSK32seSettingX_CTRL_rzR                            0x00000008

    #define     BA_seSettingX_CTRL_Lock                        0x0000
    #define     B16seSettingX_CTRL_Lock                        0x0000
    #define   LSb32seSettingX_CTRL_Lock                           4
    #define   LSb16seSettingX_CTRL_Lock                           4
    #define       bseSettingX_CTRL_Lock                        1
    #define   MSK32seSettingX_CTRL_Lock                           0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_seSettingX_seStart                          0x0004

    #define     BA_seSettingX_seStart_seStart                  0x0004
    #define     B16seSettingX_seStart_seStart                  0x0004
    #define   LSb32seSettingX_seStart_seStart                     0
    #define   LSb16seSettingX_seStart_seStart                     0
    #define       bseSettingX_seStart_seStart                  32
    #define   MSK32seSettingX_seStart_seStart                     0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_seSettingX_seEnd                            0x0008

    #define     BA_seSettingX_seEnd_seEnd                      0x0008
    #define     B16seSettingX_seEnd_seEnd                      0x0008
    #define   LSb32seSettingX_seEnd_seEnd                         0
    #define   LSb16seSettingX_seEnd_seEnd                         0
    #define       bseSettingX_seEnd_seEnd                      32
    #define   MSK32seSettingX_seEnd_seEnd                         0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_seSettingX {
    ///////////////////////////////////////////////////////////
    #define   GET32seSettingX_CTRL_seW(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32seSettingX_CTRL_seW(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16seSettingX_CTRL_seW(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16seSettingX_CTRL_seW(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32seSettingX_CTRL_seR(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32seSettingX_CTRL_seR(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16seSettingX_CTRL_seR(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16seSettingX_CTRL_seR(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define   GET32seSettingX_CTRL_rzW(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32seSettingX_CTRL_rzW(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16seSettingX_CTRL_rzW(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16seSettingX_CTRL_rzW(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define   GET32seSettingX_CTRL_rzR(r32)                    _BFGET_(r32, 3, 3)
    #define   SET32seSettingX_CTRL_rzR(r32,v)                  _BFSET_(r32, 3, 3,v)
    #define   GET16seSettingX_CTRL_rzR(r16)                    _BFGET_(r16, 3, 3)
    #define   SET16seSettingX_CTRL_rzR(r16,v)                  _BFSET_(r16, 3, 3,v)

    #define   GET32seSettingX_CTRL_Lock(r32)                   _BFGET_(r32, 4, 4)
    #define   SET32seSettingX_CTRL_Lock(r32,v)                 _BFSET_(r32, 4, 4,v)
    #define   GET16seSettingX_CTRL_Lock(r16)                   _BFGET_(r16, 4, 4)
    #define   SET16seSettingX_CTRL_Lock(r16,v)                 _BFSET_(r16, 4, 4,v)

    #define     w32seSettingX_CTRL                             {\
            UNSG32 uCTRL_seW                                   :  1;\
            UNSG32 uCTRL_seR                                   :  1;\
            UNSG32 uCTRL_rzW                                   :  1;\
            UNSG32 uCTRL_rzR                                   :  1;\
            UNSG32 uCTRL_Lock                                  :  1;\
            UNSG32 RSVDx0_b5                                   : 27;\
          }
    union { UNSG32 u32seSettingX_CTRL;
            struct w32seSettingX_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32seSettingX_seStart_seStart(r32)             _BFGET_(r32,31, 0)
    #define   SET32seSettingX_seStart_seStart(r32,v)           _BFSET_(r32,31, 0,v)

    #define     w32seSettingX_seStart                          {\
            UNSG32 useStart_seStart                            : 32;\
          }
    union { UNSG32 u32seSettingX_seStart;
            struct w32seSettingX_seStart;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32seSettingX_seEnd_seEnd(r32)                 _BFGET_(r32,31, 0)
    #define   SET32seSettingX_seEnd_seEnd(r32,v)               _BFSET_(r32,31, 0,v)

    #define     w32seSettingX_seEnd                            {\
            UNSG32 useEnd_seEnd                                : 32;\
          }
    union { UNSG32 u32seSettingX_seEnd;
            struct w32seSettingX_seEnd;
          };
    ///////////////////////////////////////////////////////////
    } SIE_seSettingX;

    typedef union  T32seSettingX_CTRL
          { UNSG32 u32;
            struct w32seSettingX_CTRL;
                 } T32seSettingX_CTRL;
    typedef union  T32seSettingX_seStart
          { UNSG32 u32;
            struct w32seSettingX_seStart;
                 } T32seSettingX_seStart;
    typedef union  T32seSettingX_seEnd
          { UNSG32 u32;
            struct w32seSettingX_seEnd;
                 } T32seSettingX_seEnd;
    ///////////////////////////////////////////////////////////

    typedef union  TseSettingX_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32seSettingX_CTRL;
                   };
                 } TseSettingX_CTRL;
    typedef union  TseSettingX_seStart
          { UNSG32 u32[1];
            struct {
            struct w32seSettingX_seStart;
                   };
                 } TseSettingX_seStart;
    typedef union  TseSettingX_seEnd
          { UNSG32 u32[1];
            struct {
            struct w32seSettingX_seEnd;
                   };
                 } TseSettingX_seEnd;

    ///////////////////////////////////////////////////////////
     SIGN32 seSettingX_drvrd(SIE_seSettingX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 seSettingX_drvwr(SIE_seSettingX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void seSettingX_reset(SIE_seSettingX *p);
     SIGN32 seSettingX_cmp  (SIE_seSettingX *p, SIE_seSettingX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define seSettingX_check(p,pie,pfx,hLOG) seSettingX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define seSettingX_print(p,    pfx,hLOG) seSettingX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: seSettingX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE defSeRegionX                             (4,4)
///     ###
///     * Default Secure Region address range
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P-)
///               %unsigned 1  seW                       0x1
///                                    ###
///                                    * 1: Only Secure Masters can write to this region
///                                    * 0: Any masters can write to this region
///                                    * (P)
///                                    ###
///               %unsigned 1  seR                       0x1
///                                    ###
///                                    * 1: Only Secure Masters can read from this region
///                                    * 0: Any masters can read from this region
///                                    * In combination with seW the access to the region is fully secure if seW and seR are 1 and non-secure when seW and seR are 0
///                                    * (P)
///                                    ###
///               %unsigned 1  rzW                       0x0
///                                    ###
///                                    * 1: Only RZ Masters can write to this region
///                                    * 0: Perform seW check
///                                    * (P)
///                                    ###
///               %unsigned 1  rzR                       0x0
///                                    ###
///                                    * 1: Only RZ Masters can write to this region
///                                    * 0: Perform seR check
///                                    * (P)
///                                    ###
///               %unsigned 1  Lock                      0x0
///                                    ###
///                                    * When Lock=1 it blocks writes to secure region registers. Once set it cannot be changed until reset.
///                                    ###
///               %%        27         # Stuffing bits...
///     @ 0x00004 seStart              (P)
///               %unsigned 32 seStart                   0xF7CA1000
///                                    ###
///                                    * Base or Start address of the region
///                                    * Bits [1:0] unused.
///                                    ###
///     @ 0x00008 seEnd                (P)
///               %unsigned 32 seEnd                     0xF7CA1FFF
///                                    ###
///                                    * Used in conjunction with seBase to define region size
///                                    * Bits [1:0] unused
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      12B, bits:      69b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_defSeRegionX
#define h_defSeRegionX (){}

    #define     RA_defSeRegionX_CTRL                           0x0000

    #define     BA_defSeRegionX_CTRL_seW                       0x0000
    #define     B16defSeRegionX_CTRL_seW                       0x0000
    #define   LSb32defSeRegionX_CTRL_seW                          0
    #define   LSb16defSeRegionX_CTRL_seW                          0
    #define       bdefSeRegionX_CTRL_seW                       1
    #define   MSK32defSeRegionX_CTRL_seW                          0x00000001

    #define     BA_defSeRegionX_CTRL_seR                       0x0000
    #define     B16defSeRegionX_CTRL_seR                       0x0000
    #define   LSb32defSeRegionX_CTRL_seR                          1
    #define   LSb16defSeRegionX_CTRL_seR                          1
    #define       bdefSeRegionX_CTRL_seR                       1
    #define   MSK32defSeRegionX_CTRL_seR                          0x00000002

    #define     BA_defSeRegionX_CTRL_rzW                       0x0000
    #define     B16defSeRegionX_CTRL_rzW                       0x0000
    #define   LSb32defSeRegionX_CTRL_rzW                          2
    #define   LSb16defSeRegionX_CTRL_rzW                          2
    #define       bdefSeRegionX_CTRL_rzW                       1
    #define   MSK32defSeRegionX_CTRL_rzW                          0x00000004

    #define     BA_defSeRegionX_CTRL_rzR                       0x0000
    #define     B16defSeRegionX_CTRL_rzR                       0x0000
    #define   LSb32defSeRegionX_CTRL_rzR                          3
    #define   LSb16defSeRegionX_CTRL_rzR                          3
    #define       bdefSeRegionX_CTRL_rzR                       1
    #define   MSK32defSeRegionX_CTRL_rzR                          0x00000008

    #define     BA_defSeRegionX_CTRL_Lock                      0x0000
    #define     B16defSeRegionX_CTRL_Lock                      0x0000
    #define   LSb32defSeRegionX_CTRL_Lock                         4
    #define   LSb16defSeRegionX_CTRL_Lock                         4
    #define       bdefSeRegionX_CTRL_Lock                      1
    #define   MSK32defSeRegionX_CTRL_Lock                         0x00000010
    ///////////////////////////////////////////////////////////
    #define     RA_defSeRegionX_seStart                        0x0004

    #define     BA_defSeRegionX_seStart_seStart                0x0004
    #define     B16defSeRegionX_seStart_seStart                0x0004
    #define   LSb32defSeRegionX_seStart_seStart                   0
    #define   LSb16defSeRegionX_seStart_seStart                   0
    #define       bdefSeRegionX_seStart_seStart                32
    #define   MSK32defSeRegionX_seStart_seStart                   0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_defSeRegionX_seEnd                          0x0008

    #define     BA_defSeRegionX_seEnd_seEnd                    0x0008
    #define     B16defSeRegionX_seEnd_seEnd                    0x0008
    #define   LSb32defSeRegionX_seEnd_seEnd                       0
    #define   LSb16defSeRegionX_seEnd_seEnd                       0
    #define       bdefSeRegionX_seEnd_seEnd                    32
    #define   MSK32defSeRegionX_seEnd_seEnd                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_defSeRegionX {
    ///////////////////////////////////////////////////////////
    #define   GET32defSeRegionX_CTRL_seW(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32defSeRegionX_CTRL_seW(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16defSeRegionX_CTRL_seW(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16defSeRegionX_CTRL_seW(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32defSeRegionX_CTRL_seR(r32)                  _BFGET_(r32, 1, 1)
    #define   SET32defSeRegionX_CTRL_seR(r32,v)                _BFSET_(r32, 1, 1,v)
    #define   GET16defSeRegionX_CTRL_seR(r16)                  _BFGET_(r16, 1, 1)
    #define   SET16defSeRegionX_CTRL_seR(r16,v)                _BFSET_(r16, 1, 1,v)

    #define   GET32defSeRegionX_CTRL_rzW(r32)                  _BFGET_(r32, 2, 2)
    #define   SET32defSeRegionX_CTRL_rzW(r32,v)                _BFSET_(r32, 2, 2,v)
    #define   GET16defSeRegionX_CTRL_rzW(r16)                  _BFGET_(r16, 2, 2)
    #define   SET16defSeRegionX_CTRL_rzW(r16,v)                _BFSET_(r16, 2, 2,v)

    #define   GET32defSeRegionX_CTRL_rzR(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32defSeRegionX_CTRL_rzR(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16defSeRegionX_CTRL_rzR(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16defSeRegionX_CTRL_rzR(r16,v)                _BFSET_(r16, 3, 3,v)

    #define   GET32defSeRegionX_CTRL_Lock(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32defSeRegionX_CTRL_Lock(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16defSeRegionX_CTRL_Lock(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16defSeRegionX_CTRL_Lock(r16,v)               _BFSET_(r16, 4, 4,v)

    #define     w32defSeRegionX_CTRL                           {\
            UNSG32 uCTRL_seW                                   :  1;\
            UNSG32 uCTRL_seR                                   :  1;\
            UNSG32 uCTRL_rzW                                   :  1;\
            UNSG32 uCTRL_rzR                                   :  1;\
            UNSG32 uCTRL_Lock                                  :  1;\
            UNSG32 RSVDx0_b5                                   : 27;\
          }
    union { UNSG32 u32defSeRegionX_CTRL;
            struct w32defSeRegionX_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32defSeRegionX_seStart_seStart(r32)           _BFGET_(r32,31, 0)
    #define   SET32defSeRegionX_seStart_seStart(r32,v)         _BFSET_(r32,31, 0,v)

    #define     w32defSeRegionX_seStart                        {\
            UNSG32 useStart_seStart                            : 32;\
          }
    union { UNSG32 u32defSeRegionX_seStart;
            struct w32defSeRegionX_seStart;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32defSeRegionX_seEnd_seEnd(r32)               _BFGET_(r32,31, 0)
    #define   SET32defSeRegionX_seEnd_seEnd(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32defSeRegionX_seEnd                          {\
            UNSG32 useEnd_seEnd                                : 32;\
          }
    union { UNSG32 u32defSeRegionX_seEnd;
            struct w32defSeRegionX_seEnd;
          };
    ///////////////////////////////////////////////////////////
    } SIE_defSeRegionX;

    typedef union  T32defSeRegionX_CTRL
          { UNSG32 u32;
            struct w32defSeRegionX_CTRL;
                 } T32defSeRegionX_CTRL;
    typedef union  T32defSeRegionX_seStart
          { UNSG32 u32;
            struct w32defSeRegionX_seStart;
                 } T32defSeRegionX_seStart;
    typedef union  T32defSeRegionX_seEnd
          { UNSG32 u32;
            struct w32defSeRegionX_seEnd;
                 } T32defSeRegionX_seEnd;
    ///////////////////////////////////////////////////////////

    typedef union  TdefSeRegionX_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32defSeRegionX_CTRL;
                   };
                 } TdefSeRegionX_CTRL;
    typedef union  TdefSeRegionX_seStart
          { UNSG32 u32[1];
            struct {
            struct w32defSeRegionX_seStart;
                   };
                 } TdefSeRegionX_seStart;
    typedef union  TdefSeRegionX_seEnd
          { UNSG32 u32[1];
            struct {
            struct w32defSeRegionX_seEnd;
                   };
                 } TdefSeRegionX_seEnd;

    ///////////////////////////////////////////////////////////
     SIGN32 defSeRegionX_drvrd(SIE_defSeRegionX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 defSeRegionX_drvwr(SIE_defSeRegionX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void defSeRegionX_reset(SIE_defSeRegionX *p);
     SIGN32 defSeRegionX_cmp  (SIE_defSeRegionX *p, SIE_defSeRegionX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define defSeRegionX_check(p,pie,pfx,hLOG) defSeRegionX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define defSeRegionX_print(p,    pfx,hLOG) defSeRegionX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: defSeRegionX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE seRegionX                                (4,4)
///     ###
///     * Config Space Secure Regions
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 CTRL0                
///               $seSettingX          CTRL0             REG          
///                                    ###
///                                    * Region 0 access control register
///                                    ###
///     @ 0x0000C                      (P)
///     # 0x0000C CTRL1                
///               $seSettingX          CTRL1             REG          
///                                    ###
///                                    * Region 1 access control register
///                                    ###
///     @ 0x00018                      (P)
///     # 0x00018 CTRL2                
///               $seSettingX          CTRL2             REG          
///                                    ###
///                                    * Region 2 access control register
///                                    ###
///     @ 0x00024                      (P)
///     # 0x00024 CTRL3                
///               $seSettingX          CTRL3             REG          
///                                    ###
///                                    * Region 3 access control register
///                                    ###
///     @ 0x00030                      (P)
///     # 0x00030 CTRL4                
///               $seSettingX          CTRL4             REG          
///                                    ###
///                                    * Region 4 access control register
///                                    ###
///     @ 0x0003C                      (P)
///     # 0x0003C CTRL5                
///               $seSettingX          CTRL5             REG          
///                                    ###
///                                    * Region 5 access control register
///                                    ###
///     @ 0x00048                      (P)
///     # 0x00048 CTRL6                
///               $seSettingX          CTRL6             REG          
///                                    ###
///                                    * Region 6 access control register
///                                    ###
///     @ 0x00054                      (P)
///     # 0x00054 CTRL7                
///               $seSettingX          CTRL7             REG          
///                                    ###
///                                    * Region 7 access control register
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      96B, bits:     552b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_seRegionX
#define h_seRegionX (){}

    #define     RA_seRegionX_CTRL0                             0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL1                             0x000C
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL2                             0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL3                             0x0024
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL4                             0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL5                             0x003C
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL6                             0x0048
    ///////////////////////////////////////////////////////////
    #define     RA_seRegionX_CTRL7                             0x0054
    ///////////////////////////////////////////////////////////

    typedef struct SIE_seRegionX {
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL0;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL1;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL2;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL3;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL4;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL5;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL6;
    ///////////////////////////////////////////////////////////
              SIE_seSettingX                                   ie_CTRL7;
    ///////////////////////////////////////////////////////////
    } SIE_seRegionX;

    ///////////////////////////////////////////////////////////
     SIGN32 seRegionX_drvrd(SIE_seRegionX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 seRegionX_drvwr(SIE_seRegionX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void seRegionX_reset(SIE_seRegionX *p);
     SIGN32 seRegionX_cmp  (SIE_seRegionX *p, SIE_seRegionX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define seRegionX_check(p,pie,pfx,hLOG) seRegionX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define seRegionX_print(p,    pfx,hLOG) seRegionX_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: seRegionX
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE seAccess                                 (4,4)
///     ###
///     * AXI Secure Access
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 seAxi                (P-)
///               %unsigned 1  ProtOverrideW             0x0
///                                    ###
///                                    * 1: Overrides AWPROT with ProtValW
///                                    * 0: AWPROT passes through
///                                    ###
///               %unsigned 1  ProtValW                  0x0
///                                    ###
///                                    * 0: AWPROT is 0
///                                    * 1: AWPROT is 1
///                                    ###
///               %unsigned 1  ProtOverrideR             0x0
///                                    ###
///                                    * 1: Overrides ARPROT with ProtValR
///                                    * 0: ARPROT passes through
///                                    ###
///               %unsigned 1  ProtValR                  0x0
///                                    ###
///                                    * 0: ARPROT is 0
///                                    * 1: ARPROT is 1
///                                    ###
///               %unsigned 1  Lock                      0x0
///                                    ###
///                                    * When Lock=1 it blocks writes to above Prot Override registers. Once set it cannot be changed until reset.
///                                    ###
///               %%        27         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       5b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_seAccess
#define h_seAccess (){}

    #define     RA_seAccess_seAxi                              0x0000

    #define     BA_seAccess_seAxi_ProtOverrideW                0x0000
    #define     B16seAccess_seAxi_ProtOverrideW                0x0000
    #define   LSb32seAccess_seAxi_ProtOverrideW                   0
    #define   LSb16seAccess_seAxi_ProtOverrideW                   0
    #define       bseAccess_seAxi_ProtOverrideW                1
    #define   MSK32seAccess_seAxi_ProtOverrideW                   0x00000001

    #define     BA_seAccess_seAxi_ProtValW                     0x0000
    #define     B16seAccess_seAxi_ProtValW                     0x0000
    #define   LSb32seAccess_seAxi_ProtValW                        1
    #define   LSb16seAccess_seAxi_ProtValW                        1
    #define       bseAccess_seAxi_ProtValW                     1
    #define   MSK32seAccess_seAxi_ProtValW                        0x00000002

    #define     BA_seAccess_seAxi_ProtOverrideR                0x0000
    #define     B16seAccess_seAxi_ProtOverrideR                0x0000
    #define   LSb32seAccess_seAxi_ProtOverrideR                   2
    #define   LSb16seAccess_seAxi_ProtOverrideR                   2
    #define       bseAccess_seAxi_ProtOverrideR                1
    #define   MSK32seAccess_seAxi_ProtOverrideR                   0x00000004

    #define     BA_seAccess_seAxi_ProtValR                     0x0000
    #define     B16seAccess_seAxi_ProtValR                     0x0000
    #define   LSb32seAccess_seAxi_ProtValR                        3
    #define   LSb16seAccess_seAxi_ProtValR                        3
    #define       bseAccess_seAxi_ProtValR                     1
    #define   MSK32seAccess_seAxi_ProtValR                        0x00000008

    #define     BA_seAccess_seAxi_Lock                         0x0000
    #define     B16seAccess_seAxi_Lock                         0x0000
    #define   LSb32seAccess_seAxi_Lock                            4
    #define   LSb16seAccess_seAxi_Lock                            4
    #define       bseAccess_seAxi_Lock                         1
    #define   MSK32seAccess_seAxi_Lock                            0x00000010
    ///////////////////////////////////////////////////////////

    typedef struct SIE_seAccess {
    ///////////////////////////////////////////////////////////
    #define   GET32seAccess_seAxi_ProtOverrideW(r32)           _BFGET_(r32, 0, 0)
    #define   SET32seAccess_seAxi_ProtOverrideW(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16seAccess_seAxi_ProtOverrideW(r16)           _BFGET_(r16, 0, 0)
    #define   SET16seAccess_seAxi_ProtOverrideW(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32seAccess_seAxi_ProtValW(r32)                _BFGET_(r32, 1, 1)
    #define   SET32seAccess_seAxi_ProtValW(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16seAccess_seAxi_ProtValW(r16)                _BFGET_(r16, 1, 1)
    #define   SET16seAccess_seAxi_ProtValW(r16,v)              _BFSET_(r16, 1, 1,v)

    #define   GET32seAccess_seAxi_ProtOverrideR(r32)           _BFGET_(r32, 2, 2)
    #define   SET32seAccess_seAxi_ProtOverrideR(r32,v)         _BFSET_(r32, 2, 2,v)
    #define   GET16seAccess_seAxi_ProtOverrideR(r16)           _BFGET_(r16, 2, 2)
    #define   SET16seAccess_seAxi_ProtOverrideR(r16,v)         _BFSET_(r16, 2, 2,v)

    #define   GET32seAccess_seAxi_ProtValR(r32)                _BFGET_(r32, 3, 3)
    #define   SET32seAccess_seAxi_ProtValR(r32,v)              _BFSET_(r32, 3, 3,v)
    #define   GET16seAccess_seAxi_ProtValR(r16)                _BFGET_(r16, 3, 3)
    #define   SET16seAccess_seAxi_ProtValR(r16,v)              _BFSET_(r16, 3, 3,v)

    #define   GET32seAccess_seAxi_Lock(r32)                    _BFGET_(r32, 4, 4)
    #define   SET32seAccess_seAxi_Lock(r32,v)                  _BFSET_(r32, 4, 4,v)
    #define   GET16seAccess_seAxi_Lock(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16seAccess_seAxi_Lock(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define     w32seAccess_seAxi                              {\
            UNSG32 useAxi_ProtOverrideW                        :  1;\
            UNSG32 useAxi_ProtValW                             :  1;\
            UNSG32 useAxi_ProtOverrideR                        :  1;\
            UNSG32 useAxi_ProtValR                             :  1;\
            UNSG32 useAxi_Lock                                 :  1;\
            UNSG32 RSVDx0_b5                                   : 27;\
          }
    union { UNSG32 u32seAccess_seAxi;
            struct w32seAccess_seAxi;
          };
    ///////////////////////////////////////////////////////////
    } SIE_seAccess;

    typedef union  T32seAccess_seAxi
          { UNSG32 u32;
            struct w32seAccess_seAxi;
                 } T32seAccess_seAxi;
    ///////////////////////////////////////////////////////////

    typedef union  TseAccess_seAxi
          { UNSG32 u32[1];
            struct {
            struct w32seAccess_seAxi;
                   };
                 } TseAccess_seAxi;

    ///////////////////////////////////////////////////////////
     SIGN32 seAccess_drvrd(SIE_seAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 seAccess_drvwr(SIE_seAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void seAccess_reset(SIE_seAccess *p);
     SIGN32 seAccess_cmp  (SIE_seAccess *p, SIE_seAccess *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define seAccess_check(p,pie,pfx,hLOG) seAccess_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define seAccess_print(p,    pfx,hLOG) seAccess_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: seAccess
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE protOR                  biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 SecureCPU            
///               $seAccess            SecureCPU         REG          
///     @ 0x00004                      (P)
///     # 0x00004 SecureAVIOM0         
///               $seAccess            SecureAVIOM0      REG          
///     @ 0x00008                      (P)
///     # 0x00008 SecureIMTEST         
///               $seAccess            SecureIMTEST      REG          
///     @ 0x0000C                      (P)
///     # 0x0000C SecureBMON           
///               $seAccess            SecureBMON        REG          
///     @ 0x00010                      (P)
///     # 0x00010 SecureNNA            
///               $seAccess            SecureNNA         REG          
///                                    ###
///                                    * The following are secured based on decoding of the PXBAR AxID values
///                                    ###
///     @ 0x00014                      (P)
///     # 0x00014 SecureUSBM0          
///               $seAccess            SecureUSBM0       REG          
///     @ 0x00018                      (P)
///     # 0x00018 SecureSDIO           
///               $seAccess            SecureSDIO        REG          
///     @ 0x0001C                      (P)
///     # 0x0001C SecureNANDEMMC       
///               $seAccess            SecureNANDEMMC    REG          
///     @ 0x00020                      (P)
///     # 0x00020 SecurePCIE0          
///               $seAccess            SecurePCIE0       REG          
///     @ 0x00024                      (P)
///     # 0x00024 SecurePCIE1          
///               $seAccess            SecurePCIE1       REG          
///     @ 0x00028                      (P)
///     # 0x00028 SecurePB             
///               $seAccess            SecurePB          REG          
///                                    ###
///                                    * The following are secured based on decoding of the TXBAR AxID values
///                                    ###
///     @ 0x0002C                      (P)
///     # 0x0002C SecureBCMCPU         
///               $seAccess            SecureBCMCPU      REG          
///     @ 0x00030                      (P)
///     # 0x00030 SecureBCMDMA         
///               $seAccess            SecureBCMDMA      REG          
///     @ 0x00034                      (P)
///     # 0x00034 SecureBCMDIR         
///               $seAccess            SecureBCMDIR      REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      56B, bits:      70b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_protOR
#define h_protOR (){}

    #define     RA_protOR_SecureCPU                            0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureAVIOM0                         0x0004
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureIMTEST                         0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureBMON                           0x000C
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureNNA                            0x0010
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureUSBM0                          0x0014
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureSDIO                           0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureNANDEMMC                       0x001C
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecurePCIE0                          0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecurePCIE1                          0x0024
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecurePB                             0x0028
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureBCMCPU                         0x002C
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureBCMDMA                         0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_protOR_SecureBCMDIR                         0x0034
    ///////////////////////////////////////////////////////////

    typedef struct SIE_protOR {
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureCPU;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureAVIOM0;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureIMTEST;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureBMON;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureNNA;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureUSBM0;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureSDIO;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureNANDEMMC;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecurePCIE0;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecurePCIE1;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecurePB;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureBCMCPU;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureBCMDMA;
    ///////////////////////////////////////////////////////////
              SIE_seAccess                                     ie_SecureBCMDIR;
    ///////////////////////////////////////////////////////////
    } SIE_protOR;

    ///////////////////////////////////////////////////////////
     SIGN32 protOR_drvrd(SIE_protOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 protOR_drvwr(SIE_protOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void protOR_reset(SIE_protOR *p);
     SIGN32 protOR_cmp  (SIE_protOR *p, SIE_protOR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define protOR_check(p,pie,pfx,hLOG) protOR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define protOR_print(p,    pfx,hLOG) protOR_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: protOR
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE RzAccess                                 (4,4)
///     ###
///     * Restrict Zone Access
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 Rz                   (P-)
///               %unsigned 1  RzValW                    0x0
///                                    ###
///                                    * 1: Enable Restrict Zone Write access
///                                    * 0: Disable Restrict Zone Write access.
///                                    ###
///               %unsigned 1  RzValR                    0x0
///                                    ###
///                                    * 1: Enable Restrict Zone Read access
///                                    * 0: Disable Restrict Zone Read access.
///                                    ###
///               %unsigned 1  Lock                      0x0
///                                    ###
///                                    * When Lock=1 it blocks writes to above Rz access registers. Once set it cannot be changed until reset.
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       3b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_RzAccess
#define h_RzAccess (){}

    #define     RA_RzAccess_Rz                                 0x0000

    #define     BA_RzAccess_Rz_RzValW                          0x0000
    #define     B16RzAccess_Rz_RzValW                          0x0000
    #define   LSb32RzAccess_Rz_RzValW                             0
    #define   LSb16RzAccess_Rz_RzValW                             0
    #define       bRzAccess_Rz_RzValW                          1
    #define   MSK32RzAccess_Rz_RzValW                             0x00000001

    #define     BA_RzAccess_Rz_RzValR                          0x0000
    #define     B16RzAccess_Rz_RzValR                          0x0000
    #define   LSb32RzAccess_Rz_RzValR                             1
    #define   LSb16RzAccess_Rz_RzValR                             1
    #define       bRzAccess_Rz_RzValR                          1
    #define   MSK32RzAccess_Rz_RzValR                             0x00000002

    #define     BA_RzAccess_Rz_Lock                            0x0000
    #define     B16RzAccess_Rz_Lock                            0x0000
    #define   LSb32RzAccess_Rz_Lock                               2
    #define   LSb16RzAccess_Rz_Lock                               2
    #define       bRzAccess_Rz_Lock                            1
    #define   MSK32RzAccess_Rz_Lock                               0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_RzAccess {
    ///////////////////////////////////////////////////////////
    #define   GET32RzAccess_Rz_RzValW(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32RzAccess_Rz_RzValW(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16RzAccess_Rz_RzValW(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16RzAccess_Rz_RzValW(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32RzAccess_Rz_RzValR(r32)                     _BFGET_(r32, 1, 1)
    #define   SET32RzAccess_Rz_RzValR(r32,v)                   _BFSET_(r32, 1, 1,v)
    #define   GET16RzAccess_Rz_RzValR(r16)                     _BFGET_(r16, 1, 1)
    #define   SET16RzAccess_Rz_RzValR(r16,v)                   _BFSET_(r16, 1, 1,v)

    #define   GET32RzAccess_Rz_Lock(r32)                       _BFGET_(r32, 2, 2)
    #define   SET32RzAccess_Rz_Lock(r32,v)                     _BFSET_(r32, 2, 2,v)
    #define   GET16RzAccess_Rz_Lock(r16)                       _BFGET_(r16, 2, 2)
    #define   SET16RzAccess_Rz_Lock(r16,v)                     _BFSET_(r16, 2, 2,v)

    #define     w32RzAccess_Rz                                 {\
            UNSG32 uRz_RzValW                                  :  1;\
            UNSG32 uRz_RzValR                                  :  1;\
            UNSG32 uRz_Lock                                    :  1;\
            UNSG32 RSVDx0_b3                                   : 29;\
          }
    union { UNSG32 u32RzAccess_Rz;
            struct w32RzAccess_Rz;
          };
    ///////////////////////////////////////////////////////////
    } SIE_RzAccess;

    typedef union  T32RzAccess_Rz
          { UNSG32 u32;
            struct w32RzAccess_Rz;
                 } T32RzAccess_Rz;
    ///////////////////////////////////////////////////////////

    typedef union  TRzAccess_Rz
          { UNSG32 u32[1];
            struct {
            struct w32RzAccess_Rz;
                   };
                 } TRzAccess_Rz;

    ///////////////////////////////////////////////////////////
     SIGN32 RzAccess_drvrd(SIE_RzAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 RzAccess_drvwr(SIE_RzAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void RzAccess_reset(SIE_RzAccess *p);
     SIGN32 RzAccess_cmp  (SIE_RzAccess *p, SIE_RzAccess *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define RzAccess_check(p,pie,pfx,hLOG) RzAccess_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define RzAccess_print(p,    pfx,hLOG) RzAccess_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: RzAccess
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE defRzAccess                              (4,4)
///     ###
///     * Restrict Zone Access
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 Rz                   (P-)
///               %unsigned 1  RzValW                    0x1
///                                    ###
///                                    * 1: Enable Restrict Zone Write access
///                                    * 0: Disable Restrict Zone Write access.
///                                    ###
///               %unsigned 1  RzValR                    0x1
///                                    ###
///                                    * 1: Enable Restrict Zone Read access
///                                    * 0: Disable Restrict Zone Read access.
///                                    ###
///               %unsigned 1  Lock                      0x0
///                                    ###
///                                    * When Lock=1 it blocks writes to above Rz access registers. Once set it cannot be changed until reset.
///                                    ###
///               %%        29         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:       3b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_defRzAccess
#define h_defRzAccess (){}

    #define     RA_defRzAccess_Rz                              0x0000

    #define     BA_defRzAccess_Rz_RzValW                       0x0000
    #define     B16defRzAccess_Rz_RzValW                       0x0000
    #define   LSb32defRzAccess_Rz_RzValW                          0
    #define   LSb16defRzAccess_Rz_RzValW                          0
    #define       bdefRzAccess_Rz_RzValW                       1
    #define   MSK32defRzAccess_Rz_RzValW                          0x00000001

    #define     BA_defRzAccess_Rz_RzValR                       0x0000
    #define     B16defRzAccess_Rz_RzValR                       0x0000
    #define   LSb32defRzAccess_Rz_RzValR                          1
    #define   LSb16defRzAccess_Rz_RzValR                          1
    #define       bdefRzAccess_Rz_RzValR                       1
    #define   MSK32defRzAccess_Rz_RzValR                          0x00000002

    #define     BA_defRzAccess_Rz_Lock                         0x0000
    #define     B16defRzAccess_Rz_Lock                         0x0000
    #define   LSb32defRzAccess_Rz_Lock                            2
    #define   LSb16defRzAccess_Rz_Lock                            2
    #define       bdefRzAccess_Rz_Lock                         1
    #define   MSK32defRzAccess_Rz_Lock                            0x00000004
    ///////////////////////////////////////////////////////////

    typedef struct SIE_defRzAccess {
    ///////////////////////////////////////////////////////////
    #define   GET32defRzAccess_Rz_RzValW(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32defRzAccess_Rz_RzValW(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16defRzAccess_Rz_RzValW(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16defRzAccess_Rz_RzValW(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32defRzAccess_Rz_RzValR(r32)                  _BFGET_(r32, 1, 1)
    #define   SET32defRzAccess_Rz_RzValR(r32,v)                _BFSET_(r32, 1, 1,v)
    #define   GET16defRzAccess_Rz_RzValR(r16)                  _BFGET_(r16, 1, 1)
    #define   SET16defRzAccess_Rz_RzValR(r16,v)                _BFSET_(r16, 1, 1,v)

    #define   GET32defRzAccess_Rz_Lock(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32defRzAccess_Rz_Lock(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16defRzAccess_Rz_Lock(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16defRzAccess_Rz_Lock(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define     w32defRzAccess_Rz                              {\
            UNSG32 uRz_RzValW                                  :  1;\
            UNSG32 uRz_RzValR                                  :  1;\
            UNSG32 uRz_Lock                                    :  1;\
            UNSG32 RSVDx0_b3                                   : 29;\
          }
    union { UNSG32 u32defRzAccess_Rz;
            struct w32defRzAccess_Rz;
          };
    ///////////////////////////////////////////////////////////
    } SIE_defRzAccess;

    typedef union  T32defRzAccess_Rz
          { UNSG32 u32;
            struct w32defRzAccess_Rz;
                 } T32defRzAccess_Rz;
    ///////////////////////////////////////////////////////////

    typedef union  TdefRzAccess_Rz
          { UNSG32 u32[1];
            struct {
            struct w32defRzAccess_Rz;
                   };
                 } TdefRzAccess_Rz;

    ///////////////////////////////////////////////////////////
     SIGN32 defRzAccess_drvrd(SIE_defRzAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 defRzAccess_drvwr(SIE_defRzAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void defRzAccess_reset(SIE_defRzAccess *p);
     SIGN32 defRzAccess_cmp  (SIE_defRzAccess *p, SIE_defRzAccess *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define defRzAccess_check(p,pie,pfx,hLOG) defRzAccess_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define defRzAccess_print(p,    pfx,hLOG) defRzAccess_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: defRzAccess
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE RestrictZone            biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 RzAccessCPU          
///               $defRzAccess         RzAccessCPU       REG          
///     @ 0x00004                      (P)
///     # 0x00004 RzAccessAVIOM0       
///               $RzAccess            RzAccessAVIOM0    REG          
///     @ 0x00008                      (P)
///     # 0x00008 RzAccessIMTEST       
///               $RzAccess            RzAccessIMTEST    REG          
///     @ 0x0000C                      (P)
///     # 0x0000C RzAccessBMON         
///               $RzAccess            RzAccessBMON      REG          
///     @ 0x00010                      (P)
///     # 0x00010 RzAccessNNA          
///               $RzAccess            RzAccessNNA       REG          
///                                    ###
///                                    * The following are secured based on decoding of the PXBAR AxID values
///                                    ###
///     @ 0x00014                      (P)
///     # 0x00014 RzAccessUSBM0        
///               $RzAccess            RzAccessUSBM0     REG          
///     @ 0x00018                      (P)
///     # 0x00018 RzAccessSDIO         
///               $RzAccess            RzAccessSDIO      REG          
///     @ 0x0001C                      (P)
///     # 0x0001C RzAccessNANDEMMC     
///               $RzAccess            RzAccessNANDEMMC  REG          
///     @ 0x00020                      (P)
///     # 0x00020 RzAccessPCIE         
///               $RzAccess            RzAccessPCIE      REG          
///     @ 0x00024                      (P)
///     # 0x00024 RzAccessPCIE1        
///               $RzAccess            RzAccessPCIE1     REG          
///     @ 0x00028                      (P)
///     # 0x00028 RzAccessPB           
///               $RzAccess            RzAccessPB        REG          
///                                    ###
///                                    * The following are secured based on decoding of the TXBAR AxID values
///                                    ###
///     @ 0x0002C                      (P)
///     # 0x0002C RzAccessBCMCPU       
///               $defRzAccess         RzAccessBCMCPU    REG          
///     @ 0x00030                      (P)
///     # 0x00030 RzAccessBCMDMA       
///               $defRzAccess         RzAccessBCMDMA    REG          
///     @ 0x00034                      (P)
///     # 0x00034 RzAccessBCMDIR       
///               $defRzAccess         RzAccessBCMDIR    REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      56B, bits:      42b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_RestrictZone
#define h_RestrictZone (){}

    #define     RA_RestrictZone_RzAccessCPU                    0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessAVIOM0                 0x0004
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessIMTEST                 0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessBMON                   0x000C
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessNNA                    0x0010
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessUSBM0                  0x0014
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessSDIO                   0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessNANDEMMC               0x001C
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessPCIE                   0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessPCIE1                  0x0024
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessPB                     0x0028
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessBCMCPU                 0x002C
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessBCMDMA                 0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_RestrictZone_RzAccessBCMDIR                 0x0034
    ///////////////////////////////////////////////////////////

    typedef struct SIE_RestrictZone {
    ///////////////////////////////////////////////////////////
              SIE_defRzAccess                                  ie_RzAccessCPU;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessAVIOM0;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessIMTEST;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessBMON;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessNNA;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessUSBM0;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessSDIO;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessNANDEMMC;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessPCIE;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessPCIE1;
    ///////////////////////////////////////////////////////////
              SIE_RzAccess                                     ie_RzAccessPB;
    ///////////////////////////////////////////////////////////
              SIE_defRzAccess                                  ie_RzAccessBCMCPU;
    ///////////////////////////////////////////////////////////
              SIE_defRzAccess                                  ie_RzAccessBCMDMA;
    ///////////////////////////////////////////////////////////
              SIE_defRzAccess                                  ie_RzAccessBCMDIR;
    ///////////////////////////////////////////////////////////
    } SIE_RestrictZone;

    ///////////////////////////////////////////////////////////
     SIGN32 RestrictZone_drvrd(SIE_RestrictZone *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 RestrictZone_drvwr(SIE_RestrictZone *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void RestrictZone_reset(SIE_RestrictZone *p);
     SIGN32 RestrictZone_cmp  (SIE_RestrictZone *p, SIE_RestrictZone *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define RestrictZone_check(p,pie,pfx,hLOG) RestrictZone_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define RestrictZone_print(p,    pfx,hLOG) RestrictZone_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: RestrictZone
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE cacheAccess                              (4,4)
///     ###
///     * AXI cache Access
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 cacheAxi             (P)
///               %unsigned 4  CacheOverrideW            0x0
///                                    ###
///                                    * 1: Overrides AWCACHE[x] with CacheValW[x]. (x=0to3)
///                                    * 0: AWCACHE passes through
///                                    ###
///               %unsigned 4  CacheValW                 0x0
///               %unsigned 4  CacheOverrideR            0x0
///                                    ###
///                                    * 1: Overrides ARCACHE[x] with CacheValR[x]. (x=0to3)
///                                    * 0: ARCACHE passes through
///                                    ###
///               %unsigned 4  CacheValR                 0x0
///               %%        16         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       4B, bits:      16b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_cacheAccess
#define h_cacheAccess (){}

    #define     RA_cacheAccess_cacheAxi                        0x0000

    #define     BA_cacheAccess_cacheAxi_CacheOverrideW         0x0000
    #define     B16cacheAccess_cacheAxi_CacheOverrideW         0x0000
    #define   LSb32cacheAccess_cacheAxi_CacheOverrideW            0
    #define   LSb16cacheAccess_cacheAxi_CacheOverrideW            0
    #define       bcacheAccess_cacheAxi_CacheOverrideW         4
    #define   MSK32cacheAccess_cacheAxi_CacheOverrideW            0x0000000F

    #define     BA_cacheAccess_cacheAxi_CacheValW              0x0000
    #define     B16cacheAccess_cacheAxi_CacheValW              0x0000
    #define   LSb32cacheAccess_cacheAxi_CacheValW                 4
    #define   LSb16cacheAccess_cacheAxi_CacheValW                 4
    #define       bcacheAccess_cacheAxi_CacheValW              4
    #define   MSK32cacheAccess_cacheAxi_CacheValW                 0x000000F0

    #define     BA_cacheAccess_cacheAxi_CacheOverrideR         0x0001
    #define     B16cacheAccess_cacheAxi_CacheOverrideR         0x0000
    #define   LSb32cacheAccess_cacheAxi_CacheOverrideR            8
    #define   LSb16cacheAccess_cacheAxi_CacheOverrideR            8
    #define       bcacheAccess_cacheAxi_CacheOverrideR         4
    #define   MSK32cacheAccess_cacheAxi_CacheOverrideR            0x00000F00

    #define     BA_cacheAccess_cacheAxi_CacheValR              0x0001
    #define     B16cacheAccess_cacheAxi_CacheValR              0x0000
    #define   LSb32cacheAccess_cacheAxi_CacheValR                 12
    #define   LSb16cacheAccess_cacheAxi_CacheValR                 12
    #define       bcacheAccess_cacheAxi_CacheValR              4
    #define   MSK32cacheAccess_cacheAxi_CacheValR                 0x0000F000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_cacheAccess {
    ///////////////////////////////////////////////////////////
    #define   GET32cacheAccess_cacheAxi_CacheOverrideW(r32)    _BFGET_(r32, 3, 0)
    #define   SET32cacheAccess_cacheAxi_CacheOverrideW(r32,v)  _BFSET_(r32, 3, 0,v)
    #define   GET16cacheAccess_cacheAxi_CacheOverrideW(r16)    _BFGET_(r16, 3, 0)
    #define   SET16cacheAccess_cacheAxi_CacheOverrideW(r16,v)  _BFSET_(r16, 3, 0,v)

    #define   GET32cacheAccess_cacheAxi_CacheValW(r32)         _BFGET_(r32, 7, 4)
    #define   SET32cacheAccess_cacheAxi_CacheValW(r32,v)       _BFSET_(r32, 7, 4,v)
    #define   GET16cacheAccess_cacheAxi_CacheValW(r16)         _BFGET_(r16, 7, 4)
    #define   SET16cacheAccess_cacheAxi_CacheValW(r16,v)       _BFSET_(r16, 7, 4,v)

    #define   GET32cacheAccess_cacheAxi_CacheOverrideR(r32)    _BFGET_(r32,11, 8)
    #define   SET32cacheAccess_cacheAxi_CacheOverrideR(r32,v)  _BFSET_(r32,11, 8,v)
    #define   GET16cacheAccess_cacheAxi_CacheOverrideR(r16)    _BFGET_(r16,11, 8)
    #define   SET16cacheAccess_cacheAxi_CacheOverrideR(r16,v)  _BFSET_(r16,11, 8,v)

    #define   GET32cacheAccess_cacheAxi_CacheValR(r32)         _BFGET_(r32,15,12)
    #define   SET32cacheAccess_cacheAxi_CacheValR(r32,v)       _BFSET_(r32,15,12,v)
    #define   GET16cacheAccess_cacheAxi_CacheValR(r16)         _BFGET_(r16,15,12)
    #define   SET16cacheAccess_cacheAxi_CacheValR(r16,v)       _BFSET_(r16,15,12,v)

    #define     w32cacheAccess_cacheAxi                        {\
            UNSG32 ucacheAxi_CacheOverrideW                    :  4;\
            UNSG32 ucacheAxi_CacheValW                         :  4;\
            UNSG32 ucacheAxi_CacheOverrideR                    :  4;\
            UNSG32 ucacheAxi_CacheValR                         :  4;\
            UNSG32 RSVDx0_b16                                  : 16;\
          }
    union { UNSG32 u32cacheAccess_cacheAxi;
            struct w32cacheAccess_cacheAxi;
          };
    ///////////////////////////////////////////////////////////
    } SIE_cacheAccess;

    typedef union  T32cacheAccess_cacheAxi
          { UNSG32 u32;
            struct w32cacheAccess_cacheAxi;
                 } T32cacheAccess_cacheAxi;
    ///////////////////////////////////////////////////////////

    typedef union  TcacheAccess_cacheAxi
          { UNSG32 u32[1];
            struct {
            struct w32cacheAccess_cacheAxi;
                   };
                 } TcacheAccess_cacheAxi;

    ///////////////////////////////////////////////////////////
     SIGN32 cacheAccess_drvrd(SIE_cacheAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 cacheAccess_drvwr(SIE_cacheAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void cacheAccess_reset(SIE_cacheAccess *p);
     SIGN32 cacheAccess_cmp  (SIE_cacheAccess *p, SIE_cacheAccess *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define cacheAccess_check(p,pie,pfx,hLOG) cacheAccess_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define cacheAccess_print(p,    pfx,hLOG) cacheAccess_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: cacheAccess
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE cacheOR                 biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 CachePCIE0           
///               $cacheAccess         CachePCIE0        REG          
///     @ 0x00004                      (P)
///     # 0x00004 CachePCIE1           
///               $cacheAccess         CachePCIE1        REG          
///     @ 0x00008                      (P)
///     # 0x00008 CacheSDIO            
///               $cacheAccess         CacheSDIO         REG          
///     @ 0x0000C                      (P)
///     # 0x0000C CacheEMMCNAND        
///               $cacheAccess         CacheEMMCNAND     REG          
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_cacheOR
#define h_cacheOR (){}

    #define     RA_cacheOR_CachePCIE0                          0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_cacheOR_CachePCIE1                          0x0004
    ///////////////////////////////////////////////////////////
    #define     RA_cacheOR_CacheSDIO                           0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_cacheOR_CacheEMMCNAND                       0x000C
    ///////////////////////////////////////////////////////////

    typedef struct SIE_cacheOR {
    ///////////////////////////////////////////////////////////
              SIE_cacheAccess                                  ie_CachePCIE0;
    ///////////////////////////////////////////////////////////
              SIE_cacheAccess                                  ie_CachePCIE1;
    ///////////////////////////////////////////////////////////
              SIE_cacheAccess                                  ie_CacheSDIO;
    ///////////////////////////////////////////////////////////
              SIE_cacheAccess                                  ie_CacheEMMCNAND;
    ///////////////////////////////////////////////////////////
    } SIE_cacheOR;

    ///////////////////////////////////////////////////////////
     SIGN32 cacheOR_drvrd(SIE_cacheOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 cacheOR_drvwr(SIE_cacheOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void cacheOR_reset(SIE_cacheOR *p);
     SIGN32 cacheOR_cmp  (SIE_cacheOR *p, SIE_cacheOR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define cacheOR_check(p,pie,pfx,hLOG) cacheOR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define cacheOR_print(p,    pfx,hLOG) cacheOR_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: cacheOR
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxiWrFilt                                (4,4)
///     ###
///     * AXI Write Strobe Filter
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (RW-)
///               %unsigned 1  En                        0x0
///                                    ###
///                                    * Write filtering is enabled. Checks against all regions will start.
///                                    ###
///               %unsigned 1  Clear                     0x0
///                                    ###
///                                    * Writing 1 to this bit will clear the status and interrupt.
///                                    * This bit self clears
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00004 STATUS               (R-)
///               %unsigned 1  Intr                      0x0
///                                    ###
///                                    * 0: No match to the regions has occurred
///                                    * 1: A region was hit and the WSTRB of the transaction is masked.
///                                    * This bit stays high and the WSTRB stays masked until a 1 is written to CTRL.Clear.
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x00008 ProtAddr0            (P)
///               %unsigned 32 Addr                      0x0
///                                    ###
///                                    * Base or Start address of the region
///                                    * Bits [1:0] unused.
///                                    ###
///     @ 0x0000C ProtMask0            (P)
///               %unsigned 32 Mask                      0x0
///                                    ###
///                                    * Used in conjunction with Addr to define region size
///                                    * Bits [1:0] unused
///                                    ###
///     @ 0x00010 ProtAddr1            (P)
///               %unsigned 32 Addr                      0x0
///                                    ###
///                                    * Base or Start address of the region
///                                    * Bits [1:0] unused.
///                                    ###
///     @ 0x00014 ProtMask1            (P)
///               %unsigned 32 Mask                      0x0
///                                    ###
///                                    * Used in conjunction with Addr to define region size
///                                    * Bits [1:0] unused
///                                    ###
///     @ 0x00018 ProtAddr2            (P)
///               %unsigned 32 Addr                      0x0
///                                    ###
///                                    * Base or Start address of the region
///                                    * Bits [1:0] unused.
///                                    ###
///     @ 0x0001C ProtMask2            (P)
///               %unsigned 32 Mask                      0x0
///                                    ###
///                                    * Used in conjunction with Addr to define region size
///                                    * Bits [1:0] unused
///                                    ###
///     @ 0x00020 ProtAddr3            (P)
///               %unsigned 32 Addr                      0x0
///                                    ###
///                                    * Base or Start address of the region
///                                    * Bits [1:0] unused.
///                                    ###
///     @ 0x00024 ProtMask3            (P)
///               %unsigned 32 Mask                      0x0
///                                    ###
///                                    * Used in conjunction with Addr to define region size
///                                    * Bits [1:0] unused
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      40B, bits:     259b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxiWrFilt
#define h_AxiWrFilt (){}

    #define     RA_AxiWrFilt_CTRL                              0x0000

    #define     BA_AxiWrFilt_CTRL_En                           0x0000
    #define     B16AxiWrFilt_CTRL_En                           0x0000
    #define   LSb32AxiWrFilt_CTRL_En                              0
    #define   LSb16AxiWrFilt_CTRL_En                              0
    #define       bAxiWrFilt_CTRL_En                           1
    #define   MSK32AxiWrFilt_CTRL_En                              0x00000001

    #define     BA_AxiWrFilt_CTRL_Clear                        0x0000
    #define     B16AxiWrFilt_CTRL_Clear                        0x0000
    #define   LSb32AxiWrFilt_CTRL_Clear                           1
    #define   LSb16AxiWrFilt_CTRL_Clear                           1
    #define       bAxiWrFilt_CTRL_Clear                        1
    #define   MSK32AxiWrFilt_CTRL_Clear                           0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_STATUS                            0x0004

    #define     BA_AxiWrFilt_STATUS_Intr                       0x0004
    #define     B16AxiWrFilt_STATUS_Intr                       0x0004
    #define   LSb32AxiWrFilt_STATUS_Intr                          0
    #define   LSb16AxiWrFilt_STATUS_Intr                          0
    #define       bAxiWrFilt_STATUS_Intr                       1
    #define   MSK32AxiWrFilt_STATUS_Intr                          0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtAddr0                         0x0008

    #define     BA_AxiWrFilt_ProtAddr0_Addr                    0x0008
    #define     B16AxiWrFilt_ProtAddr0_Addr                    0x0008
    #define   LSb32AxiWrFilt_ProtAddr0_Addr                       0
    #define   LSb16AxiWrFilt_ProtAddr0_Addr                       0
    #define       bAxiWrFilt_ProtAddr0_Addr                    32
    #define   MSK32AxiWrFilt_ProtAddr0_Addr                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtMask0                         0x000C

    #define     BA_AxiWrFilt_ProtMask0_Mask                    0x000C
    #define     B16AxiWrFilt_ProtMask0_Mask                    0x000C
    #define   LSb32AxiWrFilt_ProtMask0_Mask                       0
    #define   LSb16AxiWrFilt_ProtMask0_Mask                       0
    #define       bAxiWrFilt_ProtMask0_Mask                    32
    #define   MSK32AxiWrFilt_ProtMask0_Mask                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtAddr1                         0x0010

    #define     BA_AxiWrFilt_ProtAddr1_Addr                    0x0010
    #define     B16AxiWrFilt_ProtAddr1_Addr                    0x0010
    #define   LSb32AxiWrFilt_ProtAddr1_Addr                       0
    #define   LSb16AxiWrFilt_ProtAddr1_Addr                       0
    #define       bAxiWrFilt_ProtAddr1_Addr                    32
    #define   MSK32AxiWrFilt_ProtAddr1_Addr                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtMask1                         0x0014

    #define     BA_AxiWrFilt_ProtMask1_Mask                    0x0014
    #define     B16AxiWrFilt_ProtMask1_Mask                    0x0014
    #define   LSb32AxiWrFilt_ProtMask1_Mask                       0
    #define   LSb16AxiWrFilt_ProtMask1_Mask                       0
    #define       bAxiWrFilt_ProtMask1_Mask                    32
    #define   MSK32AxiWrFilt_ProtMask1_Mask                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtAddr2                         0x0018

    #define     BA_AxiWrFilt_ProtAddr2_Addr                    0x0018
    #define     B16AxiWrFilt_ProtAddr2_Addr                    0x0018
    #define   LSb32AxiWrFilt_ProtAddr2_Addr                       0
    #define   LSb16AxiWrFilt_ProtAddr2_Addr                       0
    #define       bAxiWrFilt_ProtAddr2_Addr                    32
    #define   MSK32AxiWrFilt_ProtAddr2_Addr                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtMask2                         0x001C

    #define     BA_AxiWrFilt_ProtMask2_Mask                    0x001C
    #define     B16AxiWrFilt_ProtMask2_Mask                    0x001C
    #define   LSb32AxiWrFilt_ProtMask2_Mask                       0
    #define   LSb16AxiWrFilt_ProtMask2_Mask                       0
    #define       bAxiWrFilt_ProtMask2_Mask                    32
    #define   MSK32AxiWrFilt_ProtMask2_Mask                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtAddr3                         0x0020

    #define     BA_AxiWrFilt_ProtAddr3_Addr                    0x0020
    #define     B16AxiWrFilt_ProtAddr3_Addr                    0x0020
    #define   LSb32AxiWrFilt_ProtAddr3_Addr                       0
    #define   LSb16AxiWrFilt_ProtAddr3_Addr                       0
    #define       bAxiWrFilt_ProtAddr3_Addr                    32
    #define   MSK32AxiWrFilt_ProtAddr3_Addr                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiWrFilt_ProtMask3                         0x0024

    #define     BA_AxiWrFilt_ProtMask3_Mask                    0x0024
    #define     B16AxiWrFilt_ProtMask3_Mask                    0x0024
    #define   LSb32AxiWrFilt_ProtMask3_Mask                       0
    #define   LSb16AxiWrFilt_ProtMask3_Mask                       0
    #define       bAxiWrFilt_ProtMask3_Mask                    32
    #define   MSK32AxiWrFilt_ProtMask3_Mask                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxiWrFilt {
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_CTRL_En(r32)                      _BFGET_(r32, 0, 0)
    #define   SET32AxiWrFilt_CTRL_En(r32,v)                    _BFSET_(r32, 0, 0,v)
    #define   GET16AxiWrFilt_CTRL_En(r16)                      _BFGET_(r16, 0, 0)
    #define   SET16AxiWrFilt_CTRL_En(r16,v)                    _BFSET_(r16, 0, 0,v)

    #define   GET32AxiWrFilt_CTRL_Clear(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32AxiWrFilt_CTRL_Clear(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16AxiWrFilt_CTRL_Clear(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16AxiWrFilt_CTRL_Clear(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define     w32AxiWrFilt_CTRL                              {\
            UNSG32 uCTRL_En                                    :  1;\
            UNSG32 uCTRL_Clear                                 :  1;\
            UNSG32 RSVDx0_b2                                   : 30;\
          }
    union { UNSG32 u32AxiWrFilt_CTRL;
            struct w32AxiWrFilt_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_STATUS_Intr(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32AxiWrFilt_STATUS_Intr(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16AxiWrFilt_STATUS_Intr(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16AxiWrFilt_STATUS_Intr(r16,v)                _BFSET_(r16, 0, 0,v)

    #define     w32AxiWrFilt_STATUS                            {\
            UNSG32 uSTATUS_Intr                                :  1;\
            UNSG32 RSVDx4_b1                                   : 31;\
          }
    union { UNSG32 u32AxiWrFilt_STATUS;
            struct w32AxiWrFilt_STATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtAddr0_Addr(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtAddr0_Addr(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtAddr0                         {\
            UNSG32 uProtAddr0_Addr                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtAddr0;
            struct w32AxiWrFilt_ProtAddr0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtMask0_Mask(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtMask0_Mask(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtMask0                         {\
            UNSG32 uProtMask0_Mask                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtMask0;
            struct w32AxiWrFilt_ProtMask0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtAddr1_Addr(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtAddr1_Addr(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtAddr1                         {\
            UNSG32 uProtAddr1_Addr                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtAddr1;
            struct w32AxiWrFilt_ProtAddr1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtMask1_Mask(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtMask1_Mask(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtMask1                         {\
            UNSG32 uProtMask1_Mask                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtMask1;
            struct w32AxiWrFilt_ProtMask1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtAddr2_Addr(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtAddr2_Addr(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtAddr2                         {\
            UNSG32 uProtAddr2_Addr                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtAddr2;
            struct w32AxiWrFilt_ProtAddr2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtMask2_Mask(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtMask2_Mask(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtMask2                         {\
            UNSG32 uProtMask2_Mask                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtMask2;
            struct w32AxiWrFilt_ProtMask2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtAddr3_Addr(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtAddr3_Addr(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtAddr3                         {\
            UNSG32 uProtAddr3_Addr                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtAddr3;
            struct w32AxiWrFilt_ProtAddr3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiWrFilt_ProtMask3_Mask(r32)               _BFGET_(r32,31, 0)
    #define   SET32AxiWrFilt_ProtMask3_Mask(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32AxiWrFilt_ProtMask3                         {\
            UNSG32 uProtMask3_Mask                             : 32;\
          }
    union { UNSG32 u32AxiWrFilt_ProtMask3;
            struct w32AxiWrFilt_ProtMask3;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxiWrFilt;

    typedef union  T32AxiWrFilt_CTRL
          { UNSG32 u32;
            struct w32AxiWrFilt_CTRL;
                 } T32AxiWrFilt_CTRL;
    typedef union  T32AxiWrFilt_STATUS
          { UNSG32 u32;
            struct w32AxiWrFilt_STATUS;
                 } T32AxiWrFilt_STATUS;
    typedef union  T32AxiWrFilt_ProtAddr0
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtAddr0;
                 } T32AxiWrFilt_ProtAddr0;
    typedef union  T32AxiWrFilt_ProtMask0
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtMask0;
                 } T32AxiWrFilt_ProtMask0;
    typedef union  T32AxiWrFilt_ProtAddr1
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtAddr1;
                 } T32AxiWrFilt_ProtAddr1;
    typedef union  T32AxiWrFilt_ProtMask1
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtMask1;
                 } T32AxiWrFilt_ProtMask1;
    typedef union  T32AxiWrFilt_ProtAddr2
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtAddr2;
                 } T32AxiWrFilt_ProtAddr2;
    typedef union  T32AxiWrFilt_ProtMask2
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtMask2;
                 } T32AxiWrFilt_ProtMask2;
    typedef union  T32AxiWrFilt_ProtAddr3
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtAddr3;
                 } T32AxiWrFilt_ProtAddr3;
    typedef union  T32AxiWrFilt_ProtMask3
          { UNSG32 u32;
            struct w32AxiWrFilt_ProtMask3;
                 } T32AxiWrFilt_ProtMask3;
    ///////////////////////////////////////////////////////////

    typedef union  TAxiWrFilt_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_CTRL;
                   };
                 } TAxiWrFilt_CTRL;
    typedef union  TAxiWrFilt_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_STATUS;
                   };
                 } TAxiWrFilt_STATUS;
    typedef union  TAxiWrFilt_ProtAddr0
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtAddr0;
                   };
                 } TAxiWrFilt_ProtAddr0;
    typedef union  TAxiWrFilt_ProtMask0
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtMask0;
                   };
                 } TAxiWrFilt_ProtMask0;
    typedef union  TAxiWrFilt_ProtAddr1
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtAddr1;
                   };
                 } TAxiWrFilt_ProtAddr1;
    typedef union  TAxiWrFilt_ProtMask1
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtMask1;
                   };
                 } TAxiWrFilt_ProtMask1;
    typedef union  TAxiWrFilt_ProtAddr2
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtAddr2;
                   };
                 } TAxiWrFilt_ProtAddr2;
    typedef union  TAxiWrFilt_ProtMask2
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtMask2;
                   };
                 } TAxiWrFilt_ProtMask2;
    typedef union  TAxiWrFilt_ProtAddr3
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtAddr3;
                   };
                 } TAxiWrFilt_ProtAddr3;
    typedef union  TAxiWrFilt_ProtMask3
          { UNSG32 u32[1];
            struct {
            struct w32AxiWrFilt_ProtMask3;
                   };
                 } TAxiWrFilt_ProtMask3;

    ///////////////////////////////////////////////////////////
     SIGN32 AxiWrFilt_drvrd(SIE_AxiWrFilt *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxiWrFilt_drvwr(SIE_AxiWrFilt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxiWrFilt_reset(SIE_AxiWrFilt *p);
     SIGN32 AxiWrFilt_cmp  (SIE_AxiWrFilt *p, SIE_AxiWrFilt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxiWrFilt_check(p,pie,pfx,hLOG) AxiWrFilt_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxiWrFilt_print(p,    pfx,hLOG) AxiWrFilt_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxiWrFilt
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE AxiPCnt                 biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P)
///               %unsigned 1  clear                     0x0
///                                    ###
///                                    * Clears the counters
///                                    ###
///               %unsigned 1  enable                    0x0
///                                    ###
///                                    * Enable counter increment. SW can make enable = 0 to temporarily disable counter increment.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00004 TOTAL_CNT            (R-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Total no. of AXI clocks
///                                    ###
///     @ 0x00008 RWAIT_CNT            (R-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks aRValid = 1 & aRReady = 0
///                                    ###
///     @ 0x0000C RDATA_CNT            (R-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks rValid = 1 & rReady = 1
///                                    ###
///     @ 0x00010 WWAIT_CNT            (R-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks aWValid = 1 & aWReady = 0
///                                    ###
///     @ 0x00014 WDATA_CNT            (R-)
///               %unsigned 32 cnt                       0x0
///                                    ###
///                                    * Counts the no.of clocks wValid = 1 & wReady = 1
///                                    ###
///     @ 0x00018 OF_STATUS            (R-)
///               %unsigned 1  total                     0x0
///               %unsigned 1  rwait                     0x0
///               %unsigned 1  rdata                     0x0
///               %unsigned 1  wwait                     0x0
///               %unsigned 1  wdata                     0x0
///                                    ###
///                                    * Overflow status of total, wait and data counters. Clear will clear the overflow status as well.
///                                    ###
///               %%        27         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      28B, bits:     167b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_AxiPCnt
#define h_AxiPCnt (){}

    #define     RA_AxiPCnt_CTRL                                0x0000

    #define     BA_AxiPCnt_CTRL_clear                          0x0000
    #define     B16AxiPCnt_CTRL_clear                          0x0000
    #define   LSb32AxiPCnt_CTRL_clear                             0
    #define   LSb16AxiPCnt_CTRL_clear                             0
    #define       bAxiPCnt_CTRL_clear                          1
    #define   MSK32AxiPCnt_CTRL_clear                             0x00000001

    #define     BA_AxiPCnt_CTRL_enable                         0x0000
    #define     B16AxiPCnt_CTRL_enable                         0x0000
    #define   LSb32AxiPCnt_CTRL_enable                            1
    #define   LSb16AxiPCnt_CTRL_enable                            1
    #define       bAxiPCnt_CTRL_enable                         1
    #define   MSK32AxiPCnt_CTRL_enable                            0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCnt_TOTAL_CNT                           0x0004

    #define     BA_AxiPCnt_TOTAL_CNT_cnt                       0x0004
    #define     B16AxiPCnt_TOTAL_CNT_cnt                       0x0004
    #define   LSb32AxiPCnt_TOTAL_CNT_cnt                          0
    #define   LSb16AxiPCnt_TOTAL_CNT_cnt                          0
    #define       bAxiPCnt_TOTAL_CNT_cnt                       32
    #define   MSK32AxiPCnt_TOTAL_CNT_cnt                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCnt_RWAIT_CNT                           0x0008

    #define     BA_AxiPCnt_RWAIT_CNT_cnt                       0x0008
    #define     B16AxiPCnt_RWAIT_CNT_cnt                       0x0008
    #define   LSb32AxiPCnt_RWAIT_CNT_cnt                          0
    #define   LSb16AxiPCnt_RWAIT_CNT_cnt                          0
    #define       bAxiPCnt_RWAIT_CNT_cnt                       32
    #define   MSK32AxiPCnt_RWAIT_CNT_cnt                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCnt_RDATA_CNT                           0x000C

    #define     BA_AxiPCnt_RDATA_CNT_cnt                       0x000C
    #define     B16AxiPCnt_RDATA_CNT_cnt                       0x000C
    #define   LSb32AxiPCnt_RDATA_CNT_cnt                          0
    #define   LSb16AxiPCnt_RDATA_CNT_cnt                          0
    #define       bAxiPCnt_RDATA_CNT_cnt                       32
    #define   MSK32AxiPCnt_RDATA_CNT_cnt                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCnt_WWAIT_CNT                           0x0010

    #define     BA_AxiPCnt_WWAIT_CNT_cnt                       0x0010
    #define     B16AxiPCnt_WWAIT_CNT_cnt                       0x0010
    #define   LSb32AxiPCnt_WWAIT_CNT_cnt                          0
    #define   LSb16AxiPCnt_WWAIT_CNT_cnt                          0
    #define       bAxiPCnt_WWAIT_CNT_cnt                       32
    #define   MSK32AxiPCnt_WWAIT_CNT_cnt                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCnt_WDATA_CNT                           0x0014

    #define     BA_AxiPCnt_WDATA_CNT_cnt                       0x0014
    #define     B16AxiPCnt_WDATA_CNT_cnt                       0x0014
    #define   LSb32AxiPCnt_WDATA_CNT_cnt                          0
    #define   LSb16AxiPCnt_WDATA_CNT_cnt                          0
    #define       bAxiPCnt_WDATA_CNT_cnt                       32
    #define   MSK32AxiPCnt_WDATA_CNT_cnt                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_AxiPCnt_OF_STATUS                           0x0018

    #define     BA_AxiPCnt_OF_STATUS_total                     0x0018
    #define     B16AxiPCnt_OF_STATUS_total                     0x0018
    #define   LSb32AxiPCnt_OF_STATUS_total                        0
    #define   LSb16AxiPCnt_OF_STATUS_total                        0
    #define       bAxiPCnt_OF_STATUS_total                     1
    #define   MSK32AxiPCnt_OF_STATUS_total                        0x00000001

    #define     BA_AxiPCnt_OF_STATUS_rwait                     0x0018
    #define     B16AxiPCnt_OF_STATUS_rwait                     0x0018
    #define   LSb32AxiPCnt_OF_STATUS_rwait                        1
    #define   LSb16AxiPCnt_OF_STATUS_rwait                        1
    #define       bAxiPCnt_OF_STATUS_rwait                     1
    #define   MSK32AxiPCnt_OF_STATUS_rwait                        0x00000002

    #define     BA_AxiPCnt_OF_STATUS_rdata                     0x0018
    #define     B16AxiPCnt_OF_STATUS_rdata                     0x0018
    #define   LSb32AxiPCnt_OF_STATUS_rdata                        2
    #define   LSb16AxiPCnt_OF_STATUS_rdata                        2
    #define       bAxiPCnt_OF_STATUS_rdata                     1
    #define   MSK32AxiPCnt_OF_STATUS_rdata                        0x00000004

    #define     BA_AxiPCnt_OF_STATUS_wwait                     0x0018
    #define     B16AxiPCnt_OF_STATUS_wwait                     0x0018
    #define   LSb32AxiPCnt_OF_STATUS_wwait                        3
    #define   LSb16AxiPCnt_OF_STATUS_wwait                        3
    #define       bAxiPCnt_OF_STATUS_wwait                     1
    #define   MSK32AxiPCnt_OF_STATUS_wwait                        0x00000008

    #define     BA_AxiPCnt_OF_STATUS_wdata                     0x0018
    #define     B16AxiPCnt_OF_STATUS_wdata                     0x0018
    #define   LSb32AxiPCnt_OF_STATUS_wdata                        4
    #define   LSb16AxiPCnt_OF_STATUS_wdata                        4
    #define       bAxiPCnt_OF_STATUS_wdata                     1
    #define   MSK32AxiPCnt_OF_STATUS_wdata                        0x00000010
    ///////////////////////////////////////////////////////////

    typedef struct SIE_AxiPCnt {
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_CTRL_clear(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32AxiPCnt_CTRL_clear(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16AxiPCnt_CTRL_clear(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16AxiPCnt_CTRL_clear(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32AxiPCnt_CTRL_enable(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32AxiPCnt_CTRL_enable(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16AxiPCnt_CTRL_enable(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16AxiPCnt_CTRL_enable(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define     w32AxiPCnt_CTRL                                {\
            UNSG32 uCTRL_clear                                 :  1;\
            UNSG32 uCTRL_enable                                :  1;\
            UNSG32 RSVDx0_b2                                   : 30;\
          }
    union { UNSG32 u32AxiPCnt_CTRL;
            struct w32AxiPCnt_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_TOTAL_CNT_cnt(r32)                  _BFGET_(r32,31, 0)
    #define   SET32AxiPCnt_TOTAL_CNT_cnt(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32AxiPCnt_TOTAL_CNT                           {\
            UNSG32 uTOTAL_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCnt_TOTAL_CNT;
            struct w32AxiPCnt_TOTAL_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_RWAIT_CNT_cnt(r32)                  _BFGET_(r32,31, 0)
    #define   SET32AxiPCnt_RWAIT_CNT_cnt(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32AxiPCnt_RWAIT_CNT                           {\
            UNSG32 uRWAIT_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCnt_RWAIT_CNT;
            struct w32AxiPCnt_RWAIT_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_RDATA_CNT_cnt(r32)                  _BFGET_(r32,31, 0)
    #define   SET32AxiPCnt_RDATA_CNT_cnt(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32AxiPCnt_RDATA_CNT                           {\
            UNSG32 uRDATA_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCnt_RDATA_CNT;
            struct w32AxiPCnt_RDATA_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_WWAIT_CNT_cnt(r32)                  _BFGET_(r32,31, 0)
    #define   SET32AxiPCnt_WWAIT_CNT_cnt(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32AxiPCnt_WWAIT_CNT                           {\
            UNSG32 uWWAIT_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCnt_WWAIT_CNT;
            struct w32AxiPCnt_WWAIT_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_WDATA_CNT_cnt(r32)                  _BFGET_(r32,31, 0)
    #define   SET32AxiPCnt_WDATA_CNT_cnt(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32AxiPCnt_WDATA_CNT                           {\
            UNSG32 uWDATA_CNT_cnt                              : 32;\
          }
    union { UNSG32 u32AxiPCnt_WDATA_CNT;
            struct w32AxiPCnt_WDATA_CNT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32AxiPCnt_OF_STATUS_total(r32)                _BFGET_(r32, 0, 0)
    #define   SET32AxiPCnt_OF_STATUS_total(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16AxiPCnt_OF_STATUS_total(r16)                _BFGET_(r16, 0, 0)
    #define   SET16AxiPCnt_OF_STATUS_total(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32AxiPCnt_OF_STATUS_rwait(r32)                _BFGET_(r32, 1, 1)
    #define   SET32AxiPCnt_OF_STATUS_rwait(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16AxiPCnt_OF_STATUS_rwait(r16)                _BFGET_(r16, 1, 1)
    #define   SET16AxiPCnt_OF_STATUS_rwait(r16,v)              _BFSET_(r16, 1, 1,v)

    #define   GET32AxiPCnt_OF_STATUS_rdata(r32)                _BFGET_(r32, 2, 2)
    #define   SET32AxiPCnt_OF_STATUS_rdata(r32,v)              _BFSET_(r32, 2, 2,v)
    #define   GET16AxiPCnt_OF_STATUS_rdata(r16)                _BFGET_(r16, 2, 2)
    #define   SET16AxiPCnt_OF_STATUS_rdata(r16,v)              _BFSET_(r16, 2, 2,v)

    #define   GET32AxiPCnt_OF_STATUS_wwait(r32)                _BFGET_(r32, 3, 3)
    #define   SET32AxiPCnt_OF_STATUS_wwait(r32,v)              _BFSET_(r32, 3, 3,v)
    #define   GET16AxiPCnt_OF_STATUS_wwait(r16)                _BFGET_(r16, 3, 3)
    #define   SET16AxiPCnt_OF_STATUS_wwait(r16,v)              _BFSET_(r16, 3, 3,v)

    #define   GET32AxiPCnt_OF_STATUS_wdata(r32)                _BFGET_(r32, 4, 4)
    #define   SET32AxiPCnt_OF_STATUS_wdata(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16AxiPCnt_OF_STATUS_wdata(r16)                _BFGET_(r16, 4, 4)
    #define   SET16AxiPCnt_OF_STATUS_wdata(r16,v)              _BFSET_(r16, 4, 4,v)

    #define     w32AxiPCnt_OF_STATUS                           {\
            UNSG32 uOF_STATUS_total                            :  1;\
            UNSG32 uOF_STATUS_rwait                            :  1;\
            UNSG32 uOF_STATUS_rdata                            :  1;\
            UNSG32 uOF_STATUS_wwait                            :  1;\
            UNSG32 uOF_STATUS_wdata                            :  1;\
            UNSG32 RSVDx18_b5                                  : 27;\
          }
    union { UNSG32 u32AxiPCnt_OF_STATUS;
            struct w32AxiPCnt_OF_STATUS;
          };
    ///////////////////////////////////////////////////////////
    } SIE_AxiPCnt;

    typedef union  T32AxiPCnt_CTRL
          { UNSG32 u32;
            struct w32AxiPCnt_CTRL;
                 } T32AxiPCnt_CTRL;
    typedef union  T32AxiPCnt_TOTAL_CNT
          { UNSG32 u32;
            struct w32AxiPCnt_TOTAL_CNT;
                 } T32AxiPCnt_TOTAL_CNT;
    typedef union  T32AxiPCnt_RWAIT_CNT
          { UNSG32 u32;
            struct w32AxiPCnt_RWAIT_CNT;
                 } T32AxiPCnt_RWAIT_CNT;
    typedef union  T32AxiPCnt_RDATA_CNT
          { UNSG32 u32;
            struct w32AxiPCnt_RDATA_CNT;
                 } T32AxiPCnt_RDATA_CNT;
    typedef union  T32AxiPCnt_WWAIT_CNT
          { UNSG32 u32;
            struct w32AxiPCnt_WWAIT_CNT;
                 } T32AxiPCnt_WWAIT_CNT;
    typedef union  T32AxiPCnt_WDATA_CNT
          { UNSG32 u32;
            struct w32AxiPCnt_WDATA_CNT;
                 } T32AxiPCnt_WDATA_CNT;
    typedef union  T32AxiPCnt_OF_STATUS
          { UNSG32 u32;
            struct w32AxiPCnt_OF_STATUS;
                 } T32AxiPCnt_OF_STATUS;
    ///////////////////////////////////////////////////////////

    typedef union  TAxiPCnt_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_CTRL;
                   };
                 } TAxiPCnt_CTRL;
    typedef union  TAxiPCnt_TOTAL_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_TOTAL_CNT;
                   };
                 } TAxiPCnt_TOTAL_CNT;
    typedef union  TAxiPCnt_RWAIT_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_RWAIT_CNT;
                   };
                 } TAxiPCnt_RWAIT_CNT;
    typedef union  TAxiPCnt_RDATA_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_RDATA_CNT;
                   };
                 } TAxiPCnt_RDATA_CNT;
    typedef union  TAxiPCnt_WWAIT_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_WWAIT_CNT;
                   };
                 } TAxiPCnt_WWAIT_CNT;
    typedef union  TAxiPCnt_WDATA_CNT
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_WDATA_CNT;
                   };
                 } TAxiPCnt_WDATA_CNT;
    typedef union  TAxiPCnt_OF_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32AxiPCnt_OF_STATUS;
                   };
                 } TAxiPCnt_OF_STATUS;

    ///////////////////////////////////////////////////////////
     SIGN32 AxiPCnt_drvrd(SIE_AxiPCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 AxiPCnt_drvwr(SIE_AxiPCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void AxiPCnt_reset(SIE_AxiPCnt *p);
     SIGN32 AxiPCnt_cmp  (SIE_AxiPCnt *p, SIE_AxiPCnt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define AxiPCnt_check(p,pie,pfx,hLOG) AxiPCnt_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define AxiPCnt_print(p,    pfx,hLOG) AxiPCnt_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: AxiPCnt
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE SOC                     biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 Configuration        (P)
///               ###
///               * SoC miscellaneous control register
///               ###
///               %unsigned 1  blockIFetch               0x0
///                                    ###
///                                    * 1: block instruction access except SDRAM, DRM TCM, ROM, SPI
///                                    * 0: allow instruction access to all region.
///                                    ###
///               %unsigned 1  AhbTrcEn                  0x0
///                                    ###
///                                    * 0: Disables the AHB Trace Monitor (Bmon)
///                                    * 1: Enables the AHB Trace Monitor (Bmon)
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00004 sysIntPol0           (P)
///               %unsigned 32 Invert                    0x0
///                                    ###
///                                    * One bit per interrupt source, interrupt position follows IRQ table defined.
///                                    * Controls bit [31:0] of interrupt sources
///                                    * 0: Don't invert before sending to GIC
///                                    * 1: Invert before sending to GIC
///                                    ###
///     @ 0x00008 sysIntPol1           (P)
///               %unsigned 32 Invert                    0x0
///                                    ###
///                                    * One bit per interrupt source, interrupt position follows IRQ table defined.
///                                    * Controls bit [63:32] of interrupt sources
///                                    * 0: Don't invert before sending to GIC
///                                    * 1: Invert before sending to GIC
///                                    ###
///     @ 0x0000C sysIntPol2           (P)
///               %unsigned 32 Invert                    0x0
///                                    ###
///                                    * One bit per interrupt source, interrupt position follows IRQ table defined.
///                                    * Controls bit [95:64] of interrupt sources
///                                    * 0: Don't invert before sending to GIC
///                                    * 1: Invert before sending to GIC
///                                    ###
///     @ 0x00010 sysIntPol3           (P)
///               %unsigned 32 Invert                    0x0
///                                    ###
///                                    * One bit per interrupt source, interrupt position follows IRQ table defined.
///                                    * Controls bit [127:96] of interrupt sources
///                                    * 0: Don't invert before sending to GIC
///                                    * 1: Invert before sending to GIC
///                                    ###
///     @ 0x00014 Dummy_SW_Intr        (P)
///               %unsigned 1  Intr0                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr1                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr2                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr3                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr4                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr5                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr6                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %unsigned 1  Intr7                     0x0
///                                    ###
///                                    * Dummy sw interrupt source to GIC
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00018                      (W-)
///     #         # Stuffing bytes...
///               %% 1856
///     @ 0x00100 AHB_RESP_CTRL        (P)
///               %unsigned 1  MaskHrespDef              0x0
///                                    ###
///                                    * Config register access that does not decode into a valid AHB slave (a “hole”) will
///                                    * 0: Return an ERROR response.
///                                    * 1: Return an OKAY response
///                                    ###
///               %unsigned 1  MaskHrespSe               0x0
///               %%        30         # Stuffing bits...
///     @ 0x00104 AXI_BRESP_CTRL       (P)
///               ###
///               * 0: bresp[1] is passed to AXI master unaltered
///               * 1: force bresp[1] to 0
///               ###
///               %unsigned 1  CPU                       0x0
///               %unsigned 1  AVIOM0                    0x0
///               %unsigned 1  IMTEST                    0x0
///               %unsigned 1  BMON                      0x0
///               %unsigned 1  NNA                       0x0
///               %unsigned 1  USBM0                     0x0
///               %unsigned 1  SDIO                      0x0
///               %unsigned 1  NANDEMMC                  0x0
///               %unsigned 1  PCIE0                     0x0
///               %unsigned 1  PCIE1                     0x0
///               %unsigned 1  PB                        0x0
///               %unsigned 1  BCMCPU                    0x0
///               %unsigned 1  BCMDMA                    0x0
///               %unsigned 1  BCMDIR                    0x0
///               %%        18         # Stuffing bits...
///     @ 0x00108 AXI_RRESP_CTRL       (P)
///               ###
///               * 0: rresp[1] is passed to AXI master unaltered
///               * 1: force rresp[1] to 0
///               ###
///               %unsigned 1  CPU                       0x0
///               %unsigned 1  AVIOM0                    0x0
///               %unsigned 1  IMTEST                    0x0
///               %unsigned 1  BMON                      0x0
///               %unsigned 1  NNA                       0x0
///               %unsigned 1  NANDEMMC                  0x0
///               %unsigned 1  USBM0                     0x0
///               %unsigned 1  SDIO                      0x0
///               %unsigned 1  PCIE0                     0x0
///               %unsigned 1  PCIE1                     0x0
///               %unsigned 1  PB                        0x0
///               %unsigned 1  BCMCPU                    0x0
///               %unsigned 1  BCMDMA                    0x0
///               %unsigned 1  BCMDIR                    0x0
///               %%        18         # Stuffing bits...
///     @ 0x0010C GFX_QOS_CTRL         (P)
///               %unsigned 1  wqos_enable               0x0
///               %unsigned 4  wqos_value0               0x0
///               %unsigned 4  wqos_value1               0x0
///               %unsigned 1  rqos_enable               0x0
///               %unsigned 4  rqos_value0               0x0
///               %unsigned 4  rqos_value1               0x0
///               %%        14         # Stuffing bits...
///     @ 0x00110 OVP_QOS_CTRL         (P)
///               %unsigned 4  wqos_value                0x0
///               %unsigned 4  rqos_value                0x0
///               %%        24         # Stuffing bits...
///     @ 0x00114                      (P)
///     # 0x00114 cacheOR              
///               $cacheOR             cacheOR           REG          
///                                    ###
///                                    * Below address space from 0x1000 - 0x1FFF is a default Secure Master Access only Region. Dont add registers not requiring this feature in this address range.
///                                    ###
///     @ 0x00124                      (W-)
///     #         # Stuffing bytes...
///               %% 30432
///     @ 0x01000                      (P)
///     # 0x01000 protOR               
///               $protOR              protOR            REG          
///                                    ###
///                                    * AxPROT override controls
///                                    ###
///     @ 0x01038                      (W-)
///     #         # Stuffing bytes...
///               %% 1600
///     @ 0x01100                      (P)
///     # 0x01100 RestrictZone         
///               $RestrictZone        RestrictZone      REG          
///     @ 0x01138                      (W-)
///     #         # Stuffing bytes...
///               %% 1600
///     @ 0x01200                      (P)
///     # 0x01200 SecureRegionCtrl0    
///               $seRegionX           SecureRegionCtrl0 REG          
///     @ 0x01260                      (W-)
///     #         # Stuffing bytes...
///               %% 1280
///     @ 0x01300                      (P)
///     # 0x01300 SecureRegionCtrl1    
///               $seRegionX           SecureRegionCtrl1 REG          
///     @ 0x01360                      (W-)
///     #         # Stuffing bytes...
///               %% 1280
///     @ 0x01400                      (P)
///     # 0x01400 SecureRegionCtrl2    
///               $seRegionX           SecureRegionCtrl2 REG          
///     @ 0x01460                      (W-)
///     #         # Stuffing bytes...
///               %% 1280
///     @ 0x01500                      (P)
///     # 0x01500 defSecureRegionCtrl0 
///               $defSeRegionX        defSecureRegionCtrl0 REG          
///                                    ###
///                                    * Secure Region Registers
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:    5388B, bits:    2095b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_SOC
#define h_SOC (){}

    #define     RA_SOC_Configuration                           0x0000

    #define     BA_SOC_Configuration_blockIFetch               0x0000
    #define     B16SOC_Configuration_blockIFetch               0x0000
    #define   LSb32SOC_Configuration_blockIFetch                  0
    #define   LSb16SOC_Configuration_blockIFetch                  0
    #define       bSOC_Configuration_blockIFetch               1
    #define   MSK32SOC_Configuration_blockIFetch                  0x00000001

    #define     BA_SOC_Configuration_AhbTrcEn                  0x0000
    #define     B16SOC_Configuration_AhbTrcEn                  0x0000
    #define   LSb32SOC_Configuration_AhbTrcEn                     1
    #define   LSb16SOC_Configuration_AhbTrcEn                     1
    #define       bSOC_Configuration_AhbTrcEn                  1
    #define   MSK32SOC_Configuration_AhbTrcEn                     0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_sysIntPol0                              0x0004

    #define     BA_SOC_sysIntPol0_Invert                       0x0004
    #define     B16SOC_sysIntPol0_Invert                       0x0004
    #define   LSb32SOC_sysIntPol0_Invert                          0
    #define   LSb16SOC_sysIntPol0_Invert                          0
    #define       bSOC_sysIntPol0_Invert                       32
    #define   MSK32SOC_sysIntPol0_Invert                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_sysIntPol1                              0x0008

    #define     BA_SOC_sysIntPol1_Invert                       0x0008
    #define     B16SOC_sysIntPol1_Invert                       0x0008
    #define   LSb32SOC_sysIntPol1_Invert                          0
    #define   LSb16SOC_sysIntPol1_Invert                          0
    #define       bSOC_sysIntPol1_Invert                       32
    #define   MSK32SOC_sysIntPol1_Invert                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_sysIntPol2                              0x000C

    #define     BA_SOC_sysIntPol2_Invert                       0x000C
    #define     B16SOC_sysIntPol2_Invert                       0x000C
    #define   LSb32SOC_sysIntPol2_Invert                          0
    #define   LSb16SOC_sysIntPol2_Invert                          0
    #define       bSOC_sysIntPol2_Invert                       32
    #define   MSK32SOC_sysIntPol2_Invert                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_sysIntPol3                              0x0010

    #define     BA_SOC_sysIntPol3_Invert                       0x0010
    #define     B16SOC_sysIntPol3_Invert                       0x0010
    #define   LSb32SOC_sysIntPol3_Invert                          0
    #define   LSb16SOC_sysIntPol3_Invert                          0
    #define       bSOC_sysIntPol3_Invert                       32
    #define   MSK32SOC_sysIntPol3_Invert                          0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_Dummy_SW_Intr                           0x0014

    #define     BA_SOC_Dummy_SW_Intr_Intr0                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr0                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr0                        0
    #define   LSb16SOC_Dummy_SW_Intr_Intr0                        0
    #define       bSOC_Dummy_SW_Intr_Intr0                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr0                        0x00000001

    #define     BA_SOC_Dummy_SW_Intr_Intr1                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr1                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr1                        1
    #define   LSb16SOC_Dummy_SW_Intr_Intr1                        1
    #define       bSOC_Dummy_SW_Intr_Intr1                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr1                        0x00000002

    #define     BA_SOC_Dummy_SW_Intr_Intr2                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr2                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr2                        2
    #define   LSb16SOC_Dummy_SW_Intr_Intr2                        2
    #define       bSOC_Dummy_SW_Intr_Intr2                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr2                        0x00000004

    #define     BA_SOC_Dummy_SW_Intr_Intr3                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr3                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr3                        3
    #define   LSb16SOC_Dummy_SW_Intr_Intr3                        3
    #define       bSOC_Dummy_SW_Intr_Intr3                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr3                        0x00000008

    #define     BA_SOC_Dummy_SW_Intr_Intr4                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr4                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr4                        4
    #define   LSb16SOC_Dummy_SW_Intr_Intr4                        4
    #define       bSOC_Dummy_SW_Intr_Intr4                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr4                        0x00000010

    #define     BA_SOC_Dummy_SW_Intr_Intr5                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr5                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr5                        5
    #define   LSb16SOC_Dummy_SW_Intr_Intr5                        5
    #define       bSOC_Dummy_SW_Intr_Intr5                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr5                        0x00000020

    #define     BA_SOC_Dummy_SW_Intr_Intr6                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr6                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr6                        6
    #define   LSb16SOC_Dummy_SW_Intr_Intr6                        6
    #define       bSOC_Dummy_SW_Intr_Intr6                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr6                        0x00000040

    #define     BA_SOC_Dummy_SW_Intr_Intr7                     0x0014
    #define     B16SOC_Dummy_SW_Intr_Intr7                     0x0014
    #define   LSb32SOC_Dummy_SW_Intr_Intr7                        7
    #define   LSb16SOC_Dummy_SW_Intr_Intr7                        7
    #define       bSOC_Dummy_SW_Intr_Intr7                     1
    #define   MSK32SOC_Dummy_SW_Intr_Intr7                        0x00000080
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_AHB_RESP_CTRL                           0x0100

    #define     BA_SOC_AHB_RESP_CTRL_MaskHrespDef              0x0100
    #define     B16SOC_AHB_RESP_CTRL_MaskHrespDef              0x0100
    #define   LSb32SOC_AHB_RESP_CTRL_MaskHrespDef                 0
    #define   LSb16SOC_AHB_RESP_CTRL_MaskHrespDef                 0
    #define       bSOC_AHB_RESP_CTRL_MaskHrespDef              1
    #define   MSK32SOC_AHB_RESP_CTRL_MaskHrespDef                 0x00000001

    #define     BA_SOC_AHB_RESP_CTRL_MaskHrespSe               0x0100
    #define     B16SOC_AHB_RESP_CTRL_MaskHrespSe               0x0100
    #define   LSb32SOC_AHB_RESP_CTRL_MaskHrespSe                  1
    #define   LSb16SOC_AHB_RESP_CTRL_MaskHrespSe                  1
    #define       bSOC_AHB_RESP_CTRL_MaskHrespSe               1
    #define   MSK32SOC_AHB_RESP_CTRL_MaskHrespSe                  0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_AXI_BRESP_CTRL                          0x0104

    #define     BA_SOC_AXI_BRESP_CTRL_CPU                      0x0104
    #define     B16SOC_AXI_BRESP_CTRL_CPU                      0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_CPU                         0
    #define   LSb16SOC_AXI_BRESP_CTRL_CPU                         0
    #define       bSOC_AXI_BRESP_CTRL_CPU                      1
    #define   MSK32SOC_AXI_BRESP_CTRL_CPU                         0x00000001

    #define     BA_SOC_AXI_BRESP_CTRL_AVIOM0                   0x0104
    #define     B16SOC_AXI_BRESP_CTRL_AVIOM0                   0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_AVIOM0                      1
    #define   LSb16SOC_AXI_BRESP_CTRL_AVIOM0                      1
    #define       bSOC_AXI_BRESP_CTRL_AVIOM0                   1
    #define   MSK32SOC_AXI_BRESP_CTRL_AVIOM0                      0x00000002

    #define     BA_SOC_AXI_BRESP_CTRL_IMTEST                   0x0104
    #define     B16SOC_AXI_BRESP_CTRL_IMTEST                   0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_IMTEST                      2
    #define   LSb16SOC_AXI_BRESP_CTRL_IMTEST                      2
    #define       bSOC_AXI_BRESP_CTRL_IMTEST                   1
    #define   MSK32SOC_AXI_BRESP_CTRL_IMTEST                      0x00000004

    #define     BA_SOC_AXI_BRESP_CTRL_BMON                     0x0104
    #define     B16SOC_AXI_BRESP_CTRL_BMON                     0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_BMON                        3
    #define   LSb16SOC_AXI_BRESP_CTRL_BMON                        3
    #define       bSOC_AXI_BRESP_CTRL_BMON                     1
    #define   MSK32SOC_AXI_BRESP_CTRL_BMON                        0x00000008

    #define     BA_SOC_AXI_BRESP_CTRL_NNA                      0x0104
    #define     B16SOC_AXI_BRESP_CTRL_NNA                      0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_NNA                         4
    #define   LSb16SOC_AXI_BRESP_CTRL_NNA                         4
    #define       bSOC_AXI_BRESP_CTRL_NNA                      1
    #define   MSK32SOC_AXI_BRESP_CTRL_NNA                         0x00000010

    #define     BA_SOC_AXI_BRESP_CTRL_USBM0                    0x0104
    #define     B16SOC_AXI_BRESP_CTRL_USBM0                    0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_USBM0                       5
    #define   LSb16SOC_AXI_BRESP_CTRL_USBM0                       5
    #define       bSOC_AXI_BRESP_CTRL_USBM0                    1
    #define   MSK32SOC_AXI_BRESP_CTRL_USBM0                       0x00000020

    #define     BA_SOC_AXI_BRESP_CTRL_SDIO                     0x0104
    #define     B16SOC_AXI_BRESP_CTRL_SDIO                     0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_SDIO                        6
    #define   LSb16SOC_AXI_BRESP_CTRL_SDIO                        6
    #define       bSOC_AXI_BRESP_CTRL_SDIO                     1
    #define   MSK32SOC_AXI_BRESP_CTRL_SDIO                        0x00000040

    #define     BA_SOC_AXI_BRESP_CTRL_NANDEMMC                 0x0104
    #define     B16SOC_AXI_BRESP_CTRL_NANDEMMC                 0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_NANDEMMC                    7
    #define   LSb16SOC_AXI_BRESP_CTRL_NANDEMMC                    7
    #define       bSOC_AXI_BRESP_CTRL_NANDEMMC                 1
    #define   MSK32SOC_AXI_BRESP_CTRL_NANDEMMC                    0x00000080

    #define     BA_SOC_AXI_BRESP_CTRL_PCIE0                    0x0105
    #define     B16SOC_AXI_BRESP_CTRL_PCIE0                    0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_PCIE0                       8
    #define   LSb16SOC_AXI_BRESP_CTRL_PCIE0                       8
    #define       bSOC_AXI_BRESP_CTRL_PCIE0                    1
    #define   MSK32SOC_AXI_BRESP_CTRL_PCIE0                       0x00000100

    #define     BA_SOC_AXI_BRESP_CTRL_PCIE1                    0x0105
    #define     B16SOC_AXI_BRESP_CTRL_PCIE1                    0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_PCIE1                       9
    #define   LSb16SOC_AXI_BRESP_CTRL_PCIE1                       9
    #define       bSOC_AXI_BRESP_CTRL_PCIE1                    1
    #define   MSK32SOC_AXI_BRESP_CTRL_PCIE1                       0x00000200

    #define     BA_SOC_AXI_BRESP_CTRL_PB                       0x0105
    #define     B16SOC_AXI_BRESP_CTRL_PB                       0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_PB                          10
    #define   LSb16SOC_AXI_BRESP_CTRL_PB                          10
    #define       bSOC_AXI_BRESP_CTRL_PB                       1
    #define   MSK32SOC_AXI_BRESP_CTRL_PB                          0x00000400

    #define     BA_SOC_AXI_BRESP_CTRL_BCMCPU                   0x0105
    #define     B16SOC_AXI_BRESP_CTRL_BCMCPU                   0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_BCMCPU                      11
    #define   LSb16SOC_AXI_BRESP_CTRL_BCMCPU                      11
    #define       bSOC_AXI_BRESP_CTRL_BCMCPU                   1
    #define   MSK32SOC_AXI_BRESP_CTRL_BCMCPU                      0x00000800

    #define     BA_SOC_AXI_BRESP_CTRL_BCMDMA                   0x0105
    #define     B16SOC_AXI_BRESP_CTRL_BCMDMA                   0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_BCMDMA                      12
    #define   LSb16SOC_AXI_BRESP_CTRL_BCMDMA                      12
    #define       bSOC_AXI_BRESP_CTRL_BCMDMA                   1
    #define   MSK32SOC_AXI_BRESP_CTRL_BCMDMA                      0x00001000

    #define     BA_SOC_AXI_BRESP_CTRL_BCMDIR                   0x0105
    #define     B16SOC_AXI_BRESP_CTRL_BCMDIR                   0x0104
    #define   LSb32SOC_AXI_BRESP_CTRL_BCMDIR                      13
    #define   LSb16SOC_AXI_BRESP_CTRL_BCMDIR                      13
    #define       bSOC_AXI_BRESP_CTRL_BCMDIR                   1
    #define   MSK32SOC_AXI_BRESP_CTRL_BCMDIR                      0x00002000
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_AXI_RRESP_CTRL                          0x0108

    #define     BA_SOC_AXI_RRESP_CTRL_CPU                      0x0108
    #define     B16SOC_AXI_RRESP_CTRL_CPU                      0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_CPU                         0
    #define   LSb16SOC_AXI_RRESP_CTRL_CPU                         0
    #define       bSOC_AXI_RRESP_CTRL_CPU                      1
    #define   MSK32SOC_AXI_RRESP_CTRL_CPU                         0x00000001

    #define     BA_SOC_AXI_RRESP_CTRL_AVIOM0                   0x0108
    #define     B16SOC_AXI_RRESP_CTRL_AVIOM0                   0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_AVIOM0                      1
    #define   LSb16SOC_AXI_RRESP_CTRL_AVIOM0                      1
    #define       bSOC_AXI_RRESP_CTRL_AVIOM0                   1
    #define   MSK32SOC_AXI_RRESP_CTRL_AVIOM0                      0x00000002

    #define     BA_SOC_AXI_RRESP_CTRL_IMTEST                   0x0108
    #define     B16SOC_AXI_RRESP_CTRL_IMTEST                   0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_IMTEST                      2
    #define   LSb16SOC_AXI_RRESP_CTRL_IMTEST                      2
    #define       bSOC_AXI_RRESP_CTRL_IMTEST                   1
    #define   MSK32SOC_AXI_RRESP_CTRL_IMTEST                      0x00000004

    #define     BA_SOC_AXI_RRESP_CTRL_BMON                     0x0108
    #define     B16SOC_AXI_RRESP_CTRL_BMON                     0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_BMON                        3
    #define   LSb16SOC_AXI_RRESP_CTRL_BMON                        3
    #define       bSOC_AXI_RRESP_CTRL_BMON                     1
    #define   MSK32SOC_AXI_RRESP_CTRL_BMON                        0x00000008

    #define     BA_SOC_AXI_RRESP_CTRL_NNA                      0x0108
    #define     B16SOC_AXI_RRESP_CTRL_NNA                      0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_NNA                         4
    #define   LSb16SOC_AXI_RRESP_CTRL_NNA                         4
    #define       bSOC_AXI_RRESP_CTRL_NNA                      1
    #define   MSK32SOC_AXI_RRESP_CTRL_NNA                         0x00000010

    #define     BA_SOC_AXI_RRESP_CTRL_NANDEMMC                 0x0108
    #define     B16SOC_AXI_RRESP_CTRL_NANDEMMC                 0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_NANDEMMC                    5
    #define   LSb16SOC_AXI_RRESP_CTRL_NANDEMMC                    5
    #define       bSOC_AXI_RRESP_CTRL_NANDEMMC                 1
    #define   MSK32SOC_AXI_RRESP_CTRL_NANDEMMC                    0x00000020

    #define     BA_SOC_AXI_RRESP_CTRL_USBM0                    0x0108
    #define     B16SOC_AXI_RRESP_CTRL_USBM0                    0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_USBM0                       6
    #define   LSb16SOC_AXI_RRESP_CTRL_USBM0                       6
    #define       bSOC_AXI_RRESP_CTRL_USBM0                    1
    #define   MSK32SOC_AXI_RRESP_CTRL_USBM0                       0x00000040

    #define     BA_SOC_AXI_RRESP_CTRL_SDIO                     0x0108
    #define     B16SOC_AXI_RRESP_CTRL_SDIO                     0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_SDIO                        7
    #define   LSb16SOC_AXI_RRESP_CTRL_SDIO                        7
    #define       bSOC_AXI_RRESP_CTRL_SDIO                     1
    #define   MSK32SOC_AXI_RRESP_CTRL_SDIO                        0x00000080

    #define     BA_SOC_AXI_RRESP_CTRL_PCIE0                    0x0109
    #define     B16SOC_AXI_RRESP_CTRL_PCIE0                    0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_PCIE0                       8
    #define   LSb16SOC_AXI_RRESP_CTRL_PCIE0                       8
    #define       bSOC_AXI_RRESP_CTRL_PCIE0                    1
    #define   MSK32SOC_AXI_RRESP_CTRL_PCIE0                       0x00000100

    #define     BA_SOC_AXI_RRESP_CTRL_PCIE1                    0x0109
    #define     B16SOC_AXI_RRESP_CTRL_PCIE1                    0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_PCIE1                       9
    #define   LSb16SOC_AXI_RRESP_CTRL_PCIE1                       9
    #define       bSOC_AXI_RRESP_CTRL_PCIE1                    1
    #define   MSK32SOC_AXI_RRESP_CTRL_PCIE1                       0x00000200

    #define     BA_SOC_AXI_RRESP_CTRL_PB                       0x0109
    #define     B16SOC_AXI_RRESP_CTRL_PB                       0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_PB                          10
    #define   LSb16SOC_AXI_RRESP_CTRL_PB                          10
    #define       bSOC_AXI_RRESP_CTRL_PB                       1
    #define   MSK32SOC_AXI_RRESP_CTRL_PB                          0x00000400

    #define     BA_SOC_AXI_RRESP_CTRL_BCMCPU                   0x0109
    #define     B16SOC_AXI_RRESP_CTRL_BCMCPU                   0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_BCMCPU                      11
    #define   LSb16SOC_AXI_RRESP_CTRL_BCMCPU                      11
    #define       bSOC_AXI_RRESP_CTRL_BCMCPU                   1
    #define   MSK32SOC_AXI_RRESP_CTRL_BCMCPU                      0x00000800

    #define     BA_SOC_AXI_RRESP_CTRL_BCMDMA                   0x0109
    #define     B16SOC_AXI_RRESP_CTRL_BCMDMA                   0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_BCMDMA                      12
    #define   LSb16SOC_AXI_RRESP_CTRL_BCMDMA                      12
    #define       bSOC_AXI_RRESP_CTRL_BCMDMA                   1
    #define   MSK32SOC_AXI_RRESP_CTRL_BCMDMA                      0x00001000

    #define     BA_SOC_AXI_RRESP_CTRL_BCMDIR                   0x0109
    #define     B16SOC_AXI_RRESP_CTRL_BCMDIR                   0x0108
    #define   LSb32SOC_AXI_RRESP_CTRL_BCMDIR                      13
    #define   LSb16SOC_AXI_RRESP_CTRL_BCMDIR                      13
    #define       bSOC_AXI_RRESP_CTRL_BCMDIR                   1
    #define   MSK32SOC_AXI_RRESP_CTRL_BCMDIR                      0x00002000
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_GFX_QOS_CTRL                            0x010C

    #define     BA_SOC_GFX_QOS_CTRL_wqos_enable                0x010C
    #define     B16SOC_GFX_QOS_CTRL_wqos_enable                0x010C
    #define   LSb32SOC_GFX_QOS_CTRL_wqos_enable                   0
    #define   LSb16SOC_GFX_QOS_CTRL_wqos_enable                   0
    #define       bSOC_GFX_QOS_CTRL_wqos_enable                1
    #define   MSK32SOC_GFX_QOS_CTRL_wqos_enable                   0x00000001

    #define     BA_SOC_GFX_QOS_CTRL_wqos_value0                0x010C
    #define     B16SOC_GFX_QOS_CTRL_wqos_value0                0x010C
    #define   LSb32SOC_GFX_QOS_CTRL_wqos_value0                   1
    #define   LSb16SOC_GFX_QOS_CTRL_wqos_value0                   1
    #define       bSOC_GFX_QOS_CTRL_wqos_value0                4
    #define   MSK32SOC_GFX_QOS_CTRL_wqos_value0                   0x0000001E

    #define     BA_SOC_GFX_QOS_CTRL_wqos_value1                0x010C
    #define     B16SOC_GFX_QOS_CTRL_wqos_value1                0x010C
    #define   LSb32SOC_GFX_QOS_CTRL_wqos_value1                   5
    #define   LSb16SOC_GFX_QOS_CTRL_wqos_value1                   5
    #define       bSOC_GFX_QOS_CTRL_wqos_value1                4
    #define   MSK32SOC_GFX_QOS_CTRL_wqos_value1                   0x000001E0

    #define     BA_SOC_GFX_QOS_CTRL_rqos_enable                0x010D
    #define     B16SOC_GFX_QOS_CTRL_rqos_enable                0x010C
    #define   LSb32SOC_GFX_QOS_CTRL_rqos_enable                   9
    #define   LSb16SOC_GFX_QOS_CTRL_rqos_enable                   9
    #define       bSOC_GFX_QOS_CTRL_rqos_enable                1
    #define   MSK32SOC_GFX_QOS_CTRL_rqos_enable                   0x00000200

    #define     BA_SOC_GFX_QOS_CTRL_rqos_value0                0x010D
    #define     B16SOC_GFX_QOS_CTRL_rqos_value0                0x010C
    #define   LSb32SOC_GFX_QOS_CTRL_rqos_value0                   10
    #define   LSb16SOC_GFX_QOS_CTRL_rqos_value0                   10
    #define       bSOC_GFX_QOS_CTRL_rqos_value0                4
    #define   MSK32SOC_GFX_QOS_CTRL_rqos_value0                   0x00003C00

    #define     BA_SOC_GFX_QOS_CTRL_rqos_value1                0x010D
    #define     B16SOC_GFX_QOS_CTRL_rqos_value1                0x010C
    #define   LSb32SOC_GFX_QOS_CTRL_rqos_value1                   14
    #define   LSb16SOC_GFX_QOS_CTRL_rqos_value1                   14
    #define       bSOC_GFX_QOS_CTRL_rqos_value1                4
    #define   MSK32SOC_GFX_QOS_CTRL_rqos_value1                   0x0003C000
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_OVP_QOS_CTRL                            0x0110

    #define     BA_SOC_OVP_QOS_CTRL_wqos_value                 0x0110
    #define     B16SOC_OVP_QOS_CTRL_wqos_value                 0x0110
    #define   LSb32SOC_OVP_QOS_CTRL_wqos_value                    0
    #define   LSb16SOC_OVP_QOS_CTRL_wqos_value                    0
    #define       bSOC_OVP_QOS_CTRL_wqos_value                 4
    #define   MSK32SOC_OVP_QOS_CTRL_wqos_value                    0x0000000F

    #define     BA_SOC_OVP_QOS_CTRL_rqos_value                 0x0110
    #define     B16SOC_OVP_QOS_CTRL_rqos_value                 0x0110
    #define   LSb32SOC_OVP_QOS_CTRL_rqos_value                    4
    #define   LSb16SOC_OVP_QOS_CTRL_rqos_value                    4
    #define       bSOC_OVP_QOS_CTRL_rqos_value                 4
    #define   MSK32SOC_OVP_QOS_CTRL_rqos_value                    0x000000F0
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_cacheOR                                 0x0114
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_protOR                                  0x1000
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_RestrictZone                            0x1100
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_SecureRegionCtrl0                       0x1200
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_SecureRegionCtrl1                       0x1300
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_SecureRegionCtrl2                       0x1400
    ///////////////////////////////////////////////////////////
    #define     RA_SOC_defSecureRegionCtrl0                    0x1500
    ///////////////////////////////////////////////////////////

    typedef struct SIE_SOC {
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_Configuration_blockIFetch(r32)          _BFGET_(r32, 0, 0)
    #define   SET32SOC_Configuration_blockIFetch(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16SOC_Configuration_blockIFetch(r16)          _BFGET_(r16, 0, 0)
    #define   SET16SOC_Configuration_blockIFetch(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32SOC_Configuration_AhbTrcEn(r32)             _BFGET_(r32, 1, 1)
    #define   SET32SOC_Configuration_AhbTrcEn(r32,v)           _BFSET_(r32, 1, 1,v)
    #define   GET16SOC_Configuration_AhbTrcEn(r16)             _BFGET_(r16, 1, 1)
    #define   SET16SOC_Configuration_AhbTrcEn(r16,v)           _BFSET_(r16, 1, 1,v)

    #define     w32SOC_Configuration                           {\
            UNSG32 uConfiguration_blockIFetch                  :  1;\
            UNSG32 uConfiguration_AhbTrcEn                     :  1;\
            UNSG32 RSVDx0_b2                                   : 30;\
          }
    union { UNSG32 u32SOC_Configuration;
            struct w32SOC_Configuration;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_sysIntPol0_Invert(r32)                  _BFGET_(r32,31, 0)
    #define   SET32SOC_sysIntPol0_Invert(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32SOC_sysIntPol0                              {\
            UNSG32 usysIntPol0_Invert                          : 32;\
          }
    union { UNSG32 u32SOC_sysIntPol0;
            struct w32SOC_sysIntPol0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_sysIntPol1_Invert(r32)                  _BFGET_(r32,31, 0)
    #define   SET32SOC_sysIntPol1_Invert(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32SOC_sysIntPol1                              {\
            UNSG32 usysIntPol1_Invert                          : 32;\
          }
    union { UNSG32 u32SOC_sysIntPol1;
            struct w32SOC_sysIntPol1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_sysIntPol2_Invert(r32)                  _BFGET_(r32,31, 0)
    #define   SET32SOC_sysIntPol2_Invert(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32SOC_sysIntPol2                              {\
            UNSG32 usysIntPol2_Invert                          : 32;\
          }
    union { UNSG32 u32SOC_sysIntPol2;
            struct w32SOC_sysIntPol2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_sysIntPol3_Invert(r32)                  _BFGET_(r32,31, 0)
    #define   SET32SOC_sysIntPol3_Invert(r32,v)                _BFSET_(r32,31, 0,v)

    #define     w32SOC_sysIntPol3                              {\
            UNSG32 usysIntPol3_Invert                          : 32;\
          }
    union { UNSG32 u32SOC_sysIntPol3;
            struct w32SOC_sysIntPol3;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_Dummy_SW_Intr_Intr0(r32)                _BFGET_(r32, 0, 0)
    #define   SET32SOC_Dummy_SW_Intr_Intr0(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr0(r16)                _BFGET_(r16, 0, 0)
    #define   SET16SOC_Dummy_SW_Intr_Intr0(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr1(r32)                _BFGET_(r32, 1, 1)
    #define   SET32SOC_Dummy_SW_Intr_Intr1(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr1(r16)                _BFGET_(r16, 1, 1)
    #define   SET16SOC_Dummy_SW_Intr_Intr1(r16,v)              _BFSET_(r16, 1, 1,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr2(r32)                _BFGET_(r32, 2, 2)
    #define   SET32SOC_Dummy_SW_Intr_Intr2(r32,v)              _BFSET_(r32, 2, 2,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr2(r16)                _BFGET_(r16, 2, 2)
    #define   SET16SOC_Dummy_SW_Intr_Intr2(r16,v)              _BFSET_(r16, 2, 2,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr3(r32)                _BFGET_(r32, 3, 3)
    #define   SET32SOC_Dummy_SW_Intr_Intr3(r32,v)              _BFSET_(r32, 3, 3,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr3(r16)                _BFGET_(r16, 3, 3)
    #define   SET16SOC_Dummy_SW_Intr_Intr3(r16,v)              _BFSET_(r16, 3, 3,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr4(r32)                _BFGET_(r32, 4, 4)
    #define   SET32SOC_Dummy_SW_Intr_Intr4(r32,v)              _BFSET_(r32, 4, 4,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr4(r16)                _BFGET_(r16, 4, 4)
    #define   SET16SOC_Dummy_SW_Intr_Intr4(r16,v)              _BFSET_(r16, 4, 4,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr5(r32)                _BFGET_(r32, 5, 5)
    #define   SET32SOC_Dummy_SW_Intr_Intr5(r32,v)              _BFSET_(r32, 5, 5,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr5(r16)                _BFGET_(r16, 5, 5)
    #define   SET16SOC_Dummy_SW_Intr_Intr5(r16,v)              _BFSET_(r16, 5, 5,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr6(r32)                _BFGET_(r32, 6, 6)
    #define   SET32SOC_Dummy_SW_Intr_Intr6(r32,v)              _BFSET_(r32, 6, 6,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr6(r16)                _BFGET_(r16, 6, 6)
    #define   SET16SOC_Dummy_SW_Intr_Intr6(r16,v)              _BFSET_(r16, 6, 6,v)

    #define   GET32SOC_Dummy_SW_Intr_Intr7(r32)                _BFGET_(r32, 7, 7)
    #define   SET32SOC_Dummy_SW_Intr_Intr7(r32,v)              _BFSET_(r32, 7, 7,v)
    #define   GET16SOC_Dummy_SW_Intr_Intr7(r16)                _BFGET_(r16, 7, 7)
    #define   SET16SOC_Dummy_SW_Intr_Intr7(r16,v)              _BFSET_(r16, 7, 7,v)

    #define     w32SOC_Dummy_SW_Intr                           {\
            UNSG32 uDummy_SW_Intr_Intr0                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr1                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr2                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr3                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr4                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr5                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr6                        :  1;\
            UNSG32 uDummy_SW_Intr_Intr7                        :  1;\
            UNSG32 RSVDx14_b8                                  : 24;\
          }
    union { UNSG32 u32SOC_Dummy_SW_Intr;
            struct w32SOC_Dummy_SW_Intr;
          };
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx18                                     [232];
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_AHB_RESP_CTRL_MaskHrespDef(r32)         _BFGET_(r32, 0, 0)
    #define   SET32SOC_AHB_RESP_CTRL_MaskHrespDef(r32,v)       _BFSET_(r32, 0, 0,v)
    #define   GET16SOC_AHB_RESP_CTRL_MaskHrespDef(r16)         _BFGET_(r16, 0, 0)
    #define   SET16SOC_AHB_RESP_CTRL_MaskHrespDef(r16,v)       _BFSET_(r16, 0, 0,v)

    #define   GET32SOC_AHB_RESP_CTRL_MaskHrespSe(r32)          _BFGET_(r32, 1, 1)
    #define   SET32SOC_AHB_RESP_CTRL_MaskHrespSe(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16SOC_AHB_RESP_CTRL_MaskHrespSe(r16)          _BFGET_(r16, 1, 1)
    #define   SET16SOC_AHB_RESP_CTRL_MaskHrespSe(r16,v)        _BFSET_(r16, 1, 1,v)

    #define     w32SOC_AHB_RESP_CTRL                           {\
            UNSG32 uAHB_RESP_CTRL_MaskHrespDef                 :  1;\
            UNSG32 uAHB_RESP_CTRL_MaskHrespSe                  :  1;\
            UNSG32 RSVDx100_b2                                 : 30;\
          }
    union { UNSG32 u32SOC_AHB_RESP_CTRL;
            struct w32SOC_AHB_RESP_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_AXI_BRESP_CTRL_CPU(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32SOC_AXI_BRESP_CTRL_CPU(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16SOC_AXI_BRESP_CTRL_CPU(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16SOC_AXI_BRESP_CTRL_CPU(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32SOC_AXI_BRESP_CTRL_AVIOM0(r32)              _BFGET_(r32, 1, 1)
    #define   SET32SOC_AXI_BRESP_CTRL_AVIOM0(r32,v)            _BFSET_(r32, 1, 1,v)
    #define   GET16SOC_AXI_BRESP_CTRL_AVIOM0(r16)              _BFGET_(r16, 1, 1)
    #define   SET16SOC_AXI_BRESP_CTRL_AVIOM0(r16,v)            _BFSET_(r16, 1, 1,v)

    #define   GET32SOC_AXI_BRESP_CTRL_IMTEST(r32)              _BFGET_(r32, 2, 2)
    #define   SET32SOC_AXI_BRESP_CTRL_IMTEST(r32,v)            _BFSET_(r32, 2, 2,v)
    #define   GET16SOC_AXI_BRESP_CTRL_IMTEST(r16)              _BFGET_(r16, 2, 2)
    #define   SET16SOC_AXI_BRESP_CTRL_IMTEST(r16,v)            _BFSET_(r16, 2, 2,v)

    #define   GET32SOC_AXI_BRESP_CTRL_BMON(r32)                _BFGET_(r32, 3, 3)
    #define   SET32SOC_AXI_BRESP_CTRL_BMON(r32,v)              _BFSET_(r32, 3, 3,v)
    #define   GET16SOC_AXI_BRESP_CTRL_BMON(r16)                _BFGET_(r16, 3, 3)
    #define   SET16SOC_AXI_BRESP_CTRL_BMON(r16,v)              _BFSET_(r16, 3, 3,v)

    #define   GET32SOC_AXI_BRESP_CTRL_NNA(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32SOC_AXI_BRESP_CTRL_NNA(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16SOC_AXI_BRESP_CTRL_NNA(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16SOC_AXI_BRESP_CTRL_NNA(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32SOC_AXI_BRESP_CTRL_USBM0(r32)               _BFGET_(r32, 5, 5)
    #define   SET32SOC_AXI_BRESP_CTRL_USBM0(r32,v)             _BFSET_(r32, 5, 5,v)
    #define   GET16SOC_AXI_BRESP_CTRL_USBM0(r16)               _BFGET_(r16, 5, 5)
    #define   SET16SOC_AXI_BRESP_CTRL_USBM0(r16,v)             _BFSET_(r16, 5, 5,v)

    #define   GET32SOC_AXI_BRESP_CTRL_SDIO(r32)                _BFGET_(r32, 6, 6)
    #define   SET32SOC_AXI_BRESP_CTRL_SDIO(r32,v)              _BFSET_(r32, 6, 6,v)
    #define   GET16SOC_AXI_BRESP_CTRL_SDIO(r16)                _BFGET_(r16, 6, 6)
    #define   SET16SOC_AXI_BRESP_CTRL_SDIO(r16,v)              _BFSET_(r16, 6, 6,v)

    #define   GET32SOC_AXI_BRESP_CTRL_NANDEMMC(r32)            _BFGET_(r32, 7, 7)
    #define   SET32SOC_AXI_BRESP_CTRL_NANDEMMC(r32,v)          _BFSET_(r32, 7, 7,v)
    #define   GET16SOC_AXI_BRESP_CTRL_NANDEMMC(r16)            _BFGET_(r16, 7, 7)
    #define   SET16SOC_AXI_BRESP_CTRL_NANDEMMC(r16,v)          _BFSET_(r16, 7, 7,v)

    #define   GET32SOC_AXI_BRESP_CTRL_PCIE0(r32)               _BFGET_(r32, 8, 8)
    #define   SET32SOC_AXI_BRESP_CTRL_PCIE0(r32,v)             _BFSET_(r32, 8, 8,v)
    #define   GET16SOC_AXI_BRESP_CTRL_PCIE0(r16)               _BFGET_(r16, 8, 8)
    #define   SET16SOC_AXI_BRESP_CTRL_PCIE0(r16,v)             _BFSET_(r16, 8, 8,v)

    #define   GET32SOC_AXI_BRESP_CTRL_PCIE1(r32)               _BFGET_(r32, 9, 9)
    #define   SET32SOC_AXI_BRESP_CTRL_PCIE1(r32,v)             _BFSET_(r32, 9, 9,v)
    #define   GET16SOC_AXI_BRESP_CTRL_PCIE1(r16)               _BFGET_(r16, 9, 9)
    #define   SET16SOC_AXI_BRESP_CTRL_PCIE1(r16,v)             _BFSET_(r16, 9, 9,v)

    #define   GET32SOC_AXI_BRESP_CTRL_PB(r32)                  _BFGET_(r32,10,10)
    #define   SET32SOC_AXI_BRESP_CTRL_PB(r32,v)                _BFSET_(r32,10,10,v)
    #define   GET16SOC_AXI_BRESP_CTRL_PB(r16)                  _BFGET_(r16,10,10)
    #define   SET16SOC_AXI_BRESP_CTRL_PB(r16,v)                _BFSET_(r16,10,10,v)

    #define   GET32SOC_AXI_BRESP_CTRL_BCMCPU(r32)              _BFGET_(r32,11,11)
    #define   SET32SOC_AXI_BRESP_CTRL_BCMCPU(r32,v)            _BFSET_(r32,11,11,v)
    #define   GET16SOC_AXI_BRESP_CTRL_BCMCPU(r16)              _BFGET_(r16,11,11)
    #define   SET16SOC_AXI_BRESP_CTRL_BCMCPU(r16,v)            _BFSET_(r16,11,11,v)

    #define   GET32SOC_AXI_BRESP_CTRL_BCMDMA(r32)              _BFGET_(r32,12,12)
    #define   SET32SOC_AXI_BRESP_CTRL_BCMDMA(r32,v)            _BFSET_(r32,12,12,v)
    #define   GET16SOC_AXI_BRESP_CTRL_BCMDMA(r16)              _BFGET_(r16,12,12)
    #define   SET16SOC_AXI_BRESP_CTRL_BCMDMA(r16,v)            _BFSET_(r16,12,12,v)

    #define   GET32SOC_AXI_BRESP_CTRL_BCMDIR(r32)              _BFGET_(r32,13,13)
    #define   SET32SOC_AXI_BRESP_CTRL_BCMDIR(r32,v)            _BFSET_(r32,13,13,v)
    #define   GET16SOC_AXI_BRESP_CTRL_BCMDIR(r16)              _BFGET_(r16,13,13)
    #define   SET16SOC_AXI_BRESP_CTRL_BCMDIR(r16,v)            _BFSET_(r16,13,13,v)

    #define     w32SOC_AXI_BRESP_CTRL                          {\
            UNSG32 uAXI_BRESP_CTRL_CPU                         :  1;\
            UNSG32 uAXI_BRESP_CTRL_AVIOM0                      :  1;\
            UNSG32 uAXI_BRESP_CTRL_IMTEST                      :  1;\
            UNSG32 uAXI_BRESP_CTRL_BMON                        :  1;\
            UNSG32 uAXI_BRESP_CTRL_NNA                         :  1;\
            UNSG32 uAXI_BRESP_CTRL_USBM0                       :  1;\
            UNSG32 uAXI_BRESP_CTRL_SDIO                        :  1;\
            UNSG32 uAXI_BRESP_CTRL_NANDEMMC                    :  1;\
            UNSG32 uAXI_BRESP_CTRL_PCIE0                       :  1;\
            UNSG32 uAXI_BRESP_CTRL_PCIE1                       :  1;\
            UNSG32 uAXI_BRESP_CTRL_PB                          :  1;\
            UNSG32 uAXI_BRESP_CTRL_BCMCPU                      :  1;\
            UNSG32 uAXI_BRESP_CTRL_BCMDMA                      :  1;\
            UNSG32 uAXI_BRESP_CTRL_BCMDIR                      :  1;\
            UNSG32 RSVDx104_b14                                : 18;\
          }
    union { UNSG32 u32SOC_AXI_BRESP_CTRL;
            struct w32SOC_AXI_BRESP_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_AXI_RRESP_CTRL_CPU(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32SOC_AXI_RRESP_CTRL_CPU(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16SOC_AXI_RRESP_CTRL_CPU(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16SOC_AXI_RRESP_CTRL_CPU(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32SOC_AXI_RRESP_CTRL_AVIOM0(r32)              _BFGET_(r32, 1, 1)
    #define   SET32SOC_AXI_RRESP_CTRL_AVIOM0(r32,v)            _BFSET_(r32, 1, 1,v)
    #define   GET16SOC_AXI_RRESP_CTRL_AVIOM0(r16)              _BFGET_(r16, 1, 1)
    #define   SET16SOC_AXI_RRESP_CTRL_AVIOM0(r16,v)            _BFSET_(r16, 1, 1,v)

    #define   GET32SOC_AXI_RRESP_CTRL_IMTEST(r32)              _BFGET_(r32, 2, 2)
    #define   SET32SOC_AXI_RRESP_CTRL_IMTEST(r32,v)            _BFSET_(r32, 2, 2,v)
    #define   GET16SOC_AXI_RRESP_CTRL_IMTEST(r16)              _BFGET_(r16, 2, 2)
    #define   SET16SOC_AXI_RRESP_CTRL_IMTEST(r16,v)            _BFSET_(r16, 2, 2,v)

    #define   GET32SOC_AXI_RRESP_CTRL_BMON(r32)                _BFGET_(r32, 3, 3)
    #define   SET32SOC_AXI_RRESP_CTRL_BMON(r32,v)              _BFSET_(r32, 3, 3,v)
    #define   GET16SOC_AXI_RRESP_CTRL_BMON(r16)                _BFGET_(r16, 3, 3)
    #define   SET16SOC_AXI_RRESP_CTRL_BMON(r16,v)              _BFSET_(r16, 3, 3,v)

    #define   GET32SOC_AXI_RRESP_CTRL_NNA(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32SOC_AXI_RRESP_CTRL_NNA(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16SOC_AXI_RRESP_CTRL_NNA(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16SOC_AXI_RRESP_CTRL_NNA(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32SOC_AXI_RRESP_CTRL_NANDEMMC(r32)            _BFGET_(r32, 5, 5)
    #define   SET32SOC_AXI_RRESP_CTRL_NANDEMMC(r32,v)          _BFSET_(r32, 5, 5,v)
    #define   GET16SOC_AXI_RRESP_CTRL_NANDEMMC(r16)            _BFGET_(r16, 5, 5)
    #define   SET16SOC_AXI_RRESP_CTRL_NANDEMMC(r16,v)          _BFSET_(r16, 5, 5,v)

    #define   GET32SOC_AXI_RRESP_CTRL_USBM0(r32)               _BFGET_(r32, 6, 6)
    #define   SET32SOC_AXI_RRESP_CTRL_USBM0(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16SOC_AXI_RRESP_CTRL_USBM0(r16)               _BFGET_(r16, 6, 6)
    #define   SET16SOC_AXI_RRESP_CTRL_USBM0(r16,v)             _BFSET_(r16, 6, 6,v)

    #define   GET32SOC_AXI_RRESP_CTRL_SDIO(r32)                _BFGET_(r32, 7, 7)
    #define   SET32SOC_AXI_RRESP_CTRL_SDIO(r32,v)              _BFSET_(r32, 7, 7,v)
    #define   GET16SOC_AXI_RRESP_CTRL_SDIO(r16)                _BFGET_(r16, 7, 7)
    #define   SET16SOC_AXI_RRESP_CTRL_SDIO(r16,v)              _BFSET_(r16, 7, 7,v)

    #define   GET32SOC_AXI_RRESP_CTRL_PCIE0(r32)               _BFGET_(r32, 8, 8)
    #define   SET32SOC_AXI_RRESP_CTRL_PCIE0(r32,v)             _BFSET_(r32, 8, 8,v)
    #define   GET16SOC_AXI_RRESP_CTRL_PCIE0(r16)               _BFGET_(r16, 8, 8)
    #define   SET16SOC_AXI_RRESP_CTRL_PCIE0(r16,v)             _BFSET_(r16, 8, 8,v)

    #define   GET32SOC_AXI_RRESP_CTRL_PCIE1(r32)               _BFGET_(r32, 9, 9)
    #define   SET32SOC_AXI_RRESP_CTRL_PCIE1(r32,v)             _BFSET_(r32, 9, 9,v)
    #define   GET16SOC_AXI_RRESP_CTRL_PCIE1(r16)               _BFGET_(r16, 9, 9)
    #define   SET16SOC_AXI_RRESP_CTRL_PCIE1(r16,v)             _BFSET_(r16, 9, 9,v)

    #define   GET32SOC_AXI_RRESP_CTRL_PB(r32)                  _BFGET_(r32,10,10)
    #define   SET32SOC_AXI_RRESP_CTRL_PB(r32,v)                _BFSET_(r32,10,10,v)
    #define   GET16SOC_AXI_RRESP_CTRL_PB(r16)                  _BFGET_(r16,10,10)
    #define   SET16SOC_AXI_RRESP_CTRL_PB(r16,v)                _BFSET_(r16,10,10,v)

    #define   GET32SOC_AXI_RRESP_CTRL_BCMCPU(r32)              _BFGET_(r32,11,11)
    #define   SET32SOC_AXI_RRESP_CTRL_BCMCPU(r32,v)            _BFSET_(r32,11,11,v)
    #define   GET16SOC_AXI_RRESP_CTRL_BCMCPU(r16)              _BFGET_(r16,11,11)
    #define   SET16SOC_AXI_RRESP_CTRL_BCMCPU(r16,v)            _BFSET_(r16,11,11,v)

    #define   GET32SOC_AXI_RRESP_CTRL_BCMDMA(r32)              _BFGET_(r32,12,12)
    #define   SET32SOC_AXI_RRESP_CTRL_BCMDMA(r32,v)            _BFSET_(r32,12,12,v)
    #define   GET16SOC_AXI_RRESP_CTRL_BCMDMA(r16)              _BFGET_(r16,12,12)
    #define   SET16SOC_AXI_RRESP_CTRL_BCMDMA(r16,v)            _BFSET_(r16,12,12,v)

    #define   GET32SOC_AXI_RRESP_CTRL_BCMDIR(r32)              _BFGET_(r32,13,13)
    #define   SET32SOC_AXI_RRESP_CTRL_BCMDIR(r32,v)            _BFSET_(r32,13,13,v)
    #define   GET16SOC_AXI_RRESP_CTRL_BCMDIR(r16)              _BFGET_(r16,13,13)
    #define   SET16SOC_AXI_RRESP_CTRL_BCMDIR(r16,v)            _BFSET_(r16,13,13,v)

    #define     w32SOC_AXI_RRESP_CTRL                          {\
            UNSG32 uAXI_RRESP_CTRL_CPU                         :  1;\
            UNSG32 uAXI_RRESP_CTRL_AVIOM0                      :  1;\
            UNSG32 uAXI_RRESP_CTRL_IMTEST                      :  1;\
            UNSG32 uAXI_RRESP_CTRL_BMON                        :  1;\
            UNSG32 uAXI_RRESP_CTRL_NNA                         :  1;\
            UNSG32 uAXI_RRESP_CTRL_NANDEMMC                    :  1;\
            UNSG32 uAXI_RRESP_CTRL_USBM0                       :  1;\
            UNSG32 uAXI_RRESP_CTRL_SDIO                        :  1;\
            UNSG32 uAXI_RRESP_CTRL_PCIE0                       :  1;\
            UNSG32 uAXI_RRESP_CTRL_PCIE1                       :  1;\
            UNSG32 uAXI_RRESP_CTRL_PB                          :  1;\
            UNSG32 uAXI_RRESP_CTRL_BCMCPU                      :  1;\
            UNSG32 uAXI_RRESP_CTRL_BCMDMA                      :  1;\
            UNSG32 uAXI_RRESP_CTRL_BCMDIR                      :  1;\
            UNSG32 RSVDx108_b14                                : 18;\
          }
    union { UNSG32 u32SOC_AXI_RRESP_CTRL;
            struct w32SOC_AXI_RRESP_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_GFX_QOS_CTRL_wqos_enable(r32)           _BFGET_(r32, 0, 0)
    #define   SET32SOC_GFX_QOS_CTRL_wqos_enable(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16SOC_GFX_QOS_CTRL_wqos_enable(r16)           _BFGET_(r16, 0, 0)
    #define   SET16SOC_GFX_QOS_CTRL_wqos_enable(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32SOC_GFX_QOS_CTRL_wqos_value0(r32)           _BFGET_(r32, 4, 1)
    #define   SET32SOC_GFX_QOS_CTRL_wqos_value0(r32,v)         _BFSET_(r32, 4, 1,v)
    #define   GET16SOC_GFX_QOS_CTRL_wqos_value0(r16)           _BFGET_(r16, 4, 1)
    #define   SET16SOC_GFX_QOS_CTRL_wqos_value0(r16,v)         _BFSET_(r16, 4, 1,v)

    #define   GET32SOC_GFX_QOS_CTRL_wqos_value1(r32)           _BFGET_(r32, 8, 5)
    #define   SET32SOC_GFX_QOS_CTRL_wqos_value1(r32,v)         _BFSET_(r32, 8, 5,v)
    #define   GET16SOC_GFX_QOS_CTRL_wqos_value1(r16)           _BFGET_(r16, 8, 5)
    #define   SET16SOC_GFX_QOS_CTRL_wqos_value1(r16,v)         _BFSET_(r16, 8, 5,v)

    #define   GET32SOC_GFX_QOS_CTRL_rqos_enable(r32)           _BFGET_(r32, 9, 9)
    #define   SET32SOC_GFX_QOS_CTRL_rqos_enable(r32,v)         _BFSET_(r32, 9, 9,v)
    #define   GET16SOC_GFX_QOS_CTRL_rqos_enable(r16)           _BFGET_(r16, 9, 9)
    #define   SET16SOC_GFX_QOS_CTRL_rqos_enable(r16,v)         _BFSET_(r16, 9, 9,v)

    #define   GET32SOC_GFX_QOS_CTRL_rqos_value0(r32)           _BFGET_(r32,13,10)
    #define   SET32SOC_GFX_QOS_CTRL_rqos_value0(r32,v)         _BFSET_(r32,13,10,v)
    #define   GET16SOC_GFX_QOS_CTRL_rqos_value0(r16)           _BFGET_(r16,13,10)
    #define   SET16SOC_GFX_QOS_CTRL_rqos_value0(r16,v)         _BFSET_(r16,13,10,v)

    #define   GET32SOC_GFX_QOS_CTRL_rqos_value1(r32)           _BFGET_(r32,17,14)
    #define   SET32SOC_GFX_QOS_CTRL_rqos_value1(r32,v)         _BFSET_(r32,17,14,v)

    #define     w32SOC_GFX_QOS_CTRL                            {\
            UNSG32 uGFX_QOS_CTRL_wqos_enable                   :  1;\
            UNSG32 uGFX_QOS_CTRL_wqos_value0                   :  4;\
            UNSG32 uGFX_QOS_CTRL_wqos_value1                   :  4;\
            UNSG32 uGFX_QOS_CTRL_rqos_enable                   :  1;\
            UNSG32 uGFX_QOS_CTRL_rqos_value0                   :  4;\
            UNSG32 uGFX_QOS_CTRL_rqos_value1                   :  4;\
            UNSG32 RSVDx10C_b18                                : 14;\
          }
    union { UNSG32 u32SOC_GFX_QOS_CTRL;
            struct w32SOC_GFX_QOS_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32SOC_OVP_QOS_CTRL_wqos_value(r32)            _BFGET_(r32, 3, 0)
    #define   SET32SOC_OVP_QOS_CTRL_wqos_value(r32,v)          _BFSET_(r32, 3, 0,v)
    #define   GET16SOC_OVP_QOS_CTRL_wqos_value(r16)            _BFGET_(r16, 3, 0)
    #define   SET16SOC_OVP_QOS_CTRL_wqos_value(r16,v)          _BFSET_(r16, 3, 0,v)

    #define   GET32SOC_OVP_QOS_CTRL_rqos_value(r32)            _BFGET_(r32, 7, 4)
    #define   SET32SOC_OVP_QOS_CTRL_rqos_value(r32,v)          _BFSET_(r32, 7, 4,v)
    #define   GET16SOC_OVP_QOS_CTRL_rqos_value(r16)            _BFGET_(r16, 7, 4)
    #define   SET16SOC_OVP_QOS_CTRL_rqos_value(r16,v)          _BFSET_(r16, 7, 4,v)

    #define     w32SOC_OVP_QOS_CTRL                            {\
            UNSG32 uOVP_QOS_CTRL_wqos_value                    :  4;\
            UNSG32 uOVP_QOS_CTRL_rqos_value                    :  4;\
            UNSG32 RSVDx110_b8                                 : 24;\
          }
    union { UNSG32 u32SOC_OVP_QOS_CTRL;
            struct w32SOC_OVP_QOS_CTRL;
          };
    ///////////////////////////////////////////////////////////
              SIE_cacheOR                                      ie_cacheOR;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx124                                    [3804];
    ///////////////////////////////////////////////////////////
              SIE_protOR                                       ie_protOR;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1038                                   [200];
    ///////////////////////////////////////////////////////////
              SIE_RestrictZone                                 ie_RestrictZone;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1138                                   [200];
    ///////////////////////////////////////////////////////////
              SIE_seRegionX                                    ie_SecureRegionCtrl0;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1260                                   [160];
    ///////////////////////////////////////////////////////////
              SIE_seRegionX                                    ie_SecureRegionCtrl1;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1360                                   [160];
    ///////////////////////////////////////////////////////////
              SIE_seRegionX                                    ie_SecureRegionCtrl2;
    ///////////////////////////////////////////////////////////
             UNSG8 RSVDx1460                                   [160];
    ///////////////////////////////////////////////////////////
              SIE_defSeRegionX                                 ie_defSecureRegionCtrl0;
    ///////////////////////////////////////////////////////////
    } SIE_SOC;

    typedef union  T32SOC_Configuration
          { UNSG32 u32;
            struct w32SOC_Configuration;
                 } T32SOC_Configuration;
    typedef union  T32SOC_sysIntPol0
          { UNSG32 u32;
            struct w32SOC_sysIntPol0;
                 } T32SOC_sysIntPol0;
    typedef union  T32SOC_sysIntPol1
          { UNSG32 u32;
            struct w32SOC_sysIntPol1;
                 } T32SOC_sysIntPol1;
    typedef union  T32SOC_sysIntPol2
          { UNSG32 u32;
            struct w32SOC_sysIntPol2;
                 } T32SOC_sysIntPol2;
    typedef union  T32SOC_sysIntPol3
          { UNSG32 u32;
            struct w32SOC_sysIntPol3;
                 } T32SOC_sysIntPol3;
    typedef union  T32SOC_Dummy_SW_Intr
          { UNSG32 u32;
            struct w32SOC_Dummy_SW_Intr;
                 } T32SOC_Dummy_SW_Intr;
    typedef union  T32SOC_AHB_RESP_CTRL
          { UNSG32 u32;
            struct w32SOC_AHB_RESP_CTRL;
                 } T32SOC_AHB_RESP_CTRL;
    typedef union  T32SOC_AXI_BRESP_CTRL
          { UNSG32 u32;
            struct w32SOC_AXI_BRESP_CTRL;
                 } T32SOC_AXI_BRESP_CTRL;
    typedef union  T32SOC_AXI_RRESP_CTRL
          { UNSG32 u32;
            struct w32SOC_AXI_RRESP_CTRL;
                 } T32SOC_AXI_RRESP_CTRL;
    typedef union  T32SOC_GFX_QOS_CTRL
          { UNSG32 u32;
            struct w32SOC_GFX_QOS_CTRL;
                 } T32SOC_GFX_QOS_CTRL;
    typedef union  T32SOC_OVP_QOS_CTRL
          { UNSG32 u32;
            struct w32SOC_OVP_QOS_CTRL;
                 } T32SOC_OVP_QOS_CTRL;
    ///////////////////////////////////////////////////////////

    typedef union  TSOC_Configuration
          { UNSG32 u32[1];
            struct {
            struct w32SOC_Configuration;
                   };
                 } TSOC_Configuration;
    typedef union  TSOC_sysIntPol0
          { UNSG32 u32[1];
            struct {
            struct w32SOC_sysIntPol0;
                   };
                 } TSOC_sysIntPol0;
    typedef union  TSOC_sysIntPol1
          { UNSG32 u32[1];
            struct {
            struct w32SOC_sysIntPol1;
                   };
                 } TSOC_sysIntPol1;
    typedef union  TSOC_sysIntPol2
          { UNSG32 u32[1];
            struct {
            struct w32SOC_sysIntPol2;
                   };
                 } TSOC_sysIntPol2;
    typedef union  TSOC_sysIntPol3
          { UNSG32 u32[1];
            struct {
            struct w32SOC_sysIntPol3;
                   };
                 } TSOC_sysIntPol3;
    typedef union  TSOC_Dummy_SW_Intr
          { UNSG32 u32[1];
            struct {
            struct w32SOC_Dummy_SW_Intr;
                   };
                 } TSOC_Dummy_SW_Intr;
    typedef union  TSOC_AHB_RESP_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32SOC_AHB_RESP_CTRL;
                   };
                 } TSOC_AHB_RESP_CTRL;
    typedef union  TSOC_AXI_BRESP_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32SOC_AXI_BRESP_CTRL;
                   };
                 } TSOC_AXI_BRESP_CTRL;
    typedef union  TSOC_AXI_RRESP_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32SOC_AXI_RRESP_CTRL;
                   };
                 } TSOC_AXI_RRESP_CTRL;
    typedef union  TSOC_GFX_QOS_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32SOC_GFX_QOS_CTRL;
                   };
                 } TSOC_GFX_QOS_CTRL;
    typedef union  TSOC_OVP_QOS_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32SOC_OVP_QOS_CTRL;
                   };
                 } TSOC_OVP_QOS_CTRL;

    ///////////////////////////////////////////////////////////
     SIGN32 SOC_drvrd(SIE_SOC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 SOC_drvwr(SIE_SOC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void SOC_reset(SIE_SOC *p);
     SIGN32 SOC_cmp  (SIE_SOC *p, SIE_SOC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define SOC_check(p,pie,pfx,hLOG) SOC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define SOC_print(p,    pfx,hLOG) SOC_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: SOC
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE SocCSApbDec                              (4,4)
///     # # ----------------------------------------------------------
///               : SOCCS_ROM          0x0
///               : SOCCS_ETB          0x1000
///               : SOCCS_CTI          0x2000
///               : SOCCS_FUN          0x4000
///               : SOCCS_RESV         0x9000
///               : CPUINT_ROM         0x20000
///               : RESV_OTHER         0x21000
///               : RESV_FUTURE        0x28000
///               : CPU0_DBG           0x30000
///               : CPU0_PMU           0x31000
///               : CPU1_DBG           0x32000
///               : CPU1_PMU           0x33000
///               : CPU2_DBG           0x34000
///               : CPU2_PMU           0x35000
///               : CPU3_DBG           0x36000
///               : CPU3_PMU           0x37000
///               : CPU0_CTI           0x38000
///               : CPU1_CTI           0x39000
///               : CPU2_CTI           0x3A000
///               : CPU3_CTI           0x3B000
///               : CPU0_TRACE         0x3C000
///               : CPU1_TRACE         0x3D000
///               : CPU2_TRACE         0x3E000
///               : CPU3_TRACE         0x3F000
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       0B, bits:       0b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_SocCSApbDec
#define h_SocCSApbDec (){}

    #define        SocCSApbDec_SOCCS_ROM                       0x0
    #define        SocCSApbDec_SOCCS_ETB                       0x1000
    #define        SocCSApbDec_SOCCS_CTI                       0x2000
    #define        SocCSApbDec_SOCCS_FUN                       0x4000
    #define        SocCSApbDec_SOCCS_RESV                      0x9000
    #define        SocCSApbDec_CPUINT_ROM                      0x20000
    #define        SocCSApbDec_RESV_OTHER                      0x21000
    #define        SocCSApbDec_RESV_FUTURE                     0x28000
    #define        SocCSApbDec_CPU0_DBG                        0x30000
    #define        SocCSApbDec_CPU0_PMU                        0x31000
    #define        SocCSApbDec_CPU1_DBG                        0x32000
    #define        SocCSApbDec_CPU1_PMU                        0x33000
    #define        SocCSApbDec_CPU2_DBG                        0x34000
    #define        SocCSApbDec_CPU2_PMU                        0x35000
    #define        SocCSApbDec_CPU3_DBG                        0x36000
    #define        SocCSApbDec_CPU3_PMU                        0x37000
    #define        SocCSApbDec_CPU0_CTI                        0x38000
    #define        SocCSApbDec_CPU1_CTI                        0x39000
    #define        SocCSApbDec_CPU2_CTI                        0x3A000
    #define        SocCSApbDec_CPU3_CTI                        0x3B000
    #define        SocCSApbDec_CPU0_TRACE                      0x3C000
    #define        SocCSApbDec_CPU1_TRACE                      0x3D000
    #define        SocCSApbDec_CPU2_TRACE                      0x3E000
    #define        SocCSApbDec_CPU3_TRACE                      0x3F000
    ///////////////////////////////////////////////////////////

#endif
//////
/// ENDOFINTERFACE: SocCSApbDec
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: soc.h
////////////////////////////////////////////////////////////