/*
 * Copyright (C) 2018 Synaptics Incorporated. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND
 * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES,
 * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY
 * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR
 * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND
 * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF
 * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT
 * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY
 * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS.
 */

#ifndef	__GALOIS_IO_H__
#define	__GALOIS_IO_H__

#include <stdint.h>

#include "com_type.h"
#include "galois_common.h"

#define	__MEMIO_DIRECT


#define	CPU_PHY_MEM(x)					((MV_U32)(x))
#define	CPU_MEMIO_CACHED_ADDR(x)			((void*)(x))
#define	CPU_MEMIO_UNCACHED_ADDR(x)			((void*)(x))

/*!
 * CPU architecture dependent 32, 16, 8 bit read/write IO addresses
 */
#define	MV_MEMIO32_WRITE(addr, data)		((*((volatile uint32_t*)((uintmax_t)addr))) = ((uint32_t)(data)))
#define	MV_MEMIO32_READ(addr)				((*((volatile uint32_t*)((uintmax_t)addr))))
#define	MV_MEMIO16_WRITE(addr, data)		((*((volatile unsigned short*)((uintmax_t)addr))) = ((unsigned short)(data)))
#define	MV_MEMIO16_READ(addr)				((*((volatile unsigned short*)((uintmax_t)addr))))
#define	MV_MEMIO08_WRITE(addr, data)		((*((volatile unsigned char*)((uintmax_t)addr))) = ((unsigned char)(data)))
#define	MV_MEMIO08_READ(addr)				((*((volatile unsigned char*)((uintmax_t)addr))))


/*!
 * No Fast Swap implementation (in assembler) for ARM
 */
#define	MV_32BIT_LE_FAST(val)				MV_32BIT_LE(val)
#define	MV_16BIT_LE_FAST(val)				MV_16BIT_LE(val)
#define	MV_32BIT_BE_FAST(val)				MV_32BIT_BE(val)
#define	MV_16BIT_BE_FAST(val)				MV_16BIT_BE(val)

/*!
 * 32 and 16 bit read/write in big/little endian mode
 */

/*!
 * 16bit write in little endian mode
 */
#define	MV_MEMIO_LE16_WRITE(addr, data)		MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data))

/*!
 * 16bit read in little endian mode
 */
#define	MV_MEMIO_LE16_READ(addr)			MV_16BIT_LE_FAST((MV_U16)(MV_MEMIO16_READ((MV_U32)(addr))))

/*!
 * 32bit write in little endian mode
 */
#define	MV_MEMIO_LE32_WRITE(addr, data)		MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data))

/*!
 * 32bit read in little endian mode
 */
#define	MV_MEMIO_LE32_READ(addr)			MV_32BIT_LE_FAST((MV_U32)(MV_MEMIO32_READ((MV_U32)(addr))))

/*!
 * Generate 32bit mask
 */
#define	GA_REG_MASK(bits, l_shift)			((bits) ? (((bits) < 32) ? (((1uL << (bits)) - 1) << (l_shift)) : (0xFFFFFFFFuL << (l_shift))) : 0)

/*!
 * Galois's register address translate
 */

#	ifndef	INTER_REGS_BASE
#	define	INTER_REGS_BASE				0
#	endif

#	define	REG_ADDR(offset)			((MV_U32)(INTER_REGS_BASE | (offset)))

/*!
 * Galois controller register read/write macros
 *
 * offset -- address offset (32bits)
 * holder -- pointer to the variable that will be used to store the data being read in.
 * val -- variable contains the data that will be written out.
 * bitMask -- variable contains the data (32bits) that will be written out. 
 * clearMask -- variable contains the mask (32bits) that will be used to clear the corresponding bits. 
 *
 * GA_REG_WORD32_READ(offset, holder) -- Read a Double-Word (32bits) from 'offset' to 'holder'
 * GA_REG_WORD16_READ(offset, holder) -- Read a Word (16bits) from 'offset' to 'holder'
 * GA_REG_BYTE_READ(offset, holder) -- Read a Byte (8bits) from 'offset' to 'holder'
 *
 * GA_REG_WORD32_WRITE(offset, val) -- Write a Double-Word (32bits) to 'offset'
 * GA_REG_WORD16_WRITE(offset, val) -- Write a Word (16bits) to 'offset'
 * GA_REG_BYTE_WIRTE(offset, val) -- Write a Byte (8bits) to 'offset'
 *
 * GA_REG_WORD32_BIT_SET(offset, bitMask) -- Set bits to '1b' at 'offset', 'bitMask' should only be used to set '1b' for corresponding bits. 
 * GA_REG_WORD32_BITS_SET(offset, clearMask, val) -- Clear the bits to zero for the bits in clearMask are '1b' and write 'val' to 'offset'.
 * GA_REG_WORD32_BIT_CLEAR(offset, clearMask) -- Clear the bits to zero for the bits in bitMask are '1b'
 *
 */
#	define	GA_REG_WORD32_READ(offset, holder)	(*(holder) = MV_MEMIO_LE32_READ(REG_ADDR(offset)))
#	define	GA_REG_WORD16_READ(offset, holder)	(*(holder) = MV_MEMIO_LE16_READ(REG_ADDR(offset)))
#	define	GA_REG_BYTE_READ(offset, holder)	(*(holder) = MV_MEMIO08_READ(REG_ADDR(offset)))

#	define	GA_REG_WORD32_WRITE(offset, val)	(MV_MEMIO_LE32_WRITE(REG_ADDR(offset), (MV_U32)(val)))
#	define	GA_REG_WORD16_WRITE(offset, val)	(MV_MEMIO_LE16_WRITE(REG_ADDR(offset), (MV_U16)(val)))
#	define	GA_REG_BYTE_WRITE(offset, val)		(MV_MEMIO08_WRITE(REG_ADDR(offset), (MV_U8)(val)))

#	define	GA_REG_WORD32_BIT_SET(offset, bitMask)	(MV_MEMIO32_WRITE(REG_ADDR(offset),					\
							(MV_MEMIO_LE32_READ(REG_ADDR(offset)) | MV_32BIT_LE_FAST(bitMask))))
#	define	GA_REG_WORD32_BITS_SET(offset, clearMask, val)									\
							(MV_MEMIO32_WRITE(REG_ADDR(offset),					\
							((MV_MEMIO_LE32_READ(REG_ADDR(offset)) & MV_32BIT_LE_FAST(~(clearMask)))\
							| MV_32BIT_LE_FAST(val))))
#	define	GA_REG_WORD32_BIT_CLEAR(offset, clearMask)									\
							(MV_MEMIO32_WRITE(REG_ADDR(offset),					\
							(MV_MEMIO_LE32_READ(REG_ADDR(offset)) & MV_32BIT_LE_FAST(~(clearMask)))))


#endif	/* __GALOIS_IO_H__ */