/*
 * Copyright (C) 2018 Synaptics Incorporated. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND
 * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES,
 * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY
 * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR
 * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND
 * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF
 * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT
 * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY
 * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS.
 */

#include "Galois_memmap.h"
#include "global.h"
#include "pinmux.h"
#include "gpio.h"
#include "io.h"
#include "SysMgr.h"
#include "apbRegBase.h"

#include "board_config.h"
#include "berlin_bootinfo.h"

#include "util.h"
#include "lgpl_printf.h"

#define	RA_SET_BITS_GENERIC(ra_base, ra_name, ra_class, bf_name, val) \
	io32_set_bits(ra_base + RA_##ra_name, val, LSb32##ra_class##_##bf_name, b##ra_class##_##bf_name)

#define	RA_SET_BITS_SIMPLE(ra_base, ra_name, bf_name, val) RA_SET_BITS_GENERIC(ra_base, ra_name, ra_name, bf_name, val)

#define	SOC_SET_PINMUX(ra_name, bf_name, val) RA_SET_BITS_GENERIC(MEMMAP_CHIP_CTRL_REG_BASE, ra_name, Gbl_pinMuxCntlBus, bf_name, val)
#define	SM_SET_PINMUX(ra_name, bf_name, val) RA_SET_BITS_GENERIC(SOC_SM_SYS_CTRL_REG_BASE, ra_name, smSysCtl_smPinMuxCntlBus, bf_name, val)

void pin_init(void)
{
	UNSG32 val = 0;

	GPIO_PortSetInOut(5, 1); //TOUCH_IRQ_L Input, active low
	GPIO_PortSetInOut(11, 1); //MIC_MUTE_STATUS Input, active high
	GPIO_PortWrite(17, 0); //AMP_EN Output, active high, default=inactive low
	GPIO_PortSetInOut(41, 1); //PP1350_DDR_FB_33 HiZ, default=HiZ
	GPIO_PortWrite(43, 1); // WLAN_GPIO14 (reset Wifi) -> Output, active low, default=inactive high
	GPIO_PortWrite(44, 1); // WLAN_GPIO15 (reset BT) -> Output, active low, default=inactive high
	GPIO_PortWrite(63, 0); //WLAN_EN Output, active high, default=inactive low

	// reset the peripherals for 20ms, no i2c commands allowed during the reset pulse
	// Set PER_RST_L output low
	GPIO_PortWrite(4, 0);
	// Wait 20ms
	berlin_delay_us(20000);
	// Set PER_RST_L output high
	GPIO_PortWrite(4, 1);

	// enable WLAN and amplifier
	// Set WLAN_EN output high
	GPIO_PortWrite(63, 1);

	// Disable MCLK
	REG_READ32(0xF7440164, &val);
	val &= 0xFFFFFFFE;
	REG_WRITE32(0xF7440164, val);

	// set SOC_AMP_24V_EN to high
	GPIO_PortWrite(42, 1);

	// Enable SDIO internal pull up
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_DAT0Cntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_DAT1Cntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_CLKCntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_DAT2Cntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_DAT3Cntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_CMDCntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_CDnCntl, PUEN, 1);
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_SD0_WPCntl, PUEN, 1);

	// Set PDM_CLKO pin drive strength to 1 (b/144031947)
	RA_SET_BITS_SIMPLE(MEMMAP_CHIP_CTRL_REG_BASE, Gbl_PDM_CLKOCntl, DRV, 1);

	// end of low level initialisation
}

unsigned int get_board_memory_size(void) {
	const volatile BERLIN_BOOTINFO *pinfo = (BERLIN_BOOTINFO *)BERLIN_BOOTINFO_ADDR;
	return pinfo->mem_size * 1024 * 1024;
}