/*
 * Copyright (C) 2018 Synaptics Incorporated. All rights reserved.
 * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND
 * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES,
 * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY
 * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR
 * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND
 * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF
 * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT
 * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY
 * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS.
 */

/*
  This code initialises the Integrator board (eg REMAP) before calling
  TCM Initialization and MMU Initialization if they exist.
  this allows scatter loading to relocate code into the TCMs

  This code must be run from a privileged mode
*/

.global enable_mmu


#define SCTLR_M_BIT		(1 << 0)
#define SCTLR_A_BIT		(1 << 1)
#define SCTLR_C_BIT		(1 << 2)
#define SCTLR_SA_BIT		(1 << 3)
#define SCTLR_I_BIT		(1 << 12)
#define SCTLR_WXN_BIT		(1 << 19)
#define SCTLR_EE_BIT		(1 << 25)

.globl BootLoaderEntry
BootLoaderEntry:

		mrs     x0, DAIF
		msr     DAIFSET, #3                 /* disable interrupt */

		/*
		 * Clear BSS so that there are no surprises
		 * Make sure this is only applied to BSS section
		 * as it is time consuming.
		 */
		ldr 	x0, =__bss
		ldr 	x1, =__bss_end
z_loop:
		cmp x0, x1
		b.eq	z_end
		strb	wzr, [x0], #1
		b	z_loop
z_end:
		isb

		mrs	x0, hcr_el2
		orr x0, x0, #0xf8
		msr	hcr_el2, x0
		isb sy

		ic	ialluis

		mrs x0, sctlr_el2
		orr x0, x0, #SCTLR_I_BIT
		bic x0, x0, #SCTLR_M_BIT
		bic x0, x0, #SCTLR_C_BIT
		msr sctlr_el2, x0

		isb sy


		/* ---------------------------------------------
		 * Set the exception vector to something sane.
		 * ---------------------------------------------
		 */
		adr	x0, exception_handler
		msr	vbar_el2, x0
		isb

		ldr x0, = __stack_start
		mov sp, x0

		bl	enable_mmu

		/*
		 * branch to C Library entry point
		 */
		ldr		x0, = 0
		ldr		x1, = 0
		ldr		x2, = 0
		bl		StartBootLoader

panic:
		b	panic

.global asm_delay
asm_delay:
		subs    w0, w0, #1
		bne     asm_delay
		ret