// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * arch/arm64/boot/dts/amlogic/mesont5d_reva.dtsi
 *
 * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-t5d-gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/meson_rc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/clock/t5d-clkc.h>
#include <dt-bindings/clock/t5d-periph-clkc.h>
#include <dt-bindings/clock/t5d-aoclkc.h>
#include <dt-bindings/clock/amlogic,t5-audio-clk.h>
#include <dt-bindings/phy/phy-amlogic-pcie.h>
#include "mesong12a-bifrost.dtsi"
#include <dt-bindings/iio/adc/amlogic-saradc.h>
#include <dt-bindings/reset/amlogic,meson-t5d-reset.h>
#include <dt-bindings/power/t5-pd.h>
#include "meson-ir-map.dtsi"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "amlogic,t5d";

	cpus:cpus {
		#address-cells = <2>;
		#size-cells = <0>;
		#cooling-cells = <2>;/* min followed by max */
		CPU0:cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x0>;
			//timer=<&timer_a>;
			enable-method = "psci";
			clocks = <&clkc CLKID_CPU_CLK>,
				<&clkc CLKID_CPU_CLK_DYN>,
				<&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			multi_tables_available;
			operating-points-v2 = <&cpu_opp_table0>,
				<&cpu_opp_table1>,
				<&cpu_opp_table2>,
				<&cpu_opp_table3>;
			cpu-supply = <&vddcpu0>;
			cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			dynamic-power-coefficient = <80>;
			#cooling-cells = <2>;
		};

		CPU1:cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x1>;
//			//timer=<&timer_b>;
			enable-method = "psci";
			clocks = <&clkc CLKID_CPU_CLK>,
				<&clkc CLKID_CPU_CLK_DYN>,
				<&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			multi_tables_available;
			operating-points-v2 = <&cpu_opp_table0>,
				<&cpu_opp_table1>,
				<&cpu_opp_table2>,
				<&cpu_opp_table3>;
			cpu-supply = <&vddcpu0>;
			cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			dynamic-power-coefficient = <80>;
			#cooling-cells = <2>;
		};

		CPU2:cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x2>;
//			//timer=<&timer_c>;
			enable-method = "psci";
			clocks = <&clkc CLKID_CPU_CLK>,
				<&clkc CLKID_CPU_CLK_DYN>,
				<&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			multi_tables_available;
			operating-points-v2 = <&cpu_opp_table0>,
				<&cpu_opp_table1>,
				<&cpu_opp_table2>,
				<&cpu_opp_table3>;
			cpu-supply = <&vddcpu0>;
			cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			dynamic-power-coefficient = <80>;
			#cooling-cells = <2>;
		};

		CPU3:cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x3>;
//			//timer=<&timer_d>;
			enable-method = "psci";
			clocks = <&clkc CLKID_CPU_CLK>,
				<&clkc CLKID_CPU_CLK_DYN>,
				<&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			multi_tables_available;
			operating-points-v2 = <&cpu_opp_table0>,
				<&cpu_opp_table1>,
				<&cpu_opp_table2>,
				<&cpu_opp_table3>;
			cpu-supply = <&vddcpu0>;
			cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			dynamic-power-coefficient = <80>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "arm,psci";
			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <5000>;
				exit-latency-us = <5000>;
				min-residency-us = <20000>;
			};
			SYSTEM_SLEEP_0: system-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0000000>;
				entry-latency-us = <0x3fffffff>;
				exit-latency-us = <0x40000000>;
				min-residency-us = <0xffffffff>;
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 0xff01>,
			     <GIC_PPI 14 0xff01>,
			     <GIC_PPI 11 0xff01>,
			     <GIC_PPI 10 0xff01>;
	};

	timer_bc {
		compatible = "arm,bc-timer";
		status = "disabled";
		reg = <0x0 0xffd0f190  0x0 0x4  0x0 0xffd0f194  0x0 0x4>;
		timer_name = "Meson TimerF";
		clockevent-rating =<300>;
		clockevent-shift =<20>;
		clockevent-features =<0x23>;
		interrupts = <0 60 1>;
		bit_enable =<16>;
		bit_mode =<12>;
		bit_resolution =<0>;
	};

	arm_pmu {
		compatible = "arm,armv8-pmuv3";
		private-interrupts;
		/* clusterb-enabled; */
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;

		reg = <0x0 0xff634680 0x0 0x4>;
		cpumasks = <0xf>;
		/* default 10ms */
		relax-timer-ns = <10000000>;
		/* default 10000us */
		max-wait-cnt = <10000>;
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		interrupt-controller;
		reg = <0x0 0xffc01000 0x0 0x1000>,
		      <0x0 0xffc02000 0x0 0x0100>;
		interrupts = <GIC_PPI 9 0xf04>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	secmon {
		compatible = "amlogic, secmon";
		memory-region = <&secmon_reserved>;
		in_base_func = <0x82000020>;
		out_base_func = <0x82000021>;
		inout_size_func = <0x8200002a>;
		reserve_mem_size = <0x00300000>;
	};

	cma_shrinker: cma_shrinker {
		compatible = "amlogic, cma-shrinker";
		status = "okay";
		adj  = <0 100 200 250 900 950>;
		free = <8192 12288 16384 24576 28672 32768>;
	};

	securitykey {
		compatible = "amlogic, securitykey";
		status = "disabled";
		storage_query = <0x82000060>;
		storage_read = <0x82000061>;
		storage_write = <0x82000062>;
		storage_tell = <0x82000063>;
		storage_verify = <0x82000064>;
		storage_status = <0x82000065>;
		storage_list = <0x82000067>;
		storage_remove = <0x82000068>;
		storage_in_func = <0x82000023>;
		storage_out_func = <0x82000024>;
		storage_block_func = <0x82000025>;
		storage_size_func = <0x82000027>;
		storage_set_enctype = <0x8200006A>;
		storage_get_enctype = <0x8200006B>;
		storage_version = <0x8200006C>;
	};

	mailbox_pl: mhu@ff63c420 {
		status = "okay";
		compatible = "amlogic, meson_mhu_pl";
		reg = <0x0 0xff63c420 0x0 0x4>,   /*from ao sts registers */
		      <0x0 0xff63c428 0x0 0x4>,   /*to ao set registers */
		      <0x0 0xff63c430 0x0 0x4>,   /*to ao clr registers */
		      <0x0 0xfffc7400 0x0 0x400>;   /*to ao payload */
		interrupts = <0 210 1>,  /* ap Rev se*/
			     <0 136 1>;  /* ap Send se*/
		mbox-names = "ao_dev",
			     "ap_to_ao";
		#mbox-cells = <1>;
		mboxes = <&mailbox_pl 0>,
			 <&mailbox_pl 1>;
		mbox-nums = <2>;
		mbox-mb = <1>;
	};

	cpu_iomap {
		compatible = "amlogic, iomap";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		io_cbus_base {
			reg = <0x0 0xffd00000 0x0 0x101000>;
		};
		io_apb_base {
			reg = <0x0 0xffe01000 0x0 0x19f000>;
		};
		io_aobus_base {
			reg = <0x0 0xff800000 0x0 0x100000>;
		};
		io_vapb_base {
			reg = <0x0 0xff900000 0x0 0x200000>;
		};
		io_hiu_base {
			reg = <0x0 0xff63c000 0x0 0x2000>;
		};
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	aml_pm {
		compatible = "amlogic, pm";
		status = "okay";
		device_name = "aml_pm";
		reg = <0x0 0xff8000a8 0x0 0x4>, /*SYSCTRL_STATUS_REG2*/
			<0x0 0xff6345cc 0x0 0x4>; /*PREG_STICKY_REG3*/
	};

	cpuinfo {
		compatible = "amlogic, cpuinfo";
		status = "okay";
		cpuinfo_cmd = <0x82000044>;
	};

	vrtc: rtc@0xfe010288 {
		compatible = "amlogic,meson-vrtc";
		reg = <0x0 0xff8000a8 0x0 0x4>;
		status = "okay";
		mboxes = <&mailbox_pl 1>;
	};

	reboot {
		compatible = "aml, reboot";
		sys_reset = <0x84000009>;
		sys_poweroff = <0x84000008>;
	};

	ram-dump {
		compatible = "amlogic, ram_dump";
		status = "disabled";
		reg = <0x0 0xFF6345E0 0x0 4>;
		reg-names = "PREG_STICKY_REG8";
		store_device = "data";
	};

	vpu: vpu {
		compatible = "amlogic, vpu-t5d";
		status = "okay";
		clocks = <&peripheral_clkc CLKID_VAPB_MUX>,
			<&peripheral_clkc CLKID_VPU_P0_GATE>,
			<&peripheral_clkc CLKID_VPU_P1_GATE>,
			<&peripheral_clkc CLKID_VPU_MUX>,
			<&clkc CLKID_VPU_INTR>;
		clock-names = "vapb_clk",
			"vpu_clk0",
			"vpu_clk1",
			"vpu_clk",
			"vpu_intr_gate";
		reg = <0x0 0xff646000 0x0 0x200    /* clk */
			0x0 0xff644000 0x0 0x40     /* pwrctrl */
			0x0 0xff900000 0x0 0x40000>; /* vcbus */
		clk_level = <4>;
		/* 0: 100.0M    1: 166.7M    2: 200.0M    3: 250.0M */
		/* 4: 333.3M    5: 400.0M */
	};

	meson_uvm{
		compatible = "amlogic, meson_uvm";
		status = "disabled";
	};

	meson_videotunnel{
		compatible = "amlogic, meson_videotunnel";
		status = "okay";
	};

	ethmac: ethernet@ff3f0000 {
		compatible = "amlogic,meson-axg-dwmac",
			     "snps,dwmac-3.70a",
			     "snps,dwmac";
		reg = <0x0 0xff3f0000 0x0 0x10000>,
			  <0x0 0xff634400 0x0 0x8>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
		clocks = <&clkc CLKID_ETH_CORE>,
			 <&clkc CLKID_FCLK_DIV2>,
			 <&clkc CLKID_MPLL2>;
		clock-names = "stmmaceth", "clkin0", "clkin1";
		rx-fifo-depth = <4096>;
		tx-fifo-depth = <2048>;
		status = "disabled";

		mdio0: mdio {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dwmac-mdio";
		};
	};

	pinctrl_aobus: pinctrl@ff800014 {
		compatible = "amlogic,meson-t5d-aobus-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio_ao: ao-bank@ff800014 {
			reg = <0x0 0xff800014 0x0 0x8>,
				  <0x0 0xff800024 0x0 0x14>,
				  <0x0 0xff80001c 0x0 0x8>;
			reg-names = "mux", "gpio", "ds";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aobus 0 0 14>;
		};
	};

	pinctrl_analog: pinctrl@ff63448c {
		compatible = "amlogic,meson-t5d-analog-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio_analog: analog-bank@ff63448c {
			reg = <0x0 0xff634480 0x0 0x4>,
			      <0x0 0xff63448c 0x0 0x8>;
			reg-names = "mux", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_analog 0 0 3>;
		};
	};

	pinctrl_periphs: pinctrl@ff6346c0 {
		compatible = "amlogic,meson-t5d-periphs-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio: banks@ff6346c0 {
			reg = <0x0 0xff6346c0 0x0 0x40>,
				  <0x0 0xff6344e8 0x0 0x18>,
				  <0x0 0xff634520 0x0 0x18>,
				  <0x0 0xff634440 0x0 0x3c>,
				  <0x0 0xff634740 0x0 0x24>;
			reg-names = "mux",
				"pull",
				"pull-enable",
				"gpio",
				"ds";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_periphs 0 0 99>;
		};

		hdmirx_a_mux:hdmirx_a_mux {
			mux {
				groups = "hdmirx_a_hpd", "hdmirx_a_det",
					"hdmirx_a_sda", "hdmirx_a_sck";
				function = "hdmirx_a";
			};
		};

		hdmirx_b_mux:hdmirx_b_mux {
			mux {
				groups = "hdmirx_b_hpd", "hdmirx_b_det",
					"hdmirx_b_sda", "hdmirx_b_sck";
				function = "hdmirx_b";
			};
		};

		hdmirx_c_mux:hdmirx_c_mux {
			mux {
				groups = "hdmirx_c_hpd", "hdmirx_c_det",
					"hdmirx_c_sda", "hdmirx_c_sck";
				function = "hdmirx_c";
			};
		};

		aocecb_mux:aocecb_mux {
			mux {
				groups = "cec";
				function = "cec";
			};
		};
	};

	crg: crg@ff500000 {
		compatible = "amlogic, crg";
		status = "disabled";
		reg = <0x0 0xff500000 0x0 0x100000>;
		interrupts = <0 30 4>;
		usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
		cpu-type = "gxl";
		clock-src = "usb3.0";
		clocks = <&clkc CLKID_USB_GENERAL>;
		clock-names = "crg_general";
	};

	usb2_phy_v2: usb2phy@ffe09000 {
		compatible = "amlogic, amlogic-new-usb2-v2";
		status = "disabled";
		reg = <0x0 0xffe09000 0x0 0x80
				0x0 0xffd01008 0x0 0x100
				0x0 0xff636000 0x0 0x2000
				0x0 0xff63a000 0x0 0x2000
				0x0 0xff658000 0x0 0x2000>;
		pll-setting-1 = <0x09400414>;
		pll-setting-2 = <0x927E0000>;
		pll-setting-3 = <0xac5f69e5>;
		pll-setting-4 = <0xbe18>;
		pll-setting-5 = <0x7>;
		pll-setting-6 = <0x78000>;
		pll-setting-7 = <0xe0004>;
		pll-setting-8 = <0xe000c>;
		version = <3>;
		pwr-ctl = <0>;
		usb-phy-trim-reg = <0xff800270>;
	};

	usb3_phy_v2: usb3phy@ffe09080 {
		compatible = "amlogic, amlogic-new-usb3-v2";
		status = "disable";
		reg = <0x0 0xffe09080 0x0 0x20
			0x0 0xffd01008 0x0 0x100>;
		phy-reg = <0xff646000>;
		phy-reg-size = <0x2000>;
		usb2-phy-reg = <0xffe09000>;
		usb2-phy-reg-size = <0x80>;
		interrupts = <0 16 4>;
		pwr-ctl = <0>;
	};

	dwc2_a: dwc2_a@ff400000 {
		compatible = "amlogic, dwc2";
		status = "disabled";
		device_name = "dwc2_a";
		reg = <0x0 0xff400000 0x0 0x40000>;
		interrupts = <0 31 4>;
		pl-periph-id = <0>; /** lm name */
		clock-src = "usb0"; /** clock src */
		port-id = <0>;  /** ref to mach/usb.h */
		port-type = <2>;        /** 0: otg, 1: host, 2: slave */
		port-speed = <0>; /** 0: default, high, 1: full */
		port-config = <0>; /** 0: default */
		/*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
		port-dma = <0>;
		port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
		usb-fifo = <728>;
		cpu-type = "v2";
		phy-reg = <0xffe09000>;
		phy-reg-size = <0xa0>;
		/** phy-interface: 0x0: amlogic-v1 phy, 0x1: synopsys phy **/
		/**                0x2: amlogic-v2 phy                    **/
		phy-interface = <0x2>;
		clocks = <&clkc CLKID_USB_GENERAL
					&clkc CLKID_USB1_TO_DDR>;
		clock-names = "usb_general",
					"usb1";
	};

	dolby_fw: dolby_fw {
		compatible = "amlogic, dolby_fw";
		mem_size = <0x100000>;
		status = "okay";
	};

	wdt: watchdog@0xffd0f0d0 {
		compatible = "amlogic,meson-gxbb-wdt";
		status = "okay";
		/* 0:userspace, 1:kernel */
		amlogic,feed_watchdog_mode = <1>;
		reg = <0x0 0xffd0f0d0 0x0 0x10>;
		clocks = <&xtal>;
	};

	jtag {
		compatible = "amlogic, jtag";
		status = "okay";
		select = "disable"; /* disable/apao */
		interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
		pinctrl-names="jtag_a_pins";
		pinctrl-0=<&jtag_apao_pins>;
	};

	saradc:saradc {
		compatible = "amlogic,meson-g12a-saradc";
		status = "disabled";
		#io-channel-cells = <1>;
		clocks = <&xtal>,
		    <&clkc_AO CLKID_AO_SAR_ADC>,
		    <&clkc_AO CLKID_SARADC_GATE>,
		    <&clkc_AO CLKID_SARADC_MUX>;
		clock-names = "clkin", "core",
		    "adc_clk", "adc_sel";
		interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
		reg = <0x0 0xff809000 0x0 0x48>;
	};

	vddcpu0: pwmb-regulator {
		compatible = "pwm-regulator";
		pwms = <&pwm_ab MESON_PWM_1 1500 0>;
		regulator-name = "vddcpu0";
		regulator-min-microvolt = <690000>;
		regulator-max-microvolt = <1050000>;
		regulator-always-on;
		max-duty-cycle = <1500>;
		/* Voltage Duty-Cycle */
		voltage-table = <1050000 0>,
				<1040000 3>,
				<1030000 6>,
				<1020000 9>,
				<1010000 12>,
				<1000000 14>,
				<990000 17>,
				<980000 20>,
				<970000 23>,
				<960000 26>,
				<950000 29>,
				<940000 31>,
				<930000 34>,
				<920000 37>,
				<910000 40>,
				<900000 43>,
				<890000 45>,
				<880000 48>,
				<870000 51>,
				<860000 54>,
				<850000 56>,
				<840000 59>,
				<830000 62>,
				<820000 65>,
				<810000 68>,
				<800000 70>,
				<790000 73>,
				<780000 76>,
				<770000 79>,
				<760000 81>,
				<750000 84>,
				<740000 87>,
				<730000 89>,
				<720000 92>,
				<710000 95>,
				<700000 98>,
				<690000 100>;
		status = "disabled";
	};

	cpu_opp_table0: cpu_opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <790000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <790000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <790000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <667000000>;
			opp-microvolt = <790000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <790000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <830000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1404000000>;
			opp-microvolt = <850000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <890000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <930000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-microvolt = <970000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1010000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <1908000000>;
			opp-microvolt = <1030000>;
		};
	};

	cpu_opp_table1: cpu_opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <790000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <790000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <790000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <667000000>;
			opp-microvolt = <790000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <790000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <830000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1404000000>;
			opp-microvolt = <850000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <890000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <930000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-microvolt = <970000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1010000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <1908000000>;
			opp-microvolt = <1030000>;
		};
	};

	cpu_opp_table2: cpu_opp_table2 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <750000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <750000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <750000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <667000000>;
			opp-microvolt = <750000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <750000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <770000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1404000000>;
			opp-microvolt = <800000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <840000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <860000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-microvolt = <900000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <940000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <1908000000>;
			opp-microvolt = <990000>;
		};
	};

	cpu_opp_table3: cpu_opp_table3 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <730000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <730000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <730000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <667000000>;
			opp-microvolt = <730000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <730000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <730000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1404000000>;
			opp-microvolt = <750000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <780000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <810000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-microvolt = <840000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <880000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <1908000000>;
			opp-microvolt = <940000>;
		};
	};

	cpufreq-meson {
		compatible = "amlogic, cpufreq-meson";
		status = "okay";
	};

	aml_dma {
		compatible = "amlogic,aml_txlx_dma";
		reg = <0x0 0xff63e000 0x0 0x48>;
		interrupts = <0 180 1>;

		aml_aes {
			compatible = "amlogic,aes_g12a_dma";
			dev_name = "aml_aes_dma";
			status = "okay";
		};

		aml_sha {
			compatible = "amlogic,sha_dma";
			dev_name = "aml_sha_dma";
			status = "okay";
		};
	};

	rng {
		compatible = "amlogic,meson-rng";
		status = "okay";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0xff630218 0x0 0x4>;
		quality = /bits/ 16 <1000>;
	};

	pwrdm: power-domains {
		compatible = "amlogic,t5-power-domain";
		#power-domain-cells = <1>;
		status = "okay";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hiubus: hiubus@ff63c000 {
			compatible = "simple-bus";
			reg = <0x0 0xff63c000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;

			hhi: system-controller@0 {
				compatible = "amlogic,meson-gx-hhi-sysctrl",
						"simple-mfd", "syscon";

				reg = <0 0 0 0x400>;
				clkc: clock-controller@0 {
					compatible = "amlogic,t5d-clkc";
					#clock-cells = <1>;
					clocks = <&xtal>;
					clock-names = "xtal";
				};
			};
		};/* end of hiubus*/

		hiubus1: hiubus@ff646000 {
			compatible = "simple-bus";
			reg = <0x0 0xff646000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff646000 0x0 0x2000>;

			hhi1: system-controller@1 {
				compatible = "amlogic,meson-gx-hhi-sysctrl",
						"simple-mfd", "syscon";

				reg = <0 0 0 0x400>;
				peripheral_clkc: clock-controller@1 {
					compatible = "amlogic,t5d-periph-clkc";
					#clock-cells = <1>;

					clocks = <&clkc CLKID_FCLK_DIV2>,
						<&clkc CLKID_FCLK_DIV3>,
						<&clkc CLKID_FCLK_DIV4>,
						<&clkc CLKID_FCLK_DIV5>,
						<&clkc CLKID_FCLK_DIV7>,
						<&clkc CLKID_FCLK_DIV2P5>,
						<&xtal>;
					clock-names = "fclk_div2", "fclk_div3", "fclk_div4",
							"fclk_div5", "fclk_div7",
							"fclk_div2p5", "xtal";
				};
			};
		};/* end of hiubus1*/

		eth_phy: mdio-multiplexer@ff64c000 {
			compatible = "amlogic,g12a-mdio-mux";
			reg = <0x0 0xff64c000 0x0 0xa4>;
			clocks = <&clkc CLKID_ETH_PHY>,
				 <&xtal>,
				 <&clkc CLKID_MPLL_50M>;
			clock-names = "pclk", "clkin0", "clkin1";
			mdio-parent-bus = <&mdio0>;
			#address-cells = <1>;
			#size-cells = <0>;
			enet_type = <4>;
			tx_amp_src = <0xFF800270>;

			ext_mdio: mdio@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			int_mdio: mdio@1 {
				reg = <1>;
				#address-cells = <1>;
				#size-cells = <0>;

				internal_ephy: ethernet_phy@8 {
					compatible = "ethernet-phy-id0180.3301",
						     "ethernet-phy-ieee802.3-c22";
					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
					reg = <8>;
					max-speed = <100>;
				};
			};
		};

		audiobus: audiobus@0xff600000 {
			compatible = "amlogic, audio-controller", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			reg = <0x0 0xff600000 0x0 0x3000>;
			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x3000>;
			chip_id = <0x35>;

			clkaudio:audio_clocks {
				compatible = "amlogic, t5-audio-clocks";
				#clock-cells = <1>;
				reg = <0x0 0x0 0x0 0xb0>;
			};

			ddr_manager {
				compatible =
					"amlogic, t5-audio-ddr-manager";
				interrupts = <
					GIC_SPI 148 IRQ_TYPE_EDGE_RISING
					GIC_SPI 149 IRQ_TYPE_EDGE_RISING
					GIC_SPI 150 IRQ_TYPE_EDGE_RISING
					GIC_SPI 48 IRQ_TYPE_EDGE_RISING
					GIC_SPI 152 IRQ_TYPE_EDGE_RISING
					GIC_SPI 153 IRQ_TYPE_EDGE_RISING
					GIC_SPI 154 IRQ_TYPE_EDGE_RISING
					GIC_SPI 49 IRQ_TYPE_EDGE_RISING
				>;
				interrupt-names =
					"toddr_a", "toddr_b", "toddr_c",
					"toddr_d",
					"frddr_a", "frddr_b", "frddr_c",
					"frddr_d";
			};

			pinctrl_audio: pinctrl {
				compatible = "amlogic, audio-pinctrl";
			};
		};/* end of audiobus*/

		demux: demux {
			compatible = "amlogic, dmx";
			status = "okay";

			interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING
				GIC_SPI 5 IRQ_TYPE_EDGE_RISING
				GIC_SPI 53 IRQ_TYPE_EDGE_RISING
				GIC_SPI 19 IRQ_TYPE_EDGE_RISING
				GIC_SPI 25 IRQ_TYPE_EDGE_RISING
				GIC_SPI 18 IRQ_TYPE_EDGE_RISING
				GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "demux0_irq",
				"demux1_irq",
				"demux2_irq",
				"dvr0_irq",
				"dvr1_irq",
				"dvrfill0_fill",
				"dvrfill1_flush";
		};

		/* Sound iomap */
		aml_snd_iomap {
			compatible = "amlogic, snd-iomap";
			status = "okay";
			#address-cells=<2>;
			#size-cells=<2>;
			ranges;
			pdm_bus {
				reg = <0x0 0xFF601000 0x0 0x400>;
			};
			audiobus_base {
				reg = <0x0 0xFF600000 0x0 0x1000>;
			};
			audiolocker_base {
				reg = <0x0 0xFF601400 0x0 0x400>;
			};
			eqdrc_base {
				reg = <0x0 0xFF602000 0x0 0x1000>;
			};
			vad_base {
				reg = <0x0 0xFF601800 0x0 0x400>;
			};
			resampleA_base {
				reg = <0x0 0xFF601C00 0x0 0x104>;
			};
			resampleB_base {
				reg = <0x0 0xFF604000 0x0 0x104>;
			};
		};

		cbus: cbus@ffd00000 {
			compatible = "simple-bus";
			reg = <0x0 0xffd00000 0x0 0x27000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x27000>;

			clk-measure@18000 {
				compatible = "amlogic,meson-t5d-clk-measure";
				reg = <0x0 0x18000 0x0 0x10>;
			};

			i2c0: i2c@1f000 {
				compatible = "amlogic,meson-i2c";
				reg = <0x0 0x1f000 0x0 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
				clock-frequency = <100000>;
				status = "disabled";
			};

			i2c1: i2c@1e000 {
				compatible = "amlogic,meson-i2c";
				reg = <0x0 0x1e000 0x0 0x20>;
				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
				clock-frequency = <100000>;
				status = "disabled";
			};

			i2c2: i2c@1d000 {
				compatible = "amlogic,meson-i2c";
				reg = <0x0 0x1d000 0x0 0x20>;
				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
				clock-frequency = <100000>;
				status = "disabled";
			};

			gpio_intc: interrupt-controller@f080 {
				compatible = "amlogic,meson-gpio-intc",
						"amlogic,meson-t5d-gpio-intc";
				reg = <0x0 0xf080 0x0 0x10>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts =
					<64 65 66 67 68 69 70 71>;
			};

			pwm_ab: pwm@1b000 {
				compatible = "amlogic,meson-t5d-ee-pwm";
				reg = <0x0 0x1b000 0x0 0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
						<&xtal>,
						<&xtal>,
						<&xtal>;
				clock-names = "clkin0",
						"clkin1",
						"clkin2",
						"clkin3";
				/* default xtal 24m  clkin0-clkin2 and
				 * clkin1-clkin3 should be set the same
				 */
				status = "disabled";
			};

			pwm_cd: pwm@1a000 {
				compatible = "amlogic,meson-t5d-ee-pwm";
				reg = <0x0 0x1a000 0x0 0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
						<&xtal>,
						<&xtal>,
						<&xtal>;
				clock-names = "clkin0",
						"clkin1",
						"clkin2",
						"clkin3";
				status = "disabled";
			};

			pwm_ef: pwm@19000 {
				compatible = "amlogic,meson-t5d-ee-pwm";
				reg = <0x0 0x19000 0x0 0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
						<&xtal>,
						<&xtal>,
						<&xtal>;
				clock-names = "clkin0",
						"clkin1",
						"clkin2",
						"clkin3";
				status = "disabled";
			};

			spicc0: spi@13000 {
				compatible = "amlogic,meson-g12-spicc";
				reg = <0x0 0x13000 0x0 0x44>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clkc CLKID_SPICC0>,
					 <&peripheral_clkc CLKID_SPICC0_GATE>;
				clock-names = "core", "async";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spifc: spi@14000 {
				compatible = "amlogic,meson-spifc";
				status = "disabled";
				reg = <0x0 0x14000 0x0 0x80>;
				clock-names = "clk81";
				clocks = <&peripheral_clkc CLKID_CLK81>;
				pinctrl-names = "default";
				pinctrl-0 = <&spifc_all_pins>;
				#address-cells = <1>;
				#size-cells = <0>;
				spi-nor@0 {
					compatible = "jedec,spi-nor";
					status = "disabled";
					reg = <0>;
					spi-max-frequency = <16000000>;
				};
			};

			reset: reset-controller@1004 {
				compatible = "amlogic,meson-t5d-reset";
				reg = <0x0 0x1004 0x0 0x9C>;
				#reset-cells = <1>;
			};
		};

		aobus: aobus@ff800000 {
			compatible = "simple-bus";
			reg = <0x0 0xff800000 0x0 0xb000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff800000 0x0 0xb000>;

			cpu_version {
				reg = <0x0 0x220 0x0 0x4>;
			};

			rti: sys-ctrl@0 {
				compatible = "amlogic,meson-gx-ao-sysctrl",
						"simple-mfd", "syscon";
				reg = <0x0 0x0 0x0 0x300>;
				#address-cells = <2>;
				#size-cells = <2>;
				ranges = <0x0 0x0 0x0 0x0 0x0 0x300>;

				clkc_AO: clock-controller@2 {
					compatible = "amlogic,t5d-aoclkc";
					#clock-cells = <1>;
					clocks = <&xtal>;
					clock-names = "xtal";
				};

				sec_AO: ao-secure@140 {
					compatible = "amlogic,meson-gx-ao-secure", "syscon";
					reg = <0x0 0x140 0x0 0x140>;
					amlogic,has-chip-id;
				};

			};

			uart_AO: serial@3000 {
				compatible = "amlogic, meson-uart";
				reg = <0x0 0x3000 0x0 0x18>;
				interrupts = <0 193 1>;
				status = "disabled";
				clocks = <&xtal>;
				clock-names = "clk_uart";
				xtal_tick_en = <2>;
				fifosize = < 64 >;
				//pinctrl-names = "default";
				//pinctrl-0 = <&ao_a_uart_pins>;
				/* 0 not support; 1 support */
				support-sysrq = <0>;
			};

			uart_AO_B: serial@4000 {
				compatible = "amlogic, meson-uart";
				reg = <0x0 0x4000 0x0 0x18>;
				interrupts = <0 197 1>;
				status = "disabled";
				clocks = <&xtal>;
				clock-names = "clk_uart";
				fifosize = < 64 >;
				pinctrl-names = "default";
				pinctrl-0 = <&ao_b_uart_pins1>;
			};

			remote: rc@8040 {
				compatible = "amlogic, meson-ir";
				reg = <0x0 0x8040 0x0 0x44>,
					<0x0 0x8000 0x0 0x20>;
				status = "okay";
				protocol = <REMOTE_TYPE_NEC>;
				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
				pinctrl-names = "default";
				pinctrl-0 = <&remote_pins>;
				map = <&custom_maps>;
				max_frame_time = <200>;
			};

			irblaster: meson-irblaster@14c {
				compatible = "amlogic, meson_irblaster";
				reg = <0x0 0x14c 0x0 0x10>,
					<0x0 0x40 0x0 0x4>;
				#irblaster-cells = <2>;
				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
				status = "okay";
			};
		};/* end of aobus */

		ion_dev {
			compatible = "amlogic, ion_dev";
			memory-region = <&ion_cma_reserved
					&ion_fb_reserved>;
		};/* end of ion_dev*/
	}; /* end of soc*/

	uart_A: serial@ffd24000 {
		compatible = "amlogic,meson-uart";
		reg = <0x0 0xffd24000 0x0 0x18>;
		interrupts = <0 26 1>;
		status = "disabled";
		clocks = <&xtal
			&clkc CLKID_UART0>;
		clock-names = "clk_uart",
			"clk_gate";
		fifosize = < 128 >;
		pinctrl-names = "default";
		pinctrl-0 = <&a_uart_pins>;
	};

	uart_B: serial@ffd23000 {
		compatible = "amlogic,meson-uart";
		reg = <0x0 0xffd23000 0x0 0x18>;
		interrupts = <0 75 1>;
		status = "okay";
		clocks = <&xtal>;
		clock-names = "clk_uart";
		xtal_tick_en = <2>;
		fifosize = < 64 >;
		//pinctrl-names = "default";
		//pinctrl-0 = <&ao_a_uart_pins>;
		/* 0 not support; 1 support */
		support-sysrq = <0>;
	};
	uart_C: serial@ffd22000 {
		compatible = "amlogic,meson-uart";
		reg = <0x0 0xffd22000 0x0 0x18>;
		interrupts = <0 93 1>;
		status = "disabled";
		clocks = <&xtal
			&clkc CLKID_UART2>;
		clock-names = "clk_uart",
			"clk_gate";
		fifosize = < 64 >;
		pinctrl-names = "default";
		pinctrl-0 = <&c_uart_pins>;
	};

	galcore {
		compatible = "amlogic, galcore";
		dev_name = "galcore";
		status = "disabled";
		/*clocks = <&clkc CLKID_VIPNANOQ_AXI_GATE>,
		 *	<&clkc CLKID_VIPNANOQ_CORE_GATE>;
		 *clock-names = "cts_vipnanoq_axi_clk_composite",
		 *	"cts_vipnanoq_core_clk_composite";
		 */
		interrupts = <0 147 4>;
		interrupt-names = "galcore";
		reg = <0x0 0xff100000 0x0 0x800
			0x0 0xff000000 0x0 0x400000
			0x0 0xff63c118 0x0 0x0
			0x0 0xff63c11c 0x0 0x0
			0x0 0xffd01088 0x0 0x0
			0x0 0xff63c1c8 0x0 0x0
			>;
		reg-names = "NN_REG","NN_SRAM","NN_MEM0",
			"NN_MEM1","NN_RESET","NN_CLK";
		nn_power_version = <3>;
		nn_efuse = <0xff63003c 0x20>;
	};
	sd_emmc_c: mmc@ffe07000 {
		status = "disabled";
		compatible = "amlogic,meson-axg-mmc";
		reg = <0x0 0xffe07000 0x0 0x800>,
				<0x0 0xff64625c 0x0 0x4>,
				<0x0 0xff6346c0 0x0 0x4>;
		interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
		clocks = <&clkc CLKID_SD_EMMC_C>,
				<&peripheral_clkc CLKID_SD_EMMC_C_MUX>,
				<&peripheral_clkc CLKID_SD_EMMC_C_GATE>,
				<&xtal>,
				<&clkc CLKID_GP0_PLL>,
				<&clkc CLKID_GP0_PLL>;

		clock-names = "core", "mux0", "mux1",
					"clkin0", "clkin1", "clkin2";
		card_type = <1>;
		tx_delay = <10>;
		save_para = <1>;
		src_clk_rate = <768000000>;
		compute_cmd_delay = <0>;
		compute_coef = <0>;
		mmc_debug_flag;
		/* 1:mmc card(include eMMC),
		 * 2:sd card(include tSD)
		 */
	};

	mtd_nand: nfc@0xFFE07800 {
		compatible = "amlogic,meson-nfc-single-ecc";
		status = "disabled";
		reg = <0x0 0xFFE07800 0x0 0x200>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;

		pinctrl-names = "nand_norb_mod", "nand_cs_only";
		pinctrl-0 = <&all_nand_pins>;
		pinctrl-1 = <&nand_cs_pins>;
		clocks = <&clkc CLKID_SD_EMMC_C>,
				<&clkc CLKID_FCLK_DIV2>;
		clock-names = "gate", "fdiv2pll";

		nand_clk_ctrl = <0xFFE07000>;
		/*partitions defined in dts*/
	};

	mesonstream {
		compatible = "amlogic, codec, streambuf";
		status = "okay";
		clocks = <&clkc CLKID_PARSER0
			&clkc CLKID_DEMUX
			&clkc CLKID_AHB_ARB0
			&clkc CLKID_DOS
			&peripheral_clkc CLKID_CLK81
			&peripheral_clkc CLKID_VDEC_MUX
			&peripheral_clkc CLKID_HEVCF_MUX>;
		clock-names = "parser_top",
			"demux",
			"ahbarb0",
			"vdec",
			"clk_81",
			"clk_vdec_mux",
			"clk_hevc_mux";
	};

	vcodec-dec {
		compatible = "amlogic, vcodec-dec";
		status = "okay";
	};

	vdec {
		compatible = "amlogic, vdec-pm-pd-sec-api";
		status = "okay";
		interrupts = <0 3 1
			0 23 1
			0 32 1
			0 43 1
			0 44 1
			0 45 1
			0 74 1>;
		interrupt-names = "vsync",
			"demux",
			"parser",
			"mailbox_0",
			"mailbox_1",
			"mailbox_2",
			"parser_b";
		power-domains = <&pwrdm PDID_T5_DOS_VDEC>,
			<&pwrdm PDID_T5_DOS_HCODEC>,
			<&pwrdm PDID_T5_DOS_HEVC>;
		power-domain-names = "pwrc-vdec",
			"pwrc-hcodec",
			"pwrc-hevc";
	};

	amvenc_avc{
		compatible = "amlogic, amvenc_avc";
		dev_name = "amvenc_avc";
		status = "disabled";
		interrupts = <0 45 1>;
		interrupt-names = "mailbox_2";
	};

	jpegenc{
		compatible = "amlogic, jpegenc";
		dev_name = "jpegenc";
		status = "disabled";
		interrupts = <0 45 1>;
		interrupt-names = "mailbox_2";
	};

	canvas: canvas {
		compatible = "amlogic, meson, canvas";
		status = "okay";
		reg = <0x0 0xff638048 0x0 0x2000>;
	};

	codec_io: codec_io {
		compatible = "amlogic, meson-t5d, codec-io";
		status = "okay";
		#address-cells=<2>;
		#size-cells=<2>;
		ranges;
		reg =	<0x0 0xffd00000 0x0 0x100000>,
			<0x0 0xff620000 0x0 0x10000>,
			<0x0 0xff63c000 0x0 0x2000>,
			<0x0 0xff800000 0x0 0x10000>,
			<0x0 0xff900000 0x0 0x40000>,
			<0x0 0xff638000 0x0 0x2000>,
			<0x0 0xff630000 0x0 0x2000>;
		reg-names = "cbus",
			    "dosbus",
			    "hiubus",
			    "aobus",
			    "vcbus",
			    "dmcbus",
			    "efusebus";
	};

	rdma {
		compatible = "amlogic, meson-tl1, rdma";
		status = "okay";
		interrupts = <0 89 1>;
		interrupt-names = "rdma";
	};

	meson_fb: fb {
		compatible = "amlogic, meson-t5d";
		memory-region = <&logo_reserved>;
		status = "disabled";
		interrupts = <0 3 1
			0 56 1
			0 89 1>;
		interrupt-names = "viu-vsync", "viu2-vsync", "rdma";
		/* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/
		display_mode_default = "1080p60hz";
		scale_mode = <1>;
		/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
		display_size_default = <1920 1080 1920 2160 32>;
		/*1920*1080*4*3 = 0x17BB000*/
		clocks = <&peripheral_clkc CLKID_VPU_CLKC_MUX>;
		clock-names = "vpu_clkc";
	};

	amhdmitx: amhdmitx{
		compatible = "amlogic, amhdmitx";
		dev_name = "amhdmitx";
		status = "disabled";
		vend-data = <&vend_data>;
		pinctrl-names="default", "hdmitx_i2c";
		pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
		pinctrl-1=<&hdmitx_hpd_gpio>;
		clocks = <&clkc CLKID_VCLK2_ENCI
			&clkc CLKID_VCLK2_VENCI0
			&clkc CLKID_VCLK2_VENCI1
			&clkc CLKID_VAPB_MUX
			&clkc CLKID_VPU_MUX>;
		clock-names = "venci_top_gate",
			"venci_0_gate",
			"venci_1_gate",
			"hdmi_vapb_clk",
			"hdmi_vpu_clk";
		interrupts = <0 7 1>;
		interrupt-names = "hdmitx_hpd";
		/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
		/* 0:M8B   1:GXBB 2:GXTVBB 3:GXL  4:GXM
		 * 5:TXL   6:TXLX 7:AXG    8:GXLX 9:TXHD
		 * 10:G12A 11:G12B 12:SM1  13:TM2 14:TM2B
		 */
		ic_type = <14>;
		vend_data: vend_data{ /* Should modified by Customer */
			vendor_name = "Amlogic"; /* Max Chars: 8 */
			product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
			/* standards.ieee.org/develop/regauth/oui/oui.txt */
			vendor_id = <0x000000>;
		};
	};

	ge2d {
		compatible = "amlogic, ge2d-t5";
		status = "okay";
		interrupts = <0 146 1>;
		interrupt-names = "ge2d";
		clocks = <&peripheral_clkc CLKID_VAPB_MUX>,
			<&clkc CLKID_G2D>,
			<&peripheral_clkc CLKID_GE2D_GATE>;
		clock-names = "clk_vapb_0",
			"clk_ge2d",
			"clk_ge2d_gate";
		reg = <0x0 0xff940000 0x0 0x10000>;
	};

	meson-amvideom {
		compatible = "amlogic, amvideom-t5d";
		status = "okay";
		interrupts = <0 3 1>;
		interrupt-names = "vsync";
	};

	ionvideo {
		compatible = "amlogic, ionvideo";
		status = "okay";
	};

	amlvideo {
		compatible = "amlogic, amlvideo";
		status = "okay";
	};

	meson_uvm {
		compatible = "amlogic, meson_uvm";
		status = "okay";
	};

	video_composer {
		compatible = "amlogic, video_composer";
		dev_name = "video_composer";
		status = "okay";
	};

	vclk_serve: vclk_serve {
		compatible = "amlogic, vclk_serve";
		status = "okay";
		reg = <0x0 0xff63c000 0x0 0x400    /* ana reg */
			0x0 0xff646000 0x0 0x4a0>; /* clk reg */
	};

	vout: vout {
		compatible = "amlogic, vout";
		status = "okay";

		/* fr_policy:
		 *    0: disable
		 *    1: nearby (only for 60->59.94 and 30->29.97)
		 *    2: force (60/50/30/24/59.94/23.97)
		 */
		fr_policy = <2>;
	};

	vout2: vout2 {
		compatible = "amlogic, vout2";
		status = "okay";
		clocks = <&peripheral_clkc CLKID_VPU_CLKC_P0_GATE>,
			<&peripheral_clkc CLKID_VPU_CLKC_MUX>;
		clock-names = "vpu_clkc0",
			"vpu_clkc";

		/* fr_policy:
		 *    0: disable
		 *    1: nearby (only for 60->59.94 and 30->29.97)
		 *    2: force (60/50/30/24/59.94/23.97)
		 */
		fr_policy = <2>;
	};

	vdac {
		compatible = "amlogic, vdac-t5d";
		status = "okay";
	};

	adc: adc {
		compatible = "amlogic, adc-t5d";
		status = "okay";
		reg = <0x0 0xff654000 0x0 0x2000/* afe reg base */
			0x0 0xff63c000 0x0 0x2000/* hiu base */>;
	};

	dummy_venc: dummy_venc {
		compatible = "amlogic, dummy_venc";
		status = "okay";
		clocks = <&clkc CLKID_VCLK2_ENCP
			&clkc CLKID_VCLK2_VENCP0
			&clkc CLKID_VCLK2_VENCP1
			&clkc CLKID_VCLK2_ENCI
			&clkc CLKID_VCLK2_VENCI0
			&clkc CLKID_VCLK2_VENCI1
			&clkc CLKID_VCLK2_ENCL
			&clkc CLKID_VCLK2_VENCL>;
		clock-names = "encp_top_gate",
			"encp_int_gate0",
			"encp_int_gate1",
			"venci_top_gate",
			"enci_int_gate0",
			"enci_int_gate1",
			"encl_top_gate",
			"encl_int_gate";
	};

	ddr_bandwidth {
		compatible = "amlogic,ddr-bandwidth-t5d";
		status = "okay";
		reg = <0x0 0xff638000 0x0 0x400
		       0x0 0xff638c00 0x0 0x100>;
		interrupts = <0 52 1>;
		interrupt-names = "ddr_bandwidth";
	};

	dmc_monitor {
		compatible = "amlogic,dmc_monitor-t5d";
		status = "okay";
		reg = <0x0 0xff638280 0x0 0x100>;
		reg_base = <0xff639000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
	};

	efuse: efuse{
		compatible = "amlogic, efuse";
		read_cmd = <0x82000030>;
		write_cmd = <0x82000031>;
		get_max_cmd = <0x82000033>;
		key = <&efusekey>;
		clocks = <&clkc CLKID_EFUSE>;
		clock-names = "efuse_clk";
		status = "disabled";
	};

	efusekey:efusekey{
		keynum = <4>;
		key0 = <&key_0>;
		key1 = <&key_1>;
		key2 = <&key_2>;
		key3 = <&key_3>;
		key_0:key_0{
			keyname = "mac";
			offset = <0>;
			size = <6>;
		};
		key_1:key_1{
			keyname = "mac_bt";
			offset = <6>;
			size = <6>;
		};
		key_2:key_2{
			keyname = "mac_wifi";
			offset = <12>;
			size = <6>;
		};
		key_3:key_3{
			keyname = "usid";
			offset = <18>;
			size = <16>;
		};
	};

	/* Audio Related start */
	dummy_codec:dummy {
		#sound-dai-cells = <0>;
		compatible = "amlogic, aml_dummy_codec";
		status = "okay";
	};

	acodec:codec {
		#sound-dai-cells = <0>;
		compatible = "amlogic, tm2_revb_acodec";
		status = "okay";
		reg = <0x0 0xff632000 0x0 0x1c>;
		tdmout_index = <1>;
		tdmin_index = <1>;
		dat0_ch_sel = <1>;
		reset-names = "acodec";
		resets = <&reset RESET_AUDIO_CODEC>;
	};

	audio_data: audio_data {
		compatible = "amlogic, audio_data";
		mem_in_base_cmd = <0x82000020>;
		query_licence_cmd = <0x82000050>;
		status = "okay";
	}; /* Audio Related end */

	defendkey: defendkey {
		compatible = "amlogic, defendkey";
		reg=<0x0 0xff800228 0x0 0x4>;
		mem_size = <0x100000>;
		status = "okay";
	};

	cpu_ver_name {
		compatible = "amlogic, cpu-major-id-t5d";
	};

	lut_dma:lut_dma {
		compatible = "amlogic, meson, lut_dma";
		status = "disabled";
	};

	p_tsensor: p_tsensor@ff634800 {
		compatible = "amlogic, r1p1-tsensor";
		status = "okay";
		reg = <0x0 0xff634800 0x0 0x50>,
			<0x0 0xff800268 0x0 0x4>;
		cal_type = <0x1>;
		cal_coeff = <324 424 3159 9411>;
		rtemp = <120000>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&peripheral_clkc CLKID_TS>; // CLKID_TS_COMP>;
		clock-names = "ts_comp";
		#thermal-sensor-cells = <1>;
	};

	meson_cooldev: meson-cooldev@0 {
		status = "okay";
		compatible = "amlogic, meson-cooldev";
		cooling_devices {
			ddr_cool {
				ddr_reg = <0xff6384b4>;
				ddr_status = <3>;
				ddr_bits = <8 15>;
				ddr_data = <0x4c 0x26 0x13>;
				node_name = "ddr_cool0";
				device_type = "ddr";
			};
			cpucore_cool_cluster0 {
				cluster_id = <0>;
				node_name = "cpucore0";
				device_type = "cpucore";
			};
			gpufreq_cool {
				dyn_coeff = <245>;
				node_name = "bifrost";
				device_type = "gpufreq";
			};
		};
		ddr_cool0:ddr_cool0 {
			#cooling-cells = <2>; /* min followed by max */
		};
		cpucore0:cpucore0 {
			#cooling-cells = <2>; /* min followed by max */
		};
	};/*meson cooling devices end*/

	thermal-zones {
		soc_thermal: soc_thermal {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			sustainable-power = <1100>;
			thermal-sensors = <&p_tsensor 0>;
			trips {
				pswitch_on: trip-point@0 {
					temperature = <95000>;
					hysteresis = <5000>;
					type = "passive";
				};
				pcontrol: trip-point@1 {
					temperature = <100000>;
					hysteresis = <5000>;
					type = "passive";
				};
				pddr_change: trip-point@2 {
					temperature = <75000>;
					hysteresis = <10000>;
					type = "hot";
				};
				pcritical: trip-point@3 {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
			cooling-maps {
				cpufreq_cooling_map {
					trip = <&pcontrol>;
					cooling-device = <&CPU0 0 8>;
					contribution = <1024>;
				};
				ddr_cooling_map {
					trip = <&pddr_change>;
					cooling-device = <&ddr_cool0 0 2>;
					contribution = <1024>;
				};
				gpufreq_cooling_map {
					trip = <&pcontrol>;
					cooling-device = <&gpu 0 3>;
					contribution = <1024>;
				};
			};
		};
	}; /*thermal zone end*/

	aml_bt: aml_bt {
		compatible = "amlogic, aml-bt";
		status = "disabled";
	};

	aml_wifi: aml_wifi {
		compatible = "amlogic, aml-wifi";
		status = "disabled";
		irq_trigger_type = "GPIO_IRQ_LOW";
		/* dhd_static_buf; */ /* if use bcm wifi, config dhd_static_buf */
		//pinctrl-0 = <&pwm_e_pins>;
		//pinctrl-names = "default";
		//pwm_config = <&wifi_pwm_conf>;
	};

}; /* end of / */

&pinctrl_aobus {
	/* GPIO_D2/D3 */
	i2c0_d_pins:i2c0_d {
		mux {
			groups = "i2c0_ao_sck",
				"i2c0_ao_sda";
			function = "i2c0_ao";
			bias-disable;
			drive-strength-microamp = <3000>;
		};
	};

	i2c0_d_pins_slp_input:i2c0_d_slp_input {
		mux {
			groups = "GPIOD_2", "GPIOD_3";
			function = "gpio_aobus";
			input-enable;
			bias-disable;
		};
	};

	i2c0_d_pins_slp_low:i2c0_d_slp_low {
		mux {
			groups = "GPIOD_2", "GPIOD_3";
			function = "gpio_aobus";
			output-low;
		};
	};

	i2c2_e_pins:i2c2_e {
		mux {
			groups = "i2c2_ao_sck",
				"i2c2_ao_sda";
			function = "i2c2_ao";
			bias-disable;
			drive-strength-microamp = <3000>;
		};
	};

	i2c2_e_pins_slp_input:i2c2_e_slp_input {
		mux {
			groups = "GPIOE_0", "GPIOE_1";
			function = "gpio_aobus";
			input-enable;
			bias-disable;
		};
	};

	i2c2_e_pins_slp_low:i2c2_e_slp_low {
		mux {
			groups = "GPIOE_0", "GPIOE_1";
			function = "gpio_aobus";
			output-low;
		};
	};

	sd_to_ao_uart_clr_pins: sd_to_ao_uart_clr_pins {
		mux {
			groups = "GPIOAO_0",
				   "GPIOAO_1",
				   "GPIOAO_2",
				   "GPIOAO_3",
				   "GPIOAO_4",
				   "GPIOAO_5",
				   "GPIOAO_6",
				   "GPIOAO_7",
				   "GPIOAO_8",
				   "GPIOAO_9",
				   "GPIOAO_10",
				   "GPIOAO_11",
				   "GPIOE_0",
				   "GPIOE_1",
				   "GPIOE_2",
				   "GPIO_TEST_N";
			function = "gpio_aobus";
		};
	};

	sd_to_ao_uart_pins: sd_to_ao_uart_pins {
		mux {
			groups = "uart_ao_a_tx",
				   "uart_ao_a_rx",
				   "uart_ao_a_cts",
				   "uart_ao_a_rts";
			function = "uart_ao_a";
			bias-pull-up;
			input-enable;
		};
	};

	remote_pins:remote_pin {
		mux {
			groups = "remote_input_ao";
			function = "remote_input_ao";
		};
	};

	pwm_ao_a_pins: pwm_ao_a_pins {
		mux {
			groups = "pwm_ao_a";
			function = "pwm_ao_a";
		};
	};

	pwm_ao_b_pins: pwm_ao_b_pins {
		mux {
			groups = "pwm_ao_b";
			function = "pwm_ao_b";
		};
	};

	pwm_ao_c_pins1: pwm_ao_c_pins1 {
		mux {
			groups = "pwm_ao_c_d5";
			function = "pwm_ao_c";
		};
	};

	pwm_ao_c_pins2: pwm_ao_c_pins2 {
		mux {
			groups = "pwm_ao_c_d7";
			function = "pwm_ao_c";
		};
	};

	pwm_ao_c_hiz_pins: pwm_ao_c_hiz_pins {
		mux {
			groups = "pwm_ao_c_hiz";
			function = "pwm_ao_c_hiz";
		};
	};

	pwm_ao_d_pins1: pwm_ao_d_pins1 {
		mux {
			groups = "pwm_ao_d_d6";
			function = "pwm_ao_d";
		};
	};

	pwm_ao_d_pins2: pwm_ao_d_pins2 {
		mux {
			groups = "pwm_ao_d_d9";
			function = "pwm_ao_d";
		};
	};

	pwm_ao_d_hiz_pins: pwm_ao_d_hiz_pins {
		mux {
			groups = "pwm_ao_d_hiz";
			function = "pwm_ao_d_hiz";
		};
	};

	pwm_ao_e_pins: pwm_ao_e_pins {
		mux {
			groups = "pwm_ao_e";
			function = "pwm_ao_e";
		};
	};

	ao_uart_pins:ao_uart {
		mux {
			groups = "uart_ao_a_rx",
				"uart_ao_a_tx";
			function = "uart_ao_a";
		};
	};

	ao_b_uart_pins1:ao_b_uart1 {
		mux {
			groups = "uart_ao_b_tx_2",
				"uart_ao_b_rx_3";
			function = "uart_ao_b";
		};
	};

	ao_b_uart_pins2:ao_b_uart2 {
		mux {
			groups = "uart_ao_b_tx_8",
				"uart_ao_b_rx_9";
			function = "uart_ao_b";
		};
	};

	irblaster_ao_pins1:irblaster_ao_pins1 {
		mux {
			groups = "remote_out_ao1";
			function = "remote_out_ao";
		};
	};

	irblaster_ao_pins2:irblaster_ao_pins2 {
		mux {
			groups = "remote_out_ao9";
			function = "remote_out_ao";
		};
	};

	jtag_apao_pins:jtag_apao_pin {
		mux {
			groups = "jtag_a_tdi",
			"jtag_a_tdo",
			"jtag_a_clk",
			"jtag_a_tms";
			function = "jtag_a";
		};
	};

	spdifout_a: spdifout_a {
		mux { /* GPIOE_2 */
			groups = "spdif_out_a_ao";
			function = "spdif_out_a_ao";
		};
	};

	spdifout_a_mute: spdifout_a_mute {
		mux { /* GPIOE_2 */
			groups = "GPIOE_2";
			function = "gpio_aobus";
		};
	};

	spdifout_b: spdifout_b {
		mux { /* GPIOD_8 */
			groups = "spdif_out_b_ao";
			function = "spdif_out_b_ao";
		};
	};

	spdifout_b_mute: spdifout_b_mute {
		mux { /* GPIOD_8 */
			groups = "GPIOD_8";
			function = "gpio_aobus";
		};
	};
};

&pinctrl_periphs {
	/* sdemmc portC */
	emmc_clk_cmd_pins: emmc_clk_cmd_pins {
		mux {
			groups = "emmc_clk",
				 "emmc_cmd";
			function = "emmc";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	emmc_conf_pull_up: emmc_conf_pull_up {
		mux {
			groups = "emmc_d7",
				 "emmc_d6",
				 "emmc_d5",
				 "emmc_d4",
				 "emmc_d3",
				 "emmc_d2",
				 "emmc_d1",
				 "emmc_d0",
				 "emmc_clk",
				 "emmc_cmd";
			function = "emmc";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	emmc_conf_pull_done: emmc_conf_pull_done {
		mux {
			groups = "emmc_ds";
			function = "emmc";
			input-enable;
			bias-pull-down;
			drive-strength-microamp = <3000>;
		};
	};

	/* sdemmc portB */
	sd_clk_cmd_pins: sd_clk_cmd_pins {
		mux {
			groups = "sdcard_cmd",
				   "sdcard_clk";
			function = "sdcard";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	sd_all_pins: sd_all_pins {
		mux {
			groups = "sdcard_d0",
				   "sdcard_d1",
				   "sdcard_d2",
				   "sdcard_d3",
				   "sdcard_cmd",
				   "sdcard_clk";
			function = "sdcard";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	sd_1bit_pins: sd_1bit_pins {
		mux {
			groups = "sdcard_d0",
					"sdcard_cmd",
					"sdcard_clk";
			function = "sdcard";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	ao_to_sd_uart_pins: ao_to_sd_uart_pins {
		mux {
			groups ="uart_ao_a_rx_w3",
					"uart_ao_a_tx_w2",
					"uart_ao_a_rx_w7",
					"uart_ao_a_tx_w6",
					"uart_ao_a_rx_w11",
					"uart_ao_a_tx_w10";
			function = "uart_ao_a_ee";
			bias-pull-up;
			input-enable;
		};
	};

	emmc_pins_sleep:emmc_all_pins_sleep {
		mux {
			groups = "GPIOB_0",
					"GPIOB_1",
					"GPIOB_2",
					"GPIOB_3",
					"GPIOB_4",
					"GPIOB_5",
					"GPIOB_6",
					"GPIOB_7";
			function = "gpio_periphs";
			input-enable;
		};
		mux1 {
			groups = "GPIOB_8",
					"GPIOB_9",
					"GPIOB_10",
					"GPIOB_11";
			function = "gpio_periphs";
			input-enable;
		};
	};

	all_nand_pins: all_nand_pins {
		mux {
			groups = "emmc_nand_d0",
				"emmc_nand_d1",
				"emmc_nand_d2",
				"emmc_nand_d3",
				"emmc_nand_d4",
				"emmc_nand_d5",
				"emmc_nand_d6",
				"emmc_nand_d7",
				"nand_ce0",
				"nand_ale",
				"nand_cle",
				"nand_wen_clk",
				"nand_ren_wr";
			function = "nand";
			input-enable;
			drive-strength-microamp = <3000>;
		};
	};

	nand_cs_pins:nand_cs {
		mux {
			groups = "nand_ce0";
			function = "nand";
			drive-strength-microamp = <3000>;
		};
	};

	/* sdemmc port */
	sdio_clk_cmd_pins: sdio_clk_cmd_pins {
		mux {
			groups = "sdcard_clk",
				"sdcard_cmd";
			function = "sdcard";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	sdio_all_pins: sdio_all_pins {
		mux {
			groups = "sdcard_d0",
				"sdcard_d1",
				"sdcard_d2",
				"sdcard_d3",
				"sdcard_clk",
				"sdcard_cmd";
			function = "sdcard";
			input-enable;
			bias-pull-up;
			drive-strength-microamp = <3000>;
		};
	};

	spifc_all_pins: spifc_all_pins {
		mux {
			groups =  "spif_hold",
				"spif_mo",
				"spif_mi",
				"spif_clk",
				"spif_wp",
				"spif_cs";
			function = "spif";
			drive-strength-microamp = <3000>;
		};
	};

	pwm_b_pins1: pwm_b_pins1 {
		mux {
			groups = "pwm_b_z";
			function = "pwm_b";
		};
	};

	pwm_b_pins2: pwm_b_pins2 {
		mux {
			groups = "pwm_b_h";
			function = "pwm_b";
		};
	};

	pwm_d_pins: pwm_d_pins {
		mux {
			groups = "pwm_d";
			function = "pwm_d";
		};
	};

	pwm_e_pins1: pwm_e_pins1 {
		mux {
			groups = "pwm_e_z";
			function = "pwm_e";
		};
	};

	pwm_e_pins2: pwm_e_pins2 {
		mux {
			groups = "pwm_e_h";
			function = "pwm_e";
		};
	};

	pwm_f_pins1: pwm_f_pins1 {
		mux {
			groups = "pwm_f_z";
			function = "pwm_f";
		};
	};

	pwm_f_pins2: pwm_f_pins2 {
		mux {
			groups = "pwm_f_h";
			function = "pwm_f";
		};
	};

	irblaster_pins: irblaster_pins {
		mux {
			groups = "remote_out";
			function = "remote_out";
		};
	};

	i2c0_z_pins:i2c0_z {
		mux {
			groups = "i2c0_sck_z",
				"i2c0_sda_z";
			function = "i2c0";
			bias-disable;
			drive-strength-microamp = <3000>;
		};
	};

	i2c0_z_pins_slp_input:i2c0_z_slp_input {
		mux {
			groups = "GPIOZ_4", "GPIOZ_5";
			function = "gpio_periphs";
			input-enable;
			bias-disable;
		};
	};

	i2c0_z_pins_slp_low:i2c0_z_slp_low {
		mux {
			groups = "GPIOZ_4", "GPIOZ_5";
			function = "gpio_periphs";
			output-low;
		};
	};

	i2c1_pins:i2c1 {
		mux {
			groups = "i2c1_sck_h",
				"i2c1_sda_h";
			function = "i2c1";
			bias-disable;
			drive-strength-microamp = <3000>;
		};
	};

	i2c1_pins_slp_input:i2c1_slp_input {
		mux {
			groups = "GPIOH_20", "GPIOH_21";
			function = "gpio_periphs";
			input-enable;
			bias-disable;
		};
	};

	i2c1_pins_slp_low:i2c1_slp_low {
		mux {
			groups = "GPIOH_20", "GPIOH_21";
			function = "gpio_periphs";
			output-low;
		};
	};

	i2c2_h_pins:i2c2_h {
		mux {
			groups = "i2c2_sck_h",
				"i2c2_sda_h";
			function = "i2c2";
			bias-disable;
			drive-strength-microamp = <3000>;
		};
	};

	i2c2_h_pins_slp_input:i2c2_h_slp_input {
		mux {
			groups = "GPIOH_10", "GPIOH_11";
			function = "gpio_periphs";
			input-enable;
			bias-disable;
		};
	};

	i2c2_h_pins_slp_low:i2ch_h_slp_low {
		mux {
			groups = "GPIOH_10", "GPIOH_11";
			function = "gpio_periphs";
			output-low;
		};
	};

	spicc0_pins_h: spicc0_pins_h {
		mux {
			groups = "spi0_mosi_h",
				 "spi0_miso_h",
				 "spi0_clk_h";
			function = "spi0";
			drive-strength-microamp = <3000>;
		};
	};

	spicc0_pins_cs_h: spicc0_pins_cs_h {
		mux {
			groups = "spi0_ss0_h";
			function = "spi0";
			drive-strength-microamp = <3000>;
		};
	};

	spicc0_pins_z: spicc0_pins_z {
		mux {
			groups = "spi0_mosi_z",
				 "spi0_miso_z",
				 "spi0_clk_z";
			function = "spi0";
			drive-strength-microamp = <3000>;
		};
	};

	internal_eth_pins: internal_eth_pins {
		mux {
			groups = "eth_link_led",
				"eth_act_led";
			function = "eth";
		};
	};

	internal_gpio_pins: internal_gpio_pins {
		mux {
			groups = "GPIOH_0",
				"GPIOH_1";
			function = "gpio_periphs";
			bias-disable;
			input-enable;
		};
	};

	external_eth_pins: external_eth_pins {
		mux {
			groups = "eth_mdio",
			"eth_mdc",
			"eth_rgmii_rx_clk",
			"eth_rx_dv",
			"eth_rxd0",
			"eth_rxd1",
			"eth_rxd2_rgmii",
			"eth_rxd3_rgmii",
			"eth_rgmii_tx_clk",
			"eth_txen",
			"eth_txd0",
			"eth_txd1",
			"eth_txd2_rgmii",
			"eth_txd3_rgmii";
			function = "eth";
			drive-strength-microamp = <3000>;
		};
	};

	a_uart_pins:a_uart {
		mux {
			groups = "uart_a_tx",
				"uart_a_rx",
				"uart_a_cts",
				"uart_a_rts";
			function = "uart_a";
		};
	};

	b_uart_pins:b_uart {
		mux {
			groups = "uart_b_tx",
				"uart_b_rx";
			function = "uart_b";
		};
	};

	b_uart_pins1:b_uart1 {
		mux {
			groups = "uart_b_tx_w6",
				"uart_b_tx_w7";
			function = "uart_b";
		};
	};

	b_uart_pins2:b_uart2 {
		mux {
			groups = "uart_b_tx_w10",
				"uart_b_tx_w11";
			function = "uart_b";
		};
	};

	c_uart_pins:c_uart {
		mux {
			groups = "uart_c_tx_h",
				"uart_c_rx_h";
			function = "uart_c";
		};
	};

	hdmitx_hpd: hdmitx_hpd {
		mux {
			groups = "hdmitx_hpd_in";
			function = "hdmitx";
			bias-disable;
		};
	};

	hdmitx_hpd_gpio: hdmitx_hpd_gpio {
		mux {
			groups = "GPIOH_16";
			function = "gpio_periphs";
			bias-disable;
		};
	};

	hdmitx_ddc: hdmitx_ddc {
		mux {
			groups = "hdmitx_sda",
				"hdmitx_sck";
			function = "hdmitx";
			bias-disable;
			drive-strength-microamp = <3000>;
		};
	};
	atvdemod_agc_pins: atvdemod_agc_pins {
		mux {
			groups = "atv_if_agc";
			function = "atv";
		};
	};

	dtvdemod_if_agc_pins: dtvdemod_if_agc_pins {
		mux {
			groups = "dtv_if_agc_z6";
			function = "dtv";
		};
	};

	dtvdemod_rf_agc_pins: dtvdemod_rf_agc_pins {
		mux {
			groups = "dtv_rf_agc_z6";
			function = "dtv";
		};
	};

	diseqc_out: diseqc_out {
		mux {
			groups = "diseqc_out_z0";
			function = "diseqc_out";
			bias-pull-down;
		};
	};

	lcd_tcon_mlvds_pins: lcd_tcon_mlvds_pin {
		mux {
			groups = "tcon_0","tcon_1","tcon_2","tcon_3",
				"tcon_4","tcon_5","tcon_6";
			function = "tcon";
		};
	};
	lcd_tcon_mlvds_off_pins: lcd_tcon_mlvds_off_pin {
		mux {
			groups = "GPIOH_0","GPIOH_1","GPIOH_2","GPIOH_3",
				"GPIOH_4","GPIOH_5","GPIOH_6";
			function = "gpio_periphs";
			input-enable;
		};
	};

	dvb_p_ts2_pins: dvb_p_ts2_pins {
		mux {
			groups = "tsin_b_d0",
			"tsin_b_d1",
			"tsin_b_d2",
			"tsin_b_d3",
			"tsin_b_d4",
			"tsin_b_d5",
			"tsin_b_d6",
			"tsin_b_d7",
			"tsin_b_clk",
			"tsin_b_sop",
			"tsin_b_valid";
			function = "tsin_b";
		};
	};
	dvb_ci_bus_pins: dvb_ci_bus_pins {
		mux {
			groups = "cicam_a0", "cicam_a1",
			"cicam_data0", "cicam_data1", "cicam_data2", "cicam_data3",
			"cicam_data4", "cicam_data5", "cicam_data6", "cicam_data7",
			"cicam_cen", "cicam_oen", "cicam_wen", "cicam_iordn", "cicam_iowrn",
			"cicam_reset";
			function = "cicam";
		};
	};
	ci_ts_pins: ci_ts_pins {
		mux {
			groups = "tsout_sop",
			"tsout_valid",
			"tsout_d0",
			"tsout_d1",
			"tsout_d2",
			"tsout_d3",
			"tsout_d4",
			"tsout_d5",
			"tsout_d6",
			"tsout_d7";
			function = "tsout";
		};
	};
	ci_addr_pins: ci_addr_pins {
		mux {
			groups = "cicam_a2", "cicam_a3", "cicam_a4",
			"cicam_a5", "cicam_a6", "cicam_a7", "cicam_a8", "cicam_a9",
			"cicam_a10", "cicam_a11";
			function = "cicam";
		};
	};
	ci_ts_clk_pins: ci_ts_clk_pins {
		mux {
			groups =  "tsout_clk";
			function = "tsout";
		};
	};
	ci_gpio_pins: ci_gpio_pins {
		mux {
			groups =  "GPIOZ_7";
			function = "gpio_periphs";
		};
	};
	mclk_1_pins: mclk_1_pin {
		mux { /* GPIOH_14 */
			groups = "mclk_1";
			function = "mclk";
		};
	};

	mclk_2_pins: mclk_2_pin {
		mux { /* GPIOZ_6 */
			groups = "mclk_2";
			function = "mclk";
		};
	};
};

&gpu{
	reg = <0 0xFFE40000 0 0x40000>, /*mali APB bus base address*/
		<0 0xFFD01000 0 0x01000>, /*reset register*/
		<0 0xFF800000 0 0x01000>, /*aobus for gpu pmu domain*/
		<0 0xFF646000 0 0x01000>, /*gpu clk cntl*/
		<0 0xFFD01000 0 0x01000>; /*reset register*/
	clocks = <&peripheral_clkc CLKID_GPU_MUX>;
	clock-names = "gpu_mux";

	/*
	 * Mali clocking is provided by two identical clock paths
	 * MALI_0 and MALI_1 muxed to a single clock by a glitch
	 * free mux to safely change frequency while running.
	 */
	assigned-clocks = <&peripheral_clkc CLKID_GPU_P0_MUX>,
			  <&peripheral_clkc CLKID_GPU_P0_GATE>,
			  <&peripheral_clkc CLKID_GPU_MUX>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
				 <0>, /* Do Nothing */
				 <&peripheral_clkc CLKID_GPU_P0_GATE>;
	assigned-clock-rates = <0>, /* Do Nothing */
				   <800000000>,
				   <0>; /* Do Nothing */

	tbl =  <&dvfs285_cfg
		&dvfs400_cfg
		&dvfs500_cfg
		&dvfs666_cfg
		&dvfs800_cfg
		&dvfs800_cfg>; /* the last one of table is for preheat */
};