// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
#include "ahb.h"
#include "debug.h"
#include "hif.h"
#include "qmi.h"
#include "pci.h"
#include <linux/remoteproc.h>

static const struct of_device_id ath11k_ahb_of_match[] = {
	/* TODO: Should we change the compatible string to something similar
	 * to one that ath10k uses?
	 */
	{ .compatible = "qcom,ipq8074-wifi",
	  .data = (void *)ATH11K_HW_IPQ8074,
	},
	{ .compatible = "qcom,ipq6018-wifi",
	  .data = (void *)ATH11K_HW_IPQ6018_HW10,
	},
	{ .compatible = "qcom,ipq5018-wifi",
	  .data = (void *)ATH11K_HW_IPQ5018,
	},
	{ .compatible = "qcom,qcn6122-wifi",
	  .data = (void *)ATH11K_HW_QCN6122,
	},
	{ }
};

MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match);

static const struct ath11k_bus_params ath11k_ahb_bus_params = {
	.mhi_support = false,
	.m3_fw_support = false,
	.fixed_bdf_addr = true,
	.fixed_mem_region = true,
};

static const struct ath11k_bus_params ath11k_internal_pci_bus_params = {
	.mhi_support = false,
	.m3_fw_support = false,
	.fixed_bdf_addr = true,
	.fixed_mem_region = true,
	.static_window_map = true,
};

#define ATH11K_IRQ_CE0_OFFSET 4

static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
	"misc-pulse1",
	"misc-latch",
	"sw-exception",
	"watchdog",
	"ce0",
	"ce1",
	"ce2",
	"ce3",
	"ce4",
	"ce5",
	"ce6",
	"ce7",
	"ce8",
	"ce9",
	"ce10",
	"ce11",
	"host2wbm-desc-feed",
	"host2reo-re-injection",
	"host2reo-command",
	"host2rxdma-monitor-ring3",
	"host2rxdma-monitor-ring2",
	"host2rxdma-monitor-ring1",
	"reo2ost-exception",
	"wbm2host-rx-release",
	"reo2host-status",
	"reo2host-destination-ring4",
	"reo2host-destination-ring3",
	"reo2host-destination-ring2",
	"reo2host-destination-ring1",
	"rxdma2host-monitor-destination-mac3",
	"rxdma2host-monitor-destination-mac2",
	"rxdma2host-monitor-destination-mac1",
	"ppdu-end-interrupts-mac3",
	"ppdu-end-interrupts-mac2",
	"ppdu-end-interrupts-mac1",
	"rxdma2host-monitor-status-ring-mac3",
	"rxdma2host-monitor-status-ring-mac2",
	"rxdma2host-monitor-status-ring-mac1",
	"host2rxdma-host-buf-ring-mac3",
	"host2rxdma-host-buf-ring-mac2",
	"host2rxdma-host-buf-ring-mac1",
	"rxdma2host-destination-ring-mac3",
	"rxdma2host-destination-ring-mac2",
	"rxdma2host-destination-ring-mac1",
	"host2tcl-input-ring4",
	"host2tcl-input-ring3",
	"host2tcl-input-ring2",
	"host2tcl-input-ring1",
	"wbm2host-tx-completions-ring3",
	"wbm2host-tx-completions-ring2",
	"wbm2host-tx-completions-ring1",
	"tcl2host-status-ring",
};

/* enum ext_irq_num - irq numbers that can be used by external modules
 * like datapath
 */
enum ext_irq_num {
	host2wbm_desc_feed = 16,
	host2reo_re_injection,
	host2reo_command,
	host2rxdma_monitor_ring3,
	host2rxdma_monitor_ring2,
	host2rxdma_monitor_ring1,
	reo2host_exception,
	wbm2host_rx_release,
	reo2host_status,
	reo2host_destination_ring4,
	reo2host_destination_ring3,
	reo2host_destination_ring2,
	reo2host_destination_ring1,
	rxdma2host_monitor_destination_mac3,
	rxdma2host_monitor_destination_mac2,
	rxdma2host_monitor_destination_mac1,
	ppdu_end_interrupts_mac3,
	ppdu_end_interrupts_mac2,
	ppdu_end_interrupts_mac1,
	rxdma2host_monitor_status_ring_mac3,
	rxdma2host_monitor_status_ring_mac2,
	rxdma2host_monitor_status_ring_mac1,
	host2rxdma_host_buf_ring_mac3,
	host2rxdma_host_buf_ring_mac2,
	host2rxdma_host_buf_ring_mac1,
	rxdma2host_destination_ring_mac3,
	rxdma2host_destination_ring_mac2,
	rxdma2host_destination_ring_mac1,
	host2tcl_input_ring4,
	host2tcl_input_ring3,
	host2tcl_input_ring2,
	host2tcl_input_ring1,
	wbm2host_tx_completions_ring3,
	wbm2host_tx_completions_ring2,
	wbm2host_tx_completions_ring1,
	tcl2host_status_ring,
};

static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
{
	if (ab->ce_remap && (offset & HAL_CE_REMAP_REG_BASE)) {
		offset = offset - HAL_CE_REMAP_REG_BASE;
		return ioread32(ab->mem_ce + offset);
	} else {
		return ioread32(ab->mem + offset);
	}
}

static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value)
{
	if (ab->ce_remap && (offset & HAL_CE_REMAP_REG_BASE)) {
		offset = offset - HAL_CE_REMAP_REG_BASE;
		iowrite32(value, ab->mem_ce + offset);
	} else {
		iowrite32(value, ab->mem + offset);
	}
}

static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab)
{
	int i;

	for (i = 0; i < ab->hw_params.ce_count; i++) {
		struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];

		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
			continue;

		tasklet_kill(&ce_pipe->intr_tq);
	}
}

static void ath11k_ahb_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
{
	int i;

	for (i = 0; i < irq_grp->num_irq; i++)
		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
}

static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
{
	int i;

	for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];

		ath11k_ahb_ext_grp_disable(irq_grp);

		napi_synchronize(&irq_grp->napi);
		napi_disable(&irq_grp->napi);
	}
}

static void ath11k_ahb_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
{
	int i;

	for (i = 0; i < irq_grp->num_irq; i++)
		enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
}

static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset)
{
	u32 val;

	val = ath11k_ahb_read32(ab, offset);
	ath11k_ahb_write32(ab, offset, val | BIT(bit));
}

static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset)
{
	u32 val;

	val = ath11k_ahb_read32(ab, offset);
	ath11k_ahb_write32(ab, offset, val & ~BIT(bit));
}

static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
{
	const struct ce_pipe_config *ce_config;
	u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr;

	if  (ab->hw_rev == ATH11K_HW_IPQ5018) {
		ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS;
		ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS;
		ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS;
	} else {
		ie1_reg_addr = CE_HOST_IE_ADDRESS;
		ie2_reg_addr = CE_HOST_IE_2_ADDRESS;
		ie3_reg_addr = CE_HOST_IE_3_ADDRESS;
	}

	ce_config = &ab->hw_params.target_ce_config[ce_id];
	if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT)
		ath11k_ahb_setbit32(ab, ce_id, ie1_reg_addr);

	if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) {
		ath11k_ahb_setbit32(ab, ce_id, ie2_reg_addr);
		ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
				    ie3_reg_addr);
	}
}

static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
{
	const struct ce_pipe_config *ce_config;
	u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr;

	if  (ab->hw_rev == ATH11K_HW_IPQ5018) {
		ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS;
		ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS;
		ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS;
	} else {
		ie1_reg_addr = CE_HOST_IE_ADDRESS;
		ie2_reg_addr = CE_HOST_IE_2_ADDRESS;
		ie3_reg_addr = CE_HOST_IE_3_ADDRESS;
	}

	ce_config = &ab->hw_params.target_ce_config[ce_id];
	if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT)
		ath11k_ahb_clearbit32(ab, ce_id, ie1_reg_addr);

	if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) {
		ath11k_ahb_clearbit32(ab, ce_id, ie2_reg_addr);
		ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
				      ie3_reg_addr);
	}
}

static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab)
{
	int i;
	int irq_idx;

	for (i = 0; i < ab->hw_params.ce_count; i++) {
		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
			continue;

		irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
		synchronize_irq(ab->irq_num[irq_idx]);
	}
}

static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab)
{
	int i, j;
	int irq_idx;

	for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];

		for (j = 0; j < irq_grp->num_irq; j++) {
			irq_idx = irq_grp->irqs[j];
			synchronize_irq(ab->irq_num[irq_idx]);
		}
	}
}

static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab)
{
	int i;

	for (i = 0; i < ab->hw_params.ce_count; i++) {
		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
			continue;
		ath11k_ahb_ce_irq_enable(ab, i);
	}
}

static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab)
{
	int i;

	for (i = 0; i < ab->hw_params.ce_count; i++) {
		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
			continue;
		ath11k_ahb_ce_irq_disable(ab, i);
	}
}

static int ath11k_ahb_start(struct ath11k_base *ab)
{
	ath11k_ahb_ce_irqs_enable(ab);
	ath11k_ce_rx_post_buf(ab);

	return 0;
}

static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
{
	int i;

	for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];

		napi_enable(&irq_grp->napi);
		ath11k_ahb_ext_grp_enable(irq_grp);
	}
}

static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
{
	__ath11k_ahb_ext_irq_disable(ab);
	ath11k_ahb_sync_ext_irqs(ab);
}

static void ath11k_ahb_stop(struct ath11k_base *ab)
{
	if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
		ath11k_ahb_ce_irqs_disable(ab);
	ath11k_ahb_sync_ce_irqs(ab);
	ath11k_ahb_kill_tasklets(ab);
	del_timer_sync(&ab->rx_replenish_retry);
	ath11k_ce_cleanup_pipes(ab);
}

static int ath11k_ahb_power_up(struct ath11k_base *ab)
{
	struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
	int ret;

	ret = rproc_boot(ab_ahb->tgt_rproc);
	if (ret)
		ath11k_err(ab, "failed to boot the remote processor Q6\n");

	return ret;
}

static void ath11k_ahb_power_down(struct ath11k_base *ab)
{
	struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);

	rproc_shutdown(ab_ahb->tgt_rproc);
}

static int ath11k_get_userpd_id(struct device *dev)
{
	int ret;
	int userpd_id = 0;
	const char *subsys_name;

	ret = of_property_read_string(dev->of_node,
				      "qcom,userpd-subsys-name",
				      &subsys_name);
	if (ret) {
		dev_err(dev, "Not multipd architecture");
		return 0;
	}

	if (strcmp(subsys_name, "q6v5_wcss_userpd2") == 0) {
		userpd_id = QCN6122_USERPD_0;
	} else if (strcmp(subsys_name, "q6v5_wcss_userpd3") == 0) {
		userpd_id = QCN6122_USERPD_1;
	}

	return userpd_id;
}

static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab)
{
	struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;

	cfg->tgt_ce_len = ab->hw_params.target_ce_count;
	cfg->tgt_ce = ab->hw_params.target_ce_config;
	cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
	cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
	ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
	ab->qmi.service_ins_id += ab->userpd_id;
}

static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab)
{
	int i, j;

	for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];

		for (j = 0; j < irq_grp->num_irq; j++)
			free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);

		netif_napi_del(&irq_grp->napi);
	}
}

static void ath11k_ahb_free_irq(struct ath11k_base *ab)
{
	int irq_idx;
	int i;

	for (i = 0; i < ab->hw_params.ce_count; i++) {
		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
			continue;
		irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
		free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
	}

	ath11k_ahb_free_ext_irq(ab);
}

static void ath11k_ahb_ce_tasklet(struct tasklet_struct *t)
{
	struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);

	if (ce_pipe->ab->ce_latency_stats_enable)
		ce_pipe->tasklet_ts.exec_entry_ts = ktime_get_boottime();

	ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);

	if (ce_pipe->ab->ce_latency_stats_enable) {
		ce_pipe->tasklet_ts.exec_complete_ts = ktime_get_boottime();
		ce_update_tasklet_time_duration_stats(ce_pipe);
	}

	ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
}

static irqreturn_t ath11k_ahb_ce_interrupt_handler(int irq, void *arg)
{
	struct ath11k_ce_pipe *ce_pipe = arg;

	/* last interrupt received for this CE */
	ce_pipe->timestamp = jiffies;

	ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);

	tasklet_schedule(&ce_pipe->intr_tq);

	if (ce_pipe->ab->ce_latency_stats_enable)
		ce_pipe->tasklet_ts.sched_entry_ts = ktime_get_boottime();

	return IRQ_HANDLED;
}

static int ath11k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget)
{
	struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
						struct ath11k_ext_irq_grp,
						napi);
	struct ath11k_base *ab = irq_grp->ab;
	int work_done;

	work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
	if (work_done < budget) {
		napi_complete_done(napi, work_done);
		ath11k_ahb_ext_grp_enable(irq_grp);
	}

	if (work_done > budget)
		work_done = budget;

	return work_done;
}

static irqreturn_t ath11k_ahb_ext_interrupt_handler(int irq, void *arg)
{
	struct ath11k_ext_irq_grp *irq_grp = arg;

	/* last interrupt received for this group */
	irq_grp->timestamp = jiffies;

	ath11k_ahb_ext_grp_disable(irq_grp);

	napi_schedule(&irq_grp->napi);

	return IRQ_HANDLED;
}

static int ath11k_ahb_ext_irq_config(struct ath11k_base *ab)
{
	struct ath11k_hw_params *hw = &ab->hw_params;
	int i, j;
	int irq;
	int ret;
	bool nss_offload;

	/* TCL Completion, REO Dest, ERR, Exception and h2rxdma rings are offloaded
	 * to nss when its enabled, hence don't enable these interrupts
	 */
	nss_offload = ath11k_nss_offload_enabled(ab);

	for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
		u32 num_irq = 0;

		irq_grp->ab = ab;
		irq_grp->grp_id = i;
		init_dummy_netdev(&irq_grp->napi_ndev);
		netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
			       ath11k_ahb_ext_grp_napi_poll, NAPI_POLL_WEIGHT);

		for (j = 0; j < ATH11K_EXT_IRQ_NUM_MAX; j++) {
			if (!nss_offload && ab->hw_params.ring_mask->tx[i] & BIT(j)) {
				irq_grp->irqs[num_irq++] =
					wbm2host_tx_completions_ring1 - j;
			}

			if (!nss_offload && ab->hw_params.ring_mask->rx[i] & BIT(j)) {
				irq_grp->irqs[num_irq++] =
					reo2host_destination_ring1 - j;
			}

			if (!nss_offload && ab->hw_params.ring_mask->rx_err[i] & BIT(j))
				irq_grp->irqs[num_irq++] = reo2host_exception;

			if (!nss_offload && ab->hw_params.ring_mask->rx_wbm_rel[i] & BIT(j))
				irq_grp->irqs[num_irq++] = wbm2host_rx_release;

			if (ab->hw_params.ring_mask->reo_status[i] & BIT(j))
				irq_grp->irqs[num_irq++] = reo2host_status;

			if (j < ab->hw_params.max_radios) {
				if (ab->hw_params.ring_mask->rxdma2host[i] & BIT(j)) {
					irq_grp->irqs[num_irq++] =
						rxdma2host_destination_ring_mac1 -
						ath11k_hw_get_mac_from_pdev_id(hw, j);
				}

				if (!nss_offload && ab->hw_params.ring_mask->host2rxdma[i] & BIT(j)) {
					irq_grp->irqs[num_irq++] =
						host2rxdma_host_buf_ring_mac1 -
						ath11k_hw_get_mac_from_pdev_id(hw, j);
				}

				if (ab->hw_params.ring_mask->rx_mon_status[i] & BIT(j)) {
					irq_grp->irqs[num_irq++] =
						ppdu_end_interrupts_mac1 -
						ath11k_hw_get_mac_from_pdev_id(hw, j);
					irq_grp->irqs[num_irq++] =
						rxdma2host_monitor_status_ring_mac1 -
						ath11k_hw_get_mac_from_pdev_id(hw, j);
				}
			}
		}
		irq_grp->num_irq = num_irq;

		for (j = 0; j < irq_grp->num_irq; j++) {
			int irq_idx = irq_grp->irqs[j];

			irq = platform_get_irq_byname(ab->pdev,
						      irq_name[irq_idx]);
			ab->irq_num[irq_idx] = irq;
			irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_DISABLE_UNLAZY);
			ret = request_irq(irq, ath11k_ahb_ext_interrupt_handler,
					  IRQF_TRIGGER_RISING,
					  irq_name[irq_idx], irq_grp);
			if (ret) {
				ath11k_err(ab, "failed request_irq for %d\n",
					   irq);
			}
		}
	}

	return 0;
}

static void ath11k_internal_pci_free_irq(struct ath11k_base *ab)
{
	struct platform_device *pdev = ab->pdev;

	ath11k_pci_free_irq(ab);
	platform_msi_domain_free_irqs(&pdev->dev);
}

static void ath11k_gicv2m_msg_handler(struct msi_desc *desc, struct msi_msg *msg)
{
	desc->msg.address_lo = msg->address_lo;
	desc->msg.address_hi = msg->address_hi;
	desc->msg.data = msg->data;
}

static int ath11k_config_irq_internal_pci(struct ath11k_base *ab)
{
	int ret;
	struct platform_device *pdev = ab->pdev;
	struct msi_desc *msi_desc;
	bool ce_done = false;
	int i = 0;

	if (ab->userpd_id != QCN6122_USERPD_0 &&
	    ab->userpd_id != QCN6122_USERPD_1) {
		ath11k_warn(ab, "ath11k userpd invalid %d\n", ab->userpd_id);
		return -ENODEV;
	}

	ab->ipci.msi_cfg = &ath11k_msi_config[ATH11K_MSI_CONFIG_QCN6122];

	ret = platform_msi_domain_alloc_irqs(&pdev->dev, ab->ipci.msi_cfg->total_vectors,
					     ath11k_gicv2m_msg_handler);
	if (ret) {
		ath11k_warn(ab, "failed to alloc irqs %d ab %pM\n", ret, ab);
		return ret;
	}

	for_each_msi_entry(msi_desc, &pdev->dev) {
		if (!ce_done && i == ab->hw_params.ce_count) {
			i = 0;
			ce_done = true;
		}

		if (!ce_done && i < ab->hw_params.ce_count) {
			if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
				i++;

			ret = ath11k_pci_config_gic_msi_irq(ab, pdev, msi_desc, i);
			if (ret) {
				ath11k_warn(ab, "failed to request irq %d\n", ret);
				return ret;
			}
		} else {
			ret = ath11k_pci_ext_config_gic_msi_irq(ab, pdev, msi_desc, i);
			if (ret) {
				ath11k_warn(ab, "failed to config ext msi irq %d\n", ret);
				return ret;
			}
		}

		i++;
		ab->ipci.address_lo = msi_desc->msg.address_lo;
		ab->ipci.address_hi = msi_desc->msg.address_hi;

		if (i == 0 && !ce_done)
			ab->ipci.gic_ep_base_data = msi_desc->msg.data;

	}

	for_each_msi_entry(msi_desc, &pdev->dev) {
		u32 user_base_data = 0, base_vector = 0;
		int vector, num_vectors = 0;

		ret = ath11k_pci_get_user_msi_assignment(ab, ab->ipci.msi_cfg, 0,
				"DP", &num_vectors, &user_base_data,
				&base_vector);
		if (ret < 0)
			return ret;

		vector = (i % num_vectors) + base_vector;

		if (i >= ATH11K_EXT_IRQ_GRP_NUM_MAX)
			break;

		if (ab->ipci.dp_irq_num[vector] != msi_desc->irq)
			continue;

		ret = ath11k_pci_ext_config_gic_msi_irq(ab, pdev, msi_desc, i);
		if (ret) {
			ath11k_warn(ab, "failed to config ext msi irq %d\n", ret);
			return ret;
		}

		i++;
	}

	ab->ipci.gic_enabled = 1;
	wake_up(&ab->ipci.gic_msi_waitq);

	return ret;
}

static int ath11k_ahb_config_irq(struct ath11k_base *ab)
{
	int irq, irq_idx, i;
	int ret = 0;

	/* Configure CE irqs */
	for (i = 0; i < ab->hw_params.ce_count; i++) {
		struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];

		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
			continue;

		irq_idx = ATH11K_IRQ_CE0_OFFSET + i;

		tasklet_setup(&ce_pipe->intr_tq, ath11k_ahb_ce_tasklet);
		irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]);
		ret = request_irq(irq, ath11k_ahb_ce_interrupt_handler,
				  IRQF_TRIGGER_RISING, irq_name[irq_idx],
				  ce_pipe);
		if (ret)
			return ret;

		ab->irq_num[irq_idx] = irq;
	}

	/* Configure external interrupts */
	ret = ath11k_ahb_ext_irq_config(ab);

	return ret;
}

static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
					  u8 *ul_pipe, u8 *dl_pipe)
{
	const struct service_to_pipe *entry;
	bool ul_set = false, dl_set = false;
	int i;

	for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
		entry = &ab->hw_params.svc_to_ce_map[i];

		if (__le32_to_cpu(entry->service_id) != service_id)
			continue;

		switch (__le32_to_cpu(entry->pipedir)) {
		case PIPEDIR_NONE:
			break;
		case PIPEDIR_IN:
			WARN_ON(dl_set);
			*dl_pipe = __le32_to_cpu(entry->pipenum);
			dl_set = true;
			break;
		case PIPEDIR_OUT:
			WARN_ON(ul_set);
			*ul_pipe = __le32_to_cpu(entry->pipenum);
			ul_set = true;
			break;
		case PIPEDIR_INOUT:
			WARN_ON(dl_set);
			WARN_ON(ul_set);
			*dl_pipe = __le32_to_cpu(entry->pipenum);
			*ul_pipe = __le32_to_cpu(entry->pipenum);
			dl_set = true;
			ul_set = true;
			break;
		}
	}

	if (WARN_ON(!ul_set || !dl_set))
		return -ENOENT;

	return 0;
}

static const struct ath11k_hif_ops ath11k_ahb_hif_ops = {
	.start = ath11k_ahb_start,
	.stop = ath11k_ahb_stop,
	.read32 = ath11k_ahb_read32,
	.write32 = ath11k_ahb_write32,
	.irq_enable = ath11k_ahb_ext_irq_enable,
	.irq_disable = ath11k_ahb_ext_irq_disable,
	.map_service_to_pipe = ath11k_ahb_map_service_to_pipe,
	.power_down = ath11k_ahb_power_down,
	.power_up = ath11k_ahb_power_up,
	.free_irq = ath11k_ahb_free_irq,
	.config_irq = ath11k_ahb_config_irq,
};

static const struct ath11k_hif_ops ath11k_internal_pci_hif_ops = {
	.start = ath11k_ipci_start,
	.stop = ath11k_pci_stop,
	.read32 = ath11k_ipci_read32,
	.write32 = ath11k_ipci_write32,
	.power_down = ath11k_ahb_power_down,
	.power_up = ath11k_ahb_power_up,
	.irq_enable = ath11k_pci_ext_irq_enable,
	.irq_disable = ath11k_pci_ext_irq_disable,
	.get_msi_address =  ath11k_pci_get_qgic_msi_address,
	.get_user_msi_vector = ath11k_get_user_qgic_msi_assignment,
	.map_service_to_pipe = ath11k_pci_map_service_to_pipe,
	.get_window_offset = ath11k_pci_get_window_offset,
	.get_ce_msi_idx = ath11k_pci_get_ce_msi_idx,
	/* TODO: Additional hif ops has been brought in to remove
	 * platform checks. QCN6122 is a hybrid bus which is a
	 * combination of pic and ahb. This addition ops needs
	 * to be removed in future
	 */
	.config_static_window = ath11k_pci_config_static_window,
	.free_irq = ath11k_internal_pci_free_irq,
	.config_irq = ath11k_config_irq_internal_pci,
};

static int ath11k_core_get_rproc(struct ath11k_base *ab)
{
	struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
	struct device *dev = ab->dev;
	struct rproc *prproc;
	phandle rproc_phandle;

	if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) {
		ath11k_err(ab, "failed to get q6_rproc handle\n");
		return -ENOENT;
	}

	prproc = rproc_get_by_phandle(rproc_phandle);
	if (!prproc) {
		ath11k_err(ab, "failed to get rproc\n");
		return -EINVAL;
	}

	ab_ahb->tgt_rproc = prproc;

	return 0;
}

static bool ath11k_skip_target_probe(int userpd_id, const struct of_device_id *of_id)
{
	int hw_rev = (enum ath11k_hw_rev)of_id->data;

	if (ath11k_skip_radio & SKIP_QCN6122_0) {
		if (hw_rev == ATH11K_HW_QCN6122 &&
		    userpd_id == QCN6122_USERPD_0)
			return true;
	} else if (ath11k_skip_radio & SKIP_QCN6122_1) {
		if (hw_rev == ATH11K_HW_QCN6122 &&
		    userpd_id == QCN6122_USERPD_1)
			return true;
	}
		return false;
}

static int ath11k_ahb_probe(struct platform_device *pdev)
{
	struct ath11k_base *ab;
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct resource *mem_res;
	void __iomem *mem;
	int ret = 0;
	int userpd_id;
	u32 hw_mode_id;
	unsigned long left;

	of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev);
	if (!of_id) {
		dev_err(&pdev->dev, "failed to find matching device tree id\n");
		return -EINVAL;
	}

	userpd_id = ath11k_get_userpd_id(dev);
	if (ath11k_skip_target_probe(userpd_id, of_id))
		goto end;

	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (ret) {
		dev_err(&pdev->dev, "failed to set 32-bit consistent dma\n");
		return ret;
	}

	ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb),
			       ATH11K_BUS_AHB,
			       &ath11k_ahb_bus_params);
	if (!ab) {
		dev_err(&pdev->dev, "failed to allocate ath11k base\n");
		return -ENOMEM;
	}

	ab->hif.ops = &ath11k_ahb_hif_ops;
	ab->pdev = pdev;
	ab->hw_rev = (enum ath11k_hw_rev)of_id->data;
	ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
	ab->enable_cold_boot_cal = ath11k_cold_boot_cal;
	ab->userpd_id = userpd_id;

	mutex_lock(&dev_init_lock);
	left = wait_event_timeout(ath11k_radio_prb_wq, dev_init_progress == false,
				  ATH11K_AHB_PROBE_SEQ_TIMEOUT);
	dev_init_progress = true;
	if (!left)
		ath11k_dbg(ab, ATH11K_DBG_AHB, "dev init is concurrently processing"
			   " this may cause random phy#\n");
	mutex_unlock(&dev_init_lock);

	platform_set_drvdata(pdev, ab);

	if (ab->hw_rev != ATH11K_HW_QCN6122) {
		mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem_res) {
			dev_err(&pdev->dev, "failed to get IO memory resource\n");
			return -ENXIO;
		}

		mem = devm_ioremap_resource(&pdev->dev, mem_res);
		if (IS_ERR(mem)) {
			dev_err(&pdev->dev, "ioremap error\n");
			return PTR_ERR(mem);
		}

		ab->mem = mem;
		ab->mem_pa = mem_res->start;
		ab->mem_len = resource_size(mem_res);
		ab->mem_ce = ab->mem;
		if (ab->hw_rev == ATH11K_HW_IPQ5018) {
			/* ce register space is moved out of wcss unlike ipq8074 or ipq6018
			 * and the space is not contiguous, hence remapping the CE registers
			 * to a new space for accessing them.
			 */
			ab->mem_ce = ioremap_nocache(HAL_IPQ5018_CE_WFSS_REG_BASE,
						     HAL_IPQ5018_CE_SIZE);
			if (IS_ERR(ab->mem_ce)) {
				dev_err(&pdev->dev, "ce ioremap error\n");
				return -ENOMEM;
			}
			ab->ce_remap = true;
			ab->ce_remap_base_addr = HAL_IPQ5018_CE_WFSS_REG_BASE;
		}
	} else {
		ab->hif.ops = &ath11k_internal_pci_hif_ops;
		ab->bus_params = ath11k_internal_pci_bus_params;
	}

	ret = ath11k_core_pre_init(ab);
	if (ret)
		goto err_core_free;

	ret = ath11k_hal_srng_init(ab);
	if (ret)
		goto err_core_free;

	ret = ath11k_ce_alloc_pipes(ab);
	if (ret) {
		ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
		goto err_hal_srng_deinit;
	}

	ath11k_ahb_init_qmi_ce_config(ab);

	ret = ath11k_core_get_rproc(ab);
	if (ret) {
		ath11k_err(ab, "failed to get rproc: %d\n", ret);
		goto err_ce_free;
	}

	ret = ath11k_core_init(ab);
	if (ret) {
		ath11k_err(ab, "failed to init core: %d\n", ret);
		goto err_ce_free;
	}

	ret = ath11k_hif_config_irq(ab);
	if (ret) {
		ath11k_err(ab, "failed to configure irq: %d\n", ret);
		goto err_ce_free;
	}

	/* TODO
	 * below 4 lines can be removed once fw changes available
	 */
	of_property_read_u32(dev->of_node, "wlan-hw-mode",
			     &hw_mode_id);

	ath11k_qmi_fwreset_from_cold_boot(ab);

	return 0;

err_ce_free:
	ath11k_ce_free_pipes(ab);

err_hal_srng_deinit:
	ath11k_hal_srng_deinit(ab);

err_core_free:
	ath11k_core_free(ab);
end:
	platform_set_drvdata(pdev, NULL);
	return ret;
}

static int ath11k_ahb_remove(struct platform_device *pdev)
{
	struct ath11k_base *ab = platform_get_drvdata(pdev);
	unsigned long left;

	if (!ab)
		return 0;

	if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
		ath11k_ahb_power_down(ab);
		ath11k_debugfs_soc_destroy(ab);
		ath11k_qmi_deinit_service(ab);
		goto qmi_fail;
	}

	reinit_completion(&ab->driver_recovery);

	if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) {
		left = wait_for_completion_timeout(&ab->driver_recovery,
						   ATH11K_AHB_RECOVERY_TIMEOUT);
		if (!left)
			ath11k_warn(ab, "failed to receive recovery response completion\n");
	}

	set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
	cancel_work_sync(&ab->restart_work);
	cancel_work_sync(&ab->wmi_ast_work);

	ath11k_core_deinit(ab);
qmi_fail:
	ath11k_hif_free_irq(ab);
	ath11k_hal_srng_deinit(ab);
	ath11k_ce_free_pipes(ab);

	if (ab->ce_remap)
		iounmap(ab->mem_ce);

	ath11k_core_free(ab);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver ath11k_ahb_driver = {
	.driver         = {
		.name   = "ath11k",
		.of_match_table = ath11k_ahb_of_match,
	},
	.probe  = ath11k_ahb_probe,
	.remove = ath11k_ahb_remove,
};

static int ath11k_ahb_init(void)
{
	return platform_driver_register(&ath11k_ahb_driver);
}
module_init(ath11k_ahb_init);

static void ath11k_ahb_exit(void)
{
	platform_driver_unregister(&ath11k_ahb_driver);
}
module_exit(ath11k_ahb_exit);

MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices");
MODULE_LICENSE("Dual BSD/GPL");