// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/clock/sm1-audio-clk.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/meson_ir.h>
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
#include "meson-ir-map.dtsi"
#include "gpu-bifrost.dtsi"

/ {
	compatible = "amlogic, sm1";

	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	ppmgr {
		compatible = "amlogic, ppmgr";
		dev_name = "ppmgr";
		status = "okay";
	};

	ionvideo {
		compatible = "amlogic, ionvideo";
		dev_name = "ionvideo";
		status = "okay";
	};

	amlvideo {
		compatible = "amlogic, amlvideo";
		dev_name = "amlvideo";
		status = "okay";
	};

	videosync {
		compatible = "amlogic, videosync";
		dev_name = "videosync";
		status = "okay";
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&l2>;
			clocks = <&clkc CLKID_CPU_CLK>,
			       <&clkc CLKID_CPU_FCLK>,
			       <&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			operating-points-v2 = <&cpu_opp_table0>;
			cpu-supply = <&vddcpu0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			capacity-dmips-mhz = <592>;
			dynamic-power-coefficient = <125>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x1>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&l2>;
			clocks = <&clkc CLKID_CPU_CLK>,
			       <&clkc CLKID_CPU_FCLK>,
			       <&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			operating-points-v2 = <&cpu_opp_table0>;
			cpu-supply = <&vddcpu0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			capacity-dmips-mhz = <592>;
			dynamic-power-coefficient = <125>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x2>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&l2>;
			clocks = <&clkc CLKID_CPU_CLK>,
			       <&clkc CLKID_CPU_FCLK>,
			       <&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			operating-points-v2 = <&cpu_opp_table0>;
			cpu-supply = <&vddcpu0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			capacity-dmips-mhz = <592>;
			dynamic-power-coefficient = <125>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x3>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&l2>;
			clocks = <&clkc CLKID_CPU_CLK>,
			       <&clkc CLKID_CPU_FCLK>,
			       <&clkc CLKID_SYS_PLL>;
			clock-names = "core_clk",
				"low_freq_clk_parent",
				"high_freq_clk_parent";
			operating-points-v2 = <&cpu_opp_table0>;
			cpu-supply = <&vddcpu0>;
			voltage-tolerance = <0>;
			clock-latency = <50000>;
			capacity-dmips-mhz = <592>;
			dynamic-power-coefficient = <125>;
			#cooling-cells = <2>;
		};
		idle-states {
			entry-method = "arm,psci-0.2";
			CPU_SLEEP_0: cpu-sleep-0 {
					compatible = "arm,idle-state";
					arm,psci-suspend-param = <0x0010000>;
					local-timer-stop;
					entry-latency-us = <2000>;
					exit-latency-us = <2000>;
					min-residency-us = <6000>;
			};
		};
		l2: l2-cache0 {
			compatible = "cache";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	arm_pmu {
		compatible = "arm,cortex-a15-pmu";
		/* clusterb-enabled; */
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0xff634680 0x4>;
		cpumasks = <0xf>;
		/* default 10ms */
		relax-timer-ns = <10000000>;
		/* default 10000us */
		max-wait-cnt = <10000>;
	};

	meson_suspend:pm {
		compatible = "amlogic, pm";
		status = "okay";
		device_name = "aml_pm";
		reg = <0xff8000a8 0x4>,
			<0xff80023c 0x4>;
	};

	aml_reboot{
		compatible = "aml, reboot";
		sys_reset = <0x84000009>;
		sys_poweroff = <0x84000008>;
	};

	rtc{
		compatible = "amlogic, aml_vrtc";
		alarm_reg_addr = <0xff8000a8>;
		timer_e_addr = <0xffd0f188>;
		init_date = "2019/01/01";
		status = "okay";
	};

	power_ctrl: power_ctrl@ff8000e8 {
		compatible = "amlogic, sm1-powerctrl";
		reg = <0xff8000e8 0x10>,
		      <0xff63c100 0x10>;
	};

	ram-dump {
		compatible = "amlogic, ram_dump";
		status = "okay";
		reg = <0xFF6345E0 4>;
		reg-names = "PREG_STICKY_REG8";
		store_device = "data";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		periphs: periphs@ff634000 {
			compatible = "simple-bus";
			reg = <0xff634000 0x2000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xff634000 0x2000>;

			pinctrl_periphs: pinctrl@6c0 {
				compatible =
					"amlogic,meson-g12a-periphs-pinctrl";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio: bank@6c0 {
					reg = <0x006c0 0x40>,
					      <0x004e8 0x18>,
					      <0x00520 0x18>,
					      <0x00440 0x4c>,
					      <0x00740 0x1c>;
					reg-names = "mux",
						"pull",
						"pull-enable",
						"gpio",
						"drive-strength";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_periphs 0 0 86>;
				};
			};
		};

		emmc_pwrseq: emmc-pwrseq {
			compatible = "mmc-pwrseq-emmc";
			reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
		};

		hiubus: bus@ff63c000 {
			compatible = "simple-bus";
			reg = <0xff63c000 0x1c00>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xff63c000 0x1c00>;

			sysctrl: syscon@0 {
				compatible = "amlogic,meson-g12a-hhi-sysctrl",
					   "syscon", "simple-mfd";
				reg = <0x0 0x400>;
				clkc: clock-controller@0 {
					compatible = "amlogic,sm1-clkc";
					#clock-cells = <1>;
					clocks = <&xtal>;
					clock-names = "core";
					status = "okay";
				};

				clkc_b: clock-controller@1 {
					compatible = "amlogic,sm1-clkc-1";
					#clock-cells = <1>;
					clocks = <&xtal>,
					       <&clkc CLKID_FCLK_DIV2>;
					clock-names = "core", "clkin0";
					status = "okay";
				};
			};
		};

		aml_dma: aml_dma@ff63e000 {
			compatible = "amlogic,aml_txlx_dma";
			reg = <0xff63e000 0x48>;
			interrupts = <0 180 1>;

			aml_aes {
				compatible = "amlogic,aes_g12a_dma";
				dev_name = "aml_aes_dma";
				status = "okay";
			};

			aml_sha {
				compatible = "amlogic,sha_dma";
				dev_name = "aml_sha_dma";
				status = "okay";
			};

			aml_tdes {
				compatible = "amlogic,tdes_dma";
				dev_name = "aml_tdes_dma";
				status = "okay";
			};
		};

		aobus: bus@ff800000 {
			compatible = "simple-bus";
			reg = <0xff800000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xff800000 0x100000>;

			cpu_version {
				reg=<0x220 0x4>;
			};

			sysctrl_AO: sys-ctrl@0 {
				compatible = "amlogic,meson-g12a-ao-sysctrl",
					     "syscon", "simple-mfd";
				reg =  <0x0 0x100>;

				clkc_AO: clock-controller {
					compatible = "amlogic,sm1-aoclkc";
					#clock-cells = <1>;
					#reset-cells = <1>;
					/* two passby clocks will realize
					 * in g12a ao driver
					 */
					clocks = <&xtal>,
						<&clkc CLKID_CLK81>;
					clocks-names = "clkin0", "clkin1";
				};
			};

			pwm_AO_cd: pwm@2000 {
				compatible = "amlogic,meson-g12a-ao-pwm";
				reg = <0x2000  0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
					 <&xtal>,
					 <&xtal>,
					 <&xtal>;
				clock-names = "clkin0",
					      "clkin1",
					      "clkin2",
					      "clkin3";
				status = "disabled";
			};

			sec_AO: ao-secure@140 {
				compatible = "amlogic,meson-gx-ao-secure",
					     "syscon";
				reg = <0x140 0x140>;
				amlogic,has-chip-id;
			};

			irblaster: meson-irblaster@14c {
				compatible = "amlogic, meson_irblaster";
				reg = <0x14c 0x10>,
					<0x40 0x4>;
				#irblaster-cells = <2>;
				pinctrl-names = "default";
				pinctrl-0 = <&irblaster_pins>;
				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			uart_AO: serial@3000 {
				compatible = "amlogic,meson-uart";
				reg = <0x3000 0x18>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&xtal>;
				clock-names = "clk_uart";
				xtal_tick_en = <0>;
				fifosize = < 64 >;
				pinctrl-names = "default";
				/*pinctrl-0 = <&ao_uart_pins>;*/
			};

			uart_AO_B: serial@4000 {
				compatible = "amlogic,meson-uart";
				reg = <0x4000 0x18>;
				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&xtal>;
				clock-names = "clk_uart";
				fifosize = < 64 >;
				pinctrl-names = "default";
				pinctrl-0 = <&ao_b_uart_pins1>;
			};

			i2c_AO: i2c@5000 {
				compatible = "amlogic,meson-i2c";
				status = "disabled";
				reg = <0x05000 0x20>;
				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
			};

			pwm_AO_ab: pwm@7000 {
				compatible = "amlogic,meson-g12a-ao-pwm";
				reg = <0x7000  0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
					 <&xtal>,
					 <&xtal>,
					 <&xtal>;
				clock-names = "clkin0",
					      "clkin1",
					      "clkin2",
					      "clkin3";
				status = "disabled";
			};

			pinctrl_aobus: pinctrl@14 {
				compatible = "amlogic,meson-g12a-aobus-pinctrl";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio_ao: bank@14 {
					reg = <0x00014 0x8>,
					      <0x00024 0x14>,
					      <0x0001c 0x8>;
					reg-names = "mux",
						"gpio",
						"drive-strength";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_aobus 0 0 16>;
				};
			};

			ir: ir@8040 {
				compatible = "amlogic, meson-ir";
				reg = <0x8040 0xA4>,
				      <0x8000 0x20>;
				status = "okay";
				protocol = <REMOTE_TYPE_NEC>;
				interrupts = <0 196 IRQ_TYPE_EDGE_RISING>;
				pinctrl-names = "default";
				pinctrl-0 = <&remote_pins>;
				map = <&custom_maps>;
				max_frame_time = <200>;
			};

			jtag {
				compatible = "amlogic, jtag";
				status = "okay";
				/* disable/ap,jtag_a/ap,jtag_b */
				select = "disable";
				pinctrl-names="jtag_a_pins", "jtag_b_pins";
				pinctrl-0=<&jtag_a_pins>;
				pinctrl-1=<&jtag_b_pins>;
			};

			saradc: adc@9000 {
				compatible = "amlogic,meson-g12a-saradc",
					"amlogic,meson-saradc";
				reg = <0x9000 0x48>;
				#io-channel-cells = <1>;
				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>,
					<&clkc_AO CLKID_AO_SAR_ADC>,
					<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
					<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
				clock-names = "clkin", "core",
					"adc_clk", "adc_sel";
				status = "disabled";
			};
		};

		gic: interrupt-controller@ffc01000 {
			compatible = "arm,gic-400";
			reg = <0xffc01000 0x1000>,
			      <0xffc02000 0x2000>,
			      <0xffc04000 0x2000>,
			      <0xffc06000 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};

		cbus: bus@ffd00000 {
			compatible = "simple-bus";
			reg = <0xffd00000 0x25000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xffd00000 0x25000>;

			reset: reset-controller@1004 {
				compatible = "amlogic,meson-g12a-reset";
				reg = <0x01004 0x9c>;
				#reset-cells = <1>;
			};

			gpio_intc: interrupt-controller@f080 {
				compatible = "amlogic,meson-gpio-intc",
						"amlogic,meson-sm1-gpio-intc";
				reg = <0xf080 0x10>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts =
						<64 65 66 67 68 69 70 71>;
				status = "okay";
			};

			spicc0: spi@13000 {
				compatible = "amlogic,meson-g12-spicc";
				reg = <0x13000 0x44>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "core", "async";
				clocks = <&clkc CLKID_SPICC0>,
					 <&clkc CLKID_SPICC0_GATE>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spifc: spi@14000 {
				compatible = "amlogic,meson-gxbb-spifc";
				reg = <0x14000 0x80>;
				clock-names = "clk81";
				clocks = <&clkc CLKID_CLK81>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spicc1: spi@15000 {
				compatible = "amlogic,meson-g12-spicc";
				reg = <0x15000 0x44>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "core", "async";
				clocks = <&clkc CLKID_SPICC1>,
					 <&clkc CLKID_SPICC1_GATE>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			meson_clk_msr@18000 {
				compatible = "amlogic,sm1-clk-measure";
			       reg = <0x18000 0x10>;
			};

			pwm_ef: pwm@19000 {
				compatible = "amlogic,meson-g12a-ee-pwm";
				reg = <0x19000  0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
					 <&xtal>,
					 <&xtal>,
					 <&xtal>;
				clock-names = "clkin0",
					      "clkin1",
					      "clkin2",
					      "clkin3";
				status = "disabled";
			};

			pwm_cd: pwm@1a000 {
				compatible = "amlogic,meson-g12a-ee-pwm";
				reg = <0x1a000  0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
					 <&xtal>,
					 <&xtal>,
					 <&xtal>;
				clock-names = "clkin0",
					      "clkin1",
					      "clkin2",
					      "clkin3";
				status = "disabled";
			};

			pwm_ab: pwm@1b000 {
				compatible = "amlogic,meson-g12a-ee-pwm";
				reg = <0x1b000 0x20>;
				#pwm-cells = <3>;
				clocks = <&xtal>,
					 <&xtal>,
					 <&xtal>,
					 <&xtal>;
				clock-names = "clkin0",
					      "clkin1",
					      "clkin2",
					      "clkin3";
				/* default xtal 24m  clkin0-clkin2 and
				 * clkin1-clkin3 should be set the same
				 */
				status = "disabled";
			};

			i2c3: i2c@1c000 {
				compatible = "amlogic,meson-i2c";
				status = "disabled";
				reg = <0x1c000 0x20>;
				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
			};

			i2c2: i2c@1d000 {
				compatible = "amlogic,meson-i2c";
				status = "disabled";
				reg = <0x1d000 0x20>;
				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
			};

			i2c1: i2c@1e000 {
				compatible = "amlogic,meson-i2c";
				status = "disabled";
				reg = <0x1e000 0x20>;
				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
			};

			i2c0: i2c@1f000 {
				compatible = "amlogic,meson-i2c";
				status = "disabled";
				reg = <0x1f000 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&clkc CLKID_I2C>;
			};

			uart_A: serial@24000 {
				compatible = "amlogic,meson-uart";
				reg = <0x24000 0x18>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&xtal
					&clkc CLKID_UART0>;
				clock-names = "clk_uart",
					"clk_gate";
				fifosize = < 128 >;
				pinctrl-names = "default";
				pinctrl-0 = <&a_uart_pins>;
			};

			uart_B: serial@23000 {
				compatible = "amlogic,meson-uart";
				reg = <0x23000 0x18>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&xtal
					&clkc CLKID_UART1>;
				clock-names = "clk_uart",
					"clk_gate";
				fifosize = < 64 >;
				pinctrl-names = "default";
				pinctrl-0 = <&b_uart_pins>;
			};

			uart_C: serial@22000 {
				compatible = "amlogic,meson-uart";
				reg = <0x22000 0x18>;
				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&xtal
					&clkc CLKID_UART1>;
				clock-names = "clk_uart",
					"clk_gate";
				fifosize = < 64 >;
				pinctrl-names = "default";
				pinctrl-0 = <&c_uart_pins>;
			};

			watchdog@0xf0d0 {
				compatible = "amlogic,meson-gxbb-wdt";
				status = "okay";
				/* 0:userspace, 1:kernel */
				amlogic,feed_watchdog_mode = <1>;
				reg = <0xf0d0 0x10>;
				clocks = <&xtal>;
			};
		};

		apb: apb@ffe00000 {
			compatible = "simple-bus";
			reg = <0xffe00000 0x200000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xffe00000 0x200000>;

			sd_emmc_c: mmc@7000 {
				compatible = "amlogic,meson-v3-mmc";
				reg = <0x7000 0x800>;
				interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&clkc CLKID_SD_EMMC_C>,
					<&clkc CLKID_SD_EMMC_C_CLK0_SEL>,
					<&clkc CLKID_SD_EMMC_C_CLK0>,
					<&clkc CLKID_EE_CORE>,
					<&clkc CLKID_FCLK_DIV2>,
					<&clkc CLKID_FCLK_DIV2P5>;
				clock-names = "core", "mux0", "mux1",
						"clkin0", "clkin1", "clkin2";
				hs4_tx_delay = <16>;
				clk_tree_base= <0xfe63425c>;
				pin_mux_reg = <0xff6346c0>;
				mmc_debug_flag;
				fixadj_have_hole;
				//resets = <&reset RESET_SD_EMMC_C>;
			};
			sd_emmc_b: mmc@5000 {
				compatible = "amlogic,meson-v3-mmc";
				reg = <0x5000 0x800>;
				interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
				clocks = <&clkc CLKID_SD_EMMC_B>,
					<&clkc CLKID_SD_EMMC_B_CLK0_SEL>,
					<&clkc CLKID_SD_EMMC_B_CLK0>,
					<&clkc CLKID_EE_CORE>,
					<&clkc CLKID_FCLK_DIV2>;
				clock-names = "core", "mux0", "mux1",
						"clkin0", "clkin1";
				pin_mux_reg = <0xff6346e4>;
				clk_tree_base= <0xfe634264>;
				mmc_debug_flag;
				fixadj_have_hole;
				//resets = <&reset RESET_SD_EMMC_B>;
			};
			sd_emmc_a: sdio@3000 {
				compatible = "amlogic,meson-v3-mmc";
				reg = <0x3000 0x800>;
				interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				clocks = <&clkc CLKID_SD_EMMC_A>,
					<&clkc CLKID_SD_EMMC_A_CLK0_SEL>,
					<&clkc CLKID_SD_EMMC_A_CLK0>,
					<&clkc CLKID_EE_CORE>,
					<&clkc CLKID_FCLK_DIV2>;
				clock-names = "core", "mux0", "mux1",
						"clkin0", "clkin1";
				clk_tree_base= <0xfe634264>;
				pin_mux_reg = <0xff6346cc>;
				mmc_debug_flag;
				fixadj_have_hole;
				//resets = <&reset RESET_SD_EMMC_A>;
			};
		};

		mtd_nand: nfc@ffe07800 {
			compatible = "amlogic,meson-g12a-nfc";
			status = "disabled";
			reg = <0xFFE07800 0x200>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;

			pinctrl-names = "nand_rb_mod","nand_norb_mod",
				"nand_cs_only";
			pinctrl-0 = <&all_nand_pins>;
			pinctrl-1 = <&all_nand_pins>;
			pinctrl-2 = <&nand_cs_pins>;
			clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
			clocks-names = "core";

			/*fip/tpl configurations, must be same
			 * with uboot if bl_mode was set as 1
			 * bl_mode: 0 compact mode; 1 descrete mode
			 * if bl_mode was set as 1, fip configuration will work
			 */
			bl_mode = <1>;
			/*copy count of fip*/
			fip_copies = <4>;
			/*size of each fip copy */
			fip_size = <0x200000>;
			nand_clk_ctrl = <0xFFE07000>;
			/*partions defined in dts */
		};

		/* Audio Related start */
		audiobus: audiobus@0xFF660000 {
			compatible = "amlogic, audio-controller", "simple-bus";
			reg = <0xFF660000 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xFF660000 0x4000>;
			clkaudio: audio_clocks {
				compatible = "amlogic, sm1-audio-clocks";
				#clock-cells = <1>;
				reg = <0x0 0xb0>;
			};
			ddr_manager {
				compatible = "amlogic, sm1-audio-ddr-manager";
				interrupts = <
					GIC_SPI 148 IRQ_TYPE_EDGE_RISING
					GIC_SPI 149 IRQ_TYPE_EDGE_RISING
					GIC_SPI 150 IRQ_TYPE_EDGE_RISING
					GIC_SPI 49 IRQ_TYPE_EDGE_RISING
					GIC_SPI 152 IRQ_TYPE_EDGE_RISING
					GIC_SPI 153 IRQ_TYPE_EDGE_RISING
					GIC_SPI 154 IRQ_TYPE_EDGE_RISING
					GIC_SPI 50 IRQ_TYPE_EDGE_RISING
				>;
				interrupt-names =
					"toddr_a", "toddr_b", "toddr_c",
					"toddr_d",
					"frddr_a", "frddr_b", "frddr_c",
					"frddr_d";
			};
		};/* end of audiobus*/
		/* Audio Related end */
		demux: demux {
			compatible = "amlogic, dmx";
			status = "okay";

			interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING
			GIC_SPI 5 IRQ_TYPE_EDGE_RISING
			GIC_SPI 53 IRQ_TYPE_EDGE_RISING
			GIC_SPI 19 IRQ_TYPE_EDGE_RISING
			GIC_SPI 25 IRQ_TYPE_EDGE_RISING
			GIC_SPI 18 IRQ_TYPE_EDGE_RISING
			GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "demux0_irq",
			"demux1_irq",
			"demux2_irq",
			"dvr0_irq",
			"dvr1_irq",
			"dvrfill0_fill",
			"dvrfill1_flush";
		};

		p_tsensor: p_tsensor@ff634800 {
			compatible = "amlogic, r1p1-tsensor";
			status = "okay";
			reg = <0xff634800 0x50>,
				<0xff800268 0x4>;
			cal_type = <0x1>;
			cal_coeff = <324 424 3159 9411>;
			rtemp = <115000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_TS_CLK>;
			clock-names = "ts_comp";
			#thermal-sensor-cells = <1>;
		};

		d_tsensor: d_tsensor@ff634c00 {
			compatible = "amlogic, r1p1-tsensor";
			status = "okay";
			reg = <0xff634c00 0x50>,
				<0xff800230 0x4>;
			cal_type = <0x1>;
			cal_coeff = <324 424 3159 9411>;
			rtemp = <115000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_TS_CLK>; /* CLKID_TS_COMP>;*/
			clock-names = "ts_comp";
			#thermal-sensor-cells = <1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
	};

	timer_bc {
		compatible = "amlogic,bc-timer";
		reg=   <0xffd0f190 0x8>;
		timer_name = "Meson TimerF";
		clockevent-rating=<300>;
		clockevent-shift=<20>;
		clockevent-features=<0x23>;
		interrupts = <0 60 1>;
		bit_enable=<16>;
		bit_mode=<12>;
		bit_resolution=<0>;
	};

	amhdmitx: amhdmitx{
		compatible = "amlogic, amhdmitx-sm1";
		dev_name = "amhdmitx";
		status = "okay";
		vend-data = <&vend_data>;
		pinctrl-names="default", "hdmitx_i2c";
		pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
		pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>;
		clocks = <&clkc CLKID_VCLK2_ENCI
			&clkc CLKID_VCLK2_VENCI0
			&clkc CLKID_VCLK2_VENCI1
			&clkc CLKID_VAPB_MUX
			&clkc CLKID_VPU_MUX>;
		clock-names = "venci_top_gate",
			"venci_0_gate",
			"venci_1_gate",
			"hdmi_vapb_clk",
			"hdmi_vpu_clk";
		/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
		interrupts = <0 57 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "hdmitx_hpd";
		/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
		 * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
		 * 10:G12A 11:G12B 12:SM1
		 */
		ic_type = <12>;
		#address-cells=<1>;
		#size-cells=<1>;
		ranges;
		cbus_base {
			reg = <0xffd00000 0x100000>;
		};
		vcbus_base {
			reg = <0xff900000 0x40000>;
		};
		hiu_base {
			reg = <0xff63c000 0x2000>;
		};
		hdmitx_sec_base {
			reg = <0xff600000 0x8000>;
		};
		hdmitx_base {
			reg = <0xff608000 0x4000>;
		};
		esm_base {
			reg = <0xffe01000 0x100>;
		};

		vend_data: vend_data{ /* Should modified by Customer */
			vendor_name = "Amlogic"; /* Max Chars: 8 */
			/* standards.ieee.org/develop/regauth/oui/oui.txt */
			vendor_id = <0x000000>;
		};
	};
	galcore {
		compatible = "amlogic, galcore";
		dev_name = "galcore";
		status = "okay";
		interrupts = <0 186 4>;
		interrupt-names = "galcore";
		reg = <0xff100000 0x800
			0xff000000 0x400000
			0xff63c118 0x0
			0xff63c11c 0x0
			0xffd01088 0x0
			0xff63c1c8 0x0
			>;
		reg-names = "NN_REG","NN_SRAM","NN_MEM0",
			"NN_MEM1","NN_RESET","NN_CLK";
		nn_power_version = <3>;
		nn_efuse = <0xff63003c 0x20>;
	};
	aocec: aocec {
		compatible = "amlogic, aocec-sm1";
		dev_name = "aocec";
		status = "okay";
		vendor_name = "Amlogic"; /* Max Chars: 8     */
		/* Refer to the following URL at:
		 * http://standards.ieee.org/develop/regauth/oui/oui.txt
		 */
		vendor_id = <0x000000>;
		product_desc = "SM1"; /* Max Chars: 16    */
		cec_osd_string = "AML_MBOX"; /* Max Chars: 14    */
		cec_version = <5>;/*5:1.4;6:2.0*/
		port_num = <1>;
		output = <1>;
		cec_sel = <1>;/*1:use one ip, 2:use 2 ip*/
		ee_cec;
		arc_port_mask = <0x1>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING
					GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;	/*0:snps 1:ts*/
		interrupt-names = "hdmi_aocecb","hdmi_aocec";
		pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep";
		pinctrl-0=<&cec_a>;
		pinctrl-1=<&cec_b>;
		pinctrl-2=<&cec_b>;
		reg = <0xFF80023c 0x4
		       0xFF800000 0x400
		       0xFF634400 0x26>;
		reg-names = "ao_exit","ao","periphs";
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	secmon {
		compatible = "amlogic,meson-gxbb-sm";
		memory-region = <&secmon_reserved>;
		reserve_mem_size = <0x00300000>;
	};

	amlogic_unifykey: unifykey{
		compatible = "amlogic,unifykey";
		status = "okay";

		key_0{
			key-name = "usid";
			key-device = "normal";
			key-permit = "read","write";
		};
		key_1{
			key-name = "mac";
			key-device = "normal";
			key-permit = "read","write";
		};
		key_2{
			key-name = "hdcp";
			key-device = "secure";
			key-type = "sha1";
			key-permit = "read","write";
		};
		key_3{
			key-name = "secure_boot_set";
			key-device = "efuse";
			key-permit = "write";
		};
		key_4{
			key-name = "mac_bt";
			key-device = "normal";
			key-permit = "read","write";
			key-type  = "mac";
		};
		key_5{
			key-name = "mac_wifi";
			key-device = "normal";
			key-permit = "read","write";
			key-type = "mac";
		};
		key_6{
			key-name = "hdcp2_tx";
			key-device = "normal";
			key-permit = "read","write";
		};
		key_7{
			key-name = "hdcp2_rx";
			key-device = "normal";
			key-permit = "read","write";
		};
		key_8{
			key-name = "widevinekeybox";
			key-device = "secure";
			key-permit = "read","write";
		};
		key_9{
			key-name = "deviceid";
			key-device = "normal";
			key-permit = "read","write";
		};
		key_10{
			key-name = "hdcp22_fw_private";
			key-device = "secure";
			key-permit = "read","write";
		};
		key_11{
			key-name = "PlayReadykeybox25";
			key-device = "secure";
			key-permit = "read","write";
		};
		key_12{
			key-name = "prpubkeybox";// PlayReady
			key-device = "secure";
			key-permit = "read","write";
		};
		key_13{
			key-name = "prprivkeybox";// PlayReady
			key-device = "secure";
			key-permit = "read","write";
		};
		key_14{
			key-name = "attestationkeybox";// attestation key
			key-device = "secure";
			key-permit = "read","write";
		};
		key_15{
			key-name = "region_code";
			key-device = "normal";
			key-permit = "read","write";
		};
	};//End unifykey

	/* Audio Related start */
	/* audio data security */
	audio_data: audio_data {
		compatible = "amlogic, audio_data";
		query_licence_cmd = <0x82000050>;
		status = "disabled";
	};

	/* Sound iomap */
	aml_snd_iomap {
		compatible = "amlogic, snd-iomap";
		status = "okay";
		#address-cells=<1>;
		#size-cells=<1>;
		ranges;
		pdm_bus {
			reg = <0xFF661000 0x400>;
		};
		audiobus_base {
			reg = <0xFF660000 0x1000>;
		};
		audiolocker_base {
			reg = <0xFF661400 0x400>;
		};
		eqdrc_base {
			reg = <0xFF662000 0x1000>;
		};
		reset_base {
			reg = <0xFFD01000 0x1000>;
		};
		vad_base {
			reg = <0xFF661800 0x400>;
		};
		resampleA_base {
			reg = <0xFF661c00 0x104>;
		};
		resampleB_base {
			reg = <0xFF664000 0x104>;
		};
		earcrx_cdmc_base {
			reg = <0xFF663800 0x30>;
		};
		earcrx_dmac_base {
			reg = <0xFF663C00 0x20>;
		};
		earcrx_top_base {
			reg = <0xFF663E00 0x10>;
		};
	};
	/* Audio Related end */

	vddcpu0: pwmao_d-regulator {
			compatible = "pwm-regulator";
			pwms = <&pwm_AO_cd MESON_PWM_1 1250 0>;
			regulator-name = "vddcpu0";
			regulator-min-microvolt = <721000>;
			regulator-max-microvolt = <1022000>;
			regulator-always-on;
			max-duty-cycle = <1250>;
			/* Voltage Duty-Cycle */
		   voltage-table = <1022000 0>,
				   <1011000 3>,
				   <1001000 6>,
				   <991000 10>,
				   <981000 13>,
				   <971000 16>,
				   <961000 20>,
				   <951000 23>,
				   <941000 26>,
				   <931000 30>,
				   <921000 33>,
				   <911000 36>,
				   <901000 40>,
				   <891000 43>,
				   <881000 46>,
				   <871000 50>,
				   <861000 53>,
				   <851000 56>,
				   <841000 60>,
				   <831000 63>,
				   <821000 67>,
				   <811000 70>,
				   <801000 73>,
				   <791000 76>,
				   <781000 80>,
				   <771000 83>,
				   <761000 86>,
				   <751000 90>,
				   <741000 93>,
				   <731000 96>,
				   <721000 100>;
		   status = "okay";
	};

	ddr_bandwidth {
		compatible = "amlogic,ddr-bandwidth-g12a";
		status = "okay";
		reg = <0xff638000 0x100
		       0xff638c00 0x100>;
		sec_base = <0xff639000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "ddr_bandwidth";
	};

	dmc_monitor {
		compatible = "amlogic,dmc_monitor-sm1";
		status = "okay";
		reg_base = <0xff639000>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>;
	};

	usb2_phy_v2: usb2phy@ffe09000 {
		compatible = "amlogic,amlogic-new-usb2-v2";
		status = "disable";
		#phy-cells = <0>;
		reg = <0xffe09000 0x80
			0xffd01008 0x100
			0xff636000 0x2000
			0xff63a000 0x2000>;
		pll-setting-1 = <0x09400414>;
		pll-setting-2 = <0x927E0000>;
		pll-setting-3 = <0xac5f69e5>;
		pll-setting-4 = <0xfe18>;
		pll-setting-5 = <0x8000fff>;
		pll-setting-6 = <0x78000>;
		pll-setting-7 = <0xe0004>;
		pll-setting-8 = <0xe000c>;
		version = <2>;
		pwr-ctl = <1>;
		u2-ctrl-sleep-shift = <17>;
		u2-hhi-mem-pd-shift = <30>;
		u2-hhi-mem-pd-mask = <0x3>;
		u2-ctrl-iso-shift = <17>;
		phy20-reset-level-bit = <16>;
		phy21-reset-level-bit = <17>;
		usb-reset-bit = <2>;
	};

	usb3_phy_v2: usb3phy@ffe09080 {
		compatible = "amlogic,amlogic-new-usb3-v2";
		status = "disable";
		clocks = <&clkc CLKID_PCIE_PLL>;
		clock-names = "pcie_refpll";
		#phy-cells = <0>;
		reg = <0xffe09080 0x20
				0xffd01008 0x100>;
		phy-reg = <0xff646000>;
		phy-reg-size = <0x2000>;
		usb2-phy-reg = <0xffe09000>;
		usb2-phy-reg-size = <0x80>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		pwr-ctl = <1>;
		u3-ctrl-sleep-shift = <18>;
		u3-hhi-mem-pd-shift = <26>;
		u3-hhi-mem-pd-mask = <0xf>;
		u3-ctrl-iso-shift = <18>;
	};

	usb0: usb@ff500000 {
		compatible = "amlogic,meson-g12a-dwc3";
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clocks = <&clkc CLKID_USB>;
		clock-names = "usb_general";

		dwc3: dwc3@ff500000 {
			compatible = "snps,dwc3";
			reg = <0xff500000 0x100000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			maximum-speed = "high-speed";
			snps,dis_u2_susphy_quirk;
			usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
			clocks = <&clkc CLKID_USB>;
			clock-names = "usb_general";
			usb5v-supply = <&vcc_5v>;
			usb3v3-supply = <&vddao_3v3>;
			usb1v8-supply = <&vddio_ao18>;
		};
	};

	dwc2_a: dwc2_a@ff400000 {
		compatible = "amlogic,dwc2";
		status = "disable";
		device_name = "dwc2_a";
		reg = <0xff400000 0x40000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		pl-periph-id = <0>; /** lm name */
		clock-src = "usb0"; /** clock src */
		port-id = <0>;  /** ref to mach/usb.h */
		port-type = <2>;        /** 0: otg, 1: host, 2: slave */
		port-speed = <0>; /** 0: default, high, 1: full */
		port-config = <0>; /** 0: default */
		/*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
		port-dma = <0>;
		port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
		usb-fifo = <728>;
		cpu-type = "v2";
		phy-reg = <0xffe09000>;
		phy-reg-size = <0xa0>;
		/** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
		phy-interface = <0x2>;
		clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
		clock-names = "usb_general",
				"usb1";
	};

	pcie: pcie@fc000000 {
		compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie";
		reg = <0xfc000000 0x400000
			0xff648000 0x2000
			0xfc400000 0x200000
			0xff646000 0x2000
			0xffd01080 0x10>;
		reg-names = "elbi", "cfg", "config", "phy",
				"reset";
		interrupts = <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>;
		#interrupt-cells = <1>;
		bus-range = <0x0 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ranges = <0x81000000 0 0 0xfc600000 0x0 0x100000
			/* downstream I/O */
			0x82000000 0 0xfc700000 0xfc700000 0 0x1900000>;
			/* non-prefetchable memory */
		num-lanes = <1>;
		pcie-num = <1>;

		clocks = <&clkc CLKID_PCIE_PLL
				&clkc CLKID_PCIE_COMB
				&clkc CLKID_PCIE_PHY>;
		clock-names = "pcie_refpll",
				"pcie",
				"pcie_phy";
		/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
		gpio-type = <2>;
		pcie-apb-rst-bit = <15>;
		pcie-phy-rst-bit = <14>;
		pcie-ctrl-a-rst-bit = <12>;
		pwr-ctl = <1>;
		pcie-ctrl-sleep-shift = <18>;
		pcie-hhi-mem-pd-shift = <26>;
		pcie-hhi-mem-pd-mask = <0xf>;
		pcie-ctrl-iso-shift = <18>;
		status = "disabled";
	};

	ethmac: ethernet@ff3f0000 {
		compatible = "amlogic, g12a-eth-dwmac","snps,dwmac";
		reg = <0xff3f0000 0x10000
			0xff634540 0x8
			0xff64c000 0xa0>;
		reg-names = "eth_base", "eth_cfg", "eth_pll";
		interrupts = <0 8 1>;
		interrupt-names = "macirq";
		status = "disable";
		clocks = <&clkc CLKID_ETH>,
			 <&clkc CLKID_FCLK_50M>,
			 <&clkc CLKID_FCLK_50M_DIV>;
		clock-names = "ethclk81", "phy_clk", "phy_parent_clk";
		pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
		analog_val = <0x20200000 0x0000c000 0x00000023>;
	};

	ion_dev {
		compatible = "amlogic, ion_dev";
		memory-region = <&ion_cma_reserved>;
	};

	meson-amvideom {
		compatible = "amlogic, amvideom";
		dev_name = "amvideom";
		status = "okay";
		interrupts = <0 3 1>;
		interrupt-names = "vsync";
	};

	codec_io: codec_io {
		compatible = "amlogic, meson-g12a, codec-io";
		status = "okay";
		#address-cells=<1>;
		#size-cells=<1>;
		ranges;
		io_cbus_base{
			reg = <0xffd00000 0x100000>;
		};
		io_dos_base{
			reg = <0xff620000 0x10000>;
		};
		io_hiubus_base{
			reg = <0xff63c000 0x2000>;
		};
		io_aobus_base{
			reg = <0xff800000 0x10000>;
		};
		io_vcbus_base{
			reg = <0xff900000 0x40000>;
		};
		io_dmc_base{
			reg = <0xff638000 0x2000>;
		};
		io_efuse_base{
			reg = <0xff630000 0x2000>;
		};
	};

	mesonstream {
		compatible = "amlogic, codec, streambuf";
		dev_name = "mesonstream";
		status = "okay";
		clocks = <&clkc CLKID_PARSER
			&clkc CLKID_DEMUX
			&clkc CLKID_AHB_ARB0
			&clkc CLKID_DOS
			&clkc CLKID_CLK81
			&clkc CLKID_VDEC_MUX
			&clkc CLKID_HCODEC_MUX
			&clkc CLKID_HEVC_MUX
			&clkc CLKID_HEVCF_MUX>;
		clock-names = "parser_top",
			"demux",
			"ahbarb0",
			"vdec",
			"clk_81",
			"clk_vdec_mux",
			"clk_hcodec_mux",
			"clk_hevc_mux",
			"clk_hevcb_mux";
	};

	vdec {
		compatible = "amlogic, vdec";
		dev_name = "vdec.0";
		status = "okay";
		interrupts = <0 3 1
			0 23 1
			0 32 1
			0 43 1
			0 44 1
			0 45 1
			0 72 1>;
		interrupt-names = "vsync",
			"demux",
			"parser",
			"mailbox_0",
			"mailbox_1",
			"mailbox_2",
			"parser_b";
	};

	vcodec_dec {
		compatible = "amlogic, vcodec-dec";
		dev_name = "aml-vcodec-dec";
		status = "okay";
	};

	canvas: canvas{
		compatible = "amlogic, meson, canvas";
		dev_name = "amlogic-canvas";
		status = "okay";
		reg = <0xff638000 0x2000>;
	};

	mailbox: mhu@c883c400 {
		compatible = "amlogic, meson_mhu";
		reg = <0xff63c400 0x4c>,   /* MHU registers */
		      <0xfffe7000 0x800>;   /* Payload area */
		interrupts = <0 209 1>,   /* low priority interrupt */
			     <0 210 1>,   /* bl4 receive interrupt */
			     <0 213 1>;   /* bl4 send interrupt */

		#mbox-cells = <1>;
		mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
		mboxes = <&mailbox 0 &mailbox 1>;
		num-chans-to-scp = <1>;  /*number of chans to send m3*/
		send-isr-bits = <5>;     /*BIT(idx) of isr listen when ap send*/
		ack-isr-bits = <4>;      /*BIT(idx) of ack isr*/
		m4-isr-bits = <6>;       /*BIT(idx) of m4 isr*/
		mbox-chans = <3>;        /*chan number*/
	};

	vpu: vpu {
		compatible = "amlogic, vpu-sm1";
		status = "okay";
		reg = <0xff63c100 0x100    /* hiu */
			0xff900000 0x50000 /* vcbus */
			0xffd01080 0x20    /* cbus */
			0xff8000e8 0x2>;   /* aobus */
		clocks = <&clkc CLKID_VAPB_MUX>,
			<&clkc CLKID_VPU_INTR>,
			<&clkc CLKID_VPU_P0>,
			<&clkc CLKID_VPU_P1>,
			<&clkc CLKID_VPU_MUX>;
		clock-names = "vapb_clk",
			"vpu_intr_gate",
			"vpu_clk0",
			"vpu_clk1",
			"vpu_clk";
		clk_level = <7>;
		/* 0: 100.0M    1: 166.7M    2: 200.0M    3: 250.0M */
		/* 4: 333.3M    5: 400.0M    6: 500.0M    7: 666.7M */
	};

	vout {
		compatible = "amlogic, vout";
		status = "okay";
	};

	vout2 {
		compatible = "amlogic, vout2";
		status = "okay";
		clocks = <&clkc CLKID_VPU_CLKC_P0>,
			<&clkc CLKID_VPU_CLKC_MUX>;
		clock-names = "vpu_clkc0",
			"vpu_clkc";
	};

	cvbsout: cvbsout {
		compatible = "amlogic, cvbsout-g12a";
		status = "disabled";
		reg = <0xff63c000 0x400    /* hiu hpll vdac */
			0xff900000 0x10000>; /* vcbus venc*/
		clocks = <&clkc CLKID_VCLK2_ENCI
			&clkc CLKID_VCLK2_VENCI0
			&clkc CLKID_VCLK2_VENCI1
			&clkc CLKID_DAC_CLK>;
		clock-names = "venci_top_gate",
			"venci_0_gate",
			"venci_1_gate",
			"vdac_clk_gate";
		/* clk path */
		/* 0:vid_pll vid2_clk */
		/* 1:gp0_pll vid2_clk */
		/* 2:vid_pll vid1_clk */
		/* 3:gp0_pll vid1_clk */
		clk_path = <0>;
	};

	vdac {
		compatible = "amlogic, vdac-g12a";
		reg = <0xff63c000 0x400>;  /* hiu VDAC*/
		status = "okay";
	};

	ge2d {
		compatible = "amlogic, ge2d-sm1";
		dev_name = "ge2d";
		status = "okay";
		interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "ge2d";
		clocks = <&clkc CLKID_VAPB_MUX>,
			<&clkc CLKID_G2D>,
			<&clkc CLKID_GE2D_GATE>;
		clock-names = "clk_vapb_0",
			"clk_ge2d",
			"clk_ge2d_gate";
		reg = <0xff940000 0x10000>;
	};

	efuse: efuse {
		compatible = "amlogic, efuse";
		read_cmd = <0x82000030>;
		write_cmd = <0x82000031>;
		get_max_cmd = <0x82000033>;
		mem_in_base_cmd = <0x82000020>;
		mem_out_base_cmd = <0x82000021>;
		key = <&efusekey>;
		clocks = <&clkc CLKID_EFUSE>;
		clock-names = "efuse_clk";
		status = "disabled";
	};

	efusekey: efusekey {
		keynum = <4>;
		key0 = <&key_0>;
		key1 = <&key_1>;
		key2 = <&key_2>;
		key3 = <&key_3>;

		key_0: key_0 {
			keyname = "mac";
			offset = <0>;
			size = <6>;
		};
		key_1: key_1 {
			keyname = "mac_bt";
			offset = <6>;
			size = <6>;
		};
		key_2: key_2 {
			keyname = "mac_wifi";
			offset = <12>;
			size = <6>;
		};
		key_3: key_3 {
			keyname = "usid";
			offset = <18>;
			size = <16>;
		};
	};

	rdma{
		compatible = "amlogic, meson, rdma";
		dev_name = "amlogic-rdma";
		status = "okay";
		interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "rdma";
	};

	meson_fb: fb {
		compatible = "amlogic, fb-sm1";
		memory-region = <&logo_reserved>;
		dev_name = "meson-fb";
		status = "disable";
		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING
			GIC_SPI 56 IRQ_TYPE_EDGE_RISING
			GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "viu-vsync", "viu2-vsync", "rdma";
		/* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/
		display_mode_default = "1080p60hz";
		scale_mode = <1>;
		/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
		display_size_default = <1920 1080 1920 2160 32>;
		/*1920*1080*4*3 = 0x17BB000*/
		clocks = <&clkc CLKID_VPU_CLKC_MUX>;
		clock-names = "vpu_clkc";
	};

	rng{
		compatible="amlogic,meson-rng";
		status="okay";
		#address-cells=<1>;
		#size-cells=<1>;
		reg=<0xff630218 0x4>;
		quality=/bits/ 16 <1000>;
	};

	cpu_ver_name {
		compatible = "amlogic, cpu-major-id-sm1";
	};

	aml_bt: aml_bt {
		compatible = "amlogic, aml-bt";
		status = "disabled";
		reset-gpios = <&gpio       GPIOX_17       GPIO_ACTIVE_HIGH>;
		hostwake-gpios = <&gpio       GPIOX_19       GPIO_ACTIVE_HIGH>;
	};

	aml_wifi: aml_wifi {
		compatible = "amlogic, aml-wifi";
		status = "disabled";
		interrupt-gpios = <&gpio       GPIOX_7       GPIO_ACTIVE_HIGH>;
		irq_trigger_type = "GPIO_IRQ_LOW";
		power_on-gpios = <&gpio       GPIOX_6       GPIO_ACTIVE_HIGH>;
		dhd_static_buf;	//if use bcm wifi, config dhd_static_buf
		pinctrl-names = "default";
		pinctrl-0 = <&pwm_e_pins>;
		pwm_config = <&wifi_pwm_conf>;
	};

	wifi_pwm_conf:wifi_pwm_conf{
		pwm_channel1_conf {
			pwms = <&pwm_ef MESON_PWM_0 30541 0>;
			duty-cycle = <15270>;
			times = <10>;
		};
		pwm_channel2_conf {
			pwms = <&pwm_ef MESON_PWM_2 30500 0>;
			duty-cycle = <15250>;
			times = <12>;
		};
	};

	meson_cooldev: meson-cooldev@0 {
		status = "okay";
		compatible = "amlogic, meson-cooldev";
		cooling_devices {
			cpucore_cool_cluster0 {
				cluster_id = <0>;
				device_type = "cpucore";
				node_name = "cpucore0";
			};
			gpufreq_cool {
				dyn_coeff = <215>;
				device_type = "gpufreq";
				node_name = "bifrost";
			};
		};
		cpucore0:cpucore0 {
			#cooling-cells = <2>;
		};
	};
	/*meson cooling devices end*/
	thermal-zones {
		soc_thermal: soc_thermal {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			sustainable-power = <1460>;
			thermal-sensors = <&p_tsensor 0>;
			trips {
				pswitch_on: trip-point@0 {
					temperature = <60000>;
					hysteresis = <2000>;
					type = "passive";
				};
				pcontrol: trip-point@1 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				phot: trip-point@2 {
					temperature = <85000>;
					hysteresis = <5000>;
					type = "hot";
				};
				pcritical: trip-point@3 {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
			cooling-maps {
				cpufreq_cooling_map {
					trip = <&pcontrol>;
					cooling-device = <&cpu0 0 6>;
					contribution = <1024>;
				};
				cpucore_cooling_map {
					trip = <&pcontrol>;
					cooling-device = <&cpucore0 0 2>;
					contribution = <1024>;
				};
				gpufreq_cooling_map {
					trip = <&pcontrol>;
					cooling-device = <&gpu 0 2>;
					contribution = <1024>;
				};
			};
		};
		ddr_thermal: ddr_thermal {
			polling-delay = <2000>;
			polling-delay-passive = <250>;
			sustainable-power = <1460>;
			thermal-sensors = <&d_tsensor 1>;
			trips {
				dswitch_on: trip-point@0 {
					temperature = <60000>;
					hysteresis = <2000>;
					type = "passive";
				};
				dcontrol: trip-point@1 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				dhot: trip-point@2 {
					temperature = <85000>;
					hysteresis = <5000>;
					type = "hot";
				};
				dcritical: trip-point@3 {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};
	};
};

&pinctrl_aobus {
	sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins {
		mux {
			groups = "GPIOAO_0",
				   "GPIOAO_1";
			function = "gpio_aobus";
		};
	};

	sd_to_ao_uart_pins:sd_to_ao_uart_pins {
		mux {
			groups = "uart_ao_a_tx",
				   "uart_ao_a_rx";
				   function = "uart_ao_a";
				   bias-pull-up;
				   input-enable;
		};
	};

	pwm_ao_a_pins: pwm_ao_a {
		mux {
			groups = "pwm_ao_a";
			function = "pwm_ao_a";
		};
	};

	pwm_ao_a_hiz_pins: pwm_ao_a_hiz {
		mux {
			groups = "pwm_ao_a_hiz";
			function = "pwm_ao_a";
		};
	};

	pwm_ao_b_pins: pwm_ao_b {
		mux {
			groups = "pwm_ao_b";
			function = "pwm_ao_b";
		};
	};

	pwm_ao_c_pins1: pwm_ao_c_pins1 {
		mux {
			groups = "pwm_ao_c_4";
			function = "pwm_ao_c";
		};
	};

	pwm_ao_c_pins2: pwm_ao_c_pins2 {
		mux {
			groups = "pwm_ao_c_6";
			function = "pwm_ao_c";
		};
	};

	pwm_ao_c_hiz_pins: pwm_ao_c_hiz {
		mux {
			groups = "pwm_ao_c_hiz";
			function = "pwm_ao_c";
		};
	};

	pwm_ao_d_pins1: pwm_ao_d_pins1 {
		mux {
			groups = "pwm_ao_d_5";
			function = "pwm_ao_d";
		};
	};

	pwm_ao_d_pins2: pwm_ao_d_pins2 {
		mux {
			groups = "pwm_ao_d_10";
			function = "pwm_ao_d";
		};
	};

	pwm_ao_d_pins3: pwm_ao_d_pins3 {
		mux {
			groups = "pwm_ao_d_e";
			function = "pwm_ao_d";
		};
	};

	ao_i2c_master_pins1:ao_i2c_pins1 {
		mux {
			groups = "i2c_ao_sck",
				"i2c_ao_sda";
			function = "i2c_ao";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	ao_i2c_master_pins2:ao_i2c_pins2 {
		mux {
			groups = "i2c_ao_sck_e",
				"i2c_ao_sda_e";
			function = "i2c_ao";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	remote_pins:remote_pin {
		mux {
			groups = "remote_ao_input";
			function = "remote_ao_input";
		};
	};

	irblaster_pins:irblaster_pin {
		mux {
			groups = "remote_ao_out";
			function = "remote_ao_out";
		};
	};

	ao_uart_pins:ao_uart {
		mux {
			groups = "uart_ao_a_tx",
				"uart_ao_a_rx";
			function = "uart_ao_a";
		};
	};

	ao_b_uart_pins1:ao_b_uart1 {
		mux {
			groups = "uart_ao_b_tx_2",
				"uart_ao_b_rx_3";
			function = "uart_ao_b";
		};
	};

	ao_b_uart_pins2:ao_b_uart2 {
		mux {
			groups = "uart_ao_b_tx_8",
				"uart_ao_b_rx_9";
			function = "uart_ao_b";
		};
	};

	jtag_a_pins:jtag_a_pin {
		mux {
			groups = "jtag_a_tdi",
			"jtag_a_tdo",
			"jtag_a_clk",
			"jtag_a_tms";
			function = "jtag_a";
		};
	};
};

&pinctrl_periphs {
	emmc_pins: emmc {
		mux {
			groups = "emmc_nand_d0",
				"emmc_nand_d1",
				"emmc_nand_d2",
				"emmc_nand_d3",
				"emmc_nand_d4",
				"emmc_nand_d5",
				"emmc_nand_d6",
				"emmc_nand_d7",
				"emmc_clk",
				"emmc_cmd";
			function = "emmc";
			bias-pull-up;
			input-enable;
		};
		mux1 {
			groups = "emmc_nand_ds";
			function = "emmc";
			input-enable;
			bias-pull-down;
		};
	};

	emmc_clk_gate_pins: emmc_clk_gate {
		mux {
			groups = "emmc_clk";
			function = "emmc";
			bias-pull-down;
		};
	};

	sdcard_pins: sdcard {
		mux {
			groups = "sdcard_d0_c",
				"sdcard_d1_c",
				"sdcard_d2_c",
				"sdcard_d3_c",
				"sdcard_cmd_c";
			function = "sdcard";
			bias-pull-up;
			input-enable;
			drive-strength = <4>;
		};
		mux1 {
			groups ="sdcard_clk_c";
			function = "sdcard";
			bias-pull-up;
			output-high;
			drive-strength = <4>;
		};
	};

	sdcard_clk_gate_pins: sdcard_clk_gate {
		mux {
			groups = "sdcard_clk_c";
			function = "sdcard";
			bias-pull-down;
		};
	};
	sdio_clk_gate_pins:sdio_clk_cmd_pins {
		mux {
			groups = "sdio_clk";
			function = "sdio";
			bias-pull-down;
			drive-strength = <4>;
		};
	};

	sdio_pins:sdio_all_pins {
		mux {
			groups = "sdio_d0",
				"sdio_d1",
				"sdio_d2",
				"sdio_d3",
				"sdio_clk",
				"sdio_cmd";
			function = "sdio";
			input-enable;
			bias-pull-up;
			drive-strength = <4>;
		};
	};
	sd_1bit_pins:sd_1bit_pins {
		mux {
			groups = "sdcard_d0_c",
					"sdcard_cmd_c";
			function = "sdcard";
			input-enable;
			bias-pull-up;
			drive-strength = <4>;
		};
		mux1 {
			groups = "sdcard_clk_c";
			function = "sdcard";
			bias-pull-up;
			output-high;
			drive-strength = <4>;
		};
	};

	sd_clr_all_pins:sd_clr_all_pins {
		mux {
			groups = "GPIOC_0",
				   "GPIOC_1",
				   "GPIOC_2",
				   "GPIOC_3",
				   "GPIOC_5";
			function = "gpio_periphs";
			output-high;
		};
		mux1 {
			groups = "GPIOC_4";
			function = "gpio_periphs";
			output-low;
		};
	};

	sd_clr_noall_pins:sd_clr_noall_pins {
		mux {
			groups = "GPIOC_0",
				   "GPIOC_1",
				   "GPIOC_4",
				   "GPIOC_5";
			function = "gpio_periphs";
			output-high;
		};
	};

	ao_to_sd_uart_pins:ao_to_sd_uart_pins {
		mux {
			groups = "uart_ao_a_rx_c",
					"uart_ao_a_tx_c";
			function = "uart_ao_a_c";
			bias-pull-up;
			input-enable;
		};
	};
	pwm_a_pins: pwm_a {
		mux {
			groups = "pwm_a";
			function = "pwm_a";
		};
	};

	pwm_b_pins1: pwm_b_pins1 {
		mux {
			groups = "pwm_b_x7";
			function = "pwm_b";
		};
	};

	pwm_b_pins2: pwm_b_pins2 {
		mux {
			groups = "pwm_b_x19";
			function = "pwm_b";
		};
	};

	pwm_c_pins1: pwm_c_pins1 {
		mux {
			groups = "pwm_c_c";
			function = "pwm_c";
		};
	};

	pwm_c_pins2: pwm_c_pins2 {
		mux {
			groups = "pwm_c_x5";
			function = "pwm_c";
		};
	};

	pwm_c_pins3: pwm_c_pins3 {
		mux {
			groups = "pwm_c_x8";
			function = "pwm_c";
		};
	};

	pwm_d_pins1: pwm_d_pins1 {
		mux {
			groups = "pwm_d_x3";
			function = "pwm_d";
		};
	};

	pwm_d_pins2: pwm_d_pins2 {
		mux {
			groups = "pwm_d_x6";
			function = "pwm_d";
		};
	};

	pwm_e_pins: pwm_e {
		mux {
			groups = "pwm_e";
			function = "pwm_e";
		};
	};

	pwm_f_pins1: pwm_f_pins1 {
		mux {
			groups = "pwm_f_x";
			function = "pwm_f";
		};
	};

	pwm_f_pins2: pwm_f_pins2 {
		mux {
			groups = "pwm_f_h";
			function = "pwm_f";
		};
	};

	i2c0_master_pins1:i2c0_pins1 {
		mux {
			groups = "i2c0_sda_c",
				"i2c0_sck_c";
			function = "i2c0";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c0_master_pins2:i2c0_pins2 {
		mux {
			groups = "i2c0_sda_z0",
				"i2c0_sck_z1";
			function = "i2c0";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c0_master_pins3:i2c0_pins3 {
		mux {
			groups = "i2c0_sda_z7",
				"i2c0_sck_z8";
			function = "i2c0";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c1_master_pins1:i2c1_pins1 {
		mux {
			groups = "i2c1_sda_x",
				"i2c1_sck_x";
			function = "i2c1";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c1_master_pins2:i2c1_pins2 {
		mux {
			groups = "i2c1_sda_h2",
				"i2c1_sck_h3";
			function = "i2c1";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c1_master_pins3:i2c1_pins3 {
		mux {
			groups = "i2c1_sda_h6",
				"i2c1_sck_h7";
			function = "i2c1";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c2_master_pins1:i2c2_pins1 {
		mux {
			groups = "i2c2_sda_x",
				"i2c2_sck_x";
			function = "i2c2";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c2_master_pins2:i2c2_pins2 {
		mux {
			groups = "i2c2_sda_z",
				"i2c2_sck_z";
			function = "i2c2";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c3_master_pins1:i2c3_pins1 {
		mux {
			groups = "i2c3_sda_h",
				"i2c3_sck_h";
			function = "i2c3";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	i2c3_master_pins2:i2c3_pins2 {
		mux {
			groups = "i2c3_sda_a",
				"i2c3_sck_a";
			function = "i2c3";
			bias-pull-up;
			drive-strength = <2>;
		};
	};

	internal_eth_pins: internal_eth_pins {
		mux {
			groups = "eth_link_led",
				"eth_act_led";
			function = "eth";
		};
	};

	internal_gpio_pins: internal_gpio_pins {
		mux {
			groups = "GPIOZ_14",
				"GPIOZ_15";
			function = "gpio_periphs";
			bias-disable;
			input-enable;
		};
	};

	external_eth_pins: external_eth_pins {
		mux {
			groups = "eth_mdio",
			"eth_mdc",
			"eth_rgmii_rx_clk",
			"eth_rx_dv",
			"eth_rxd0",
			"eth_rxd1",
			"eth_rxd2_rgmii",
			"eth_rxd3_rgmii",
			"eth_rgmii_tx_clk",
			"eth_txen",
			"eth_txd0",
			"eth_txd1",
			"eth_txd2_rgmii",
			"eth_txd3_rgmii";
			function = "eth";
			drive-strength = <3>;
		};
	};

	spicc0_pins_x: spicc0_pins_x {
		mux {
			groups = "spi0_mosi_x",
				 "spi0_miso_x",
				 "spi0_clk_x";
			function = "spi0";
			drive-strength = <2>;
		};
	};

	spicc0_pins_c: spicc0_pins_c {
		mux {
			groups = "spi0_mosi_c",
				 "spi0_miso_c",
				 "spi0_clk_c";
			function = "spi0";
			drive-strength = <2>;
		};
	};

	spicc1_pins: spicc1_pins {
		mux {
			groups = "spi1_mosi",
				 "spi1_miso",
				 "spi1_clk";
			function = "spi1";
			drive-strength = <2>;
		};
	};

	spifc_pins: spifc_pins {
		mux {
			groups = "nor_d",
				 "nor_q",
				 "nor_c",
				 "nor_cs",
				 "nor_hold",
				 "nor_wp";
			function = "nor";
			drive-strength = <1>;
		};
	};

	all_nand_pins: all_nand_pins {
		mux {
			groups = "emmc_nand_d0",
				"emmc_nand_d1",
				"emmc_nand_d2",
				"emmc_nand_d3",
				"emmc_nand_d4",
				"emmc_nand_d5",
				"emmc_nand_d6",
				"emmc_nand_d7",
				"nand_ce0",
				"nand_ale",
				"nand_cle",
				"nand_wen_clk",
				"nand_ren_wr",
				"nand_rb0";
			function = "nand";
			input-enable;
		};
	};

	nand_cs_pins: nand_cs {
		mux {
			groups = "nand_ce0";
			function = "nand";
		};
	};

	a_uart_pins:a_uart {
		mux {
			groups = "uart_a_tx",
				"uart_a_rx",
				"uart_a_cts",
				"uart_a_rts";
			function = "uart_a";
		};
	};

	b_uart_pins:b_uart {
		mux {
			groups = "uart_b_tx",
				"uart_b_rx";
			function = "uart_b";
		};
	};

	c_uart_pins:c_uart {
		mux {
			groups = "uart_c_rx",
				"uart_c_tx";
			function = "uart_c";
		};
	};

	hdmitx_hpd: hdmitx_hpd {
		mux {
			groups = "hdmitx_hpd_in";
			function = "hdmitx";
			bias-disable;
		};
	};

	hdmitx_hpd_gpio: hdmitx_hpd_gpio {
		mux {
			groups = "GPIOH_1";
			function = "gpio_periphs";
			bias-disable;
		};
	};

	hdmitx_ddc: hdmitx_ddc {
		mux {
			groups = "hdmitx_sda",
				"hdmitx_sck";
			function = "hdmitx";
			bias-disable;
			drive-strength = <3>;
		};
	};

	cec_a: cec_a {
		mux {
			groups = "cec_ao_a_h";
			function = "cec_ao_a_h";
		};
	};

	cec_b: cec_b {
		mux {
			groups = "cec_ao_b_h";
			function = "cec_ao_b_h";
		};
	};

	jtag_b_pins:jtag_b_pin {
		mux {
			groups = "jtag_b_tdi",
			"jtag_b_tdo",
			"jtag_b_clk",
			"jtag_b_tms";
			function = "jtag_b";
		};
	};
};

&gpu{
	tbl =  <&dvfs285_cfg
	&dvfs400_cfg
	&dvfs500_cfg
	&dvfs666_cfg
	&dvfs800_cfg
	&dvfs800_cfg>;
};