// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/of_address.h>

#include "../clkc.h"
#include "../clk-dualdiv.h"
#include "c1.h"

//static DEFINE_SPINLOCK(meson_clk_lock);

/*
 * GATE for c1
 * its parent clock is sys clock, the same the
 * clk81 in previos SoC
 */
#define MESON_C1_SYS_GATE(_name, _reg, _bit)				\
struct clk_regmap _name = {						\
	.data = &(struct clk_regmap_gate_data){				\
		.offset = (_reg),					\
		.bit_idx = (_bit),					\
	},								\
	.hw.init = &(struct clk_init_data) {				\
		.name = #_name,						\
		.ops = &clk_regmap_gate_ops,				\
		.parent_names = (const char *[]){ "sys_clk" },		\
		.num_parents = 1,					\
		.flags = CLK_IGNORE_UNUSED,				\
	},								\
}

#define MESON_C1_AXI_GATE(_name, _reg, _bit)				\
struct clk_regmap _name = {						\
	.data = &(struct clk_regmap_gate_data){				\
		.offset = (_reg),					\
		.bit_idx = (_bit),					\
	},								\
	.hw.init = &(struct clk_init_data) {				\
		.name = #_name,						\
		.ops = &clk_regmap_gate_ops,				\
		.parent_names = (const char *[]){ "axi_clk" },		\
		.num_parents = 1,					\
		.flags = CLK_IGNORE_UNUSED,				\
	},								\
}

#define MESON_C1_XTAL_GATE(_name, _reg, _bit)				\
struct clk_regmap _name = {						\
	.data = &(struct clk_regmap_gate_data){				\
		.offset = (_reg),					\
		.bit_idx = (_bit),					\
	},								\
	.hw.init = &(struct clk_init_data) {				\
		.name = #_name,						\
		.ops = &clk_regmap_gate_ops,				\
		.parent_names = (const char *[]){ "c1_ee_core" },	\
		.num_parents = 1,					\
		.flags = CLK_IGNORE_UNUSED | CLK_IS_CRITICAL,		\
	},								\
}

/* PLL clock in gates,its parent is xtal */
static MESON_C1_XTAL_GATE(xtal_clktree,		SYS_OSCIN_CTRL,	0);
static MESON_C1_XTAL_GATE(xtal_fixpll,		SYS_OSCIN_CTRL,	1);
static MESON_C1_XTAL_GATE(xtal_ddrpll,		SYS_OSCIN_CTRL,	2);
static MESON_C1_XTAL_GATE(xtal_usb_ctrl,	SYS_OSCIN_CTRL,	3);
static MESON_C1_XTAL_GATE(xtal_hifipll,		SYS_OSCIN_CTRL,	4);
static MESON_C1_XTAL_GATE(xtal_syspll,		SYS_OSCIN_CTRL,	5);
static MESON_C1_XTAL_GATE(xtal_dds,		SYS_OSCIN_CTRL,	6);
static MESON_C1_XTAL_GATE(xtal_ethpll,		SYS_OSCIN_CTRL,	7);
static MESON_C1_XTAL_GATE(xtal_usbphy,		SYS_OSCIN_CTRL,	8);
static MESON_C1_XTAL_GATE(xtal_gppll,		SYS_OSCIN_CTRL,	9);
static MESON_C1_XTAL_GATE(xtal_gpio_m10,		SYS_OSCIN_CTRL,	10);
static MESON_C1_XTAL_GATE(xtal_gpio_m13,		SYS_OSCIN_CTRL,	11);

/* Everything Else (EE) domain gates */
/* CLKTREE_SYS_CLK_EN0 */
static MESON_C1_SYS_GATE(clk_tree,		SYS_CLK_EN0,	0);
static MESON_C1_SYS_GATE(reset_ctrl,	SYS_CLK_EN0,	1);
static MESON_C1_SYS_GATE(analog_ctrl,	SYS_CLK_EN0,	2);
static MESON_C1_SYS_GATE(pwr_ctrl,		SYS_CLK_EN0,	3);
static MESON_C1_SYS_GATE(pad_ctrl,		SYS_CLK_EN0,	4);
static MESON_C1_SYS_GATE(sys_ctrl,		SYS_CLK_EN0,	5);
static MESON_C1_SYS_GATE(temp_sensor,	SYS_CLK_EN0,	6);
static MESON_C1_SYS_GATE(am2axi_dev,	SYS_CLK_EN0,	7);
static MESON_C1_SYS_GATE(spicc_b,		SYS_CLK_EN0,	8);
static MESON_C1_SYS_GATE(spicc_a,		SYS_CLK_EN0,	9);
static MESON_C1_SYS_GATE(clk_msr,		SYS_CLK_EN0,	10);
static MESON_C1_SYS_GATE(audio,		SYS_CLK_EN0,	11);
static MESON_C1_SYS_GATE(jtag_ctrl,		SYS_CLK_EN0,	12);
static MESON_C1_SYS_GATE(saradc,		SYS_CLK_EN0,	13);
static MESON_C1_SYS_GATE(pwm_ef,		SYS_CLK_EN0,	14);
static MESON_C1_SYS_GATE(pwm_cd,		SYS_CLK_EN0,	15);
static MESON_C1_SYS_GATE(pwm_ab,		SYS_CLK_EN0,	16);
static MESON_C1_SYS_GATE(i2c_s,		SYS_CLK_EN0,	18);
static MESON_C1_SYS_GATE(ir_ctrl,		SYS_CLK_EN0,	19);
static MESON_C1_SYS_GATE(i2c_m_d,		SYS_CLK_EN0,	20);
static MESON_C1_SYS_GATE(i2c_m_c,		SYS_CLK_EN0,	21);
static MESON_C1_SYS_GATE(i2c_m_b,		SYS_CLK_EN0,	22);
static MESON_C1_SYS_GATE(i2c_m_a,		SYS_CLK_EN0,	23);
static MESON_C1_SYS_GATE(acodec,		SYS_CLK_EN0,	24);
static MESON_C1_SYS_GATE(otp,		SYS_CLK_EN0,	25);
static MESON_C1_SYS_GATE(sys_sd_emmc_a,		SYS_CLK_EN0,	26);
static MESON_C1_SYS_GATE(usb_phy,		SYS_CLK_EN0,	27);
static MESON_C1_SYS_GATE(usb_ctrl,		SYS_CLK_EN0,	28);
static MESON_C1_SYS_GATE(sys_dspb,		SYS_CLK_EN0,	29);
static MESON_C1_SYS_GATE(sys_dspa,		SYS_CLK_EN0,	30);
static MESON_C1_SYS_GATE(dma,		SYS_CLK_EN0,	31);
/* CLKTREE_SYS_CLK_EN1 */
static MESON_C1_SYS_GATE(irq_ctrl,		SYS_CLK_EN1,	0);
static MESON_C1_SYS_GATE(nic,		SYS_CLK_EN1,	1);
static MESON_C1_SYS_GATE(gic,		SYS_CLK_EN1,	2);
static MESON_C1_SYS_GATE(uart_c,		SYS_CLK_EN1,	3);
static MESON_C1_SYS_GATE(uart_b,		SYS_CLK_EN1,	4);
static MESON_C1_SYS_GATE(uart_a,		SYS_CLK_EN1,	5);
static MESON_C1_SYS_GATE(rsa,		SYS_CLK_EN1,	8);
static MESON_C1_SYS_GATE(coresight,		SYS_CLK_EN1,	9);
static MESON_C1_SYS_GATE(csi_ph1,		SYS_CLK_EN1,	10);
static MESON_C1_SYS_GATE(csi_phy0,		SYS_CLK_EN1,	11);
static MESON_C1_SYS_GATE(mipi_isp,		SYS_CLK_EN1,	12);
static MESON_C1_SYS_GATE(csi_dig,		SYS_CLK_EN1,	13);
static MESON_C1_SYS_GATE(ge2d,		SYS_CLK_EN1,	14);
static MESON_C1_SYS_GATE(gdc,		SYS_CLK_EN1,	15);
static MESON_C1_SYS_GATE(dos_apb,		SYS_CLK_EN1,	16);
static MESON_C1_SYS_GATE(nna,		SYS_CLK_EN1,	17);
static MESON_C1_SYS_GATE(eth_phy,		SYS_CLK_EN1,	18);
static MESON_C1_SYS_GATE(eth_mac,		SYS_CLK_EN1,	19);
static MESON_C1_SYS_GATE(uart_e,		SYS_CLK_EN1,	20);
static MESON_C1_SYS_GATE(uart_d,		SYS_CLK_EN1,	21);
static MESON_C1_SYS_GATE(pwm_ij,		SYS_CLK_EN1,	22);
static MESON_C1_SYS_GATE(pwm_gh,		SYS_CLK_EN1,	23);
static MESON_C1_SYS_GATE(i2c_m_e,		SYS_CLK_EN1,	24);
static MESON_C1_SYS_GATE(sd_emmc_C,		SYS_CLK_EN1,	25);
static MESON_C1_SYS_GATE(sd_emmc_B,		SYS_CLK_EN1,	26);
static MESON_C1_SYS_GATE(rom,		SYS_CLK_EN1,	27);
static MESON_C1_SYS_GATE(spifc,		SYS_CLK_EN1,	28);
static MESON_C1_SYS_GATE(prod_i2c,		SYS_CLK_EN1,	29);
static MESON_C1_SYS_GATE(dos,		SYS_CLK_EN1,	30);
static MESON_C1_SYS_GATE(cpu_ctrl,		SYS_CLK_EN1,	31);
/* CLKTREE_SYS_CLK_EN2 */
static MESON_C1_SYS_GATE(sys_rama,		SYS_CLK_EN2,	0);
static MESON_C1_SYS_GATE(sys_ramb,		SYS_CLK_EN2,	1);
static MESON_C1_SYS_GATE(sys_ramc,		SYS_CLK_EN2,	2);
/* CLKTREE_AXI_CLK_EN */
static MESON_C1_AXI_GATE(axi_am2axi_vad,	AXI_CLK_EN,	0);
static MESON_C1_AXI_GATE(axi_audio_vad,		AXI_CLK_EN,	1);
static MESON_C1_AXI_GATE(axi_dmc,		AXI_CLK_EN,	3);
static MESON_C1_AXI_GATE(axi_ramb,		AXI_CLK_EN,	5);
static MESON_C1_AXI_GATE(axi_rama,		AXI_CLK_EN,	6);
static MESON_C1_AXI_GATE(axi_nic,		AXI_CLK_EN,	8);
static MESON_C1_AXI_GATE(axi_dma,		AXI_CLK_EN,	9);
static MESON_C1_AXI_GATE(axi_ramc,		AXI_CLK_EN,	13);

/* fixed pll = 2000M
 *
 * fixed pll ----- fclk_div2 = 1000M
 *           |
 *           ----- fclk_div2.5 = 800M
 *           |
 *           ----- fclk_div3 = 666M
 *           |
 *           ----- fclk_div4 = 500M
 *           |
 *           ----- fclk_div5 = 400M
 *           |
 *           ----- fclk_div7 = 286M
 */
static struct clk_regmap c1_fixed_pll_dco = {
	.data = &(struct meson_clk_pll_data){
		.en = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.m = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 0,
			.width   = 8,
		},
		.n = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 10,
			.width   = 5,
		},
		.od = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 16,
			.width   = 2,
		},
		.frac = {
			.reg_off = ANACTRL_FIXPLL_CTRL1,
			.shift   = 0,
			.width   = 19,
		},
		.l = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 31,
			.width   = 1,
		},
		.rst = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 29,
			.width   = 1,
		},
	},
	.hw.init = &(struct clk_init_data){
		.name = "fixed_pll_dco",
		.ops = &meson_c1_clk_pll_ro_ops,
		.parent_names = (const char *[]){ "xtal_fixpll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fixed_pll = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 20,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "fixed_pll",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fixed_pll_dco" },
		.num_parents = 1,
		.flags = CLK_IGNORE_UNUSED,
	},
};

static struct clk_fixed_factor c1_fclk_div2_div = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div2_div",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div2 = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 21,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div2",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div2_div" },
		.num_parents = 1,
		/*
		 * add CLK_IS_CRITICAL flag to avoid being disabled by clk core
		 * or its children clocks.
		 */
		.flags = CLK_IS_CRITICAL,
	},
};

static struct clk_fixed_factor c1_fclk_div2p5_div = {
	.mult = 2,
	.div = 5,
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div2p5_div",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div2p5 = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 21,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div2p5",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div2p5_div" },
		.num_parents = 1,
		/*
		 * add CLK_IS_CRITICAL flag to avoid being disabled by clk core
		 * or its children clocks.
		 */
		.flags = CLK_IS_CRITICAL,
	},
};

static struct clk_fixed_factor c1_fclk_div3_div = {
	.mult = 1,
	.div = 3,
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div3_div",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div3 = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 22,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div3",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div3_div" },
		.num_parents = 1,
		/*
		 * add CLK_IS_CRITICAL flag to avoid being disabled by clk core
		 * its children clocks.
		 */
		.flags = CLK_IS_CRITICAL,
	},
};

static struct clk_fixed_factor c1_fclk_div4_div = {
	.mult = 1,
	.div = 4,
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div4_div",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div4 = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 21,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div4",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div4_div" },
		.num_parents = 1,
		/*
		 * add CLK_IS_CRITICAL flag to avoid being disabled by clk core
		 * or its children clocks.
		 */
		.flags = CLK_IS_CRITICAL,
	},
};

static struct clk_fixed_factor c1_fclk_div5_div = {
	.mult = 1,
	.div = 5,
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div5_div",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div5 = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 23,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div5",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div5_div" },
		.num_parents = 1,
		/*
		 * add CLK_IS_CRITICAL flag to avoid being disabled by clk core
		 * its children clocks.
		 */
		.flags = CLK_IS_CRITICAL,
	},
};

static struct clk_fixed_factor c1_fclk_div7_div = {
	.mult = 1,
	.div = 7,
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div7_div",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div7 = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div7",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div7_div" },
		.num_parents = 1,
		/*
		 * add CLK_IS_CRITICAL flag to avoid being disabled by clk core
		 * or its children clock.
		 */
		.flags = CLK_IS_CRITICAL,
	},
};

/*
 * HIFI PLL and SYS PLL rang from 768M to 1536M
 * the PLL parameter table is for hifi/sys pll.
 * Adtional, there is no OD in A1 PLL.
 */
#ifdef CONFIG_ARM
static const struct pll_params_table c1_pll_params_table[] = {
	PLL_PARAMS(32, 1, 0), /* DCO = 768M */
	PLL_PARAMS(33, 1, 0), /* DCO = 792M */
	PLL_PARAMS(34, 1, 0), /* DCO = 816M */
	PLL_PARAMS(35, 1, 0), /* DCO = 840M */
	PLL_PARAMS(36, 1, 0), /* DCO = 864M */
	PLL_PARAMS(37, 1, 0), /* DCO = 888M */
	PLL_PARAMS(38, 1, 0), /* DCO = 912M */
	PLL_PARAMS(39, 1, 0), /* DCO = 936M */
	PLL_PARAMS(40, 1, 0), /* DCO = 960M */
	PLL_PARAMS(41, 1, 0), /* DCO = 984M */
	PLL_PARAMS(42, 1, 0), /* DCO = 1008M */
	PLL_PARAMS(43, 1, 0), /* DCO = 1032M */
	PLL_PARAMS(44, 1, 0), /* DCO = 1056M */
	PLL_PARAMS(45, 1, 0), /* DCO = 1080M */
	PLL_PARAMS(46, 1, 0), /* DCO = 1104M */
	PLL_PARAMS(47, 1, 0), /* DCO = 1128M */
	PLL_PARAMS(48, 1, 0), /* DCO = 1152M */
	PLL_PARAMS(49, 1, 0), /* DCO = 1176M */
	PLL_PARAMS(50, 1, 0), /* DCO = 1200M */
	PLL_PARAMS(51, 1, 0), /* DCO = 1224M */
	PLL_PARAMS(52, 1, 0), /* DCO = 1248M */
	PLL_PARAMS(53, 1, 0), /* DCO = 1272M */
	PLL_PARAMS(54, 1, 0), /* DCO = 1296M */
	PLL_PARAMS(55, 1, 0), /* DCO = 1320M */
	PLL_PARAMS(56, 1, 0), /* DCO = 1344M */
	PLL_PARAMS(57, 1, 0), /* DCO = 1368M */
	PLL_PARAMS(58, 1, 0), /* DCO = 1392M */
	PLL_PARAMS(59, 1, 0), /* DCO = 1416M */
	PLL_PARAMS(60, 1, 0), /* DCO = 1440M */
	PLL_PARAMS(61, 1, 0), /* DCO = 1464M */
	PLL_PARAMS(62, 1, 0), /* DCO = 1488M */
	PLL_PARAMS(63, 1, 0), /* DCO = 1512M */
	PLL_PARAMS(64, 1, 0), /* DCO = 1536M */

	{ /* sentinel */ },
};
#else
static const struct pll_params_table c1_pll_params_table[] = {
	PLL_PARAMS(32, 1), /* DCO = 768M */
	PLL_PARAMS(33, 1), /* DCO = 792M */
	PLL_PARAMS(34, 1), /* DCO = 816M */
	PLL_PARAMS(35, 1), /* DCO = 840M */
	PLL_PARAMS(36, 1), /* DCO = 864M */
	PLL_PARAMS(37, 1), /* DCO = 888M */
	PLL_PARAMS(38, 1), /* DCO = 912M */
	PLL_PARAMS(39, 1), /* DCO = 936M */
	PLL_PARAMS(40, 1), /* DCO = 960M */
	PLL_PARAMS(41, 1), /* DCO = 984M */
	PLL_PARAMS(42, 1), /* DCO = 1008M */
	PLL_PARAMS(43, 1), /* DCO = 1032M */
	PLL_PARAMS(44, 1), /* DCO = 1056M */
	PLL_PARAMS(45, 1), /* DCO = 1080M */
	PLL_PARAMS(46, 1), /* DCO = 1104M */
	PLL_PARAMS(47, 1), /* DCO = 1128M */
	PLL_PARAMS(48, 1), /* DCO = 1152M */
	PLL_PARAMS(49, 1), /* DCO = 1176M */
	PLL_PARAMS(50, 1), /* DCO = 1200M */
	PLL_PARAMS(51, 1), /* DCO = 1224M */
	PLL_PARAMS(52, 1), /* DCO = 1248M */
	PLL_PARAMS(53, 1), /* DCO = 1272M */
	PLL_PARAMS(54, 1), /* DCO = 1296M */
	PLL_PARAMS(55, 1), /* DCO = 1320M */
	PLL_PARAMS(56, 1), /* DCO = 1344M */
	PLL_PARAMS(57, 1), /* DCO = 1368M */
	PLL_PARAMS(58, 1), /* DCO = 1392M */
	PLL_PARAMS(59, 1), /* DCO = 1416M */
	PLL_PARAMS(60, 1), /* DCO = 1440M */
	PLL_PARAMS(61, 1), /* DCO = 1464M */
	PLL_PARAMS(62, 1), /* DCO = 1488M */
	PLL_PARAMS(63, 1), /* DCO = 1512M */
	PLL_PARAMS(64, 1), /* DCO = 1536M */

	{ /* sentinel */ },
};
#endif

/*
 * Internal hifi pll emulation configuration parameters
 * the table update by vlsi, keep the old table here.
 */
/*
 *static const struct reg_sequence c1_hifi_init_regs[] = {
 *       { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x10022300 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x00300000 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18440 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x11f18440, .delay_us = 10 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x15f18440, .delay_us = 40 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001140 },
 *       { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
 *};
 */

#ifdef CONFIG_ARM
static const struct pll_params_table c1_gp_pll_params_table[] = {
	PLL_PARAMS(99, 2, 0), /* DCO = 1188M */
	{ /* sentinel */ }
};
#else
static const struct pll_params_table c1_gp_pll_params_table[] = {
	PLL_PARAMS(99, 2), /* DCO = 1188M */
	{ /* sentinel */ }
};
#endif

static const struct reg_sequence c1_gp_init_regs[] = {
	{ .reg = ANACTRL_GPPLL_CTRL1,	.def = 0x01800000 },
	{ .reg = ANACTRL_GPPLL_CTRL2,	.def = 0x00001100 },
	{ .reg = ANACTRL_GPPLL_CTRL3,	.def = 0x10022300 },
	{ .reg = ANACTRL_GPPLL_CTRL4,	.def = 0x00300000 },
	{ .reg = ANACTRL_GPPLL_CTRL5,   .def = 0x00080000 },
	{ .reg = ANACTRL_GPPLL_CTRL0,   .def = 0x01f18000 },
	{ .reg = ANACTRL_GPPLL_CTRL0,   .def = 0x11f18000, .delay_us = 10 },
	{ .reg = ANACTRL_GPPLL_CTRL0,	.def = 0x15f18000, .delay_us = 40 },
	{ .reg = ANACTRL_GPPLL_CTRL2,	.def = 0x00001120, .delay_us = 10 },
//	{ .reg = ANACTRL_GPPLL_CTRL2,	.def = 0x00001100 },
};

/*
 * hifi pll = 1188M
 */
static struct clk_regmap c1_gp_pll = {
	.data = &(struct meson_clk_pll_data){
		.en = {
			.reg_off = ANACTRL_GPPLL_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.m = {
			.reg_off = ANACTRL_GPPLL_CTRL0,
			.shift   = 0,
			.width   = 8,
		},
		.n = {
			.reg_off = ANACTRL_GPPLL_CTRL0,
			.shift   = 10,
			.width   = 5,
		},
		/*
		.frac = {
			.reg_off = ANACTRL_GPPLL_CTRL1,
			.shift   = 0,
			.width   = 19,
		},
		*/
		.l = {
			.reg_off = ANACTRL_GPPLL_STS,
			.shift   = 31,
			.width   = 1,
		},
		.table = c1_gp_pll_params_table,
		.init_regs = c1_gp_init_regs,
		.init_count = ARRAY_SIZE(c1_gp_init_regs),
	},
	.hw.init = &(struct clk_init_data){
		.name = "gp_pll",
		.ops = &meson_c1_clk_pll_ops,
		.parent_names = (const char *[]){ "xtal_gppll" },
		.num_parents = 1,
	},
};

static struct clk_fixed_factor c1_gp_pll_div1_fix_div2 = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data){
		.name = "c1_gp_pll_div1_fix_div2",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "gp_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_gp_pll_div1 = {
	.data = &(struct clk_regmap_div_data){
		.offset = ANACTRL_GPPLL_CTRL5,
		.shift = 0,
		.width = 5,
		.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
	},
	.hw.init = &(struct clk_init_data){
		.name = "c1_gp_pll_div1",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "c1_gp_pll_div1_fix_div2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_gp_pll_div1_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = FCLK_DIV1_SEL,
		.bit_idx = 7,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "c1_gp_pll_div1_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "c1_gp_pll_div1" },
		.num_parents = 1,
		/*
		 * add CLK_IGNORE_UNUSED to avoid fixed pll disable
		 * by clk core or enable it in clock driver.
		 * disable fixed_pll_div2_gate-->disable fixed pll
		 */
		.flags = CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
	},
};

static struct clk_fixed_factor c1_gp_pll_div2_fix_div2 = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data){
		.name = "c1_gp_pll_div2_fix_div2",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "gp_pll" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_gp_pll_div2 = {
	.data = &(struct clk_regmap_div_data){
		.offset = ANACTRL_GPPLL_CTRL5,
		.shift = 8,
		.width = 5,
		.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
	},
	.hw.init = &(struct clk_init_data){
		.name = "c1_gp_pll_div2",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "c1_gp_pll_div2_fix_div2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_gp_pll_div2_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = FCLK_DIV1_SEL,
		.bit_idx = 15,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "c1_gp_pll_div2_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "c1_gp_pll_div2" },
		.num_parents = 1,
		/*
		 * add CLK_IGNORE_UNUSED to avoid fixed pll disable
		 * by clk core or enable it in clock driver.
		 * disable fixed_pll_div2_gate-->disable fixed pll
		 */
		.flags = CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_gp_pll_div3 = {
	.data = &(struct clk_regmap_div_data){
		.offset = ANACTRL_GPPLL_CTRL5,
		.shift = 16,
		.width = 2,
		.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
	},
	.hw.init = &(struct clk_init_data){
		.name = "c1_gp_pll_div3",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "gp_pll" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_gp_pll_div3_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = FCLK_DIV1_SEL,
		.bit_idx = 19,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "c1_gp_pll_div3_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "c1_gp_pll_div3" },
		.num_parents = 1,
		/*
		 * add CLK_IGNORE_UNUSED to avoid fixed pll disable
		 * by clk core or enable it in clock driver.
		 * disable fixed_pll_div2_gate-->disable fixed pll
		 */
		.flags = CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
	},
};

/* 614.4M */
static const struct reg_sequence c1_hifi_init_regs[] = {
	{ .reg = ANACTRL_HIFIPLL_CTRL1,	.def = 0x01800000 },
	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00001120 },
	{ .reg = ANACTRL_HIFIPLL_CTRL3,	.def = 0x10022200 },
	{ .reg = ANACTRL_HIFIPLL_CTRL4,	.def = 0x00301000 },
	{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f19480 },
	{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x11f19480, .delay_us = 10 },
	{ .reg = ANACTRL_HIFIPLL_CTRL0,	.def = 0x15f11480, .delay_us = 40 },
	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00001160 },
	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00001120 },
};

/* 1467.648M */
static const struct reg_sequence c1_hifi_init_regs1[] = {
	{ .reg = ANACTRL_HIFIPLL_CTRL1,	.def = 0x0f904dd3 },
	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00001120 },
	{ .reg = ANACTRL_HIFIPLL_CTRL3,	.def = 0x100a1100 },
	{ .reg = ANACTRL_HIFIPLL_CTRL4,	.def = 0x00301000 },
	{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f1843d },
	{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x11f1843d, .delay_us = 10 },
	{ .reg = ANACTRL_HIFIPLL_CTRL0,	.def = 0x15f1843d, .delay_us = 40 },
	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00001160 },
	{ .reg = ANACTRL_HIFIPLL_CTRL2,	.def = 0x00001120 },
};

#ifdef CONFIG_ARM
static const struct pll_params_table c1_hifi_pll_params_table[] = {
	{ .m = 128, .n = 4, .od = 0, .regs = c1_hifi_init_regs,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs)},  /*DCO = 768M */
	{ .m = 213, .n = 8, .od = 0, .regs = c1_hifi_init_regs,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs)},  /*DCO = 639M */
	{ .m = 128, .n = 5, .od = 0, .regs = c1_hifi_init_regs,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs)},  /*DCO = 614.4M */
	{ .m = 61, .n = 1, .od = 0, .regs = c1_hifi_init_regs1,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs1)},  /*DCO = 1467.648M */
};
#else
static const struct pll_params_table c1_hifi_pll_params_table[] = {
	{ .m = 128, .n = 4, .regs = c1_hifi_init_regs,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs)},  /*DCO = 768M */
	{ .m = 213, .n = 8, .regs = c1_hifi_init_regs,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs)},  /*DCO = 639M */
	{ .m = 128, .n = 5, .regs = c1_hifi_init_regs,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs)},  /*DCO = 614.4M */
	{ .m = 61, .n = 1,  .regs = c1_hifi_init_regs1,
	  .regs_count = ARRAY_SIZE(c1_hifi_init_regs1)},  /*DCO = 1467.648M */
};
#endif

static struct clk_regmap c1_hifi_pll = {
	.data = &(struct meson_clk_pll_data){
		.en = {
			.reg_off = ANACTRL_HIFIPLL_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.m = {
			.reg_off = ANACTRL_HIFIPLL_CTRL0,
			.shift   = 0,
			.width   = 8,
		},
		.n = {
			.reg_off = ANACTRL_HIFIPLL_CTRL0,
			.shift   = 10,
			.width   = 5,
		},
		.frac = {
			.reg_off = ANACTRL_HIFIPLL_CTRL1,
			.shift   = 0,
			.width   = 19,
		},
		.l = {
			.reg_off = ANACTRL_HIFIPLL_STS,
			.shift   = 31,
			.width   = 1,
		},
		.table = c1_hifi_pll_params_table,
	},
	.hw.init = &(struct clk_init_data){
		.name = "hifi_pll",
		.ops = &meson_c1_clk_hifi_pll_ops,
		.parent_names = (const char *[]){ "xtal_hifipll" },
		.num_parents = 1,
	},
};

/*
 * Internal sys pll emulation configuration parameters
 */
static const struct reg_sequence c1_sys_init_regs[] = {
	{ .reg = ANACTRL_SYSPLL_CTRL1,	.def = 0x01800000 },
	{ .reg = ANACTRL_SYSPLL_CTRL2,	.def = 0x00001100 },
	{ .reg = ANACTRL_SYSPLL_CTRL3,	.def = 0x10022300 },
	{ .reg = ANACTRL_SYSPLL_CTRL4,	.def = 0x00300000 },
	{ .reg = ANACTRL_SYSPLL_CTRL0,  .def = 0x01f18000 },
	{ .reg = ANACTRL_SYSPLL_CTRL0,  .def = 0x11f18000, .delay_us = 10 },
	{ .reg = ANACTRL_SYSPLL_CTRL0,	.def = 0x15f18000, .delay_us = 40 },
	{ .reg = ANACTRL_SYSPLL_CTRL2,	.def = 0x00001120, .delay_us = 10 },
};

/*
 * sys pll = 768M ~ 1536M
 */
static struct clk_regmap c1_sys_pll = {
	.data = &(struct meson_clk_pll_data){
		.en = {
			.reg_off = ANACTRL_SYSPLL_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.m = {
			.reg_off = ANACTRL_SYSPLL_CTRL0,
			.shift   = 0,
			.width   = 8,
		},
		.n = {
			.reg_off = ANACTRL_SYSPLL_CTRL0,
			.shift   = 10,
			.width   = 5,
		},
		.l = {
			.reg_off = ANACTRL_SYSPLL_STS,
			.shift   = 31,
			.width   = 1,
		},
		.table = c1_pll_params_table,
		.init_regs = c1_sys_init_regs,
		.init_count = ARRAY_SIZE(c1_sys_init_regs),
	},
	.hw.init = &(struct clk_init_data){
		.name = "sys_pll",
		.ops = &meson_c1_clk_pll_ops,
		.parent_names = (const char *[]){ "c1_ee_core" },
		.num_parents = 1,
		.flags = CLK_IGNORE_UNUSED,
	},
};

/* 24.567M */
static const struct reg_sequence c1_aud_dds_init_regs[] = {
	{ .reg = ANACTRL_MISCTOP_CTRL0,	.def = 0x4, .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL0,	.def = 0x50021340, .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL1,	.def = 0x0,	   .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL2,	.def = 0x0,	   .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL3,	.def = 0x4f79, .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL4,  .def = 0x3e8, .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL0,  .def = 0x60041f40, .delay_us = 20 },
	{ .reg = ANACTRL_AUDDDS_CTRL1,	.def = 0x80000000, .delay_us = 20 },
};

/*
 * aud dds clock is not pll clock, not divider clock,
 * No clock model can describe it.
 * So we regard it as a gate, and the gate ops
 * should realize lonely.
 */
static struct clk_regmap c1_aud_dds = {
	.data = &(struct clk_regmap_reg_gate_data){
		.offset = ANACTRL_AUDDDS_CTRL0,
		.have_gate = 1,
		.bit_idx = 30,
		.init_regs = c1_aud_dds_init_regs,
		.init_count = ARRAY_SIZE(c1_aud_dds_init_regs),
	},
	.hw.init = &(struct clk_init_data) {
		.name = "aud_dds",
		.ops = &clk_regmap_reg_gate_ops,
		.parent_names = (const char *[]){ "xtal_dds" },
		.num_parents = 1,
		.flags =  CLK_IGNORE_UNUSED,
	},
};

/* sys clk = 64M */
static u32 mux_table_sys_ab_clk_sel[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static const char * const sys_ab_clk_parent_names[] = {
	"c1_ee_core", "fclk_div2", "fclk_div3", "fclk_div5",
	"fclk_div4", "axi_clk_frcpu", "fclk_div7", "rtc_clk"
};

static struct clk_regmap c1_sys_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SYS_CLK_CTRL0,
		.mask = 0x7,
		.shift = 26,
		.table = mux_table_sys_ab_clk_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sys_b_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = sys_ab_clk_parent_names,
		.num_parents = ARRAY_SIZE(sys_ab_clk_parent_names),
	},
};

static struct clk_regmap c1_sys_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SYS_CLK_CTRL0,
		.shift = 16,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sys_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "sys_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_sys_b = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SYS_CLK_CTRL0,
		.bit_idx = 29,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "sys_b",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "sys_b_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED
			 | CLK_IS_CRITICAL,
	},
};

static struct clk_regmap c1_sys_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SYS_CLK_CTRL0,
		.mask = 0x7,
		.shift = 10,
		.table = mux_table_sys_ab_clk_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sys_a_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = sys_ab_clk_parent_names,
		.num_parents = ARRAY_SIZE(sys_ab_clk_parent_names),
	},
};

static struct clk_regmap c1_sys_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SYS_CLK_CTRL0,
		.shift = 0,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sys_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "sys_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_sys_a = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SYS_CLK_CTRL0,
		.bit_idx = 13,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "sys_a",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "sys_a_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED
			 | CLK_IS_CRITICAL,
	},
};

static const char * const sys_clk_parent_names[] = {
	"sys_a", "sys_b"};

static struct clk_regmap c1_sys_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SYS_CLK_CTRL0,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sys_clk",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = sys_clk_parent_names,
		.num_parents = ARRAY_SIZE(sys_clk_parent_names),
	},
};

static u32 mux_table_axi_ab_clk_sel[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static const char * const axi_ab_clk_parent_names[] = {
	"c1_ee_core", "fclk_div2", "fclk_div3", "fclk_div5",
	"fclk_div4", "axi_clk_frcpu", "fclk_div7", "rtc_clk"
};

static struct clk_regmap axi_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = AXI_CLK_CTRL0,
		.mask = 0x7,
		.shift = 26,
		.table = mux_table_axi_ab_clk_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "axi_b_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = axi_ab_clk_parent_names,
		.num_parents = ARRAY_SIZE(axi_ab_clk_parent_names),
	},
};

static struct clk_regmap axi_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = AXI_CLK_CTRL0,
		.shift = 16,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "axi_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "axi_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap axi_b = {
	.data = &(struct clk_regmap_gate_data){
		.offset = AXI_CLK_CTRL0,
		.bit_idx = 29,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "axi_b",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "axi_b_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap axi_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = AXI_CLK_CTRL0,
		.mask = 0x7,
		.shift = 10,
		.table = mux_table_sys_ab_clk_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "axi_a_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = axi_ab_clk_parent_names,
		.num_parents = ARRAY_SIZE(axi_ab_clk_parent_names),
	},
};

static struct clk_regmap axi_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = AXI_CLK_CTRL0,
		.shift = 0,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "axi_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "axi_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap axi_a = {
	.data = &(struct clk_regmap_gate_data){
		.offset = AXI_CLK_CTRL0,
		.bit_idx = 13,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "axi_a",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "axi_a_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static const char * const axi_clk_parent_names[] = {
	"axi_a", "axi_b"};

static struct clk_regmap axi_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = AXI_CLK_CTRL0,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "axi_clk",
		.ops = &clk_regmap_mux_ro_ops,
		.parent_names = axi_clk_parent_names,
		.num_parents = ARRAY_SIZE(axi_clk_parent_names),
	},
};

/* dsp a clk */
static u32 mux_table_dspab_sel[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static const char * const dspab_parent_names[] = {
	"c1_ee_core", "fclk_div2", "fclk_div3", "fclk_div5",
	"hifi_pll", "fclk_div4", "fclk_div7", "rtc_clk"
};

static struct clk_regmap c1_dspa_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = DSPA_CLK_CTRL0,
		.mask = 0x7,
		.shift = 10,
		.table = mux_table_dspab_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspa_a_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = dspab_parent_names,
		.num_parents = ARRAY_SIZE(dspab_parent_names),
	},
};

static struct clk_regmap c1_dspa_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = DSPA_CLK_CTRL0,
		.shift = 0,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspa_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dspa_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_dspa_a = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPA_CLK_CTRL0,
		.bit_idx = 13,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspa_a",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspa_a_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap c1_dspa_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = DSPA_CLK_CTRL0,
		.mask = 0x7,
		.shift = 26,
		.table = mux_table_dspab_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspa_b_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = dspab_parent_names,
		.num_parents = ARRAY_SIZE(dspab_parent_names),
	},
};

static struct clk_regmap c1_dspa_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = DSPA_CLK_CTRL0,
		.shift = 16,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspa_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dspa_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_dspa_b = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPA_CLK_CTRL0,
		.bit_idx = 29,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspa_b",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspa_b_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static const char * const dspa_parent_names[] = {
	"dspa_a", "dspa_b"
};

static struct clk_regmap c1_dspa_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = DSPA_CLK_CTRL0,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspa_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = dspa_parent_names,
		.num_parents = ARRAY_SIZE(dspa_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_dspa_en_dspa = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPA_CLK_EN,
		.bit_idx = 1,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspa_en_dspa",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspa_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap c1_dspa_en_nic = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPA_CLK_EN,
		.bit_idx = 0,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspa_en_nic",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspa_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

/* dsp b clk */
static struct clk_regmap c1_dspb_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = DSPB_CLK_CTRL0,
		.mask = 0x7,
		.shift = 10,
		.table = mux_table_dspab_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspb_a_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = dspab_parent_names,
		.num_parents = ARRAY_SIZE(dspab_parent_names),
	},
};

static struct clk_regmap c1_dspb_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = DSPB_CLK_CTRL0,
		.shift = 0,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspb_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dspb_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_dspb_a = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPB_CLK_CTRL0,
		.bit_idx = 13,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspb_a",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspb_a_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap c1_dspb_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = DSPB_CLK_CTRL0,
		.mask = 0x7,
		.shift = 26,
		.table = mux_table_dspab_sel,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspb_b_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = dspab_parent_names,
		.num_parents = ARRAY_SIZE(dspab_parent_names),
	},
};

static struct clk_regmap c1_dspb_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = DSPB_CLK_CTRL0,
		.shift = 16,
		.width = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspb_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dspb_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_dspb_b = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPB_CLK_CTRL0,
		.bit_idx = 29,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspb_b",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspb_b_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static const char * const dspb_parent_names[] = {
	"dspb_a", "dspb_b"};

static struct clk_regmap c1_dspb_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = DSPB_CLK_CTRL0,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dspb_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = dspb_parent_names,
		.num_parents = ARRAY_SIZE(dspb_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_dspb_en_dspb = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPB_CLK_EN,
		.bit_idx = 1,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspb_en_dspb",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspb_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap c1_dspb_en_nic = {
	.data = &(struct clk_regmap_gate_data){
		.offset = DSPB_CLK_EN,
		.bit_idx = 0,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dspb_en_nic",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "dspb_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

/* 12M/24M clock */
static struct clk_regmap c1_24m = {
	.data = &(struct clk_regmap_gate_data){
		.offset = CLK12_24_CTRL,
		.bit_idx = 11,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "24m",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "c1_ee_core" },
		.num_parents = 1,
	},
};

static struct clk_fixed_factor c1_24m_div2 = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data){
		.name = "24m_div2",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "24m" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_12m = {
	.data = &(struct clk_regmap_gate_data){
		.offset = CLK12_24_CTRL,
		.bit_idx = 10,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "12m",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "24m_div2" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div2_divn_pre = {
	.data = &(struct clk_regmap_div_data){
		.offset = CLK12_24_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div2_divn_pre",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "fclk_div2" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_fclk_div2_divn = {
	.data = &(struct clk_regmap_gate_data){
		.offset = CLK12_24_CTRL,
		.bit_idx = 12,
	},
	.hw.init = &(struct clk_init_data){
		.name = "fclk_div2_divn",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div2_divn_pre" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* gen clk */
static const char * const gen_parent_names[] = {
	"c1_ee_core", "rtc_clk", "sys_pll_div16", "hifi",
	"clk_msr_src", "fclk_div2", "fclk_div3", "fclk_div5",
	"fclk_div7", "gp_pll", "fclk_div2p5", "fclk_div4",
	"sys_clk", "axi_clk"
};

static struct clk_regmap c1_gen_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GEN_CLK_CTRL,
		.mask = 0xf,
		.shift = 12,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gen_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gen_parent_names,
		.num_parents = ARRAY_SIZE(gen_parent_names),
	},
};

static struct clk_regmap c1_gen_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = GEN_CLK_CTRL,
		.shift = 0,
		.width = 11,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gen_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "gen_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_gen = {
	.data = &(struct clk_regmap_gate_data){
		.offset = GEN_CLK_CTRL,
		.bit_idx = 11,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "gen",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "gen_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const saradc_parent_names[] = {
	"xtal", "sys_clk"
};

static struct clk_regmap c1_saradc_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SAR_ADC_CLK_CTRL,
		/*
		 * bit9 and bit10 to select parent
		 * no clock for third and forth parent
		 * So mask is 0x1.
		 */
		.mask = 0x1,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "saradc_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = saradc_parent_names,
		.num_parents = ARRAY_SIZE(saradc_parent_names),
	},
};

static struct clk_regmap c1_saradc_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SAR_ADC_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "saradc_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "saradc_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_saradc_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SAR_ADC_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "saradc_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "saradc_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const pwm_parent_names[] = {
	"c1_ee_core", "sys_clk", "rtc_clk", "fclk_div4"
};

/*
 * add CLK_IGNORE_UNUSED flag for pwm controller GATE
 * clk core will disable unused clock, it may disable
 * vddcore voltage which contrlled by one pwm in bl21.
 * add the flag to avoid changing cpu voltage.
 */
#define MESON_C1_PWM_SEL(_name, _reg, _mask, _shift)			\
struct clk_regmap _name = {						\
	.data = &(struct clk_regmap_mux_data) {				\
		.offset = (_reg),					\
		.mask = (_mask),					\
		.shift = (_shift),					\
	},								\
	.hw.init = &(struct clk_init_data) {				\
		.name = #_name,						\
		.ops = &clk_regmap_mux_ops,				\
		.parent_names = pwm_parent_names,			\
		.num_parents =  ARRAY_SIZE(pwm_parent_names),		\
		.flags = CLK_IGNORE_UNUSED,				\
	},								\
}

#define MESON_C1_PWM_DIV(_name, _reg, _shift, _width, _parent) \
struct clk_regmap _name = {						\
	.data = &(struct clk_regmap_div_data) {				\
		.offset = (_reg),					\
		.shift = (_shift),					\
		.width = (_width),					\
	},								\
	.hw.init = &(struct clk_init_data) {				\
		.name = #_name,						\
		.ops = &clk_regmap_divider_ops,				\
		.parent_names = (const char *[]){ #_parent }, \
		.num_parents =  1,		\
		.flags = CLK_SET_RATE_PARENT,				\
	},								\
}

#define MESON_C1_PWM_GATE(_name, _reg, _bit, _parent)			\
struct clk_regmap _name = {						\
	.data = &(struct clk_regmap_gate_data){				\
		.offset = (_reg),					\
		.bit_idx = (_bit),					\
	},								\
	.hw.init = &(struct clk_init_data) {				\
		.name = #_name,						\
		.ops = &clk_regmap_gate_ops,				\
		.parent_names = (const char *[]){ #_parent },		\
		.num_parents = 1,					\
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,	\
	},								\
}

MESON_C1_PWM_SEL(pwm_a_sel, PWM_CLK_AB_CTRL, 0x3, 9);
MESON_C1_PWM_DIV(pwm_a_div, PWM_CLK_AB_CTRL, 0, 8, pwm_a_sel);
MESON_C1_PWM_GATE(pwm_a, PWM_CLK_AB_CTRL, 8, pwm_a_div);
MESON_C1_PWM_SEL(pwm_b_sel, PWM_CLK_AB_CTRL, 0x3, 25);
MESON_C1_PWM_DIV(pwm_b_div, PWM_CLK_AB_CTRL, 16, 8, pwm_b_sel);
MESON_C1_PWM_GATE(pwm_b, PWM_CLK_AB_CTRL, 24, pwm_b_div);
MESON_C1_PWM_SEL(pwm_c_sel, PWM_CLK_CD_CTRL, 0x3, 9);
MESON_C1_PWM_DIV(pwm_c_div, PWM_CLK_CD_CTRL, 0, 8, pwm_c_sel);
MESON_C1_PWM_GATE(pwm_c, PWM_CLK_CD_CTRL, 8, pwm_c_div);
MESON_C1_PWM_SEL(pwm_d_sel, PWM_CLK_CD_CTRL, 0x3, 25);
MESON_C1_PWM_DIV(pwm_d_div, PWM_CLK_CD_CTRL, 16, 8, pwm_d_sel);
MESON_C1_PWM_GATE(pwm_d, PWM_CLK_CD_CTRL, 24, pwm_d_div);
MESON_C1_PWM_SEL(pwm_e_sel, PWM_CLK_EF_CTRL, 0x3, 9);
MESON_C1_PWM_DIV(pwm_e_div, PWM_CLK_EF_CTRL, 0, 8, pwm_e_sel);
MESON_C1_PWM_GATE(pwm_e, PWM_CLK_EF_CTRL, 8, pwm_e_div);
MESON_C1_PWM_SEL(pwm_f_sel, PWM_CLK_EF_CTRL, 0x3, 25);
MESON_C1_PWM_DIV(pwm_f_div, PWM_CLK_EF_CTRL, 16, 8, pwm_f_sel);
MESON_C1_PWM_GATE(pwm_f, PWM_CLK_EF_CTRL, 24, pwm_f_div);
MESON_C1_PWM_SEL(pwm_g_sel, PWM_CLK_GH_CTRL, 0x3, 9);
MESON_C1_PWM_DIV(pwm_g_div, PWM_CLK_GH_CTRL, 0, 8, pwm_g_sel);
MESON_C1_PWM_GATE(pwm_g, PWM_CLK_GH_CTRL, 8, pwm_g_div);
MESON_C1_PWM_SEL(pwm_h_sel, PWM_CLK_GH_CTRL, 0x3, 25);
MESON_C1_PWM_DIV(pwm_h_div, PWM_CLK_GH_CTRL, 16, 8, pwm_h_sel);
MESON_C1_PWM_GATE(pwm_h, PWM_CLK_GH_CTRL, 24, pwm_h_div);
MESON_C1_PWM_SEL(pwm_i_sel, PWM_CLK_IJ_CTRL, 0x3, 9);
MESON_C1_PWM_DIV(pwm_i_div, PWM_CLK_IJ_CTRL, 0, 8, pwm_i_sel);
MESON_C1_PWM_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8, pwm_i_div);
MESON_C1_PWM_SEL(pwm_j_sel, PWM_CLK_IJ_CTRL, 0x3, 25);
MESON_C1_PWM_DIV(pwm_j_div, PWM_CLK_IJ_CTRL, 16, 8, pwm_j_sel);
MESON_C1_PWM_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24, pwm_j_div);

/* spicc clk */

/*    div2   |\         |\       _____
 *  ---------| |---DIV--| |     |     |    spicc out
 *  ---------| |        | |-----| GATE|---------
 *     ..... |/         | /     |_____|
 *  --------------------|/
 *                 24M
 */
static const char * const spicc_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap c1_spicc_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SPICC_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spicc_a_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = spicc_parent_names,
		.num_parents = ARRAY_SIZE(spicc_parent_names),
	},
};

static struct clk_regmap c1_spicc_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SPICC_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spicc_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "spicc_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spicc_a = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SPICC_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spicc_a_mux",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "spicc_a_div", "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spicc_a_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SPICC_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "spicc_a_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "spicc_a_mux" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spicc_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SPICC_CLK_CTRL,
		.mask = 0x7,
		.shift = 25,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spicc_b_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = spicc_parent_names,
		.num_parents = ARRAY_SIZE(spicc_parent_names),
	},
};

static struct clk_regmap c1_spicc_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SPICC_CLK_CTRL,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spicc_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "spicc_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spicc_b = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SPICC_CLK_CTRL,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spicc_b_mux",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "spicc_b_div", "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spicc_b_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SPICC_CLK_CTRL,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "spicc_b_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "spicc_b_mux" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* ts clk */
static struct clk_regmap c1_ts_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = TS_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "ts_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "c1_ee_core" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_ts = {
	.data = &(struct clk_regmap_gate_data){
		.offset = TS_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "ts",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "ts_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* spifc clk */
static const char * const spifc_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap c1_spifc_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SPIFC_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spifc_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = spifc_parent_names,
		.num_parents = ARRAY_SIZE(spifc_parent_names),
	},
};

static struct clk_regmap c1_spifc_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SPIFC_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spifc_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "spifc_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spifc = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SPIFC_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "spifc_mux",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "spifc_div", "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_spifc_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SPIFC_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "spifc_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "spifc_mux" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* usb bus clk */
static const char * const usb_bus_parent_names[] = {
	"c1_ee_core", "sys_clk", "fclk_div3", "fclk_div5"
};

static struct clk_regmap c1_usb_bus_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = USB_BUSCLK_CTRL,
		.mask = 0x3,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "usb_bus_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = usb_bus_parent_names,
		.num_parents = ARRAY_SIZE(usb_bus_parent_names),
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap c1_usb_bus_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = USB_BUSCLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "usb_bus_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "usb_bus_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap c1_usb_bus = {
	.data = &(struct clk_regmap_gate_data){
		.offset = USB_BUSCLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "usb_bus",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "usb_bus_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

/* sd emmc clk */
static u32 mux_table_sd_emmc[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
/* delete the forth parent : hifi_pll
 * hifi pll only work for Audio
 */
static const char * const sd_emmc_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap sd_emmc_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SD_EMMC_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
		.table = mux_table_sd_emmc,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_a_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = sd_emmc_parent_names,
		.num_parents = ARRAY_SIZE(sd_emmc_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SD_EMMC_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "sd_emmc_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_a = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SD_EMMC_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_a",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "sd_emmc_a_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_a_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SD_EMMC_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "sd_emmc_a_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "sd_emmc_a" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SD_EMMC_CLK_CTRL,
		.mask = 0x7,
		.shift = 25,
		.table = mux_table_sd_emmc,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_b_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = sd_emmc_parent_names,
		.num_parents = ARRAY_SIZE(sd_emmc_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SD_EMMC_CLK_CTRL,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "sd_emmc_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_b = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SD_EMMC_CLK_CTRL,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_b",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "sd_emmc_b_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_b_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SD_EMMC_CLK_CTRL,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "sd_emmc_b_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "sd_emmc_b" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_c_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SD_EMMC_CLK_CTRL1,
		.mask = 0x7,
		.shift = 9,
		.table = mux_table_sd_emmc,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_c_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = sd_emmc_parent_names,
		.num_parents = ARRAY_SIZE(sd_emmc_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_c_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = SD_EMMC_CLK_CTRL1,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_c_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "sd_emmc_c_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_c = {
	.data = &(struct clk_regmap_mux_data){
		.offset = SD_EMMC_CLK_CTRL1,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "sd_emmc_c",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "sd_emmc_c_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap sd_emmc_c_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SD_EMMC_CLK_CTRL1,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "sd_emmc_c_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "sd_emmc_c" },
		.flags = CLK_SET_RATE_PARENT,
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/*
 * change fixed pll 1536M to 768M
 */
static struct clk_regmap c1_fixed_pll_div2_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = FCLK_DIV1_SEL,
		.bit_idx = 0,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "fixed_pll_div2_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fixed_pll" },
		.num_parents = 1,
		/*
		 * add CLK_IGNORE_UNUSED to avoid fixed pll disable
		 * by clk core or enable it in clock driver.
		 * disable fixed_pll_div2_gate-->disable fixed pll
		 */
		.flags = CLK_IGNORE_UNUSED,
	},
};

/*
 *rtc 32k clock
 *
 *xtal--GATE------------------GATE---------------------|\
 *	              |  --------                      | \
 *	              |  |      |                      |  \
 *	              ---| DUAL |----------------------|   |
 *	                 |      |                      |   |____GATE__
 *	                 --------                      |   |     rtc_32k_out
 *	   PAD-----------------------------------------|  /
 *	                                               | /
 *	   DUAL function:                              |/
 *	   bit 28 in RTC_BY_OSCIN_CTRL0 control the dual function.
 *	   when bit 28 = 0
 *	         f = 24M/N0
 *	   when bit 28 = 1
 *	         output N1 and N2 in rurn.
 *	   T = (x*T1 + y*T2)/x+y
 *	   f = (24M/(N0*M0 + N1*M1)) * (M0 + M1)
 *	   f: the frequecy value (HZ)
 *	       |      | |      |
 *	       | Div1 |-| Cnt1 |
 *	      /|______| |______|\
 *	    -|  ______   ______  ---> Out
 *	      \|      | |      |/
 *	       | Div2 |-| Cnt2 |
 *	       |______| |______|
 **/

/*
 * rtc 32k clock in gate
 */
static struct clk_regmap c1_rtc_32k_clkin = {
	.data = &(struct clk_regmap_gate_data){
		.offset = RTC_BY_OSCIN_CTRL0,
		.bit_idx = 31,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_32k_clkin",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "c1_ee_core" },
		.num_parents = 1,
	},
};

static const struct meson_clk_dualdiv_param c1_32k_div_table[] = {
	{
		.dual	= 1,
		.n1		= 733,
		.m1		= 8,
		.n2		= 732,
		.m2		= 11,
	}, {}
};

static struct clk_regmap c1_rtc_32k_div = {
	.data = &(struct meson_clk_dualdiv_data){
		.n1 = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 0,
			.width   = 12,
		},
		.n2 = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 12,
			.width   = 12,
		},
		.m1 = {
			.reg_off = RTC_BY_OSCIN_CTRL1,
			.shift   = 0,
			.width   = 12,
		},
		.m2 = {
			.reg_off = RTC_BY_OSCIN_CTRL1,
			.shift   = 12,
			.width   = 12,
		},
		.dual = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.table = c1_32k_div_table,
	},
	.hw.init = &(struct clk_init_data){
		.name = "rtc_32k_div",
		.ops = &meson_clk_dualdiv_ops,
		.parent_names = (const char *[]){ "rtc_32k_clkin" },
		.num_parents = 1,
	},
};

static struct clk_regmap c1_rtc_32k_xtal = {
	.data = &(struct clk_regmap_gate_data){
		.offset = RTC_BY_OSCIN_CTRL1,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_32k_xtal",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "rtc_32k_clkin" },
		.num_parents = 1,
	},
};

/*
 *static struct clk_regmap c1_rtc_32k_sel = {
 *	.data = &(struct clk_regmap_mux_data) {
 *		.offset = RTC_BY_OSCIN_CTRL1,
 *		.mask = 0x1,
 *		.shift = 24,
 *		.flags = CLK_MUX_ROUND_CLOSEST,
 *	},
 *	.hw.init = &(struct clk_init_data){
 *		.name = "rtc_32k_sel",
 *		.ops = &clk_regmap_mux_ops,
 *		.parent_names = (const char *[]){ "rtc_32k_div",
 *						  "rtc_32k_clkin" },
 *		.num_parents = 2,
 *		.flags = CLK_SET_RATE_PARENT,
 *	},
 *};
 */

/*
 * three parent for rtc clock out
 * pad is from where?
 */
static u32 rtc_32k_sel[] = { 0, 1, 2 };
static const char * const rtc_32k_sel_parent_names[] = {
	"rtc_32k_xtal", "rtc_32k_div", "pad"
};

static struct clk_regmap c1_rtc_32k_sel = {
	.data = &(struct clk_regmap_mux_data) {
		.offset = RTC_CTRL,
		.mask = 0x3,
		.shift = 0,
		.table = rtc_32k_sel,
		.flags = CLK_MUX_ROUND_CLOSEST,
	},
	.hw.init = &(struct clk_init_data){
		.name = "rtc_32k_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = rtc_32k_sel_parent_names,
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_rtc_clk = {
	.data = &(struct clk_regmap_gate_data){
		.offset = RTC_BY_OSCIN_CTRL0,
		.bit_idx = 30,
	},
	.hw.init = &(struct clk_init_data){
		.name = "rtc_clk",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "rtc_32k_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static u32 cpu_fixed_source_sel_table[]	= { 0, 1, 2 };

static const char * const cpu_fixed_source_sel_parent_names[] = {
	"c1_ee_core", "fclk_div2", "fclk_div3"
};

/* cpu_fixed_sel0 */
static struct clk_regmap c1_cpu_fixed_source_sel0 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.mask = 0x3,
		.shift = 0,
		.table = cpu_fixed_source_sel_table,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cpu_fixed_source_sel0",
		.ops = &clk_regmap_mux_ops,
		.parent_names = cpu_fixed_source_sel_parent_names,
		.num_parents = ARRAY_SIZE(cpu_fixed_source_sel_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_cpu_fixed_source_div0 = {
	.data = &(struct clk_regmap_div_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.shift = 4,
		.width = 6,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "cpu_fixed_source_div0",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "cpu_fixed_source_sel0" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_cpu_fixed_sel0 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.mask = 0x1,
		.shift = 2,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cpu_fixed_sel0",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "cpu_fixed_source_sel0",
						"cpu_fixed_source_div0" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* cpu_fixed_sel1 */
static struct clk_regmap c1_cpu_fixed_source_sel1 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.mask = 0x3,
		.shift = 16,
		.table = cpu_fixed_source_sel_table,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cpu_fixed_source_sel1",
		.ops = &clk_regmap_mux_ops,
		.parent_names = cpu_fixed_source_sel_parent_names,
		.num_parents = ARRAY_SIZE(cpu_fixed_source_sel_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_cpu_fixed_source_div1 = {
	.data = &(struct clk_regmap_div_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.shift = 20,
		.width = 6,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "cpu_fixed_source_div1",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "cpu_fixed_source_sel1" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap c1_cpu_fixed_sel1 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.mask = 0x1,
		.shift = 18,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cpu_fixed_sel1",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "cpu_fixed_source_sel1",
						"cpu_fixed_source_div1" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* cpu_fixed_clk */
static struct clk_regmap c1_cpu_fixed_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.mask = 0x1,
		.shift = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cpu_fixed_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "cpu_fixed_sel0",
						"cpu_fixed_sel1" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* cpu clocks */
/* cpu_fixed_clk |\
 *---------------| \     cts_cpu_clk
 *  sys_pll      |  |--------
 *---------------| /
 *               |/
 */

static struct clk_regmap c1_cpu_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL0,
		.mask = 0x1,
		.shift = 11,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cpu_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "cpu_fixed_clk", "sys_pll" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* dsu_sel0 */
static struct clk_regmap dsu_source_sel0 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.mask = 0x3,
		.shift = 0,
		.table = cpu_fixed_source_sel_table,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_source_sel0",
		.ops = &clk_regmap_mux_ops,
		.parent_names = cpu_fixed_source_sel_parent_names,
		.num_parents = ARRAY_SIZE(cpu_fixed_source_sel_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap dsu_source_div0 = {
	.data = &(struct clk_regmap_div_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.shift = 4,
		.width = 6,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dsu_source_div0",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dsu_source_sel0" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap dsu_fixed_sel0 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.mask = 0x1,
		.shift = 2,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_fixed_sel0",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "dsu_source_sel0",
						"dsu_source_div0" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* dsu_sel1 */
static struct clk_regmap dsu_source_sel1 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.mask = 0x3,
		.shift = 16,
		.table = cpu_fixed_source_sel_table,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_source_sel1",
		.ops = &clk_regmap_mux_ops,
		.parent_names = cpu_fixed_source_sel_parent_names,
		.num_parents = ARRAY_SIZE(cpu_fixed_source_sel_parent_names),
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap dsu_source_div1 = {
	.data = &(struct clk_regmap_div_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.shift = 20,
		.width = 6,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "dsu_source_div1",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dsu_source_sel1" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap dsu_fixed_sel1 = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.mask = 0x1,
		.shift = 18,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_fixed_sel1",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "dsu_source_sel1",
						"dsu_source_div1" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* dsu_fixed_clk */
static struct clk_regmap dsu_fixed_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.mask = 0x1,
		.shift = 10,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_fixed_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "dsu_fixed_sel0",
						"dsu_fixed_sel1" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap dsu_clk_pre = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL5,
		.mask = 0x1,
		.shift = 11,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_clk_pre",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "dsu_fixed_clk", "sys_pll" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap dsu_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = CPUCTRL_CLK_CTRL6,
		.mask = 0x1,
		.shift = 27,
	},
	.hw.init = &(struct clk_init_data){
		.name = "dsu_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "cpu_clk", "dsu_clk_pre" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap axi_clk_frcpu = {
	.data = &(struct clk_regmap_div_data){
		.offset = CPUCTRL_CLK_CTRL6,
		.shift = 4,
		.width = 3,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "axi_clk_frcpu",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "dsu_clk" },
		.num_parents = 1,
		//.flags = CLK_SET_RATE_PARENT,
	},
};

/* wave_aclk */
static const char * const wave_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap wave_a_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL0,
		.mask = 0x7,
		.shift = 25,
		.table = mux_table_sd_emmc,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_a_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = wave_parent_names,
		.num_parents = ARRAY_SIZE(wave_parent_names),
	},
};

static struct clk_regmap wave_a_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = WAVE_CLK_CTRL0,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_a_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "wave_a_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_aclk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL0,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_aclk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "wave_a_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_a_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = WAVE_CLK_CTRL0,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "wave_a_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "wave_aclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_b_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL0,
		.mask = 0x7,
		.shift = 9,
		.table = mux_table_sd_emmc,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_b_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = wave_parent_names,
		.num_parents = ARRAY_SIZE(wave_parent_names),
	},
};

static struct clk_regmap wave_b_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = WAVE_CLK_CTRL0,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_b_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "wave_b_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_bclk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL0,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_bclk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "wave_b_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_b_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = WAVE_CLK_CTRL0,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "wave_b_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "wave_bclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_c_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL1,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_c_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = wave_parent_names,
		.num_parents = ARRAY_SIZE(wave_parent_names),
	},
};

static struct clk_regmap wave_c_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = WAVE_CLK_CTRL1,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_c_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "wave_c_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_cclk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL0,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "wave_cclk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "wave_c_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap wave_c_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = WAVE_CLK_CTRL1,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "wave_c_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "wave_cclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const jpeg_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap jpeg_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = JPEG_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "jpeg_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = jpeg_parent_names,
		.num_parents = ARRAY_SIZE(jpeg_parent_names),
	},
};

static struct clk_regmap jpeg_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = JPEG_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "jpeg_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "jpeg_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap jpeg_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = WAVE_CLK_CTRL0,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "jpeg_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "jpeg_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap jpeg_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = JPEG_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "jpeg_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "jpeg_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const mipi_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap mipi_csi_phy_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.mask = 0x7,
		.shift = 25,
	},
	.hw.init = &(struct clk_init_data){
		.name = "mipi_csi_phy_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = mipi_parent_names,
		.num_parents = ARRAY_SIZE(jpeg_parent_names),
	},
};

static struct clk_regmap mipi_csi_phy_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "mipi_csi_phy_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "mipi_csi_phy_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap mipi_csi_phy_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "mipi_csi_phy_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "mipi_csi_phy_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap mipi_csi_phy_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "mipi_csi_phy_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "mipi_csi_phy_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static struct clk_regmap mipi_isp_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "mipi_isp_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = mipi_parent_names,
		.num_parents = ARRAY_SIZE(jpeg_parent_names),
	},
};

static struct clk_regmap mipi_isp_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "mipi_isp_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "mipi_isp_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap mipi_isp_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "mipi_isp_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "mipi_isp_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap mipi_isp_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = MIPI_ISP_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "mipi_isp_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "mipi_isp_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
	},
};

static const char * const nna_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap nna_axi_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = NNA_CLK_CTRL,
		.mask = 0x7,
		.shift = 25,
	},
	.hw.init = &(struct clk_init_data){
		.name = "nna_axi_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = nna_parent_names,
		.num_parents = ARRAY_SIZE(jpeg_parent_names),
	},
};

static struct clk_regmap nna_axi_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = NNA_CLK_CTRL,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "nna_axi_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "nna_axi_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap nna_axi_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = NNA_CLK_CTRL,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "nna_axi_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "nna_axi_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap nna_axi_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = NNA_CLK_CTRL,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "nna_axi_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "nna_axi_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap nna_core_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = NNA_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "nna_core_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = nna_parent_names,
		.num_parents = ARRAY_SIZE(jpeg_parent_names),
	},
};

static struct clk_regmap nna_core_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = NNA_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "nna_core_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "nna_core_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap nna_core_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = NNA_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "nna_core_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "nna_core_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap nna_core_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = NNA_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "nna_core_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "nna_core_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const gdc_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap gdc_axi_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GDC_CLK_CTRL,
		.mask = 0x7,
		.shift = 25,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gdc_axi_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gdc_parent_names,
		.num_parents = ARRAY_SIZE(jpeg_parent_names),
	},
};

static struct clk_regmap gdc_axi_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = GDC_CLK_CTRL,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gdc_axi_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "gdc_axi_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap gdc_axi_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GDC_CLK_CTRL,
		.mask = 0x1,
		.shift = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gdc_axi_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "gdc_axi_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap gdc_axi_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = GDC_CLK_CTRL,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "gdc_axi_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "gdc_axi_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap gdc_core_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GDC_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gdc_core_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gdc_parent_names,
		.num_parents = ARRAY_SIZE(gdc_parent_names),
	},
};

static struct clk_regmap gdc_core_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = GDC_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gdc_core_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "gdc_core_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap gdc_core_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GDC_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "gdc_core_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "gdc_core_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap gdc_core_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = GDC_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "gdc_core_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "gdc_core_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const ge2d_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div2p5", "hifi_pll",
	"gp_pll", "fclk_div4", "fclk_div5", "fclk_div7"
};

static struct clk_regmap ge2d_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GE2D_CLK_CTRL,
		.mask = 0x7,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "ge2d_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = ge2d_parent_names,
		.num_parents = ARRAY_SIZE(ge2d_parent_names),
	},
};

static struct clk_regmap ge2d_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = GE2D_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "ge2d_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "ge2d_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap ge2d_clk = {
	.data = &(struct clk_regmap_mux_data){
		.offset = GE2D_CLK_CTRL,
		.mask = 0x1,
		.shift = 15,
	},
	.hw.init = &(struct clk_init_data){
		.name = "ge2d_clk",
		.ops = &clk_regmap_mux_ops,
		.parent_names = (const char *[]){ "ge2d_div",
						  "c1_ee_core" },
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap ge2d_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = GE2D_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "ge2d_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "ge2d_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static const char * const eth_parent_names[] = {
	"fclk_div2", "fclk_div3", "fclk_div5", "hifi_pll"
};

static struct clk_regmap eth_clk_125_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = ETH_CLK_CTRL,
		.mask = 0x3,
		.shift = 25,
	},
	.hw.init = &(struct clk_init_data){
		.name = "eth_clk_125_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = eth_parent_names,
		.num_parents = ARRAY_SIZE(eth_parent_names),
	},
};

static struct clk_regmap eth_clk_125_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = ETH_CLK_CTRL,
		.shift = 16,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "eth_clk_125_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "eth_clk_125_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap eth_clk_125_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ETH_CLK_CTRL,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "eth_clk_125_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "eth_clk_125_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap eth_clk_rmii_sel = {
	.data = &(struct clk_regmap_mux_data){
		.offset = ETH_CLK_CTRL,
		.mask = 0x3,
		.shift = 9,
	},
	.hw.init = &(struct clk_init_data){
		.name = "eth_clk_rmii_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = eth_parent_names,
		.num_parents = ARRAY_SIZE(eth_parent_names),
	},
};

static struct clk_regmap eth_clk_rmii_div = {
	.data = &(struct clk_regmap_div_data){
		.offset = ETH_CLK_CTRL,
		.shift = 0,
		.width = 8,
	},
	.hw.init = &(struct clk_init_data){
		.name = "eth_clk_rmii_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "eth_clk_rmii_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

static struct clk_regmap eth_clk_rmii_gate = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ETH_CLK_CTRL,
		.bit_idx = 8,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "eth_clk_rmii_gate",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "eth_clk_rmii_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
	},
};

/* Array of all clocks provided by this provider */
/* Array of all clocks provided by this provider */
/* Array of all clocks provided by this provider */
static struct clk_hw_onecell_data c1_hw_onecell_data = {
	.hws = {
		[CLKID_FIXED_PLL_DCO]		= &c1_fixed_pll_dco.hw,
		[CLKID_FIXED_PLL]		= &c1_fixed_pll.hw,
		[CLKID_FCLK_DIV2]		= &c1_fclk_div2.hw,
		[CLKID_FCLK_DIV2P5]		= &c1_fclk_div2p5.hw,
		[CLKID_FCLK_DIV3]		= &c1_fclk_div3.hw,
		[CLKID_FCLK_DIV4]		= &c1_fclk_div4.hw,
		[CLKID_FCLK_DIV5]		= &c1_fclk_div5.hw,
		[CLKID_FCLK_DIV7]		= &c1_fclk_div7.hw,
		[CLKID_FCLK_DIV2_DIV]		= &c1_fclk_div2_div.hw,
		[CLKID_FCLK_DIV2P5_DIV]		= &c1_fclk_div2p5_div.hw,
		[CLKID_FCLK_DIV3_DIV]		= &c1_fclk_div3_div.hw,
		[CLKID_FCLK_DIV4_DIV]		= &c1_fclk_div4_div.hw,
		[CLKID_FCLK_DIV5_DIV]		= &c1_fclk_div5_div.hw,
		[CLKID_FCLK_DIV7_DIV]		= &c1_fclk_div7_div.hw,
		[CLKID_GP_PLL]			= &c1_gp_pll.hw,
		[CLKID_GP_PLL_DIV1]			= &c1_gp_pll_div1.hw,
		[CLKID_GP_PLL_DIV1_FIX_DIV2]	= &c1_gp_pll_div1_fix_div2.hw,
		[CLKID_GP_PLL_DIV1_GATE]	= &c1_gp_pll_div1_gate.hw,
		[CLKID_GP_PLL_DIV2]			= &c1_gp_pll_div2.hw,
		[CLKID_GP_PLL_DIV2_FIX_DIV2]	= &c1_gp_pll_div2_fix_div2.hw,
		[CLKID_GP_PLL_DIV2_GATE]	= &c1_gp_pll_div2_gate.hw,
		[CLKID_GP_PLL_DIV3]			= &c1_gp_pll_div3.hw,
		[CLKID_GP_PLL_DIV3_GATE]	= &c1_gp_pll_div3_gate.hw,
		[CLKID_HIFI_PLL]		= &c1_hifi_pll.hw,
		[CLKID_SYS_PLL]			= &c1_sys_pll.hw,
		[CLKID_AUD_DDS]			= &c1_aud_dds.hw,
		[CLKID_SYS_B_SEL]		= &c1_sys_b_sel.hw,
		[CLKID_SYS_B_DIV]		= &c1_sys_b_div.hw,
		[CLKID_SYS_B]			= &c1_sys_b.hw,
		[CLKID_SYS_A_SEL]		= &c1_sys_a_sel.hw,
		[CLKID_SYS_A_DIV]		= &c1_sys_a_div.hw,
		[CLKID_SYS_A]			= &c1_sys_a.hw,
		[CLKID_SYS_CLK]			= &c1_sys_clk.hw,
		[CLKID_AXI_B_SEL]		= &axi_b_sel.hw,
		[CLKID_AXI_B_DIV]		= &axi_b_div.hw,
		[CLKID_AXI_B]			= &axi_b.hw,
		[CLKID_AXI_A_SEL]		= &axi_a_sel.hw,
		[CLKID_AXI_A_DIV]		= &axi_a_div.hw,
		[CLKID_AXI_A]			= &axi_a.hw,
		[CLKID_AXI_CLK]			= &axi_clk.hw,
		[CLKID_CPU_FSOURCE_SEL0]	= &c1_cpu_fixed_source_sel0.hw,
		[CLKID_CPU_FSOURCE_DIV0]	= &c1_cpu_fixed_source_div0.hw,
		[CLKID_CPU_FSEL0]		= &c1_cpu_fixed_sel0.hw,
		[CLKID_CPU_FSOURCE_SEL1]	= &c1_cpu_fixed_source_sel1.hw,
		[CLKID_CPU_FSOURCE_DIV1]	= &c1_cpu_fixed_source_div1.hw,
		[CLKID_CPU_FSEL1]	= &c1_cpu_fixed_sel1.hw,
		[CLKID_CPU_FCLK]	= &c1_cpu_fixed_clk.hw,
		[CLKID_CPU_CLK]		= &c1_cpu_clk.hw,
		[CLKID_DSU_SOURCE_SEL0]	= &dsu_source_sel0.hw,
		[CLKID_DSU_SOURCE_DIV0]	= &dsu_source_div0.hw,
		[CLKID_DSU_SEL0]	= &dsu_fixed_sel0.hw,
		[CLKID_DSU_SOURCE_SEL1]	= &dsu_source_sel1.hw,
		[CLKID_DSU_SOURCE_DIV1]	= &dsu_source_div1.hw,
		[CLKID_DSU_SEL1]	= &dsu_fixed_sel1.hw,
		[CLKID_DSU_FIXED]	= &dsu_fixed_clk.hw,
		[CLKID_DSU_PRE]		= &dsu_clk_pre.hw,
		[CLKID_DSU_CLK]		= &dsu_clk.hw,
		[CLKID_XTAL_CLKTREE]	= &xtal_clktree.hw,
		[CLKID_XTAL_FIXPLL]	= &xtal_fixpll.hw,
		[CLKID_XTAL_DDRPLL]	= &xtal_ddrpll.hw,
		[CLKID_XTAL_USB_CTRL]	= &xtal_usb_ctrl.hw,
		[CLKID_XTAL_HIFIPLL]	= &xtal_hifipll.hw,
		[CLKID_XTAL_SYSPLL]	= &xtal_syspll.hw,
		[CLKID_XTAL_DDS]	= &xtal_dds.hw,
		[CLKID_XTAL_ETHPLL]	= &xtal_ethpll.hw,
		[CLKID_XTAL_USBPHY]	= &xtal_usbphy.hw,
		[CLKID_XTAL_GPPLL]	= &xtal_gppll.hw,
		[CLKID_XTAL_GPIOM10]	= &xtal_gpio_m10.hw,
		[CLKID_XTAL_GPIOM13]	= &xtal_gpio_m13.hw,
		[CLKID_CLKTREE]		= &clk_tree.hw,
		[CLKID_RESET_CTRL]	= &reset_ctrl.hw,
		[CLKID_ANALOG_CTRL]	= &analog_ctrl.hw,
		[CLKID_PWR_CTRL]	= &pwr_ctrl.hw,
		[CLKID_PAD_CTRL]	= &pad_ctrl.hw,
		[CLKID_SYS_CTRL]	= &sys_ctrl.hw,
		[CLKID_TEMP_SENSOR]	= &temp_sensor.hw,
		[CLKID_AM2AXI_DIV]	= &am2axi_dev.hw,
		[CLKID_SPICC_B]		= &spicc_b.hw,
		[CLKID_SPICC_A]		= &spicc_a.hw,
		[CLKID_CLK_MSR]		= &clk_msr.hw,
		[CLKID_AUDIO]		= &audio.hw,
		[CLKID_JTAG_CTRL]	= &jtag_ctrl.hw,
		[CLKID_SARADC]		= &saradc.hw,
		[CLKID_PWM_EF]		= &pwm_ef.hw,
		[CLKID_PWM_CD]		= &pwm_cd.hw,
		[CLKID_PWM_AB]		= &pwm_ab.hw,
		[CLKID_I2C_S]		= &i2c_s.hw,
		[CLKID_IR_CTRL]		= &ir_ctrl.hw,
		[CLKID_I2C_M_D]		= &i2c_m_d.hw,
		[CLKID_I2C_M_C]		= &i2c_m_c.hw,
		[CLKID_I2C_M_B]		= &i2c_m_b.hw,
		[CLKID_I2C_M_A]		= &i2c_m_a.hw,
		[CLKID_ACODEC]		= &acodec.hw,
		[CLKID_OTP]		= &otp.hw,
		[CLKID_SYS_SD_EMMC_A]	= &sys_sd_emmc_a.hw,
		[CLKID_USB_PHY]		= &usb_phy.hw,
		[CLKID_USB_CTRL]	= &usb_ctrl.hw,
		[CLKID_SYS_DSPB]	= &sys_dspb.hw,
		[CLKID_SYS_DSPA]	= &sys_dspa.hw,
		[CLKID_DMA]		= &dma.hw,
		[CLKID_IRQ_CTRL]	= &irq_ctrl.hw,
		[CLKID_NIC]		= &nic.hw,
		[CLKID_GIC]		= &gic.hw,
		[CLKID_UART_C]		= &uart_c.hw,
		[CLKID_UART_B]		= &uart_b.hw,
		[CLKID_UART_A]		= &uart_a.hw,
		[CLKID_RSA]		= &rsa.hw,
		[CLKID_SYS_CORESIGHT]   = &coresight.hw,
		[CLKID_CSI_PH1]		= &csi_ph1.hw,
		[CLKID_CSI_PHY0]	= &csi_phy0.hw,
		[CLKID_MIPI_ISP]	= &mipi_isp.hw,
		[CLKID_CSI_DIG]		= &csi_dig.hw,
		[CLKID_SYS_G2ED]	= &ge2d.hw,
		[CLKID_SYS_GDC]		= &gdc.hw,
		[CLKID_DOS_APB]		= &dos_apb.hw,
		[CLKID_SYS_NNA]		= &nna.hw,
		[CLKID_SYS_ETH_PHY]	= &eth_phy.hw,
		[CLKID_SYS_ETH_MAC]	= &eth_mac.hw,
		[CLKID_SYS_UART_E]	= &uart_e.hw,
		[CLKID_SYS_UART_D]	= &uart_d.hw,
		[CLKID_SYS_PWM_IJ]	= &pwm_ij.hw,
		[CLKID_SYS_PWM_GH]	= &pwm_gh.hw,
		[CLKID_SYS_I2C_M_E]	= &i2c_m_e.hw,
		[CLKID_SYS_SD_EMMC_C]	= &sd_emmc_C.hw,
		[CLKID_SYS_SD_EMMC_B]	= &sd_emmc_B.hw,
		[CLKID_SYS_ROM]		= &rom.hw,
		[CLKID_SYS_SPIFC]	= &spifc.hw,
		[CLKID_SYS_PROD_I2C]	= &prod_i2c.hw,
		[CLKID_SYS_DOS]		= &dos.hw,
		[CLKID_SYS_CPU_CTRL]	= &cpu_ctrl.hw,
		[CLKID_SYS_RAMA]	= &sys_rama.hw,
		[CLKID_SYS_RAMB]	= &sys_ramb.hw,
		[CLKID_SYS_RAMC]	= &sys_ramc.hw,
		[CLKID_AM2AXI_VAD]	= &axi_am2axi_vad.hw,
		[CLKID_AUDIO_VAD]	= &axi_audio_vad.hw,
		[CLKID_AXI_DMC]		= &axi_dmc.hw,
		[CLKID_AXI_RAMB]	= &axi_ramb.hw,
		[CLKID_AXI_RAMA]	= &axi_rama.hw,
		[CLKID_AXI_NIC]		= &axi_nic.hw,
		[CLKID_AXI_DMA]		= &axi_dma.hw,
		[CLKID_AXI_RAMC]	= &axi_ramc.hw,
		[CLKID_DSPA_A_SEL]	= &c1_dspa_a_sel.hw,
		[CLKID_DSPA_A_DIV]	= &c1_dspa_a_div.hw,
		[CLKID_DSPA_A]		= &c1_dspa_a.hw,
		[CLKID_DSPA_B_SEL]	= &c1_dspa_b_sel.hw,
		[CLKID_DSPA_B_DIV]	= &c1_dspa_b_div.hw,
		[CLKID_DSPA_B]		= &c1_dspa_b.hw,
		[CLKID_DSPA_SEL]	= &c1_dspa_sel.hw,
		[CLKID_DSPB_A_SEL]	= &c1_dspb_a_sel.hw,
		[CLKID_DSPB_A_DIV]	= &c1_dspb_a_div.hw,
		[CLKID_DSPB_A]		= &c1_dspb_a.hw,
		[CLKID_DSPB_B_SEL]	= &c1_dspb_b_sel.hw,
		[CLKID_DSPB_B_DIV]	= &c1_dspb_b_div.hw,
		[CLKID_DSPB_B]		= &c1_dspb_b.hw,
		[CLKID_DSPB_SEL]	= &c1_dspb_sel.hw,
		[CLKID_DSPA_EN_DSPA]	= &c1_dspa_en_dspa.hw,
		[CLKID_DSPA_EN_NIC]	= &c1_dspa_en_nic.hw,
		[CLKID_DSPB_EN_DSPB]	= &c1_dspb_en_dspb.hw,
		[CLKID_DSPB_EN_NIC]	= &c1_dspb_en_nic.hw,
		[CLKID_24M]		= &c1_24m.hw,
		[CLKID_24M_DIV2]	= &c1_24m_div2.hw,
		[CLKID_12M]		= &c1_12m.hw,
		[CLKID_DIV2_PRE]	= &c1_fclk_div2_divn_pre.hw,
		[CLKID_FCLK_DIV2_DIVN]	= &c1_fclk_div2_divn.hw,
		[CLKID_GEN_SEL]		= &c1_gen_sel.hw,
		[CLKID_GEN_DIV]		= &c1_gen_div.hw,
		[CLKID_GEN]		= &c1_gen.hw,
		[CLKID_SARADC_SEL]	= &c1_saradc_sel.hw,
		[CLKID_SARADC_DIV]	= &c1_saradc_div.hw,
		[CLKID_SARADC_GATE]	= &c1_saradc_gate.hw,
		[CLKID_PWM_A_SEL]	= &pwm_a_sel.hw,
		[CLKID_PWM_A_DIV]	= &pwm_a_div.hw,
		[CLKID_PWM_A]		= &pwm_a.hw,
		[CLKID_PWM_B_SEL]	= &pwm_b_sel.hw,
		[CLKID_PWM_B_DIV]	= &pwm_b_div.hw,
		[CLKID_PWM_B]		= &pwm_b.hw,
		[CLKID_PWM_C_SEL]	= &pwm_c_sel.hw,
		[CLKID_PWM_C_DIV]	= &pwm_c_div.hw,
		[CLKID_PWM_C]		= &pwm_c.hw,
		[CLKID_PWM_D_SEL]	= &pwm_d_sel.hw,
		[CLKID_PWM_D_DIV]	= &pwm_d_div.hw,
		[CLKID_PWM_D]		= &pwm_d.hw,
		[CLKID_PWM_E_SEL]	= &pwm_e_sel.hw,
		[CLKID_PWM_E_DIV]	= &pwm_e_div.hw,
		[CLKID_PWM_E]		= &pwm_e.hw,
		[CLKID_PWM_F_SEL]	= &pwm_f_sel.hw,
		[CLKID_PWM_F_DIV]	= &pwm_f_div.hw,
		[CLKID_PWM_F]		= &pwm_f.hw,
		[CLKID_PWM_G_SEL]	= &pwm_g_sel.hw,
		[CLKID_PWM_G_DIV]	= &pwm_g_div.hw,
		[CLKID_PWM_G]		= &pwm_g.hw,
		[CLKID_PWM_H_SEL]	= &pwm_h_sel.hw,
		[CLKID_PWM_H_DIV]	= &pwm_h_div.hw,
		[CLKID_PWM_H]		= &pwm_h.hw,
		[CLKID_PWM_I_SEL]	= &pwm_i_sel.hw,
		[CLKID_PWM_I_DIV]	= &pwm_i_div.hw,
		[CLKID_PWM_I]		= &pwm_i.hw,
		[CLKID_PWM_J_SEL]	= &pwm_j_sel.hw,
		[CLKID_PWM_J_DIV]	= &pwm_j_div.hw,
		[CLKID_PWM_J]		= &pwm_j.hw,
		[CLKID_SPICC_A_SEL]	= &c1_spicc_a_sel.hw,
		[CLKID_SPICC_A_DIV]	= &c1_spicc_a_div.hw,
		[CLKID_SPICC_A_GATE]	= &c1_spicc_a_gate.hw,
		[CLKID_SPICC_A_MUX]		= &c1_spicc_a.hw,
		[CLKID_SPICC_B_SEL]	= &c1_spicc_b_sel.hw,
		[CLKID_SPICC_B_DIV]	= &c1_spicc_b_div.hw,
		[CLKID_SPICC_B_GATE]	= &c1_spicc_b_gate.hw,
		[CLKID_SPICC_B_MUX]		= &c1_spicc_b.hw,
		[CLKID_TS_DIV]		= &c1_ts_div.hw,
		[CLKID_TS]		= &c1_ts.hw,
		[CLKID_SPIFC_SEL]	= &c1_spifc_sel.hw,
		[CLKID_SPIFC_DIV]	= &c1_spifc_div.hw,
		[CLKID_SPIFC_GATE]	= &c1_spifc_gate.hw,
		[CLKID_SPIFC]		= &c1_spifc.hw,
		[CLKID_USB_BUS_SEL]	= &c1_usb_bus_sel.hw,
		[CLKID_USB_BUS_DIV]	= &c1_usb_bus_div.hw,
		[CLKID_USB_BUS]		= &c1_usb_bus.hw,
		[CLKID_SD_EMMC_A_SEL]	= &sd_emmc_a_sel.hw,
		[CLKID_SD_EMMC_A_DIV]	= &sd_emmc_a_div.hw,
		[CLKID_SD_EMMC_A_GATE]	= &sd_emmc_a_gate.hw,
		[CLKID_SD_EMMC_A]	= &sd_emmc_a.hw,
		[CLKID_SD_EMMC_B_SEL]	= &sd_emmc_b_sel.hw,
		[CLKID_SD_EMMC_B_DIV]	= &sd_emmc_b_div.hw,
		[CLKID_SD_EMMC_B_GATE]	= &sd_emmc_b_gate.hw,
		[CLKID_SD_EMMC_B]	= &sd_emmc_b.hw,
		[CLKID_SD_EMMC_C_SEL]	= &sd_emmc_c_sel.hw,
		[CLKID_SD_EMMC_C_DIV]	= &sd_emmc_c_div.hw,
		[CLKID_SD_EMMC_C_GATE]	= &sd_emmc_c_gate.hw,
		[CLKID_SD_EMMC_C]	= &sd_emmc_c.hw,
		[CLKID_FIXED_PLL_DIV2]	= &c1_fixed_pll_div2_gate.hw,
		[CLKID_RTC_32K_CLKIN]   = &c1_rtc_32k_clkin.hw,
		[CLKID_RTC_32K_DIV]	= &c1_rtc_32k_div.hw,
		[CLKID_RTC_32K_XTAL]	= &c1_rtc_32k_xtal.hw,
		[CLKID_RTC_32K_SEL]	= &c1_rtc_32k_sel.hw,
		[CLKID_RTC_CLK]		= &c1_rtc_clk.hw,
		[CLKID_AXI_CLK_FRCPU]	= &axi_clk_frcpu.hw,
		[CLKID_WAVE_A_SEL]	= &wave_a_sel.hw,
		[CLKID_WAVE_A_DIV]	= &wave_a_div.hw,
		[CLKID_WAVE_A_CLK]	= &wave_aclk.hw,
		[CLKID_WAVE_A_GATE]	= &wave_a_gate.hw,
		[CLKID_WAVE_B_SEL]	= &wave_b_sel.hw,
		[CLKID_WAVE_B_DIV]	= &wave_b_div.hw,
		[CLKID_WAVE_B_CLK]	= &wave_bclk.hw,
		[CLKID_WAVE_B_GATE]	= &wave_b_gate.hw,
		[CLKID_WAVE_C_SEL]	= &wave_c_sel.hw,
		[CLKID_WAVE_C_DIV]	= &wave_c_div.hw,
		[CLKID_WAVE_C_CLK]	= &wave_cclk.hw,
		[CLKID_WAVE_C_GATE]	= &wave_c_gate.hw,
		[CLKID_JPEG_SEL]	= &jpeg_sel.hw,
		[CLKID_JPEG_DIV]	= &jpeg_div.hw,
		[CLKID_JPEG_CLK]	= &jpeg_clk.hw,
		[CLKID_JPEG_GATE]	= &jpeg_gate.hw,
		[CLKID_MIPI_CSI_PHY_SEL] = &mipi_csi_phy_sel.hw,
		[CLKID_MIPI_CSI_PHY_DIV] = &mipi_csi_phy_div.hw,
		[CLKID_MIPI_CSI_PHY_CLK] = &mipi_csi_phy_clk.hw,
		[CLKID_MIPI_CSI_PHY_GATE] = &mipi_csi_phy_gate.hw,
		[CLKID_MIPI_ISP_SEL]	= &mipi_isp_sel.hw,
		[CLKID_MIPI_ISP_DIV]	= &mipi_isp_div.hw,
		[CLKID_MIPI_ISP_CLK]	= &mipi_isp_clk.hw,
		[CLKID_MIPI_ISP_GATE]	= &mipi_isp_gate.hw,
		[CLKID_NNA_AXI_SEL]	= &nna_axi_sel.hw,
		[CLKID_NNA_AXI_DIV]	= &nna_axi_div.hw,
		[CLKID_NNA_AXI_CLK]	= &nna_axi_clk.hw,
		[CLKID_NNA_AXI_GATE]	= &nna_axi_gate.hw,
		[CLKID_NNA_CORE_SEL]	= &nna_core_sel.hw,
		[CLKID_NNA_CORE_DIV]	= &nna_core_div.hw,
		[CLKID_NNA_CORE_CLK]	= &nna_core_clk.hw,
		[CLKID_NNA_CORE_GATE]	= &nna_core_gate.hw,
		[CLKID_GDC_AXI_SEL]	= &gdc_axi_sel.hw,
		[CLKID_GDC_AXI_DIV]	= &gdc_axi_div.hw,
		[CLKID_GDC_AXI_CLK]	= &gdc_axi_clk.hw,
		[CLKID_GDC_AXI_GATE]	= &gdc_axi_gate.hw,
		[CLKID_GDC_CORE_SEL]	= &gdc_core_sel.hw,
		[CLKID_GDC_CORE_DIV]	= &gdc_core_div.hw,
		[CLKID_GDC_CORE_CLK]	= &gdc_core_clk.hw,
		[CLKID_GDC_CORE_GATE]	= &gdc_core_gate.hw,
		[CLKID_GE2D_SEL]	= &ge2d_sel.hw,
		[CLKID_GE2D_DIV]	= &ge2d_div.hw,
		[CLKID_GE2D_CLK]	= &ge2d_clk.hw,
		[CLKID_GE2D_GATE]	= &ge2d_gate.hw,
		[CLKID_ETH_CLK125_SEL]	= &eth_clk_125_sel.hw,
		[CLKID_ETH_CLK125_DIV]	= &eth_clk_125_div.hw,
		[CLKID_ETH_CLK125_GATE]	= &eth_clk_125_gate.hw,
		[CLKID_ETH_CLK_RMII_SEL] = &eth_clk_rmii_sel.hw,
		[CLKID_ETH_CLK_RMII_DIV] = &eth_clk_rmii_div.hw,
		[CLKID_ETH_CLK_RMII_GATE] = &eth_clk_rmii_gate.hw,
		[NR_CLKS]		= NULL,
	},
	.num = NR_CLKS,
};

/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const c1_clk_regmaps[] = {
	&xtal_clktree,
	&xtal_fixpll,
	&xtal_ddrpll,
	&xtal_usb_ctrl,
	&xtal_hifipll,
	&xtal_syspll,
	&xtal_dds,
	&xtal_ethpll,
	&xtal_usbphy,
	&xtal_gppll,
	&xtal_gpio_m10,
	&xtal_gpio_m13,
	&clk_tree,
	&reset_ctrl,
	&analog_ctrl,
	&pwr_ctrl,
	&pad_ctrl,
	&sys_ctrl,
	&temp_sensor,
	&am2axi_dev,
	&spicc_b,
	&spicc_a,
	&clk_msr,
	&audio,
	&jtag_ctrl,
	&saradc,
	&pwm_ef,
	&pwm_cd,
	&pwm_ab,
	&i2c_s,
	&ir_ctrl,
	&i2c_m_d,
	&i2c_m_c,
	&i2c_m_b,
	&i2c_m_a,
	&acodec,
	&otp,
	&sys_sd_emmc_a,
	&usb_phy,
	&usb_ctrl,
	&sys_dspb,
	&sys_dspa,
	&dma,
	&irq_ctrl,
	&nic,
	&gic,
	&uart_c,
	&uart_b,
	&uart_a,
	&rsa,
	&coresight,
	&csi_ph1,
	&csi_phy0,
	&mipi_isp,
	&csi_dig,
	&ge2d,
	&gdc,
	&dos_apb,
	&nna,
	&eth_phy,
	&eth_mac,
	&uart_e,
	&uart_d,
	&pwm_ij,
	&pwm_gh,
	&i2c_m_e,
	&sd_emmc_C,
	&sd_emmc_B,
	&rom,
	&spifc,
	&prod_i2c,
	&dos,
	&cpu_ctrl,
	&sys_rama,
	&sys_ramb,
	&sys_ramc,
	&axi_am2axi_vad,
	&axi_audio_vad,
	&axi_dmc,
	&axi_ramb,
	&axi_rama,
	&axi_nic,
	&axi_dma,
	&axi_ramc,
	&c1_dspa_a_sel,
	&c1_dspa_a_div,
	&c1_dspa_a,
	&c1_dspa_b_sel,
	&c1_dspa_b_div,
	&c1_dspa_b,
	&c1_dspa_sel,
	&c1_dspb_a_sel,
	&c1_dspb_a_div,
	&c1_dspb_a,
	&c1_dspb_b_sel,
	&c1_dspb_b_div,
	&c1_dspb_b,
	&c1_dspb_sel,
	&c1_dspa_en_dspa,
	&c1_dspa_en_nic,
	&c1_dspb_en_dspb,
	&c1_dspb_en_nic,
	&c1_24m,
	&c1_12m,
	&c1_fclk_div2_divn_pre,
	&c1_fclk_div2_divn,
	&c1_gen_sel,
	&c1_gen_div,
	&c1_gen,
	&c1_saradc_sel,
	&c1_saradc_div,
	&c1_saradc_gate,
	&pwm_a_sel,
	&pwm_a_div,
	&pwm_a,
	&pwm_b_sel,
	&pwm_b_div,
	&pwm_b,
	&pwm_c_sel,
	&pwm_c_div,
	&pwm_c,
	&pwm_d_sel,
	&pwm_d_div,
	&pwm_d,
	&pwm_e_sel,
	&pwm_e_div,
	&pwm_e,
	&pwm_f_sel,
	&pwm_f_div,
	&pwm_f,
	&pwm_g_sel,
	&pwm_g_div,
	&pwm_g,
	&pwm_h_sel,
	&pwm_h_div,
	&pwm_h,
	&pwm_i_sel,
	&pwm_i_div,
	&pwm_i,
	&pwm_j_sel,
	&pwm_j_div,
	&pwm_j,
	&c1_spicc_a_sel,
	&c1_spicc_a_div,
	&c1_spicc_a_gate,
	&c1_spicc_a,
	&c1_spicc_b_sel,
	&c1_spicc_b_div,
	&c1_spicc_b_gate,
	&c1_spicc_b,
	&c1_ts_div,
	&c1_ts,
	&c1_spifc_sel,
	&c1_spifc_div,
	&c1_spifc_gate,
	&c1_spifc,
	&c1_usb_bus_sel,
	&c1_usb_bus_div,
	&c1_usb_bus,
	&sd_emmc_a_sel,
	&sd_emmc_a_div,
	&sd_emmc_a_gate,
	&sd_emmc_a,
	&sd_emmc_b_sel,
	&sd_emmc_b_div,
	&sd_emmc_b_gate,
	&sd_emmc_b,
	&sd_emmc_c_sel,
	&sd_emmc_c_div,
	&sd_emmc_c_gate,
	&sd_emmc_c,
	&c1_fixed_pll_div2_gate,
	&c1_rtc_32k_clkin,
	&c1_rtc_32k_div,
	&c1_rtc_32k_xtal,
	&c1_rtc_32k_sel,
	&c1_rtc_clk,
	&wave_a_sel,
	&wave_a_div,
	&wave_aclk,
	&wave_a_gate,
	&wave_b_sel,
	&wave_b_div,
	&wave_bclk,
	&wave_b_gate,
	&wave_c_sel,
	&wave_c_div,
	&wave_cclk,
	&wave_c_gate,
	&jpeg_sel,
	&jpeg_div,
	&jpeg_clk,
	&jpeg_gate,
	&mipi_csi_phy_sel,
	&mipi_csi_phy_div,
	&mipi_csi_phy_clk,
	&mipi_csi_phy_gate,
	&mipi_isp_sel,
	&mipi_isp_div,
	&mipi_isp_clk,
	&mipi_isp_gate,
	&nna_axi_sel,
	&nna_axi_div,
	&nna_axi_clk,
	&nna_axi_gate,
	&nna_core_sel,
	&nna_core_div,
	&nna_core_clk,
	&nna_core_gate,
	&gdc_axi_sel,
	&gdc_axi_div,
	&gdc_axi_clk,
	&gdc_axi_gate,
	&gdc_core_sel,
	&gdc_core_div,
	&gdc_core_clk,
	&gdc_core_gate,
	&ge2d_sel,
	&ge2d_div,
	&ge2d_clk,
	&ge2d_gate,
	&eth_clk_125_sel,
	&eth_clk_125_div,
	&eth_clk_125_gate,
	&eth_clk_rmii_sel,
	&eth_clk_rmii_div,
	&eth_clk_rmii_gate,
	&c1_sys_b_sel,
	&c1_sys_b_div,
	&c1_sys_b,
	&c1_sys_a_sel,
	&c1_sys_a_div,
	&c1_sys_a,
	&c1_sys_clk,
	&axi_b_sel,
	&axi_b_div,
	&axi_b,
	&axi_a_sel,
	&axi_a_div,
	&axi_a,
	&axi_clk,
};

/*
 * cpu clock register base is 0xfd000000
 * the clk_regmap init alone
 */
static struct clk_regmap *const c1_cpu_clk_regmaps[] = {
	&c1_cpu_fixed_source_sel0,
	&c1_cpu_fixed_source_div0,
	&c1_cpu_fixed_sel0,
	&c1_cpu_fixed_source_sel1,
	&c1_cpu_fixed_source_div1,
	&c1_cpu_fixed_sel1,
	&c1_cpu_fixed_clk,
	&c1_cpu_clk,
	&dsu_source_sel0,
	&dsu_source_div0,
	&dsu_fixed_sel0,
	&dsu_source_sel1,
	&dsu_source_div1,
	&dsu_fixed_sel1,
	&dsu_fixed_clk,
	&dsu_clk_pre,
	&dsu_clk,
	&axi_clk_frcpu,
};

/*
 * pll clock register base is 0xfe007c00
 * the clk_regmap init alone
 */
static struct clk_regmap *const c1_pll_clk_regmaps[] = {
	&c1_fixed_pll_dco,
	&c1_fixed_pll,
	&c1_fclk_div2,
	&c1_fclk_div2p5,
	&c1_fclk_div3,
	&c1_fclk_div4,
	&c1_fclk_div5,
	&c1_fclk_div7,
	&c1_gp_pll,
	&c1_gp_pll_div1,
	&c1_gp_pll_div1_gate,
	&c1_gp_pll_div2,
	&c1_gp_pll_div2_gate,
	&c1_gp_pll_div3,
	&c1_gp_pll_div3_gate,
	&c1_hifi_pll,
	&c1_sys_pll,
	&c1_aud_dds,
};

struct c1_nb_data {
	struct notifier_block nb;
	struct clk_hw_onecell_data *onecell_data;
};

static int c1_cpu_fixed_clk_notifier_cb(struct notifier_block *nb,
					unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct clk *cpu_fixed_clk, *parent_clk;
	int ret;

	switch (event) {
	case PRE_RATE_CHANGE:
	parent_clk = c1_cpu_fixed_sel1.hw.clk;
	ret = clk_set_rate(parent_clk, ndata->new_rate);
	if (ret)
		pr_err("set fixed sel1 to new rate failed\n");
		break;
	case POST_RATE_CHANGE:
	parent_clk = c1_cpu_fixed_sel0.hw.clk;
		break;
	default:
		return NOTIFY_DONE;
	}

	cpu_fixed_clk = c1_cpu_fixed_clk.hw.clk;
	ret = clk_set_parent(cpu_fixed_clk, parent_clk);
	if (ret)
		return notifier_from_errno(ret);

	return NOTIFY_OK;
}

static struct c1_nb_data c1_cpu_fixed_nb_data = {
	.nb.notifier_call = c1_cpu_fixed_clk_notifier_cb,
	.onecell_data = &c1_hw_onecell_data,
};

static const struct of_device_id clkc_match_table[] = {
	{ .compatible = "amlogic,c1-clkc" },
	{}
};

static struct regmap_config clkc_regmap_config = {
	.reg_bits       = 32,
	.val_bits       = 32,
	.reg_stride     = 4,
};

static struct regmap *c1_regmap_resource(struct device *dev, char *name)
{
	struct resource res;
	void __iomem *base;
	int i;
	struct device_node *node = dev->of_node;

	i = of_property_match_string(node, "reg-names", name);
	if (of_address_to_resource(node, i, &res))
		return ERR_PTR(-ENOENT);

	base = devm_ioremap_resource(dev, &res);
	if (IS_ERR(base))
		return ERR_CAST(base);

	clkc_regmap_config.max_register = resource_size(&res) - 4;
	clkc_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL,
						 "%s-%s", node->name,
						 name);
	if (!clkc_regmap_config.name)
		return ERR_PTR(-ENOMEM);

	return devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
}

static int c1_clkc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct regmap *basic_map;
	struct regmap *pll_map;
	struct regmap *cpu_clk_map;
	struct clk_hw *hw;
	int ret, i;

	/* Get the hhi system controller node */
	/*
	 *map = syscon_node_to_regmap(of_get_parent(dev->of_node));
	 *if (IS_ERR(map)) {
	 *	dev_err(dev,
	 *		"failed to get HHI regmap\n");
	 *	return PTR_ERR(map);
	 *}
	 */

	/* Get regmap for different clock area */
	basic_map = c1_regmap_resource(dev, "basic");
	if (IS_ERR(basic_map)) {
		dev_err(dev, "basic clk registers not found\n");
		return PTR_ERR(basic_map);
	}

	pll_map = c1_regmap_resource(dev, "pll");
	if (IS_ERR(pll_map)) {
		dev_err(dev, "pll clk registers not found\n");
		return PTR_ERR(pll_map);
	}

	cpu_clk_map = c1_regmap_resource(dev, "cpu_clk");
	if (IS_ERR(cpu_clk_map)) {
		dev_err(dev, "cpu clk registers not found\n");
		return PTR_ERR(cpu_clk_map);
	}

	hw = meson_clk_hw_register_input(dev, "core", "c1_ee_core", 0);
	if (IS_ERR(hw))
		return PTR_ERR(hw);

	c1_hw_onecell_data.hws[CLKID_EE_CORE] = hw;

	/* Populate regmap for the regmap backed clocks */
	for (i = 0; i < ARRAY_SIZE(c1_clk_regmaps); i++)
		c1_clk_regmaps[i]->map = basic_map;

	for (i = 0; i < ARRAY_SIZE(c1_cpu_clk_regmaps); i++)
		c1_cpu_clk_regmaps[i]->map = cpu_clk_map;

	for (i = 0; i < ARRAY_SIZE(c1_pll_clk_regmaps); i++)
		c1_pll_clk_regmaps[i]->map = pll_map;

	for (i = 1; i < c1_hw_onecell_data.num; i++) {
		/* array might be sparse */
		if (!c1_hw_onecell_data.hws[i])
			continue;
		/*
		 * dev_err(dev, "register %d  %s\n",i,
		 *		c1_hw_onecell_data.hws[i]->init->name);
		 */
		ret = devm_clk_hw_register(dev, c1_hw_onecell_data.hws[i]);
		if (ret) {
			dev_err(dev, "Clock registration failed\n");
			return ret;
		}
	}
	/*
	 * FIXME we shouldn't program the muxes in notifier handlers. The
	 * tricky programming sequence will be handled by the forthcoming
	 * coordinated clock rates mechanism once that feature is released.
	 */
	/*
	 *ret = clk_notifier_register(c1_sys_pll.hw.clk, &c1_cpu_nb_data.nb);
	 *if (ret) {
	 *	pr_err("%s: failed to register the CPU clock:
	 *	       sys pll notifier\n", __func__);
	 *	return ret;
	 *}
	 */

	ret = clk_notifier_register(c1_cpu_fixed_sel0.hw.clk,
				    &c1_cpu_fixed_nb_data.nb);
	if (ret) {
		pr_err("%s: failed to register the CPU Fixed clock:fsel0 notifier\n",
		       __func__);
		return ret;
	}
	/*
	 * keep cpu_fixed_clk's parent as cpu_fixed_sel0 clock
	 */
	ret = clk_set_parent(c1_cpu_fixed_clk.hw.clk, c1_cpu_fixed_sel0.hw.clk);
	if (ret) {
		pr_err("%s: failed to set cpu_fixed_sel1 as cpu fixed clk's parent\n",
		       __func__);
		return ret;
	}

	/*
	 * fclk_div2, fclk_div3, fclk_div5, fclk_div7 should enable
	 * default it may be disabled when operate the child clock.
	 */
	ret = clk_prepare_enable(c1_fclk_div2.hw.clk);
	if (ret) {
		pr_err("%s: enable %s failed\n",
		       __func__, c1_fclk_div2.hw.init->name);
		return ret;
	}
	ret = clk_prepare_enable(c1_fclk_div3.hw.clk);
	if (ret) {
		pr_err("%s: enable %s failed\n",
		       __func__, c1_fclk_div3.hw.init->name);
		return ret;
	}
	ret = clk_prepare_enable(c1_fclk_div5.hw.clk);
	if (ret) {
		pr_err("%s: enable %s failed\n",
		       __func__, c1_fclk_div5.hw.init->name);
		return ret;
	}
	ret = clk_prepare_enable(c1_fclk_div7.hw.clk);
	if (ret) {
		pr_err("%s: enable %s failed\n",
		       __func__, c1_fclk_div7.hw.init->name);
		return ret;
	}

	/*
	 * set dsu_source_sel1 parent to c1_fclk_div2 1G
	 */
	ret = clk_set_parent(dsu_source_sel1.hw.clk, c1_fclk_div2.hw.clk);
	if (ret) {
		pr_err("%s: failed to set parent\n", __func__);
		return ret;
	}

	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
					   &c1_hw_onecell_data);
}

static struct platform_driver c1_driver = {
	.probe		= c1_clkc_probe,
	.driver		= {
		.name	= "c1-clkc",
		.of_match_table = clkc_match_table,
	},
};

static int c1_clkc_init(void)
{
	return platform_driver_register(&c1_driver);
}
arch_initcall_sync(c1_clkc_init);