/* SPDX-License-Identifier: GPL-2.0 */
/**
 * Register map for PS13216 (Schumacher)
 *
 * Refer to nest-internal/platform/nlplatform/src/devices/i2c/ps13216_regs.h for a complete list of
 * registers/values.
 *
 * Copyright 2021 Google LLC.
 */

#ifndef __SSR_PS13216_SSR_REGS_H_
#define __SSR_PS13216_SSR_REGS_H_

// Register addresses
#define PS13216_REG_EVENT0					0x02
#define PS13216_REG_EVENT1					0x03
#define PS13216_REG_GLOBAL_EVENTS				0x04
#define PS13216_REG_SETUP					0x06
#define PS13216_REG_CTRL					0x0D
#define PS13216_REG_BB1XB					0x0E
#define PS13216_REG_BB0XB					0x0F
#define PS13216_REG_FORCE_ACTIVE				0x16
#define PS13216_REG_EVENT0_MASK					0x1d
#define PS13216_REG_EVENT1_MASK					0x1e
#define PS13216_REG_ADC_CTRL					0x20
#define PS13216_REG_ADC_FIFO					0x2B
#define PS13216_REG_ADC_FIFO_FILL_CNT_LSB			0x34
#define PS13216_REG_ADC_FIFO_FILL_CNT_MSB			0x35
#define PS13216_REG_TEST_SIGNAL_SPY				0xD8
#define PS13216_REG_SW_TEST_MODE				0xFF

#define PS13216_MAX_REGISTER					0xFF

// Event masking register masks
#define PS13216_M_EVENT0_MASK_OVC0			BIT(0)
#define PS13216_M_EVENT0_MASK_OVC1			BIT(1)
#define PS13216_M_EVENT0_MASK_CP_PF0			BIT(2)
#define PS13216_M_EVENT0_MASK_CP_PF1			BIT(3)
#define PS13216_M_EVENT0_MASK_OT0			BIT(4)
#define PS13216_M_EVENT0_MASK_OT1			BIT(5)
#define PS13216_M_EVENT0_MASK_SW0_OFF			BIT(6)
#define PS13216_M_EVENT0_MASK_SW1_OFF			BIT(7)
#define PS13216_M_EVENT0_MASK_ALL    \
	(PS13216_M_EVENT0_MASK_OVC0         \
	 | PS13216_M_EVENT0_MASK_OVC1       \
	 | PS13216_M_EVENT0_MASK_CP_PF0     \
	 | PS13216_M_EVENT0_MASK_CP_PF1     \
	 | PS13216_M_EVENT0_MASK_OT0        \
	 | PS13216_M_EVENT0_MASK_OT1        \
	 | PS13216_M_EVENT0_MASK_SW0_OFF    \
	 | PS13216_M_EVENT0_MASK_SW1_OFF)

#define PS13216_V_EVENT0_MASK_OVCx(ch)    (PS13216_M_EVENT0_MASK_OVC0 << (ch))
#define PS13216_V_EVENT0_MASK_CP_PFx(ch)  (PS13216_M_EVENT0_MASK_CP_PF0 << (ch))
#define PS13216_V_EVENT0_MASK_OTx(ch)     (PS13216_M_EVENT0_MASK_OT0 << (ch))
#define PS13216_V_EVENT0_MASK_SWx_OFF(ch) (PS13216_M_EVENT0_MASK_SW0_OFF << (ch))

#define PS13216_M_EVENT1_MASK_RESET			BIT(0)
#define PS13216_M_EVENT1_MASK_GPI			BIT(1)
#define PS13216_M_EVENT1_MASK_SUPF			BIT(2)
#define PS13216_M_EVENT1_MASK_EOC			BIT(3)
#define PS13216_M_EVENT1_MASK_ADDR			BIT(5)
#define PS13216_M_EVENT1_MASK_ALL \
	(PS13216_M_EVENT1_MASK_RESET \
	 | PS13216_M_EVENT1_MASK_GPI \
	 | PS13216_M_EVENT1_MASK_SUPF \
	 | PS13216_M_EVENT1_MASK_EOC \
	 | PS13216_M_EVENT1_MASK_ADDR)

// Event and Status Masks
#define PS13216_M_EVENT0_OVC0				BIT(0)
#define PS13216_M_EVENT0_OVC1				BIT(1)
#define PS13216_M_EVENT0_CP_PF0				BIT(2)
#define PS13216_M_EVENT0_CP_PF1				BIT(3)
#define PS13216_M_EVENT0_OT0				BIT(4)
#define PS13216_M_EVENT0_OT1				BIT(5)
#define PS13216_M_EVENT0_SW0_OFF			BIT(6)
#define PS13216_M_EVENT0_SW1_OFF			BIT(7)
#define PS13216_M_EVENT0_ALL  \
	(PS13216_M_EVENT0_OVC0     \
	 | PS13216_M_EVENT0_OVC1   \
	 | PS13216_M_EVENT0_CP_PF0 \
	 | PS13216_M_EVENT0_CP_PF1 \
	 | PS13216_M_EVENT0_OT0    \
	 | PS13216_M_EVENT0_OT1    \
	 | PS13216_M_EVENT0_SW0_OFF \
	 | PS13216_M_EVENT0_SW1_OFF)

#define PS13216_V_EVENT0_OVCx(ch)    (PS13216_M_EVENT0_OVC0 << (ch))
#define PS13216_V_EVENT0_CP_PFx(ch)  (PS13216_M_EVENT0_CP_PF0 << (ch))
#define PS13216_V_EVENT0_OTx(ch)     (PS13216_M_EVENT0_OT0 << (ch))
#define PS13216_V_EVENT0_SWx_OFF(ch) (PS13216_M_EVENT0_SW0_OFF << (ch))

#define PS13216_M_EVENT1_RESET				BIT(0)
#define PS13216_M_EVENT1_GPI				BIT(1)
#define PS13216_M_EVENT1_SUPF				BIT(2)
#define PS13216_M_EVENT1_EOC				BIT(3)
#define PS13216_M_EVENT1_ADDR				BIT(5)
#define PS13216_M_EVENT1_ALL \
	(PS13216_M_EVENT1_RESET \
	 | PS13216_M_EVENT1_GPI \
	 | PS13216_M_EVENT1_SUPF \
	 | PS13216_M_EVENT1_EOC \
	 | PS13216_M_EVENT1_ADDR)

#define PS13216_M_GLOBAL_EVENTS_BLACKOUT		BIT(0)
#define PS13216_M_GLOBAL_EVENTS_BROWNOUT		BIT(1)
#define PS13216_M_GLOBAL_EVENTS_OT_CORE			BIT(2)
#define PS13216_M_GLOBAL_EVENTS_DEAD_MAN		BIT(4)
#define PS13216_M_GLOBAL_EVENTS_LV2HV0			BIT(5)
#define PS13216_M_GLOBAL_EVENTS_LV2HV1			BIT(6)
#define PS13216_M_GLOBAL_EVENTS_ALL    \
	(PS13216_M_GLOBAL_EVENTS_BLACKOUT  \
	 | PS13216_M_GLOBAL_EVENTS_BROWNOUT \
	 | PS13216_M_GLOBAL_EVENTS_OT_CORE  \
	 | PS13216_M_GLOBAL_EVENTS_DEAD_MAN \
	 | PS13216_M_GLOBAL_EVENTS_LV2HV0   \
	 | PS13216_M_GLOBAL_EVENTS_LV2HV1)

// Setup Register Masks and Macros
#define PS13216_M_SETUP_RESTART_CONFIG			(BIT(0) | BIT(1))
#define PS13216_G_SETUP_RESTART_CONFIG(r)		(((r) >> 0) & 0x3u)
#define PS13216_V_SETUP_RESTART_CONFIG(x)		((x) << 0)
#define PS13216_SETUP_RESTART_DISABLED			(0)
#define PS13216_SETUP_RESTART_4_TIMES			(1)
#define PS13216_SETUP_RESTART_8_TIMES			(2)
#define PS13216_SETUP_RESTART_15_TIMES			(3)

#define PS13216_M_SETUP_FAST_MODE_CONFIG		(BIT(2) | BIT(3))
#define PS13216_G_SETUP_FAST_MODE_CONFIG(r)		(((r) >> 2) & 0x3u)
#define PS13216_V_SETUP_FAST_MODE_CONFIG(x)		((x) << 2)
#define PS13216_SETUP_FAST_MODE_DISABLED		(0)
#define PS13216_SETUP_FAST_MODE_CH0			(1)
#define PS13216_SETUP_FAST_MODE_CH1			(2)
#define PS13216_SETUP_FAST_MODE_CH0_CH1			(3)

#define PS13216_M_SETUP_PULSE_MODE_CONFIG		(BIT(4) | BIT(5))
#define PS13216_G_SETUP_PULSE_MODE_CONFIG(r)		(((r) >> 4) & 0x3u)
#define PS13216_V_SETUP_PULSE_MODE_CONFIG(x)		((x) << 4)
#define PS13216_SETUP_PULSE_MODE_DISABLED		(0)
#define PS13216_SETUP_PULSE_MODE_CH0			(1)
#define PS13216_SETUP_PULSE_MODE_CH1			(2)

#define PS13216_M_SETUP_GP_CONFIG			(BIT(6) | BIT(7))
#define PS13216_G_SETUP_GP_CONFIG(r)			(((r) >> 6) & 0x3u)
#define PS13216_V_SETUP_GP_CONFIG(x)			((x) << 6)
#define PS13216_SETUP_GP_DISABLED			(0)
#define PS13216_SETUP_GP_CH0				(1)
#define PS13216_SETUP_GP_CH1				(2)

// Bit-Banding Control Register Masks and Macros
#define PS13216_M_BB0XB_C0	BIT(0)

#define PS13216_M_BB1XB_C0	BIT(0)

// ADC Register Masks
#define PS13216_M_ADC_CTRL_VI0				BIT(0)
#define PS13216_M_ADC_CTRL_VI1				BIT(1)
#define PS13216_M_ADC_CTRL_T0				BIT(2)
#define PS13216_M_ADC_CTRL_T1				BIT(3)
#define PS13216_M_ADC_CTRL_HV_SENSE			BIT(4)
#define PS13216_M_ADC_CTRL_ALL_CHANNELS	\
	(PS13216_M_ADC_CTRL_VI0			\
	 | PS13216_M_ADC_CTRL_VI1		\
	 | PS13216_M_ADC_CTRL_T0		\
	 | PS13216_M_ADC_CTRL_T1		\
	 | PS13216_M_ADC_CTRL_HV_SENSE)

#define PS13216_M_ADC_CTRL_COD				BIT(5)
#define PS13216_M_ADC_CTRL_MODE				(BIT(6) | BIT(7))
#define PS13216_G_ADC_CTRL_MODE(r)			(((r) >> 6) & 0x3)
#define PS13216_V_ADC_CTRL_MODE(x)			((x) << 6)
#define PS13216_ADC_MODE_DISABLED			(0)
#define PS13216_ADC_MODE_MAM				(1)
#define PS13216_ADC_MODE_SAM				(2)
#define PS13216_ADC_MODE_CAM				(3)

// Force active register masks
#define PS13216_V_FORCE_ACTIVE(x)	((x) << 0)

// Event and status masks
#define PS13216_M_EVENT1_EOC		BIT(3)

// Test mode commands
#define PS13216_ENTER_TEST_MODE_1ST_BYTE	0x4D
#define PS13216_ENTER_TEST_MODE_2ND_BYTE	0x53

#define PS13216_LEAVE_TEST_MODE_1ST_BYTE	(~0x53)
#define PS13216_LEAVE_TEST_MODE_2ND_BYTE	(~0x4D)

#define PS13216_SIGNALSPY_ZERO_CROSS_CH0	0x8F
#define PS13216_SIGNALSPY_ZERO_CROSS_CH1	0x94
#define PS13216_SIGNALSPY_DISABLE		0x00

#endif // __SSR_PS13216_SSR_REGS_H_