/*************************************************************************************
*       Copyright (C) 2007-2011
*       Copyright ? 2007 Marvell International Ltd.
*
*       This program is free software; you can redistribute it and/or
*       modify it under the terms of the GNU General Public License
*       as published by the Free Software Foundation; either version 2
*       of the License, or (at your option) any later version.
*
*       This program is distributed in the hope that it will be useful,
*       but WITHOUT ANY WARRANTY; without even the implied warranty of
*       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*       GNU General Public License for more details.
*
*       You should have received a copy of the GNU General Public License
*       along with this program; if not, write to the Free Software
*       Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
*
***************************************************************************************/
//////
/// don't edit! auto-generated by docc: avioGbl.h
////////////////////////////////////////////////////////////
#ifndef avioGbl_h
#define avioGbl_h (){}


#include "ctypes.h"

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
/// 
/// $INTERFACE avpllCh                 biu              (4,4)
///     ###
///     * AVPLL control signals for one channel
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               %unsigned 13 POSTDIV                   0x0
///               %unsigned 1  POSTDIV_0P5               0x0
///                                    ###
///                                    * Audio clock divider program
///                                    * 1, When POSTDIV_CX[12:0]=
///                                    * 0 0000 0000 0000, then disable post divider
///                                    * 2, When POSTDIV_CX[12:0]>0:
///                                    * if POSTDIV_0P5_CX=0:
///                                    * Divider=POSTDIV_CX[12:0],
///                                    * if POSTDIV_0P5_CX=1:
///                                    * Divider=POSTDIV_CX[12:0]+0.5
///                                    * For C1-C7 only
///                                    ###
///               %unsigned 1  EN_DPLL                   0x0
///                                    ###
///                                    * 0: disable channel CX's DPLL
///                                    * 1: enable channel CX's DPLL
///                                    ###
///               %unsigned 2  EN_LP                     0x0
///                                    ###
///                                    * EN_LP_CX[1:0] FREQ_OFFSET   CK_INTG
///                                    * 00        X             CK_SSC
///                                    * 01         X*2          CK_SSC/2
///                                    * 10         X              CK_SSC
///                                    * 11          X*4                CK_SSC/4
///                                    ###
///               %%        15         # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 19 FREQ_OFFSET               0x0
///                                    ###
///                                    * [18] is sign bit
///                                    * 0: PI's Frequency down
///                                    * 1: PI's Frequency up
///                                    * [17:0]: 1 LSB -> 0.25ppm,
///                                    * up to 5%
///                                    ###
///               %unsigned 1  FREQ_OFFSET_READY         0x0
///                                    ###
///                                    * Frequency offset value readiness
///                                    * indicator for FREQ_OFFSET_CX [18:0],
///                                    * the pulse need to be longer
///                                    * than 320/Fvco. For Fvco=3GHz,
///                                    * the pulse with should > 172ns;
///                                    * For Fvco=1.5GHz, pulse width >344ns
///                                    ###
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * 0: power down channel CX
///                                    * 1: power up channel CX
///                                    ###
///               %unsigned 1  PU_OFST_CTRL              0x1
///                                    ###
///                                    * 0: power down FREQ_OFFS
///                                    * 1: power up FREQ_OFFSET
///                                    ###
///               %%        10         # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 20 P_SYNC1                   0x10
///                                    ###
///                                    * Set DPLL's reference divider
///                                    * Divider= P_SYNC1_CX[19:0]
///                                    * It is forbidden when N<16
///                                    ###
///               %%        12         # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 20 P_SYNC2                   0x10
///                                    ###
///                                    * Set DPLL's feedback divider
///                                    * Divider= P_SYNC2_CX[19:0]
///                                    * It is forbidden when N<16
///                                    ###
///               %unsigned 1  RESET                     0x1
///                                    ###
///                                    * Reset channel CX logic:
///                                    * 0: not reset
///                                    * 1: active reset
///                                    ###
///               %unsigned 2  RESERVE_IN                0x0
///               %%        9          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      82b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_avpllCh
#define h_avpllCh (){}

    #define     RA_avpllCh_ctrl                                0x0000

    #define     BA_avpllCh_ctrl_POSTDIV                        0x0000
    #define     B16avpllCh_ctrl_POSTDIV                        0x0000
    #define   LSb32avpllCh_ctrl_POSTDIV                           0
    #define   LSb16avpllCh_ctrl_POSTDIV                           0
    #define       bavpllCh_ctrl_POSTDIV                        13
    #define   MSK32avpllCh_ctrl_POSTDIV                           0x00001FFF

    #define     BA_avpllCh_ctrl_POSTDIV_0P5                    0x0001
    #define     B16avpllCh_ctrl_POSTDIV_0P5                    0x0000
    #define   LSb32avpllCh_ctrl_POSTDIV_0P5                       13
    #define   LSb16avpllCh_ctrl_POSTDIV_0P5                       13
    #define       bavpllCh_ctrl_POSTDIV_0P5                    1
    #define   MSK32avpllCh_ctrl_POSTDIV_0P5                       0x00002000

    #define     BA_avpllCh_ctrl_EN_DPLL                        0x0001
    #define     B16avpllCh_ctrl_EN_DPLL                        0x0000
    #define   LSb32avpllCh_ctrl_EN_DPLL                           14
    #define   LSb16avpllCh_ctrl_EN_DPLL                           14
    #define       bavpllCh_ctrl_EN_DPLL                        1
    #define   MSK32avpllCh_ctrl_EN_DPLL                           0x00004000

    #define     BA_avpllCh_ctrl_EN_LP                          0x0001
    #define     B16avpllCh_ctrl_EN_LP                          0x0000
    #define   LSb32avpllCh_ctrl_EN_LP                             15
    #define   LSb16avpllCh_ctrl_EN_LP                             15
    #define       bavpllCh_ctrl_EN_LP                          2
    #define   MSK32avpllCh_ctrl_EN_LP                             0x00018000

    #define     RA_avpllCh_ctrl1                               0x0004

    #define     BA_avpllCh_ctrl_FREQ_OFFSET                    0x0004
    #define     B16avpllCh_ctrl_FREQ_OFFSET                    0x0004
    #define   LSb32avpllCh_ctrl_FREQ_OFFSET                       0
    #define   LSb16avpllCh_ctrl_FREQ_OFFSET                       0
    #define       bavpllCh_ctrl_FREQ_OFFSET                    19
    #define   MSK32avpllCh_ctrl_FREQ_OFFSET                       0x0007FFFF

    #define     BA_avpllCh_ctrl_FREQ_OFFSET_READY              0x0006
    #define     B16avpllCh_ctrl_FREQ_OFFSET_READY              0x0006
    #define   LSb32avpllCh_ctrl_FREQ_OFFSET_READY                 19
    #define   LSb16avpllCh_ctrl_FREQ_OFFSET_READY                 3
    #define       bavpllCh_ctrl_FREQ_OFFSET_READY              1
    #define   MSK32avpllCh_ctrl_FREQ_OFFSET_READY                 0x00080000

    #define     BA_avpllCh_ctrl_PU                             0x0006
    #define     B16avpllCh_ctrl_PU                             0x0006
    #define   LSb32avpllCh_ctrl_PU                                20
    #define   LSb16avpllCh_ctrl_PU                                4
    #define       bavpllCh_ctrl_PU                             1
    #define   MSK32avpllCh_ctrl_PU                                0x00100000

    #define     BA_avpllCh_ctrl_PU_OFST_CTRL                   0x0006
    #define     B16avpllCh_ctrl_PU_OFST_CTRL                   0x0006
    #define   LSb32avpllCh_ctrl_PU_OFST_CTRL                      21
    #define   LSb16avpllCh_ctrl_PU_OFST_CTRL                      5
    #define       bavpllCh_ctrl_PU_OFST_CTRL                   1
    #define   MSK32avpllCh_ctrl_PU_OFST_CTRL                      0x00200000

    #define     RA_avpllCh_ctrl2                               0x0008

    #define     BA_avpllCh_ctrl_P_SYNC1                        0x0008
    #define     B16avpllCh_ctrl_P_SYNC1                        0x0008
    #define   LSb32avpllCh_ctrl_P_SYNC1                           0
    #define   LSb16avpllCh_ctrl_P_SYNC1                           0
    #define       bavpllCh_ctrl_P_SYNC1                        20
    #define   MSK32avpllCh_ctrl_P_SYNC1                           0x000FFFFF

    #define     RA_avpllCh_ctrl3                               0x000C

    #define     BA_avpllCh_ctrl_P_SYNC2                        0x000C
    #define     B16avpllCh_ctrl_P_SYNC2                        0x000C
    #define   LSb32avpllCh_ctrl_P_SYNC2                           0
    #define   LSb16avpllCh_ctrl_P_SYNC2                           0
    #define       bavpllCh_ctrl_P_SYNC2                        20
    #define   MSK32avpllCh_ctrl_P_SYNC2                           0x000FFFFF

    #define     BA_avpllCh_ctrl_RESET                          0x000E
    #define     B16avpllCh_ctrl_RESET                          0x000E
    #define   LSb32avpllCh_ctrl_RESET                             20
    #define   LSb16avpllCh_ctrl_RESET                             4
    #define       bavpllCh_ctrl_RESET                          1
    #define   MSK32avpllCh_ctrl_RESET                             0x00100000

    #define     BA_avpllCh_ctrl_RESERVE_IN                     0x000E
    #define     B16avpllCh_ctrl_RESERVE_IN                     0x000E
    #define   LSb32avpllCh_ctrl_RESERVE_IN                        21
    #define   LSb16avpllCh_ctrl_RESERVE_IN                        5
    #define       bavpllCh_ctrl_RESERVE_IN                     2
    #define   MSK32avpllCh_ctrl_RESERVE_IN                        0x00600000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_avpllCh {
    ///////////////////////////////////////////////////////////
    #define   GET32avpllCh_ctrl_POSTDIV(r32)                   _BFGET_(r32,12, 0)
    #define   SET32avpllCh_ctrl_POSTDIV(r32,v)                 _BFSET_(r32,12, 0,v)
    #define   GET16avpllCh_ctrl_POSTDIV(r16)                   _BFGET_(r16,12, 0)
    #define   SET16avpllCh_ctrl_POSTDIV(r16,v)                 _BFSET_(r16,12, 0,v)

    #define   GET32avpllCh_ctrl_POSTDIV_0P5(r32)               _BFGET_(r32,13,13)
    #define   SET32avpllCh_ctrl_POSTDIV_0P5(r32,v)             _BFSET_(r32,13,13,v)
    #define   GET16avpllCh_ctrl_POSTDIV_0P5(r16)               _BFGET_(r16,13,13)
    #define   SET16avpllCh_ctrl_POSTDIV_0P5(r16,v)             _BFSET_(r16,13,13,v)

    #define   GET32avpllCh_ctrl_EN_DPLL(r32)                   _BFGET_(r32,14,14)
    #define   SET32avpllCh_ctrl_EN_DPLL(r32,v)                 _BFSET_(r32,14,14,v)
    #define   GET16avpllCh_ctrl_EN_DPLL(r16)                   _BFGET_(r16,14,14)
    #define   SET16avpllCh_ctrl_EN_DPLL(r16,v)                 _BFSET_(r16,14,14,v)

    #define   GET32avpllCh_ctrl_EN_LP(r32)                     _BFGET_(r32,16,15)
    #define   SET32avpllCh_ctrl_EN_LP(r32,v)                   _BFSET_(r32,16,15,v)

    #define     w32avpllCh_ctrl                                {\
            UNSG32 uctrl_POSTDIV                               : 13;\
            UNSG32 uctrl_POSTDIV_0P5                           :  1;\
            UNSG32 uctrl_EN_DPLL                               :  1;\
            UNSG32 uctrl_EN_LP                                 :  2;\
            UNSG32 RSVDx0_b17                                  : 15;\
          }
    union { UNSG32 u32avpllCh_ctrl;
            struct w32avpllCh_ctrl;
          };
    #define   GET32avpllCh_ctrl_FREQ_OFFSET(r32)               _BFGET_(r32,18, 0)
    #define   SET32avpllCh_ctrl_FREQ_OFFSET(r32,v)             _BFSET_(r32,18, 0,v)

    #define   GET32avpllCh_ctrl_FREQ_OFFSET_READY(r32)         _BFGET_(r32,19,19)
    #define   SET32avpllCh_ctrl_FREQ_OFFSET_READY(r32,v)       _BFSET_(r32,19,19,v)
    #define   GET16avpllCh_ctrl_FREQ_OFFSET_READY(r16)         _BFGET_(r16, 3, 3)
    #define   SET16avpllCh_ctrl_FREQ_OFFSET_READY(r16,v)       _BFSET_(r16, 3, 3,v)

    #define   GET32avpllCh_ctrl_PU(r32)                        _BFGET_(r32,20,20)
    #define   SET32avpllCh_ctrl_PU(r32,v)                      _BFSET_(r32,20,20,v)
    #define   GET16avpllCh_ctrl_PU(r16)                        _BFGET_(r16, 4, 4)
    #define   SET16avpllCh_ctrl_PU(r16,v)                      _BFSET_(r16, 4, 4,v)

    #define   GET32avpllCh_ctrl_PU_OFST_CTRL(r32)              _BFGET_(r32,21,21)
    #define   SET32avpllCh_ctrl_PU_OFST_CTRL(r32,v)            _BFSET_(r32,21,21,v)
    #define   GET16avpllCh_ctrl_PU_OFST_CTRL(r16)              _BFGET_(r16, 5, 5)
    #define   SET16avpllCh_ctrl_PU_OFST_CTRL(r16,v)            _BFSET_(r16, 5, 5,v)

    #define     w32avpllCh_ctrl1                               {\
            UNSG32 uctrl_FREQ_OFFSET                           : 19;\
            UNSG32 uctrl_FREQ_OFFSET_READY                     :  1;\
            UNSG32 uctrl_PU                                    :  1;\
            UNSG32 uctrl_PU_OFST_CTRL                          :  1;\
            UNSG32 RSVDx4_b22                                  : 10;\
          }
    union { UNSG32 u32avpllCh_ctrl1;
            struct w32avpllCh_ctrl1;
          };
    #define   GET32avpllCh_ctrl_P_SYNC1(r32)                   _BFGET_(r32,19, 0)
    #define   SET32avpllCh_ctrl_P_SYNC1(r32,v)                 _BFSET_(r32,19, 0,v)

    #define     w32avpllCh_ctrl2                               {\
            UNSG32 uctrl_P_SYNC1                               : 20;\
            UNSG32 RSVDx8_b20                                  : 12;\
          }
    union { UNSG32 u32avpllCh_ctrl2;
            struct w32avpllCh_ctrl2;
          };
    #define   GET32avpllCh_ctrl_P_SYNC2(r32)                   _BFGET_(r32,19, 0)
    #define   SET32avpllCh_ctrl_P_SYNC2(r32,v)                 _BFSET_(r32,19, 0,v)

    #define   GET32avpllCh_ctrl_RESET(r32)                     _BFGET_(r32,20,20)
    #define   SET32avpllCh_ctrl_RESET(r32,v)                   _BFSET_(r32,20,20,v)
    #define   GET16avpllCh_ctrl_RESET(r16)                     _BFGET_(r16, 4, 4)
    #define   SET16avpllCh_ctrl_RESET(r16,v)                   _BFSET_(r16, 4, 4,v)

    #define   GET32avpllCh_ctrl_RESERVE_IN(r32)                _BFGET_(r32,22,21)
    #define   SET32avpllCh_ctrl_RESERVE_IN(r32,v)              _BFSET_(r32,22,21,v)
    #define   GET16avpllCh_ctrl_RESERVE_IN(r16)                _BFGET_(r16, 6, 5)
    #define   SET16avpllCh_ctrl_RESERVE_IN(r16,v)              _BFSET_(r16, 6, 5,v)

    #define     w32avpllCh_ctrl3                               {\
            UNSG32 uctrl_P_SYNC2                               : 20;\
            UNSG32 uctrl_RESET                                 :  1;\
            UNSG32 uctrl_RESERVE_IN                            :  2;\
            UNSG32 RSVDxC_b23                                  :  9;\
          }
    union { UNSG32 u32avpllCh_ctrl3;
            struct w32avpllCh_ctrl3;
          };
    ///////////////////////////////////////////////////////////
    } SIE_avpllCh;

    typedef union  T32avpllCh_ctrl
          { UNSG32 u32;
            struct w32avpllCh_ctrl;
                 } T32avpllCh_ctrl;
    typedef union  T32avpllCh_ctrl1
          { UNSG32 u32;
            struct w32avpllCh_ctrl1;
                 } T32avpllCh_ctrl1;
    typedef union  T32avpllCh_ctrl2
          { UNSG32 u32;
            struct w32avpllCh_ctrl2;
                 } T32avpllCh_ctrl2;
    typedef union  T32avpllCh_ctrl3
          { UNSG32 u32;
            struct w32avpllCh_ctrl3;
                 } T32avpllCh_ctrl3;
    ///////////////////////////////////////////////////////////

    typedef union  TavpllCh_ctrl
          { UNSG32 u32[4];
            struct {
            struct w32avpllCh_ctrl;
            struct w32avpllCh_ctrl1;
            struct w32avpllCh_ctrl2;
            struct w32avpllCh_ctrl3;
                   };
                 } TavpllCh_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 avpllCh_drvrd(SIE_avpllCh *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 avpllCh_drvwr(SIE_avpllCh *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void avpllCh_reset(SIE_avpllCh *p);
     SIGN32 avpllCh_cmp  (SIE_avpllCh *p, SIE_avpllCh *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define avpllCh_check(p,pie,pfx,hLOG) avpllCh_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define avpllCh_print(p,    pfx,hLOG) avpllCh_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: avpllCh
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE avpllCh8                biu              (4,4)
///     ###
///     * AVPLL control signals for channel 8 (Channel inside PLL)
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrl                 (P-)
///               %unsigned 13 POSTDIV                   0x0
///               %unsigned 1  POSTDIV_0P5               0x0
///                                    ###
///                                    * Audio clock divider program
///                                    * 1, When POSTDIV_CX[12:0]=
///                                    * 0 0000 0000 0000, then disable post divider
///                                    * 2, When POSTDIV_CX[12:0]>0:
///                                    * if POSTDIV_0P5_CX=0:
///                                    * Divider=POSTDIV_CX[12:0],
///                                    * if POSTDIV_0P5_CX=1:
///                                    * Divider=POSTDIV_CX[12:0]+0.5
///                                    * For C1-C7 only
///                                    ###
///               %unsigned 1  EN_DPLL                   0x0
///                                    ###
///                                    * 0: disable channel CX's DPLL
///                                    * 1: enable channel CX's DPLL
///                                    ###
///               %unsigned 2  EN_LP                     0x0
///                                    ###
///                                    * EN_LP_CX[1:0] FREQ_OFFSET   CK_INTG
///                                    * 00        X             CK_SSC
///                                    * 01         X*2          CK_SSC/2
///                                    * 10         X              CK_SSC
///                                    * 11          X*4                CK_SSC/4
///                                    ###
///               %%        15         # Stuffing bits...
///     # 0x00004 ctrl1                
///               %unsigned 19 FREQ_OFFSET               0x0
///                                    ###
///                                    * [18] is sign bit
///                                    * 0: PI's Frequency down
///                                    * 1: PI's Frequency up
///                                    * [17:0]: 1 LSB -> 0.25ppm,
///                                    * up to 5%
///                                    ###
///               %unsigned 1  FREQ_OFFSET_READY         0x0
///                                    ###
///                                    * Frequency offset value readiness
///                                    * indicator for FREQ_OFFSET_CX [18:0],
///                                    * the pulse need to be longer
///                                    * than 320/Fvco. For Fvco=3GHz,
///                                    * the pulse with should > 172ns;
///                                    * For Fvco=1.5GHz, pulse width >344ns
///                                    ###
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * 0: power down channel CX
///                                    * 1: power up channel CX
///                                    ###
///               %unsigned 1  PU_OFST_CTRL              0x1
///                                    ###
///                                    * 0: power down FREQ_OFFS
///                                    * 1: power up FREQ_OFFSET
///                                    ###
///               %%        10         # Stuffing bits...
///     # 0x00008 ctrl2                
///               %unsigned 20 P_SYNC1                   0x10
///                                    ###
///                                    * Set DPLL's reference divider
///                                    * Divider= P_SYNC1_CX[19:0]
///                                    * It is forbidden when N<16
///                                    ###
///               %%        12         # Stuffing bits...
///     # 0x0000C ctrl3                
///               %unsigned 20 P_SYNC2                   0x10
///                                    ###
///                                    * Set DPLL's feedback divider
///                                    * Divider= P_SYNC2_CX[19:0]
///                                    * It is forbidden when N<16
///                                    ###
///               %unsigned 1  RESET                     0x0
///                                    ###
///                                    * Reset channel CX logic:
///                                    * 0: not reset
///                                    * 1: active reset
///                                    ###
///               %unsigned 2  RESERVE_IN                0x1
///               %%        9          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      82b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_avpllCh8
#define h_avpllCh8 (){}

    #define     RA_avpllCh8_ctrl                               0x0000

    #define     BA_avpllCh8_ctrl_POSTDIV                       0x0000
    #define     B16avpllCh8_ctrl_POSTDIV                       0x0000
    #define   LSb32avpllCh8_ctrl_POSTDIV                          0
    #define   LSb16avpllCh8_ctrl_POSTDIV                          0
    #define       bavpllCh8_ctrl_POSTDIV                       13
    #define   MSK32avpllCh8_ctrl_POSTDIV                          0x00001FFF

    #define     BA_avpllCh8_ctrl_POSTDIV_0P5                   0x0001
    #define     B16avpllCh8_ctrl_POSTDIV_0P5                   0x0000
    #define   LSb32avpllCh8_ctrl_POSTDIV_0P5                      13
    #define   LSb16avpllCh8_ctrl_POSTDIV_0P5                      13
    #define       bavpllCh8_ctrl_POSTDIV_0P5                   1
    #define   MSK32avpllCh8_ctrl_POSTDIV_0P5                      0x00002000

    #define     BA_avpllCh8_ctrl_EN_DPLL                       0x0001
    #define     B16avpllCh8_ctrl_EN_DPLL                       0x0000
    #define   LSb32avpllCh8_ctrl_EN_DPLL                          14
    #define   LSb16avpllCh8_ctrl_EN_DPLL                          14
    #define       bavpllCh8_ctrl_EN_DPLL                       1
    #define   MSK32avpllCh8_ctrl_EN_DPLL                          0x00004000

    #define     BA_avpllCh8_ctrl_EN_LP                         0x0001
    #define     B16avpllCh8_ctrl_EN_LP                         0x0000
    #define   LSb32avpllCh8_ctrl_EN_LP                            15
    #define   LSb16avpllCh8_ctrl_EN_LP                            15
    #define       bavpllCh8_ctrl_EN_LP                         2
    #define   MSK32avpllCh8_ctrl_EN_LP                            0x00018000

    #define     RA_avpllCh8_ctrl1                              0x0004

    #define     BA_avpllCh8_ctrl_FREQ_OFFSET                   0x0004
    #define     B16avpllCh8_ctrl_FREQ_OFFSET                   0x0004
    #define   LSb32avpllCh8_ctrl_FREQ_OFFSET                      0
    #define   LSb16avpllCh8_ctrl_FREQ_OFFSET                      0
    #define       bavpllCh8_ctrl_FREQ_OFFSET                   19
    #define   MSK32avpllCh8_ctrl_FREQ_OFFSET                      0x0007FFFF

    #define     BA_avpllCh8_ctrl_FREQ_OFFSET_READY             0x0006
    #define     B16avpllCh8_ctrl_FREQ_OFFSET_READY             0x0006
    #define   LSb32avpllCh8_ctrl_FREQ_OFFSET_READY                19
    #define   LSb16avpllCh8_ctrl_FREQ_OFFSET_READY                3
    #define       bavpllCh8_ctrl_FREQ_OFFSET_READY             1
    #define   MSK32avpllCh8_ctrl_FREQ_OFFSET_READY                0x00080000

    #define     BA_avpllCh8_ctrl_PU                            0x0006
    #define     B16avpllCh8_ctrl_PU                            0x0006
    #define   LSb32avpllCh8_ctrl_PU                               20
    #define   LSb16avpllCh8_ctrl_PU                               4
    #define       bavpllCh8_ctrl_PU                            1
    #define   MSK32avpllCh8_ctrl_PU                               0x00100000

    #define     BA_avpllCh8_ctrl_PU_OFST_CTRL                  0x0006
    #define     B16avpllCh8_ctrl_PU_OFST_CTRL                  0x0006
    #define   LSb32avpllCh8_ctrl_PU_OFST_CTRL                     21
    #define   LSb16avpllCh8_ctrl_PU_OFST_CTRL                     5
    #define       bavpllCh8_ctrl_PU_OFST_CTRL                  1
    #define   MSK32avpllCh8_ctrl_PU_OFST_CTRL                     0x00200000

    #define     RA_avpllCh8_ctrl2                              0x0008

    #define     BA_avpllCh8_ctrl_P_SYNC1                       0x0008
    #define     B16avpllCh8_ctrl_P_SYNC1                       0x0008
    #define   LSb32avpllCh8_ctrl_P_SYNC1                          0
    #define   LSb16avpllCh8_ctrl_P_SYNC1                          0
    #define       bavpllCh8_ctrl_P_SYNC1                       20
    #define   MSK32avpllCh8_ctrl_P_SYNC1                          0x000FFFFF

    #define     RA_avpllCh8_ctrl3                              0x000C

    #define     BA_avpllCh8_ctrl_P_SYNC2                       0x000C
    #define     B16avpllCh8_ctrl_P_SYNC2                       0x000C
    #define   LSb32avpllCh8_ctrl_P_SYNC2                          0
    #define   LSb16avpllCh8_ctrl_P_SYNC2                          0
    #define       bavpllCh8_ctrl_P_SYNC2                       20
    #define   MSK32avpllCh8_ctrl_P_SYNC2                          0x000FFFFF

    #define     BA_avpllCh8_ctrl_RESET                         0x000E
    #define     B16avpllCh8_ctrl_RESET                         0x000E
    #define   LSb32avpllCh8_ctrl_RESET                            20
    #define   LSb16avpllCh8_ctrl_RESET                            4
    #define       bavpllCh8_ctrl_RESET                         1
    #define   MSK32avpllCh8_ctrl_RESET                            0x00100000

    #define     BA_avpllCh8_ctrl_RESERVE_IN                    0x000E
    #define     B16avpllCh8_ctrl_RESERVE_IN                    0x000E
    #define   LSb32avpllCh8_ctrl_RESERVE_IN                       21
    #define   LSb16avpllCh8_ctrl_RESERVE_IN                       5
    #define       bavpllCh8_ctrl_RESERVE_IN                    2
    #define   MSK32avpllCh8_ctrl_RESERVE_IN                       0x00600000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_avpllCh8 {
    ///////////////////////////////////////////////////////////
    #define   GET32avpllCh8_ctrl_POSTDIV(r32)                  _BFGET_(r32,12, 0)
    #define   SET32avpllCh8_ctrl_POSTDIV(r32,v)                _BFSET_(r32,12, 0,v)
    #define   GET16avpllCh8_ctrl_POSTDIV(r16)                  _BFGET_(r16,12, 0)
    #define   SET16avpllCh8_ctrl_POSTDIV(r16,v)                _BFSET_(r16,12, 0,v)

    #define   GET32avpllCh8_ctrl_POSTDIV_0P5(r32)              _BFGET_(r32,13,13)
    #define   SET32avpllCh8_ctrl_POSTDIV_0P5(r32,v)            _BFSET_(r32,13,13,v)
    #define   GET16avpllCh8_ctrl_POSTDIV_0P5(r16)              _BFGET_(r16,13,13)
    #define   SET16avpllCh8_ctrl_POSTDIV_0P5(r16,v)            _BFSET_(r16,13,13,v)

    #define   GET32avpllCh8_ctrl_EN_DPLL(r32)                  _BFGET_(r32,14,14)
    #define   SET32avpllCh8_ctrl_EN_DPLL(r32,v)                _BFSET_(r32,14,14,v)
    #define   GET16avpllCh8_ctrl_EN_DPLL(r16)                  _BFGET_(r16,14,14)
    #define   SET16avpllCh8_ctrl_EN_DPLL(r16,v)                _BFSET_(r16,14,14,v)

    #define   GET32avpllCh8_ctrl_EN_LP(r32)                    _BFGET_(r32,16,15)
    #define   SET32avpllCh8_ctrl_EN_LP(r32,v)                  _BFSET_(r32,16,15,v)

    #define     w32avpllCh8_ctrl                               {\
            UNSG32 uctrl_POSTDIV                               : 13;\
            UNSG32 uctrl_POSTDIV_0P5                           :  1;\
            UNSG32 uctrl_EN_DPLL                               :  1;\
            UNSG32 uctrl_EN_LP                                 :  2;\
            UNSG32 RSVDx0_b17                                  : 15;\
          }
    union { UNSG32 u32avpllCh8_ctrl;
            struct w32avpllCh8_ctrl;
          };
    #define   GET32avpllCh8_ctrl_FREQ_OFFSET(r32)              _BFGET_(r32,18, 0)
    #define   SET32avpllCh8_ctrl_FREQ_OFFSET(r32,v)            _BFSET_(r32,18, 0,v)

    #define   GET32avpllCh8_ctrl_FREQ_OFFSET_READY(r32)        _BFGET_(r32,19,19)
    #define   SET32avpllCh8_ctrl_FREQ_OFFSET_READY(r32,v)      _BFSET_(r32,19,19,v)
    #define   GET16avpllCh8_ctrl_FREQ_OFFSET_READY(r16)        _BFGET_(r16, 3, 3)
    #define   SET16avpllCh8_ctrl_FREQ_OFFSET_READY(r16,v)      _BFSET_(r16, 3, 3,v)

    #define   GET32avpllCh8_ctrl_PU(r32)                       _BFGET_(r32,20,20)
    #define   SET32avpllCh8_ctrl_PU(r32,v)                     _BFSET_(r32,20,20,v)
    #define   GET16avpllCh8_ctrl_PU(r16)                       _BFGET_(r16, 4, 4)
    #define   SET16avpllCh8_ctrl_PU(r16,v)                     _BFSET_(r16, 4, 4,v)

    #define   GET32avpllCh8_ctrl_PU_OFST_CTRL(r32)             _BFGET_(r32,21,21)
    #define   SET32avpllCh8_ctrl_PU_OFST_CTRL(r32,v)           _BFSET_(r32,21,21,v)
    #define   GET16avpllCh8_ctrl_PU_OFST_CTRL(r16)             _BFGET_(r16, 5, 5)
    #define   SET16avpllCh8_ctrl_PU_OFST_CTRL(r16,v)           _BFSET_(r16, 5, 5,v)

    #define     w32avpllCh8_ctrl1                              {\
            UNSG32 uctrl_FREQ_OFFSET                           : 19;\
            UNSG32 uctrl_FREQ_OFFSET_READY                     :  1;\
            UNSG32 uctrl_PU                                    :  1;\
            UNSG32 uctrl_PU_OFST_CTRL                          :  1;\
            UNSG32 RSVDx4_b22                                  : 10;\
          }
    union { UNSG32 u32avpllCh8_ctrl1;
            struct w32avpllCh8_ctrl1;
          };
    #define   GET32avpllCh8_ctrl_P_SYNC1(r32)                  _BFGET_(r32,19, 0)
    #define   SET32avpllCh8_ctrl_P_SYNC1(r32,v)                _BFSET_(r32,19, 0,v)

    #define     w32avpllCh8_ctrl2                              {\
            UNSG32 uctrl_P_SYNC1                               : 20;\
            UNSG32 RSVDx8_b20                                  : 12;\
          }
    union { UNSG32 u32avpllCh8_ctrl2;
            struct w32avpllCh8_ctrl2;
          };
    #define   GET32avpllCh8_ctrl_P_SYNC2(r32)                  _BFGET_(r32,19, 0)
    #define   SET32avpllCh8_ctrl_P_SYNC2(r32,v)                _BFSET_(r32,19, 0,v)

    #define   GET32avpllCh8_ctrl_RESET(r32)                    _BFGET_(r32,20,20)
    #define   SET32avpllCh8_ctrl_RESET(r32,v)                  _BFSET_(r32,20,20,v)
    #define   GET16avpllCh8_ctrl_RESET(r16)                    _BFGET_(r16, 4, 4)
    #define   SET16avpllCh8_ctrl_RESET(r16,v)                  _BFSET_(r16, 4, 4,v)

    #define   GET32avpllCh8_ctrl_RESERVE_IN(r32)               _BFGET_(r32,22,21)
    #define   SET32avpllCh8_ctrl_RESERVE_IN(r32,v)             _BFSET_(r32,22,21,v)
    #define   GET16avpllCh8_ctrl_RESERVE_IN(r16)               _BFGET_(r16, 6, 5)
    #define   SET16avpllCh8_ctrl_RESERVE_IN(r16,v)             _BFSET_(r16, 6, 5,v)

    #define     w32avpllCh8_ctrl3                              {\
            UNSG32 uctrl_P_SYNC2                               : 20;\
            UNSG32 uctrl_RESET                                 :  1;\
            UNSG32 uctrl_RESERVE_IN                            :  2;\
            UNSG32 RSVDxC_b23                                  :  9;\
          }
    union { UNSG32 u32avpllCh8_ctrl3;
            struct w32avpllCh8_ctrl3;
          };
    ///////////////////////////////////////////////////////////
    } SIE_avpllCh8;

    typedef union  T32avpllCh8_ctrl
          { UNSG32 u32;
            struct w32avpllCh8_ctrl;
                 } T32avpllCh8_ctrl;
    typedef union  T32avpllCh8_ctrl1
          { UNSG32 u32;
            struct w32avpllCh8_ctrl1;
                 } T32avpllCh8_ctrl1;
    typedef union  T32avpllCh8_ctrl2
          { UNSG32 u32;
            struct w32avpllCh8_ctrl2;
                 } T32avpllCh8_ctrl2;
    typedef union  T32avpllCh8_ctrl3
          { UNSG32 u32;
            struct w32avpllCh8_ctrl3;
                 } T32avpllCh8_ctrl3;
    ///////////////////////////////////////////////////////////

    typedef union  TavpllCh8_ctrl
          { UNSG32 u32[4];
            struct {
            struct w32avpllCh8_ctrl;
            struct w32avpllCh8_ctrl1;
            struct w32avpllCh8_ctrl2;
            struct w32avpllCh8_ctrl3;
                   };
                 } TavpllCh8_ctrl;

    ///////////////////////////////////////////////////////////
     SIGN32 avpllCh8_drvrd(SIE_avpllCh8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 avpllCh8_drvwr(SIE_avpllCh8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void avpllCh8_reset(SIE_avpllCh8 *p);
     SIGN32 avpllCh8_cmp  (SIE_avpllCh8 *p, SIE_avpllCh8 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define avpllCh8_check(p,pie,pfx,hLOG) avpllCh8_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define avpllCh8_print(p,    pfx,hLOG) avpllCh8_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: avpllCh8
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE avPll                   biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 ctrlPLL              (P-)
///               ###
///               * AVPLL Control Registers
///               * The AVPLL is designed to generate clocks for digital Audio and Video applications. It consists of only one core PLL which generates clock outputs covering the frequency range from 1.5GHz to 2.97GHz. There are totally 8 PIs, with 1 PI used inside PLL, 7 PIs used in output clock channels. The PI used inside PLL is referred to C8.
///               * Other PIs in each channel provides 7 channels output clock signal:
///               * a), The other five channels (C1..C5) can be programmed as audio/video clock. They are single end output clock.
///               * b), In contrast with C1..C5, CHANNEL6 provide clock of lower jitter. They are proposed to be programmed as video DAC or other higher performance clock (Of course, they also can be programmed as audio clock). C6 are differential output clock.
///               * c), CHANNEL7 (C7) is dedicated HDMI clock. C7 is differential output clock.
///               ###
///               %unsigned 1  RESET                     0x1
///                                    ###
///                                    * 0
///                                    * De-asserted
///                                    * 1
///                                    * Asserted
///                                    * Reset PLL
///                                    * Must be de-asserted after 10us from the time when PU is set to 1.
///                                    * Note: Firmware should first set PU then de-assert PLL reset after 10us and then enable the video and audio clocks using the clk enable register.
///                                    ###
///               %unsigned 1  PU                        0x0
///                                    ###
///                                    * Power up signal for AVPLL
///                                    * 0=power down
///                                    * 1=active
///                                    * When PU=0, all circuits including IVREF, INTP, REGULATOR and PLL are POWERED OFF
///                                    ###
///               %unsigned 3  PLL_VDDRA_SEL             0x3
///                                    ###
///                                    * Select gate voltage for
///                                    * VDDBUF
///                                    * 000   1,16v
///                                    * 001   1.18v
///                                    * 010   1.20v
///                                    * 011   1.22v
///                                    * 100      1.24v
///                                    * 101     1.26v
///                                    * 110      1.28v
///                                    * 111   1.30v
///                                    * VGATE=1.22V,
///                                    * range from 1.16-1.3,
///                                    * 20mv/step
///                                    ###
///               %unsigned 1  REG_RING_EXTRA_I_EN       0x0
///                                    ###
///                                    * "1" : turn on extra current for
///                                    * the oscillator of vdda23 charge pump
///                                    ###
///               %unsigned 2  VCO_REF1P45_SEL           0x1
///                                    ###
///                                    * Select VREF1P0V_VCO1P45
///                                    * 00        0.975v
///                                    * 01        1.0v
///                                    * 10        1.025v
///                                    * 11 1.05v
///                                    ###
///               %unsigned 2  VDDA23_PUMP_SEL           0x1
///                                    ###
///                                    * Select VREF0P96_VDDA23PUMP
///                                    * 00 0.925v
///                                    * 01 0.95v
///                                    * 10 1.0v
///                                    * 11 1.05v
///                                    ###
///               %unsigned 3  VDDBUF_ADJ                0x0
///                                    ###
///                                    * Adjust for VDDVDOFBUF
///                                    * VDDBUF_ADJ[2:1] are reserved
///                                    * VDDBUF[0]:
///                                    * 0: vddvcofbuf=vddvco
///                                    * 1: vddvcofbuf=1.08*vddvco
///                                    ###
///               %unsigned 4  VDDL                      0xC
///                                    ###
///                                    * Internal regulated VDD supply
///                                    * 0001:   0.88v
///                                    * 0010:   0.90v
///                                    * 0011:   0.92v
///                                    * 0100:   0.94 v
///                                    * 0101:   0.96 v
///                                    * 0110:   0.98 v
///                                    * 0111:   1.00 v
///                                    * 1000:   1.02 v
///                                    * 1001:   1.04 v
///                                    * 1010:   1.06 v
///                                    * 1011:   1.08 v
///                                    * 1100:   1.10v
///                                    * 1101:   1.12v
///                                    * 1110:   1.14v
///                                    * 1111:   1.16v
///                                    ###
///               %unsigned 9  FBDIV                     0x10
///                                    ###
///                                    * Feedback clock divider select
///                                    * Divider= FBDIV [8:0], start from 16.
///                                    ###
///               %unsigned 4  ICP                       0x5
///                                    ###
///                                    * Charge-pump current con
///                                    * 0000   30uA
///                                    * 0001   37.5uA
///                                    * 0010   45uA
///                                    * 0011   52.5uA
///                                    * 0100   60uA
///                                    * 0101   75uA
///                                    * 0110   90uA
///                                    * 0111   105uA
///                                    * 1000   120uA
///                                    * 1001   150uA
///                                    * 1010   180uA
///                                    * 1011   210uA
///                                    * 1100   240uA
///                                    * 1101   300uA
///                                    * 1110   360uA
///                                    * 1111   420uA
///                                    ###
///               %unsigned 1  PLL_LPFC2_LESS            0x0
///                                    ###
///                                    * PLL_LPFC1=1, C2=1.2pf
///                                    * PLL_LPFC1=0, C2=1.4pf
///                                    ###
///               %%        1          # Stuffing bits...
///     # 0x00004 ctrlPLL1             
///               %unsigned 7  REFDIV                    0x1
///                                    ###
///                                    * Reference clock divider select
///                                    * [5:0]
///                                    * 0000000: not used.
///                                    * 0000001: div1.
///                                    * 0000010: div2
///                                    * 0000011: div3
///                                    * 0000100: div4
///                                    * .
///                                    * .
///                                    * Divider=REFDIV[5:0], for N>=2
///                                    ###
///               %unsigned 6  RESERVE_PLL_IN            0x0
///               %unsigned 4  EXT_SPEED                 0x0
///                                    ###
///                                    * External VCO speed control for
///                                    * different VCO frequencies. The following table is for simulation purpose, it matches the verilog model. The actual VCO speed setting is coming from the calibration result.
///                                    * SPEED[3:0]: typical freq range
///                                    * 0000   reserved
///                                    * 0001   reserved
///                                    * 0010   1.5G~1.7GHz
///                                    * 0011   1.7G~1.9GHz
///                                    * 0100   1.9G~2.1GHz
///                                    * 0101   2.1G~2.3GHz
///                                    * 0110   2.3G~2.45GHz
///                                    * 0111   2.45G~2.6GHz
///                                    * 1000   2.6G~2.75GHz
///                                    * 1001   2.75G~2.9GHz
///                                    * 1010   2.9G~3.0GHz
///                                    * 1011   reserved
///                                    * 1100   reserved
///                                    * 1101   reserved
///                                    * 1110   reserved
///                                    ###
///               %unsigned 4  SPEED_FBRES               0x0
///                                    ###
///                                    * External feedback resistor (VCO ring) set up bits
///                                    ###
///               %unsigned 1  UPDATE_SEL                0x0
///                                    ###
///                                    * Select the PLL update_rate:
///                                    * 0: 19M~26MHz
///                                    * for refclk 19.2M, 38.4M 2
///                                    * 1: 13MHz for refclk 13MHz
///                                    ###
///               %%        10         # Stuffing bits...
///     @ 0x00008 ctrlCAL              (P-)
///               %unsigned 9  CAL_FBDIV                 0x64
///                                    ###
///                                    * During calibration, count Fvco/CAL_FBDIV cycles in 1us, and compare it with SPEED_THRESH[5:0] to decide fvco is higher or lower than the expected frequency, set to dec100.
///                                    ###
///               %unsigned 1  EXT_SLLP_DAC_EN           0x0
///                                    ###
///                                    * 0: use the calibrated code SLLP_DAC_RD[6:0]
///                                    * 1: use the external input EXT_SLLP_DAC[6:0]
///                                    ###
///               %unsigned 1  EXT_SPEED_EN              0x0
///                                    ###
///                                    * 0: use the calibrated code SPEED_RD[3:0]
///                                    * 1: use the external input SPEED[3:0]
///                                    ###
///               %unsigned 1  EXT_SP_FBRES_EN           0x0
///                                    ###
///                                    * External speed enable pin
///                                    * 0: take SPEED_RD[3:0] for feedback resistor
///                                    * 1: take SPEED_FBRES[3:0]
///                                    ###
///               %unsigned 5  PLL_CALCLK_DIV            0x19
///                                    ###
///                                    * Divider to generate around 1MHz calibration clock from the internal update clock:
///                                    * 00000: not used.
///                                    * 00001: div1.
///                                    * 00010: div2
///                                    * 00011: div3
///                                    * 00100: div4
///                                    * .. .
///                                    * Divider=PLL_CALCLK_DIV[4:0], for N>=2
///                                    * D13 for refclk 13MHz
///                                    * D19 for refclk 19.2MHz/38.4MHz
///                                    * D25 for refclk 25MHz
///                                    * D26 for refclk 26MHz
///                                    ###
///               %unsigned 1  PLL_CAL_START             0x0
///                                    ###
///                                    * Rising edge to start PLL calibration
///                                    ###
///               %unsigned 4  REG_SETTLE_LIMIT          0x8
///                                    ###
///                                    * Select waiting time before calibration logic start to take action after PLL_CAL_START is issued, default is 8us
///                                    ###
///               %unsigned 1  SEL_VTHVCOCONT            0x1
///                                    ###
///                                    * Select the source of threshold
///                                    * 0: select IPP+IPTAT generated threshold voltage
///                                    * 1: select IPP generated threshold voltage
///                                    ###
///               %unsigned 6  SPEED_THRESH              0x1E
///                                    ###
///                                    * Digital counter threshold for VCO speed setting calibration loop, threshold value varies with the target VCO frequency.
///                                    * if CAL_FBDIV=dec100,
///                                    * speed_thresh[5:0]   VCO_frequency
///                                    * dec15                    1.5GHz
///                                    * dec20                    2.0GHz
///                                    * dec30                    3.0GHz
///                                    ###
///               %unsigned 2  VCON_SEL                  0x2
///                                    ###
///                                    * Used to set VCON value during PLL Open loop calibration
///                                    * 00: 0.6
///                                    * 01: 0.65
///                                    * 10: 0.7
///                                    * 11: 0.75
///                                    ###
///               %%        1          # Stuffing bits...
///     # 0x0000C ctrlCAL1             
///               %unsigned 7  EXT_SLLP_DAC              0x32
///                                    ###
///                                    * External input used to set VDDVCO value. Used to set Vcon reference value during PLL normal calibration.
///                                    * Vcon: 0.35 + 0.01125*VSET_SLLP_DAC[6:0] default: 01,1011 -------- Vcon=0.697V
///                                    ###
///               %unsigned 2  VTH_VCO_CAL               0x2
///                                    ###
///                                    * 2 bits to select the threshold for calibrated VDDVCO voltage
///                                    * When SEL_VTHVCOCON=1, select IPP generated threshold:
///                                    * 00 1.05v
///                                    * 01 1.075v
///                                    * 10 1.1v
///                                    * 11 1.125v
///                                    * When SEL_VTHVCOCON=0, select IPP portion for IPP+IPTAT generated threshold:
///                                    * 00: 31uA
///                                    * 01: 33uA
///                                    * 10: 35uA
///                                    * 11: 37uA
///                                    ###
///               %unsigned 2  VTH_VCO_PTAT              0x1
///                                    ###
///                                    * 2 bits to select IPTAT curren
///                                    * IPTAT current
///                                    * 00      0uA
///                                    * 01      2uA
///                                    * 10         4uA
///                                    * 11         6uA
///                                    ###
///               %%        21         # Stuffing bits...
///     @ 0x00010 ctrlSlowLoop         (P-)
///               %unsigned 3  PW_SLLP                   0x3
///                                    ###
///                                    * This set of signals define PLL
///                                    * 000: 2T_vco
///                                    * 001: 4T_vco
///                                    * 010: 8T_vco
///                                    * 011: 16T_vco
///                                    * 100: 32T_vco
///                                    * 101: 64T_vco
///                                    * 110:128T_vco
///                                    * 111:256T_vco
///                                    ###
///               %unsigned 1  SLLP_CLK_DIV5EN           0x0
///                                    ###
///                                    * Enable slow loop
///                                    * clock=200KHz, default is 100KHz
///                                    * SLLP_CLK_DIV5EN=0,
///                                    * slow loop clock is 100KHz;
///                                    * SLLP_CLK_DIV5EN=1,
///                                    * slow loop clock is 200KHz
///                                    ###
///               %unsigned 1  SLLP_EN_DIS               0x0
///                                    ###
///                                    * 0: Enable slow loop
///                                    * 1: Disable slow loop
///                                    ###
///               %unsigned 3  SLLP_PSF_LEVEL            0x1
///                                    ###
///                                    * IPP current control to genera
///                                    * SLLP_PSF_LEVEL[2] is re
///                                    * [1:0]   IPP current
///                                    * 00             2uA
///                                    * 01             4uA
///                                    * 10              6uA
///                                    * 11              8uA
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00014 ctrlINTP             (P-)
///               %unsigned 1  CLK_DET_EN                0x1
///                                    ###
///                                    * Enables PI output clock for internal reset circuit.
///                                    * 0: disable
///                                    * 1: enable
///                                    ###
///               %unsigned 2  DPHER_DLY_SEL             0x2
///                                    ###
///                                    * Tuning DPHERCK delay
///                                    * 00: smallest
///                                    * 01
///                                    * 10
///                                    * 11: largest
///                                    ###
///               %unsigned 4  INTPI                     0xB
///                                    ###
///                                    * Select PI bias current:
///                                    * INTPI[3:0] CURRENT VCO's Freq
///                                    * 0000       20uA
///                                    * 0001       22.5uA
///                                    * 0010       25uA     1.5GHz
///                                    * 0011       27.5uA
///                                    * 0100       30uA
///                                    * 0101       32.5uA 2.0GHz
///                                    * 0110       35uA
///                                    * 0111       37.5uA 2.3Ghz
///                                    * 1000       40uA
///                                    * 1001       42.5uA     2.65GHz
///                                    * 1010       45uA
///                                    * 1011       47.5uA     3GHz
///                                    * 1100       50uA
///                                    * 1101       52.5uA     3.3GHz
///                                    * 1110       55uA
///                                    * 1111      57.5uA     3.6GHz
///                                    * Use high frequency band on boarder
///                                    * Default setting is for 3.0GHz
///                                    ###
///               %unsigned 3  INTPR                     0x2
///                                    ###
///                                    * Used for PI Rload resistor se
///                                    * INTPR[2:0]   RES   VCO's Freq
///                                    * 000       650
///                                    * 001      750    3.3~4GHz
///                                    * 010       900   2.65~3.3GHz
///                                    * 011       1150 2.0~2.65GHz
///                                    * 100       1500   1.5~2GHz
///                                    * 101        2300   1~1.5GHz
///                                    * 110        4600
///                                    * 111          RESERVED
///                                    * Use high frequency band on boarder
///                                    * Default setting is for 3.0GHz
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x00018 ctrlC8AddOn          (P-)
///               %unsigned 1  MASTER_SLAVEB             0x1
///                                    ###
///                                    * Used to sync frequencies
///                                    * if using 2 PLLs.
///                                    * 1 ' Master PLL
///                                    * 0 ' Slave PLL
///                                    ###
///               %unsigned 2  MODE                      0x0
///                                    ###
///                                    * Mode[1:0] cali_done fbclk
///                                    * 0x         0         fb_vco
///                                    * 0x         1         fb_pi
///                                    * 10         x         fb_vco
///                                    * 11         x         fb_pi
///                                    ###
///               %%        29         # Stuffing bits...
///     @ 0x0001C                      (P)
///     # 0x0001C C1                   
///               $avpllCh             C1                REG          
///     @ 0x0002C                      (P)
///     # 0x0002C C2                   
///               $avpllCh             C2                REG          
///     @ 0x0003C                      (P)
///     # 0x0003C C3                   
///               $avpllCh             C3                REG          
///     @ 0x0004C                      (P)
///     # 0x0004C C4                   
///               $avpllCh             C4                REG          
///     @ 0x0005C                      (P)
///     # 0x0005C C5                   
///               $avpllCh             C5                REG          
///     @ 0x0006C                      (P)
///     # 0x0006C C6                   
///               $avpllCh             C6                REG          
///     @ 0x0007C                      (P)
///     # 0x0007C C7                   
///               $avpllCh             C7                REG          
///     @ 0x0008C                      (P)
///     # 0x0008C C8                   
///               $avpllCh8            C8                REG          
///     @ 0x0009C ctrlTest             (P-)
///               %unsigned 1  CLKOUT_TST_EN             0x0
///                                    ###
///                                    * 0: CLKOUT_TST=0
///                                    * 1: Enable CLKOUT_TST output
///                                    ###
///               %unsigned 6  TEST_MON                  0x0
///                                    ###
///                                    * TEST_MON[5]:
///                                    * 0: TP = high Z
///                                    * 1: enable test point
///                                    * If TEST_MON[5]=1 :
///                                    * TEST_MON[4:0]      TP
///                                    * 0 0000              DVSS
///                                    * 0 0001              AVDD
///                                    * 0 0010              AVSS
///                                    * 0 0011~0 1001       AVSS
///                                    * 0 1010           TP_V0P7
///                                    * 0 1011           TP_VCOVTH
///                                    * 0 1100           VDDR_VCOFBUF
///                                    * 0 1101           TP_CHGPMP_
///                                    * 0 1110           TP_CHGPMP_
///                                    * 0 1111           VDDR_REFDIV
///                                    * 1 0000           VDDR_FBDIV
///                                    * 1 0001           VDDR_INTP_LA
///                                    * 1 0010           VDDR_INTP_LA
///                                    * 1 0011           TP_NBIAS_INTP
///                                    * 1 0100           DVDD
///                                    * 1 0101           PLL_LOCK
///                                    * 1 0110           PLL_CAL_EN
///                                    * 1 0111          PLL_CAL_DONE
///                                    * 1 1000          TP_VCTL_SLOW
///                                    * 1 1001          TP_VDAC_OUT
///                                    * 1 1010          TP_VDDVCO
///                                    * 1 1011          TP_VCON
///                                    * 1 1100~1 1111    AVSS
///                                    ###
///               %%        25         # Stuffing bits...
///     @ 0x000A0 status               (R-)
///               ###
///               * PLL status register
///               ###
///               %unsigned 1  PLL_LOCK                  
///                                    ###
///                                    * PLL Lock
///                                    * 1: PLL locked.
///                                    * 0: PLL not locked.
///                                    ###
///               %unsigned 6  RESERVE_PLL_OUT           
///               %unsigned 9  FBDIV_RD                  
///                                    ###
///                                    * Output register bits for calibrated FBDIV[8:0]
///                                    ###
///               %unsigned 1  PLL_CAL_DONE              
///                                    ###
///                                    * Rising edge indicate the end of PLL calibration
///                                    ###
///               %unsigned 6  SPEED_CNT                 
///                                    ###
///                                    * Output register bits for speed counter in calibration
///                                    ###
///               %unsigned 4  SPEED_RD                  
///                                    ###
///                                    * Output register bits for calibrated SPEED[3:0]
///                                    ###
///               %%        5          # Stuffing bits...
///     # 0x000A4 status1              
///               %unsigned 7  SLLP_DAC_RD               
///                                    ###
///                                    * Output register bits for calibrated SLLP_DAC[6:0]
///                                    ###
///               %%        25         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     168B, bits:     813b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_avPll
#define h_avPll (){}

    #define     RA_avPll_ctrlPLL                               0x0000

    #define     BA_avPll_ctrlPLL_RESET                         0x0000
    #define     B16avPll_ctrlPLL_RESET                         0x0000
    #define   LSb32avPll_ctrlPLL_RESET                            0
    #define   LSb16avPll_ctrlPLL_RESET                            0
    #define       bavPll_ctrlPLL_RESET                         1
    #define   MSK32avPll_ctrlPLL_RESET                            0x00000001

    #define     BA_avPll_ctrlPLL_PU                            0x0000
    #define     B16avPll_ctrlPLL_PU                            0x0000
    #define   LSb32avPll_ctrlPLL_PU                               1
    #define   LSb16avPll_ctrlPLL_PU                               1
    #define       bavPll_ctrlPLL_PU                            1
    #define   MSK32avPll_ctrlPLL_PU                               0x00000002

    #define     BA_avPll_ctrlPLL_PLL_VDDRA_SEL                 0x0000
    #define     B16avPll_ctrlPLL_PLL_VDDRA_SEL                 0x0000
    #define   LSb32avPll_ctrlPLL_PLL_VDDRA_SEL                    2
    #define   LSb16avPll_ctrlPLL_PLL_VDDRA_SEL                    2
    #define       bavPll_ctrlPLL_PLL_VDDRA_SEL                 3
    #define   MSK32avPll_ctrlPLL_PLL_VDDRA_SEL                    0x0000001C

    #define     BA_avPll_ctrlPLL_REG_RING_EXTRA_I_EN           0x0000
    #define     B16avPll_ctrlPLL_REG_RING_EXTRA_I_EN           0x0000
    #define   LSb32avPll_ctrlPLL_REG_RING_EXTRA_I_EN              5
    #define   LSb16avPll_ctrlPLL_REG_RING_EXTRA_I_EN              5
    #define       bavPll_ctrlPLL_REG_RING_EXTRA_I_EN           1
    #define   MSK32avPll_ctrlPLL_REG_RING_EXTRA_I_EN              0x00000020

    #define     BA_avPll_ctrlPLL_VCO_REF1P45_SEL               0x0000
    #define     B16avPll_ctrlPLL_VCO_REF1P45_SEL               0x0000
    #define   LSb32avPll_ctrlPLL_VCO_REF1P45_SEL                  6
    #define   LSb16avPll_ctrlPLL_VCO_REF1P45_SEL                  6
    #define       bavPll_ctrlPLL_VCO_REF1P45_SEL               2
    #define   MSK32avPll_ctrlPLL_VCO_REF1P45_SEL                  0x000000C0

    #define     BA_avPll_ctrlPLL_VDDA23_PUMP_SEL               0x0001
    #define     B16avPll_ctrlPLL_VDDA23_PUMP_SEL               0x0000
    #define   LSb32avPll_ctrlPLL_VDDA23_PUMP_SEL                  8
    #define   LSb16avPll_ctrlPLL_VDDA23_PUMP_SEL                  8
    #define       bavPll_ctrlPLL_VDDA23_PUMP_SEL               2
    #define   MSK32avPll_ctrlPLL_VDDA23_PUMP_SEL                  0x00000300

    #define     BA_avPll_ctrlPLL_VDDBUF_ADJ                    0x0001
    #define     B16avPll_ctrlPLL_VDDBUF_ADJ                    0x0000
    #define   LSb32avPll_ctrlPLL_VDDBUF_ADJ                       10
    #define   LSb16avPll_ctrlPLL_VDDBUF_ADJ                       10
    #define       bavPll_ctrlPLL_VDDBUF_ADJ                    3
    #define   MSK32avPll_ctrlPLL_VDDBUF_ADJ                       0x00001C00

    #define     BA_avPll_ctrlPLL_VDDL                          0x0001
    #define     B16avPll_ctrlPLL_VDDL                          0x0000
    #define   LSb32avPll_ctrlPLL_VDDL                             13
    #define   LSb16avPll_ctrlPLL_VDDL                             13
    #define       bavPll_ctrlPLL_VDDL                          4
    #define   MSK32avPll_ctrlPLL_VDDL                             0x0001E000

    #define     BA_avPll_ctrlPLL_FBDIV                         0x0002
    #define     B16avPll_ctrlPLL_FBDIV                         0x0002
    #define   LSb32avPll_ctrlPLL_FBDIV                            17
    #define   LSb16avPll_ctrlPLL_FBDIV                            1
    #define       bavPll_ctrlPLL_FBDIV                         9
    #define   MSK32avPll_ctrlPLL_FBDIV                            0x03FE0000

    #define     BA_avPll_ctrlPLL_ICP                           0x0003
    #define     B16avPll_ctrlPLL_ICP                           0x0002
    #define   LSb32avPll_ctrlPLL_ICP                              26
    #define   LSb16avPll_ctrlPLL_ICP                              10
    #define       bavPll_ctrlPLL_ICP                           4
    #define   MSK32avPll_ctrlPLL_ICP                              0x3C000000

    #define     BA_avPll_ctrlPLL_PLL_LPFC2_LESS                0x0003
    #define     B16avPll_ctrlPLL_PLL_LPFC2_LESS                0x0002
    #define   LSb32avPll_ctrlPLL_PLL_LPFC2_LESS                   30
    #define   LSb16avPll_ctrlPLL_PLL_LPFC2_LESS                   14
    #define       bavPll_ctrlPLL_PLL_LPFC2_LESS                1
    #define   MSK32avPll_ctrlPLL_PLL_LPFC2_LESS                   0x40000000

    #define     RA_avPll_ctrlPLL1                              0x0004

    #define     BA_avPll_ctrlPLL_REFDIV                        0x0004
    #define     B16avPll_ctrlPLL_REFDIV                        0x0004
    #define   LSb32avPll_ctrlPLL_REFDIV                           0
    #define   LSb16avPll_ctrlPLL_REFDIV                           0
    #define       bavPll_ctrlPLL_REFDIV                        7
    #define   MSK32avPll_ctrlPLL_REFDIV                           0x0000007F

    #define     BA_avPll_ctrlPLL_RESERVE_PLL_IN                0x0004
    #define     B16avPll_ctrlPLL_RESERVE_PLL_IN                0x0004
    #define   LSb32avPll_ctrlPLL_RESERVE_PLL_IN                   7
    #define   LSb16avPll_ctrlPLL_RESERVE_PLL_IN                   7
    #define       bavPll_ctrlPLL_RESERVE_PLL_IN                6
    #define   MSK32avPll_ctrlPLL_RESERVE_PLL_IN                   0x00001F80

    #define     BA_avPll_ctrlPLL_EXT_SPEED                     0x0005
    #define     B16avPll_ctrlPLL_EXT_SPEED                     0x0004
    #define   LSb32avPll_ctrlPLL_EXT_SPEED                        13
    #define   LSb16avPll_ctrlPLL_EXT_SPEED                        13
    #define       bavPll_ctrlPLL_EXT_SPEED                     4
    #define   MSK32avPll_ctrlPLL_EXT_SPEED                        0x0001E000

    #define     BA_avPll_ctrlPLL_SPEED_FBRES                   0x0006
    #define     B16avPll_ctrlPLL_SPEED_FBRES                   0x0006
    #define   LSb32avPll_ctrlPLL_SPEED_FBRES                      17
    #define   LSb16avPll_ctrlPLL_SPEED_FBRES                      1
    #define       bavPll_ctrlPLL_SPEED_FBRES                   4
    #define   MSK32avPll_ctrlPLL_SPEED_FBRES                      0x001E0000

    #define     BA_avPll_ctrlPLL_UPDATE_SEL                    0x0006
    #define     B16avPll_ctrlPLL_UPDATE_SEL                    0x0006
    #define   LSb32avPll_ctrlPLL_UPDATE_SEL                       21
    #define   LSb16avPll_ctrlPLL_UPDATE_SEL                       5
    #define       bavPll_ctrlPLL_UPDATE_SEL                    1
    #define   MSK32avPll_ctrlPLL_UPDATE_SEL                       0x00200000
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_ctrlCAL                               0x0008

    #define     BA_avPll_ctrlCAL_CAL_FBDIV                     0x0008
    #define     B16avPll_ctrlCAL_CAL_FBDIV                     0x0008
    #define   LSb32avPll_ctrlCAL_CAL_FBDIV                        0
    #define   LSb16avPll_ctrlCAL_CAL_FBDIV                        0
    #define       bavPll_ctrlCAL_CAL_FBDIV                     9
    #define   MSK32avPll_ctrlCAL_CAL_FBDIV                        0x000001FF

    #define     BA_avPll_ctrlCAL_EXT_SLLP_DAC_EN               0x0009
    #define     B16avPll_ctrlCAL_EXT_SLLP_DAC_EN               0x0008
    #define   LSb32avPll_ctrlCAL_EXT_SLLP_DAC_EN                  9
    #define   LSb16avPll_ctrlCAL_EXT_SLLP_DAC_EN                  9
    #define       bavPll_ctrlCAL_EXT_SLLP_DAC_EN               1
    #define   MSK32avPll_ctrlCAL_EXT_SLLP_DAC_EN                  0x00000200

    #define     BA_avPll_ctrlCAL_EXT_SPEED_EN                  0x0009
    #define     B16avPll_ctrlCAL_EXT_SPEED_EN                  0x0008
    #define   LSb32avPll_ctrlCAL_EXT_SPEED_EN                     10
    #define   LSb16avPll_ctrlCAL_EXT_SPEED_EN                     10
    #define       bavPll_ctrlCAL_EXT_SPEED_EN                  1
    #define   MSK32avPll_ctrlCAL_EXT_SPEED_EN                     0x00000400

    #define     BA_avPll_ctrlCAL_EXT_SP_FBRES_EN               0x0009
    #define     B16avPll_ctrlCAL_EXT_SP_FBRES_EN               0x0008
    #define   LSb32avPll_ctrlCAL_EXT_SP_FBRES_EN                  11
    #define   LSb16avPll_ctrlCAL_EXT_SP_FBRES_EN                  11
    #define       bavPll_ctrlCAL_EXT_SP_FBRES_EN               1
    #define   MSK32avPll_ctrlCAL_EXT_SP_FBRES_EN                  0x00000800

    #define     BA_avPll_ctrlCAL_PLL_CALCLK_DIV                0x0009
    #define     B16avPll_ctrlCAL_PLL_CALCLK_DIV                0x0008
    #define   LSb32avPll_ctrlCAL_PLL_CALCLK_DIV                   12
    #define   LSb16avPll_ctrlCAL_PLL_CALCLK_DIV                   12
    #define       bavPll_ctrlCAL_PLL_CALCLK_DIV                5
    #define   MSK32avPll_ctrlCAL_PLL_CALCLK_DIV                   0x0001F000

    #define     BA_avPll_ctrlCAL_PLL_CAL_START                 0x000A
    #define     B16avPll_ctrlCAL_PLL_CAL_START                 0x000A
    #define   LSb32avPll_ctrlCAL_PLL_CAL_START                    17
    #define   LSb16avPll_ctrlCAL_PLL_CAL_START                    1
    #define       bavPll_ctrlCAL_PLL_CAL_START                 1
    #define   MSK32avPll_ctrlCAL_PLL_CAL_START                    0x00020000

    #define     BA_avPll_ctrlCAL_REG_SETTLE_LIMIT              0x000A
    #define     B16avPll_ctrlCAL_REG_SETTLE_LIMIT              0x000A
    #define   LSb32avPll_ctrlCAL_REG_SETTLE_LIMIT                 18
    #define   LSb16avPll_ctrlCAL_REG_SETTLE_LIMIT                 2
    #define       bavPll_ctrlCAL_REG_SETTLE_LIMIT              4
    #define   MSK32avPll_ctrlCAL_REG_SETTLE_LIMIT                 0x003C0000

    #define     BA_avPll_ctrlCAL_SEL_VTHVCOCONT                0x000A
    #define     B16avPll_ctrlCAL_SEL_VTHVCOCONT                0x000A
    #define   LSb32avPll_ctrlCAL_SEL_VTHVCOCONT                   22
    #define   LSb16avPll_ctrlCAL_SEL_VTHVCOCONT                   6
    #define       bavPll_ctrlCAL_SEL_VTHVCOCONT                1
    #define   MSK32avPll_ctrlCAL_SEL_VTHVCOCONT                   0x00400000

    #define     BA_avPll_ctrlCAL_SPEED_THRESH                  0x000A
    #define     B16avPll_ctrlCAL_SPEED_THRESH                  0x000A
    #define   LSb32avPll_ctrlCAL_SPEED_THRESH                     23
    #define   LSb16avPll_ctrlCAL_SPEED_THRESH                     7
    #define       bavPll_ctrlCAL_SPEED_THRESH                  6
    #define   MSK32avPll_ctrlCAL_SPEED_THRESH                     0x1F800000

    #define     BA_avPll_ctrlCAL_VCON_SEL                      0x000B
    #define     B16avPll_ctrlCAL_VCON_SEL                      0x000A
    #define   LSb32avPll_ctrlCAL_VCON_SEL                         29
    #define   LSb16avPll_ctrlCAL_VCON_SEL                         13
    #define       bavPll_ctrlCAL_VCON_SEL                      2
    #define   MSK32avPll_ctrlCAL_VCON_SEL                         0x60000000

    #define     RA_avPll_ctrlCAL1                              0x000C

    #define     BA_avPll_ctrlCAL_EXT_SLLP_DAC                  0x000C
    #define     B16avPll_ctrlCAL_EXT_SLLP_DAC                  0x000C
    #define   LSb32avPll_ctrlCAL_EXT_SLLP_DAC                     0
    #define   LSb16avPll_ctrlCAL_EXT_SLLP_DAC                     0
    #define       bavPll_ctrlCAL_EXT_SLLP_DAC                  7
    #define   MSK32avPll_ctrlCAL_EXT_SLLP_DAC                     0x0000007F

    #define     BA_avPll_ctrlCAL_VTH_VCO_CAL                   0x000C
    #define     B16avPll_ctrlCAL_VTH_VCO_CAL                   0x000C
    #define   LSb32avPll_ctrlCAL_VTH_VCO_CAL                      7
    #define   LSb16avPll_ctrlCAL_VTH_VCO_CAL                      7
    #define       bavPll_ctrlCAL_VTH_VCO_CAL                   2
    #define   MSK32avPll_ctrlCAL_VTH_VCO_CAL                      0x00000180

    #define     BA_avPll_ctrlCAL_VTH_VCO_PTAT                  0x000D
    #define     B16avPll_ctrlCAL_VTH_VCO_PTAT                  0x000C
    #define   LSb32avPll_ctrlCAL_VTH_VCO_PTAT                     9
    #define   LSb16avPll_ctrlCAL_VTH_VCO_PTAT                     9
    #define       bavPll_ctrlCAL_VTH_VCO_PTAT                  2
    #define   MSK32avPll_ctrlCAL_VTH_VCO_PTAT                     0x00000600
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_ctrlSlowLoop                          0x0010

    #define     BA_avPll_ctrlSlowLoop_PW_SLLP                  0x0010
    #define     B16avPll_ctrlSlowLoop_PW_SLLP                  0x0010
    #define   LSb32avPll_ctrlSlowLoop_PW_SLLP                     0
    #define   LSb16avPll_ctrlSlowLoop_PW_SLLP                     0
    #define       bavPll_ctrlSlowLoop_PW_SLLP                  3
    #define   MSK32avPll_ctrlSlowLoop_PW_SLLP                     0x00000007

    #define     BA_avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN          0x0010
    #define     B16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN          0x0010
    #define   LSb32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN             3
    #define   LSb16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN             3
    #define       bavPll_ctrlSlowLoop_SLLP_CLK_DIV5EN          1
    #define   MSK32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN             0x00000008

    #define     BA_avPll_ctrlSlowLoop_SLLP_EN_DIS              0x0010
    #define     B16avPll_ctrlSlowLoop_SLLP_EN_DIS              0x0010
    #define   LSb32avPll_ctrlSlowLoop_SLLP_EN_DIS                 4
    #define   LSb16avPll_ctrlSlowLoop_SLLP_EN_DIS                 4
    #define       bavPll_ctrlSlowLoop_SLLP_EN_DIS              1
    #define   MSK32avPll_ctrlSlowLoop_SLLP_EN_DIS                 0x00000010

    #define     BA_avPll_ctrlSlowLoop_SLLP_PSF_LEVEL           0x0010
    #define     B16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL           0x0010
    #define   LSb32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL              5
    #define   LSb16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL              5
    #define       bavPll_ctrlSlowLoop_SLLP_PSF_LEVEL           3
    #define   MSK32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL              0x000000E0
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_ctrlINTP                              0x0014

    #define     BA_avPll_ctrlINTP_CLK_DET_EN                   0x0014
    #define     B16avPll_ctrlINTP_CLK_DET_EN                   0x0014
    #define   LSb32avPll_ctrlINTP_CLK_DET_EN                      0
    #define   LSb16avPll_ctrlINTP_CLK_DET_EN                      0
    #define       bavPll_ctrlINTP_CLK_DET_EN                   1
    #define   MSK32avPll_ctrlINTP_CLK_DET_EN                      0x00000001

    #define     BA_avPll_ctrlINTP_DPHER_DLY_SEL                0x0014
    #define     B16avPll_ctrlINTP_DPHER_DLY_SEL                0x0014
    #define   LSb32avPll_ctrlINTP_DPHER_DLY_SEL                   1
    #define   LSb16avPll_ctrlINTP_DPHER_DLY_SEL                   1
    #define       bavPll_ctrlINTP_DPHER_DLY_SEL                2
    #define   MSK32avPll_ctrlINTP_DPHER_DLY_SEL                   0x00000006

    #define     BA_avPll_ctrlINTP_INTPI                        0x0014
    #define     B16avPll_ctrlINTP_INTPI                        0x0014
    #define   LSb32avPll_ctrlINTP_INTPI                           3
    #define   LSb16avPll_ctrlINTP_INTPI                           3
    #define       bavPll_ctrlINTP_INTPI                        4
    #define   MSK32avPll_ctrlINTP_INTPI                           0x00000078

    #define     BA_avPll_ctrlINTP_INTPR                        0x0014
    #define     B16avPll_ctrlINTP_INTPR                        0x0014
    #define   LSb32avPll_ctrlINTP_INTPR                           7
    #define   LSb16avPll_ctrlINTP_INTPR                           7
    #define       bavPll_ctrlINTP_INTPR                        3
    #define   MSK32avPll_ctrlINTP_INTPR                           0x00000380
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_ctrlC8AddOn                           0x0018

    #define     BA_avPll_ctrlC8AddOn_MASTER_SLAVEB             0x0018
    #define     B16avPll_ctrlC8AddOn_MASTER_SLAVEB             0x0018
    #define   LSb32avPll_ctrlC8AddOn_MASTER_SLAVEB                0
    #define   LSb16avPll_ctrlC8AddOn_MASTER_SLAVEB                0
    #define       bavPll_ctrlC8AddOn_MASTER_SLAVEB             1
    #define   MSK32avPll_ctrlC8AddOn_MASTER_SLAVEB                0x00000001

    #define     BA_avPll_ctrlC8AddOn_MODE                      0x0018
    #define     B16avPll_ctrlC8AddOn_MODE                      0x0018
    #define   LSb32avPll_ctrlC8AddOn_MODE                         1
    #define   LSb16avPll_ctrlC8AddOn_MODE                         1
    #define       bavPll_ctrlC8AddOn_MODE                      2
    #define   MSK32avPll_ctrlC8AddOn_MODE                         0x00000006
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C1                                    0x001C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C2                                    0x002C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C3                                    0x003C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C4                                    0x004C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C5                                    0x005C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C6                                    0x006C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C7                                    0x007C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_C8                                    0x008C
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_ctrlTest                              0x009C

    #define     BA_avPll_ctrlTest_CLKOUT_TST_EN                0x009C
    #define     B16avPll_ctrlTest_CLKOUT_TST_EN                0x009C
    #define   LSb32avPll_ctrlTest_CLKOUT_TST_EN                   0
    #define   LSb16avPll_ctrlTest_CLKOUT_TST_EN                   0
    #define       bavPll_ctrlTest_CLKOUT_TST_EN                1
    #define   MSK32avPll_ctrlTest_CLKOUT_TST_EN                   0x00000001

    #define     BA_avPll_ctrlTest_TEST_MON                     0x009C
    #define     B16avPll_ctrlTest_TEST_MON                     0x009C
    #define   LSb32avPll_ctrlTest_TEST_MON                        1
    #define   LSb16avPll_ctrlTest_TEST_MON                        1
    #define       bavPll_ctrlTest_TEST_MON                     6
    #define   MSK32avPll_ctrlTest_TEST_MON                        0x0000007E
    ///////////////////////////////////////////////////////////
    #define     RA_avPll_status                                0x00A0

    #define     BA_avPll_status_PLL_LOCK                       0x00A0
    #define     B16avPll_status_PLL_LOCK                       0x00A0
    #define   LSb32avPll_status_PLL_LOCK                          0
    #define   LSb16avPll_status_PLL_LOCK                          0
    #define       bavPll_status_PLL_LOCK                       1
    #define   MSK32avPll_status_PLL_LOCK                          0x00000001

    #define     BA_avPll_status_RESERVE_PLL_OUT                0x00A0
    #define     B16avPll_status_RESERVE_PLL_OUT                0x00A0
    #define   LSb32avPll_status_RESERVE_PLL_OUT                   1
    #define   LSb16avPll_status_RESERVE_PLL_OUT                   1
    #define       bavPll_status_RESERVE_PLL_OUT                6
    #define   MSK32avPll_status_RESERVE_PLL_OUT                   0x0000007E

    #define     BA_avPll_status_FBDIV_RD                       0x00A0
    #define     B16avPll_status_FBDIV_RD                       0x00A0
    #define   LSb32avPll_status_FBDIV_RD                          7
    #define   LSb16avPll_status_FBDIV_RD                          7
    #define       bavPll_status_FBDIV_RD                       9
    #define   MSK32avPll_status_FBDIV_RD                          0x0000FF80

    #define     BA_avPll_status_PLL_CAL_DONE                   0x00A2
    #define     B16avPll_status_PLL_CAL_DONE                   0x00A2
    #define   LSb32avPll_status_PLL_CAL_DONE                      16
    #define   LSb16avPll_status_PLL_CAL_DONE                      0
    #define       bavPll_status_PLL_CAL_DONE                   1
    #define   MSK32avPll_status_PLL_CAL_DONE                      0x00010000

    #define     BA_avPll_status_SPEED_CNT                      0x00A2
    #define     B16avPll_status_SPEED_CNT                      0x00A2
    #define   LSb32avPll_status_SPEED_CNT                         17
    #define   LSb16avPll_status_SPEED_CNT                         1
    #define       bavPll_status_SPEED_CNT                      6
    #define   MSK32avPll_status_SPEED_CNT                         0x007E0000

    #define     BA_avPll_status_SPEED_RD                       0x00A2
    #define     B16avPll_status_SPEED_RD                       0x00A2
    #define   LSb32avPll_status_SPEED_RD                          23
    #define   LSb16avPll_status_SPEED_RD                          7
    #define       bavPll_status_SPEED_RD                       4
    #define   MSK32avPll_status_SPEED_RD                          0x07800000

    #define     RA_avPll_status1                               0x00A4

    #define     BA_avPll_status_SLLP_DAC_RD                    0x00A4
    #define     B16avPll_status_SLLP_DAC_RD                    0x00A4
    #define   LSb32avPll_status_SLLP_DAC_RD                       0
    #define   LSb16avPll_status_SLLP_DAC_RD                       0
    #define       bavPll_status_SLLP_DAC_RD                    7
    #define   MSK32avPll_status_SLLP_DAC_RD                       0x0000007F
    ///////////////////////////////////////////////////////////

    typedef struct SIE_avPll {
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_ctrlPLL_RESET(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32avPll_ctrlPLL_RESET(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16avPll_ctrlPLL_RESET(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16avPll_ctrlPLL_RESET(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32avPll_ctrlPLL_PU(r32)                       _BFGET_(r32, 1, 1)
    #define   SET32avPll_ctrlPLL_PU(r32,v)                     _BFSET_(r32, 1, 1,v)
    #define   GET16avPll_ctrlPLL_PU(r16)                       _BFGET_(r16, 1, 1)
    #define   SET16avPll_ctrlPLL_PU(r16,v)                     _BFSET_(r16, 1, 1,v)

    #define   GET32avPll_ctrlPLL_PLL_VDDRA_SEL(r32)            _BFGET_(r32, 4, 2)
    #define   SET32avPll_ctrlPLL_PLL_VDDRA_SEL(r32,v)          _BFSET_(r32, 4, 2,v)
    #define   GET16avPll_ctrlPLL_PLL_VDDRA_SEL(r16)            _BFGET_(r16, 4, 2)
    #define   SET16avPll_ctrlPLL_PLL_VDDRA_SEL(r16,v)          _BFSET_(r16, 4, 2,v)

    #define   GET32avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r32)      _BFGET_(r32, 5, 5)
    #define   SET32avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r32,v)    _BFSET_(r32, 5, 5,v)
    #define   GET16avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r16)      _BFGET_(r16, 5, 5)
    #define   SET16avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r16,v)    _BFSET_(r16, 5, 5,v)

    #define   GET32avPll_ctrlPLL_VCO_REF1P45_SEL(r32)          _BFGET_(r32, 7, 6)
    #define   SET32avPll_ctrlPLL_VCO_REF1P45_SEL(r32,v)        _BFSET_(r32, 7, 6,v)
    #define   GET16avPll_ctrlPLL_VCO_REF1P45_SEL(r16)          _BFGET_(r16, 7, 6)
    #define   SET16avPll_ctrlPLL_VCO_REF1P45_SEL(r16,v)        _BFSET_(r16, 7, 6,v)

    #define   GET32avPll_ctrlPLL_VDDA23_PUMP_SEL(r32)          _BFGET_(r32, 9, 8)
    #define   SET32avPll_ctrlPLL_VDDA23_PUMP_SEL(r32,v)        _BFSET_(r32, 9, 8,v)
    #define   GET16avPll_ctrlPLL_VDDA23_PUMP_SEL(r16)          _BFGET_(r16, 9, 8)
    #define   SET16avPll_ctrlPLL_VDDA23_PUMP_SEL(r16,v)        _BFSET_(r16, 9, 8,v)

    #define   GET32avPll_ctrlPLL_VDDBUF_ADJ(r32)               _BFGET_(r32,12,10)
    #define   SET32avPll_ctrlPLL_VDDBUF_ADJ(r32,v)             _BFSET_(r32,12,10,v)
    #define   GET16avPll_ctrlPLL_VDDBUF_ADJ(r16)               _BFGET_(r16,12,10)
    #define   SET16avPll_ctrlPLL_VDDBUF_ADJ(r16,v)             _BFSET_(r16,12,10,v)

    #define   GET32avPll_ctrlPLL_VDDL(r32)                     _BFGET_(r32,16,13)
    #define   SET32avPll_ctrlPLL_VDDL(r32,v)                   _BFSET_(r32,16,13,v)

    #define   GET32avPll_ctrlPLL_FBDIV(r32)                    _BFGET_(r32,25,17)
    #define   SET32avPll_ctrlPLL_FBDIV(r32,v)                  _BFSET_(r32,25,17,v)
    #define   GET16avPll_ctrlPLL_FBDIV(r16)                    _BFGET_(r16, 9, 1)
    #define   SET16avPll_ctrlPLL_FBDIV(r16,v)                  _BFSET_(r16, 9, 1,v)

    #define   GET32avPll_ctrlPLL_ICP(r32)                      _BFGET_(r32,29,26)
    #define   SET32avPll_ctrlPLL_ICP(r32,v)                    _BFSET_(r32,29,26,v)
    #define   GET16avPll_ctrlPLL_ICP(r16)                      _BFGET_(r16,13,10)
    #define   SET16avPll_ctrlPLL_ICP(r16,v)                    _BFSET_(r16,13,10,v)

    #define   GET32avPll_ctrlPLL_PLL_LPFC2_LESS(r32)           _BFGET_(r32,30,30)
    #define   SET32avPll_ctrlPLL_PLL_LPFC2_LESS(r32,v)         _BFSET_(r32,30,30,v)
    #define   GET16avPll_ctrlPLL_PLL_LPFC2_LESS(r16)           _BFGET_(r16,14,14)
    #define   SET16avPll_ctrlPLL_PLL_LPFC2_LESS(r16,v)         _BFSET_(r16,14,14,v)

    #define     w32avPll_ctrlPLL                               {\
            UNSG32 uctrlPLL_RESET                              :  1;\
            UNSG32 uctrlPLL_PU                                 :  1;\
            UNSG32 uctrlPLL_PLL_VDDRA_SEL                      :  3;\
            UNSG32 uctrlPLL_REG_RING_EXTRA_I_EN                :  1;\
            UNSG32 uctrlPLL_VCO_REF1P45_SEL                    :  2;\
            UNSG32 uctrlPLL_VDDA23_PUMP_SEL                    :  2;\
            UNSG32 uctrlPLL_VDDBUF_ADJ                         :  3;\
            UNSG32 uctrlPLL_VDDL                               :  4;\
            UNSG32 uctrlPLL_FBDIV                              :  9;\
            UNSG32 uctrlPLL_ICP                                :  4;\
            UNSG32 uctrlPLL_PLL_LPFC2_LESS                     :  1;\
            UNSG32 RSVDx0_b31                                  :  1;\
          }
    union { UNSG32 u32avPll_ctrlPLL;
            struct w32avPll_ctrlPLL;
          };
    #define   GET32avPll_ctrlPLL_REFDIV(r32)                   _BFGET_(r32, 6, 0)
    #define   SET32avPll_ctrlPLL_REFDIV(r32,v)                 _BFSET_(r32, 6, 0,v)
    #define   GET16avPll_ctrlPLL_REFDIV(r16)                   _BFGET_(r16, 6, 0)
    #define   SET16avPll_ctrlPLL_REFDIV(r16,v)                 _BFSET_(r16, 6, 0,v)

    #define   GET32avPll_ctrlPLL_RESERVE_PLL_IN(r32)           _BFGET_(r32,12, 7)
    #define   SET32avPll_ctrlPLL_RESERVE_PLL_IN(r32,v)         _BFSET_(r32,12, 7,v)
    #define   GET16avPll_ctrlPLL_RESERVE_PLL_IN(r16)           _BFGET_(r16,12, 7)
    #define   SET16avPll_ctrlPLL_RESERVE_PLL_IN(r16,v)         _BFSET_(r16,12, 7,v)

    #define   GET32avPll_ctrlPLL_EXT_SPEED(r32)                _BFGET_(r32,16,13)
    #define   SET32avPll_ctrlPLL_EXT_SPEED(r32,v)              _BFSET_(r32,16,13,v)

    #define   GET32avPll_ctrlPLL_SPEED_FBRES(r32)              _BFGET_(r32,20,17)
    #define   SET32avPll_ctrlPLL_SPEED_FBRES(r32,v)            _BFSET_(r32,20,17,v)
    #define   GET16avPll_ctrlPLL_SPEED_FBRES(r16)              _BFGET_(r16, 4, 1)
    #define   SET16avPll_ctrlPLL_SPEED_FBRES(r16,v)            _BFSET_(r16, 4, 1,v)

    #define   GET32avPll_ctrlPLL_UPDATE_SEL(r32)               _BFGET_(r32,21,21)
    #define   SET32avPll_ctrlPLL_UPDATE_SEL(r32,v)             _BFSET_(r32,21,21,v)
    #define   GET16avPll_ctrlPLL_UPDATE_SEL(r16)               _BFGET_(r16, 5, 5)
    #define   SET16avPll_ctrlPLL_UPDATE_SEL(r16,v)             _BFSET_(r16, 5, 5,v)

    #define     w32avPll_ctrlPLL1                              {\
            UNSG32 uctrlPLL_REFDIV                             :  7;\
            UNSG32 uctrlPLL_RESERVE_PLL_IN                     :  6;\
            UNSG32 uctrlPLL_EXT_SPEED                          :  4;\
            UNSG32 uctrlPLL_SPEED_FBRES                        :  4;\
            UNSG32 uctrlPLL_UPDATE_SEL                         :  1;\
            UNSG32 RSVDx4_b22                                  : 10;\
          }
    union { UNSG32 u32avPll_ctrlPLL1;
            struct w32avPll_ctrlPLL1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_ctrlCAL_CAL_FBDIV(r32)                _BFGET_(r32, 8, 0)
    #define   SET32avPll_ctrlCAL_CAL_FBDIV(r32,v)              _BFSET_(r32, 8, 0,v)
    #define   GET16avPll_ctrlCAL_CAL_FBDIV(r16)                _BFGET_(r16, 8, 0)
    #define   SET16avPll_ctrlCAL_CAL_FBDIV(r16,v)              _BFSET_(r16, 8, 0,v)

    #define   GET32avPll_ctrlCAL_EXT_SLLP_DAC_EN(r32)          _BFGET_(r32, 9, 9)
    #define   SET32avPll_ctrlCAL_EXT_SLLP_DAC_EN(r32,v)        _BFSET_(r32, 9, 9,v)
    #define   GET16avPll_ctrlCAL_EXT_SLLP_DAC_EN(r16)          _BFGET_(r16, 9, 9)
    #define   SET16avPll_ctrlCAL_EXT_SLLP_DAC_EN(r16,v)        _BFSET_(r16, 9, 9,v)

    #define   GET32avPll_ctrlCAL_EXT_SPEED_EN(r32)             _BFGET_(r32,10,10)
    #define   SET32avPll_ctrlCAL_EXT_SPEED_EN(r32,v)           _BFSET_(r32,10,10,v)
    #define   GET16avPll_ctrlCAL_EXT_SPEED_EN(r16)             _BFGET_(r16,10,10)
    #define   SET16avPll_ctrlCAL_EXT_SPEED_EN(r16,v)           _BFSET_(r16,10,10,v)

    #define   GET32avPll_ctrlCAL_EXT_SP_FBRES_EN(r32)          _BFGET_(r32,11,11)
    #define   SET32avPll_ctrlCAL_EXT_SP_FBRES_EN(r32,v)        _BFSET_(r32,11,11,v)
    #define   GET16avPll_ctrlCAL_EXT_SP_FBRES_EN(r16)          _BFGET_(r16,11,11)
    #define   SET16avPll_ctrlCAL_EXT_SP_FBRES_EN(r16,v)        _BFSET_(r16,11,11,v)

    #define   GET32avPll_ctrlCAL_PLL_CALCLK_DIV(r32)           _BFGET_(r32,16,12)
    #define   SET32avPll_ctrlCAL_PLL_CALCLK_DIV(r32,v)         _BFSET_(r32,16,12,v)

    #define   GET32avPll_ctrlCAL_PLL_CAL_START(r32)            _BFGET_(r32,17,17)
    #define   SET32avPll_ctrlCAL_PLL_CAL_START(r32,v)          _BFSET_(r32,17,17,v)
    #define   GET16avPll_ctrlCAL_PLL_CAL_START(r16)            _BFGET_(r16, 1, 1)
    #define   SET16avPll_ctrlCAL_PLL_CAL_START(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32avPll_ctrlCAL_REG_SETTLE_LIMIT(r32)         _BFGET_(r32,21,18)
    #define   SET32avPll_ctrlCAL_REG_SETTLE_LIMIT(r32,v)       _BFSET_(r32,21,18,v)
    #define   GET16avPll_ctrlCAL_REG_SETTLE_LIMIT(r16)         _BFGET_(r16, 5, 2)
    #define   SET16avPll_ctrlCAL_REG_SETTLE_LIMIT(r16,v)       _BFSET_(r16, 5, 2,v)

    #define   GET32avPll_ctrlCAL_SEL_VTHVCOCONT(r32)           _BFGET_(r32,22,22)
    #define   SET32avPll_ctrlCAL_SEL_VTHVCOCONT(r32,v)         _BFSET_(r32,22,22,v)
    #define   GET16avPll_ctrlCAL_SEL_VTHVCOCONT(r16)           _BFGET_(r16, 6, 6)
    #define   SET16avPll_ctrlCAL_SEL_VTHVCOCONT(r16,v)         _BFSET_(r16, 6, 6,v)

    #define   GET32avPll_ctrlCAL_SPEED_THRESH(r32)             _BFGET_(r32,28,23)
    #define   SET32avPll_ctrlCAL_SPEED_THRESH(r32,v)           _BFSET_(r32,28,23,v)
    #define   GET16avPll_ctrlCAL_SPEED_THRESH(r16)             _BFGET_(r16,12, 7)
    #define   SET16avPll_ctrlCAL_SPEED_THRESH(r16,v)           _BFSET_(r16,12, 7,v)

    #define   GET32avPll_ctrlCAL_VCON_SEL(r32)                 _BFGET_(r32,30,29)
    #define   SET32avPll_ctrlCAL_VCON_SEL(r32,v)               _BFSET_(r32,30,29,v)
    #define   GET16avPll_ctrlCAL_VCON_SEL(r16)                 _BFGET_(r16,14,13)
    #define   SET16avPll_ctrlCAL_VCON_SEL(r16,v)               _BFSET_(r16,14,13,v)

    #define     w32avPll_ctrlCAL                               {\
            UNSG32 uctrlCAL_CAL_FBDIV                          :  9;\
            UNSG32 uctrlCAL_EXT_SLLP_DAC_EN                    :  1;\
            UNSG32 uctrlCAL_EXT_SPEED_EN                       :  1;\
            UNSG32 uctrlCAL_EXT_SP_FBRES_EN                    :  1;\
            UNSG32 uctrlCAL_PLL_CALCLK_DIV                     :  5;\
            UNSG32 uctrlCAL_PLL_CAL_START                      :  1;\
            UNSG32 uctrlCAL_REG_SETTLE_LIMIT                   :  4;\
            UNSG32 uctrlCAL_SEL_VTHVCOCONT                     :  1;\
            UNSG32 uctrlCAL_SPEED_THRESH                       :  6;\
            UNSG32 uctrlCAL_VCON_SEL                           :  2;\
            UNSG32 RSVDx8_b31                                  :  1;\
          }
    union { UNSG32 u32avPll_ctrlCAL;
            struct w32avPll_ctrlCAL;
          };
    #define   GET32avPll_ctrlCAL_EXT_SLLP_DAC(r32)             _BFGET_(r32, 6, 0)
    #define   SET32avPll_ctrlCAL_EXT_SLLP_DAC(r32,v)           _BFSET_(r32, 6, 0,v)
    #define   GET16avPll_ctrlCAL_EXT_SLLP_DAC(r16)             _BFGET_(r16, 6, 0)
    #define   SET16avPll_ctrlCAL_EXT_SLLP_DAC(r16,v)           _BFSET_(r16, 6, 0,v)

    #define   GET32avPll_ctrlCAL_VTH_VCO_CAL(r32)              _BFGET_(r32, 8, 7)
    #define   SET32avPll_ctrlCAL_VTH_VCO_CAL(r32,v)            _BFSET_(r32, 8, 7,v)
    #define   GET16avPll_ctrlCAL_VTH_VCO_CAL(r16)              _BFGET_(r16, 8, 7)
    #define   SET16avPll_ctrlCAL_VTH_VCO_CAL(r16,v)            _BFSET_(r16, 8, 7,v)

    #define   GET32avPll_ctrlCAL_VTH_VCO_PTAT(r32)             _BFGET_(r32,10, 9)
    #define   SET32avPll_ctrlCAL_VTH_VCO_PTAT(r32,v)           _BFSET_(r32,10, 9,v)
    #define   GET16avPll_ctrlCAL_VTH_VCO_PTAT(r16)             _BFGET_(r16,10, 9)
    #define   SET16avPll_ctrlCAL_VTH_VCO_PTAT(r16,v)           _BFSET_(r16,10, 9,v)

    #define     w32avPll_ctrlCAL1                              {\
            UNSG32 uctrlCAL_EXT_SLLP_DAC                       :  7;\
            UNSG32 uctrlCAL_VTH_VCO_CAL                        :  2;\
            UNSG32 uctrlCAL_VTH_VCO_PTAT                       :  2;\
            UNSG32 RSVDxC_b11                                  : 21;\
          }
    union { UNSG32 u32avPll_ctrlCAL1;
            struct w32avPll_ctrlCAL1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_ctrlSlowLoop_PW_SLLP(r32)             _BFGET_(r32, 2, 0)
    #define   SET32avPll_ctrlSlowLoop_PW_SLLP(r32,v)           _BFSET_(r32, 2, 0,v)
    #define   GET16avPll_ctrlSlowLoop_PW_SLLP(r16)             _BFGET_(r16, 2, 0)
    #define   SET16avPll_ctrlSlowLoop_PW_SLLP(r16,v)           _BFSET_(r16, 2, 0,v)

    #define   GET32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r32)     _BFGET_(r32, 3, 3)
    #define   SET32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r32,v)   _BFSET_(r32, 3, 3,v)
    #define   GET16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r16)     _BFGET_(r16, 3, 3)
    #define   SET16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r16,v)   _BFSET_(r16, 3, 3,v)

    #define   GET32avPll_ctrlSlowLoop_SLLP_EN_DIS(r32)         _BFGET_(r32, 4, 4)
    #define   SET32avPll_ctrlSlowLoop_SLLP_EN_DIS(r32,v)       _BFSET_(r32, 4, 4,v)
    #define   GET16avPll_ctrlSlowLoop_SLLP_EN_DIS(r16)         _BFGET_(r16, 4, 4)
    #define   SET16avPll_ctrlSlowLoop_SLLP_EN_DIS(r16,v)       _BFSET_(r16, 4, 4,v)

    #define   GET32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r32)      _BFGET_(r32, 7, 5)
    #define   SET32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r32,v)    _BFSET_(r32, 7, 5,v)
    #define   GET16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r16)      _BFGET_(r16, 7, 5)
    #define   SET16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r16,v)    _BFSET_(r16, 7, 5,v)

    #define     w32avPll_ctrlSlowLoop                          {\
            UNSG32 uctrlSlowLoop_PW_SLLP                       :  3;\
            UNSG32 uctrlSlowLoop_SLLP_CLK_DIV5EN               :  1;\
            UNSG32 uctrlSlowLoop_SLLP_EN_DIS                   :  1;\
            UNSG32 uctrlSlowLoop_SLLP_PSF_LEVEL                :  3;\
            UNSG32 RSVDx10_b8                                  : 24;\
          }
    union { UNSG32 u32avPll_ctrlSlowLoop;
            struct w32avPll_ctrlSlowLoop;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_ctrlINTP_CLK_DET_EN(r32)              _BFGET_(r32, 0, 0)
    #define   SET32avPll_ctrlINTP_CLK_DET_EN(r32,v)            _BFSET_(r32, 0, 0,v)
    #define   GET16avPll_ctrlINTP_CLK_DET_EN(r16)              _BFGET_(r16, 0, 0)
    #define   SET16avPll_ctrlINTP_CLK_DET_EN(r16,v)            _BFSET_(r16, 0, 0,v)

    #define   GET32avPll_ctrlINTP_DPHER_DLY_SEL(r32)           _BFGET_(r32, 2, 1)
    #define   SET32avPll_ctrlINTP_DPHER_DLY_SEL(r32,v)         _BFSET_(r32, 2, 1,v)
    #define   GET16avPll_ctrlINTP_DPHER_DLY_SEL(r16)           _BFGET_(r16, 2, 1)
    #define   SET16avPll_ctrlINTP_DPHER_DLY_SEL(r16,v)         _BFSET_(r16, 2, 1,v)

    #define   GET32avPll_ctrlINTP_INTPI(r32)                   _BFGET_(r32, 6, 3)
    #define   SET32avPll_ctrlINTP_INTPI(r32,v)                 _BFSET_(r32, 6, 3,v)
    #define   GET16avPll_ctrlINTP_INTPI(r16)                   _BFGET_(r16, 6, 3)
    #define   SET16avPll_ctrlINTP_INTPI(r16,v)                 _BFSET_(r16, 6, 3,v)

    #define   GET32avPll_ctrlINTP_INTPR(r32)                   _BFGET_(r32, 9, 7)
    #define   SET32avPll_ctrlINTP_INTPR(r32,v)                 _BFSET_(r32, 9, 7,v)
    #define   GET16avPll_ctrlINTP_INTPR(r16)                   _BFGET_(r16, 9, 7)
    #define   SET16avPll_ctrlINTP_INTPR(r16,v)                 _BFSET_(r16, 9, 7,v)

    #define     w32avPll_ctrlINTP                              {\
            UNSG32 uctrlINTP_CLK_DET_EN                        :  1;\
            UNSG32 uctrlINTP_DPHER_DLY_SEL                     :  2;\
            UNSG32 uctrlINTP_INTPI                             :  4;\
            UNSG32 uctrlINTP_INTPR                             :  3;\
            UNSG32 RSVDx14_b10                                 : 22;\
          }
    union { UNSG32 u32avPll_ctrlINTP;
            struct w32avPll_ctrlINTP;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_ctrlC8AddOn_MASTER_SLAVEB(r32)        _BFGET_(r32, 0, 0)
    #define   SET32avPll_ctrlC8AddOn_MASTER_SLAVEB(r32,v)      _BFSET_(r32, 0, 0,v)
    #define   GET16avPll_ctrlC8AddOn_MASTER_SLAVEB(r16)        _BFGET_(r16, 0, 0)
    #define   SET16avPll_ctrlC8AddOn_MASTER_SLAVEB(r16,v)      _BFSET_(r16, 0, 0,v)

    #define   GET32avPll_ctrlC8AddOn_MODE(r32)                 _BFGET_(r32, 2, 1)
    #define   SET32avPll_ctrlC8AddOn_MODE(r32,v)               _BFSET_(r32, 2, 1,v)
    #define   GET16avPll_ctrlC8AddOn_MODE(r16)                 _BFGET_(r16, 2, 1)
    #define   SET16avPll_ctrlC8AddOn_MODE(r16,v)               _BFSET_(r16, 2, 1,v)

    #define     w32avPll_ctrlC8AddOn                           {\
            UNSG32 uctrlC8AddOn_MASTER_SLAVEB                  :  1;\
            UNSG32 uctrlC8AddOn_MODE                           :  2;\
            UNSG32 RSVDx18_b3                                  : 29;\
          }
    union { UNSG32 u32avPll_ctrlC8AddOn;
            struct w32avPll_ctrlC8AddOn;
          };
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C1;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C2;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C3;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C4;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C5;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C6;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh                                      ie_C7;
    ///////////////////////////////////////////////////////////
              SIE_avpllCh8                                     ie_C8;
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_ctrlTest_CLKOUT_TST_EN(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avPll_ctrlTest_CLKOUT_TST_EN(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avPll_ctrlTest_CLKOUT_TST_EN(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avPll_ctrlTest_CLKOUT_TST_EN(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avPll_ctrlTest_TEST_MON(r32)                _BFGET_(r32, 6, 1)
    #define   SET32avPll_ctrlTest_TEST_MON(r32,v)              _BFSET_(r32, 6, 1,v)
    #define   GET16avPll_ctrlTest_TEST_MON(r16)                _BFGET_(r16, 6, 1)
    #define   SET16avPll_ctrlTest_TEST_MON(r16,v)              _BFSET_(r16, 6, 1,v)

    #define     w32avPll_ctrlTest                              {\
            UNSG32 uctrlTest_CLKOUT_TST_EN                     :  1;\
            UNSG32 uctrlTest_TEST_MON                          :  6;\
            UNSG32 RSVDx9C_b7                                  : 25;\
          }
    union { UNSG32 u32avPll_ctrlTest;
            struct w32avPll_ctrlTest;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avPll_status_PLL_LOCK(r32)                  _BFGET_(r32, 0, 0)
    #define   SET32avPll_status_PLL_LOCK(r32,v)                _BFSET_(r32, 0, 0,v)
    #define   GET16avPll_status_PLL_LOCK(r16)                  _BFGET_(r16, 0, 0)
    #define   SET16avPll_status_PLL_LOCK(r16,v)                _BFSET_(r16, 0, 0,v)

    #define   GET32avPll_status_RESERVE_PLL_OUT(r32)           _BFGET_(r32, 6, 1)
    #define   SET32avPll_status_RESERVE_PLL_OUT(r32,v)         _BFSET_(r32, 6, 1,v)
    #define   GET16avPll_status_RESERVE_PLL_OUT(r16)           _BFGET_(r16, 6, 1)
    #define   SET16avPll_status_RESERVE_PLL_OUT(r16,v)         _BFSET_(r16, 6, 1,v)

    #define   GET32avPll_status_FBDIV_RD(r32)                  _BFGET_(r32,15, 7)
    #define   SET32avPll_status_FBDIV_RD(r32,v)                _BFSET_(r32,15, 7,v)
    #define   GET16avPll_status_FBDIV_RD(r16)                  _BFGET_(r16,15, 7)
    #define   SET16avPll_status_FBDIV_RD(r16,v)                _BFSET_(r16,15, 7,v)

    #define   GET32avPll_status_PLL_CAL_DONE(r32)              _BFGET_(r32,16,16)
    #define   SET32avPll_status_PLL_CAL_DONE(r32,v)            _BFSET_(r32,16,16,v)
    #define   GET16avPll_status_PLL_CAL_DONE(r16)              _BFGET_(r16, 0, 0)
    #define   SET16avPll_status_PLL_CAL_DONE(r16,v)            _BFSET_(r16, 0, 0,v)

    #define   GET32avPll_status_SPEED_CNT(r32)                 _BFGET_(r32,22,17)
    #define   SET32avPll_status_SPEED_CNT(r32,v)               _BFSET_(r32,22,17,v)
    #define   GET16avPll_status_SPEED_CNT(r16)                 _BFGET_(r16, 6, 1)
    #define   SET16avPll_status_SPEED_CNT(r16,v)               _BFSET_(r16, 6, 1,v)

    #define   GET32avPll_status_SPEED_RD(r32)                  _BFGET_(r32,26,23)
    #define   SET32avPll_status_SPEED_RD(r32,v)                _BFSET_(r32,26,23,v)
    #define   GET16avPll_status_SPEED_RD(r16)                  _BFGET_(r16,10, 7)
    #define   SET16avPll_status_SPEED_RD(r16,v)                _BFSET_(r16,10, 7,v)

    #define     w32avPll_status                                {\
            UNSG32 ustatus_PLL_LOCK                            :  1;\
            UNSG32 ustatus_RESERVE_PLL_OUT                     :  6;\
            UNSG32 ustatus_FBDIV_RD                            :  9;\
            UNSG32 ustatus_PLL_CAL_DONE                        :  1;\
            UNSG32 ustatus_SPEED_CNT                           :  6;\
            UNSG32 ustatus_SPEED_RD                            :  4;\
            UNSG32 RSVDxA0_b27                                 :  5;\
          }
    union { UNSG32 u32avPll_status;
            struct w32avPll_status;
          };
    #define   GET32avPll_status_SLLP_DAC_RD(r32)               _BFGET_(r32, 6, 0)
    #define   SET32avPll_status_SLLP_DAC_RD(r32,v)             _BFSET_(r32, 6, 0,v)
    #define   GET16avPll_status_SLLP_DAC_RD(r16)               _BFGET_(r16, 6, 0)
    #define   SET16avPll_status_SLLP_DAC_RD(r16,v)             _BFSET_(r16, 6, 0,v)

    #define     w32avPll_status1                               {\
            UNSG32 ustatus_SLLP_DAC_RD                         :  7;\
            UNSG32 RSVDxA4_b7                                  : 25;\
          }
    union { UNSG32 u32avPll_status1;
            struct w32avPll_status1;
          };
    ///////////////////////////////////////////////////////////
    } SIE_avPll;

    typedef union  T32avPll_ctrlPLL
          { UNSG32 u32;
            struct w32avPll_ctrlPLL;
                 } T32avPll_ctrlPLL;
    typedef union  T32avPll_ctrlPLL1
          { UNSG32 u32;
            struct w32avPll_ctrlPLL1;
                 } T32avPll_ctrlPLL1;
    typedef union  T32avPll_ctrlCAL
          { UNSG32 u32;
            struct w32avPll_ctrlCAL;
                 } T32avPll_ctrlCAL;
    typedef union  T32avPll_ctrlCAL1
          { UNSG32 u32;
            struct w32avPll_ctrlCAL1;
                 } T32avPll_ctrlCAL1;
    typedef union  T32avPll_ctrlSlowLoop
          { UNSG32 u32;
            struct w32avPll_ctrlSlowLoop;
                 } T32avPll_ctrlSlowLoop;
    typedef union  T32avPll_ctrlINTP
          { UNSG32 u32;
            struct w32avPll_ctrlINTP;
                 } T32avPll_ctrlINTP;
    typedef union  T32avPll_ctrlC8AddOn
          { UNSG32 u32;
            struct w32avPll_ctrlC8AddOn;
                 } T32avPll_ctrlC8AddOn;
    typedef union  T32avPll_ctrlTest
          { UNSG32 u32;
            struct w32avPll_ctrlTest;
                 } T32avPll_ctrlTest;
    typedef union  T32avPll_status
          { UNSG32 u32;
            struct w32avPll_status;
                 } T32avPll_status;
    typedef union  T32avPll_status1
          { UNSG32 u32;
            struct w32avPll_status1;
                 } T32avPll_status1;
    ///////////////////////////////////////////////////////////

    typedef union  TavPll_ctrlPLL
          { UNSG32 u32[2];
            struct {
            struct w32avPll_ctrlPLL;
            struct w32avPll_ctrlPLL1;
                   };
                 } TavPll_ctrlPLL;
    typedef union  TavPll_ctrlCAL
          { UNSG32 u32[2];
            struct {
            struct w32avPll_ctrlCAL;
            struct w32avPll_ctrlCAL1;
                   };
                 } TavPll_ctrlCAL;
    typedef union  TavPll_ctrlSlowLoop
          { UNSG32 u32[1];
            struct {
            struct w32avPll_ctrlSlowLoop;
                   };
                 } TavPll_ctrlSlowLoop;
    typedef union  TavPll_ctrlINTP
          { UNSG32 u32[1];
            struct {
            struct w32avPll_ctrlINTP;
                   };
                 } TavPll_ctrlINTP;
    typedef union  TavPll_ctrlC8AddOn
          { UNSG32 u32[1];
            struct {
            struct w32avPll_ctrlC8AddOn;
                   };
                 } TavPll_ctrlC8AddOn;
    typedef union  TavPll_ctrlTest
          { UNSG32 u32[1];
            struct {
            struct w32avPll_ctrlTest;
                   };
                 } TavPll_ctrlTest;
    typedef union  TavPll_status
          { UNSG32 u32[2];
            struct {
            struct w32avPll_status;
            struct w32avPll_status1;
                   };
                 } TavPll_status;

    ///////////////////////////////////////////////////////////
     SIGN32 avPll_drvrd(SIE_avPll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 avPll_drvwr(SIE_avPll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void avPll_reset(SIE_avPll *p);
     SIGN32 avPll_cmp  (SIE_avPll *p, SIE_avPll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define avPll_check(p,pie,pfx,hLOG) avPll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define avPll_print(p,    pfx,hLOG) avPll_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: avPll
////////////////////////////////////////////////////////////

//////
/// 
/// $INTERFACE avioGbl                 biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 AVPLLA               
///               $avPll               AVPLLA            REG          
///                                    ###
///                                    * All the registers for AVPLL-A.
///                                    ###
///     @ 0x000A8 AVPLLA_CLK_EN        (P)
///               %unsigned 6  ctrl                      0x0
///                                    ###
///                                    * Gates the output of AVPLL-A before it is passed to any logic. One bit for each channel. Bit#0 is for Channel1, Bit#1 is for Channel2, ... Bit#5 is for Channel6. Channel7 is for HDMI PHY and there is no gating on that clock.
///                                    * 0: Disable channel output
///                                    * 1: Enable channel output
///                                    * SW should program this bit as 1 after programming the respective AVPLL-A channel to make sure that clean clock is passed to the logic.
///                                    ###
///               %unsigned 1  dbg_mux_sel               0x0
///                                    ###
///                                    * 0: CLKOUT_TSTfrom AVPLL is connected to Clock Debug pin.
///                                    * 1:CLKOUT_C1 from AVPLL is connected to Clock Debug pin.
///                                    ###
///               %%        25         # Stuffing bits...
///     @ 0x000AC VCLK0_CTRL           (P)
///               %unsigned 1  extClkSel                 0x0
///                                    ###
///                                    * Select External clock source or PLL output for vClk0.
///                                    * 0: Select AVPLL output
///                                    * 1: Select external clock source (please refer to pinlist to know which pin is used for bypass clock)
///                                    ###
///               %%        31         # Stuffing bits...
///     @ 0x000B0 VCLK1_CTRL           (P)
///               %unsigned 1  extClkSel                 0x0
///                                    ###
///                                    * Select External clock source or PLL output for vClk1.
///                                    * 0: Select AVPLL output
///                                    * 1: Select external clock source (please refer to pinlist to know which pin is used for bypass clock)
///                                    ###
///               %unsigned 1  pllSel                    0x0
///                                    ###
///                                    * Select Video Source for vClk1 (CPCB1 clock)
///                                    * 0: Select AVPLL-A[2] as source
///                                    * 1: Select AVPLL-B[2] as source
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x000B4 VCLK2_CTRL           (P)
///               %unsigned 1  extClkSel                 0x0
///                                    ###
///                                    * Select External clock source or PLL output for vClk2.
///                                    * 0: Select AVPLL output
///                                    * 1: Select external clock source (please refer to pinlist to know which pin is used for bypass clock)
///                                    ###
///               %unsigned 1  pllSel                    0x0
///                                    ###
///                                    * Select Video source for vClk1 (CPCB2 clock)
///                                    * 0: Select AVPLL-B[1] as source
///                                    * 1: Select AVPLL-A[5] as source
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x000B8 ACLK0_CTRL           (P)
///               ###
///               * Clock controls for Audio0 clock (Primary Audio Output – I2S0),
///               ###
///               %unsigned 1  clkSwitch                 0x0
///                                    ###
///                                    * 0: use source clock
///                                    * 1: use divided clock (decided by clkD3Switch and clkSel)
///                                    ###
///               %unsigned 1  clkD3Switch               0x0
///                                    ###
///                                    * 0 : divide factor is decided by clkSwitch and clkSel
///                                    * 1: use divide by 3 clock when clkSwitch = 1
///                                    ###
///               %unsigned 3  clkSel                    0x0
///                                    ###
///                                    * Use the following divide factor if clkD3Switch=0.
///                                    ###
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///               %unsigned 1  srcSel                    0x0
///                                    ###
///                                    * 0: AVPLL-A[3] is used as clock source
///                                    * 1: AVPLL-A[4] is used as clock source
///                                    ###
///               %%        26         # Stuffing bits...
///     @ 0x000BC ACLK1_CTRL           (P)
///               ###
///               * Clock controls for Audio1 clock (Secondary Audio Output – I2S1).
///               ###
///               %unsigned 1  clkSwitch                 0x0
///                                    ###
///                                    * 0: use source clock
///                                    * 1: use divided clock (decided by clkD3Switch and clkSel)
///                                    ###
///               %unsigned 1  clkD3Switch               0x0
///                                    ###
///                                    * 0 : divide factor is decided by clkSwitch and clkSel
///                                    * 1: use divide by 3 clock when clkSwitch = 1
///                                    ###
///               %unsigned 3  clkSel                    0x0
///                                    ###
///                                    * Use the following divide factor if clkD3Switch=0.
///                                    ###
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///               %unsigned 1  pllSel                    0x0
///                                    ###
///                                    * 0: Select AVPLL-B[3] as source
///                                    * 1: Select AVPLL-A[3] as source
///                                    ###
///               %%        26         # Stuffing bits...
///     @ 0x000C0 ACLK2_CTRL           (P)
///               ###
///               * Clock Controls for Audio2 clock (Audio input – I2S2).
///               ###
///               %unsigned 1  clkSwitch                 0x0
///                                    ###
///                                    * 0: use source clock
///                                    * 1: use divided clock (decided by clkD3Switch and clkSel)
///                                    ###
///               %unsigned 1  clkD3Switch               0x0
///                                    ###
///                                    * 0 : divide factor is decided by clkSwitch and clkSel
///                                    * 1: use divide by 3 clock when clkSwitch = 1
///                                    ###
///               %unsigned 3  clkSel                    0x0
///                                    ###
///                                    * Use the following divide factor if clkD3Switch=0.
///                                    ###
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///               %%        27         # Stuffing bits...
///     @ 0x000C4 ACLK3_CTRL           (P)
///               ###
///               * Clock controls for Audio3 clock (SPDIF output)
///               ###
///               %unsigned 1  clkSwitch                 0x0
///                                    ###
///                                    * 0: use source clock
///                                    * 1: use divided clock (decided by clkD3Switch and clkSel)
///                                    ###
///               %unsigned 1  clkD3Switch               0x0
///                                    ###
///                                    * 0 : divide factor is decided by clkSwitch and clkSel
///                                    * 1: use divide by 3 clock when clkSwitch = 1
///                                    ###
///               %unsigned 3  clkSel                    0x0
///                                    ###
///                                    * Use the following divide factor if clkD3Switch=0.
///                                    ###
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///               %%        27         # Stuffing bits...
///     @ 0x000C8 ACLK4_CTRL           (P)
///               ###
///               * Clock controls for Audio4clock (4-ch MIC output)
///               ###
///               %unsigned 1  clkSwitch                 0x0
///                                    ###
///                                    * 0: use source clock
///                                    * 1: use divided clock (decided by clkD3Switch and clkSel)
///                                    ###
///               %unsigned 1  clkD3Switch               0x0
///                                    ###
///                                    * 0 : divide factor is decided by clkSwitch and clkSel
///                                    * 1: use divide by 3 clock when clkSwitch = 1
///                                    ###
///               %unsigned 3  clkSel                    0x0
///                                    ###
///                                    * Use the following divide factor if clkD3Switch=0.
///                                    ###
///                                    : d2                        0x1
///                                    : d4                        0x2
///                                    : d6                        0x3
///                                    : d8                        0x4
///                                    : d12                       0x5
///               %%        27         # Stuffing bits...
///     @ 0x000CC SWRST_CTRL           (P-)
///               ###
///               * Soft resets for various blocks inside AVIO.
///               ###
///               %unsigned 1  audio0SyncRstn            0x1
///                                    ###
///                                    * Reset control for Primary Audio Output (I2S0).
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  audio1SyncRstn            0x1
///                                    ###
///                                    * Reset for Secondary Audio Output (I2S1).
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  audio2SyncRstn            0x1
///                                    ###
///                                    * Reset for SPDIF Output.
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  audio3SyncRstn            0x1
///                                    ###
///                                    * Reset for 7.1 Audio Input (I2S2).
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  audio4SyncRstn            0x1
///                                    ###
///                                    * Reset for 4-channel Audio Input (I2S3).
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  audioHdSyncRstn           0x1
///                                    ###
///                                    * Reset for HDMI Audio Output.
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  spdifRxSyncRstn           0x1
///                                    ###
///                                    * Reset for SPDIF Input.
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  vppSyncRstn               0x1
///                                    ###
///                                    * Reset for all the logic that works on vppSysClk (FE and SCL)
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  vipSyncRstn               0x1
///                                    ###
///                                    * Reset for VIP module.
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %unsigned 1  appSyncRstn               0x1
///                                    ###
///                                    * Reset for APP module.
///                                    * 1: de-assert reset
///                                    * 0: Assert reset
///                                    ###
///               %%        22         # Stuffing bits...
///     @ 0x000D0 RWTC_31to0           (P)
///               ###
///               * rwtcBus[31:0]
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 32 value                     0xAAAA99AA
///                                    ###
///                                    * RTWC [31:0] value for AVIO internal memories.
///                                    ###
///     @ 0x000D4 RWTC_57to32          (P)
///               ###
///               * rwtcBus[57:32]
///               * *INTERNAL_ONLY**
///               ###
///               %unsigned 26 value                     0x2A95B5A
///                                    ###
///                                    * RTWC [57:32] value for AVIO internal memories.
///                                    ###
///               %%        6          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     216B, bits:     920b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_avioGbl
#define h_avioGbl (){}

    #define     RA_avioGbl_AVPLLA                              0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_AVPLLA_CLK_EN                       0x00A8

    #define     BA_avioGbl_AVPLLA_CLK_EN_ctrl                  0x00A8
    #define     B16avioGbl_AVPLLA_CLK_EN_ctrl                  0x00A8
    #define   LSb32avioGbl_AVPLLA_CLK_EN_ctrl                     0
    #define   LSb16avioGbl_AVPLLA_CLK_EN_ctrl                     0
    #define       bavioGbl_AVPLLA_CLK_EN_ctrl                  6
    #define   MSK32avioGbl_AVPLLA_CLK_EN_ctrl                     0x0000003F

    #define     BA_avioGbl_AVPLLA_CLK_EN_dbg_mux_sel           0x00A8
    #define     B16avioGbl_AVPLLA_CLK_EN_dbg_mux_sel           0x00A8
    #define   LSb32avioGbl_AVPLLA_CLK_EN_dbg_mux_sel              6
    #define   LSb16avioGbl_AVPLLA_CLK_EN_dbg_mux_sel              6
    #define       bavioGbl_AVPLLA_CLK_EN_dbg_mux_sel           1
    #define   MSK32avioGbl_AVPLLA_CLK_EN_dbg_mux_sel              0x00000040
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_VCLK0_CTRL                          0x00AC

    #define     BA_avioGbl_VCLK0_CTRL_extClkSel                0x00AC
    #define     B16avioGbl_VCLK0_CTRL_extClkSel                0x00AC
    #define   LSb32avioGbl_VCLK0_CTRL_extClkSel                   0
    #define   LSb16avioGbl_VCLK0_CTRL_extClkSel                   0
    #define       bavioGbl_VCLK0_CTRL_extClkSel                1
    #define   MSK32avioGbl_VCLK0_CTRL_extClkSel                   0x00000001
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_VCLK1_CTRL                          0x00B0

    #define     BA_avioGbl_VCLK1_CTRL_extClkSel                0x00B0
    #define     B16avioGbl_VCLK1_CTRL_extClkSel                0x00B0
    #define   LSb32avioGbl_VCLK1_CTRL_extClkSel                   0
    #define   LSb16avioGbl_VCLK1_CTRL_extClkSel                   0
    #define       bavioGbl_VCLK1_CTRL_extClkSel                1
    #define   MSK32avioGbl_VCLK1_CTRL_extClkSel                   0x00000001

    #define     BA_avioGbl_VCLK1_CTRL_pllSel                   0x00B0
    #define     B16avioGbl_VCLK1_CTRL_pllSel                   0x00B0
    #define   LSb32avioGbl_VCLK1_CTRL_pllSel                      1
    #define   LSb16avioGbl_VCLK1_CTRL_pllSel                      1
    #define       bavioGbl_VCLK1_CTRL_pllSel                   1
    #define   MSK32avioGbl_VCLK1_CTRL_pllSel                      0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_VCLK2_CTRL                          0x00B4

    #define     BA_avioGbl_VCLK2_CTRL_extClkSel                0x00B4
    #define     B16avioGbl_VCLK2_CTRL_extClkSel                0x00B4
    #define   LSb32avioGbl_VCLK2_CTRL_extClkSel                   0
    #define   LSb16avioGbl_VCLK2_CTRL_extClkSel                   0
    #define       bavioGbl_VCLK2_CTRL_extClkSel                1
    #define   MSK32avioGbl_VCLK2_CTRL_extClkSel                   0x00000001

    #define     BA_avioGbl_VCLK2_CTRL_pllSel                   0x00B4
    #define     B16avioGbl_VCLK2_CTRL_pllSel                   0x00B4
    #define   LSb32avioGbl_VCLK2_CTRL_pllSel                      1
    #define   LSb16avioGbl_VCLK2_CTRL_pllSel                      1
    #define       bavioGbl_VCLK2_CTRL_pllSel                   1
    #define   MSK32avioGbl_VCLK2_CTRL_pllSel                      0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_ACLK0_CTRL                          0x00B8

    #define     BA_avioGbl_ACLK0_CTRL_clkSwitch                0x00B8
    #define     B16avioGbl_ACLK0_CTRL_clkSwitch                0x00B8
    #define   LSb32avioGbl_ACLK0_CTRL_clkSwitch                   0
    #define   LSb16avioGbl_ACLK0_CTRL_clkSwitch                   0
    #define       bavioGbl_ACLK0_CTRL_clkSwitch                1
    #define   MSK32avioGbl_ACLK0_CTRL_clkSwitch                   0x00000001

    #define     BA_avioGbl_ACLK0_CTRL_clkD3Switch              0x00B8
    #define     B16avioGbl_ACLK0_CTRL_clkD3Switch              0x00B8
    #define   LSb32avioGbl_ACLK0_CTRL_clkD3Switch                 1
    #define   LSb16avioGbl_ACLK0_CTRL_clkD3Switch                 1
    #define       bavioGbl_ACLK0_CTRL_clkD3Switch              1
    #define   MSK32avioGbl_ACLK0_CTRL_clkD3Switch                 0x00000002

    #define     BA_avioGbl_ACLK0_CTRL_clkSel                   0x00B8
    #define     B16avioGbl_ACLK0_CTRL_clkSel                   0x00B8
    #define   LSb32avioGbl_ACLK0_CTRL_clkSel                      2
    #define   LSb16avioGbl_ACLK0_CTRL_clkSel                      2
    #define       bavioGbl_ACLK0_CTRL_clkSel                   3
    #define   MSK32avioGbl_ACLK0_CTRL_clkSel                      0x0000001C
    #define        avioGbl_ACLK0_CTRL_clkSel_d2                             0x1
    #define        avioGbl_ACLK0_CTRL_clkSel_d4                             0x2
    #define        avioGbl_ACLK0_CTRL_clkSel_d6                             0x3
    #define        avioGbl_ACLK0_CTRL_clkSel_d8                             0x4
    #define        avioGbl_ACLK0_CTRL_clkSel_d12                            0x5

    #define     BA_avioGbl_ACLK0_CTRL_srcSel                   0x00B8
    #define     B16avioGbl_ACLK0_CTRL_srcSel                   0x00B8
    #define   LSb32avioGbl_ACLK0_CTRL_srcSel                      5
    #define   LSb16avioGbl_ACLK0_CTRL_srcSel                      5
    #define       bavioGbl_ACLK0_CTRL_srcSel                   1
    #define   MSK32avioGbl_ACLK0_CTRL_srcSel                      0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_ACLK1_CTRL                          0x00BC

    #define     BA_avioGbl_ACLK1_CTRL_clkSwitch                0x00BC
    #define     B16avioGbl_ACLK1_CTRL_clkSwitch                0x00BC
    #define   LSb32avioGbl_ACLK1_CTRL_clkSwitch                   0
    #define   LSb16avioGbl_ACLK1_CTRL_clkSwitch                   0
    #define       bavioGbl_ACLK1_CTRL_clkSwitch                1
    #define   MSK32avioGbl_ACLK1_CTRL_clkSwitch                   0x00000001

    #define     BA_avioGbl_ACLK1_CTRL_clkD3Switch              0x00BC
    #define     B16avioGbl_ACLK1_CTRL_clkD3Switch              0x00BC
    #define   LSb32avioGbl_ACLK1_CTRL_clkD3Switch                 1
    #define   LSb16avioGbl_ACLK1_CTRL_clkD3Switch                 1
    #define       bavioGbl_ACLK1_CTRL_clkD3Switch              1
    #define   MSK32avioGbl_ACLK1_CTRL_clkD3Switch                 0x00000002

    #define     BA_avioGbl_ACLK1_CTRL_clkSel                   0x00BC
    #define     B16avioGbl_ACLK1_CTRL_clkSel                   0x00BC
    #define   LSb32avioGbl_ACLK1_CTRL_clkSel                      2
    #define   LSb16avioGbl_ACLK1_CTRL_clkSel                      2
    #define       bavioGbl_ACLK1_CTRL_clkSel                   3
    #define   MSK32avioGbl_ACLK1_CTRL_clkSel                      0x0000001C
    #define        avioGbl_ACLK1_CTRL_clkSel_d2                             0x1
    #define        avioGbl_ACLK1_CTRL_clkSel_d4                             0x2
    #define        avioGbl_ACLK1_CTRL_clkSel_d6                             0x3
    #define        avioGbl_ACLK1_CTRL_clkSel_d8                             0x4
    #define        avioGbl_ACLK1_CTRL_clkSel_d12                            0x5

    #define     BA_avioGbl_ACLK1_CTRL_pllSel                   0x00BC
    #define     B16avioGbl_ACLK1_CTRL_pllSel                   0x00BC
    #define   LSb32avioGbl_ACLK1_CTRL_pllSel                      5
    #define   LSb16avioGbl_ACLK1_CTRL_pllSel                      5
    #define       bavioGbl_ACLK1_CTRL_pllSel                   1
    #define   MSK32avioGbl_ACLK1_CTRL_pllSel                      0x00000020
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_ACLK2_CTRL                          0x00C0

    #define     BA_avioGbl_ACLK2_CTRL_clkSwitch                0x00C0
    #define     B16avioGbl_ACLK2_CTRL_clkSwitch                0x00C0
    #define   LSb32avioGbl_ACLK2_CTRL_clkSwitch                   0
    #define   LSb16avioGbl_ACLK2_CTRL_clkSwitch                   0
    #define       bavioGbl_ACLK2_CTRL_clkSwitch                1
    #define   MSK32avioGbl_ACLK2_CTRL_clkSwitch                   0x00000001

    #define     BA_avioGbl_ACLK2_CTRL_clkD3Switch              0x00C0
    #define     B16avioGbl_ACLK2_CTRL_clkD3Switch              0x00C0
    #define   LSb32avioGbl_ACLK2_CTRL_clkD3Switch                 1
    #define   LSb16avioGbl_ACLK2_CTRL_clkD3Switch                 1
    #define       bavioGbl_ACLK2_CTRL_clkD3Switch              1
    #define   MSK32avioGbl_ACLK2_CTRL_clkD3Switch                 0x00000002

    #define     BA_avioGbl_ACLK2_CTRL_clkSel                   0x00C0
    #define     B16avioGbl_ACLK2_CTRL_clkSel                   0x00C0
    #define   LSb32avioGbl_ACLK2_CTRL_clkSel                      2
    #define   LSb16avioGbl_ACLK2_CTRL_clkSel                      2
    #define       bavioGbl_ACLK2_CTRL_clkSel                   3
    #define   MSK32avioGbl_ACLK2_CTRL_clkSel                      0x0000001C
    #define        avioGbl_ACLK2_CTRL_clkSel_d2                             0x1
    #define        avioGbl_ACLK2_CTRL_clkSel_d4                             0x2
    #define        avioGbl_ACLK2_CTRL_clkSel_d6                             0x3
    #define        avioGbl_ACLK2_CTRL_clkSel_d8                             0x4
    #define        avioGbl_ACLK2_CTRL_clkSel_d12                            0x5
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_ACLK3_CTRL                          0x00C4

    #define     BA_avioGbl_ACLK3_CTRL_clkSwitch                0x00C4
    #define     B16avioGbl_ACLK3_CTRL_clkSwitch                0x00C4
    #define   LSb32avioGbl_ACLK3_CTRL_clkSwitch                   0
    #define   LSb16avioGbl_ACLK3_CTRL_clkSwitch                   0
    #define       bavioGbl_ACLK3_CTRL_clkSwitch                1
    #define   MSK32avioGbl_ACLK3_CTRL_clkSwitch                   0x00000001

    #define     BA_avioGbl_ACLK3_CTRL_clkD3Switch              0x00C4
    #define     B16avioGbl_ACLK3_CTRL_clkD3Switch              0x00C4
    #define   LSb32avioGbl_ACLK3_CTRL_clkD3Switch                 1
    #define   LSb16avioGbl_ACLK3_CTRL_clkD3Switch                 1
    #define       bavioGbl_ACLK3_CTRL_clkD3Switch              1
    #define   MSK32avioGbl_ACLK3_CTRL_clkD3Switch                 0x00000002

    #define     BA_avioGbl_ACLK3_CTRL_clkSel                   0x00C4
    #define     B16avioGbl_ACLK3_CTRL_clkSel                   0x00C4
    #define   LSb32avioGbl_ACLK3_CTRL_clkSel                      2
    #define   LSb16avioGbl_ACLK3_CTRL_clkSel                      2
    #define       bavioGbl_ACLK3_CTRL_clkSel                   3
    #define   MSK32avioGbl_ACLK3_CTRL_clkSel                      0x0000001C
    #define        avioGbl_ACLK3_CTRL_clkSel_d2                             0x1
    #define        avioGbl_ACLK3_CTRL_clkSel_d4                             0x2
    #define        avioGbl_ACLK3_CTRL_clkSel_d6                             0x3
    #define        avioGbl_ACLK3_CTRL_clkSel_d8                             0x4
    #define        avioGbl_ACLK3_CTRL_clkSel_d12                            0x5
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_ACLK4_CTRL                          0x00C8

    #define     BA_avioGbl_ACLK4_CTRL_clkSwitch                0x00C8
    #define     B16avioGbl_ACLK4_CTRL_clkSwitch                0x00C8
    #define   LSb32avioGbl_ACLK4_CTRL_clkSwitch                   0
    #define   LSb16avioGbl_ACLK4_CTRL_clkSwitch                   0
    #define       bavioGbl_ACLK4_CTRL_clkSwitch                1
    #define   MSK32avioGbl_ACLK4_CTRL_clkSwitch                   0x00000001

    #define     BA_avioGbl_ACLK4_CTRL_clkD3Switch              0x00C8
    #define     B16avioGbl_ACLK4_CTRL_clkD3Switch              0x00C8
    #define   LSb32avioGbl_ACLK4_CTRL_clkD3Switch                 1
    #define   LSb16avioGbl_ACLK4_CTRL_clkD3Switch                 1
    #define       bavioGbl_ACLK4_CTRL_clkD3Switch              1
    #define   MSK32avioGbl_ACLK4_CTRL_clkD3Switch                 0x00000002

    #define     BA_avioGbl_ACLK4_CTRL_clkSel                   0x00C8
    #define     B16avioGbl_ACLK4_CTRL_clkSel                   0x00C8
    #define   LSb32avioGbl_ACLK4_CTRL_clkSel                      2
    #define   LSb16avioGbl_ACLK4_CTRL_clkSel                      2
    #define       bavioGbl_ACLK4_CTRL_clkSel                   3
    #define   MSK32avioGbl_ACLK4_CTRL_clkSel                      0x0000001C
    #define        avioGbl_ACLK4_CTRL_clkSel_d2                             0x1
    #define        avioGbl_ACLK4_CTRL_clkSel_d4                             0x2
    #define        avioGbl_ACLK4_CTRL_clkSel_d6                             0x3
    #define        avioGbl_ACLK4_CTRL_clkSel_d8                             0x4
    #define        avioGbl_ACLK4_CTRL_clkSel_d12                            0x5
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_SWRST_CTRL                          0x00CC

    #define     BA_avioGbl_SWRST_CTRL_audio0SyncRstn           0x00CC
    #define     B16avioGbl_SWRST_CTRL_audio0SyncRstn           0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_audio0SyncRstn              0
    #define   LSb16avioGbl_SWRST_CTRL_audio0SyncRstn              0
    #define       bavioGbl_SWRST_CTRL_audio0SyncRstn           1
    #define   MSK32avioGbl_SWRST_CTRL_audio0SyncRstn              0x00000001

    #define     BA_avioGbl_SWRST_CTRL_audio1SyncRstn           0x00CC
    #define     B16avioGbl_SWRST_CTRL_audio1SyncRstn           0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_audio1SyncRstn              1
    #define   LSb16avioGbl_SWRST_CTRL_audio1SyncRstn              1
    #define       bavioGbl_SWRST_CTRL_audio1SyncRstn           1
    #define   MSK32avioGbl_SWRST_CTRL_audio1SyncRstn              0x00000002

    #define     BA_avioGbl_SWRST_CTRL_audio2SyncRstn           0x00CC
    #define     B16avioGbl_SWRST_CTRL_audio2SyncRstn           0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_audio2SyncRstn              2
    #define   LSb16avioGbl_SWRST_CTRL_audio2SyncRstn              2
    #define       bavioGbl_SWRST_CTRL_audio2SyncRstn           1
    #define   MSK32avioGbl_SWRST_CTRL_audio2SyncRstn              0x00000004

    #define     BA_avioGbl_SWRST_CTRL_audio3SyncRstn           0x00CC
    #define     B16avioGbl_SWRST_CTRL_audio3SyncRstn           0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_audio3SyncRstn              3
    #define   LSb16avioGbl_SWRST_CTRL_audio3SyncRstn              3
    #define       bavioGbl_SWRST_CTRL_audio3SyncRstn           1
    #define   MSK32avioGbl_SWRST_CTRL_audio3SyncRstn              0x00000008

    #define     BA_avioGbl_SWRST_CTRL_audio4SyncRstn           0x00CC
    #define     B16avioGbl_SWRST_CTRL_audio4SyncRstn           0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_audio4SyncRstn              4
    #define   LSb16avioGbl_SWRST_CTRL_audio4SyncRstn              4
    #define       bavioGbl_SWRST_CTRL_audio4SyncRstn           1
    #define   MSK32avioGbl_SWRST_CTRL_audio4SyncRstn              0x00000010

    #define     BA_avioGbl_SWRST_CTRL_audioHdSyncRstn          0x00CC
    #define     B16avioGbl_SWRST_CTRL_audioHdSyncRstn          0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_audioHdSyncRstn             5
    #define   LSb16avioGbl_SWRST_CTRL_audioHdSyncRstn             5
    #define       bavioGbl_SWRST_CTRL_audioHdSyncRstn          1
    #define   MSK32avioGbl_SWRST_CTRL_audioHdSyncRstn             0x00000020

    #define     BA_avioGbl_SWRST_CTRL_spdifRxSyncRstn          0x00CC
    #define     B16avioGbl_SWRST_CTRL_spdifRxSyncRstn          0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_spdifRxSyncRstn             6
    #define   LSb16avioGbl_SWRST_CTRL_spdifRxSyncRstn             6
    #define       bavioGbl_SWRST_CTRL_spdifRxSyncRstn          1
    #define   MSK32avioGbl_SWRST_CTRL_spdifRxSyncRstn             0x00000040

    #define     BA_avioGbl_SWRST_CTRL_vppSyncRstn              0x00CC
    #define     B16avioGbl_SWRST_CTRL_vppSyncRstn              0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_vppSyncRstn                 7
    #define   LSb16avioGbl_SWRST_CTRL_vppSyncRstn                 7
    #define       bavioGbl_SWRST_CTRL_vppSyncRstn              1
    #define   MSK32avioGbl_SWRST_CTRL_vppSyncRstn                 0x00000080

    #define     BA_avioGbl_SWRST_CTRL_vipSyncRstn              0x00CD
    #define     B16avioGbl_SWRST_CTRL_vipSyncRstn              0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_vipSyncRstn                 8
    #define   LSb16avioGbl_SWRST_CTRL_vipSyncRstn                 8
    #define       bavioGbl_SWRST_CTRL_vipSyncRstn              1
    #define   MSK32avioGbl_SWRST_CTRL_vipSyncRstn                 0x00000100

    #define     BA_avioGbl_SWRST_CTRL_appSyncRstn              0x00CD
    #define     B16avioGbl_SWRST_CTRL_appSyncRstn              0x00CC
    #define   LSb32avioGbl_SWRST_CTRL_appSyncRstn                 9
    #define   LSb16avioGbl_SWRST_CTRL_appSyncRstn                 9
    #define       bavioGbl_SWRST_CTRL_appSyncRstn              1
    #define   MSK32avioGbl_SWRST_CTRL_appSyncRstn                 0x00000200
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_RWTC_31to0                          0x00D0

    #define     BA_avioGbl_RWTC_31to0_value                    0x00D0
    #define     B16avioGbl_RWTC_31to0_value                    0x00D0
    #define   LSb32avioGbl_RWTC_31to0_value                       0
    #define   LSb16avioGbl_RWTC_31to0_value                       0
    #define       bavioGbl_RWTC_31to0_value                    32
    #define   MSK32avioGbl_RWTC_31to0_value                       0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_avioGbl_RWTC_57to32                         0x00D4

    #define     BA_avioGbl_RWTC_57to32_value                   0x00D4
    #define     B16avioGbl_RWTC_57to32_value                   0x00D4
    #define   LSb32avioGbl_RWTC_57to32_value                      0
    #define   LSb16avioGbl_RWTC_57to32_value                      0
    #define       bavioGbl_RWTC_57to32_value                   26
    #define   MSK32avioGbl_RWTC_57to32_value                      0x03FFFFFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_avioGbl {
    ///////////////////////////////////////////////////////////
              SIE_avPll                                        ie_AVPLLA;
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_AVPLLA_CLK_EN_ctrl(r32)             _BFGET_(r32, 5, 0)
    #define   SET32avioGbl_AVPLLA_CLK_EN_ctrl(r32,v)           _BFSET_(r32, 5, 0,v)
    #define   GET16avioGbl_AVPLLA_CLK_EN_ctrl(r16)             _BFGET_(r16, 5, 0)
    #define   SET16avioGbl_AVPLLA_CLK_EN_ctrl(r16,v)           _BFSET_(r16, 5, 0,v)

    #define   GET32avioGbl_AVPLLA_CLK_EN_dbg_mux_sel(r32)      _BFGET_(r32, 6, 6)
    #define   SET32avioGbl_AVPLLA_CLK_EN_dbg_mux_sel(r32,v)    _BFSET_(r32, 6, 6,v)
    #define   GET16avioGbl_AVPLLA_CLK_EN_dbg_mux_sel(r16)      _BFGET_(r16, 6, 6)
    #define   SET16avioGbl_AVPLLA_CLK_EN_dbg_mux_sel(r16,v)    _BFSET_(r16, 6, 6,v)

    #define     w32avioGbl_AVPLLA_CLK_EN                       {\
            UNSG32 uAVPLLA_CLK_EN_ctrl                         :  6;\
            UNSG32 uAVPLLA_CLK_EN_dbg_mux_sel                  :  1;\
            UNSG32 RSVDxA8_b7                                  : 25;\
          }
    union { UNSG32 u32avioGbl_AVPLLA_CLK_EN;
            struct w32avioGbl_AVPLLA_CLK_EN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_VCLK0_CTRL_extClkSel(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_VCLK0_CTRL_extClkSel(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_VCLK0_CTRL_extClkSel(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_VCLK0_CTRL_extClkSel(r16,v)         _BFSET_(r16, 0, 0,v)

    #define     w32avioGbl_VCLK0_CTRL                          {\
            UNSG32 uVCLK0_CTRL_extClkSel                       :  1;\
            UNSG32 RSVDxAC_b1                                  : 31;\
          }
    union { UNSG32 u32avioGbl_VCLK0_CTRL;
            struct w32avioGbl_VCLK0_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_VCLK1_CTRL_extClkSel(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_VCLK1_CTRL_extClkSel(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_VCLK1_CTRL_extClkSel(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_VCLK1_CTRL_extClkSel(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_VCLK1_CTRL_pllSel(r32)              _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_VCLK1_CTRL_pllSel(r32,v)            _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_VCLK1_CTRL_pllSel(r16)              _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_VCLK1_CTRL_pllSel(r16,v)            _BFSET_(r16, 1, 1,v)

    #define     w32avioGbl_VCLK1_CTRL                          {\
            UNSG32 uVCLK1_CTRL_extClkSel                       :  1;\
            UNSG32 uVCLK1_CTRL_pllSel                          :  1;\
            UNSG32 RSVDxB0_b2                                  : 30;\
          }
    union { UNSG32 u32avioGbl_VCLK1_CTRL;
            struct w32avioGbl_VCLK1_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_VCLK2_CTRL_extClkSel(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_VCLK2_CTRL_extClkSel(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_VCLK2_CTRL_extClkSel(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_VCLK2_CTRL_extClkSel(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_VCLK2_CTRL_pllSel(r32)              _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_VCLK2_CTRL_pllSel(r32,v)            _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_VCLK2_CTRL_pllSel(r16)              _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_VCLK2_CTRL_pllSel(r16,v)            _BFSET_(r16, 1, 1,v)

    #define     w32avioGbl_VCLK2_CTRL                          {\
            UNSG32 uVCLK2_CTRL_extClkSel                       :  1;\
            UNSG32 uVCLK2_CTRL_pllSel                          :  1;\
            UNSG32 RSVDxB4_b2                                  : 30;\
          }
    union { UNSG32 u32avioGbl_VCLK2_CTRL;
            struct w32avioGbl_VCLK2_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_ACLK0_CTRL_clkSwitch(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_ACLK0_CTRL_clkSwitch(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_ACLK0_CTRL_clkSwitch(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_ACLK0_CTRL_clkSwitch(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_ACLK0_CTRL_clkD3Switch(r32)         _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_ACLK0_CTRL_clkD3Switch(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_ACLK0_CTRL_clkD3Switch(r16)         _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_ACLK0_CTRL_clkD3Switch(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32avioGbl_ACLK0_CTRL_clkSel(r32)              _BFGET_(r32, 4, 2)
    #define   SET32avioGbl_ACLK0_CTRL_clkSel(r32,v)            _BFSET_(r32, 4, 2,v)
    #define   GET16avioGbl_ACLK0_CTRL_clkSel(r16)              _BFGET_(r16, 4, 2)
    #define   SET16avioGbl_ACLK0_CTRL_clkSel(r16,v)            _BFSET_(r16, 4, 2,v)

    #define   GET32avioGbl_ACLK0_CTRL_srcSel(r32)              _BFGET_(r32, 5, 5)
    #define   SET32avioGbl_ACLK0_CTRL_srcSel(r32,v)            _BFSET_(r32, 5, 5,v)
    #define   GET16avioGbl_ACLK0_CTRL_srcSel(r16)              _BFGET_(r16, 5, 5)
    #define   SET16avioGbl_ACLK0_CTRL_srcSel(r16,v)            _BFSET_(r16, 5, 5,v)

    #define     w32avioGbl_ACLK0_CTRL                          {\
            UNSG32 uACLK0_CTRL_clkSwitch                       :  1;\
            UNSG32 uACLK0_CTRL_clkD3Switch                     :  1;\
            UNSG32 uACLK0_CTRL_clkSel                          :  3;\
            UNSG32 uACLK0_CTRL_srcSel                          :  1;\
            UNSG32 RSVDxB8_b6                                  : 26;\
          }
    union { UNSG32 u32avioGbl_ACLK0_CTRL;
            struct w32avioGbl_ACLK0_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_ACLK1_CTRL_clkSwitch(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_ACLK1_CTRL_clkSwitch(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_ACLK1_CTRL_clkSwitch(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_ACLK1_CTRL_clkSwitch(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_ACLK1_CTRL_clkD3Switch(r32)         _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_ACLK1_CTRL_clkD3Switch(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_ACLK1_CTRL_clkD3Switch(r16)         _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_ACLK1_CTRL_clkD3Switch(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32avioGbl_ACLK1_CTRL_clkSel(r32)              _BFGET_(r32, 4, 2)
    #define   SET32avioGbl_ACLK1_CTRL_clkSel(r32,v)            _BFSET_(r32, 4, 2,v)
    #define   GET16avioGbl_ACLK1_CTRL_clkSel(r16)              _BFGET_(r16, 4, 2)
    #define   SET16avioGbl_ACLK1_CTRL_clkSel(r16,v)            _BFSET_(r16, 4, 2,v)

    #define   GET32avioGbl_ACLK1_CTRL_pllSel(r32)              _BFGET_(r32, 5, 5)
    #define   SET32avioGbl_ACLK1_CTRL_pllSel(r32,v)            _BFSET_(r32, 5, 5,v)
    #define   GET16avioGbl_ACLK1_CTRL_pllSel(r16)              _BFGET_(r16, 5, 5)
    #define   SET16avioGbl_ACLK1_CTRL_pllSel(r16,v)            _BFSET_(r16, 5, 5,v)

    #define     w32avioGbl_ACLK1_CTRL                          {\
            UNSG32 uACLK1_CTRL_clkSwitch                       :  1;\
            UNSG32 uACLK1_CTRL_clkD3Switch                     :  1;\
            UNSG32 uACLK1_CTRL_clkSel                          :  3;\
            UNSG32 uACLK1_CTRL_pllSel                          :  1;\
            UNSG32 RSVDxBC_b6                                  : 26;\
          }
    union { UNSG32 u32avioGbl_ACLK1_CTRL;
            struct w32avioGbl_ACLK1_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_ACLK2_CTRL_clkSwitch(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_ACLK2_CTRL_clkSwitch(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_ACLK2_CTRL_clkSwitch(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_ACLK2_CTRL_clkSwitch(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_ACLK2_CTRL_clkD3Switch(r32)         _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_ACLK2_CTRL_clkD3Switch(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_ACLK2_CTRL_clkD3Switch(r16)         _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_ACLK2_CTRL_clkD3Switch(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32avioGbl_ACLK2_CTRL_clkSel(r32)              _BFGET_(r32, 4, 2)
    #define   SET32avioGbl_ACLK2_CTRL_clkSel(r32,v)            _BFSET_(r32, 4, 2,v)
    #define   GET16avioGbl_ACLK2_CTRL_clkSel(r16)              _BFGET_(r16, 4, 2)
    #define   SET16avioGbl_ACLK2_CTRL_clkSel(r16,v)            _BFSET_(r16, 4, 2,v)

    #define     w32avioGbl_ACLK2_CTRL                          {\
            UNSG32 uACLK2_CTRL_clkSwitch                       :  1;\
            UNSG32 uACLK2_CTRL_clkD3Switch                     :  1;\
            UNSG32 uACLK2_CTRL_clkSel                          :  3;\
            UNSG32 RSVDxC0_b5                                  : 27;\
          }
    union { UNSG32 u32avioGbl_ACLK2_CTRL;
            struct w32avioGbl_ACLK2_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_ACLK3_CTRL_clkSwitch(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_ACLK3_CTRL_clkSwitch(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_ACLK3_CTRL_clkSwitch(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_ACLK3_CTRL_clkSwitch(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_ACLK3_CTRL_clkD3Switch(r32)         _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_ACLK3_CTRL_clkD3Switch(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_ACLK3_CTRL_clkD3Switch(r16)         _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_ACLK3_CTRL_clkD3Switch(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32avioGbl_ACLK3_CTRL_clkSel(r32)              _BFGET_(r32, 4, 2)
    #define   SET32avioGbl_ACLK3_CTRL_clkSel(r32,v)            _BFSET_(r32, 4, 2,v)
    #define   GET16avioGbl_ACLK3_CTRL_clkSel(r16)              _BFGET_(r16, 4, 2)
    #define   SET16avioGbl_ACLK3_CTRL_clkSel(r16,v)            _BFSET_(r16, 4, 2,v)

    #define     w32avioGbl_ACLK3_CTRL                          {\
            UNSG32 uACLK3_CTRL_clkSwitch                       :  1;\
            UNSG32 uACLK3_CTRL_clkD3Switch                     :  1;\
            UNSG32 uACLK3_CTRL_clkSel                          :  3;\
            UNSG32 RSVDxC4_b5                                  : 27;\
          }
    union { UNSG32 u32avioGbl_ACLK3_CTRL;
            struct w32avioGbl_ACLK3_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_ACLK4_CTRL_clkSwitch(r32)           _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_ACLK4_CTRL_clkSwitch(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_ACLK4_CTRL_clkSwitch(r16)           _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_ACLK4_CTRL_clkSwitch(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_ACLK4_CTRL_clkD3Switch(r32)         _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_ACLK4_CTRL_clkD3Switch(r32,v)       _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_ACLK4_CTRL_clkD3Switch(r16)         _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_ACLK4_CTRL_clkD3Switch(r16,v)       _BFSET_(r16, 1, 1,v)

    #define   GET32avioGbl_ACLK4_CTRL_clkSel(r32)              _BFGET_(r32, 4, 2)
    #define   SET32avioGbl_ACLK4_CTRL_clkSel(r32,v)            _BFSET_(r32, 4, 2,v)
    #define   GET16avioGbl_ACLK4_CTRL_clkSel(r16)              _BFGET_(r16, 4, 2)
    #define   SET16avioGbl_ACLK4_CTRL_clkSel(r16,v)            _BFSET_(r16, 4, 2,v)

    #define     w32avioGbl_ACLK4_CTRL                          {\
            UNSG32 uACLK4_CTRL_clkSwitch                       :  1;\
            UNSG32 uACLK4_CTRL_clkD3Switch                     :  1;\
            UNSG32 uACLK4_CTRL_clkSel                          :  3;\
            UNSG32 RSVDxC8_b5                                  : 27;\
          }
    union { UNSG32 u32avioGbl_ACLK4_CTRL;
            struct w32avioGbl_ACLK4_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_SWRST_CTRL_audio0SyncRstn(r32)      _BFGET_(r32, 0, 0)
    #define   SET32avioGbl_SWRST_CTRL_audio0SyncRstn(r32,v)    _BFSET_(r32, 0, 0,v)
    #define   GET16avioGbl_SWRST_CTRL_audio0SyncRstn(r16)      _BFGET_(r16, 0, 0)
    #define   SET16avioGbl_SWRST_CTRL_audio0SyncRstn(r16,v)    _BFSET_(r16, 0, 0,v)

    #define   GET32avioGbl_SWRST_CTRL_audio1SyncRstn(r32)      _BFGET_(r32, 1, 1)
    #define   SET32avioGbl_SWRST_CTRL_audio1SyncRstn(r32,v)    _BFSET_(r32, 1, 1,v)
    #define   GET16avioGbl_SWRST_CTRL_audio1SyncRstn(r16)      _BFGET_(r16, 1, 1)
    #define   SET16avioGbl_SWRST_CTRL_audio1SyncRstn(r16,v)    _BFSET_(r16, 1, 1,v)

    #define   GET32avioGbl_SWRST_CTRL_audio2SyncRstn(r32)      _BFGET_(r32, 2, 2)
    #define   SET32avioGbl_SWRST_CTRL_audio2SyncRstn(r32,v)    _BFSET_(r32, 2, 2,v)
    #define   GET16avioGbl_SWRST_CTRL_audio2SyncRstn(r16)      _BFGET_(r16, 2, 2)
    #define   SET16avioGbl_SWRST_CTRL_audio2SyncRstn(r16,v)    _BFSET_(r16, 2, 2,v)

    #define   GET32avioGbl_SWRST_CTRL_audio3SyncRstn(r32)      _BFGET_(r32, 3, 3)
    #define   SET32avioGbl_SWRST_CTRL_audio3SyncRstn(r32,v)    _BFSET_(r32, 3, 3,v)
    #define   GET16avioGbl_SWRST_CTRL_audio3SyncRstn(r16)      _BFGET_(r16, 3, 3)
    #define   SET16avioGbl_SWRST_CTRL_audio3SyncRstn(r16,v)    _BFSET_(r16, 3, 3,v)

    #define   GET32avioGbl_SWRST_CTRL_audio4SyncRstn(r32)      _BFGET_(r32, 4, 4)
    #define   SET32avioGbl_SWRST_CTRL_audio4SyncRstn(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16avioGbl_SWRST_CTRL_audio4SyncRstn(r16)      _BFGET_(r16, 4, 4)
    #define   SET16avioGbl_SWRST_CTRL_audio4SyncRstn(r16,v)    _BFSET_(r16, 4, 4,v)

    #define   GET32avioGbl_SWRST_CTRL_audioHdSyncRstn(r32)     _BFGET_(r32, 5, 5)
    #define   SET32avioGbl_SWRST_CTRL_audioHdSyncRstn(r32,v)   _BFSET_(r32, 5, 5,v)
    #define   GET16avioGbl_SWRST_CTRL_audioHdSyncRstn(r16)     _BFGET_(r16, 5, 5)
    #define   SET16avioGbl_SWRST_CTRL_audioHdSyncRstn(r16,v)   _BFSET_(r16, 5, 5,v)

    #define   GET32avioGbl_SWRST_CTRL_spdifRxSyncRstn(r32)     _BFGET_(r32, 6, 6)
    #define   SET32avioGbl_SWRST_CTRL_spdifRxSyncRstn(r32,v)   _BFSET_(r32, 6, 6,v)
    #define   GET16avioGbl_SWRST_CTRL_spdifRxSyncRstn(r16)     _BFGET_(r16, 6, 6)
    #define   SET16avioGbl_SWRST_CTRL_spdifRxSyncRstn(r16,v)   _BFSET_(r16, 6, 6,v)

    #define   GET32avioGbl_SWRST_CTRL_vppSyncRstn(r32)         _BFGET_(r32, 7, 7)
    #define   SET32avioGbl_SWRST_CTRL_vppSyncRstn(r32,v)       _BFSET_(r32, 7, 7,v)
    #define   GET16avioGbl_SWRST_CTRL_vppSyncRstn(r16)         _BFGET_(r16, 7, 7)
    #define   SET16avioGbl_SWRST_CTRL_vppSyncRstn(r16,v)       _BFSET_(r16, 7, 7,v)

    #define   GET32avioGbl_SWRST_CTRL_vipSyncRstn(r32)         _BFGET_(r32, 8, 8)
    #define   SET32avioGbl_SWRST_CTRL_vipSyncRstn(r32,v)       _BFSET_(r32, 8, 8,v)
    #define   GET16avioGbl_SWRST_CTRL_vipSyncRstn(r16)         _BFGET_(r16, 8, 8)
    #define   SET16avioGbl_SWRST_CTRL_vipSyncRstn(r16,v)       _BFSET_(r16, 8, 8,v)

    #define   GET32avioGbl_SWRST_CTRL_appSyncRstn(r32)         _BFGET_(r32, 9, 9)
    #define   SET32avioGbl_SWRST_CTRL_appSyncRstn(r32,v)       _BFSET_(r32, 9, 9,v)
    #define   GET16avioGbl_SWRST_CTRL_appSyncRstn(r16)         _BFGET_(r16, 9, 9)
    #define   SET16avioGbl_SWRST_CTRL_appSyncRstn(r16,v)       _BFSET_(r16, 9, 9,v)

    #define     w32avioGbl_SWRST_CTRL                          {\
            UNSG32 uSWRST_CTRL_audio0SyncRstn                  :  1;\
            UNSG32 uSWRST_CTRL_audio1SyncRstn                  :  1;\
            UNSG32 uSWRST_CTRL_audio2SyncRstn                  :  1;\
            UNSG32 uSWRST_CTRL_audio3SyncRstn                  :  1;\
            UNSG32 uSWRST_CTRL_audio4SyncRstn                  :  1;\
            UNSG32 uSWRST_CTRL_audioHdSyncRstn                 :  1;\
            UNSG32 uSWRST_CTRL_spdifRxSyncRstn                 :  1;\
            UNSG32 uSWRST_CTRL_vppSyncRstn                     :  1;\
            UNSG32 uSWRST_CTRL_vipSyncRstn                     :  1;\
            UNSG32 uSWRST_CTRL_appSyncRstn                     :  1;\
            UNSG32 RSVDxCC_b10                                 : 22;\
          }
    union { UNSG32 u32avioGbl_SWRST_CTRL;
            struct w32avioGbl_SWRST_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_RWTC_31to0_value(r32)               _BFGET_(r32,31, 0)
    #define   SET32avioGbl_RWTC_31to0_value(r32,v)             _BFSET_(r32,31, 0,v)

    #define     w32avioGbl_RWTC_31to0                          {\
            UNSG32 uRWTC_31to0_value                           : 32;\
          }
    union { UNSG32 u32avioGbl_RWTC_31to0;
            struct w32avioGbl_RWTC_31to0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32avioGbl_RWTC_57to32_value(r32)              _BFGET_(r32,25, 0)
    #define   SET32avioGbl_RWTC_57to32_value(r32,v)            _BFSET_(r32,25, 0,v)

    #define     w32avioGbl_RWTC_57to32                         {\
            UNSG32 uRWTC_57to32_value                          : 26;\
            UNSG32 RSVDxD4_b26                                 :  6;\
          }
    union { UNSG32 u32avioGbl_RWTC_57to32;
            struct w32avioGbl_RWTC_57to32;
          };
    ///////////////////////////////////////////////////////////
    } SIE_avioGbl;

    typedef union  T32avioGbl_AVPLLA_CLK_EN
          { UNSG32 u32;
            struct w32avioGbl_AVPLLA_CLK_EN;
                 } T32avioGbl_AVPLLA_CLK_EN;
    typedef union  T32avioGbl_VCLK0_CTRL
          { UNSG32 u32;
            struct w32avioGbl_VCLK0_CTRL;
                 } T32avioGbl_VCLK0_CTRL;
    typedef union  T32avioGbl_VCLK1_CTRL
          { UNSG32 u32;
            struct w32avioGbl_VCLK1_CTRL;
                 } T32avioGbl_VCLK1_CTRL;
    typedef union  T32avioGbl_VCLK2_CTRL
          { UNSG32 u32;
            struct w32avioGbl_VCLK2_CTRL;
                 } T32avioGbl_VCLK2_CTRL;
    typedef union  T32avioGbl_ACLK0_CTRL
          { UNSG32 u32;
            struct w32avioGbl_ACLK0_CTRL;
                 } T32avioGbl_ACLK0_CTRL;
    typedef union  T32avioGbl_ACLK1_CTRL
          { UNSG32 u32;
            struct w32avioGbl_ACLK1_CTRL;
                 } T32avioGbl_ACLK1_CTRL;
    typedef union  T32avioGbl_ACLK2_CTRL
          { UNSG32 u32;
            struct w32avioGbl_ACLK2_CTRL;
                 } T32avioGbl_ACLK2_CTRL;
    typedef union  T32avioGbl_ACLK3_CTRL
          { UNSG32 u32;
            struct w32avioGbl_ACLK3_CTRL;
                 } T32avioGbl_ACLK3_CTRL;
    typedef union  T32avioGbl_ACLK4_CTRL
          { UNSG32 u32;
            struct w32avioGbl_ACLK4_CTRL;
                 } T32avioGbl_ACLK4_CTRL;
    typedef union  T32avioGbl_SWRST_CTRL
          { UNSG32 u32;
            struct w32avioGbl_SWRST_CTRL;
                 } T32avioGbl_SWRST_CTRL;
    typedef union  T32avioGbl_RWTC_31to0
          { UNSG32 u32;
            struct w32avioGbl_RWTC_31to0;
                 } T32avioGbl_RWTC_31to0;
    typedef union  T32avioGbl_RWTC_57to32
          { UNSG32 u32;
            struct w32avioGbl_RWTC_57to32;
                 } T32avioGbl_RWTC_57to32;
    ///////////////////////////////////////////////////////////

    typedef union  TavioGbl_AVPLLA_CLK_EN
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_AVPLLA_CLK_EN;
                   };
                 } TavioGbl_AVPLLA_CLK_EN;
    typedef union  TavioGbl_VCLK0_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_VCLK0_CTRL;
                   };
                 } TavioGbl_VCLK0_CTRL;
    typedef union  TavioGbl_VCLK1_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_VCLK1_CTRL;
                   };
                 } TavioGbl_VCLK1_CTRL;
    typedef union  TavioGbl_VCLK2_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_VCLK2_CTRL;
                   };
                 } TavioGbl_VCLK2_CTRL;
    typedef union  TavioGbl_ACLK0_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_ACLK0_CTRL;
                   };
                 } TavioGbl_ACLK0_CTRL;
    typedef union  TavioGbl_ACLK1_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_ACLK1_CTRL;
                   };
                 } TavioGbl_ACLK1_CTRL;
    typedef union  TavioGbl_ACLK2_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_ACLK2_CTRL;
                   };
                 } TavioGbl_ACLK2_CTRL;
    typedef union  TavioGbl_ACLK3_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_ACLK3_CTRL;
                   };
                 } TavioGbl_ACLK3_CTRL;
    typedef union  TavioGbl_ACLK4_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_ACLK4_CTRL;
                   };
                 } TavioGbl_ACLK4_CTRL;
    typedef union  TavioGbl_SWRST_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_SWRST_CTRL;
                   };
                 } TavioGbl_SWRST_CTRL;
    typedef union  TavioGbl_RWTC_31to0
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_RWTC_31to0;
                   };
                 } TavioGbl_RWTC_31to0;
    typedef union  TavioGbl_RWTC_57to32
          { UNSG32 u32[1];
            struct {
            struct w32avioGbl_RWTC_57to32;
                   };
                 } TavioGbl_RWTC_57to32;

    ///////////////////////////////////////////////////////////
     SIGN32 avioGbl_drvrd(SIE_avioGbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 avioGbl_drvwr(SIE_avioGbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void avioGbl_reset(SIE_avioGbl *p);
     SIGN32 avioGbl_cmp  (SIE_avioGbl *p, SIE_avioGbl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define avioGbl_check(p,pie,pfx,hLOG) avioGbl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define avioGbl_print(p,    pfx,hLOG) avioGbl_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: avioGbl
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: avioGbl.h
////////////////////////////////////////////////////////////