qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_reg.h - manifest_repos/sdk - Git at Google

 /*
  **************************************************************************
  * Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
  * above copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  **************************************************************************
  */

 #ifndef __SYN_REG_H__
 #define __SYN_REG_H__

 /*
  *
  MAC Register Offset
  *
  */
 #define SYN_MAC_TX_CONFIG		0x0000
 #define SYN_MAC_RX_CONFIG		0x0004
 #define SYN_MAC_PACKET_FILTER		0x0008
 #define SYN_MAC_WDOG_TIMEOUT		0x000c
 #define SYN_MAC_HASH_TBL_REG0		0x0010
 #define SYN_MAC_VLAN_TAG		0x0050
 #define SYN_MAC_VLAN_HASH_TBL		0x0058
 #define SYN_MAC_VLAN_INCL		0x0060
 #define SYN_MAC_INNER_VLAN_INCL		0x0064
 #define SYN_MAC_RX_ETH_TYP_MATCH	0x006c
 #define SYN_MAC_Q0_TX_FLOW_CTL		0x0070
 #define SYN_MAC_Q1_TX_FLOW_CTL		0x0074
 #define SYN_MAC_Q2_TX_FLOW_CTL		0x0078
 #define SYN_MAC_Q3_TX_FLOW_CTL		0x007c
 #define SYN_MAC_Q4_TX_FLOW_CTL		0x0080
 #define SYN_MAC_Q5_TX_FLOW_CTL		0x0084
 #define SYN_MAC_Q6_TX_FLOW_CTL		0x0088
 #define SYN_MAC_Q7_TX_FLOW_CTL		0x008c
 #define SYN_MAC_RX_FLOW_CTL		0x0090
 #define SYN_MAC_RXQ_CTL0		0x00a0
 #define SYN_MAC_RXQ_CTL1		0x00a4
 #define SYN_MAC_RXQ_CTL2		0x00a8
 #define SYN_MAC_RXQ_CTL3		0x00ac
 #define SYN_MAC_INT_STATUS		0x00b0
 #define SYN_MAC_INT_ENABLE		0x00b4
 #define SYN_MAC_TX_RX_STATUS		0x00b8
 #define SYN_MAC_PMT_CTL_STATUS		0x00c0
 #define SYN_MAC_RWK_PACKET_FILTER	0x00c4
 #define SYN_MAC_LPI_CTL_STATUS		0x00d0
 #define SYN_MAC_LPI_TIMER_STATUS	0x00d4
 #define SYN_MAC_VERSION			0x0110
 #define SYN_MAC_DEBUG			0x0114
 #define SYN_MAC_FW_FEATURE0		0x011c
 #define SYN_MAC_FW_FEATURE1		0x0120
 #define SYN_MAC_FW_FEATURE2		0x0124
 #define SYN_MAC_GPIO_CTL		0x0278
 #define SYN_MAC_GPIO_STATUS		0x027c
 #define SYN_MAC_ADDR0_HIGH		0x0300
 #define SYN_MAC_ADDR0_LOW		0x0304
 #define SYN_MAC_ADDR1_HIGH		0x0308
 #define SYN_MAC_ADDR1_LOW		0x030c
 #define SYN_MAC_TS_CTL			0x0d00
 #define SYN_MAC_SUB_SEC_INCR		0x0d04
 #define SYN_MAC_SYS_TIME_SECS		0x0d08
 #define SYN_MAC_SYS_TIME_NSECS		0x0d0c
 #define SYN_MAC_SYS_TIME_SECS_UPDATE	0x0d10
 #define SYN_MAC_SYS_TIME_NSECS_UPDATE	0x0d14
 #define SYN_MAC_TS_ADDEND		0x0d18
 #define SYN_MAC_TS_STATUS		0x0d20
 #define SYN_MAC_TX_TS_STATUS_NSECS	0x0d30
 #define SYN_MAC_TX_TS_STATUS_SECS	0x0d34
 #define SYN_MAC_PPS_CTL			0x0d70
 #define SYN_MAC_MMC_CTL			0x0800
 #define SYN_MAC_MMC_RX_INT		0x0804
 #define SYN_MAC_MMC_TX_INT		0x0808
 #define SYN_MAC_MMC_RX_INT_EN		0x080c
 #define SYN_MAC_MMC_TX_INT_EN		0x0810

 /* MAC TX MMC Counters */
 #define SYN_MAC_MMC_TX_BCAST_LO		0x0824
 #define SYN_MAC_MMC_TX_BCAST_HI		0x0828
 #define SYN_MAC_MMC_TX_FRAME_LO		0x0894
 #define SYN_MAC_MMC_TX_FRAME_HI		0x0898
 #define SYN_MAC_MMC_TX_MCAST_LO		0x082c
 #define SYN_MAC_MMC_TX_MCAST_HI		0x0830
 #define SYN_MAC_MMC_TX_PKT64_LO		0x0834
 #define SYN_MAC_MMC_TX_PKT64_HI		0x0838
 #define SYN_MAC_MMC_TX_PKT65TO127_LO	0x083c
 #define SYN_MAC_MMC_TX_PKT65TO127_HI	0x0840
 #define SYN_MAC_MMC_TX_PKT128TO255_LO	0x0844
 #define SYN_MAC_MMC_TX_PKT128TO255_HI	0x0848
 #define SYN_MAC_MMC_TX_PKT256TO511_LO	0x084c
 #define SYN_MAC_MMC_TX_PKT256TO511_HI	0x0850
 #define SYN_MAC_MMC_TX_PKT512TO1023_LO	0x0854
 #define SYN_MAC_MMC_TX_PKT512TO1023_HI	0x0858
 #define SYN_MAC_MMC_TX_PKT1024TOMAX_LO	0x085c
 #define SYN_MAC_MMC_TX_PKT1024TOMAX_HI	0x0860
 #define SYN_MAC_MMC_TX_UNICAST_LO	0x0864
 #define SYN_MAC_MMC_TX_UNICAST_HI	0x0868
 #define SYN_MAC_MMC_TX_MCAST_GB_LO	0x086c
 #define SYN_MAC_MMC_TX_MCAST_GB_HI	0x0870
 #define SYN_MAC_MMC_TX_BCAST_GB_LO	0x0874
 #define SYN_MAC_MMC_TX_BCAST_GB_HI	0x0878
 #define SYN_MAC_MMC_TX_UNDERFLOW_ERR_LO	0x087c
 #define SYN_MAC_MMC_TX_UNDERFLOW_ERR_HI	0x0880
 #define SYN_MAC_MMC_TX_BYTES_LO		0x0884
 #define SYN_MAC_MMC_TX_BYTES_HI		0x0888
 #define SYN_MAC_MMC_TX_PAUSE_FRAME_LO	0x0894
 #define SYN_MAC_MMC_TX_PAUSE_FRAME_HI	0x0898
 #define SYN_MAC_MMC_TX_VLAN_LO		0x089c
 #define SYN_MAC_MMC_TX_VLAN_HI		0x08a0
 #define SYN_MAC_MMC_TX_LPI_USEC_CTR_LO	0x08a4
 #define SYN_MAC_MMC_TX_LPI_USEC_CTR_HI	0x08a8

 /* MAC RX MMC Counters */
 #define SYN_MAC_MMC_RX_FRAME_LO		0x0900
 #define SYN_MAC_MMC_RX_FRAME_HI		0x0904
 #define SYN_MAC_MMC_RX_BYTES_LO		0x0910
 #define SYN_MAC_MMC_RX_BYTES_HI		0x0914
 #define SYN_MAC_MMC_RX_BCAST_LO		0x0918
 #define SYN_MAC_MMC_RX_BCAST_HI		0x091c
 #define SYN_MAC_MMC_RX_MCAST_LO		0x0920
 #define SYN_MAC_MMC_RX_MCAST_HI		0x0924
 #define SYN_MAC_MMC_RX_CRC_ERR_LO	0x0928
 #define SYN_MAC_MMC_RX_CRC_ERR_HI	0x092c
 #define SYN_MAC_MMC_RX_RUNT_ERR		0x0930
 #define SYN_MAC_MMC_RX_JABBER_ERR	0x0934
 #define SYN_MAC_MMC_RX_UNDERSIZE	0x0938
 #define SYN_MAC_MMC_RX_OVERSIZE		0x093c
 #define SYN_MAC_MMC_RX_PKT64_LO		0x0940
 #define SYN_MAC_MMC_RX_PKT64_HI		0x0944
 #define SYN_MAC_MMC_RX_PKT65TO127_LO	0x0948
 #define SYN_MAC_MMC_RX_PKT65TO127_HI	0x094c
 #define SYN_MAC_MMC_RX_PKT128TO255_LO	0x0950
 #define SYN_MAC_MMC_RX_PKT128TO255_HI	0x0954
 #define SYN_MAC_MMC_RX_PKT256TO511_LO	0x0958
 #define SYN_MAC_MMC_RX_PKT256TO511_HI	0x095c
 #define SYN_MAC_MMC_RX_PKT512TO1023_LO	0x0960
 #define SYN_MAC_MMC_RX_PKT512TO1023_HI	0x0964
 #define SYN_MAC_MMC_RX_PKT1024TOMAX_LO	0x0968
 #define SYN_MAC_MMC_RX_PKT1024TOMAX_HI	0x096c
 #define SYN_MAC_MMC_RX_UNICAST_LO	0x0970
 #define SYN_MAC_MMC_RX_UNICAST_HI	0x0974
 #define SYN_MAC_MMC_RX_LEN_ERR_LO	0x0978
 #define SYN_MAC_MMC_RX_LEN_ERR_HI	0x097c
 #define SYN_MAC_MMC_RX_PAUSE_FRAME_LO	0x0988
 #define SYN_MAC_MMC_RX_PAUSE_FRAME_HI	0x098c
 #define SYN_MAC_MMC_RX_FIFO_OVERFLOW_LO	0x0990
 #define SYN_MAC_MMC_RX_FIFO_OVERFLOW_HI	0x0994
 #define SYN_MAC_MMC_RX_VLAN_FRAME_LO	0x0998
 #define SYN_MAC_MMC_RX_VLAN_FRAME_HI	0x099c
 #define SYN_MAC_MMC_RX_LPI_USEC_CTR_LO	0x09a4
 #define SYN_MAC_MMC_RX_LPI_USEC_CTR_HI	0x09a8
 #define SYN_MAC_MMC_RX_DISCARD_FRAME_LO	0x09ac
 #define SYN_MAC_MMC_RX_DISCARD_FRAME_HI	0x09b0

 /* MAC Register Bit Definitions*/

 /* SYN_MAC_Q0_TX_FLOW_CTL Bit definitions */
 #define SYN_MAC_TX_PAUSE_SEND		0x00000001
 #define SYN_MAC_TX_FLOW_ENABLE		0x00000002
 #define SYN_MAC_TX_PAUSE_LOW_THRESHOLD	0x00000070
 #define SYN_MAC_ADDR_RSVD_BIT		0x80000000

 /* SYN_MAC_RX_FLOW_CTL Bit definitions */
 #define SYN_MAC_RX_FLOW_ENABLE		0x00000001

 /* SYN_MAC_TX_CONFIG Bit definitions */
 #define SYN_MAC_TX_ENABLE		0x00000001
 #define SYN_MAC_TX_SPEED_SELECT		0x60000000

 /* SYN_MAC_RX_CONFIG Bit definitions */
 #define SYN_MAC_RX_ENABLE		0x00000001
 #define SYN_MAC_JUMBO_FRAME_ENABLE	0x00000100

 #define SYN_MAC_SPEED_10G		0x0
 #define SYN_MAC_SPEED_2_5G		0x2
 #define SYN_MAC_SPEED_1G		0x3
 #define SYN_MAC_SPEED_BITPOS		29
 #define SYN_MAC_SPEED_BITMASK		0x3

 #define SYN_MAC_DEFAULT_MAX_FRAME_SIZE	1518
 #define SYN_MAC_MAX_FRAME_SIZE_BITPOS	16
 #define SYN_MAC_MAX_FRAME_SIZE_BITMASK	0x3fff

 /* SYN_MAC_MMC_CTL Bit definitions */
 #define  SYN_MAC_MMC_RSTONRD		0x00000004

 /*
  *
  MTL Register Offset
  *
  */
 #define SYN_MTL_OPER_MODE		0x1000
 #define SYN_MTL_DEBUG_CTL		0x1008
 #define SYN_MTL_DEBUG_STATUS		0x100c
 #define SYN_MTL_DEBUG_DATA		0x1010
 #define SYN_MTL_INT_STATUS		0x1020
 #define SYN_MTL_RXQ_DMA_MAP0		0x1030
 #define SYN_MTL_RXQ_DMA_MAP1		0x1034
 #define SYN_MTL_RXQ_DMA_MAP2		0x1038
 #define SYN_MTL_TC_PRIO_MAP0		0x1040
 #define SYN_MTL_TC_PRIO_MAP1		0x1044
 #define SYN_MTL_TXQ0_OPER_MODE		0x1100
 #define SYN_MTL_TXQ0_UNDERFLOW		0x1104
 #define SYN_MTL_TXQ0_DEBUG		0x1108
 #define SYN_MTL_TC0_ETS_CTL		0x1110
 #define SYN_MTL_TC0_ETS_STATUS		0x1114
 #define SYN_MTL_TC0_QUANTUM_WEIGHT	0x1118
 #define SYN_MTL_RXQ0_DEBUG		0x1148
 #define SYN_MTL_RXQ0_CTL		0x114c
 #define SYN_MTL_RXQ0_FLOW_CTL		0x1150
 #define SYN_MTL_Q0_INT_ENABLE		0x1170
 #define SYN_MTL_Q0_INT_STATUS		0x1174

 /* MTL Register Bit definitions */

 /*
  *
  DMA Register Offset
  *
  */
 #define SYN_DMA_MODE			0x3000
 #define SYN_DMA_SYSBUS_MODE		0x3004
 #define SYN_DMA_INT_STATUS		0x3008
 #define SYN_DMA_AXI_TX_AR_ACE_CTL	0x3010
 #define SYN_DMA_AXI_RX_AW_ACE_CTL	0x3018
 #define SYN_DMA_AXI_TXRX_AWAR_ACE_CTL	0x301c
 #define SYN_DMA_DEBUG_STATUS0		0x3020
 #define SYN_DMA_DEBUG_STATUS1		0x3024
 #define SYN_DMA_TX_EDMA_CTL		0x3040
 #define SYN_DMA_RX_EDMA_CTL		0x3044
 #define SYN_DMA_CH0_CTL			0x3100
 #define SYN_DMA_CH0_TX_CTL		0x3104
 #define SYN_DMA_CH0_RX_CTL		0x3108
 #define SYN_DMA_CH0_TXDESC_LIST_HADDR	0x3110
 #define SYN_DMA_CH0_TXDESC_LIST_LADDR	0x3114
 #define SYN_DMA_CH0_RXDESC_LIST_HADDR	0x3118
 #define SYN_DMA_CH0_RXDESC_LIST_LADDR	0x311c
 #define SYN_DMA_CH0_TXDESC_TAIL_LPTR	0x3124
 #define SYN_DMA_CH0_RXDESC_TAIL_LPTR	0x312c
 #define SYN_DMA_CH0_TXDESC_RING_LEN	0x3130
 #define SYN_DMA_CH0_RXDESC_RING_LEN	0x3134
 #define SYN_DMA_INT_ENABLE		0x3138
 #define SYN_DMA_RX_INT_WDOG_TIMER	0x313c

 /* DMA Register Bit definitions */

 #endif /*__SYN_REG_H__*/
	/*
	**************************************************************************
	* Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
	*
	* Permission to use, copy, modify, and/or distribute this software for
	* any purpose with or without fee is hereby granted, provided that the
	* above copyright notice and this permission notice appear in all copies.
	*
	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
	* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	**************************************************************************
	*/

	#ifndef __SYN_REG_H__
	#define __SYN_REG_H__

	/*
	*
	MAC Register Offset
	*
	*/
	#define SYN_MAC_TX_CONFIG 0x0000
	#define SYN_MAC_RX_CONFIG 0x0004
	#define SYN_MAC_PACKET_FILTER 0x0008
	#define SYN_MAC_WDOG_TIMEOUT 0x000c
	#define SYN_MAC_HASH_TBL_REG0 0x0010
	#define SYN_MAC_VLAN_TAG 0x0050
	#define SYN_MAC_VLAN_HASH_TBL 0x0058
	#define SYN_MAC_VLAN_INCL 0x0060
	#define SYN_MAC_INNER_VLAN_INCL 0x0064
	#define SYN_MAC_RX_ETH_TYP_MATCH 0x006c
	#define SYN_MAC_Q0_TX_FLOW_CTL 0x0070
	#define SYN_MAC_Q1_TX_FLOW_CTL 0x0074
	#define SYN_MAC_Q2_TX_FLOW_CTL 0x0078
	#define SYN_MAC_Q3_TX_FLOW_CTL 0x007c
	#define SYN_MAC_Q4_TX_FLOW_CTL 0x0080
	#define SYN_MAC_Q5_TX_FLOW_CTL 0x0084
	#define SYN_MAC_Q6_TX_FLOW_CTL 0x0088
	#define SYN_MAC_Q7_TX_FLOW_CTL 0x008c
	#define SYN_MAC_RX_FLOW_CTL 0x0090
	#define SYN_MAC_RXQ_CTL0 0x00a0
	#define SYN_MAC_RXQ_CTL1 0x00a4
	#define SYN_MAC_RXQ_CTL2 0x00a8
	#define SYN_MAC_RXQ_CTL3 0x00ac
	#define SYN_MAC_INT_STATUS 0x00b0
	#define SYN_MAC_INT_ENABLE 0x00b4
	#define SYN_MAC_TX_RX_STATUS 0x00b8
	#define SYN_MAC_PMT_CTL_STATUS 0x00c0
	#define SYN_MAC_RWK_PACKET_FILTER 0x00c4
	#define SYN_MAC_LPI_CTL_STATUS 0x00d0
	#define SYN_MAC_LPI_TIMER_STATUS 0x00d4
	#define SYN_MAC_VERSION 0x0110
	#define SYN_MAC_DEBUG 0x0114
	#define SYN_MAC_FW_FEATURE0 0x011c
	#define SYN_MAC_FW_FEATURE1 0x0120
	#define SYN_MAC_FW_FEATURE2 0x0124
	#define SYN_MAC_GPIO_CTL 0x0278
	#define SYN_MAC_GPIO_STATUS 0x027c
	#define SYN_MAC_ADDR0_HIGH 0x0300
	#define SYN_MAC_ADDR0_LOW 0x0304
	#define SYN_MAC_ADDR1_HIGH 0x0308
	#define SYN_MAC_ADDR1_LOW 0x030c
	#define SYN_MAC_TS_CTL 0x0d00
	#define SYN_MAC_SUB_SEC_INCR 0x0d04
	#define SYN_MAC_SYS_TIME_SECS 0x0d08
	#define SYN_MAC_SYS_TIME_NSECS 0x0d0c
	#define SYN_MAC_SYS_TIME_SECS_UPDATE 0x0d10
	#define SYN_MAC_SYS_TIME_NSECS_UPDATE 0x0d14
	#define SYN_MAC_TS_ADDEND 0x0d18
	#define SYN_MAC_TS_STATUS 0x0d20
	#define SYN_MAC_TX_TS_STATUS_NSECS 0x0d30
	#define SYN_MAC_TX_TS_STATUS_SECS 0x0d34
	#define SYN_MAC_PPS_CTL 0x0d70
	#define SYN_MAC_MMC_CTL 0x0800
	#define SYN_MAC_MMC_RX_INT 0x0804
	#define SYN_MAC_MMC_TX_INT 0x0808
	#define SYN_MAC_MMC_RX_INT_EN 0x080c
	#define SYN_MAC_MMC_TX_INT_EN 0x0810

	/* MAC TX MMC Counters */
	#define SYN_MAC_MMC_TX_BCAST_LO 0x0824
	#define SYN_MAC_MMC_TX_BCAST_HI 0x0828
	#define SYN_MAC_MMC_TX_FRAME_LO 0x0894
	#define SYN_MAC_MMC_TX_FRAME_HI 0x0898
	#define SYN_MAC_MMC_TX_MCAST_LO 0x082c
	#define SYN_MAC_MMC_TX_MCAST_HI 0x0830
	#define SYN_MAC_MMC_TX_PKT64_LO 0x0834
	#define SYN_MAC_MMC_TX_PKT64_HI 0x0838
	#define SYN_MAC_MMC_TX_PKT65TO127_LO 0x083c
	#define SYN_MAC_MMC_TX_PKT65TO127_HI 0x0840
	#define SYN_MAC_MMC_TX_PKT128TO255_LO 0x0844
	#define SYN_MAC_MMC_TX_PKT128TO255_HI 0x0848
	#define SYN_MAC_MMC_TX_PKT256TO511_LO 0x084c
	#define SYN_MAC_MMC_TX_PKT256TO511_HI 0x0850
	#define SYN_MAC_MMC_TX_PKT512TO1023_LO 0x0854
	#define SYN_MAC_MMC_TX_PKT512TO1023_HI 0x0858
	#define SYN_MAC_MMC_TX_PKT1024TOMAX_LO 0x085c
	#define SYN_MAC_MMC_TX_PKT1024TOMAX_HI 0x0860
	#define SYN_MAC_MMC_TX_UNICAST_LO 0x0864
	#define SYN_MAC_MMC_TX_UNICAST_HI 0x0868
	#define SYN_MAC_MMC_TX_MCAST_GB_LO 0x086c
	#define SYN_MAC_MMC_TX_MCAST_GB_HI 0x0870
	#define SYN_MAC_MMC_TX_BCAST_GB_LO 0x0874
	#define SYN_MAC_MMC_TX_BCAST_GB_HI 0x0878
	#define SYN_MAC_MMC_TX_UNDERFLOW_ERR_LO 0x087c
	#define SYN_MAC_MMC_TX_UNDERFLOW_ERR_HI 0x0880
	#define SYN_MAC_MMC_TX_BYTES_LO 0x0884
	#define SYN_MAC_MMC_TX_BYTES_HI 0x0888
	#define SYN_MAC_MMC_TX_PAUSE_FRAME_LO 0x0894
	#define SYN_MAC_MMC_TX_PAUSE_FRAME_HI 0x0898
	#define SYN_MAC_MMC_TX_VLAN_LO 0x089c
	#define SYN_MAC_MMC_TX_VLAN_HI 0x08a0
	#define SYN_MAC_MMC_TX_LPI_USEC_CTR_LO 0x08a4
	#define SYN_MAC_MMC_TX_LPI_USEC_CTR_HI 0x08a8

	/* MAC RX MMC Counters */
	#define SYN_MAC_MMC_RX_FRAME_LO 0x0900
	#define SYN_MAC_MMC_RX_FRAME_HI 0x0904
	#define SYN_MAC_MMC_RX_BYTES_LO 0x0910
	#define SYN_MAC_MMC_RX_BYTES_HI 0x0914
	#define SYN_MAC_MMC_RX_BCAST_LO 0x0918
	#define SYN_MAC_MMC_RX_BCAST_HI 0x091c
	#define SYN_MAC_MMC_RX_MCAST_LO 0x0920
	#define SYN_MAC_MMC_RX_MCAST_HI 0x0924
	#define SYN_MAC_MMC_RX_CRC_ERR_LO 0x0928
	#define SYN_MAC_MMC_RX_CRC_ERR_HI 0x092c
	#define SYN_MAC_MMC_RX_RUNT_ERR 0x0930
	#define SYN_MAC_MMC_RX_JABBER_ERR 0x0934
	#define SYN_MAC_MMC_RX_UNDERSIZE 0x0938
	#define SYN_MAC_MMC_RX_OVERSIZE 0x093c
	#define SYN_MAC_MMC_RX_PKT64_LO 0x0940
	#define SYN_MAC_MMC_RX_PKT64_HI 0x0944
	#define SYN_MAC_MMC_RX_PKT65TO127_LO 0x0948
	#define SYN_MAC_MMC_RX_PKT65TO127_HI 0x094c
	#define SYN_MAC_MMC_RX_PKT128TO255_LO 0x0950
	#define SYN_MAC_MMC_RX_PKT128TO255_HI 0x0954
	#define SYN_MAC_MMC_RX_PKT256TO511_LO 0x0958
	#define SYN_MAC_MMC_RX_PKT256TO511_HI 0x095c
	#define SYN_MAC_MMC_RX_PKT512TO1023_LO 0x0960
	#define SYN_MAC_MMC_RX_PKT512TO1023_HI 0x0964
	#define SYN_MAC_MMC_RX_PKT1024TOMAX_LO 0x0968
	#define SYN_MAC_MMC_RX_PKT1024TOMAX_HI 0x096c
	#define SYN_MAC_MMC_RX_UNICAST_LO 0x0970
	#define SYN_MAC_MMC_RX_UNICAST_HI 0x0974
	#define SYN_MAC_MMC_RX_LEN_ERR_LO 0x0978
	#define SYN_MAC_MMC_RX_LEN_ERR_HI 0x097c
	#define SYN_MAC_MMC_RX_PAUSE_FRAME_LO 0x0988
	#define SYN_MAC_MMC_RX_PAUSE_FRAME_HI 0x098c
	#define SYN_MAC_MMC_RX_FIFO_OVERFLOW_LO 0x0990
	#define SYN_MAC_MMC_RX_FIFO_OVERFLOW_HI 0x0994
	#define SYN_MAC_MMC_RX_VLAN_FRAME_LO 0x0998
	#define SYN_MAC_MMC_RX_VLAN_FRAME_HI 0x099c
	#define SYN_MAC_MMC_RX_LPI_USEC_CTR_LO 0x09a4
	#define SYN_MAC_MMC_RX_LPI_USEC_CTR_HI 0x09a8
	#define SYN_MAC_MMC_RX_DISCARD_FRAME_LO 0x09ac
	#define SYN_MAC_MMC_RX_DISCARD_FRAME_HI 0x09b0

	/* MAC Register Bit Definitions*/

	/* SYN_MAC_Q0_TX_FLOW_CTL Bit definitions */
	#define SYN_MAC_TX_PAUSE_SEND 0x00000001
	#define SYN_MAC_TX_FLOW_ENABLE 0x00000002
	#define SYN_MAC_TX_PAUSE_LOW_THRESHOLD 0x00000070
	#define SYN_MAC_ADDR_RSVD_BIT 0x80000000

	/* SYN_MAC_RX_FLOW_CTL Bit definitions */
	#define SYN_MAC_RX_FLOW_ENABLE 0x00000001

	/* SYN_MAC_TX_CONFIG Bit definitions */
	#define SYN_MAC_TX_ENABLE 0x00000001
	#define SYN_MAC_TX_SPEED_SELECT 0x60000000

	/* SYN_MAC_RX_CONFIG Bit definitions */
	#define SYN_MAC_RX_ENABLE 0x00000001
	#define SYN_MAC_JUMBO_FRAME_ENABLE 0x00000100

	#define SYN_MAC_SPEED_10G 0x0
	#define SYN_MAC_SPEED_2_5G 0x2
	#define SYN_MAC_SPEED_1G 0x3
	#define SYN_MAC_SPEED_BITPOS 29
	#define SYN_MAC_SPEED_BITMASK 0x3

	#define SYN_MAC_DEFAULT_MAX_FRAME_SIZE 1518
	#define SYN_MAC_MAX_FRAME_SIZE_BITPOS 16
	#define SYN_MAC_MAX_FRAME_SIZE_BITMASK 0x3fff

	/* SYN_MAC_MMC_CTL Bit definitions */
	#define SYN_MAC_MMC_RSTONRD 0x00000004

	/*
	*
	MTL Register Offset
	*
	*/
	#define SYN_MTL_OPER_MODE 0x1000
	#define SYN_MTL_DEBUG_CTL 0x1008
	#define SYN_MTL_DEBUG_STATUS 0x100c
	#define SYN_MTL_DEBUG_DATA 0x1010
	#define SYN_MTL_INT_STATUS 0x1020
	#define SYN_MTL_RXQ_DMA_MAP0 0x1030
	#define SYN_MTL_RXQ_DMA_MAP1 0x1034
	#define SYN_MTL_RXQ_DMA_MAP2 0x1038
	#define SYN_MTL_TC_PRIO_MAP0 0x1040
	#define SYN_MTL_TC_PRIO_MAP1 0x1044
	#define SYN_MTL_TXQ0_OPER_MODE 0x1100
	#define SYN_MTL_TXQ0_UNDERFLOW 0x1104
	#define SYN_MTL_TXQ0_DEBUG 0x1108
	#define SYN_MTL_TC0_ETS_CTL 0x1110
	#define SYN_MTL_TC0_ETS_STATUS 0x1114
	#define SYN_MTL_TC0_QUANTUM_WEIGHT 0x1118
	#define SYN_MTL_RXQ0_DEBUG 0x1148
	#define SYN_MTL_RXQ0_CTL 0x114c
	#define SYN_MTL_RXQ0_FLOW_CTL 0x1150
	#define SYN_MTL_Q0_INT_ENABLE 0x1170
	#define SYN_MTL_Q0_INT_STATUS 0x1174

	/* MTL Register Bit definitions */

	/*
	*
	DMA Register Offset
	*
	*/
	#define SYN_DMA_MODE 0x3000
	#define SYN_DMA_SYSBUS_MODE 0x3004
	#define SYN_DMA_INT_STATUS 0x3008
	#define SYN_DMA_AXI_TX_AR_ACE_CTL 0x3010
	#define SYN_DMA_AXI_RX_AW_ACE_CTL 0x3018
	#define SYN_DMA_AXI_TXRX_AWAR_ACE_CTL 0x301c
	#define SYN_DMA_DEBUG_STATUS0 0x3020
	#define SYN_DMA_DEBUG_STATUS1 0x3024
	#define SYN_DMA_TX_EDMA_CTL 0x3040
	#define SYN_DMA_RX_EDMA_CTL 0x3044
	#define SYN_DMA_CH0_CTL 0x3100
	#define SYN_DMA_CH0_TX_CTL 0x3104
	#define SYN_DMA_CH0_RX_CTL 0x3108
	#define SYN_DMA_CH0_TXDESC_LIST_HADDR 0x3110
	#define SYN_DMA_CH0_TXDESC_LIST_LADDR 0x3114
	#define SYN_DMA_CH0_RXDESC_LIST_HADDR 0x3118
	#define SYN_DMA_CH0_RXDESC_LIST_LADDR 0x311c
	#define SYN_DMA_CH0_TXDESC_TAIL_LPTR 0x3124
	#define SYN_DMA_CH0_RXDESC_TAIL_LPTR 0x312c
	#define SYN_DMA_CH0_TXDESC_RING_LEN 0x3130
	#define SYN_DMA_CH0_RXDESC_RING_LEN 0x3134
	#define SYN_DMA_INT_ENABLE 0x3138
	#define SYN_DMA_RX_INT_WDOG_TIMER 0x313c

	/* DMA Register Bit definitions */

	#endif /__SYN_REG_H__/