| /* |
| * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| * Permission to use, copy, modify, and/or distribute this software for |
| * any purpose with or without fee is hereby granted, provided that the |
| * above copyright notice and this permission notice appear in all copies. |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT |
| * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| */ |
| |
| |
| /** |
| * @defgroup |
| * @{ |
| */ |
| #include "sw.h" |
| #include "hsl.h" |
| #include "hppe_reg_access.h" |
| #include "hppe_qm_reg.h" |
| #include "hppe_qm.h" |
| |
| sw_error_t |
| hppe_queue_tx_counter_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union queue_tx_counter_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| NSS_PTX_CSR_BASE_ADDR + QUEUE_TX_COUNTER_TBL_ADDRESS + \ |
| index * QUEUE_TX_COUNTER_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_queue_tx_counter_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union queue_tx_counter_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| NSS_PTX_CSR_BASE_ADDR + QUEUE_TX_COUNTER_TBL_ADDRESS + \ |
| index * QUEUE_TX_COUNTER_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_get( |
| a_uint32_t dev_id, |
| union flush_cfg_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + FLUSH_CFG_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_set( |
| a_uint32_t dev_id, |
| union flush_cfg_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + FLUSH_CFG_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_in_mirror_priority_ctrl_get( |
| a_uint32_t dev_id, |
| union in_mirror_priority_ctrl_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + IN_MIRROR_PRIORITY_CTRL_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_in_mirror_priority_ctrl_set( |
| a_uint32_t dev_id, |
| union in_mirror_priority_ctrl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + IN_MIRROR_PRIORITY_CTRL_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_eg_mirror_priority_ctrl_get( |
| a_uint32_t dev_id, |
| union eg_mirror_priority_ctrl_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + EG_MIRROR_PRIORITY_CTRL_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_eg_mirror_priority_ctrl_set( |
| a_uint32_t dev_id, |
| union eg_mirror_priority_ctrl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + EG_MIRROR_PRIORITY_CTRL_ADDRESS, |
| value->val); |
| } |
| |
| #ifndef IN_QM_MINI |
| sw_error_t |
| hppe_ucast_default_hash_get( |
| a_uint32_t dev_id, |
| union ucast_default_hash_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_DEFAULT_HASH_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ucast_default_hash_set( |
| a_uint32_t dev_id, |
| union ucast_default_hash_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_DEFAULT_HASH_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_spare_reg0_get( |
| a_uint32_t dev_id, |
| union spare_reg0_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + SPARE_REG0_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_spare_reg0_set( |
| a_uint32_t dev_id, |
| union spare_reg0_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + SPARE_REG0_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_spare_reg1_get( |
| a_uint32_t dev_id, |
| union spare_reg1_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + SPARE_REG1_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_spare_reg1_set( |
| a_uint32_t dev_id, |
| union spare_reg1_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + SPARE_REG1_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_addr_get( |
| a_uint32_t dev_id, |
| union qm_dbg_addr_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + QM_DBG_ADDR_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_addr_set( |
| a_uint32_t dev_id, |
| union qm_dbg_addr_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + QM_DBG_ADDR_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_data_get( |
| a_uint32_t dev_id, |
| union qm_dbg_data_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + QM_DBG_DATA_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_data_set( |
| a_uint32_t dev_id, |
| union qm_dbg_data_u *value) |
| { |
| return SW_NOT_SUPPORTED; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map0_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map0_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP0_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP0_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP0_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map0_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map0_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP0_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP0_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map1_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map1_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP1_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP1_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP1_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map1_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map1_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP1_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP1_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map2_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map2_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP2_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP2_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP2_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map2_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map2_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP2_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP2_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map3_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map3_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP3_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP3_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP3_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map3_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map3_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP3_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP3_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map4_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map4_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP4_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP4_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP4_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map4_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map4_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP4_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP4_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map5_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map5_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP5_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP5_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP5_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map5_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map5_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP5_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP5_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map6_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map6_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP6_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP6_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP6_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map6_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map6_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP6_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP6_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map7_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map7_u *value) |
| { |
| if (index >= MCAST_PRIORITY_MAP7_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP7_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP7_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map7_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_priority_map7_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP7_ADDRESS + \ |
| index * MCAST_PRIORITY_MAP7_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_get( |
| a_uint32_t dev_id, |
| union agg_profile_cnt_en_u *value) |
| { |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AGG_PROFILE_CNT_EN_ADDRESS, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_set( |
| a_uint32_t dev_id, |
| union agg_profile_cnt_en_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AGG_PROFILE_CNT_EN_ADDRESS, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_profile_cfg_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_profile_cfg_u *value) |
| { |
| if (index >= UQ_AGG_PROFILE_CFG_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_CFG_ADDRESS + \ |
| index * UQ_AGG_PROFILE_CFG_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_profile_cfg_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_profile_cfg_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_CFG_ADDRESS + \ |
| index * UQ_AGG_PROFILE_CFG_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mq_agg_profile_cfg_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mq_agg_profile_cfg_u *value) |
| { |
| if (index >= MQ_AGG_PROFILE_CFG_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MQ_AGG_PROFILE_CFG_ADDRESS + \ |
| index * MQ_AGG_PROFILE_CFG_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mq_agg_profile_cfg_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mq_agg_profile_cfg_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MQ_AGG_PROFILE_CFG_ADDRESS + \ |
| index * MQ_AGG_PROFILE_CFG_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_grp_agg_profile_cfg_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union grp_agg_profile_cfg_u *value) |
| { |
| if (index >= GRP_AGG_PROFILE_CFG_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + GRP_AGG_PROFILE_CFG_ADDRESS + \ |
| index * GRP_AGG_PROFILE_CFG_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_grp_agg_profile_cfg_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union grp_agg_profile_cfg_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + GRP_AGG_PROFILE_CFG_ADDRESS + \ |
| index * GRP_AGG_PROFILE_CFG_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_in_profile_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_in_profile_cnt_u *value) |
| { |
| if (index >= UQ_AGG_IN_PROFILE_CNT_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_IN_PROFILE_CNT_ADDRESS + \ |
| index * UQ_AGG_IN_PROFILE_CNT_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_in_profile_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_in_profile_cnt_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_IN_PROFILE_CNT_ADDRESS + \ |
| index * UQ_AGG_IN_PROFILE_CNT_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_out_profile_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_out_profile_cnt_u *value) |
| { |
| if (index >= UQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ |
| index * UQ_AGG_OUT_PROFILE_CNT_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_out_profile_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_out_profile_cnt_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ |
| index * UQ_AGG_OUT_PROFILE_CNT_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mq_agg_in_profile_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mq_agg_in_profile_cnt_u *value) |
| { |
| if (index >= MQ_AGG_IN_PROFILE_CNT_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MQ_AGG_IN_PROFILE_CNT_ADDRESS + \ |
| index * MQ_AGG_IN_PROFILE_CNT_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mq_agg_in_profile_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mq_agg_in_profile_cnt_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MQ_AGG_IN_PROFILE_CNT_ADDRESS + \ |
| index * MQ_AGG_IN_PROFILE_CNT_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mq_agg_out_profile_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mq_agg_out_profile_cnt_u *value) |
| { |
| if (index >= MQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ |
| index * MQ_AGG_OUT_PROFILE_CNT_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mq_agg_out_profile_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mq_agg_out_profile_cnt_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ |
| index * MQ_AGG_OUT_PROFILE_CNT_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_grp_agg_in_profile_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union grp_agg_in_profile_cnt_u *value) |
| { |
| if (index >= GRP_AGG_IN_PROFILE_CNT_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + GRP_AGG_IN_PROFILE_CNT_ADDRESS + \ |
| index * GRP_AGG_IN_PROFILE_CNT_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_grp_agg_in_profile_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union grp_agg_in_profile_cnt_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + GRP_AGG_IN_PROFILE_CNT_ADDRESS + \ |
| index * GRP_AGG_IN_PROFILE_CNT_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_grp_agg_out_profile_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union grp_agg_out_profile_cnt_u *value) |
| { |
| if (index >= GRP_AGG_OUT_PROFILE_CNT_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + GRP_AGG_OUT_PROFILE_CNT_ADDRESS + \ |
| index * GRP_AGG_OUT_PROFILE_CNT_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_grp_agg_out_profile_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union grp_agg_out_profile_cnt_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + GRP_AGG_OUT_PROFILE_CNT_ADDRESS + \ |
| index * GRP_AGG_OUT_PROFILE_CNT_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_ucast_queue_map_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ucast_queue_map_tbl_u *value) |
| { |
| if (index >= UCAST_QUEUE_MAP_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_QUEUE_MAP_TBL_ADDRESS + \ |
| index * UCAST_QUEUE_MAP_TBL_INC, |
| &value->val); |
| } |
| #endif |
| |
| sw_error_t |
| hppe_ucast_queue_map_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ucast_queue_map_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_QUEUE_MAP_TBL_ADDRESS + \ |
| index * UCAST_QUEUE_MAP_TBL_INC, |
| value->val); |
| } |
| |
| #ifndef IN_QM_MINI |
| sw_error_t |
| hppe_ucast_hash_map_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ucast_hash_map_tbl_u *value) |
| { |
| if (index >= UCAST_HASH_MAP_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_HASH_MAP_TBL_ADDRESS + \ |
| index * UCAST_HASH_MAP_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ucast_hash_map_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ucast_hash_map_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_HASH_MAP_TBL_ADDRESS + \ |
| index * UCAST_HASH_MAP_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_ucast_priority_map_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ucast_priority_map_tbl_u *value) |
| { |
| if (index >= UCAST_PRIORITY_MAP_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_PRIORITY_MAP_TBL_ADDRESS + \ |
| index * UCAST_PRIORITY_MAP_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ucast_priority_map_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ucast_priority_map_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UCAST_PRIORITY_MAP_TBL_ADDRESS + \ |
| index * UCAST_PRIORITY_MAP_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_queue_map_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_queue_map_tbl_u *value) |
| { |
| if (index >= MCAST_QUEUE_MAP_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_QUEUE_MAP_TBL_ADDRESS + \ |
| index * MCAST_QUEUE_MAP_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_mcast_queue_map_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mcast_queue_map_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MCAST_QUEUE_MAP_TBL_ADDRESS + \ |
| index * MCAST_QUEUE_MAP_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_mseq_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mseq_tbl_u *value) |
| { |
| if (index >= AC_MSEQ_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MSEQ_TBL_ADDRESS + \ |
| index * AC_MSEQ_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_mseq_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mseq_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MSEQ_TBL_ADDRESS + \ |
| index * AC_MSEQ_TBL_INC, |
| value->val); |
| } |
| #endif |
| |
| sw_error_t |
| hppe_ac_uni_queue_cfg_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_uni_queue_cfg_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CFG_TBL_ADDRESS + \ |
| index * AC_UNI_QUEUE_CFG_TBL_INC, |
| value->val, |
| 4); |
| } |
| |
| sw_error_t |
| hppe_ac_uni_queue_cfg_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_uni_queue_cfg_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CFG_TBL_ADDRESS + \ |
| index * AC_UNI_QUEUE_CFG_TBL_INC, |
| value->val, |
| 4); |
| } |
| |
| sw_error_t |
| hppe_ac_mul_queue_cfg_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mul_queue_cfg_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CFG_TBL_ADDRESS + \ |
| index * AC_MUL_QUEUE_CFG_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_ac_mul_queue_cfg_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mul_queue_cfg_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CFG_TBL_ADDRESS + \ |
| index * AC_MUL_QUEUE_CFG_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_ac_grp_cfg_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_grp_cfg_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_GRP_CFG_TBL_ADDRESS + \ |
| index * AC_GRP_CFG_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_ac_grp_cfg_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_grp_cfg_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_GRP_CFG_TBL_ADDRESS + \ |
| index * AC_GRP_CFG_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| #ifndef IN_QM_MINI |
| sw_error_t |
| hppe_ac_uni_queue_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_uni_queue_cnt_tbl_u *value) |
| { |
| if (index >= AC_UNI_QUEUE_CNT_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CNT_TBL_ADDRESS + \ |
| index * AC_UNI_QUEUE_CNT_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_uni_queue_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_uni_queue_cnt_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CNT_TBL_ADDRESS + \ |
| index * AC_UNI_QUEUE_CNT_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_mul_queue_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mul_queue_cnt_tbl_u *value) |
| { |
| if (index >= AC_MUL_QUEUE_CNT_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CNT_TBL_ADDRESS + \ |
| index * AC_MUL_QUEUE_CNT_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_mul_queue_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mul_queue_cnt_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CNT_TBL_ADDRESS + \ |
| index * AC_MUL_QUEUE_CNT_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_grp_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_grp_cnt_tbl_u *value) |
| { |
| if (index >= AC_GRP_CNT_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_GRP_CNT_TBL_ADDRESS + \ |
| index * AC_GRP_CNT_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_grp_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_grp_cnt_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_GRP_CNT_TBL_ADDRESS + \ |
| index * AC_GRP_CNT_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_ac_uni_queue_drop_state_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_uni_queue_drop_state_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS + \ |
| index * AC_UNI_QUEUE_DROP_STATE_TBL_INC, |
| value->val, |
| 2); |
| } |
| |
| sw_error_t |
| hppe_ac_uni_queue_drop_state_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_uni_queue_drop_state_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS + \ |
| index * AC_UNI_QUEUE_DROP_STATE_TBL_INC, |
| value->val, |
| 2); |
| } |
| |
| sw_error_t |
| hppe_ac_mul_queue_drop_state_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mul_queue_drop_state_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS + \ |
| index * AC_MUL_QUEUE_DROP_STATE_TBL_INC, |
| value->val, |
| 2); |
| } |
| |
| sw_error_t |
| hppe_ac_mul_queue_drop_state_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_mul_queue_drop_state_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS + \ |
| index * AC_MUL_QUEUE_DROP_STATE_TBL_INC, |
| value->val, |
| 2); |
| } |
| |
| sw_error_t |
| hppe_ac_grp_drop_state_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_grp_drop_state_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_GRP_DROP_STATE_TBL_ADDRESS + \ |
| index * AC_GRP_DROP_STATE_TBL_INC, |
| value->val, |
| 2); |
| } |
| |
| sw_error_t |
| hppe_ac_grp_drop_state_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union ac_grp_drop_state_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + AC_GRP_DROP_STATE_TBL_ADDRESS + \ |
| index * AC_GRP_DROP_STATE_TBL_INC, |
| value->val, |
| 2); |
| } |
| |
| sw_error_t |
| hppe_oq_enq_opr_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_enq_opr_tbl_u *value) |
| { |
| if (index >= OQ_ENQ_OPR_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_ENQ_OPR_TBL_ADDRESS + \ |
| index * OQ_ENQ_OPR_TBL_INC, |
| &value->val); |
| } |
| #endif |
| |
| sw_error_t |
| hppe_oq_enq_opr_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_enq_opr_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_ENQ_OPR_TBL_ADDRESS + \ |
| index * OQ_ENQ_OPR_TBL_INC, |
| value->val); |
| } |
| |
| #ifndef IN_QM_MINI |
| sw_error_t |
| hppe_oq_deq_opr_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_deq_opr_tbl_u *value) |
| { |
| if (index >= OQ_DEQ_OPR_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_DEQ_OPR_TBL_ADDRESS + \ |
| index * OQ_DEQ_OPR_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_deq_opr_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_deq_opr_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_DEQ_OPR_TBL_ADDRESS + \ |
| index * OQ_DEQ_OPR_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_head_uni_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_head_uni_tbl_u *value) |
| { |
| if (index >= OQ_HEAD_UNI_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_UNI_TBL_ADDRESS + \ |
| index * OQ_HEAD_UNI_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_head_uni_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_head_uni_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_UNI_TBL_ADDRESS + \ |
| index * OQ_HEAD_UNI_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_head_mul_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_head_mul_tbl_u *value) |
| { |
| if (index >= OQ_HEAD_MUL_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_MUL_TBL_ADDRESS + \ |
| index * OQ_HEAD_MUL_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_head_mul_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_head_mul_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_MUL_TBL_ADDRESS + \ |
| index * OQ_HEAD_MUL_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_uni_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_uni_tbl_u *value) |
| { |
| if (index >= OQ_LL_UNI_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_UNI_TBL_ADDRESS + \ |
| index * OQ_LL_UNI_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_uni_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_uni_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_UNI_TBL_ADDRESS + \ |
| index * OQ_LL_UNI_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p0_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p0_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P0_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P0_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P0_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p0_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p0_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P0_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P0_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p1_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p1_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P1_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P1_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P1_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p1_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p1_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P1_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P1_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p2_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p2_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P2_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P2_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P2_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p2_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p2_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P2_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P2_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p3_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p3_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P3_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P3_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P3_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p3_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p3_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P3_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P3_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p4_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p4_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P4_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P4_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P4_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p4_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p4_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P4_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P4_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p5_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p5_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P5_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P5_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P5_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p5_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p5_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P5_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P5_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p6_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p6_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P6_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P6_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P6_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p6_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p6_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P6_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P6_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p7_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p7_tbl_u *value) |
| { |
| if (index >= OQ_LL_MUL_P7_TBL_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P7_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P7_TBL_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_oq_ll_mul_p7_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union oq_ll_mul_p7_tbl_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P7_TBL_ADDRESS + \ |
| index * OQ_LL_MUL_P7_TBL_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_pkt_desp_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union pkt_desp_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + PKT_DESP_TBL_ADDRESS + \ |
| index * PKT_DESP_TBL_INC, |
| value->val, |
| 13); |
| } |
| |
| sw_error_t |
| hppe_pkt_desp_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union pkt_desp_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + PKT_DESP_TBL_ADDRESS + \ |
| index * PKT_DESP_TBL_INC, |
| value->val, |
| 13); |
| } |
| |
| sw_error_t |
| hppe_uni_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uni_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UNI_DROP_CNT_TBL_ADDRESS + \ |
| index * UNI_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_uni_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uni_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UNI_DROP_CNT_TBL_ADDRESS + \ |
| index * UNI_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p0_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p0_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P0_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P0_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p0_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p0_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P0_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P0_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p1_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p1_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P1_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P1_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p1_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p1_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P1_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P1_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p2_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p2_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P2_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P2_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p2_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p2_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P2_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P2_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p3_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p3_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P3_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P3_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p3_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p3_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P3_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P3_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p4_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p4_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P4_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P4_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p4_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p4_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P4_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P4_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p5_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p5_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P5_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P5_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p5_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p5_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P5_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P5_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p6_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p6_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P6_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P6_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p6_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p6_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P6_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P6_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p7_drop_cnt_tbl_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p7_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P7_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P7_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_mul_p7_drop_cnt_tbl_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union mul_p7_drop_cnt_tbl_u *value) |
| { |
| return hppe_reg_tbl_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + MUL_P7_DROP_CNT_TBL_ADDRESS + \ |
| index * MUL_P7_DROP_CNT_TBL_INC, |
| value->val, |
| 3); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_profile_map_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_profile_map_u *value) |
| { |
| if (index >= UQ_AGG_PROFILE_MAP_MAX_ENTRY) |
| return SW_OUT_OF_RANGE; |
| return hppe_reg_get( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_MAP_ADDRESS + \ |
| index * UQ_AGG_PROFILE_MAP_INC, |
| &value->val); |
| } |
| |
| sw_error_t |
| hppe_uq_agg_profile_map_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| union uq_agg_profile_map_u *value) |
| { |
| return hppe_reg_set( |
| dev_id, |
| QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_MAP_ADDRESS + \ |
| index * UQ_AGG_PROFILE_MAP_INC, |
| value->val); |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_busy_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| *value = reg_val.bf.flush_busy; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_busy_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.flush_busy = value; |
| ret = hppe_flush_cfg_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_qid_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| *value = reg_val.bf.flush_qid; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_qid_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.flush_qid = value; |
| ret = hppe_flush_cfg_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_dst_port_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| *value = reg_val.bf.flush_dst_port; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_dst_port_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.flush_dst_port = value; |
| ret = hppe_flush_cfg_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_all_queues_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| *value = reg_val.bf.flush_all_queues; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_all_queues_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.flush_all_queues = value; |
| ret = hppe_flush_cfg_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_wt_time_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| *value = reg_val.bf.flush_wt_time; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_wt_time_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.flush_wt_time = value; |
| ret = hppe_flush_cfg_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_status_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| *value = reg_val.bf.flush_status; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_flush_cfg_flush_status_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union flush_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_flush_cfg_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.flush_status = value; |
| ret = hppe_flush_cfg_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_in_mirror_priority_ctrl_priority_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union in_mirror_priority_ctrl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_in_mirror_priority_ctrl_get(dev_id, ®_val); |
| *value = reg_val.bf.priority; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_in_mirror_priority_ctrl_priority_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union in_mirror_priority_ctrl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_in_mirror_priority_ctrl_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.priority = value; |
| ret = hppe_in_mirror_priority_ctrl_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_eg_mirror_priority_ctrl_priority_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union eg_mirror_priority_ctrl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_eg_mirror_priority_ctrl_get(dev_id, ®_val); |
| *value = reg_val.bf.priority; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_eg_mirror_priority_ctrl_priority_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union eg_mirror_priority_ctrl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_eg_mirror_priority_ctrl_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.priority = value; |
| ret = hppe_eg_mirror_priority_ctrl_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_default_hash_hash_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union ucast_default_hash_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_default_hash_get(dev_id, ®_val); |
| *value = reg_val.bf.hash; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_default_hash_hash_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union ucast_default_hash_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_default_hash_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.hash = value; |
| ret = hppe_ucast_default_hash_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_spare_reg0_spare_reg0_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union spare_reg0_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_spare_reg0_get(dev_id, ®_val); |
| *value = reg_val.bf.spare_reg0; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_spare_reg0_spare_reg0_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union spare_reg0_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_spare_reg0_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.spare_reg0 = value; |
| ret = hppe_spare_reg0_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_spare_reg1_spare_reg1_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union spare_reg1_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_spare_reg1_get(dev_id, ®_val); |
| *value = reg_val.bf.spare_reg1; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_spare_reg1_spare_reg1_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union spare_reg1_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_spare_reg1_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.spare_reg1 = value; |
| ret = hppe_spare_reg1_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_addr_dbg_addr_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union qm_dbg_addr_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_qm_dbg_addr_get(dev_id, ®_val); |
| *value = reg_val.bf.dbg_addr; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_addr_dbg_addr_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union qm_dbg_addr_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_qm_dbg_addr_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.dbg_addr = value; |
| ret = hppe_qm_dbg_addr_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_data_dbg_data_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union qm_dbg_data_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_qm_dbg_data_get(dev_id, ®_val); |
| *value = reg_val.bf.dbg_data; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_qm_dbg_data_dbg_data_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| return SW_NOT_SUPPORTED; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map0_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map0_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map0_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map0_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map0_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map0_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map0_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map1_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map1_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map1_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map1_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map1_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map1_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map1_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map2_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map2_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map2_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map2_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map2_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map2_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map2_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map3_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map3_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map3_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map3_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map3_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map3_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map3_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map4_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map4_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map4_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map4_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map4_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map4_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map4_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map5_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map5_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map5_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map5_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map5_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map5_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map5_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map6_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map6_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map6_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map6_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map6_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map6_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map6_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map7_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_priority_map7_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map7_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_priority_map7_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_priority_map7_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_priority_map7_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_priority_map7_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p2_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p2_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p2_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p2_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_1_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_1; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_1_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_1 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p0_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p0_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p0_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p0_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_1_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.grp_1_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_1_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.grp_1_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_0_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.grp_0_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_0_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.grp_0_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p6_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p6_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p6_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p6_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_3_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_3; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_3_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_3 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p4_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p4_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p4_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p4_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_2_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_2; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_2_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_2 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_5_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_5; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_5_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_5 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_6_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_6; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_6_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_6 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_3_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.grp_3_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_3_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.grp_3_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_2_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.grp_2_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_grp_2_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.grp_2_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_4_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_4; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_4_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_4 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p7_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p7_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p7_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p7_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_7_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_7; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_7_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_7 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_global_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.global_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_global_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.global_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p5_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p5_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p5_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p5_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p1_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p1_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p1_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p1_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_0_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.uq_en_0; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_uq_en_0_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.uq_en_0 = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p3_en_get( |
| a_uint32_t dev_id, |
| a_uint32_t *value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| *value = reg_val.bf.mq_p3_en; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_agg_profile_cnt_en_mq_p3_en_set( |
| a_uint32_t dev_id, |
| a_uint32_t value) |
| { |
| union agg_profile_cnt_en_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.mq_p3_en = value; |
| ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_uq_agg_profile_cfg_th_cfg_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union uq_agg_profile_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_uq_agg_profile_cfg_get(dev_id, index, ®_val); |
| *value = reg_val.bf.th_cfg; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_uq_agg_profile_cfg_th_cfg_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union uq_agg_profile_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_uq_agg_profile_cfg_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.th_cfg = value; |
| ret = hppe_uq_agg_profile_cfg_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mq_agg_profile_cfg_th_cfg_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mq_agg_profile_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mq_agg_profile_cfg_get(dev_id, index, ®_val); |
| *value = reg_val.bf.th_cfg; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mq_agg_profile_cfg_th_cfg_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mq_agg_profile_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mq_agg_profile_cfg_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.th_cfg = value; |
| ret = hppe_mq_agg_profile_cfg_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_grp_agg_profile_cfg_th_cfg_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union grp_agg_profile_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_grp_agg_profile_cfg_get(dev_id, index, ®_val); |
| *value = reg_val.bf.th_cfg; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_grp_agg_profile_cfg_th_cfg_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union grp_agg_profile_cfg_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_grp_agg_profile_cfg_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.th_cfg = value; |
| ret = hppe_grp_agg_profile_cfg_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_uq_agg_in_profile_cnt_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union uq_agg_in_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_uq_agg_in_profile_cnt_get(dev_id, index, ®_val); |
| *value = reg_val.bf.cnt; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_uq_agg_in_profile_cnt_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union uq_agg_in_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_uq_agg_in_profile_cnt_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.cnt = value; |
| ret = hppe_uq_agg_in_profile_cnt_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_uq_agg_out_profile_cnt_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union uq_agg_out_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_uq_agg_out_profile_cnt_get(dev_id, index, ®_val); |
| *value = reg_val.bf.cnt; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_uq_agg_out_profile_cnt_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union uq_agg_out_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_uq_agg_out_profile_cnt_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.cnt = value; |
| ret = hppe_uq_agg_out_profile_cnt_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mq_agg_in_profile_cnt_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mq_agg_in_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mq_agg_in_profile_cnt_get(dev_id, index, ®_val); |
| *value = reg_val.bf.cnt; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mq_agg_in_profile_cnt_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mq_agg_in_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mq_agg_in_profile_cnt_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.cnt = value; |
| ret = hppe_mq_agg_in_profile_cnt_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mq_agg_out_profile_cnt_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mq_agg_out_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mq_agg_out_profile_cnt_get(dev_id, index, ®_val); |
| *value = reg_val.bf.cnt; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mq_agg_out_profile_cnt_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mq_agg_out_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mq_agg_out_profile_cnt_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.cnt = value; |
| ret = hppe_mq_agg_out_profile_cnt_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_grp_agg_in_profile_cnt_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union grp_agg_in_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_grp_agg_in_profile_cnt_get(dev_id, index, ®_val); |
| *value = reg_val.bf.cnt; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_grp_agg_in_profile_cnt_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union grp_agg_in_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_grp_agg_in_profile_cnt_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.cnt = value; |
| ret = hppe_grp_agg_in_profile_cnt_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_grp_agg_out_profile_cnt_cnt_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union grp_agg_out_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_grp_agg_out_profile_cnt_get(dev_id, index, ®_val); |
| *value = reg_val.bf.cnt; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_grp_agg_out_profile_cnt_cnt_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union grp_agg_out_profile_cnt_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_grp_agg_out_profile_cnt_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.cnt = value; |
| ret = hppe_grp_agg_out_profile_cnt_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_queue_map_tbl_profile_id_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union ucast_queue_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.profile_id; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_queue_map_tbl_profile_id_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union ucast_queue_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.profile_id = value; |
| ret = hppe_ucast_queue_map_tbl_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_queue_map_tbl_queue_id_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union ucast_queue_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.queue_id; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_queue_map_tbl_queue_id_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union ucast_queue_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.queue_id = value; |
| ret = hppe_ucast_queue_map_tbl_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_hash_map_tbl_hash_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union ucast_hash_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_hash_map_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.hash; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_hash_map_tbl_hash_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union ucast_hash_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_hash_map_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.hash = value; |
| ret = hppe_ucast_hash_map_tbl_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_priority_map_tbl_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union ucast_priority_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_priority_map_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ucast_priority_map_tbl_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union ucast_priority_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ucast_priority_map_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_ucast_priority_map_tbl_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_queue_map_tbl_class_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union mcast_queue_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_queue_map_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.class; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_mcast_queue_map_tbl_class_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union mcast_queue_map_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_mcast_queue_map_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.class = value; |
| ret = hppe_mcast_queue_map_tbl_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ac_mseq_tbl_ac_mseq_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union ac_mseq_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ac_mseq_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.ac_mseq; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ac_mseq_tbl_ac_mseq_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union ac_mseq_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ac_mseq_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.ac_mseq = value; |
| ret = hppe_ac_mseq_tbl_set(dev_id, index, ®_val); |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_get( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t *value) |
| { |
| union ac_uni_queue_cfg_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); |
| *value = reg_val.bf.ac_cfg_gap_grn_yel_max; |
| return ret; |
| } |
| |
| sw_error_t |
| hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_set( |
| a_uint32_t dev_id, |
| a_uint32_t index, |
| a_uint32_t value) |
| { |
| union ac_uni_queue_cfg_tbl_u reg_val; |
| sw_error_t ret = SW_OK; |
| |
| ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); |
| if (SW_OK != ret) |
| return ret; |
| reg_val.bf.ac_cfg_gap_grn_yel_max = value; |
| ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val |
