Project import generated by Copybara.
GitOrigin-RevId: 93d41fed737e3bd6bce48340d6ad2df5dfda1dc8
diff --git a/.checkpatch.conf b/.checkpatch.conf
index 35167e1..95f1963 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -21,3 +21,10 @@
# Ignore networking block comment style
--ignore NETWORKING_BLOCK_COMMENT_STYLE
+
+# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet
+# addresses are __aligned(2)".
+--ignore PREFER_ETHER_ADDR_COPY
+
+# A bit shorter of a description is OK with us.
+--min-conf-desc-length=2
diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
new file mode 100644
index 0000000..23599b9
--- /dev/null
+++ b/.github/pull_request_template.md
@@ -0,0 +1,3 @@
+Please do not submit a Pull Request via github. Our project makes use of
+mailing lists for patch submission and review. For more details please
+see https://www.denx.de/wiki/U-Boot/Patches
diff --git a/.mailmap b/.mailmap
index e1c6663..1bee048 100644
--- a/.mailmap
+++ b/.mailmap
@@ -10,13 +10,21 @@
Allen Martin <amartin@nvidia.com>
Andreas Bießmann <andreas.devel@googlemail.com>
+Andreas Bießmann <andreas@biessmann.org>
Aneesh V <aneesh@ti.com>
Dirk Behme <dirk.behme@googlemail.com>
-Fabio Estevam <fabio.estevam@freescale.com>
-Jagannadha Sutradharudu Teki <402jagan@gmail.com>
+Fabio Estevam <fabio.estevam@nxp.com>
+Jagan Teki <402jagan@gmail.com>
+Jagan Teki <jaganna@gmail.com>
+Jagan Teki <jaganna@xilinx.com>
+Jagan Teki <jagannadh.teki@gmail.com>
+Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Markus Klotzbuecher <mk@denx.de>
+Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Ricardo Ribalda <ricardo.ribalda@uam.es>
+Ricardo Ribalda <ricardo.ribalda@gmail.com>
Sandeep Paulraj <s-paulraj@ti.com>
Shaohui Xie <Shaohui.Xie@freescale.com>
Stefan Roese <stroese>
@@ -24,4 +32,7 @@
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Wolfgang Denk <wdenk>
York Sun <yorksun@freescale.com>
+York Sun <york.sun@nxp.com>
Łukasz Majewski <l.majewski@samsung.com>
+Lukasz Majewski <lukma@denx.de>
+Mirza <Taimoor_Mirza@mentor.com>
diff --git a/.travis.yml b/.travis.yml
new file mode 100644
index 0000000..321fd79
--- /dev/null
+++ b/.travis.yml
@@ -0,0 +1,465 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright Roger Meier <r.meier@siemens.com>
+
+# build U-Boot on Travis CI - https://travis-ci.org/
+
+sudo: required
+dist: trusty
+
+language: c
+
+addons:
+ apt:
+ sources:
+ - ubuntu-toolchain-r-test
+ - llvm-toolchain-trusty-7
+ packages:
+ - cppcheck
+ - sloccount
+ - sparse
+ - bc
+ - build-essential
+ - libsdl1.2-dev
+ - python
+ - python-virtualenv
+ - swig
+ - libpython-dev
+ - iasl
+ - grub-efi-ia32-bin
+ - grub-efi-amd64-bin
+ - rpm2cpio
+ - wget
+ - device-tree-compiler
+ - lzop
+ - liblz4-tool
+ - libisl15
+ - clang-7
+
+install:
+ # Clone uboot-test-hooks
+ - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
+ - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
+ - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
+ # prepare buildman environment
+ - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
+ - echo -e "arc = /tmp/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh2\n" >> ~/.buildman
+ - cat ~/.buildman
+ - virtualenv /tmp/venv
+ - . /tmp/venv/bin/activate
+ - pip install pytest==2.8.7
+ - pip install python-subunit
+ - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - mkdir ~/grub2-arm
+ - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
+ - mkdir ~/grub2-arm64
+ - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
+
+env:
+ global:
+ - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
+ - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
+ - BUILD_DIR=build
+ - HOSTCC="cc"
+ - HOSTCXX="c++"
+
+before_script:
+ # install toolchains based on TOOLCHAIN} variable
+ - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
+ - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
+ - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
+ - if [[ "${TOOLCHAIN}" == *sh* ]]; then ./tools/buildman/buildman --fetch-arch sh2 ; fi
+ - if [[ "${TOOLCHAIN}" == *i386* ]]; then
+ ./tools/buildman/buildman --fetch-arch i386;
+ echo -e "\n[toolchain-alias]\nx86 = i386" >> ~/.buildman;
+ fi
+ - if [[ "${TOOLCHAIN}" == arc ]]; then
+ wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
+ tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
+ fi
+ - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
+ wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
+ tar -C /tmp -xf x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
+ echo -e "\n[toolchain-prefix]\nxtensa = /tmp/2018.02/${TOOLCHAIN}/bin/${TOOLCHAIN}-" >> ~/.buildman;
+ fi
+ # If TOOLCHAIN is unset, we're on some flavour of ARM.
+ - if [[ "${TOOLCHAIN}" == "" ]]; then
+ ./tools/buildman/buildman --fetch-arch arm &&
+ ./tools/buildman/buildman --fetch-arch aarch64;
+ fi
+ - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi
+ - if [[ "${TOOLCHAIN}" == "riscv" ]]; then
+ ./tools/buildman/buildman --fetch-arch riscv64;
+ echo -e "\n[toolchain-alias]\nriscv = riscv64" >> ~/.buildman;
+ fi
+ - if [[ "${QEMU_TARGET}" != "" ]]; then
+ git clone git://git.qemu.org/qemu.git /tmp/qemu;
+ pushd /tmp/qemu;
+ git submodule update --init dtc &&
+ git checkout v3.0.0 &&
+ ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
+ make -j4 all install;
+ popd;
+ fi
+
+script:
+ # Comments must be outside the command strings below, or the Travis parser
+ # will get confused.
+ #
+ # From buildman, exit code 129 means warnings only. If we've been asked to
+ # use clang only do one configuration.
+ - if [[ "${TOOLCHAIN}" == "clang" ]]; then
+ ret=0;
+ make O=../.bm-work/${TEST_PY_BD} HOSTCC=clang-7 CC=clang-7 -j$(nproc)
+ KCFLAGS=-Werror sandbox_config all || ret=$?;
+ if [[ $ret -ne 0 ]]; then
+ exit $ret;
+ fi;
+ elif [[ "${BUILDMAN}" != "" ]]; then
+ ret=0;
+ tools/buildman/buildman -P -E ${BUILDMAN} || ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ tools/buildman/buildman -sdeP ${BUILDMAN};
+ exit $ret;
+ fi;
+ fi
+ # "not a_test_which_does_not_exist" is a dummy -k parameter which will
+ # never prevent any test from running. That way, we can always pass
+ # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
+ # value.
+ - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
+ cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
+ cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/;
+ cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
+ cp ~/grub2-arm64/usr/lib/grub2/arm64-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi;
+ if [[ "${TEST_PY_BD}" != "" ]]; then
+ ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
+ -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
+ --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+ ret=$?;
+ if [[ $ret -ne 0 ]]; then
+ exit $ret;
+ fi;
+ fi;
+ if [[ -n "${TEST_PY_TOOLS}" ]]; then
+ PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+ PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
+ ./tools/binman/binman -t &&
+ ./tools/patman/patman --test &&
+ ./tools/buildman/buildman -t &&
+ PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+ PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
+ ./tools/dtoc/dtoc -t;
+ fi
+
+matrix:
+ include:
+ # we need to build by vendor due to 50min time limit for builds
+ # each env setting here is a dedicated build
+ - name: "buildman arc"
+ env:
+ - BUILDMAN="arc"
+ TOOLCHAIN="arc"
+ - name: "buildman arm11 arm7 arm920t arm946es"
+ env:
+ - BUILDMAN="arm11 arm7 arm920t arm946es"
+ - name: "buildman arm926ejs (non-freescale,siemens,atmel,kirkwood,spear)"
+ env:
+ - JOB="arm926ejs"
+ BUILDMAN="arm926ejs -x freescale,siemens,atmel,kirkwood,spear"
+ - name: "buildman atmel"
+ env:
+ - BUILDMAN="atmel"
+ - name: "buildman boundary engicam toradex"
+ env:
+ - BUILDMAN="boundary engicam toradex"
+ - name: "buildman Freescale ARM32"
+ env:
+ - BUILDMAN="freescale -x powerpc,m68k,aarch64"
+ - name: "buildman Freescale AArch64 LS10xx"
+ env:
+ - BUILDMAN="freescale&aarch64&&ls1"
+ - name: "buildman Freescale AArch64 LS20xx"
+ env:
+ - BUILDMAN="freescale&aarch64&&ls2"
+ - name: "buildman i.MX6 (non-Freescale)"
+ env:
+ - BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
+ - name: "buildman i.MX (non-Freescale,i.MX6,toradex)"
+ env:
+ - BUILDMAN="mx -x freescale,mx6,toradex"
+ - name: "buildman k2"
+ env:
+ - BUILDMAN="k2"
+ - name: "buildman samsung socfpga"
+ env:
+ - BUILDMAN="samsung socfpga"
+ - name: "buildman spear"
+ env:
+ - BUILDMAN="spear"
+ - name: "buildman sun4i"
+ env:
+ - BUILDMAN="sun4i"
+ - name: "buildman sun5i"
+ env:
+ - BUILDMAN="sun5i"
+ - name: "buildman sun6i"
+ env:
+ - BUILDMAN="sun6i"
+ - name: "buildman sun7i"
+ env:
+ - BUILDMAN="sun7i"
+ - name: "buildman sun8i"
+ env:
+ - BUILDMAN="sun8i"
+ - name: "buildman sun9i"
+ env:
+ - BUILDMAN="sun9i"
+ - name: "buildman sun50i"
+ env:
+ - BUILDMAN="sun50i"
+ - name: "buildman catch-all ARM"
+ env:
+ - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
+ - name: "buildman sandbox x86"
+ env:
+ - BUILDMAN="sandbox x86"
+ TOOLCHAIN="i386"
+ - name: "buildman kirkwood (excluding openrd)"
+ env:
+ - BUILDMAN="kirkwood -x openrd"
+ - name: "buildman mvebu"
+ env:
+ - BUILDMAN="mvebu"
+ - name: "buildman PXA (non-toradex)"
+ env:
+ - BUILDMAN="pxa -x toradex"
+ - name: "buildman m68k"
+ env:
+ - BUILDMAN="m68k"
+ TOOLCHAIN="m68k"
+ - name: "buildman microblaze"
+ env:
+ - BUILDMAN="microblaze"
+ TOOLCHAIN="microblaze"
+ - name: "buildman mips"
+ env:
+ - BUILDMAN="mips"
+ TOOLCHAIN="mips"
+ - name: "buildman non-Freescale PowerPC"
+ env:
+ - BUILDMAN="powerpc -x freescale"
+ TOOLCHAIN="powerpc"
+ - name: "buildman mpc85xx&freescale (excluding many)"
+ env:
+ - BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+ TOOLCHAIN="powerpc"
+ - name: "buildman t208xrdb corenet_ds"
+ env:
+ - BUILDMAN="t208xrdb corenet_ds"
+ TOOLCHAIN="powerpc"
+ - name: "buildman Freescale PowerPC"
+ env:
+ - BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
+ TOOLCHAIN="powerpc"
+ - name: "buildman t102*"
+ env:
+ - BUILDMAN="t102*"
+ TOOLCHAIN="powerpc"
+ - name: "buildman p1_p2_rdb_pc"
+ env:
+ - BUILDMAN="p1_p2_rdb_pc"
+ TOOLCHAIN="powerpc"
+ - name: "buildman p1010rdb bsc91"
+ env:
+ - BUILDMAN="p1010rdb bsc91"
+ TOOLCHAIN="powerpc"
+ - name: "buildman siemens"
+ env:
+ - BUILDMAN="siemens"
+ - name: "buildman tegra"
+ env:
+ - BUILDMAN="tegra -x toradex"
+ - name: "buildman am33xx (no siemens)"
+ env:
+ - BUILDMAN="am33xx -x siemens"
+ - name: "buildman omap"
+ env:
+ - BUILDMAN="omap"
+ - name: "buildman uniphier"
+ env:
+ - BUILDMAN="uniphier"
+ - name: "buildman catch-all AArch64"
+ env:
+ - BUILDMAN="aarch64 -x tegra,ls1,ls2,mvebu,uniphier,sunxi,samsung,rockchip,xilinx"
+ - name: "buildman rockchip"
+ env:
+ - BUILDMAN="rockchip"
+ - name: "buildman sh"
+ env:
+ - BUILDMAN="sh -x arm"
+ TOOLCHAIN="sh"
+ - name: "buildman Xilinx (ARM)"
+ env:
+ - BUILDMAN="xilinx -x microblaze"
+ - name: "buildman xtensa"
+ env:
+ - BUILDMAN="xtensa"
+ TOOLCHAIN="xtensa-dc233c-elf"
+ - name: "buildman riscv"
+ env:
+ - BUILDMAN="riscv"
+ TOOLCHAIN="riscv"
+
+ # QA jobs for code analytics
+ # static code analysis with cppcheck (we can add --enable=all later)
+ - name: "cppcheck"
+ script:
+ - cppcheck --force --quiet --inline-suppr .
+ # search for TODO within source tree
+ - name: "grep TODO"
+ script:
+ - grep -r TODO .
+ # search for FIXME within source tree
+ - name: "grep FIXME HACK"
+ script:
+ - grep -r FIXME .
+ # search for HACK within source tree and ignore HACKKIT board
+ script:
+ - grep -r HACK . | grep -v HACKKIT
+ # some statistics about the code base
+ - name: "sloccount"
+ script:
+ - sloccount .
+ # ensure all configs have MAINTAINERS entries
+ - name: "Check for configs without MAINTAINERS entry"
+ script:
+ - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
+ # Ensure host tools build
+ - name: "Build tools-only"
+ script:
+ - make tools-only_config tools-only -j$(nproc)
+
+ # test/py
+ - name: "test/py sandbox"
+ env:
+ - TEST_PY_BD="sandbox"
+ BUILDMAN="^sandbox$"
+ TOOLCHAIN="i386"
+ - name: "test/py sandbox with clang"
+ env:
+ - TEST_PY_BD="sandbox"
+ BUILDMAN="^sandbox$"
+ TOOLCHAIN="clang"
+ - name: "test/py sandbox_spl"
+ env:
+ - TEST_PY_BD="sandbox_spl"
+ TEST_PY_TEST_SPEC="test_ofplatdata"
+ BUILDMAN="^sandbox$"
+ TOOLCHAIN="i386"
+ TEST_PY_TOOLS="yes"
+ - name: "test/py sandbox_flattree"
+ env:
+ - TEST_PY_BD="sandbox_flattree"
+ BUILDMAN="^sandbox_flattree$"
+ TOOLCHAIN="i386"
+ - name: "test/py vexpress_ca15_tc2"
+ env:
+ - TEST_PY_BD="vexpress_ca15_tc2"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^vexpress_ca15_tc2$"
+ - name: "test/py vexpress_ca9x4"
+ env:
+ - TEST_PY_BD="vexpress_ca9x4"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^vexpress_ca9x4$"
+ - name: "test/py integratorcp_cm926ejs"
+ env:
+ - TEST_PY_BD="integratorcp_cm926ejs"
+ TEST_PY_TEST_SPEC="not sleep"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^integratorcp_cm926ejs$"
+ - name: "test/py qemu_arm"
+ env:
+ - TEST_PY_BD="qemu_arm"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^qemu_arm$"
+ - name: "test/py qemu_arm64"
+ env:
+ - TEST_PY_BD="qemu_arm64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="aarch64-softmmu"
+ BUILDMAN="^qemu_arm64$"
+ - name: "test/py qemu_mips"
+ env:
+ - TEST_PY_BD="qemu_mips"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mips-softmmu"
+ BUILDMAN="^qemu_mips$"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu_mipsel"
+ env:
+ - TEST_PY_BD="qemu_mipsel"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mipsel-softmmu"
+ BUILDMAN="^qemu_mipsel$"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu_mips64"
+ env:
+ - TEST_PY_BD="qemu_mips64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mips64-softmmu"
+ BUILDMAN="^qemu_mips64$"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu_mips64el"
+ env:
+ - TEST_PY_BD="qemu_mips64el"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mips64el-softmmu"
+ BUILDMAN="^qemu_mips64el$"
+ TOOLCHAIN="mips"
+ - name: "test/py qemu-ppce500"
+ env:
+ - TEST_PY_BD="qemu-ppce500"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="ppc-softmmu"
+ BUILDMAN="^qemu-ppce500$"
+ TOOLCHAIN="powerpc"
+ - name: "test/py qemu-x86"
+ env:
+ - TEST_PY_BD="qemu-x86"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="i386-softmmu"
+ BUILDMAN="^qemu-x86$"
+ TOOLCHAIN="i386"
+ BUILD_ROM="yes"
+ - name: "test/py qemu-x86_64"
+ env:
+ - TEST_PY_BD="qemu-x86_64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="x86_64-softmmu"
+ BUILDMAN="^qemu-x86_64$"
+ TOOLCHAIN="i386"
+ BUILD_ROM="yes"
+ - name: "test/py zynq_zc702"
+ env:
+ - TEST_PY_BD="zynq_zc702"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="arm-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^zynq_zc702$"
+ - name: "test/py xtfpga"
+ env:
+ - TEST_PY_BD="xtfpga"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="xtensa-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^xtfpga$"
+ TOOLCHAIN="xtensa-dc233c-elf"
+
+# TODO make it perfect ;-r
diff --git a/Documentation/.gitignore b/Documentation/.gitignore
new file mode 100644
index 0000000..e74fec8
--- /dev/null
+++ b/Documentation/.gitignore
@@ -0,0 +1,2 @@
+output
+*.pyc
diff --git a/Documentation/Makefile b/Documentation/Makefile
new file mode 100644
index 0000000..2ca77ad
--- /dev/null
+++ b/Documentation/Makefile
@@ -0,0 +1,124 @@
+# -*- makefile -*-
+# Makefile for Sphinx documentation
+#
+
+subdir-y :=
+
+# You can set these variables from the command line.
+SPHINXBUILD = sphinx-build
+SPHINXOPTS =
+SPHINXDIRS = .
+_SPHINXDIRS = $(patsubst $(srctree)/Documentation/%/conf.py,%,$(wildcard $(srctree)/Documentation/*/conf.py))
+SPHINX_CONF = conf.py
+PAPER =
+BUILDDIR = $(obj)/output
+PDFLATEX = xelatex
+LATEXOPTS = -interaction=batchmode
+
+# User-friendly check for sphinx-build
+HAVE_SPHINX := $(shell if which $(SPHINXBUILD) >/dev/null 2>&1; then echo 1; else echo 0; fi)
+
+ifeq ($(HAVE_SPHINX),0)
+
+.DEFAULT:
+ $(warning The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed and in PATH, or set the SPHINXBUILD make variable to point to the full path of the '$(SPHINXBUILD)' executable.)
+ @echo
+ @./scripts/sphinx-pre-install
+ @echo " SKIP Sphinx $@ target."
+
+else # HAVE_SPHINX
+
+# User-friendly check for pdflatex
+HAVE_PDFLATEX := $(shell if which $(PDFLATEX) >/dev/null 2>&1; then echo 1; else echo 0; fi)
+
+# Internal variables.
+PAPEROPT_a4 = -D latex_paper_size=a4
+PAPEROPT_letter = -D latex_paper_size=letter
+KERNELDOC = $(srctree)/scripts/kernel-doc
+KERNELDOC_CONF = -D kerneldoc_srctree=$(srctree) -D kerneldoc_bin=$(KERNELDOC)
+ALLSPHINXOPTS = $(KERNELDOC_CONF) $(PAPEROPT_$(PAPER)) $(SPHINXOPTS)
+# the i18n builder cannot share the environment and doctrees with the others
+I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
+
+# commands; the 'cmd' from scripts/Kbuild.include is not *loopable*
+loop_cmd = $(echo-cmd) $(cmd_$(1)) || exit;
+
+# $2 sphinx builder e.g. "html"
+# $3 name of the build subfolder / e.g. "media", used as:
+# * dest folder relative to $(BUILDDIR) and
+# * cache folder relative to $(BUILDDIR)/.doctrees
+# $4 dest subfolder e.g. "man" for man pages at media/man
+# $5 reST source folder relative to $(srctree)/$(src),
+# e.g. "media" for the linux-tv book-set at ./Documentation/media
+
+quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4)
+ cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media $2 && \
+ PYTHONDONTWRITEBYTECODE=1 \
+ BUILDDIR=$(abspath $(BUILDDIR)) SPHINX_CONF=$(abspath $(srctree)/$(src)/$5/$(SPHINX_CONF)) \
+ $(SPHINXBUILD) \
+ -b $2 \
+ -c $(abspath $(srctree)/$(src)) \
+ -d $(abspath $(BUILDDIR)/.doctrees/$3) \
+ -D version=$(KERNELVERSION) -D release=$(KERNELRELEASE) \
+ $(ALLSPHINXOPTS) \
+ $(abspath $(srctree)/$(src)/$5) \
+ $(abspath $(BUILDDIR)/$3/$4)
+
+htmldocs:
+ @+$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,html,$(var),,$(var)))
+
+linkcheckdocs:
+ @$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,linkcheck,$(var),,$(var)))
+
+latexdocs:
+ @+$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,latex,$(var),latex,$(var)))
+
+ifeq ($(HAVE_PDFLATEX),0)
+
+pdfdocs:
+ $(warning The '$(PDFLATEX)' command was not found. Make sure you have it installed and in PATH to produce PDF output.)
+ @echo " SKIP Sphinx $@ target."
+
+else # HAVE_PDFLATEX
+
+pdfdocs: latexdocs
+ $(foreach var,$(SPHINXDIRS), $(MAKE) PDFLATEX=$(PDFLATEX) LATEXOPTS="$(LATEXOPTS)" -C $(BUILDDIR)/$(var)/latex || exit;)
+
+endif # HAVE_PDFLATEX
+
+epubdocs:
+ @+$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,epub,$(var),epub,$(var)))
+
+xmldocs:
+ @+$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,xml,$(var),xml,$(var)))
+
+endif # HAVE_SPHINX
+
+# The following targets are independent of HAVE_SPHINX, and the rules should
+# work or silently pass without Sphinx.
+
+refcheckdocs:
+ $(Q)cd $(srctree);scripts/documentation-file-ref-check
+
+cleandocs:
+ $(Q)rm -rf $(BUILDDIR)
+ $(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media clean
+
+dochelp:
+ @echo ' Linux kernel internal documentation in different formats from ReST:'
+ @echo ' htmldocs - HTML'
+ @echo ' latexdocs - LaTeX'
+ @echo ' pdfdocs - PDF'
+ @echo ' epubdocs - EPUB'
+ @echo ' xmldocs - XML'
+ @echo ' linkcheckdocs - check for broken external links (will connect to external hosts)'
+ @echo ' refcheckdocs - check for references to non-existing files under Documentation'
+ @echo ' cleandocs - clean all generated files'
+ @echo
+ @echo ' make SPHINXDIRS="s1 s2" [target] Generate only docs of folder s1, s2'
+ @echo ' valid values for SPHINXDIRS are: $(_SPHINXDIRS)'
+ @echo
+ @echo ' make SPHINX_CONF={conf-file} [target] use *additional* sphinx-build'
+ @echo ' configuration. This is e.g. useful to build with nit-picking config.'
+ @echo
+ @echo ' Default location for the generated documents is Documentation/output'
diff --git a/Documentation/conf.py b/Documentation/conf.py
new file mode 100644
index 0000000..168c313
--- /dev/null
+++ b/Documentation/conf.py
@@ -0,0 +1,528 @@
+# -*- coding: utf-8 -*-
+#
+# The U-Boot documentation build configuration file, created by
+# sphinx-quickstart on Fri Feb 12 13:51:46 2016.
+#
+# This file is execfile()d with the current directory set to its
+# containing dir.
+#
+# Note that not all possible configuration values are present in this
+# autogenerated file.
+#
+# All configuration values have a default; values that are commented out
+# serve to show the default.
+
+import sys
+import os
+import sphinx
+
+# Get Sphinx version
+major, minor, patch = sphinx.version_info[:3]
+
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+sys.path.insert(0, os.path.abspath('sphinx'))
+from load_config import loadConfig
+
+# -- General configuration ------------------------------------------------
+
+# If your documentation needs a minimal Sphinx version, state it here.
+needs_sphinx = '1.3'
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain', 'kfigure']
+
+# The name of the math extension changed on Sphinx 1.4
+if major == 1 and minor > 3:
+ extensions.append("sphinx.ext.imgmath")
+else:
+ extensions.append("sphinx.ext.pngmath")
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# The suffix(es) of source filenames.
+# You can specify multiple suffix as a list of string:
+# source_suffix = ['.rst', '.md']
+source_suffix = '.rst'
+
+# The encoding of source files.
+#source_encoding = 'utf-8-sig'
+
+# The master toctree document.
+master_doc = 'index'
+
+# General information about the project.
+project = 'Das U-Boot'
+copyright = 'The U-Boot development community'
+author = 'The U-Boot development community'
+
+# The version info for the project you're documenting, acts as replacement for
+# |version| and |release|, also used in various other places throughout the
+# built documents.
+#
+# In a normal build, version and release are are set to KERNELVERSION and
+# KERNELRELEASE, respectively, from the Makefile via Sphinx command line
+# arguments.
+#
+# The following code tries to extract the information by reading the Makefile,
+# when Sphinx is run directly (e.g. by Read the Docs).
+try:
+ makefile_version = None
+ makefile_patchlevel = None
+ for line in open('../Makefile'):
+ key, val = [x.strip() for x in line.split('=', 2)]
+ if key == 'VERSION':
+ makefile_version = val
+ elif key == 'PATCHLEVEL':
+ makefile_patchlevel = val
+ if makefile_version and makefile_patchlevel:
+ break
+except:
+ pass
+finally:
+ if makefile_version and makefile_patchlevel:
+ version = release = makefile_version + '.' + makefile_patchlevel
+ else:
+ version = release = "unknown version"
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+#
+# This is also used if you do content translation via gettext catalogs.
+# Usually you set "language" from the command line for these cases.
+language = None
+
+# There are two options for replacing |today|: either, you set today to some
+# non-false value, then it is used:
+#today = ''
+# Else, today_fmt is used as the format for a strftime call.
+#today_fmt = '%B %d, %Y'
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+exclude_patterns = ['output']
+
+# The reST default role (used for this markup: `text`) to use for all
+# documents.
+#default_role = None
+
+# If true, '()' will be appended to :func: etc. cross-reference text.
+#add_function_parentheses = True
+
+# If true, the current module name will be prepended to all description
+# unit titles (such as .. function::).
+#add_module_names = True
+
+# If true, sectionauthor and moduleauthor directives will be shown in the
+# output. They are ignored by default.
+#show_authors = False
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+# A list of ignored prefixes for module index sorting.
+#modindex_common_prefix = []
+
+# If true, keep warnings as "system message" paragraphs in the built documents.
+#keep_warnings = False
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = False
+
+primary_domain = 'c'
+highlight_language = 'none'
+
+# -- Options for HTML output ----------------------------------------------
+
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+
+# The Read the Docs theme is available from
+# - https://github.com/snide/sphinx_rtd_theme
+# - https://pypi.python.org/pypi/sphinx_rtd_theme
+# - python-sphinx-rtd-theme package (on Debian)
+try:
+ import sphinx_rtd_theme
+ html_theme = 'sphinx_rtd_theme'
+ html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
+except ImportError:
+ sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme was not found. Make sure you have the theme installed to produce pretty HTML output. Falling back to the default theme.\n')
+
+# Theme options are theme-specific and customize the look and feel of a theme
+# further. For a list of options available for each theme, see the
+# documentation.
+#html_theme_options = {}
+
+# Add any paths that contain custom themes here, relative to this directory.
+#html_theme_path = []
+
+# The name for this set of Sphinx documents. If None, it defaults to
+# "<project> v<release> documentation".
+#html_title = None
+
+# A shorter title for the navigation bar. Default is the same as html_title.
+#html_short_title = None
+
+# The name of an image file (relative to this directory) to place at the top
+# of the sidebar.
+#html_logo = None
+
+# The name of an image file (within the static path) to use as favicon of the
+# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
+# pixels large.
+#html_favicon = None
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+
+html_static_path = ['sphinx-static']
+
+html_context = {
+ 'css_files': [
+ '_static/theme_overrides.css',
+ ],
+}
+
+# Add any extra paths that contain custom files (such as robots.txt or
+# .htaccess) here, relative to this directory. These files are copied
+# directly to the root of the documentation.
+#html_extra_path = []
+
+# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
+# using the given strftime format.
+#html_last_updated_fmt = '%b %d, %Y'
+
+# If true, SmartyPants will be used to convert quotes and dashes to
+# typographically correct entities.
+#html_use_smartypants = True
+
+# Custom sidebar templates, maps document names to template names.
+#html_sidebars = {}
+
+# Additional templates that should be rendered to pages, maps page names to
+# template names.
+#html_additional_pages = {}
+
+# If false, no module index is generated.
+#html_domain_indices = True
+
+# If false, no index is generated.
+#html_use_index = True
+
+# If true, the index is split into individual pages for each letter.
+#html_split_index = False
+
+# If true, links to the reST sources are added to the pages.
+#html_show_sourcelink = True
+
+# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
+#html_show_sphinx = True
+
+# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
+#html_show_copyright = True
+
+# If true, an OpenSearch description file will be output, and all pages will
+# contain a <link> tag referring to it. The value of this option must be the
+# base URL from which the finished HTML is served.
+#html_use_opensearch = ''
+
+# This is the file name suffix for HTML files (e.g. ".xhtml").
+#html_file_suffix = None
+
+# Language to be used for generating the HTML full-text search index.
+# Sphinx supports the following languages:
+# 'da', 'de', 'en', 'es', 'fi', 'fr', 'h', 'it', 'ja'
+# 'nl', 'no', 'pt', 'ro', 'r', 'sv', 'tr'
+#html_search_language = 'en'
+
+# A dictionary with options for the search language support, empty by default.
+# Now only 'ja' uses this config value
+#html_search_options = {'type': 'default'}
+
+# The name of a javascript file (relative to the configuration directory) that
+# implements a search results scorer. If empty, the default will be used.
+#html_search_scorer = 'scorer.js'
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = 'TheUBootdoc'
+
+# -- Options for LaTeX output ---------------------------------------------
+
+latex_elements = {
+# The paper size ('letterpaper' or 'a4paper').
+'papersize': 'a4paper',
+
+# The font size ('10pt', '11pt' or '12pt').
+'pointsize': '8pt',
+
+# Latex figure (float) alignment
+#'figure_align': 'htbp',
+
+# Don't mangle with UTF-8 chars
+'inputenc': '',
+'utf8extra': '',
+
+# Additional stuff for the LaTeX preamble.
+ 'preamble': '''
+ % Use some font with UTF-8 support with XeLaTeX
+ \\usepackage{fontspec}
+ \\setsansfont{DejaVu Serif}
+ \\setromanfont{DejaVu Sans}
+ \\setmonofont{DejaVu Sans Mono}
+
+ '''
+}
+
+# Fix reference escape troubles with Sphinx 1.4.x
+if major == 1 and minor > 3:
+ latex_elements['preamble'] += '\\renewcommand*{\\DUrole}[2]{ #2 }\n'
+
+if major == 1 and minor <= 4:
+ latex_elements['preamble'] += '\\usepackage[margin=0.5in, top=1in, bottom=1in]{geometry}'
+elif major == 1 and (minor > 5 or (minor == 5 and patch >= 3)):
+ latex_elements['sphinxsetup'] = 'hmargin=0.5in, vmargin=1in'
+ latex_elements['preamble'] += '\\fvset{fontsize=auto}\n'
+
+# Customize notice background colors on Sphinx < 1.6:
+if major == 1 and minor < 6:
+ latex_elements['preamble'] += '''
+ \\usepackage{ifthen}
+
+ % Put notes in color and let them be inside a table
+ \\definecolor{NoteColor}{RGB}{204,255,255}
+ \\definecolor{WarningColor}{RGB}{255,204,204}
+ \\definecolor{AttentionColor}{RGB}{255,255,204}
+ \\definecolor{ImportantColor}{RGB}{192,255,204}
+ \\definecolor{OtherColor}{RGB}{204,204,204}
+ \\newlength{\\mynoticelength}
+ \\makeatletter\\newenvironment{coloredbox}[1]{%
+ \\setlength{\\fboxrule}{1pt}
+ \\setlength{\\fboxsep}{7pt}
+ \\setlength{\\mynoticelength}{\\linewidth}
+ \\addtolength{\\mynoticelength}{-2\\fboxsep}
+ \\addtolength{\\mynoticelength}{-2\\fboxrule}
+ \\begin{lrbox}{\\@tempboxa}\\begin{minipage}{\\mynoticelength}}{\\end{minipage}\\end{lrbox}%
+ \\ifthenelse%
+ {\\equal{\\py@noticetype}{note}}%
+ {\\colorbox{NoteColor}{\\usebox{\\@tempboxa}}}%
+ {%
+ \\ifthenelse%
+ {\\equal{\\py@noticetype}{warning}}%
+ {\\colorbox{WarningColor}{\\usebox{\\@tempboxa}}}%
+ {%
+ \\ifthenelse%
+ {\\equal{\\py@noticetype}{attention}}%
+ {\\colorbox{AttentionColor}{\\usebox{\\@tempboxa}}}%
+ {%
+ \\ifthenelse%
+ {\\equal{\\py@noticetype}{important}}%
+ {\\colorbox{ImportantColor}{\\usebox{\\@tempboxa}}}%
+ {\\colorbox{OtherColor}{\\usebox{\\@tempboxa}}}%
+ }%
+ }%
+ }%
+ }\\makeatother
+
+ \\makeatletter
+ \\renewenvironment{notice}[2]{%
+ \\def\\py@noticetype{#1}
+ \\begin{coloredbox}{#1}
+ \\bf\\it
+ \\par\\strong{#2}
+ \\csname py@noticestart@#1\\endcsname
+ }
+ {
+ \\csname py@noticeend@\\py@noticetype\\endcsname
+ \\end{coloredbox}
+ }
+ \\makeatother
+
+ '''
+
+# With Sphinx 1.6, it is possible to change the Bg color directly
+# by using:
+# \definecolor{sphinxnoteBgColor}{RGB}{204,255,255}
+# \definecolor{sphinxwarningBgColor}{RGB}{255,204,204}
+# \definecolor{sphinxattentionBgColor}{RGB}{255,255,204}
+# \definecolor{sphinximportantBgColor}{RGB}{192,255,204}
+#
+# However, it require to use sphinx heavy box with:
+#
+# \renewenvironment{sphinxlightbox} {%
+# \\begin{sphinxheavybox}
+# }
+# \\end{sphinxheavybox}
+# }
+#
+# Unfortunately, the implementation is buggy: if a note is inside a
+# table, it isn't displayed well. So, for now, let's use boring
+# black and white notes.
+
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title,
+# author, documentclass [howto, manual, or own class]).
+# Sorted in alphabetical order
+latex_documents = [
+ ('index', 'u-boot-hacker-manual.tex', 'U-Boot Hacker Manual',
+ 'The U-Boot development community', 'manual'),
+]
+
+# The name of an image file (relative to this directory) to place at the top of
+# the title page.
+#latex_logo = None
+
+# For "manual" documents, if this is true, then toplevel headings are parts,
+# not chapters.
+#latex_use_parts = False
+
+# If true, show page references after internal links.
+#latex_show_pagerefs = False
+
+# If true, show URL addresses after external links.
+#latex_show_urls = False
+
+# Documents to append as an appendix to all manuals.
+#latex_appendices = []
+
+# If false, no module index is generated.
+#latex_domain_indices = True
+
+
+# -- Options for manual page output ---------------------------------------
+
+# One entry per manual page. List of tuples
+# (source start file, name, description, authors, manual section).
+man_pages = [
+ (master_doc, 'dasuboot', 'The U-Boot Documentation',
+ [author], 1)
+]
+
+# If true, show URL addresses after external links.
+#man_show_urls = False
+
+
+# -- Options for Texinfo output -------------------------------------------
+
+# Grouping the document tree into Texinfo files. List of tuples
+# (source start file, target name, title, author,
+# dir menu entry, description, category)
+texinfo_documents = [
+ (master_doc, 'DasUBoot', 'The U-Boot Documentation',
+ author, 'DasUBoot', 'One line description of project.',
+ 'Miscellaneous'),
+]
+
+# Documents to append as an appendix to all manuals.
+#texinfo_appendices = []
+
+# If false, no module index is generated.
+#texinfo_domain_indices = True
+
+# How to display URL addresses: 'footnote', 'no', or 'inline'.
+#texinfo_show_urls = 'footnote'
+
+# If true, do not generate a @detailmenu in the "Top" node's menu.
+#texinfo_no_detailmenu = False
+
+
+# -- Options for Epub output ----------------------------------------------
+
+# Bibliographic Dublin Core info.
+epub_title = project
+epub_author = author
+epub_publisher = author
+epub_copyright = copyright
+
+# The basename for the epub file. It defaults to the project name.
+#epub_basename = project
+
+# The HTML theme for the epub output. Since the default themes are not
+# optimized for small screen space, using the same theme for HTML and epub
+# output is usually not wise. This defaults to 'epub', a theme designed to save
+# visual space.
+#epub_theme = 'epub'
+
+# The language of the text. It defaults to the language option
+# or 'en' if the language is not set.
+#epub_language = ''
+
+# The scheme of the identifier. Typical schemes are ISBN or URL.
+#epub_scheme = ''
+
+# The unique identifier of the text. This can be a ISBN number
+# or the project homepage.
+#epub_identifier = ''
+
+# A unique identification for the text.
+#epub_uid = ''
+
+# A tuple containing the cover image and cover page html template filenames.
+#epub_cover = ()
+
+# A sequence of (type, uri, title) tuples for the guide element of content.opf.
+#epub_guide = ()
+
+# HTML files that should be inserted before the pages created by sphinx.
+# The format is a list of tuples containing the path and title.
+#epub_pre_files = []
+
+# HTML files that should be inserted after the pages created by sphinx.
+# The format is a list of tuples containing the path and title.
+#epub_post_files = []
+
+# A list of files that should not be packed into the epub file.
+epub_exclude_files = ['search.html']
+
+# The depth of the table of contents in toc.ncx.
+#epub_tocdepth = 3
+
+# Allow duplicate toc entries.
+#epub_tocdup = True
+
+# Choose between 'default' and 'includehidden'.
+#epub_tocscope = 'default'
+
+# Fix unsupported image types using the Pillow.
+#epub_fix_images = False
+
+# Scale large images.
+#epub_max_image_width = 0
+
+# How to display URL addresses: 'footnote', 'no', or 'inline'.
+#epub_show_urls = 'inline'
+
+# If false, no index is generated.
+#epub_use_index = True
+
+#=======
+# rst2pdf
+#
+# Grouping the document tree into PDF files. List of tuples
+# (source start file, target name, title, author, options).
+#
+# See the Sphinx chapter of http://ralsina.me/static/manual.pdf
+#
+# FIXME: Do not add the index file here; the result will be too big. Adding
+# multiple PDF files here actually tries to get the cross-referencing right
+# *between* PDF files.
+pdf_documents = [
+ ('uboot-documentation', u'U-Boot', u'U-Boot', u'J. Random Bozo'),
+]
+
+# kernel-doc extension configuration for running Sphinx directly (e.g. by Read
+# the Docs). In a normal build, these are supplied from the Makefile via command
+# line arguments.
+kerneldoc_bin = '../scripts/kernel-doc'
+kerneldoc_srctree = '..'
+
+# ------------------------------------------------------------------------------
+# Since loadConfig overwrites settings from the global namespace, it has to be
+# the last statement in the conf.py file
+# ------------------------------------------------------------------------------
+loadConfig(globals())
diff --git a/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt b/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt
new file mode 100644
index 0000000..110788f
--- /dev/null
+++ b/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt
@@ -0,0 +1,22 @@
+gdsys AXI busses of IHS FPGA devices
+
+Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which
+the connected devices (usually IP cores) can be controlled via software.
+
+Required properties:
+- compatible: must be "gdsys,ihs_axi"
+- reg: describes the address and length of the AXI bus's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+
+ axi_dev_1 {
+ ...
+ };
+};
diff --git a/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt b/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt
new file mode 100644
index 0000000..28c1080
--- /dev/null
+++ b/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt
@@ -0,0 +1,46 @@
+gdsys Gazerbeam board driver
+
+This driver provides capabilities to access the gdsys Gazerbeam board's device
+information. Furthermore, phandles to some internal devices are provided for
+the board files.
+
+Required properties:
+- compatible: should be "gdsys,board_gazerbeam"
+- csb: phandle to the board's coherent system bus (CSB) device node
+- rxaui[0-3]: phandles to the rxaui control device nodes
+- fpga[0-1]: phandles to the board's gdsys FPGA device nodes
+- ioep[0-1]: phandles to the board's IO endpoint device nodes
+- ver-gpios: GPIO list to read the hardware version from
+- var-gpios: GPIO list to read the hardware variant information from
+- reset-gpios: GPIO list for the board's reset GPIOs
+
+Example:
+
+
+board {
+ compatible = "gdsys,board_gazerbeam";
+ csb = <&board_soc>;
+ serdes = <&SERDES>;
+ rxaui0 = <&RXAUI0>;
+ rxaui1 = <&RXAUI1>;
+ rxaui2 = <&RXAUI2>;
+ rxaui3 = <&RXAUI3>;
+ fpga0 = <&FPGA0>;
+ fpga1 = <&FPGA1>;
+ ioep0 = <&IOEP0>;
+ ioep1 = <&IOEP1>;
+
+ ver-gpios = <&PPCPCA 12 0
+ &PPCPCA 13 0
+ &PPCPCA 14 0
+ &PPCPCA 15 0>;
+
+ /* MC2/SC-Board */
+ var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
+ &GPIO_VB0 11 0>; /* VAR-CON */
+ /* MC4-Board */
+ var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
+ &GPIO_VB1 11 0>; /* VAR-CON */
+
+ reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
+};
diff --git a/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt b/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt
new file mode 100644
index 0000000..8313da8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt
@@ -0,0 +1,23 @@
+MPC83xx system clock devices
+
+MPC83xx SoCs supply a variety of clocks to drive various components of a
+system.
+
+Required properties:
+- compatible: must be one of "fsl,mpc8308-clk",
+ "fsl,mpc8309-clk",
+ "fsl,mpc8313-clk",
+ "fsl,mpc8315-clk",
+ "fsl,mpc832x-clk",
+ "fsl,mpc8349-clk",
+ "fsl,mpc8360-clk",
+ "fsl,mpc8379-clk"
+ depending on which SoC is employed
+- #clock-cells: Must be 1
+
+Example:
+
+socclocks: clocks {
+ compatible = "fsl,mpc832x-clk";
+ #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt b/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt
new file mode 100644
index 0000000..ac563d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt
@@ -0,0 +1,34 @@
+MPC83xx CPU devices
+
+MPC83xx SoCs contain a e300 core as their main processor.
+
+Required properties:
+- compatible: must be one of "fsl,mpc83xx",
+ "fsl,mpc8308",
+ "fsl,mpc8309",
+ "fsl,mpc8313",
+ "fsl,mpc8315",
+ "fsl,mpc832x",
+ "fsl,mpc8349",
+ "fsl,mpc8360",
+ "fsl,mpc8379"
+- clocks: has to have two entries, which must be the core clock at index 0 and
+ the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable
+ "fsl,mpc83xx-clk" device
+
+Example:
+
+socclocks: clocks {
+ compatible = "fsl,mpc8315-clk";
+ #clock-cells = <1>;
+};
+
+cpus {
+ compatible = "cpu_bus";
+
+ PowerPC,8315@0 {
+ compatible = "fsl,mpc8315";
+ clocks = <&socclocks MPC83XX_CLK_CORE
+ &socclocks MPC83XX_CLK_CSB>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt b/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt
new file mode 100644
index 0000000..64a9b5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt
@@ -0,0 +1,24 @@
+MPC83xx SerDes controller devices
+
+MPC83xx SoCs contain a built-in SerDes controller that determines which
+protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
+and how the lines are configured.
+
+Required properties:
+- compatible: must be "fsl,mpc83xx-serdes"
+- reg: must point to the serdes controller's register map
+- proto: selects for which protocol the serdes lines are configured. One of
+ "sata", "pex", "pex-x2", "sgmii"
+- serdes-clk: determines the frequency the serdes lines are configured for. One
+ of 100, 125, 150.
+- vdd: determines whether 1.0V core VDD is used or not
+
+Example:
+
+SERDES: serdes@e3000 {
+ reg = <0xe3000 0x200>;
+ compatible = "fsl,mpc83xx-serdes";
+ proto = "pex";
+ serdes-clk = <100>;
+ vdd;
+};
diff --git a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt b/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt
new file mode 100644
index 0000000..db2ff8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt
@@ -0,0 +1,20 @@
+gdsys IO endpoint of IHS FPGA devices
+
+The IO endpoint of IHS FPGA devices is a packet-based transmission interface
+that allows interconnected gdsys devices to send and receive data over the
+FPGA's main ethernet connection.
+
+Required properties:
+- compatible: must be "gdsys,io-endpoint"
+- reg: describes the address and length of the endpoint's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = <0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+};
diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt
new file mode 100644
index 0000000..acd466f
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt
@@ -0,0 +1,19 @@
+gdsys IHS FPGA for CON devices
+
+The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides
+support for enabling and starting the FPGA, as well as verifying working bus
+communication.
+
+Required properties:
+- compatible: must be "gdsys,iocon_fpga"
+- reset-gpios: List of GPIOs controlling the FPGA's reset
+- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
+ done
+
+Example:
+
+FPGA0 {
+ compatible = "gdsys,iocon_fpga";
+ reset-gpios = <&PPCPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+};
diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt
new file mode 100644
index 0000000..819db22
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt
@@ -0,0 +1,19 @@
+gdsys IHS FPGA for CPU devices
+
+The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides
+support for enabling and starting the FPGA, as well as verifying working bus
+communication.
+
+Required properties:
+- compatible: must be "gdsys,iocpu_fpga"
+- reset-gpios: List of GPIOs controlling the FPGA's reset
+- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
+ done
+
+Example:
+
+FPGA0 {
+ compatible = "gdsys,iocpu_fpga";
+ reset-gpios = <&PPCPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+};
diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/Documentation/devicetree/bindings/misc/gdsys,soc.txt
new file mode 100644
index 0000000..278e935
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,soc.txt
@@ -0,0 +1,16 @@
+gdsys soc bus driver
+
+This driver provides a simple interface for the busses associated with gdsys
+IHS FPGAs. The bus itself contains devices whose register maps are contained
+within the FPGA's register space.
+
+Required properties:
+- fpga: A phandle to the controlling IHS FPGA
+
+Example:
+
+FPGA0BUS: fpga0bus {
+ compatible = "gdsys,soc";
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+};
diff --git a/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt b/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt
new file mode 100644
index 0000000..da01fe9
--- /dev/null
+++ b/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt
@@ -0,0 +1,314 @@
+MPC83xx RAM controller
+
+This driver supplies support for the embedded RAM controller on MCP83xx-series
+SoCs.
+
+For static configuration mode, each controller node should have child nodes
+describing the actual RAM modules installed.
+
+Controller node
+===============
+
+Required properties:
+- compatible: Must be "fsl,mpc83xx-mem-controller"
+- reg: The address of the RAM controller's register space
+- #address-cells: Must be 2
+- #size-cells: Must be 1
+- driver_software_override: DDR driver software override is enabled (1) or
+ disabled (0)
+- p_impedance_override: DDR driver software p-impedance override; possible
+ values:
+ * DSO_P_IMPEDANCE_HIGHEST_Z
+ * DSO_P_IMPEDANCE_MUCH_HIGHER_Z
+ * DSO_P_IMPEDANCE_HIGHER_Z
+ * DSO_P_IMPEDANCE_NOMINAL
+ * DSO_P_IMPEDANCE_LOWER_Z
+- n_impedance_override: DDR driver software n-impedance override; possible
+ values:
+ * DSO_N_IMPEDANCE_HIGHEST_Z
+ * DSO_N_IMPEDANCE_MUCH_HIGHER_Z
+ * DSO_N_IMPEDANCE_HIGHER_Z
+ * DSO_N_IMPEDANCE_NOMINAL
+ * DSO_N_IMPEDANCE_LOWER_Z
+- odt_termination_value: ODT termination value for I/Os; possible values:
+ * ODT_TERMINATION_75_OHM
+ * ODT_TERMINATION_150_OHM
+- ddr_type: Selects voltage level for DDR pads; possible
+ values:
+ * DDR_TYPE_DDR2_1_8_VOLT
+ * DDR_TYPE_DDR1_2_5_VOLT
+- mvref_sel: Determine where MVREF_SEL signal is generated;
+ possible values:
+ * MVREF_SEL_EXTERNAL
+ * MVREF_SEL_INTERNAL_GVDD
+- m_odr: Disable memory transaction reordering; possible
+ values:
+ * M_ODR_ENABLE
+ * M_ODR_DISABLE
+- clock_adjust: Clock adjust; possible values:
+ * CLOCK_ADJUST_025
+ * CLOCK_ADJUST_05
+ * CLOCK_ADJUST_075
+ * CLOCK_ADJUST_1
+- ext_refresh_rec: Extended refresh recovery time; possible values:
+ 0, 16, 32, 48, 64, 80, 96, 112
+- read_to_write: Read-to-write turnaround; possible values:
+ 0, 1, 2, 3
+- write_to_read: Write-to-read turnaround; possible values:
+ 0, 1, 2, 3
+- read_to_read: Read-to-read turnaround; possible values:
+ 0, 1, 2, 3
+- write_to_write: Write-to-write turnaround; possible values:
+ 0, 1, 2, 3
+- active_powerdown_exit: Active powerdown exit timing; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- precharge_powerdown_exit: Precharge powerdown exit timing; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- odt_powerdown_exit: ODT powerdown exit timing; possible values:
+ 0, 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15
+- mode_reg_set_cycle: Mode register set cycle time; possible values:
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+- precharge_to_activate: Precharge-to-acitvate interval; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- activate_to_precharge: Activate to precharge interval; possible values:
+ 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19
+- activate_to_readwrite: Activate to read/write interval for SDRAM;
+ possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- mcas_latency: MCAS latency from READ command; possible values:
+ * CASLAT_20
+ * CASLAT_25
+ * CASLAT_30
+ * CASLAT_35
+ * CASLAT_40
+ * CASLAT_45
+ * CASLAT_50
+ * CASLAT_55
+ * CASLAT_60
+ * CASLAT_65
+ * CASLAT_70
+ * CASLAT_75
+ * CASLAT_80
+- refresh_recovery: Refresh recovery time; possible values:
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23
+- last_data_to_precharge: Last data to precharge minimum interval; possible
+ values:
+ 1, 2, 3, 4, 5, 6, 7
+- activate_to_activate: Activate-to-activate interval; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- last_write_data_to_read: Last write data pair to read command issue
+ interval; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- additive_latency: Additive latency; possible values:
+ 0, 1, 2, 3, 4, 5
+- mcas_to_preamble_override: MCAS-to-preamble-override; possible values:
+ * READ_LAT
+ * READ_LAT_PLUS_1_4
+ * READ_LAT_PLUS_1_2
+ * READ_LAT_PLUS_3_4
+ * READ_LAT_PLUS_1
+ * READ_LAT_PLUS_5_4
+ * READ_LAT_PLUS_3_2
+ * READ_LAT_PLUS_7_4
+ * READ_LAT_PLUS_2
+ * READ_LAT_PLUS_9_4
+ * READ_LAT_PLUS_5_2
+ * READ_LAT_PLUS_11_4
+ * READ_LAT_PLUS_3
+ * READ_LAT_PLUS_13_4
+ * READ_LAT_PLUS_7_2
+ * READ_LAT_PLUS_15_4
+ * READ_LAT_PLUS_4
+ * READ_LAT_PLUS_17_4
+ * READ_LAT_PLUS_9_2
+ * READ_LAT_PLUS_19_4
+- write_latency: Write latency; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- read_to_precharge: Read to precharge; possible values:
+ 1, 2, 3, 4
+- write_cmd_to_write_data: Write command to write data strobe timing
+ adjustment; possible values:
+ * CLOCK_DELAY_0
+ * CLOCK_DELAY_1_4
+ * CLOCK_DELAY_1_2
+ * CLOCK_DELAY_3_4
+ * CLOCK_DELAY_1
+ * CLOCK_DELAY_5_4
+ * CLOCK_DELAY_3_2
+- minimum_cke_pulse_width: Minimum CKE pulse width; possible values:
+ 1, 2, 3, 4
+- four_activates_window: Window for four activates; possible values:
+ 1, 2, 3, 4 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19
+- self_refresh: Self refresh (during sleep); possible values:
+ * SREN_DISABLE
+ * SREN_ENABLE
+- ecc: Support for ECC; possible values:
+ * ECC_DISABLE
+ * ECC_ENABLE
+- registered_dram: Support for registered DRAM; possible values:
+ * RD_DISABLE
+ * RD_ENABLE
+- sdram_type: Type of SDRAM device to be used; possible values:
+ * TYPE_DDR1
+ * TYPE_DDR2
+- dynamic_power_management: Dynamic power management mode; possible values:
+ * DYN_PWR_DISABLE
+ * DYN_PWR_ENABLE
+- databus_width: DRAM data bus width; possible values
+ * DATA_BUS_WIDTH_16
+ * DATA_BUS_WIDTH_32
+- nc_auto_precharge: Non-concurrent auto-precharge; possible values:
+ * NCAP_DISABLE
+ * NCAP_ENABLE
+- timing_2t: 2T timing; possible values:
+ * TIMING_1T
+ * TIMING_2T
+- bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
+ values:
+ * INTERLEAVE_NONE
+ * INTERLEAVE_1_AND_2
+- precharge_bit_8: Precharge bin 8; possible values
+ * PRECHARGE_MA_10
+ * PRECHARGE_MA_8
+- half_strength: Global half-strength override; possible values:
+ * STRENGTH_FULL
+ * STRENGTH_HALF
+- bypass_initialization: Bypass initialization; possible values:
+ * INITIALIZATION_DONT_BYPASS
+ * INITIALIZATION_BYPASS
+- force_self_refresh: Force self refresh; possible values:
+ * MODE_NORMAL
+ * MODE_REFRESH
+- dll_reset: DLL reset; possible values:
+ * DLL_RESET_ENABLE
+ * DLL_RESET_DISABLE
+- dqs_config: DQS configuration; possible values:
+ * DQS_TRUE
+- odt_config: ODT configuration; possible values:
+ * ODT_ASSERT_NEVER
+ * ODT_ASSERT_WRITES
+ * ODT_ASSERT_READS
+ * ODT_ASSERT_ALWAYS
+- posted_refreshes: Number of posted refreshes
+ 1, 2, 3, 4, 5, 6, 7, 8
+- sdmode: Initial value loaded into the DDR SDRAM mode
+ register
+- esdmode: Initial value loaded into the DDR SDRAM extended
+ mode register
+- esdmode2: Initial value loaded into the DDR SDRAM extended
+ mode 2 register
+- esdmode3: Initial value loaded into the DDR SDRAM extended
+ mode 3 register
+- refresh_interval: Refresh interval; possible values:
+ 0 - 65535
+- precharge_interval: Precharge interval; possible values:
+ 0 - 16383
+
+RAM module node:
+================
+
+Required properties:
+- reg: A triple <cs addr size>, which consists of:
+ * cs - the chipselect used to drive this RAM module
+ * addr - the address where this RAM module's memory is map
+ to in the global memory space
+ * size - the size of the RAM module's memory in bytes
+- auto_precharge: Chip select auto-precharge; possible values:
+ * AUTO_PRECHARGE_ENABLE
+ * AUTO_PRECHARGE_DISABLE
+- odt_rd_cfg: ODT for reads configuration; possible values:
+ * ODT_RD_NEVER
+ * ODT_RD_ONLY_CURRENT
+ * ODT_RD_ONLY_OTHER_CS
+ * ODT_RD_ONLY_OTHER_DIMM
+ * ODT_RD_ALL
+- odt_wr_cfg: ODT for writes configuration; possible values:
+ * ODT_WR_NEVER
+ * ODT_WR_ONLY_CURRENT
+ * ODT_WR_ONLY_OTHER_CS
+ * ODT_WR_ONLY_OTHER_DIMM
+ * ODT_WR_ALL
+- bank_bits: Number of bank bits for SDRAM on chip select; possible
+ values:
+ 2, 3
+- row_bits: Number of row bits for SDRAM on chip select; possible values:
+ 12, 13, 14
+- col_bits: Number of column bits for SDRAM on chip select; possible
+ values:
+ 8, 9, 10, 11
+
+Example:
+
+memory@2000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc83xx-mem-controller";
+ reg = <0x2000 0x1000>;
+ device_type = "memory";
+ u-boot,dm-pre-reloc;
+
+ driver_software_override = <DSO_ENABLE>;
+ p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
+ n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
+ odt_termination_value = <ODT_TERMINATION_150_OHM>;
+ ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
+
+ clock_adjust = <CLOCK_ADJUST_05>;
+
+ read_to_write = <0>;
+ write_to_read = <0>;
+ read_to_read = <0>;
+ write_to_write = <0>;
+ active_powerdown_exit = <2>;
+ precharge_powerdown_exit = <6>;
+ odt_powerdown_exit = <8>;
+ mode_reg_set_cycle = <2>;
+
+ precharge_to_activate = <2>;
+ activate_to_precharge = <6>;
+ activate_to_readwrite = <2>;
+ mcas_latency = <CASLAT_40>;
+ refresh_recovery = <17>;
+ last_data_to_precharge = <2>;
+ activate_to_activate = <2>;
+ last_write_data_to_read = <2>;
+
+ additive_latency = <0>;
+ mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
+ write_latency = <3>;
+ read_to_precharge = <2>;
+ write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
+ minimum_cke_pulse_width = <3>;
+ four_activates_window = <5>;
+
+ self_refresh = <SREN_ENABLE>;
+ sdram_type = <TYPE_DDR2>;
+ databus_width = <DATA_BUS_WIDTH_32>;
+
+ force_self_refresh = <MODE_NORMAL>;
+ dll_reset = <DLL_RESET_ENABLE>;
+ dqs_config = <DQS_TRUE>;
+ odt_config = <ODT_ASSERT_READS>;
+ posted_refreshes = <1>;
+
+ refresh_interval = <2084>;
+ precharge_interval = <256>;
+
+ sdmode = <0x0242>;
+ esdmode = <0x0440>;
+
+ ram@0 {
+ reg = <0x0 0x0 0x8000000>;
+ compatible = "nanya,nt5tu64m16hg";
+
+ odt_rd_cfg = <ODT_RD_NEVER>;
+ odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
+ bank_bits = <3>;
+ row_bits = <13>;
+ col_bits = <10>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt b/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt
new file mode 100644
index 0000000..608d241
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt
@@ -0,0 +1,21 @@
+MPC83xx timer devices
+
+MPC83xx SoCs offer a decrementer interrupt that can be used to implement delay
+functionality, and periodically triggered actions.
+
+Required properties:
+- compatible: must be "fsl,mpc83xx-timer"
+- clocks: must be a reference to the system's CSB (coherent system bus) clock,
+ provided by one of the "fsl,mpc83xx-clk" devices
+
+Example:
+
+socclocks: clocks {
+ compatible = "fsl,mpc832x-clk";
+ #clock-cells = <1>;
+};
+
+timer {
+ compatible = "fsl,mpc83xx-timer";
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+};
diff --git a/Documentation/efi.rst b/Documentation/efi.rst
new file mode 100644
index 0000000..51c1de2
--- /dev/null
+++ b/Documentation/efi.rst
@@ -0,0 +1,16 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+EFI subsystem
+=============
+
+Boot services
+-------------
+
+.. kernel-doc:: lib/efi_loader/efi_boottime.c
+ :internal:
+
+Runtime services
+----------------
+
+.. kernel-doc:: lib/efi_loader/efi_runtime.c
+ :internal:
diff --git a/Documentation/index.rst b/Documentation/index.rst
new file mode 100644
index 0000000..0353c10
--- /dev/null
+++ b/Documentation/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+#######################
+U-Boot Developer Manual
+#######################
+
+.. toctree::
+
+ efi
+ linker_lists
+ serial
diff --git a/Documentation/linker_lists.rst b/Documentation/linker_lists.rst
new file mode 100644
index 0000000..72f514e
--- /dev/null
+++ b/Documentation/linker_lists.rst
@@ -0,0 +1,100 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Linker-Generated Arrays
+=======================
+
+A linker list is constructed by grouping together linker input
+sections, each containing one entry of the list. Each input section
+contains a constant initialized variable which holds the entry's
+content. Linker list input sections are constructed from the list
+and entry names, plus a prefix which allows grouping all lists
+together. Assuming _list and _entry are the list and entry names,
+then the corresponding input section name is
+
+::
+
+ .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+
+and the C variable name is
+
+::
+
+ _u_boot_list + _2_ + @_list + _2_ + @_entry
+
+This ensures uniqueness for both input section and C variable name.
+
+Note that the names differ only in the first character, "." for the
+section and "_" for the variable, so that the linker cannot confuse
+section and symbol names. From now on, both names will be referred
+to as
+
+::
+
+ %u_boot_list_ + 2_ + @_list + _2_ + @_entry
+
+Entry variables need never be referred to directly.
+
+The naming scheme for input sections allows grouping all linker lists
+into a single linker output section and grouping all entries for a
+single list.
+
+Note the two '_2_' constant components in the names: their presence
+allows putting a start and end symbols around a list, by mapping
+these symbols to sections names with components "1" (before) and
+"3" (after) instead of "2" (within).
+Start and end symbols for a list can generally be defined as
+
+::
+
+ %u_boot_list_2_ + @_list + _1_...
+ %u_boot_list_2_ + @_list + _3_...
+
+Start and end symbols for the whole of the linker lists area can be
+defined as
+
+::
+
+ %u_boot_list_1_...
+ %u_boot_list_3_...
+
+Here is an example of the sorted sections which result from a list
+"array" made up of three entries : "first", "second" and "third",
+iterated at least once.
+
+::
+
+ .u_boot_list_2_array_1
+ .u_boot_list_2_array_2_first
+ .u_boot_list_2_array_2_second
+ .u_boot_list_2_array_2_third
+ .u_boot_list_2_array_3
+
+If lists must be divided into sublists (e.g. for iterating only on
+part of a list), one can simply give the list a name of the form
+'outer_2_inner', where 'outer' is the global list name and 'inner'
+is the sub-list name. Iterators for the whole list should use the
+global list name ("outer"); iterators for only a sub-list should use
+the full sub-list name ("outer_2_inner").
+
+Here is an example of the sections generated from a global list
+named "drivers", two sub-lists named "i2c" and "pci", and iterators
+defined for the whole list and each sub-list:
+
+::
+
+ %u_boot_list_2_drivers_1
+ %u_boot_list_2_drivers_2_i2c_1
+ %u_boot_list_2_drivers_2_i2c_2_first
+ %u_boot_list_2_drivers_2_i2c_2_first
+ %u_boot_list_2_drivers_2_i2c_2_second
+ %u_boot_list_2_drivers_2_i2c_2_third
+ %u_boot_list_2_drivers_2_i2c_3
+ %u_boot_list_2_drivers_2_pci_1
+ %u_boot_list_2_drivers_2_pci_2_first
+ %u_boot_list_2_drivers_2_pci_2_second
+ %u_boot_list_2_drivers_2_pci_2_third
+ %u_boot_list_2_drivers_2_pci_3
+ %u_boot_list_2_drivers_3
+
+.. kernel-doc:: include/linker_lists.h
+ :internal:
diff --git a/Documentation/media/Makefile b/Documentation/media/Makefile
new file mode 100644
index 0000000..0efd18a
--- /dev/null
+++ b/Documentation/media/Makefile
@@ -0,0 +1,38 @@
+# Rules to convert a .h file to inline RST documentation
+
+SRC_DIR=$(srctree)/Documentation/media
+PARSER = $(srctree)/Documentation/sphinx/parse-headers.pl
+API = $(srctree)/include
+
+FILES = linker_lists.h.rst
+
+TARGETS := $(addprefix $(BUILDDIR)/, $(FILES))
+
+gen_rst = \
+ echo ${PARSER} $< $@ $(SRC_DIR)/$(notdir $@).exceptions; \
+ ${PARSER} $< $@ $(SRC_DIR)/$(notdir $@).exceptions
+
+quiet_gen_rst = echo ' PARSE $(patsubst $(srctree)/%,%,$<)'; \
+ ${PARSER} $< $@ $(SRC_DIR)/$(notdir $@).exceptions
+
+silent_gen_rst = ${gen_rst}
+
+$(BUILDDIR)/linker_lists.h.rst: ${API}/linker_lists.h ${PARSER} $(SRC_DIR)/linker_lists.h.rst.exceptions
+ @$($(quiet)gen_rst)
+
+# Media build rules
+
+.PHONY: all html epub xml latex
+
+all: $(IMGDOT) $(BUILDDIR) ${TARGETS}
+html: all
+epub: all
+xml: all
+latex: $(IMGPDF) all
+linkcheck:
+
+clean:
+ -rm -f $(DOTTGT) $(IMGTGT) ${TARGETS} 2>/dev/null
+
+$(BUILDDIR):
+ $(Q)mkdir -p $@
diff --git a/drivers/hwmon/Kconfig b/Documentation/media/linker_lists.h.rst.exceptions
similarity index 100%
rename from drivers/hwmon/Kconfig
rename to Documentation/media/linker_lists.h.rst.exceptions
diff --git a/Documentation/serial.rst b/Documentation/serial.rst
new file mode 100644
index 0000000..ed34e59
--- /dev/null
+++ b/Documentation/serial.rst
@@ -0,0 +1,7 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Serial system
+=============
+
+.. kernel-doc:: drivers/serial/serial.c
+ :internal:
diff --git a/Documentation/sphinx-static/theme_overrides.css b/Documentation/sphinx-static/theme_overrides.css
new file mode 100644
index 0000000..522b6d4
--- /dev/null
+++ b/Documentation/sphinx-static/theme_overrides.css
@@ -0,0 +1,89 @@
+/* -*- coding: utf-8; mode: css -*-
+ *
+ * Sphinx HTML theme customization: read the doc
+ *
+ */
+
+/* Interim: Code-blocks with line nos - lines and line numbers don't line up.
+ * see: https://github.com/rtfd/sphinx_rtd_theme/issues/419
+ */
+
+div[class^="highlight"] pre {
+ line-height: normal;
+}
+.rst-content .highlight > pre {
+ line-height: normal;
+}
+
+@media screen {
+
+ /* content column
+ *
+ * RTD theme's default is 800px as max width for the content, but we have
+ * tables with tons of columns, which need the full width of the view-port.
+ */
+
+ .wy-nav-content{max-width: none; }
+
+ /* table:
+ *
+ * - Sequences of whitespace should collapse into a single whitespace.
+ * - make the overflow auto (scrollbar if needed)
+ * - align caption "left" ("center" is unsuitable on vast tables)
+ */
+
+ .wy-table-responsive table td { white-space: normal; }
+ .wy-table-responsive { overflow: auto; }
+ .rst-content table.docutils caption { text-align: left; font-size: 100%; }
+
+ /* captions:
+ *
+ * - captions should have 100% (not 85%) font size
+ * - hide the permalink symbol as long as link is not hovered
+ */
+
+ .toc-title {
+ font-size: 150%;
+ font-weight: bold;
+ }
+
+ caption, .wy-table caption, .rst-content table.field-list caption {
+ font-size: 100%;
+ }
+ caption a.headerlink { opacity: 0; }
+ caption a.headerlink:hover { opacity: 1; }
+
+ /* Menu selection and keystrokes */
+
+ span.menuselection {
+ color: blue;
+ font-family: "Courier New", Courier, monospace
+ }
+
+ code.kbd, code.kbd span {
+ color: white;
+ background-color: darkblue;
+ font-weight: bold;
+ font-family: "Courier New", Courier, monospace
+ }
+
+ /* fix bottom margin of lists items */
+
+ .rst-content .section ul li:last-child, .rst-content .section ul li p:last-child {
+ margin-bottom: 12px;
+ }
+
+ /* inline literal: drop the borderbox, padding and red color */
+
+ code, .rst-content tt, .rst-content code {
+ color: inherit;
+ border: none;
+ padding: unset;
+ background: inherit;
+ font-size: 85%;
+ }
+
+ .rst-content tt.literal,.rst-content tt.literal,.rst-content code.literal {
+ color: inherit;
+ }
+}
diff --git a/Documentation/sphinx/cdomain.py b/Documentation/sphinx/cdomain.py
new file mode 100644
index 0000000..cf13ff3
--- /dev/null
+++ b/Documentation/sphinx/cdomain.py
@@ -0,0 +1,165 @@
+# -*- coding: utf-8; mode: python -*-
+# pylint: disable=W0141,C0113,C0103,C0325
+u"""
+ cdomain
+ ~~~~~~~
+
+ Replacement for the sphinx c-domain.
+
+ :copyright: Copyright (C) 2016 Markus Heiser
+ :license: GPL Version 2, June 1991 see Linux/COPYING for details.
+
+ List of customizations:
+
+ * Moved the *duplicate C object description* warnings for function
+ declarations in the nitpicky mode. See Sphinx documentation for
+ the config values for ``nitpick`` and ``nitpick_ignore``.
+
+ * Add option 'name' to the "c:function:" directive. With option 'name' the
+ ref-name of a function can be modified. E.g.::
+
+ .. c:function:: int ioctl( int fd, int request )
+ :name: VIDIOC_LOG_STATUS
+
+ The func-name (e.g. ioctl) remains in the output but the ref-name changed
+ from 'ioctl' to 'VIDIOC_LOG_STATUS'. The function is referenced by::
+
+ * :c:func:`VIDIOC_LOG_STATUS` or
+ * :any:`VIDIOC_LOG_STATUS` (``:any:`` needs sphinx 1.3)
+
+ * Handle signatures of function-like macros well. Don't try to deduce
+ arguments types of function-like macros.
+
+"""
+
+from docutils import nodes
+from docutils.parsers.rst import directives
+
+import sphinx
+from sphinx import addnodes
+from sphinx.domains.c import c_funcptr_sig_re, c_sig_re
+from sphinx.domains.c import CObject as Base_CObject
+from sphinx.domains.c import CDomain as Base_CDomain
+
+__version__ = '1.0'
+
+# Get Sphinx version
+major, minor, patch = sphinx.version_info[:3]
+
+def setup(app):
+
+ app.override_domain(CDomain)
+
+ return dict(
+ version = __version__,
+ parallel_read_safe = True,
+ parallel_write_safe = True
+ )
+
+class CObject(Base_CObject):
+
+ """
+ Description of a C language object.
+ """
+ option_spec = {
+ "name" : directives.unchanged
+ }
+
+ def handle_func_like_macro(self, sig, signode):
+ u"""Handles signatures of function-like macros.
+
+ If the objtype is 'function' and the the signature ``sig`` is a
+ function-like macro, the name of the macro is returned. Otherwise
+ ``False`` is returned. """
+
+ if not self.objtype == 'function':
+ return False
+
+ m = c_funcptr_sig_re.match(sig)
+ if m is None:
+ m = c_sig_re.match(sig)
+ if m is None:
+ raise ValueError('no match')
+
+ rettype, fullname, arglist, _const = m.groups()
+ arglist = arglist.strip()
+ if rettype or not arglist:
+ return False
+
+ arglist = arglist.replace('`', '').replace('\\ ', '') # remove markup
+ arglist = [a.strip() for a in arglist.split(",")]
+
+ # has the first argument a type?
+ if len(arglist[0].split(" ")) > 1:
+ return False
+
+ # This is a function-like macro, it's arguments are typeless!
+ signode += addnodes.desc_name(fullname, fullname)
+ paramlist = addnodes.desc_parameterlist()
+ signode += paramlist
+
+ for argname in arglist:
+ param = addnodes.desc_parameter('', '', noemph=True)
+ # separate by non-breaking space in the output
+ param += nodes.emphasis(argname, argname)
+ paramlist += param
+
+ return fullname
+
+ def handle_signature(self, sig, signode):
+ """Transform a C signature into RST nodes."""
+
+ fullname = self.handle_func_like_macro(sig, signode)
+ if not fullname:
+ fullname = super(CObject, self).handle_signature(sig, signode)
+
+ if "name" in self.options:
+ if self.objtype == 'function':
+ fullname = self.options["name"]
+ else:
+ # FIXME: handle :name: value of other declaration types?
+ pass
+ return fullname
+
+ def add_target_and_index(self, name, sig, signode):
+ # for C API items we add a prefix since names are usually not qualified
+ # by a module name and so easily clash with e.g. section titles
+ targetname = 'c.' + name
+ if targetname not in self.state.document.ids:
+ signode['names'].append(targetname)
+ signode['ids'].append(targetname)
+ signode['first'] = (not self.names)
+ self.state.document.note_explicit_target(signode)
+ inv = self.env.domaindata['c']['objects']
+ if (name in inv and self.env.config.nitpicky):
+ if self.objtype == 'function':
+ if ('c:func', name) not in self.env.config.nitpick_ignore:
+ self.state_machine.reporter.warning(
+ 'duplicate C object description of %s, ' % name +
+ 'other instance in ' + self.env.doc2path(inv[name][0]),
+ line=self.lineno)
+ inv[name] = (self.env.docname, self.objtype)
+
+ indextext = self.get_index_text(name)
+ if indextext:
+ if major == 1 and minor < 4:
+ # indexnode's tuple changed in 1.4
+ # https://github.com/sphinx-doc/sphinx/commit/e6a5a3a92e938fcd75866b4227db9e0524d58f7c
+ self.indexnode['entries'].append(
+ ('single', indextext, targetname, ''))
+ else:
+ self.indexnode['entries'].append(
+ ('single', indextext, targetname, '', None))
+
+class CDomain(Base_CDomain):
+
+ """C language domain."""
+ name = 'c'
+ label = 'C'
+ directives = {
+ 'function': CObject,
+ 'member': CObject,
+ 'macro': CObject,
+ 'type': CObject,
+ 'var': CObject,
+ }
diff --git a/Documentation/sphinx/kernel_include.py b/Documentation/sphinx/kernel_include.py
new file mode 100755
index 0000000..f523aa6
--- /dev/null
+++ b/Documentation/sphinx/kernel_include.py
@@ -0,0 +1,190 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8; mode: python -*-
+# pylint: disable=R0903, C0330, R0914, R0912, E0401
+
+u"""
+ kernel-include
+ ~~~~~~~~~~~~~~
+
+ Implementation of the ``kernel-include`` reST-directive.
+
+ :copyright: Copyright (C) 2016 Markus Heiser
+ :license: GPL Version 2, June 1991 see linux/COPYING for details.
+
+ The ``kernel-include`` reST-directive is a replacement for the ``include``
+ directive. The ``kernel-include`` directive expand environment variables in
+ the path name and allows to include files from arbitrary locations.
+
+ .. hint::
+
+ Including files from arbitrary locations (e.g. from ``/etc``) is a
+ security risk for builders. This is why the ``include`` directive from
+ docutils *prohibit* pathnames pointing to locations *above* the filesystem
+ tree where the reST document with the include directive is placed.
+
+ Substrings of the form $name or ${name} are replaced by the value of
+ environment variable name. Malformed variable names and references to
+ non-existing variables are left unchanged.
+"""
+
+# ==============================================================================
+# imports
+# ==============================================================================
+
+import os.path
+
+from docutils import io, nodes, statemachine
+from docutils.utils.error_reporting import SafeString, ErrorString
+from docutils.parsers.rst import directives
+from docutils.parsers.rst.directives.body import CodeBlock, NumberLines
+from docutils.parsers.rst.directives.misc import Include
+
+__version__ = '1.0'
+
+# ==============================================================================
+def setup(app):
+# ==============================================================================
+
+ app.add_directive("kernel-include", KernelInclude)
+ return dict(
+ version = __version__,
+ parallel_read_safe = True,
+ parallel_write_safe = True
+ )
+
+# ==============================================================================
+class KernelInclude(Include):
+# ==============================================================================
+
+ u"""KernelInclude (``kernel-include``) directive"""
+
+ def run(self):
+ path = os.path.realpath(
+ os.path.expandvars(self.arguments[0]))
+
+ # to get a bit security back, prohibit /etc:
+ if path.startswith(os.sep + "etc"):
+ raise self.severe(
+ 'Problems with "%s" directive, prohibited path: %s'
+ % (self.name, path))
+
+ self.arguments[0] = path
+
+ #return super(KernelInclude, self).run() # won't work, see HINTs in _run()
+ return self._run()
+
+ def _run(self):
+ """Include a file as part of the content of this reST file."""
+
+ # HINT: I had to copy&paste the whole Include.run method. I'am not happy
+ # with this, but due to security reasons, the Include.run method does
+ # not allow absolute or relative pathnames pointing to locations *above*
+ # the filesystem tree where the reST document is placed.
+
+ if not self.state.document.settings.file_insertion_enabled:
+ raise self.warning('"%s" directive disabled.' % self.name)
+ source = self.state_machine.input_lines.source(
+ self.lineno - self.state_machine.input_offset - 1)
+ source_dir = os.path.dirname(os.path.abspath(source))
+ path = directives.path(self.arguments[0])
+ if path.startswith('<') and path.endswith('>'):
+ path = os.path.join(self.standard_include_path, path[1:-1])
+ path = os.path.normpath(os.path.join(source_dir, path))
+
+ # HINT: this is the only line I had to change / commented out:
+ #path = utils.relative_path(None, path)
+
+ path = nodes.reprunicode(path)
+ encoding = self.options.get(
+ 'encoding', self.state.document.settings.input_encoding)
+ e_handler=self.state.document.settings.input_encoding_error_handler
+ tab_width = self.options.get(
+ 'tab-width', self.state.document.settings.tab_width)
+ try:
+ self.state.document.settings.record_dependencies.add(path)
+ include_file = io.FileInput(source_path=path,
+ encoding=encoding,
+ error_handler=e_handler)
+ except UnicodeEncodeError as error:
+ raise self.severe('Problems with "%s" directive path:\n'
+ 'Cannot encode input file path "%s" '
+ '(wrong locale?).' %
+ (self.name, SafeString(path)))
+ except IOError as error:
+ raise self.severe('Problems with "%s" directive path:\n%s.' %
+ (self.name, ErrorString(error)))
+ startline = self.options.get('start-line', None)
+ endline = self.options.get('end-line', None)
+ try:
+ if startline or (endline is not None):
+ lines = include_file.readlines()
+ rawtext = ''.join(lines[startline:endline])
+ else:
+ rawtext = include_file.read()
+ except UnicodeError as error:
+ raise self.severe('Problem with "%s" directive:\n%s' %
+ (self.name, ErrorString(error)))
+ # start-after/end-before: no restrictions on newlines in match-text,
+ # and no restrictions on matching inside lines vs. line boundaries
+ after_text = self.options.get('start-after', None)
+ if after_text:
+ # skip content in rawtext before *and incl.* a matching text
+ after_index = rawtext.find(after_text)
+ if after_index < 0:
+ raise self.severe('Problem with "start-after" option of "%s" '
+ 'directive:\nText not found.' % self.name)
+ rawtext = rawtext[after_index + len(after_text):]
+ before_text = self.options.get('end-before', None)
+ if before_text:
+ # skip content in rawtext after *and incl.* a matching text
+ before_index = rawtext.find(before_text)
+ if before_index < 0:
+ raise self.severe('Problem with "end-before" option of "%s" '
+ 'directive:\nText not found.' % self.name)
+ rawtext = rawtext[:before_index]
+
+ include_lines = statemachine.string2lines(rawtext, tab_width,
+ convert_whitespace=True)
+ if 'literal' in self.options:
+ # Convert tabs to spaces, if `tab_width` is positive.
+ if tab_width >= 0:
+ text = rawtext.expandtabs(tab_width)
+ else:
+ text = rawtext
+ literal_block = nodes.literal_block(rawtext, source=path,
+ classes=self.options.get('class', []))
+ literal_block.line = 1
+ self.add_name(literal_block)
+ if 'number-lines' in self.options:
+ try:
+ startline = int(self.options['number-lines'] or 1)
+ except ValueError:
+ raise self.error(':number-lines: with non-integer '
+ 'start value')
+ endline = startline + len(include_lines)
+ if text.endswith('\n'):
+ text = text[:-1]
+ tokens = NumberLines([([], text)], startline, endline)
+ for classes, value in tokens:
+ if classes:
+ literal_block += nodes.inline(value, value,
+ classes=classes)
+ else:
+ literal_block += nodes.Text(value, value)
+ else:
+ literal_block += nodes.Text(text, text)
+ return [literal_block]
+ if 'code' in self.options:
+ self.options['source'] = path
+ codeblock = CodeBlock(self.name,
+ [self.options.pop('code')], # arguments
+ self.options,
+ include_lines, # content
+ self.lineno,
+ self.content_offset,
+ self.block_text,
+ self.state,
+ self.state_machine)
+ return codeblock.run()
+ self.state_machine.insert_input(include_lines, path)
+ return []
diff --git a/Documentation/sphinx/kerneldoc.py b/Documentation/sphinx/kerneldoc.py
new file mode 100644
index 0000000..fbedcc3
--- /dev/null
+++ b/Documentation/sphinx/kerneldoc.py
@@ -0,0 +1,146 @@
+# coding=utf-8
+#
+# Copyright © 2016 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+#
+# Authors:
+# Jani Nikula <jani.nikula@intel.com>
+#
+# Please make sure this works on both python2 and python3.
+#
+
+import codecs
+import os
+import subprocess
+import sys
+import re
+import glob
+
+from docutils import nodes, statemachine
+from docutils.statemachine import ViewList
+from docutils.parsers.rst import directives, Directive
+from sphinx.ext.autodoc import AutodocReporter
+
+__version__ = '1.0'
+
+class KernelDocDirective(Directive):
+ """Extract kernel-doc comments from the specified file"""
+ required_argument = 1
+ optional_arguments = 4
+ option_spec = {
+ 'doc': directives.unchanged_required,
+ 'functions': directives.unchanged_required,
+ 'export': directives.unchanged,
+ 'internal': directives.unchanged,
+ }
+ has_content = False
+
+ def run(self):
+ env = self.state.document.settings.env
+ cmd = [env.config.kerneldoc_bin, '-rst', '-enable-lineno']
+
+ filename = env.config.kerneldoc_srctree + '/' + self.arguments[0]
+ export_file_patterns = []
+
+ # Tell sphinx of the dependency
+ env.note_dependency(os.path.abspath(filename))
+
+ tab_width = self.options.get('tab-width', self.state.document.settings.tab_width)
+
+ # FIXME: make this nicer and more robust against errors
+ if 'export' in self.options:
+ cmd += ['-export']
+ export_file_patterns = str(self.options.get('export')).split()
+ elif 'internal' in self.options:
+ cmd += ['-internal']
+ export_file_patterns = str(self.options.get('internal')).split()
+ elif 'doc' in self.options:
+ cmd += ['-function', str(self.options.get('doc'))]
+ elif 'functions' in self.options:
+ for f in str(self.options.get('functions')).split():
+ cmd += ['-function', f]
+
+ for pattern in export_file_patterns:
+ for f in glob.glob(env.config.kerneldoc_srctree + '/' + pattern):
+ env.note_dependency(os.path.abspath(f))
+ cmd += ['-export-file', f]
+
+ cmd += [filename]
+
+ try:
+ env.app.verbose('calling kernel-doc \'%s\'' % (" ".join(cmd)))
+
+ p = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+ out, err = p.communicate()
+
+ out, err = codecs.decode(out, 'utf-8'), codecs.decode(err, 'utf-8')
+
+ if p.returncode != 0:
+ sys.stderr.write(err)
+
+ env.app.warn('kernel-doc \'%s\' failed with return code %d' % (" ".join(cmd), p.returncode))
+ return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
+ elif env.config.kerneldoc_verbosity > 0:
+ sys.stderr.write(err)
+
+ lines = statemachine.string2lines(out, tab_width, convert_whitespace=True)
+ result = ViewList()
+
+ lineoffset = 0;
+ line_regex = re.compile("^#define LINENO ([0-9]+)$")
+ for line in lines:
+ match = line_regex.search(line)
+ if match:
+ # sphinx counts lines from 0
+ lineoffset = int(match.group(1)) - 1
+ # we must eat our comments since the upset the markup
+ else:
+ result.append(line, filename, lineoffset)
+ lineoffset += 1
+
+ node = nodes.section()
+ buf = self.state.memo.title_styles, self.state.memo.section_level, self.state.memo.reporter
+ self.state.memo.reporter = AutodocReporter(result, self.state.memo.reporter)
+ self.state.memo.title_styles, self.state.memo.section_level = [], 0
+ try:
+ self.state.nested_parse(result, 0, node, match_titles=1)
+ finally:
+ self.state.memo.title_styles, self.state.memo.section_level, self.state.memo.reporter = buf
+
+ return node.children
+
+ except Exception as e: # pylint: disable=W0703
+ env.app.warn('kernel-doc \'%s\' processing failed with: %s' %
+ (" ".join(cmd), str(e)))
+ return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
+
+def setup(app):
+ app.add_config_value('kerneldoc_bin', None, 'env')
+ app.add_config_value('kerneldoc_srctree', None, 'env')
+ app.add_config_value('kerneldoc_verbosity', 1, 'env')
+
+ app.add_directive('kernel-doc', KernelDocDirective)
+
+ return dict(
+ version = __version__,
+ parallel_read_safe = True,
+ parallel_write_safe = True
+ )
diff --git a/Documentation/sphinx/kfigure.py b/Documentation/sphinx/kfigure.py
new file mode 100644
index 0000000..b97228d
--- /dev/null
+++ b/Documentation/sphinx/kfigure.py
@@ -0,0 +1,551 @@
+# -*- coding: utf-8; mode: python -*-
+# pylint: disable=C0103, R0903, R0912, R0915
+u"""
+ scalable figure and image handling
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Sphinx extension which implements scalable image handling.
+
+ :copyright: Copyright (C) 2016 Markus Heiser
+ :license: GPL Version 2, June 1991 see Linux/COPYING for details.
+
+ The build for image formats depend on image's source format and output's
+ destination format. This extension implement methods to simplify image
+ handling from the author's POV. Directives like ``kernel-figure`` implement
+ methods *to* always get the best output-format even if some tools are not
+ installed. For more details take a look at ``convert_image(...)`` which is
+ the core of all conversions.
+
+ * ``.. kernel-image``: for image handling / a ``.. image::`` replacement
+
+ * ``.. kernel-figure``: for figure handling / a ``.. figure::`` replacement
+
+ * ``.. kernel-render``: for render markup / a concept to embed *render*
+ markups (or languages). Supported markups (see ``RENDER_MARKUP_EXT``)
+
+ - ``DOT``: render embedded Graphviz's **DOC**
+ - ``SVG``: render embedded Scalable Vector Graphics (**SVG**)
+ - ... *developable*
+
+ Used tools:
+
+ * ``dot(1)``: Graphviz (http://www.graphviz.org). If Graphviz is not
+ available, the DOT language is inserted as literal-block.
+
+ * SVG to PDF: To generate PDF, you need at least one of this tools:
+
+ - ``convert(1)``: ImageMagick (https://www.imagemagick.org)
+
+ List of customizations:
+
+ * generate PDF from SVG / used by PDF (LaTeX) builder
+
+ * generate SVG (html-builder) and PDF (latex-builder) from DOT files.
+ DOT: see http://www.graphviz.org/content/dot-language
+
+ """
+
+import os
+from os import path
+import subprocess
+from hashlib import sha1
+import sys
+
+from docutils import nodes
+from docutils.statemachine import ViewList
+from docutils.parsers.rst import directives
+from docutils.parsers.rst.directives import images
+import sphinx
+
+from sphinx.util.nodes import clean_astext
+from six import iteritems
+
+PY3 = sys.version_info[0] == 3
+
+if PY3:
+ _unicode = str
+else:
+ _unicode = unicode
+
+# Get Sphinx version
+major, minor, patch = sphinx.version_info[:3]
+if major == 1 and minor > 3:
+ # patches.Figure only landed in Sphinx 1.4
+ from sphinx.directives.patches import Figure # pylint: disable=C0413
+else:
+ Figure = images.Figure
+
+__version__ = '1.0.0'
+
+# simple helper
+# -------------
+
+def which(cmd):
+ """Searches the ``cmd`` in the ``PATH`` environment.
+
+ This *which* searches the PATH for executable ``cmd`` . First match is
+ returned, if nothing is found, ``None` is returned.
+ """
+ envpath = os.environ.get('PATH', None) or os.defpath
+ for folder in envpath.split(os.pathsep):
+ fname = folder + os.sep + cmd
+ if path.isfile(fname):
+ return fname
+
+def mkdir(folder, mode=0o775):
+ if not path.isdir(folder):
+ os.makedirs(folder, mode)
+
+def file2literal(fname):
+ with open(fname, "r") as src:
+ data = src.read()
+ node = nodes.literal_block(data, data)
+ return node
+
+def isNewer(path1, path2):
+ """Returns True if ``path1`` is newer than ``path2``
+
+ If ``path1`` exists and is newer than ``path2`` the function returns
+ ``True`` is returned otherwise ``False``
+ """
+ return (path.exists(path1)
+ and os.stat(path1).st_ctime > os.stat(path2).st_ctime)
+
+def pass_handle(self, node): # pylint: disable=W0613
+ pass
+
+# setup conversion tools and sphinx extension
+# -------------------------------------------
+
+# Graphviz's dot(1) support
+dot_cmd = None
+
+# ImageMagick' convert(1) support
+convert_cmd = None
+
+
+def setup(app):
+ # check toolchain first
+ app.connect('builder-inited', setupTools)
+
+ # image handling
+ app.add_directive("kernel-image", KernelImage)
+ app.add_node(kernel_image,
+ html = (visit_kernel_image, pass_handle),
+ latex = (visit_kernel_image, pass_handle),
+ texinfo = (visit_kernel_image, pass_handle),
+ text = (visit_kernel_image, pass_handle),
+ man = (visit_kernel_image, pass_handle), )
+
+ # figure handling
+ app.add_directive("kernel-figure", KernelFigure)
+ app.add_node(kernel_figure,
+ html = (visit_kernel_figure, pass_handle),
+ latex = (visit_kernel_figure, pass_handle),
+ texinfo = (visit_kernel_figure, pass_handle),
+ text = (visit_kernel_figure, pass_handle),
+ man = (visit_kernel_figure, pass_handle), )
+
+ # render handling
+ app.add_directive('kernel-render', KernelRender)
+ app.add_node(kernel_render,
+ html = (visit_kernel_render, pass_handle),
+ latex = (visit_kernel_render, pass_handle),
+ texinfo = (visit_kernel_render, pass_handle),
+ text = (visit_kernel_render, pass_handle),
+ man = (visit_kernel_render, pass_handle), )
+
+ app.connect('doctree-read', add_kernel_figure_to_std_domain)
+
+ return dict(
+ version = __version__,
+ parallel_read_safe = True,
+ parallel_write_safe = True
+ )
+
+
+def setupTools(app):
+ u"""
+ Check available build tools and log some *verbose* messages.
+
+ This function is called once, when the builder is initiated.
+ """
+ global dot_cmd, convert_cmd # pylint: disable=W0603
+ app.verbose("kfigure: check installed tools ...")
+
+ dot_cmd = which('dot')
+ convert_cmd = which('convert')
+
+ if dot_cmd:
+ app.verbose("use dot(1) from: " + dot_cmd)
+ else:
+ app.warn("dot(1) not found, for better output quality install "
+ "graphviz from http://www.graphviz.org")
+ if convert_cmd:
+ app.verbose("use convert(1) from: " + convert_cmd)
+ else:
+ app.warn(
+ "convert(1) not found, for SVG to PDF conversion install "
+ "ImageMagick (https://www.imagemagick.org)")
+
+
+# integrate conversion tools
+# --------------------------
+
+RENDER_MARKUP_EXT = {
+ # The '.ext' must be handled by convert_image(..) function's *in_ext* input.
+ # <name> : <.ext>
+ 'DOT' : '.dot',
+ 'SVG' : '.svg'
+}
+
+def convert_image(img_node, translator, src_fname=None):
+ """Convert a image node for the builder.
+
+ Different builder prefer different image formats, e.g. *latex* builder
+ prefer PDF while *html* builder prefer SVG format for images.
+
+ This function handles output image formats in dependence of source the
+ format (of the image) and the translator's output format.
+ """
+ app = translator.builder.app
+
+ fname, in_ext = path.splitext(path.basename(img_node['uri']))
+ if src_fname is None:
+ src_fname = path.join(translator.builder.srcdir, img_node['uri'])
+ if not path.exists(src_fname):
+ src_fname = path.join(translator.builder.outdir, img_node['uri'])
+
+ dst_fname = None
+
+ # in kernel builds, use 'make SPHINXOPTS=-v' to see verbose messages
+
+ app.verbose('assert best format for: ' + img_node['uri'])
+
+ if in_ext == '.dot':
+
+ if not dot_cmd:
+ app.verbose("dot from graphviz not available / include DOT raw.")
+ img_node.replace_self(file2literal(src_fname))
+
+ elif translator.builder.format == 'latex':
+ dst_fname = path.join(translator.builder.outdir, fname + '.pdf')
+ img_node['uri'] = fname + '.pdf'
+ img_node['candidates'] = {'*': fname + '.pdf'}
+
+
+ elif translator.builder.format == 'html':
+ dst_fname = path.join(
+ translator.builder.outdir,
+ translator.builder.imagedir,
+ fname + '.svg')
+ img_node['uri'] = path.join(
+ translator.builder.imgpath, fname + '.svg')
+ img_node['candidates'] = {
+ '*': path.join(translator.builder.imgpath, fname + '.svg')}
+
+ else:
+ # all other builder formats will include DOT as raw
+ img_node.replace_self(file2literal(src_fname))
+
+ elif in_ext == '.svg':
+
+ if translator.builder.format == 'latex':
+ if convert_cmd is None:
+ app.verbose("no SVG to PDF conversion available / include SVG raw.")
+ img_node.replace_self(file2literal(src_fname))
+ else:
+ dst_fname = path.join(translator.builder.outdir, fname + '.pdf')
+ img_node['uri'] = fname + '.pdf'
+ img_node['candidates'] = {'*': fname + '.pdf'}
+
+ if dst_fname:
+ # the builder needs not to copy one more time, so pop it if exists.
+ translator.builder.images.pop(img_node['uri'], None)
+ _name = dst_fname[len(translator.builder.outdir) + 1:]
+
+ if isNewer(dst_fname, src_fname):
+ app.verbose("convert: {out}/%s already exists and is newer" % _name)
+
+ else:
+ ok = False
+ mkdir(path.dirname(dst_fname))
+
+ if in_ext == '.dot':
+ app.verbose('convert DOT to: {out}/' + _name)
+ ok = dot2format(app, src_fname, dst_fname)
+
+ elif in_ext == '.svg':
+ app.verbose('convert SVG to: {out}/' + _name)
+ ok = svg2pdf(app, src_fname, dst_fname)
+
+ if not ok:
+ img_node.replace_self(file2literal(src_fname))
+
+
+def dot2format(app, dot_fname, out_fname):
+ """Converts DOT file to ``out_fname`` using ``dot(1)``.
+
+ * ``dot_fname`` pathname of the input DOT file, including extension ``.dot``
+ * ``out_fname`` pathname of the output file, including format extension
+
+ The *format extension* depends on the ``dot`` command (see ``man dot``
+ option ``-Txxx``). Normally you will use one of the following extensions:
+
+ - ``.ps`` for PostScript,
+ - ``.svg`` or ``svgz`` for Structured Vector Graphics,
+ - ``.fig`` for XFIG graphics and
+ - ``.png`` or ``gif`` for common bitmap graphics.
+
+ """
+ out_format = path.splitext(out_fname)[1][1:]
+ cmd = [dot_cmd, '-T%s' % out_format, dot_fname]
+ exit_code = 42
+
+ with open(out_fname, "w") as out:
+ exit_code = subprocess.call(cmd, stdout = out)
+ if exit_code != 0:
+ app.warn("Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
+ return bool(exit_code == 0)
+
+def svg2pdf(app, svg_fname, pdf_fname):
+ """Converts SVG to PDF with ``convert(1)`` command.
+
+ Uses ``convert(1)`` from ImageMagick (https://www.imagemagick.org) for
+ conversion. Returns ``True`` on success and ``False`` if an error occurred.
+
+ * ``svg_fname`` pathname of the input SVG file with extension (``.svg``)
+ * ``pdf_name`` pathname of the output PDF file with extension (``.pdf``)
+
+ """
+ cmd = [convert_cmd, svg_fname, pdf_fname]
+ # use stdout and stderr from parent
+ exit_code = subprocess.call(cmd)
+ if exit_code != 0:
+ app.warn("Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
+ return bool(exit_code == 0)
+
+
+# image handling
+# ---------------------
+
+def visit_kernel_image(self, node): # pylint: disable=W0613
+ """Visitor of the ``kernel_image`` Node.
+
+ Handles the ``image`` child-node with the ``convert_image(...)``.
+ """
+ img_node = node[0]
+ convert_image(img_node, self)
+
+class kernel_image(nodes.image):
+ """Node for ``kernel-image`` directive."""
+ pass
+
+class KernelImage(images.Image):
+ u"""KernelImage directive
+
+ Earns everything from ``.. image::`` directive, except *remote URI* and
+ *glob* pattern. The KernelImage wraps a image node into a
+ kernel_image node. See ``visit_kernel_image``.
+ """
+
+ def run(self):
+ uri = self.arguments[0]
+ if uri.endswith('.*') or uri.find('://') != -1:
+ raise self.severe(
+ 'Error in "%s: %s": glob pattern and remote images are not allowed'
+ % (self.name, uri))
+ result = images.Image.run(self)
+ if len(result) == 2 or isinstance(result[0], nodes.system_message):
+ return result
+ (image_node,) = result
+ # wrap image node into a kernel_image node / see visitors
+ node = kernel_image('', image_node)
+ return [node]
+
+# figure handling
+# ---------------------
+
+def visit_kernel_figure(self, node): # pylint: disable=W0613
+ """Visitor of the ``kernel_figure`` Node.
+
+ Handles the ``image`` child-node with the ``convert_image(...)``.
+ """
+ img_node = node[0][0]
+ convert_image(img_node, self)
+
+class kernel_figure(nodes.figure):
+ """Node for ``kernel-figure`` directive."""
+
+class KernelFigure(Figure):
+ u"""KernelImage directive
+
+ Earns everything from ``.. figure::`` directive, except *remote URI* and
+ *glob* pattern. The KernelFigure wraps a figure node into a kernel_figure
+ node. See ``visit_kernel_figure``.
+ """
+
+ def run(self):
+ uri = self.arguments[0]
+ if uri.endswith('.*') or uri.find('://') != -1:
+ raise self.severe(
+ 'Error in "%s: %s":'
+ ' glob pattern and remote images are not allowed'
+ % (self.name, uri))
+ result = Figure.run(self)
+ if len(result) == 2 or isinstance(result[0], nodes.system_message):
+ return result
+ (figure_node,) = result
+ # wrap figure node into a kernel_figure node / see visitors
+ node = kernel_figure('', figure_node)
+ return [node]
+
+
+# render handling
+# ---------------------
+
+def visit_kernel_render(self, node):
+ """Visitor of the ``kernel_render`` Node.
+
+ If rendering tools available, save the markup of the ``literal_block`` child
+ node into a file and replace the ``literal_block`` node with a new created
+ ``image`` node, pointing to the saved markup file. Afterwards, handle the
+ image child-node with the ``convert_image(...)``.
+ """
+ app = self.builder.app
+ srclang = node.get('srclang')
+
+ app.verbose('visit kernel-render node lang: "%s"' % (srclang))
+
+ tmp_ext = RENDER_MARKUP_EXT.get(srclang, None)
+ if tmp_ext is None:
+ app.warn('kernel-render: "%s" unknown / include raw.' % (srclang))
+ return
+
+ if not dot_cmd and tmp_ext == '.dot':
+ app.verbose("dot from graphviz not available / include raw.")
+ return
+
+ literal_block = node[0]
+
+ code = literal_block.astext()
+ hashobj = code.encode('utf-8') # str(node.attributes)
+ fname = path.join('%s-%s' % (srclang, sha1(hashobj).hexdigest()))
+
+ tmp_fname = path.join(
+ self.builder.outdir, self.builder.imagedir, fname + tmp_ext)
+
+ if not path.isfile(tmp_fname):
+ mkdir(path.dirname(tmp_fname))
+ with open(tmp_fname, "w") as out:
+ out.write(code)
+
+ img_node = nodes.image(node.rawsource, **node.attributes)
+ img_node['uri'] = path.join(self.builder.imgpath, fname + tmp_ext)
+ img_node['candidates'] = {
+ '*': path.join(self.builder.imgpath, fname + tmp_ext)}
+
+ literal_block.replace_self(img_node)
+ convert_image(img_node, self, tmp_fname)
+
+
+class kernel_render(nodes.General, nodes.Inline, nodes.Element):
+ """Node for ``kernel-render`` directive."""
+ pass
+
+class KernelRender(Figure):
+ u"""KernelRender directive
+
+ Render content by external tool. Has all the options known from the
+ *figure* directive, plus option ``caption``. If ``caption`` has a
+ value, a figure node with the *caption* is inserted. If not, a image node is
+ inserted.
+
+ The KernelRender directive wraps the text of the directive into a
+ literal_block node and wraps it into a kernel_render node. See
+ ``visit_kernel_render``.
+ """
+ has_content = True
+ required_arguments = 1
+ optional_arguments = 0
+ final_argument_whitespace = False
+
+ # earn options from 'figure'
+ option_spec = Figure.option_spec.copy()
+ option_spec['caption'] = directives.unchanged
+
+ def run(self):
+ return [self.build_node()]
+
+ def build_node(self):
+
+ srclang = self.arguments[0].strip()
+ if srclang not in RENDER_MARKUP_EXT.keys():
+ return [self.state_machine.reporter.warning(
+ 'Unknown source language "%s", use one of: %s.' % (
+ srclang, ",".join(RENDER_MARKUP_EXT.keys())),
+ line=self.lineno)]
+
+ code = '\n'.join(self.content)
+ if not code.strip():
+ return [self.state_machine.reporter.warning(
+ 'Ignoring "%s" directive without content.' % (
+ self.name),
+ line=self.lineno)]
+
+ node = kernel_render()
+ node['alt'] = self.options.get('alt','')
+ node['srclang'] = srclang
+ literal_node = nodes.literal_block(code, code)
+ node += literal_node
+
+ caption = self.options.get('caption')
+ if caption:
+ # parse caption's content
+ parsed = nodes.Element()
+ self.state.nested_parse(
+ ViewList([caption], source=''), self.content_offset, parsed)
+ caption_node = nodes.caption(
+ parsed[0].rawsource, '', *parsed[0].children)
+ caption_node.source = parsed[0].source
+ caption_node.line = parsed[0].line
+
+ figure_node = nodes.figure('', node)
+ for k,v in self.options.items():
+ figure_node[k] = v
+ figure_node += caption_node
+
+ node = figure_node
+
+ return node
+
+def add_kernel_figure_to_std_domain(app, doctree):
+ """Add kernel-figure anchors to 'std' domain.
+
+ The ``StandardDomain.process_doc(..)`` method does not know how to resolve
+ the caption (label) of ``kernel-figure`` directive (it only knows about
+ standard nodes, e.g. table, figure etc.). Without any additional handling
+ this will result in a 'undefined label' for kernel-figures.
+
+ This handle adds labels of kernel-figure to the 'std' domain labels.
+ """
+
+ std = app.env.domains["std"]
+ docname = app.env.docname
+ labels = std.data["labels"]
+
+ for name, explicit in iteritems(doctree.nametypes):
+ if not explicit:
+ continue
+ labelid = doctree.nameids[name]
+ if labelid is None:
+ continue
+ node = doctree.ids[labelid]
+
+ if node.tagname == 'kernel_figure':
+ for n in node.next_node():
+ if n.tagname == 'caption':
+ sectname = clean_astext(n)
+ # add label to std domain
+ labels[name] = docname, labelid, sectname
+ break
diff --git a/Documentation/sphinx/load_config.py b/Documentation/sphinx/load_config.py
new file mode 100644
index 0000000..301a21a
--- /dev/null
+++ b/Documentation/sphinx/load_config.py
@@ -0,0 +1,32 @@
+# -*- coding: utf-8; mode: python -*-
+# pylint: disable=R0903, C0330, R0914, R0912, E0401
+
+import os
+import sys
+from sphinx.util.pycompat import execfile_
+
+# ------------------------------------------------------------------------------
+def loadConfig(namespace):
+# ------------------------------------------------------------------------------
+
+ u"""Load an additional configuration file into *namespace*.
+
+ The name of the configuration file is taken from the environment
+ ``SPHINX_CONF``. The external configuration file extends (or overwrites) the
+ configuration values from the origin ``conf.py``. With this you are able to
+ maintain *build themes*. """
+
+ config_file = os.environ.get("SPHINX_CONF", None)
+ if (config_file is not None
+ and os.path.normpath(namespace["__file__"]) != os.path.normpath(config_file) ):
+ config_file = os.path.abspath(config_file)
+
+ if os.path.isfile(config_file):
+ sys.stdout.write("load additional sphinx-config: %s\n" % config_file)
+ config = namespace.copy()
+ config['__file__'] = config_file
+ execfile_(config_file, config)
+ del config['__file__']
+ namespace.update(config)
+ else:
+ sys.stderr.write("WARNING: additional sphinx-config not found: %s\n" % config_file)
diff --git a/Documentation/sphinx/parse-headers.pl b/Documentation/sphinx/parse-headers.pl
new file mode 100755
index 0000000..d410f47
--- /dev/null
+++ b/Documentation/sphinx/parse-headers.pl
@@ -0,0 +1,401 @@
+#!/usr/bin/perl
+use strict;
+use Text::Tabs;
+use Getopt::Long;
+use Pod::Usage;
+
+my $debug;
+my $help;
+my $man;
+
+GetOptions(
+ "debug" => \$debug,
+ 'usage|?' => \$help,
+ 'help' => \$man
+) or pod2usage(2);
+
+pod2usage(1) if $help;
+pod2usage(-exitstatus => 0, -verbose => 2) if $man;
+pod2usage(2) if (scalar @ARGV < 2 || scalar @ARGV > 3);
+
+my ($file_in, $file_out, $file_exceptions) = @ARGV;
+
+my $data;
+my %ioctls;
+my %defines;
+my %typedefs;
+my %enums;
+my %enum_symbols;
+my %structs;
+
+require Data::Dumper if ($debug);
+
+#
+# read the file and get identifiers
+#
+
+my $is_enum = 0;
+my $is_comment = 0;
+open IN, $file_in or die "Can't open $file_in";
+while (<IN>) {
+ $data .= $_;
+
+ my $ln = $_;
+ if (!$is_comment) {
+ $ln =~ s,/\*.*(\*/),,g;
+
+ $is_comment = 1 if ($ln =~ s,/\*.*,,);
+ } else {
+ if ($ln =~ s,^(.*\*/),,) {
+ $is_comment = 0;
+ } else {
+ next;
+ }
+ }
+
+ if ($is_enum && $ln =~ m/^\s*([_\w][\w\d_]+)\s*[\,=]?/) {
+ my $s = $1;
+ my $n = $1;
+ $n =~ tr/A-Z/a-z/;
+ $n =~ tr/_/-/;
+
+ $enum_symbols{$s} = "\\ :ref:`$s <$n>`\\ ";
+
+ $is_enum = 0 if ($is_enum && m/\}/);
+ next;
+ }
+ $is_enum = 0 if ($is_enum && m/\}/);
+
+ if ($ln =~ m/^\s*#\s*define\s+([_\w][\w\d_]+)\s+_IO/) {
+ my $s = $1;
+ my $n = $1;
+ $n =~ tr/A-Z/a-z/;
+
+ $ioctls{$s} = "\\ :ref:`$s <$n>`\\ ";
+ next;
+ }
+
+ if ($ln =~ m/^\s*#\s*define\s+([_\w][\w\d_]+)\s+/) {
+ my $s = $1;
+ my $n = $1;
+ $n =~ tr/A-Z/a-z/;
+ $n =~ tr/_/-/;
+
+ $defines{$s} = "\\ :ref:`$s <$n>`\\ ";
+ next;
+ }
+
+ if ($ln =~ m/^\s*typedef\s+([_\w][\w\d_]+)\s+(.*)\s+([_\w][\w\d_]+);/) {
+ my $s = $2;
+ my $n = $3;
+
+ $typedefs{$n} = "\\ :c:type:`$n <$s>`\\ ";
+ next;
+ }
+ if ($ln =~ m/^\s*enum\s+([_\w][\w\d_]+)\s+\{/
+ || $ln =~ m/^\s*enum\s+([_\w][\w\d_]+)$/
+ || $ln =~ m/^\s*typedef\s*enum\s+([_\w][\w\d_]+)\s+\{/
+ || $ln =~ m/^\s*typedef\s*enum\s+([_\w][\w\d_]+)$/) {
+ my $s = $1;
+
+ $enums{$s} = "enum :c:type:`$s`\\ ";
+
+ $is_enum = $1;
+ next;
+ }
+ if ($ln =~ m/^\s*struct\s+([_\w][\w\d_]+)\s+\{/
+ || $ln =~ m/^\s*struct\s+([[_\w][\w\d_]+)$/
+ || $ln =~ m/^\s*typedef\s*struct\s+([_\w][\w\d_]+)\s+\{/
+ || $ln =~ m/^\s*typedef\s*struct\s+([[_\w][\w\d_]+)$/
+ ) {
+ my $s = $1;
+
+ $structs{$s} = "struct :c:type:`$s`\\ ";
+ next;
+ }
+}
+close IN;
+
+#
+# Handle multi-line typedefs
+#
+
+my @matches = ($data =~ m/typedef\s+struct\s+\S+?\s*\{[^\}]+\}\s*(\S+)\s*\;/g,
+ $data =~ m/typedef\s+enum\s+\S+?\s*\{[^\}]+\}\s*(\S+)\s*\;/g,);
+foreach my $m (@matches) {
+ my $s = $m;
+
+ $typedefs{$s} = "\\ :c:type:`$s`\\ ";
+ next;
+}
+
+#
+# Handle exceptions, if any
+#
+
+my %def_reftype = (
+ "ioctl" => ":ref",
+ "define" => ":ref",
+ "symbol" => ":ref",
+ "typedef" => ":c:type",
+ "enum" => ":c:type",
+ "struct" => ":c:type",
+);
+
+if ($file_exceptions) {
+ open IN, $file_exceptions or die "Can't read $file_exceptions";
+ while (<IN>) {
+ next if (m/^\s*$/ || m/^\s*#/);
+
+ # Parsers to ignore a symbol
+
+ if (m/^ignore\s+ioctl\s+(\S+)/) {
+ delete $ioctls{$1} if (exists($ioctls{$1}));
+ next;
+ }
+ if (m/^ignore\s+define\s+(\S+)/) {
+ delete $defines{$1} if (exists($defines{$1}));
+ next;
+ }
+ if (m/^ignore\s+typedef\s+(\S+)/) {
+ delete $typedefs{$1} if (exists($typedefs{$1}));
+ next;
+ }
+ if (m/^ignore\s+enum\s+(\S+)/) {
+ delete $enums{$1} if (exists($enums{$1}));
+ next;
+ }
+ if (m/^ignore\s+struct\s+(\S+)/) {
+ delete $structs{$1} if (exists($structs{$1}));
+ next;
+ }
+ if (m/^ignore\s+symbol\s+(\S+)/) {
+ delete $enum_symbols{$1} if (exists($enum_symbols{$1}));
+ next;
+ }
+
+ # Parsers to replace a symbol
+ my ($type, $old, $new, $reftype);
+
+ if (m/^replace\s+(\S+)\s+(\S+)\s+(\S+)/) {
+ $type = $1;
+ $old = $2;
+ $new = $3;
+ } else {
+ die "Can't parse $file_exceptions: $_";
+ }
+
+ if ($new =~ m/^\:c\:(data|func|macro|type)\:\`(.+)\`/) {
+ $reftype = ":c:$1";
+ $new = $2;
+ } elsif ($new =~ m/\:ref\:\`(.+)\`/) {
+ $reftype = ":ref";
+ $new = $1;
+ } else {
+ $reftype = $def_reftype{$type};
+ }
+ $new = "$reftype:`$old <$new>`";
+
+ if ($type eq "ioctl") {
+ $ioctls{$old} = $new if (exists($ioctls{$old}));
+ next;
+ }
+ if ($type eq "define") {
+ $defines{$old} = $new if (exists($defines{$old}));
+ next;
+ }
+ if ($type eq "symbol") {
+ $enum_symbols{$old} = $new if (exists($enum_symbols{$old}));
+ next;
+ }
+ if ($type eq "typedef") {
+ $typedefs{$old} = $new if (exists($typedefs{$old}));
+ next;
+ }
+ if ($type eq "enum") {
+ $enums{$old} = $new if (exists($enums{$old}));
+ next;
+ }
+ if ($type eq "struct") {
+ $structs{$old} = $new if (exists($structs{$old}));
+ next;
+ }
+
+ die "Can't parse $file_exceptions: $_";
+ }
+}
+
+if ($debug) {
+ print Data::Dumper->Dump([\%ioctls], [qw(*ioctls)]) if (%ioctls);
+ print Data::Dumper->Dump([\%typedefs], [qw(*typedefs)]) if (%typedefs);
+ print Data::Dumper->Dump([\%enums], [qw(*enums)]) if (%enums);
+ print Data::Dumper->Dump([\%structs], [qw(*structs)]) if (%structs);
+ print Data::Dumper->Dump([\%defines], [qw(*defines)]) if (%defines);
+ print Data::Dumper->Dump([\%enum_symbols], [qw(*enum_symbols)]) if (%enum_symbols);
+}
+
+#
+# Align block
+#
+$data = expand($data);
+$data = " " . $data;
+$data =~ s/\n/\n /g;
+$data =~ s/\n\s+$/\n/g;
+$data =~ s/\n\s+\n/\n\n/g;
+
+#
+# Add escape codes for special characters
+#
+$data =~ s,([\_\`\*\<\>\&\\\\:\/\|\%\$\#\{\}\~\^]),\\$1,g;
+
+$data =~ s,DEPRECATED,**DEPRECATED**,g;
+
+#
+# Add references
+#
+
+my $start_delim = "[ \n\t\(\=\*\@]";
+my $end_delim = "(\\s|,|\\\\=|\\\\:|\\;|\\\)|\\}|\\{)";
+
+foreach my $r (keys %ioctls) {
+ my $s = $ioctls{$r};
+
+ $r =~ s,([\_\`\*\<\>\&\\\\:\/]),\\\\$1,g;
+
+ print "$r -> $s\n" if ($debug);
+
+ $data =~ s/($start_delim)($r)$end_delim/$1$s$3/g;
+}
+
+foreach my $r (keys %defines) {
+ my $s = $defines{$r};
+
+ $r =~ s,([\_\`\*\<\>\&\\\\:\/]),\\\\$1,g;
+
+ print "$r -> $s\n" if ($debug);
+
+ $data =~ s/($start_delim)($r)$end_delim/$1$s$3/g;
+}
+
+foreach my $r (keys %enum_symbols) {
+ my $s = $enum_symbols{$r};
+
+ $r =~ s,([\_\`\*\<\>\&\\\\:\/]),\\\\$1,g;
+
+ print "$r -> $s\n" if ($debug);
+
+ $data =~ s/($start_delim)($r)$end_delim/$1$s$3/g;
+}
+
+foreach my $r (keys %enums) {
+ my $s = $enums{$r};
+
+ $r =~ s,([\_\`\*\<\>\&\\\\:\/]),\\\\$1,g;
+
+ print "$r -> $s\n" if ($debug);
+
+ $data =~ s/enum\s+($r)$end_delim/$s$2/g;
+}
+
+foreach my $r (keys %structs) {
+ my $s = $structs{$r};
+
+ $r =~ s,([\_\`\*\<\>\&\\\\:\/]),\\\\$1,g;
+
+ print "$r -> $s\n" if ($debug);
+
+ $data =~ s/struct\s+($r)$end_delim/$s$2/g;
+}
+
+foreach my $r (keys %typedefs) {
+ my $s = $typedefs{$r};
+
+ $r =~ s,([\_\`\*\<\>\&\\\\:\/]),\\\\$1,g;
+
+ print "$r -> $s\n" if ($debug);
+ $data =~ s/($start_delim)($r)$end_delim/$1$s$3/g;
+}
+
+$data =~ s/\\ ([\n\s])/\1/g;
+
+#
+# Generate output file
+#
+
+my $title = $file_in;
+$title =~ s,.*/,,;
+
+open OUT, "> $file_out" or die "Can't open $file_out";
+print OUT ".. -*- coding: utf-8; mode: rst -*-\n\n";
+print OUT "$title\n";
+print OUT "=" x length($title);
+print OUT "\n\n.. parsed-literal::\n\n";
+print OUT $data;
+close OUT;
+
+__END__
+
+=head1 NAME
+
+parse_headers.pl - parse a C file, in order to identify functions, structs,
+enums and defines and create cross-references to a Sphinx book.
+
+=head1 SYNOPSIS
+
+B<parse_headers.pl> [<options>] <C_FILE> <OUT_FILE> [<EXCEPTIONS_FILE>]
+
+Where <options> can be: --debug, --help or --man.
+
+=head1 OPTIONS
+
+=over 8
+
+=item B<--debug>
+
+Put the script in verbose mode, useful for debugging.
+
+=item B<--usage>
+
+Prints a brief help message and exits.
+
+=item B<--help>
+
+Prints a more detailed help message and exits.
+
+=back
+
+=head1 DESCRIPTION
+
+Convert a C header or source file (C_FILE), into a ReStructured Text
+included via ..parsed-literal block with cross-references for the
+documentation files that describe the API. It accepts an optional
+EXCEPTIONS_FILE with describes what elements will be either ignored or
+be pointed to a non-default reference.
+
+The output is written at the (OUT_FILE).
+
+It is capable of identifying defines, functions, structs, typedefs,
+enums and enum symbols and create cross-references for all of them.
+It is also capable of distinguish #define used for specifying a Linux
+ioctl.
+
+The EXCEPTIONS_FILE contain two rules to allow ignoring a symbol or
+to replace the default references by a custom one.
+
+Please read Documentation/doc-guide/parse-headers.rst at the Kernel's
+tree for more details.
+
+=head1 BUGS
+
+Report bugs to Mauro Carvalho Chehab <mchehab@kernel.org>
+
+=head1 COPYRIGHT
+
+Copyright (c) 2016 by Mauro Carvalho Chehab <mchehab+samsung@kernel.org>.
+
+License GPLv2: GNU GPL version 2 <http://gnu.org/licenses/gpl.html>.
+
+This is free software: you are free to change and redistribute it.
+There is NO WARRANTY, to the extent permitted by law.
+
+=cut
diff --git a/Documentation/sphinx/requirements.txt b/Documentation/sphinx/requirements.txt
new file mode 100644
index 0000000..742be3e
--- /dev/null
+++ b/Documentation/sphinx/requirements.txt
@@ -0,0 +1,3 @@
+docutils==0.12
+Sphinx==1.4.9
+sphinx_rtd_theme
diff --git a/Documentation/sphinx/rstFlatTable.py b/Documentation/sphinx/rstFlatTable.py
new file mode 100755
index 0000000..25feb0d
--- /dev/null
+++ b/Documentation/sphinx/rstFlatTable.py
@@ -0,0 +1,376 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8; mode: python -*-
+# pylint: disable=C0330, R0903, R0912
+
+u"""
+ flat-table
+ ~~~~~~~~~~
+
+ Implementation of the ``flat-table`` reST-directive.
+
+ :copyright: Copyright (C) 2016 Markus Heiser
+ :license: GPL Version 2, June 1991 see linux/COPYING for details.
+
+ The ``flat-table`` (:py:class:`FlatTable`) is a double-stage list similar to
+ the ``list-table`` with some additional features:
+
+ * *column-span*: with the role ``cspan`` a cell can be extended through
+ additional columns
+
+ * *row-span*: with the role ``rspan`` a cell can be extended through
+ additional rows
+
+ * *auto span* rightmost cell of a table row over the missing cells on the
+ right side of that table-row. With Option ``:fill-cells:`` this behavior
+ can changed from *auto span* to *auto fill*, which automaticly inserts
+ (empty) cells instead of spanning the last cell.
+
+ Options:
+
+ * header-rows: [int] count of header rows
+ * stub-columns: [int] count of stub columns
+ * widths: [[int] [int] ... ] widths of columns
+ * fill-cells: instead of autospann missing cells, insert missing cells
+
+ roles:
+
+ * cspan: [int] additionale columns (*morecols*)
+ * rspan: [int] additionale rows (*morerows*)
+"""
+
+# ==============================================================================
+# imports
+# ==============================================================================
+
+import sys
+
+from docutils import nodes
+from docutils.parsers.rst import directives, roles
+from docutils.parsers.rst.directives.tables import Table
+from docutils.utils import SystemMessagePropagation
+
+# ==============================================================================
+# common globals
+# ==============================================================================
+
+# The version numbering follows numbering of the specification
+# (Documentation/books/kernel-doc-HOWTO).
+__version__ = '1.0'
+
+PY3 = sys.version_info[0] == 3
+PY2 = sys.version_info[0] == 2
+
+if PY3:
+ # pylint: disable=C0103, W0622
+ unicode = str
+ basestring = str
+
+# ==============================================================================
+def setup(app):
+# ==============================================================================
+
+ app.add_directive("flat-table", FlatTable)
+ roles.register_local_role('cspan', c_span)
+ roles.register_local_role('rspan', r_span)
+
+ return dict(
+ version = __version__,
+ parallel_read_safe = True,
+ parallel_write_safe = True
+ )
+
+# ==============================================================================
+def c_span(name, rawtext, text, lineno, inliner, options=None, content=None):
+# ==============================================================================
+ # pylint: disable=W0613
+
+ options = options if options is not None else {}
+ content = content if content is not None else []
+ nodelist = [colSpan(span=int(text))]
+ msglist = []
+ return nodelist, msglist
+
+# ==============================================================================
+def r_span(name, rawtext, text, lineno, inliner, options=None, content=None):
+# ==============================================================================
+ # pylint: disable=W0613
+
+ options = options if options is not None else {}
+ content = content if content is not None else []
+ nodelist = [rowSpan(span=int(text))]
+ msglist = []
+ return nodelist, msglist
+
+
+# ==============================================================================
+class rowSpan(nodes.General, nodes.Element): pass # pylint: disable=C0103,C0321
+class colSpan(nodes.General, nodes.Element): pass # pylint: disable=C0103,C0321
+# ==============================================================================
+
+# ==============================================================================
+class FlatTable(Table):
+# ==============================================================================
+
+ u"""FlatTable (``flat-table``) directive"""
+
+ option_spec = {
+ 'name': directives.unchanged
+ , 'class': directives.class_option
+ , 'header-rows': directives.nonnegative_int
+ , 'stub-columns': directives.nonnegative_int
+ , 'widths': directives.positive_int_list
+ , 'fill-cells' : directives.flag }
+
+ def run(self):
+
+ if not self.content:
+ error = self.state_machine.reporter.error(
+ 'The "%s" directive is empty; content required.' % self.name,
+ nodes.literal_block(self.block_text, self.block_text),
+ line=self.lineno)
+ return [error]
+
+ title, messages = self.make_title()
+ node = nodes.Element() # anonymous container for parsing
+ self.state.nested_parse(self.content, self.content_offset, node)
+
+ tableBuilder = ListTableBuilder(self)
+ tableBuilder.parseFlatTableNode(node)
+ tableNode = tableBuilder.buildTableNode()
+ # SDK.CONSOLE() # print --> tableNode.asdom().toprettyxml()
+ if title:
+ tableNode.insert(0, title)
+ return [tableNode] + messages
+
+
+# ==============================================================================
+class ListTableBuilder(object):
+# ==============================================================================
+
+ u"""Builds a table from a double-stage list"""
+
+ def __init__(self, directive):
+ self.directive = directive
+ self.rows = []
+ self.max_cols = 0
+
+ def buildTableNode(self):
+
+ colwidths = self.directive.get_column_widths(self.max_cols)
+ if isinstance(colwidths, tuple):
+ # Since docutils 0.13, get_column_widths returns a (widths,
+ # colwidths) tuple, where widths is a string (i.e. 'auto').
+ # See https://sourceforge.net/p/docutils/patches/120/.
+ colwidths = colwidths[1]
+ stub_columns = self.directive.options.get('stub-columns', 0)
+ header_rows = self.directive.options.get('header-rows', 0)
+
+ table = nodes.table()
+ tgroup = nodes.tgroup(cols=len(colwidths))
+ table += tgroup
+
+
+ for colwidth in colwidths:
+ colspec = nodes.colspec(colwidth=colwidth)
+ # FIXME: It seems, that the stub method only works well in the
+ # absence of rowspan (observed by the html buidler, the docutils-xml
+ # build seems OK). This is not extraordinary, because there exists
+ # no table directive (except *this* flat-table) which allows to
+ # define coexistent of rowspan and stubs (there was no use-case
+ # before flat-table). This should be reviewed (later).
+ if stub_columns:
+ colspec.attributes['stub'] = 1
+ stub_columns -= 1
+ tgroup += colspec
+ stub_columns = self.directive.options.get('stub-columns', 0)
+
+ if header_rows:
+ thead = nodes.thead()
+ tgroup += thead
+ for row in self.rows[:header_rows]:
+ thead += self.buildTableRowNode(row)
+
+ tbody = nodes.tbody()
+ tgroup += tbody
+
+ for row in self.rows[header_rows:]:
+ tbody += self.buildTableRowNode(row)
+ return table
+
+ def buildTableRowNode(self, row_data, classes=None):
+ classes = [] if classes is None else classes
+ row = nodes.row()
+ for cell in row_data:
+ if cell is None:
+ continue
+ cspan, rspan, cellElements = cell
+
+ attributes = {"classes" : classes}
+ if rspan:
+ attributes['morerows'] = rspan
+ if cspan:
+ attributes['morecols'] = cspan
+ entry = nodes.entry(**attributes)
+ entry.extend(cellElements)
+ row += entry
+ return row
+
+ def raiseError(self, msg):
+ error = self.directive.state_machine.reporter.error(
+ msg
+ , nodes.literal_block(self.directive.block_text
+ , self.directive.block_text)
+ , line = self.directive.lineno )
+ raise SystemMessagePropagation(error)
+
+ def parseFlatTableNode(self, node):
+ u"""parses the node from a :py:class:`FlatTable` directive's body"""
+
+ if len(node) != 1 or not isinstance(node[0], nodes.bullet_list):
+ self.raiseError(
+ 'Error parsing content block for the "%s" directive: '
+ 'exactly one bullet list expected.' % self.directive.name )
+
+ for rowNum, rowItem in enumerate(node[0]):
+ row = self.parseRowItem(rowItem, rowNum)
+ self.rows.append(row)
+ self.roundOffTableDefinition()
+
+ def roundOffTableDefinition(self):
+ u"""Round off the table definition.
+
+ This method rounds off the table definition in :py:member:`rows`.
+
+ * This method inserts the needed ``None`` values for the missing cells
+ arising from spanning cells over rows and/or columns.
+
+ * recount the :py:member:`max_cols`
+
+ * Autospan or fill (option ``fill-cells``) missing cells on the right
+ side of the table-row
+ """
+
+ y = 0
+ while y < len(self.rows):
+ x = 0
+
+ while x < len(self.rows[y]):
+ cell = self.rows[y][x]
+ if cell is None:
+ x += 1
+ continue
+ cspan, rspan = cell[:2]
+ # handle colspan in current row
+ for c in range(cspan):
+ try:
+ self.rows[y].insert(x+c+1, None)
+ except: # pylint: disable=W0702
+ # the user sets ambiguous rowspans
+ pass # SDK.CONSOLE()
+ # handle colspan in spanned rows
+ for r in range(rspan):
+ for c in range(cspan + 1):
+ try:
+ self.rows[y+r+1].insert(x+c, None)
+ except: # pylint: disable=W0702
+ # the user sets ambiguous rowspans
+ pass # SDK.CONSOLE()
+ x += 1
+ y += 1
+
+ # Insert the missing cells on the right side. For this, first
+ # re-calculate the max columns.
+
+ for row in self.rows:
+ if self.max_cols < len(row):
+ self.max_cols = len(row)
+
+ # fill with empty cells or cellspan?
+
+ fill_cells = False
+ if 'fill-cells' in self.directive.options:
+ fill_cells = True
+
+ for row in self.rows:
+ x = self.max_cols - len(row)
+ if x and not fill_cells:
+ if row[-1] is None:
+ row.append( ( x - 1, 0, []) )
+ else:
+ cspan, rspan, content = row[-1]
+ row[-1] = (cspan + x, rspan, content)
+ elif x and fill_cells:
+ for i in range(x):
+ row.append( (0, 0, nodes.comment()) )
+
+ def pprint(self):
+ # for debugging
+ retVal = "[ "
+ for row in self.rows:
+ retVal += "[ "
+ for col in row:
+ if col is None:
+ retVal += ('%r' % col)
+ retVal += "\n , "
+ else:
+ content = col[2][0].astext()
+ if len (content) > 30:
+ content = content[:30] + "..."
+ retVal += ('(cspan=%s, rspan=%s, %r)'
+ % (col[0], col[1], content))
+ retVal += "]\n , "
+ retVal = retVal[:-2]
+ retVal += "]\n , "
+ retVal = retVal[:-2]
+ return retVal + "]"
+
+ def parseRowItem(self, rowItem, rowNum):
+ row = []
+ childNo = 0
+ error = False
+ cell = None
+ target = None
+
+ for child in rowItem:
+ if (isinstance(child , nodes.comment)
+ or isinstance(child, nodes.system_message)):
+ pass
+ elif isinstance(child , nodes.target):
+ target = child
+ elif isinstance(child, nodes.bullet_list):
+ childNo += 1
+ cell = child
+ else:
+ error = True
+ break
+
+ if childNo != 1 or error:
+ self.raiseError(
+ 'Error parsing content block for the "%s" directive: '
+ 'two-level bullet list expected, but row %s does not '
+ 'contain a second-level bullet list.'
+ % (self.directive.name, rowNum + 1))
+
+ for cellItem in cell:
+ cspan, rspan, cellElements = self.parseCellItem(cellItem)
+ if target is not None:
+ cellElements.insert(0, target)
+ row.append( (cspan, rspan, cellElements) )
+ return row
+
+ def parseCellItem(self, cellItem):
+ # search and remove cspan, rspan colspec from the first element in
+ # this listItem (field).
+ cspan = rspan = 0
+ if not len(cellItem):
+ return cspan, rspan, []
+ for elem in cellItem[0]:
+ if isinstance(elem, colSpan):
+ cspan = elem.get("span")
+ elem.parent.remove(elem)
+ continue
+ if isinstance(elem, rowSpan):
+ rspan = elem.get("span")
+ elem.parent.remove(elem)
+ continue
+ return cspan, rspan, cellItem[:]
diff --git a/Kbuild b/Kbuild
index ef97787..e2e3b29 100644
--- a/Kbuild
+++ b/Kbuild
@@ -4,39 +4,47 @@
# 1) Generate generic-asm-offsets.h
# 2) Generate asm-offsets.h
+# Default sed regexp - multiline due to syntax constraints
+define sed-y
+ "s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \
+ /^->/{s:->#\(.*\):/* \1 */:; \
+ s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
+ s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+ s:->::; p;}"
+endef
+
+# Use filechk to avoid rebuilds when a header changes, but the resulting file
+# does not
+define filechk_offsets
+ (set -e; \
+ echo "#ifndef $2"; \
+ echo "#define $2"; \
+ echo "/*"; \
+ echo " * DO NOT MODIFY."; \
+ echo " *"; \
+ echo " * This file was generated by Kbuild"; \
+ echo " */"; \
+ echo ""; \
+ sed -ne $(sed-y); \
+ echo ""; \
+ echo "#endif" )
+endef
+
#####
# 1) Generate generic-asm-offsets.h
generic-offsets-file := include/generated/generic-asm-offsets.h
always := $(generic-offsets-file)
-targets := $(generic-offsets-file) lib/asm-offsets.s
-
-quiet_cmd_generic-offsets = GEN $@
-define cmd_generic-offsets
- (set -e; \
- echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \
- echo "#define __GENERIC_ASM_OFFSETS_H__"; \
- echo "/*"; \
- echo " * DO NOT MODIFY."; \
- echo " *"; \
- echo " * This file was generated by Kbuild"; \
- echo " *"; \
- echo " */"; \
- echo ""; \
- sed -ne $(sed-y) $<; \
- echo ""; \
- echo "#endif" ) > $@
-endef
+targets := lib/asm-offsets.s
# We use internal kbuild rules to avoid the "is up to date" message from make
lib/asm-offsets.s: lib/asm-offsets.c FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cc_s_c)
-$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild
- $(Q)mkdir -p $(dir $@)
- $(call cmd,generic-offsets)
+$(obj)/$(generic-offsets-file): lib/asm-offsets.s FORCE
+ $(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
#####
# 2) Generate asm-offsets.h
@@ -47,42 +55,14 @@
endif
always += $(offsets-file)
-targets += $(offsets-file)
targets += arch/$(ARCH)/lib/asm-offsets.s
-
-# Default sed regexp - multiline due to syntax constraints
-define sed-y
- "s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \
- /^->/{s:->#\(.*\):/* \1 */:; \
- s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
- s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
- s:->::; p;}"
-endef
-
CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
-quiet_cmd_offsets = GEN $@
-define cmd_offsets
- (set -e; \
- echo "#ifndef __ASM_OFFSETS_H__"; \
- echo "#define __ASM_OFFSETS_H__"; \
- echo "/*"; \
- echo " * DO NOT MODIFY."; \
- echo " *"; \
- echo " * This file was generated by Kbuild"; \
- echo " *"; \
- echo " */"; \
- echo ""; \
- sed -ne $(sed-y) $<; \
- echo ""; \
- echo "#endif" ) > $@
-endef
-
# We use internal kbuild rules to avoid the "is up to date" message from make
arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cc_s_c)
-$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild
- $(call cmd,offsets)
+$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s FORCE
+ $(call filechk,offsets,__ASM_OFFSETS_H__)
diff --git a/Kconfig b/Kconfig
index 60cf1dd..e332245 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1,6 +1,7 @@
#
# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
+# see the file Documentation/kbuild/kconfig-language.txt in the
+# Linux kernel source tree.
#
mainmenu "U-Boot $UBOOTVERSION Configuration"
@@ -8,18 +9,22 @@
string
option env="UBOOTVERSION"
-config KCONFIG_OBJDIR
- string
- option env="KCONFIG_OBJDIR"
+# Allow defaults in arch-specific code to override any given here
+source "arch/Kconfig"
menu "General setup"
+config BROKEN
+ bool
+ help
+ This option cannot be enabled. It is used as dependency
+ for broken and incomplete features.
+
config LOCALVERSION
string "Local version - append to U-Boot release"
- depends on !SPL_BUILD
help
Append an extra string to the end of your U-Boot version.
- This will show up on your boot log, for example.
+ This will show up in your boot log, for example.
The string you set here will be appended after the contents of
any files with a filename matching localversion* in your
object and source tree, in that order. Your total string can
@@ -27,15 +32,14 @@
config LOCALVERSION_AUTO
bool "Automatically append version information to the version string"
- depends on !SPL_BUILD
default y
help
This will try to automatically determine if the current tree is a
- release tree by looking for git tags that belong to the current
+ release tree by looking for Git tags that belong to the current
top of tree revision.
A string of the format -gxxxxxxxx will be added to the localversion
- if a git-based tree is found. The string generated by this will be
+ if a Git-based tree is found. The string generated by this will be
appended after any matching localversion* files, and after the value
set in CONFIG_LOCALVERSION.
@@ -48,7 +52,6 @@
config CC_OPTIMIZE_FOR_SIZE
bool "Optimize for size"
- depends on !SPL_BUILD
default y
help
Enabling this option will pass "-Os" instead of "-O2" to gcc
@@ -56,76 +59,427 @@
This option is enabled by default for U-Boot.
+config CC_COVERAGE
+ bool "Enable code coverage analysis"
+ depends on SANDBOX
+ help
+ Enabling this option will pass "--coverage" to gcc to compile
+ and link code instrumented for coverage analysis.
+
+config DISTRO_DEFAULTS
+ bool "Select defaults suitable for booting general purpose Linux distributions"
+ select AUTO_COMPLETE
+ select CMDLINE_EDITING
+ select CMD_BOOTI if ARM64 && !AML_DISABLE_DEV_CMDS
+ select CMD_BOOTZ if ARM && !ARM64 && !AML_DISABLE_DEV_CMDS
+ select CMD_DHCP if CMD_NET
+ select CMD_ENV_EXISTS
+ select CMD_EXT2
+ select CMD_EXT4
+ select CMD_FAT
+ select CMD_FS_GENERIC
+ select CMD_PART if PARTITIONS
+ select CMD_PING if CMD_NET
+ select CMD_PXE if NET
+ select ENV_VARS_UBOOT_CONFIG
+ select HUSH_PARSER
+ select SUPPORT_RAW_INITRD
+ select SYS_LONGHELP
+ imply CMD_MII if NET
+ imply USB_STORAGE
+ imply USE_BOOTCOMMAND
+ help
+ Select this to enable various options and commands which are suitable
+ for building u-boot for booting general purpose Linux distributions.
+
+config ENV_VARS_UBOOT_CONFIG
+ bool "Add arch, board, vendor and soc variables to default environment"
+ help
+ Define this in order to add variables describing the
+ U-Boot build configuration to the default environment.
+ These will be named arch, cpu, board, vendor, and soc.
+ Enabling this option will cause the following to be defined:
+ - CONFIG_SYS_ARCH
+ - CONFIG_SYS_CPU
+ - CONFIG_SYS_BOARD
+ - CONFIG_SYS_VENDOR
+ - CONFIG_SYS_SOC
+
+config NR_DRAM_BANKS
+ int "Number of DRAM banks"
+ default 4
+ help
+ This defines the number of DRAM banks.
+
+config SYS_BOOT_GET_CMDLINE
+ bool "Enable kernel command line setup"
+ help
+ Enables allocating and saving kernel cmdline in space between
+ "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+config SYS_BOOT_GET_KBD
+ bool "Enable kernel board information setup"
+ help
+ Enables allocating and saving a kernel copy of the bd_info in
+ space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+config SYS_MALLOC_F
+ bool "Enable malloc() pool before relocation"
+ default y if DM
+
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
+config SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool before relocation"
+ depends on SYS_MALLOC_F
+ default 0x1000 if AM33XX
+ default 0x2800 if SANDBOX
+ default 0x400
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
+config SYS_MALLOC_LEN
+ hex "Define memory for Dynamic allocation"
+ depends on ARCH_ZYNQ || ARCH_VERSAL
+ help
+ This defines memory to be allocated for Dynamic allocation
+ TODO: Use for other architectures
+
+config SPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in SPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
+config TPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in TPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
menuconfig EXPERT
- bool "Configure standard U-Boot features (expert users)"
- help
- This option allows certain base U-Boot options and settings
- to be disabled or tweaked. This is for specialized
- environments which can tolerate a "non-standard" U-Boot.
- Only use this if you really know what you are doing.
+ bool "Configure standard U-Boot features (expert users)"
+ default y
+ help
+ This option allows certain base U-Boot options and settings
+ to be disabled or tweaked. This is for specialized
+ environments which can tolerate a "non-standard" U-Boot.
+ Use this only if you really know what you are doing.
+
+if EXPERT
+ config SYS_MALLOC_CLEAR_ON_INIT
+ bool "Init with zeros the memory reserved for malloc (slow)"
+ default y
+ help
+ This setting is enabled by default. The reserved malloc
+ memory is initialized with zeros, so first malloc calls
+ will return the pointer to the zeroed memory. But this
+ slows the boot time.
+
+ It is recommended to disable it, when CONFIG_SYS_MALLOC_LEN
+ value, has more than few MiB, e.g. when uses bzip2 or bmp logo.
+ Then the boot time can be significantly reduced.
+ Warning:
+ When disabling this, please check if malloc calls, maybe
+ should be replaced by calloc - if one expects zeroed memory.
+
+config TOOLS_DEBUG
+ bool "Enable debug information for tools"
+ help
+ Enable generation of debug information for tools such as mkimage.
+ This can be used for debugging purposes. With debug information
+ it is possible to set breakpoints on particular lines, single-step
+ debug through the source code, etc.
+
+endif # EXPERT
+
+config PHYS_64BIT
+ bool "64bit physical address support"
+ help
+ Say Y here to support 64bit physical memory address.
+ This can be used not only for 64bit SoCs, but also for
+ large physical address extention on 32bit SoCs.
+
+config BUILD_ROM
+ bool "Build U-Boot as BIOS replacement"
+ depends on X86
+ help
+ This option allows to build a ROM version of U-Boot.
+ The build process generally requires several binary blobs
+ which are not shipped in the U-Boot source tree.
+ Please, see doc/README.x86 for details.
endmenu # General setup
menu "Boot images"
-config SPL_BUILD
- bool
- depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
- default y
-
-config TPL_BUILD
- bool
- depends on $KCONFIG_OBJDIR="tpl"
- default y
-
-config SUPPORT_SPL
- bool
-
-config SUPPORT_TPL
- bool
-
-config SPL
- bool
- depends on SUPPORT_SPL
- prompt "Enable SPL" if !SPL_BUILD
- default y if SPL_BUILD
+config ANDROID_BOOT_IMAGE
+ bool "Enable support for Android Boot Images"
+ default y if FASTBOOT
help
- If you want to build SPL as well as the normal image, say Y.
-
-config TPL
- bool
- depends on SPL && SUPPORT_TPL
- prompt "Enable TPL" if !SPL_BUILD
- default y if TPL_BUILD
- default n
- help
- If you want to build TPL as well as the normal image and SPL, say Y.
+ This enables support for booting images which use the Android
+ image format header.
config FIT
bool "Support Flattened Image Tree"
- depends on !SPL_BUILD
+ select MD5
+ select SHA1
help
- This option allows to boot the new uImage structrure,
+ This option allows you to boot the new uImage structure,
Flattened Image Tree. FIT is formally a FDT, which can include
images of various types (kernel, FDT blob, ramdisk, etc.)
in a single blob. To boot this new uImage structure,
- pass the the address of the blob to the "bootm" command.
+ pass the address of the blob to the "bootm" command.
+ FIT is very flexible, supporting compression, multiple images,
+ multiple configurations, verification through hashing and also
+ verified boot (secure boot using RSA).
-config FIT_VERBOSE
- bool "Display verbose messages on FIT boot"
- depends on FIT
+if FIT
+
+config FIT_EXTERNAL_OFFSET
+ hex "Text Base"
+ default 0x0
+ help
+ This specifies a data offset in fit image.
+ The offset is from data payload offset to the beginning of
+ fit image header. When specifies a offset, specific data
+ could be put in the hole between data payload and fit image
+ header, such as CSF data on i.MX platform.
+
+config FIT_ENABLE_SHA256_SUPPORT
+ bool "Support SHA256 checksum of FIT image contents"
+ default y
+ select SHA256
+ help
+ Enable this to support SHA256 checksum of FIT image contents. A
+ SHA256 checksum is a 256-bit (32-byte) hash value used to check that
+ the image contents have not been corrupted. SHA256 is recommended
+ for use in secure applications since (as at 2016) there is no known
+ feasible attack that could produce a 'collision' with differing
+ input data. Use this for the highest security. Note that only the
+ SHA256 variant is supported: SHA512 and others are not currently
+ supported in U-Boot.
+
+config FIT_FULL_CHECK
+ bool "Do a full check of the FIT before using it"
+ default y
+ help
+ Enable this do a full check of the FIT to make sure it is valid. This
+ helps to protect against carefully crafted FITs which take advantage
+ of bugs or omissions in the code. This includes a bad structure,
+ multiple root nodes and the like.
config FIT_SIGNATURE
- bool "Enabel signature verification of FIT uImages"
- depends on FIT
+ bool "Enable signature verification of FIT uImages"
+ depends on DM
+ select HASH
+ select FIT_FULL_CHECK
+ select RSA
help
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA.
- See doc/uImage.FIT/signature.txt for more details.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, then the RSA library will use
+ it. See doc/uImage.FIT/signature.txt for more details.
+
+ WARNING: When relying on signed FIT images with a required signature
+ check the legacy image format is disabled by default, so that
+ unsigned images cannot be loaded. If a board needs the legacy image
+ format support in this case, enable it using
+ CONFIG_IMAGE_FORMAT_LEGACY.
+
+config FIT_SIGNATURE_MAX_SIZE
+ hex "Max size of signed FIT structures"
+ depends on FIT_SIGNATURE
+ default 0x10000000
+ help
+ This option sets a max size in bytes for verified FIT uImages.
+ A sane value of 256MB protects corrupted DTB structures from overlapping
+ device memory. Assure this size does not extend past expected storage
+ space.
+
+config FIT_ENABLE_RSASSA_PSS_SUPPORT
+ bool "Support rsassa-pss signature scheme of FIT image contents"
+ depends on FIT_SIGNATURE
+ default n
+ help
+ Enable this to support the pss padding algorithm as described
+ in the rfc8017 (https://tools.ietf.org/html/rfc8017).
+
+config FIT_VERBOSE
+ bool "Show verbose messages when FIT images fail"
+ help
+ Generally a system will have valid FIT images so debug messages
+ are a waste of code space. If you are debugging your images then
+ you can enable this option to get more verbose information about
+ failures.
+
+config FIT_BEST_MATCH
+ bool "Select the best match for the kernel device tree"
+ help
+ When no configuration is explicitly selected, default to the
+ one whose fdt's compatibility field best matches that of
+ U-Boot itself. A match is considered "best" if it matches the
+ most specific compatibility entry of U-Boot's fdt's root node.
+ The order of entries in the configuration's fdt is ignored.
+
+config FIT_IMAGE_POST_PROCESS
+ bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+ depends on TI_SECURE_DEVICE
+ help
+ Allows doing any sort of manipulation to blobs after they got extracted
+ from FIT images like stripping off headers or modifying the size of the
+ blob, verification, authentication, decryption etc. in a platform or
+ board specific way. In order to use this feature a platform or board-
+ specific implementation of board_fit_image_post_process() must be
+ provided. Also, anything done during this post-processing step would
+ need to be comprehended in how the images were prepared before being
+ injected into the FIT creation (i.e. the blobs would have been pre-
+ processed before being added to the FIT image).
+
+if SPL
+
+config SPL_FIT
+ bool "Support Flattened Image Tree within SPL"
+ depends on SPL
+ select SPL_OF_LIBFDT
+
+config SPL_FIT_PRINT
+ bool "Support FIT printing within SPL"
+ depends on SPL_FIT
+ help
+ Support printing the content of the fitImage in a verbose manner in SPL.
+
+config SPL_FIT_FULL_CHECK
+ bool "Do a full check of the FIT before using it"
+ help
+ Enable this do a full check of the FIT to make sure it is valid. This
+ helps to protect against carefully crafted FITs which take advantage
+ of bugs or omissions in the code. This includes a bad structure,
+ multiple root nodes and the like.
+
+
+config SPL_FIT_SIGNATURE
+ bool "Enable signature verification of FIT firmware within SPL"
+ depends on SPL_DM
+ select SPL_FIT
+ select SPL_RSA
+ select SPL_FIT_FULL_CHECK
+
+config SPL_LOAD_FIT
+ bool "Enable SPL loading U-Boot as a FIT"
+ select SPL_FIT
+ help
+ Normally with the SPL framework a legacy image is generated as part
+ of the build. This contains U-Boot along with information as to
+ where it should be loaded. This option instead enables generation
+ of a FIT (Flat Image Tree) which provides more flexibility. In
+ particular it can handle selecting from multiple device tree
+ and passing the correct one to U-Boot.
+
+config SPL_LOAD_FIT_FULL
+ bool "Enable SPL loading U-Boot as a FIT"
+ select SPL_FIT
+ help
+ Normally with the SPL framework a legacy image is generated as part
+ of the build. This contains U-Boot along with information as to
+ where it should be loaded. This option instead enables generation
+ of a FIT (Flat Image Tree) which provides more flexibility. In
+ particular it can handle selecting from multiple device tree
+ and passing the correct one to U-Boot.
+
+config SPL_FIT_IMAGE_POST_PROCESS
+ bool "Enable post-processing of FIT artifacts after loading by the SPL"
+ depends on SPL_LOAD_FIT
+ help
+ Allows doing any sort of manipulation to blobs after they got extracted
+ from the U-Boot FIT image like stripping off headers or modifying the
+ size of the blob, verification, authentication, decryption etc. in a
+ platform or board specific way. In order to use this feature a platform
+ or board-specific implementation of board_fit_image_post_process() must
+ be provided. Also, anything done during this post-processing step would
+ need to be comprehended in how the images were prepared before being
+ injected into the FIT creation (i.e. the blobs would have been pre-
+ processed before being added to the FIT image).
+
+config SPL_FIT_SOURCE
+ string ".its source file for U-Boot FIT image"
+ depends on SPL_FIT
+ help
+ Specifies a (platform specific) FIT source file to generate the
+ U-Boot FIT image. This could specify further image to load and/or
+ execute.
+
+config SPL_FIT_GENERATOR
+ string ".its file generator script for U-Boot FIT image"
+ depends on SPL_FIT
+ default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
+ help
+ Specifies a (platform specific) script file to generate the FIT
+ source file used to build the U-Boot FIT image file. This gets
+ passed a list of supported device tree file stub names to
+ include in the generated image.
+
+endif # SPL
+
+endif # FIT
+
+config IMAGE_FORMAT_LEGACY
+ bool "Enable support for the legacy image format"
+ default y if !FIT_SIGNATURE
+ help
+ This option enables the legacy image format. It is enabled by
+ default for backward compatibility, unless FIT_SIGNATURE is
+ set where it is disabled so that unsigned images cannot be
+ loaded. If a board needs the legacy image format support in this
+ case, enable it here.
+
+config OF_BOARD_SETUP
+ bool "Set up board-specific details in device tree before boot"
+ depends on OF_LIBFDT
+ help
+ This causes U-Boot to call ft_board_setup() before booting into
+ the Operating System. This function can set up various
+ board-specific information in the device tree for use by the OS.
+ The device tree is then passed to the OS.
+
+config OF_SYSTEM_SETUP
+ bool "Set up system-specific details in device tree before boot"
+ depends on OF_LIBFDT
+ help
+ This causes U-Boot to call ft_system_setup() before booting into
+ the Operating System. This function can set up various
+ system-specific information in the device tree for use by the OS.
+ The device tree is then passed to the OS.
+
+config OF_STDOUT_VIA_ALIAS
+ bool "Update the device-tree stdout alias from U-Boot"
+ depends on OF_LIBFDT
+ help
+ This uses U-Boot's serial alias from the aliases node to update
+ the device tree passed to the OS. The "linux,stdout-path" property
+ in the chosen node is set to point to the correct serial node.
+ This option currently references CONFIG_CONS_INDEX, which is
+ incorrect when used with device tree as this option does not
+ exist / should not be used.
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
- depends on !SPL_BUILD
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. If you have something like
@@ -138,19 +492,46 @@
new boards should not use this option.
config SYS_TEXT_BASE
- depends on SPARC
+ depends on !NIOS2 && !XTENSA
+ depends on !EFI_APP
+ default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
+ default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
+ default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
+ default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
hex "Text Base"
help
- TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+ The address in memory that U-Boot will be running from, initially.
+
+
+
+config SYS_CLK_FREQ
+ depends on ARC || ARCH_SUNXI
+ int "CPU clock frequency"
+ help
+ TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
+
+config ARCH_FIXUP_FDT_MEMORY
+ bool "Enable arch_fixup_memory_banks() call"
+ default y
+ help
+ Enable FDT memory map syncup before OS boot. This feature can be
+ used for booting OS with different memory setup where the part of
+ the memory location should be used for different purpose.
endmenu # Boot images
-source "arch/Kconfig"
+source "api/Kconfig"
source "common/Kconfig"
+source "cmd/Kconfig"
+
+source "disk/Kconfig"
+
source "dts/Kconfig"
+source "env/Kconfig"
+
source "net/Kconfig"
source "drivers/Kconfig"
@@ -158,3 +539,5 @@
source "fs/Kconfig"
source "lib/Kconfig"
+
+source "test/Kconfig"
diff --git a/Licenses/OFL.txt b/Licenses/OFL.txt
new file mode 100644
index 0000000..07c881f
--- /dev/null
+++ b/Licenses/OFL.txt
@@ -0,0 +1,97 @@
+Copyright (c) 2010, Andrey Makarov (makarov@bmstu.ru, mka-at-mailru@mail.ru),
+with Reserved Font Name Anka/Coder Narrow.
+
+Copyright (c) 2011, Pablo Impallari (www.impallari.com|impallari@gmail.com),
+Rodrigo Fuenzalida (www.rfuenzalida.com) with Reserved Font Name Cantora.
+
+This Font Software is licensed under the SIL Open Font License, Version 1.1.
+This license is copied below, and is also available with a FAQ at:
+http://scripts.sil.org/OFL
+
+
+-----------------------------------------------------------
+SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007
+-----------------------------------------------------------
+
+PREAMBLE
+The goals of the Open Font License (OFL) are to stimulate worldwide
+development of collaborative font projects, to support the font creation
+efforts of academic and linguistic communities, and to provide a free and
+open framework in which fonts may be shared and improved in partnership
+with others.
+
+The OFL allows the licensed fonts to be used, studied, modified and
+redistributed freely as long as they are not sold by themselves. The
+fonts, including any derivative works, can be bundled, embedded,
+redistributed and/or sold with any software provided that any reserved
+names are not used by derivative works. The fonts and derivatives,
+however, cannot be released under any other type of license. The
+requirement for fonts to remain under this license does not apply
+to any document created using the fonts or their derivatives.
+
+DEFINITIONS
+"Font Software" refers to the set of files released by the Copyright
+Holder(s) under this license and clearly marked as such. This may
+include source files, build scripts and documentation.
+
+"Reserved Font Name" refers to any names specified as such after the
+copyright statement(s).
+
+"Original Version" refers to the collection of Font Software components as
+distributed by the Copyright Holder(s).
+
+"Modified Version" refers to any derivative made by adding to, deleting,
+or substituting -- in part or in whole -- any of the components of the
+Original Version, by changing formats or by porting the Font Software to a
+new environment.
+
+"Author" refers to any designer, engineer, programmer, technical
+writer or other person who contributed to the Font Software.
+
+PERMISSION & CONDITIONS
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of the Font Software, to use, study, copy, merge, embed, modify,
+redistribute, and sell modified and unmodified copies of the Font
+Software, subject to the following conditions:
+
+1) Neither the Font Software nor any of its individual components,
+in Original or Modified Versions, may be sold by itself.
+
+2) Original or Modified Versions of the Font Software may be bundled,
+redistributed and/or sold with any software, provided that each copy
+contains the above copyright notice and this license. These can be
+included either as stand-alone text files, human-readable headers or
+in the appropriate machine-readable metadata fields within text or
+binary files as long as those fields can be easily viewed by the user.
+
+3) No Modified Version of the Font Software may use the Reserved Font
+Name(s) unless explicit written permission is granted by the corresponding
+Copyright Holder. This restriction only applies to the primary font name as
+presented to the users.
+
+4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font
+Software shall not be used to promote, endorse or advertise any
+Modified Version, except to acknowledge the contribution(s) of the
+Copyright Holder(s) and the Author(s) or with their explicit written
+permission.
+
+5) The Font Software, modified or unmodified, in part or in whole,
+must be distributed entirely under this license, and must not be
+distributed under any other license. The requirement for fonts to
+remain under this license does not apply to any document created
+using the Font Software.
+
+TERMINATION
+This license becomes null and void if any of the above conditions are
+not met.
+
+DISCLAIMER
+THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT
+OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM
+OTHER DEALINGS IN THE FONT SOFTWARE.
diff --git a/Licenses/README b/Licenses/README
index fe6dadc..486e18d 100644
--- a/Licenses/README
+++ b/Licenses/README
@@ -1,3 +1,5 @@
+SPDX-License-Identifier: GPL-2.0
+
U-Boot is Free Software. It is copyrighted by Wolfgang Denk and
many others who contributed code (see the actual source code and the
git commit messages for details). You can redistribute U-Boot and/or
@@ -31,27 +33,107 @@
To make this easier, such license headers in the source files will be
replaced with a single line reference to Unique License Identifiers
-as defined by the Linux Foundation's SPDX project [1]. For example,
-in a source file the full "GPL v2.0 or later" header text will be
-replaced by a single line:
-
- SPDX-License-Identifier: GPL-2.0+
-
-Ideally, the license terms of all files in the source tree should be
-defined by such License Identifiers; in no case a file can contain
-more than one such License Identifier list.
+as defined by the Linux Foundation's SPDX project [1].
If a "SPDX-License-Identifier:" line references more than one Unique
License Identifier, then this means that the respective file can be
used under the terms of either of these licenses, i. e. with
- SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-you can chose between GPL-2.0+ and BSD-3-Clause licensing.
+you can choose between GPL-2.0+ and BSD-3-Clause licensing.
We use the SPDX Unique License Identifiers here; these are available
at [2].
+License identifier syntax
+-------------------------
+
+1. Placement:
+
+ The SPDX license identifier in U-Boot files shall be added at the first
+ possible line in a file which can contain a comment. For the majority
+ or files this is the first line, except for scripts which require the
+ '#!PATH_TO_INTERPRETER' in the first line. For those scripts the SPDX
+ identifier goes into the second line.
+
+|
+
+2. Style:
+
+ The SPDX license identifier is added in form of a comment. The comment
+ style depends on the file type::
+
+ C source: // SPDX-License-Identifier: <SPDX License Expression>
+ C header: /* SPDX-License-Identifier: <SPDX License Expression> */
+ ASM: /* SPDX-License-Identifier: <SPDX License Expression> */
+ scripts: # SPDX-License-Identifier: <SPDX License Expression>
+ .rst: .. SPDX-License-Identifier: <SPDX License Expression>
+ .dts{i}: // SPDX-License-Identifier: <SPDX License Expression>
+
+ If a specific tool cannot handle the standard comment style, then the
+ appropriate comment mechanism which the tool accepts shall be used. This
+ is the reason for having the "/\* \*/" style comment in C header
+ files. There was build breakage observed with generated .lds files where
+ 'ld' failed to parse the C++ comment. This has been fixed by now, but
+ there are still older assembler tools which cannot handle C++ style
+ comments.
+
+|
+
+3. Syntax:
+
+ A <SPDX License Expression> is either an SPDX short form license
+ identifier found on the SPDX License List, or the combination of two
+ SPDX short form license identifiers separated by "WITH" when a license
+ exception applies. When multiple licenses apply, an expression consists
+ of keywords "AND", "OR" separating sub-expressions and surrounded by
+ "(", ")" .
+
+ License identifiers for licenses like [L]GPL with the 'or later' option
+ are constructed by using a "+" for indicating the 'or later' option.::
+
+ // SPDX-License-Identifier: GPL-2.0+
+ // SPDX-License-Identifier: LGPL-2.1+
+
+ WITH should be used when there is a modifier to a license needed.
+ For example, the linux kernel UAPI files use the expression::
+
+ // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
+ // SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note
+
+ Other examples using WITH exceptions found in the linux kernel are::
+
+ // SPDX-License-Identifier: GPL-2.0 WITH mif-exception
+ // SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
+
+ Exceptions can only be used with particular License identifiers. The
+ valid License identifiers are listed in the tags of the exception text
+ file.
+
+ OR should be used if the file is dual licensed and only one license is
+ to be selected. For example, some dtsi files are available under dual
+ licenses::
+
+ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+
+ Examples from U-Boot for license expressions in dual licensed files::
+
+ // SPDX-License-Identifier: GPL-2.0 OR MIT
+ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+
+ AND should be used if the file has multiple licenses whose terms all
+ apply to use the file. For example, if code is inherited from another
+ project and permission has been given to put it in U-Boot, but the
+ original license terms need to remain in effect::
+
+ // SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) AND MIT
+
+ Another other example where both sets of license terms need to be
+ adhered to is::
+
+ // SPDX-License-Identifier: GPL-1.0+ AND LGPL-2.1+
+
[1] http://spdx.org/
[2] http://spdx.org/licenses/
@@ -67,3 +149,5 @@
IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt
Boot Software) license
ISC License ISC Y isc.txt https://spdx.org/licenses/ISC
+SIL OPEN FONT LICENSE (OFL-1.1) OFL-1.1 Y OFL.txt https://spdx.org/licenses/OFL-1.1.html
+X11 License X11 x11.txt https://spdx.org/licenses/X11.html
diff --git a/Licenses/r8a779x_usb3.txt b/Licenses/r8a779x_usb3.txt
new file mode 100644
index 0000000..e2afcc9
--- /dev/null
+++ b/Licenses/r8a779x_usb3.txt
@@ -0,0 +1,26 @@
+Copyright (c) 2014, Renesas Electronics Corporation
+All rights reserved.
+
+Redistribution and use in binary form, without modification, are permitted
+provided that the following conditions are met:
+
+1. Redistribution in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+2. The name of Renesas Electronics Corporation may not be used to endorse or
+ promote products derived from this software without specific prior written
+ permission.
+3. Reverse engineering, decompilation, or disassembly of this software is
+ not permitted.
+
+THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS ELECTRONICS CORPORATION DISCLAIMS
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND
+NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT SHALL RENESAS ELECTRONICS
+CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Licenses/x11.txt b/Licenses/x11.txt
new file mode 100644
index 0000000..23a3c63
--- /dev/null
+++ b/Licenses/x11.txt
@@ -0,0 +1,25 @@
+X11 License
+Copyright (C) 1996 X Consortium
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE X
+CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+Except as contained in this notice, the name of the X Consortium shall not be
+used in advertising or otherwise to promote the sale, use or other dealings in
+this Software without prior written authorization from the X Consortium.
+
+X Window System is a trademark of X Consortium, Inc.
diff --git a/MAINTAINERS b/MAINTAINERS
index 57d2cfd..f86fdf9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2,6 +2,8 @@
P: Person (obsolete)
M: Mail patches to: FullName <address@domain>
+ R: Designated reviewer: FullName <address@domain>
+ These reviewers should be CCed on patches.
L: Mailing list that is relevant to this area
W: Web-page with status/info
Q: Patchwork web based patch tracking system site
@@ -55,9 +57,27 @@
-----------------------------------
ARC
M: Alexey Brodkin <alexey.brodkin@synopsys.com>
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Maintained
+L: uboot-snps-arc@synopsys.com
T: git git://git.denx.de/u-boot-arc.git
F: arch/arc/
+F: board/synopsys/
+
+ARC HSDK CGU CLOCK
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+L: uboot-snps-arc@synopsys.com
+F: drivers/clk/clk-hsdk-cgu.c
+F: include/dt-bindings/clock/snps,hsdk-cgu.h
+F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
+
+ARC HSDK CREG GPIO
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+L: uboot-snps-arc@synopsys.com
+F: doc/device-tree-bindings/gpio/snps,creg-gpio.txt
+F: drivers/gpio/hsdk-creg-gpio.c
ARM
M: Albert Aribaud <albert.u.boot@aribaud.net>
@@ -69,39 +89,69 @@
M: Marek Vasut <marex@denx.de>
S: Maintainted
T: git git://git.denx.de/u-boot-socfpga.git
-F: arch/arm/cpu/armv7/socfpga/
-F: board/altera/socfpga/
+F: arch/arm/mach-socfpga/
ARM ATMEL AT91
-M: Andreas Bießmann <andreas.devel@googlemail.com>
+M: Andreas Bießmann <andreas@biessmann.org>
S: Maintained
T: git git://git.denx.de/u-boot-atmel.git
-F: arch/arm/cpu/armv7/at91/
-F: arch/arm/cpu/at91-common/
-F: arch/arm/include/asm/arch-at91/
+F: arch/arm/mach-at91/
+
+ARM BROADCOM BCM283X
+M: Alexander Graf <agraf@suse.de>
+S: Maintained
+F: arch/arm/mach-bcm283x/
+F: drivers/gpio/bcm2835_gpio.c
+F: drivers/mmc/bcm2835_sdhci.c
+F: drivers/mmc/bcm2835_sdhost.c
+F: drivers/serial/serial_bcm283x_mu.c
+F: drivers/serial/serial_bcm283x_pl011.c
+F: drivers/video/bcm2835.c
+F: include/dm/platform_data/serial_bcm283x_mu.h
+F: drivers/pinctrl/broadcom/
+
+ARM BROADCOM BCMSTB
+M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
+S: Maintained
+F: arch/arm/mach-bcmstb/
+F: board/broadcom/bcmstb/
+F: configs/bcm7*_defconfig
+F: doc/README.bcm7xxx
+F: drivers/mmc/bcmstb_sdhci.c
+F: drivers/spi/bcmstb_spi.c
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
+M: Fabio Estevam <fabio.estevam@nxp.com>
+R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
-F: arch/arm/cpu/arm926ejs/imx/
-F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
-F: arch/arm/cpu/imx-common/
+F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
-F: arch/arm/include/asm/imx-common/
+F: arch/arm/include/asm/mach-imx/
+F: board/freescale/*mx*/
-ARM MARVELL KIRKWOOD
+ARM HISILICON
+M: Peter Griffin <peter.griffin@linaro.org>
+S: Maintained
+F: arch/arm/cpu/armv8/hisilicon
+F: arch/arm/include/asm/arch-hi6220/
+
+ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX
M: Prafulla Wadaskar <prafulla@marvell.com>
M: Luka Perkov <luka.perkov@sartura.hr>
+M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
-F: arch/arm/cpu/arm926ejs/kirkwood/
-F: arch/arm/include/asm/arch-kirkwood/
+F: arch/arm/mach-kirkwood/
+F: arch/arm/mach-mvebu/
+F: drivers/ata/ahci_mvebu.c
+F: drivers/phy/marvell/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
@@ -110,25 +160,116 @@
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
+ARM MEDIATEK
+M: Ryder Lee <ryder.lee@mediatek.com>
+M: Weijie Gao <weijie.gao@mediatek.com>
+S: Maintained
+F: arch/arm/mach-mediatek/
+F: arch/arm/include/asm/arch-mediatek/
+F: board/mediatek/
+F: doc/README.mediatek
+F: drivers/clk/mediatek/
+F: drivers/mmc/mtk-sd.c
+F: drivers/pinctrl/mediatek/
+F: drivers/power/domain/mtk-power-domain.c
+F: drivers/ram/mediatek/
+F: drivers/spi/mtk_qspi.c
+F: drivers/timer/mtk_timer.c
+F: drivers/watchdog/mtk_wdt.c
+F: tools/mtk_image.c
+F: tools/mtk_image.h
+N: mediatek
+
+ARM OWL
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: arch/arm/include/asm/arch-owl/
+F: arch/arm/mach-owl/
+F: board/ucRobotics/
+F: drivers/clk/owl/
+F: drivers/serial/serial_owl.c
+
+ARM RENESAS RMOBILE/R-CAR
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-sh.git
+F: arch/arm/mach-rmobile/
+
+ARM ROCKCHIP
+M: Simon Glass <sjg@chromium.org>
+M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-rockchip.git
+F: arch/arm/include/asm/arch-rockchip/
+F: arch/arm/mach-rockchip/
+F: board/rockchip/
+F: drivers/clk/rockchip/
+F: drivers/gpio/rk_gpio.c
+F: drivers/misc/rockchip-efuse.c
+F: drivers/mmc/rockchip_sdhci.c
+F: drivers/mmc/rockchip_dw_mmc.c
+F: drivers/pinctrl/rockchip/
+F: drivers/ram/rockchip/
+F: drivers/sysreset/sysreset_rockchip.c
+F: drivers/video/rockchip/
+F: tools/rkcommon.c
+F: tools/rkcommon.h
+F: tools/rkimage.c
+F: tools/rksd.c
+F: tools/rkspi.c
+
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
-F: arch/arm/cpu/arm920t/s3c24x0/
-F: arch/arm/cpu/armv7/exynos/
-F: arch/arm/cpu/armv7/s5pc1xx/
+F: arch/arm/mach-exynos/
+F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
-F: arch/arm/include/asm/arch-exynos/
-F: arch/arm/include/asm/arch-s3c24x0/
-F: arch/arm/include/asm/arch-s5pc1xx/
+
+ARM SNAPDRAGON
+M: Ramon Fried <ramon.fried@gmail.com>
+S: Maintained
+F: arch/arm/mach-snapdragon/
+F: drivers/gpio/msm_gpio.c
+F: drivers/mmc/msm_sdhci.c
+F: drivers/phy/msm8916-usbh-phy.c
+F: drivers/serial/serial_msm.c
+F: drivers/smem/msm_smem.c
+F: drivers/usb/host/ehci-msm.c
+
+ARM STI
+M: Patrice Chotard <patrice.chotard@st.com>
+S: Maintained
+F: arch/arm/mach-sti/
+F: arch/arm/include/asm/arch-sti*/
ARM STM SPEAR
-M: Vipin Kumar <vipin.kumar@st.com>
-S: Maintained
+#M: Vipin Kumar <vipin.kumar@st.com>
+S: Orphaned (Since 2016-02)
T: git git://git.denx.de/u-boot-stm.git
F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
+ARM STM STM32MP
+M: Patrick Delaunay <patrick.delaunay@st.com>
+M: Christophe Kerello <christophe.kerello@st.com>
+M: Patrice Chotard <patrice.chotard@st.com>
+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/mach-stm32mp
+F: drivers/clk/clk_stm32mp1.c
+F: drivers/i2c/stm32f7_i2c.c
+F: drivers/misc/stm32mp_fuse.c
+F: drivers/mmc/stm32_sdmmc2.c
+F: drivers/phy/phy-stm32-usbphyc.c
+F: drivers/pinctrl/pinctrl_stm32.c
+F: drivers/power/regulator/stm32-vrefbuf.c
+F: drivers/ram/stm32mp1/
+F: drivers/misc/stm32_rcc.c
+F: drivers/reset/stm32-reset.c
+F: drivers/spi/stm32_qspi.c
+
ARM STM STV0991
M: Vikas Manocha <vikas.manocha@st.com>
S: Maintained
@@ -136,59 +277,113 @@
F: arch/arm/include/asm/arch-stv0991/
ARM SUNXI
-M: Ian Campbell <ijc@hellion.org.uk>
-M: Hans De Goede <hdegoede@redhat.com>
+M: Jagan Teki <jagan@openedev.com>
+M: Maxime Ripard <maxime.ripard@bootlin.com>
S: Maintained
T: git git://git.denx.de/u-boot-sunxi.git
F: arch/arm/cpu/armv7/sunxi/
F: arch/arm/include/asm/arch-sunxi/
+F: arch/arm/mach-sunxi/
+F: board/sunxi/
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
S: Maintained
T: git git://git.denx.de/u-boot-tegra.git
-F: arch/arm/cpu/arm720t/tegra*/
-F: arch/arm/cpu/armv7/tegra*/
-F: arch/arm/cpu/tegra*/
+F: arch/arm/mach-tegra/
F: arch/arm/include/asm/arch-tegra*/
ARM TI
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git git://git.denx.de/u-boot-ti.git
-F: arch/arm/cpu/arm926ejs/davinci/
-F: arch/arm/cpu/arm926ejs/omap/
-F: arch/arm/cpu/armv7/omap*/
-F: arch/arm/include/asm/arch-davinci/
+F: arch/arm/mach-davinci/
+F: arch/arm/mach-k3/
+F: arch/arm/mach-keystone/
F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
ARM UNIPHIER
-M: Masahiro Yamada <yamada.m@jp.panasonic.com>
+M: Masahiro Yamada <yamada.masahiro@socionext.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
-F: arch/arm/cpu/armv7/uniphier/
-F: arch/arm/include/asm/arch-uniphier/
-F: configs/ph1_*_defconfig
-F: drivers/serial/serial_uniphier.c
+F: arch/arm/mach-uniphier/
+F: configs/uniphier_*_defconfig
+N: uniphier
+
+ARM VERSAL
+M: Michal Simek <michal.simek@xilinx.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/mach-versal/
+
+ARM VERSATILE EXPRESS DRIVERS
+M: Liviu Dudau <liviu.dudau@foss.arm.com>
+S: Maintained
+T: git git://github.com/ARM-software/u-boot.git
+F: drivers/misc/vexpress_config.c
+N: vexpress
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>
S: Maintained
-F: arch/arm/cpu/armv7/zynq/
-F: arch/arm/include/asm/arch-zynq/
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/mach-zynq/
+F: drivers/clk/clk_zynq.c
+F: drivers/fpga/zynqpl.c
+F: drivers/gpio/zynq_gpio.c
+F: drivers/i2c/i2c-cdns.c
+F: drivers/i2c/muxes/pca954x.c
+F: drivers/i2c/zynq_i2c.c
+F: drivers/mmc/zynq_sdhci.c
+F: drivers/mtd/nand/raw/zynq_nand.c
+F: drivers/net/phy/xilinx_phy.c
+F: drivers/net/zynq_gem.c
+F: drivers/serial/serial_zynq.c
+F: drivers/spi/zynq_qspi.c
+F: drivers/spi/zynq_spi.c
+F: drivers/usb/host/ehci-zynq.c
+F: drivers/watchdog/cdns_wdt.c
+F: include/zynqpl.h
+F: tools/zynqimage.c
+N: zynq
-AVR32
-M: Andreas Bießmann <andreas.devel@googlemail.com>
+ARM ZYNQMP
+M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git git://git.denx.de/u-boot-avr32.git
-F: arch/avr32/
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/cpu/armv8/zynqmp/
+F: drivers/clk/clk_zynqmp.c
+F: drivers/fpga/zynqpl.c
+F: drivers/gpio/zynq_gpio.c
+F: drivers/i2c/i2c-cdns.c
+F: drivers/i2c/muxes/pca954x.c
+F: drivers/i2c/zynq_i2c.c
+F: drivers/mmc/zynq_sdhci.c
+F: drivers/mtd/nand/raw/zynq_nand.c
+F: drivers/net/phy/xilinx_phy.c
+F: drivers/net/zynq_gem.c
+F: drivers/serial/serial_zynq.c
+F: drivers/spi/zynq_qspi.c
+F: drivers/spi/zynq_spi.c
+F: drivers/timer/cadence-ttc.c
+F: drivers/usb/host/ehci-zynq.c
+F: drivers/watchdog/cdns_wdt.c
+F: include/zynqmppl.h
+F: tools/zynqmp*
+N: ultra96
+N: zynqmp
-BLACKFIN
-M: Sonic Zhang <sonic.adi@gmail.com>
+ARM ZYNQMP R5
+M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git git://git.denx.de/u-boot-blackfin.git
-F: arch/blackfin/
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/mach-zynqmp-r5/
+
+BINMAN
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: tools/binman/
BUILDMAN
M: Simon Glass <sjg@chromium.org>
@@ -203,25 +398,56 @@
F: drivers/mtd/jedec_flash.c
COLDFIRE
-M: Huan Wang <alison.wang@freescale.com>
+M: Huan Wang <alison.wang@nxp.com>
M: Angelo Dureghello <angelo@sysam.it>
S: Maintained
T: git git://git.denx.de/u-boot-coldfire.git
F: arch/m68k/
DFU
-M: Lukasz Majewski <l.majewski@samsung.com>
+M: Lukasz Majewski <lukma@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
F: drivers/dfu/
+F: drivers/usb/gadget/
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
S: Maintained
+T: git git://git.denx.de/u-boot-dm.git
F: drivers/core/
F: include/dm/
F: test/dm/
+EFI PAYLOAD
+M: Alexander Graf <agraf@suse.de>
+R: Heinrich Schuchardt <xypron.glpk@gmx.de>
+S: Maintained
+T: git git://github.com/agraf/u-boot.git
+F: doc/README.uefi
+F: doc/README.iscsi
+F: Documentation/efi.rst
+F: include/capitalization.h
+F: include/cp1250.h
+F: include/cp437.h
+F: include/efi*
+F: include/pe.h
+F: include/asm-generic/pe.h
+F: lib/charset.c
+F: lib/efi*/
+F: test/py/tests/test_efi*
+F: test/unicode_ut.c
+F: cmd/bootefi.c
+F: tools/file2include.c
+
+FPGA
+M: Michal Simek <michal.simek@xilinx.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-microblaze.git
+F: drivers/fpga/
+F: cmd/fpga.c
+F: include/fpga.h
+
FLATTENED DEVICE TREE
M: Simon Glass <sjg@chromium.org>
S: Maintained
@@ -229,8 +455,8 @@
F: lib/fdtdec*
F: lib/libfdt/
F: include/fdt*
-F: include/libfdt*
-F. common/cmd_fdt.c
+F: include/linux/libfdt*
+F: cmd/fdt.c
F: common/fdt_support.c
FREEBSD
@@ -239,7 +465,7 @@
T: git git://git.denx.de/u-boot-freebsd.git
FREESCALE QORIQ
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
@@ -249,11 +475,36 @@
T: git git://git.denx.de/u-boot-i2c.git
F: drivers/i2c/
+LOGGING
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+T: git git://git.denx.de/u-boot.git
+F: common/log.c
+F: cmd/log.c
+F: test/log/log_test.c
+F: test/py/tests/test_log.py
+
+MALI DISPLAY PROCESSORS
+M: Liviu Dudau <liviu.dudau@foss.arm.com>
+S: Supported
+T: git git://github.com/ARM-software/u-boot.git
+F: drivers/video/mali_dp.c
+F: drivers/i2c/i2c-versatile.c
+
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained
T: git git://git.denx.de/u-boot-microblaze.git
F: arch/microblaze/
+F: cmd/mfsl.c
+F: drivers/gpio/xilinx_gpio.c
+F: drivers/net/xilinx_axi_emac.c
+F: drivers/net/xilinx_emaclite.c
+F: drivers/serial/serial_xuartlite.c
+F: drivers/spi/xilinx_spi.c
+F: drivers/sysreset/sysreset_gpio.c
+F: drivers/watchdog/xilinx_tb_wdt.c
+N: xilinx
MIPS
M: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
@@ -261,87 +512,35 @@
T: git git://git.denx.de/u-boot-mips.git
F: arch/mips/
+MIPS MSCC
+M: Gregory CLEMENT <gregory.clement@bootlin.com>
+M: Lars Povlsen <lars.povlsen@microchip.com>
+M: Horatiu Vultur <horatiu.vultur@microchip.com>
+S: Maintained
+F: arch/mips/mach-mscc/
+F: arch/mips/dts/luton*
+F: arch/mips/dts/mscc*
+F: arch/mips/dts/ocelot*
+F: board/mscc/
+F: configs/mscc*
+F: include/configs/vcoreiii.h
+
+MIPS JZ4780
+M: Ezequiel Garcia <ezequiel@collabora.com>
+S: Maintained
+F: arch/mips/mach-jz47xx/
+
MMC
-M: Pantelis Antoniou <panto@antoniou-consulting.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
-OPENRISC
-M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S: Maintained
-F: arch/openrisc/
-
-PATMAN
-M: Simon Glass <sjg@chromium.org>
-S: Maintained
-F: tools/patman/
-
-POWERPC
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: arch/powerpc/
-
-POWERPC MPC5XXX
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc5xxx.git
-F: arch/powerpc/cpu/mpc5*/
-
-POWERPC MPC8XX
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc8xx.git
-F: arch/powerpc/cpu/mpc8xx/
-
-POWERPC MPC82XX
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc82xx.git
-F: arch/powerpc/cpu/mpc82*/
-
-POWERPC MPC83XX
-M: Kim Phillips <kim.phillips@freescale.com>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc83xx.git
-F: arch/powerpc/cpu/mpc83xx/
-F: arch/powerpc/include/asm/arch-mpc83xx/
-
-POWERPC MPC85XX
-M: York Sun <yorksun@freescale.com>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc85xx.git
-F: arch/powerpc/cpu/mpc85xx/
-
-POWERPC MPC86XX
-M: York Sun <yorksun@freescale.com>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc86xx.git
-F: arch/powerpc/cpu/mpc86xx/
-
-POWERPC PPC74XX PPC7XX
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-74xx-7xx.git
-F: arch/powerpc/cpu/74xx_7xx/
-
-POWERPC PPC4XX
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-ppc4xx.git
-F: arch/powerpc/cpu/ppc4xx/
-
-NETWORK
-M: Joe Hershberger <joe.hershberger@gmail.com>
-S: Maintained
-T: git git://git.denx.de/u-boot-net.git
-F: drivers/net/
-
NAND FLASH
-M: Scott Wood <scottwood@freescale.com>
-S: Maintained
+#M: Scott Wood <oss@buserror.net>
+S: Orphaned (Since 2018-07)
T: git git://git.denx.de/u-boot-nand-flash.git
-F: drivers/mtd/nand/
+F: drivers/mtd/nand/raw/
NDS32
M: Macpaul Lin <macpaul@andestech.com>
@@ -349,6 +548,13 @@
T: git git://git.denx.de/u-boot-nds32.git
F: arch/nds32/
+NETWORK
+M: Joe Hershberger <joe.hershberger@ni.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-net.git
+F: drivers/net/
+F: net/
+
NIOS
M: Thomas Chou <thomas@wytron.com.tw>
S: Maintained
@@ -356,11 +562,77 @@
F: arch/nios2/
ONENAND
-M: Lukasz Majewski <l.majewski@samsung.com>
-S: Maintained
+#M: Lukasz Majewski <l.majewski@majess.pl>
+S: Orphaned (Since 2017-01)
T: git git://git.denx.de/u-boot-onenand.git
F: drivers/mtd/onenand/
+PATMAN
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: tools/patman/
+
+POWER
+M: Jaehoon Chung <jh80.chung@samsung.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-pmic.git
+F: drivers/power/
+
+POWERPC
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: arch/powerpc/
+
+POWERPC MPC8XX
+M: Christophe Leroy <christophe.leroy@c-s.fr>
+S: Maintained
+T: git git://git.denx.de/u-boot-mpc8xx.git
+F: arch/powerpc/cpu/mpc8xx/
+
+POWERPC MPC83XX
+M: Mario Six <mario.six@gdsys.cc>
+S: Maintained
+T: git git://git.denx.de/u-boot-mpc83xx.git
+F: drivers/ram/mpc83xx_sdram.c
+F: include/dt-bindings/memory/mpc83xx-sdram.h
+F: drivers/sysreset/sysreset_mpc83xx.c
+F: drivers/sysreset/sysreset_mpc83xx.h
+F: drivers/clk/mpc83xx_clk.c
+F: drivers/clk/mpc83xx_clk.h
+F: include/dt-bindings/clk/mpc83xx-clk.h
+F: drivers/timer/mpc83xx_timer.c
+F: drivers/cpu/mpc83xx_cpu.c
+F: drivers/cpu/mpc83xx_cpu.h
+F: drivers/misc/mpc83xx_serdes.c
+F: arch/powerpc/cpu/mpc83xx/
+F: arch/powerpc/include/asm/arch-mpc83xx/
+
+POWERPC MPC85XX
+M: York Sun <york.sun@nxp.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-mpc85xx.git
+F: arch/powerpc/cpu/mpc85xx/
+
+POWERPC MPC86XX
+M: York Sun <york.sun@nxp.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-mpc86xx.git
+F: arch/powerpc/cpu/mpc86xx/
+
+RISC-V
+M: Rick Chen <rick@andestech.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-riscv.git
+F: arch/riscv/
+F: tools/prelink-riscv.c
+
+ROCKUSB
+M: Eddie Cai <eddie.cai.linux@gmail.com>
+S: Maintained
+F: drivers/usb/gadget/f_rockusb.c
+F: cmd/rockusb.c
+F: doc/README.rockusb
+
SANDBOX
M: Simon Glass <sjg@chromium.org>
S: Maintained
@@ -372,30 +644,53 @@
T: git git://git.denx.de/u-boot-sh.git
F: arch/sh/
-SPARC
-M: Daniel Hellstrom <daniel@gaisler.com>
-S: Maintained
-T: git git://git.denx.de/u-boot-sparc.git
-F: arch/sparc/
-
SPI
-M: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+M: Jagan Teki <jagan@openedev.com>
S: Maintained
T: git git://git.denx.de/u-boot-spi.git
F: drivers/mtd/spi/
F: drivers/spi/
F: include/spi*
-TESTING
-M: Detlev Zundel <dzu@denx.de>
+SPMI
+M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
S: Maintained
-T: git git://git.denx.de/u-boot-testing.git
+F: drivers/spmi/
+F: include/spmi/
+
+TDA19988 HDMI ENCODER
+M: Liviu Dudau <liviu.dudau@foss.arm.com>
+S: Maintained
+F: drivers/video/tda19988.c
+
+TI SYSTEM SECURITY
+M: Andrew F. Davis <afd@ti.com>
+S: Supported
+F: arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+F: arch/arm/mach-omap2/sec-common.c
+F: arch/arm/mach-omap2/config_secure.mk
+F: configs/am335x_hs_evm_defconfig
+F: configs/am335x_hs_evm_uart_defconfig
+F: configs/am43xx_hs_evm_defconfig
+F: configs/am57xx_hs_evm_defconfig
+F: configs/dra7xx_hs_evm_defconfig
+F: configs/k2hk_hs_evm_defconfig
+F: configs/k2e_hs_evm_defconfig
+F: configs/k2g_hs_evm_defconfig
+F: configs/k2l_hs_evm_defconfig
TQ GROUP
-M: Martin Krause <martin.krause@tq-systems.de>
-S: Maintained
+#M: Martin Krause <martin.krause@tq-systems.de>
+S: Orphaned (Since 2016-02)
T: git git://git.denx.de/u-boot-tq-group.git
+TEE
+M: Jens Wiklander <jens.wiklander@linaro.org>
+S: Maintained
+F: drivers/tee/
+F: include/tee.h
+F: include/tee/
+
UBI
M: Kyungmin Park <kmpark@infradead.org>
M: Heiko Schocher <hs@denx.de>
@@ -409,29 +704,39 @@
T: git git://git.denx.de/u-boot-usb.git
F: drivers/usb/
+USB xHCI
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-usb.git topic-xhci
+F: drivers/usb/host/xhci*
+
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-video.git
F: drivers/video/
+F: common/lcd*.c
+F: include/lcd*.h
+F: include/video*.h
X86
M: Simon Glass <sjg@chromium.org>
+M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
+XTENSA
+M: Max Filippov <jcmvbkbc@gmail.com>
+S: Maintained
+F: arch/xtensa/
+
THE REST
-M: Tom Rini <trini@ti.com>
+M: Tom Rini <trini@konsulko.com>
L: u-boot@lists.denx.de
Q: http://patchwork.ozlabs.org/project/uboot/list/
S: Maintained
T: git git://git.denx.de/u-boot.git
+F: configs/tools-only_defconfig
F: *
F: */
-
-LCD
-M: Shaochan Liu<shaochan.liu@amlogic.com>
-S: Maintained
-T: git /scgit.amlogic.com:29418/kernel/common.git
-F: drivers/dispaly/lcd/lcd_extern/i2c_CS602.c
diff --git a/MAKEALL b/MAKEALL
deleted file mode 100644
index 4d643d1..0000000
--- a/MAKEALL
+++ /dev/null
@@ -1,853 +0,0 @@
-#!/bin/bash
-# Tool mainly for U-Boot Quality Assurance: build one or more board
-# configurations with minimal verbosity, showing only warnings and
-# errors.
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-usage()
-{
- # if exiting with 0, write to stdout, else write to stderr
- local ret=${1:-0}
- [ "${ret}" -eq 1 ] && exec 1>&2
- cat <<-EOF
- Usage: MAKEALL [options] [--] [boards-to-build]
-
- Options:
- -a ARCH, --arch ARCH Build all boards with arch ARCH
- -c CPU, --cpu CPU Build all boards with cpu CPU
- -v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR
- -s SOC, --soc SOC Build all boards with soc SOC
- -b BOARD, --board BOARD Build all boards with board name BOARD
- -l, --list List all targets to be built
- -m, --maintainers List all targets and maintainer email
- -M, --mails List all targets and all affilated emails
- -C, --check Enable build checking
- -n, --continue Continue (skip boards already built)
- -r, --rebuild-errors Rebuild any boards that errored
- -h, --help This help output
-
- Selections by these options are logically ANDed; if the same option
- is used repeatedly, such selections are ORed. So "-v FOO -v BAR"
- will select all configurations where the vendor is either FOO or
- BAR. Any additional arguments specified on the command line are
- always build additionally. See the boards.cfg file for more info.
-
- If no boards are specified, then the default is "powerpc".
-
- Environment variables:
- BUILD_NCPUS number of parallel make jobs (default: auto)
- CROSS_COMPILE cross-compiler toolchain prefix (default: "")
- CROSS_COMPILE_<ARCH> cross-compiler toolchain prefix for
- architecture "ARCH". Substitute "ARCH" for any
- supported architecture (default: "")
- MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
- BUILD_DIR output build directory (default: ./)
- BUILD_NBUILDS number of parallel targets (default: 1)
-
- Examples:
- - build all Power Architecture boards:
- MAKEALL -a powerpc
- MAKEALL --arch powerpc
- MAKEALL powerpc
- - build all PowerPC boards manufactured by vendor "esd":
- MAKEALL -a powerpc -v esd
- - build all PowerPC boards manufactured either by "keymile" or "siemens":
- MAKEALL -a powerpc -v keymile -v siemens
- - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards:
- MAKEALL -c mpc83xx -v freescale 4xx
- EOF
- exit ${ret}
-}
-
-SHORT_OPTS="ha:c:v:s:b:lmMCnr"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors"
-
-# Option processing based on util-linux-2.13/getopt-parse.bash
-
-# Note that we use `"$@"' to let each command-line parameter expand to a
-# separate word. The quotes around `$@' are essential!
-# We need TEMP as the `eval set --' would nuke the return value of
-# getopt.
-TEMP=`getopt -o ${SHORT_OPTS} --long ${LONG_OPTS} \
- -n 'MAKEALL' -- "$@"`
-
-[ $? != 0 ] && usage 1
-
-# Note the quotes around `$TEMP': they are essential!
-eval set -- "$TEMP"
-
-SELECTED=''
-ONLY_LIST=''
-PRINT_MAINTS=''
-MAINTAINERS_ONLY=''
-CONTINUE=''
-REBUILD_ERRORS=''
-
-while true ; do
- case "$1" in
- -a|--arch)
- # echo "Option ARCH: argument \`$2'"
- if [ "$opt_a" ] ; then
- opt_a="${opt_a%)} || \$2 == \"$2\")"
- else
- opt_a="(\$2 == \"$2\")"
- fi
- SELECTED='y'
- shift 2 ;;
- -c|--cpu)
- # echo "Option CPU: argument \`$2'"
- if [ "$opt_c" ] ; then
- opt_c="${opt_c%)} || \$3 == \"$2\" || \$3 ~ /$2:/)"
- else
- opt_c="(\$3 == \"$2\" || \$3 ~ /$2:/)"
- fi
- SELECTED='y'
- shift 2 ;;
- -s|--soc)
- # echo "Option SoC: argument \`$2'"
- if [ "$opt_s" ] ; then
- opt_s="${opt_s%)} || \$4 == \"$2\" || \$4 ~ /$2/)"
- else
- opt_s="(\$4 == \"$2\" || \$4 ~ /$2/)"
- fi
- SELECTED='y'
- shift 2 ;;
- -v|--vendor)
- # echo "Option VENDOR: argument \`$2'"
- if [ "$opt_v" ] ; then
- opt_v="${opt_v%)} || \$5 == \"$2\")"
- else
- opt_v="(\$5 == \"$2\")"
- fi
- SELECTED='y'
- shift 2 ;;
- -b|--board)
- # echo "Option BOARD: argument \`$2'"
- if [ "$opt_b" ] ; then
- opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")"
- else
- # We need to check the 7th field too
- # for boards whose 6th field is "-"
- opt_b="(\$6 == \"$2\" || \$7 == \"$2\")"
- fi
- SELECTED='y'
- shift 2 ;;
- -C|--check)
- CHECK='C=1'
- shift ;;
- -n|--continue)
- CONTINUE='y'
- shift ;;
- -r|--rebuild-errors)
- REBUILD_ERRORS='y'
- shift ;;
- -l|--list)
- ONLY_LIST='y'
- shift ;;
- -m|--maintainers)
- ONLY_LIST='y'
- PRINT_MAINTS='y'
- MAINTAINERS_ONLY='y'
- shift ;;
- -M|--mails)
- ONLY_LIST='y'
- PRINT_MAINTS='y'
- shift ;;
- -h|--help)
- usage ;;
- --)
- shift ; break ;;
- *)
- echo "Internal error!" >&2 ; exit 1 ;;
- esac
-done
-
-GNU_MAKE=$(scripts/show-gnu-make) || {
- echo "GNU Make not found" >&2
- exit 1
-}
-
-# echo "Remaining arguments:"
-# for arg do echo '--> '"\`$arg'" ; done
-
-tools/genboardscfg.py || {
- echo "Failed to generate boards.cfg" >&2
- exit 1
-}
-
-FILTER="\$1 !~ /^#/"
-[ "$opt_a" ] && FILTER="${FILTER} && $opt_a"
-[ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
-[ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
-[ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
-[ "$opt_b" ] && FILTER="${FILTER} && $opt_b"
-
-if [ "$SELECTED" ] ; then
- SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
-
- # Make sure some boards from boards.cfg are actually found
- if [ -z "$SELECTED" ] ; then
- echo "Error: No boards selected, invalid arguments"
- exit 1
- fi
-fi
-
-#########################################################################
-
-# Print statistics when we exit
-trap exit 1 2 3 15
-trap print_stats 0
-
-# Determine number of CPU cores if no default was set
-: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
-
-if [ "$BUILD_NCPUS" -gt 1 ]
-then
- JOBS="-j $((BUILD_NCPUS + 1))"
-else
- JOBS=""
-fi
-
-if [ "${MAKEALL_LOGDIR}" ] ; then
- LOG_DIR=${MAKEALL_LOGDIR}
-else
- LOG_DIR="LOG"
-fi
-
-: ${BUILD_NBUILDS:=1}
-BUILD_MANY=0
-
-if [ "${BUILD_NBUILDS}" -gt 1 ] ; then
- BUILD_MANY=1
- : ${BUILD_DIR:=./build}
- mkdir -p "${BUILD_DIR}/ERR"
- find "${BUILD_DIR}/ERR/" -type f -exec rm -f {} +
-fi
-
-: ${BUILD_DIR:=.}
-
-OUTPUT_PREFIX="${BUILD_DIR}"
-
-[ -d ${LOG_DIR} ] || mkdir "${LOG_DIR}" || exit 1
-if [ "$CONTINUE" != 'y' -a "$REBUILD_ERRORS" != 'y' ] ; then
- find "${LOG_DIR}/" -type f -exec rm -f {} +
-fi
-
-LIST=""
-
-# Keep track of the number of builds and errors
-ERR_CNT=0
-ERR_LIST=""
-WRN_CNT=0
-WRN_LIST=""
-TOTAL_CNT=0
-SKIP_CNT=0
-CURRENT_CNT=0
-OLDEST_IDX=1
-RC=0
-
-# Helper funcs for parsing boards.cfg
-targets_by_field()
-{
- field=$1
- regexp=$2
-
- awk '($1 !~ /^#/ && $'"$field"' ~ /^'"$regexp"'$/) { print $7 }' \
- boards.cfg
-}
-
-targets_by_arch() { targets_by_field 2 "$@" ; }
-targets_by_cpu() { targets_by_field 3 "$@" ; targets_by_field 3 "$@:.*" ; }
-targets_by_soc() { targets_by_field 4 "$@" ; }
-
-#########################################################################
-## MPC5xx Systems
-#########################################################################
-
-LIST_5xx="$(targets_by_cpu mpc5xx)"
-
-#########################################################################
-## MPC5xxx Systems
-#########################################################################
-
-LIST_5xxx="$(targets_by_cpu mpc5xxx)"
-
-#########################################################################
-## MPC512x Systems
-#########################################################################
-
-LIST_512x="$(targets_by_cpu mpc512x)"
-
-#########################################################################
-## MPC8xx Systems
-#########################################################################
-
-LIST_8xx="$(targets_by_cpu mpc8xx)"
-
-#########################################################################
-## PPC4xx Systems
-#########################################################################
-
-LIST_4xx="$(targets_by_cpu ppc4xx)"
-
-#########################################################################
-## MPC8260 Systems (includes 8250, 8255 etc.)
-#########################################################################
-
-LIST_8260="$(targets_by_cpu mpc8260)"
-
-#########################################################################
-## MPC83xx Systems (includes 8349, etc.)
-#########################################################################
-
-LIST_83xx="$(targets_by_cpu mpc83xx)"
-
-#########################################################################
-## MPC85xx Systems (includes 8540, 8560 etc.)
-#########################################################################
-
-LIST_85xx="$(targets_by_cpu mpc85xx)"
-
-#########################################################################
-## MPC86xx Systems
-#########################################################################
-
-LIST_86xx="$(targets_by_cpu mpc86xx)"
-
-#########################################################################
-## 74xx/7xx Systems
-#########################################################################
-
-LIST_74xx_7xx="$(targets_by_cpu 74xx_7xx)"
-
-#########################################################################
-## PowerPC groups
-#########################################################################
-
-LIST_TSEC=" \
- ${LIST_83xx} \
- ${LIST_85xx} \
- ${LIST_86xx} \
-"
-
-LIST_powerpc=" \
- ${LIST_5xx} \
- ${LIST_512x} \
- ${LIST_5xxx} \
- ${LIST_8xx} \
- ${LIST_824x} \
- ${LIST_8260} \
- ${LIST_83xx} \
- ${LIST_85xx} \
- ${LIST_86xx} \
- ${LIST_4xx} \
- ${LIST_74xx_7xx}\
-"
-
-# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
-# still using "ppc" instead of "powerpc"
-LIST_ppc=" \
- ${LIST_powerpc} \
-"
-
-#########################################################################
-## StrongARM Systems
-#########################################################################
-
-LIST_SA="$(targets_by_cpu sa1100)"
-
-#########################################################################
-## ARM7 Systems
-#########################################################################
-
-LIST_ARM7="$(targets_by_cpu arm720t)"
-
-#########################################################################
-## ARM9 Systems
-#########################################################################
-
-LIST_ARM9="$(targets_by_cpu arm920t) \
- $(targets_by_cpu arm926ejs) \
- $(targets_by_cpu arm946es) \
-"
-
-#########################################################################
-## ARM11 Systems
-#########################################################################
-LIST_ARM11="$(targets_by_cpu arm1136) \
- $(targets_by_cpu arm1176) \
-"
-
-#########################################################################
-## ARMV7 Systems
-#########################################################################
-
-LIST_ARMV7="$(targets_by_cpu armv7)"
-
-#########################################################################
-## ARMV8 Systems
-#########################################################################
-
-LIST_ARMV8="$(targets_by_cpu armv8)"
-
-#########################################################################
-## AT91 Systems
-#########################################################################
-
-LIST_at91="$(targets_by_soc at91)"
-
-#########################################################################
-## Xscale Systems
-#########################################################################
-
-LIST_pxa="$(targets_by_cpu pxa)"
-
-#########################################################################
-## SPEAr Systems
-#########################################################################
-
-LIST_spear="$(targets_by_soc spear)"
-
-#########################################################################
-## ARM groups
-#########################################################################
-
-LIST_arm="$(targets_by_arch arm | \
- for ARMV8_TARGET in $LIST_ARMV8; \
- do sed "/$ARMV8_TARGET/d"; \
- done) \
-"
-
-#########################################################################
-## MIPS Systems (default = big endian)
-#########################################################################
-
-LIST_mips="$(targets_by_arch mips)"
-
-#########################################################################
-## OpenRISC Systems
-#########################################################################
-
-LIST_openrisc="$(targets_by_arch openrisc)"
-
-#########################################################################
-## x86 Systems
-#########################################################################
-
-LIST_x86="$(targets_by_arch x86)"
-
-#########################################################################
-## Nios-II Systems
-#########################################################################
-
-LIST_nios2="$(targets_by_arch nios2)"
-
-#########################################################################
-## MicroBlaze Systems
-#########################################################################
-
-LIST_microblaze="$(targets_by_arch microblaze)"
-
-#########################################################################
-## ColdFire Systems
-#########################################################################
-
-LIST_m68k="$(targets_by_arch m68k)"
-LIST_coldfire=${LIST_m68k}
-
-#########################################################################
-## AVR32 Systems
-#########################################################################
-
-LIST_avr32="$(targets_by_arch avr32)"
-
-#########################################################################
-## Blackfin Systems
-#########################################################################
-
-LIST_blackfin="$(targets_by_arch blackfin)"
-
-#########################################################################
-## SH Systems
-#########################################################################
-
-LIST_sh2="$(targets_by_cpu sh2)"
-LIST_sh3="$(targets_by_cpu sh3)"
-LIST_sh4="$(targets_by_cpu sh4)"
-
-LIST_sh="$(targets_by_arch sh)"
-
-#########################################################################
-## SPARC Systems
-#########################################################################
-
-LIST_sparc="$(targets_by_arch sparc)"
-
-#########################################################################
-## NDS32 Systems
-#########################################################################
-
-LIST_nds32="$(targets_by_arch nds32)"
-
-#########################################################################
-## ARC Systems
-#########################################################################
-
-LIST_arc="$(targets_by_arch arc)"
-
-#-----------------------------------------------------------------------
-
-get_target_location() {
- local target=$1
- local BOARD_NAME=""
- local CONFIG_NAME=""
- local board=""
- local vendor=""
-
- # Automatic mode
- local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
- if [ -z "${line}" ] ; then echo "" ; return ; fi
-
- set ${line}
-
- CONFIG_NAME="${7%_defconfig}"
-
- [ "${BOARD_NAME}" ] || BOARD_NAME="${7%_defconfig}"
-
- if [ $# -gt 5 ]; then
- if [ "$6" = "-" ] ; then
- board=${BOARD_NAME}
- else
- board="$6"
- fi
- fi
-
- [ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5"
- [ $# -gt 6 ] && [ "$8" != "-" ] && {
- tmp="${8%:*}"
- if [ "$tmp" ] ; then
- CONFIG_NAME="$tmp"
- fi
- }
-
- # Assign board directory to BOARDIR variable
- if [ "${vendor}" == "-" ] ; then
- BOARDDIR=${board}
- else
- BOARDDIR=${vendor}/${board}
- fi
-
- echo "${CONFIG_NAME}:${BOARDDIR}:${BOARD_NAME}"
-}
-
-get_target_maintainers() {
- local name=`echo $1 | cut -d : -f 3`
-
- local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
- if [ -z "${line}" ]; then
- echo ""
- return ;
- fi
-
- local mails=`echo ${line} | cut -d ' ' -f 9- | sed -e 's/[^<]*<//' -e 's/>.*</ /' -e 's/>[^>]*$//'`
- [ "$mails" == "-" ] && mails=""
- echo "$mails"
-}
-
-get_target_arch() {
- local target=$1
-
- # Automatic mode
- local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
-
- if [ -z "${line}" ] ; then echo "" ; return ; fi
-
- set ${line}
- echo "$2"
-}
-
-list_target() {
- if [ "$PRINT_MAINTS" != 'y' ] ; then
- echo "$1"
- return
- fi
-
- echo -n "$1:"
-
- local loc=`get_target_location $1`
-
- if [ -z "${loc}" ] ; then echo "ERROR" ; return ; fi
-
- local maintainers_result=`get_target_maintainers ${loc} | tr " " "\n"`
-
- if [ "$MAINTAINERS_ONLY" != 'y' ] ; then
-
- local dir=`echo ${loc} | cut -d ":" -f 2`
- local cfg=`echo ${loc} | cut -d ":" -f 1`
- local git_result=`git log --format=%aE board/${dir} \
- include/configs/${cfg}.h | grep "@"`
- local git_result_recent=`echo ${git_result} | tr " " "\n" | \
- head -n 3`
- local git_result_top=`echo ${git_result} | tr " " "\n" | \
- sort | uniq -c | sort -nr | head -n 3 | \
- sed "s/^ \+[0-9]\+ \+//"`
-
- echo -e "$git_result_recent\n$git_result_top\n$maintainers_result" | \
- sort -u | tr "\n" " " | sed "s/ $//" ;
- else
- echo -e "$maintainers_result" | sort -u | tr "\n" " " | \
- sed "s/ $//" ;
- fi
-
- echo ""
-}
-
-# Each finished build will have a file called ${donep}${n},
-# where n is the index of the build. Each build
-# we've already noted as finished will have ${skipp}${n}.
-# The code managing the build process will use this information
-# to ensure that only BUILD_NBUILDS builds are in flight at once
-donep="${LOG_DIR}/._done_"
-skipp="${LOG_DIR}/._skip_"
-
-build_target_killed() {
- echo "Aborted $target build."
- # Remove the logs for this board since it was aborted
- rm -f ${LOG_DIR}/$target.MAKELOG ${LOG_DIR}/$target.ERR
- exit
-}
-
-build_target() {
- target=$1
- build_idx=$2
-
- if [ "$ONLY_LIST" == 'y' ] ; then
- list_target ${target}
- return
- fi
-
- if [ $BUILD_MANY == 1 ] ; then
- output_dir="${OUTPUT_PREFIX}/${target}"
- mkdir -p "${output_dir}"
- trap build_target_killed TERM
- else
- output_dir="${OUTPUT_PREFIX}"
- fi
-
- target_arch=$(get_target_arch ${target})
- eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'`
- if [ "${cross_toolchain}" ] ; then
- MAKE="$GNU_MAKE CROSS_COMPILE=${cross_toolchain}"
- elif [ "${CROSS_COMPILE}" ] ; then
- MAKE="$GNU_MAKE CROSS_COMPILE=${CROSS_COMPILE}"
- else
- MAKE=$GNU_MAKE
- fi
-
- if [ "${output_dir}" != "." ] ; then
- MAKE="${MAKE} O=${output_dir}"
- fi
-
- ${MAKE} mrproper >/dev/null
-
- echo "Building ${target} board..."
- ${MAKE} -s ${target}_defconfig >/dev/null
-
- ${MAKE} ${JOBS} ${CHECK} all \
- >${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR
-
- # Check for 'make' errors
- if [ ${PIPESTATUS[0]} -ne 0 ] ; then
- RC=1
- fi
-
- if [ $BUILD_MANY == 1 ] ; then
- trap - TERM
-
- ${MAKE} -s clean
-
- if [ -s ${LOG_DIR}/${target}.ERR ] ; then
- cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}
- else
- rm ${LOG_DIR}/${target}.ERR
- fi
- else
- if [ -s ${LOG_DIR}/${target}.ERR ] ; then
- if grep -iw error ${LOG_DIR}/${target}.ERR ; then
- : $(( ERR_CNT += 1 ))
- ERR_LIST="${ERR_LIST} $target"
- else
- : $(( WRN_CNT += 1 ))
- WRN_LIST="${WRN_LIST} $target"
- fi
- else
- rm ${LOG_DIR}/${target}.ERR
- fi
- fi
-
- OBJS=${output_dir}/u-boot
- if [ -e ${output_dir}/spl/u-boot-spl ]; then
- OBJS="${OBJS} ${output_dir}/spl/u-boot-spl"
- fi
-
- ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
-
- [ -e "${LOG_DIR}/${target}.ERR" ] && cat "${LOG_DIR}/${target}.ERR"
-
- touch "${donep}${build_idx}"
-}
-
-manage_builds() {
- search_idx=${OLDEST_IDX}
- if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
-
- while true; do
- if [ -e "${donep}${search_idx}" ] ; then
- : $(( CURRENT_CNT-- ))
- [ ${OLDEST_IDX} -eq ${search_idx} ] &&
- : $(( OLDEST_IDX++ ))
-
- # Only want to count it once
- rm -f "${donep}${search_idx}"
- touch "${skipp}${search_idx}"
- elif [ -e "${skipp}${search_idx}" ] ; then
- [ ${OLDEST_IDX} -eq ${search_idx} ] &&
- : $(( OLDEST_IDX++ ))
- fi
- : $(( search_idx++ ))
- if [ ${search_idx} -gt ${TOTAL_CNT} ] ; then
- if [ ${CURRENT_CNT} -ge ${BUILD_NBUILDS} ] ; then
- search_idx=${OLDEST_IDX}
- sleep 1
- else
- break
- fi
- fi
- done
-}
-
-build_targets() {
- for t in "$@" ; do
- # If a LIST_xxx var exists, use it. But avoid variable
- # expansion in the eval when a board name contains certain
- # characters that the shell interprets.
- case ${t} in
- *[-+=]*) list= ;;
- *) list=$(eval echo '${LIST_'$t'}') ;;
- esac
- if [ -n "${list}" ] ; then
- build_targets ${list}
- else
- : $((TOTAL_CNT += 1))
- : $((CURRENT_CNT += 1))
- rm -f "${donep}${TOTAL_CNT}"
- rm -f "${skipp}${TOTAL_CNT}"
- if [ "$CONTINUE" = 'y' -a -e ${LOG_DIR}/$t.MAKELOG ] ; then
- : $((SKIP_CNT += 1))
- touch "${donep}${TOTAL_CNT}"
- elif [ "$REBUILD_ERRORS" = 'y' -a ! -e ${LOG_DIR}/$t.ERR ] ; then
- : $((SKIP_CNT += 1))
- touch "${donep}${TOTAL_CNT}"
- else
- if [ $BUILD_MANY == 1 ] ; then
- build_target ${t} ${TOTAL_CNT} &
- else
- CUR_TGT="${t}"
- build_target ${t} ${TOTAL_CNT}
- CUR_TGT=''
- fi
- fi
- fi
-
- # We maintain a running count of all the builds we have done.
- # Each finished build will have a file called ${donep}${n},
- # where n is the index of the build. Each build
- # we've already noted as finished will have ${skipp}${n}.
- # We track the current index via TOTAL_CNT, and the oldest
- # index. When we exceed the maximum number of parallel builds,
- # We look from oldest to current for builds that have completed,
- # and update the current count and oldest index as appropriate.
- # If we've gone through the entire list, wait a second, and
- # reprocess the entire list until we find a build that has
- # completed
- if [ ${CURRENT_CNT} -ge ${BUILD_NBUILDS} ] ; then
- manage_builds
- fi
- done
-}
-
-#-----------------------------------------------------------------------
-
-kill_children() {
- local OS=$(uname -s)
- local children=""
- case "${OS}" in
- "Darwin")
- # Mac OS X is known to have BSD style ps
- local pgid=$(ps -p $$ -o pgid | sed -e "/PGID/d")
- children=$(ps -g $pgid -o pid | sed -e "/PID\|$$\|$pgid/d")
- ;;
- *)
- # everything else tries the GNU style
- local pgid=$(ps -p $$ --no-headers -o "%r" | tr -d ' ')
- children=$(pgrep -g $pgid | sed -e "/$$\|$pgid/d")
- ;;
- esac
-
- kill $children 2> /dev/null
- wait $children 2> /dev/null
-
- exit
-}
-
-print_stats() {
- if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
-
- # Only count boards that completed
- : $((TOTAL_CNT = `find ${skipp}* 2> /dev/null | wc -l`))
-
- rm -f ${donep}* ${skipp}*
-
- if [ $BUILD_MANY == 1 ] && [ -e "${OUTPUT_PREFIX}/ERR" ] ; then
- ERR_LIST=`grep -riwl error ${OUTPUT_PREFIX}/ERR/`
- ERR_LIST=`for f in $ERR_LIST ; do echo -n " $(basename $f)" ; done`
- ERR_CNT=`echo $ERR_LIST | wc -w | awk '{print $1}'`
- WRN_LIST=`grep -riwL error ${OUTPUT_PREFIX}/ERR/`
- WRN_LIST=`for f in $WRN_LIST ; do echo -n " $(basename $f)" ; done`
- WRN_CNT=`echo $WRN_LIST | wc -w | awk '{print $1}'`
- else
- # Remove the logs for any board that was interrupted
- rm -f ${LOG_DIR}/${CUR_TGT}.MAKELOG ${LOG_DIR}/${CUR_TGT}.ERR
- fi
-
- : $((TOTAL_CNT -= ${SKIP_CNT}))
- echo ""
- echo "--------------------- SUMMARY ----------------------------"
- if [ "$CONTINUE" = 'y' -o "$REBUILD_ERRORS" = 'y' ] ; then
- echo "Boards skipped: ${SKIP_CNT}"
- fi
- echo "Boards compiled: ${TOTAL_CNT}"
- if [ ${ERR_CNT} -gt 0 ] ; then
- echo "Boards with errors: ${ERR_CNT} (${ERR_LIST} )"
- fi
- if [ ${WRN_CNT} -gt 0 ] ; then
- echo "Boards with warnings but no errors: ${WRN_CNT} (${WRN_LIST} )"
- fi
- echo "----------------------------------------------------------"
-
- if [ $BUILD_MANY == 1 ] ; then
- kill_children
- fi
-
- exit $RC
-}
-
-#-----------------------------------------------------------------------
-
-# Build target groups selected by options, plus any command line args
-set -- ${SELECTED} "$@"
-# run PowerPC by default
-[ $# = 0 ] && set -- powerpc
-build_targets "$@"
-wait
diff --git a/Makefile b/Makefile
index a6a43f9..6087d06 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,6 @@
-VERSION = 2015
+# SPDX-License-Identifier: GPL-2.0+
+
+VERSION = 2019
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
@@ -10,9 +12,10 @@
# Comments in this file are targeted only to the developer, do not
# expect to learn how to build the kernel reading this file.
-# Do not use make's built-in rules and variables
-# (this increases performance and avoids hard-to-debug behaviour);
-MAKEFLAGS += -rR --no-print-directory
+# o Do not use make's built-in rules and variables
+# (this increases performance and avoids hard-to-debug behaviour);
+# o Look for make include files relative to root of kernel src
+MAKEFLAGS += -rR --include-dir=$(CURDIR)
# Avoid funny character set dependencies
unexport LC_ALL
@@ -158,7 +161,7 @@
# Do not print "Entering directory ...",
# but we want to display it when entering to the output directory
# so that IDEs/editors are able to understand relative filenames.
-#MAKEFLAGS += --no-print-directory
+MAKEFLAGS += --no-print-directory
# Call a source code checker (by default, "sparse") as part of the
# C compilation.
@@ -212,12 +215,12 @@
src := $(srctree)
obj := $(objtree)
+VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))
+
buildsrc := $(abspath $(srctree))
buildtree := $(abspath $(CURDIR)/$(KBUILD_OUTPUT))
-VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))
-
-export srctree objtree VPATH KBUILD_OUTPUT buildtree buildsrc
+export srctree objtree VPATH buildsrc buildtree KBUILD_OUTPUT
# Make sure CDPATH settings don't interfere
unexport CDPATH
@@ -246,6 +249,8 @@
CROSS_COMPILE ?=
endif
+CROSS_COMPILE ?=/opt/gcc-linaro-7.3.1-2018.05-i686_aarch64-elf/bin/aarch64-elf-
+export CROSS_COMPILE
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
@@ -257,9 +262,20 @@
HOSTCC = cc
HOSTCXX = c++
-HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
+HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
+ $(if $(CONFIG_TOOLS_DEBUG),-g)
HOSTCXXFLAGS = -O2
+# With the move to GCC 6, we have implicitly upgraded our language
+# standard to GNU11 (see https://gcc.gnu.org/gcc-5/porting_to.html).
+# Some Linux distributions (including RHEL7, SLES13, Debian 8) still
+# have older compilers as their default, so we make it explicit for
+# these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
+CSTD_FLAG := -std=gnu11
+ifeq ($(HOSTOS),linux)
+HOSTCFLAGS += $(CSTD_FLAG)
+endif
+
ifeq ($(HOSTOS),cygwin)
HOSTCFLAGS += -ansi
endif
@@ -287,6 +303,11 @@
HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc")
HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp")
HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
+
+# since Lion (10.7) ASLR is on by default, but we use linker generated lists
+# in some host tools which is a problem then ... so disable ASLR for these
+# tools
+HOSTLDFLAGS += $(call os_x_before, 10, 7, "", "-Xlinker -no_pie")
endif
# Decide whether to build built-in, modular, or both.
@@ -320,12 +341,9 @@
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
-# Look for make include files relative to root of kernel src
-MAKEFLAGS += --include-dir=$(srctree)
-
# We need some generic definitions (do not try to remake the file).
-$(srctree)/scripts/Kbuild.include: ;
-include $(srctree)/scripts/Kbuild.include
+scripts/Kbuild.include: ;
+include scripts/Kbuild.include
# Make variables (CC, etc...)
@@ -344,10 +362,14 @@
STRIP = $(CROSS_COMPILE)strip
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
+LEX = flex
+YACC = bison
AWK = awk
PERL = perl
-PYTHON = python
-DTC = dtc
+PYTHON ?= python
+PYTHON2 = python2
+PYTHON3 = python3
+DTC ?= $(objtree)/scripts/dtc/dtc
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -355,21 +377,28 @@
KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
-KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
+KBUILD_CFLAGS := -Wall -Wstrict-prototypes -Werror \
-Wno-format-security \
- -fno-builtin -ffreestanding
+ -fno-builtin -ffreestanding $(CSTD_FLAG)
+KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing
KBUILD_AFLAGS := -D__ASSEMBLY__
+# Don't generate position independent code
+KBUILD_CFLAGS += $(call cc-option,-fno-PIE)
+KBUILD_AFLAGS += $(call cc-option,-fno-PIE)
+
# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
-export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
+ACSRELEASE = $(shell cat include/config/acs.release 2> /dev/null)
+
+export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION ACSRELEASE
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK PERL PYTHON
-export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
+export MAKE LEX YACC AWK PERL PYTHON PYTHON2 PYTHON3
+export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
export KBUILD_CFLAGS KBUILD_AFLAGS
@@ -395,6 +424,13 @@
scripts_basic:
$(Q)$(MAKE) $(build)=scripts/basic
$(Q)rm -f .tmp_quiet_recordmcount
+ $(Q)if [ -d $(srctree)/.git/hooks ]; then \
+ if [ ! -f $(srctree)/.git/hooks/pre-commit-old -a -f $(srctree)/.git/hooks/pre-commit ]; then \
+ cp $(srctree)/.git/hooks/pre-commit $(srctree)/.git/hooks/pre-commit-old; \
+ fi; \
+ cp $(srctree)/scripts/amlogic/coding_style/pre-commit $(srctree)/.git/hooks/; \
+ chmod +x $(srctree)/.git/hooks/pre-commit; \
+ fi
# To avoid any implicit rule to kick in, define an empty command.
scripts/basic/%: scripts_basic ;
@@ -420,10 +456,11 @@
version_h := include/generated/version_autogenerated.h
timestamp_h := include/generated/timestamp_autogenerated.h
+defaultenv_h := include/generated/defaultenv_autogenerated.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
- ubootversion backup
+ ubootversion backup tests check qcheck
config-targets := 0
mixed-targets := 0
@@ -438,16 +475,12 @@
ifeq ($(KBUILD_EXTMOD),)
ifneq ($(filter config %config,$(MAKECMDGOALS)),)
config-targets := 1
- ifneq ($(filter-out config %config,$(MAKECMDGOALS)),)
+ ifneq ($(words $(MAKECMDGOALS)),1)
mixed-targets := 1
endif
endif
endif
-ifneq ($(ENABLE_UBOOT_UPDATE),1)
- KBUILD_CFLAGS += -DAML_DISABLE_UPDATE_MODE
-endif
-
ifeq ($(mixed-targets),1)
# ===========================================================================
# We're called with mixed targets (*config and build targets).
@@ -474,16 +507,23 @@
export KBUILD_DEFCONFIG KBUILD_KCONFIG
config: scripts_basic outputmakefile FORCE
- +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
+ $(Q)$(MAKE) $(build)=scripts/kconfig $@
%config: scripts_basic outputmakefile FORCE
- +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
+ $(Q)$(MAKE) $(build)=scripts/kconfig $@
else
# ===========================================================================
# Build targets only - this includes vmlinux, arch specific targets, clean
# targets and others. In general all targets except *config targets.
+# Additional helpers built in scripts/
+# Carefully list dependencies so we do not try to build scripts twice
+# in parallel
+PHONY += scripts
+scripts: scripts_basic include/config/auto.conf
+ $(Q)$(MAKE) $(build)=$(@)
+
ifeq ($(dot-config),1)
# Read in config
-include include/config/auto.conf
@@ -500,7 +540,19 @@
# if auto.conf.cmd is missing then we are probably in a cleaned tree so
# we execute the config step to be sure to catch updated Kconfig files
include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
- $(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig
+ $(Q)$(MAKE) -f $(srctree)/Makefile syncconfig
+ @# If the following part fails, include/config/auto.conf should be
+ @# deleted so "make silentoldconfig" will be re-run on the next build.
+ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf || \
+ { rm -f include/config/auto.conf; false; }
+ @# include/config.h has been updated after "make silentoldconfig".
+ @# We need to touch include/config/auto.conf so it gets newer
+ @# than include/config.h.
+ @# Otherwise, 'make silentoldconfig' would be invoked twice.
+ $(Q)touch include/config/auto.conf
+
+u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: include/config.h FORCE
+ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
-include include/autoconf.mk
-include include/autoconf.mk.dep
@@ -509,12 +561,25 @@
# is up-to-date. When we switch to a different board configuration, old CONFIG
# macros are still remaining in include/config/auto.conf. Without the following
# gimmick, wrong config.mk would be included leading nasty warnings/errors.
-autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \
- -path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
-ifneq ($(autoconf_is_current),)
-include $(srctree)/config.mk
-include $(srctree)/arch/$(ARCH)/Makefile
+ifneq ($(wildcard $(KCONFIG_CONFIG)),)
+ifneq ($(wildcard include/config/auto.conf),)
+autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \
+ include/config/auto.conf)
+ifeq ($(autoconf_is_old),)
+include config.mk
+include arch/$(ARCH)/Makefile
endif
+endif
+endif
+
+# These are set by the arch-specific config.mk. Make sure they are exported
+# so they can be used when building an EFI application.
+export EFI_LDS # Filename of EFI link script in arch/$(ARCH)/lib
+export EFI_CRT0 # Filename of EFI CRT0 in arch/$(ARCH)/lib
+export EFI_RELOC # Filename of EFU relocation code in arch/$(ARCH)/lib
+export CFLAGS_EFI # Compiler flags to add when building EFI app
+export CFLAGS_NON_EFI # Compiler flags to remove when building EFI app
+export EFI_TARGET # binutils target if EFI is natively supported
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
# that (or fail if absent). Otherwise, search for a linker script in a
@@ -546,17 +611,26 @@
include/config/auto.conf: ;
endif # $(dot-config)
+#
+# Xtensa linker script cannot be preprocessed with -ansi because of
+# preprocessor operations on strings that don't make C identifiers.
+#
+ifeq ($(CONFIG_XTENSA),)
+LDPPFLAGS += -ansi
+endif
+
ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
KBUILD_CFLAGS += -Os
else
KBUILD_CFLAGS += -O2
endif
-ifdef BUILD_TAG
-KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
-endif
+STACK_CFLAGS := $(call cc-option,-fstack-protector-strong)
+KBUILD_CFLAGS += $(STACK_CFLAGS)
+KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
-KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
+# change __FILE__ to the relative path from the srctree
+KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
KBUILD_CFLAGS += -g
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
@@ -564,11 +638,22 @@
KBUILD_AFLAGS += -g
# Report stack usage if supported
+# ARC tools based on GCC 7.1 has an issue with stack usage
+# with naked functions, see commit message for more details
+ifndef CONFIG_ARC
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y)
KBUILD_CFLAGS += -fstack-usage
endif
+endif
KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+ifeq ($(cc-name),clang)
+KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
+KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
+KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
+KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
+KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
+endif
# turn jbsr into jsr for m68k
ifeq ($(ARCH),m68k)
@@ -580,25 +665,21 @@
# Prohibit date/time macros, which would make the build non-deterministic
KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
-endif
-
-export CONFIG_SYS_TEXT_BASE
-
-include $(srctree)/scripts/Makefile.extrawarn
+include scripts/Makefile.extrawarn
# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
KBUILD_CPPFLAGS += $(KCPPFLAGS)
KBUILD_AFLAGS += $(KAFLAGS)
KBUILD_CFLAGS += $(KCFLAGS)
-KBUILD_CFLAGS += -Werror
# Use UBOOTINCLUDE when you must reference the include/ directory.
# Needed to be compatible with the O= option
UBOOTINCLUDE := \
-Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
+ $(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \
+ $(if $(CONFIG_HAS_THUMB2),, \
+ -I$(srctree)/arch/$(ARCH)/thumb1/include),) \
-I$(srctree)/arch/$(ARCH)/include \
-include $(srctree)/include/linux/kconfig.h
@@ -625,41 +706,47 @@
libs-y += drivers/dma/
libs-y += drivers/gpio/
libs-y += drivers/i2c/
-libs-y += drivers/mmc/
libs-y += drivers/mtd/
-libs-$(CONFIG_AML_NAND) += drivers/nand/
-libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
-libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/amlogic_mtd/
+libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/raw/
libs-y += drivers/mtd/onenand/
libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
libs-y += drivers/mtd/spi/
libs-y += drivers/net/
libs-y += drivers/net/phy/
-libs-y += drivers/pci/
libs-y += drivers/power/ \
+ drivers/power/domain/ \
drivers/power/fuel_gauge/ \
drivers/power/mfd/ \
drivers/power/pmic/ \
- drivers/power/battery/
+ drivers/power/battery/ \
+ drivers/power/regulator/
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
+libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
+libs-y += drivers/usb/dwc3/
+libs-y += drivers/usb/common/
+libs-y += drivers/usb/emul/
libs-y += drivers/usb/eth/
-libs-y += drivers/usb/gadget/
+libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
+libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
libs-y += drivers/usb/host/
libs-y += drivers/usb/musb/
libs-y += drivers/usb/musb-new/
libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
+libs-y += cmd/
libs-y += common/
+libs-y += env/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
-libs-y += test/
-libs-y += test/dm/
+libs-$(CONFIG_UNIT_TEST) += test/ test/dm/
+libs-$(CONFIG_UT_ENV) += test/env/
+libs-$(CONFIG_UT_OVERLAY) += test/overlay/
-#libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
-libs-y += $(if $(BOARDDIR),$(BOARDDIR)/)
+libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-y := $(sort $(libs-y))
@@ -672,7 +759,6 @@
u-boot-init := $(head-y)
u-boot-main := $(libs-y)
-
# Add GCC lib
ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
@@ -680,6 +766,12 @@
PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
endif
PLATFORM_LIBS += $(PLATFORM_LIBGCC)
+
+ifdef CONFIG_CC_COVERAGE
+KBUILD_CFLAGS += --coverage
+PLATFORM_LIBGCC += -lgcov
+endif
+
export PLATFORM_LIBS
export PLATFORM_LIBGCC
@@ -711,6 +803,9 @@
endif
# Statically apply RELA-style relocations (currently arm64 only)
+# This is useful for arm64 where static relocation needs to be performed on
+# the raw binary, but certain simulators only accept an ELF file (but don't
+# do the relocation).
ifneq ($(CONFIG_STATIC_RELA),)
# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
DO_STATIC_RELA = \
@@ -722,21 +817,31 @@
endif
# Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin System.map binary_size_check
-ALL-y += u-boot.hex
-ifeq ($(CONFIG_NEED_BL301), y)
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
ALL-y += bl301.bin
-endif
+
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
+ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
+else
+ifeq ($(CONFIG_MX7)$(CONFIG_SECURE_BOOT), yy)
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
+else
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
+endif
+endif
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
-ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
+ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
endif
@@ -745,37 +850,69 @@
ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
+ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
+ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
-# We can't do this yet due to the need for binary blobs
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
+ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+endif
+
+# Build a combined spl + u-boot image for sunxi
+ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
# enable combined SPL/u-boot/dtb rules for tegra
-ifneq ($(CONFIG_TEGRA),)
-ifeq ($(CONFIG_SPL),y)
-ifeq ($(CONFIG_OF_SEPARATE),y)
-ALL-y += u-boot-dtb-tegra.bin
-else
-ALL-y += u-boot-nodtb-tegra.bin
+ifeq ($(CONFIG_TEGRA)$(CONFIG_SPL),yy)
+ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
+ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
-endif
-endif
+
+ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
endif
+ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
+ALL-y += init_sp_bss_offset_check
+endif
+
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+ALL-y += u-boot-with-dtb.bin
+endif
+
LDFLAGS_u-boot += $(LDFLAGS_FINAL)
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
+
+# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
+LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
+
+ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
endif
+# Normally we fill empty space with 0xff
quiet_cmd_objcopy = OBJCOPY $@
-cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+cmd_objcopy = $(OBJCOPY) --gap-fill=0xff $(OBJCOPYFLAGS) \
+ $(OBJCOPYFLAGS_$(@F)) $< $@
+
+# Provide a version which does not do this, for use by EFI
+quiet_cmd_zobjcopy = OBJCOPY $@
+cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+
+quiet_cmd_efipayload = OBJCOPY $@
+cmd_efipayload = $(OBJCOPY) -I binary -O $(EFIPAYLOAD_BFDTARGET) -B $(EFIPAYLOAD_BFDARCH) $< $@
+
+MKIMAGEOUTPUT ?= /dev/null
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
+
+quiet_cmd_mkfitimage = MKIMAGE $@
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
+ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_cat = CAT $@
cmd_cat = cat $(filter-out $(PHONY), $^) > $@
@@ -785,24 +922,155 @@
quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
-all: $(ALL-y)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
- @echo "===================== WARNING ======================"
- @echo "Please convert this board to generic board."
- @echo "Otherwise it will be removed by the end of 2014."
- @echo "See doc/README.generic-board for further information"
- @echo "===================================================="
+cfg: u-boot.cfg
+
+quiet_cmd_cfgcheck = CFGCHK $2
+cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
+ $(srctree)/scripts/config_whitelist.txt $(srctree)
+
+all: $(ALL-y) cfg
+ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
+ @echo >&2 "(possibly in a subsequent patch in your series)"
+ @echo >&2 "before sending patches to the mailing list."
+ @echo >&2 "===================================================="
endif
+ifeq ($(CONFIG_MMC),y)
+ifneq ($(CONFIG_DM_MMC)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_MMC. Please update"
+ @echo >&2 "the board to use CONFIG_DM_MMC before the v2019.04 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_USB),y)
+ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_USB. Please update"
+ @echo >&2 "the board to use CONFIG_DM_USB before the v2019.07 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_LIBATA)$(CONFIG_MVSATA_IDE),y)
+ifneq ($(CONFIG_DM_SCSI),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_SCSI. Please update"
+ @echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_PCI),y)
+ifneq ($(CONFIG_DM_PCI),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_PCI Please update"
+ @echo >&2 "the board to use CONFIG_DM_PCI before the v2019.07 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ifneq ($(CONFIG_LCD)$(CONFIG_VIDEO),)
+ifneq ($(CONFIG_DM_VIDEO),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_VIDEO Please update"
+ @echo >&2 "the board to use CONFIG_DM_VIDEO before the v2019.07 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_OF_EMBED),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
+ @echo >&2 "be used for debugging purposes. Please use"
+ @echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
+ @echo >&2 "See doc/README.fdt-control for more info."
+ @echo >&2 "===================================================="
+endif
+ifeq ($(CONFIG_SPI),y)
+ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_SPI. Please update"
+ @echo >&2 "the board before v2019.04 for no dm conversion"
+ @echo >&2 "and v2019.07 for partially dm converted drivers."
+ @echo >&2 "Failure to update can lead to driver/board removal"
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_SPI_FLASH),y)
+ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_SPI_FLASH. Please update"
+ @echo >&2 "the board to use CONFIG_SPI_FLASH before the v2019.07 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
+endif
+ @# Check that this build does not use CONFIG options that we do not
+ @# know about unless they are in Kconfig. All the existing CONFIG
+ @# options are whitelisted, so new ones should not be added.
+ $(call cmd,cfgcheck,u-boot.cfg)
PHONY += dtbs
-dtbs dts/dt.dtb: checkdtc u-boot
+dtbs: dts/dt.dtb
+ @:
+dts/dt.dtb: u-boot
$(Q)$(MAKE) $(build)=dts dtbs
-u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
+quiet_cmd_copy = COPY $@
+ cmd_copy = cp $< $@
+
+ifeq ($(CONFIG_MULTI_DTB_FIT),y)
+
+fit-dtb.blob: dts/dt.dtb FORCE
+ $(call if_changed,mkimage)
+
+MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+ -a 0 -e 0 -E \
+ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
+
+u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
$(call if_changed,cat)
+u-boot.bin: u-boot-fit-dtb.bin FORCE
+ $(call if_changed,copy)
+else ifeq ($(CONFIG_OF_SEPARATE),y)
+u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
+ $(call if_changed,cat)
+
+u-boot.bin: u-boot-dtb.bin FORCE
+ $(call if_changed,copy)
+else
+u-boot.bin: u-boot-nodtb.bin FORCE
+ $(call if_changed,copy)
+endif
+
+.PHONY : bl301.bin
+bl301.bin: tools prepare acs.bin bl21.bin
+ $(Q)$(MAKE) -C $(srctree)/arch/arm/mach-meson/${SOC}/firmware/scp_task
+
+.PHONY : acs.bin
+acs.bin: tools prepare u-boot.bin
+ $(Q)$(MAKE) -C $(srctree)/arch/arm/mach-meson/${SOC}/firmware/acs all FIRMWARE=$@
+
+.PHONY : bl21.bin
+bl21.bin: tools prepare u-boot.bin acs.bin
+ $(Q)$(MAKE) -C $(srctree)/arch/arm/mach-meson/${SOC}/firmware/bl21 all FIRMWARE=$@
+
%.imx: %.bin
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+
+%.vyb: %.imx
+ $(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
@@ -817,11 +1085,27 @@
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
-OBJCOPYFLAGS_u-boot.bin := -O binary \
- $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
+OBJCOPYFLAGS_u-boot-elf.srec := $(OBJCOPYFLAGS_u-boot.srec)
-binary_size_check: u-boot.bin FORCE
- @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
+u-boot-elf.srec: u-boot.elf FORCE
+ $(call if_changed,objcopy)
+
+OBJCOPYFLAGS_u-boot-spl.srec = $(OBJCOPYFLAGS_u-boot.srec)
+
+spl/u-boot-spl.srec: spl/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
+OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
+ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
+ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
+
+OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
+
+spl/u-boot-spl.hex: spl/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
+binary_size_check: u-boot-nodtb.bin FORCE
+ @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
| sed 's/0X//g' \
@@ -829,14 +1113,41 @@
if [ "" != "$$map_size" ]; then \
if test $$map_size -ne $$file_size; then \
echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
- echo " but u-boot.bin shows $$file_size" >&2 ; \
+ echo " but u-boot-nodtb.bin shows $$file_size" >&2 ; \
exit 1; \
fi \
fi
-u-boot.bin: u-boot FORCE
+ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
+ifneq ($(CONFIG_SYS_MALLOC_F_LEN),)
+subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN)))
+else
+subtract_sys_malloc_f_len = true
+endif
+# The 1/4 margin below is somewhat arbitrary. The likely initial SP usage is
+# so low that the DTB could probably use 90%+ of the available space, for
+# current values of CONFIG_SYS_INIT_SP_BSS_OFFSET at least. However, let's be
+# safe for now and tweak this later if space becomes tight.
+# A rejected alternative would be to check that some absolute minimum stack
+# space was available. However, since CONFIG_SYS_INIT_SP_BSS_OFFSET is
+# deliberately build-specific, to take account of build-to-build stack usage
+# differences due to different feature sets, there is no common absolute value
+# to check against.
+init_sp_bss_offset_check: u-boot.dtb FORCE
+ @dtb_size=$(shell wc -c u-boot.dtb | awk '{print $$1}') ; \
+ space=$(CONFIG_SYS_INIT_SP_BSS_OFFSET) ; \
+ $(subtract_sys_malloc_f_len) ; \
+ quarter_space=$$(($${space} / 4)) ; \
+ if [ $${dtb_size} -gt $${quarter_space} ]; then \
+ echo "u-boot.dtb is larger than 1 quarter of " >&2 ; \
+ echo "(CONFIG_SYS_INIT_SP_BSS_OFFSET - CONFIG_SYS_MALLOC_F_LEN)" >&2 ; \
+ exit 1 ; \
+ fi
+endif
+
+u-boot-nodtb.bin: u-boot FORCE
$(call if_changed,objcopy)
- @$(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
+ $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
$(BOARD_SIZE_CHECK)
u-boot.ldr: u-boot
@@ -844,6 +1155,14 @@
$(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
+# binman
+# ---------------------------------------------------------------------------
+# Use 'make BINMAN_DEBUG=1' to enable debugging
+quiet_cmd_binman = BINMAN $@
+cmd_binman = $(srctree)/tools/binman/binman -u -d u-boot.dtb -O . -m \
+ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
+ $(if $(BINMAN_DEBUG),-D) $(BINMAN_$(@F)) $<
+
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
@@ -851,26 +1170,6 @@
u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
$(call if_changed,objcopy)
-.PHONY: u-boot-comp.bin
-u-boot-comp.bin:u-boot.bin
- #tools/uclpack $< $@
- cp $< $@
-# $(objtree)/tools/uclpack $< $@
-
-ifeq ($(CONFIG_NEED_BL301), y)
-.PHONY : bl301.bin
-bl301.bin: tools prepare acs.bin bl21.bin
- $(Q)$(MAKE) -C $(srctree)/$(CPUDIR)/${SOC}/firmware/scp_task
-endif
-
-.PHONY : acs.bin
-acs.bin: tools prepare u-boot.bin
- $(Q)$(MAKE) -C $(srctree)/$(CPUDIR)/${SOC}/firmware/acs all FIRMWARE=$@
-
-.PHONY : bl21.bin
-bl21.bin: tools prepare u-boot.bin acs.bin
- $(Q)$(MAKE) -C $(srctree)/$(CPUDIR)/${SOC}/firmware/bl21 all FIRMWARE=$@
-
#
# U-Boot entry point, needed for booting of full-blown U-Boot
# from the SPL U-Boot version.
@@ -879,22 +1178,62 @@
CONFIG_SYS_UBOOT_START := 0
endif
+# Boards with more complex image requirments can provide an .its source file
+# or a generator script
+ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
+U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+else
+ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
+U_BOOT_ITS := u-boot.its
+ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
+U_BOOT_ITS_DEPS += u-boot-nodtb.bin
+endif
+ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
+U_BOOT_ITS_DEPS += u-boot
+endif
+$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
+ $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
+ $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
+endif
+endif
+
+ifdef CONFIG_SPL_LOAD_FIT
+MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
+ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
+CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
+endif
+
+MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
+MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
+ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ $(if $(KEYDIR),-k $(KEYDIR))
+
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
-u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
+ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
-MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
+u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+ $(call if_changed,mkfitimage)
+ $(BOARD_SIZE_CHECK)
-u-boot-dtb.img: u-boot-dtb.bin FORCE
+u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
u-boot.sha1: u-boot.bin
@@ -903,8 +1242,8 @@
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-ifdef CONFIG_TPL
-SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
+ifneq ($(CONFIG_SPL_PAYLOAD),)
+SPL_PAYLOAD := $(CONFIG_SPL_PAYLOAD:"%"=%)
else
SPL_PAYLOAD := u-boot.bin
endif
@@ -914,16 +1253,43 @@
u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE
$(call if_changed,pad_cat)
+ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
+MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
+
+lpc32xx-spl.img: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+
+lpc32xx-boot-0.bin: lpc32xx-spl.img FORCE
+ $(call if_changed,objcopy)
+
+OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+
+lpc32xx-boot-1.bin: lpc32xx-spl.img FORCE
+ $(call if_changed,objcopy)
+
+lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img FORCE
+ $(call if_changed,cat)
+
+CLEAN_FILES += lpc32xx-*
+endif
+
OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \
--pad-to=$(CONFIG_TPL_PAD_TO)
tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
$(call if_changed,pad_cat)
SPL: spl/u-boot-spl.bin FORCE
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+
+ifeq ($(CONFIG_ARCH_IMX8M), y)
+flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+endif
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
@@ -961,90 +1327,105 @@
u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
-MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \
- -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL
-spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage)
+ifneq ($(CONFIG_ARCH_SOCFPGA),)
+quiet_cmd_socboot = SOCBOOT $@
+cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
+ spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
+ u-boot.img > $@ || rm -f $@
+u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
+ $(call if_changed,socboot)
+endif
-OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
- --gap-fill=0
-u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
- $(call if_changed,pad_cat)
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \
+ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE
+ $(call if_changed,binman)
-MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
- -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
-u-boot-nand.gph: u-boot.bin FORCE
- $(call if_changed,mkimage)
- @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y)
+OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec
+u-boot-br.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+endif
# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
-# the middle.
+# the middle. This is handled by binman based on an image description in the
+# board's device tree.
ifneq ($(CONFIG_X86_RESET_VECTOR),)
rom: u-boot.rom FORCE
-IFDTOOL=$(objtree)/tools/ifdtool
-IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb
-IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
-IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
-IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
+refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
+ $(call if_changed,copy)
-ifneq ($(CONFIG_HAVE_INTEL_ME),)
-IFDTOOL_ME_FLAGS = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
-IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
-endif
+quiet_cmd_ldr = LD $@
+cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
+ $(filter-out FORCE,$^) -o $@
-ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
-endif
-
-ifneq ($(CONFIG_HAVE_FSP),)
-IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_CMC),)
-IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
-endif
-
-ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
-endif
-
-quiet_cmd_ifdtool = IFDTOOL $@
-cmd_ifdtool = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
-ifneq ($(CONFIG_HAVE_INTEL_ME),)
-cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
-endif
-cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
-cmd_ifdtool += mv u-boot.tmp $@
-
-u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin
- $(call if_changed,ifdtool)
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
+ $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
+ $(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE
+ $(call if_changed,binman)
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
u-boot-x86-16bit.bin: u-boot FORCE
$(call if_changed,objcopy)
endif
-ifneq ($(CONFIG_SUNXI),)
-OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
- --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
- u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
- $(call if_changed,pad_cat)
-endif
-
-ifneq ($(CONFIG_TEGRA),)
-OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
-u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
- $(call if_changed,pad_cat)
-
-ifeq ($(CONFIG_OF_SEPARATE),y)
-u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE
+ifneq ($(CONFIG_ARCH_SUNXI),)
+ifeq ($(CONFIG_ARM64),)
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
+ $(call if_changed,binman)
+else
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
$(call if_changed,cat)
endif
endif
+ifneq ($(CONFIG_TEGRA),)
+ifneq ($(CONFIG_BINMAN),)
+# Makes u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin
+%-dtb-tegra.bin %-tegra.bin %-nodtb-tegra.bin: \
+ spl/%-spl %.bin FORCE
+ $(call if_changed,binman)
+else
+OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
+u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot-nodtb.bin FORCE
+ $(call if_changed,pad_cat)
+
+OBJCOPYFLAGS_u-boot-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
+u-boot-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
+ $(call if_changed,pad_cat)
+
+u-boot-dtb-tegra.bin: u-boot-tegra.bin FORCE
+ $(call if_changed,copy)
+endif # binman
+endif
+
+OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
+u-boot-app.efi: u-boot FORCE
+ $(call if_changed,zobjcopy)
+
+u-boot.bin.o: u-boot.bin FORCE
+ $(call if_changed,efipayload)
+
+u-boot-payload.lds: $(LDSCRIPT_EFI) FORCE
+ $(call if_changed_dep,cpp_lds)
+
+# Rule to link the EFI payload which contains a stub and a U-Boot binary
+quiet_cmd_u-boot_payload ?= LD $@
+ cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \
+ -T u-boot-payload.lds arch/x86/cpu/call32.o \
+ lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \
+ $(addprefix arch/$(ARCH)/lib/,$(EFISTUB))
+
+u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE
+ $(call if_changed,u-boot_payload)
+
+OBJCOPYFLAGS_u-boot-payload.efi := $(OBJCOPYFLAGS_EFI)
+u-boot-payload.efi: u-boot-payload FORCE
+ $(call if_changed,zobjcopy)
+
u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
$(call if_changed,cat)
@@ -1061,8 +1442,12 @@
ifeq ($(ARCH),arm)
UBOOT_BINLOAD := u-boot.img
else
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+UBOOT_BINLOAD := u-boot-with-dtb.bin
+else
UBOOT_BINLOAD := u-boot.bin
endif
+endif
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0xff
@@ -1081,17 +1466,39 @@
u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,pad_cat)
-# Create a new ELF from a raw binary file. This is useful for arm64
-# where static relocation needs to be performed on the raw binary,
-# but certain simulators only accept an ELF file (but don't do the
-# relocation).
-# FIXME refactor dts/Makefile to share target/arch detection
+# Create a new ELF from a raw binary file.
+ifndef PLATFORM_ELFENTRY
+ PLATFORM_ELFENTRY = "_start"
+endif
+quiet_cmd_u-boot-elf ?= LD $@
+ cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
+ --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
+ -Ttext=$(CONFIG_SYS_TEXT_BASE)
u-boot.elf: u-boot.bin
- @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \
- $< u-boot-elf.o
- @$(LD) u-boot-elf.o -o $@ \
- --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
- -Ttext=$(CONFIG_SYS_TEXT_BASE)
+ $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
+ $(call if_changed,u-boot-elf)
+
+# MediaTek's ARM-based u-boot needs a header to contains its load address
+# which is parsed by the BootROM.
+# If the SPL build is enabled, the header will be added to the spl binary,
+# and the spl binary and the u-boot.img will be combined into one file.
+# Otherwise the header will be added to the u-boot.bin directly.
+
+ifeq ($(CONFIG_SPL),y)
+spl/u-boot-spl-mtk.bin: spl/u-boot-spl
+
+u-boot-mtk.bin: u-boot.dtb u-boot.img spl/u-boot-spl-mtk.bin FORCE
+ $(call if_changed,binman)
+else
+MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+u-boot-mtk.bin: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
+ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
@@ -1099,7 +1506,8 @@
cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
--start-group $(u-boot-main) --end-group \
- $(PLATFORM_LIBS) -Map u-boot.map
+ $(PLATFORM_LIBS) -Map u-boot.map; \
+ $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
@@ -1108,13 +1516,22 @@
$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
-c $(srctree)/common/system_map.c -o common/system_map.o
-u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds
- $(call if_changed,u-boot__)
+u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
+ +$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
$(call cmd,u-boot__) common/system_map.o
endif
+ifeq ($(CONFIG_RISCV),y)
+ @tools/prelink-riscv $@ 0
+endif
+
+quiet_cmd_sym ?= SYM $@
+ cmd_sym ?= $(OBJDUMP) -t $< > $@
+u-boot.sym: u-boot FORCE
+ $(call if_changed,sym)
+
# The actual objects are generated when descending,
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
@@ -1140,10 +1557,17 @@
echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
endef
+define filechk_acs.release
+ echo "$(BOARD)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+endef
+
# Store (new) UBOOTRELEASE string in include/config/uboot.release
include/config/uboot.release: include/config/auto.conf FORCE
$(call filechk,uboot.release)
+include/config/acs.release: include/config/auto.conf FORCE
+ $(call filechk,acs.release)
+
# Things we need to do before we recursively start building the kernel
# or the modules are listed in "prepare".
@@ -1157,7 +1581,7 @@
# prepare3 is used to check if we are building in a separate output directory,
# and if so do:
# 1) Check that make has not been executed in the kernel src $(srctree)
-prepare3: include/config/uboot.release
+prepare3: include/config/uboot.release include/config/acs.release
ifneq ($(KBUILD_SRC),)
@$(kecho) ' Using $(srctree) as source for U-Boot'
$(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \
@@ -1172,18 +1596,15 @@
prepare1: prepare2 $(version_h) $(timestamp_h) \
include/config/auto.conf
-ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
-ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
- @echo >&2 " Your architecture does not support generic board."
- @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
- @/bin/false
-endif
-endif
ifeq ($(wildcard $(LDSCRIPT)),)
@echo >&2 " Could not find linker script."
@/bin/false
endif
+ifeq ($(CONFIG_USE_DEFAULT_ENV_FILE),y)
+prepare1: $(defaultenv_h)
+endif
+
archprepare: prepare1 scripts_basic
prepare0: archprepare FORCE
@@ -1197,50 +1618,92 @@
define filechk_version.h
(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
+ echo \#define ACS_VERSION \"$(ACSRELEASE)\"; \
echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
echo \#define CONFIG_SYSTEM_AS_ROOT \"${SYSTEMMODE}\"; \
- echo \#define CONFIG_BUILD_TYPE \"${BUILD_TYPE}\"; \
- echo \#define CONFIG_BOARD_NAME \"${BOARD_NAME}\"; \
echo \#define CONFIG_AVB2 \"${AVBMODE}\"; \
- echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \
- echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; )
+ echo \#define CONFIG_CMD_BOOTCTOL_VAB \"${BOOTCTRLMODE}\"; \
+ echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
+ echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef
+# The SOURCE_DATE_EPOCH mechanism requires a date that behaves like GNU date.
+# The BSD date on the other hand behaves different and would produce errors
+# with the misused '-d' switch. Respect that and search a working date with
+# well known pre- and suffixes for the GNU variant of date.
define filechk_timestamp.h
- (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
- LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
- LC_ALL=C date +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"';)
+ (if test -n "$${SOURCE_DATE_EPOCH}"; then \
+ SOURCE_DATE="@$${SOURCE_DATE_EPOCH}"; \
+ DATE=""; \
+ for date in gdate date.gnu date; do \
+ $${date} -u -d "$${SOURCE_DATE}" >/dev/null 2>&1 && DATE="$${date}"; \
+ done; \
+ if test -n "$${DATE}"; then \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \
+ else \
+ return 42; \
+ fi; \
+ else \
+ LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
+ LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
+ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
+ LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
+ LC_ALL=C date +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \
+ fi)
endef
-$(version_h): include/config/uboot.release FORCE
+define filechk_defaultenv.h
+ (grep -v '^#' | \
+ grep -v '^$$' | \
+ tr '\n' '\0' | \
+ sed -e 's/\\\x0/\n/' | \
+ xxd -i ; echo ", 0x00" ; )
+endef
+
+$(version_h): include/config/uboot.release include/config/acs.release FORCE
$(call filechk,version.h)
$(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
-# ---------------------------------------------------------------------------
-
-PHONY += depend dep
-depend dep:
- @echo '*** Warning: make $@ is unnecessary now.'
+$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
+ $(call filechk,defaultenv.h)
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@
-cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
- -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $<
+cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) \
+ -D__ASSEMBLY__ -x assembler-with-cpp -std=c99 -P -o $@ $<
u-boot.lds: $(LDSCRIPT) prepare FORCE
$(call if_changed_dep,cpp_lds)
spl/u-boot-spl.bin: spl/u-boot-spl
@:
-spl/u-boot-spl: tools prepare
+spl/u-boot-spl: tools prepare \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
spl/sunxi-spl.bin: spl/u-boot-spl
@:
-tpl/u-boot-tpl.bin: tools prepare
+spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
+ @:
+
+spl/u-boot-spl.sfp: spl/u-boot-spl
+ @:
+
+spl/boot.bin: spl/u-boot-spl
+ @:
+
+tpl/u-boot-tpl.bin: tools prepare \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
@@ -1251,6 +1714,7 @@
tags ctags:
ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
+ ln -s ctags tags
etags:
etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
@@ -1267,12 +1731,6 @@
System.map: u-boot
@$(call SYSTEM_MAP,$<) > $@
-checkdtc:
- @if test $(call dtc-version) -lt 0104; then \
- echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \
- false; \
- fi
-
#########################################################################
# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
@@ -1286,14 +1744,14 @@
false; \
fi
-env: scripts_basic
- $(Q)$(MAKE) $(build)=tools/$@
+envtools: scripts_basic $(version_h) $(timestamp_h)
+ $(Q)$(MAKE) $(build)=tools/env
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
tools-all: export HOST_TOOLS_ALL=y
-tools-all: env tools ;
+tools-all: envtools tools ;
cross_tools: export CROSS_BUILD_TOOLS=y
cross_tools: tools ;
@@ -1303,8 +1761,6 @@
git log --no-merges U-Boot-1_1_5.. | \
unexpand -a | sed -e 's/\s\s*$$//' > $@
-include/license.h: tools/bin2header COPYING
- cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h
#########################################################################
###
@@ -1320,13 +1776,13 @@
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- u-boot* MLO* SPL System.map
+ boot* u-boot* MLO* SPL System.map fit-dtb.blob
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
.tmp_objdiff
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
- ctags etags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
+ ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
# clean - Delete most, but leave enough to build external modules
#
@@ -1335,23 +1791,25 @@
clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
-clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook)
+clean-dirs := $(addprefix _clean_, $(clean-dirs))
PHONY += $(clean-dirs) clean archclean
$(clean-dirs):
$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
-# TODO: Do not use *.cfgtmp
clean: $(clean-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
- -o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \
+ -o -name '*.ko.*' -o -name '*.su' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+ -o -name '*.lex.c' -o -name '*.tab.[ch]' \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
- -o -name '*.gcno' \) -type f -print | xargs rm -f
+ -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
+ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
+ -type f -print | xargs rm -f
# mrproper - Delete all generated files, including .config
#
@@ -1377,21 +1835,10 @@
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
-o -name '.*.rej' -o -name '*%' -o -name 'core' \
- -o -name '*.o' \) \
+ -o -name '*.pyc' \) \
-type f -print | xargs rm -f
@rm -f boards.cfg
- @rm -rf $(buildtree)/*
- @rm -f $(FIP_FOLDER_SOC)/acs.bin
- @rm -f $(FIP_FOLDER_SOC)/bl2_acs.bin
- @rm -f $(FIP_FOLDER_SOC)/bl301.bin
- @rm -f $(FIP_FOLDER_SOC)/bl33.bin
- @rm -f $(FIP_FOLDER_SOC)/fip.bin
- @rm -f $(FIP_FOLDER_SOC)/boot.bin
- @rm -f $(FIP_FOLDER_SOC)/boot_sd.bin
- @rm -f $(FIP_FOLDER_SOC)/u-boot.bin
- @rm -f $(FIP_FOLDER_SOC)/u-boot.bin.* $(FIP_FOLDER_SOC)/*.encrypt
- @rm -f $(FIP_FOLDER)/u-boot.bin.* $(FIP_FOLDER)/*.bin $(FIP_FOLDER)/*.encrypt
- @rm -f $(srctree)/fip/aml_encrypt_gxb
+ @rm -rf $(srctree)/build
backup:
F=`basename $(srctree)` ; cd .. ; \
@@ -1406,8 +1853,14 @@
@echo 'Configuration targets:'
@$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
@echo ''
+ @echo 'Test targets:'
+ @echo ''
+ @echo ' check - Run all automated tests that use sandbox'
+ @echo ' qcheck - Run quick automated tests that use sandbox'
+ @echo ''
@echo 'Other generic targets:'
@echo ' all - Build all necessary images depending on configuration'
+ @echo ' tests - Build U-Boot for sandbox and run tests'
@echo '* u-boot - Build the bare u-boot'
@echo ' dir/ - Build all files in dir and below'
@echo ' dir/file.[oisS] - Build specified target only'
@@ -1418,12 +1871,15 @@
@echo ' cscope - Generate cscope index'
@echo ' ubootrelease - Output the release version string (use with make -s)'
@echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
+ @echo " cfg - Don't build, just create the .cfg files"
+ @echo " envtools - Build only the target-side environment tools"
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'
+ @echo ' coccicheck - Execute static code analysis with Coccinelle'
@echo ''
@echo 'Documentation targets:'
- @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp
+ @$(MAKE) -f $(srctree)/Documentation/Makefile dochelp
@echo ''
@echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build'
@echo ' make V=2 [targets] 2 => give reason for rebuild of target'
@@ -1439,20 +1895,20 @@
@echo ''
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
@echo 'For further info see the ./README file'
- @export srctree
- @$(srctree)/amlogic_help.sh
+tests check:
+ $(srctree)/test/run
+
+qcheck:
+ $(srctree)/test/run quick
# Documentation targets
# ---------------------------------------------------------------------------
-%docs: scripts_basic FORCE
- $(Q)$(MAKE) $(build)=scripts build_docproc
- $(Q)$(MAKE) $(build)=doc/DocBook $@
-
-# Dummies...
-PHONY += prepare scripts
-prepare: ;
-scripts: ;
+DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
+ linkcheckdocs dochelp refcheckdocs
+PHONY += $(DOC_TARGETS)
+$(DOC_TARGETS): scripts_basic FORCE
+ $(Q)$(MAKE) $(build)=Documentation $@
endif #ifeq ($(config-targets),1)
endif #ifeq ($(mixed-targets),1)
@@ -1518,6 +1974,14 @@
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
+# Consistency checks
+# ---------------------------------------------------------------------------
+
+PHONY += coccicheck
+
+coccicheck:
+ $(Q)$(CONFIG_SHELL) $(srctree)/scripts/$@
+
# FIXME Should go into a make.lib or something
# ===========================================================================
@@ -1537,11 +2001,6 @@
include $(cmd_files)
endif
-# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
-# Usage:
-# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(srctree)/scripts/Makefile.clean obj
-
endif # skip-makefile
PHONY += FORCE
diff --git a/README b/README
index 7fe8afe..17d56b8 100644
--- a/README
+++ b/README
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000 - 2013
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
Summary:
========
@@ -34,12 +32,14 @@
Makefile have been tested to some extent and can be considered
"working". In fact, many of them are used in production systems.
-In case of problems see the CHANGELOG and CREDITS files to find out
-who contributed the specific port. The boards.cfg file lists board
-maintainers.
+In case of problems see the CHANGELOG file to find out who contributed
+the specific port. In addition, there are various MAINTAINERS files
+scattered throughout the U-Boot source identifying the people or
+companies responsible for various boards and subsystems.
-Note: There is no CHANGELOG file in the actual U-Boot source tree;
-it can be created dynamically from the Git log using:
+Note: As of August, 2010, there is no longer a CHANGELOG file in the
+actual U-Boot source tree; however, it can be created dynamically
+from the Git log using:
make CHANGELOG
@@ -48,7 +48,7 @@
==================
In case you have questions about, problems with or contributions for
-U-Boot you should send a message to the U-Boot mailing list at
+U-Boot, you should send a message to the U-Boot mailing list at
<u-boot@lists.denx.de>. There is also an archive of previous traffic
on the mailing list - please search the archive before asking FAQ's.
Please see http://lists.denx.de/pipermail/u-boot and
@@ -58,7 +58,7 @@
Where to get source code:
=========================
-The U-Boot source code is maintained in the git repository at
+The U-Boot source code is maintained in the Git repository at
git://www.denx.de/git/u-boot.git ; you can browse it online at
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
@@ -125,7 +125,7 @@
Examples:
U-Boot v2009.11 - Release November 2009
U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree
- U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
+ U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
Directory Hierarchy:
@@ -133,80 +133,23 @@
/arch Architecture specific files
/arc Files generic to ARC architecture
- /cpu CPU specific files
- /arc700 Files specific to ARC 700 CPUs
- /lib Architecture specific library files
/arm Files generic to ARM architecture
- /cpu CPU specific files
- /arm720t Files specific to ARM 720 CPUs
- /arm920t Files specific to ARM 920 CPUs
- /at91 Files specific to Atmel AT91RM9200 CPU
- /imx Files specific to Freescale MC9328 i.MX CPUs
- /s3c24x0 Files specific to Samsung S3C24X0 CPUs
- /arm926ejs Files specific to ARM 926 CPUs
- /arm1136 Files specific to ARM 1136 CPUs
- /pxa Files specific to Intel XScale PXA CPUs
- /sa1100 Files specific to Intel StrongARM SA1100 CPUs
- /lib Architecture specific library files
- /avr32 Files generic to AVR32 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
- /blackfin Files generic to Analog Devices Blackfin architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/m68k Files generic to m68k architecture
- /cpu CPU specific files
- /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs
- /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
- /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs
- /lib Architecture specific library files
/microblaze Files generic to microblaze architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/mips Files generic to MIPS architecture
- /cpu CPU specific files
- /mips32 Files specific to MIPS32 CPUs
- /mips64 Files specific to MIPS64 CPUs
- /lib Architecture specific library files
/nds32 Files generic to NDS32 architecture
- /cpu CPU specific files
- /n1213 Files specific to Andes Technology N1213 CPUs
- /lib Architecture specific library files
/nios2 Files generic to Altera NIOS2 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/openrisc Files generic to OpenRISC architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/powerpc Files generic to PowerPC architecture
- /cpu CPU specific files
- /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
- /mpc5xx Files specific to Freescale MPC5xx CPUs
- /mpc5xxx Files specific to Freescale MPC5xxx CPUs
- /mpc8xx Files specific to Freescale MPC8xx CPUs
- /mpc8260 Files specific to Freescale MPC8260 CPUs
- /mpc85xx Files specific to Freescale MPC85xx CPUs
- /ppc4xx Files specific to AMCC PowerPC 4xx CPUs
- /lib Architecture specific library files
+ /riscv Files generic to RISC-V architecture
+ /sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
- /cpu CPU specific files
- /sh2 Files specific to sh2 CPUs
- /sh3 Files specific to sh3 CPUs
- /sh4 Files specific to sh4 CPUs
- /lib Architecture specific library files
- /sparc Files generic to SPARC architecture
- /cpu CPU specific files
- /leon2 Files specific to Gaisler LEON2 SPARC CPU
- /leon3 Files specific to Gaisler LEON3 SPARC CPU
- /lib Architecture specific library files
/x86 Files generic to x86 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/api Machine/arch independent API for external apps
/board Board dependent files
+/cmd U-Boot commands functions
/common Misc architecture independent functions
+/configs Board default configuration files
/disk Code for disk drive partition handling
/doc Documentation (don't expect too much)
/drivers Commonly used device drivers
@@ -214,13 +157,12 @@
/examples Example code for standalone applications, etc.
/fs Filesystem code (cramfs, ext2, jffs2, etc.)
/include Header Files
-/lib Files generic to all architectures
- /libfdt Library files to support flattened device trees
- /lzma Library files to support LZMA decompression
- /lzo Library files to support LZO decompression
+/lib Library routines generic to all architectures
+/Licenses Various license files
/net Networking code
/post Power On Self Test
-/spl Secondary Program Loader framework
+/scripts Various build scripts and Makefiles
+/test Various unit test files
/tools Tools to build S-Record or U-Boot images, etc.
Software Configuration:
@@ -240,11 +182,11 @@
you don't know what you're doing; they have names beginning with
"CONFIG_SYS_".
-Later we will add a configuration tool - probably similar to or even
-identical to what's used for the Linux kernel. Right now, we have to
-do the configuration by hand, which means creating some symbolic
-links and editing some configuration files. We use the TQM8xxL boards
-as an example here.
+Previously, all configuration was done by hand, which involved creating
+symbolic links and editing configuration files manually. More recently,
+U-Boot has added the Kbuild infrastructure used by the Linux kernel,
+allowing you to use the "make menuconfig" command to configure your
+build.
Selection of Processor Architecture and Board Type:
@@ -258,10 +200,9 @@
cd u-boot
make TQM823L_defconfig
-For the Cogent platform, you need to specify the CPU type as well;
-e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent
-directory according to the instructions in cogent/README.
-
+Note: If you're looking for the default configuration file for a board
+you're sure used to be there but is now missing, check the file
+doc/README.scrapyard for a list of no longer supported boards.
Sandbox Environment:
--------------------
@@ -274,6 +215,87 @@
See board/sandbox/README.sandbox for more details.
+Board Initialisation Flow:
+--------------------------
+
+This is the intended start-up flow for boards. This should apply for both
+SPL and U-Boot proper (i.e. they both follow the same rules).
+
+Note: "SPL" stands for "Secondary Program Loader," which is explained in
+more detail later in this file.
+
+At present, SPL mostly uses a separate code path, but the function names
+and roles of each function are the same. Some boards or architectures
+may not conform to this. At least most ARM boards which use
+CONFIG_SPL_FRAMEWORK conform to this.
+
+Execution typically starts with an architecture-specific (and possibly
+CPU-specific) start.S file, such as:
+
+ - arch/arm/cpu/armv7/start.S
+ - arch/powerpc/cpu/mpc83xx/start.S
+ - arch/mips/cpu/start.S
+
+and so on. From there, three functions are called; the purpose and
+limitations of each of these functions are described below.
+
+lowlevel_init():
+ - purpose: essential init to permit execution to reach board_init_f()
+ - no global_data or BSS
+ - there is no stack (ARMv7 may have one but it will soon be removed)
+ - must not set up SDRAM or use console
+ - must only do the bare minimum to allow execution to continue to
+ board_init_f()
+ - this is almost never needed
+ - return normally from this function
+
+board_init_f():
+ - purpose: set up the machine ready for running board_init_r():
+ i.e. SDRAM and serial UART
+ - global_data is available
+ - stack is in SRAM
+ - BSS is not available, so you cannot use global/static variables,
+ only stack variables and global_data
+
+ Non-SPL-specific notes:
+ - dram_init() is called to set up DRAM. If already done in SPL this
+ can do nothing
+
+ SPL-specific notes:
+ - you can override the entire board_init_f() function with your own
+ version as needed.
+ - preloader_console_init() can be called here in extremis
+ - should set up SDRAM, and anything needed to make the UART work
+ - these is no need to clear BSS, it will be done by crt0.S
+ - must return normally from this function (don't call board_init_r()
+ directly)
+
+Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
+this point the stack and global_data are relocated to below
+CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
+memory.
+
+board_init_r():
+ - purpose: main execution, common code
+ - global_data is available
+ - SDRAM is available
+ - BSS is available, all static/global variables can be used
+ - execution eventually continues to main_loop()
+
+ Non-SPL-specific notes:
+ - U-Boot is relocated to the top of memory and is now running from
+ there.
+
+ SPL-specific notes:
+ - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
+ CONFIG_SPL_STACK_R_ADDR points into SDRAM
+ - preloader_console_init() can be called here - typically this is
+ done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
+ spl_board_init() function containing this call
+ - loads U-Boot or (in falcon mode) Linux
+
+
+
Configuration Options:
----------------------
@@ -289,6 +311,19 @@
kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
+
+ CONFIG_SYS_FSL_HAS_CCN504
+
+ Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured:
@@ -296,63 +331,6 @@
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
-- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
- Define exactly one, e.g. CONFIG_ATSTK1002
-
-- CPU Module Type: (if CONFIG_COGENT is defined)
- Define exactly one of
- CONFIG_CMA286_60_OLD
---- FIXME --- not tested yet:
- CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
- CONFIG_CMA287_23, CONFIG_CMA287_50
-
-- Motherboard Type: (if CONFIG_COGENT is defined)
- Define exactly one of
- CONFIG_CMA101, CONFIG_CMA102
-
-- Motherboard I/O Modules: (if CONFIG_COGENT is defined)
- Define one or more of
- CONFIG_CMA302
-
-- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
- Define one or more of
- CONFIG_LCD_HEARTBEAT - update a character position on
- the LCD display every second with
- a "rotator" |\-/|\-/
-
-- Marvell Family Member
- CONFIG_SYS_MVFS - define it if you want to enable
- multiple fs option at one time
- for marvell soc family
-
-- 8xx CPU Options: (if using an MPC8xx CPU)
- CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
- get_gclk_freq() cannot work
- e.g. if there is no 32KHz
- reference PIT/RTC clock
- CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK
- or XTAL/EXTAL)
-
-- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
- CONFIG_SYS_8xx_CPUCLK_MIN
- CONFIG_SYS_8xx_CPUCLK_MAX
- CONFIG_8xx_CPUCLK_DEFAULT
- See doc/README.MPC866
-
- CONFIG_SYS_MEASURE_CPUCLK
-
- Define this to measure the actual CPU clock instead
- of relying on the correctness of the configured
- values. Mostly useful for board bringup to make sure
- the PLL is locked at the intended frequency. Note
- that this requires a (stable) reference clock (32 kHz
- RTC clock or CONFIG_SYS_8XX_XIN)
-
- CONFIG_SYS_DELAYED_ICACHE
-
- Define this option if you want to enable the
- ICache only when Code runs from RAM.
-
- 85xx CPU Options:
CONFIG_SYS_PPC64
@@ -371,15 +349,6 @@
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
- CONFIG_SYS_PPC_E500_DEBUG_TLB
-
- Enables a temporary TLB entry to be used during boot to work
- around limitations in e500v1 and e500v2 external debugger
- support. This reduces the portions of the boot code where
- breakpoints and single stepping do not work. The value of this
- symbol should be set to the TLB1 entry to be used for this
- purpose.
-
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
@@ -435,19 +404,13 @@
CONFIG_SYS_CPC_REINIT_F
This CONFIG is defined when the CPC is configured as SRAM at the
- time of U-boot entry and is required to be re-initialized.
+ time of U-Boot entry and is required to be re-initialized.
CONFIG_DEEP_SLEEP
Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
- CONFIG_SYS_GENERIC_GLOBAL_DATA
- Defines global data is initialized in generic board board_init_f().
- If this macro is defined, global data is created and cleared in
- generic board board_init_f(). Without this macro, architecture/board
- should initialize global data before calling board_init_f().
-
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
@@ -486,7 +449,7 @@
implemetation.
CONFIG_SYS_FSL_DDR2
- Board config to use DDR2. It can be eanbeld for SoCs with
+ Board config to use DDR2. It can be enabled for SoCs with
Freescale DDR2 or DDR3 controllers, depending on the board
implementation.
@@ -508,6 +471,12 @@
CONFIG_SYS_FSL_IFC_LE
Defines the IFC controller register space as Little Endian
+ CONFIG_SYS_FSL_IFC_CLK_DIV
+ Defines divider of platform clock(clock input to IFC controller).
+
+ CONFIG_SYS_FSL_LBC_CLK_DIV
+ Defines divider of platform clock(clock input to eLBC controller).
+
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details
@@ -543,26 +512,15 @@
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
+ CONFIG_SYS_FSL_HAS_DP_DDR
+ Defines the SoC has DP-DDR used for DPAA.
+
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
CONFIG_SYS_FSL_SEC_LE
Defines the SEC controller register space as Little Endian
-- Intel Monahans options:
- CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
-
- Defines the Monahans run mode to oscillator
- ratio. Valid values are 8, 16, 24, 31. The core
- frequency is this value multiplied by 13 MHz.
-
- CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
-
- Defines the Monahans turbo mode to oscillator
- ratio. Valid values are 1 (default if undefined) and
- 2. The core frequency as calculated above is multiplied
- by this value.
-
- MIPS CPU options:
CONFIG_SYS_INIT_SP_OFFSET
@@ -570,25 +528,6 @@
pointer. This is needed for the temporary stack before
relocation.
- CONFIG_SYS_MIPS_CACHE_MODE
-
- Cache operation mode for the MIPS CPU.
- See also arch/mips/include/asm/mipsregs.h.
- Possible values are:
- CONF_CM_CACHABLE_NO_WA
- CONF_CM_CACHABLE_WA
- CONF_CM_UNCACHED
- CONF_CM_CACHABLE_NONCOHERENT
- CONF_CM_CACHABLE_CE
- CONF_CM_CACHABLE_COW
- CONF_CM_CACHABLE_CUW
- CONF_CM_CACHABLE_ACCELERATED
-
- CONFIG_SYS_XWAY_EBU_BOOTCFG
-
- Special option for Lantiq XWAY SoCs for booting from NOR flash.
- See also arch/mips/cpu/mips32/start.S.
-
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
@@ -601,140 +540,20 @@
Select high exception vectors of the ARM core, e.g., do not
clear the V bit of the c1 register of CP15.
- CONFIG_SYS_THUMB_BUILD
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
- Use this flag to build U-Boot using the Thumb instruction
- set for ARM architectures. Thumb instruction set provides
- better code density. For ARM architectures that support
- Thumb2 this flag will result in Thumb2 code generated by
- GCC.
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
- CONFIG_ARM_ERRATA_716044
- CONFIG_ARM_ERRATA_742230
- CONFIG_ARM_ERRATA_743622
- CONFIG_ARM_ERRATA_751472
- CONFIG_ARM_ERRATA_794072
- CONFIG_ARM_ERRATA_761320
+- Tegra SoC options:
+ CONFIG_TEGRA_SUPPORT_NON_SECURE
- If set, the workarounds for these ARM errata are applied early
- during U-Boot startup. Note that these options force the
- workarounds to be applied; no CPU-type/version detection
- exists, unlike the similar options in the Linux kernel. Do not
- set these options unless they apply!
-
-- Driver Model
- Driver model is a new framework for devices in U-Boot
- introduced in early 2014. U-Boot is being progressively
- moved over to this. It offers a consistent device structure,
- supports grouping devices into classes and has built-in
- handling of platform data and device tree.
-
- To enable transition to driver model in a relatively
- painful fashion, each subsystem can be independently
- switched between the legacy/ad-hoc approach and the new
- driver model using the options below. Also, many uclass
- interfaces include compatibility features which may be
- removed once the conversion of that subsystem is complete.
- As a result, the API provided by the subsystem may in fact
- not change with driver model.
-
- See doc/driver-model/README.txt for more information.
-
- CONFIG_DM
-
- Enable driver model. This brings in the core support,
- including scanning of platform data on start-up. If
- CONFIG_OF_CONTROL is enabled, the device tree will be
- scanned also when available.
-
- CONFIG_CMD_DM
-
- Enable driver model test commands. These allow you to print
- out the driver model tree and the uclasses.
-
- CONFIG_DM_DEMO
-
- Enable some demo devices and the 'demo' command. These are
- really only useful for playing around while trying to
- understand driver model in sandbox.
-
- CONFIG_SPL_DM
-
- Enable driver model in SPL. You will need to provide a
- suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
- consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
- In most cases driver model will only allocate a few uclasses
- and devices in SPL, so 1KB should be enable. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
- it.
-
- CONFIG_DM_SERIAL
-
- Enable driver model for serial. This replaces
- drivers/serial/serial.c with the serial uclass, which
- implements serial_putc() etc. The uclass interface is
- defined in include/serial.h.
-
- CONFIG_DM_GPIO
-
- Enable driver model for GPIO access. The standard GPIO
- interface (gpio_get_value(), etc.) is then implemented by
- the GPIO uclass. Drivers provide methods to query the
- particular GPIOs that they provide. The uclass interface
- is defined in include/asm-generic/gpio.h.
-
- CONFIG_DM_SPI
-
- Enable driver model for SPI. The SPI slave interface
- (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
- the SPI uclass. Drivers provide methods to access the SPI
- buses that they control. The uclass interface is defined in
- include/spi.h. The existing spi_slave structure is attached
- as 'parent data' to every slave on each bus. Slaves
- typically use driver-private data instead of extending the
- spi_slave structure.
-
- CONFIG_DM_SPI_FLASH
-
- Enable driver model for SPI flash. This SPI flash interface
- (spi_flash_probe(), spi_flash_write(), etc.) is then
- implemented by the SPI flash uclass. There is one standard
- SPI flash driver which knows how to probe most chips
- supported by U-Boot. The uclass interface is defined in
- include/spi_flash.h, but is currently fully compatible
- with the old interface to avoid confusion and duplication
- during the transition parent. SPI and SPI flash must be
- enabled together (it is not possible to use driver model
- for one and not the other).
-
- CONFIG_DM_CROS_EC
-
- Enable driver model for the Chrome OS EC interface. This
- allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
- but otherwise makes few changes. Since cros_ec also supports
- I2C and LPC (which don't support driver model yet), a full
- conversion is not yet possible.
-
-
- ** Code size options: The following options are enabled by
- default except in SPL. Enable them explicitly to get these
- features in SPL.
-
- CONFIG_DM_WARN
-
- Enable the dm_warn() function. This can use up quite a bit
- of space for its strings.
-
- CONFIG_DM_STDIO
-
- Enable registering a serial device with the stdio library.
-
- CONFIG_DM_DEVICE_REMOVE
-
- Enable removing of devices.
-
+ Support executing U-Boot in non-secure (NS) mode. Certain
+ impossible actions will be skipped if the CPU is in NS mode,
+ such as ARM architectural timer initialization.
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
@@ -767,10 +586,6 @@
* Adds the "fdt" command
* The bootm command automatically updates the fdt
- OF_CPU - The proper name of the cpus node (only required for
- MPC512X and MPC5xxx based boards).
- OF_SOC - The proper name of the soc node (only required for
- MPC512X and MPC5xxx based boards).
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
@@ -789,11 +604,6 @@
This causes ft_system_setup() to be called before booting
the kernel.
- CONFIG_OF_BOOT_CPU
-
- This define fills in the correct boot CPU in the boot
- param header, the default value is zero if undefined.
-
CONFIG_OF_IDE_FIXUP
U-Boot can detect if an IDE device is present or not.
@@ -816,18 +626,10 @@
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
- environments variables: bootfile, ipaddr, serverip, hostname.
+ environments variables: bootdev, bootfile, ipaddr, netmask,
+ serverip, gatewayip, hostname, othbootargs.
It loads the vxWorks image pointed bootfile.
- CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
- CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
- CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
- CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
-
- CONFIG_SYS_VXWORKS_ADD_PARAMS
-
- Add it at the end of the bootline. E.g "u=username pw=secret"
-
Note: If a "bootargs" environment is defined, it will overwride
the defaults discussed just above.
@@ -862,145 +664,15 @@
define this to a list of base addresses for each (supported)
port. See e.g. include/configs/versatile.h
- CONFIG_PL011_SERIAL_RLCR
-
- Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
- have separate receive and transmit line control registers. Set
- this variable to initialize the extra register.
-
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-
- On some platforms (e.g. U8500) U-Boot is loaded by a second stage
- boot loader that has already initialized the UART. Define this
- variable to flush the UART at init time.
-
CONFIG_SERIAL_HW_FLOW_CONTROL
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Console Interface:
- Depending on board, define exactly one serial port
- (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
- CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
- console by defining CONFIG_8xx_CONS_NONE
-
- Note: if CONFIG_8xx_CONS_NONE is defined, the serial
- port routines must be defined elsewhere
- (i.e. serial_init(), serial_getc(), ...)
-
- CONFIG_CFB_CONSOLE
- Enables console device for a color framebuffer. Needs following
- defines (cf. smiLynxEM, i8042)
- VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
- (default big endian)
- VIDEO_HW_RECTFILL graphic chip supports
- rectangle fill
- (cf. smiLynxEM)
- VIDEO_HW_BITBLT graphic chip supports
- bit-blit (cf. smiLynxEM)
- VIDEO_VISIBLE_COLS visible pixel columns
- (cols=pitch)
- VIDEO_VISIBLE_ROWS visible pixel rows
- VIDEO_PIXEL_SIZE bytes per pixel
- VIDEO_DATA_FORMAT graphic data format
- (0-5, cf. cfb_console.c)
- VIDEO_FB_ADRS framebuffer address
- VIDEO_KBD_INIT_FCT keyboard int fct
- (i.e. i8042_kbd_init())
- VIDEO_TSTC_FCT test char fct
- (i.e. i8042_tstc)
- VIDEO_GETC_FCT get char fct
- (i.e. i8042_getc)
- CONFIG_CONSOLE_CURSOR cursor drawing on/off
- (requires blink timer
- cf. i8042.c)
- CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
- CONFIG_CONSOLE_TIME display time/date info in
- upper right corner
- (requires CONFIG_CMD_DATE)
- CONFIG_VIDEO_LOGO display Linux logo in
- upper left corner
- CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of
- linux_logo.h for logo.
- Requires CONFIG_VIDEO_LOGO
- CONFIG_CONSOLE_EXTRA_INFO
- additional board info beside
- the logo
-
- When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
- a limited number of ANSI escape sequences (cursor control,
- erase functions and limited graphics rendition control).
-
- When CONFIG_CFB_CONSOLE is defined, video console is
- default i/o. Serial console can be forced with
- environment 'console=serial'.
-
- When CONFIG_SILENT_CONSOLE is defined, all console
- messages (by U-Boot and Linux!) can be silenced with
- the "silent" environment variable. See
- doc/README.silent for more information.
-
- CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
- is 0x00.
- CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
- is 0xa0.
-
- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
- CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
-
-- Console Rx buffer length
- With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
- the maximum receive buffer length for the SMC.
- This option is actual only for 82xx and 8xx possible.
- If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
- must be defined, to setup the maximum idle timeout for
- the SMC.
-
-- Pre-Console Buffer:
- Prior to the console being initialised (i.e. serial UART
- initialised etc) all console output is silently discarded.
- Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
- buffer any console messages prior to the console being
- initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
- bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
- a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
- bytes are output before the console is initialised, the
- earlier bytes are discarded.
-
- 'Sane' compilers will generate smaller code if
- CONFIG_PRE_CON_BUF_SZ is a power of 2
-
-- Safe printf() functions
- Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
- the printf() functions. These are defined in
- include/vsprintf.h and include snprintf(), vsnprintf() and
- so on. Code size increase is approximately 300-500 bytes.
- If this option is not given then these functions will
- silently discard their buffer size argument - this means
- you are not getting any overflow checking in this case.
-
-- Boot Delay: CONFIG_BOOTDELAY - in seconds
- Delay before automatically booting the default image;
- set to -1 to disable autoboot.
- set to -2 to autoboot with no delay and not check for abort
- (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
-
- See doc/README.autoboot for these options that
- work with CONFIG_BOOTDELAY. None are required.
- CONFIG_BOOT_RETRY_TIME
- CONFIG_BOOT_RETRY_MIN
- CONFIG_AUTOBOOT_KEYED
- CONFIG_AUTOBOOT_PROMPT
- CONFIG_AUTOBOOT_DELAY_STR
- CONFIG_AUTOBOOT_STOP_STR
- CONFIG_AUTOBOOT_DELAY_STR2
- CONFIG_AUTOBOOT_STOP_STR2
- CONFIG_ZERO_BOOTDELAY_CHECK
- CONFIG_RESET_TO_RETRY
- Autoboot Command:
CONFIG_BOOTCOMMAND
@@ -1009,33 +681,12 @@
when no character is read on the console interface
within "Boot Delay" after reset.
- CONFIG_BOOTARGS
- This can be used to pass arguments to the bootm
- command. The value of CONFIG_BOOTARGS goes into the
- environment value "bootargs".
-
CONFIG_RAMBOOT and CONFIG_NFSBOOT
The value of these goes into the environment as
"ramboot" and "nfsboot" respectively, and can be used
as a convenience, when switching between booting from
RAM and NFS.
-- Bootcount:
- CONFIG_BOOTCOUNT_LIMIT
- Implements a mechanism for detecting a repeating reboot
- cycle, see:
- http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
-
- CONFIG_BOOTCOUNT_ENV
- If no softreset save registers are found on the hardware
- "bootcount" is stored in the environment. To prevent a
- saveenv on all reboots, the environment variable
- "upgrade_available" is used. If "upgrade_available" is
- 0, "bootcount" is always 0, if "upgrade_available" is
- 1 "bootcount" is incremented in the environment.
- So the Userspace Applikation must set the "upgrade_available"
- and "bootcount" variable to 0, if a boot was successfully.
-
- Pre-Boot Commands:
CONFIG_PREBOOT
@@ -1066,146 +717,13 @@
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
-- Monitor Functions:
- Monitor commands can be included or excluded
- from the build by using the #include files
- <config_cmd_all.h> and #undef'ing unwanted
- commands, or using <config_cmd_default.h>
- and augmenting with additional #define's
- for wanted commands.
-
- The default command configuration includes all commands
- except those marked below with a "*".
-
- CONFIG_CMD_AES AES 128 CBC encrypt/decrypt
- CONFIG_CMD_ASKENV * ask for env variable
- CONFIG_CMD_BDI bdinfo
- CONFIG_CMD_BEDBUG * Include BedBug Debugger
- CONFIG_CMD_BMP * BMP support
- CONFIG_CMD_BSP * Board specific commands
- CONFIG_CMD_BOOTD bootd
- CONFIG_CMD_BOOTI * ARM64 Linux kernel Image support
- CONFIG_CMD_CACHE * icache, dcache
- CONFIG_CMD_CLK * clock command support
- CONFIG_CMD_CONSOLE coninfo
- CONFIG_CMD_CRC32 * crc32
- CONFIG_CMD_DATE * support for RTC, date/time...
- CONFIG_CMD_DHCP * DHCP support
- CONFIG_CMD_DIAG * Diagnostics
- CONFIG_CMD_DS4510 * ds4510 I2C gpio commands
- CONFIG_CMD_DS4510_INFO * ds4510 I2C info command
- CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd
- CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
- CONFIG_CMD_DTT * Digital Therm and Thermostat
- CONFIG_CMD_ECHO echo arguments
- CONFIG_CMD_EDITENV edit env variable
- CONFIG_CMD_EEPROM * EEPROM read/write support
- CONFIG_CMD_ELF * bootelf, bootvx
- CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
- CONFIG_CMD_ENV_FLAGS * display details about env flags
- CONFIG_CMD_ENV_EXISTS * check existence of env variable
- CONFIG_CMD_EXPORTENV * export the environment
- CONFIG_CMD_EXT2 * ext2 command support
- CONFIG_CMD_EXT4 * ext4 command support
- CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
- that work for multiple fs types
- CONFIG_CMD_FS_UUID * Look up a filesystem UUID
- CONFIG_CMD_SAVEENV saveenv
- CONFIG_CMD_FDC * Floppy Disk Support
- CONFIG_CMD_FAT * FAT command support
- CONFIG_CMD_FLASH flinfo, erase, protect
- CONFIG_CMD_FPGA FPGA device initialization support
- CONFIG_CMD_FUSE * Device fuse support
- CONFIG_CMD_GETTIME * Get time since boot
- CONFIG_CMD_GO * the 'go' command (exec code)
- CONFIG_CMD_GREPENV * search environment
- CONFIG_CMD_HASH * calculate hash / digest
- CONFIG_CMD_HWFLOW * RTS/CTS hw flow control
- CONFIG_CMD_I2C * I2C serial bus support
- CONFIG_CMD_IDE * IDE harddisk support
- CONFIG_CMD_IMI iminfo
- CONFIG_CMD_IMLS List all images found in NOR flash
- CONFIG_CMD_IMLS_NAND * List all images found in NAND flash
- CONFIG_CMD_IMMAP * IMMR dump support
- CONFIG_CMD_IOTRACE * I/O tracing for debugging
- CONFIG_CMD_IMPORTENV * import an environment
- CONFIG_CMD_INI * import data from an ini file into the env
- CONFIG_CMD_IRQ * irqinfo
- CONFIG_CMD_ITEST Integer/string test of 2 values
- CONFIG_CMD_JFFS2 * JFFS2 Support
- CONFIG_CMD_KGDB * kgdb
- CONFIG_CMD_LDRINFO * ldrinfo (display Blackfin loader)
- CONFIG_CMD_LINK_LOCAL * link-local IP address auto-configuration
- (169.254.*.*)
- CONFIG_CMD_LOADB loadb
- CONFIG_CMD_LOADS loads
- CONFIG_CMD_MD5SUM * print md5 message digest
- (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
- CONFIG_CMD_MEMINFO * Display detailed memory information
- CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
- loop, loopw
- CONFIG_CMD_MEMTEST * mtest
- CONFIG_CMD_MISC Misc functions like sleep etc
- CONFIG_CMD_MMC * MMC memory mapped support
- CONFIG_CMD_GPT * GPT command
- CONFIG_CMD_MII * MII utility commands
- CONFIG_CMD_MTDPARTS * MTD partition support
- CONFIG_CMD_NAND * NAND support
- CONFIG_CMD_NET bootp, tftpboot, rarpboot
- CONFIG_CMD_NFS NFS support
- CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
- CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
- CONFIG_CMD_PCI * pciinfo
- CONFIG_CMD_PCMCIA * PCMCIA support
- CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
- host
- CONFIG_CMD_PORTIO * Port I/O
- CONFIG_CMD_READ * Read raw data from partition
- CONFIG_CMD_REGINFO * Register dump
- CONFIG_CMD_RUN run command in env variable
- CONFIG_CMD_SANDBOX * sb command to access sandbox features
- CONFIG_CMD_SAVES * save S record dump
- CONFIG_CMD_SCSI * SCSI Support
- CONFIG_CMD_SDRAM * print SDRAM configuration information
- (requires CONFIG_CMD_I2C)
- CONFIG_CMD_SETGETDCR Support for DCR Register access
- (4xx only)
- CONFIG_CMD_SF * Read/write/erase SPI NOR flash
- CONFIG_CMD_SHA1SUM * print sha1 memory digest
- (requires CONFIG_CMD_MEMORY)
- CONFIG_CMD_SOFTSWITCH * Soft switch setting command for BF60x
- CONFIG_CMD_SOURCE "source" command Support
- CONFIG_CMD_SPI * SPI serial bus support
- CONFIG_CMD_TFTPSRV * TFTP transfer in server mode
- CONFIG_CMD_TFTPPUT * TFTP put command (upload)
- CONFIG_CMD_TIME * run command and report execution time (ARM specific)
- CONFIG_CMD_TIMER * access to the system tick timer
- CONFIG_CMD_USB * USB support
- CONFIG_CMD_CDP * Cisco Discover Protocol support
- CONFIG_CMD_MFSL * Microblaze FSL support
- CONFIG_CMD_XIMG Load part of Multi Image
- CONFIG_CMD_UUID * Generate random UUID or GUID string
-
- EXAMPLE: If you want all functions except of network
- support you can write:
-
- #include "config_cmd_all.h"
- #undef CONFIG_CMD_NET
-
- Other Commands:
- fdt (flattened device tree) command: CONFIG_OF_LIBFDT
-
- Note: Don't enable the "icache" and "dcache" commands
- (configuration option CONFIG_CMD_CACHE) unless you know
- what you (and your U-Boot users) are doing. Data
- cache cannot be enabled on systems like the 8xx or
- 8260 (where accesses to the IMMR region must be
- uncached), and it cannot be disabled on all other
- systems where we (mis-) use the data cache to hold an
- initial stack and some data.
-
-
- XXX - this list needs to get updated!
+- Removal of commands
+ If no commands are needed to boot, you can disable
+ CONFIG_CMDLINE to remove them. In this case, the command line
+ will not be available, and when U-Boot wants to execute the
+ boot command (on start-up) it will call board_run_command()
+ instead. This can reduce image size significantly for very
+ simple boot procedures.
- Regular expression support:
CONFIG_REGEX
@@ -1223,14 +741,14 @@
tree is available in the global data as gd->fdt_blob.
U-Boot needs to get its device tree from somewhere. This can
- be done using one of the two options below:
+ be done using one of the three options below:
CONFIG_OF_EMBED
If this variable is defined, U-Boot will embed a device tree
binary in its image. This device tree file should be in the
board directory and called <soc>-<board>.dts. The binary file
is then picked up in board_init_f() and made available through
- the global data structure as gd->blob.
+ the global data structure as gd->fdt_blob.
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
@@ -1244,11 +762,17 @@
still use the individual files if you need something more
exotic.
+ CONFIG_OF_BOARD
+ If this variable is defined, U-Boot will use the device tree
+ provided by the board at runtime instead of embedding one with
+ the image. Only boards defining board_fdt_blob_setup() support
+ this option (see include/fdtdec.h file).
+
- Watchdog:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
support for the SoC. There must be support in the SoC
- specific code for a watchdog. For the 8xx and 8260
+ specific code for a watchdog. For the 8xx
CPUs, the SIU Watchdog feature is enabled in the SYPCR
register. When supported for a specific SoC is
available, then no further board specific code should
@@ -1259,13 +783,8 @@
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
-- U-Boot Version:
- CONFIG_VERSION_VARIABLE
- If this variable is defined, an environment variable
- named "ver" is created by U-Boot showing the U-Boot
- version as printed by the "version" command.
- Any change to this variable will be reverted at the
- next reset.
+ CONFIG_AT91_HW_WDT_TIMEOUT
+ specify the timeout in seconds. default 2 seconds.
- Real-Time Clock:
@@ -1273,7 +792,6 @@
has to be selected, too. Define exactly one of the
following options:
- CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx
CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
CONFIG_RTC_MC146818 - use MC146818 RTC
@@ -1284,7 +802,7 @@
CONFIG_RTC_DS164x - use Dallas DS164x RTC
CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
- CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
+ CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
CONFIG_SYS_RV3029_TCR - enable trickle charger on
RV3029 RTC.
@@ -1333,16 +851,11 @@
- Partition Labels (disklabels) Supported:
Zero or more of the following:
CONFIG_MAC_PARTITION Apple's MacOS partition table.
- CONFIG_DOS_PARTITION MS Dos partition table, traditional on the
- Intel architecture, USB sticks, etc.
CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc.
CONFIG_EFI_PARTITION GPT partition table, common when EFI is the
bootloader. Note 2TB partition limit; see
disk/part_efi.c
- CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
-
- If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
- CONFIG_CMD_SCSI) you must configure support for at
+ CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
- IDE Reset method:
@@ -1372,16 +885,11 @@
Default is 32bit.
- SCSI Support:
- At the moment only there is only support for the
- SYM53C8XX SCSI controller; define
- CONFIG_SCSI_SYM53C8XX to enable it.
-
CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
maximum numbers of LUNs, SCSI ID's and target
devices.
- CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
@@ -1399,13 +907,6 @@
Allow generic access to the SPI bus on the Intel 8257x, for
example with the "sspi" command.
- CONFIG_CMD_E1000
- Management command for E1000 devices. When used on devices
- with SPI support you can reprogram the EEPROM from U-Boot.
-
- CONFIG_E1000_FALLBACK_MAC
- default MAC for empty EEPROM after production.
-
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
@@ -1440,10 +941,6 @@
CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
- CONFIG_LAN91C96_BASE
- Define this to hold the physical address
- of the LAN91C96's I/O space
-
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
@@ -1461,9 +958,6 @@
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
- CONFIG_DRIVER_TI_EMAC
- Support for davinci emac
-
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
Define this if you have more then 3 PHYs.
@@ -1479,21 +973,6 @@
control registers. This behavior won't affect the
correctnessof 10/100 link speed update.
- CONFIG_SMC911X
- Support for SMSC's LAN911x and LAN921x chips
-
- CONFIG_SMC911X_BASE
- Define this to hold the physical address
- of the device (I/O space)
-
- CONFIG_SMC911X_32_BIT
- Define this if data bus is 32 bits
-
- CONFIG_SMC911X_16_BIT
- Define this if data bus is 16 bits. If your processor
- automatically converts one 32 bit word to two 16 bit
- words you may also try CONFIG_SMC911X_32_BIT.
-
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller
@@ -1508,25 +987,30 @@
- PWM Support:
CONFIG_PWM_IMX
- Support for PWM modul on the imx6.
+ Support for PWM module on the imx6.
- TPM Support:
CONFIG_TPM
Support TPM devices.
- CONFIG_TPM_TIS_I2C
- Support for i2c bus TPM devices. Only one device
+ CONFIG_TPM_TIS_INFINEON
+ Support for Infineon i2c bus TPM devices. Only one device
per system is supported at this time.
- CONFIG_TPM_TIS_I2C_BUS_NUMBER
- Define the the i2c bus number for the TPM device
-
- CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
- Define the TPM's address on the i2c bus
-
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
Define the burst count bytes upper limit
+ CONFIG_TPM_ST33ZP24
+ Support for STMicroelectronics TPM devices. Requires DM_TPM support.
+
+ CONFIG_TPM_ST33ZP24_I2C
+ Support for STMicroelectronics ST33ZP24 I2C devices.
+ Requires TPM_ST33ZP24 and I2C.
+
+ CONFIG_TPM_ST33ZP24_SPI
+ Support for STMicroelectronics ST33ZP24 SPI devices.
+ Requires TPM_ST33ZP24 and SPI.
+
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
@@ -1539,11 +1023,6 @@
to. Contemporary x86 systems usually map it at
0xfed40000.
- CONFIG_CMD_TPM
- Add tpm monitor functions.
- Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
- provides monitor access to authorized functions.
-
CONFIG_TPM
Define this to enable the TPM support library which provides
functional interfaces to some TPM commands.
@@ -1555,7 +1034,7 @@
- USB Support:
At the moment only the UHCI host controller is
- supported (PIP405, MIP405, MPC5200); define
+ supported (PIP405, MIP405); define
CONFIG_USB_UHCI to enable it.
define CONFIG_USB_KEYBOARD to enable the USB Keyboard
and define CONFIG_USB_STORAGE to enable the USB
@@ -1563,19 +1042,6 @@
Note:
Supported are USB Keyboards and USB Floppy drives
(TEAC FD-05PUB).
- MPC5200 USB requires additional defines:
- CONFIG_USB_CLOCK
- for 528 MHz Clock: 0x0001bbbb
- CONFIG_PSC3_USB
- for USB on PSC3
- CONFIG_USB_CONFIG
- for differential drivers: 0x00001000
- for single ended drivers: 0x00005000
- for differential drivers on PSC3: 0x00000100
- for single ended drivers on PSC3: 0x00004100
- CONFIG_SYS_USB_EVENT_POLL
- May be defined to allow interrupt polling
- instead of using asynchronous interrupts
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
@@ -1618,15 +1084,6 @@
Define this if you want stdin, stdout &/or stderr to
be set to usbtty.
- mpc8xx:
- CONFIG_SYS_USB_EXTC_CLK 0xBLAH
- Derive USB clock from external clock "blah"
- - CONFIG_SYS_USB_EXTC_CLK 0x02
-
- CONFIG_SYS_USB_BRG_CLK 0xBLAH
- Derive USB clock from brgclk
- - CONFIG_SYS_USB_BRG_CLK 0x04
-
If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
or directly in usbd_vendor_info.h. If you don't define
@@ -1682,26 +1139,13 @@
CONFIG_SH_MMCIF_CLK
Define the clock frequency for MMCIF
- CONFIG_GENERIC_MMC
- Enable the generic MMC driver
-
CONFIG_SUPPORT_EMMC_BOOT
Enable some additional features of the eMMC boot partitions.
- CONFIG_SUPPORT_EMMC_RPMB
- Enable the commands for reading, writing and programming the
- key for the Replay Protection Memory Block partition in eMMC.
-
- USB Device Firmware Update (DFU) class support:
- CONFIG_DFU_FUNCTION
+ CONFIG_DFU_OVER_USB
This enables the USB portion of the DFU USB class
- CONFIG_CMD_DFU
- This enables the command "dfu" which is used to have
- U-Boot create a DFU class device via USB. This command
- requires that the "dfu_alt_info" environment variable be
- set and define the alt settings to expose to the host.
-
CONFIG_DFU_MMC
This enables support for exposing (e)MMC devices via DFU.
@@ -1737,144 +1181,26 @@
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
-- USB Device Android Fastboot support:
- CONFIG_CMD_FASTBOOT
- This enables the command "fastboot" which enables the Android
- fastboot mode for the platform's USB device. Fastboot is a USB
- protocol for downloading images, flashing and device control
- used on Android devices.
- See doc/README.android-fastboot for more information.
-
- CONFIG_ANDROID_BOOT_IMAGE
- This enables support for booting images which use the Android
- image format header.
-
- CONFIG_USB_FASTBOOT_BUF_ADDR
- The fastboot protocol requires a large memory buffer for
- downloads. Define this to the starting RAM address to use for
- downloaded images.
-
- CONFIG_USB_FASTBOOT_BUF_SIZE
- The fastboot protocol requires a large memory buffer for
- downloads. This buffer should be as large as possible for a
- platform. Define this to the size available RAM for fastboot.
-
- CONFIG_FASTBOOT_FLASH
- The fastboot protocol includes a "flash" command for writing
- the downloaded image to a non-volatile storage device. Define
- this to enable the "fastboot flash" command.
-
- CONFIG_FASTBOOT_FLASH_MMC_DEV
- The fastboot "flash" command requires additional information
- regarding the non-volatile storage device. Define this to
- the eMMC device that fastboot should use to store the image.
-
- CONFIG_FASTBOOT_GPT_NAME
- The fastboot "flash" command supports writing the downloaded
- image to the Protective MBR and the Primary GUID Partition
- Table. (Additionally, this downloaded image is post-processed
- to generate and write the Backup GUID Partition Table.)
- This occurs when the specified "partition name" on the
- "fastboot flash" command line matches this value.
- Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
-
- Journaling Flash filesystem support:
- CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
- CONFIG_JFFS2_NAND_DEV
+ CONFIG_JFFS2_NAND
Define these for a default partition on a NAND device
CONFIG_SYS_JFFS2_FIRST_SECTOR,
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
- CONFIG_SYS_JFFS_CUSTOM_PART
- Define this to create an own partition. You have to provide a
- function struct part_info* jffs2_part_info(int part_num)
-
- If you define only one JFFS2 partition you may also want to
- #define CONFIG_SYS_JFFS_SINGLE_PART 1
- to disable the command chpart. This is the default when you
- have not defined a custom partition
-
-- FAT(File Allocation Table) filesystem write function support:
- CONFIG_FAT_WRITE
-
- Define this to enable support for saving memory data as a
- file in FAT formatted partition.
-
- This will also enable the command "fatwrite" enabling the
- user to write files to FAT.
-
-CBFS (Coreboot Filesystem) support
- CONFIG_CMD_CBFS
-
- Define this to enable support for reading from a Coreboot
- filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
- and cbfsload.
-
-- FAT(File Allocation Table) filesystem cluster size:
- CONFIG_FS_FAT_MAX_CLUSTSIZE
-
- Define the max cluster size for fat operations else
- a default value of 65536 will be defined.
-
- Keyboard Support:
- CONFIG_ISA_KEYBOARD
+ See Kconfig help for available keyboard drivers.
- Define this to enable standard (PC-Style) keyboard
- support
+ CONFIG_KEYBOARD
- CONFIG_I8042_KBD
- Standard PC keyboard driver with US (is default) and
- GERMAN key layout (switch via environment 'keymap=de') support.
- Export function i8042_kbd_init, i8042_tstc and i8042_getc
- for cfb_console. Supports cursor blinking.
-
- CONFIG_CROS_EC_KEYB
- Enables a Chrome OS keyboard using the CROS_EC interface.
- This uses CROS_EC to communicate with a second microcontroller
- which provides key scans on request.
+ Define this to enable a custom keyboard support.
+ This simply calls drv_keyboard_init() which must be
+ defined in your board-specific files. This option is deprecated
+ and is only used by novena. For new boards, use driver model
+ instead.
- Video support:
- CONFIG_VIDEO
-
- Define this to enable video support (for output to
- video).
-
- CONFIG_VIDEO_CT69000
-
- Enable Chips & Technologies 69000 Video chip
-
- CONFIG_VIDEO_SMI_LYNXEM
- Enable Silicon Motion SMI 712/710/810 Video chip. The
- video output is selected via environment 'videoout'
- (1 = LCD and 2 = CRT). If videoout is undefined, CRT is
- assumed.
-
- For the CT69000 and SMI_LYNXEM drivers, videomode is
- selected via environment 'videomode'. Two different ways
- are possible:
- - "videomode=num" 'num' is a standard LiLo mode numbers.
- Following standard modes are supported (* is default):
-
- Colors 640x480 800x600 1024x768 1152x864 1280x1024
- -------------+---------------------------------------------
- 8 bits | 0x301* 0x303 0x305 0x161 0x307
- 15 bits | 0x310 0x313 0x316 0x162 0x319
- 16 bits | 0x311 0x314 0x317 0x163 0x31A
- 24 bits | 0x312 0x315 0x318 ? 0x31B
- -------------+---------------------------------------------
- (i.e. setenv videomode 317; saveenv; reset;)
-
- - "videomode=bootargs" all the video parameters are parsed
- from the bootargs. (See drivers/video/videomodes.c)
-
-
- CONFIG_VIDEO_SED13806
- Enable Epson SED13806 driver. This driver supports 8bpp
- and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
- or CONFIG_VIDEO_SED13806_16BPP
-
CONFIG_FSL_DIU_FB
Enable the Freescale DIU video driver. Reference boards for
SOCs that have a DIU should define this macro to enable DIU
@@ -1882,7 +1208,6 @@
CONFIG_SYS_DIU_ADDR
CONFIG_VIDEO
- CONFIG_CMD_BMP
CONFIG_CFB_CONSOLE
CONFIG_VIDEO_SW_CURSOR
CONFIG_VGA_AS_SINGLE_DEVICE
@@ -1891,24 +1216,9 @@
The DIU driver will look for the 'video-mode' environment
variable, and if defined, enable the DIU as a console during
- boot. See the documentation file README.video for a
+ boot. See the documentation file doc/README.video for a
description of this variable.
- CONFIG_VIDEO_VGA
-
- Enable the VGA video / BIOS for x86. The alternative if you
- are using coreboot is to use the coreboot frame buffer
- driver.
-
-
-- Keyboard Support:
- CONFIG_KEYBOARD
-
- Define this to enable a custom keyboard support.
- This simply calls drv_keyboard_init() which must be
- defined in your board-specific files.
- The only board using this so far is RBC823.
-
- LCD Support: CONFIG_LCD
Define this to enable LCD support (for output to LCD
@@ -1958,9 +1268,6 @@
320x240. Black & white.
- Normally display is black on white background; define
- CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
-
CONFIG_LCD_ALIGNMENT
Normally the LCD is page-aligned (typically 4KB). If this is
@@ -1969,12 +1276,26 @@
here, since it is cheaper to change data cache settings on
a per-section basis.
- CONFIG_CONSOLE_SCROLL_LINES
- When the console need to be scrolled, this is the number of
- lines to scroll by. It defaults to 1. Increasing this makes
- the console jump but can help speed up operation when scrolling
- is slow.
+ CONFIG_LCD_ROTATION
+
+ Sometimes, for example if the display is mounted in portrait
+ mode or even if it's mounted landscape but rotated by 180degree,
+ we need to rotate our content of the display relative to the
+ framebuffer, so that user can read the messages which are
+ printed out.
+ Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
+ initialized with a given rotation from "vl_rot" out of
+ "vidinfo_t" which is provided by the board specific code.
+ The value for vl_rot is coded as following (matching to
+ fbcon=rotate:<n> linux-kernel commandline):
+ 0 = no rotation respectively 0 degree
+ 1 = 90 degree rotation
+ 2 = 180 degree rotation
+ 3 = 270 degree rotation
+
+ If CONFIG_LCD_ROTATION is not defined, the console will be
+ initialized with 0degree rotation.
CONFIG_LCD_BMP_RLE8
@@ -2000,7 +1321,7 @@
If this option is set, then U-Boot will prevent the environment
variable "splashimage" from being set to a problematic address
- (see README.displaying-bmps).
+ (see doc/README.displaying-bmps).
This option is useful for targets where, due to alignment
restrictions, an improperly aligned BMP image will cause a data
abort. If you think you will not have problems with unaligned
@@ -2039,12 +1360,6 @@
can be displayed via the splashscreen support or the
bmp command.
-- Do compressing for memory range:
- CONFIG_CMD_ZIP
-
- If this option is set, it would use zlib deflate method
- to compress the specified memory at its best effort.
-
- Compression support:
CONFIG_GZIP
@@ -2060,48 +1375,11 @@
the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
- CONFIG_LZMA
-
- If this option is set, support for lzma compressed
- images is included.
-
- Note: The LZMA algorithm adds between 2 and 4KB of code and it
- requires an amount of dynamic memory that is given by the
- formula:
-
- (1846 + 768 << (lc + lp)) * sizeof(uint16)
-
- Where lc and lp stand for, respectively, Literal context bits
- and Literal pos bits.
-
- This value is upper-bounded by 14MB in the worst case. Anyway,
- for a ~4MB large kernel image, we have lc=3 and lp=0 for a
- total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
- a very small buffer.
-
- Use the lzmainfo tool to determinate the lc and lp values and
- then calculate the amount of needed dynamic memory (ensuring
- the appropriate CONFIG_SYS_MALLOC_LEN value).
-
- CONFIG_LZO
-
- If this option is set, support for LZO compressed images
- is included.
-
- MII/PHY support:
- CONFIG_PHY_ADDR
-
- The address of PHY on MII bus.
-
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
The clock frequency of the MII bus
- CONFIG_PHY_GIGE
-
- If this option is set, support for speed/duplex
- detection of gigabit PHY is included.
-
CONFIG_PHY_RESET_DELAY
Some PHY like Intel LXT971A need extra delay after
@@ -2114,18 +1392,6 @@
Some PHY like Intel LXT971A need extra delay after
command issued before MII status register can be read
-- Ethernet address:
- CONFIG_ETHADDR
- CONFIG_ETH1ADDR
- CONFIG_ETH2ADDR
- CONFIG_ETH3ADDR
- CONFIG_ETH4ADDR
- CONFIG_ETH5ADDR
-
- Define a default value for Ethernet address to use
- for the respective Ethernet interface, in case this
- is not determined automatically.
-
- IP address:
CONFIG_IPADDR
@@ -2213,14 +1479,8 @@
You can fine tune the DHCP functionality by defining
CONFIG_BOOTP_* symbols:
- CONFIG_BOOTP_SUBNETMASK
- CONFIG_BOOTP_GATEWAY
- CONFIG_BOOTP_HOSTNAME
CONFIG_BOOTP_NISDOMAIN
- CONFIG_BOOTP_BOOTPATH
CONFIG_BOOTP_BOOTFILESIZE
- CONFIG_BOOTP_DNS
- CONFIG_BOOTP_DNS2
CONFIG_BOOTP_SEND_HOSTNAME
CONFIG_BOOTP_NTPSERVER
CONFIG_BOOTP_TIMEOFFSET
@@ -2236,15 +1496,6 @@
to Link-local IP address configuration if the DHCP server
is not available.
- CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
- serverip from a DHCP server, it is possible that more
- than one DNS serverip is offered to the client.
- If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
- serverip will be stored in the additional environment
- variable "dnsip2". The first DNS serverip is always
- stored in the variable "dnsip", when CONFIG_BOOTP_DNS
- is defined.
-
CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
to do a dynamic update of a DNS server. To do this, they
need the hostname of the DHCP requester.
@@ -2274,6 +1525,15 @@
See doc/README.link-local for more information.
+ - MAC address from environment variables
+
+ FDT_SEQ_MACADDR_FROM_ENV
+
+ Fix-up device tree with MAC addresses fetched sequentially from
+ environment variables. This config work on assumption that
+ non-usable ethernet node of device-tree are either not present
+ or their status has been marked as "disabled".
+
- CDP Options:
CONFIG_CDP_DEVICE_ID
@@ -2316,7 +1576,7 @@
A byte containing the id of the VLAN.
-- Status LED: CONFIG_STATUS_LED
+- Status LED: CONFIG_LED_STATUS
Several configurations allow to display the current
status using a LED. For instance, the LED will blink
@@ -2324,15 +1584,15 @@
soon as a reply to a BOOTP request was received, and
start blinking slow once the Linux kernel is running
(supported by a status LED driver in the Linux
- kernel). Defining CONFIG_STATUS_LED enables this
+ kernel). Defining CONFIG_LED_STATUS enables this
feature in U-Boot.
Additional options:
- CONFIG_GPIO_LED
+ CONFIG_LED_STATUS_GPIO
The status LED can be connected to a GPIO pin.
In such cases, the gpio_led driver can be used as a
- status LED backend implementation. Define CONFIG_GPIO_LED
+ status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
to include the gpio_led driver in the U-Boot binary.
CONFIG_GPIO_LED_INVERTED_TABLE
@@ -2342,12 +1602,6 @@
In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
-- CAN Support: CONFIG_CAN_DRIVER
-
- Defining CONFIG_CAN_DRIVER enables CAN driver support
- on those systems that support this (optional)
- feature, like the TQM8xxL modules.
-
- I2C Support: CONFIG_SYS_I2C
This enable the NEW i2c subsystem, and will allow you to use
@@ -2396,12 +1650,18 @@
- drivers/i2c/i2c_mxc.c
- activate this driver with CONFIG_SYS_I2C_MXC
+ - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
+ - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
+ - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+ - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
- define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
- define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+ - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
+ - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
If those defines are not set, default value is 100000
for speed, and 0 for slave.
@@ -2433,8 +1693,6 @@
- CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
- CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
- CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
- - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
- - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
- CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
- drivers/i2c/omap24xx_i2c.c
@@ -2475,14 +1733,20 @@
- CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
- CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
- CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+ - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
+ - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
+ - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
+ - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
+ - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
+ - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
+ - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
+ - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
+ - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
- Hold the number of i2c buses you want to use. If you
- don't use/have i2c muxes on your i2c bus, this
- is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
- omit this define.
+ Hold the number of i2c buses you want to use.
CONFIG_SYS_I2C_DIRECT_BUS
define this, if you don't use i2c muxes on your hardware.
@@ -2524,52 +1788,7 @@
If you do not have i2c muxes on your board, omit this define.
-- Legacy I2C Support: CONFIG_HARD_I2C
-
- NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
- provides the following compelling advantages:
-
- - more than one i2c adapter is usable
- - approved multibus support
- - better i2c mux support
-
- ** Please consider updating your I2C driver now. **
-
- These enable legacy I2C serial bus commands. Defining
- CONFIG_HARD_I2C will include the appropriate I2C driver
- for the selected CPU.
-
- This will allow you to use i2c commands at the u-boot
- command line (as long as you set CONFIG_CMD_I2C in
- CONFIG_COMMANDS) and communicate with i2c based realtime
- clock chips. See common/cmd_i2c.c for a description of the
- command line interface.
-
- CONFIG_HARD_I2C selects a hardware I2C controller.
-
- There are several other quantities that must also be
- defined when you define CONFIG_HARD_I2C.
-
- In both cases you will need to define CONFIG_SYS_I2C_SPEED
- to be the frequency (in Hz) at which you wish your i2c bus
- to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
- the CPU's i2c node address).
-
- Now, the u-boot i2c code for the mpc8xx
- (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
- and so its address should therefore be cleared to 0 (See,
- eg, MPC823e User's Manual p.16-473). So, set
- CONFIG_SYS_I2C_SLAVE to 0.
-
- CONFIG_SYS_I2C_INIT_MPC5XXX
-
- When a board is reset during an i2c bus transfer
- chips might think that the current transfer is still
- in progress. Reset the slave devices by sending start
- commands until the slave device responds.
-
- That's all that's required for CONFIG_HARD_I2C.
-
+- Legacy I2C Support:
If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
then the following macros need to be defined (examples are
from include/configs/lwmon.h):
@@ -2581,12 +1800,6 @@
eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
- I2C_PORT
-
- (Only for MPC8260 CPU). The I/O port to use (the code
- assumes both bits are on the same port). Valid values
- are 0..3 for ports A..D.
-
I2C_ACTIVE
The code necessary to make the I2C data line active
@@ -2658,23 +1871,6 @@
custom i2c_init_board() routine in boards/xxx/board.c
is run early in the boot sequence.
- CONFIG_SYS_I2C_BOARD_LATE_INIT
-
- An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
- defined a custom i2c_board_late_init() routine in
- boards/xxx/board.c is run AFTER the operations in i2c_init()
- is completed. This callpoint can be used to unreset i2c bus
- using CPU i2c controller register accesses for CPUs whose i2c
- controller provide such a method. It is called at the end of
- i2c_init() to allow i2c_init operations to setup the i2c bus
- controller on the CPU (e.g. setting bus speed & slave address).
-
- CONFIG_I2CFAST (PPC405GP|PPC405EP only)
-
- This option enables configuration of bi_iic_fast[] flags
- in u-boot bd_info structure based on u-boot environment
- variable "i2cfast". (see also i2cfast)
-
CONFIG_I2C_MULTI_BUS
This option allows the use of multiple I2C buses, each of which
@@ -2696,7 +1892,7 @@
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
+ #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
@@ -2710,17 +1906,6 @@
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
- CONFIG_SYS_DTT_BUS_NUM
-
- If defined, then this indicates the I2C bus number for the DTT.
- If not defined, then U-Boot assumes that DTT is on I2C bus 0.
-
- CONFIG_SYS_I2C_DTT_ADDR:
-
- If defined, specifies the I2C address of the DTT device.
- If not defined, then U-Boot uses predefined value for
- specified DTT device.
-
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
@@ -2737,16 +1922,6 @@
SPI EEPROM, also an instance works with Crystal A/D and
D/As on the SACSng board)
- CONFIG_SH_SPI
-
- Enables the driver for SPI controller on SuperH. Currently
- only SH7757 is supported.
-
- CONFIG_SPI_X
-
- Enables extended (16-bit) SPI EEPROM addressing.
- (symmetrical to CONFIG_I2C_X)
-
CONFIG_SOFT_SPI
Enables a software (bit-bang) SPI driver rather than
@@ -2757,19 +1932,6 @@
SPI configuration items (port pins to use, etc). For
an example, see include/configs/sacsng.h.
- CONFIG_HARD_SPI
-
- Enables a hardware SPI driver for general-purpose reads
- and writes. As with CONFIG_SOFT_SPI, the board configuration
- must define a list of chip-select function pointers.
- Currently supported on some MPC8xxx processors. For an
- example, see include/configs/mpc8349emds.h.
-
- CONFIG_MXC_SPI
-
- Enables the driver for the SPI controllers on i.MX and MXC
- SoCs. Currently i.MX31/35/51 are supported.
-
CONFIG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */
@@ -2792,19 +1954,6 @@
Specify the number of FPGA devices to support.
- CONFIG_CMD_FPGA_LOADMK
-
- Enable support for fpga loadmk command
-
- CONFIG_CMD_FPGA_LOADP
-
- Enable support for fpga loadp command - load partial bitstream
-
- CONFIG_CMD_FPGA_LOADBP
-
- Enable support for fpga loadbp command - load partial bitstream
- (Xilinx only)
-
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
@@ -2855,7 +2004,7 @@
with a special header) as build targets. By defining
CONFIG_BUILD_TARGET in the SoC / board header, this
special image will be automatically built upon calling
- make / MAKEALL.
+ make / buildman.
CONFIG_IDENT_STRING
@@ -2878,8 +2027,8 @@
completely disabled. Anybody can change or delete
these parameters.
- Alternatively, if you #define _both_ CONFIG_ETHADDR
- _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
+ Alternatively, if you define _both_ an ethaddr in the
+ default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
Ethernet address is installed in the environment,
which can be changed exactly ONCE by the user. [The
serial# is unaffected by this, i. e. it remains
@@ -2919,9 +2068,9 @@
following board configurations are known to be
"pRAM-clean":
- IVMS8, IVML24, SPD8xx, TQM8xxL,
+ IVMS8, IVML24, SPD8xx,
HERMES, IP860, RPXlite, LWMON,
- FLAGADM, TQM8260
+ FLAGADM
- Access to physical memory region (> 4GB)
Some basic support is provided for operations on memory not
@@ -2932,16 +2081,6 @@
currently only supports clearing the memory.
- Error Recovery:
- CONFIG_PANIC_HANG
-
- Define this variable to stop the system in case of a
- fatal error, so that you have to reset it manually.
- This is probably NOT a good idea for an embedded
- system where you want the system to reboot
- automatically as fast as possible, but it may be
- useful during development since you can try to debug
- the conditions that lead to the situation.
-
CONFIG_NET_RETRY_COUNT
This variable defines the number of retries for
@@ -2961,10 +2100,6 @@
#define CONFIG_NFS_TIMEOUT 10000UL
- Command Interpreter:
- CONFIG_AUTO_COMPLETE
-
- Enable auto completion of commands using TAB.
-
CONFIG_SYS_PROMPT_HUSH_PS2
This defines the secondary prompt string, which is
@@ -2993,10 +2128,12 @@
symbols.
- Command Line Editing and History:
- CONFIG_CMDLINE_EDITING
+ CONFIG_CMDLINE_PS_SUPPORT
- Enable editing and History functions for interactive
- command line input operations
+ Enable support for changing the command prompt string
+ at run-time. Only static string is supported so far.
+ The string is obtained from environment variables PS1
+ and PS2.
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS
@@ -3024,26 +2161,6 @@
the environment like the "source" command or the
boot command first.
- CONFIG_ENV_VARS_UBOOT_CONFIG
-
- Define this in order to add variables describing the
- U-Boot build configuration to the default environment.
- These will be named arch, cpu, board, vendor, and soc.
-
- Enabling this option will cause the following to be defined:
-
- - CONFIG_SYS_ARCH
- - CONFIG_SYS_CPU
- - CONFIG_SYS_BOARD
- - CONFIG_SYS_VENDOR
- - CONFIG_SYS_SOC
-
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
- Define this in order to add variables describing certain
- run-time determined information about the hardware to the
- environment. These will be named board_name, board_rev.
-
CONFIG_DELAY_ENVIRONMENT
Normally the environment is loaded when the board is
@@ -3053,20 +2170,8 @@
this is instead controlled by the value of
/config/load-environment.
-- DataFlash Support:
- CONFIG_HAS_DATAFLASH
-
- Defining this option enables DataFlash features and
- allows to read/write in Dataflash via the standard
- commands cp, md...
-
- Serial Flash support
- CONFIG_CMD_SF
-
- Defining this option enables SPI flash commands
- 'sf probe/read/write/erase/update'.
-
- Usage requires an initial 'probe' to define the serial
+ Usage requires an initial 'sf probe' to define the serial
flash parameters, followed by read/write/erase/update
commands.
@@ -3079,46 +2184,6 @@
CONFIG_SF_DEFAULT_MODE (see include/spi.h)
CONFIG_SF_DEFAULT_SPEED in Hz
- CONFIG_CMD_SF_TEST
-
- Define this option to include a destructive SPI flash
- test ('sf test').
-
- CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg
-
- Define this option to use the Bank addr/Extended addr
- support on SPI flashes which has size > 16Mbytes.
-
- CONFIG_SF_DUAL_FLASH Dual flash memories
-
- Define this option to use dual flash support where two flash
- memories can be connected with a given cs line.
- Currently Xilinx Zynq qspi supports these type of connections.
-
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
-- SystemACE Support:
- CONFIG_SYSTEMACE
-
- Adding this option adds support for Xilinx SystemACE
- chips attached via some sort of local bus. The address
- of the chip must also be defined in the
- CONFIG_SYS_SYSTEMACE_BASE macro. For example:
-
- #define CONFIG_SYSTEMACE
- #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
-
- When SystemACE support is added, the "ace" device type
- becomes available to the fat commands, i.e. fatls.
- TFTP Fixed UDP Port:
CONFIG_TFTP_PORT
@@ -3140,68 +2205,6 @@
A better solution is to properly configure the firewall,
but sometimes that is not allowed.
-- Hashing support:
- CONFIG_CMD_HASH
-
- This enables a generic 'hash' command which can produce
- hashes / digests from a few algorithms (e.g. SHA1, SHA256).
-
- CONFIG_HASH_VERIFY
-
- Enable the hash verify command (hash -v). This adds to code
- size a little.
-
- CONFIG_SHA1 - support SHA1 hashing
- CONFIG_SHA256 - support SHA256 hashing
-
- Note: There is also a sha1sum command, which should perhaps
- be deprecated in favour of 'hash sha1'.
-
-- Freescale i.MX specific commands:
- CONFIG_CMD_HDMIDETECT
- This enables 'hdmidet' command which returns true if an
- HDMI monitor is detected. This command is i.MX 6 specific.
-
- CONFIG_CMD_BMODE
- This enables the 'bmode' (bootmode) command for forcing
- a boot from specific media.
-
- This is useful for forcing the ROM's usb downloader to
- activate upon a watchdog reset which is nice when iterating
- on U-Boot. Using the reset button or running bmode normal
- will set it back to normal. This command currently
- supports i.MX53 and i.MX6.
-
-- Signing support:
- CONFIG_RSA
-
- This enables the RSA algorithm used for FIT image verification
- in U-Boot. See doc/uImage.FIT/signature.txt for more information.
-
- The signing part is build into mkimage regardless of this
- option.
-
-- bootcount support:
- CONFIG_BOOTCOUNT_LIMIT
-
- This enables the bootcounter support, see:
- http://www.denx.de/wiki/DULG/UBootBootCountLimit
-
- CONFIG_AT91SAM9XE
- enable special bootcounter support on at91sam9xe based boards.
- CONFIG_BLACKFIN
- enable special bootcounter support on blackfin based boards.
- CONFIG_SOC_DA8XX
- enable special bootcounter support on da850 based boards.
- CONFIG_BOOTCOUNT_RAM
- enable support for the bootcounter in RAM
- CONFIG_BOOTCOUNT_I2C
- enable support for the bootcounter on an i2c (like RTC) device.
- CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
- CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
- the bootcounter.
- CONFIG_BOOTCOUNT_ALEN = address len
-
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS
@@ -3212,55 +2215,6 @@
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
-- Detailed boot stage timing
- CONFIG_BOOTSTAGE
- Define this option to get detailed timing of each stage
- of the boot process.
-
- CONFIG_BOOTSTAGE_USER_COUNT
- This is the number of available user bootstage records.
- Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
- a new ID will be allocated from this stash. If you exceed
- the limit, recording will stop.
-
- CONFIG_BOOTSTAGE_REPORT
- Define this to print a report before boot, similar to this:
-
- Timer summary in microseconds:
- Mark Elapsed Stage
- 0 0 reset
- 3,575,678 3,575,678 board_init_f start
- 3,575,695 17 arch_cpu_init A9
- 3,575,777 82 arch_cpu_init done
- 3,659,598 83,821 board_init_r start
- 3,910,375 250,777 main_loop
- 29,916,167 26,005,792 bootm_start
- 30,361,327 445,160 start_kernel
-
- CONFIG_CMD_BOOTSTAGE
- Add a 'bootstage' command which supports printing a report
- and un/stashing of bootstage data.
-
- CONFIG_BOOTSTAGE_FDT
- Stash the bootstage information in the FDT. A root 'bootstage'
- node is created with each bootstage id as a child. Each child
- has a 'name' property and either 'mark' containing the
- mark time in microsecond, or 'accum' containing the
- accumulated time for that bootstage id in microseconds.
- For example:
-
- bootstage {
- 154 {
- name = "board_init_f";
- mark = <3575678>;
- };
- 170 {
- name = "lcd";
- accum = <33482>;
- };
- };
-
- Code in the Linux kernel can find this in /proc/devicetree.
Legacy uImage format:
@@ -3354,9 +2308,9 @@
65 net/eth.c Ethernet found.
-80 common/cmd_net.c usage wrong
- 80 common/cmd_net.c before calling NetLoop()
- -81 common/cmd_net.c some error in NetLoop() occurred
- 81 common/cmd_net.c NetLoop() back without error
+ 80 common/cmd_net.c before calling net_loop()
+ -81 common/cmd_net.c some error in net_loop() occurred
+ 81 common/cmd_net.c net_loop() back without error
-82 common/cmd_net.c size == 0 (File with size 0 loaded)
82 common/cmd_net.c trying automatic boot
83 common/cmd_net.c running "source" command
@@ -3415,45 +2369,6 @@
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
-- legacy image format:
- CONFIG_IMAGE_FORMAT_LEGACY
- enables the legacy image format support in U-Boot.
-
- Default:
- enabled if CONFIG_FIT_SIGNATURE is not defined.
-
- CONFIG_DISABLE_IMAGE_LEGACY
- disable the legacy image format
-
- This define is introduced, as the legacy image format is
- enabled per default for backward compatibility.
-
-- FIT image support:
- CONFIG_FIT
- Enable support for the FIT uImage format.
-
- CONFIG_FIT_BEST_MATCH
- When no configuration is explicitly selected, default to the
- one whose fdt's compatibility field best matches that of
- U-Boot itself. A match is considered "best" if it matches the
- most specific compatibility entry of U-Boot's fdt's root node.
- The order of entries in the configuration's fdt is ignored.
-
- CONFIG_FIT_SIGNATURE
- This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA. See
- doc/uImage.FIT/signature.txt for more details.
-
- WARNING: When relying on signed FIT images with required
- signature check the legacy image format is default
- disabled. If a board need legacy image format support
- enable this through CONFIG_IMAGE_FORMAT_LEGACY
-
- CONFIG_FIT_DISABLE_SHA256
- Supporting SHA256 hashes has quite an impact on binary size.
- For constrained systems sha256 hash support can be disabled
- with this option.
-
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
@@ -3485,33 +2400,6 @@
for a more detailed description refer to doc/README.update.
- MTD Support (mtdparts command, UBI support)
- CONFIG_MTD_DEVICE
-
- Adds the MTD device infrastructure from the Linux kernel.
- Needed for mtdparts command support.
-
- CONFIG_MTD_PARTITIONS
-
- Adds the MTD partitioning infrastructure from the Linux
- kernel. Needed for UBI support.
-
- CONFIG_MTD_NAND_VERIFY_WRITE
- verify if the written data is correct reread.
-
-- UBI support
- CONFIG_CMD_UBI
-
- Adds commands for interacting with MTD partitions formatted
- with the UBI flash translation layer
-
- Requires also defining CONFIG_RBTREE
-
- CONFIG_UBI_SILENCE_MSG
-
- Make the verbose messages from UBI stop printing. This leaves
- warnings and errors enabled.
-
-
CONFIG_MTD_UBI_WL_THRESHOLD
This parameter defines the maximum difference between the highest
erase counter value and the lowest erase counter value of eraseblocks
@@ -3569,18 +2457,9 @@
without a fastmap.
default: 0
-- UBIFS support
- CONFIG_CMD_UBIFS
-
- Adds commands for interacting with UBI volumes formatted as
- UBIFS. UBIFS is read-only in u-boot.
-
- Requires UBI support as well as CONFIG_LZO
-
- CONFIG_UBIFS_SILENCE_MSG
-
- Make the verbose messages from UBIFS stop printing. This leaves
- warnings and errors enabled.
+ CONFIG_MTD_UBI_FM_DEBUG
+ Enable UBI fastmap debug
+ default: 0
- SPL framework
CONFIG_SPL
@@ -3622,6 +2501,16 @@
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
+ CONFIG_SPL_PANIC_ON_RAW_IMAGE
+ When defined, SPL will panic() if the image it has
+ loaded does not have a signature.
+ Defining this is useful when code which loads images
+ in SPL cannot guarantee that absolutely all read errors
+ will be caught.
+ An example is the LPC32XX MLC NAND driver, which will
+ consider that a completely unreadable NAND block is bad,
+ and thus should be skipped silently.
+
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
@@ -3629,15 +2518,13 @@
CONFIG_SYS_SPL_MALLOC_START
Starting address of the malloc pool used in SPL.
+ When this option is set the full malloc is used in SPL and
+ it is set up by spl_init() and before that, the simple malloc()
+ can be used if CONFIG_SYS_MALLOC_F is defined.
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
- CONFIG_SPL_FRAMEWORK
- Enable the SPL framework under common/. This framework
- supports MMC, NAND and YMODEM loading of U-Boot and NAND
- NAND loading of the Linux Kernel.
-
CONFIG_SPL_OS_BOOT
Enable booting directly to an OS from SPL.
See also: doc/README.falcon
@@ -3649,26 +2536,6 @@
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
- CONFIG_SPL_LIBCOMMON_SUPPORT
- Support for common/libcommon.o in SPL binary
-
- CONFIG_SPL_LIBDISK_SUPPORT
- Support for disk/libdisk.o in SPL binary
-
- CONFIG_SPL_I2C_SUPPORT
- Support for drivers/i2c/libi2c.o in SPL binary
-
- CONFIG_SPL_GPIO_SUPPORT
- Support for drivers/gpio/libgpio.o in SPL binary
-
- CONFIG_SPL_MMC_SUPPORT
- Support for drivers/mmc/libmmc.o in SPL binary
-
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
- CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- Address and partition on the MMC to load U-Boot from
- when the MMC is being used in raw mode.
-
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
Partition on the MMC to load U-Boot from when the MMC is being
used in raw mode
@@ -3687,12 +2554,6 @@
Partition on the MMC to load U-Boot from when the MMC is being
used in fs mode
- CONFIG_SPL_FAT_SUPPORT
- Support for fs/fat/libfat.o in SPL binary
-
- CONFIG_SPL_EXT_SUPPORT
- Support for EXT filesystem in SPL binary
-
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from filesystem
@@ -3720,6 +2581,10 @@
CONFIG_SPL_NAND_DRIVERS
SPL uses normal NAND drivers, not minimal drivers.
+ CONFIG_SPL_NAND_IDENT
+ SPL uses the chip ID list to identify the NAND flash.
+ Requires CONFIG_SPL_NAND_BASE.
+
CONFIG_SPL_NAND_ECC
Include standard software ECC in the SPL
@@ -3727,18 +2592,14 @@
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
- CONFIG_SPL_MTD_SUPPORT
- Support for the MTD subsystem within SPL. Useful for
- environment on NAND support within SPL.
+ CONFIG_SPL_UBI
+ Support for a lightweight UBI (fastmap) scanner and
+ loader
CONFIG_SPL_NAND_RAW_ONLY
Support to boot only raw u-boot.bin images. Use this only
if you need to save space.
- CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
- Set for the SPL on PPC mpc8xxx targets, support for
- drivers/ddr/fsl/libddr.o in SPL binary.
-
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
SPL binary.
@@ -3770,33 +2631,9 @@
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
- CONFIG_SPL_OMAP3_ID_NAND
- Support for an OMAP3-specific set of functions to return the
- ID and MFR of the first attached NAND chip, if present.
-
- CONFIG_SPL_SERIAL_SUPPORT
- Support for drivers/serial/libserial.o in SPL binary
-
- CONFIG_SPL_SPI_FLASH_SUPPORT
- Support for drivers/mtd/spi/libspi_flash.o in SPL binary
-
- CONFIG_SPL_SPI_SUPPORT
- Support for drivers/spi/libspi.o in SPL binary
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
- CONFIG_SPL_LIBGENERIC_SUPPORT
- Support for lib/libgeneric.o in SPL binary
-
- CONFIG_SPL_ENV_SUPPORT
- Support for the environment operating in SPL binary
-
- CONFIG_SPL_NET_SUPPORT
- Support for the net/libnet.o in SPL binary.
- It conflicts with SPL env from storage medium specified by
- CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
-
CONFIG_SPL_PAD_TO
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
@@ -3809,7 +2646,7 @@
use an arch-specific makefile fragment instead, for
example if more than one image needs to be produced.
- CONFIG_FIT_SPL_PRINT
+ CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
@@ -3826,23 +2663,6 @@
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-Modem Support:
---------------
-
-[so far only for SMDK2400 boards]
-
-- Modem support enable:
- CONFIG_MODEM_SUPPORT
-
-- RTS/CTS Flow control enable:
- CONFIG_HWFLOW
-
-- Modem debug support:
- CONFIG_MODEM_SUPPORT_DEBUG
-
- Enables debugging stuff (char screen[1024], dbg())
- for modem support. Useful only with BDI2000.
-
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
@@ -3856,22 +2676,6 @@
/ other_activity_monitor it works automatically from
general timer_interrupt().
-- General:
-
- In the target system modem support is enabled when a
- specific key (key combination) is pressed during
- power-on. Otherwise U-Boot will boot normally
- (autoboot). The key_pressed() function is called from
- board_init(). Currently key_pressed() is a dummy
- function, returning 1 and thus enabling modem
- initialization.
-
- If there are no modem init strings in the
- environment, U-Boot proceed to autoboot; the
- previous output (banner, info printfs) will be
- suppressed, though.
-
- See also: doc/README.Modem
Board initialization settings:
------------------------------
@@ -3916,33 +2720,24 @@
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
-- CONFIG_SYS_CONSOLE_INFO_QUIET
- Suppress display of console information at boot.
-
-- CONFIG_SYS_CONSOLE_IS_IN_ENV
- If the board specific function
- extern int overwrite_console (void);
- returns 1, the stdin, stderr and stdout are switched to the
- serial port, else the settings in the environment are used.
-
-- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
- Enable the call to overwrite_console().
-
-- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
- Enable overwrite of previous console environment settings.
-
- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
Begin and End addresses of the area used by the
simple memory test.
-- CONFIG_SYS_ALT_MEMTEST:
- Enable an alternate, more extensive memory test.
-
- CONFIG_SYS_MEMTEST_SCRATCH:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
-- CONFIG_SYS_MEM_TOP_HIDE (PPC only):
+- CONFIG_SYS_MEM_RESERVE_SECURE
+ Only implemented for ARMv8 for now.
+ If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+ is substracted from total RAM and won't be reported to OS.
+ This memory can be used as secure memory. A variable
+ gd->arch.secure_ram is used to track the location. In systems
+ the RAM base is not zero, or RAM is divided into banks,
+ this variable needs to be recalcuated to get the address.
+
+- CONFIG_SYS_MEM_TOP_HIDE:
If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
this specified memory area will get subtracted from the top
(end) of RAM and won't get "touched" at all by U-Boot. By
@@ -3969,10 +2764,6 @@
- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
-- CONFIG_SYS_MBIO_BASE:
- Physical start address of Motherboard I/O (if using a
- Cogent motherboard)
-
- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
@@ -4004,9 +2795,6 @@
The memory will be freed (or in fact just forgotten) when
U-Boot relocates itself.
- Pre-relocation malloc() is only supported on ARM and sandbox
- at present but is fairly easy to enable for other archs.
-
- CONFIG_SYS_MALLOC_SIMPLE
Provides a simple and small malloc() and calloc() for those
boards which do not use the full malloc in SPL (which is
@@ -4192,30 +2980,14 @@
list, simply add an entry for the same variable name to the
".flags" variable.
+ If CONFIG_REGEX is defined, the variable_name above is evaluated as a
+ regular expression. This allows multiple variables to define the same
+ flags without explicitly listing them for each variable.
+
- CONFIG_ENV_ACCESS_IGNORE_FORCE
If defined, don't allow the -f switch to env set override variable
access flags.
-- CONFIG_SYS_GENERIC_BOARD
- This selects the architecture-generic board system instead of the
- architecture-specific board files. It is intended to move boards
- to this new framework over time. Defining this will disable the
- arch/foo/lib/board.c file and use common/board_f.c and
- common/board_r.c instead. To use this option your architecture
- must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
- its config.mk file). If you find problems enabling this option on
- your board please report the problem and send patches!
-
-- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
- This is set by OMAP boards for the max time that reset should
- be asserted. See doc/README.omap-reset-time for details on how
- the value can be calculated on a given board.
-
-- CONFIG_USE_STDINT
- If stdint.h is available with your toolchain you can define this
- option to enable it. You can provide option 'USE_STDINT=1' when
- building U-Boot to enable this.
-
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
following configurations:
@@ -4225,90 +2997,6 @@
Builds up envcrc with the target environment so that external utils
may easily extract it and embed it in final U-Boot images.
-- CONFIG_ENV_IS_IN_FLASH:
-
- Define this if the environment is in flash memory.
-
- a) The environment occupies one whole flash sector, which is
- "embedded" in the text segment with the U-Boot code. This
- happens usually with "bottom boot sector" or "top boot
- sector" type flash chips, which have several smaller
- sectors at the start or the end. For instance, such a
- layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
- such a case you would place the environment in one of the
- 4 kB sectors - with U-Boot code before and after it. With
- "top boot sector" type flash chips, you would put the
- environment in one of the last sectors, leaving a gap
- between U-Boot and the environment.
-
- - CONFIG_ENV_OFFSET:
-
- Offset of environment data (variable area) to the
- beginning of flash memory; for instance, with bottom boot
- type flash chips the second sector can be used: the offset
- for this sector is given here.
-
- CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
-
- - CONFIG_ENV_ADDR:
-
- This is just another way to specify the start address of
- the flash sector containing the environment (instead of
- CONFIG_ENV_OFFSET).
-
- - CONFIG_ENV_SECT_SIZE:
-
- Size of the sector containing the environment.
-
-
- b) Sometimes flash chips have few, equal sized, BIG sectors.
- In such a case you don't want to spend a whole sector for
- the environment.
-
- - CONFIG_ENV_SIZE:
-
- If you use this in combination with CONFIG_ENV_IS_IN_FLASH
- and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
- of this flash sector for the environment. This saves
- memory for the RAM copy of the environment.
-
- It may also save flash memory if you decide to use this
- when your environment is "embedded" within U-Boot code,
- since then the remainder of the flash sector could be used
- for U-Boot code. It should be pointed out that this is
- STRONGLY DISCOURAGED from a robustness point of view:
- updating the environment in flash makes it always
- necessary to erase the WHOLE sector. If something goes
- wrong before the contents has been restored from a copy in
- RAM, your target system will be dead.
-
- - CONFIG_ENV_ADDR_REDUND
- CONFIG_ENV_SIZE_REDUND
-
- These settings describe a second storage area used to hold
- a redundant copy of the environment data, so that there is
- a valid backup copy in case there is a power failure during
- a "saveenv" operation.
-
-BE CAREFUL! Any changes to the flash layout, and some changes to the
-source code will make it necessary to adapt <board>/u-boot.lds*
-accordingly!
-
-
-- CONFIG_ENV_IS_IN_NVRAM:
-
- Define this if you have some non-volatile memory device
- (NVRAM, battery buffered SRAM) which you want to use for the
- environment.
-
- - CONFIG_ENV_ADDR:
- - CONFIG_ENV_SIZE:
-
- These two #defines are used to determine the memory area you
- want to use for environment. It is assumed that this memory
- can just be read and written to, without any special
- provision.
-
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
@@ -4319,295 +3007,20 @@
keep settings there always unmodified except somebody uses "saveenv"
to save the current settings.
-
-- CONFIG_ENV_IS_IN_EEPROM:
-
- Use this if you have an EEPROM or similar serial access
- device and a driver for it.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the
- environment area within the total memory of your EEPROM.
-
- - CONFIG_SYS_I2C_EEPROM_ADDR:
- If defined, specified the chip address of the EEPROM device.
- The default address is zero.
-
- - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
- If defined, the number of bits used to address bytes in a
- single page in the EEPROM device. A 64 byte page, for example
- would require six bits.
-
- - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
- If defined, the number of milliseconds to delay between
- page writes. The default is zero milliseconds.
-
- - CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
- The length in bytes of the EEPROM memory array address. Note
- that this is NOT the chip address length!
-
- - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
- EEPROM chips that implement "address overflow" are ones
- like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- address and the extra bits end up in the "chip address" bit
- slots. This makes a 24WC08 (1Kbyte) chip look like four 256
- byte chips.
-
- Note that we consider the length of the address field to
- still be one byte because the extra address bits are hidden
- in the chip address.
-
- - CONFIG_SYS_EEPROM_SIZE:
- The size in bytes of the EEPROM device.
-
- - CONFIG_ENV_EEPROM_IS_ON_I2C
- define this, if you have I2C and SPI activated, and your
- EEPROM, which holds the environment, is on the I2C bus.
-
- - CONFIG_I2C_ENV_EEPROM_BUS
- if you have an Environment on an EEPROM reached over
- I2C muxes, you can define here, how to reach this
- EEPROM. For example:
-
- #define CONFIG_I2C_ENV_EEPROM_BUS 1
-
- EEPROM which holds the environment, is reached over
- a pca9547 i2c mux with address 0x70, channel 3.
-
-- CONFIG_ENV_IS_IN_DATAFLASH:
-
- Define this if you have a DataFlash memory device which you
- want to use for the environment.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_ADDR:
- - CONFIG_ENV_SIZE:
-
- These three #defines specify the offset and size of the
- environment area within the total memory of your DataFlash placed
- at the specified address.
-
-- CONFIG_ENV_IS_IN_SPI_FLASH:
-
- Define this if you have a SPI Flash memory device which you
- want to use for the environment.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the
- environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
- aligned to an erase sector boundary.
-
- - CONFIG_ENV_SECT_SIZE:
-
- Define the SPI flash's sector size.
-
- - CONFIG_ENV_OFFSET_REDUND (optional):
-
- This setting describes a second storage area of CONFIG_ENV_SIZE
- size used to hold a redundant copy of the environment data, so
- that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
- aligned to an erase sector boundary.
-
- - CONFIG_ENV_SPI_BUS (optional):
- - CONFIG_ENV_SPI_CS (optional):
-
- Define the SPI bus and chip select. If not defined they will be 0.
-
- - CONFIG_ENV_SPI_MAX_HZ (optional):
-
- Define the SPI max work clock. If not defined then use 1MHz.
-
- - CONFIG_ENV_SPI_MODE (optional):
-
- Define the SPI work mode. If not defined then use SPI_MODE_3.
-
-- CONFIG_ENV_IS_IN_REMOTE:
-
- Define this if you have a remote memory space which you
- want to use for the local device's environment.
-
- - CONFIG_ENV_ADDR:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the address and size of the
- environment area within the remote memory space. The
- local device can get the environment from remote memory
- space by SRIO or PCIE links.
-
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
-- CONFIG_ENV_IS_IN_NAND:
-
- Define this if you have a NAND device which you want to use
- for the environment.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the environment
- area within the first NAND device. CONFIG_ENV_OFFSET must be
- aligned to an erase block boundary.
-
- - CONFIG_ENV_OFFSET_REDUND (optional):
-
- This setting describes a second storage area of CONFIG_ENV_SIZE
- size used to hold a redundant copy of the environment data, so
- that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
- aligned to an erase block boundary.
-
- - CONFIG_ENV_RANGE (optional):
-
- Specifies the length of the region in which the environment
- can be written. This should be a multiple of the NAND device's
- block size. Specifying a range with more erase blocks than
- are needed to hold CONFIG_ENV_SIZE allows bad blocks within
- the range to be avoided.
-
- - CONFIG_ENV_OFFSET_OOB (optional):
-
- Enables support for dynamically retrieving the offset of the
- environment from block zero's out-of-band data. The
- "nand env.oob" command can be used to record this offset.
- Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
- using CONFIG_ENV_OFFSET_OOB.
-
- CONFIG_NAND_ENV_DST
Defines address in RAM to which the nand_spl code should copy the
environment. If redundant environment is used, it will be copied to
CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
-- CONFIG_ENV_IS_IN_UBI:
-
- Define this if you have an UBI volume that you want to use for the
- environment. This has the benefit of wear-leveling the environment
- accesses, which is important on NAND.
-
- - CONFIG_ENV_UBI_PART:
-
- Define this to a string that is the mtd partition containing the UBI.
-
- - CONFIG_ENV_UBI_VOLUME:
-
- Define this to the name of the volume that you want to store the
- environment in.
-
- - CONFIG_ENV_UBI_VOLUME_REDUND:
-
- Define this to the name of another volume to store a second copy of
- the environment in. This will enable redundant environments in UBI.
- It is assumed that both volumes are in the same MTD partition.
-
- - CONFIG_UBI_SILENCE_MSG
- - CONFIG_UBIFS_SILENCE_MSG
-
- You will probably want to define these to avoid a really noisy system
- when storing the env in UBI.
-
-- CONFIG_ENV_IS_IN_FAT:
- Define this if you want to use the FAT file system for the environment.
-
- - FAT_ENV_INTERFACE:
-
- Define this to a string that is the name of the block device.
-
- - FAT_ENV_DEV_AND_PART:
-
- Define this to a string to specify the partition of the device. It can
- be as following:
-
- "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
- - "D:P": device D partition P. Error occurs if device D has no
- partition table.
- - "D:0": device D.
- - "D" or "D:": device D partition 1 if device D has partition
- table, or the whole device D if has no partition
- table.
- - "D:auto": first partition in device D with bootable flag set.
- If none, first valid partition in device D. If no
- partition table then means device D.
-
- - FAT_ENV_FILE:
-
- It's a string of the FAT file name. This file use to store the
- environment.
-
- - CONFIG_FAT_WRITE:
- This should be defined. Otherwise it cannot save the environment file.
-
-- CONFIG_ENV_IS_IN_MMC:
-
- Define this if you have an MMC device which you want to use for the
- environment.
-
- - CONFIG_SYS_MMC_ENV_DEV:
-
- Specifies which MMC device the environment is stored in.
-
- - CONFIG_SYS_MMC_ENV_PART (optional):
-
- Specifies which MMC partition the environment is stored in. If not
- set, defaults to partition 0, the user area. Common values might be
- 1 (first MMC boot partition), 2 (second MMC boot partition).
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the environment
- area within the specified MMC device.
-
- If offset is positive (the usual case), it is treated as relative to
- the start of the MMC partition. If offset is negative, it is treated
- as relative to the end of the MMC partition. This can be useful if
- your board may be fitted with different MMC devices, which have
- different sizes for the MMC partitions, and you always want the
- environment placed at the very end of the partition, to leave the
- maximum possible space before it, to store other data.
-
- These two values are in units of bytes, but must be aligned to an
- MMC sector boundary.
-
- - CONFIG_ENV_OFFSET_REDUND (optional):
-
- Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
- hold a redundant copy of the environment data. This provides a
- valid backup copy in case the other copy is corrupted, e.g. due
- to a power failure during a "saveenv" operation.
-
- This value may also be positive or negative; this is handled in the
- same way as CONFIG_ENV_OFFSET.
-
- This value is also in units of bytes, but must also be aligned to
- an MMC sector boundary.
-
- - CONFIG_ENV_SIZE_REDUND (optional):
-
- This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
- set. If this value is set, it must be set to the same value as
- CONFIG_ENV_SIZE.
-
-- CONFIG_SYS_SPI_INIT_OFFSET
-
- Defines offset to the initial SPI buffer area in DPRAM. The
- area is used at an early stage (ROM part) if the environment
- is configured to reside in the SPI EEPROM: We need a 520 byte
- scratch DPRAM area. It is used between the two initialization
- calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
- to be a good choice since it makes it far enough from the
- start of the data area as well as from the stack pointer.
-
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
-created; also, when using EEPROM you will have to use getenv_f()
+created; also, when using EEPROM you will have to use env_get_f()
until then to read environment variables.
The environment is protected by a CRC32 checksum. Before the monitor
@@ -4658,13 +3071,6 @@
- CONFIG_SYS_CACHELINE_SIZE:
Cache Line Size of the CPU.
-- CONFIG_SYS_DEFAULT_IMMR:
- Default address of the IMMR after system reset.
-
- Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
- and RPXsuper) to be able to adjust the position of
- the IMMR register after a reset.
-
- CONFIG_SYS_CCSRBAR_DEFAULT:
Default (power-on reset) physical address of CCSR on Freescale
PowerPC SOCs.
@@ -4673,9 +3079,6 @@
Virtual address of CCSR. On a 32-bit build, this is typically
the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
- CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
- for cross-platform code that uses that macro instead.
-
- CONFIG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should
@@ -4738,7 +3141,7 @@
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
- doing! (11-4) [MPC8xx/82xx systems only]
+ doing! (11-4) [MPC8xx systems only]
- CONFIG_SYS_INIT_RAM_ADDR:
@@ -4751,9 +3154,7 @@
sequences.
U-Boot uses the following memory types:
- - MPC8xx and MPC8260: IMMR (internal memory of the CPU)
- - MPC824X: data cache
- - PPC4xx: data cache
+ - MPC8xx: IMMR (internal memory of the CPU)
- CONFIG_SYS_GBL_DATA_OFFSET:
@@ -4762,7 +3163,7 @@
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
- CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
+ GENERATED_GBL_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
@@ -4773,16 +3174,6 @@
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
-- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
-
-- CONFIG_SYS_SYPCR: System Protection Control (11-9)
-
-- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
-
-- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
-
-- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
@@ -4791,8 +3182,6 @@
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
-- CONFIG_SYS_DER: Debug Event Register (37-47)
-
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
@@ -4804,48 +3193,6 @@
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
-- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
- CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
- Machine Mode Register and Memory Periodic Timer
- Prescaler definitions (SDRAM timing)
-
-- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
- enable I2C microcode relocation patch (MPC8xx);
- define relocation offset in DPRAM [DSP2]
-
-- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
- enable SMC microcode relocation patch (MPC8xx);
- define relocation offset in DPRAM [SMC1]
-
-- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
- enable SPI microcode relocation patch (MPC8xx);
- define relocation offset in DPRAM [SCC4]
-
-- CONFIG_SYS_USE_OSCCLK:
- Use OSCM clock mode on MBX8xx board. Be careful,
- wrong setting might damage your board. Read
- doc/README.MBX before setting this variable!
-
-- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
- Offset of the bootmode word in DPRAM used by post
- (Power On Self Tests). This definition overrides
- #define'd default value in commproc.h resp.
- cpm_8260.h.
-
-- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
- CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
- CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
- CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
- CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
- CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
- CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
- CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
- Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
-
-- CONFIG_PCI_DISABLE_PCIE:
- Disable PCI-Express on systems where it is supported but not
- required.
-
- CONFIG_PCI_ENUM_ONLY
Only scan through and get the devices on the buses.
Don't do any setup work, presumably because someone or
@@ -4882,8 +3229,8 @@
a 16 bit bus.
Not all NAND drivers use this symbol.
Example of drivers that use it:
- - drivers/mtd/nand/ndfc.c
- - drivers/mtd/nand/mxc_nand.c
+ - drivers/mtd/nand/raw/ndfc.c
+ - drivers/mtd/nand/raw/mxc_nand.c
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined
@@ -4910,25 +3257,16 @@
- CONFIG_FSL_DDR_INTERACTIVE
Enable interactive DDR debugging. See doc/README.fsl-ddr.
+- CONFIG_FSL_DDR_SYNC_REFRESH
+ Enable sync of refresh for multiple controllers.
+
+- CONFIG_FSL_DDR_BIST
+ Enable built-in memory test for Freescale DDR controllers.
+
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
-- CONFIG_ETHER_ON_FEC[12]
- Define to enable FEC[12] on a 8xx series processor.
-
-- CONFIG_FEC[12]_PHY
- Define to the hardcoded PHY address which corresponds
- to the given FEC; i. e.
- #define CONFIG_FEC1_PHY 4
- means that the PHY with address 4 is connected to FEC1
-
- When set to -1, means to probe for first available.
-
-- CONFIG_FEC[12]_PHY_NORXERR
- The PHY does not have a RXERR line (RMII only).
- (so program the FEC to ignore it).
-
- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't
@@ -4946,7 +3284,7 @@
- CONFIG_LOOPW
Add the "loopw" memory command. This only takes effect if
- the memory commands are activated globally (CONFIG_CMD_MEM).
+ the memory commands are activated globally (CONFIG_CMD_MEMORY).
- CONFIG_MX_CYCLIC
Add the "mdc" and "mwc" memory commands. These are cyclic
@@ -4960,10 +3298,10 @@
This command will write 12345678 to address 100 all 10 ms.
This only takes effect if the memory commands are activated
- globally (CONFIG_CMD_MEM).
+ globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT
- [ARM, NDS32, MIPS only] If this variable is defined, then certain
+ [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
@@ -4973,6 +3311,11 @@
other boot loader or by a debugger which performs
these initializations itself.
+- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+ [ARM926EJ-S only] This allows just the call to lowlevel_init()
+ to be skipped. The normal CP15 init (such as enabling the
+ instruction cache) is still performed.
+
- CONFIG_SPL_BUILD
Modifies the behaviour of start.S when compiling a loader
that is executed before the actual U-Boot. E.g. when
@@ -4997,28 +3340,14 @@
addressable memory. This option causes some memory accesses
to be mapped through map_sysmem() / unmap_sysmem().
-- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
- If these options are used a optimized version of memcpy/memset will
- be used if available. These functions may be faster under some
- conditions but may increase the binary size.
-
- CONFIG_X86_RESET_VECTOR
If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot.
-- CONFIG_SYS_MPUCLK
- Defines the MPU clock speed (in MHz).
-
- NOTE : currently only supported on AM335x platforms.
-
-- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
- Enables the RTC32K OSC on AM33xx based plattforms
-
- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Option to disable subpage write in NAND driver
driver that uses this:
- drivers/mtd/nand/davinci_nand.c
+ drivers/mtd/nand/raw/davinci_nand.c
Freescale QE/FMAN Firmware Support:
-----------------------------------
@@ -5058,10 +3387,6 @@
Specifies that QE/FMAN firmware is located on the primary SD/MMC
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
-- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
- Specifies that QE/FMAN firmware is located on the primary SPI
- device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
-
- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Specifies that QE/FMAN firmware is located in the remote (master)
memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
@@ -5080,21 +3405,26 @@
- CONFIG_FSL_MC_ENET
Enable the MC driver for Layerscape SoCs.
-- CONFIG_SYS_LS_MC_FW_ADDR
- The address in the storage device where the firmware is located. The
- meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
- is also specified.
+Freescale Layerscape Debug Server Support:
+-------------------------------------------
+The Freescale Layerscape Debug Server Support supports the loading of
+"Debug Server firmware" and triggering SP boot-rom.
+This firmware often needs to be loaded during U-Boot booting.
-- CONFIG_SYS_LS_MC_FW_LENGTH
- The maximum possible size of the firmware. The firmware binary format
- has a field that specifies the actual size of the firmware, but it
- might not be possible to read any part of the firmware unless some
- local storage is allocated to hold the entire firmware first.
+- CONFIG_SYS_MC_RSV_MEM_ALIGN
+ Define alignment of reserved memory MC requires
-- CONFIG_SYS_LS_MC_FW_IN_NOR
- Specifies that MC firmware is located in NOR flash, mapped as
- normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
- virtual address in NOR flash.
+Reproducible builds
+-------------------
+
+In order to achieve reproducible builds, timestamps used in the U-Boot build
+process have to be set to a fixed value.
+
+This is done using the SOURCE_DATE_EPOCH environment variable.
+SOURCE_DATE_EPOCH is to be set on the build host's shell, not as a configuration
+option for U-Boot or an environment variable in U-Boot.
+
+SOURCE_DATE_EPOCH should be set to a number of seconds since the epoch, in UTC.
Building the Software:
======================
@@ -5176,6 +3506,11 @@
Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment
variable.
+User specific CPPFLAGS, AFLAGS and CFLAGS can be passed to the compiler by
+setting the according environment variables KCPPFLAGS, KAFLAGS and KCFLAGS.
+For example to treat all compiler warnings as errors:
+
+ make KCFLAGS=-Werror
Please be aware that the Makefiles assume you are using GNU make, so
for instance on NetBSD you might need to use "gmake" instead of
@@ -5186,14 +3521,11 @@
to port U-Boot to your hardware platform. To do this, follow these
steps:
-1. Add a new configuration option for your board to the toplevel
- "boards.cfg" file, using the existing entries as examples.
- Follow the instructions there to keep the boards in order.
-2. Create a new directory to hold your board specific code. Add any
+1. Create a new directory to hold your board specific code. Add any
files you need. In your board directory, you will need at least
- the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
-3. Create a new configuration file "include/configs/<board>.h" for
- your board
+ the "Makefile" and a "<board>.c".
+2. Create a new configuration file "include/configs/<board>.h" for
+ your board.
3. If you're porting U-Boot to a new CPU, then also create a new
directory to hold your CPU specific code. Add any files you need.
4. Run "make <board>_defconfig" with your new name.
@@ -5215,33 +3547,10 @@
But before you submit such a patch, please verify that your modifi-
cation did not break existing code. At least make sure that *ALL* of
the supported boards compile WITHOUT ANY compiler warnings. To do so,
-just run the "MAKEALL" script, which will configure and build U-Boot
-for ALL supported system. Be warned, this will take a while. You can
-select which (cross) compiler to use by passing a `CROSS_COMPILE'
-environment variable to the script, i. e. to use the ELDK cross tools
-you can type
-
- CROSS_COMPILE=ppc_8xx- MAKEALL
-
-or to build on a native PowerPC system you can type
-
- CROSS_COMPILE=' ' MAKEALL
-
-When using the MAKEALL script, the default behaviour is to build
-U-Boot in the source directory. This location can be changed by
-setting the BUILD_DIR environment variable. Also, for each target
-built, the MAKEALL script saves two log files (<target>.ERR and
-<target>.MAKEALL) in the <source dir>/LOG directory. This default
-location can be changed by setting the MAKEALL_LOGDIR environment
-variable. For example:
-
- export BUILD_DIR=/tmp/build
- export MAKEALL_LOGDIR=/tmp/log
- CROSS_COMPILE=ppc_8xx- MAKEALL
-
-With the above settings build objects are saved in the /tmp/build,
-log files are saved in the /tmp/log and the source tree remains clean
-during the whole build process.
+just run the buildman script (tools/buildman/buildman), which will
+configure and build U-Boot for ALL supported system. Be warned, this
+will take a while. Please see the buildman README, or run 'buildman -H'
+for documentation.
See also "U-Boot Porting Guide" below.
@@ -5475,10 +3784,10 @@
unset, then it will be made silent if the U-Boot console
is silent.
- tftpsrcport - If this is set, the value is used for TFTP's
+ tftpsrcp - If this is set, the value is used for TFTP's
UDP source port.
- tftpdstport - If this is set, the value is used for TFTP's UDP
+ tftpdstp - If this is set, the value is used for TFTP's UDP
destination port instead of the Well Know Port 69.
tftpblocksize - Block size to use for TFTP transfers; if not set,
@@ -5492,10 +3801,24 @@
faster in networks with high packet loss rates or
with unreliable TFTP servers.
+ tftptimeoutcountmax - maximum count of TFTP timeouts (no
+ unit, minimum value = 0). Defines how many timeouts
+ can happen during a single file transfer before that
+ transfer is aborted. The default is 10, and 0 means
+ 'no timeouts allowed'. Increasing this value may help
+ downloads succeed with high packet loss rates, or with
+ unreliable TFTP servers or client hardware.
+
vlan - When set to a value < 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
+ bootpretryperiod - Period during which BOOTP/DHCP sends retries.
+ Unsigned value, in milliseconds. If not set, the period will
+ be either the default (28000), or a value based on
+ CONFIG_NET_RETRY_COUNT, if defined. This value has
+ precedence over the valu based on CONFIG_NET_RETRY_COUNT.
+
The following image location variables contain the location of images
used in booting. The "Image" column gives the role of the image and is
not an environment variable name. The other columns are environment
@@ -5505,7 +3828,7 @@
flash or offset in NAND flash.
*Note* - these variables don't have to be defined for all boards, some
-boards currenlty use other variables for these purposes, and some
+boards currently use other variables for these purposes, and some
boards use these variables for other purposes.
Image File Name RAM Address Flash Location
@@ -5581,6 +3904,21 @@
CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
".callbacks" environment variable in the default or embedded environment.
+If CONFIG_REGEX is defined, the variable_name above is evaluated as a
+regular expression. This allows multiple variables to be connected to
+the same callback without explicitly listing them all out.
+
+The signature of the callback functions is:
+
+ int callback(const char *name, const char *value, enum env_op op, int flags)
+
+* name - changed environment variable
+* value - new value of the environment variable
+* op - operation (create, overwrite, or delete)
+* flags - attributes of the environment variable change, see flags H_* in
+ include/search.h
+
+The return value is 0 if the variable change is accepted and 1 otherwise.
Command Line Parsing:
=====================
@@ -5655,7 +3993,8 @@
warning is printed.
o If neither SROM nor the environment contain a MAC address, an error
- is raised.
+ is raised. If CONFIG_NET_RANDOM_ETHADDR is defined, then in this case
+ a random, locally-assigned MAC is used.
If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
will be programmed into hardware as part of the initialization process. This
@@ -5690,9 +4029,9 @@
LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
INTEGRITY).
-* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
+* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
- Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
+ Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).
* Compression Type (uncompressed, gzip, bzip2)
* Load Address
* Entry Point
@@ -5901,9 +4240,10 @@
option). Given an image built by mkimage, the dumpimage extracts a "data file"
from the image:
- tools/dumpimage -i image -p position data_file
- -i ==> extract from the 'image' a specific 'data_file', \
- indexed by 'position'
+ tools/dumpimage -i image -T type -p position data_file
+ -i ==> extract from the 'image' a specific 'data_file'
+ -T ==> set image type to 'type'
+ -p ==> 'position' (starting at 0) of the 'data_file' inside the 'image'
Installing a Linux Image:
@@ -6387,11 +4727,6 @@
average for all boards 752 bytes for the whole U-Boot image,
624 text + 127 data).
-On Blackfin, the normal C ABI (except for P3) is followed as documented here:
- http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
-
- ==> U-Boot will use P3 to hold a pointer to the global data
-
On ARM, the following registers are used:
R0: function argument word/integer result
@@ -6433,6 +4768,22 @@
NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
or current versions of GCC may "optimize" the code too much.
+On RISC-V, the following registers are used:
+
+ x0: hard-wired zero (zero)
+ x1: return address (ra)
+ x2: stack pointer (sp)
+ x3: global pointer (gp)
+ x4: thread pointer (tp)
+ x5: link register (t0)
+ x8: frame pointer (fp)
+ x10-x11: arguments/return values (a0-1)
+ x12-x17: arguments (a2-7)
+ x28-31: temporaries (t3-6)
+ pc: program counter (pc)
+
+ ==> U-Boot will use gp to hold a pointer to the global data
+
Memory Management:
------------------
@@ -6487,9 +4838,9 @@
To be able to re-map memory U-Boot then jumps to its link address.
To be able to implement the initialization code in C, a (small!)
initial stack is set up in the internal Dual Ported RAM (in case CPUs
-which provide such a feature like MPC8xx or MPC8260), or in a locked
-part of the data cache. After that, U-Boot initializes the CPU core,
-the caches and the SIU.
+which provide such a feature like), or in a locked part of the data
+cache. After that, U-Boot initializes the CPU core, the caches and
+the SIU.
Next, all (potentially) available memory banks are mapped using a
preliminary mapping. For example, we put them on 512 MB boundaries
@@ -6594,8 +4945,9 @@
-----------------
All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory.
+coding style; see the kernel coding style guide at
+https://www.kernel.org/doc/html/latest/process/coding-style.html, and the
+script "scripts/Lindent" in your Linux kernel source directory.
Source files originating from a different project (for example the
MTD subsystem) are generally exempt from these guidelines and are not
@@ -6627,7 +4979,7 @@
Please see http://www.denx.de/wiki/U-Boot/Patches for details.
Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
-see http://lists.denx.de/mailman/listinfo/u-boot
+see https://lists.denx.de/listinfo/u-boot
When you send a patch, please include the following information with
it:
@@ -6641,7 +4993,8 @@
* A CHANGELOG entry as plaintext (separate from the patch)
-* For major contributions, your entry to the CREDITS file
+* For major contributions, add a MAINTAINERS file with your
+ information and associated file and directory references.
* When you add support for a new board, don't forget to add a
maintainer e-mail address to the boards.cfg file, too.
@@ -6676,7 +5029,7 @@
Notes:
-* Before sending the patch, run the MAKEALL script on your patched
+* Before sending the patch, run the buildman script on your patched
source tree and make sure that no errors or warnings are reported
for any of the boards.
diff --git a/amlogic_help.sh b/amlogic_help.sh
deleted file mode 100755
index d29218d..0000000
--- a/amlogic_help.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-# print amlogic board config
-
-if [ -z ${srctree} ]; then
- srctree=`pwd`
-fi
-
-folder_board=${srctree}"/board/amlogic"
-
-#echo $folder_board
-#ls -a ${folder_board}
-
-echo ""
-echo "**************Amlogic Configs**************"
-echo "* *"
-echo "* ./mk (config_name) *"
-echo "* *"
-echo "*******************************************"
-
-for file in ${folder_board}/*; do
- temp_file=`basename $file`
- #echo "$temp_file"
- if [ -d ${folder_board}/${temp_file} ] && [ "$temp_file" != "defconfigs" ] && [ "$temp_file" != "configs" ];then
- printf "\t$temp_file\n"
- fi
-done
-
-echo "*******************************************"
-
-customer_folder=${srctree}"/customer/board"
-if [ -e ${customer_folder} ];then
- echo "**************Customer Configs*************"
- for file in ${customer_folder}/*; do
- temp_file=`basename $file`
- if [ -d ${customer_folder}/${temp_file} ] && [ "$temp_file" != "defconfigs" ] && [ "$temp_file" != "configs" ];then
- printf "\t$temp_file\n"
- fi
- done
- echo "*******************************************"
-fi
diff --git a/api/Kconfig b/api/Kconfig
new file mode 100644
index 0000000..16731d3
--- /dev/null
+++ b/api/Kconfig
@@ -0,0 +1,9 @@
+menu "API"
+
+config API
+ bool "Enable U-Boot API"
+ default n
+ help
+ This option enables the U-Boot API. See api/README for more information.
+
+endmenu
diff --git a/api/Makefile b/api/Makefile
index 3c095ee..bd2d035 100644
--- a/api/Makefile
+++ b/api/Makefile
@@ -1,9 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2007 Semihalf
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += api.o api_display.o api_net.o api_storage.o
obj-$(CONFIG_ARM) += api_platform-arm.o
obj-$(CONFIG_PPC) += api_platform-powerpc.o
+obj-$(CONFIG_MIPS) += api_platform-mips.o
diff --git a/api/api.c b/api/api.c
index c5f6edb..9f03f1a 100644
--- a/api/api.c
+++ b/api/api.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
@@ -52,7 +51,7 @@
{
int *c;
- if ((c = (int *)va_arg(ap, u_int32_t)) == NULL)
+ if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*c = getc();
@@ -68,7 +67,7 @@
{
int *t;
- if ((t = (int *)va_arg(ap, u_int32_t)) == NULL)
+ if ((t = (int *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*t = tstc();
@@ -84,7 +83,7 @@
{
char *c;
- if ((c = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((c = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
putc(*c);
@@ -100,7 +99,7 @@
{
char *s;
- if ((s = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((s = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
puts(s);
@@ -132,7 +131,7 @@
{
struct sys_info *si;
- si = (struct sys_info *)va_arg(ap, u_int32_t);
+ si = (struct sys_info *)va_arg(ap, uintptr_t);
if (si == NULL)
return API_ENOMEM;
@@ -148,7 +147,7 @@
{
unsigned long *d;
- if ((d = (unsigned long *)va_arg(ap, u_int32_t)) == NULL)
+ if ((d = (unsigned long *)va_arg(ap, unsigned long)) == NULL)
return API_EINVAL;
udelay(*d);
@@ -164,11 +163,11 @@
{
unsigned long *base, *cur;
- cur = (unsigned long *)va_arg(ap, u_int32_t);
+ cur = (unsigned long *)va_arg(ap, unsigned long);
if (cur == NULL)
return API_EINVAL;
- base = (unsigned long *)va_arg(ap, u_int32_t);
+ base = (unsigned long *)va_arg(ap, unsigned long);
if (base == NULL)
return API_EINVAL;
@@ -189,7 +188,7 @@
*
* - net: ð_device struct address from list pointed to by eth_devices
*
- * - storage: block_dev_desc_t struct address from &ide_dev_desc[n],
+ * - storage: struct blk_desc struct address from &ide_dev_desc[n],
* &scsi_dev_desc[n] and similar tables
*
****************************************************************************/
@@ -199,7 +198,7 @@
struct device_info *di;
/* arg is ptr to the device_info struct we are going to fill out */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
@@ -233,7 +232,7 @@
int err = 0;
/* arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
@@ -265,7 +264,7 @@
int err = 0;
/* arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
@@ -319,7 +318,7 @@
int err = 0;
/* 1. arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
@@ -329,12 +328,12 @@
return API_ENODEV;
/* 2. arg is ptr to buffer from where to get data to write */
- buf = (void *)va_arg(ap, u_int32_t);
+ buf = (void *)va_arg(ap, uintptr_t);
if (buf == NULL)
return API_EINVAL;
/* 3. arg is length of buffer */
- len = (int *)va_arg(ap, u_int32_t);
+ len = (int *)va_arg(ap, uintptr_t);
if (len == NULL)
return API_EINVAL;
if (*len <= 0)
@@ -387,7 +386,7 @@
int *len_net, *act_len_net;
/* 1. arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
@@ -397,23 +396,23 @@
return API_ENODEV;
/* 2. arg is ptr to buffer from where to put the read data */
- buf = (void *)va_arg(ap, u_int32_t);
+ buf = (void *)va_arg(ap, uintptr_t);
if (buf == NULL)
return API_EINVAL;
if (di->type & DEV_TYP_STOR) {
/* 3. arg - ptr to var with # of blocks to read */
- len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+ len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
if (!len_stor)
return API_EINVAL;
if (*len_stor <= 0)
return API_EINVAL;
/* 4. arg - ptr to var with start block */
- start = (lbastart_t *)va_arg(ap, u_int32_t);
+ start = (lbastart_t *)va_arg(ap, uintptr_t);
/* 5. arg - ptr to var where to put the len actually read */
- act_len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+ act_len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
if (!act_len_stor)
return API_EINVAL;
@@ -422,14 +421,14 @@
} else if (di->type & DEV_TYP_NET) {
/* 3. arg points to the var with length of packet to read */
- len_net = (int *)va_arg(ap, u_int32_t);
+ len_net = (int *)va_arg(ap, uintptr_t);
if (!len_net)
return API_EINVAL;
if (*len_net <= 0)
return API_EINVAL;
/* 4. - ptr to var where to put the len actually read */
- act_len_net = (int *)va_arg(ap, u_int32_t);
+ act_len_net = (int *)va_arg(ap, uintptr_t);
if (!act_len_net)
return API_EINVAL;
@@ -453,12 +452,12 @@
{
char *name, **value;
- if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- if ((value = (char **)va_arg(ap, u_int32_t)) == NULL)
+ if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- *value = getenv(name);
+ *value = env_get(name);
return 0;
}
@@ -476,12 +475,12 @@
{
char *name, *value;
- if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- if ((value = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- setenv(name, value);
+ env_set(name, value);
return 0;
}
@@ -495,45 +494,47 @@
*/
static int API_env_enum(va_list ap)
{
- int i, n;
- char *last, **next;
+ int i, buflen;
+ char *last, **next, *s;
+ ENTRY *match, search;
+ static char *var;
- last = (char *)va_arg(ap, u_int32_t);
+ last = (char *)va_arg(ap, unsigned long);
- if ((next = (char **)va_arg(ap, u_int32_t)) == NULL)
+ if ((next = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- if (last == NULL)
- /* start over */
- *next = ((char *)env_get_addr(0));
- else {
- *next = last;
-
- for (i = 0; env_get_char(i) != '\0'; i = n + 1) {
- for (n = i; env_get_char(n) != '\0'; ++n) {
- if (n >= CONFIG_ENV_SIZE) {
- /* XXX shouldn't we set *next = NULL?? */
- return 0;
- }
- }
-
- if (envmatch((uchar *)last, i) < 0)
- continue;
-
- /* try to get next name */
- i = n + 1;
- if (env_get_char(i) == '\0') {
- /* no more left */
- *next = NULL;
- return 0;
- }
-
- *next = ((char *)env_get_addr(i));
- return 0;
+ if (last == NULL) {
+ var = NULL;
+ i = 0;
+ } else {
+ var = strdup(last);
+ s = strchr(var, '=');
+ if (s != NULL)
+ *s = 0;
+ search.key = var;
+ i = hsearch_r(search, FIND, &match, &env_htab, 0);
+ if (i == 0) {
+ i = API_EINVAL;
+ goto done;
}
}
+ /* match the next entry after i */
+ i = hmatch_r("", i, &match, &env_htab);
+ if (i == 0)
+ goto done;
+ buflen = strlen(match->key) + strlen(match->data) + 2;
+ var = realloc(var, buflen);
+ snprintf(var, buflen, "%s=%s", match->key, match->data);
+ *next = var;
return 0;
+
+done:
+ free(var);
+ var = NULL;
+ *next = NULL;
+ return i;
}
/*
@@ -623,7 +624,7 @@
void api_init(void)
{
- struct api_signature *sig = NULL;
+ struct api_signature *sig;
/* TODO put this into linker set one day... */
calls_table[API_RSVD] = NULL;
@@ -661,14 +662,15 @@
return;
}
- debugf("API sig @ 0x%08x\n", sig);
+ env_set_hex("api_address", (unsigned long)sig);
+ debugf("API sig @ 0x%lX\n", (unsigned long)sig);
memcpy(sig->magic, API_SIG_MAGIC, 8);
sig->version = API_SIG_VERSION;
sig->syscall = &syscall;
sig->checksum = 0;
sig->checksum = crc32(0, (unsigned char *)sig,
sizeof(struct api_signature));
- debugf("syscall entry: 0x%08x\n", sig->syscall);
+ debugf("syscall entry: 0x%lX\n", (unsigned long)sig->syscall);
}
void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,
diff --git a/api/api_display.c b/api/api_display.c
index fe04d39..8ae358a 100644
--- a/api/api_display.c
+++ b/api/api_display.c
@@ -1,6 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2011 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/api/api_net.c b/api/api_net.c
index 7b3805e..7515c26 100644
--- a/api/api_net.c
+++ b/api/api_net.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
@@ -12,8 +11,6 @@
#include <linux/types.h>
#include <api_public.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DEBUG
#undef DEBUG
@@ -25,7 +22,7 @@
#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
static int dev_valid_net(void *cookie)
{
@@ -37,7 +34,7 @@
if (!dev_valid_net(cookie))
return API_ENODEV;
- if (eth_init(gd->bd) < 0)
+ if (eth_init() < 0)
return API_EIO;
return 0;
diff --git a/api/api_platform-arm.c b/api/api_platform-arm.c
index eb5338f..6cfd9e6 100644
--- a/api/api_platform-arm.c
+++ b/api/api_platform-arm.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* This file contains routines that fetch data from ARM-dependent sources
* (bd_info etc.)
*/
diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c
new file mode 100644
index 0000000..51cd328
--- /dev/null
+++ b/api/api_platform-mips.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007 Stanislav Galabov <sgalabov@gmail.com>
+ *
+ * This file contains routines that fetch data from bd_info sources
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+#include "api_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Important notice: handling of individual fields MUST be kept in sync with
+ * include/asm-generic/u-boot.h, so any changes
+ * need to reflect their current state and layout of structures involved!
+ */
+int platform_sys_info(struct sys_info *si)
+{
+
+ platform_set_mr(si, gd->bd->bi_memstart,
+ gd->bd->bi_memsize, MR_ATTR_DRAM);
+
+ return 1;
+}
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index f23f175..15930cf 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* This file contains routines that fetch data from PowerPC-dependent sources
* (bd_info etc.)
*/
@@ -30,11 +29,8 @@
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
- defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
-#elif defined(CONFIG_MPC5xxx)
-#define bi_bar bi_mbar_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
#endif
diff --git a/api/api_private.h b/api/api_private.h
index a8866ef..8d97ca9 100644
--- a/api/api_private.h
+++ b/api/api_private.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _API_PRIVATE_H_
diff --git a/api/api_storage.c b/api/api_storage.c
index b76b07d..2b90c18 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
@@ -37,16 +36,19 @@
int max_dev;
int enum_started;
int enum_ended;
- int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
+ int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
char *name;
};
-static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
+#ifndef CONFIG_SYS_MMC_MAX_DEVICE
+#define CONFIG_SYS_MMC_MAX_DEVICE 1
+#endif
void dev_stor_init(void)
{
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
specs[ENUM_IDE].enum_started = 0;
specs[ENUM_IDE].enum_ended = 0;
@@ -60,14 +62,14 @@
specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
specs[ENUM_MMC].name = "mmc";
#endif
-#if defined(CONFIG_CMD_SATA)
+#if defined(CONFIG_SATA)
specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
specs[ENUM_SATA].enum_started = 0;
specs[ENUM_SATA].enum_ended = 0;
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
@@ -88,97 +90,87 @@
*
* type: storage group type - ENUM_IDE, ENUM_SCSI etc.
*
- * first: if 1 the first device in the storage group is returned (if
- * exists), if 0 the next available device is searched
- *
* more: returns 0/1 depending if there are more devices in this group
* available (for future iterations)
*
* returns: 0/1 depending if device found in this iteration
*/
-static int dev_stor_get(int type, int first, int *more, struct device_info *di)
+static int dev_stor_get(int type, int *more, struct device_info *di)
{
+ struct blk_desc *dd;
int found = 0;
- *more = 0;
+ int found_last = 0;
+ int i = 0;
- int i;
+ /* Wasn't configured for this type, return 0 directly */
+ if (specs[type].name == NULL)
+ return 0;
- block_dev_desc_t *dd;
-
- if (first) {
- di->cookie = (void *)get_dev(specs[type].name, 0);
- if (di->cookie == NULL)
- return 0;
- else
- found = 1;
-
- } else {
- for (i = 0; i < specs[type].max_dev; i++)
- if (di->cookie == (void *)get_dev(specs[type].name, i)) {
- /* previous cookie found -- advance to the
- * next device, if possible */
-
- if (++i >= specs[type].max_dev) {
- /* out of range, no more to enum */
- di->cookie = NULL;
- break;
- }
-
- di->cookie = (void *)get_dev(specs[type].name, i);
- if (di->cookie == NULL)
- return 0;
- else
- found = 1;
-
- /* provide hint if there are more devices in
- * this group to enumerate */
- if ((i + 1) < specs[type].max_dev)
- *more = 1;
-
+ if (di->cookie != NULL) {
+ /* Find the last device we've returned */
+ for (i = 0; i < specs[type].max_dev; i++) {
+ if (di->cookie ==
+ (void *)blk_get_dev(specs[type].name, i)) {
+ i += 1;
+ found_last = 1;
break;
}
+ }
+
+ if (!found_last)
+ i = 0;
}
+ for (; i < specs[type].max_dev; i++) {
+ di->cookie = (void *)blk_get_dev(specs[type].name, i);
+
+ if (di->cookie != NULL) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (i == specs[type].max_dev)
+ *more = 0;
+ else
+ *more = 1;
+
if (found) {
di->type = specs[type].type;
- if (di->cookie != NULL) {
- dd = (block_dev_desc_t *)di->cookie;
- if (dd->type == DEV_TYPE_UNKNOWN) {
- debugf("device instance exists, but is not active..");
- found = 0;
- } else {
- di->di_stor.block_count = dd->lba;
- di->di_stor.block_size = dd->blksz;
- }
+ dd = (struct blk_desc *)di->cookie;
+ if (dd->type == DEV_TYPE_UNKNOWN) {
+ debugf("device instance exists, but is not active..");
+ found = 0;
+ } else {
+ di->di_stor.block_count = dd->lba;
+ di->di_stor.block_size = dd->blksz;
}
-
- } else
+ } else {
di->cookie = NULL;
+ }
return found;
}
-/*
- * returns: ENUM_IDE, ENUM_USB etc. based on block_dev_desc_t
- */
-static int dev_stor_type(block_dev_desc_t *dd)
+/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
+
+static int dev_stor_type(struct blk_desc *dd)
{
int i, j;
for (i = ENUM_IDE; i < ENUM_MAX; i++)
for (j = 0; j < specs[i].max_dev; j++)
- if (dd == get_dev(specs[i].name, j))
+ if (dd == blk_get_dev(specs[i].name, j))
return i;
return ENUM_MAX;
}
-/*
- * returns: 0/1 whether cookie points to some device in this group
- */
+/* returns: 0/1 whether cookie points to some device in this group */
+
static int dev_is_stor(int type, struct device_info *di)
{
return (dev_stor_type(di->cookie) == type) ? 1 : 0;
@@ -209,18 +201,16 @@
*/
if (di->cookie == NULL) {
-
debugf("group%d - enum restart\n", type);
/*
* 1. Enumeration (re-)started: take the first available
* device, if exists
*/
- found = dev_stor_get(type, 1, &more, di);
+ found = dev_stor_get(type, &more, di);
specs[type].enum_started = 1;
} else if (dev_is_stor(type, di)) {
-
debugf("group%d - enum continued for the next device\n", type);
if (specs[type].enum_ended) {
@@ -229,10 +219,9 @@
}
/* 2a. Attempt to take a next available device in the group */
- found = dev_stor_get(type, 0, &more, di);
+ found = dev_stor_get(type, &more, di);
} else {
-
if (specs[type].enum_ended) {
debugf("group %d - already enumerated, skipping\n", type);
return 0;
@@ -244,7 +233,7 @@
/*
* 2b. If enumerating devices in this group did not
* happen before, it means the cookie pointed to a
- * device frome some other group (another storage
+ * device from some other group (another storage
* group, or network); in this case try to take the
* first available device from our group
*/
@@ -254,7 +243,7 @@
* Attempt to take the first device in this group:
*'first element' flag is set
*/
- found = dev_stor_get(type, 1, &more, di);
+ found = dev_stor_get(type, &more, di);
} else {
errf("group%d - out of order iteration\n", type);
@@ -271,7 +260,7 @@
if (found)
debugf("device found, returning cookie 0x%08x\n",
- (u_int32_t)di->cookie);
+ (u_int32_t)di->cookie);
else
debugf("no device found\n");
@@ -292,9 +281,7 @@
{
int i;
- /*
- * check: ide, usb, scsi, mmc
- */
+ /* check: ide, usb, scsi, mmc */
for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
if (dev_enum_stor(i, di))
return 1;
@@ -303,12 +290,12 @@
return 0;
}
-static int dev_stor_is_valid(int type, block_dev_desc_t *dd)
+static int dev_stor_is_valid(int type, struct blk_desc *dd)
{
int i;
for (i = 0; i < specs[type].max_dev; i++)
- if (dd == get_dev(specs[type].name, i))
+ if (dd == blk_get_dev(specs[type].name, i))
if (dd->type != DEV_TYPE_UNKNOWN)
return 1;
@@ -323,7 +310,7 @@
if (type == ENUM_MAX)
return API_ENODEV;
- if (dev_stor_is_valid(type, (block_dev_desc_t *)cookie))
+ if (dev_stor_is_valid(type, (struct blk_desc *)cookie))
return 0;
return API_ENODEV;
@@ -340,23 +327,10 @@
}
-static int dev_stor_index(block_dev_desc_t *dd)
-{
- int i, type;
-
- type = dev_stor_type(dd);
- for (i = 0; i < specs[type].max_dev; i++)
- if (dd == get_dev(specs[type].name, i))
- return i;
-
- return (specs[type].max_dev);
-}
-
-
lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
int type;
- block_dev_desc_t *dd = (block_dev_desc_t *)cookie;
+ struct blk_desc *dd = (struct blk_desc *)cookie;
if ((type = dev_stor_type(dd)) == ENUM_MAX)
return 0;
@@ -364,10 +338,14 @@
if (!dev_stor_is_valid(type, dd))
return 0;
+#ifdef CONFIG_BLK
+ return blk_dread(dd, start, len, buf);
+#else
if ((dd->block_read) == NULL) {
debugf("no block_read() for device 0x%08x\n", cookie);
return 0;
}
- return (dd->block_read(dev_stor_index(dd), start, len, buf));
+ return dd->block_read(dd, start, len, buf);
+#endif /* defined(CONFIG_BLK) */
}
diff --git a/arch/Kconfig b/arch/Kconfig
index f63cc5a..35e2712 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1,59 +1,169 @@
+config CREATE_ARCH_SYMLINK
+ bool
+
+config HAVE_ARCH_IOREMAP
+ bool
+
choice
prompt "Architecture select"
default SANDBOX
config ARC
bool "ARC architecture"
+ select ARCH_EARLY_INIT_R
+ select ARC_TIMER
+ select CLK
+ select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
+ select TIMER
config ARM
bool "ARM architecture"
- select HAVE_PRIVATE_LIBGCC
+ select CREATE_ARCH_SYMLINK
+ select HAVE_PRIVATE_LIBGCC if !ARM64
select SUPPORT_OF_CONTROL
-config AVR32
- bool "AVR32 architecture"
-
-config BLACKFIN
- bool "Blackfin architecture"
-
config M68K
bool "M68000 architecture"
+ select HAVE_PRIVATE_LIBGCC
+ select SYS_BOOT_GET_CMDLINE
+ select SYS_BOOT_GET_KBD
config MICROBLAZE
bool "MicroBlaze architecture"
select SUPPORT_OF_CONTROL
+ imply CMD_IRQ
config MIPS
bool "MIPS architecture"
+ select HAVE_ARCH_IOREMAP
select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
+ select SUPPORT_OF_CONTROL
config NIOS2
bool "Nios II architecture"
-
-config OPENRISC
- bool "OpenRISC architecture"
+ select CPU
+ select DM
+ select OF_CONTROL
+ select SUPPORT_OF_CONTROL
+ imply CMD_DM
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
+ select SYS_BOOT_GET_CMDLINE
+ select SYS_BOOT_GET_KBD
+
+config RISCV
+ bool "RISC-V architecture"
+ select SUPPORT_OF_CONTROL
+ select OF_CONTROL
+ select DM
+ imply DM_SERIAL
+ imply DM_ETH
+ imply DM_MMC
+ imply DM_SPI
+ imply DM_SPI_FLASH
+ imply BLK
+ imply CLK
+ imply MTD
+ imply TIMER
+ imply CMD_DM
config SANDBOX
bool "Sandbox"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_GPIO
+ select DM_I2C
+ select DM_KEYBOARD
+ select DM_MMC
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select HAVE_BLOCK_DEVICE
+ select LZO
+ select SPI
select SUPPORT_OF_CONTROL
+ imply BITREVERSE
+ select BLOBLIST
+ imply CMD_DM
+ imply CMD_GETTIME
+ imply CMD_HASH
+ imply CMD_IO
+ imply CMD_IOTRACE
+ imply CMD_LZMADEC
+ imply CMD_SATA
+ imply CMD_SF_TEST
+ imply CRC32_VERIFY
+ imply FAT_WRITE
+ imply FIRMWARE
+ imply HASH_VERIFY
+ imply LZMA
+ imply SCSI
+ imply TEE
+ imply AVB_VERIFY
+ imply LIBAVB
+ imply CMD_AVB
+ imply UDP_FUNCTION_FASTBOOT
+ imply VIRTIO_MMIO
+ imply VIRTIO_PCI
+ imply VIRTIO_SANDBOX
+ imply VIRTIO_BLK
+ imply VIRTIO_NET
+ imply DM_SOUND
config SH
bool "SuperH architecture"
select HAVE_PRIVATE_LIBGCC
-config SPARC
- bool "SPARC architecture"
-
config X86
bool "x86 architecture"
+ select CREATE_ARCH_SYMLINK
+ select DM
+ select DM_PCI
+ select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
+ select OF_CONTROL
+ select PCI
+ select SUPPORT_OF_CONTROL
+ select TIMER
+ select USE_PRIVATE_LIBGCC
+ select X86_TSC_TIMER
+ imply BLK
+ imply CMD_DM
+ imply CMD_FPGA_LOADMK
+ imply CMD_GETTIME
+ imply CMD_IO
+ imply CMD_IRQ
+ imply CMD_PCI
+ imply CMD_SF_TEST
+ imply CMD_ZBOOT
+ imply DM_ETH
+ imply DM_GPIO
+ imply DM_KEYBOARD
+ imply DM_MMC
+ imply DM_RTC
+ imply DM_SCSI
+ imply DM_SERIAL
+ imply DM_SPI
+ imply DM_SPI_FLASH
+ imply DM_USB
+ imply DM_VIDEO
+ imply SYSRESET
+ imply SYSRESET_X86
+ imply USB_ETHER_ASIX
+ imply USB_ETHER_SMSC95XX
+ imply USB_HOST_ETHER
+
+config XTENSA
+ bool "Xtensa architecture"
+ select CREATE_ARCH_SYMLINK
select SUPPORT_OF_CONTROL
endchoice
@@ -116,16 +226,14 @@
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
-source "arch/avr32/Kconfig"
-source "arch/blackfin/Kconfig"
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
-source "arch/openrisc/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
source "arch/sh/Kconfig"
-source "arch/sparc/Kconfig"
source "arch/x86/Kconfig"
+source "arch/xtensa/Kconfig"
+source "arch/riscv/Kconfig"
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index d3ef58b..fa6b344 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -4,25 +4,170 @@
config SYS_ARCH
default "arc"
+config SYS_CPU
+ default "arcv1" if ISA_ARCOMPACT
+ default "arcv2" if ISA_ARCV2
+
+choice
+ prompt "ARC Instruction Set"
+ default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+ bool "ARCompact ISA"
+ help
+ The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+ bool "ARC ISA v2"
+ help
+ ISA for the Next Generation ARC-HS cores
+
+endchoice
+
+choice
+ prompt "CPU selection"
+ default CPU_ARC770D if ISA_ARCOMPACT
+ default CPU_ARCHS38 if ISA_ARCV2
+
+config CPU_ARC750D
+ bool "ARC 750D"
+ depends on ISA_ARCOMPACT
+ select ARC_MMU_V2
+ help
+ Choose this option to build an U-Boot for ARC750D CPU.
+
+config CPU_ARC770D
+ bool "ARC 770D"
+ depends on ISA_ARCOMPACT
+ select ARC_MMU_V3
+ help
+ Choose this option to build an U-Boot for ARC770D CPU.
+
+config CPU_ARCEM6
+ bool "ARC EM6"
+ depends on ISA_ARCV2
+ select ARC_MMU_ABSENT
+ help
+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+ bool "ARC HS36"
+ depends on ISA_ARCV2
+ select ARC_MMU_ABSENT
+ help
+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+ bool "ARC HS38"
+ depends on ISA_ARCV2
+ select ARC_MMU_V4
+ help
+ Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
+endchoice
+
+choice
+ prompt "MMU Version"
+ default ARC_MMU_V3 if CPU_ARC770D
+ default ARC_MMU_V2 if CPU_ARC750D
+ default ARC_MMU_ABSENT if CPU_ARCEM6
+ default ARC_MMU_ABSENT if CPU_ARCHS36
+ default ARC_MMU_V4 if CPU_ARCHS38
+
+config ARC_MMU_ABSENT
+ bool "No MMU"
+ help
+ No MMU
+
+config ARC_MMU_V2
+ bool "MMU v2"
+ depends on CPU_ARC750D
+ help
+ Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
+ when 2 D-TLB and 1 I-TLB entries index into same 2way set.
+
+config ARC_MMU_V3
+ bool "MMU v3"
+ depends on CPU_ARC770D
+ help
+ Introduced with ARC700 4.10: New Features
+ Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
+ Shared Address Spaces (SASID)
+
+config ARC_MMU_V4
+ bool "MMU v4"
+ depends on CPU_ARCHS38
+ help
+ Introduced as a part of ARC HS38 release.
+
+endchoice
+
+config CPU_BIG_ENDIAN
+ bool "Enable Big Endian Mode"
+ default n
+ help
+ Build kernel for Big Endian Mode of ARC CPU
+
+config SYS_ICACHE_OFF
+ bool "Do not use Instruction Cache"
+ default n
+
+config SYS_DCACHE_OFF
+ bool "Do not use Data Cache"
+ default n
+
+menuconfig ARC_DBG
+ bool "ARC debugging"
+ default n
+
+if ARC_DBG
+
+config ARC_DBG_IOC_ENABLE
+ bool "Enable IO coherency unit"
+ depends on CPU_ARCHS38
+ default n
+ help
+ Enable IO coherency unit to debug problems with caches and
+ DMA peripherals.
+ NOTE: as of today linux will not work properly if this option
+ is enabled in u-boot!
+
+endif
+
choice
prompt "Target select"
+ default TARGET_AXS103
config TARGET_TB100
bool "Support tb100"
-config TARGET_ARCANGEL4
- bool "Support arcangel4"
-
-config TARGET_ARCANGEL4_BE
- bool "Support arcangel4-be"
+config TARGET_NSIM
+ bool "Support standalone nSIM & Free nSIM"
config TARGET_AXS101
- bool "Support axs101"
+ bool "Support Synopsys Designware SDP board AXS101"
+
+config TARGET_AXS103
+ bool "Support Synopsys Designware SDP board AXS103"
+
+config TARGET_EMSDP
+ bool "Synopsys EM Software Development Platform"
+ select CPU_ARCEM6
+
+config TARGET_HSDK
+ bool "Support Synpsys HS DevelopmentKit board"
+
+config TARGET_IOT_DEVKIT
+ bool "Synopsys Brite IoT Development kit"
+ select CPU_ARCEM6
endchoice
source "board/abilis/tb100/Kconfig"
source "board/synopsys/Kconfig"
-source "board/synopsys/axs101/Kconfig"
+source "board/synopsys/axs10x/Kconfig"
+source "board/synopsys/emsdp/Kconfig"
+source "board/synopsys/hsdk/Kconfig"
+source "board/synopsys/iot_devkit/Kconfig"
endmenu
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 03ea6db..44568f8 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -1,8 +1,4 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-head-y := arch/arc/cpu/$(CPU)/start.o
+# SPDX-License-Identifier: GPL-2.0+
libs-y += arch/arc/cpu/$(CPU)/
libs-y += arch/arc/lib/
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index e408800..18005d9 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -1,33 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SYS_BIG_ENDIAN
+ifndef CONFIG_CPU_BIG_ENDIAN
CONFIG_SYS_LITTLE_ENDIAN = 1
+else
+CONFIG_SYS_BIG_ENDIAN = 1
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
-ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EL
+PLATFORM_CPPFLAGS += -mlittle-endian
endif
ifdef CONFIG_SYS_BIG_ENDIAN
-ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
PLATFORM_LDFLAGS += -EB
+PLATFORM_CPPFLAGS += -mbig-endian
endif
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := $(ARC_CROSS_COMPILE)
+ifdef CONFIG_ARC_MMU_VER
+CONFIG_MMU = 1
endif
-PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
+ifdef CONFIG_CPU_ARC750D
+PLATFORM_CPPFLAGS += -mcpu=arc700
+endif
+
+ifdef CONFIG_CPU_ARC770D
+PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+endif
+
+ifdef CONFIG_CPU_ARCEM6
+PLATFORM_CPPFLAGS += -mcpu=arcem
+endif
+
+ifdef CONFIG_CPU_ARCHS34
+PLATFORM_CPPFLAGS += -mcpu=archs
+endif
+
+ifdef CONFIG_CPU_ARCHS38
+PLATFORM_CPPFLAGS += -mcpu=archs
+endif
+
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
# Needed for relocation
-LDFLAGS_FINAL += -pie
+LDFLAGS_FINAL += -pie --gc-sections
# Load address for standalone apps
CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
-
-# Support generic board on ARC
-__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile
deleted file mode 100644
index cdc5002..0000000
--- a/arch/arc/cpu/arc700/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y += start.o
-
-obj-y += cache.o
-obj-y += cpu.o
-obj-y += interrupts.o
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c
deleted file mode 100644
index 39d522d..0000000
--- a/arch/arc/cpu/arc700/cache.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arcregs.h>
-
-/* Bit values in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE (1 << 0)
-
-/* Bit values in DC_CTRL */
-#define DC_CTRL_CACHE_DISABLE (1 << 0)
-#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
-#define DC_CTRL_FLUSH_STATUS (1 << 8)
-
-int icache_status(void)
-{
- return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
- IC_CTRL_CACHE_DISABLE;
-}
-
-void icache_enable(void)
-{
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
- ~IC_CTRL_CACHE_DISABLE);
-}
-
-void icache_disable(void)
-{
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
- IC_CTRL_CACHE_DISABLE);
-}
-
-void invalidate_icache_all(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- /* Any write to IC_IVIC register triggers invalidation of entire I$ */
- write_aux_reg(ARC_AUX_IC_IVIC, 1);
-#endif /* CONFIG_SYS_ICACHE_OFF */
-}
-
-int dcache_status(void)
-{
- return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
- DC_CTRL_CACHE_DISABLE;
-}
-
-void dcache_enable(void)
-{
- write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
- ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
-}
-
-void dcache_disable(void)
-{
- write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
- DC_CTRL_CACHE_DISABLE);
-}
-
-void flush_dcache_all(void)
-{
- /* Do flush of entire cache */
- write_aux_reg(ARC_AUX_DC_FLSH, 1);
-
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-static void dcache_flush_line(unsigned addr)
-{
-#if (CONFIG_ARC_MMU_VER > 2)
- write_aux_reg(ARC_AUX_DC_PTAG, addr);
-#endif
- write_aux_reg(ARC_AUX_DC_FLDL, addr);
-
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
-
-#ifndef CONFIG_SYS_ICACHE_OFF
- /*
- * Invalidate I$ for addresses range just flushed from D$.
- * If we try to execute data flushed above it will be valid/correct
- */
-#if (CONFIG_ARC_MMU_VER > 2)
- write_aux_reg(ARC_AUX_IC_PTAG, addr);
-#endif
- write_aux_reg(ARC_AUX_IC_IVIL, addr);
-#endif /* CONFIG_SYS_ICACHE_OFF */
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- unsigned int addr;
-
- start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
- end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
- dcache_flush_line(addr);
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- unsigned int addr;
-
- start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
- end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
-#if (CONFIG_ARC_MMU_VER > 2)
- write_aux_reg(ARC_AUX_DC_PTAG, addr);
-#endif
- write_aux_reg(ARC_AUX_DC_IVDL, addr);
- }
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
-
-void invalidate_dcache_all(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
- write_aux_reg(ARC_AUX_DC_IVDC, 1);
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arc700/config.mk
deleted file mode 100644
index 3206ff4..0000000
--- a/arch/arc/cpu/arc700/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mA7
diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/cpu/arc700/cpu.c
deleted file mode 100644
index 50634b8..0000000
--- a/arch/arc/cpu/arc700/cpu.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arcregs.h>
-#include <asm/cache.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int arch_cpu_init(void)
-{
-#ifdef CONFIG_SYS_ICACHE_OFF
- icache_disable();
-#else
- icache_enable();
- invalidate_icache_all();
-#endif
-
- flush_dcache_all();
-#ifdef CONFIG_SYS_DCACHE_OFF
- dcache_disable();
-#else
- dcache_enable();
-#endif
- timer_init();
-
-/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
- if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
- gd->arch.running_on_hw = 0;
- else
- gd->arch.running_on_hw = 1;
-
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
-
-int arch_early_init_r(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- return 0;
-}
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c
deleted file mode 100644
index d93a6eb..0000000
--- a/arch/arc/cpu/arc700/interrupts.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arcregs.h>
-#include <asm/ptrace.h>
-
-/* Bit values in STATUS32 */
-#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
-#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-/*
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts(void)
-{
- int status = read_aux_reg(ARC_AUX_STATUS32);
- int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
-
- status &= ~(E1_MASK | E2_MASK);
- /* STATUS32 register is updated indirectly with "FLAG" instruction */
- __asm__("flag %0" : : "r" (status));
- return state;
-}
-
-void enable_interrupts(void)
-{
- unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
-
- status |= E1_MASK | E2_MASK;
- /* STATUS32 register is updated indirectly with "FLAG" instruction */
- __asm__("flag %0" : : "r" (status));
-}
-
-static void print_reg_file(long *reg_rev, int start_num)
-{
- unsigned int i;
-
- /* Print 3 registers per line */
- for (i = start_num; i < start_num + 25; i++) {
- printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
- if (((i + 1) % 3) == 0)
- printf("\n");
-
- /* Because pt_regs has registers reversed */
- reg_rev--;
- }
-
- /* Add new-line if none was inserted in the end of loop above */
- if (((i + 1) % 3) != 0)
- printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
- regs->ret, regs->blink, regs->status32);
- printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
- printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
- regs->sp, regs->fp);
- printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
- regs->lp_end, regs->lp_count);
-
- print_reg_file(&(regs->r0), 0);
-}
-
-void bad_mode(struct pt_regs *regs)
-{
- if (regs)
- show_regs(regs);
-
- panic("Resetting CPU ...\n");
-}
-
-void do_memory_error(unsigned long address, struct pt_regs *regs)
-{
- printf("Memory error exception @ 0x%lx\n", address);
- bad_mode(regs);
-}
-
-void do_instruction_error(unsigned long address, struct pt_regs *regs)
-{
- printf("Instruction error exception @ 0x%lx\n", address);
- bad_mode(regs);
-}
-
-void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
-{
- printf("Machine check exception @ 0x%lx\n", address);
- bad_mode(regs);
-}
-
-void do_interrupt_handler(void)
-{
- printf("Interrupt fired\n");
- bad_mode(0);
-}
-
-void do_itlb_miss(struct pt_regs *regs)
-{
- printf("I TLB miss exception\n");
- bad_mode(regs);
-}
-
-void do_dtlb_miss(struct pt_regs *regs)
-{
- printf("D TLB miss exception\n");
- bad_mode(regs);
-}
-
-void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
-{
- printf("TLB protection violation or misaligned access @ 0x%lx\n",
- address);
- bad_mode(regs);
-}
-
-void do_privilege_violation(struct pt_regs *regs)
-{
- printf("Privilege violation exception\n");
- bad_mode(regs);
-}
-
-void do_trap(struct pt_regs *regs)
-{
- printf("Trap exception\n");
- bad_mode(regs);
-}
-
-void do_extension(struct pt_regs *regs)
-{
- printf("Extension instruction exception\n");
- bad_mode(regs);
-}
diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/cpu/arc700/reset.c
deleted file mode 100644
index 98ebf1d..0000000
--- a/arch/arc/cpu/arc700/reset.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <command.h>
-#include <common.h>
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- printf("Put your restart handler here\n");
-
-#ifdef DEBUG
- /* Stop debug session here */
- __asm__("brk");
-#endif
- return 0;
-}
diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S
deleted file mode 100644
index 563513b..0000000
--- a/arch/arc/cpu/arc700/start.S
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/arcregs.h>
-
-/*
- * Note on the LD/ST addressing modes with address register write-back
- *
- * LD.a same as LD.aw
- *
- * LD.a reg1, [reg2, x] => Pre Incr
- * Eff Addr for load = [reg2 + x]
- *
- * LD.ab reg1, [reg2, x] => Post Incr
- * Eff Addr for load = [reg2]
- */
-
-.macro PUSH reg
- st.a \reg, [%sp, -4]
-.endm
-
-.macro PUSHAX aux
- lr %r9, [\aux]
- PUSH %r9
-.endm
-
-.macro SAVE_R1_TO_R24
- PUSH %r1
- PUSH %r2
- PUSH %r3
- PUSH %r4
- PUSH %r5
- PUSH %r6
- PUSH %r7
- PUSH %r8
- PUSH %r9
- PUSH %r10
- PUSH %r11
- PUSH %r12
- PUSH %r13
- PUSH %r14
- PUSH %r15
- PUSH %r16
- PUSH %r17
- PUSH %r18
- PUSH %r19
- PUSH %r20
- PUSH %r21
- PUSH %r22
- PUSH %r23
- PUSH %r24
-.endm
-
-.macro SAVE_ALL_SYS
-
- st %r0, [%sp]
- lr %r0, [%ecr]
- st %r0, [%sp, 8] /* ECR */
- st %sp, [%sp, 4]
-
- SAVE_R1_TO_R24
- PUSH %r25
- PUSH %gp
- PUSH %fp
- PUSH %blink
- PUSHAX %eret
- PUSHAX %erstatus
- PUSH %lp_count
- PUSHAX %lp_end
- PUSHAX %lp_start
- PUSHAX %erbta
-.endm
-
-.align 4
-.globl _start
-_start:
- /* Critical system events */
- j reset /* 0 - 0x000 */
- j memory_error /* 1 - 0x008 */
- j instruction_error /* 2 - 0x010 */
-
- /* Device interrupts */
-.rept 29
- j interrupt_handler /* 3:31 - 0x018:0xF8 */
-.endr
- /* Exceptions */
- j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
- j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
- j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
- j EV_TLBProtV /* 0x118, Protection Violation (0x23)
- or Misaligned Access */
- j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
- j EV_Trap /* 0x128, Trap exception (0x25) */
- j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
-
-memory_error:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_memory_error
-
-instruction_error:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_instruction_error
-
-interrupt_handler:
- /* Todo - save and restore CPU context when interrupts will be in use */
- bl do_interrupt_handler
- rtie
-
-EV_MachineCheck:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_machine_check_fault
-
-EV_TLBMissI:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_itlb_miss
-
-EV_TLBMissD:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_dtlb_miss
-
-EV_TLBProtV:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_tlb_prot_violation
-
-EV_PrivilegeV:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_privilege_violation
-
-EV_Trap:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_trap
-
-EV_Extension:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_extension
-
-
-reset:
- /* Setup interrupt vector base that matches "__text_start" */
- sr __text_start, [ARC_AUX_INTR_VEC_BASE]
-
- /* Setup stack pointer */
- mov %sp, CONFIG_SYS_INIT_SP_ADDR
- mov %fp, %sp
-
- /* Clear bss */
- mov %r0, __bss_start
- mov %r1, __bss_end
-
-clear_bss:
- st.ab 0, [%r0, 4]
- brlt %r0, %r1, clear_bss
-
- /* Zero the one and only argument of "board_init_f" */
- mov_s %r0, 0
- j board_init_f
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r0 = start_addr_sp
- * r1 = new__gd
- * r2 = relocaddr
- */
-.align 4
-.globl relocate_code
-relocate_code:
- /*
- * r0-r12 might be clobbered by C functions
- * so we use r13-r16 for storage here
- */
- mov %r13, %r0 /* save addr_sp */
- mov %r14, %r1 /* save addr of gd */
- mov %r15, %r2 /* save addr of destination */
-
- mov %r16, %r2 /* %r9 - relocation offset */
- sub %r16, %r16, __image_copy_start
-
-/* Set up the stack */
-stack_setup:
- mov %sp, %r13
- mov %fp, %sp
-
-/* Check if monitor is loaded right in place for relocation */
- mov %r0, __image_copy_start
- cmp %r0, %r15 /* skip relocation if code loaded */
- bz do_board_init_r /* in target location already */
-
-/* Copy data (__image_copy_start - __image_copy_end) to new location */
- mov %r1, %r15
- mov %r2, __image_copy_end
- sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
- asr %r2, %r2, 2 /* r3 <- amount of words to copy */
- mov %lp_count, %r2
- lp copy_end
- ld.ab %r2,[%r0,4]
- st.ab %r2,[%r1,4]
-copy_end:
-
-/* Fix relocations related issues */
- bl do_elf_reloc_fixups
-#ifndef CONFIG_SYS_ICACHE_OFF
- bl invalidate_icache_all
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- bl flush_dcache_all
-#endif
-
-/* Update position of intterupt vector table */
- lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
- add %r0, %r0, %r16 /* Update address */
- sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
-
-do_board_init_r:
-/* Prepare for exection of "board_init_r" in relocated monitor */
- mov %r2, board_init_r /* old address of "board_init_r()" */
- add %r2, %r2, %r16 /* new address of "board_init_r()" */
- mov %r0, %r14 /* 1-st parameter: gd_t */
- mov %r1, %r15 /* 2-nd parameter: dest_addr */
- j [%r2]
diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/cpu/arc700/timer.c
deleted file mode 100644
index a0acbbc..0000000
--- a/arch/arc/cpu/arc700/timer.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arcregs.h>
-
-#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */
-
-int timer_init(void)
-{
- write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
- /* Set max value for counter/timer */
- write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
- /* Set initial count value and restart counter/timer */
- write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
- return 0;
-}
-
-unsigned long timer_read_counter(void)
-{
- return read_aux_reg(ARC_AUX_TIMER0_CNT);
-}
diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds
deleted file mode 100644
index 2d01b21..0000000
--- a/arch/arc/cpu/arc700/u-boot.lds
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
-OUTPUT_ARCH(arc)
-ENTRY(_start)
-SECTIONS
-{
- . = ALIGN(4);
- .text : {
- *(.__text_start)
- *(.__image_copy_start)
- CPUDIR/start.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .text_end :
- {
- *(.__text_end)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
- .rel_dyn_start : {
- *(.__rel_dyn_start)
- }
-
- .rela.dyn : {
- *(.rela.dyn)
- }
-
- .rel_dyn_end : {
- *(.__rel_dyn_end)
- }
-
- . = ALIGN(4);
- .bss_start : {
- *(.__bss_start);
- }
-
- .bss : {
- *(.bss*)
- }
-
- .bss_end : {
- *(.__bss_end);
- }
-
- . = ALIGN(4);
- .image_copy_end : {
- *(.__image_copy_end)
- *(.__init_end)
- }
-}
diff --git a/arch/arc/cpu/arcv1/Makefile b/arch/arc/cpu/arcv1/Makefile
new file mode 100644
index 0000000..4d42ac6
--- /dev/null
+++ b/arch/arc/cpu/arcv1/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+
+obj-y += ivt.o
diff --git a/arch/arc/cpu/arcv1/ivt.S b/arch/arc/cpu/arcv1/ivt.S
new file mode 100644
index 0000000..3d63430
--- /dev/null
+++ b/arch/arc/cpu/arcv1/ivt.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+.section .ivt, "ax",@progbits
+.align 4
+_ivt:
+ /* Critical system events */
+ j _start /* 0 - 0x000 */
+ j memory_error /* 1 - 0x008 */
+ j instruction_error /* 2 - 0x010 */
+
+ /* Device interrupts */
+.rept 29
+ j interrupt_handler /* 3:31 - 0x018:0xF8 */
+.endr
+ /* Exceptions */
+ j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
+ j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
+ j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
+ j EV_TLBProtV /* 0x118, Protection Violation (0x23)
+ or Misaligned Access */
+ j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
+ j EV_Trap /* 0x128, Trap exception (0x25) */
+ j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
diff --git a/arch/arc/cpu/arcv2/Makefile b/arch/arc/cpu/arcv2/Makefile
new file mode 100644
index 0000000..ab74026
--- /dev/null
+++ b/arch/arc/cpu/arcv2/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+
+obj-y += ivt.o
diff --git a/arch/arc/cpu/arcv2/ivt.S b/arch/arc/cpu/arcv2/ivt.S
new file mode 100644
index 0000000..3f5b409
--- /dev/null
+++ b/arch/arc/cpu/arcv2/ivt.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ */
+
+.section .ivt, "a",@progbits
+.align 4
+ /* Critical system events */
+.word _start /* 0x00 - Reset */
+.word memory_error /* 0x01 - Memory Error */
+.word instruction_error /* 0x02 - Instruction Error */
+
+ /* Exceptions */
+.word EV_MachineCheck /* 0x03 - Fatal Machine check */
+.word EV_TLBMissI /* 0x04 - Intruction TLB miss */
+.word EV_TLBMissD /* 0x05 - Data TLB miss */
+.word EV_TLBProtV /* 0x06 - Protection Violation or Misaligned Access */
+.word EV_PrivilegeV /* 0x07 - Privilege Violation */
+.word EV_SWI /* 0x08 - Software Interrupt */
+.word EV_Trap /* 0x09 - Trap */
+.word EV_Extension /* 0x0A - Extension Intruction Exception */
+.word EV_DivZero /* 0x0B - Division by Zero */
+.word EV_DCError /* 0x0C - Data cache consistency error */
+.word EV_Maligned /* 0x0D - Misaligned data access */
+.word 0 /* 0x0E - Unused */
+.word 0 /* 0x0F - Unused */
+
+ /* Device interrupts */
+.rept 240
+.word interrupt_handler /* 0x10 - 0xFF */
+.endr
diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds
new file mode 100644
index 0000000..e12145c
--- /dev/null
+++ b/arch/arc/cpu/u-boot.lds
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#include <config.h>
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+ . = CONFIG_SYS_TEXT_BASE;
+ __image_copy_start = .;
+ . = ALIGN(1024);
+ __ivt_start = .;
+ .ivt :
+ {
+ KEEP(*(.ivt))
+ }
+ __ivt_end = .;
+
+ . = ALIGN(1024);
+ __text_start = .;
+ .text : {
+ arch/arc/lib/start.o (.text*)
+ *(.text*)
+ }
+ __text_end = .;
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rela.dyn : {
+ *(.rela.dyn)
+ }
+ __rel_dyn_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : {
+ *(.bss*)
+ }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ __init_end = .;
+}
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
new file mode 100644
index 0000000..4f1e463
--- /dev/null
+++ b/arch/arc/dts/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb
+dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
+dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
+dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
+dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
+dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
+dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/arch/arc/dts/abilis_tb100.dts b/arch/arc/dts/abilis_tb100.dts
new file mode 100644
index 0000000..19e45b9
--- /dev/null
+++ b/arch/arc/dts/abilis_tb100.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "abilis,tb100";
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial@ff100000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff100000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+};
diff --git a/arch/arc/dts/axc001.dtsi b/arch/arc/dts/axc001.dtsi
new file mode 100644
index 0000000..412580a
--- /dev/null
+++ b/arch/arc/dts/axc001.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <750000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
diff --git a/arch/arc/dts/axc003.dtsi b/arch/arc/dts/axc003.dtsi
new file mode 100644
index 0000000..75a9de6
--- /dev/null
+++ b/arch/arc/dts/axc003.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
diff --git a/arch/arc/dts/axs101.dts b/arch/arc/dts/axs101.dts
new file mode 100644
index 0000000..fc9fa93
--- /dev/null
+++ b/arch/arc/dts/axs101.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+/include/ "axc001.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+ model = "snps,axs101";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
diff --git a/arch/arc/dts/axs103.dts b/arch/arc/dts/axs103.dts
new file mode 100644
index 0000000..6e2dd00
--- /dev/null
+++ b/arch/arc/dts/axs103.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+/include/ "axc003.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+ model = "snps,axs103";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
new file mode 100644
index 0000000..dfc0381
--- /dev/null
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
+
+ axs10x_mb@e0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0xe0000000 0x10000000>;
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
+
+ apbclk: apbclk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ uartclk: uartclk {
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ethernet@18000 {
+ compatible = "altr,socfpga-stmmac";
+ reg = < 0x18000 0x2000 >;
+ phy-mode = "gmii";
+ snps,pbl = < 32 >;
+ clocks = <&apbclk>;
+ clock-names = "stmmaceth";
+ max-speed = <100>;
+ };
+
+ ehci@0x40000 {
+ compatible = "generic-ehci";
+ reg = < 0x40000 0x100 >;
+ };
+
+ ohci@0x60000 {
+ compatible = "generic-ohci";
+ reg = < 0x60000 0x100 >;
+ };
+
+ uart0: serial0@22000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x22000 0x100>;
+ clocks = <&uartclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ spi0: spi@0 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&apbclk>;
+ clock-names = "spi_clk";
+ cs-gpio = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@11218 {
+ compatible = "snps,creg-gpio";
+ reg = <0x11218 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "axs-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <1>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
+ };
+};
diff --git a/arch/arc/dts/emsdp.dts b/arch/arc/dts/emsdp.dts
new file mode 100644
index 0000000..d307b95
--- /dev/null
+++ b/arch/arc/dts/emsdp.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "snps,emsdp";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial0@f0004000 {
+ compatible = "snps,dw-apb-uart";
+ clock-frequency = <100000000>;
+ reg = <0xf0004000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+};
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
new file mode 100644
index 0000000..f024b96
--- /dev/null
+++ b/arch/arc/dts/hsdk.dts
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
+
+/ {
+ model = "snps,hsdk";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ spi0 = &spi0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clk-fmeas {
+ clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+ <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+ <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+ <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+ <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+ <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+ <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+ <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
+ <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
+ <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
+ <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+ <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
+ <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
+ clock-names = "cpu-pll", "sys-pll",
+ "tun-pll", "ddr-clk",
+ "cpu-clk", "hdmi-pll",
+ "tun-clk", "hdmi-clk",
+ "apb-clk", "axi-clk",
+ "eth-clk", "usb-clk",
+ "sdio-clk", "hdmi-sys-clk",
+ "gfx-core-clk", "gfx-dma-clk",
+ "gfx-cfg-clk", "dmac-core-clk",
+ "dmac-cfg-clk", "sdio-ref-clk",
+ "spi-clk", "i2c-clk",
+ "uart-clk", "ebi-clk",
+ "rom-clk", "pwm-clk";
+ };
+
+ cgu_clk: cgu-clk@f0000000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial0@f0005000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf0005000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ ethernet@f0008000 {
+ #interrupt-cells = <1>;
+ compatible = "altr,socfpga-stmmac";
+ reg = <0xf0008000 0x2000>;
+ phy-mode = "gmii";
+ };
+
+ ehci@0xf0040000 {
+ compatible = "generic-ehci";
+ reg = <0xf0040000 0x100>;
+ };
+
+ ohci@0xf0060000 {
+ compatible = "generic-ohci";
+ reg = <0xf0060000 0x100>;
+ };
+
+ spi0: spi@f0020000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xf0020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+ clock-names = "spi_clk";
+ cs-gpio = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@f00014b0 {
+ compatible = "snps,creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "hsdk-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
+};
diff --git a/arch/arc/dts/iot_devkit.dts b/arch/arc/dts/iot_devkit.dts
new file mode 100644
index 0000000..ebf5a95
--- /dev/null
+++ b/arch/arc/dts/iot_devkit.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <144000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial0@80014000 {
+ compatible = "snps,dw-apb-uart";
+ clock-frequency = <16000000>;
+ reg = <0x80014000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ usb: usb@f0040000 {
+ compatible = "snps,dwc2";
+ reg = <0xf0040000 0x10000>;
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
+ };
+
+ usbphy: phy {
+ compatible = "nop-phy";
+ #phy-cells = <0>;
+ };
+};
diff --git a/arch/arc/dts/nsim.dts b/arch/arc/dts/nsim.dts
new file mode 100644
index 0000000..243ecb1
--- /dev/null
+++ b/arch/arc/dts/nsim.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "snps,nsim";
+
+ aliases {
+ console = &arcuart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <70000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ arcuart0: serial@0xc0fc1000 {
+ compatible = "snps,arc-uart";
+ reg = <0xc0fc1000 0x100>;
+ clock-frequency = <70000000>;
+ };
+
+};
diff --git a/arch/arc/dts/skeleton.dtsi b/arch/arc/dts/skeleton.dtsi
new file mode 100644
index 0000000..279fc6c
--- /dev/null
+++ b/arch/arc/dts/skeleton.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+
+ cpu_card {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ timer@0 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ reg = <0 1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256M */
+ };
+};
diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h
new file mode 100644
index 0000000..823906d
--- /dev/null
+++ b/arch/arc/include/asm/arc-bcr.h
@@ -0,0 +1,77 @@
+/*
+ * ARC Build Configuration Registers, with encoded hardware config
+ *
+ * Copyright (C) 2018 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARC_BCR_H
+#define __ARC_BCR_H
+#ifndef __ASSEMBLY__
+
+#include <config.h>
+
+union bcr_di_cache {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+ unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_slc_cfg {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:24, way:2, lsz:2, sz:4;
+#else
+ unsigned int sz:4, lsz:2, way:2, pad:24;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_generic {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:24, ver:8;
+#else
+ unsigned int ver:8, pad:24;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_clust_cfg {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
+#else
+ unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+union bcr_mmu_4 {
+ struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+ n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+ /* DTLB ITLB JES JE JA */
+ unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+ pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif
+ } fields;
+ unsigned int word;
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARC_BCR_H */
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 5d48d11..fff6591 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -1,12 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H
+#include <asm/cache.h>
+#include <config.h>
+
/*
* ARC architecture has additional address space - auxiliary registers.
* These registers are mostly used for configuration purposes.
@@ -14,22 +16,50 @@
* access: "lr"/"sr".
*/
+/*
+ * Typically 8 least significant bits of Build Configuration Register (BCR)
+ * describe version of the HW block in question. Moreover if decoded version
+ * is 0 this means given HW block is absent - this is especially useful because
+ * we may safely read BRC regardless HW block existence while an attempt to
+ * access any other AUX regs associated with this HW block lead to imediate
+ * "instruction error" exception.
+ *
+ * I.e. before using any cofigurable HW block it's required to make sure it
+ * exists at all, and for that we introduce a special macro below.
+ */
+#define ARC_BCR_VERSION_MASK GENMASK(7, 0)
+#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
+
#define ARC_AUX_IDENTITY 0x04
#define ARC_AUX_STATUS32 0x0a
+/* STATUS32 Bits Positions */
+#define STATUS_AD_BIT 19 /* Enable unaligned access */
+
/* Instruction cache related auxiliary registers */
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
#define ARC_AUX_IC_IVIL 0x19
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_IC_PTAG 0x1E
#endif
+#define ARC_BCR_IC_BUILD 0x77
+#define AUX_AUX_CACHE_LIMIT 0x5D
+#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
+
+/* ICCM and DCCM auxiliary registers */
+#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
+#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
+#define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
+#define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
+#define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
+
#define ARC_AUX_INTR_VEC_BASE 0x25
/* Data cache related auxiliary registers */
@@ -39,9 +69,40 @@
#define ARC_AUX_DC_IVDL 0x4A
#define ARC_AUX_DC_FLSH 0x4B
#define ARC_AUX_DC_FLDL 0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_DC_PTAG 0x5C
#endif
+#define ARC_BCR_DC_BUILD 0x72
+#define ARC_BCR_SLC 0xce
+#define ARC_AUX_SLC_CONFIG 0x901
+#define ARC_AUX_SLC_CTRL 0x903
+#define ARC_AUX_SLC_FLUSH 0x904
+#define ARC_AUX_SLC_INVALIDATE 0x905
+#define ARC_AUX_SLC_IVDL 0x910
+#define ARC_AUX_SLC_FLDL 0x912
+#define ARC_AUX_SLC_RGN_START 0x914
+#define ARC_AUX_SLC_RGN_START1 0x915
+#define ARC_AUX_SLC_RGN_END 0x916
+#define ARC_AUX_SLC_RGN_END1 0x917
+#define ARC_BCR_CLUSTER 0xcf
+
+/* MMU Management regs */
+#define ARC_AUX_MMU_BCR 0x6f
+
+/* IO coherency related auxiliary registers */
+#define ARC_AUX_IO_COH_ENABLE 0x500
+#define ARC_AUX_IO_COH_PARTIAL 0x501
+#define ARC_AUX_IO_COH_AP0_BASE 0x508
+#define ARC_AUX_IO_COH_AP0_SIZE 0x509
+
+/* XY-memory related */
+#define ARC_AUX_XY_BUILD 0x79
+
+/* DSP-extensions related auxiliary registers */
+#define ARC_AUX_DSP_BUILD 0x7A
+
+/* ARC Subsystems related auxiliary registers */
+#define ARC_AUX_SUBSYS_BUILD 0xF0
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */
@@ -50,6 +111,19 @@
/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val) \
__builtin_arc_sr((unsigned int)val, reg_immed)
+
+/* ARCNUM [15:8] - field to identify each core in a multi-core system */
+#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
+
+static const inline int is_isa_arcv2(void)
+{
+ return IS_ENABLED(CONFIG_ISA_ARCV2);
+}
+
+static const inline int is_isa_arcompact(void)
+{
+ return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
+}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index 85721aa..c6dd28e 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_BITOPS_H
@@ -16,4 +15,9 @@
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
#endif /* __ASM_ARC_BITOPS_H */
diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h
index 2fa9776..8c171bb 100644
--- a/arch/arc/include/asm/byteorder.h
+++ b/arch/arc/include/asm/byteorder.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_BYTEORDER_H
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 16e7568..1604cd0 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_CACHE_H
@@ -10,14 +9,34 @@
#include <config.h>
/*
- * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
- * We use that value for aligning DMA buffers unless the board config has
- * specified an alternate cache line size.
+ * As of today we may handle any L1 cache line length right in software.
+ * For that essentially cache line length is a variable not constant.
+ * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
+ * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
*/
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
#define ARCH_DMA_MINALIGN 128
+
+#if defined(ARC_MMU_ABSENT)
+#define CONFIG_ARC_MMU_VER 0
+#elif defined(CONFIG_ARC_MMU_V2)
+#define CONFIG_ARC_MMU_VER 2
+#elif defined(CONFIG_ARC_MMU_V3)
+#define CONFIG_ARC_MMU_VER 3
+#elif defined(CONFIG_ARC_MMU_V4)
+#define CONFIG_ARC_MMU_VER 4
#endif
+#ifndef __ASSEMBLY__
+
+void cache_init(void);
+void flush_n_invalidate_dcache_all(void);
+void sync_n_cleanup_cache_all(void);
+
+static const inline int is_ioc_enabled(void)
+{
+ return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
+}
+
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
index e5be078..d88c361 100644
--- a/arch/arc/include/asm/config.h
+++ b/arch/arc/include/asm/config.h
@@ -1,13 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_LMB
diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/arc/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
index d644e80..8f9c83d 100644
--- a/arch/arc/include/asm/global_data.h
+++ b/arch/arc/include/asm/global_data.h
@@ -1,16 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_GLOBAL_DATA_H
#define __ASM_ARC_GLOBAL_DATA_H
+#include <config.h>
+
+#ifndef __ASSEMBLY__
/* Architecture-specific global data */
struct arch_global_data {
- int running_on_hw;
+ int l1_line_sz;
+#if defined(CONFIG_ISA_ARCV2)
+ int slc_line_sz;
+#endif
};
+#endif /* __ASSEMBLY__ */
#include <asm-generic/global_data.h>
diff --git a/arch/arc/include/asm/gpio.h b/arch/arc/include/asm/gpio.h
new file mode 100644
index 0000000..306ab4c
--- /dev/null
+++ b/arch/arc/include/asm/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 24b7337..fa844b5 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_IO_H
@@ -10,6 +9,46 @@
#include <linux/types.h>
#include <asm/byteorder.h>
+#ifdef __ARCHS__
+
+/*
+ * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
+ * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
+ *
+ * Explicit barrier provided by DMB instruction
+ * - Operand supports fine grained load/store/load+store semantics
+ * - Ensures that selected memory operation issued before it will complete
+ * before any subsequent memory operation of same type
+ * - DMB guarantees SMP as well as local barrier semantics
+ * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
+ * UP: barrier(), SMP: smp_*mb == *mb)
+ * - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
+ * in the general case. Plus it only provides full barrier.
+ */
+
+#define mb() asm volatile("dmb 3\n" : : : "memory")
+#define rmb() asm volatile("dmb 1\n" : : : "memory")
+#define wmb() asm volatile("dmb 2\n" : : : "memory")
+
+#else
+
+/*
+ * ARCompact based cores (ARC700) only have SYNC instruction which is super
+ * heavy weight as it flushes the pipeline as well.
+ * There are no real SMP implementations of such cores.
+ */
+
+#define mb() asm volatile("sync\n" : : : "memory")
+#endif
+
+#ifdef __ARCHS__
+#define __iormb() rmb()
+#define __iowmb() wmb()
+#else
+#define __iormb() asm volatile("" : : : "memory")
+#define __iowmb() asm volatile("" : : : "memory")
+#endif
+
static inline void sync(void)
{
/* Not yet implemented */
@@ -48,18 +87,6 @@
return w;
}
-#define readb __raw_readb
-
-static inline u16 readw(const volatile void __iomem *addr)
-{
- return __le16_to_cpu(__raw_readw(addr));
-}
-
-static inline u32 readl(const volatile void __iomem *addr)
-{
- return __le32_to_cpu(__raw_readl(addr));
-}
-
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
{
__asm__ __volatile__("stb%U1 %0, %1\n"
@@ -84,10 +111,6 @@
: "memory");
}
-#define writeb __raw_writeb
-#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
-#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
-
static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
{
__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
@@ -160,6 +183,45 @@
return longlen;
}
+/*
+ * MMIO can also get buffered/optimized in micro-arch, so barriers needed
+ * Based on ARM model for the typical use case
+ *
+ * <ST [DMA buffer]>
+ * <writel MMIO "go" reg>
+ * or:
+ * <readl MMIO "status" reg>
+ * <LD [DMA buffer]>
+ *
+ * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
+ */
+#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
+
+/*
+ * Relaxed API for drivers which can handle barrier ordering themselves
+ *
+ * Also these are defined to perform little endian accesses.
+ * To provide the typical device register semantics of fixed endian,
+ * swap the byte order for Big Endian
+ *
+ * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
+ */
+#define readb_relaxed(c) __raw_readb(c)
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+ __raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+ __raw_readl(c)); __r; })
+
+#define writeb_relaxed(v,c) __raw_writeb(v,c)
+#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
+#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
+
#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
@@ -215,4 +277,6 @@
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+#include <asm-generic/io.h>
+
#endif /* __ASM_ARC_IO_H */
diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h
new file mode 100644
index 0000000..2d42ed4
--- /dev/null
+++ b/arch/arc/include/asm/linkage.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_LINKAGE_H
+#define __ASM_ARC_LINKAGE_H
+
+#define ASM_NL ` /* use '`' to mark new line in macro */
+
+#endif /* __ASM_ARC_LINKAGE_H */
diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h
index 51347a4..13838cb 100644
--- a/arch/arc/include/asm/posix_types.h
+++ b/arch/arc/include/asm/posix_types.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_POSIX_TYPES_H
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
new file mode 100644
index 0000000..03e31fb
--- /dev/null
+++ b/arch/arc/include/asm/processor.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_ARC_PROCESSOR_H
+#define _ASM_ARC_PROCESSOR_H
+
+/* This file is required by some generic code like USB etc */
+
+#endif /* _ASM_ARC_PROCESSOR_H */
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 8f73b31..6965e89 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_PTRACE_H
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
index 18484a1..1c9c9db 100644
--- a/arch/arc/include/asm/sections.h
+++ b/arch/arc/include/asm/sections.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_SECTIONS_H
@@ -9,6 +8,7 @@
#include <asm-generic/sections.h>
-extern ulong __text_end;
+extern ulong __ivt_start;
+extern ulong __ivt_end;
#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
index 909129c..8b13789 100644
--- a/arch/arc/include/asm/string.h
+++ b/arch/arc/include/asm/string.h
@@ -1,27 +1 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARC_STRING_H
-#define __ASM_ARC_STRING_H
-
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_STRCHR
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRLEN
-
-extern void *memset(void *ptr, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-extern void memzero(void *ptr, __kernel_size_t n);
-extern int memcmp(const void *, const void *, __kernel_size_t);
-extern char *strchr(const char *s, int c);
-extern char *strcpy(char *dest, const char *src);
-extern int strcmp(const char *cs, const char *ct);
-extern __kernel_size_t strlen(const char *);
-
-#endif /* __ASM_ARC_STRING_H */
diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h
index 24eeb76..f31dcdf 100644
--- a/arch/arc/include/asm/types.h
+++ b/arch/arc/include/asm/types.h
@@ -1,48 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_TYPES_H
#define __ASM_ARC_TYPES_H
+#include <asm-generic/int-ll64.h>
+
typedef unsigned short umode_t;
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
#define BITS_PER_LONG 32
/* Dma addresses are 32-bits wide. */
diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h
index 0c0e8e6..dd2c094 100644
--- a/arch/arc/include/asm/u-boot-arc.h
+++ b/arch/arc/include/asm/u-boot-arc.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_U_BOOT_ARC_H__
@@ -9,4 +8,7 @@
int arch_early_init_r(void);
+void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
+void board_init_f_r(void) __attribute__ ((noreturn));
+
#endif /* __ASM_ARC_U_BOOT_ARC_H__ */
diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h
index e354edf..36c2207 100644
--- a/arch/arc/include/asm/u-boot.h
+++ b/arch/arc/include/asm/u-boot.h
@@ -1,13 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_U_BOOT_H__
#define __ASM_ARC_U_BOOT_H__
#include <asm-generic/u-boot.h>
+#include <asm/u-boot-arc.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_ARC
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index 7675f85..0eb44bc 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -1,16 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-obj-y += sections.o
+extra-y = start.o
+head-y := start.o
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += interrupts.o
obj-y += relocate.o
-obj-y += strchr-700.o
-obj-y += strcmp.o
-obj-y += strcpy-700.o
-obj-y += strlen.o
-obj-y += memcmp.o
-obj-y += memcpy-700.o
-obj-y += memset.o
+obj-y += reset.o
+obj-y += ints_low.o
+obj-y += init_helpers.o
+
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o
diff --git a/arch/arc/lib/_millicodethunk.S b/arch/arc/lib/_millicodethunk.S
new file mode 100644
index 0000000..4ad16ae
--- /dev/null
+++ b/arch/arc/lib/_millicodethunk.S
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc.
+ */
+
+ /* ANSI concatenation macros. */
+
+ #define CONCAT1(a, b) CONCAT2(a, b)
+ #define CONCAT2(a, b) a ## b
+
+ /* Use the right prefix for global labels. */
+
+ #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+#ifndef WORKING_ASSEMBLER
+#define abs_l abs
+#define asl_l asl
+#define mov_l mov
+#endif
+
+#define FUNC(X) .type SYM(X),@function
+#define HIDDEN_FUNC(X) FUNC(X)` .hidden X
+#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X
+#define ENDFUNC(X) ENDFUNC0(X)
+
+ .section .text
+ .align 4
+ .global SYM(__st_r13_to_r15)
+ .global SYM(__st_r13_to_r16)
+ .global SYM(__st_r13_to_r17)
+ .global SYM(__st_r13_to_r18)
+ .global SYM(__st_r13_to_r19)
+ .global SYM(__st_r13_to_r20)
+ .global SYM(__st_r13_to_r21)
+ .global SYM(__st_r13_to_r22)
+ .global SYM(__st_r13_to_r23)
+ .global SYM(__st_r13_to_r24)
+ .global SYM(__st_r13_to_r25)
+ HIDDEN_FUNC(__st_r13_to_r15)
+ HIDDEN_FUNC(__st_r13_to_r16)
+ HIDDEN_FUNC(__st_r13_to_r17)
+ HIDDEN_FUNC(__st_r13_to_r18)
+ HIDDEN_FUNC(__st_r13_to_r19)
+ HIDDEN_FUNC(__st_r13_to_r20)
+ HIDDEN_FUNC(__st_r13_to_r21)
+ HIDDEN_FUNC(__st_r13_to_r22)
+ HIDDEN_FUNC(__st_r13_to_r23)
+ HIDDEN_FUNC(__st_r13_to_r24)
+ HIDDEN_FUNC(__st_r13_to_r25)
+ .align 4
+SYM(__st_r13_to_r25):
+ st r25, [sp,48]
+SYM(__st_r13_to_r24):
+ st r24, [sp,44]
+SYM(__st_r13_to_r23):
+ st r23, [sp,40]
+SYM(__st_r13_to_r22):
+ st r22, [sp,36]
+SYM(__st_r13_to_r21):
+ st r21, [sp,32]
+SYM(__st_r13_to_r20):
+ st r20, [sp,28]
+SYM(__st_r13_to_r19):
+ st r19, [sp,24]
+SYM(__st_r13_to_r18):
+ st r18, [sp,20]
+SYM(__st_r13_to_r17):
+ st r17, [sp,16]
+SYM(__st_r13_to_r16):
+ st r16, [sp,12]
+SYM(__st_r13_to_r15):
+#ifdef __ARC700__
+ st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
+#else
+ st_s r15, [sp,8]
+#endif
+ st_s r14, [sp,4]
+ j_s.d [%blink]
+ st_s r13, [sp,0]
+ ENDFUNC(__st_r13_to_r15)
+ ENDFUNC(__st_r13_to_r16)
+ ENDFUNC(__st_r13_to_r17)
+ ENDFUNC(__st_r13_to_r18)
+ ENDFUNC(__st_r13_to_r19)
+ ENDFUNC(__st_r13_to_r20)
+ ENDFUNC(__st_r13_to_r21)
+ ENDFUNC(__st_r13_to_r22)
+ ENDFUNC(__st_r13_to_r23)
+ ENDFUNC(__st_r13_to_r24)
+ ENDFUNC(__st_r13_to_r25)
+
+ .section .text
+ .align 4
+; ==================================
+; the loads
+
+ .global SYM(__ld_r13_to_r15)
+ .global SYM(__ld_r13_to_r16)
+ .global SYM(__ld_r13_to_r17)
+ .global SYM(__ld_r13_to_r18)
+ .global SYM(__ld_r13_to_r19)
+ .global SYM(__ld_r13_to_r20)
+ .global SYM(__ld_r13_to_r21)
+ .global SYM(__ld_r13_to_r22)
+ .global SYM(__ld_r13_to_r23)
+ .global SYM(__ld_r13_to_r24)
+ .global SYM(__ld_r13_to_r25)
+ HIDDEN_FUNC(__ld_r13_to_r15)
+ HIDDEN_FUNC(__ld_r13_to_r16)
+ HIDDEN_FUNC(__ld_r13_to_r17)
+ HIDDEN_FUNC(__ld_r13_to_r18)
+ HIDDEN_FUNC(__ld_r13_to_r19)
+ HIDDEN_FUNC(__ld_r13_to_r20)
+ HIDDEN_FUNC(__ld_r13_to_r21)
+ HIDDEN_FUNC(__ld_r13_to_r22)
+ HIDDEN_FUNC(__ld_r13_to_r23)
+ HIDDEN_FUNC(__ld_r13_to_r24)
+ HIDDEN_FUNC(__ld_r13_to_r25)
+SYM(__ld_r13_to_r25):
+ ld r25, [sp,48]
+SYM(__ld_r13_to_r24):
+ ld r24, [sp,44]
+SYM(__ld_r13_to_r23):
+ ld r23, [sp,40]
+SYM(__ld_r13_to_r22):
+ ld r22, [sp,36]
+SYM(__ld_r13_to_r21):
+ ld r21, [sp,32]
+SYM(__ld_r13_to_r20):
+ ld r20, [sp,28]
+SYM(__ld_r13_to_r19):
+ ld r19, [sp,24]
+SYM(__ld_r13_to_r18):
+ ld r18, [sp,20]
+SYM(__ld_r13_to_r17):
+ ld r17, [sp,16]
+SYM(__ld_r13_to_r16):
+ ld r16, [sp,12]
+SYM(__ld_r13_to_r15):
+#ifdef __ARC700__
+ ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
+#else
+ ld_s r15, [sp,8]
+#endif
+ ld_s r14, [sp,4]
+ j_s.d [%blink]
+ ld_s r13, [sp,0]
+ ENDFUNC(__ld_r13_to_r15)
+ ENDFUNC(__ld_r13_to_r16)
+ ENDFUNC(__ld_r13_to_r17)
+ ENDFUNC(__ld_r13_to_r18)
+ ENDFUNC(__ld_r13_to_r19)
+ ENDFUNC(__ld_r13_to_r20)
+ ENDFUNC(__ld_r13_to_r21)
+ ENDFUNC(__ld_r13_to_r22)
+ ENDFUNC(__ld_r13_to_r23)
+ ENDFUNC(__ld_r13_to_r24)
+ ENDFUNC(__ld_r13_to_r25)
+
+ .global SYM(__ld_r13_to_r14_ret)
+ .global SYM(__ld_r13_to_r15_ret)
+ .global SYM(__ld_r13_to_r16_ret)
+ .global SYM(__ld_r13_to_r17_ret)
+ .global SYM(__ld_r13_to_r18_ret)
+ .global SYM(__ld_r13_to_r19_ret)
+ .global SYM(__ld_r13_to_r20_ret)
+ .global SYM(__ld_r13_to_r21_ret)
+ .global SYM(__ld_r13_to_r22_ret)
+ .global SYM(__ld_r13_to_r23_ret)
+ .global SYM(__ld_r13_to_r24_ret)
+ .global SYM(__ld_r13_to_r25_ret)
+ HIDDEN_FUNC(__ld_r13_to_r14_ret)
+ HIDDEN_FUNC(__ld_r13_to_r15_ret)
+ HIDDEN_FUNC(__ld_r13_to_r16_ret)
+ HIDDEN_FUNC(__ld_r13_to_r17_ret)
+ HIDDEN_FUNC(__ld_r13_to_r18_ret)
+ HIDDEN_FUNC(__ld_r13_to_r19_ret)
+ HIDDEN_FUNC(__ld_r13_to_r20_ret)
+ HIDDEN_FUNC(__ld_r13_to_r21_ret)
+ HIDDEN_FUNC(__ld_r13_to_r22_ret)
+ HIDDEN_FUNC(__ld_r13_to_r23_ret)
+ HIDDEN_FUNC(__ld_r13_to_r24_ret)
+ HIDDEN_FUNC(__ld_r13_to_r25_ret)
+ .section .text
+ .align 4
+SYM(__ld_r13_to_r25_ret):
+ ld r25, [sp,48]
+SYM(__ld_r13_to_r24_ret):
+ ld r24, [sp,44]
+SYM(__ld_r13_to_r23_ret):
+ ld r23, [sp,40]
+SYM(__ld_r13_to_r22_ret):
+ ld r22, [sp,36]
+SYM(__ld_r13_to_r21_ret):
+ ld r21, [sp,32]
+SYM(__ld_r13_to_r20_ret):
+ ld r20, [sp,28]
+SYM(__ld_r13_to_r19_ret):
+ ld r19, [sp,24]
+SYM(__ld_r13_to_r18_ret):
+ ld r18, [sp,20]
+SYM(__ld_r13_to_r17_ret):
+ ld r17, [sp,16]
+SYM(__ld_r13_to_r16_ret):
+ ld r16, [sp,12]
+SYM(__ld_r13_to_r15_ret):
+ ld r15, [sp,8]
+SYM(__ld_r13_to_r14_ret):
+ ld blink,[sp,r12]
+ ld_s r14, [sp,4]
+ ld.ab r13, [sp,r12]
+ j_s.d [%blink]
+ add_s sp,sp,4
+ ENDFUNC(__ld_r13_to_r14_ret)
+ ENDFUNC(__ld_r13_to_r15_ret)
+ ENDFUNC(__ld_r13_to_r16_ret)
+ ENDFUNC(__ld_r13_to_r17_ret)
+ ENDFUNC(__ld_r13_to_r18_ret)
+ ENDFUNC(__ld_r13_to_r19_ret)
+ ENDFUNC(__ld_r13_to_r20_ret)
+ ENDFUNC(__ld_r13_to_r21_ret)
+ ENDFUNC(__ld_r13_to_r22_ret)
+ ENDFUNC(__ld_r13_to_r23_ret)
+ ENDFUNC(__ld_r13_to_r24_ret)
+ ENDFUNC(__ld_r13_to_r25_ret)
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index d185a50..254e028 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -1,9 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm/cache.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,48 +40,64 @@
static int cleanup_before_linux(void)
{
disable_interrupts();
- flush_dcache_all();
- invalidate_icache_all();
+ sync_n_cleanup_cache_all();
return 0;
}
+__weak int board_prep_linux(bootm_headers_t *images) { return 0; }
+
/* Subcommand: PREP */
-static void boot_prep_linux(bootm_headers_t *images)
+static int boot_prep_linux(bootm_headers_t *images)
{
- if (image_setup_linux(images))
- hang();
+ int ret;
+
+ ret = image_setup_linux(images);
+ if (ret)
+ return ret;
+
+ return board_prep_linux(images);
+}
+
+/* Generic implementation for single core CPU */
+__weak void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+ kernel_entry = (void (*)(int, int, uint))entry;
+
+ kernel_entry(zero, arch, params);
}
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
- void (*kernel_entry)(int zero, int arch, uint params);
+ ulong kernel_entry;
unsigned int r0, r2;
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
- kernel_entry = (void (*)(int, int, uint))images->ep;
+ kernel_entry = images->ep;
debug("## Transferring control to Linux (at address %08lx)...\n",
- (ulong) kernel_entry);
+ kernel_entry);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
printf("\nStarting kernel ...%s\n\n", fake ?
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- cleanup_before_linux();
-
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
} else {
r0 = 1;
- r2 = (unsigned int)getenv("bootargs");
+ r2 = (unsigned int)env_get("bootargs");
}
+ cleanup_before_linux();
+
if (!fake)
- kernel_entry(r0, 0, r2);
+ board_jump_and_run(kernel_entry, r0, 0, r2);
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
@@ -90,17 +106,13 @@
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
return -1;
- if (flag & BOOTM_STATE_OS_PREP) {
- boot_prep_linux(images);
- return 0;
- }
+ if (flag & BOOTM_STATE_OS_PREP)
+ return boot_prep_linux(images);
if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
boot_jump_linux(images, flag);
return 0;
}
- boot_prep_linux(images);
- boot_jump_linux(images, flag);
- return 0;
+ return -1;
}
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
new file mode 100644
index 0000000..8c1cb6e
--- /dev/null
+++ b/arch/arc/lib/cache.c
@@ -0,0 +1,719 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <asm/arcregs.h>
+#include <asm/arc-bcr.h>
+#include <asm/cache.h>
+
+/*
+ * [ NOTE 1 ]:
+ * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
+ * operation may result in unexpected behavior and data loss even if we flush
+ * data cache right before invalidation. That may happens if we store any context
+ * on stack (like we store BLINK register on stack before function call).
+ * BLINK register is the register where return address is automatically saved
+ * when we do function call with instructions like 'bl'.
+ *
+ * There is the real example:
+ * We may hang in the next code as we store any BLINK register on stack in
+ * invalidate_dcache_all() function.
+ *
+ * void flush_dcache_all() {
+ * __dc_entire_op(OP_FLUSH);
+ * // Other code //
+ * }
+ *
+ * void invalidate_dcache_all() {
+ * __dc_entire_op(OP_INV);
+ * // Other code //
+ * }
+ *
+ * void foo(void) {
+ * flush_dcache_all();
+ * invalidate_dcache_all();
+ * }
+ *
+ * Now let's see what really happens during that code execution:
+ *
+ * foo()
+ * |->> call flush_dcache_all
+ * [return address is saved to BLINK register]
+ * [push BLINK] (save to stack) ![point 1]
+ * |->> call __dc_entire_op(OP_FLUSH)
+ * [return address is saved to BLINK register]
+ * [flush L1 D$]
+ * return [jump to BLINK]
+ * <<------
+ * [other flush_dcache_all code]
+ * [pop BLINK] (get from stack)
+ * return [jump to BLINK]
+ * <<------
+ * |->> call invalidate_dcache_all
+ * [return address is saved to BLINK register]
+ * [push BLINK] (save to stack) ![point 2]
+ * |->> call __dc_entire_op(OP_FLUSH)
+ * [return address is saved to BLINK register]
+ * [invalidate L1 D$] ![point 3]
+ * // Oops!!!
+ * // We lose return address from invalidate_dcache_all function:
+ * // we save it to stack and invalidate L1 D$ after that!
+ * return [jump to BLINK]
+ * <<------
+ * [other invalidate_dcache_all code]
+ * [pop BLINK] (get from stack)
+ * // we don't have this data in L1 dcache as we invalidated it in [point 3]
+ * // so we get it from next memory level (for example DDR memory)
+ * // but in the memory we have value which we save in [point 1], which
+ * // is return address from flush_dcache_all function (instead of
+ * // address from current invalidate_dcache_all function which we
+ * // saved in [point 2] !)
+ * return [jump to BLINK]
+ * <<------
+ * // As BLINK points to invalidate_dcache_all, we call it again and
+ * // loop forever.
+ *
+ * Fortunately we may fix that by using flush & invalidation of D$ with a single
+ * one instruction (instead of flush and invalidation instructions pair) and
+ * enabling force function inline with '__attribute__((always_inline))' gcc
+ * attribute to avoid any function call (and BLINK store) between cache flush
+ * and disable.
+ *
+ *
+ * [ NOTE 2 ]:
+ * As of today we only support the following cache configurations on ARC.
+ * Other configurations may exist in HW (for example, since version 3.0 HS
+ * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
+ * Configuration 1:
+ * ______________________
+ * | |
+ * | ARC CPU |
+ * |______________________|
+ * ___|___ ___|___
+ * | | | |
+ * | L1 I$ | | L1 D$ |
+ * |_______| |_______|
+ * on/off on/off
+ * ___|______________|____
+ * | |
+ * | main memory |
+ * |______________________|
+ *
+ * Configuration 2:
+ * ______________________
+ * | |
+ * | ARC CPU |
+ * |______________________|
+ * ___|___ ___|___
+ * | | | |
+ * | L1 I$ | | L1 D$ |
+ * |_______| |_______|
+ * on/off on/off
+ * ___|______________|____
+ * | |
+ * | L2 (SL$) |
+ * |______________________|
+ * always must be on
+ * ___|______________|____
+ * | |
+ * | main memory |
+ * |______________________|
+ *
+ * Configuration 3:
+ * ______________________
+ * | |
+ * | ARC CPU |
+ * |______________________|
+ * ___|___ ___|___
+ * | | | |
+ * | L1 I$ | | L1 D$ |
+ * |_______| |_______|
+ * on/off must be on
+ * ___|______________|____ _______
+ * | | | |
+ * | L2 (SL$) |-----| IOC |
+ * |______________________| |_______|
+ * always must be on on/off
+ * ___|______________|____
+ * | |
+ * | main memory |
+ * |______________________|
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE BIT(0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE BIT(0)
+#define DC_CTRL_INV_MODE_FLUSH BIT(6)
+#define DC_CTRL_FLUSH_STATUS BIT(8)
+
+#define OP_INV BIT(0)
+#define OP_FLUSH BIT(1)
+#define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
+
+/* Bit val in SLC_CONTROL */
+#define SLC_CTRL_DIS 0x001
+#define SLC_CTRL_IM 0x040
+#define SLC_CTRL_BUSY 0x100
+#define SLC_CTRL_RGN_OP_INV 0x200
+
+#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
+
+/*
+ * We don't want to use '__always_inline' macro here as it can be redefined
+ * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
+ * details about the reasons we need to use always_inline functions.
+ */
+#define inlined_cachefunc inline __attribute__((always_inline))
+
+static inlined_cachefunc void __ic_entire_invalidate(void);
+static inlined_cachefunc void __dc_entire_op(const int cacheop);
+
+static inline bool pae_exists(void)
+{
+ /* TODO: should we compare mmu version from BCR and from CONFIG? */
+#if (CONFIG_ARC_MMU_VER >= 4)
+ union bcr_mmu_4 mmu4;
+
+ mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
+
+ if (mmu4.fields.pae)
+ return true;
+#endif /* (CONFIG_ARC_MMU_VER >= 4) */
+
+ return false;
+}
+
+static inlined_cachefunc bool icache_exists(void)
+{
+ union bcr_di_cache ibcr;
+
+ ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
+ return !!ibcr.fields.ver;
+}
+
+static inlined_cachefunc bool icache_enabled(void)
+{
+ if (!icache_exists())
+ return false;
+
+ return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
+}
+
+static inlined_cachefunc bool dcache_exists(void)
+{
+ union bcr_di_cache dbcr;
+
+ dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
+ return !!dbcr.fields.ver;
+}
+
+static inlined_cachefunc bool dcache_enabled(void)
+{
+ if (!dcache_exists())
+ return false;
+
+ return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
+}
+
+static inlined_cachefunc bool slc_exists(void)
+{
+ if (is_isa_arcv2()) {
+ union bcr_generic sbcr;
+
+ sbcr.word = read_aux_reg(ARC_BCR_SLC);
+ return !!sbcr.fields.ver;
+ }
+
+ return false;
+}
+
+static inlined_cachefunc bool slc_data_bypass(void)
+{
+ /*
+ * If L1 data cache is disabled SL$ is bypassed and all load/store
+ * requests are sent directly to main memory.
+ */
+ return !dcache_enabled();
+}
+
+static inline bool ioc_exists(void)
+{
+ if (is_isa_arcv2()) {
+ union bcr_clust_cfg cbcr;
+
+ cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
+ return cbcr.fields.c;
+ }
+
+ return false;
+}
+
+static inline bool ioc_enabled(void)
+{
+ /*
+ * We check only CONFIG option instead of IOC HW state check as IOC
+ * must be disabled by default.
+ */
+ if (is_ioc_enabled())
+ return ioc_exists();
+
+ return false;
+}
+
+static inlined_cachefunc void __slc_entire_op(const int op)
+{
+ unsigned int ctrl;
+
+ if (!slc_exists())
+ return;
+
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ if (!(op & OP_FLUSH)) /* i.e. OP_INV */
+ ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
+ else
+ ctrl |= SLC_CTRL_IM;
+
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
+
+ if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
+ write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
+ else
+ write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
+
+ /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+ read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ /* Important to wait for flush to complete */
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
+}
+
+static void slc_upper_region_init(void)
+{
+ /*
+ * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
+ * only if PAE exists in current HW. So we had to check pae_exist
+ * before using them.
+ */
+ if (!pae_exists())
+ return;
+
+ /*
+ * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
+ * as we don't use PAE40.
+ */
+ write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
+ write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
+}
+
+static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
+{
+#ifdef CONFIG_ISA_ARCV2
+
+ unsigned int ctrl;
+ unsigned long end;
+
+ if (!slc_exists())
+ return;
+
+ /*
+ * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
+ * - b'000 (default) is Flush,
+ * - b'001 is Invalidate if CTRL.IM == 0
+ * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
+ */
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ /* Don't rely on default value of IM bit */
+ if (!(op & OP_FLUSH)) /* i.e. OP_INV */
+ ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
+ else
+ ctrl |= SLC_CTRL_IM;
+
+ if (op & OP_INV)
+ ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
+ else
+ ctrl &= ~SLC_CTRL_RGN_OP_INV;
+
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
+
+ /*
+ * Lower bits are ignored, no need to clip
+ * END needs to be setup before START (latter triggers the operation)
+ * END can't be same as START, so add (l2_line_sz - 1) to sz
+ */
+ end = paddr + sz + gd->arch.slc_line_sz - 1;
+
+ /*
+ * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
+ * are always == 0 as we don't use PAE40, so we only setup lower ones
+ * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
+ */
+ write_aux_reg(ARC_AUX_SLC_RGN_END, end);
+ write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
+
+ /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+ read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
+
+#endif /* CONFIG_ISA_ARCV2 */
+}
+
+static void arc_ioc_setup(void)
+{
+ /* IOC Aperture start is equal to DDR start */
+ unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+ /* IOC Aperture size is equal to DDR size */
+ long ap_size = CONFIG_SYS_SDRAM_SIZE;
+
+ /* Unsupported configuration. See [ NOTE 2 ] for more details. */
+ if (!slc_exists())
+ panic("Try to enable IOC but SLC is not present");
+
+ /* Unsupported configuration. See [ NOTE 2 ] for more details. */
+ if (!dcache_enabled())
+ panic("Try to enable IOC but L1 D$ is disabled");
+
+ if (!is_power_of_2(ap_size) || ap_size < 4096)
+ panic("IOC Aperture size must be power of 2 and bigger 4Kib");
+
+ /* IOC Aperture start must be aligned to the size of the aperture */
+ if (ap_base % ap_size != 0)
+ panic("IOC Aperture start must be aligned to the size of the aperture");
+
+ flush_n_invalidate_dcache_all();
+
+ /*
+ * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
+ * so setting 0x11 implies 512M, 0x12 implies 1G...
+ */
+ write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
+ order_base_2(ap_size / 1024) - 2);
+
+ write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
+ write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
+ write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
+}
+
+static void read_decode_cache_bcr_arcv2(void)
+{
+#ifdef CONFIG_ISA_ARCV2
+
+ union bcr_slc_cfg slc_cfg;
+
+ if (slc_exists()) {
+ slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
+ gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
+
+ /*
+ * We don't support configuration where L1 I$ or L1 D$ is
+ * absent but SL$ exists. See [ NOTE 2 ] for more details.
+ */
+ if (!icache_exists() || !dcache_exists())
+ panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
+ }
+
+#endif /* CONFIG_ISA_ARCV2 */
+}
+
+void read_decode_cache_bcr(void)
+{
+ int dc_line_sz = 0, ic_line_sz = 0;
+ union bcr_di_cache ibcr, dbcr;
+
+ /*
+ * We don't care much about I$ line length really as there're
+ * no per-line ops on I$ instead we only do full invalidation of it
+ * on occasion of relocation and right before jumping to the OS.
+ * Still we check insane config with zero-encoded line length in
+ * presense of version field in I$ BCR. Just in case.
+ */
+ ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
+ if (ibcr.fields.ver) {
+ ic_line_sz = 8 << ibcr.fields.line_len;
+ if (!ic_line_sz)
+ panic("Instruction exists but line length is 0\n");
+ }
+
+ dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
+ if (dbcr.fields.ver) {
+ gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
+ if (!dc_line_sz)
+ panic("Data cache exists but line length is 0\n");
+ }
+}
+
+void cache_init(void)
+{
+ read_decode_cache_bcr();
+
+ if (is_isa_arcv2())
+ read_decode_cache_bcr_arcv2();
+
+ if (is_isa_arcv2() && ioc_enabled())
+ arc_ioc_setup();
+
+ if (is_isa_arcv2() && slc_exists())
+ slc_upper_region_init();
+}
+
+int icache_status(void)
+{
+ return icache_enabled();
+}
+
+void icache_enable(void)
+{
+ if (icache_exists())
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+ ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+ if (!icache_exists())
+ return;
+
+ __ic_entire_invalidate();
+
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+ IC_CTRL_CACHE_DISABLE);
+}
+
+/* IC supports only invalidation */
+static inlined_cachefunc void __ic_entire_invalidate(void)
+{
+ if (!icache_enabled())
+ return;
+
+ /* Any write to IC_IVIC register triggers invalidation of entire I$ */
+ write_aux_reg(ARC_AUX_IC_IVIC, 1);
+ /*
+ * As per ARC HS databook (see chapter 5.3.3.2)
+ * it is required to add 3 NOPs after each write to IC_IVIC.
+ */
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
+}
+
+void invalidate_icache_all(void)
+{
+ __ic_entire_invalidate();
+
+ /*
+ * If SL$ is bypassed for data it is used only for instructions,
+ * so we need to invalidate it too.
+ * TODO: HS 3.0 supports SLC disable so we need to check slc
+ * enable/disable status here.
+ */
+ if (is_isa_arcv2() && slc_data_bypass())
+ __slc_entire_op(OP_INV);
+}
+
+int dcache_status(void)
+{
+ return dcache_enabled();
+}
+
+void dcache_enable(void)
+{
+ if (!dcache_exists())
+ return;
+
+ write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+ ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+ if (!dcache_exists())
+ return;
+
+ __dc_entire_op(OP_FLUSH_N_INV);
+
+ /*
+ * As SLC will be bypassed for data after L1 D$ disable we need to
+ * flush it first before L1 D$ disable. Also we invalidate SLC to
+ * avoid any inconsistent data problems after enabling L1 D$ again with
+ * dcache_enable function.
+ */
+ if (is_isa_arcv2())
+ __slc_entire_op(OP_FLUSH_N_INV);
+
+ write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+ DC_CTRL_CACHE_DISABLE);
+}
+
+/* Common Helper for Line Operations on D-cache */
+static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
+ const int cacheop)
+{
+ unsigned int aux_cmd;
+ int num_lines;
+
+ /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
+ aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
+
+ sz += paddr & ~CACHE_LINE_MASK;
+ paddr &= CACHE_LINE_MASK;
+
+ num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
+
+ while (num_lines-- > 0) {
+#if (CONFIG_ARC_MMU_VER == 3)
+ write_aux_reg(ARC_AUX_DC_PTAG, paddr);
+#endif
+ write_aux_reg(aux_cmd, paddr);
+ paddr += gd->arch.l1_line_sz;
+ }
+}
+
+static inlined_cachefunc void __before_dc_op(const int op)
+{
+ unsigned int ctrl;
+
+ ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
+
+ /* IM bit implies flush-n-inv, instead of vanilla inv */
+ if (op == OP_INV)
+ ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
+ else
+ ctrl |= DC_CTRL_INV_MODE_FLUSH;
+
+ write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
+}
+
+static inlined_cachefunc void __after_dc_op(const int op)
+{
+ if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
+}
+
+static inlined_cachefunc void __dc_entire_op(const int cacheop)
+{
+ int aux;
+
+ if (!dcache_enabled())
+ return;
+
+ __before_dc_op(cacheop);
+
+ if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
+ aux = ARC_AUX_DC_IVDC;
+ else
+ aux = ARC_AUX_DC_FLSH;
+
+ write_aux_reg(aux, 0x1);
+
+ __after_dc_op(cacheop);
+}
+
+static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
+ const int cacheop)
+{
+ if (!dcache_enabled())
+ return;
+
+ __before_dc_op(cacheop);
+ __dcache_line_loop(paddr, sz, cacheop);
+ __after_dc_op(cacheop);
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ if (start >= end)
+ return;
+
+ /*
+ * ARCv1 -> call __dc_line_op
+ * ARCv2 && L1 D$ disabled -> nothing
+ * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
+ * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
+ */
+ if (!is_isa_arcv2() || !ioc_enabled())
+ __dc_line_op(start, end - start, OP_INV);
+
+ if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
+ __slc_rgn_op(start, end - start, OP_INV);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ if (start >= end)
+ return;
+
+ /*
+ * ARCv1 -> call __dc_line_op
+ * ARCv2 && L1 D$ disabled -> nothing
+ * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
+ * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
+ */
+ if (!is_isa_arcv2() || !ioc_enabled())
+ __dc_line_op(start, end - start, OP_FLUSH);
+
+ if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
+ __slc_rgn_op(start, end - start, OP_FLUSH);
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+/*
+ * As invalidate_dcache_all() is not used in generic U-Boot code and as we
+ * don't need it in arch/arc code alone (invalidate without flush) we implement
+ * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
+ * it's much safer. See [ NOTE 1 ] for more details.
+ */
+void flush_n_invalidate_dcache_all(void)
+{
+ __dc_entire_op(OP_FLUSH_N_INV);
+
+ if (is_isa_arcv2() && !slc_data_bypass())
+ __slc_entire_op(OP_FLUSH_N_INV);
+}
+
+void flush_dcache_all(void)
+{
+ __dc_entire_op(OP_FLUSH);
+
+ if (is_isa_arcv2() && !slc_data_bypass())
+ __slc_entire_op(OP_FLUSH);
+}
+
+/*
+ * This is function to cleanup all caches (and therefore sync I/D caches) which
+ * can be used for cleanup before linux launch or to sync caches during
+ * relocation.
+ */
+void sync_n_cleanup_cache_all(void)
+{
+ __dc_entire_op(OP_FLUSH_N_INV);
+
+ /*
+ * If SL$ is bypassed for data it is used only for instructions,
+ * and we shouldn't flush it. So invalidate it instead of flush_n_inv.
+ */
+ if (is_isa_arcv2()) {
+ if (slc_data_bypass())
+ __slc_entire_op(OP_INV);
+ else
+ __slc_entire_op(OP_FLUSH_N_INV);
+ }
+
+ __ic_entire_invalidate();
+}
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
new file mode 100644
index 0000000..07daaa8
--- /dev/null
+++ b/arch/arc/lib/cpu.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arcregs.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+ timer_init();
+
+ gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ cache_init();
+
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+/* This is a dummy function on arc */
+int dram_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+const char *arc_700_version(int arcver, char *name, int name_len)
+{
+ const char *arc_ver;
+
+ switch (arcver) {
+ case 0x32:
+ arc_ver = "v4.4-4.5";
+ break;
+ case 0x33:
+ arc_ver = "v4.6-v4.9";
+ break;
+ case 0x34:
+ arc_ver = "v4.10";
+ break;
+ case 0x35:
+ arc_ver = "v4.11";
+ break;
+ default:
+ arc_ver = "unknown version";
+ }
+
+ snprintf(name, name_len, "ARC 700 %s", arc_ver);
+
+ return name;
+}
+
+struct em_template_t {
+ const bool cache;
+ const bool dsp;
+ const bool xymem;
+ const char name[8];
+};
+
+static const struct em_template_t em_versions[] = {
+ {false, false, false, "EM4"},
+ {true, false, false, "EM6"},
+ {false, true, false, "EM5D"},
+ {true, true, false, "EM7D"},
+ {false, true, true, "EM9D"},
+ {true, true, true, "EM11D"},
+};
+
+const char *arc_em_version(int arcver, char *name, int name_len)
+{
+ const char *arc_name = "EM";
+ const char *arc_ver;
+ bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
+ bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
+ bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD);
+ int i;
+
+ for (i = 0; i++ < sizeof(em_versions) / sizeof(struct em_template_t);) {
+ if (em_versions[i].cache == cache &&
+ em_versions[i].dsp == dsp &&
+ em_versions[i].xymem == xymem) {
+ arc_name = em_versions[i].name;
+ break;
+ }
+ }
+
+ switch (arcver) {
+ case 0x41:
+ arc_ver = "v1.1a";
+ break;
+ case 0x42:
+ arc_ver = "v3.0";
+ break;
+ case 0x43:
+ arc_ver = "v4.0";
+ break;
+ case 0x44:
+ arc_ver = "v5.0";
+ break;
+ default:
+ arc_ver = "unknown version";
+ }
+
+ snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
+
+ return name;
+}
+
+struct hs_template_t {
+ const bool cache;
+ const bool mmu;
+ const bool dual_issue;
+ const bool dsp;
+ const char name[8];
+};
+
+static const struct hs_template_t hs_versions[] = {
+ {false, false, false, false, "HS34"},
+ {true, false, false, false, "HS36"},
+ {true, true, false, false, "HS38"},
+ {false, false, true, false, "HS44"},
+ {true, false, true, false, "HS46"},
+ {true, true, true, false, "HS48"},
+ {false, false, true, true, "HS45D"},
+ {true, false, true, true, "HS47D"},
+};
+
+const char *arc_hs_version(int arcver, char *name, int name_len)
+{
+ const char *arc_name = "HS";
+ const char *arc_ver;
+ bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
+ bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
+ bool mmu = !!read_aux_reg(ARC_AUX_MMU_BCR);
+ bool dual_issue = arcver == 0x54 ? true : false;
+ int i;
+
+ for (i = 0; i++ < sizeof(hs_versions) / sizeof(struct hs_template_t);) {
+ if (hs_versions[i].cache == cache &&
+ hs_versions[i].mmu == mmu &&
+ hs_versions[i].dual_issue == dual_issue &&
+ hs_versions[i].dsp == dsp) {
+ arc_name = hs_versions[i].name;
+ break;
+ }
+ }
+
+ switch (arcver) {
+ case 0x50:
+ arc_ver = "v1.0";
+ break;
+ case 0x51:
+ arc_ver = "v2.0";
+ break;
+ case 0x52:
+ arc_ver = "v2.1c";
+ break;
+ case 0x53:
+ arc_ver = "v3.0";
+ break;
+ case 0x54:
+ arc_ver = "v4.0";
+ break;
+ default:
+ arc_ver = "unknown version";
+ }
+
+ snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
+
+ return name;
+}
+
+const char *decode_identity(void)
+{
+#define MAX_CPU_NAME_LEN 64
+
+ int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+ char *name = malloc(MAX_CPU_NAME_LEN);
+
+ if (arcver >= 0x50)
+ return arc_hs_version(arcver, name, MAX_CPU_NAME_LEN);
+ else if (arcver >= 0x40)
+ return arc_em_version(arcver, name, MAX_CPU_NAME_LEN);
+ else if (arcver >= 0x30)
+ return arc_700_version(arcver, name, MAX_CPU_NAME_LEN);
+ else
+ return "Unknown ARC core";
+}
+
+const char *decode_subsystem(void)
+{
+ int subsys_type = read_aux_reg(ARC_AUX_SUBSYS_BUILD) & GENMASK(3, 0);
+
+ switch (subsys_type) {
+ case 0: return NULL;
+ case 2: return "ARC Sensor & Control IP Subsystem";
+ case 3: return "ARC Data Fusion IP Subsystem";
+ case 4: return "ARC Secure Subsystem";
+ default: return "Unknown subsystem";
+ };
+}
+
+__weak int print_cpuinfo(void)
+{
+ const char *subsys_name = decode_subsystem();
+ char mhz[8];
+
+ printf("CPU: %s at %s MHz\n", decode_identity(),
+ strmhz(mhz, gd->cpu_clk));
+
+ if (subsys_name)
+ printf("Subsys:%s\n", subsys_name);
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
new file mode 100644
index 0000000..c853f25
--- /dev/null
+++ b/arch/arc/lib/init_helpers.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ */
+
+#include <asm/cache.h>
+#include <common.h>
+
+int init_cache_f_r(void)
+{
+ sync_n_cleanup_cache_all();
+
+ return 0;
+}
diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c
new file mode 100644
index 0000000..24ff751
--- /dev/null
+++ b/arch/arc/lib/interrupts.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
+#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+ return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+ int status = read_aux_reg(ARC_AUX_STATUS32);
+ int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
+
+ status &= ~(E1_MASK | E2_MASK);
+ /* STATUS32 register is updated indirectly with "FLAG" instruction */
+ __asm__("flag %0" : : "r" (status));
+ return state;
+}
+
+void enable_interrupts(void)
+{
+ unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+ status |= E1_MASK | E2_MASK;
+ /* STATUS32 register is updated indirectly with "FLAG" instruction */
+ __asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+ unsigned int i;
+
+ /* Print 3 registers per line */
+ for (i = start_num; i < start_num + 25; i++) {
+ printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+ if (((i + 1) % 3) == 0)
+ printf("\n");
+
+ /* Because pt_regs has registers reversed */
+ reg_rev--;
+ }
+
+ /* Add new-line if none was inserted in the end of loop above */
+ if (((i + 1) % 3) != 0)
+ printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ printf("ECR:\t0x%08lx\n", regs->ecr);
+ printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+ regs->ret, regs->blink, regs->status32);
+ printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+ printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+ regs->sp, regs->fp);
+ printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+ regs->lp_end, regs->lp_count);
+
+ print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+ if (regs)
+ show_regs(regs);
+
+ panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+ printf("Memory error exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+ printf("Instruction error exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+ printf("Machine check exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+ printf("Interrupt fired\n");
+ bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+ printf("I TLB miss exception\n");
+ bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+ printf("D TLB miss exception\n");
+ bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+ printf("TLB protection violation or misaligned access @ 0x%lx\n",
+ address);
+ bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+ printf("Privilege violation exception\n");
+ bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+ printf("Trap exception\n");
+ bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+ printf("Extension instruction exception\n");
+ bad_mode(regs);
+}
+
+#ifdef CONFIG_ISA_ARCV2
+void do_swi(struct pt_regs *regs)
+{
+ printf("Software Interrupt exception\n");
+ bad_mode(regs);
+}
+
+void do_divzero(unsigned long address, struct pt_regs *regs)
+{
+ printf("Division by zero exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_dcerror(struct pt_regs *regs)
+{
+ printf("Data cache consistency error exception\n");
+ bad_mode(regs);
+}
+
+void do_maligned(unsigned long address, struct pt_regs *regs)
+{
+ printf("Misaligned data access exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+#endif
diff --git a/arch/arc/lib/ints_low.S b/arch/arc/lib/ints_low.S
new file mode 100644
index 0000000..38c45c6
--- /dev/null
+++ b/arch/arc/lib/ints_low.S
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a reg1, [reg2, x] => Pre Incr
+ * Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab reg1, [reg2, x] => Post Incr
+ * Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+ st.a \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+ lr %r9, [\aux]
+ PUSH %r9
+.endm
+
+.macro SAVE_R1_TO_R24
+ PUSH %r1
+ PUSH %r2
+ PUSH %r3
+ PUSH %r4
+ PUSH %r5
+ PUSH %r6
+ PUSH %r7
+ PUSH %r8
+ PUSH %r9
+ PUSH %r10
+ PUSH %r11
+ PUSH %r12
+ PUSH %r13
+ PUSH %r14
+ PUSH %r15
+ PUSH %r16
+ PUSH %r17
+ PUSH %r18
+ PUSH %r19
+ PUSH %r20
+ PUSH %r21
+ PUSH %r22
+ PUSH %r23
+ PUSH %r24
+.endm
+
+.macro SAVE_ALL_SYS
+ /* saving %r0 to reg->r0 in advance since we read %ecr into it */
+ st %r0, [%sp, -8]
+ lr %r0, [%ecr] /* all stack addressing is manual so far */
+ st %r0, [%sp]
+ st %sp, [%sp, -4]
+ /* now move %sp to reg->r0 position so we can do "push" automatically */
+ sub %sp, %sp, 8
+
+ SAVE_R1_TO_R24
+ PUSH %r25
+ PUSH %gp
+ PUSH %fp
+ PUSH %blink
+ PUSHAX %eret
+ PUSHAX %erstatus
+ PUSH %lp_count
+ PUSHAX %lp_end
+ PUSHAX %lp_start
+ PUSHAX %erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+ /* If MMU exists exception faulting address is loaded in EFA reg */
+ lr %r0, [%efa]
+#else
+ /* Otherwise in ERET (exception return) reg */
+ lr %r0, [%eret]
+#endif
+.endm
+
+ENTRY(memory_error)
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_memory_error
+ENDPROC(memory_error)
+
+ENTRY(instruction_error)
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_instruction_error
+ENDPROC(instruction_error)
+
+ENTRY(interrupt_handler)
+ /* Todo - save and restore CPU context when interrupts will be in use */
+ bl do_interrupt_handler
+ rtie
+ENDPROC(interrupt_handler)
+
+ENTRY(EV_MachineCheck)
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_machine_check_fault
+ENDPROC(EV_MachineCheck)
+
+ENTRY(EV_TLBMissI)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_itlb_miss
+ENDPROC(EV_TLBMissI)
+
+ENTRY(EV_TLBMissD)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_dtlb_miss
+ENDPROC(EV_TLBMissD)
+
+ENTRY(EV_TLBProtV)
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_tlb_prot_violation
+ENDPROC(EV_TLBProtV)
+
+ENTRY(EV_PrivilegeV)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_privilege_violation
+ENDPROC(EV_PrivilegeV)
+
+ENTRY(EV_Trap)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_trap
+ENDPROC(EV_Trap)
+
+ENTRY(EV_Extension)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_extension
+ENDPROC(EV_Extension)
+
+#ifdef CONFIG_ISA_ARCV2
+ENTRY(EV_SWI)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_swi
+ENDPROC(EV_SWI)
+
+ENTRY(EV_DivZero)
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_divzero
+ENDPROC(EV_DivZero)
+
+ENTRY(EV_DCError)
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_dcerror
+ENDPROC(EV_DCError)
+
+ENTRY(EV_Maligned)
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_maligned
+ENDPROC(EV_Maligned)
+#endif
diff --git a/arch/arc/lib/libgcc2.c b/arch/arc/lib/libgcc2.c
new file mode 100644
index 0000000..b92a841
--- /dev/null
+++ b/arch/arc/lib/libgcc2.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 1989-2013 Free Software Foundation, Inc.
+ */
+
+#include "libgcc2.h"
+
+DWtype
+__ashldi3(DWtype u, shift_count_type b)
+{
+ if (b == 0)
+ return u;
+
+ const DWunion uu = {.ll = u};
+ const shift_count_type bm = W_TYPE_SIZE - b;
+ DWunion w;
+
+ if (bm <= 0) {
+ w.s.low = 0;
+ w.s.high = (UWtype)uu.s.low << -bm;
+ } else {
+ const UWtype carries = (UWtype) uu.s.low >> bm;
+
+ w.s.low = (UWtype)uu.s.low << b;
+ w.s.high = ((UWtype)uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
+
+DWtype
+__ashrdi3(DWtype u, shift_count_type b)
+{
+ if (b == 0)
+ return u;
+
+ const DWunion uu = {.ll = u};
+ const shift_count_type bm = W_TYPE_SIZE - b;
+ DWunion w;
+
+ if (bm <= 0) {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high = uu.s.high >> (W_TYPE_SIZE - 1);
+ w.s.low = uu.s.high >> -bm;
+ } else {
+ const UWtype carries = (UWtype) uu.s.high << bm;
+
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((UWtype)uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+
+DWtype
+__lshrdi3(DWtype u, shift_count_type b)
+{
+ if (b == 0)
+ return u;
+
+ const DWunion uu = {.ll = u};
+ const shift_count_type bm = W_TYPE_SIZE - b;
+ DWunion w;
+
+ if (bm <= 0) {
+ w.s.high = 0;
+ w.s.low = (UWtype)uu.s.high >> -bm;
+ } else {
+ const UWtype carries = (UWtype)uu.s.high << bm;
+
+ w.s.high = (UWtype)uu.s.high >> b;
+ w.s.low = ((UWtype)uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+
+unsigned long
+udivmodsi4(unsigned long num, unsigned long den, int modwanted)
+{
+ unsigned long bit = 1;
+ unsigned long res = 0;
+
+ while (den < num && bit && !(den & (1L<<31))) {
+ den <<= 1;
+ bit <<= 1;
+ }
+
+ while (bit) {
+ if (num >= den) {
+ num -= den;
+ res |= bit;
+ }
+ bit >>= 1;
+ den >>= 1;
+ }
+
+ if (modwanted)
+ return num;
+
+ return res;
+}
+
+long
+__divsi3(long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0) {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0) {
+ b = -b;
+ neg = !neg;
+ }
+
+ res = udivmodsi4(a, b, 0);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+long
+__modsi3(long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0) {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+ res = udivmodsi4(a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+long
+__udivsi3(long a, long b)
+{
+ return udivmodsi4(a, b, 0);
+}
+
+long
+__umodsi3(long a, long b)
+{
+ return udivmodsi4(a, b, 1);
+}
diff --git a/arch/arc/lib/libgcc2.h b/arch/arc/lib/libgcc2.h
new file mode 100644
index 0000000..9c3ce99
--- /dev/null
+++ b/arch/arc/lib/libgcc2.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 1989-2013 Free Software Foundation, Inc.
+ */
+
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#define UNITS_PER_WORD 4 /* for ARC */
+#define BITS_PER_UNIT 8 /* for ARC */
+
+#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
+
+#define MIN_UNITS_PER_WORD UNITS_PER_WORD
+
+/* Work out the largest "word" size that we can deal with on this target. */
+#if MIN_UNITS_PER_WORD > 4
+# define LIBGCC2_MAX_UNITS_PER_WORD 8
+#elif (MIN_UNITS_PER_WORD > 2 \
+ || (MIN_UNITS_PER_WORD > 1 && __SIZEOF_LONG_LONG__ > 4))
+# define LIBGCC2_MAX_UNITS_PER_WORD 4
+#else
+# define LIBGCC2_MAX_UNITS_PER_WORD MIN_UNITS_PER_WORD
+#endif
+
+/* Work out what word size we are using for this compilation.
+ The value can be set on the command line. */
+#ifndef LIBGCC2_UNITS_PER_WORD
+#define LIBGCC2_UNITS_PER_WORD LIBGCC2_MAX_UNITS_PER_WORD
+#endif
+
+typedef int QItype __attribute__ ((mode (QI)));
+typedef unsigned int UQItype __attribute__ ((mode (QI)));
+typedef int HItype __attribute__ ((mode (HI)));
+typedef unsigned int UHItype __attribute__ ((mode (HI)));
+#if MIN_UNITS_PER_WORD > 1
+/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+#if __SIZEOF_LONG_LONG__ > 4
+/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+#if MIN_UNITS_PER_WORD > 4
+/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 4. */
+typedef int TItype __attribute__ ((mode (TI)));
+typedef unsigned int UTItype __attribute__ ((mode (TI)));
+#endif
+#endif
+#endif
+
+#if LIBGCC2_UNITS_PER_WORD == 8
+#define W_TYPE_SIZE (8 * BITS_PER_UNIT)
+#define Wtype DItype
+#define UWtype UDItype
+#define HWtype DItype
+#define UHWtype UDItype
+#define DWtype TItype
+#define UDWtype UTItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## di ## b
+#define __NDW(a,b) __gnu_ ## a ## ti ## b
+#else
+#define __NW(a,b) __ ## a ## di ## b
+#define __NDW(a,b) __ ## a ## ti ## b
+#endif
+#elif LIBGCC2_UNITS_PER_WORD == 4
+#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
+#define Wtype SItype
+#define UWtype USItype
+#define HWtype SItype
+#define UHWtype USItype
+#define DWtype DItype
+#define UDWtype UDItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## si ## b
+#define __NDW(a,b) __gnu_ ## a ## di ## b
+#else
+#define __NW(a,b) __ ## a ## si ## b
+#define __NDW(a,b) __ ## a ## di ## b
+#endif
+#elif LIBGCC2_UNITS_PER_WORD == 2
+#define W_TYPE_SIZE (2 * BITS_PER_UNIT)
+#define Wtype HItype
+#define UWtype UHItype
+#define HWtype HItype
+#define UHWtype UHItype
+#define DWtype SItype
+#define UDWtype USItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## hi ## b
+#define __NDW(a,b) __gnu_ ## a ## si ## b
+#else
+#define __NW(a,b) __ ## a ## hi ## b
+#define __NDW(a,b) __ ## a ## si ## b
+#endif
+#else
+#define W_TYPE_SIZE BITS_PER_UNIT
+#define Wtype QItype
+#define UWtype UQItype
+#define HWtype QItype
+#define UHWtype UQItype
+#define DWtype HItype
+#define UDWtype UHItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## qi ## b
+#define __NDW(a,b) __gnu_ ## a ## hi ## b
+#else
+#define __NW(a,b) __ ## a ## qi ## b
+#define __NDW(a,b) __ ## a ## hi ## b
+#endif
+#endif
+
+typedef int shift_count_type __attribute__((mode (__libgcc_shift_count__)));
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+ struct DWstruct {Wtype high, low;};
+#else
+ struct DWstruct {Wtype low, high;};
+#endif
+
+/* We need this union to unpack/pack DImode values, since we don't have
+ any arithmetic yet. Incoming DImode parameters are stored into the
+ `ll' field, and the unpacked result is read from the struct `s'. */
+
+typedef union {
+ struct DWstruct s;
+ DWtype ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
deleted file mode 100644
index fa5aac5..0000000
--- a/arch/arc/lib/memcmp.S
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef __LITTLE_ENDIAN__
-#define WORD2 r2
-#define SHIFT r3
-#else /* __BIG_ENDIAN__ */
-#define WORD2 r3
-#define SHIFT r2
-#endif /* _ENDIAN__ */
-
-.global memcmp
-.align 4
-memcmp:
- or %r12, %r0, %r1
- asl_s %r12, %r12, 30
- sub %r3, %r2, 1
- brls %r2, %r12, .Lbytewise
- ld %r4, [%r0, 0]
- ld %r5, [%r1, 0]
- lsr.f %lp_count, %r3, 3
- lpne .Loop_end
- ld_s WORD2, [%r0, 4]
- ld_s %r12, [%r1, 4]
- brne %r4, %r5, .Leven
- ld.a %r4, [%r0, 8]
- ld.a %r5, [%r1, 8]
- brne WORD2, %r12, .Lodd
-.Loop_end:
- asl_s SHIFT, SHIFT, 3
- bhs_s .Last_cmp
- brne %r4, %r5, .Leven
- ld %r4, [%r0, 4]
- ld %r5, [%r1, 4]
-#ifdef __LITTLE_ENDIAN__
- nop_s
- /* one more load latency cycle */
-.Last_cmp:
- xor %r0, %r4, %r5
- bset %r0, %r0, SHIFT
- sub_s %r1, %r0, 1
- bic_s %r1, %r1, %r0
- norm %r1, %r1
- b.d .Leven_cmp
- and %r1, %r1, 24
-.Leven:
- xor %r0, %r4, %r5
- sub_s %r1, %r0, 1
- bic_s %r1, %r1, %r0
- norm %r1, %r1
- /* slow track insn */
- and %r1, %r1, 24
-.Leven_cmp:
- asl %r2, %r4, %r1
- asl %r12, %r5, %r1
- lsr_s %r2, %r2, 1
- lsr_s %r12, %r12, 1
- j_s.d [%blink]
- sub %r0, %r2, %r12
- .balign 4
-.Lodd:
- xor %r0, WORD2, %r12
- sub_s %r1, %r0, 1
- bic_s %r1, %r1, %r0
- norm %r1, %r1
- /* slow track insn */
- and %r1, %r1, 24
- asl_s %r2, %r2, %r1
- asl_s %r12, %r12, %r1
- lsr_s %r2, %r2, 1
- lsr_s %r12, %r12, 1
- j_s.d [%blink]
- sub %r0, %r2, %r12
-#else /* __BIG_ENDIAN__ */
-.Last_cmp:
- neg_s SHIFT, SHIFT
- lsr %r4, %r4, SHIFT
- lsr %r5, %r5, SHIFT
- /* slow track insn */
-.Leven:
- sub.f %r0, %r4, %r5
- mov.ne %r0, 1
- j_s.d [%blink]
- bset.cs %r0, %r0, 31
-.Lodd:
- cmp_s WORD2, %r12
-
- mov_s %r0, 1
- j_s.d [%blink]
- bset.cs %r0, %r0, 31
-#endif /* _ENDIAN__ */
- .balign 4
-.Lbytewise:
- breq %r2, 0, .Lnil
- ldb %r4, [%r0, 0]
- ldb %r5, [%r1, 0]
- lsr.f %lp_count, %r3
- lpne .Lbyte_end
- ldb_s %r3, [%r0, 1]
- ldb %r12, [%r1, 1]
- brne %r4, %r5, .Lbyte_even
- ldb.a %r4, [%r0, 2]
- ldb.a %r5, [%r1, 2]
- brne %r3, %r12, .Lbyte_odd
-.Lbyte_end:
- bcc .Lbyte_even
- brne %r4, %r5, .Lbyte_even
- ldb_s %r3, [%r0, 1]
- ldb_s %r12, [%r1, 1]
-.Lbyte_odd:
- j_s.d [%blink]
- sub %r0, %r3, %r12
-.Lbyte_even:
- j_s.d [%blink]
- sub %r0, %r4, %r5
-.Lnil:
- j_s.d [%blink]
- mov %r0, 0
diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
deleted file mode 100644
index 51dd73a..0000000
--- a/arch/arc/lib/memcpy-700.S
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global memcpy
-.align 4
-memcpy:
- or %r3, %r0, %r1
- asl_s %r3, %r3, 30
- mov_s %r5, %r0
- brls.d %r2, %r3, .Lcopy_bytewise
- sub.f %r3, %r2, 1
- ld_s %r12, [%r1, 0]
- asr.f %lp_count, %r3, 3
- bbit0.d %r3, 2, .Lnox4
- bmsk_s %r2, %r2, 1
- st.ab %r12, [%r5, 4]
- ld.a %r12, [%r1, 4]
-.Lnox4:
- lppnz .Lendloop
- ld_s %r3, [%r1, 4]
- st.ab %r12, [%r5, 4]
- ld.a %r12, [%r1, 8]
- st.ab %r3, [%r5, 4]
-.Lendloop:
- breq %r2, 0, .Last_store
- ld %r3, [%r5, 0]
-#ifdef __LITTLE_ENDIAN__
- add3 %r2, -1, %r2
- /* uses long immediate */
- xor_s %r12, %r12, %r3
- bmsk %r12, %r12, %r2
- xor_s %r12, %r12, %r3
-#else /* __BIG_ENDIAN__ */
- sub3 %r2, 31, %r2
- /* uses long immediate */
- xor_s %r3, %r3, %r12
- bmsk %r3, %r3, %r2
- xor_s %r12, %r12, %r3
-#endif /* _ENDIAN__ */
-.Last_store:
- j_s.d [%blink]
- st %r12, [%r5, 0]
-
- .balign 4
-.Lcopy_bytewise:
- jcs [%blink]
- ldb_s %r12, [%r1, 0]
- lsr.f %lp_count, %r3
- bhs_s .Lnox1
- stb.ab %r12, [%r5, 1]
- ldb.a %r12, [%r1, 1]
-.Lnox1:
- lppnz .Lendbloop
- ldb_s %r3, [%r1, 1]
- stb.ab %r12, [%r5, 1]
- ldb.a %r12, [%r1, 2]
- stb.ab %r3, [%r5, 1]
-.Lendbloop:
- j_s.d [%blink]
- stb %r12, [%r5, 0]
diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
deleted file mode 100644
index 017e8af..0000000
--- a/arch/arc/lib/memset.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */
-
-.global memset
-.align 4
-memset:
- mov_s %r4, %r0
- or %r12, %r0, %r2
- bmsk.f %r12, %r12, 1
- extb_s %r1, %r1
- asl %r3, %r1, 8
- beq.d .Laligned
- or_s %r1, %r1, %r3
- brls %r2, SMALL, .Ltiny
- add %r3, %r2, %r0
- stb %r1, [%r3, -1]
- bclr_s %r3, %r3, 0
- stw %r1, [%r3, -2]
- bmsk.f %r12, %r0, 1
- add_s %r2, %r2, %r12
- sub.ne %r2, %r2, 4
- stb.ab %r1, [%r4, 1]
- and %r4, %r4, -2
- stw.ab %r1, [%r4, 2]
- and %r4, %r4, -4
-
- .balign 4
-.Laligned:
- asl %r3, %r1, 16
- lsr.f %lp_count, %r2, 2
- or_s %r1, %r1, %r3
- lpne .Loop_end
- st.ab %r1, [%r4, 4]
-.Loop_end:
- j_s [%blink]
-
- .balign 4
-.Ltiny:
- mov.f %lp_count, %r2
- lpne .Ltiny_end
- stb.ab %r1, [%r4, 1]
-.Ltiny_end:
- j_s [%blink]
-
-/*
- * memzero: @r0 = mem, @r1 = size_t
- * memset: @r0 = mem, @r1 = char, @r2 = size_t
- */
-
-.global memzero
-.align 4
-memzero:
- /* adjust bzero args to memset args */
- mov %r2, %r1
- mov %r1, 0
- /* tail call so need to tinker with blink */
- b memset
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
index 2482bcd..4ffba84 100644
--- a/arch/arc/lib/relocate.c
+++ b/arch/arc/lib/relocate.c
@@ -1,15 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <elf.h>
-#include <asm/sections.h>
+#include <asm-generic/sections.h>
+
+extern ulong __image_copy_start;
+extern ulong __ivt_start;
+extern ulong __ivt_end;
+extern ulong __text_end;
DECLARE_GLOBAL_DATA_PTR;
+int copy_uboot_to_ram(void)
+{
+ size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
+
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ return 0;
+
+ memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
+
+ return 0;
+}
+
+int clear_bss(void)
+{
+ ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
+ size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+
+ memset((void *)dst_addr, 0x00, len);
+
+ return 0;
+}
+
/*
* Base functionality is taken from x86 version with added ARC-specifics
*/
@@ -18,7 +44,13 @@
Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
- Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ return 0;
+
+ debug("Section .rela.dyn is located at %08x-%08x\n",
+ (unsigned int)re_src, (unsigned int)re_end);
+
+ Elf32_Addr *offset_ptr_rom;
Elf32_Addr *offset_ptr_ram;
do {
@@ -26,13 +58,30 @@
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
- if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
- offset_ptr_rom > last_offset) {
- unsigned int val;
+ if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
+ offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
+ unsigned int val, do_swap = 0;
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
gd->reloc_off);
+#ifdef __LITTLE_ENDIAN__
+ /* If location in ".text" section swap value */
+ if (((u32)offset_ptr_rom >= (u32)&__text_start &&
+ (u32)offset_ptr_rom <= (u32)&__text_end)
+#if defined(__ARC700__) || defined(__ARC600__)
+ || ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
+ (u32)offset_ptr_rom <= (u32)&__ivt_end)
+#endif
+ )
+ do_swap = 1;
+#endif
+
+ debug("Patching value @ %08x (relocated to %08x)%s\n",
+ (unsigned int)offset_ptr_rom,
+ (unsigned int)offset_ptr_ram,
+ do_swap ? ", middle-endian encoded" : "");
+
/*
* Use "memcpy" because target location might be
* 16-bit aligned on ARC so we may need to read
@@ -41,35 +90,45 @@
*/
memcpy(&val, offset_ptr_ram, sizeof(int));
-#ifdef __LITTLE_ENDIAN__
- /* If location in ".text" section swap value */
- if ((unsigned int)offset_ptr_rom <
- (unsigned int)&__text_end)
+ if (do_swap)
val = (val << 16) | (val >> 16);
-#endif
- /* Check that the target points into .text */
- if (val >= CONFIG_SYS_TEXT_BASE && val <=
- (unsigned int)&__bss_end) {
- val += gd->reloc_off;
-#ifdef __LITTLE_ENDIAN__
- /* If location in ".text" section swap value */
- if ((unsigned int)offset_ptr_rom <
- (unsigned int)&__text_end)
- val = (val << 16) | (val >> 16);
-#endif
- memcpy(offset_ptr_ram, &val, sizeof(int));
- } else {
- debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n",
- re_src, re_src->r_offset, offset_ptr_ram,
- val, (unsigned int)&__bss_end);
+ /* Check that the target points into executable */
+ if (val < (unsigned int)&__image_copy_start ||
+ val > (unsigned int)&__image_copy_end) {
+ /* TODO: Use panic() instead of debug()
+ *
+ * For some reason GCC might generate
+ * fake relocation even for LD/SC of constant
+ * inderectly. See an example below:
+ * ----------------------->8--------------------
+ * static int setup_mon_len(void)
+ * {
+ * gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+ * return 0;
+ * }
+ * ----------------------->8--------------------
+ *
+ * And that's what we get in the binary:
+ * ----------------------->8--------------------
+ * 10005cb4 <setup_mon_len>:
+ * 10005cb4: 193c 3f80 0003 2f80 st 0x32f80,[r25,60]
+ * 10005cb8: R_ARC_RELATIVE *ABS*-0x10000000
+ * 10005cbc: 7fe0 j_s.d [blink]
+ * 10005cbe: 700c mov_s r0,0
+ * ----------------------->8--------------------
+ */
+ debug("Relocation target %08x points outside of image\n",
+ val);
}
- } else {
- debug(" %p: rom reloc %x, last %p\n", re_src,
- re_src->r_offset, last_offset);
- }
- last_offset = offset_ptr_rom;
+ val += gd->reloc_off;
+
+ if (do_swap)
+ val = (val << 16) | (val >> 16);
+
+ memcpy(offset_ptr_ram, &val, sizeof(int));
+ }
} while (++re_src < re_end);
return 0;
diff --git a/arch/arc/lib/reset.c b/arch/arc/lib/reset.c
new file mode 100644
index 0000000..02e08df
--- /dev/null
+++ b/arch/arc/lib/reset.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#include <command.h>
+#include <common.h>
+
+__weak void reset_cpu(ulong addr)
+{
+ /* Stop debug session here */
+ __builtin_arc_brk();
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ printf("Resetting the board...\n");
+
+ reset_cpu(0);
+
+ return 0;
+}
diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c
deleted file mode 100644
index b0b46a4..0000000
--- a/arch/arc/lib/sections.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * For some reason linker sets linker-generated symbols to zero in PIE mode.
- * A work-around is substitution of linker-generated symbols with
- * compiler-generated symbols which are properly handled by linker in PAE mode.
- */
-
-char __bss_start[0] __attribute__((section(".__bss_start")));
-char __bss_end[0] __attribute__((section(".__bss_end")));
-char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
-char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
-char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
-char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
-char __text_start[0] __attribute__((section(".__text_start")));
-char __text_end[0] __attribute__((section(".__text_end")));
-char __init_end[0] __attribute__((section(".__init_end")));
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
new file mode 100644
index 0000000..84959b4
--- /dev/null
+++ b/arch/arc/lib/start.S
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/arcregs.h>
+
+ENTRY(_start)
+ /* Setup interrupt vector base that matches "__text_start" */
+ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+ ; Disable/enable I-cache according to configuration
+ lr r5, [ARC_BCR_IC_BUILD]
+ breq r5, 0, 1f ; I$ doesn't exist
+ lr r5, [ARC_AUX_IC_CTRL]
+#ifndef CONFIG_SYS_ICACHE_OFF
+ bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
+#else
+ bset r5, r5, 0 ; I$ exists, but is not used
+#endif
+ sr r5, [ARC_AUX_IC_CTRL]
+
+ mov r5, 1
+ sr r5, [ARC_AUX_IC_IVIC]
+ ; As per ARC HS databook (see chapter 5.3.3.2)
+ ; it is required to add 3 NOPs after each write to IC_IVIC.
+ nop
+ nop
+ nop
+
+1:
+ ; Disable/enable D-cache according to configuration
+ lr r5, [ARC_BCR_DC_BUILD]
+ breq r5, 0, 1f ; D$ doesn't exist
+ lr r5, [ARC_AUX_DC_CTRL]
+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
+#ifndef CONFIG_SYS_DCACHE_OFF
+ bclr r5, r5, 0 ; Enable (+Inv)
+#else
+ bset r5, r5, 0 ; Disable (+Inv)
+#endif
+ sr r5, [ARC_AUX_DC_CTRL]
+
+ mov r5, 1
+ sr r5, [ARC_AUX_DC_IVDC]
+
+
+1:
+#ifdef CONFIG_ISA_ARCV2
+ ; Disable System-Level Cache (SLC)
+ lr r5, [ARC_BCR_SLC]
+ breq r5, 0, 1f ; SLC doesn't exist
+ lr r5, [ARC_AUX_SLC_CTRL]
+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
+ bclr r5, r5, 0 ; Enable (+Inv)
+ sr r5, [ARC_AUX_SLC_CTRL]
+
+1:
+#endif
+
+#ifdef __ARC_UNALIGNED__
+ /*
+ * Enable handling of unaligned access in the CPU as by default
+ * this HW feature is disabled while GCC starting from 8.1.0
+ * unconditionally uses it for ARC HS cores.
+ */
+ flag 1 << STATUS_AD_BIT
+#endif
+
+ /* Establish C runtime stack and frame */
+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %fp, %sp
+
+ /* Allocate reserved area from current top of stack */
+ mov %r0, %sp
+ bl board_init_f_alloc_reserve
+ /* Set stack below reserved area, adjust frame pointer accordingly */
+ mov %sp, %r0
+ mov %fp, %sp
+
+ /* Initialize reserved area - note: r0 already contains address */
+ bl board_init_f_init_reserve
+
+#ifdef CONFIG_DEBUG_UART
+ /* Earliest point to set up early debug uart */
+ bl debug_uart_init
+#endif
+
+ /* Zero the one and only argument of "board_init_f" */
+ mov_s %r0, 0
+ bl board_init_f
+
+ /* We only get here if relocation is disabled by GD_FLG_SKIP_RELOC */
+ /* Make sure we don't lose GD overwritten by zero new GD */
+ mov %r0, %r25
+ mov %r1, 0
+ bl board_init_r
+ENDPROC(_start)
+
+/*
+ * void board_init_f_r_trampoline(stack-pointer address)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = new stack-pointer
+ */
+ENTRY(board_init_f_r_trampoline)
+ /* Set up the stack- and frame-pointers */
+ mov %sp, %r0
+ mov %fp, %sp
+
+ /* Update position of intterupt vector table */
+ lr %r0, [ARC_AUX_INTR_VEC_BASE]
+ ld %r1, [%r25, GD_RELOC_OFF]
+ add %r0, %r0, %r1
+ sr %r0, [ARC_AUX_INTR_VEC_BASE]
+
+ /* Re-enter U-Boot by calling board_init_f_r */
+ j board_init_f_r
+ENDPROC(board_init_f_r_trampoline)
diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
deleted file mode 100644
index 55fcc9f..0000000
--- a/arch/arc/lib/strchr-700.S
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * ARC700 has a relatively long pipeline and branch prediction, so we want
- * to avoid branches that are hard to predict. On the other hand, the
- * presence of the norm instruction makes it easier to operate on whole
- * words branch-free.
- */
-
-.global strchr
-.align 4
-strchr:
- extb_s %r1, %r1
- asl %r5, %r1, 8
- bmsk %r2, %r0, 1
- or %r5, %r5, %r1
- mov_s %r3, 0x01010101
- breq.d %r2, %r0, .Laligned
- asl %r4, %r5, 16
- sub_s %r0, %r0, %r2
- asl %r7, %r2, 3
- ld_s %r2, [%r0]
-#ifdef __LITTLE_ENDIAN__
- asl %r7, %r3, %r7
-#else /* __BIG_ENDIAN__ */
- lsr %r7, %r3, %r7
-#endif /* _ENDIAN__ */
- or %r5, %r5, %r4
- ror %r4, %r3
- sub %r12, %r2, %r7
- bic_s %r12, %r12, %r2
- and %r12, %r12, %r4
- brne.d %r12, 0, .Lfound0_ua
- xor %r6, %r2, %r5
- ld.a %r2, [%r0, 4]
- sub %r12, %r6, %r7
- bic %r12, %r12, %r6
-#ifdef __LITTLE_ENDIAN__
- and %r7, %r12, %r4
- /* For speed, we want this branch to be unaligned. */
- breq %r7, 0, .Loop
- /* Likewise this one */
- b .Lfound_char
-#else /* __BIG_ENDIAN__ */
- and %r12, %r12, %r4
- /* For speed, we want this branch to be unaligned. */
- breq %r12, 0, .Loop
- lsr_s %r12, %r12, 7
- bic %r2, %r7, %r6
- b.d .Lfound_char_b
- and_s %r2, %r2, %r12
-#endif /* _ENDIAN__ */
- /* We require this code address to be unaligned for speed... */
-.Laligned:
- ld_s %r2, [%r0]
- or %r5, %r5, %r4
- ror %r4, %r3
- /* ... so that this code address is aligned, for itself and ... */
-.Loop:
- sub %r12, %r2, %r3
- bic_s %r12, %r12, %r2
- and %r12, %r12, %r4
- brne.d %r12, 0, .Lfound0
- xor %r6, %r2, %r5
- ld.a %r2, [%r0, 4]
- sub %r12, %r6, %r3
- bic %r12, %r12, %r6
- and %r7, %r12, %r4
- breq %r7, 0, .Loop
- /*
- *... so that this branch is unaligned.
- * Found searched-for character.
- * r0 has already advanced to next word.
- */
-#ifdef __LITTLE_ENDIAN__
- /*
- * We only need the information about the first matching byte
- * (i.e. the least significant matching byte) to be exact,
- * hence there is no problem with carry effects.
- */
-.Lfound_char:
- sub %r3, %r7, 1
- bic %r3, %r3, %r7
- norm %r2, %r3
- sub_s %r0, %r0, 1
- asr_s %r2, %r2, 3
- j.d [%blink]
- sub_s %r0, %r0, %r2
-
- .balign 4
-.Lfound0_ua:
- mov %r3, %r7
-.Lfound0:
- sub %r3, %r6, %r3
- bic %r3, %r3, %r6
- and %r2, %r3, %r4
- or_s %r12, %r12, %r2
- sub_s %r3, %r12, 1
- bic_s %r3, %r3, %r12
- norm %r3, %r3
- add_s %r0, %r0, 3
- asr_s %r12, %r3, 3
- asl.f 0, %r2, %r3
- sub_s %r0, %r0, %r12
- j_s.d [%blink]
- mov.pl %r0, 0
-#else /* __BIG_ENDIAN__ */
-.Lfound_char:
- lsr %r7, %r7, 7
-
- bic %r2, %r7, %r6
-.Lfound_char_b:
- norm %r2, %r2
- sub_s %r0, %r0, 4
- asr_s %r2, %r2, 3
- j.d [%blink]
- add_s %r0, %r0, %r2
-
-.Lfound0_ua:
- mov_s %r3, %r7
-.Lfound0:
- asl_s %r2, %r2, 7
- or %r7, %r6, %r4
- bic_s %r12, %r12, %r2
- sub %r2, %r7, %r3
- or %r2, %r2, %r6
- bic %r12, %r2, %r12
- bic.f %r3, %r4, %r12
- norm %r3, %r3
-
- add.pl %r3, %r3, 1
- asr_s %r12, %r3, 3
- asl.f 0, %r2, %r3
- add_s %r0, %r0, %r12
- j_s.d [%blink]
- mov.mi %r0, 0
-#endif /* _ENDIAN__ */
diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
deleted file mode 100644
index 8cb7d2f..0000000
--- a/arch/arc/lib/strcmp.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This is optimized primarily for the ARC700.
- * It would be possible to speed up the loops by one cycle / word
- * respective one cycle / byte by forcing double source 1 alignment, unrolling
- * by a factor of two, and speculatively loading the second word / byte of
- * source 1; however, that would increase the overhead for loop setup / finish,
- * and strcmp might often terminate early.
- */
-
-.global strcmp
-.align 4
-strcmp:
- or %r2, %r0, %r1
- bmsk_s %r2, %r2, 1
- brne %r2, 0, .Lcharloop
- mov_s %r12, 0x01010101
- ror %r5, %r12
-.Lwordloop:
- ld.ab %r2, [%r0, 4]
- ld.ab %r3, [%r1, 4]
- nop_s
- sub %r4, %r2, %r12
- bic %r4, %r4, %r2
- and %r4, %r4, %r5
- brne %r4, 0, .Lfound0
- breq %r2 ,%r3, .Lwordloop
-#ifdef __LITTLE_ENDIAN__
- xor %r0, %r2, %r3 /* mask for difference */
- sub_s %r1, %r0, 1
- bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
- sub %r1, %r5, %r0
- xor %r0, %r5, %r1 /* mask for least significant difference byte */
- and_s %r2, %r2, %r0
- and_s %r3, %r3, %r0
-#endif /* _ENDIAN__ */
- cmp_s %r2, %r3
- mov_s %r0, 1
- j_s.d [%blink]
- bset.lo %r0, %r0, 31
-
- .balign 4
-#ifdef __LITTLE_ENDIAN__
-.Lfound0:
- xor %r0, %r2, %r3 /* mask for difference */
- or %r0, %r0, %r4 /* or in zero indicator */
- sub_s %r1, %r0, 1
- bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
- sub %r1, %r5, %r0
- xor %r0, %r5, %r1 /* mask for least significant difference byte */
- and_s %r2, %r2, %r0
- and_s %r3, %r3, %r0
- sub.f %r0, %r2, %r3
- mov.hi %r0, 1
- j_s.d [%blink]
- bset.lo %r0, %r0, 31
-#else /* __BIG_ENDIAN__ */
- /*
- * The zero-detection above can mis-detect 0x01 bytes as zeroes
- * because of carry-propagateion from a lower significant zero byte.
- * We can compensate for this by checking that bit0 is zero.
- * This compensation is not necessary in the step where we
- * get a low estimate for r2, because in any affected bytes
- * we already have 0x00 or 0x01, which will remain unchanged
- * when bit 7 is cleared.
- */
- .balign 4
-.Lfound0:
- lsr %r0, %r4, 8
- lsr_s %r1, %r2
- bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */
- bic_s %r0, %r0, %r1 /* <this is the adjusted mask for zeros> */
- or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */
- cmp_s %r3, %r2 /* ... be independent of trailing garbage */
- or_s %r2, %r2, %r0 /* likewise for r3 > r2 */
- bic_s %r3, %r3, %r0
- rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */
- cmp_s %r2, %r3
- j_s.d [%blink]
- bset.lo %r0, %r0, 31
-#endif /* _ENDIAN__ */
-
- .balign 4
-.Lcharloop:
- ldb.ab %r2,[%r0,1]
- ldb.ab %r3,[%r1,1]
- nop_s
- breq %r2, 0, .Lcmpend
- breq %r2, %r3, .Lcharloop
-.Lcmpend:
- j_s.d [%blink]
- sub %r0, %r2, %r3
diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
deleted file mode 100644
index 41bb53e..0000000
--- a/arch/arc/lib/strcpy-700.S
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * If dst and src are 4 byte aligned, copy 8 bytes at a time.
- * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
- * it 8 byte aligned. Thus, we can do a little read-ahead, without
- * dereferencing a cache line that we should not touch.
- * Note that short and long instructions have been scheduled to avoid
- * branch stalls.
- * The beq_s to r3z could be made unaligned & long to avoid a stall
- * there, but it is not likely to be taken often, and it would also be likely
- * to cost an unaligned mispredict at the next call.
- */
-
-.global strcpy
-.align 4
-strcpy:
- or %r2, %r0, %r1
- bmsk_s %r2, %r2, 1
- brne.d %r2, 0, charloop
- mov_s %r10, %r0
- ld_s %r3, [%r1, 0]
- mov %r8, 0x01010101
- bbit0.d %r1, 2, loop_start
- ror %r12, %r8
- sub %r2, %r3, %r8
- bic_s %r2, %r2, %r3
- tst_s %r2,%r12
- bne r3z
- mov_s %r4,%r3
- .balign 4
-loop:
- ld.a %r3, [%r1, 4]
- st.ab %r4, [%r10, 4]
-loop_start:
- ld.a %r4, [%r1, 4]
- sub %r2, %r3, %r8
- bic_s %r2, %r2, %r3
- tst_s %r2, %r12
- bne_s r3z
- st.ab %r3, [%r10, 4]
- sub %r2, %r4, %r8
- bic %r2, %r2, %r4
- tst %r2, %r12
- beq loop
- mov_s %r3, %r4
-#ifdef __LITTLE_ENDIAN__
-r3z: bmsk.f %r1, %r3, 7
- lsr_s %r3, %r3, 8
-#else /* __BIG_ENDIAN__ */
-r3z: lsr.f %r1, %r3, 24
- asl_s %r3, %r3, 8
-#endif /* _ENDIAN__ */
- bne.d r3z
- stb.ab %r1, [%r10, 1]
- j_s [%blink]
-
- .balign 4
-charloop:
- ldb.ab %r3, [%r1, 1]
- brne.d %r3, 0, charloop
- stb.ab %r3, [%r10, 1]
- j [%blink]
diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
deleted file mode 100644
index 666e22c..0000000
--- a/arch/arc/lib/strlen.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global strlen
-.align 4
-strlen:
- or %r3, %r0, 7
- ld %r2, [%r3, -7]
- ld.a %r6, [%r3, -3]
- mov %r4, 0x01010101
- /* uses long immediate */
-#ifdef __LITTLE_ENDIAN__
- asl_s %r1, %r0, 3
- btst_s %r0, 2
- asl %r7, %r4, %r1
- ror %r5, %r4
- sub %r1, %r2, %r7
- bic_s %r1, %r1, %r2
- mov.eq %r7, %r4
- sub %r12, %r6, %r7
- bic %r12, %r12, %r6
- or.eq %r12, %r12, %r1
- and %r12, %r12, %r5
- brne %r12, 0, .Learly_end
-#else /* __BIG_ENDIAN__ */
- ror %r5, %r4
- btst_s %r0, 2
- mov_s %r1, 31
- sub3 %r7, %r1, %r0
- sub %r1, %r2, %r4
- bic_s %r1, %r1, %r2
- bmsk %r1, %r1, %r7
- sub %r12, %r6, %r4
- bic %r12, %r12, %r6
- bmsk.ne %r12, %r12, %r7
- or.eq %r12, %r12, %r1
- and %r12, %r12, %r5
- brne %r12, 0, .Learly_end
-#endif /* _ENDIAN__ */
-
-.Loop:
- ld_s %r2, [%r3, 4]
- ld.a %r6, [%r3, 8]
- /* stall for load result */
- sub %r1, %r2, %r4
- bic_s %r1, %r1, %r2
- sub %r12, %r6, %r4
- bic %r12, %r12, %r6
- or %r12, %r12, %r1
- and %r12, %r12, %r5
- breq %r12, 0, .Loop
-.Lend:
- and.f %r1, %r1, %r5
- sub.ne %r3, %r3, 4
- mov.eq %r1, %r12
-#ifdef __LITTLE_ENDIAN__
- sub_s %r2, %r1, 1
- bic_s %r2, %r2, %r1
- norm %r1, %r2
- sub_s %r0, %r0, 3
- lsr_s %r1, %r1, 3
- sub %r0, %r3, %r0
- j_s.d [%blink]
- sub %r0, %r0, %r1
-#else /* __BIG_ENDIAN__ */
- lsr_s %r1, %r1, 7
- mov.eq %r2, %r6
- bic_s %r1, %r1, %r2
- norm %r1, %r1
- sub %r0, %r3, %r0
- lsr_s %r1, %r1, 3
- j_s.d [%blink]
- add %r0, %r0, %r1
-#endif /* _ENDIAN */
-.Learly_end:
- b.d .Lend
- sub_s.ne %r1, %r1, %r1
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bb680e8..d6b1629 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -6,113 +6,409 @@
config ARM64
bool
+ select PHYS_64BIT
+ select SYS_CACHE_SHIFT_6
+
+if ARM64
+config POSITION_INDEPENDENT
+ bool "Generate position-independent pre-relocation code"
+ help
+ U-Boot expects to be linked to a specific hard-coded address, and to
+ be loaded to and run from that address. This option lifts that
+ restriction, thus allowing the code to be loaded to and executed
+ from almost any address. This logic relies on the relocation
+ information that is embedded into the binary to support U-Boot
+ relocating itself to the top-of-RAM later during execution.
+
+config SYS_INIT_SP_BSS_OFFSET
+ int
+ help
+ U-Boot typically uses a hard-coded value for the stack pointer
+ before relocation. Define this option to instead calculate the
+ initial SP at run-time. This is useful to avoid hard-coding addresses
+ into U-Boot, so that can be loaded and executed at arbitrary
+ addresses and thus avoid using arbitrary addresses at runtime. This
+ option's value is the offset added to &_bss_start in order to
+ calculate the stack pointer. This offset should be large enough so
+ that the early malloc region, global data (gd), and early stack usage
+ do not overlap any appended DTB.
+
+config LINUX_KERNEL_IMAGE_HEADER
+ bool
+ help
+ Place a Linux kernel image header at the start of the U-Boot binary.
+ The format of the header is described in the Linux kernel source at
+ Documentation/arm64/booting.txt. This feature is useful since the
+ image header reports the amount of memory (BSS and similar) that
+ U-Boot needs to use, but which isn't part of the binary.
+
+if LINUX_KERNEL_IMAGE_HEADER
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ hex
+ help
+ The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
+ TEXT_OFFSET value written in to the Linux kernel image header.
+endif
+endif
+
+config STATIC_RELA
+ bool
+ default y if ARM64 && !POSITION_INDEPENDENT
+
+config DMA_ADDR_T_64BIT
+ bool
+ default y if ARM64
config HAS_VBAR
- bool
+ bool
+
+config HAS_THUMB2
+ bool
+
+# Used for compatibility with asm files copied from the kernel
+config ARM_ASM_UNIFIED
+ bool
+ default y
+
+# Used for compatibility with asm files copied from the kernel
+config THUMB2_KERNEL
+ bool
+
+config SYS_ARM_CACHE_CP15
+ bool "CP15 based cache enabling support"
+ help
+ Select this if your processor suports enabling caches by using
+ CP15 registers.
+
+config SYS_ARM_MMU
+ bool "MMU-based Paged Memory Management Support"
+ select SYS_ARM_CACHE_CP15
+ help
+ Select if you want MMU-based virtualised addressing space
+ support by paged memory management.
+
+config SYS_ARM_MPU
+ bool 'Use the ARM v7 PMSA Compliant MPU'
+ help
+ Some ARM systems without an MMU have instead a Memory Protection
+ Unit (MPU) that defines the type and permissions for regions of
+ memory.
+ If your CPU has an MPU then you should choose 'y' here unless you
+ know that you do not want to use the MPU.
+
+# If set, the workarounds for these ARM errata are applied early during U-Boot
+# startup. Note that in general these options force the workarounds to be
+# applied; no CPU-type/version detection exists, unlike the similar options in
+# the Linux kernel. Do not set these options unless they apply! Also note that
+# the following can be machine specific errata. These do have ability to
+# provide rudimentary version and machine specific checks, but expect no
+# product checks:
+# CONFIG_ARM_ERRATA_430973
+# CONFIG_ARM_ERRATA_454179
+# CONFIG_ARM_ERRATA_621766
+# CONFIG_ARM_ERRATA_798870
+# CONFIG_ARM_ERRATA_801819
+# CONFIG_ARM_CORTEX_A8_CVE_2017_5715
+# CONFIG_ARM_CORTEX_A15_CVE_2017_5715
+
+config ARM_ERRATA_430973
+ bool
+
+config ARM_ERRATA_454179
+ bool
+
+config ARM_ERRATA_621766
+ bool
+
+config ARM_ERRATA_716044
+ bool
+
+config ARM_ERRATA_725233
+ bool
+
+config ARM_ERRATA_742230
+ bool
+
+config ARM_ERRATA_743622
+ bool
+
+config ARM_ERRATA_751472
+ bool
+
+config ARM_ERRATA_761320
+ bool
+
+config ARM_ERRATA_773022
+ bool
+
+config ARM_ERRATA_774769
+ bool
+
+config ARM_ERRATA_794072
+ bool
+
+config ARM_ERRATA_798870
+ bool
+
+config ARM_ERRATA_801819
+ bool
+
+config ARM_ERRATA_826974
+ bool
+
+config ARM_ERRATA_828024
+ bool
+
+config ARM_ERRATA_829520
+ bool
+
+config ARM_ERRATA_833069
+ bool
+
+config ARM_ERRATA_833471
+ bool
+
+config ARM_ERRATA_845369
+ bool
+
+config ARM_ERRATA_852421
+ bool
+
+config ARM_ERRATA_852423
+ bool
+
+config ARM_ERRATA_855873
+ bool
+
+config ARM_CORTEX_A8_CVE_2017_5715
+ bool
+
+config ARM_CORTEX_A15_CVE_2017_5715
+ bool
config CPU_ARM720T
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config CPU_ARM920T
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config CPU_ARM926EJS
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config CPU_ARM946ES
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config CPU_ARM1136
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config CPU_ARM1176
- bool
- select HAS_VBAR
+ bool
+ select HAS_VBAR
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
-config CPU_V7
- bool
- select HAS_VBAR
+config CPU_V7A
+ bool
+ select HAS_THUMB2
+ select HAS_VBAR
+ select SYS_CACHE_SHIFT_6
+ imply SYS_ARM_MMU
+
+config CPU_V7M
+ bool
+ select HAS_THUMB2
+ select SYS_ARM_MPU
+ select SYS_CACHE_SHIFT_5
+ select SYS_THUMB_BUILD
+ select THUMB2_KERNEL
+
+config CPU_V7R
+ bool
+ select HAS_THUMB2
+ select SYS_ARM_CACHE_CP15
+ select SYS_ARM_MPU
+ select SYS_CACHE_SHIFT_6
config CPU_PXA
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config CPU_SA1100
- bool
+ bool
+ select SYS_CACHE_SHIFT_5
+ imply SYS_ARM_MMU
config SYS_CPU
- default "arm720t" if CPU_ARM720T
- default "arm920t" if CPU_ARM920T
- default "arm926ejs" if CPU_ARM926EJS
- default "arm946es" if CPU_ARM946ES
- default "arm1136" if CPU_ARM1136
- default "arm1176" if CPU_ARM1176
- default "armv7" if CPU_V7
- default "pxa" if CPU_PXA
- default "sa1100" if CPU_SA1100
+ default "arm720t" if CPU_ARM720T
+ default "arm920t" if CPU_ARM920T
+ default "arm926ejs" if CPU_ARM926EJS
+ default "arm946es" if CPU_ARM946ES
+ default "arm1136" if CPU_ARM1136
+ default "arm1176" if CPU_ARM1176
+ default "armv7" if CPU_V7A
+ default "armv7" if CPU_V7R
+ default "armv7m" if CPU_V7M
+ default "pxa" if CPU_PXA
+ default "sa1100" if CPU_SA1100
default "armv8" if ARM64
+config SYS_ARM_ARCH
+ int
+ default 4 if CPU_ARM720T
+ default 4 if CPU_ARM920T
+ default 5 if CPU_ARM926EJS
+ default 5 if CPU_ARM946ES
+ default 6 if CPU_ARM1136
+ default 6 if CPU_ARM1176
+ default 7 if CPU_V7A
+ default 7 if CPU_V7M
+ default 7 if CPU_V7R
+ default 5 if CPU_PXA
+ default 4 if CPU_SA1100
+ default 8 if ARM64
+
+config SYS_CACHE_SHIFT_5
+ bool
+
+config SYS_CACHE_SHIFT_6
+ bool
+
+config SYS_CACHE_SHIFT_7
+ bool
+
+config SYS_CACHELINE_SIZE
+ int
+ default 128 if SYS_CACHE_SHIFT_7
+ default 64 if SYS_CACHE_SHIFT_6
+ default 32 if SYS_CACHE_SHIFT_5
+
+config SYS_ARCH_TIMER
+ bool "ARM Generic Timer support"
+ depends on CPU_V7A || ARM64
+ default y if ARM64
+ help
+ The ARM Generic Timer (aka arch-timer) provides an architected
+ interface to a timer source on an SoC.
+ It is mandantory for ARMv8 implementation and widely available
+ on ARMv7 systems.
+
+config ARM_SMCCC
+ bool "Support for ARM SMC Calling Convention (SMCCC)"
+ depends on CPU_V7A || ARM64
+ select ARM_PSCI_FW
+ help
+ Say Y here if you want to enable ARM SMC Calling Convention.
+ This should be enabled if U-Boot needs to communicate with system
+ firmware (for example, PSCI) according to SMCCC.
+
+config SEMIHOSTING
+ bool "support boot from semihosting"
+ help
+ In emulated environments, semihosting is a way for
+ the hosted environment to call out to the emulator to
+ retrieve files from the host machine.
+
+config SYS_THUMB_BUILD
+ bool "Build U-Boot using the Thumb instruction set"
+ depends on !ARM64
+ help
+ Use this flag to build U-Boot using the Thumb instruction set for
+ ARM architectures. Thumb instruction set provides better code
+ density. For ARM architectures that support Thumb2 this flag will
+ result in Thumb2 code generated by GCC.
+
+config SPL_SYS_THUMB_BUILD
+ bool "Build SPL using the Thumb instruction set"
+ default y if SYS_THUMB_BUILD
+ depends on !ARM64
+ help
+ Use this flag to build SPL using the Thumb instruction set for
+ ARM architectures. Thumb instruction set provides better code
+ density. For ARM architectures that support Thumb2 this flag will
+ result in Thumb2 code generated by GCC.
+
+config SYS_L2CACHE_OFF
+ bool "L2cache off"
+ help
+ If SoC does not support L2CACHE or one do not want to enable
+ L2CACHE, choose this option.
+
+config ENABLE_ARM_SOC_BOOT0_HOOK
+ bool "prepare BOOT0 header"
+ help
+ If the SoC's BOOT0 requires a header area filled with (magic)
+ values, then choose this option, and create a file included as
+ <asm/arch/boot0.h> which contains the required assembler code.
+
+config ARM_CORTEX_CPU_IS_UP
+ bool
+ default n
+
+config USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy"
+ default y
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config SPL_USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy for SPL"
+ default y if USE_ARCH_MEMCPY
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset"
+ default y
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memset.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config SPL_USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset for SPL"
+ default y if USE_ARCH_MEMSET
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memset.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config ARM64_SUPPORT_AARCH32
+ bool "ARM64 system support AArch32 execution state"
+ default y if ARM64 && !TARGET_THUNDERX_88XX
+ help
+ This ARM64 system supports AArch32 execution state.
+
choice
prompt "Target select"
+ default TARGET_HIKEY
-config TARGET_INTEGRATORAP_CM720T
- bool "Support integratorap_cm720t"
- select CPU_ARM720T
-
-config TARGET_INTEGRATORAP_CM920T
- bool "Support integratorap_cm920t"
- select CPU_ARM920T
-
-config TARGET_INTEGRATORCP_CM920T
- bool "Support integratorcp_cm920t"
- select CPU_ARM920T
-
-config TARGET_A320EVB
- bool "Support a320evb"
- select CPU_ARM920T
-
-config TARGET_AT91RM9200EK
- bool "Support at91rm9200ek"
- select CPU_ARM920T
-
-config TARGET_EB_CPUX9K2
- bool "Support eb_cpux9k2"
- select CPU_ARM920T
-
-config TARGET_CPUAT91
- bool "Support cpuat91"
- select CPU_ARM920T
+config ARCH_AT91
+ bool "Atmel AT91"
+ select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
-
-config TARGET_SCB9328
- bool "Support scb9328"
- select CPU_ARM920T
-
-config TARGET_CM4008
- bool "Support cm4008"
- select CPU_ARM920T
-
-config TARGET_CM41XX
- bool "Support cm41xx"
- select CPU_ARM920T
-
-config TARGET_VCMA9
- bool "Support VCMA9"
- select CPU_ARM920T
-
-config TARGET_SMDK2410
- bool "Support smdk2410"
- select CPU_ARM920T
-
-config TARGET_INTEGRATORAP_CM926EJS
- bool "Support integratorap_cm926ejs"
- select CPU_ARM926EJS
-
-config TARGET_INTEGRATORCP_CM926EJS
- bool "Support integratorcp_cm926ejs"
- select CPU_ARM926EJS
+ select PL010_SERIAL
config TARGET_ASPENITE
bool "Support aspenite"
@@ -122,267 +418,87 @@
bool "Support gplugd"
select CPU_ARM926EJS
-config TARGET_AFEB9260
- bool "Support afeb9260"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9260EK
- bool "Support at91sam9260ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9261EK
- bool "Support at91sam9261ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9263EK
- bool "Support at91sam9263ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9M10G45EK
- bool "Support at91sam9m10g45ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9N12EK
- bool "Support at91sam9n12ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9RLEK
- bool "Support at91sam9rlek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9X5EK
- bool "Support at91sam9x5ek"
- select CPU_ARM926EJS
-
-config TARGET_SNAPPER9260
- bool "Support snapper9260"
- select CPU_ARM926EJS
-
-config TARGET_VL_MA2SC
- bool "Support vl_ma2sc"
- select CPU_ARM926EJS
-
-config TARGET_SBC35_A9G20
- bool "Support sbc35_a9g20"
- select CPU_ARM926EJS
-
-config TARGET_TNY_A9260
- bool "Support tny_a9260"
- select CPU_ARM926EJS
-
-config TARGET_USB_A9263
- bool "Support usb_a9263"
- select CPU_ARM926EJS
-
-config TARGET_ETHERNUT5
- bool "Support ethernut5"
- select CPU_ARM926EJS
-
-config TARGET_MEESC
- bool "Support meesc"
- select CPU_ARM926EJS
-
-config TARGET_OTC570
- bool "Support otc570"
- select CPU_ARM926EJS
-
-config TARGET_CPU9260
- bool "Support cpu9260"
- select CPU_ARM926EJS
-
-config TARGET_PM9261
- bool "Support pm9261"
- select CPU_ARM926EJS
-
-config TARGET_PM9263
- bool "Support pm9263"
- select CPU_ARM926EJS
-
-config TARGET_PM9G45
- bool "Support pm9g45"
- select CPU_ARM926EJS
-
-config TARGET_CORVUS
- select SUPPORT_SPL
- bool "Support corvus"
- select CPU_ARM926EJS
-
-config TARGET_TAURUS
- select SUPPORT_SPL
- bool "Support taurus"
- select CPU_ARM926EJS
-
-config TARGET_STAMP9G20
- bool "Support stamp9g20"
- select CPU_ARM926EJS
-
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
+ imply CMD_SAVES
help
Support for TI's DaVinci platform.
config KIRKWOOD
bool "Marvell Kirkwood"
+ select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
-config TARGET_DB_MV784MP_GP
- bool "Support db-mv784mp-gp"
- select CPU_V7
-
-config TARGET_MAXBCM
- bool "Support maxbcm"
- select CPU_V7
-
-config TARGET_DEVKIT3250
- bool "Support devkit3250"
- select CPU_ARM926EJS
-
-config TARGET_JADECPU
- bool "Support jadecpu"
- select CPU_ARM926EJS
-
-config TARGET_MX25PDK
- bool "Support mx25pdk"
- select CPU_ARM926EJS
-
-config TARGET_TX25
- bool "Support tx25"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_ZMX25
- bool "Support zmx25"
- select CPU_ARM926EJS
+config ARCH_MVEBU
+ bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select OF_CONTROL
+ select OF_SEPARATE
+ select SPI
+ imply CMD_DM
config TARGET_APF27
bool "Support apf27"
select CPU_ARM926EJS
select SUPPORT_SPL
-config TARGET_IMX27LITE
- bool "Support imx27lite"
- select CPU_ARM926EJS
-
-config TARGET_MAGNESIUM
- bool "Support magnesium"
- select CPU_ARM926EJS
-
-config TARGET_APX4DEVKIT
- bool "Support apx4devkit"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_XFI3
- bool "Support xfi3"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_M28EVK
- bool "Support m28evk"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_MX23EVK
- bool "Support mx23evk"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_MX28EVK
- bool "Support mx28evk"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_MX23_OLINUXINO
- bool "Support mx23_olinuxino"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_BG0900
- bool "Support bg0900"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_SANSA_FUZE_PLUS
- bool "Support sansa_fuze_plus"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config TARGET_SC_SPS_1
- bool "Support sc_sps_1"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
-config ARCH_NOMADIK
- bool "ST-Ericsson Nomadik"
- select CPU_ARM926EJS
-
config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
-config TARGET_DKB
- bool "Support dkb"
- select CPU_ARM926EJS
-
config TARGET_SPEAR300
bool "Support spear300"
+ select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR310
bool "Support spear310"
+ select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR320
bool "Support spear320"
+ select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR600
bool "Support spear600"
+ select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_STV0991
bool "Support stv0991"
- select CPU_V7
+ select CPU_V7A
+ select DM
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select PL01X_SERIAL
+ select SPI
+ select SPI_FLASH
+ imply CMD_DM
config TARGET_X600
bool "Support x600"
+ select BOARD_LATE_INIT
select CPU_ARM926EJS
+ select PL011_SERIAL
select SUPPORT_SPL
-config ARCH_VERSATILE
- bool "ARM Ltd. Versatile family"
- select CPU_ARM926EJS
-
-config TARGET_INTEGRATORCP_CM1136
- bool "Support integratorcp_cm1136"
- select CPU_ARM1136
-
-config TARGET_IMX31_PHYCORE
- bool "Support imx31_phycore"
- select CPU_ARM1136
-
-config TARGET_QONG
- bool "Support qong"
- select CPU_ARM1136
-
-config TARGET_MX31ADS
- bool "Support mx31ads"
- select CPU_ARM1136
-
-config TARGET_MX31PDK
- bool "Support mx31pdk"
- select CPU_ARM1136
- select SUPPORT_SPL
-
-config TARGET_TT01
- bool "Support tt01"
- select CPU_ARM1136
-
-config TARGET_IMX31_LITEKIT
- bool "Support imx31_litekit"
- select CPU_ARM1136
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
@@ -398,635 +514,1064 @@
config TARGET_MX35PDK
bool "Support mx35pdk"
+ select BOARD_LATE_INIT
select CPU_ARM1136
-config TARGET_RPI
- bool "Support rpi"
- select CPU_ARM1176
+config ARCH_BCM283X
+ bool "Broadcom BCM283X family"
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select OF_CONTROL
+ select PL01X_SERIAL
+ select SERIAL_SEARCH_ALL
+ imply CMD_DM
+ imply FAT_WRITE
-config TARGET_TNETV107X_EVM
- bool "Support tnetv107x_evm"
- select CPU_ARM1176
-
-config TARGET_INTEGRATORAP_CM946ES
- bool "Support integratorap_cm946es"
- select CPU_ARM946ES
-
-config TARGET_INTEGRATORCP_CM946ES
- bool "Support integratorcp_cm946es"
- select CPU_ARM946ES
+config ARCH_BCM6858
+ bool "Broadcom BCM6858 family"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
- select CPU_V7
+ select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select PL011_SERIAL
+
+config ARCH_BCMSTB
+ bool "Broadcom BCM7XXX family"
+ select CPU_V7A
+ select DM
+ select OF_CONTROL
+ select OF_PRIOR_STAGE
+ imply CMD_DM
+ help
+ This enables support for Broadcom ARM-based set-top box
+ chipsets, including the 7445 family of chips.
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
- select CPU_V7
+ select CPU_V7A
+ select PL011_SERIAL
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
- select CPU_V7
+ select CPU_V7A
+ select PL011_SERIAL
-config TARGET_KWB
- bool "Support kwb"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_TSERIES
- bool "Support tseries"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_CM_T335
- bool "Support cm_t335"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_PEPPER
- bool "Support pepper"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_AM335X_IGEP0033
- bool "Support am335x_igep0033"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_PCM051
- bool "Support pcm051"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_DRACO
- bool "Support draco"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_DXR2
- bool "Support dxr2"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_PXM2
- bool "Support pxm2"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_RUT
- bool "Support rut"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_PENGWYN
- bool "Support pengwyn"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_AM335X_EVM
- bool "Support am335x_evm"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_AM43XX_EVM
- bool "Support am43xx_evm"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_TI814X_EVM
- bool "Support ti814x_evm"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_TI816X_EVM
- bool "Support ti816x_evm"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SAMA5D3_XPLAINED
- bool "Support sama5d3_xplained"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SAMA5D3XEK
- bool "Support sama5d3xek"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SAMA5D4_XPLAINED
- bool "Support sama5d4_xplained"
- select CPU_V7
-
-config TARGET_SAMA5D4EK
- bool "Support sama5d4ek"
- select CPU_V7
+config TARGET_BCM23550_W1D
+ bool "Support bcm23550_w1d"
+ select CPU_V7A
+ imply CRC32_VERIFY
+ imply FAT_WRITE
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
- select CPU_V7
+ select CPU_V7A
+ imply CRC32_VERIFY
+ imply FAT_WRITE
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
- select CPU_V7
+ select CPU_V7A
+ imply BCM_SF2_ETH
+ imply BCM_SF2_ETH_GMAC
+ imply CMD_HASH
+ imply CRC32_VERIFY
+ imply FAT_WRITE
+ imply HASH_VERIFY
+ imply NETDEVICES
config TARGET_BCMNSP
bool "Support bcmnsp"
- select CPU_V7
+ select CPU_V7A
+
+config TARGET_BCMNS2
+ bool "Support Broadcom Northstar2"
+ select ARM64
+ help
+ Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
+ ARMv8 Cortex-A57 processors targeting a broad range of networking
+ applications
config ARCH_EXYNOS
bool "Samsung EXYNOS"
- select CPU_V7
+ select DM
+ select DM_GPIO
+ select DM_I2C
+ select DM_KEYBOARD
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select SPI
+ imply SYS_THUMB_BUILD
+ imply CMD_DM
+ imply FAT_WRITE
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
- select CPU_V7
+ select CPU_V7A
+ select DM
+ select DM_GPIO
+ select DM_I2C
+ select DM_SERIAL
+ imply CMD_DM
config ARCH_HIGHBANK
bool "Calxeda Highbank"
- select CPU_V7
+ select CPU_V7A
+ select PL011_SERIAL
+
+config ARCH_INTEGRATOR
+ bool "ARM Ltd. Integrator family"
+ select DM
+ select DM_SERIAL
+ select PL01X_SERIAL
+ imply CMD_DM
config ARCH_KEYSTONE
bool "TI Keystone"
- select CPU_V7
+ select CMD_POWEROFF
+ select CPU_V7A
+ select SUPPORT_SPL
+ select SYS_ARCH_TIMER
+ select SYS_THUMB_BUILD
+ imply CMD_MTDPARTS
+ imply CMD_SAVES
+ imply FIT
+
+config ARCH_K3
+ bool "Texas Instruments' K3 Architecture"
+ select SPL
+ select SUPPORT_SPL
+ select FIT
+
+config ARCH_OMAP2PLUS
+ bool "TI OMAP2+"
+ select CPU_V7A
+ select SPL_BOARD_INIT if SPL
+ select SPL_STACK_R if SPL
+ select SUPPORT_SPL
+ imply FIT
+
+config ARCH_MESON
+ bool "Amlogic Meson"
+ imply DISTRO_DEFAULTS
+ help
+ Support for the Meson SoC family developed by Amlogic Inc.,
+ targeted at media players and tablet computers. We currently
+ support the S905 (GXBaby) 64-bit SoC.
+
+config ARCH_MEDIATEK
+ bool "MediaTek SoCs"
+ select BINMAN
+ select DM
+ select OF_CONTROL
+ select SPL_DM if SPL
+ select SPL_LIBCOMMON_SUPPORT if SPL
+ select SPL_LIBGENERIC_SUPPORT if SPL
+ select SPL_OF_CONTROL if SPL
+ select SUPPORT_SPL
+ help
+ Support for the MediaTek SoCs family developed by MediaTek Inc.
+ Please refer to doc/README.mediatek for more information.
+
+config ARCH_LPC32XX
+ bool "NXP LPC32xx platform"
+ select CPU_ARM926EJS
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select SPL_DM if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
+
+config ARCH_IMX8
+ bool "NXP i.MX8 platform"
+ select ARM64
+ select DM
+ select OF_CONTROL
+
+config ARCH_IMX8M
+ bool "NXP i.MX8M platform"
+ select ARM64
+ select DM
+ select SUPPORT_SPL
+ imply CMD_DM
+
+config ARCH_MX23
+ bool "NXP i.MX23 family"
+ select CPU_ARM926EJS
+ select PL011_SERIAL
select SUPPORT_SPL
-config TARGET_M53EVK
- bool "Support m53evk"
- select CPU_V7
+config ARCH_MX25
+ bool "NXP MX25"
+ select CPU_ARM926EJS
+ imply MXC_GPIO
+
+config ARCH_MX28
+ bool "NXP i.MX28 family"
+ select CPU_ARM926EJS
+ select PL011_SERIAL
select SUPPORT_SPL
-config TARGET_IMA3_MX53
- bool "Support ima3-mx53"
- select CPU_V7
+config ARCH_MX31
+ bool "NXP i.MX31 family"
+ select CPU_ARM1136
-config TARGET_MX51EVK
- bool "Support mx51evk"
- select CPU_V7
+config ARCH_MX7ULP
+ bool "NXP MX7ULP"
+ select CPU_V7A
+ select ROM_UNIFIED_SECTIONS
+ imply MXC_GPIO
-config TARGET_MX53ARD
- bool "Support mx53ard"
- select CPU_V7
+config ARCH_MX7
+ bool "Freescale MX7"
+ select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
+ select CPU_V7A
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
+ imply MXC_GPIO
-config TARGET_MX53EVK
- bool "Support mx53evk"
- select CPU_V7
+config ARCH_MX6
+ bool "Freescale MX6"
+ select CPU_V7A
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
+ select SYS_THUMB_BUILD if SPL
+ imply MXC_GPIO
-config TARGET_MX53LOCO
- bool "Support mx53loco"
- select CPU_V7
+if ARCH_MX6
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+endif
-config TARGET_MX53SMD
- bool "Support mx53smd"
- select CPU_V7
+config ARCH_MX5
+ bool "Freescale MX5"
+ select BOARD_EARLY_INIT_F
+ select CPU_V7A
+ imply MXC_GPIO
-config TARGET_MX51_EFIKAMX
- bool "Support mx51_efikamx"
- select CPU_V7
+config ARCH_OWL
+ bool "Actions Semi OWL SoCs"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ imply CMD_DM
-config TARGET_VISION2
- bool "Support vision2"
- select CPU_V7
+config ARCH_QEMU
+ bool "QEMU Virtual Platform"
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select PL01X_SERIAL
+ imply CMD_DM
+ imply DM_RTC
+ imply RTC_PL031
-config TARGET_UDOO
- bool "Support udoo"
- select CPU_V7
-
-config TARGET_WANDBOARD
- bool "Support wandboard"
- select CPU_V7
-
-config TARGET_TITANIUM
- bool "Support titanium"
- select CPU_V7
-
-config TARGET_NITROGEN6X
- bool "Support nitrogen6x"
- select CPU_V7
-
-config TARGET_CGTQMX6EVAL
- bool "Support cgtqmx6eval"
- select CPU_V7
-
-config TARGET_EMBESTMX6BOARDS
- bool "Support embestmx6boards"
- select CPU_V7
-
-config TARGET_ARISTAINETOS
- bool "Support aristainetos"
- select CPU_V7
-
-config TARGET_MX6QARM2
- bool "Support mx6qarm2"
- select CPU_V7
-
-config TARGET_MX6QSABREAUTO
- bool "Support mx6qsabreauto"
- select CPU_V7
-
-config TARGET_MX6SABRESD
- bool "Support mx6sabresd"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_MX6SLEVK
- bool "Support mx6slevk"
- select CPU_V7
-
-config TARGET_MX6SXSABRESD
- bool "Support mx6sxsabresd"
- select CPU_V7
-
-config TARGET_GW_VENTANA
- bool "Support gw_ventana"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_HUMMINGBOARD
- bool "Support hummingboard"
- select CPU_V7
-
-config TARGET_KOSAGI_NOVENA
- bool "Support Kosagi Novena"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_TBS2910
- bool "Support tbs2910"
- select CPU_V7
-
-config TARGET_TQMA6
- bool "TQ Systems TQMa6 board"
- select CPU_V7
-
-config TARGET_OT1200
- bool "Bachmann OT1200"
- select CPU_V7
-
-config OMAP34XX
- bool "OMAP34XX SoC"
- select CPU_V7
-
-config OMAP44XX
- bool "OMAP44XX SoC"
- select CPU_V7
- select SUPPORT_SPL
-
-config OMAP54XX
- bool "OMAP54XX SoC"
- select CPU_V7
- select SUPPORT_SPL
-
-config RMOBILE
+config ARCH_RMOBILE
bool "Renesas ARM SoCs"
- select CPU_V7
+ select BOARD_EARLY_INIT_F
+ select DM
+ select DM_SERIAL
+ imply CMD_DM
+ imply FAT_WRITE
+ imply SYS_THUMB_BUILD
+ imply ARCH_MISC_INIT if DISPLAY_CPUINFO
-config TARGET_CM_FX6
- bool "Support cm_fx6"
- select CPU_V7
- select SUPPORT_SPL
+config TARGET_S32V234EVB
+ bool "Support s32v234evb"
+ select ARM64
+ select SYS_FSL_ERRATUM_ESDHC111
-config TARGET_SOCFPGA_CYCLONE5
- bool "Support socfpga_cyclone5"
- select CPU_V7
+config ARCH_SNAPDRAGON
+ bool "Qualcomm Snapdragon SoCs"
+ select ARM64
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select MSM_SMEM
+ select OF_CONTROL
+ select OF_SEPARATE
+ select SMEM
+ select SPMI
+ imply CMD_DM
+
+config ARCH_SOCFPGA
+ bool "Altera SOCFPGA family"
+ select ARCH_EARLY_INIT_R
+ select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
+ select ARM64 if TARGET_SOCFPGA_STRATIX10
+ select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select DM
+ select DM_SERIAL
+ select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select OF_CONTROL
+ select SPL_DM_RESET if DM_RESET
+ select SPL_DM_SERIAL
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_NAND_SUPPORT if SPL_NAND_DENALI
+ select SPL_OF_CONTROL
+ select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
+ select SPL_SERIAL_SUPPORT
+ select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
+ select SYS_NS16550
+ select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ imply CMD_DM
+ imply CMD_MTDPARTS
+ imply CRC32_VERIFY
+ imply DM_SPI
+ imply DM_SPI_FLASH
+ imply FAT_WRITE
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_MMC_SUPPORT
+ imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ imply SPL_SPI_FLASH_SUPPORT
+ imply SPL_SPI_SUPPORT
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
+ select BINMAN
+ select CMD_GPIO
+ select CMD_MMC if MMC
+ select CMD_USB if DISTRO_DEFAULTS
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_KEYBOARD
+ select DM_SERIAL
+ select DM_USB if DISTRO_DEFAULTS
+ select OF_BOARD_SETUP
+ select OF_CONTROL
+ select OF_SEPARATE
+ select SPECIFY_CONSOLE_INDEX
+ select SPL_STACK_R if SPL
+ select SPL_SYS_MALLOC_SIMPLE if SPL
+ select SPL_SYS_THUMB_BUILD if !ARM64
+ select SYS_NS16550
+ select SYS_THUMB_BUILD if !ARM64
+ select USB if DISTRO_DEFAULTS
+ select USB_KEYBOARD if DISTRO_DEFAULTS
+ select USB_STORAGE if DISTRO_DEFAULTS
+ select USE_TINY_PRINTF
+ imply CMD_DM
+ imply CMD_GPT
+ imply CMD_UBI if NAND
+ imply DISTRO_DEFAULTS
+ imply FAT_WRITE
+ imply FIT
+ imply OF_LIBFDT_OVERLAY
+ imply PRE_CONSOLE_BUFFER
+ imply SPL_GPIO_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_MMC_SUPPORT if MMC
+ imply SPL_POWER_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply USB_GADGET
-config TARGET_SNOWBALL
- bool "Support snowball"
- select CPU_V7
+config ARCH_VERSAL
+ bool "Support Xilinx Versal Platform"
+ select ARM64
+ select CLK
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
-config TARGET_U8500_HREF
- bool "Support u8500_href"
- select CPU_V7
+config ARCH_VF610
+ bool "Freescale Vybrid"
+ select CPU_V7A
+ select SYS_FSL_ERRATUM_ESDHC111
+ imply CMD_MTDPARTS
+ imply NAND
-config TARGET_VF610TWR
- bool "Support vf610twr"
- select CPU_V7
-
-config ZYNQ
- bool "Xilinx Zynq Platform"
- select CPU_V7
+config ARCH_ZYNQ
+ bool "Xilinx Zynq based platform"
+ select BOARD_EARLY_INIT_F if WDT
+ select CLK
+ select CLK_ZYNQ
+ select CPU_V7A
+ select DM
+ select DM_ETH if NET
+ select DM_MMC if MMC
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select DM_USB if USB
+ select OF_CONTROL
+ select SPI
+ select SPL_BOARD_INIT if SPL
+ select SPL_CLK if SPL
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
+ imply ARCH_EARLY_INIT_R
+ imply BOARD_LATE_INIT
+ imply CMD_CLK
+ imply CMD_DM
+ imply CMD_SPL
+ imply FAT_WRITE
+
+config ARCH_ZYNQMP_R5
+ bool "Xilinx ZynqMP R5 based platform"
+ select CLK
+ select CPU_V7R
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ imply CMD_DM
+ imply DM_USB_GADGET
+
+config ARCH_ZYNQMP
+ bool "Xilinx ZynqMP based platform"
+ select ARM64
+ select CLK
+ select DM
+ select DM_SERIAL
+ select DM_USB if USB
+ select OF_CONTROL
+ select SPL_BOARD_INIT if SPL
+ select SPL_CLK if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply BOARD_LATE_INIT
+ imply CMD_DM
+ imply FAT_WRITE
+ imply MP
+ imply DM_USB_GADGET
config TEGRA
bool "NVIDIA Tegra"
- select SUPPORT_SPL
- select SPL
- select OF_CONTROL if !SPL_BUILD
- select CPU_ARM720T if SPL_BUILD
- select CPU_V7 if !SPL_BUILD
+ imply DISTRO_DEFAULTS
+ imply FAT_WRITE
-config TARGET_VEXPRESS_AEMV8A
+config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select ARM64
+ select PL01X_SERIAL
-config TARGET_LS2085A_EMU
- bool "Support ls2085a_emu"
+config TARGET_VEXPRESS64_BASE_FVP
+ bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
+ select PL01X_SERIAL
+ select SEMIHOSTING
-config TARGET_LS2085A_SIMU
- bool "Support ls2085a_simu"
+config TARGET_VEXPRESS64_BASE_FVP_DRAM
+ bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
select ARM64
+ select PL01X_SERIAL
+ help
+ This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
+ the default config to allow the user to load the images directly into
+ DRAM using model parameters rather than by using semi-hosting to load
+ the files from the host filesystem.
-config TARGET_MESON_GX
- bool "Support meson gx-series 64bit"
+config TARGET_VEXPRESS64_JUNO
+ bool "Support Versatile Express Juno Development Platform"
select ARM64
+ select PL01X_SERIAL
-config TARGET_MESON_GXTV
- bool "Support meson gxtv-series 64bit"
+config TARGET_LS2080A_EMU
+ bool "Support ls2080a_emu"
+ select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2080A_EMU platform
+ The LS2080A Development System (EMULATOR) is a pre silicon
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_MESON_TXL
- bool "Support meson txl-series 64bit"
+config TARGET_LS2080A_SIMU
+ bool "Support ls2080a_simu"
+ select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2080A_SIMU platform
+ The LS2080A Development System (QDS) is a pre silicon
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_MESON_TXLX
- bool "Support meson txlx-series 64bit"
+config TARGET_LS1088AQDS
+ bool "Support ls1088aqds"
+ select ARCH_LS1088A
+ select ARCH_MISC_INIT
select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ help
+ Support for NXP LS1088AQDS platform
+ The LS1088A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1088A
+ Layerscape Architecture processor.
-config TARGET_MESON_AXG
- bool "Support meson axg-series 64bit"
+config TARGET_LS2080AQDS
+ bool "Support ls2080aqds"
+ select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ imply SCSI
+ imply SCSI_AHCI
+ help
+ Support for Freescale LS2080AQDS platform
+ The LS2080A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_MESON_TXHD
- bool "Support meson txhd-series 64bit"
+config TARGET_LS2080ARDB
+ bool "Support ls2080ardb"
+ select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ imply SCSI
+ imply SCSI_AHCI
+ help
+ Support for Freescale LS2080ARDB platform.
+ The LS2080A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_MESON_G12A
- bool "Support meson g12a-series 64bit"
+config TARGET_LS2081ARDB
+ bool "Support ls2081ardb"
+ select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ help
+ Support for Freescale LS2081ARDB platform.
+ The LS2081A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2081A/LS2041A
+ Layerscape Architecture processor.
-config TARGET_MESON_G12B
- bool "Support meson g12b-series 64bit"
+config TARGET_HIKEY
+ bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select OF_CONTROL
+ select PL01X_SERIAL
+ select SPECIFY_CONSOLE_INDEX
+ imply CMD_DM
+ help
+ Support for HiKey 96boards platform. It features a HI6220
+ SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
-config TARGET_MESON_TL1
- bool "Support meson tl1-series 64bit"
+config TARGET_POPLAR
+ bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
+ select DM
+ select DM_SERIAL
+ select DM_USB
+ select OF_CONTROL
+ select PL01X_SERIAL
+ imply CMD_DM
+ help
+ Support for Poplar 96boards EE platform. It features a HI3798cv200
+ SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
+ making it capable of running any commercial set-top solution based on
+ Linux or Android.
-config TARGET_MESON_TM2
- bool "Support meson tm2-series 64bit"
+config TARGET_LS1012AQDS
+ bool "Support ls1012aqds"
+ select ARCH_LS1012A
select ARM64
+ select BOARD_LATE_INIT
+ help
+ Support for Freescale LS1012AQDS platform.
+ The LS1012A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1012ARDB
+ bool "Support ls1012ardb"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ imply SCSI_AHCI
+ help
+ Support for Freescale LS1012ARDB platform.
+ The LS1012A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1012A2G5RDB
+ bool "Support ls1012a2g5rdb"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ help
+ Support for Freescale LS1012A2G5RDB platform.
+ The LS1012A 2G5 Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1012AFRWY
+ bool "Support ls1012afrwy"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ imply SCSI_AHCI
+ help
+ Support for Freescale LS1012AFRWY platform.
+ The LS1012A FRWY board (FRWY) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1012AFRDM
+ bool "Support ls1012afrdm"
+ select ARCH_LS1012A
+ select ARM64
+ help
+ Support for Freescale LS1012AFRDM platform.
+ The LS1012A Freedom board (FRDM) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1088ARDB
+ bool "Support ls1088ardb"
+ select ARCH_LS1088A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ help
+ Support for NXP LS1088ARDB platform.
+ The LS1088A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1088A
+ Layerscape Architecture processor.
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
- select CPU_V7
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select LS1_DEEP_SLEEP
select SUPPORT_SPL
+ select SYS_FSL_DDR
+ imply SCSI
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
- select CPU_V7
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select LS1_DEEP_SLEEP
select SUPPORT_SPL
+ imply SCSI
-config TARGET_BALLOON3
- bool "Support balloon3"
- select CPU_PXA
+config TARGET_LS1021AIOT
+ bool "Support ls1021aiot"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select SUPPORT_SPL
+ imply SCSI
+ help
+ Support for Freescale LS1021AIOT platform.
+ The LS1021A Freescale board (IOT) is a high-performance
+ development platform that supports the QorIQ LS1021A
+ Layerscape Architecture processor.
+
+config TARGET_LS1043AQDS
+ bool "Support ls1043aqds"
+ select ARCH_LS1043A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ imply SCSI
+ help
+ Support for Freescale LS1043AQDS platform.
+
+config TARGET_LS1043ARDB
+ bool "Support ls1043ardb"
+ select ARCH_LS1043A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ imply SCSI
+ help
+ Support for Freescale LS1043ARDB platform.
+
+config TARGET_LS1046AQDS
+ bool "Support ls1046aqds"
+ select ARCH_LS1046A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select DM_SPI_FLASH if DM_SPI
+ select SUPPORT_SPL
+ imply SCSI
+ help
+ Support for Freescale LS1046AQDS platform.
+ The LS1046A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
+config TARGET_LS1046ARDB
+ bool "Support ls1046ardb"
+ select ARCH_LS1046A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select DM_SPI_FLASH if DM_SPI
+ select POWER_MC34VR500
+ select SUPPORT_SPL
+ imply SCSI
+ help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
-config TARGET_PALMLD
- bool "Support palmld"
- select CPU_PXA
-
-config TARGET_PALMTC
- bool "Support palmtc"
- select CPU_PXA
-
-config TARGET_PALMTREO680
- bool "Support palmtreo680"
- select CPU_PXA
- select SUPPORT_SPL
-
-config TARGET_PXA255_IDP
- bool "Support pxa255_idp"
- select CPU_PXA
-
-config TARGET_TRIZEPSIV
- bool "Support trizepsiv"
- select CPU_PXA
-
-config TARGET_VPAC270
- bool "Support vpac270"
- select CPU_PXA
- select SUPPORT_SPL
-
-config TARGET_XAENIAX
- bool "Support xaeniax"
- select CPU_PXA
-
config TARGET_ZIPITZ2
bool "Support zipitz2"
select CPU_PXA
-config TARGET_LP8X4X
- bool "Support lp8x4x"
- select CPU_PXA
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
-config TARGET_JORNADA
- bool "Support jornada"
- select CPU_SA1100
-
config ARCH_UNIPHIER
- bool "Panasonic UniPhier platform"
- select CPU_V7
+ bool "Socionext UniPhier SoCs"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_RESET
+ select DM_SERIAL
+ select DM_USB
+ select OF_BOARD_SETUP
+ select OF_CONTROL
+ select OF_LIBFDT
+ select PINCTRL
+ select SPL_BOARD_INIT if SPL
+ select SPL_DM if SPL
+ select SPL_LIBCOMMON_SUPPORT if SPL
+ select SPL_LIBGENERIC_SUPPORT if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_PINCTRL if SPL
select SUPPORT_SPL
- select SPL
- select OF_CONTROL if !SPL_BUILD
+ imply CMD_DM
+ imply DISTRO_DEFAULTS
+ imply FAT_WRITE
+ help
+ Support for UniPhier SoC family developed by Socionext Inc.
+ (formerly, System LSI Business Division of Panasonic Corporation)
+
+config STM32
+ bool "Support STMicroelectronics STM32 MCU with cortex M"
+ select CPU_V7M
+ select DM
+ select DM_SERIAL
+ imply CMD_DM
+
+config ARCH_STI
+ bool "Support STMicrolectronics SoCs"
+ select BLK
+ select CPU_V7A
+ select DM
+ select DM_MMC
+ select DM_RESET
+ select DM_SERIAL
+ imply CMD_DM
+ help
+ Support for STMicroelectronics STiH407/10 SoC family.
+ This SoC is used on Linaro 96Board STiH410-B2260
+
+config ARCH_STM32MP
+ bool "Support STMicroelectronics STM32MP Socs with cortex A"
+ select ARCH_MISC_INIT
+ select BOARD_LATE_INIT
+ select CLK
+ select DM
+ select DM_GPIO
+ select DM_RESET
+ select DM_SERIAL
+ select MISC
+ select OF_CONTROL
+ select OF_LIBFDT
+ select PINCTRL
+ select REGMAP
+ select SUPPORT_SPL
+ select SYSCON
+ select SYSRESET
+ select SYS_THUMB_BUILD
+ imply CMD_DM
+ help
+ Support for STM32MP SoC family developed by STMicroelectronics,
+ MPUs based on ARM cortex A core
+ U-BOOT is running in DDR and SPL support is the unsecure First Stage
+ BootLoader (FSBL)
+
+config ARCH_ROCKCHIP
+ bool "Support Rockchip SoCs"
+ select BLK
+ select DM
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_PWM
+ select DM_REGULATOR
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select DM_USB if USB
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ select OF_CONTROL
+ select SPI
+ select SPL_DM if SPL
+ select SPL_SYS_MALLOC_SIMPLE if SPL
+ select SYS_MALLOC_F
+ select SYS_THUMB_BUILD if !ARM64
+ imply ADC
+ imply CMD_DM
+ imply DISTRO_DEFAULTS
+ imply FAT_WRITE
+ imply SARADC_ROCKCHIP
+ imply SPL_SYSRESET
+ imply SYS_NS16550
+ imply TPL_SYSRESET
+ imply USB_FUNCTION_FASTBOOT
+
+config TARGET_THUNDERX_88XX
+ bool "Support ThunderX 88xx"
+ select ARM64
+ select OF_CONTROL
+ select PL01X_SERIAL
+ select SYS_CACHE_SHIFT_7
+
+config ARCH_ASPEED
+ bool "Support Aspeed SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
endchoice
-source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
+config TI_SECURE_DEVICE
+ bool "HS Device Type Support"
+ depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS
+ help
+ If a high secure (HS) device type is being used, this config
+ must be set. This option impacts various aspects of the
+ build system (to create signed boot images that can be
+ authenticated) and the code. See the doc/README.ti-secure
+ file for further details.
-source "arch/arm/cpu/armv7/exynos/Kconfig"
+source "arch/arm/mach-aspeed/Kconfig"
-source "arch/arm/cpu/armv7/highbank/Kconfig"
+source "arch/arm/mach-at91/Kconfig"
-source "arch/arm/cpu/armv7/keystone/Kconfig"
+source "arch/arm/mach-bcm283x/Kconfig"
-source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
+source "arch/arm/mach-bcmstb/Kconfig"
-source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
+source "arch/arm/mach-davinci/Kconfig"
-source "arch/arm/cpu/armv7/omap3/Kconfig"
+source "arch/arm/mach-exynos/Kconfig"
-source "arch/arm/cpu/armv7/omap4/Kconfig"
+source "arch/arm/mach-highbank/Kconfig"
-source "arch/arm/cpu/armv7/omap5/Kconfig"
+source "arch/arm/mach-integrator/Kconfig"
-source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
+source "arch/arm/mach-k3/Kconfig"
-source "arch/arm/cpu/armv7/rmobile/Kconfig"
+source "arch/arm/mach-keystone/Kconfig"
-source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
+source "arch/arm/mach-kirkwood/Kconfig"
-source "arch/arm/cpu/armv7/tegra-common/Kconfig"
+source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig"
-source "arch/arm/cpu/armv7/uniphier/Kconfig"
+source "arch/arm/mach-mvebu/Kconfig"
-source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
+source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-source "arch/arm/cpu/armv7/zynq/Kconfig"
+source "arch/arm/mach-imx/mx2/Kconfig"
+
+source "arch/arm/mach-imx/mx3/Kconfig"
+
+source "arch/arm/mach-imx/mx5/Kconfig"
+
+source "arch/arm/mach-imx/mx6/Kconfig"
+
+source "arch/arm/mach-imx/mx7/Kconfig"
+
+source "arch/arm/mach-imx/mx7ulp/Kconfig"
+
+source "arch/arm/mach-imx/imx8/Kconfig"
+
+source "arch/arm/mach-imx/imx8m/Kconfig"
+
+source "arch/arm/mach-imx/mxs/Kconfig"
+
+source "arch/arm/mach-omap2/Kconfig"
+
+source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
+
+source "arch/arm/mach-orion5x/Kconfig"
+
+source "arch/arm/mach-owl/Kconfig"
+
+source "arch/arm/mach-rmobile/Kconfig"
+
+source "arch/arm/mach-meson/Kconfig"
+
+source "arch/arm/mach-mediatek/Kconfig"
+
+source "arch/arm/mach-qemu/Kconfig"
+
+source "arch/arm/mach-rockchip/Kconfig"
+
+source "arch/arm/mach-s5pc1xx/Kconfig"
+
+source "arch/arm/mach-snapdragon/Kconfig"
+
+source "arch/arm/mach-socfpga/Kconfig"
+
+source "arch/arm/mach-sti/Kconfig"
+
+source "arch/arm/mach-stm32/Kconfig"
+
+source "arch/arm/mach-stm32mp/Kconfig"
+
+source "arch/arm/mach-sunxi/Kconfig"
+
+source "arch/arm/mach-tegra/Kconfig"
+
+source "arch/arm/mach-uniphier/Kconfig"
+
+source "arch/arm/cpu/armv7/vf610/Kconfig"
+
+source "arch/arm/mach-zynq/Kconfig"
+
+source "arch/arm/mach-versal/Kconfig"
+
+source "arch/arm/mach-zynqmp-r5/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
-source "board/aristainetos/Kconfig"
-source "board/BuR/kwb/Kconfig"
-source "board/BuR/tseries/Kconfig"
-source "board/BuS/eb_cpux9k2/Kconfig"
-source "board/BuS/vl_ma2sc/Kconfig"
+source "arch/arm/cpu/armv8/zynqmp/Kconfig"
+
+source "arch/arm/cpu/armv8/Kconfig"
+
+source "arch/arm/mach-imx/Kconfig"
+
+source "board/bosch/shc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
-source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
-source "board/afeb9260/Kconfig"
-source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
-source "board/armltd/integrator/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
-source "board/atmel/at91rm9200ek/Kconfig"
-source "board/atmel/at91sam9260ek/Kconfig"
-source "board/atmel/at91sam9261ek/Kconfig"
-source "board/atmel/at91sam9263ek/Kconfig"
-source "board/atmel/at91sam9m10g45ek/Kconfig"
-source "board/atmel/at91sam9n12ek/Kconfig"
-source "board/atmel/at91sam9rlek/Kconfig"
-source "board/atmel/at91sam9x5ek/Kconfig"
-source "board/atmel/sama5d3_xplained/Kconfig"
-source "board/atmel/sama5d3xek/Kconfig"
-source "board/atmel/sama5d4_xplained/Kconfig"
-source "board/atmel/sama5d4ek/Kconfig"
-source "board/bachmann/ot1200/Kconfig"
-source "board/balloon3/Kconfig"
-source "board/barco/titanium/Kconfig"
-source "board/bluegiga/apx4devkit/Kconfig"
-source "board/bluewater/snapper9260/Kconfig"
-source "board/boundary/nitrogen6x/Kconfig"
+source "board/broadcom/bcm23550_w1d/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
+source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
-source "board/calao/sbc35_a9g20/Kconfig"
-source "board/calao/tny_a9260/Kconfig"
-source "board/calao/usb_a9263/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
+source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
-source "board/cm4008/Kconfig"
-source "board/cm41xx/Kconfig"
-source "board/compulab/cm_t335/Kconfig"
-source "board/compulab/cm_fx6/Kconfig"
-source "board/congatec/cgtqmx6eval/Kconfig"
-source "board/creative/xfi3/Kconfig"
-source "board/davedenx/qong/Kconfig"
-source "board/denx/m28evk/Kconfig"
-source "board/denx/m53evk/Kconfig"
-source "board/egnite/ethernut5/Kconfig"
-source "board/embest/mx6boards/Kconfig"
-source "board/esd/meesc/Kconfig"
-source "board/esd/otc570/Kconfig"
-source "board/esg/ima3-mx53/Kconfig"
-source "board/eukrea/cpu9260/Kconfig"
-source "board/eukrea/cpuat91/Kconfig"
-source "board/faraday/a320evb/Kconfig"
-source "board/freescale/ls2085a/Kconfig"
+source "board/eets/pdu001/Kconfig"
+source "board/emulation/qemu-arm/Kconfig"
+source "board/freescale/ls2080a/Kconfig"
+source "board/freescale/ls2080aqds/Kconfig"
+source "board/freescale/ls2080ardb/Kconfig"
+source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
-source "board/freescale/mx23evk/Kconfig"
-source "board/freescale/mx25pdk/Kconfig"
-source "board/freescale/mx28evk/Kconfig"
-source "board/freescale/mx31ads/Kconfig"
-source "board/freescale/mx31pdk/Kconfig"
+source "board/freescale/ls1021aiot/Kconfig"
+source "board/freescale/ls1046aqds/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
-source "board/freescale/mx51evk/Kconfig"
-source "board/freescale/mx53ard/Kconfig"
-source "board/freescale/mx53evk/Kconfig"
-source "board/freescale/mx53loco/Kconfig"
-source "board/freescale/mx53smd/Kconfig"
-source "board/freescale/mx6qarm2/Kconfig"
-source "board/freescale/mx6qsabreauto/Kconfig"
-source "board/freescale/mx6sabresd/Kconfig"
-source "board/freescale/mx6slevk/Kconfig"
-source "board/freescale/mx6sxsabresd/Kconfig"
-source "board/freescale/vf610twr/Kconfig"
-source "board/gateworks/gw_ventana/Kconfig"
-source "board/genesi/mx51_efikamx/Kconfig"
+source "board/freescale/s32v234evb/Kconfig"
+source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
-source "board/hale/tt01/Kconfig"
-source "board/icpdas/lp8x4x/Kconfig"
-source "board/imx31_phycore/Kconfig"
-source "board/isee/igep0033/Kconfig"
-source "board/jornada/Kconfig"
-source "board/karo/tx25/Kconfig"
-source "board/kosagi/novena/Kconfig"
-source "board/logicpd/imx27lite/Kconfig"
-source "board/logicpd/imx31_litekit/Kconfig"
-source "board/maxbcm/Kconfig"
-source "board/mpl/vcma9/Kconfig"
-source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/palmld/Kconfig"
-source "board/palmtc/Kconfig"
-source "board/palmtreo680/Kconfig"
+source "board/hisilicon/hikey/Kconfig"
+source "board/hisilicon/poplar/Kconfig"
+source "board/isee/igep003x/Kconfig"
source "board/phytec/pcm051/Kconfig"
-source "board/ppcag/bg0900/Kconfig"
-source "board/pxa255_idp/Kconfig"
-source "board/raspberrypi/rpi/Kconfig"
-source "board/ronetix/pm9261/Kconfig"
-source "board/ronetix/pm9263/Kconfig"
-source "board/ronetix/pm9g45/Kconfig"
-source "board/samsung/smdk2410/Kconfig"
-source "board/sandisk/sansa_fuze_plus/Kconfig"
-source "board/scb9328/Kconfig"
-source "board/schulercontrol/sc_sps_1/Kconfig"
-source "board/siemens/corvus/Kconfig"
-source "board/siemens/draco/Kconfig"
-source "board/siemens/pxm2/Kconfig"
-source "board/siemens/rut/Kconfig"
-source "board/siemens/taurus/Kconfig"
source "board/silica/pengwyn/Kconfig"
-source "board/solidrun/hummingboard/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
-source "board/st-ericsson/snowball/Kconfig"
-source "board/st-ericsson/u8500/Kconfig"
source "board/st/stv0991/Kconfig"
-source "board/sunxi/Kconfig"
-source "board/syteco/jadecpu/Kconfig"
-source "board/syteco/zmx25/Kconfig"
-source "board/taskit/stamp9g20/Kconfig"
-source "board/tbs/tbs2910/Kconfig"
-source "board/ti/am335x/Kconfig"
-source "board/ti/am43xx/Kconfig"
-source "board/ti/ti814x/Kconfig"
-source "board/ti/ti816x/Kconfig"
-source "board/ti/tnetv107xevm/Kconfig"
-source "board/timll/devkit3250/Kconfig"
+source "board/tcl/sl50/Kconfig"
+source "board/ucRobotics/bubblegum_96/Kconfig"
+source "board/birdland/bav335x/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
-source "board/tqc/tqma6/Kconfig"
-source "board/trizepsiv/Kconfig"
-source "board/ttcontrol/vision2/Kconfig"
-source "board/udoo/Kconfig"
-source "board/vpac270/Kconfig"
-source "board/wandboard/Kconfig"
+source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
-source "board/xaeniax/Kconfig"
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynq/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
-source "board/amlogic/Kconfig"
-source "customer/board/Kconfig"
-
source "arch/arm/Kconfig.debug"
endmenu
+
+config SPL_LDSCRIPT
+ default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
+ default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
+ default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
+
+
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ebb7dc3..87d9d4b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -1,6 +1,94 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
+# SPDX-License-Identifier: GPL-2.0+
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+CONFIG_CPU_V7A=
+CONFIG_CPU_ARM720T=y
+endif
+
+# This selects which instruction set is used.
+arch-$(CONFIG_CPU_ARM720T) =-march=armv4
+arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
+arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
+arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
+arch-$(CONFIG_CPU_SA1100) =-march=armv4
+arch-$(CONFIG_CPU_PXA) =
+arch-$(CONFIG_CPU_ARM1136) =-march=armv5
+arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
+arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
+ $(call cc-option, -march=armv7))
+arch-$(CONFIG_CPU_V7M) =-march=armv7-m
+arch-$(CONFIG_CPU_V7R) =-march=armv7-r
+arch-$(CONFIG_ARM64) =-march=armv8-a
+
+# On Tegra systems we must build SPL for the armv4 core on the device
+# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+arch-y += -D__LINUX_ARM_ARCH__=4
+else
+arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
+# Evaluate arch cc-option calls now
+arch-y := $(arch-y)
+
+# This selects how we optimise for the processor.
+tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM920T) =
+tune-$(CONFIG_CPU_ARM926EJS) =
+tune-$(CONFIG_CPU_ARM946ES) =
+tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
+tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
+tune-$(CONFIG_CPU_ARM1136) =
+tune-$(CONFIG_CPU_ARM1176) =
+tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a
+tune-$(CONFIG_CPU_V7R) =
+tune-$(CONFIG_ARM64) =
+
+# Evaluate tune cc-option calls now
+tune-y := $(tune-y)
+
+PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
+
+# Machine directory name. This list is sorted alphanumerically
+# by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ASPEED) += aspeed
+machine-$(CONFIG_ARCH_AT91) += at91
+machine-$(CONFIG_ARCH_BCM283X) += bcm283x
+machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
+machine-$(CONFIG_ARCH_DAVINCI) += davinci
+machine-$(CONFIG_ARCH_EXYNOS) += exynos
+machine-$(CONFIG_ARCH_HIGHBANK) += highbank
+machine-$(CONFIG_ARCH_K3) += k3
+machine-$(CONFIG_ARCH_KEYSTONE) += keystone
+# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
+machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
+machine-$(CONFIG_ARCH_MESON) += meson
+machine-$(CONFIG_ARCH_MVEBU) += mvebu
+# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
+# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
+machine-$(CONFIG_ORION5X) += orion5x
+machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
+machine-$(CONFIG_ARCH_OWL) += owl
+machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
+machine-$(CONFIG_ARCH_SUNXI) += sunxi
+machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
+machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
+machine-$(CONFIG_ARCH_RMOBILE) += rmobile
+machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
+machine-$(CONFIG_STM32) += stm32
+machine-$(CONFIG_ARCH_STM32MP) += stm32mp
+machine-$(CONFIG_TEGRA) += tegra
+machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
+machine-$(CONFIG_ARCH_ZYNQ) += zynq
+machine-$(CONFIG_ARCH_VERSAL) += versal
+machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
+
+machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
+
+PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+
+libs-y += $(machdirs)
head-y := arch/arm/cpu/$(CPU)/start.o
@@ -15,15 +103,18 @@
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-libs-y += arch/arm/imx-common/
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
+libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-libs-y += arch/arm/imx-common/
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+libs-y += arch/arm/mach-imx/
endif
endif
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
-libs-y += arch/arm/mvebu-common/
+ifneq (,$(filter $(SOC), kirkwood))
+libs-y += arch/arm/mach-mvebu/
endif
+
+# deprecated
+-include $(machdirs)/config.mk
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 0667984..f256031 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -1,31 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_OMAP_COMMON),)
+ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
+CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
+CFLAGS_EFI := -fpic -fshort-wchar
+
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-# Support generic board on ARM
-__HAVE_ARCH_GENERIC_BOARD := y
+# LLVM support
+LLVM_RELFLAGS := $(call cc-option,-mllvm,) \
+ $(call cc-option,-mno-movt,)
+PLATFORM_RELFLAGS += $(LLVM_RELFLAGS)
PLATFORM_CPPFLAGS += -D__ARM__
+ifdef CONFIG_ARM64
+PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64
+else
+PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm
+endif
+
# Choose between ARM/Thumb instruction sets
-ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always)
PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \
$(call cc-option, -mthumb -mthumb-interwork,\
@@ -38,19 +47,28 @@
endif
# Only test once
-ifneq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
-archprepare: checkthumb
+ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
+archprepare: checkthumb checkgcc6
checkthumb:
- @if test "$(call cc-version)" -lt "0404"; then \
+ @if test "$(call cc-name)" = "gcc" -a \
+ "$(call cc-version)" -lt "0404"; then \
echo -n '*** Your GCC does not produce working '; \
echo 'binaries in THUMB mode.'; \
echo '*** Your board is configured for THUMB mode.'; \
false; \
fi
+else
+archprepare: checkgcc6
endif
-endif
+
+checkgcc6:
+ @if test "$(call cc-name)" = "gcc" -a \
+ "$(call cc-version)" -lt "0600"; then \
+ echo '*** Your GCC is older than 6.0 and is not supported'; \
+ false; \
+ fi
+
# Try if EABI is supported, else fall back to old API,
# i. e. for example:
@@ -92,7 +110,7 @@
#
# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
#
-ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
ifeq ($(GAS_BUG_12532),)
export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
then echo y; else echo n; fi)
@@ -109,17 +127,28 @@
# instruction. Relocation is not supported for that case, so disable
# such usage by requiring word relocations.
PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
+PLATFORM_CPPFLAGS += $(call cc-option, -fno-pic)
endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+ -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+ -j .binman_sym_table -j .text_rest
else
-OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
+ -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+ -j .binman_sym_table -j .text_rest
endif
-ifdef CONFIG_OF_EMBED
+# if a dtb section exists we always have to include it
+# there are only two cases where it is generated
+# 1) OF_EMBEDED is turned on
+# 2) unit tests include device tree blobs
OBJCOPYFLAGS += -j .dtb.init.rodata
+
+ifdef CONFIG_EFI_LOADER
+OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
endif
ifneq ($(CONFIG_IMX_CONFIG),)
@@ -134,4 +163,11 @@
ALL-y += u-boot.imx
endif
endif
+ifneq ($(CONFIG_VF610),)
+ALL-y += u-boot.vyb
endif
+endif
+
+EFI_LDS := elf_arm_efi.lds
+EFI_CRT0 := crt0_arm_efi.o
+EFI_RELOC := reloc_arm_efi.o
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 35d8d38..a0e1c2a 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,6 +1,3 @@
-obj-$(CONFIG_AT91FAMILY) += at91-common/
-obj-$(CONFIG_TEGRA20) += tegra20-common/
-obj-$(CONFIG_TEGRA30) += tegra30-common/
-obj-$(CONFIG_TEGRA114) += tegra114-common/
-obj-$(CONFIG_TEGRA124) += tegra124-common/
-obj-$(CONFIG_TEGRA) += tegra-common/
+# SPDX-License-Identifier: GPL-2.0+
+
+obj- += dummy.o
diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile
new file mode 100644
index 0000000..5d721fc
--- /dev/null
+++ b/arch/arm/cpu/arm11/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y = cpu.o
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
new file mode 100644
index 0000000..41feeef
--- /dev/null
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ */
+
+ disable_interrupts ();
+
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+ /* flush I/D-cache */
+ cache_flush();
+
+ return 0;
+}
+
+static void cache_flush(void)
+{
+ unsigned long i = 0;
+ /* clean entire data cache */
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+ /* invalidate both caches and flush btb */
+ asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+ /* mem barrier to sync things */
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void invalidate_dcache_all(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (!check_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (!check_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 56a9390..24c3386 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -1,12 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-y = start.o
-obj-y = cpu.o
+obj-y += ../arm11/
obj-$(CONFIG_MX31) += mx31/
obj-$(CONFIG_MX35) += mx35/
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
deleted file mode 100644
index a82c6ce..0000000
--- a/arch/arm/cpu/arm1136/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
deleted file mode 100644
index a7aed4b..0000000
--- a/arch/arm/cpu/arm1136/cpu.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- */
-
- disable_interrupts ();
-
-#ifdef CONFIG_LCD
- {
- extern void lcd_disable(void);
- extern void lcd_panel_disable(void);
-
- lcd_disable(); /* proper disable of lcd & panel */
- lcd_panel_disable();
- }
-#endif
-
- /* turn off I/D-cache */
- icache_disable();
- dcache_disable();
- /* flush I/D-cache */
- cache_flush();
-
- return 0;
-}
-
-static void cache_flush(void)
-{
- unsigned long i = 0;
- /* clean entire data cache */
- asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
- /* invalidate both caches and flush btb */
- asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
- /* mem barrier to sync things */
- asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
-void invalidate_dcache_all(void)
-{
- asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
-}
-
-void flush_dcache_all(void)
-{
- asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
- asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-}
-
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
- int ok = 1;
-
- if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
- ok = 0;
-
- if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
- ok = 0;
-
- if (!ok)
- debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
- start, stop);
-
- return ok;
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
- if (!check_cache_range(start, stop))
- return;
-
- while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
- start += CONFIG_SYS_CACHELINE_SIZE;
- }
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
- if (!check_cache_range(start, stop))
- return;
-
- while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
- start += CONFIG_SYS_CACHELINE_SIZE;
- }
-
- asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
-
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
-void invalidate_dcache_all(void)
-{
-}
-
-void flush_dcache_all(void)
-{
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
-
-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
index 9670ed9..67799ee 100644
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
@@ -1,10 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += generic.o
obj-y += timer.o
obj-y += devices.o
+obj-y += relocate.o
diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c
index ae5db86..9997e8f 100644
--- a/arch/arm/cpu/arm1136/mx31/devices.c
+++ b/arch/arm/cpu/arm1136/mx31/devices.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 060d46b..3f6af6f 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -175,7 +174,7 @@
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev)
- return mx31_cpu_type[i].v;
+ return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12);
return srev | 0x8000;
}
diff --git a/arch/arm/cpu/arm1136/mx31/relocate.S b/arch/arm/cpu/arm1136/mx31/relocate.S
new file mode 100644
index 0000000..225e528
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx31/relocate.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * relocate - i.MX31-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX31 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c
index 3a81ce4..3d07ee6 100644
--- a/arch/arm/cpu/arm1136/mx31/timer.c
+++ b/arch/arm/cpu/arm1136/mx31/timer.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -23,8 +22,6 @@
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-DECLARE_GLOBAL_DATA_PTR;
-
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index c533215..36568f9 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -1,12 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
+obj-y += relocate.o
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index bc98edd..cbc4364 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -1,16 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
@@ -524,24 +523,3 @@
return BOOT_DEVICE_NONE;
}
-
-#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_mode(void)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
-#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
- break;
- case BOOT_DEVICE_NAND:
- return 0;
- break;
- default:
- puts("spl: ERROR: unsupported device\n");
- hang();
- }
-}
-#endif
diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
index d358f5f..f120e84 100644
--- a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
+++ b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <linux/types.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/cpu/arm1136/mx35/relocate.S b/arch/arm/cpu/arm1136/mx35/relocate.S
new file mode 100644
index 0000000..e41e5a5
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx35/relocate.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * relocate - i.MX35-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX35 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c
index 4edf533..c1cdf35 100644
--- a/arch/arm/cpu/arm1136/mx35/timer.c
+++ b/arch/arm/cpu/arm1136/mx35/timer.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -12,8 +11,6 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 1cfcca9..da7278e 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for OMP2420/ARM1136 CPU-core
*
@@ -8,13 +9,10 @@
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
/*
*************************************************************************
@@ -79,10 +77,11 @@
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00000002 @ set bit 1 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
@@ -90,5 +89,6 @@
mov ip, lr /* persevere link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds
index 97e4a8b..881275a 100644
--- a/arch/arm/cpu/arm1136/u-boot-spl.lds
+++ b/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
@@ -5,8 +6,6 @@
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index ead2303..3233247 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -1,15 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
+obj- += dummy.o
extra-y = start.o
-obj-y = cpu.o
-obj-$(CONFIG_BCM2835) += bcm2835/
-obj-$(CONFIG_TNETV107X) += tnetv107x/
+obj-y += ../arm11/
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile
deleted file mode 100644
index 0ad3690..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-obj-y := lowlevel_init.o
-obj-y += init.o reset.o timer.o mbox.o
diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/cpu/arm1176/bcm2835/init.c
deleted file mode 100644
index e90d3bb..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/init.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-
-int arch_cpu_init(void)
-{
- icache_enable();
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S
deleted file mode 100644
index c7b0843..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-.globl lowlevel_init
-lowlevel_init:
- mov pc, lr
diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c
deleted file mode 100644
index 3b17a31..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/mbox.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mbox.h>
-
-#define TIMEOUT 1000 /* ms */
-
-int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
-{
- struct bcm2835_mbox_regs *regs =
- (struct bcm2835_mbox_regs *)BCM2835_MBOX_PHYSADDR;
- ulong endtime = get_timer(0) + TIMEOUT;
- u32 val;
-
- debug("time: %lu timeout: %lu\n", get_timer(0), endtime);
-
- if (send & BCM2835_CHAN_MASK) {
- printf("mbox: Illegal mbox data 0x%08x\n", send);
- return -1;
- }
-
- /* Drain any stale responses */
-
- for (;;) {
- val = readl(®s->status);
- if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
- break;
- if (get_timer(0) >= endtime) {
- printf("mbox: Timeout draining stale responses\n");
- return -1;
- }
- val = readl(®s->read);
- }
-
- /* Wait for space to send */
-
- for (;;) {
- val = readl(®s->status);
- if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
- break;
- if (get_timer(0) >= endtime) {
- printf("mbox: Timeout waiting for send space\n");
- return -1;
- }
- }
-
- /* Send the request */
-
- val = BCM2835_MBOX_PACK(chan, send);
- debug("mbox: TX raw: 0x%08x\n", val);
- writel(val, ®s->write);
-
- /* Wait for the response */
-
- for (;;) {
- val = readl(®s->status);
- if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
- break;
- if (get_timer(0) >= endtime) {
- printf("mbox: Timeout waiting for response\n");
- return -1;
- }
- }
-
- /* Read the response */
-
- val = readl(®s->read);
- debug("mbox: RX raw: 0x%08x\n", val);
-
- /* Validate the response */
-
- if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) {
- printf("mbox: Response channel mismatch\n");
- return -1;
- }
-
- *recv = BCM2835_MBOX_UNPACK_DATA(val);
-
- return 0;
-}
-
-#ifdef DEBUG
-void dump_buf(struct bcm2835_mbox_hdr *buffer)
-{
- u32 *p;
- u32 words;
- int i;
-
- p = (u32 *)buffer;
- words = buffer->buf_size / 4;
- for (i = 0; i < words; i++)
- printf(" 0x%04x: 0x%08x\n", i * 4, p[i]);
-}
-#endif
-
-int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
-{
- int ret;
- u32 rbuffer;
- struct bcm2835_mbox_tag_hdr *tag;
- int tag_index;
-
-#ifdef DEBUG
- printf("mbox: TX buffer\n");
- dump_buf(buffer);
-#endif
-
- ret = bcm2835_mbox_call_raw(chan, (u32)buffer, &rbuffer);
- if (ret)
- return ret;
- if (rbuffer != (u32)buffer) {
- printf("mbox: Response buffer mismatch\n");
- return -1;
- }
-
-#ifdef DEBUG
- printf("mbox: RX buffer\n");
- dump_buf(buffer);
-#endif
-
- /* Validate overall response status */
-
- if (buffer->code != BCM2835_MBOX_RESP_CODE_SUCCESS) {
- printf("mbox: Header response code invalid\n");
- return -1;
- }
-
- /* Validate each tag's response status */
-
- tag = (void *)(buffer + 1);
- tag_index = 0;
- while (tag->tag) {
- if (!(tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)) {
- printf("mbox: Tag %d missing val_len response bit\n",
- tag_index);
- return -1;
- }
- /*
- * Clear the reponse bit so clients can just look right at the
- * length field without extra processing
- */
- tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE;
- tag = (void *)(((u8 *)tag) + sizeof(*tag) + tag->val_buf_size);
- tag_index++;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/cpu/arm1176/bcm2835/reset.c
deleted file mode 100644
index 8c37ad9..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/reset.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/wdog.h>
-
-#define RESET_TIMEOUT 10
-
-void reset_cpu(ulong addr)
-{
- struct bcm2835_wdog_regs *regs =
- (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
- uint32_t rstc;
-
- rstc = readl(®s->rstc);
- rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
- rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
-
- writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, ®s->wdog);
- writel(BCM2835_WDOG_PASSWORD | rstc, ®s->rstc);
-}
diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c
deleted file mode 100644
index 017907c..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/timer.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer.h>
-
-ulong get_timer_us(ulong base)
-{
- struct bcm2835_timer_regs *regs =
- (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
-
- return readl(®s->clo) - base;
-}
-
-ulong get_timer(ulong base)
-{
- ulong us = get_timer_us(0);
- us /= (1000000 / CONFIG_SYS_HZ);
- us -= base;
- return us;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
-
-void __udelay(unsigned long usec)
-{
- ulong endtime;
- signed long diff;
-
- endtime = get_timer_us(0) + usec;
-
- do {
- ulong now = get_timer_us(0);
- diff = endtime - now;
- } while (diff >= 0);
-}
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
deleted file mode 100644
index 5dc2ebb..0000000
--- a/arch/arm/cpu/arm1176/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
deleted file mode 100644
index 2d81651..0000000
--- a/arch/arm/cpu/arm1176/cpu.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush (void);
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- */
-
- disable_interrupts ();
-
- /* turn off I/D-cache */
- icache_disable();
- dcache_disable();
- /* flush I/D-cache */
- cache_flush();
-
- return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- /* invalidate both caches and flush btb */
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
- /* mem barrier to sync things */
- asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
-}
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 0704bdd..1402924 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM1176 CPU-core
*
@@ -6,8 +7,6 @@
* Copyright (C) 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
* 2007-09-21 - Added MoviNAND and OneNAND boot codes by
* jsgood (jsgood.yang@samsung.com)
@@ -16,7 +15,7 @@
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
+#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
@@ -38,6 +37,11 @@
.globl reset
reset:
+ /* Allow the board to save important registers */
+ b save_boot_params
+.globl save_boot_params_ret
+save_boot_params_ret:
+
/*
* set the cpu to SVC32 mode
*/
@@ -79,7 +83,7 @@
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00000002 @ set bit 1 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
/* Prepare to disable the MMU */
@@ -96,28 +100,6 @@
mov pc, r2
mmu_disable_phys:
-#ifdef CONFIG_DISABLE_TCM
- /*
- * Disable the TCMs
- */
- mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
- cmp r0, #0
- beq skip_tcmdisable
- mov r1, #0
- mov r2, #1
- tst r0, r2
- mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
- tst r0, r2, LSL #16
- mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
- /* Peri port setup */
- ldr r0, =CONFIG_PERIPORT_BASE
- orr r0, r0, #CONFIG_PERIPORT_SIZE
- mcr p15,0,r0,c15,c2,4
#endif
/*
@@ -133,3 +115,7 @@
c_runtime_cpu_setup:
mov pc, lr
+
+WEAK(save_boot_params)
+ b save_boot_params_ret /* back to my caller */
+ENDPROC(save_boot_params)
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
deleted file mode 100644
index a4c1edf..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += aemif.o clock.o init.o mux.o timer.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
deleted file mode 100644
index a0f5728..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define NUM_CS 4
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~CONFIG_##field(0xffffffff); \
- reg |= CONFIG_##field(val); \
- } \
- } while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
- unsigned long tmp;
-
- if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
- tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
- } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
- tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
- }
-
- tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
- int cs;
-
- clk_enable(TNETV107X_LPSC_AEMIF);
-
- for (cs = 0; cs < num_cs; cs++)
- configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
deleted file mode 100644
index 7ba28d3..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE TNETV107X_PSC_BASE
-
-#define BIT(x) (1 << (x))
-
-#define MAX_PREDIV 64
-#define MAX_POSTDIV 8UL
-#define MAX_MULT 512
-#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD 0x120
-#define PSC_PTSTAT 0x128
-#define PSC_MDSTAT(n) (0x800 + (n) * 4)
-#define PSC_MDCTL(n) (0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ BIT(8)
-
-#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
- u32 modes;
- u32 postdiv;
- u32 prediv;
- u32 mult_factor;
- u32 divider_range;
- u32 bw_divider;
- u32 spr_amount;
- u32 spr_rate_div;
- u32 diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
- (struct sspll_regs *)(CLOCK_BASE + 0x040),
- (struct sspll_regs *)(CLOCK_BASE + 0x080),
- (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
- u32 ctl; /* 00 */
- u32 ocsel; /* 04 */
- u32 secctl; /* 08 */
- u32 __pad0;
- u32 mult; /* 10 */
- u32 prediv; /* 14 */
- u32 div1; /* 18 */
- u32 div2; /* 1c */
- u32 div3; /* 20 */
- u32 oscdiv1; /* 24 */
- u32 postdiv; /* 28 */
- u32 bpdiv; /* 2c */
- u32 wakeup; /* 30 */
- u32 __pad1;
- u32 cmd; /* 38 */
- u32 stat; /* 3c */
- u32 alnctl; /* 40 */
- u32 dchange; /* 44 */
- u32 cken; /* 48 */
- u32 ckstat; /* 4c */
- u32 systat; /* 50 */
- u32 ckctl; /* 54 */
- u32 __pad2[2];
- u32 div4; /* 60 */
- u32 div5; /* 64 */
- u32 div6; /* 68 */
- u32 div7; /* 6c */
- u32 div8; /* 70 */
-};
-
-struct lpsc_map {
- int pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x700),
- (struct pllctl_regs *)(CLOCK_BASE + 0x300),
- (struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val) \
- pllctl_reg_write(pll, reg, \
- (pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE BIT(8)
-#define PLLCTL_PLLSELB BIT(7)
-#define PLLCTL_PLLENSRC BIT(5)
-#define PLLCTL_PLLDIS BIT(4)
-#define PLLCTL_PLLRST BIT(3)
-#define PLLCTL_PLLPWRDN BIT(1)
-#define PLLCTL_PLLEN BIT(0)
-
-#define PLLDIV_ENABLE BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg) offsetof(struct pllctl_regs, reg)
- div_offset(div1), div_offset(div2), div_offset(div3),
- div_offset(div4), div_offset(div5), div_offset(div6),
- div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk {SYS_PLL, 0}
-#define sys_dsp_clk {SYS_PLL, 1}
-#define sys_ddr_clk {SYS_PLL, 2}
-#define sys_full_clk {SYS_PLL, 3}
-#define sys_lcd_clk {SYS_PLL, 4}
-#define sys_vlynq_ref_clk {SYS_PLL, 5}
-#define sys_tsc_clk {SYS_PLL, 6}
-#define sys_half_clk {SYS_PLL, 7}
-
-#define eth_clk_5 {ETH_PLL, 0}
-#define eth_clk_50 {ETH_PLL, 1}
-#define eth_clk_125 {ETH_PLL, 2}
-#define eth_clk_250 {ETH_PLL, 3}
-#define eth_clk_25 {ETH_PLL, 4}
-
-#define tdm_clk {TDM_PLL, 0}
-#define tdm_extra_clk {TDM_PLL, 1}
-#define tdm1_clk {TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
- [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
- [TNETV107X_LPSC_GEM] = sys_dsp_clk,
- [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
- [TNETV107X_LPSC_TPCC] = sys_full_clk,
- [TNETV107X_LPSC_TPTC0] = sys_full_clk,
- [TNETV107X_LPSC_TPTC1] = sys_full_clk,
- [TNETV107X_LPSC_RAM] = sys_full_clk,
- [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
- [TNETV107X_LPSC_LCD] = sys_lcd_clk,
- [TNETV107X_LPSC_ETHSS] = eth_clk_125,
- [TNETV107X_LPSC_AEMIF] = sys_full_clk,
- [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
- [TNETV107X_LPSC_TSC] = sys_tsc_clk,
- [TNETV107X_LPSC_ROM] = sys_half_clk,
- [TNETV107X_LPSC_UART2] = sys_half_clk,
- [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
- [TNETV107X_LPSC_SECCTL] = sys_half_clk,
- [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
- [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
- [TNETV107X_LPSC_GPIO] = sys_half_clk,
- [TNETV107X_LPSC_MDIO] = sys_half_clk,
- [TNETV107X_LPSC_SDIO0] = sys_half_clk,
- [TNETV107X_LPSC_UART0] = sys_half_clk,
- [TNETV107X_LPSC_UART1] = sys_half_clk,
- [TNETV107X_LPSC_TIMER0] = sys_half_clk,
- [TNETV107X_LPSC_TIMER1] = sys_half_clk,
- [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
- [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
- [TNETV107X_LPSC_SSP] = sys_half_clk,
- [TNETV107X_LPSC_TDM0] = tdm_clk,
- [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
- [TNETV107X_LPSC_MCDMA] = sys_half_clk,
- [TNETV107X_LPSC_USB0] = sys_half_clk,
- [TNETV107X_LPSC_TDM1] = tdm1_clk,
- [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
- [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
- [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
- [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
- [TNETV107X_LPSC_SPARE] = sys_half_clk,
- [TNETV107X_LPSC_SDIO1] = sys_half_clk,
- [TNETV107X_LPSC_USB1] = sys_half_clk,
- [TNETV107X_LPSC_USBSS] = sys_half_clk,
- [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
- [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
- [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
- [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
- [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, postdiv = 1;
- unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
- unsigned long ret;
- u32 bypass;
-
- bypass = __raw_readl((u32 *)(CLOCK_BASE));
- if (!(bypass & pll_bypass_mask[pll])) {
- mult = sspll_reg_read(pll, mult_factor);
- prediv = sspll_reg_read(pll, prediv) + 1;
- postdiv = sspll_reg_read(pll, postdiv) + 1;
- }
-
- if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
- ref = pll_ext_freq[pll];
-
- if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
- return ref;
-
- ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
- ret /= (prediv * postdiv);
-
- return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
- int div)
-{
- int divider = 1;
- unsigned long divreg;
-
- divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
- if (divreg & PLLDIV_ENABLE)
- divider = (divreg & pll_div_mask[pll]) + 1;
-
- return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
- unsigned long hz)
-{
- int divider = (fpll / hz - 1);
-
- divider &= pll_div_mask[pll];
- divider |= PLLDIV_ENABLE;
-
- __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
- pllctl_reg_setbits(pll, alnctl, (1 << div));
- pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- __pll_div_freq_set(pll, fpll, div, hz);
-
- pllctl_reg_write(pll, cmd, 1);
-
- /* Wait until new divider takes effect */
- while (pllctl_reg_read(pll, stat) & 0x01);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
- unsigned long fpll, divider, pll;
-
- pll = lpsc_clk_map[clk].pll;
- fpll = pll_freq_get(pll);
- divider = (fpll / hz - 1);
- divider &= pll_div_mask[pll];
-
- return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
- unsigned long hz;
-
- hz = clk_round_rate(clk, _hz);
- if (hz != _hz)
- return -EINVAL; /* Cannot set to target freq */
-
- pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
- return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
- u32 mdctl;
-
- mdctl = psc_reg_read(PSC_MDCTL(mod));
- mdctl &= ~0x1f;
- mdctl |= state;
-
- if (lrstz == 0)
- mdctl &= ~PSC_MDCTL_LRSTZ;
- else if (lrstz == 1)
- mdctl |= PSC_MDCTL_LRSTZ;
-
- psc_reg_write(PSC_MDCTL(mod), mdctl);
-
- psc_reg_write(PSC_PTCMD, 1);
-
- /* wait for power domain transition to end */
- while (psc_reg_read(PSC_PTSTAT) & 1);
-
- /* Wait for module state change */
- while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
- return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
- unsigned long fpll;
- unsigned long best_pre = 0, best_post = 0, best_mult = 0;
- unsigned long div, prediv, postdiv, mult;
- unsigned long delta, actual;
- long best_delta = -1;
- int i;
- u32 tmp;
-
- if (data->pll == SYS_PLL)
- return; /* cannot reconfigure system pll on the fly */
-
- tmp = pllctl_reg_read(data->pll, ctl);
- if (data->internal_osc) {
- tmp &= ~PLLCTL_CLKMODE;
- fpll = CONFIG_SYS_INT_OSC_FREQ;
- } else {
- tmp |= PLLCTL_CLKMODE;
- fpll = pll_ext_freq[data->pll];
- }
- pllctl_reg_write(data->pll, ctl, tmp);
-
- mult = data->pll_freq / fpll;
- for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
- div = (fpll * mult) / data->pll_freq;
- if (div < 1 || div > MAX_DIV)
- continue;
-
- for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
- prediv = div / postdiv;
- if (prediv < 1 || prediv > MAX_PREDIV)
- continue;
-
- actual = (fpll / prediv) * (mult / postdiv);
- delta = (actual - data->pll_freq);
- if (delta < 0)
- delta = -delta;
- if ((delta < best_delta) || (best_delta == -1)) {
- best_delta = delta;
- best_mult = mult;
- best_pre = prediv;
- best_post = postdiv;
- if (delta == 0)
- goto done;
- }
- }
- }
-done:
-
- if (best_delta == -1) {
- printf("pll cannot derive %lu from %lu\n",
- data->pll_freq, fpll);
- return;
- }
-
- fpll = fpll * best_mult;
- fpll /= best_pre * best_post;
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
- sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
- sspll_reg_write(data->pll, prediv, best_pre - 1);
- sspll_reg_write(data->pll, postdiv, best_post - 1);
-
- for (i = 0; i < 10; i++)
- if (data->div_freq[i])
- __pll_div_freq_set(data->pll, fpll, i,
- data->div_freq[i]);
-
- pllctl_reg_write(data->pll, cmd, 1);
-
- /* Wait until pll "go" operation completes */
- while (pllctl_reg_read(data->pll, stat) & 0x01);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
deleted file mode 100644
index d870826..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
- __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
- icache_enable();
- chip_configuration_unlock();
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
deleted file mode 100644
index a8bce47..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
- /* nothing for now, maybe needed for more exotic boot modes */
- mov pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
deleted file mode 100644
index 310d84d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1 0x00
-#define MUX_MODE_2 0x04
-#define MUX_MODE_3 0x0c
-#define MUX_MODE_4 0x1c
-
-#define MUX_DEBUG 0
-
-static const struct pin_config pin_table[] = {
- /* reg shift mode */
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
- const struct pin_config *cfg;
- unsigned long mask, mode, reg;
-
- if (index >= pin_table_size)
- return 0;
-
- cfg = &pin_table[index];
-
- mask = 0x1f << cfg->mask_offset;
- mode = cfg->mode << cfg->mask_offset;
-
- reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
- reg = (reg & ~mask) | mode;
- __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
- return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
- int i, ret = 1;
-
- for (i = 0; pins[i] >= 0; i++)
- ret &= mux_select_pin(pins[i]);
-
- return ret;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
deleted file mode 100644
index 6e0dd0d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
- u_int32_t pid12;
- u_int32_t pad[3];
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
- clk_enable(TNETV107X_LPSC_TIMER0);
-
- lastinc = timestamp = 0;
-
- /* We are using timer34 in unchained 32-bit mode, full speed */
- __raw_writel(0x0, ®s->tcr);
- __raw_writel(0x0, ®s->tgcr);
- __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), ®s->tgcr);
- __raw_writel(0x0, ®s->tim34);
- __raw_writel(TIMER_LOAD_VAL, ®s->prd34);
- __raw_writel(2 << 22, ®s->tcr);
-
- return 0;
-}
-
-static ulong get_timer_raw(void)
-{
- ulong now = __raw_readl(®s->tim34);
-
- if (now >= lastinc)
- timestamp += now - lastinc;
- else
- timestamp += now + TIMER_LOAD_VAL - lastinc;
-
- lastinc = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
-
- endtime = get_timer_raw() + tmo;
-
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile
index 9f61ea2..e70b590 100644
--- a/arch/arm/cpu/arm720t/Makefile
+++ b/arch/arm/cpu/arm720t/Makefile
@@ -1,15 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-y = start.o
obj-y = interrupts.o cpu.o
-
-obj-$(CONFIG_TEGRA) += tegra-common/
-obj-$(CONFIG_TEGRA20) += tegra20/
-obj-$(CONFIG_TEGRA30) += tegra30/
-obj-$(CONFIG_TEGRA114) += tegra114/
-obj-$(CONFIG_TEGRA124) += tegra124/
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
deleted file mode 100644
index 772fb41..0000000
--- a/arch/arm/cpu/arm720t/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
index 745fccd..ece09c8 100644
--- a/arch/arm/cpu/arm720t/cpu.c
+++ b/arch/arm/cpu/arm720t/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -6,8 +7,6 @@
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
index e8ba1ae..8437717 100644
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -6,18 +7,10 @@
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#ifdef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
-{
-}
-#endif
-
#if defined(CONFIG_TEGRA)
static ulong timestamp;
static ulong lastdec;
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 01c85be..ecb4e44 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -1,16 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM720 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
-#include <asm/hardware.h>
/*
*************************************************************************
@@ -40,7 +37,8 @@
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
@@ -64,7 +62,8 @@
*************************************************************************
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
deleted file mode 100644
index a9c2b67..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
deleted file mode 100644
index c6f3b02..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include "cpu.h"
-
-int get_num_cpus(void)
-{
- struct apb_misc_gp_ctlr *gp;
- uint rev;
-
- gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
- rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
- switch (rev) {
- case CHIPID_TEGRA20:
- return 2;
- break;
- case CHIPID_TEGRA30:
- case CHIPID_TEGRA114:
- default:
- return 4;
- break;
- }
-}
-
-/*
- * Timing tables for each SOC for all four oscillator options.
- */
-struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
- /*
- * T20: 1 GHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 22:20 3
- * PLLX_BASE n 17: 8 10
- * PLLX_BASE m 4: 0 5
- * PLLX_MISC cpcon 11: 8 4
- */
- {
- { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
- { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
- { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
- { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- },
- /*
- * T25: 1.2 GHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 22:20 3
- * PLLX_BASE n 17: 8 10
- * PLLX_BASE m 4: 0 5
- * PLLX_MISC cpcon 11: 8 4
- */
- {
- { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
- { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
- { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
- { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- },
- /*
- * T30: 600 MHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 22:20 3
- * PLLX_BASE n 17: 8 10
- * PLLX_BASE m 4: 0 5
- * PLLX_MISC cpcon 11: 8 4
- */
- {
- { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
- { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
- { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
- { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
- },
- /*
- * T114: 700 MHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 23:20 4
- * PLLX_BASE n 15: 8 8
- * PLLX_BASE m 7: 0 8
- */
- {
- { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
- { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
- { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
- { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
- },
-
- /*
- * T124: 700 MHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 23:20 4
- * PLLX_BASE n 15: 8 8
- * PLLX_BASE m 7: 0 8
- */
- {
- { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
- { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
- { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
- { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
- },
-};
-
-static inline void pllx_set_iddq(void)
-{
-#if defined(CONFIG_TEGRA124)
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- /* Disable IDDQ */
- reg = readl(&clkrst->crc_pllx_misc3);
- reg &= ~PLLX_IDDQ_MASK;
- writel(reg, &clkrst->crc_pllx_misc3);
- udelay(2);
- debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
- readl(&clkrst->crc_pllx_misc3));
-#endif
-}
-
-int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
- u32 divp, u32 cpcon)
-{
- int chip = tegra_get_chip();
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
- debug("pllx_set_rate: PLLX already enabled, returning\n");
- return 0;
- }
-
- debug(" pllx_set_rate entry\n");
-
- pllx_set_iddq();
-
- /* Set BYPASS, m, n and p to PLLX_BASE */
- reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
- reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
- writel(reg, &pll->pll_base);
-
- /* Set cpcon to PLLX_MISC */
- if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
- reg = (cpcon << PLL_CPCON_SHIFT);
- else
- reg = 0;
-
- /* Set dccon to PLLX_MISC if freq > 600MHz */
- if (divn > 600)
- reg |= (1 << PLL_DCCON_SHIFT);
- writel(reg, &pll->pll_misc);
-
- /* Disable BYPASS */
- reg = readl(&pll->pll_base);
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base = 0x%08X\n", reg);
-
- /* Set lock_enable to PLLX_MISC */
- reg = readl(&pll->pll_misc);
- reg |= PLL_LOCK_ENABLE_MASK;
- writel(reg, &pll->pll_misc);
- debug("pllx_set_rate: misc = 0x%08X\n", reg);
-
- /* Enable PLLX last, once it's all configured */
- reg = readl(&pll->pll_base);
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base final = 0x%08X\n", reg);
-
- return 0;
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
- int soc_type, sku_info, chip_sku;
- enum clock_osc_freq osc;
- struct clk_pll_table *sel;
-
- debug("init_pllx entry\n");
-
- /* get SOC (chip) type */
- soc_type = tegra_get_chip();
- debug(" init_pllx: SoC = 0x%02X\n", soc_type);
-
- /* get SKU info */
- sku_info = tegra_get_sku_info();
- debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
-
- /* get chip SKU, combo of the above info */
- chip_sku = tegra_get_chip_sku();
- debug(" init_pllx: Chip SKU = %d\n", chip_sku);
-
- /* get osc freq */
- osc = clock_get_osc_freq();
- debug(" init_pllx: osc = %d\n", osc);
-
- /* set pllx */
- sel = &tegra_pll_x_table[chip_sku][osc];
- pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-}
-
-void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
- * NOTE:
- * Regardless of whether the request is to enable or disable the CPU
- * clock, every processor in the CPU complex except the master (CPU 0)
- * will have it's clock stopped because the AVP only talks to the
- * master.
- */
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
- * Read the register containing the individual CPU clock enables and
- * always stop the clocks to CPUs > 0.
- */
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
- if (get_num_cpus() == 4)
- clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-void powerup_cpu(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
- int timeout = IO_STABILIZATION_DELAY;
-
- if (!is_cpu_powered()) {
- /* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
- reg &= PARTID_CP;
- reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_cpu_powered()) {
- if (timeout-- == 0)
- printf("CPU failed to power up!\n");
- else
- udelay(10);
- }
-
- /*
- * Remove the I/O clamps from CPU power partition.
- * Recommended only on a Warm boot, if the CPU partition gets
- * power gated. Shouldn't cause any harm when called after a
- * cold boot according to HW, probably just redundant.
- */
- remove_cpu_io_clamps();
- }
-}
-
-void reset_A9_cpu(int reset)
-{
- /*
- * NOTE: Regardless of whether the request is to hold the CPU in reset
- * or take it out of reset, every processor in the CPU complex
- * except the master (CPU 0) will be held in reset because the
- * AVP only talks to the master. The AVP does not know that there
- * are multiple processors in the CPU complex.
- */
- int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
- int num_cpus = get_num_cpus();
- int cpu;
-
- debug("reset_a9_cpu entry\n");
- /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
- for (cpu = 1; cpu < num_cpus; cpu++)
- reset_cmplx_set_enable(cpu, mask, 1);
- reset_cmplx_set_enable(0, mask, reset);
-
- /* Enable/Disable master CPU reset */
- reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-void clock_enable_coresight(int enable)
-{
- u32 rst, src = 2;
-
- debug("clock_enable_coresight entry\n");
- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
- if (enable) {
- /*
- * Put CoreSight on PLLP_OUT0 and divide it down as per
- * PLLP base frequency based on SoC type (T20/T30+).
- * Clock divider request would setup CSITE clock as 144MHz
- * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
- */
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
- /* Unlock the CPU CoreSight interfaces */
- rst = CORESIGHT_UNLOCK;
- writel(rst, CSITE_CPU_DBG0_LAR);
- writel(rst, CSITE_CPU_DBG1_LAR);
- if (get_num_cpus() == 4) {
- writel(rst, CSITE_CPU_DBG2_LAR);
- writel(rst, CSITE_CPU_DBG3_LAR);
- }
- }
-}
-
-void halt_avp(void)
-{
- for (;;) {
- writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
- FLOW_CTLR_HALT_COP_EVENTS);
- }
-}
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
deleted file mode 100644
index b4ca44f..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010-2014
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
-#define IO_STABILIZATION_DELAY (1000)
-
-#if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ 216000
-#define CSITE_KHZ 144000
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
- defined(CONFIG_TEGRA124)
-#define NVBL_PLLP_KHZ 408000
-#define CSITE_KHZ 204000
-#else
-#error "Unknown Tegra chip!"
-#endif
-
-#define PLLX_ENABLED (1 << 30)
-#define CCLK_BURST_POLICY 0x20008888
-#define SUPER_CCLK_DIVIDER 0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0 0x0
-
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
-#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
-#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP 2
-#define HALT_COP_EVENT_JTAG (1 << 28)
-#define HALT_COP_EVENT_IRQ_1 (1 << 11)
-#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-
-#define FLOW_MODE_NONE 0
-
-#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-
-struct clk_pll_table {
- u16 n;
- u16 m;
- u8 p;
- u8 cpcon;
-};
-
-void clock_enable_coresight(int enable);
-void enable_cpu_clock(int enable);
-void halt_avp(void) __attribute__ ((noreturn));
-void init_pllx(void);
-void powerup_cpu(void);
-void reset_A9_cpu(int reset);
-void start_cpu(u32 reset_vector);
-int tegra_get_chip(void);
-int tegra_get_sku_info(void);
-int tegra_get_chip_sku(void);
-void adjust_pllp_out_freqs(void);
-void pmic_enable_cpu_vdd(void);
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
deleted file mode 100644
index e0f9d5b..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Inc, <www.nvidia.com>
- *
- * Allen Martin <amartin@nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <spl.h>
-
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/apb_misc.h>
-#include <asm/arch-tegra/board.h>
-#include <asm/spl.h>
-#include "cpu.h"
-
-void spl_board_init(void)
-{
- struct apb_misc_pp_ctlr *apb_misc =
- (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
-
- /* enable JTAG */
- writel(0xC0, &apb_misc->cfg_ctl);
-
- board_init_uart_f();
-
- /* Initialize periph GPIOs */
- gpio_early_init_uart();
-
- clock_early_init();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_RAM;
-}
-
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- debug("image entry point: 0x%X\n", spl_image->entry_point);
-
- start_cpu((u32)spl_image->entry_point);
- halt_avp();
-}
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile
deleted file mode 100644
index ea3e55e..0000000
--- a/arch/arm/cpu/arm720t/tegra114/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-#obj-y += cpu.o t11x.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
deleted file mode 100644
index 5ed3bb9..0000000
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra114-specific CPU init code */
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("enable_cpu_power_rail entry\n");
-
- /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
-
- /*
- * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
- * set it for 25ms (102MHz * .025)
- */
- reg = 0x26E8F0;
- writel(reg, &pmc->pmc_cpupwrgood_timer);
-
- /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
- clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
- setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
-
- /*
- * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
- * to 408 to satisfy the requirement of having at least 16 CPU clock
- * cycles before clamp removal.
- */
-
- clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
- setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
-}
-
-static void enable_cpu_clocks(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("enable_cpu_clocks entry\n");
-
- /* Wait for PLL-X to lock */
- do {
- reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- } while ((reg & PLL_LOCK_MASK) == 0);
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-
- /* Always enable the main CPU complex clocks */
- clock_enable(PERIPH_ID_CPU);
- clock_enable(PERIPH_ID_CPULP);
- clock_enable(PERIPH_ID_CPUG);
-}
-
-static void remove_cpu_resets(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("remove_cpu_resets entry\n");
- /* Take the slow non-CPU partition out of reset */
- reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
- writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
-
- /* Take the fast non-CPU partition out of reset */
- reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
- writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
-
- /* Clear the SW-controlled reset of the slow cluster */
- reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
- reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
- writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
-
- /* Clear the SW-controlled reset of the fast cluster */
- reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
- reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
- reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
- reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
- reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
- writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-}
-
-/**
- * The T114 requires some special clock initialization, including setting up
- * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
- */
-void t114_init_clocks(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- u32 val;
-
- debug("t114_init_clocks entry\n");
-
- /* Set active CPU cluster to G */
- clrbits_le32(&flow->cluster_control, 1);
-
- writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
- debug("Setting up PLLX\n");
- init_pllx();
-
- val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
- writel(val, &clkrst->crc_clk_sys_rate);
-
- /* Enable clocks to required peripherals. TBD - minimize this list */
- debug("Enabling clocks\n");
-
- clock_set_enable(PERIPH_ID_CACHE2, 1);
- clock_set_enable(PERIPH_ID_GPIO, 1);
- clock_set_enable(PERIPH_ID_TMR, 1);
- clock_set_enable(PERIPH_ID_RTC, 1);
- clock_set_enable(PERIPH_ID_CPU, 1);
- clock_set_enable(PERIPH_ID_EMC, 1);
- clock_set_enable(PERIPH_ID_I2C5, 1);
- clock_set_enable(PERIPH_ID_FUSE, 1);
- clock_set_enable(PERIPH_ID_PMC, 1);
- clock_set_enable(PERIPH_ID_APBDMA, 1);
- clock_set_enable(PERIPH_ID_MEM, 1);
- clock_set_enable(PERIPH_ID_IRAMA, 1);
- clock_set_enable(PERIPH_ID_IRAMB, 1);
- clock_set_enable(PERIPH_ID_IRAMC, 1);
- clock_set_enable(PERIPH_ID_IRAMD, 1);
- clock_set_enable(PERIPH_ID_CORESIGHT, 1);
- clock_set_enable(PERIPH_ID_MSELECT, 1);
- clock_set_enable(PERIPH_ID_EMC1, 1);
- clock_set_enable(PERIPH_ID_MC1, 1);
- clock_set_enable(PERIPH_ID_DVFS, 1);
-
- /*
- * Set MSELECT clock source as PLLP (00), and ask for a clock
- * divider that would set the MSELECT clock at 102MHz for a
- * PLLP base of 408MHz.
- */
- clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
- CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
-
- /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
- clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
-
- /* Give clocks time to stabilize */
- udelay(1000);
-
- /* Take required peripherals out of reset */
- debug("Taking periphs out of reset\n");
- reset_set_enable(PERIPH_ID_CACHE2, 0);
- reset_set_enable(PERIPH_ID_GPIO, 0);
- reset_set_enable(PERIPH_ID_TMR, 0);
- reset_set_enable(PERIPH_ID_COP, 0);
- reset_set_enable(PERIPH_ID_EMC, 0);
- reset_set_enable(PERIPH_ID_I2C5, 0);
- reset_set_enable(PERIPH_ID_FUSE, 0);
- reset_set_enable(PERIPH_ID_APBDMA, 0);
- reset_set_enable(PERIPH_ID_MEM, 0);
- reset_set_enable(PERIPH_ID_CORESIGHT, 0);
- reset_set_enable(PERIPH_ID_MSELECT, 0);
- reset_set_enable(PERIPH_ID_EMC1, 0);
- reset_set_enable(PERIPH_ID_MC1, 0);
- reset_set_enable(PERIPH_ID_DVFS, 0);
-
- debug("t114_init_clocks exit\n");
-}
-
-static bool is_partition_powered(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Get power gate status */
- reg = readl(&pmc->pmc_pwrgate_status);
- return !!(reg & (1 << partid));
-}
-
-static bool is_clamp_enabled(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Get clamp status. */
- reg = readl(&pmc->pmc_clamp_status);
- return !!(reg & (1 << partid));
-}
-
-static void power_partition(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("%s: part ID = %08X\n", __func__, partid);
- /* Is the partition already on? */
- if (!is_partition_powered(partid)) {
- /* No, toggle the partition power state (OFF -> ON) */
- debug("power_partition, toggling state\n");
- writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_partition_powered(partid))
- ;
-
- /* Wait for the clamp status to be cleared */
- while (is_clamp_enabled(partid))
- ;
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
- }
-}
-
-void powerup_cpus(void)
-{
- debug("powerup_cpus entry\n");
-
- /* We boot to the fast cluster */
- debug("powerup_cpus entry: G cluster\n");
- /* Power up the fast cluster rail partition */
- power_partition(CRAIL);
-
- /* Power up the fast cluster non-CPU partition */
- power_partition(C0NC);
-
- /* Power up the fast cluster CPU0 partition */
- power_partition(CE0);
-}
-
-void start_cpu(u32 reset_vector)
-{
- u32 imme, inst;
-
- debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-
- t114_init_clocks();
-
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- /* Get the CPU(s) running */
- enable_cpu_clocks();
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /* Take CPU(s) out of reset */
- remove_cpu_resets();
-
- /* Set the entry point for CPU execution from reset */
-
- /*
- * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
- * See nvbug 1193357 for details.
- */
-
- /* mov r0, #lsb(reset_vector) */
- imme = reset_vector & 0xffff;
- inst = imme & 0xfff;
- inst |= ((imme >> 12) << 16);
- inst |= 0xe3000000;
- writel(inst, 0x4003fff0);
-
- /* movt r0, #msb(reset_vector) */
- imme = (reset_vector >> 16) & 0xffff;
- inst = imme & 0xfff;
- inst |= ((imme >> 12) << 16);
- inst |= 0xe3400000;
- writel(inst, 0x4003fff4);
-
- /* bx r0 */
- writel(0xe12fff10, 0x4003fff8);
-
- /* b -12 */
- imme = (u32)-20;
- inst = (imme >> 2) & 0xffffff;
- inst |= 0xea000000;
- writel(inst, 0x4003fffc);
-
- /* Write to orignal location for compatibility */
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* If the CPU(s) don't already have power, power 'em up */
- powerup_cpus();
-}
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
deleted file mode 100644
index 61abf45..0000000
--- a/arch/arm/cpu/arm720t/tegra124/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
deleted file mode 100644
index 6ff6aeb..0000000
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ahb.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/ap.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra124-specific CPU init code */
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("enable_cpu_power_rail entry\n");
-
- /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
-
- pmic_enable_cpu_vdd();
-
- /*
- * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
- * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
- */
- writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
-
- /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
- clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
- setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
-}
-
-static void enable_cpu_clocks(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("enable_cpu_clocks entry\n");
-
- /* Wait for PLL-X to lock */
- do {
- reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- debug("%s: PLLX base = 0x%08X\n", __func__, reg);
- } while ((reg & PLL_LOCK_MASK) == 0);
-
- debug("%s: PLLX locked, delay for stable clocks\n", __func__);
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-
- debug("%s: Enabling clock to all CPUs\n", __func__);
- /* Enable the clock to all CPUs */
- reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
- CLR_CPU0_CLK_STP;
- writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
-
- debug("%s: Enabling main CPU complex clocks\n", __func__);
- /* Always enable the main CPU complex clocks */
- clock_enable(PERIPH_ID_CPU);
- clock_enable(PERIPH_ID_CPULP);
- clock_enable(PERIPH_ID_CPUG);
-
- debug("%s: Done\n", __func__);
-}
-
-static void remove_cpu_resets(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("remove_cpu_resets entry\n");
-
- /* Take the slow and fast partitions out of reset */
- reg = CLR_NONCPURESET;
- writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
- writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-
- /* Clear the SW-controlled reset of the slow cluster */
- reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
- CLR_L2RESET | CLR_PRESETDBG;
- writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
-
- /* Clear the SW-controlled reset of the fast cluster */
- reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
- CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
- CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
- CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
- CLR_L2RESET | CLR_PRESETDBG;
- writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-}
-
-/**
- * The Tegra124 requires some special clock initialization, including setting up
- * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
- */
-void tegra124_init_clocks(void)
-{
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 val;
-
- debug("tegra124_init_clocks entry\n");
-
- /* Set active CPU cluster to G */
- clrbits_le32(&flow->cluster_control, 1);
-
- /* Change the oscillator drive strength */
- val = readl(&clkrst->crc_osc_ctrl);
- val &= ~OSC_XOFS_MASK;
- val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
- writel(val, &clkrst->crc_osc_ctrl);
-
- /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
- val = readl(&pmc->pmc_osc_edpd_over);
- val &= ~PMC_XOFS_MASK;
- val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
- writel(val, &pmc->pmc_osc_edpd_over);
-
- /* Set HOLD_CKE_LOW_EN to 1 */
- setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
-
- debug("Setting up PLLX\n");
- init_pllx();
-
- val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
- writel(val, &clkrst->crc_clk_sys_rate);
-
- /* Enable clocks to required peripherals. TBD - minimize this list */
- debug("Enabling clocks\n");
-
- clock_set_enable(PERIPH_ID_CACHE2, 1);
- clock_set_enable(PERIPH_ID_GPIO, 1);
- clock_set_enable(PERIPH_ID_TMR, 1);
- clock_set_enable(PERIPH_ID_CPU, 1);
- clock_set_enable(PERIPH_ID_EMC, 1);
- clock_set_enable(PERIPH_ID_I2C5, 1);
- clock_set_enable(PERIPH_ID_APBDMA, 1);
- clock_set_enable(PERIPH_ID_MEM, 1);
- clock_set_enable(PERIPH_ID_CORESIGHT, 1);
- clock_set_enable(PERIPH_ID_MSELECT, 1);
- clock_set_enable(PERIPH_ID_DVFS, 1);
-
- /*
- * Set MSELECT clock source as PLLP (00), and ask for a clock
- * divider that would set the MSELECT clock at 102MHz for a
- * PLLP base of 408MHz.
- */
- clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
- CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
-
- /* Give clock time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-
- /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
- clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
-
- /* Give clock time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-
- /* Take required peripherals out of reset */
- debug("Taking periphs out of reset\n");
- reset_set_enable(PERIPH_ID_CACHE2, 0);
- reset_set_enable(PERIPH_ID_GPIO, 0);
- reset_set_enable(PERIPH_ID_TMR, 0);
- reset_set_enable(PERIPH_ID_COP, 0);
- reset_set_enable(PERIPH_ID_EMC, 0);
- reset_set_enable(PERIPH_ID_I2C5, 0);
- reset_set_enable(PERIPH_ID_APBDMA, 0);
- reset_set_enable(PERIPH_ID_MEM, 0);
- reset_set_enable(PERIPH_ID_CORESIGHT, 0);
- reset_set_enable(PERIPH_ID_MSELECT, 0);
- reset_set_enable(PERIPH_ID_DVFS, 0);
-
- debug("tegra124_init_clocks exit\n");
-}
-
-static bool is_partition_powered(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Get power gate status */
- reg = readl(&pmc->pmc_pwrgate_status);
- return !!(reg & (1 << partid));
-}
-
-static void power_partition(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("%s: part ID = %08X\n", __func__, partid);
- /* Is the partition already on? */
- if (!is_partition_powered(partid)) {
- /* No, toggle the partition power state (OFF -> ON) */
- debug("power_partition, toggling state\n");
- writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_partition_powered(partid))
- ;
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
- }
-}
-
-void powerup_cpus(void)
-{
- debug("powerup_cpus entry\n");
-
- /* We boot to the fast cluster */
- debug("powerup_cpus entry: G cluster\n");
-
- /* Power up the fast cluster rail partition */
- debug("powerup_cpus: CRAIL\n");
- power_partition(CRAIL);
-
- /* Power up the fast cluster non-CPU partition */
- debug("powerup_cpus: C0NC\n");
- power_partition(C0NC);
-
- /* Power up the fast cluster CPU0 partition */
- debug("powerup_cpus: CE0\n");
- power_partition(CE0);
-
- debug("powerup_cpus: done\n");
-}
-
-void start_cpu(u32 reset_vector)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-
- tegra124_init_clocks();
-
- /* Set power-gating timer multiplier */
- writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
- &pmc->pmc_pwrgate_timer_mult);
-
- enable_cpu_power_rail();
- enable_cpu_clocks();
- clock_enable_coresight(1);
- remove_cpu_resets();
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
- powerup_cpus();
- debug("start_cpu exit, should continue @ reset_vector\n");
-}
diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile
deleted file mode 100644
index 12243fa..0000000
--- a/arch/arm/cpu/arm720t/tegra20/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
deleted file mode 100644
index 2533899..0000000
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- reg = readl(&pmc->pmc_cntrl);
- reg |= CPUPWRREQ_OE;
- writel(reg, &pmc->pmc_cntrl);
-
- /*
- * The TI PMU65861C needs a 3.75ms delay between enabling
- * the power rail and enabling the CPU clock. This delay
- * between SM1EN and SM1 is for switching time + the ramp
- * up of the voltage to the CPU (VDD_CPU from PMU).
- */
- udelay(3750);
-}
-
-void start_cpu(u32 reset_vector)
-{
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- /* Hold the CPUs in reset */
- reset_A9_cpu(1);
-
- /* Disable the CPU clock */
- enable_cpu_clock(0);
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
- */
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Enable the CPU clock */
- enable_cpu_clock(1);
-
- /* If the CPU doesn't already have power, power it up */
- powerup_cpu();
-
- /* Take the CPU out of reset */
- reset_A9_cpu(0);
-}
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
deleted file mode 100644
index 6ff4c55..0000000
--- a/arch/arm/cpu/arm720t/tegra30/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
deleted file mode 100644
index 9003902..0000000
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra30-specific CPU init code */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(addr, ®->cmd_addr0);
- writel(config, ®->cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(data, ®->cmd_data1);
- writel(config, ®->cnfg);
-}
-
-#define TPS62366A_I2C_ADDR 0xC0
-#define TPS62366A_SET1_REG 0x01
-#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
-
-#define TPS62361B_I2C_ADDR 0xC0
-#define TPS62361B_SET3_REG 0x03
-#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
-
-#define TPS65911_I2C_ADDR 0x5A
-#define TPS65911_VDDCTRL_OP_REG 0x28
-#define TPS65911_VDDCTRL_SR_REG 0x27
-#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
-#define I2C_SEND_2_BYTES 0x0A02
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- debug("enable_cpu_power_rail entry\n");
- reg = readl(&pmc->pmc_cntrl);
- reg |= CPUPWRREQ_OE;
- writel(reg, &pmc->pmc_cntrl);
-
- /* Set VDD_CORE to 1.200V. */
-#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
- tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
-#endif
-#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
- tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
-#endif
- udelay(1000);
-
- /*
- * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
- * First set VDD to 1.0125V, then enable the VDD regulator.
- */
- tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
- udelay(1000);
- tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-}
-
-/**
- * The T30 requires some special clock initialization, including setting up
- * the dvc i2c, turning on mselect and selecting the G CPU cluster
- */
-void t30_init_clocks(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- u32 val;
-
- debug("t30_init_clocks entry\n");
- /* Set active CPU cluster to G */
- clrbits_le32(flow->cluster_control, 1 << 0);
-
- writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
- val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
- (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
- (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
- (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
- writel(val, &clkrst->crc_clk_sys_rate);
-
- /* Put i2c, mselect in reset and enable clocks */
- reset_set_enable(PERIPH_ID_DVC_I2C, 1);
- clock_set_enable(PERIPH_ID_DVC_I2C, 1);
- reset_set_enable(PERIPH_ID_MSELECT, 1);
- clock_set_enable(PERIPH_ID_MSELECT, 1);
-
- /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
- clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
-
- /*
- * Our high-level clock routines are not available prior to
- * relocation. We use the low-level functions which require a
- * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
- */
- clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
-
- /*
- * Give clocks time to stabilize, then take i2c and mselect out of
- * reset
- */
- udelay(1000);
- reset_set_enable(PERIPH_ID_DVC_I2C, 0);
- reset_set_enable(PERIPH_ID_MSELECT, 0);
-}
-
-static void set_cpu_running(int run)
-{
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- debug("set_cpu_running entry, run = %d\n", run);
- writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
-}
-
-void start_cpu(u32 reset_vector)
-{
- debug("start_cpu entry, reset_vector = %x\n", reset_vector);
- t30_init_clocks();
-
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- set_cpu_running(0);
-
- /* Hold the CPUs in reset */
- reset_A9_cpu(1);
-
- /* Disable the CPU clock */
- enable_cpu_clock(0);
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
- */
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Enable the CPU clock */
- enable_cpu_clock(1);
-
- /* If the CPU doesn't already have power, power it up */
- powerup_cpu();
-
- /* Take the CPU out of reset */
- reset_A9_cpu(0);
-
- set_cpu_running(1);
-}
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index a72e5de..c63f578 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -1,18 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-y = start.o
obj-y += cpu.o
-obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-$(if $(filter a320,$(SOC)),y) += a320/
-obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_KS8695) += ks8695/
-obj-$(CONFIG_S3C24X0) += s3c24x0/
+
+# some files can only build in ARM mode
+
+ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
+CFLAGS_cpu.o := -marm
+endif
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
deleted file mode 100644
index bbdab58..0000000
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S
deleted file mode 100644
index 81f9dc9..0000000
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
- b reset_cpu
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
deleted file mode 100644
index 1ac5b60..0000000
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK 32768
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-int timer_init(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- unsigned int cr;
-
- debug("%s()\n", __func__);
-
- /* disable timers */
- writel(0, &tmr->cr);
-
- /* use 32768Hz oscillator for RTC, WDT, TIMER */
- ftpmu010_32768osc_enable();
-
- /* setup timer */
- writel(TIMER_LOAD_VAL, &tmr->timer3_load);
- writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
- writel(0, &tmr->timer3_match1);
- writel(0, &tmr->timer3_match2);
-
- /* we don't want timer to issue interrupts */
- writel(FTTMR010_TM3_MATCH1 |
- FTTMR010_TM3_MATCH2 |
- FTTMR010_TM3_OVERFLOW,
- &tmr->interrupt_mask);
-
- cr = readl(&tmr->cr);
- cr |= FTTMR010_TM3_CLOCK; /* use external clock */
- cr |= FTTMR010_TM3_ENABLE;
- writel(cr, &tmr->cr);
-
- gd->arch.timer_rate_hz = TIMER_CLOCK;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile
deleted file mode 100644
index 561b4b4..0000000
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += lowlevel_init.o
-obj-y += reset.o
-obj-y += timer.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += at91rm9200_devices.o
diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
deleted file mode 100644
index fc54327..0000000
--- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
- *
- * (C) Copyright 2011
- * Andreas Bießmann <andreas.devel@googlemail.com>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTA, 30, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 31, 1); /* DTXD */
- /* writing SYS to PCER has no effect on AT91RM9200 */
-}
diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/cpu/arm920t/at91/clock.c
deleted file mode 100644
index 2813bf7..0000000
--- a/arch/arm/cpu/arm920t/at91/clock.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2011 Andreas Bießmann
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
- case AT91_PMC_MCKR_CSS_MAIN:
- return gd->arch.main_clk_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLA:
- return gd->arch.plla_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLB:
- return gd->arch.pllb_rate_hz;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 16) & 0x7ff;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
- unsigned freq, mckr;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
- unsigned tmp;
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = readl(&pmc->mcfr);
- } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
- tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
- }
-#endif
- gd->arch.main_clk_rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
- AT91_PMC_PLLBR_USBDIV_2;
- gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
- gd->arch.at91_pllb_usb_init);
-#endif
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = readl(&pmc->mckr);
- gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->arch.mck_rate_hz;
-
- freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
- /* mdiv */
- gd->arch.mck_rate_hz = freq /
- (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
- gd->arch.cpu_clk_rate_hz = freq;
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm920t/at91/cpu.c b/arch/arm/cpu/arm920t/at91/cpu.c
deleted file mode 100644
index b0f411b..0000000
--- a/arch/arm/cpu/arm920t/at91/cpu.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
- *
- * (C) Copyright 2011
- * Andreas Bießmann, andreas.devel@googlemail.com
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S
deleted file mode 100644
index d2934a3..0000000
--- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
- .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- ldr r1, =AT91_ASM_PMC_MOR
- /* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
- ldr r0, =0x0000FF01 /* Enable main oscillator */
-#else
- ldr r0, =0x0000FF00 /* Disable main oscillator */
-#endif
- str r0, [r1] /*AT91C_CKGR_MOR] */
- /* Add loop to compensate Main Oscillator startup time */
- ldr r0, =0x00000010
-LoopOsc:
- subs r0, r0, #1
- bhi LoopOsc
-
- /* memory control configuration */
- /* this isn't very elegant, but what the heck */
- ldr r0, =SMRDATA
- ldr r1, _MTEXT_BASE
- sub r0, r0, r1
- ldr r2, =SMRDATAE
- sub r2, r2, r1
-pllloop:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne pllloop
- /* delay - this is all done by guess */
- ldr r0, =0x00010000
- /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-lock:
- subs r0, r0, #1
- bhi lock
- ldr r0, =SMRDATA1
- ldr r1, _MTEXT_BASE
- sub r0, r0, r1
- ldr r2, =SMRDATA1E
- sub r2, r2, r1
-sdinit:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne sdinit
-
- /* switch from FastBus to Asynchronous clock mode */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #ARM920T_CONTROL
- mcr p15, 0, r0, c1, c0, 0
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-
-SMRDATA:
- .word AT91_ASM_MC_EBI_CFG
- .word CONFIG_SYS_EBI_CFGR_VAL
- .word AT91_ASM_MC_SMC_CSR0
- .word CONFIG_SYS_SMC_CSR0_VAL
- .word AT91_ASM_PMC_PLLAR
- .word CONFIG_SYS_PLLAR_VAL
- .word AT91_ASM_PMC_PLLBR
- .word CONFIG_SYS_PLLBR_VAL
- .word AT91_ASM_PMC_MCKR
- .word CONFIG_SYS_MCKR_VAL
-SMRDATAE:
- /* here there's a delay */
-SMRDATA1:
- .word AT91_ASM_PIOC_ASR
- .word CONFIG_SYS_PIOC_ASR_VAL
- .word AT91_ASM_PIOC_BSR
- .word CONFIG_SYS_PIOC_BSR_VAL
- .word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL
- .word AT91_ASM_MC_EBI_CSA
- .word CONFIG_SYS_EBI_CSA_VAL
- .word AT91_ASM_MC_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM1
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
-SMRDATA1E:
- /* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c
deleted file mode 100644
index d47777a..0000000
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_st.h>
-
-void __attribute__((weak)) board_reset(void)
-{
- /* true empty function for defining weak symbol */
-}
-
-void reset_cpu(ulong ignored)
-{
- at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
-
- board_reset();
-
- /* Reset the cpu by setting up the watchdog timer */
- writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
- &st->wdmr);
- writel(AT91_ST_CR_WDRST, &st->cr);
- /* and let it timeout */
- while (1)
- ;
- /* Never reached */
-}
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c
deleted file mode 100644
index 6aa2994..0000000
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_tc.h>
-#include <asm/arch/at91_pmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-int timer_init(void)
-{
- at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* enables TC1.0 clock */
- writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */
-
- writel(0, &tc->bcr);
- writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
- AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
-
- writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
- /* set to MCLK/2 and restart the timer
- when the value in TC_RC is reached */
- writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
-
- writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
- writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
-
- writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
- gd->arch.lastinc = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-ulong get_timer_raw(void)
-{
- at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
- u32 now;
-
- now = readl(&tc->tc[0].cv) & 0x0000ffff;
-
- if (now >= gd->arch.lastinc) {
- /* normal mode */
- gd->arch.tbl += now - gd->arch.lastinc;
- } else {
- /* we have an overflow ... */
- gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
- }
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
- return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked(unsigned long usec)
-{
- u32 tmo;
- u32 endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= 1000;
-
- endtime = get_timer_raw() + tmo;
-
- do {
- u32 now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
deleted file mode 100644
index 799afff..0000000
--- a/arch/arm/cpu/arm920t/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c
index d73b51d..2ef133f 100644
--- a/arch/arm/cpu/arm920t/cpu.c
+++ b/arch/arm/cpu/arm920t/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -5,8 +6,6 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
diff --git a/arch/arm/cpu/arm920t/ep93xx/Makefile b/arch/arm/cpu/arm920t/ep93xx/Makefile
index 638333a..152b5e7 100644
--- a/arch/arm/cpu/arm920t/ep93xx/Makefile
+++ b/arch/arm/cpu/arm920t/ep93xx/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Cirrus Logic EP93xx CPU-specific Makefile
#
@@ -13,9 +14,6 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y = cpu.o led.o speed.o timer.o
obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c
index bb5ffd2..3aae12f 100644
--- a/arch/arm/cpu/arm920t/ep93xx/cpu.c
+++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx CPU-specific support.
*
@@ -5,8 +6,6 @@
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm920t/ep93xx/led.c b/arch/arm/cpu/arm920t/ep93xx/led.c
index 6144729..862663a 100644
--- a/arch/arm/cpu/arm920t/ep93xx/led.c
+++ b/arch/arm/cpu/arm920t/ep93xx/led.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
@@ -9,44 +8,44 @@
#include <config.h>
#include <status_led.h>
-static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
-static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
- 1 << STATUS_LED_RED};
+static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
+static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
+ 1 << CONFIG_LED_STATUS_RED};
-inline void switch_LED_on(uint8_t led)
+static inline void switch_LED_on(uint8_t led)
{
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
- saved_state[led] = STATUS_LED_ON;
+ saved_state[led] = CONFIG_LED_STATUS_ON;
}
-inline void switch_LED_off(uint8_t led)
+static inline void switch_LED_off(uint8_t led)
{
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
- saved_state[led] = STATUS_LED_OFF;
+ saved_state[led] = CONFIG_LED_STATUS_OFF;
}
void red_led_on(void)
{
- switch_LED_on(STATUS_LED_RED);
+ switch_LED_on(CONFIG_LED_STATUS_RED);
}
void red_led_off(void)
{
- switch_LED_off(STATUS_LED_RED);
+ switch_LED_off(CONFIG_LED_STATUS_RED);
}
void green_led_on(void)
{
- switch_LED_on(STATUS_LED_GREEN);
+ switch_LED_on(CONFIG_LED_STATUS_GREEN);
}
void green_led_off(void)
{
- switch_LED_off(STATUS_LED_GREEN);
+ switch_LED_off(CONFIG_LED_STATUS_GREEN);
}
void __led_init(led_id_t mask, int state)
@@ -56,13 +55,14 @@
void __led_toggle(led_id_t mask)
{
- if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+ if (CONFIG_LED_STATUS_RED == mask) {
+ if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
red_led_off();
else
red_led_on();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+ } else if (CONFIG_LED_STATUS_GREEN == mask) {
+ if (CONFIG_LED_STATUS_ON ==
+ saved_state[CONFIG_LED_STATUS_GREEN])
green_led_off();
else
green_led_on();
@@ -71,13 +71,13 @@
void __led_set(led_id_t mask, int state)
{
- if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
+ if (CONFIG_LED_STATUS_RED == mask) {
+ if (CONFIG_LED_STATUS_ON == state)
red_led_on();
else
red_led_off();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == state)
+ } else if (CONFIG_LED_STATUS_GREEN == mask) {
+ if (CONFIG_LED_STATUS_ON == state)
green_led_on();
else
green_led_off();
diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
index cfad206..5239b10 100644
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Low-level initialization for EP93xx
*
@@ -10,8 +11,6 @@
*
* See file CREDITS for list of people who contributed to this
* project.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
diff --git a/arch/arm/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c
index 9dc60b6..51e9dda 100644
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ b/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx PLL support.
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -39,7 +38,7 @@
}
/* return FCLK frequency */
-ulong get_FCLK()
+ulong get_FCLK(void)
{
const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
diff --git a/arch/arm/cpu/arm920t/ep93xx/timer.c b/arch/arm/cpu/arm920t/ep93xx/timer.c
index c2f239a..49bf49b 100644
--- a/arch/arm/cpu/arm920t/ep93xx/timer.c
+++ b/arch/arm/cpu/arm920t/ep93xx/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx timer support.
*
@@ -8,8 +9,6 @@
*
* Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
* author unknown.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -67,14 +66,9 @@
return sys_ticks;
}
-unsigned long get_timer_masked(void)
-{
- return get_ticks();
-}
-
unsigned long get_timer(unsigned long base)
{
- return get_timer_masked() - base;
+ return get_ticks() - base;
}
void __udelay(unsigned long usec)
diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile
index 54ce646..04bc129 100644
--- a/arch/arm/cpu/arm920t/imx/Makefile
+++ b/arch/arm/cpu/arm920t/imx/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += generic.o
obj-y += speed.o
diff --git a/arch/arm/cpu/arm920t/imx/generic.c b/arch/arm/cpu/arm920t/imx/generic.c
index 1441ab4..dbb908e 100644
--- a/arch/arm/cpu/arm920t/imx/generic.c
+++ b/arch/arm/cpu/arm920t/imx/generic.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* arch/arm/mach-imx/generic.c
*
@@ -6,8 +7,6 @@
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
index 1951313..eff6113 100644
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ b/arch/arm/cpu/arm920t/imx/speed.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
*
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
index b62558f..96fff3f 100644
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ b/arch/arm/cpu/arm920t/imx/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -9,8 +10,6 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -37,17 +36,17 @@
/*
* timer without interrupts
*/
+static ulong get_timer_masked (void)
+{
+ return TCN1;
+}
+
ulong get_timer (ulong base)
{
return get_timer_masked() - base;
}
-ulong get_timer_masked (void)
-{
- return TCN1;
-}
-
-void udelay_masked (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong endtime = get_timer_masked() + usec;
signed long diff;
@@ -58,11 +57,6 @@
} while (diff >= 0);
}
-void __udelay (unsigned long usec)
-{
- udelay_masked(usec);
-}
-
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
@@ -78,11 +72,7 @@
*/
ulong get_tbclk (void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
-
- return tbclk;
+ return CONFIG_SYS_HZ;
}
/*
diff --git a/arch/arm/cpu/arm920t/interrupts.c b/arch/arm/cpu/arm920t/interrupts.c
deleted file mode 100644
index 0e04d36..0000000
--- a/arch/arm/cpu/arm920t/interrupts.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-
-#if defined (CONFIG_ARCH_INTEGRATOR)
-void do_irq (struct pt_regs *pt_regs)
-{
- /* ASSUMED to be a timer interrupt */
- /* Just clear it - count handled in */
- /* integratorap.c */
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
deleted file mode 100644
index 400aa89..0000000
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lowlevel_init.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
deleted file mode 100644
index a2a07f2..0000000
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
- /*
- * enable UART for early debug trace
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
- mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
- str r2, [r1]
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
- mov r2, #KS8695_UART_LINEC_WLEN8
- str r2, [r1] /* 8 data bits, no parity, 1 stop */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x41
- str r2, [r1] /* write 'A' */
-#endif
-#if DEBUG
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x42
- str r2, [r1]
-#endif
-
- /*
- * remap the memory and flash regions. we want to end up with
- * ram from address 0, and flash at 32MB.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
- ldr r2, =0xbfc00040
- str r2, [r1] /* large flash map */
- ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
-highflash:
- ldr r2, =0x8fe00040
- str r2, [r1] /* remap flash range */
-
- /*
- * remap the second select region to the 4MB immediately after
- * the first region. This way if you have a larger flash (say 8Mb)
- * then you can have it all mapped nicely. Has no effect if you
- * only have a 4Mb or smaller flash.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
- ldr r2, =0x9fe40040
- str r2, [r1] /* remap flash2 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30000005
- str r2, [r1] /* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
- /*
- * map the second flash chip, using the external IO lines.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
- ldr r2, =0xafe80b6d
- str r2, [r1] /* remap io0 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
- ldr r2, =0xbfec0b6d
- str r2, [r1] /* remap io1 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30050005
- str r2, [r1] /* enable second flash */
-#endif
-
- /*
- * before relocating, we have to setup RAM timing
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
- ldr r2, =0x7fc0000e /* 32MB */
-#else
- ldr r2, =0x3fc0000e /* 16MB */
-#endif
- str r2, [r1] /* configure sdram bank0 setup */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
- mov r2, #0
- str r2, [r1] /* configure sdram bank1 setup */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
- ldr r2, =0x0000000a
- str r2, [r1] /* set RAS/CAS timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00030000
- str r2, [r1] /* send NOP command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00010000
- str r2, [r1] /* send PRECHARGE-ALL */
- DELAY_FOR 0x100, r0
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
- ldr r2, =0x00000020
- str r2, [r1] /* set for fast refresh */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00000190
- str r2, [r1] /* set normal refresh timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00020033
- str r2, [r1] /* send mode command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x01f00000
- str r2, [r1] /* enable sdram fifos */
-
- /*
- * set pll to top speed
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
- mov r2, #0
- str r2, [r1] /* set pll clock to 166MHz */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
- ldr r2, [r1] /* Get switch ctrl0 register */
- and r2, r2, #0x0fc00000 /* Mask out LED control bits */
- orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
- str r2, [r1]
-
-#ifdef CONFIG_CM4008
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
- ldr r2, =0x0000fe30
- str r2, [r1] /* enable LED's as outputs */
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
- ldr r2, =0x0000fe20
- str r2, [r1] /* turn on power LED */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
- ldr r2, [r1] /* get current GPIO input data */
- tst r2, #0x8 /* check if "erase" depressed */
- beq nobutton
- mov r2, #0 /* be quiet on boot, no console */
- ldr r1, =serial_console
- str r2, [r1]
-nobutton:
-#endif
-
- add lr, lr, #0x02000000 /* flash is now mapped high */
- add ip, ip, #0x02000000 /* this is a hack */
- mov pc, lr /* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c
deleted file mode 100644
index 23db557..0000000
--- a/arch/arm/cpu/arm920t/ks8695/timer.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
-#define TIMER_COUNT (TIMER_INTERVAL / 2)
-#define TIMER_PULSE TIMER_COUNT
-
-/*
- * Handy KS8695 register access functions.
- */
-#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
- /* Set the hadware timer for 1ms */
- ks8695_write(KS8695_TIMER1, TIMER_COUNT);
- ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
- ks8695_write(KS8695_TIMER_CTRL, 0x2);
- timer_ticks = 0;
-
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* Check for timer wrap */
- if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
- /* Clear interrupt condition */
- ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
- timer_ticks++;
- }
- return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() - base);
-}
-
-void __udelay(ulong usec)
-{
- ulong start = get_timer_masked();
- ulong end;
-
- /* Only 1ms resolution :-( */
- end = usec / 1000;
- while (get_timer(start) < end)
- ;
-}
-
-void reset_cpu (ulong ignored)
-{
- ulong tc;
-
- /* Set timer0 to watchdog, and let it timeout */
- tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
- ks8695_write(KS8695_TIMER_CTRL, tc);
- ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
- ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
- /* Should only wait here till watchdog resets */
- for (;;)
- ;
-}
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
deleted file mode 100644
index e44c549..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
-obj-y += speed.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
deleted file mode 100644
index fede51a..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2010
- * David Mueller <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-typedef ulong (*getfreq)(void);
-
-static const getfreq freq_f[] = {
- get_FCLK,
- get_HCLK,
- get_PCLK,
-};
-
-static const char freq_c[] = { 'F', 'H', 'P' };
-
-int print_cpuinfo(void)
-{
- int i;
- char buf[32];
-/* the S3C2400 seems to be lacking a CHIP ID register */
-#ifndef CONFIG_S3C2400
- ulong cpuid;
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- cpuid = readl(&gpio->gstatus1);
- printf("CPUID: %8lX\n", cpuid);
-#endif
- for (i = 0; i < ARRAY_SIZE(freq_f); i++)
- printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
deleted file mode 100644
index 036e3b9..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/proc-armv/ptrace.h>
-
-void do_irq (struct pt_regs *pt_regs)
-{
- struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
- u_int32_t intpnd = readl(&irq->INTPND);
-
-}
diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c
deleted file mode 100644
index 3701c5d..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#ifdef CONFIG_S3C24X0
-
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#define MPLL 0
-#define UPLL 1
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- ulong r, m, p, s;
-
- if (pllreg == MPLL)
- r = readl(&clk_power->mpllcon);
- else if (pllreg == UPLL)
- r = readl(&clk_power->upllcon);
- else
- hang();
-
- m = ((r & 0xFF000) >> 12) + 8;
- p = ((r & 0x003F0) >> 4) + 2;
- s = r & 0x3;
-
-#if defined(CONFIG_S3C2440)
- if (pllreg == MPLL)
- return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
-#endif
- return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
-
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
- return get_PLLCLK(MPLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-#ifdef CONFIG_S3C2440
- switch (readl(&clk_power->clkdivn) & 0x6) {
- default:
- case 0:
- return get_FCLK();
- case 2:
- return get_FCLK() / 2;
- case 4:
- return (readl(&clk_power->camdivn) & (1 << 9)) ?
- get_FCLK() / 8 : get_FCLK() / 4;
- case 6:
- return (readl(&clk_power->camdivn) & (1 << 8)) ?
- get_FCLK() / 6 : get_FCLK() / 3;
- }
-#else
- return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
-#endif
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
- return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
- return get_PLLCLK(UPLL);
-}
-
-#endif /* CONFIG_S3C24X0 */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c
deleted file mode 100644
index ba1e616..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#ifdef CONFIG_S3C24X0
-
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init(void)
-{
- struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- ulong tmr;
-
- /* use PWM Timer 4 because it has no output */
- /* prescaler for Timer 4 is 16 */
- writel(0x0f00, &timers->tcfg0);
- if (gd->arch.tbu == 0) {
- /*
- * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
- * (default) and prescaler = 16. Should be 10390
- * @33.25MHz and 15625 @ 50 MHz
- */
- gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
- gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
- }
- /* load value for 10 ms timeout */
- writel(gd->arch.tbu, &timers->tcntb4);
- /* auto load, manual update of timer 4 */
- tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
- writel(tmr, &timers->tcon);
- /* auto load, start timer 4 */
- tmr = (tmr & ~0x0700000) | 0x0500000;
- writel(tmr, &timers->tcon);
- gd->arch.lastinc = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay (unsigned long usec)
-{
- ulong tmo;
- ulong start = get_ticks();
-
- tmo = usec / 1000;
- tmo *= (gd->arch.tbu * 100);
- tmo /= 1000;
-
- while ((ulong) (get_ticks() - start) < tmo)
- /*NOP*/;
-}
-
-ulong get_timer_masked(void)
-{
- ulong tmr = get_ticks();
-
- return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
-}
-
-void udelay_masked(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= (gd->arch.tbu * 100);
- tmo /= 1000;
- } else {
- tmo = usec * (gd->arch.tbu * 100);
- tmo /= (1000 * 1000);
- }
-
- endtime = get_ticks() + tmo;
-
- do {
- ulong now = get_ticks();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- ulong now = readl(&timers->tcnto4) & 0xffff;
-
- if (gd->arch.lastinc >= now) {
- /* normal mode */
- gd->arch.tbl += gd->arch.lastinc - now;
- } else {
- /* we have an overflow ... */
- gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
- }
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
-
-/*
- * reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu(ulong ignored)
-{
- struct s3c24x0_watchdog *watchdog;
-
- watchdog = s3c24x0_get_base_watchdog();
-
- /* Disable watchdog */
- writel(0x0000, &watchdog->wtcon);
-
- /* Initialize watchdog timer count register */
- writel(0x0001, &watchdog->wtcnt);
-
- /* Enable watchdog timer; assert reset at timer timeout */
- writel(0x0021, &watchdog->wtcon);
-
- while (1)
- /* loop forever and wait for reset to happen */;
-
- /*NOTREACHED*/
-}
-
-#endif /* CONFIG_S3C24X0 */
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 0740450..e9326f4 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -1,11 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM920 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
@@ -50,43 +49,6 @@
bne copyex
#endif
-#ifdef CONFIG_S3C24X0
- /* turn off the watchdog */
-
-# if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
-# define CLKDIVN 0x14800014 /* clock divisor register */
-#else
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
-# define INTSUBMSK 0x4A00001C
-# define CLKDIVN 0x4C000014 /* clock divisor register */
-# endif
-
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =INTMSK
- str r1, [r0]
-# if defined(CONFIG_S3C2410)
- ldr r1, =0x3ff
- ldr r0, =INTSUBMSK
- str r1, [r0]
-# endif
-
- /* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #3
- str r1, [r0]
-#endif /* CONFIG_S3C24X0 */
-
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
@@ -131,10 +93,11 @@
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00000002 @ set bit 1 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
@@ -143,7 +106,7 @@
mov ip, lr
bl lowlevel_init
-
mov lr, ip
+#endif
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index adcea9f..fdb0c92 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-y = start.o
obj-y = cpu.o cache.o
@@ -15,16 +13,19 @@
endif
obj-$(CONFIG_ARMADA100) += armada100/
-obj-$(CONFIG_AT91FAMILY) += at91/
-obj-$(CONFIG_ARCH_DAVINCI) += davinci/
-obj-$(CONFIG_KIRKWOOD) += kirkwood/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
-obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
-obj-$(CONFIG_ORION5X) += orion5x/
-obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
-obj-$(CONFIG_ARCH_VERSATILE) += versatile/
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
+
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
index fca98ef..77ac0e2 100644
--- a/arch/arm/cpu/arm926ejs/armada100/Makefile
+++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
index 8b02d0b..4cd8511 100644
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
index 8d7c71f..f4e1f0d 100644
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
* Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -72,7 +71,6 @@
}
}
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
int dram_init(void)
{
int i;
@@ -109,8 +107,9 @@
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
dram_init();
+
+ return 0;
}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
index bbd0505..d2ecbd0 100644
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -62,7 +61,7 @@
return(readl(&armd1timers->cvwr));
}
-ulong get_timer_masked(void)
+static ulong get_timer_masked(void)
{
ulong now = read_timer();
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile
deleted file mode 100644
index 698a28d..0000000
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_AT91CAP9) += at91cap9_devices.o
-obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o
-obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o
-obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
-obj-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
-obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
-obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
-obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
-obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
-obj-$(CONFIG_AT91_EFLASH) += eflash.o
-obj-$(CONFIG_AT91_LED) += led.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += reset.o
-obj-y += timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
deleted file mode 100644
index 16eeca7..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
- writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
- writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
- writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
- at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
- at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
- at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
- }
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
-
- /* Enable clock */
- writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
deleted file mode 100644
index efb53d6..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
- }
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- /* Enable EMAC clock */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
- /*
- * use PA10, PA11 for ETX2, ETX3.
- * PA23 and PA24 are for TWI EEPROM
- */
- at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
-#else
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
-#if defined(CONFIG_AT91SAM9G20)
- /* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
-#endif
-#endif
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
-#endif
-}
-#endif
-
-#if defined(CONFIG_GENERIC_ATMEL_MCI)
-void at91_mci_hw_init(void)
-{
- /* Enable mci clock */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_MCI, &pmc->pcer);
-
- at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
-#if defined(CONFIG_ATMEL_MCI_PORTB)
- at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
- at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */
- at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */
- at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */
- at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */
-#else
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */
-#endif
-}
-#endif
-
-void at91_sdram_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
-}
-
-/* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
- { ATMEL_BASE_PIOA, "PA" },
- { ATMEL_BASE_PIOB, "PB" },
- { ATMEL_BASE_PIOC, "PC" },
-};
-
-U_BOOT_DEVICES(at91sam9260_gpios) = {
- { "gpio_at91", &at91sam9260_plat[0] },
- { "gpio_at91", &at91sam9260_plat[1] },
- { "gpio_at91", &at91sam9260_plat[2] },
-};
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
deleted file mode 100644
index a445c75..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
- }
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
deleted file mode 100644
index 6b51d5f..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
- }
-}
-#endif
-
-#if defined(CONFIG_GENERIC_ATMEL_MCI)
-void at91_mci_hw_init(void)
-{
- /* Enable mci clock */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
-
- at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
-
-#if defined(CONFIG_ATMEL_MCI_PORTB)
- at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
- at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
- at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
- at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
-#else
- at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
- at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
-#endif
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */
- at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_USB_OHCI_NEW
-void at91_uhp_hw_init(void)
-{
- /* Enable VBus on UHP ports */
- at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
- at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
deleted file mode 100644
index 0e6c0da..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
- }
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
-#ifndef CONFIG_RMII
- at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void at91_mci_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
deleted file mode 100644
index 39f17a1..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2013 Atmel Corporation
- * Josh Wu <josh.wu@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-unsigned int has_lcdc()
-{
- return 1;
-}
-
-void at91_serial0_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
- writel(1 << ATMEL_ID_USART3, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
- if (cs_mask & (1 << 1))
- at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
- if (cs_mask & (1 << 2))
- at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
- if (cs_mask & (1 << 3))
- at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
- if (cs_mask & (1 << 1))
- at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
- if (cs_mask & (1 << 2))
- at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
- if (cs_mask & (1 << 3))
- at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
-}
-#endif
-
-void at91_mci_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
-
- writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
-}
-
-#ifdef CONFIG_LCD
-void at91_lcd_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
- at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
-
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
deleted file mode 100644
index 0ec32c3..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
- }
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
deleted file mode 100644
index 6d94572..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Copyright (C) 2012 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-unsigned int get_chip_id(void)
-{
- /* The 0x40 is the offset of cidr in DBGU */
- return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
-}
-
-unsigned int get_extension_chip_id(void)
-{
- /* The 0x44 is the offset of exid in DBGU */
- return readl(ATMEL_BASE_DBGU + 0x44);
-}
-
-unsigned int has_emac1()
-{
- return cpu_is_at91sam9x25();
-}
-
-unsigned int has_emac0()
-{
- return !(cpu_is_at91sam9g15());
-}
-
-unsigned int has_lcdc()
-{
- return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35();
-}
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_at91sam9x5()) {
- switch (extension_id) {
- case ARCH_EXID_AT91SAM9G15:
- return "AT91SAM9G15";
- case ARCH_EXID_AT91SAM9G25:
- return "AT91SAM9G25";
- case ARCH_EXID_AT91SAM9G35:
- return "AT91SAM9G35";
- case ARCH_EXID_AT91SAM9X25:
- return "AT91SAM9X25";
- case ARCH_EXID_AT91SAM9X35:
- return "AT91SAM9X35";
- default:
- return "Unknown CPU type";
- }
- } else {
- return "Unknown CPU type";
- }
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
-
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
-
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
-
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
-
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_mci_hw_init(void)
-{
- /* Initialize the MCI0 */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
-
- /* Enable clock for MCI0 */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
- if (cs_mask & (1 << 1))
- at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
- if (cs_mask & (1 << 2))
- at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
- if (cs_mask & (1 << 3))
- at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
- if (cs_mask & (1 << 4))
- at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
- if (cs_mask & (1 << 5))
- at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
- if (cs_mask & (1 << 6))
- at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
- if (cs_mask & (1 << 7))
- at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
- if (cs_mask & (1 << 1))
- at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
- if (cs_mask & (1 << 2))
- at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
- if (cs_mask & (1 << 3))
- at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
- if (cs_mask & (1 << 4))
- at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
- if (cs_mask & (1 << 5))
- at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
- if (cs_mask & (1 << 6))
- at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
- if (cs_mask & (1 << 7))
- at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
-}
-#endif
-
-#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
-void at91_uhp_hw_init(void)
-{
- /* Enable VBus on UHP ports */
- at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
- at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
-#if defined(CONFIG_USB_OHCI_NEW)
- /* port C is OHCI only */
- at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
-#endif
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- if (has_emac0()) {
- /* Enable EMAC0 clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
- /* EMAC0 pins setup */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
- }
-
- if (has_emac1()) {
- /* Enable EMAC1 clock */
- writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
- /* EMAC1 pins setup */
- at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
- at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
- at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
- at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
- at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
- at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
- }
-
-#ifndef CONFIG_RMII
- /* Only emac0 support MII */
- if (has_emac0()) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
- }
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
deleted file mode 100644
index f363982..0000000
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
- case AT91_PMC_MCKR_CSS_MAIN:
- return gd->arch.main_clk_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLA:
- return gd->arch.plla_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLB:
- return gd->arch.pllb_rate_hz;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
-#if defined(CONFIG_AT91SAM9G20)
- if (input < 2000000)
- continue;
-#endif
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
-#if defined(CONFIG_AT91SAM9G20)
- if (mul > 63)
- continue;
-#endif
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 16) & 0x7ff;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
- unsigned freq, mckr;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
- unsigned tmp;
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = readl(&pmc->mcfr);
- } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
- tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
- }
-#endif
- gd->arch.main_clk_rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
- AT91_PMC_PLLBR_USBDIV_2;
- gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
- gd->arch.at91_pllb_usb_init);
-#endif
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = readl(&pmc->mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
- /* plla divisor by 2 */
- gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
-#endif
- gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->arch.mck_rate_hz;
-
- freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
-#if defined(CONFIG_AT91SAM9G20)
- /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
- freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
- if (mckr & AT91_PMC_MCKR_MDIV_MASK)
- freq /= 2; /* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
- /* mdiv <==> divisor
- * 0 <==> 1
- * 1 <==> 2
- * 2 <==> 4
- * 3 <==> 3
- */
- gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
- (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
- ? freq / 3
- : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#else
- gd->arch.mck_rate_hz = freq /
- (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#endif
- gd->arch.cpu_clk_rate_hz = freq;
-
- return 0;
-}
-
-#if !defined(AT91_PLL_LOCK_TIMEOUT)
-#define AT91_PLL_LOCK_TIMEOUT 1000000
-#endif
-
-void at91_plla_init(u32 pllar)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
-
- writel(pllar, &pmc->pllar);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
-}
-void at91_pllb_init(u32 pllbr)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
-
- writel(pllbr, &pmc->pllbr);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
-}
-
-void at91_mck_init(u32 mckr)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
- u32 tmp;
-
- tmp = readl(&pmc->mckr);
- tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
- tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
- writel(tmp, &pmc->mckr);
-
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
- timeout--;
- if (timeout == 0)
- break;
- }
-}
-
-void at91_periph_clk_enable(int id)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- writel(1 << id, &pmc->pcer);
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk
deleted file mode 100644
index 370630d..0000000
--- a/arch/arm/cpu/arm926ejs/at91/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE)
diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c
deleted file mode 100644
index da1d359..0000000
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_gpbr.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-void arch_preboot_os(void)
-{
- ulong cpiv;
- at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
-
- cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
-
- /*
- * Disable PITC
- * Add 0x1000 to current counter to stop it faster
- * without waiting for wrapping back to 0
- */
- writel(cpiv + 0x1000, &pit->mr);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- char buf[32];
-
- printf("CPU: %s\n", ATMEL_CPU_NAME);
- printf("Crystal frequency: %8s MHz\n",
- strmhz(buf, get_main_clk_rate()));
- printf("CPU clock : %8s MHz\n",
- strmhz(buf, get_cpu_clk_rate()));
- printf("Master clock : %8s MHz\n",
- strmhz(buf, get_mck_clk_rate()));
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c
deleted file mode 100644
index 3f39264..0000000
--- a/arch/arm/cpu/arm926ejs/at91/eflash.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * this driver supports the enhanced embedded flash in the Atmel
- * AT91SAM9XE devices with the following geometry:
- *
- * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages)
- * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages)
- * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages)
- * (the exact geometry is read from the flash at runtime, so any
- * future devices should already be covered)
- *
- * Regions can be write/erase protected.
- * Whole (!) pages can be individually written with erase on the fly.
- * Writing partial pages will corrupt the rest of the page.
- *
- * The flash is presented to u-boot with each region being a sector,
- * having the following effects:
- * Each sector can be hardware protected (protect on/off).
- * Each page in a sector can be rewritten anytime.
- * Since pages are erased when written, the "erase" does nothing.
- * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected
- * by u-Boot commands.
- *
- * Note: Redundant environment will not work in this flash since
- * it does use partial page writes. Make sure the environment spans
- * whole pages!
- */
-
-/*
- * optional TODOs (nice to have features):
- *
- * make the driver coexist with other NOR flash drivers
- * (use an index into flash_info[], requires work
- * in those other drivers, too)
- * Make the erase command fill the sectors with 0xff
- * (if the flashes grow larger in the future and
- * someone puts a jffs2 into them)
- * do a read-modify-write for partially programmed pages
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_eefc.h>
-#include <asm/arch/at91_dbu.h>
-
-/* checks to detect configuration errors */
-#if CONFIG_SYS_MAX_FLASH_BANKS!=1
-#error eflash: this driver can only handle 1 bank
-#endif
-
-/* global structure */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-static u32 pagesize;
-
-unsigned long flash_init (void)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
- at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU;
- u32 id, size, nplanes, planesize, nlocks;
- u32 addr, i, tmp=0;
-
- debug("eflash: init\n");
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
-
- /* check if its an AT91ARM9XE SoC */
- if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) {
- puts("eflash: not an AT91SAM9XE\n");
- return 0;
- }
-
- /* now query the eflash for its structure */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- id = readl(&eefc->frr); /* word 0 */
- size = readl(&eefc->frr); /* word 1 */
- pagesize = readl(&eefc->frr); /* word 2 */
- nplanes = readl(&eefc->frr); /* word 3 */
- planesize = readl(&eefc->frr); /* word 4 */
- debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n",
- id, size, pagesize, nplanes, planesize);
- for (i=1; i<nplanes; i++) {
- tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */
- };
- nlocks = readl(&eefc->frr); /* word 4+nplanes */
- debug("nlocks=%u\n", nlocks);
- /* since we are going to use the lock regions as sectors, check count */
- if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) {
- printf("eflash: number of lock regions(%u) "\
- "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n",
- nlocks);
- nlocks = CONFIG_SYS_MAX_FLASH_SECT;
- }
- flash_info[0].size = size;
- flash_info[0].sector_count = nlocks;
- flash_info[0].flash_id = id;
-
- addr = ATMEL_BASE_FLASH;
- for (i=0; i<nlocks; i++) {
- tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */
- flash_info[0].start[i] = addr;
- flash_info[0].protect[i] = 0;
- addr += tmp;
- };
-
- /* now read the protection information for all regions */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- for (i=0; i<flash_info[0].sector_count; i++) {
- if (i%32 == 0)
- tmp = readl(&eefc->frr);
- flash_info[0].protect[i] = (tmp >> (i%32)) & 1;
-#if defined(CONFIG_EFLASH_PROTSECTORS)
- if (i < CONFIG_EFLASH_PROTSECTORS)
- flash_info[0].protect[i] = 1;
-#endif
- }
-
- return size;
-}
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- puts("AT91SAM9XE embedded flash\n Size: ");
- print_size(info->size, " in ");
- printf("%d Sectors\n", info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
- u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize;
- u32 i, tmp=0;
-
- debug("protect sector=%ld prot=%d\n", sector, prot);
-
-#if defined(CONFIG_EFLASH_PROTSECTORS)
- if (sector < CONFIG_EFLASH_PROTSECTORS) {
- if (!prot) {
- printf("eflash: sector %lu cannot be unprotected\n",
- sector);
- }
- return 1; /* return anyway, caller does not care for result */
- }
-#endif
- if (prot) {
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- } else {
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- }
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- /* now re-read the protection information for all regions */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- for (i=0; i<info->sector_count; i++) {
- if (i%32 == 0)
- tmp = readl(&eefc->frr);
- info->protect[i] = (tmp >> (i%32)) & 1;
- }
- return 0;
-}
-
-static u32 erase_write_page (u32 pagenum)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
-
- debug("erase+write page=%u\n", pagenum);
-
- /* give erase and write page command */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- /* return status */
- return readl(&eefc->fsr)
- & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE);
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- debug("erase first=%d last=%d\n", s_first, s_last);
- puts("this flash does not need and support erasing!\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- u32 pagenum;
- u32 *src32, *dst32;
- u32 i;
-
- debug("write src=%08lx addr=%08lx cnt=%lx\n",
- (ulong)src, addr, cnt);
-
- /* REQUIRE addr to be on a page start, abort if not */
- if (addr % pagesize) {
- printf ("eflash: start %08lx is not on page start\n"\
- " write aborted\n", addr);
- return 1;
- }
-
- /* now start copying data */
- pagenum = (addr-ATMEL_BASE_FLASH)/pagesize;
- src32 = (u32 *) src;
- dst32 = (u32 *) addr;
- while (cnt > 0) {
- i = pagesize / 4;
- /* fill page buffer */
- while (i--)
- *dst32++ = *src32++;
- /* write page */
- if (erase_write_page(pagenum))
- return 1;
- pagenum++;
- if (cnt > pagesize)
- cnt -= pagesize;
- else
- cnt = 0;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
deleted file mode 100644
index b8d5c78..0000000
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <status_led.h>
-
-#ifdef CONFIG_RED_LED
-void red_led_on(void)
-{
- gpio_set_value(CONFIG_RED_LED, 1);
-}
-
-void red_led_off(void)
-{
- gpio_set_value(CONFIG_RED_LED, 0);
-}
-#endif
-
-#ifdef CONFIG_GREEN_LED
-void green_led_on(void)
-{
- gpio_set_value(CONFIG_GREEN_LED, 0);
-}
-
-void green_led_off(void)
-{
- gpio_set_value(CONFIG_GREEN_LED, 1);
-}
-#endif
-
-#ifdef CONFIG_YELLOW_LED
-void yellow_led_on(void)
-{
- gpio_set_value(CONFIG_YELLOW_LED, 0);
-}
-
-void yellow_led_off(void)
-{
- gpio_set_value(CONFIG_YELLOW_LED, 1);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
deleted file mode 100644
index a9ec81a..0000000
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_rstc.h>
-#ifdef CONFIG_ATMEL_LEGACY
-#include <asm/arch/at91sam9_matrix.h>
-#endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
-#endif
-
-.globl lowlevel_init
-.type lowlevel_init,function
-lowlevel_init:
-
-POS1:
- adr r5, POS1 /* r5 = POS1 run time */
- ldr r0, =POS1 /* r0 = POS1 compile */
- sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
-
- /* memory control configuration 1 */
- ldr r0, =SMRDATA
- ldr r2, =SMRDATA1
- add r0, r0, r5
- add r2, r2, r5
-0:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 0b
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 1.
- * ----------------------------------------------------------------------------
- * - Check if the PLL is already initialized
- * ----------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_MCKR)
- ldr r0, [r1]
- and r0, r0, #3
- cmp r0, #0
- bne PLL_setup_end
-
-/* ---------------------------------------------------------------------------
- * - Enable the Main Oscillator
- * ---------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_MOR)
- ldr r2, =(AT91_ASM_PMC_SR)
- /* Main oscillator Enable register PMC_MOR: */
- ldr r0, =CONFIG_SYS_MOR_VAL
- str r0, [r1]
-
- /* Reading the PMC Status to detect when the Main Oscillator is enabled */
- mov r4, #AT91_PMC_IXR_MOSCS
-MOSCS_Loop:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_MOSCS
- bne MOSCS_Loop
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 2.
- * ----------------------------------------------------------------------------
- * Setup PLLA
- * ----------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_PLLAR)
- ldr r0, =CONFIG_SYS_PLLAR_VAL
- str r0, [r1]
-
- /* Reading the PMC Status register to detect when the PLLA is locked */
- mov r4, #AT91_PMC_IXR_LOCKA
-MOSCS_Loop1:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_LOCKA
- bne MOSCS_Loop1
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 3.
- * ----------------------------------------------------------------------------
- * - Switch on the Main Oscillator
- * ----------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_MCKR)
-
- /* -Master Clock Controller register PMC_MCKR */
- ldr r0, =CONFIG_SYS_MCKR1_VAL
- str r0, [r1]
-
- /* Reading the PMC Status to detect when the Master clock is ready */
- mov r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_MCKRDY
- bne MCKRDY_Loop
-
- ldr r0, =CONFIG_SYS_MCKR2_VAL
- str r0, [r1]
-
- /* Reading the PMC Status to detect when the Master clock is ready */
- mov r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop1:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_MCKRDY
- bne MCKRDY_Loop1
-PLL_setup_end:
-
-/* ----------------------------------------------------------------------------
- * - memory control configuration 2
- * ----------------------------------------------------------------------------
- */
- ldr r0, =(AT91_ASM_SDRAMC_TR)
- ldr r1, [r0]
- cmp r1, #0
- bne SDRAM_setup_end
-
- ldr r0, =SMRDATA1
- ldr r2, =SMRDATA2
- add r0, r0, r5
- add r2, r2, r5
-2:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 2b
-
-SDRAM_setup_end:
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-
-SMRDATA:
- .word AT91_ASM_WDT_MR
- .word CONFIG_SYS_WDTC_WDMR_VAL
- /* configure PIOx as EBI0 D[16-31] */
-#if defined(CONFIG_AT91SAM9263)
- .word AT91_ASM_PIOD_PDR
- .word CONFIG_SYS_PIOD_PDR_VAL1
- .word AT91_ASM_PIOD_PUDR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
- .word AT91_ASM_PIOD_ASR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
- || defined(CONFIG_AT91SAM9G20)
- .word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL1
- .word AT91_ASM_PIOC_PUDR
- .word CONFIG_SYS_PIOC_PPUDR_VAL
-#endif
- .word AT91_ASM_MATRIX_CSA0
- .word CONFIG_SYS_MATRIX_EBICSA_VAL
-
- /* flash */
- .word AT91_ASM_SMC_MODE0
- .word CONFIG_SYS_SMC0_MODE0_VAL
-
- .word AT91_ASM_SMC_CYCLE0
- .word CONFIG_SYS_SMC0_CYCLE0_VAL
-
- .word AT91_ASM_SMC_PULSE0
- .word CONFIG_SYS_SMC0_PULSE0_VAL
-
- .word AT91_ASM_SMC_SETUP0
- .word CONFIG_SYS_SMC0_SETUP0_VAL
-
-SMRDATA1:
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
- .word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL1
- .word AT91_ASM_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
- .word AT91_ASM_SDRAMC_MDR
- .word CONFIG_SYS_SDRC_MDR_VAL
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL1
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL6
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL7
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL8
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL9
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL10
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL11
- .word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL12
- /* User reset enable*/
- .word AT91_ASM_RSTC_MR
- .word CONFIG_SYS_RSTC_RMR_VAL
-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
- /* MATRIX_MCFG - REMAP all masters */
- .word AT91_ASM_MATRIX_MCFG
- .word 0x1FF
-#endif
-SMRDATA2:
- .word 0
diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c
deleted file mode 100644
index e67f47b..0000000
--- a/arch/arm/cpu/arm926ejs/at91/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-
-/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
-{
- at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
-
- writel(AT91_RSTC_KEY
- | AT91_RSTC_CR_PROCRST /* Processor Reset */
- | AT91_RSTC_CR_PERRST /* Peripheral Reset */
-#ifdef CONFIG_AT91RESET_EXTRST
- | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
-#endif
- , &rstc->cr);
- /* never reached */
- while (1)
- ;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
deleted file mode 100644
index b0b7fb9..0000000
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <div64.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- * (See the relevant data sheets to understand that this really works)
- *
- * We do also mimic the typical powerpc way of incrementing
- * two 32 bit registers called tbl and tbu.
- *
- * Those registers increment at 1/16 the main clock rate.
- */
-
-#define TIMER_LOAD_VAL 0xfffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/*
- * Use the PITC in full 32 bit incrementing mode
- */
-int timer_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
-
- /* Enable PITC Clock */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-
- /* Enable PITC */
- writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
- gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
-
- ulong now = readl(&pit->piir);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 8d7873c..22a55f5 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -1,18 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011
* Ilya Yanok, EmCraft Systems
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/types.h>
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -29,23 +23,6 @@
);
}
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
- int ok = 1;
-
- if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
- ok = 0;
-
- if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
- ok = 0;
-
- if (!ok)
- debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
- start, stop);
-
- return ok;
-}
-
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
if (!check_cache_range(start, stop))
@@ -69,11 +46,6 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -82,21 +54,37 @@
void flush_dcache_all(void)
{
}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
/*
* Stub implementations for l2 cache operations
*/
+
__weak void l2_cache_disable(void) {}
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+__weak void invalidate_l2_cache(void) {}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+/* Invalidate entire I-cache and branch predictor array */
+void invalidate_icache_all(void)
+{
+ unsigned long i = 0;
+
+ asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+#else
+void invalidate_icache_all(void) {}
+#endif
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
deleted file mode 100644
index bdb3da1..0000000
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv5te
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index e37e87b..c3f1ee1 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -5,8 +6,6 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
@@ -45,7 +44,9 @@
/* flush I/D-cache */
static void cache_flush (void)
{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+#endif
}
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
deleted file mode 100644
index 613f04d..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/Kconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-if ARCH_DAVINCI
-
-choice
- prompt "DaVinci board select"
-
-config TARGET_ENBW_CMC
- bool "EnBW CMC board"
-
-config TARGET_IPAM390
- bool "IPAM390 board"
- select SUPPORT_SPL
-
-config TARGET_DA830EVM
- bool "DA830 EVM board"
-
-config TARGET_DA850EVM
- bool "DA850 EVM board"
- select SUPPORT_SPL
-
-config TARGET_CAM_ENC_4XX
- bool "CAM ENC 4xx board"
- select SUPPORT_SPL
-
-config TARGET_HAWKBOARD
- bool "Hawkboard"
- select SUPPORT_SPL
-
-config TARGET_DAVINCI_DM355EVM
- bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
- bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
- bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
- bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
- bool "DVEVM board"
-
-config TARGET_EA20
- bool "EA20 board"
-
-config TARGET_DAVINCI_SCHMOOGIE
- bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
- bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
- bool "Sonata board"
-
-config TARGET_CALIMAIN
- bool "Calimain board"
-
-endchoice
-
-config SYS_SOC
- default "davinci"
-
-source "board/enbw/enbw_cmc/Kconfig"
-source "board/ait/cam_enc_4xx/Kconfig"
-source "board/Barix/ipam390/Kconfig"
-source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
-source "board/omicron/calimain/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
deleted file mode 100644
index 7d67191..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o
-obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
-obj-$(CONFIG_SOC_DM355) += dm355.o
-obj-$(CONFIG_SOC_DM365) += dm365.o
-obj-$(CONFIG_SOC_DM644X) += dm644x.o
-obj-$(CONFIG_SOC_DM646X) += dm646x.o
-obj-$(CONFIG_SOC_DA830) += da830_pinmux.o
-obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
-obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
-obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
-obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
-endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk
deleted file mode 100644
index 69e9d5a..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
deleted file mode 100644
index ff61147..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL 0x100
-#define PLLC_PLLM 0x110
-#define PLLC_PREDIV 0x114
-#define PLLC_PLLDIV1 0x118
-#define PLLC_PLLDIV2 0x11c
-#define PLLC_PLLDIV3 0x120
-#define PLLC_POSTDIV 0x128
-#define PLLC_BPDIV 0x12c
-#define PLLC_PLLDIV4 0x160
-#define PLLC_PLLDIV5 0x164
-#define PLLC_PLLDIV6 0x168
-#define PLLC_PLLDIV7 0x16c
-#define PLLC_PLLDIV8 0x170
-#define PLLC_PLLDIV9 0x174
-
-#define BIT(x) (1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-unsigned int sysdiv[9] = {
- PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
- PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
- int pre_div;
- int pllm;
- int post_div;
- int pll_out;
- unsigned int pll_base;
-
- pll_out = CONFIG_SYS_OSCIN_FREQ;
-
- if (id == DAVINCI_AUXCLK_CLKID)
- goto out;
-
- if ((id >> 16) == 1)
- pll_base = (unsigned int)davinci_pllc1_regs;
- else
- pll_base = (unsigned int)davinci_pllc0_regs;
-
- id &= 0xFFFF;
-
- /*
- * Lets keep this simple. Combining operations can result in
- * unexpected approximations
- */
- pre_div = (readl(pll_base + PLLC_PREDIV) &
- DAVINCI_PLLC_DIV_MASK) + 1;
- pllm = readl(pll_base + PLLC_PLLM) + 1;
-
- pll_out /= pre_div;
- pll_out *= pllm;
-
- if (id == DAVINCI_PLLM_CLKID)
- goto out;
-
- post_div = (readl(pll_base + PLLC_POSTDIV) &
- DAVINCI_PLLC_DIV_MASK) + 1;
-
- pll_out /= post_div;
-
- if (id == DAVINCI_PLLC_CLKID)
- goto out;
-
- pll_out /= (readl(pll_base + sysdiv[id - 1]) &
- DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
- return pll_out;
-}
-
-int set_cpu_clk_info(void)
-{
- gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
- /* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
- (clk_get(DAVINCI_DDR_CLKID) / 1000000);
- gd->bd->bi_dsp_freq = 0;
- return 0;
-}
-
-#else /* CONFIG_SOC_DA8XX */
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
- u32 div;
-
- div = REG(pllbase + offset);
- return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
- /* this register read seems to fail on pll0 */
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return 8;
- else
- return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_PREDIV);
-#endif
- return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return pll_div(pllbase, PLLC_POSTDIV);
-#endif
- return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
- volatile void *pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
- unsigned base = CONFIG_REFCLK_FREQ / 1000;
-#else
- unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
- /* the PLL might be bypassed */
- if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
- base /= pll_prediv(pllbase);
-#if defined(CONFIG_SOC_DM365)
- base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
-#else
- base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-#endif
- base /= pll_postdiv(pllbase);
- }
- return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
-#endif
-
-int set_cpu_clk_info(void)
-{
- unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#if defined(CONFIG_SOC_DM365)
- pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#endif
- gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
-
-#ifdef DSP_PLLDIV
- gd->bd->bi_dsp_freq =
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
-#else
- gd->bd->bi_dsp_freq = 0;
-#endif
-
- pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#if defined(CONFIG_SOC_DM365)
- pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#endif
- gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-
- return 0;
-}
-
-#endif /* !CONFIG_SOC_DA8XX */
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_DRIVER_TI_EMAC)
- davinci_emac_initialize();
-#endif
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
deleted file mode 100644
index edaab45..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Pinmux configurations for the DA830 SoCs
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI0 pin muxer settings */
-const struct pinmux_config spi0_pins_base[] = {
- { pinmux(7), 1, 3 }, /* SPI0_SOMI */
- { pinmux(7), 1, 4 }, /* SPI0_SIMO */
- { pinmux(7), 1, 6 } /* SPI0_CLK */
-};
-
-const struct pinmux_config spi0_pins_scs0[] = {
- { pinmux(7), 1, 7 } /* SPI0_SCS[0] */
-};
-
-const struct pinmux_config spi0_pins_ena[] = {
- { pinmux(7), 1, 5 } /* SPI0_ENA */
-};
-
-/* NAND pin muxer settings */
-const struct pinmux_config emifa_pins_cs0[] = {
- { pinmux(18), 1, 2 } /* EMA_CS[0] */
-};
-
-const struct pinmux_config emifa_pins_cs2[] = {
- { pinmux(18), 1, 3 } /* EMA_CS[2] */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
- { pinmux(18), 1, 4 } /* EMA_CS[3] */
-};
-
-#ifdef CONFIG_USE_NAND
-const struct pinmux_config emifa_pins[] = {
- { pinmux(13), 1, 6 }, /* EMA_D[0] */
- { pinmux(13), 1, 7 }, /* EMA_D[1] */
- { pinmux(14), 1, 0 }, /* EMA_D[2] */
- { pinmux(14), 1, 1 }, /* EMA_D[3] */
- { pinmux(14), 1, 2 }, /* EMA_D[4] */
- { pinmux(14), 1, 3 }, /* EMA_D[5] */
- { pinmux(14), 1, 4 }, /* EMA_D[6] */
- { pinmux(14), 1, 5 }, /* EMA_D[7] */
- { pinmux(14), 1, 6 }, /* EMA_D[8] */
- { pinmux(14), 1, 7 }, /* EMA_D[9] */
- { pinmux(15), 1, 0 }, /* EMA_D[10] */
- { pinmux(15), 1, 1 }, /* EMA_D[11] */
- { pinmux(15), 1, 2 }, /* EMA_D[12] */
- { pinmux(15), 1, 3 }, /* EMA_D[13] */
- { pinmux(15), 1, 4 }, /* EMA_D[14] */
- { pinmux(15), 1, 5 }, /* EMA_D[15] */
- { pinmux(15), 1, 6 }, /* EMA_A[0] */
- { pinmux(15), 1, 7 }, /* EMA_A[1] */
- { pinmux(16), 1, 0 }, /* EMA_A[2] */
- { pinmux(16), 1, 1 }, /* EMA_A[3] */
- { pinmux(16), 1, 2 }, /* EMA_A[4] */
- { pinmux(16), 1, 3 }, /* EMA_A[5] */
- { pinmux(16), 1, 4 }, /* EMA_A[6] */
- { pinmux(16), 1, 5 }, /* EMA_A[7] */
- { pinmux(16), 1, 6 }, /* EMA_A[8] */
- { pinmux(16), 1, 7 }, /* EMA_A[9] */
- { pinmux(17), 1, 0 }, /* EMA_A[10] */
- { pinmux(17), 1, 1 }, /* EMA_A[11] */
- { pinmux(17), 1, 2 }, /* EMA_A[12] */
- { pinmux(17), 1, 3 }, /* EMA_BA[1] */
- { pinmux(17), 1, 4 }, /* EMA_BA[0] */
- { pinmux(17), 1, 5 }, /* EMA_CLK */
- { pinmux(17), 1, 6 }, /* EMA_SDCKE */
- { pinmux(17), 1, 7 }, /* EMA_CAS */
- { pinmux(18), 1, 0 }, /* EMA_CAS */
- { pinmux(18), 1, 1 }, /* EMA_WE */
- { pinmux(18), 1, 5 }, /* EMA_OE */
- { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */
- { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */
- { pinmux(10), 1, 0 } /* Tristate */
-};
-#endif
-
-/* EMAC PHY interface pins */
-const struct pinmux_config emac_pins_rmii[] = {
- { pinmux(10), 2, 1 }, /* RMII_TXD[0] */
- { pinmux(10), 2, 2 }, /* RMII_TXD[1] */
- { pinmux(10), 2, 3 }, /* RMII_TXEN */
- { pinmux(10), 2, 4 }, /* RMII_CRS_DV */
- { pinmux(10), 2, 5 }, /* RMII_RXD[0] */
- { pinmux(10), 2, 6 }, /* RMII_RXD[1] */
- { pinmux(10), 2, 7 } /* RMII_RXER */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
- { pinmux(11), 2, 0 }, /* MDIO_CLK */
- { pinmux(11), 2, 1 } /* MDIO_D */
-};
-
-const struct pinmux_config emac_pins_rmii_clk_source[] = {
- { pinmux(9), 0, 5 } /* ref.clk from external source */
-};
-
-/* UART2 pin muxer settings */
-const struct pinmux_config uart2_pins_txrx[] = {
- { pinmux(8), 2, 7 }, /* UART2_RXD */
- { pinmux(9), 2, 0 } /* UART2_TXD */
-};
-
-/* I2C0 pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
- { pinmux(8), 2, 3 }, /* I2C0_SDA */
- { pinmux(8), 2, 4 } /* I2C0_SCL */
-};
-
-/* USB0_DRVVBUS pin muxer settings */
-const struct pinmux_config usb_pins[] = {
- { pinmux(9), 1, 1 } /* USB0_DRVVBUS */
-};
-
-#ifdef CONFIG_DAVINCI_MMC
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins_8bit[] = {
- { pinmux(15), 2, 7 }, /* MMCSD0_CLK */
- { pinmux(16), 2, 0 }, /* MMCSD0_CMD */
- { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
- { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
- { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
- { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
- { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
- { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
- { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
- { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */
- /* DA830 supports 8-bit mode */
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
deleted file mode 100644
index 19730ce..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * SoC-specific lowlevel code for DA850
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/pll_defs.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-#if defined(CONFIG_SYS_DA850_PLL_INIT)
-static void da850_waitloop(unsigned long loopcnt)
-{
- unsigned long i;
-
- for (i = 0; i < loopcnt; i++)
- asm(" NOP");
-}
-
-static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
-{
- if (reg == davinci_pllc0_regs)
- /* Unlock PLL registers. */
- clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
-
- /*
- * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
- /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
- clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(®->pllctl, PLLCTL_PLLEN);
-
- da850_waitloop(150);
-
- if (reg == davinci_pllc0_regs) {
- /*
- * Select the Clock Mode bit 8 as External Clock or On Chip
- * Oscilator
- */
- dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
- setbits_le32(®->pllctl,
- (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
- }
-
- /* Clear PLLRST bit to reset the PLL */
- clrbits_le32(®->pllctl, PLLCTL_PLLRST);
-
- /* Disable the PLL output */
- setbits_le32(®->pllctl, PLLCTL_PLLDIS);
-
- /* PLL initialization sequence */
- /*
- * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
- * power down bit
- */
- clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
-
- /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
- clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
-
-#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
- /* program the prediv */
- if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
- writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
- ®->prediv);
-#endif
-
- /* Program the required multiplier value in PLLM */
- writel(pllmult, ®->pllm);
-
- /* program the postdiv */
- if (reg == davinci_pllc0_regs)
- writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
- ®->postdiv);
- else
- writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
- ®->postdiv);
-
- /*
- * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
- * no GO operation is currently in progress
- */
- while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
- ;
-
- if (reg == davinci_pllc0_regs) {
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
- } else {
- writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
- writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
- writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
- }
-
- /*
- * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
- * transition.
- */
- setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
-
- /*
- * Wait for the GOSTAT bit in PLLSTAT to clear to 0
- * (completion of phase alignment).
- */
- while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
- ;
-
- /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
- da850_waitloop(200);
-
- /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
- setbits_le32(®->pllctl, PLLCTL_PLLRST);
-
- /* Wait for PLL to lock. See PLL spec for PLL lock time */
- da850_waitloop(2400);
-
- /*
- * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
- * mode
- */
- setbits_le32(®->pllctl, PLLCTL_PLLEN);
-
-
- /*
- * clear EMIFA and EMIFB clock source settings, let them
- * run off SYSCLK
- */
- if (reg == davinci_pllc0_regs)
- dv_maskbits(&davinci_syscfg_regs->cfgchip3,
- ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
-
- return 0;
-}
-#endif /* CONFIG_SYS_DA850_PLL_INIT */
-
-#if defined(CONFIG_SYS_DA850_DDR_INIT)
-static int da850_ddr_setup(void)
-{
- unsigned long tmp;
-
- /* Enable the Clock to DDR2/mDDR */
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
- if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
- /* Begin VTP Calibration */
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-
- /* Polling READY bit to see when VTP calibration is done */
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
- while ((tmp & VTP_READY) != VTP_READY)
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
- }
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
- writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
- if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
- /* DDR2 */
- clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_DDR_PDENA_BIT) |
- (1 << DDR_SLEW_CMOSEN_BIT));
- } else {
- /* MOBILE DDR */
- setbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_DDR_PDENA_BIT) |
- (1 << DDR_SLEW_CMOSEN_BIT));
- }
-
- /*
- * SDRAM Configuration Register (SDCR):
- * First set the BOOTUNLOCK bit to make configuration bits
- * writeable.
- */
- setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
-
- /*
- * Write the new value of these bits and clear BOOTUNLOCK.
- * At the same time, set the TIMUNLOCK bit to allow changing
- * the timing registers
- */
- tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
- tmp &= ~DV_DDR_BOOTUNLOCK;
- tmp |= DV_DDR_TIMUNLOCK;
- writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
-
- /* write memory configuration and timing */
- if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
- /* MOBILE DDR only*/
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
- &dv_ddr2_regs_ctrl->sdbcr2);
- }
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
- /* clear the TIMUNLOCK bit and write the value of the CL field */
- tmp &= ~DV_DDR_TIMUNLOCK;
- writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
-
- /*
- * LPMODEN and MCLKSTOPEN must be set!
- * Without this bits set, PSC don;t switch states !!
- */
- writel(CONFIG_SYS_DA850_DDR2_SDRCR |
- (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
- (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
- &dv_ddr2_regs_ctrl->sdrcr);
-
- /* SyncReset the Clock to EMIF3A SDRAM */
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- /* Enable the Clock to EMIF3A SDRAM */
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- /* disable self refresh */
- clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
- writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
- return 0;
-}
-#endif /* CONFIG_SYS_DA850_DDR_INIT */
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
- return;
-}
-
-int arch_cpu_init(void)
-{
- /* Unlock kick registers */
- writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
- writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
-
- dv_maskbits(&davinci_syscfg_regs->suspsrc,
- CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
-
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
- return 1;
-
-#if defined(CONFIG_SYS_DA850_PLL_INIT)
- /* PLL setup */
- da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
- da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
-#endif
- /* setup CSn config */
-#if defined(CONFIG_SYS_DA850_CS2CFG)
- writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
-#endif
-#if defined(CONFIG_SYS_DA850_CS3CFG)
- writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
-#endif
-
- da8xx_configure_lpsc_items(lpsc, lpsc_size);
-
- /* GPIO setup */
- board_gpio_init();
-
-
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- /*
- * Fix Power and Emulation Management Register
- * see sprufw3a.pdf page 37 Table 24
- */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
- &davinci_uart0_ctrl_regs->pwremu_mgmt);
-#else
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
-#endif
-
-#if defined(CONFIG_SYS_DA850_DDR_INIT)
- da850_ddr_setup();
-#endif
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
deleted file mode 100644
index 6105f63..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Pinmux configurations for the DA850 SoCs
- *
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI pin muxer settings */
-const struct pinmux_config spi1_pins_base[] = {
- { pinmux(5), 1, 2 }, /* SPI1_CLK */
- { pinmux(5), 1, 4 }, /* SPI1_SOMI */
- { pinmux(5), 1, 5 }, /* SPI1_SIMO */
-};
-
-const struct pinmux_config spi1_pins_scs0[] = {
- { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
-};
-
-/* UART pin muxer settings */
-const struct pinmux_config uart0_pins_txrx[] = {
- { pinmux(3), 2, 4 }, /* UART0_RXD */
- { pinmux(3), 2, 5 }, /* UART0_TXD */
-};
-
-const struct pinmux_config uart0_pins_rtscts[] = {
- { pinmux(3), 2, 6 },
- { pinmux(3), 2, 7 },
-};
-
-const struct pinmux_config uart1_pins_txrx[] = {
- { pinmux(4), 2, 6 }, /* UART1_RXD */
- { pinmux(4), 2, 7 }, /* UART1_TXD */
-};
-
-const struct pinmux_config uart2_pins_txrx[] = {
- { pinmux(4), 2, 4 }, /* UART2_RXD */
- { pinmux(4), 2, 5 }, /* UART2_TXD */
-};
-
-const struct pinmux_config uart2_pins_rtscts[] = {
- { pinmux(0), 4, 6 }, /* UART2_RTS */
- { pinmux(0), 4, 7 }, /* UART2_CTS */
-};
-
-/* EMAC pin muxer settings*/
-const struct pinmux_config emac_pins_rmii[] = {
- { pinmux(14), 8, 2 }, /* RMII_TXD[1] */
- { pinmux(14), 8, 3 }, /* RMII_TXD[0] */
- { pinmux(14), 8, 4 }, /* RMII_TXEN */
- { pinmux(14), 8, 5 }, /* RMII_RXD[1] */
- { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
- { pinmux(14), 8, 7 }, /* RMII_RXER */
- { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */
- { pinmux(15), 8, 1 }, /* RMII_CRS_DV */
-};
-
-const struct pinmux_config emac_pins_mii[] = {
- { pinmux(2), 8, 1 }, /* MII_TXEN */
- { pinmux(2), 8, 2 }, /* MII_TXCLK */
- { pinmux(2), 8, 3 }, /* MII_COL */
- { pinmux(2), 8, 4 }, /* MII_TXD[3] */
- { pinmux(2), 8, 5 }, /* MII_TXD[2] */
- { pinmux(2), 8, 6 }, /* MII_TXD[1] */
- { pinmux(2), 8, 7 }, /* MII_TXD[0] */
- { pinmux(3), 8, 0 }, /* MII_RXCLK */
- { pinmux(3), 8, 1 }, /* MII_RXDV */
- { pinmux(3), 8, 2 }, /* MII_RXER */
- { pinmux(3), 8, 3 }, /* MII_CRS */
- { pinmux(3), 8, 4 }, /* MII_RXD[3] */
- { pinmux(3), 8, 5 }, /* MII_RXD[2] */
- { pinmux(3), 8, 6 }, /* MII_RXD[1] */
- { pinmux(3), 8, 7 }, /* MII_RXD[0] */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
- { pinmux(4), 8, 0 }, /* MDIO_CLK */
- { pinmux(4), 8, 1 }, /* MDIO_D */
-};
-
-/* I2C pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
- { pinmux(4), 2, 2 }, /* I2C0_SCL */
- { pinmux(4), 2, 3 }, /* I2C0_SDA */
-};
-
-const struct pinmux_config i2c1_pins[] = {
- { pinmux(4), 4, 4 }, /* I2C1_SCL */
- { pinmux(4), 4, 5 }, /* I2C1_SDA */
-};
-
-/* EMIFA pin muxer settings */
-const struct pinmux_config emifa_pins_cs2[] = {
- { pinmux(7), 1, 0 }, /* EMA_CS2 */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
- { pinmux(7), 1, 1 }, /* EMA_CS[3] */
-};
-
-const struct pinmux_config emifa_pins_cs4[] = {
- { pinmux(7), 1, 2 }, /* EMA_CS[4] */
-};
-
-const struct pinmux_config emifa_pins_nand[] = {
- { pinmux(7), 1, 4 }, /* EMA_WE */
- { pinmux(7), 1, 5 }, /* EMA_OE */
- { pinmux(9), 1, 0 }, /* EMA_D[7] */
- { pinmux(9), 1, 1 }, /* EMA_D[6] */
- { pinmux(9), 1, 2 }, /* EMA_D[5] */
- { pinmux(9), 1, 3 }, /* EMA_D[4] */
- { pinmux(9), 1, 4 }, /* EMA_D[3] */
- { pinmux(9), 1, 5 }, /* EMA_D[2] */
- { pinmux(9), 1, 6 }, /* EMA_D[1] */
- { pinmux(9), 1, 7 }, /* EMA_D[0] */
- { pinmux(12), 1, 5 }, /* EMA_A[2] */
- { pinmux(12), 1, 6 }, /* EMA_A[1] */
-};
-
-/* NOR pin muxer settings */
-const struct pinmux_config emifa_pins_nor[] = {
- { pinmux(5), 1, 6 }, /* EMA_BA[1] */
- { pinmux(6), 1, 6 }, /* EMA_WAIT[1] */
- { pinmux(7), 1, 4 }, /* EMA_WE */
- { pinmux(7), 1, 5 }, /* EMA_OE */
- { pinmux(8), 1, 0 }, /* EMA_D[15] */
- { pinmux(8), 1, 1 }, /* EMA_D[14] */
- { pinmux(8), 1, 2 }, /* EMA_D[13] */
- { pinmux(8), 1, 3 }, /* EMA_D[12] */
- { pinmux(8), 1, 4 }, /* EMA_D[11] */
- { pinmux(8), 1, 5 }, /* EMA_D[10] */
- { pinmux(8), 1, 6 }, /* EMA_D[9] */
- { pinmux(8), 1, 7 }, /* EMA_D[8] */
- { pinmux(9), 1, 0 }, /* EMA_D[7] */
- { pinmux(9), 1, 1 }, /* EMA_D[6] */
- { pinmux(9), 1, 2 }, /* EMA_D[5] */
- { pinmux(9), 1, 3 }, /* EMA_D[4] */
- { pinmux(9), 1, 4 }, /* EMA_D[3] */
- { pinmux(9), 1, 5 }, /* EMA_D[2] */
- { pinmux(9), 1, 6 }, /* EMA_D[1] */
- { pinmux(9), 1, 7 }, /* EMA_D[0] */
- { pinmux(10), 1, 1 }, /* EMA_A[22] */
- { pinmux(10), 1, 2 }, /* EMA_A[21] */
- { pinmux(10), 1, 3 }, /* EMA_A[20] */
- { pinmux(10), 1, 4 }, /* EMA_A[19] */
- { pinmux(10), 1, 5 }, /* EMA_A[18] */
- { pinmux(10), 1, 6 }, /* EMA_A[17] */
- { pinmux(10), 1, 7 }, /* EMA_A[16] */
- { pinmux(11), 1, 0 }, /* EMA_A[15] */
- { pinmux(11), 1, 1 }, /* EMA_A[14] */
- { pinmux(11), 1, 2 }, /* EMA_A[13] */
- { pinmux(11), 1, 3 }, /* EMA_A[12] */
- { pinmux(11), 1, 4 }, /* EMA_A[11] */
- { pinmux(11), 1, 5 }, /* EMA_A[10] */
- { pinmux(11), 1, 6 }, /* EMA_A[9] */
- { pinmux(11), 1, 7 }, /* EMA_A[8] */
- { pinmux(12), 1, 0 }, /* EMA_A[7] */
- { pinmux(12), 1, 1 }, /* EMA_A[6] */
- { pinmux(12), 1, 2 }, /* EMA_A[5] */
- { pinmux(12), 1, 3 }, /* EMA_A[4] */
- { pinmux(12), 1, 4 }, /* EMA_A[3] */
- { pinmux(12), 1, 5 }, /* EMA_A[2] */
- { pinmux(12), 1, 6 }, /* EMA_A[1] */
- { pinmux(12), 1, 7 }, /* EMA_A[0] */
-};
-
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins[] = {
- { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
- { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
- { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
- { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
- { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
- { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
- /* DA850 supports only 4-bit mode, remaining pins are not configured */
-};
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c
deleted file mode 100644
index f9550a1..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm355.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-
- /* Enable I2C pin Mux */
- REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c
deleted file mode 100644
index f6ca527..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm365.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SoC-specific code for tms320dm365 and similar chips
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
deleted file mode 100644
index c8b4498..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- * Actually used for booting from NAND with nand_spl.
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <asm/arch/hardware.h>
-
-void dm365_waitloop(unsigned long loopcnt)
-{
- unsigned long i;
-
- for (i = 0; i < loopcnt; i++)
- asm(" NOP");
-}
-
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
-{
- unsigned int clksrc = 0x0;
-
- /* Power up the PLL */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
-
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll0_regs->pllctl,
- clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
- /*
- * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
- dm365_waitloop(150);
-
- /* PLLRST=1(reset assert) */
- setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
- dm365_waitloop(300);
-
- /*Bring PLL out of Reset*/
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
- /* Program the Multiper and Pre-Divider for PLL1 */
- writel(pllmult, &dv_pll0_regs->pllm);
- writel(prediv, &dv_pll0_regs->prediv);
-
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
- PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
- &dv_pll0_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-
- /* Program the PostDiv for PLL1 */
- writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
-
- /* Post divider setting for PLL1 */
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
-
- dm365_waitloop(300);
-
- /* Set the GOSET bit */
- writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
-
- dm365_waitloop(300);
-
- /* Wait for PLL to LOCK */
- while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
- == PLL0_LOCK))
- ;
-
- /* Enable the PLL Bit of PLLCTL*/
- setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
- return 0;
-}
-
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
-{
- unsigned int clksrc = 0x0;
-
- /* Power up the PLL*/
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
-
- /*
- * Select the Clock Mode as Onchip Oscilator or External Clock on
- * MXI pin
- * VDB has input on MXI pin
- */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll1_regs->pllctl,
- clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
- /*
- * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
- dm365_waitloop(50);
-
- /* PLLRST=1(reset assert) */
- setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
- dm365_waitloop(300);
-
- /* Bring PLL out of Reset */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
- /* Program the Multiper and Pre-Divider for PLL2 */
- writel(pllm, &dv_pll1_regs->pllm);
- writel(prediv, &dv_pll1_regs->prediv);
-
- writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
-
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
- PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
- &dv_pll1_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-
- /* Post divider setting for PLL2 */
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
-
- /* GoCmd for PostDivider to take effect */
- writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
-
- dm365_waitloop(150);
-
- /* Wait for PLL to LOCK */
- while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
- == PLL1_LOCK))
- ;
-
- dm365_waitloop(4100);
-
- /* Enable the PLL2 */
- setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
- /* do this after PLL's have been set up */
- writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
- &dv_sys_module_regs->peri_clkctl);
-
- return 0;
-}
-
-int dm365_ddr_setup(void)
-{
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
- clrbits_le32(&dv_sys_module_regs->vtpiocr,
- VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
-
- /* Set bit CLRZ (bit 13) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
-
- /* Check VTP READY Status */
- while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
- ;
-
- /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
-
- /* Set bit LOCK(bit7) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
-
- /*
- * Powerdown VTP as it is locked (bit 6)
- * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
- */
- setbits_le32(&dv_sys_module_regs->vtpiocr,
- VPTIO_IOPWRDN | VPTIO_PWRDN);
-
- /* Wait for calibration to complete */
- dm365_waitloop(150);
-
- /* Set the DDR2 to synreset, then enable it again */
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
- /* Program SDRAM Bank Config Register */
- writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
- &dv_ddr2_regs_ctrl->sdbcr);
- writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
- &dv_ddr2_regs_ctrl->sdbcr);
-
- /* Program SDRAM Timing Control Register1 */
- writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- /* Program SDRAM Timing Control Register2 */
- writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
- writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
- writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
-
- /* Program SDRAM Refresh Control Register */
- writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
-
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- return 0;
-}
-
-static void dm365_vpss_sync_reset(void)
-{
- unsigned int PdNum = 0;
-
- /* VPSS_CLKMD 1:1 */
- setbits_le32(&dv_sys_module_regs->vpss_clkctl,
- VPSS_CLK_CTL_VPSS_CLKMD);
-
- /* LPSC SyncReset DDR Clock Enable */
- writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
- ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
- &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
-
- writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
- while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
- ;
- while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
- PSC_MD_STATE_MSK) == PSC_SYNCRESET))
- ;
-}
-
-static void dm365_por_reset(void)
-{
- struct davinci_timer *wdog =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
- if (readl(&dv_pll0_regs->rstype) &
- (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
- dm365_vpss_sync_reset();
-
- writel(DV_TMPBUF_VAL, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_PORRST);
- writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
- writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
- while (1);
- }
-}
-
-static void dm365_wdt_reset(void)
-{
- struct davinci_timer *wdog =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
- if (readl(TMPBUF) != DV_TMPBUF_VAL) {
- writel(DV_TMPBUF_VAL, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_PORRST);
- setbits_le32(TMPSTATUS, FLAG_FLGOFF);
-
- dm365_waitloop(100);
-
- dm365_vpss_sync_reset();
-
- writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
- writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
- while (1);
- }
-}
-
-static void dm365_wdt_flag_on(void)
-{
- /* VPSS_CLKMD 1:2 */
- clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
- VPSS_CLK_CTL_VPSS_CLKMD);
- writel(0, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_FLGON);
-}
-
-void dm365_psc_init(void)
-{
- unsigned char i = 0;
- unsigned char lpsc_start;
- unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
- unsigned int PdNum = 0;
-
- lpscmin = 0;
- lpscmax = 2;
-
- for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
- if (lpscgroup == 0) {
- /* Enabling LPSC 3 to 28 SCR first */
- lpsc_start = DAVINCI_LPSC_VPSSMSTR;
- lpsc_end = DAVINCI_LPSC_TIMER1;
- } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
- lpsc_start = DAVINCI_LPSC_CFG5;
- lpsc_end = DAVINCI_LPSC_VPSSMASTER;
- } else {
- lpsc_start = DAVINCI_LPSC_MJCP;
- lpsc_end = DAVINCI_LPSC_HDVICP;
- }
-
- /* NEXT=0x3, Enable LPSC's */
- for (i = lpsc_start; i <= lpsc_end; i++)
- setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
-
- /*
- * Program goctl to start transition sequence for LPSCs
- * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
- * Domain 0 Modules
- */
- writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
- /*
- * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
- */
- while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
- == 0))
- ;
-
- /* Wait for MODSTAT = ENABLE from LPSC's */
- for (i = lpsc_start; i <= lpsc_end; i++)
- while (!((readl(&dv_psc_regs->mdstat[i]) &
- PSC_MD_STATE_MSK) == PSC_ENABLE))
- ;
- }
-}
-
-static void dm365_emif_init(void)
-{
- writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
- writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
-
- setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
-
- writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
-
- return;
-}
-
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
- unsigned long value)
-{
- clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
- setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
- return;
-}
-
-#if defined(CONFIG_POST)
-int post_log(char *format, ...)
-{
- return 0;
-}
-#endif
-
-void dm36x_lowlevel_init(ulong bootflag)
-{
- struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
- (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
- DAVINCI_UART_CTRL_BASE);
-
- /* Mask all interrupts */
- writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
- writel(0x0, &dv_aintc_regs->eabase);
- writel(0x0, &dv_aintc_regs->eint0);
- writel(0x0, &dv_aintc_regs->eint1);
-
- /* Clear all interrupts */
- writel(0xffffffff, &dv_aintc_regs->fiq0);
- writel(0xffffffff, &dv_aintc_regs->fiq1);
- writel(0xffffffff, &dv_aintc_regs->irq0);
- writel(0xffffffff, &dv_aintc_regs->irq1);
-
- dm365_por_reset();
- dm365_wdt_reset();
-
- /* System PSC setup - enable all */
- dm365_psc_init();
-
- /* Setup Pinmux */
- dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
- dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
- dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
- dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
- dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
-
- /* PLL setup */
- dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
- CONFIG_SYS_DM36x_PLL1_PREDIV);
- dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
- CONFIG_SYS_DM36x_PLL2_PREDIV);
-
- /* GPIO setup */
- board_gpio_init();
-
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- /*
- * Fix Power and Emulation Management Register
- * see sprufh2.pdf page 38 Table 22
- */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart_ctrl_regs->pwremu_mgmt);
-
- puts("ddr init\n");
- dm365_ddr_setup();
-
- puts("emif init\n");
- dm365_emif_init();
-
- dm365_wdt_flag_on();
-
-#if defined(CONFIG_POST)
- /*
- * Do memory tests, calls arch_memory_failure_handle()
- * if error detected.
- */
- memory_post_test(0);
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c
deleted file mode 100644
index c58e271..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5 (1 << 11)
-#define PINMUX0_AECS4 (1 << 10)
-
-#define PINMUX1_I2C (1 << 7)
-#define PINMUX1_UART1 (1 << 1)
-#define PINMUX1_UART0 (1 << 0)
-
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-
- /* Enable UART0 MUX lines */
- REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
- lpsc_on(DAVINCI_LPSC_EMAC);
- lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
- lpsc_on(DAVINCI_LPSC_MDIO);
-
- /* Enable GIO3.3V cells used for EMAC */
- REG(VDD3P3V_PWDN) = 0;
-
- /* Enable EMAC. */
- REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-
- /* Enable I2C pin Mux */
- REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
- /*
- * Workaround for TMS320DM6446 errata 1.3.22:
- * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
- * Revision(s) Affected: 1.3 and earlier
- */
- REG(PSC_SILVER_BULLET) = 0;
-
- /*
- * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
- * as suggested in TMS320DM6446 errata 2.1.2:
- *
- * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
- * low priority modules can occupy the bus and prevent high priority
- * modules like the VPSS from getting the required DDR2 throughput.
- * A hex value of 0x20 should provide a good ARM (cache enabled)
- * performance and still allow good utilization by the VPSS or other
- * modules.
- */
- REG(VBPR) = 0x20;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c
deleted file mode 100644
index cfea830..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SoC-specific code for TMS320DM646x chips
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c
deleted file mode 100644
index 603d507..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <dp83848.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int dp83848_is_phy_connected(int phy_addr)
-{
- u_int16_t id1, id2;
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
- return(0);
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
- return(0);
-
- if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
- return(1);
-
- return(0);
-}
-
-int dp83848_get_link_speed(int phy_addr)
-{
- u_int16_t tmp;
- volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
- return(0);
-
- if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
- return(0);
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
- return(0);
-
- /* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
-}
-
-
-int dp83848_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (!dp83848_get_link_speed(phy_addr)) {
- /* Try another time */
- udelay(100000);
- ret = dp83848_get_link_speed(phy_addr);
- }
-
- /* Disable PHY Interrupts */
- davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
-
- return(ret);
-}
-
-
-int dp83848_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
-
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
- return(0);
-
- /* Restart Auto_negotiation */
- tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
- tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /* Set the Auto_negotiation Advertisement Register
- * MII advertising for Next page, 100BaseTxFD and HD,
- * 10BaseTFD and HD, IEEE 802.3
- */
- tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
- DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
- davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
-
-
- /* Read Control Register */
- if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
- return(0);
-
- tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /* Restart Auto_negotiation */
- tmp |= DP83848_RESTART_AUTONEG;
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /*check AutoNegotiate complete */
- udelay(10000);
- if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
- return(0);
-
- if (!(tmp & DP83848_AUTONEG_COMP))
- return(0);
-
- return (dp83848_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
deleted file mode 100644
index 9d53875..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
-
-#define MII_PHY_CONFIG_REG 22
-
-/* PHY Config bits */
-#define PHY_SYS_CLK_EN (1 << 4)
-
-int et1011c_get_link_speed(int phy_addr)
-{
- u_int16_t data;
-
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
- davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
- /* Enable 125MHz clock sourced from PHY */
- davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
- data | PHY_SYS_CLK_EN);
- return (1);
- }
- return (0);
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
deleted file mode 100644
index 4af5dd2..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Micrel KSZ8873 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2011 Heiko Schocher <hsdenx.de>
- *
- * based on:
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-int ksz8873_is_phy_connected(int phy_addr)
-{
- u_int16_t dummy;
-
- return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
-}
-
-int ksz8873_get_link_speed(int phy_addr)
-{
- emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
- /* we always have a link to the switch, 100 FD */
- writel((EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
- &emac->MACCONTROL);
- return 1;
-}
-
-
-int ksz8873_init_phy(int phy_addr)
-{
- return 1;
-}
-
-
-int ksz8873_auto_negotiate(int phy_addr)
-{
- return dp83848_get_link_speed(phy_addr);
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
deleted file mode 100644
index e916234..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
+++ /dev/null
@@ -1,693 +0,0 @@
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE 0x3f
-
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
- /*-------------------------------------------------------*
- * Mask all IRQs by setting all bits in the EINT default *
- *-------------------------------------------------------*/
- mov r1, $0
- ldr r0, =EINT_ENABLE0
- str r1, [r0]
- ldr r0, =EINT_ENABLE1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Put the GEM in reset *
- *------------------------------------------------------*/
-
- /* Put the GEM in reset */
- ldr r8, PSC_GEM_FLAG_CLEAR
- ldr r6, MDCTL_GEM
- ldr r7, [r6]
- and r7, r7, r8
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x02
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x02
- bne checkStatClkStopGem
-
- /* Check for GEM Reset Completion */
-checkGemStatClkStop:
- ldr r6, MDSTAT_GEM
- ldr r7, [r6]
- ands r7, r7, $0x100
- bne checkGemStatClkStop
-
- /* Do this for enabling a WDT initiated reset this is a workaround
- for a chip bug. Not required under normal situations */
- ldr r6, P1394
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * Enable L1 & L2 Memories in Fast mode *
- *------------------------------------------------------*/
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, MMARG_BRF0
- ldr r10, MMARG_BRF0_VAL
- str r10, [r6]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * DDR2 PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r10, $0
- ldr r6, PLL2_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r10, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-WaitPPL2Loop:
- subs r10, r10, $1
- bne WaitPPL2Loop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
- str r2, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV2
- mov r3, $0x01
- str r3, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
- str r4, [r6]
-
- /* PLL2 DIV2 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV2
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop_0:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop_0
-
- /* PLL2 DIV1 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV1
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0x218
-ResetPPL2Loop:
- subs r10, r10, $1
- bne ResetPPL2Loop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-PLL2Lock:
- subs r10, r10, $1
- bne PLL2Lock
-
- /* Enable the PLL */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x01
- str r8, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkStop
-
- /*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
- *------------------------------------------------------*/
-
- /* Program PHY Control Register */
- ldr r6, DDRCTL
- ldr r7, DDRCTL_VAL
- str r7, [r6]
-
- /* Program SDRAM Bank Config Register */
- ldr r6, SDCFG
- ldr r7, SDCFG_VAL
- str r7, [r6]
-
- /* Program SDRAM TIM-0 Config Register */
- ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
- str r7, [r6]
-
- /* Program SDRAM TIM-1 Config Register */
- ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
- str r7, [r6]
-
- /* Program the SDRAM Bank Config Control Register */
- ldr r10, MASK_VAL
- ldr r8, SDCFG
- ldr r9, SDCFG_VAL
- and r9, r9, r10
- str r9, [r8]
-
- /* Program SDRAM SDREF Config Register */
- ldr r6, SDREF
- ldr r7, SDREF_VAL
- str r7, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Issue a Dummy DDR2 read/write */
- ldr r8, DDR2_START_ADDR
- ldr r7, DUMMY_VAL
- str r7, [r8]
- ldr r7, [r8]
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x01
- bne checkDDRStatClkStop2
-
- /*------------------------------------------------------*
- * Turn DDR2 Controller Clocks On *
- *------------------------------------------------------*/
-
- /* Enable the DDR2 LPSC Module */
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkEn2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkEn2
-
- /* DDR Writes and Reads */
- ldr r6, CFGTEST
- mov r3, $0x01
- str r3, [r6]
-
- /*------------------------------------------------------*
- * System PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r2, $0
- ldr r6, PLL1_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r2, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-
-WaitLoop:
- subs r10, r10, $1
- bne WaitLoop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Disable the PLL */
- orr r8, r8, $0x10
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
- str r3, [r6]
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0xff
-
-ResetLoop:
- subs r10, r10, $1
- bne ResetLoop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL1_CTL
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-
-PLL1Lock:
- subs r10, r10, $1
- bne PLL1Lock
-
- /* Enable the PLL */
- orr r8, r8, $0x01
- str r8, [r6]
-
- nop
- nop
- nop
- nop
-
- /*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
- *------------------------------------------------------*/
- ldr r0, _PINMUX0
- ldr r1, _DEV_SETTING
- str r1, [r0]
-
- ldr r0, WAITCFG
- ldr r1, WAITCFG_VAL
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r0, ACFG3
- ldr r1, ACFG3_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG4
- ldr r1, ACFG4_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG5
- ldr r1, ACFG5_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- /*--------------------------------------*
- * VTP manual Calibration *
- *--------------------------------------*/
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR0
- str r1, [r0]
-
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR1
- str r1, [r0]
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTPLock:
- subs r10, r10, $1
- bne VTPLock
-
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, DDRVTPR
- ldr r7, [r6]
- mov r8, r7, LSL #32-10
- mov r8, r8, LSR #32-10 /* grab low 10 bits */
- ldr r7, VTP_RECAL
- orr r8, r7, r8
- ldr r7, VTP_EN
- orr r8, r7, r8
- str r8, [r0]
-
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTP1Lock:
- subs r10, r10, $1
- bne VTP1Lock
-
- ldr r1, [r0]
- ldr r2, VTP_MASK
- and r2, r1, r2
- str r2, [r0]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*
- * Call board-specific lowlevel init.
- * That MUST be present and THAT returns
- * back to arch calling code with "mov pc, lr."
- */
- b dv_board_init
-
-.ltorg
-
-_PINMUX0:
- .word 0x01c40000 /* Device Configuration Registers */
-_PINMUX1:
- .word 0x01c40004 /* Device Configuration Registers */
-
-_DEV_SETTING:
- .word 0x00000c1f
-
-WAITCFG:
- .word 0x01e00004
-WAITCFG_VAL:
- .word 0
-ACFG3:
- .word 0x01e00014
-ACFG3_VAL:
- .word 0x3ffffffd
-ACFG4:
- .word 0x01e00018
-ACFG4_VAL:
- .word 0x3ffffffd
-ACFG5:
- .word 0x01e0001c
-ACFG5_VAL:
- .word 0x3ffffffd
-
-MDCTL_DDR2:
- .word 0x01c41a34
-MDSTAT_DDR2:
- .word 0x01c41834
-
-PTCMD:
- .word 0x01c41120
-PTSTAT:
- .word 0x01c41128
-
-EINT_ENABLE0:
- .word 0x01c48018
-EINT_ENABLE1:
- .word 0x01c4801c
-
-PSC_FLAG_CLEAR:
- .word 0xffffffe0
-PSC_GEM_FLAG_CLEAR:
- .word 0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
- .word 0x200000e4
-DDRCTL_VAL:
- .word 0x50006405
-SDREF:
- .word 0x2000000c
-SDREF_VAL:
- .word 0x000005c3
-SDCFG:
- .word 0x20000008
-SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
- .word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
-SDTIM1:
- .word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
-VTPIOCR:
- .word 0x200000f0 /* VTP IO Control register */
-DDRVTPR:
- .word 0x01c42030 /* DDR VPTR MMR */
-VTP_MMR0:
- .word 0x201f
-VTP_MMR1:
- .word 0xa01f
-DFT_ENABLE:
- .word 0x01c4004c
-VTP_LOCK_COUNT:
- .word 0x5b0
-VTP_MASK:
- .word 0xffffdfff
-VTP_RECAL:
- .word 0x08000
-VTP_EN:
- .word 0x02000
-CFGTEST:
- .word 0x80010000
-MASK_VAL:
- .word 0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
- .word 0x01c41a9c
-MDSTAT_GEM:
- .word 0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
- .word 0x01c41a20
-
-PLL_CLKSRC_MASK:
- .word 0xfffffeff /* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
- .word 0xffffffdf /* Select the PLLEN source */
-PLL_BYPASS_MASK:
- .word 0xfffffffe /* Put the PLL in BYPASS */
-PLL_RESET_MASK:
- .word 0xfffffff7 /* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
- .word 0xfffffffd /* PLL Power up Mask Bit */
-PLL_DISABLE_ENABLE_MASK:
- .word 0xffffffef /* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
- .word 0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
- .word 0x01c40900
-PLL1_PLLM:
- .word 0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
- .word 0x01c40d00
-PLL2_PLLM:
- .word 0x01c40d10
-PLL2_DIV1:
- .word 0x01c40d18
-PLL2_DIV2:
- .word 0x01c40d1c
-PLL2_PLLCMD:
- .word 0x01c40d38
-PLL2_PLLSTAT:
- .word 0x01c40d3c
-PLL2_DIV_MASK:
- .word 0xffff7fff
-
-MMARG_BRF0:
- .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
- .word 0x00444400
-
-DDR2_START_ADDR:
- .word 0x80000000
-DUMMY_VAL:
- .word 0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
- mov pc, lr
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c
deleted file mode 100644
index c482fd9..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Intel LXT971/LXT972 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int lxt972_is_phy_connected(int phy_addr)
-{
- u_int16_t id1, id2;
-
- if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
- return(0);
- if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
- return(0);
-
- if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
- return(1);
-
- return(0);
-}
-
-int lxt972_get_link_speed(int phy_addr)
-{
- u_int16_t stat1, tmp;
- volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
- return(0);
-
- if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
- return(0);
-
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
- return(0);
-
- tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
-
- davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
- /* Read back */
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
- return(0);
-
- /* Speed doesn't matter, there is no setting for it in EMAC... */
- if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
-}
-
-
-int lxt972_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (!lxt972_get_link_speed(phy_addr)) {
- /* Try another time */
- ret = lxt972_get_link_speed(phy_addr);
- }
-
- /* Disable PHY Interrupts */
- davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
-
- return(ret);
-}
-
-
-int lxt972_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
-
- if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
- return(0);
-
- /* Restart Auto_negotiation */
- tmp |= BMCR_ANRESTART;
- davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
-
- /*check AutoNegotiate complete */
- udelay (10000);
- if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
- return(0);
-
- if (!(tmp & BMSR_ANEGCOMPLETE))
- return(0);
-
- return (lxt972_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c
deleted file mode 100644
index e18bdfc..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/misc.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Miscelaneous DaVinci functions.
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_BUILD
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
- * Returns 1 if found, 0 otherwise.
- */
-int dvevm_read_mac_address(uint8_t *buf)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- /* Read MAC address. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
- goto i2cerr;
-
- /* Check that MAC address is valid. */
- if (!is_valid_ether_addr(buf))
- goto err;
-
- return 1; /* Found */
-
-i2cerr:
- printf("Read from EEPROM @ 0x%02x failed\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
-err:
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
-
- return 0;
-}
-
-/*
- * Set the mii mode as MII or RMII
- */
-#if defined(CONFIG_SOC_DA8XX)
-void davinci_emac_mii_mode_sel(int mode_sel)
-{
- int val;
-
- val = readl(&davinci_syscfg_regs->cfgchip3);
- if (mode_sel == 0)
- val &= ~(1 << 8);
- else
- val |= (1 << 8);
- writel(val, &davinci_syscfg_regs->cfgchip3);
-}
-#endif
-/*
- * If there is no MAC address in the environment, then it will be initialized
- * (silently) from the value in the EEPROM.
- */
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
-{
- uint8_t env_enetaddr[6];
- int ret;
-
- ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
- if (!ret) {
- /*
- * There is no MAC address in the environment, so we
- * initialize it from the value in the EEPROM.
- */
- debug("### Setting environment from EEPROM MAC address = "
- "\"%pM\"\n",
- env_enetaddr);
- ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
- }
- if (!ret)
- printf("Failed to set mac address from EEPROM: %d\n", ret);
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#if defined(CONFIG_SOC_DA8XX)
-#ifndef CONFIG_USE_IRQ
-void irq_init(void)
-{
- /*
- * Mask all IRQs by clearing the global enable and setting
- * the enable clear for all the 90 interrupts.
- */
- writel(0, &davinci_aintc_regs->ger);
-
- writel(0, &davinci_aintc_regs->hier);
-
- writel(0xffffffff, &davinci_aintc_regs->ecr1);
- writel(0xffffffff, &davinci_aintc_regs->ecr2);
- writel(0xffffffff, &davinci_aintc_regs->ecr3);
-}
-#endif
-
-/*
- * Enable PSC for various peripherals.
- */
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- const int n_items)
-{
- int i;
-
- for (i = 0; i < n_items; i++)
- lpsc_on(item[i].lpsc_no);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/cpu/arm926ejs/davinci/pinmux.c
deleted file mode 100644
index e9d8c87..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/pinmux.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * DaVinci pinmux functions.
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-
-/*
- * Change the setting of a pin multiplexer field.
- *
- * Takes an array of pinmux settings similar to:
- *
- * struct pinmux_config uart_pins[] = {
- * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
- * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
- * };
- *
- * Stepping through the array, each pinmux[n] register has the given value
- * set in the pin mux field specified.
- *
- * The number of pins in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Returns 0 if all field numbers and values are in the correct range,
- * else returns -1.
- */
-int davinci_configure_pin_mux(const struct pinmux_config *pins,
- const int n_pins)
-{
- int i;
-
- /* check for invalid pinmux values */
- for (i = 0; i < n_pins; i++) {
- if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
- (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
- return -1;
- }
-
- /* configure the pinmuxes */
- for (i = 0; i < n_pins; i++) {
- const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
- const unsigned int value = pins[i].value << offset;
- const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
- const dv_reg *mux = pins[i].mux;
-
- writel(value | (readl(mux) & (~mask)), mux);
- }
-
- return 0;
-}
-
-/*
- * Configure multiple pinmux resources.
- *
- * Takes an pinmux_resource array of pinmux_config and pin counts:
- *
- * const struct pinmux_resource pinmuxes[] = {
- * PINMUX_ITEM(uart_pins),
- * PINMUX_ITEM(i2c_pins),
- * };
- *
- * The number of items in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Each item entry is configured in the defined order. If configuration
- * of any item fails, -1 is returned and none of the following items are
- * configured. On success, 0 is returned.
- */
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
- const int n_items)
-{
- int i;
-
- for (i = 0; i < n_items; i++) {
- if (davinci_configure_pin_mux(item[i].pins,
- item[i].n_pins) != 0)
- return -1;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c
deleted file mode 100644
index 8d99e2e..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/psc.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Power and Sleep Controller (PSC) functions.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/*
- * The PSC manages three inputs to a "module" which may be a peripheral or
- * CPU. Those inputs are the module's: clock; reset signal; and sometimes
- * its power domain. For our purposes, we only care whether clock and power
- * are active, and the module is out of reset.
- *
- * DaVinci chips may include two separate power domains: "Always On" and "DSP".
- * Chips without a DSP generally have only one domain.
- *
- * The "Always On" power domain is always on when the chip is on, and is
- * powered by the VDD pins (on DM644X). The majority of DaVinci modules
- * lie within the "Always On" power domain.
- *
- * A separate domain called the "DSP" domain houses the C64x+ and other video
- * hardware such as VICP. In some chips, the "DSP" domain is not always on.
- * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
- */
-
-/* Works on Always On power domain only (no PD argument) */
-static void lpsc_transition(unsigned int id, unsigned int state)
-{
- dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-#ifdef CONFIG_SOC_DA8XX
- struct davinci_psc_regs *psc_regs;
-#endif
-
-#ifndef CONFIG_SOC_DA8XX
- if (id >= DAVINCI_LPSC_GEM)
- return; /* Don't work on DSP Power Domain */
-
- mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
- mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
- ptstat = REG_P(PSC_PTSTAT);
- ptcmd = REG_P(PSC_PTCMD);
-#else
- if (id < DAVINCI_LPSC_PSC1_BASE) {
- if (id >= PSC_PSC0_MODULE_ID_CNT)
- return;
- psc_regs = davinci_psc0_regs;
- mdstat = &psc_regs->psc0.mdstat[id];
- mdctl = &psc_regs->psc0.mdctl[id];
- } else {
- id -= DAVINCI_LPSC_PSC1_BASE;
- if (id >= PSC_PSC1_MODULE_ID_CNT)
- return;
- psc_regs = davinci_psc1_regs;
- mdstat = &psc_regs->psc1.mdstat[id];
- mdctl = &psc_regs->psc1.mdctl[id];
- }
- ptstat = &psc_regs->ptstat;
- ptcmd = &psc_regs->ptcmd;
-#endif
-
- while (readl(ptstat) & 0x01)
- continue;
-
- if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
- return; /* Already in that state */
-
- writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
-
- switch (id) {
-#ifdef CONFIG_SOC_DM644X
- /* Special treatment for some modules as for sprue14 p.7.4.2 */
- case DAVINCI_LPSC_VPSSSLV:
- case DAVINCI_LPSC_EMAC:
- case DAVINCI_LPSC_EMAC_WRAPPER:
- case DAVINCI_LPSC_MDIO:
- case DAVINCI_LPSC_USB:
- case DAVINCI_LPSC_ATA:
- case DAVINCI_LPSC_VLYNQ:
- case DAVINCI_LPSC_UHPI:
- case DAVINCI_LPSC_DDR_EMIF:
- case DAVINCI_LPSC_AEMIF:
- case DAVINCI_LPSC_MMC_SD:
- case DAVINCI_LPSC_MEMSTICK:
- case DAVINCI_LPSC_McBSP:
- case DAVINCI_LPSC_GPIO:
- writel(readl(mdctl) | 0x200, mdctl);
- break;
-#endif
- }
-
- writel(0x01, ptcmd);
-
- while (readl(ptstat) & 0x01)
- continue;
- while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
- continue;
-}
-
-void lpsc_on(unsigned int id)
-{
- lpsc_transition(id, 0x03);
-}
-
-void lpsc_syncreset(unsigned int id)
-{
- lpsc_transition(id, 0x01);
-}
-
-void lpsc_disable(unsigned int id)
-{
- lpsc_transition(id, 0x0);
-}
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
- int i;
-
- if (REG(PSC_PDSTAT1) & 0x1f)
- return; /* Already on */
-
- REG(PSC_GBLCTL) |= 0x01;
- REG(PSC_PDCTL1) |= 0x01;
- REG(PSC_PDCTL1) &= ~0x100;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
- REG(PSC_PTCMD) = 0x02;
-
- for (i = 0; i < 100; i++) {
- if (REG(PSC_EPCPR) & 0x02)
- break;
- }
-
- REG(PSC_CHP_SHRTSW) = 0x01;
- REG(PSC_PDCTL1) |= 0x100;
- REG(PSC_EPCCR) = 0x02;
-
- for (i = 0; i < 100; i++) {
- if (!(REG(PSC_PTSTAT) & 0x02))
- break;
- }
-
- REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c
deleted file mode 100644
index 6b0f154..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/reset.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Processor reset using WDT.
- *
- * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer_defs.h>
-#include <asm/arch/hardware.h>
-
-void reset_cpu(unsigned long a)
-{
- struct davinci_timer *const wdttimer =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
- writel(0x08, &wdttimer->tgcr);
- writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
- writel(0, &wdttimer->tim12);
- writel(0, &wdttimer->tim34);
- writel(0, &wdttimer->prd12);
- writel(0, &wdttimer->prd34);
- writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
- writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
- writel(0xa5c64000, &wdttimer->wdtcr);
- writel(0xda7e4000, &wdttimer->wdtcr);
- writel(0x4000, &wdttimer->wdtcr);
- while (1)
- /*nothing*/;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
deleted file mode 100644
index 59b304e..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spi_flash.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
-
- NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
-}
-#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-
-void board_init_f(ulong dummy)
-{
- /* First, setup our stack pointer. */
- asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
- /* Second, perform our low-level init. */
-#ifdef CONFIG_SOC_DM365
- dm36x_lowlevel_init(0);
-#endif
-#ifdef CONFIG_SOC_DA8XX
- arch_cpu_init();
-#endif
-
- /* Third, we clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* Finally, setup gd and move to the next step. */
- gd = &gdata;
- board_init_r(NULL, 0);
-}
-
-void spl_board_init(void)
-{
- preloader_console_init();
-}
-
-u32 spl_boot_mode(void)
-{
- return MMCSD_MODE_RAW;
-}
-
-u32 spl_boot_device(void)
-{
-#ifdef CONFIG_SPL_NAND_SIMPLE
- return BOOT_DEVICE_NAND;
-#elif defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_SPL_MMC_LOAD)
- return BOOT_DEVICE_MMC1;
-#else
- puts("Unknown boot device\n");
- hang();
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
deleted file mode 100644
index c7d0652..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer_defs.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct davinci_timer * const timer =
- (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define TIM_CLK_DIV 16
-
-int timer_init(void)
-{
- /* We are using timer34 in unchained 32-bit mode, full speed */
- writel(0x0, &timer->tcr);
- writel(0x0, &timer->tgcr);
- writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
- writel(0x0, &timer->tim34);
- writel(TIMER_LOAD_VAL, &timer->prd34);
- writel(2 << 22, &timer->tcr);
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
- gd->arch.timer_reset_value = 0;
-
- return(0);
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- unsigned long now = readl(&timer->tim34);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
-
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-ulong get_timer(ulong base)
-{
- unsigned long long timer_diff;
-
- timer_diff = get_ticks() - gd->arch.timer_reset_value;
-
- return lldiv(timer_diff,
- (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long endtime;
-
- endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
- 1000000UL);
- endtime += get_ticks();
-
- while (get_ticks() < endtime)
- ;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-static struct davinci_timer * const wdttimer =
- (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
-
-/*
- * See prufw2.pdf for using Timer as a WDT
- */
-void davinci_hw_watchdog_enable(void)
-{
- writel(0x0, &wdttimer->tcr);
- writel(0x0, &wdttimer->tgcr);
- /* TIMMODE = 2h */
- writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
- writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
- writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
- writel(2 << 22, &wdttimer->tcr);
- writel(0x0, &wdttimer->tim12);
- writel(0x0, &wdttimer->tim34);
- /* set WDEN bit, WDKEY 0xa5c6 */
- writel(0xa5c64000, &wdttimer->wdtcr);
- /* clear counter register */
- writel(0xda7e4000, &wdttimer->wdtcr);
-}
-
-void davinci_hw_watchdog_reset(void)
-{
- writel(0xa5c64000, &wdttimer->wdtcr);
- writel(0xda7e4000, &wdttimer->wdtcr);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
deleted file mode 100644
index 6c037a1..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-if KIRKWOOD
-
-choice
- prompt "Marvell Kirkwood board select"
-
-config TARGET_OPENRD
- bool "Marvell OpenRD Board"
-
-config TARGET_MV88F6281GTW_GE
- bool "MV88f6281GTW_GE Board"
-
-config TARGET_RD6281A
- bool "RD6281A Board"
-
-config TARGET_DREAMPLUG
- bool "DreamPlug Board"
-
-config TARGET_GURUPLUG
- bool "GuruPlug Board"
-
-config TARGET_SHEEVAPLUG
- bool "SheevaPlug Board"
-
-config TARGET_LSXL
- bool "lsxl Board"
-
-config TARGET_POGO_E02
- bool "pogo_e02 Board"
-
-config TARGET_DNS325
- bool "dns325 Board"
-
-config TARGET_ICONNECT
- bool "iconnect Board"
-
-config TARGET_TK71
- bool "TK71 Board"
-
-config TARGET_KM_KIRKWOOD
- bool "KM_KIRKWOOD Board"
-
-config TARGET_NET2BIG_V2
- bool "LaCie 2Big Network v2 NAS Board"
-
-config TARGET_NETSPACE_V2
- bool "LaCie netspace_v2 Board"
-
-config TARGET_WIRELESS_SPACE
- bool "LaCie Wireless_space Board"
-
-config TARGET_IB62X0
- bool "ib62x0 Board"
-
-config TARGET_DOCKSTAR
- bool "Dockstar Board"
-
-config TARGET_GOFLEXHOME
- bool "GoFlex Home Board"
-
-endchoice
-
-config SYS_SOC
- default "kirkwood"
-
-source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
-source "board/Marvell/rd6281a/Kconfig"
-source "board/Marvell/dreamplug/Kconfig"
-source "board/Marvell/guruplug/Kconfig"
-source "board/Marvell/sheevaplug/Kconfig"
-source "board/buffalo/lsxl/Kconfig"
-source "board/cloudengines/pogo_e02/Kconfig"
-source "board/d-link/dns325/Kconfig"
-source "board/iomega/iconnect/Kconfig"
-source "board/karo/tk71/Kconfig"
-source "board/keymile/km_arm/Kconfig"
-source "board/LaCie/net2big_v2/Kconfig"
-source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
-source "board/raidsonic/ib62x0/Kconfig"
-source "board/Seagate/dockstar/Kconfig"
-source "board/Seagate/goflexhome/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
deleted file mode 100644
index df4756e..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o
-obj-y += cache.o
-obj-y += mpp.o
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
deleted file mode 100644
index e18a309..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/cache.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2012 Michael Walle
- * Michael Walle <michael@walle.cc>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-
-#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
-
-void l2_cache_disable()
-{
- u32 ctrl;
-
- ctrl = readfr_extra_feature_reg();
- ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
- writefr_extra_feature_reg(ctrl);
-}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
deleted file mode 100644
index 9e412bb..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <mvebu_mmc.h>
-
-void reset_cpu(unsigned long ignored)
-{
- struct kwcpu_registers *cpureg =
- (struct kwcpu_registers *)KW_CPU_REG_BASE;
-
- writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
- &cpureg->rstoutn_mask);
- writel(readl(&cpureg->sys_soft_rst) | 1,
- &cpureg->sys_soft_rst);
- while (1) ;
-}
-
-/*
- * Window Size
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
- */
-unsigned int kw_winctrl_calcsize(unsigned int sizeval)
-{
- int i;
- unsigned int j = 0;
- u32 val = sizeval >> 1;
-
- for (i = 0; val >= 0x10000; i++) {
- j |= (1 << i);
- val = val >> 1;
- }
- return (0x0000ffff & j);
-}
-
-/*
- * kw_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Kirkwood Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int kw_config_adr_windows(void)
-{
- struct kwwin_registers *winregs =
- (struct kwwin_registers *)KW_CPU_WIN_BASE;
-
- /* Window 0: PCIE MEM address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
- KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
-
- writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
- writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
- writel(0x0, &winregs[0].remap_hi);
-
- /* Window 1: PCIE IO address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
- KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
- writel(KW_DEFADR_PCI_IO, &winregs[1].base);
- writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
- writel(0x0, &winregs[1].remap_hi);
-
- /* Window 2: NAND Flash address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
- KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
- writel(KW_DEFADR_NANDF, &winregs[2].base);
- writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
- writel(0x0, &winregs[2].remap_hi);
-
- /* Window 3: SPI Flash address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
- KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
- writel(KW_DEFADR_SPIF, &winregs[3].base);
- writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
- writel(0x0, &winregs[3].remap_hi);
-
- /* Window 4: BOOT Memory address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
- KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
- writel(KW_DEFADR_BOOTROM, &winregs[4].base);
-
- /* Window 5: Security SRAM address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
- KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
- writel(KW_DEFADR_SASRAM, &winregs[5].base);
-
- /* Window 6-7: Disabled */
- writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
- writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
-
- return 0;
-}
-
-/*
- * SYSRSTn Duration Counter Support
- *
- * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
- * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
- * The SYSRSTn duration counter is useful for implementing a manufacturer
- * or factory reset. Upon a long reset assertion that is greater than a
- * pre-configured environment variable value for sysrstdelay,
- * The counter value is stored in the SYSRSTn Length Counter Register
- * The counter is based on the 25-MHz reference clock (40ns)
- * It is a 29-bit counter, yielding a maximum counting duration of
- * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
- * it remains at this value until counter reset is triggered by setting
- * bit 31 of KW_REG_SYSRST_CNT
- */
-static void kw_sysrst_action(void)
-{
- int ret;
- char *s = getenv("sysrstcmd");
-
- if (!s) {
- debug("Error.. %s failed, check sysrstcmd\n",
- __FUNCTION__);
- return;
- }
-
- debug("Starting %s process...\n", __FUNCTION__);
- ret = run_command(s, 0);
- if (ret != 0)
- debug("Error.. %s failed\n", __FUNCTION__);
- else
- debug("%s process finished\n", __FUNCTION__);
-}
-
-static void kw_sysrst_check(void)
-{
- u32 sysrst_cnt, sysrst_dly;
- char *s;
-
- /*
- * no action if sysrstdelay environment variable is not defined
- */
- s = getenv("sysrstdelay");
- if (s == NULL)
- return;
-
- /* read sysrstdelay value */
- sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
-
- /* read SysRst Length counter register (bits 28:0) */
- sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
- debug("H/w Rst hold time: %d.%d secs\n",
- sysrst_cnt / SYSRST_CNT_1SEC_VAL,
- sysrst_cnt % SYSRST_CNT_1SEC_VAL);
-
- /* clear the counter for next valid read*/
- writel(1 << 31, KW_REG_SYSRST_CNT);
-
- /*
- * sysrst_action:
- * if H/w Reset key is pressed and hold for time
- * more than sysrst_dly in seconds
- */
- if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
- kw_sysrst_action();
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- char *rev;
- u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
- u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
-
- if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
- printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
- return -1;
- }
-
- switch (revid) {
- case 0:
- rev = "Z0";
- break;
- case 2:
- rev = "A0";
- break;
- case 3:
- rev = "A1";
- break;
- default:
- rev = "??";
- break;
- }
-
- printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- u32 reg;
- struct kwcpu_registers *cpureg =
- (struct kwcpu_registers *)KW_CPU_REG_BASE;
-
- /* Linux expects` the internal registers to be at 0xf1000000 */
- writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
-
- /* Enable and invalidate L2 cache in write through mode */
- writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
- invalidate_l2_cache();
-
- kw_config_adr_windows();
-
-#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
- /*
- * Configures the I/O voltage of the pads connected to Egigabit
- * Ethernet interface to 1.8V
- * By default it is set to 3.3V
- */
- reg = readl(KW_REG_MPP_OUT_DRV_REG);
- reg |= (1 << 7);
- writel(reg, KW_REG_MPP_OUT_DRV_REG);
-#endif
-#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
- /*
- * Set egiga port0/1 in normal functional mode
- * This is required becasue on kirkwood by default ports are in reset mode
- * OS egiga driver may not have provision to set them in normal mode
- * and if u-boot is build without network support, network may fail at OS level
- */
- reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
- reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
-#endif
-#ifdef CONFIG_KIRKWOOD_PCIE_INIT
- /*
- * Enable PCI Express Port0
- */
- reg = readl(&cpureg->ctrl_stat);
- reg |= (1 << 0); /* Set PEX0En Bit */
- writel(reg, &cpureg->ctrl_stat);
-#endif
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
- volatile u32 temp;
-
- /*CPU streaming & write allocate */
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 28); /* disable wr alloc */
- writefr_extra_feature_reg(temp);
-
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 29); /* streaming disabled */
- writefr_extra_feature_reg(temp);
-
- /* L2Cache settings */
- temp = readfr_extra_feature_reg();
- /* Disable L2C pre fetch - Set bit 24 */
- temp |= (1 << 24);
- /* enable L2C - Set bit 22 */
- temp |= (1 << 22);
- writefr_extra_feature_reg(temp);
-
- icache_enable();
- /* Change reset vector to address 0x0 */
- temp = get_cr();
- set_cr(temp & ~CR_V);
-
- /* checks and execute resset to factory event */
- kw_sysrst_check();
-
- return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVGBE
-int cpu_eth_init(bd_t *bis)
-{
- mvgbe_initialize(bis);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MVEBU_MMC
-int board_mmc_init(bd_t *bis)
-{
- mvebu_mmc_init(bis);
- return 0;
-}
-#endif /* CONFIG_MVEBU_MMC */
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
new file mode 100644
index 0000000..986ad73
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_LPC32XX
+
+config SYS_SOC
+ default "lpc32xx"
+
+choice
+ prompt "NXP LPC32xx board select"
+
+config TARGET_DEVKIT3250
+ bool "Timll DevKit3250"
+
+config TARGET_WORK_92105
+ bool "Work Microwave Work_92105"
+
+endchoice
+
+source "board/timll/devkit3250/Kconfig"
+source "board/work-microwave/work_92105/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
index 314f004..6303570 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y = cpu.o clk.o devices.o timer.o
+
+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d5..5eb630d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -54,12 +53,12 @@
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
- fout = fref * m_div;
- if (val & CLK_HCLK_PLL_FEEDBACK) {
- fcco = fout;
+ fcco = fref * m_div;
+ fout = fcco;
+ if (val & CLK_HCLK_PLL_FEEDBACK)
+ fcco *= p_div;
+ else
do_div(fout, p_div);
- } else
- fcco = fout * p_div;
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;
@@ -98,6 +97,40 @@
return get_hclk_pll_rate() / get_periph_clk_div();
}
+unsigned int get_sdram_clk_rate(void)
+{
+ unsigned int src_clk;
+
+ if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+ return get_sys_clk_rate();
+
+ src_clk = get_hclk_pll_rate();
+
+ if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
+ /* using DDR */
+ switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
+ case CLK_HCLK_DDRAM_HALF:
+ return src_clk/2;
+ case CLK_HCLK_DDRAM_NOMINAL:
+ return src_clk;
+ default:
+ return 0;
+ }
+ } else {
+ /* using SDR */
+ switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
+ case CLK_HCLK_ARM_PLL_DIV_4:
+ return src_clk/4;
+ case CLK_HCLK_ARM_PLL_DIV_2:
+ return src_clk/2;
+ case CLK_HCLK_ARM_PLL_DIV_1:
+ return src_clk;
+ default:
+ return 0;
+ }
+ }
+}
+
int get_serial_clock(void)
{
return get_periph_clk_rate();
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..5117177 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -1,13 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
@@ -18,12 +19,23 @@
/* Enable watchdog clock */
setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- /* Reset pulse length is 13005 peripheral clock frames */
- writel(13000, &wdt->pulse);
+ /* To be compatible with the original U-Boot code:
+ * addr: - 0: perform hard reset.
+ * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
+ if (addr == 0) {
+ /* Reset pulse length is 13005 peripheral clock frames */
+ writel(13000, &wdt->pulse);
- /* Force WDOG_RESET2 and RESOUT_N signal active */
- writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
- &wdt->mctrl);
+ /* Force WDOG_RESET2 and RESOUT_N signal active */
+ writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
+ | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
+ } else {
+ /* Force match output active */
+ writel(0x01, &wdt->emr);
+
+ /* Internal reset on match output (no pulse on "RESOUT_N") */
+ writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
+ }
while (1)
/* NOP */;
@@ -33,7 +45,7 @@
int arch_cpu_init(void)
{
/*
- * It might be necessary to flush data cache, if U-boot is loaded
+ * It might be necessary to flush data cache, if U-Boot is loaded
* from kickstart bootloader, e.g. from S1L loader
*/
flush_dcache_all();
@@ -55,3 +67,11 @@
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..7e7646a 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -1,17 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/arch/cpu.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
+#include <asm/arch/mux.h>
#include <asm/io.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -37,3 +41,101 @@
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
&clk->u3clk + (uart_id - 3));
}
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata lpc32xx_uart[] = {
+ { .base = UART3_BASE, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = UART4_BASE, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = UART5_BASE, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = UART6_BASE, .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+};
+
+#if defined(CONFIG_LPC32XX_HSUART)
+static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+ { HS_UART1_BASE, },
+ { HS_UART2_BASE, },
+ { HS_UART7_BASE, },
+};
+#endif
+
+U_BOOT_DEVICES(lpc32xx_uarts) = {
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
+#endif
+ { "ns16550_serial", &lpc32xx_uart[0], },
+ { "ns16550_serial", &lpc32xx_uart[1], },
+ { "ns16550_serial", &lpc32xx_uart[2], },
+ { "ns16550_serial", &lpc32xx_uart[3], },
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
+#endif
+};
+#endif
+
+void lpc32xx_dma_init(void)
+{
+ /* Enable DMA interface */
+ writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
+}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+#if defined(CONFIG_RMII)
+ | CLK_MAC_RMII,
+#else
+ | CLK_MAC_MII,
+#endif
+ &clk->macclk_ctrl);
+}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
+}
+
+void lpc32xx_slc_nand_init(void)
+{
+ /* Enable SLC NAND interface */
+ writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
+void lpc32xx_usb_init(void)
+{
+ /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
+ clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
+}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(&clk->i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, &clk->i2cclk_ctrl);
+}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = "gpio_lpc32xx"
+};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, &mux->p_mux_set);
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/dram.c b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c
new file mode 100644
index 0000000..4f97569
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LPC32xx dram init
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * This is called by SPL to gain access to the SDR DRAM.
+ *
+ * This code runs from SRAM.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/emc.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+void ddr_init(struct emc_dram_settings *dram)
+{
+ uint32_t ck;
+
+ /* Enable EMC interface and choose little endian mode */
+ writel(1, &emc->ctrl);
+ writel(0, &emc->config);
+ /* Select maximum EMC Dynamic Memory Refresh Time */
+ writel(0x7FF, &emc->refresh);
+ /* Determine CLK */
+ ck = get_sdram_clk_rate();
+ /* Configure SDRAM */
+ writel(dram->cmddelay, &clk->sdramclk_ctrl);
+ writel(dram->config0, &emc->config0);
+ writel(dram->rascas0, &emc->rascas0);
+ writel(dram->rdconfig, &emc->read_config);
+ /* Set timings */
+ writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
+ writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
+ writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
+ writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
+ writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
+ writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
+ writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
+ writel(dram->trrd, &emc->t_rrd);
+ writel(dram->tmrd, &emc->t_mrd);
+ writel(dram->tcdlr, &emc->t_cdlr);
+ /* Dynamic refresh */
+ writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+ udelay(10);
+ /* Force all clocks, enable inverted ck, issue NOP command */
+ writel(0x00000193, &emc->control);
+ udelay(100);
+ /* Keep all clocks enabled, issue a PRECHARGE ALL command */
+ writel(0x00000113, &emc->control);
+ /* Fast dynamic refresh for at least a few SDRAM ck cycles */
+ writel((((128) >> 4) & 0x7FF), &emc->refresh);
+ udelay(10);
+ /* set correct dynamic refresh timing */
+ writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+ udelay(10);
+ /* set normal mode to CAS=3 */
+ writel(0x00000093, &emc->control);
+ readl(EMC_DYCS0_BASE | dram->mode);
+ /* set extended mode to all zeroes */
+ writel(0x00000093, &emc->control);
+ readl(EMC_DYCS0_BASE | dram->emode);
+ /* stop forcing clocks, keep inverted clock, issue normal mode */
+ writel(0x00000010, &emc->control);
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
new file mode 100644
index 0000000..d42da2b
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * WORK Microwave work_92105 board low level init
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Low level init is called from SPL to set up the clocks.
+ * On entry, the LPC3250 is in Direct Run mode with all clocks
+ * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
+ * 104 MHz and PCLK is 13 MHz.
+ *
+ * This code must run from SRAM so that the clock changes do
+ * not prevent it from executing.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+ /* Set ARM, HCLK, PCLK dividers for normal mode */
+ ldr r0, =0x0000003D
+ ldr r1, =0x40004040
+ str r0, [r1]
+
+ /* Start HCLK PLL for 208 MHz */
+ ldr r0, =0x0001401E
+ ldr r1, =0x40004058
+ str r0, [r1]
+
+ /* wait for HCLK PLL to lock */
+1:
+ ldr r0, [r1]
+ ands r0, r0, #1
+ beq 1b
+
+ /* switch to normal mode */
+ ldr r1, =0x40004044
+ ldr r0, [r1]
+ orr r0, #0x00000004
+ str r0, [r1]
+
+ /* Return to U-Boot via saved link register */
+ mov pc, lr
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
index dc1217e..404ccbb 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
deleted file mode 100644
index 365892c..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = clock.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
deleted file mode 100644
index 1f6f66e..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
- uint32_t pllmode;
-
- pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
- if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
- return 40000000;
-
- return 41164767;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
deleted file mode 100644
index 7bd77ff..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
-
- writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
- while (1)
- /* NOP */;
- /* Never reached */
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
deleted file mode 100644
index bb07819..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= TIMER_FREQ;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong ctrl = readl(&timer->control);
-
- writel(TIMER_LOAD_VAL, &timer->load);
-
- ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
- MB86R0x_TIMER_SIZE_32;
-
- writel(ctrl, &timer->control);
-
- /* capture current value time */
- lastdec = readl(&timer->value);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong now = readl(&timer->value);
-
- if (now <= lastdec) {
- /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += lastdec - now;
- } else {
- /* we have rollover of incrementer */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
- return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec_to_tick(usec);
- tmp = get_ticks(); /* get current timestamp */
-
- while ((get_ticks() - tmp) < tmo) /* loop till event */
- /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = TIMER_FREQ;
- return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index ebc0407..ac5ebaf 100644
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -1,11 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-# SPDX-License-Identifier: GPL-2.0+
-obj-y = generic.o timer.o reset.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += generic.o timer.o reset.o relocate.o
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 8912098..2795a5f 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
@@ -5,14 +6,13 @@
* Based on mx27/generic.c:
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <netdev.h>
#include <asm/io.h>
+#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
@@ -57,6 +57,14 @@
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
+static ulong imx_get_upllclk(void)
+{
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong fref = MXC_HCLK;
+
+ return imx_decode_pll(readl(&ccm->upctl), fref);
+}
+
static ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
@@ -94,7 +102,8 @@
static ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong fref = imx_get_ahbclk();
+ ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
+ imx_get_ahbclk();
ulong div;
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
@@ -103,6 +112,25 @@
return fref / div;
}
+int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
+{
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
+ ulong div = (fref + freq - 1) / freq;
+
+ if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
+ return -EINVAL;
+
+ clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
+ CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
+ div << CCM_PERCLK_SHIFT(clk));
+ if (from_upll)
+ setbits_le32(&ccm->mcr, 1 << clk);
+ else
+ clrbits_le32(&ccm->mcr, 1 << clk);
+ return 0;
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
if (clk >= MXC_CLK_NUM)
@@ -186,14 +214,6 @@
}
#endif
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-#endif
-}
-
#if defined(CONFIG_FEC_MXC)
/*
* Initializes on-chip ethernet controllers.
diff --git a/arch/arm/cpu/arm926ejs/mx25/relocate.S b/arch/arm/cpu/arm926ejs/mx25/relocate.S
index 8ebb81f..709e35c 100644
--- a/arch/arm/cpu/arm926ejs/mx25/relocate.S
+++ b/arch/arm/cpu/arm926ejs/mx25/relocate.S
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX25-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c
index 5db689d..576f7fa 100644
--- a/arch/arm/cpu/arm926ejs/mx25/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx25/reset.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -12,8 +13,6 @@
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 7f19791..04698fe 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -16,8 +17,6 @@
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
* Add support for MX25
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 0edf144..ac5ebaf 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -1,11 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-# SPDX-License-Identifier: GPL-2.0+
-obj-y = generic.o reset.o timer.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += generic.o timer.o reset.o relocate.o
diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
index 5ee9f07..08b1b4d 100644
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -12,7 +11,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-#ifdef CONFIG_MXC_MMC
+#include <asm/mach-imx/sys_proto.h>
+#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
@@ -159,6 +159,11 @@
}
+u32 get_cpu_rev(void)
+{
+ return MXC_CPU_MX27 << 12;
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
@@ -190,7 +195,7 @@
*/
int cpu_mmc_init(bd_t *bis)
{
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
#else
return 0;
@@ -334,7 +339,7 @@
}
#endif /* CONFIG_FEC_MXC */
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
void mx27_sd1_init_pins(void)
{
int i;
@@ -368,12 +373,4 @@
imx_gpio_mode(mode[i]);
}
-#endif /* CONFIG_MXC_MMC */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* CONFIG_MMC_MXC */
diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S
index 0c4b272..5dfa272 100644
--- a/arch/arm/cpu/arm926ejs/mx27/relocate.S
+++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c
index f7b4a1c..e2437d1 100644
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx27/reset.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -12,8 +13,6 @@
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -27,14 +26,14 @@
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
- writel(0x00000000, ®s->wcr);
+ writew(0x0000, ®s->wcr);
/* Write Service Sequence */
- writel(0x00005555, ®s->wsr);
- writel(0x0000AAAA, ®s->wsr);
+ writew(0x5555, ®s->wsr);
+ writew(0xAAAA, ®s->wsr);
/* Enable watchdog */
- writel(WCR_WDE, ®s->wcr);
+ writew(WCR_WDE, ®s->wcr);
while (1);
/*NOTREACHED*/
diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c
index 40fe2aa..94b5d45 100644
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx27/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -12,8 +13,6 @@
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -127,7 +126,7 @@
return timestamp;
}
-ulong get_timer_masked(void)
+static ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 6c59494..f60e61e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-$(CONFIG_SPL_BUILD) := start.o
@@ -14,8 +12,8 @@
endif
# Specify the target for use in elftosb call
-MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
-MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
+MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
# Generate HAB-capable IVT
#
@@ -74,12 +72,10 @@
%.sig: %.csf
$(call if_changed,mkcst_mxs)
-quiet_cmd_mkimage_mxs = MKIMAGE $@
-cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
+MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage
u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage_mxs)
+ $(call if_changed,mkimage)
+MKIMAGEFLAGS_u-boot-signed.sb = -n $< -T mxsimage
u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
- $(call if_changed,mkimage_mxs)
+ $(call if_changed,mkimage)
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index e9d8800..43d044d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX23/i.MX28 clock setup code
*
@@ -6,12 +7,10 @@
*
* Based on code from LTIB:
* Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
@@ -309,7 +308,7 @@
bus, tgtclk, freq);
}
-void mxs_set_lcdclk(uint32_t freq)
+void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c
index 2e6be06..381264b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/iomux.c
+++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c
@@ -1,14 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index ef130ae..85c65dc 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX23/i.MX28 common code
*
@@ -6,15 +7,13 @@
*
* Based on code from LTIB:
* Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
@@ -24,7 +23,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
-inline void lowlevel_init(void) {}
+__weak void lowlevel_init(void) {}
void reset_cpu(ulong ignored) __attribute__((noreturn));
@@ -50,16 +49,6 @@
;
}
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
/*
* This function will craft a jumptable at 0x0 which will redirect interrupt
* vectoring to proper location of U-Boot in RAM.
@@ -132,23 +121,7 @@
return 0;
}
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static const char *get_cpu_type(void)
-{
- struct mxs_digctl_regs *digctl_regs =
- (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
-
- switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
- case HW_DIGCTL_CHIPID_MX23:
- return "23";
- case HW_DIGCTL_CHIPID_MX28:
- return "28";
- default:
- return "??";
- }
-}
-
-static const char *get_cpu_rev(void)
+u32 get_cpu_rev(void)
{
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
@@ -158,38 +131,49 @@
case HW_DIGCTL_CHIPID_MX23:
switch (rev) {
case 0x0:
- return "1.0";
case 0x1:
- return "1.1";
case 0x2:
- return "1.2";
case 0x3:
- return "1.3";
case 0x4:
- return "1.4";
+ return (MXC_CPU_MX23 << 12) | (rev + 0x10);
default:
- return "??";
+ return 0;
}
case HW_DIGCTL_CHIPID_MX28:
switch (rev) {
case 0x1:
- return "1.2";
+ return (MXC_CPU_MX28 << 12) | 0x12;
default:
- return "??";
+ return 0;
}
default:
+ return 0;
+ }
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+const char *get_imx_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_MX23:
+ return "23";
+ case MXC_CPU_MX28:
+ return "28";
+ default:
return "??";
}
}
int print_cpuinfo(void)
{
- struct mxs_spl_data *data = (struct mxs_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ u32 cpurev;
+ struct mxs_spl_data *data = MXS_SPL_DATA;
- printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
- get_cpu_type(),
- get_cpu_rev(),
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
return 0;
@@ -281,8 +265,7 @@
int mxs_dram_init(void)
{
- struct mxs_spl_data *data = (struct mxs_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = MXS_SPL_DATA;
if (data->mem_dram_size == 0) {
printf("MXS:\n"
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
index 1200ae1..062deb7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Freescale i.MX28 SPL functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __M28_INIT_H__
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
new file mode 100644
index 0000000..ab2183e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
@@ -0,0 +1,5 @@
+DISPLAYPROGRESS
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x1000 spl/u-boot-spl.bin
+ CALL 0x1000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
new file mode 100644
index 0000000..0d95064
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
@@ -0,0 +1,6 @@
+DISPLAYPROGRESS
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x1000 spl/u-boot-spl.bin
+ LOAD IVT 0x8000 0x1000
+ CALL HAB 0x8000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index d29b9aa..cb361ac 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX28 Boot setup
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -40,24 +39,17 @@
;
}
+#if defined(CONFIG_MX23)
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
static const iomux_cfg_t iomux_boot[] = {
-#if defined(CONFIG_MX23)
MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-#elif defined(CONFIG_MX28)
- MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
- MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
- MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
- MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
- MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
- MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-#endif
};
+#endif
static uint8_t mxs_get_bootmode_index(void)
{
@@ -65,10 +57,10 @@
int i;
uint8_t masked;
+#if defined(CONFIG_MX23)
/* Setup IOMUX of bootmode pads to GPIO */
mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
-#if defined(CONFIG_MX23)
/* Setup bootmode pins as GPIO input */
gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
@@ -83,21 +75,11 @@
bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
#elif defined(CONFIG_MX28)
- /* Setup bootmode pins as GPIO input */
- gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
- gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
- gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2);
- gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3);
- gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4);
- gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5);
-
- /* Read bootmode pads */
- bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
- bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
- bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
- bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
- bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
- bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+ /* The global boot mode will be detected by ROM code and its value
+ * is stored at the fixed address 0x00019BF0 in OCRAM.
+ */
+#define GLOBAL_BOOT_MODE_ADDR 0x00019BF0
+ bootmode = __raw_readl(GLOBAL_BOOT_MODE_ADDR);
#endif
for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
@@ -137,8 +119,7 @@
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
- struct mxs_spl_data *data = (struct mxs_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = MXS_SPL_DATA;
uint8_t bootmode = mxs_get_bootmode_index();
gd = &gdata;
@@ -147,6 +128,7 @@
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
mxs_spl_console_init();
+ debug("SPL: Serial Console Initialised\n");
mxs_power_init();
@@ -156,8 +138,14 @@
data->boot_mode_idx = bootmode;
mxs_power_wait_pswitch();
+
+ if (mxs_boot_modes[data->boot_mode_idx].boot_pads == MXS_BM_JTAG) {
+ debug("SPL: Waiting for JTAG user\n");
+ asm volatile ("x: b x");
+ }
}
+#ifndef CONFIG_SPL_FRAMEWORK
/* Support aparatus */
inline void board_init_f(unsigned long bootflag)
{
@@ -170,3 +158,4 @@
for (;;)
;
}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
index cdfcddd..cfd6c4a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX28 Battery measurement init
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -18,6 +17,8 @@
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Initialisating LRADC\n");
+
writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr);
@@ -37,9 +38,15 @@
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Enabling LRADC battery measurement\n");
+
/* Check if the channel is present at all. */
- if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+ if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
+ debug("SPL: LRADC channel 7 is not present - aborting\n");
return;
+ }
+
+ debug("SPL: LRADC channel 7 is present - configuring\n");
writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr);
writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr);
@@ -65,6 +72,7 @@
100, ®s->hw_lradc_delay3);
writel(0xffffffff, ®s->hw_lradc_ch7_clr);
-
writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set);
+
+ debug("SPL: LRADC channel 7 configuration complete\n");
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 97ef67d..7818d72 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX28 RAM init
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -16,7 +15,7 @@
#include "mxs_init.h"
-static uint32_t dram_vals[] = {
+__weak uint32_t mxs_dram_vals[] = {
/*
* i.MX28 DDR2 at 200MHz
*/
@@ -92,6 +91,7 @@
__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{
+ debug("SPL: Using default SDRAM parameters\n");
}
#ifdef CONFIG_MX28
@@ -99,17 +99,20 @@
{
int i;
- mxs_adjust_memory_params(dram_vals);
+ debug("SPL: Setting mx28 board specific SDRAM parameters\n");
+ mxs_adjust_memory_params(mxs_dram_vals);
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ debug("SPL: Applying SDRAM parameters\n");
+ for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
+ writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
#else
static void initialize_dram_values(void)
{
int i;
- mxs_adjust_memory_params(dram_vals);
+ debug("SPL: Setting mx23 board specific SDRAM parameters\n");
+ mxs_adjust_memory_params(mxs_dram_vals);
/*
* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
@@ -120,10 +123,11 @@
* HW_DRAM_CTL8 is setup as the last element.
* So skip the initialization of these HW_DRAM_CTL registers.
*/
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+ debug("SPL: Applying SDRAM parameters\n");
+ for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
/*
@@ -146,6 +150,8 @@
const unsigned char divider = 21;
#endif
+ debug("SPL: Initialising FRAC0\n");
+
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
@@ -170,6 +176,7 @@
&clkctrl_regs->hw_clkctrl_clkseq_clr);
early_delay(10000);
+ debug("SPL: FRAC0 Initialised\n");
}
static void mxs_mem_setup_cpu_and_hbus(void)
@@ -177,6 +184,8 @@
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Setting CPU and HBUS clock frequencies\n");
+
/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
* and ungate CPU clock */
writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
@@ -209,6 +218,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring VDDA\n");
+
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
@@ -240,6 +251,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Setting mx23 VDDMEM\n");
+
/* We must wait before and after disabling the current limiter! */
early_delay(10000);
@@ -252,6 +265,8 @@
static void mx23_mem_init(void)
{
+ debug("SPL: Initialising mx23 SDRAM Controller\n");
+
/*
* Reset/ungate the EMI block. This is essential, otherwise the system
* suffers from memory instability. This thing is mx23 specific and is
@@ -297,6 +312,8 @@
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+ debug("SPL: Initialising mx28 SDRAM Controller\n");
+
/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 1c54ab7..a5c528a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX28 Boot PMIC init
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -14,6 +13,13 @@
#include "mxs_init.h"
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
+#else
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
+#endif
/**
* mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
*
@@ -26,6 +32,8 @@
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Switching CPU clock to 24MHz XTAL\n");
+
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
@@ -43,9 +51,23 @@
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Switching CPU core clock source to PLL\n");
+
+ /*
+ * TODO: Are we really? It looks like we turn on PLL0, but we then
+ * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
+ * set by mxs_power_clock2xtal()). Clearing this bit here seems to
+ * introduce some instability (causing the CPU core to hang). Maybe
+ * we aren't giving PLL0 enough time to stabilise?
+ */
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
early_delay(100);
+
+ /*
+ * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
+ * wait on the PLL0 LOCK bit?
+ */
setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
@@ -62,6 +84,8 @@
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
+ debug("SPL: Setting auto-restart bit\n");
+
writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
;
@@ -101,14 +125,17 @@
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Set linear regulator 25mV below switching converter */
+ debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+ debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_LINREG_OFFSET_MASK,
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+ debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
@@ -127,6 +154,8 @@
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
+
+ debug("SPL: Battery Voltage = %dmV\n", volt);
return volt;
}
@@ -154,8 +183,10 @@
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mxs_get_batt_volt();
- if ((volt >= 2400) && (volt <= 4300))
+ if ((volt >= 2400) && (volt <= 4300)) {
+ debug("SPL: Battery is good\n");
return 1;
+ }
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@@ -175,16 +206,21 @@
volt = mxs_get_batt_volt();
- if (volt >= 3500)
+ if (volt >= 3500) {
+ debug("SPL: Battery Voltage too high\n");
return 0;
+ }
- if (volt >= 2400)
+ if (volt >= 2400) {
+ debug("SPL: Battery is good\n");
return 1;
+ }
writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
&power_regs->hw_power_charge_clr);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+ debug("SPL: Battery Voltage too low\n");
return 0;
}
@@ -203,6 +239,7 @@
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Start 5V detection */
+ debug("SPL: Starting 5V input detection comparator\n");
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
@@ -210,6 +247,39 @@
}
/**
+ * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
+ * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock
+ *
+ * This function configures and then enables an alternative PLL clock source
+ * for the DC-DC converters.
+ */
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
+{
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
+
+ /* Select clocksource for DC-DC converters */
+ clrsetbits_le32(&power_regs->hw_power_misc,
+ POWER_MISC_FREQSEL_MASK,
+ freqsel);
+ setbits_le32(&power_regs->hw_power_misc,
+ POWER_MISC_SEL_PLLCLK);
+}
+
+/**
+ * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
+ *
+ * Normally, there is no need to switch DC-DC clocksource. This is the reason,
+ * why this function is a stub and does nothing. However, boards can implement
+ * this function when required and call mxs_power_switch_dcdc_clocksource() to
+ * switch to an alternative clock source.
+ */
+__weak void mxs_power_setup_dcdc_clocksource(void)
+{
+ debug("SPL: Using default DC-DC clocksource\n");
+}
+
+/**
* mxs_src_power_init() - Preconfigure the power block
*
* This function configures reasonable values for the DC-DC control loop
@@ -220,6 +290,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Pre-Configuring power block\n");
+
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
@@ -257,6 +329,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring common 4P2 regulator params\n");
+
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
@@ -268,8 +342,7 @@
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_DROPOUT_CTRL_MASK,
- POWER_DCDC4P2_DROPOUT_CTRL_100MV |
- POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+ DCDC4P2_DROPOUT_CONFIG);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@@ -289,6 +362,13 @@
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
+ debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
+
+ if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return;
+ }
+
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
@@ -300,11 +380,6 @@
clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
- if (xfer && (readl(&power_regs->hw_power_5vctrl) &
- POWER_5VCTRL_ENABLE_DCDC)) {
- return;
- }
-
/*
* Recording orignal values that will be modified temporarlily
* to handle a chip bug. See chip errata for CQ ENGR00115837
@@ -390,6 +465,8 @@
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
+ debug("SPL: Enabling 4P2 regulator\n");
+
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
@@ -407,6 +484,7 @@
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
+ debug("SPL: Charging 4P2 capacitor\n");
mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
@@ -420,6 +498,8 @@
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
+
+ debug("SPL: Unable to recover from mx23 errata 5837\n");
hang();
}
@@ -433,6 +513,7 @@
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
+ debug("SPL: Setting 4P2 brownout level\n");
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
@@ -479,8 +560,11 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Switching DC-DC converters to 4P2\n");
+
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
+ debug("SPL: Already switched - aborting\n");
hang();
}
@@ -509,6 +593,8 @@
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
+ debug("SPL: Powering up 4P2 regulator\n");
+
vdddctrl = readl(&power_regs->hw_power_vdddctrl);
vddactrl = readl(&power_regs->hw_power_vddactrl);
vddioctrl = readl(&power_regs->hw_power_vddioctrl);
@@ -559,6 +645,8 @@
if (tmp)
writel(POWER_CHARGE_ENABLE_LOAD,
&power_regs->hw_power_charge_clr);
+
+ debug("SPL: 4P2 regulator powered-up\n");
}
/**
@@ -574,6 +662,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Booting from 5V supply\n");
+
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
@@ -601,6 +691,9 @@
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+
+ debug("Powering Down\n");
+
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
@@ -617,6 +710,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring power block to boot from battery\n");
+
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
@@ -672,6 +767,8 @@
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
+ debug("SPL: Resolving 5V conflict\n");
+
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_BO_OFFSET_MASK);
@@ -683,19 +780,27 @@
* VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
* unreliable
*/
+ debug("SPL: VDDIO has a brownout\n");
mxs_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
mxs_boot_valid_5v();
break;
} else {
+ debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
mxs_powerdown();
break;
}
+ /*
+ * TODO: I can't see this being reached. We'll either
+ * powerdown or boot from a stable 5V supply.
+ */
if (tmp & POWER_STS_PSWITCH_MASK) {
+ debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
mxs_batt_boot();
break;
}
@@ -713,21 +818,26 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring power block to boot from 5V input\n");
+
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: 5V VDD good\n");
mxs_boot_valid_5v();
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
return;
}
+ debug("SPL: 5V VDD not good\n");
mxs_handle_5v_conflict();
}
@@ -742,6 +852,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Initialising battery brown-out level to 3.0V\n");
+
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
@@ -762,6 +874,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Switching VDDD to DC-DC converters\n");
+
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
@@ -788,6 +902,9 @@
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Configuring power source\n");
+
+ mxs_power_setup_dcdc_clocksource();
mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
@@ -811,6 +928,10 @@
mxs_batt_boot();
}
+ /*
+ * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
+ * from USB VBUS
+ */
mxs_power_clock2pll();
mxs_init_batt_bo();
@@ -819,6 +940,7 @@
#ifdef CONFIG_MX23
/* Fire up the VDDMEM LinReg now that we're all set. */
+ debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
&power_regs->hw_power_vddmemctrl);
#endif
@@ -838,6 +960,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Enabling output rail protection\n");
+
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
@@ -1077,6 +1201,8 @@
*/
static void mxs_setup_batt_detect(void)
{
+ debug("SPL: Starting battery voltage measurement logic\n");
+
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
early_delay(10);
@@ -1111,6 +1237,8 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Initialising Power Block\n");
+
mxs_ungate_power();
mxs_power_clock2xtal();
@@ -1123,9 +1251,13 @@
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
+ debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
- mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
+
+ debug("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n");
+ mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1315);
#ifdef CONFIG_MX23
+ debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
@@ -1150,6 +1282,7 @@
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Waiting for power switch input\n");
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S
index 9b60436..adec2c8 100644
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
@@ -15,14 +16,11 @@
* Change to support call back into iMX28 bootrom
* Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
-#include <version.h>
/*
*************************************************************************
diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index f2e7225..7492ba4 100644
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX28 timer driver
*
@@ -6,8 +7,6 @@
*
* Based on code from LTIB:
* (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -111,14 +110,9 @@
return timestamp;
}
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
ulong get_timer(ulong base)
{
- return get_timer_masked() - base;
+ return tick_to_time(get_ticks()) - base;
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index bf2ac13..ffc70ce 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@@ -7,8 +8,6 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
deleted file mode 100644
index 265f336..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if ARCH_NOMADIK
-
-choice
- prompt "Nomadik board select"
-
-config NOMADIK_NHK8815
- bool "ST 8815 Nomadik Hardware Kit"
-
-endchoice
-
-config SYS_SOC
- default "nomadik"
-
-source "board/st/nhk8815/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/cpu/arm926ejs/nomadik/Makefile
deleted file mode 100644
index cdf1345..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o gpio.o
-obj-y += reset.o
diff --git a/arch/arm/cpu/arm926ejs/nomadik/gpio.c b/arch/arm/cpu/arm926ejs/nomadik/gpio.c
deleted file mode 100644
index eff5b2b..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/gpio.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
- NOMADIK_GPIO0_BASE,
- NOMADIK_GPIO1_BASE,
- NOMADIK_GPIO2_BASE,
- NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
- GPIO_DAT = 0x00, /* data register */
- GPIO_DATS = 0x04, /* data set */
- GPIO_DATC = 0x08, /* data clear */
- GPIO_PDIS = 0x0c, /* pull disable */
- GPIO_DIR = 0x10, /* direction */
- GPIO_DIRS = 0x14, /* direction set */
- GPIO_DIRC = 0x18, /* direction clear */
- GPIO_AFSLA = 0x20, /* alternate function select A */
- GPIO_AFSLB = 0x24, /* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
- return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
- return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
- u32 afunc, bfunc;
-
- /* alternate function is 0..3, with one bit per register */
- afunc = readl(base + GPIO_AFSLA) & ~bit;
- bfunc = readl(base + GPIO_AFSLB) & ~bit;
- if (alternate_function & 1) afunc |= bit;
- if (alternate_function & 2) bfunc |= bit;
- writel(afunc, base + GPIO_AFSLA);
- writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (dir)
- writel(bit, base + GPIO_DIRS);
- else
- writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (val)
- writel(bit, base + GPIO_DATS);
- else
- writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- return readl(base + GPIO_DAT) & bit;
-}
diff --git a/arch/arm/cpu/arm926ejs/nomadik/reset.S b/arch/arm/cpu/arm926ejs/nomadik/reset.S
deleted file mode 100644
index ec95472..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/reset.S
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
- ldr r1, =0x1
- str r1, [r0, #0x18]
-
-_loop_forever:
- b _loop_forever
diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c
deleted file mode 100644
index 775d0b7..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/timer.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK (24 * 100 * 1000)
-#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
-#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
- ulong val;
-
- writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
- CONFIG_SYS_TIMERBASE + MTU_CR(0));
-
- /* Reset the timer */
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
- /*
- * The load-register isn't really immediate: it changes on clock
- * edges, so we must wait for our newly-written value to appear.
- * Since we might miss reading 0, wait for any change in value.
- */
- val = READ_TIMER();
- while (READ_TIMER() == val)
- ;
-
- return 0;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
- return TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
- ulong ini, end;
-
- ini = READ_TIMER();
- end = ini + USEC_TO_COUNT(usec);
- while ((signed)(end - READ_TIMER()) > 0)
- ;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile
deleted file mode 100644
index add9232..0000000
--- a/arch/arm/cpu/arm926ejs/omap/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
-obj-y += reset.o
diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
deleted file mode 100644
index 587d99a..0000000
--- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * OMAP1 CPU identification code
- *
- * Copyright (C) 2004 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <command.h>
-#include <linux/compiler.h>
-
-#if defined(CONFIG_OMAP)
-
-#define omap_readw(x) *(volatile unsigned short *)(x)
-#define omap_readl(x) *(volatile unsigned long *)(x)
-
-#define OMAP_DIE_ID_0 0xfffe1800
-#define OMAP_DIE_ID_1 0xfffe1804
-#define OMAP_PRODUCTION_ID_0 0xfffe2000
-#define OMAP_PRODUCTION_ID_1 0xfffe2004
-#define OMAP32_ID_0 0xfffed400
-#define OMAP32_ID_1 0xfffed404
-
-struct omap_id {
- u16 jtag_id; /* Used to determine OMAP type */
- u8 die_rev; /* Processor revision */
- u32 omap_id; /* OMAP revision */
- u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] = {
- { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
- { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
- { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
- { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
- { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
- { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
- { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
- { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
- { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
- { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
- { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
- { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
- { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
- { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
- { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
- { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
- { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
- { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
- { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
-};
-
-/*
- * Get OMAP type from PROD_ID.
- * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
- * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
- * Undocumented register in TEST BLOCK is used as fallback; This seems to
- * work on 1510, 1610 & 1710. The official way hopefully will work in future
- * processors.
- */
-static u16 omap_get_jtag_id(void)
-{
- u32 prod_id, omap_id;
-
- prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
- omap_id = omap_readl(OMAP32_ID_1);
-
- /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
- if (((prod_id >> 20) == 0) || (prod_id == omap_id))
- prod_id = 0;
- else
- prod_id &= 0xffff;
-
- if (prod_id)
- return prod_id;
-
- /* Use OMAP32_ID_1 as fallback */
- prod_id = ((omap_id >> 12) & 0xffff);
-
- return prod_id;
-}
-
-/*
- * Get OMAP revision from DIE_REV.
- * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
- * Undocumented register in the TEST BLOCK is used as fallback.
- * REVISIT: This does not seem to work on 1510
- */
-static u8 omap_get_die_rev(void)
-{
- u32 die_rev;
-
- die_rev = omap_readl(OMAP_DIE_ID_1);
-
- /* Check for broken OMAP_DIE_ID on early 1710 */
- if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
- die_rev = 0;
-
- die_rev = (die_rev >> 17) & 0xf;
- if (die_rev)
- return die_rev;
-
- die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
-
- return die_rev;
-}
-
-static unsigned long dpll1(void)
-{
- unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
- unsigned long rate;
-
- rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
- if (pll_ctl_val & 0x10) {
- /* PLL enabled, apply multiplier and divisor */
- if (pll_ctl_val & 0xf80)
- rate *= (pll_ctl_val & 0xf80) >> 7;
- rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
- } else {
- /* PLL disabled, apply bypass divisor */
- switch (pll_ctl_val & 0xc) {
- case 0:
- break;
- case 0x4:
- rate /= 2;
- break;
- default:
- rate /= 4;
- break;
- }
- }
-
- return rate;
-}
-
-static unsigned long armcore(void)
-{
- unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
-
- return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
-}
-
-int print_cpuinfo (void)
-{
- int i;
- u16 jtag_id;
- u8 die_rev;
- u32 omap_id;
- u8 cpu_type;
- __maybe_unused u32 system_serial_high;
- __maybe_unused u32 system_serial_low;
- u32 system_rev = 0;
-
- jtag_id = omap_get_jtag_id();
- die_rev = omap_get_die_rev();
- omap_id = omap_readl(OMAP32_ID_0);
-
-#ifdef DEBUG
- printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
- printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
- omap_readl(OMAP_DIE_ID_1),
- (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
- printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
- printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
- omap_readl(OMAP_PRODUCTION_ID_1),
- omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
- printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
- printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
- printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
-#endif
-
- system_serial_high = omap_readl(OMAP_DIE_ID_0);
- system_serial_low = omap_readl(OMAP_DIE_ID_1);
-
- /* First check only the major version in a safe way */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (jtag_id == (omap_ids[i].jtag_id)) {
- system_rev = omap_ids[i].type;
- break;
- }
- }
-
- /* Check if we can find the die revision */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
- system_rev = omap_ids[i].type;
- break;
- }
- }
-
- /* Finally check also the omap_id */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (jtag_id == omap_ids[i].jtag_id
- && die_rev == omap_ids[i].die_rev
- && omap_id == omap_ids[i].omap_id) {
- system_rev = omap_ids[i].type;
- break;
- }
- }
-
- /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
- cpu_type = system_rev >> 24;
-
- switch (cpu_type) {
- case 0x07:
- system_rev |= 0x07;
- break;
- case 0x03:
- case 0x15:
- system_rev |= 0x15;
- break;
- case 0x16:
- case 0x17:
- system_rev |= 0x16;
- break;
- case 0x24:
- system_rev |= 0x24;
- break;
- default:
- printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
- }
-
- printf("CPU: OMAP%04x", system_rev >> 16);
- if ((system_rev >> 8) & 0xff)
- printf("%x", (system_rev >> 8) & 0xff);
-#ifdef DEBUG
- printf(" revision %i handled as %02xxx id: %08x%08x",
- die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
-#endif
- printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
- armcore() / 1000000, (armcore() / 100000) % 10,
- dpll1() / 1000000, (dpll1() / 100000) % 10);
-
- return 0;
-}
-
-#endif /* #if defined(CONFIG_OMAP) */
diff --git a/arch/arm/cpu/arm926ejs/omap/reset.S b/arch/arm/cpu/arm926ejs/omap/reset.S
deleted file mode 100644
index 1c557b0..0000000
--- a/arch/arm/cpu/arm926ejs/omap/reset.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * armboot - Startup Code for ARM926EJS CPU-core
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-_loop_forever:
- b _loop_forever
-
-rstctl1:
- .word 0xfffece10
diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c
deleted file mode 100644
index b971565..0000000
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \
- / (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-int timer_init (void)
-{
- int32_t val;
-
- /* Start the decrementer ticking down from 0xffffffff */
- *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
- *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- }else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer (0); /* get current timestamp */
- if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
- else
- tmo += tmp; /* else, set advancing stamp wake up time */
-
- while (get_timer_masked () < tmo)/* loop till event */
- /*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
- } else { /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and cause problems.
- */
- timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
- CONFIG_SYS_HZ)) - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- endtime = get_timer_masked () + tmo;
-
- do {
- ulong now = get_timer_masked ();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
deleted file mode 100644
index 5a54262..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if ORION5X
-
-choice
- prompt "Marvell Orion board select"
-
-config TARGET_EDMINIV2
- bool "LaCie Ethernet Disk mini V2"
-
-endchoice
-
-config SYS_SOC
- default "orion5x"
-
-source "board/LaCie/edminiv2/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile
deleted file mode 100644
index 546ebcb..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# Based on original Kirkwood support which is
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o
-obj-y += dram.o
-obj-y += timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
deleted file mode 100644
index f88db3b..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <u-boot/md5.h>
-#include <asm/arch/cpu.h>
-
-#define BUFLEN 16
-
-void reset_cpu(unsigned long ignored)
-{
- struct orion5x_cpu_registers *cpureg =
- (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
-
- writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
- &cpureg->rstoutn_mask);
- writel(readl(&cpureg->sys_soft_rst) | 1,
- &cpureg->sys_soft_rst);
- while (1)
- ;
-}
-
-/*
- * Compute Window Size field value from size expressed in bytes
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
- * NOTES:
- * 1) A sizeval equal to 0x0 specifies 4 GiB.
- * 2) A return value of 0x0 specifies 64 KiB.
- */
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
-{
- /*
- * Calculate the number of 64 KiB blocks needed minus one (rounding up).
- * For sizeval > 0 this is equivalent to:
- * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
- */
- sizeval = (sizeval - 1) >> 16;
-
- /*
- * Propagate 'one' bits to the right by 'oring' them.
- * We need only treat bits 15-0.
- */
- sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
- sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
- sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
- sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
-
- return sizeval;
-}
-
-/*
- * orion5x_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Orion5x Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * NOTES:
- *
- * 1) in order to avoid windows with inconsistent control and base values
- * (which could prevent access to BOOTCS and hence execution from FLASH)
- * always disable window before writing the base value then reenable it
- * by writing the control value.
- *
- * 2) in order to avoid losing access to BOOTCS when disabling window 7,
- * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
- * then configure windows 6 for its own target.
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int orion5x_config_adr_windows(void)
-{
- struct orion5x_win_registers *winregs =
- (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
-
-/* Disable window 0, configure it for its intended target, enable it. */
- writel(0, &winregs[0].ctrl);
- writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
- writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
- writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
- ORION5X_WIN_ENABLE), &winregs[0].ctrl);
-/* Disable window 1, configure it for its intended target, enable it. */
- writel(0, &winregs[1].ctrl);
- writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
- writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
- writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
- ORION5X_WIN_ENABLE), &winregs[1].ctrl);
-/* Disable window 2, configure it for its intended target, enable it. */
- writel(0, &winregs[2].ctrl);
- writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
- ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
- ORION5X_WIN_ENABLE), &winregs[2].ctrl);
-/* Disable window 3, configure it for its intended target, enable it. */
- writel(0, &winregs[3].ctrl);
- writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
- ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
- ORION5X_WIN_ENABLE), &winregs[3].ctrl);
-/* Disable window 4, configure it for its intended target, enable it. */
- writel(0, &winregs[4].ctrl);
- writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
- ORION5X_WIN_ENABLE), &winregs[4].ctrl);
-/* Disable window 5, configure it for its intended target, enable it. */
- writel(0, &winregs[5].ctrl);
- writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
- ORION5X_WIN_ENABLE), &winregs[5].ctrl);
-/* Disable window 6, configure it for FLASH, enable it. */
- writel(0, &winregs[6].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
- ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-/* Disable window 7, configure it for FLASH, enable it. */
- writel(0, &winregs[7].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
- ORION5X_WIN_ENABLE), &winregs[7].ctrl);
-/* Disable window 6, configure it for its intended target, enable it. */
- writel(0, &winregs[6].ctrl);
- writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
- ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-
- return 0;
-}
-
-/*
- * Orion5x identification is done through PCIE space.
- */
-
-u32 orion5x_device_id(void)
-{
- return readl(PCIE_DEV_ID_OFF) >> 16;
-}
-
-u32 orion5x_device_rev(void)
-{
- return readl(PCIE_DEV_REV_OFF) & 0xff;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
-/* Display device and revision IDs.
- * This function must cover all known device/revision
- * combinations, not only the one for which u-boot is
- * compiled; this way, one can identify actual HW in
- * case of a mismatch.
- */
-int print_cpuinfo(void)
-{
- char dev_str[7]; /* room enough for 0x0000 plus null byte */
- char rev_str[5]; /* room enough for 0x00 plus null byte */
- char *dev_name = NULL;
- char *rev_name = NULL;
-
- u32 dev = orion5x_device_id();
- u32 rev = orion5x_device_rev();
-
- if (dev == MV88F5181_DEV_ID) {
- dev_name = "MV88F5181";
- if (rev == MV88F5181_REV_B1)
- rev_name = "B1";
- else if (rev == MV88F5181L_REV_A1) {
- dev_name = "MV88F5181L";
- rev_name = "A1";
- } else if (rev == MV88F5181L_REV_A0) {
- dev_name = "MV88F5181L";
- rev_name = "A0";
- }
- } else if (dev == MV88F5182_DEV_ID) {
- dev_name = "MV88F5182";
- if (rev == MV88F5182_REV_A2)
- rev_name = "A2";
- } else if (dev == MV88F5281_DEV_ID) {
- dev_name = "MV88F5281";
- if (rev == MV88F5281_REV_D2)
- rev_name = "D2";
- else if (rev == MV88F5281_REV_D1)
- rev_name = "D1";
- else if (rev == MV88F5281_REV_D0)
- rev_name = "D0";
- } else if (dev == MV88F6183_DEV_ID) {
- dev_name = "MV88F6183";
- if (rev == MV88F6183_REV_B0)
- rev_name = "B0";
- }
- if (dev_name == NULL) {
- sprintf(dev_str, "0x%04x", dev);
- dev_name = dev_str;
- }
- if (rev_name == NULL) {
- sprintf(rev_str, "0x%02x", rev);
- rev_name = rev_str;
- }
-
- printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- /* Enable and invalidate L2 cache in write through mode */
- invalidate_l2_cache();
-
- orion5x_config_adr_windows();
-
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
- u32 temp;
-
- /*CPU streaming & write allocate */
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 28); /* disable wr alloc */
- writefr_extra_feature_reg(temp);
-
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 29); /* streaming disabled */
- writefr_extra_feature_reg(temp);
-
- /* L2Cache settings */
- temp = readfr_extra_feature_reg();
- /* Disable L2C pre fetch - Set bit 24 */
- temp |= (1 << 24);
- /* enable L2C - Set bit 22 */
- temp |= (1 << 22);
- writefr_extra_feature_reg(temp);
-
- icache_enable();
- /* Change reset vector to address 0x0 */
- temp = get_cr();
- set_cr(temp & ~CR_V);
-
- /* Set CPIOs and MPPs - values provided by board
- include file */
- writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
- writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
- writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
- writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
- writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
- writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
-
- /* initialize timer */
- timer_init_r();
- return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVGBE
-int cpu_eth_init(bd_t *bis)
-{
- mvgbe_initialize(bis);
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
deleted file mode 100644
index 9ed93d2..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/arch/cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * orion5x_sdram_bar - reads SDRAM Base Address Register
- */
-u32 orion5x_sdram_bar(enum memory_bank bank)
-{
- struct orion5x_ddr_addr_decode_registers *winregs =
- (struct orion5x_ddr_addr_decode_registers *)
- ORION5X_DRAM_BASE;
-
- u32 result = 0;
- u32 enable = 0x01 & winregs[bank].size;
-
- if ((!enable) || (bank > BANK3))
- return 0;
-
- result = winregs[bank].base;
- return result;
-}
-int dram_init (void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
- (long *) orion5x_sdram_bar(0),
- CONFIG_MAX_RAM_BANK_SIZE);
- return 0;
-}
-
-void dram_init_banksize (void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
- gd->bd->bi_dram[i].size = get_ram_size(
- (long *) (gd->bd->bi_dram[i].start),
- CONFIG_MAX_RAM_BANK_SIZE);
- }
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
deleted file mode 100644
index 4dacc29..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include "asm/arch/orion5x.h"
-
-/*
- * Configuration values for SDRAM access setup
- */
-
-#define SDRAM_CONFIG 0x3148400
-#define SDRAM_MODE 0x62
-#define SDRAM_CONTROL 0x4041000
-#define SDRAM_TIME_CTRL_LOW 0x11602220
-#define SDRAM_TIME_CTRL_HI 0x40c
-#define SDRAM_OPEN_PAGE_EN 0x0
-/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
-#define SDRAM_BANK0_SIZE 0x3ff0001
-#define SDRAM_ADDR_CTRL 0x10
-
-#define SDRAM_OP_NOP 0x05
-#define SDRAM_OP_SETMODE 0x03
-
-#define SDRAM_PAD_CTRL_WR_EN 0x80000000
-#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
-#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
-#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
-
-/*
- * For Guideline MEM-3 - Drive Strength value
- */
-
-#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
-#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
-
-/*
- * For Guideline MEM-4 - DQS Reference Delay Tuning
- */
-
-#define MSAR_ARMDDRCLCK_MASK 0x000000f0
-#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
-
-#define MSAR_ARMDDRCLCK_333_167 0x00000000
-#define MSAR_ARMDDRCLCK_500_167 0x00000030
-#define MSAR_ARMDDRCLCK_667_167 0x00000060
-#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
-#define MSAR_ARMDDRCLCK_400_200 0x00000010
-#define MSAR_ARMDDRCLCK_600_200 0x00000050
-#define MSAR_ARMDDRCLCK_800_200 0x00000070
-
-#define FTDLL_DDR1_166MHZ 0x0047F001
-
-#define FTDLL_DDR1_200MHZ 0x0044D001
-
-/*
- * Low-level init happens right after start.S has switched to SVC32,
- * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
- */
-
-.globl lowlevel_init
-
-lowlevel_init:
-
- /* Use 'r4 as the base for internal register accesses */
- ldr r4, =ORION5X_REGS_PHY_BASE
-
- /* move internal registers from the default 0xD0000000
- * to their intended location, defined by SoC */
- ldr r3, =0xD0000000
- add r3, r3, #0x20000
- str r4, [r3, #0x80]
-
- /* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
-
- /*DDR SDRAM Initialization Control */
- ldr r6, =0x00000001
- str r6, [r3, #0x480]
-
- /* Use R3 as the base for PCI registers */
- add r3, r4, #0x31000
-
- /* Disable arbiter */
- ldr r6, =0x00000030
- str r6, [r3, #0xd00]
-
- /* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
-
- /* set all dram windows to 0 */
- mov r6, #0
- str r6, [r3, #0x504]
- str r6, [r3, #0x50C]
- str r6, [r3, #0x514]
- str r6, [r3, #0x51C]
-
- /* 1) Configure SDRAM */
- ldr r6, =SDRAM_CONFIG
- str r6, [r3, #0x400]
-
- /* 2) Set SDRAM Control reg */
- ldr r6, =SDRAM_CONTROL
- str r6, [r3, #0x404]
-
- /* 3) Write SDRAM address control register */
- ldr r6, =SDRAM_ADDR_CTRL
- str r6, [r3, #0x410]
-
- /* 4) Write SDRAM bank 0 size register */
- ldr r6, =SDRAM_BANK0_SIZE
- str r6, [r3, #0x504]
- /* keep other banks disabled */
-
- /* 5) Write SDRAM open pages control register */
- ldr r6, =SDRAM_OPEN_PAGE_EN
- str r6, [r3, #0x414]
-
- /* 6) Write SDRAM timing Low register */
- ldr r6, =SDRAM_TIME_CTRL_LOW
- str r6, [r3, #0x408]
-
- /* 7) Write SDRAM timing High register */
- ldr r6, =SDRAM_TIME_CTRL_HI
- str r6, [r3, #0x40C]
-
- /* 8) Write SDRAM mode register */
- /* The CPU must not attempt to change the SDRAM Mode register setting */
- /* prior to DRAM controller completion of the DRAM initialization */
- /* sequence. To guarantee this restriction, it is recommended that */
- /* the CPU sets the SDRAM Operation register to NOP command, performs */
- /* read polling until the register is back in Normal operation value, */
- /* and then sets SDRAM Mode register to its new value. */
-
- /* 8.1 write 'nop' to SDRAM operation */
- ldr r6, =SDRAM_OP_NOP
- str r6, [r3, #0x418]
-
- /* 8.2 poll SDRAM operation until back in 'normal' mode. */
-1:
- ldr r6, [r3, #0x418]
- cmp r6, #0
- bne 1b
-
- /* 8.3 Now its safe to write new value to SDRAM Mode register */
- ldr r6, =SDRAM_MODE
- str r6, [r3, #0x41C]
-
- /* 8.4 Set new mode */
- ldr r6, =SDRAM_OP_SETMODE
- str r6, [r3, #0x418]
-
- /* 8.5 poll SDRAM operation until back in 'normal' mode. */
-2:
- ldr r6, [r3, #0x418]
- cmp r6, #0
- bne 2b
-
- /* DDR SDRAM Address/Control Pads Calibration */
- ldr r6, [r3, #0x4C0]
-
- /* Set Bit [31] to make the register writable */
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C0]
-
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
- bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
- bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r6
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
- orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
-
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
- orr r6, r6, r1
- str r6, [r3, #0x4C0]
-
- /* DDR SDRAM Data Pads Calibration */
- ldr r6, [r3, #0x4C4]
-
- /* Set Bit [31] to make the register writable */
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C4]
-
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
- bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
- bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r6
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26
- orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
-
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
- orr r6, r6, r1
-
- str r6, [r3, #0x4C4]
-
- /* Implement Guideline (GL# MEM-3) Drive Strength Value */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
-
- ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
-
- /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
- ldr r6, [r3, #0x4C0]
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C0]
-
- /* Correct strength and disable writes again */
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
- orr r6, r6, r1
- str r6, [r3, #0x4C0]
-
- /* Enable writes to DDR SDRAM Data Pads Calibration register */
- ldr r6, [r3, #0x4C4]
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C4]
-
- /* Correct strength and disable writes again */
- bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- orr r6, r6, r1
- str r6, [r3, #0x4C4]
-
- /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
-
- /* Get the "sample on reset" register for the DDR frequancy */
- ldr r3, =0x10000
- ldr r6, [r3, #0x010]
- ldr r1, =MSAR_ARMDDRCLCK_MASK
- and r1, r6, r1
-
- ldr r6, =FTDLL_DDR1_166MHZ
- cmp r1, #MSAR_ARMDDRCLCK_333_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_500_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_667_167
- beq 3f
-
- ldr r6, =FTDLL_DDR1_200MHZ
- cmp r1, #MSAR_ARMDDRCLCK_400_200_1
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_400_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_600_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_800_200
- beq 3f
-
- ldr r6, =0
-
-3:
- /* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
-
- ldr r2, [r3, #0x484]
- orr r2, r2, r6
- str r2, [r3, #0x484]
-
- /* Return to U-boot via saved link register */
- mov pc, lr
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
deleted file mode 100644
index ec4f6be..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define UBOOT_CNTR 0 /* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct orion5x_tmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-
-/* Timer registers */
-struct orion5x_tmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct orion5x_tmr_val tmr[2];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
-struct orion5x_tmr_registers *orion5x_tmr_regs =
- (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
-#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
-#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
-#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS 0
-#define TRG_ARM_TIMER_REL_MASK 0xffffffff
-
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS 0
-#define TVR_ARM_TIMER_MASK 0xffffffff
-#define TVR_ARM_TIMER_MAX 0xffffffff
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline ulong read_timer(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR))
- / (CONFIG_SYS_TCLK / 1000);
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-static inline ulong uboot_cntr_val(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR));
-}
-
-void __udelay(unsigned long usec)
-{
- uint current;
- ulong delayticks;
-
- current = uboot_cntr_val();
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
- if (current < delayticks) {
- delayticks -= current;
- while (uboot_cntr_val() < current)
- ;
- while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
- ;
- } else {
- while (uboot_cntr_val() > (current - delayticks))
- ;
- }
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
- unsigned int cntmrctrl;
-
- /* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
- /* enable timer in auto reload mode */
- cntmrctrl = readl(CNTMR_CTRL_REG);
- cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
- cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
- writel(cntmrctrl, CNTMR_CTRL_REG);
- return 0;
-}
-
-void timer_init_r(void)
-{
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
new file mode 100644
index 0000000..fbdb1d7
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on:
+ *
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ CPUDIR/start.o (.text)
+ *(.text*)
+ } > .nor
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .nor
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .bss
+}
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644
index 988341f..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644
index 4e2a177..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- struct panthapb_registers *apbclkres =
- (struct panthapb_registers*) PANTHEON_APBC_BASE;
-
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
- struct panthapmu_registers *apmu =
- (struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
- /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Turn on clock gating (PMUM_CCGR) */
- writel(0xFFFFFFFF, &mpmu->ccgr);
-
- /* Turn on clock gating (PMUM_ACGR) */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on uart2 clock */
- writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
- writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
- /* Enable mmc clock */
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd1);
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd3);
-#endif
-
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644
index f77e3d0..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct panthddr_registers {
- u8 pad[0x100 - 0x000];
- struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = panth_sdram_base(i);
- gd->bd->bi_dram[i].size = panth_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /*
- * If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash
- */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644
index 6382d3b..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr[3];
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
- volatile int loop=100;
- ulong val;
-
- writel(COUNT_RD_REQ, &panthtimers->cvwr);
- while (loop--)
- val = readl(&panthtimers->cvwr);
-
- /*
- * This stop gcc complain and prevent loop mistake init to 0
- */
- val = readl(&panthtimers->cvwr);
-
- return val;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime)
- ;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct panthapb_registers *apb1clkres =
- (struct panthapb_registers *) PANTHEON_APBC_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
- /* Enable Timer clock at 3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &panthtimers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &panthtimers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &panthtimers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK, &mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0, &panthtimers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0xf, &panthtimers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0x3, &panthtimers->wdt_match_en);
-
- /*enable functional WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 3f190bc..b1b6b40 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -1,21 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y := cpu.o \
reset.o \
timer.o
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o spl_boot.o
+obj-y += spl.o
obj-$(CONFIG_SPEAR600) += spear600.o
obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+else
+obj-y += spr_misc.o spr_lowlevel_init.o
endif
extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 697e094..51c4a73 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -32,7 +31,7 @@
periph_clk_cfg |= CONFIG_SPEAR_UART48M;
writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
#endif
-#if defined(CONFIG_DESIGNWARE_ETH)
+#if defined(CONFIG_ETH_DESIGNWARE)
periph1_clken |= MISC_ETHENB;
#endif
#if defined(CONFIG_DW_UDC)
@@ -47,8 +46,18 @@
#if defined(CONFIG_NAND_FSMC)
periph1_clken |= MISC_FSMCENB;
#endif
+#if defined(CONFIG_USB_EHCI_SPEAR)
+ periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
+#endif
+#if defined(CONFIG_SPEAR_GPIO)
+ periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
+#endif
+#if defined(CONFIG_PL022_SPI)
+ periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
+#endif
writel(periph1_clken, &misc_p->periph1_clken);
+
return 0;
}
@@ -69,3 +78,37 @@
return 0;
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ /* 1-bit HW ECC */
+ printf("Switching to 1-bit HW ECC\n");
+ fsmc_nand_switch_ecc(1);
+ } else if (strncmp(argv[1], "bch4", 2) == 0) {
+ /* 4-bit SW ECC BCH4 */
+ printf("Switching to 4-bit SW ECC (BCH4)\n");
+ fsmc_nand_switch_ecc(4);
+ } else {
+ goto usage;
+ }
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 0, do_switch_ecc,
+ "switch NAND ECC calculation algorithm",
+ "hw|bch4 - Switch between NAND hardware 1-bit HW and"
+ " 4-bit SW BCH\n"
+);
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c
index 9546e80..05c7ecd 100644
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ b/arch/arm/cpu/arm926ejs/spear/reset.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
index 6474e9d..b31ede5 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -12,6 +11,21 @@
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_defs.h>
+void spear_late_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ writel(0x80000007, &misc_p->arb_icm_ml1);
+ writel(0x80000007, &misc_p->arb_icm_ml2);
+ writel(0x80000007, &misc_p->arb_icm_ml3);
+ writel(0x80000007, &misc_p->arb_icm_ml4);
+ writel(0x80000007, &misc_p->arb_icm_ml5);
+ writel(0x80000007, &misc_p->arb_icm_ml6);
+ writel(0x80000007, &misc_p->arb_icm_ml7);
+ writel(0x80000007, &misc_p->arb_icm_ml8);
+ writel(0x80000007, &misc_p->arb_icm_ml9);
+}
+
static void sel_1v8(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -104,14 +118,6 @@
}
/*
- * soc_init:
- */
-void soc_init(void)
-{
- /* Nothing to be done for SPEAr600 */
-}
-
-/*
* xxx_boot_selected:
*
* return true if the particular booting option is selected
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index b550404..d2bddb5 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -1,19 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_syscntl.h>
+#include <linux/mtd/st_smi.h>
static void ddr_clock_init(void)
{
@@ -205,55 +206,51 @@
#endif
}
-void lowlevel_init(void)
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+static void snor_init(void)
+{
+ struct smi_regs *const smicntl =
+ (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+ /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+ writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+ &smicntl->smi_cr1);
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode = 0;
+
+ /* Currently only SNOR is supported as the only */
+ if (snor_boot_selected()) {
+ /* SNOR-SMI initialization */
+ snor_init();
+
+ mode = BOOT_DEVICE_NOR;
+ }
+
+ return mode;
+}
+
+void board_init_f(ulong dummy)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- const char *u_boot_rev = U_BOOT_VERSION;
/* Initialize PLLs */
sys_init();
- /* Initialize UART */
- serial_init();
-
- /* Print U-Boot SPL version string */
- serial_puts("\nU-Boot SPL ");
- /* Avoid a second "U-Boot" coming from this string */
- u_boot_rev = &u_boot_rev[7];
- serial_puts(u_boot_rev);
- serial_puts(" (");
- serial_puts(U_BOOT_DATE);
- serial_puts(" - ");
- serial_puts(U_BOOT_TIME);
- serial_puts(")\n");
-
-#if defined(CONFIG_OS_BOOT)
- writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
- &misc_p->periph1_clken);
-#endif
+ preloader_console_init();
+ arch_cpu_init();
/* Enable IPs (release reset) */
writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
/* Initialize MPMC */
- serial_puts("Configure DDR\n");
+ puts("Configure DDR\n");
mpmc_init();
+ spear_late_init();
- /* SoC specific initialization */
- soc_init();
-}
-
-void spear_late_init(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
- writel(0x80000007, &misc_p->arb_icm_ml1);
- writel(0x80000007, &misc_p->arb_icm_ml2);
- writel(0x80000007, &misc_p->arb_icm_ml3);
- writel(0x80000007, &misc_p->arb_icm_ml4);
- writel(0x80000007, &misc_p->arb_icm_ml5);
- writel(0x80000007, &misc_p->arb_icm_ml6);
- writel(0x80000007, &misc_p->arb_icm_ml7);
- writel(0x80000007, &misc_p->arb_icm_ml8);
- writel(0x80000007, &misc_p->arb_icm_ml9);
+ board_init_r(NULL, 0);
}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
deleted file mode 100644
index c846d75..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <image.h>
-#include <linux/compiler.h>
-#include <asm/io.h>
-#include <asm/arch/spr_defs.h>
-#include <linux/mtd/st_smi.h>
-
-static const char kernel_name[] = "Linux";
-static const char loader_name[] = "U-Boot";
-
-int image_check_header(image_header_t *hdr, const char *name)
-{
- if (image_check_magic(hdr) &&
- (!strncmp(image_get_name(hdr), name, strlen(name))) &&
- image_check_hcrc(hdr)) {
- return 1;
- }
- return 0;
-}
-
-int image_check_data(image_header_t *hdr)
-{
- if (image_check_dcrc(hdr))
- return 1;
-
- return 0;
-}
-
-/*
- * SNOR (Serial NOR flash) related functions
- */
-void snor_init(void)
-{
- struct smi_regs *const smicntl =
- (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
-
- /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
- writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
- &smicntl->smi_cr1);
-}
-
-static int snor_image_load(u8 *load_addr, void (**image_p)(void),
- const char *image_name)
-{
- image_header_t *header;
-
- /*
- * Since calculating the crc in the SNOR flash does not
- * work, we copy the image to the destination address
- * minus the header size. And point the header to this
- * new destination. This will not work for address 0
- * of course.
- */
- header = (image_header_t *)load_addr;
- memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
- (const ulong *)load_addr,
- image_get_data_size(header) + sizeof(image_header_t));
- header = (image_header_t *)(image_get_load(header) -
- sizeof(image_header_t));
-
- if (image_check_header(header, image_name)) {
- if (image_check_data(header)) {
- /* Jump to boot image */
- *image_p = (void *)image_get_load(header);
- return 1;
- }
- }
-
- return 0;
-}
-
-static void boot_image(void (*image)(void))
-{
- void (*funcp)(void) __noreturn = (void *)image;
-
- (*funcp)();
-}
-
-/*
- * spl_boot:
- *
- * All supported booting types of all supported SoCs are listed here.
- * Generic readback APIs are provided for each supported booting type
- * eg. nand_read_skip_bad
- */
-u32 spl_boot(void)
-{
- void (*image)(void);
-
-#ifdef CONFIG_SPEAR_USBTTY
- plat_late_init();
- return 1;
-#endif
-
- /*
- * All the supported booting devices are listed here. Each of
- * the booting type supported by the platform would define the
- * macro xxx_BOOT_SUPPORTED to true.
- */
-
- if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
- /* SNOR-SMI initialization */
- snor_init();
-
- serial_puts("Booting via SNOR\n");
- /* Serial NOR booting */
- if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
- &image, loader_name)) {
- /* Platform related late initialasations */
- plat_late_init();
-
- /* Jump to boot image */
- serial_puts("Jumping to U-Boot\n");
- boot_image(image);
- return 1;
- }
- }
-
- if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
- /* NAND booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
- }
-
- if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
- /* PNOR booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
- }
-
- if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
- /* MMC booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
- }
-
- if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
- /* SPI booting */
- /* Not supported for any platform as of now */
- return 0;
- }
-
- if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
- /* I2C booting */
- /* Not supported for any platform as of now */
- return 0;
- }
-
- /*
- * All booting types without memory are listed as below
- * Control has to be returned to BootROM in case of all
- * the following booting scenarios
- */
-
- if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
- plat_late_init();
- return 1;
- }
-
- if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
- plat_late_init();
- return 1;
- }
-
- if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
- plat_late_init();
- return 1;
- }
-
- /* Ideally, the control should not reach here. */
- hang();
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
index 3d6ad04..79ab2a7 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
index 105b305..121b636 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
index 00b6b29..64c8bab 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
index a406c3e..8765466 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
new file mode 100644
index 0000000..417e87a
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <config.h>
+
+/*
+ * platform specific initializations are already done in Xloader
+ * Initializations already done include
+ * DDR, PLLs, IP's clock enable and reset release etc
+ */
+.globl lowlevel_init
+lowlevel_init:
+ mov pc, lr
+
+/* void setfreq(unsigned int device, unsigned int frequency) */
+.global setfreq
+setfreq:
+ stmfd sp!,{r14}
+ stmfd sp!,{r0-r12}
+
+ mov r8,sp
+ ldr sp,SRAM_STACK_V
+
+ /* Saving the function arguements for later use */
+ mov r4,r0
+ mov r5,r1
+
+ /* Putting DDR into self refresh */
+ ldr r0,DDR_07_V
+ ldr r1,[r0]
+ ldr r2,DDR_ACTIVE_V
+ bic r1, r1, r2
+ str r1,[r0]
+ ldr r0,DDR_57_V
+ ldr r1,[r0]
+ ldr r2,CYCLES_MASK_V
+ bic r1, r1, r2
+ ldr r2,REFRESH_CYCLES_V
+ orr r1, r1, r2, lsl #16
+ str r1,[r0]
+ ldr r0,DDR_07_V
+ ldr r1,[r0]
+ ldr r2,SREFRESH_MASK_V
+ orr r1, r1, r2
+ str r1,[r0]
+
+ /* flush pipeline */
+ b flush
+ .align 5
+flush:
+ /* Delay to ensure self refresh mode */
+ ldr r0,SREFRESH_DELAY_V
+delay:
+ sub r0,r0,#1
+ cmp r0,#0
+ bne delay
+
+ /* Putting system in slow mode */
+ ldr r0,SCCTRL_V
+ mov r1,#2
+ str r1,[r0]
+
+ /* Changing PLL(1/2) frequency */
+ mov r0,r4
+ mov r1,r5
+
+ cmp r4,#0
+ beq pll1_freq
+
+ /* Change PLL2 (DDR frequency) */
+ ldr r6,PLL2_FREQ_V
+ ldr r7,PLL2_CNTL_V
+ b pll2_freq
+
+pll1_freq:
+ /* Change PLL1 (CPU frequency) */
+ ldr r6,PLL1_FREQ_V
+ ldr r7,PLL1_CNTL_V
+
+pll2_freq:
+ mov r0,r6
+ ldr r1,[r0]
+ ldr r2,PLLFREQ_MASK_V
+ bic r1,r1,r2
+ mov r2,r5,lsr#1
+ orr r1,r1,r2,lsl#24
+ str r1,[r0]
+
+ mov r0,r7
+ ldr r1,P1C0A_V
+ str r1,[r0]
+ ldr r1,P1C0E_V
+ str r1,[r0]
+ ldr r1,P1C06_V
+ str r1,[r0]
+ ldr r1,P1C0E_V
+ str r1,[r0]
+
+lock:
+ ldr r1,[r0]
+ and r1,r1,#1
+ cmp r1,#0
+ beq lock
+
+ /* Putting system back to normal mode */
+ ldr r0,SCCTRL_V
+ mov r1,#4
+ str r1,[r0]
+
+ /* Putting DDR back to normal */
+ ldr r0,DDR_07_V
+ ldr r1,[R0]
+ ldr r2,SREFRESH_MASK_V
+ bic r1, r1, r2
+ str r1,[r0]
+ ldr r2,DDR_ACTIVE_V
+ orr r1, r1, r2
+ str r1,[r0]
+
+ /* Delay to ensure self refresh mode */
+ ldr r0,SREFRESH_DELAY_V
+1:
+ sub r0,r0,#1
+ cmp r0,#0
+ bne 1b
+
+ mov sp,r8
+ /* Resuming back to code */
+ ldmia sp!,{r0-r12}
+ ldmia sp!,{pc}
+
+SCCTRL_V:
+ .word 0xfca00000
+PLL1_FREQ_V:
+ .word 0xfca8000C
+PLL1_CNTL_V:
+ .word 0xfca80008
+PLL2_FREQ_V:
+ .word 0xfca80018
+PLL2_CNTL_V:
+ .word 0xfca80014
+PLLFREQ_MASK_V:
+ .word 0xff000000
+P1C0A_V:
+ .word 0x1C0A
+P1C0E_V:
+ .word 0x1C0E
+P1C06_V:
+ .word 0x1C06
+
+SREFRESH_DELAY_V:
+ .word 0x9999
+SRAM_STACK_V:
+ .word 0xD2800600
+DDR_07_V:
+ .word 0xfc60001c
+DDR_ACTIVE_V:
+ .word 0x01000000
+DDR_57_V:
+ .word 0xfc6000e4
+CYCLES_MASK_V:
+ .word 0xffff0000
+REFRESH_CYCLES_V:
+ .word 0xf0f0
+SREFRESH_MASK_V:
+ .word 0x00010000
+
+.global setfreq_sz
+setfreq_sz:
+ .word setfreq_sz - setfreq
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
new file mode 100644
index 0000000..371dea5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <i2c.h>
+#include <net.h>
+#include <linux/mtd/st_smi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_emi.h>
+#include <asm/arch/spr_defs.h>
+
+#define CPU 0
+#define DDR 1
+#define SRAM_REL 0xD2801000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer);
+#endif
+
+int dram_init(void)
+{
+ /* Store complete RAM size and return */
+ gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int board_early_init_f()
+{
+#if defined(CONFIG_ST_SMI)
+ smi_init();
+#endif
+ return 0;
+}
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_NET)
+ uchar mac_id[6];
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+ eth_env_set_enetaddr("ethaddr", mac_id);
+#endif
+ env_set("verify", "n");
+
+#if defined(CONFIG_SPEAR_USBTTY)
+ env_set("stdin", "usbtty");
+ env_set("stdout", "usbtty");
+ env_set("stderr", "usbtty");
+
+#ifndef CONFIG_SYS_NO_DCACHE
+ dcache_enable();
+#endif
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+ unsigned int tap;
+ unsigned int tsdp;
+ unsigned int tdpw;
+ unsigned int tdpr;
+ unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+ .tap = 0x10,
+ .tsdp = 0x05,
+ .tdpw = 0x0a,
+ .tdpr = 0x0a,
+ .tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+ .tap = 0xf,
+ .tsdp = 0x0,
+ .tdpw = 0xff,
+ .tdpr = 0x111,
+ .tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+ const struct cust_emi_para *p = &emi_timing_m28w640hc;
+ struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+ unsigned int cs;
+ unsigned int val, tmp;
+
+ val = readl(CONFIG_SPEAR_RASBASE);
+
+ if (val & EMI_ACKMSK)
+ tmp = 0x3f;
+ else
+ tmp = 0x0;
+
+ writel(tmp, &emi_regs_p->ack);
+
+ for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+ writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+ writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+ writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+ writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+ writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+ writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+ &emi_regs_p->bank_regs[cs].control);
+ }
+}
+#endif
+
+int spear_board_init(ulong mach_type)
+{
+ gd->bd->bi_arch_number = mach_type;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+#ifdef CONFIG_SPEAR_EMI
+ spear_emi_init();
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer)
+{
+ u8 buf[2];
+
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+ /* Check if mac in i2c memory is valid */
+ if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+ /* Valid mac address is saved in i2c eeprom */
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
+ return 0;
+ }
+
+ return -1;
+}
+
+static int write_mac(uchar *mac)
+{
+ u8 buf[2];
+
+ buf[0] = (u8)MAGIC_BYTE0;
+ buf[1] = (u8)MAGIC_BYTE1;
+ i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+ buf[0] = (u8)~MAGIC_BYTE0;
+ buf[1] = (u8)~MAGIC_BYTE1;
+
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+ /* check if valid MAC address is saved in I2C EEPROM or not? */
+ if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+ i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
+ puts("I2C EEPROM written with mac address \n");
+ return 0;
+ }
+
+ puts("I2C EEPROM writing failed\n");
+ return -1;
+}
+#endif
+
+int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ void (*sram_setfreq) (unsigned int, unsigned int);
+ unsigned int frequency;
+#if defined(CONFIG_CMD_NET)
+ unsigned char mac[6];
+#endif
+
+ if ((argc > 3) || (argc < 2))
+ return cmd_usage(cmdtp);
+
+ if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
+
+ frequency = simple_strtoul(argv[2], NULL, 0);
+
+ if (frequency > 333) {
+ printf("Frequency is limited to 333MHz\n");
+ return 1;
+ }
+
+ sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
+
+ if (!strcmp(argv[1], "cpufreq")) {
+ sram_setfreq(CPU, frequency);
+ printf("CPU frequency changed to %u\n", frequency);
+ } else {
+ sram_setfreq(DDR, frequency);
+ printf("DDR frequency changed to %u\n", frequency);
+ }
+
+ return 0;
+
+#if defined(CONFIG_CMD_NET)
+ } else if (!strcmp(argv[1], "ethaddr")) {
+
+ u32 reg;
+ char *e, *s = argv[2];
+ for (reg = 0; reg < 6; ++reg) {
+ mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+ write_mac(mac);
+
+ return 0;
+#endif
+ } else if (!strcmp(argv[1], "print")) {
+#if defined(CONFIG_CMD_NET)
+ if (!i2c_read_mac(mac)) {
+ printf("Ethaddr (from i2c mem) = %pM\n", mac);
+ } else {
+ printf("Ethaddr (from i2c mem) = Not set\n");
+ }
+#endif
+ return 0;
+ }
+
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
+ "configure chip",
+ "chip_config cpufreq/ddrfreq frequency\n"
+#if defined(CONFIG_CMD_NET)
+ "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
+#endif
+ "chip_config print");
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
index 290ac2e..1cab4ca 100644
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
@@ -10,8 +11,6 @@
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
@@ -45,7 +44,6 @@
* BSS area lies in the DDR location which is not yet initialized
* bss is assumed to be uninitialized.
*/
- bl spl_boot
ldmia sp!, {r0-r12,pc}
/*
@@ -77,5 +75,5 @@
* Go setup Memory and board specific bits prior to relocation.
*/
stmdb sp!, {lr}
- bl lowlevel_init /* go setup pll,mux,memory */
+ bl _main /* _main will call board_init_f */
ldmia sp!, {pc}
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index c88e962..e7b5bda 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -22,6 +21,8 @@
DECLARE_GLOBAL_DATA_PTR;
+static ulong get_timer_masked(void);
+
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
@@ -37,7 +38,7 @@
writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
synth = MISC_GPT3SYNTH;
#else
-# error Incorrect config. Can only be spear{600|300|310|320}
+# error Incorrect config. Can only be SPEAR{600|300|310|320}
#endif
writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
@@ -83,7 +84,7 @@
;
}
-ulong get_timer_masked(void)
+static ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
@@ -99,11 +100,6 @@
return timestamp;
}
-void udelay_masked(unsigned long usec)
-{
- return udelay(usec);
-}
-
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index c7ee199..569704c 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -1,4 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
@@ -7,63 +10,45 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
+ .text :
{
+ __start = .;
*(.vectors)
- arch/arm/cpu/arm926ejs/spear/start.o (.text*)
+ CPUDIR/spear/start.o (.text*)
*(.text*)
- }
+ } > .sram
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
- .data : {
- *(.data*)
- }
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .sram
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
- .bss : {
+ .bss :
+ {
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
- }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
+ } > .sram
}
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 8eb2494..1045673 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
@@ -11,14 +12,11 @@
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
-#include <version.h>
/*
*************************************************************************
@@ -96,17 +94,19 @@
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+ orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
#ifndef CONFIG_SYS_ICACHE_OFF
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
- mov ip, lr /* perserve link reg across call */
+ mov r4, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
- mov lr, ip /* restore link */
+ mov lr, r4 /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig
deleted file mode 100644
index d2e76f4..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if ARCH_VERSATILE
-
-config SYS_BOARD
- default "versatile"
-
-config SYS_VENDOR
- default "armltd"
-
-config SYS_SOC
- default "versatile"
-
-config SYS_CONFIG_NAME
- default "versatile"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/cpu/arm926ejs/versatile/Makefile
deleted file mode 100644
index 907f516..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o
-obj-y += reset.o
diff --git a/arch/arm/cpu/arm926ejs/versatile/reset.S b/arch/arm/cpu/arm926ejs/versatile/reset.S
deleted file mode 100644
index 1c557b0..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/reset.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * armboot - Startup Code for ARM926EJS CPU-core
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-_loop_forever:
- b _loop_forever
-
-rstctl1:
- .word 0xfffece10
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
deleted file mode 100644
index 5d694d8..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#define TIMER_ENABLE (1 << 7)
-#define TIMER_MODE_MSK (1 << 6)
-#define TIMER_MODE_FR (0 << 6)
-#define TIMER_MODE_PD (1 << 6)
-
-#define TIMER_INT_EN (1 << 5)
-#define TIMER_PRS_MSK (3 << 2)
-#define TIMER_PRS_8S (1 << 3)
-#define TIMER_SIZE_MSK (1 << 2)
-#define TIMER_ONE_SHT (1 << 0)
-
-int timer_init (void)
-{
- ulong tmr_ctrl_val;
-
- /* 1st disable the Timer */
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
- tmr_ctrl_val &= ~TIMER_ENABLE;
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
- /*
- * The Timer Control Register has one Undefined/Shouldn't Use Bit
- * So we should do read/modify/write Operation
- */
-
- /*
- * Timer Mode : Free Running
- * Interrupt : Disabled
- * Prescale : 8 Stage, Clk/256
- * Tmr Siz : 16 Bit Counter
- * Tmr in Wrapping Mode
- */
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
- tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
- tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
-
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
- return 0;
-}
-
diff --git a/arch/arm/cpu/arm946es/Makefile b/arch/arm/cpu/arm946es/Makefile
index a44bddc..24cebe3 100644
--- a/arch/arm/cpu/arm946es/Makefile
+++ b/arch/arm/cpu/arm946es/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-y = start.o
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
deleted file mode 100644
index 438668d..0000000
--- a/arch/arm/cpu/arm946es/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c
index e20e5a8..3b4f5de 100644
--- a/arch/arm/cpu/arm946es/cpu.c
+++ b/arch/arm/cpu/arm946es/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -5,8 +6,6 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
@@ -53,7 +52,7 @@
asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
}
-#ifndef CONFIG_INTEGRATOR
+#ifndef CONFIG_ARCH_INTEGRATOR
__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
{
@@ -63,4 +62,4 @@
;
}
-#endif /* #ifdef CONFIG_INTEGRATOR */
+#endif /* #ifdef CONFIG_ARCH_INTEGRATOR */
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 4112371..0ec340b 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
@@ -11,13 +12,10 @@
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
/*
*************************************************************************
@@ -87,15 +85,17 @@
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+ orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
bl lowlevel_init /* go setup memory */
mov lr, ip /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 61e7c82..73d57a2 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -1,4 +1,4 @@
-if CPU_V7
+if CPU_V7A
config CPU_V7_HAS_NONSEC
bool
@@ -6,29 +6,56 @@
config CPU_V7_HAS_VIRT
bool
+config ARCH_SUPPORT_PSCI
+ bool
+
config ARMV7_NONSEC
- boolean "Enable support for booting in non-secure mode" if EXPERT
+ bool "Enable support for booting in non-secure mode" if EXPERT
depends on CPU_V7_HAS_NONSEC
default y
---help---
Say Y here to enable support for booting in non-secure / SVC mode.
config ARMV7_BOOT_SEC_DEFAULT
- boolean "Boot in secure mode by default" if EXPERT
+ bool "Boot in secure mode by default" if EXPERT
depends on ARMV7_NONSEC
- default n
+ default y if TEGRA
---help---
Say Y here to boot in secure mode by default even if non-secure mode
is supported. This option is useful to boot kernels which do not
suppport booting in non-secure mode. Only set this if you need it.
- This can be overriden at run-time by setting the bootm_boot_mode env.
+ This can be overridden at run-time by setting the bootm_boot_mode env.
variable to "sec" or "nonsec".
config ARMV7_VIRT
- boolean "Enable support for hardware virtualization" if EXPERT
+ bool "Enable support for hardware virtualization" if EXPERT
depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
default y
---help---
Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
+config ARMV7_PSCI
+ bool "Enable PSCI support" if EXPERT
+ depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
+ default y
+ help
+ Say Y here to enable PSCI support.
+
+config ARMV7_PSCI_NR_CPUS
+ int "Maximum supported CPUs for PSCI"
+ depends on ARMV7_NONSEC
+ default 4
+ help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of
+ CPUs in the actual hardware implementation.
+
+config ARMV7_LPAE
+ bool "Use LPAE page table format" if EXPERT
+ depends on CPU_V7A
+ default y if ARMV7_VIRT
+ ---help---
+ Say Y here to use the long descriptor page table format. This is
+ required if U-Boot runs in HYP mode.
+
endif
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5..4f4647c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -1,65 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
extra-y := start.o
-obj-y += cache_v7.o
+obj-y += cache_v7.o cache_v7_asm.o
-obj-y += cpu.o
+obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
+obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_EFI_LOADER) += sctlr.o
+endif
+
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
-endif
-ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
-obj-y += nonsec_virt.o
-obj-y += virt-v7.o
-obj-y += virt-dt.o
-endif
-
-ifneq ($(CONFIG_ARMV7_PSCI),)
-obj-y += psci.o
-endif
+obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
+obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o
obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
-obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
-obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
endif
-obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
-obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
-obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
-obj-$(CONFIG_ARCH_EXYNOS) += exynos/
-obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
-obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
-obj-$(if $(filter mx5,$(SOC)),y) += mx5/
-obj-$(CONFIG_MX6) += mx6/
-obj-$(CONFIG_OMAP34XX) += omap3/
-obj-$(CONFIG_OMAP44XX) += omap4/
-obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_RMOBILE) += rmobile/
-obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
-obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_TEGRA20) += tegra20/
-obj-$(CONFIG_U8500) += u8500/
-obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
-obj-$(CONFIG_ZYNQ) += zynq/
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
deleted file mode 100644
index aae3f09..0000000
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_AM33XX) += clock_am33xx.o
-obj-$(CONFIG_TI814X) += clock_ti814x.o
-obj-$(CONFIG_AM43XX) += clock_am43xx.o
-
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
-obj-y += clock.o
-endif
-
-obj-$(CONFIG_TI816X) += clock_ti816x.o
-obj-y += sys_info.o
-obj-y += ddr.o
-obj-y += emif4.o
-obj-y += board.o
-obj-y += mux.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
deleted file mode 100644
index eaf09d1..0000000
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * board.c
- *
- * Common board functions for AM33XX based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <ns16550.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <asm/errno.h>
-#include <linux/compiler.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <linux/usb/musb.h>
-#include <asm/omap_musb.h>
-#include <asm/davinci_rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_DM_GPIO
-static const struct omap_gpio_platdata am33xx_gpio[] = {
- { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
- { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
-#ifdef CONFIG_AM43XX
- { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
-#endif
-};
-
-U_BOOT_DEVICES(am33xx_gpios) = {
- { "gpio_omap", &am33xx_gpio[0] },
- { "gpio_omap", &am33xx_gpio[1] },
- { "gpio_omap", &am33xx_gpio[2] },
- { "gpio_omap", &am33xx_gpio[3] },
-#ifdef CONFIG_AM43XX
- { "gpio_omap", &am33xx_gpio[4] },
- { "gpio_omap", &am33xx_gpio[5] },
-#endif
-};
-
-# ifndef CONFIG_OF_CONTROL
-/*
- * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
- * the CONFIGs. At the same time, we should move this to the board files.
- */
-static const struct ns16550_platdata am33xx_serial[] = {
- { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
-# ifdef CONFIG_SYS_NS16550_COM2
- { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
-# ifdef CONFIG_SYS_NS16550_COM3
- { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
- { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
- { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
- { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
-# endif
-# endif
-};
-
-U_BOOT_DEVICES(am33xx_uarts) = {
- { "serial_omap", &am33xx_serial[0] },
-# ifdef CONFIG_SYS_NS16550_COM2
- { "serial_omap", &am33xx_serial[1] },
-# ifdef CONFIG_SYS_NS16550_COM3
- { "serial_omap", &am33xx_serial[2] },
- { "serial_omap", &am33xx_serial[3] },
- { "serial_omap", &am33xx_serial[4] },
- { "serial_omap", &am33xx_serial[5] },
-# endif
-# endif
-};
-# endif
-
-#else
-
-static const struct gpio_bank gpio_bank_am33xx[] = {
- { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
-#ifdef CONFIG_AM43XX
- { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
-#endif
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-
-#endif
-
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int cpu_mmc_init(bd_t *bis)
-{
- int ret;
-
- ret = omap_mmc_init(0, 0, 0, -1, -1);
- if (ret)
- return ret;
-
- return omap_mmc_init(1, 0, 0, -1, -1);
-}
-#endif
-
-/* AM33XX has two MUSB controllers which can be host or gadget */
-#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
- (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* USB 2.0 PHY Control */
-#define CM_PHY_PWRDN (1 << 0)
-#define CM_PHY_OTG_PWRDN (1 << 1)
-#define OTGVDET_EN (1 << 19)
-#define OTGSESSENDEN (1 << 20)
-
-static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
-{
- if (on) {
- clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
- OTGVDET_EN | OTGSESSENDEN);
- } else {
- clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
- }
-}
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-#ifdef CONFIG_AM335X_USB0
-static void am33xx_otg0_set_phy_power(u8 on)
-{
- am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
-}
-
-struct omap_musb_board_data otg0_board_data = {
- .set_phy_power = am33xx_otg0_set_phy_power,
-};
-
-static struct musb_hdrc_platform_data otg0_plat = {
- .mode = CONFIG_AM335X_USB0_MODE,
- .config = &musb_config,
- .power = 50,
- .platform_ops = &musb_dsps_ops,
- .board_data = &otg0_board_data,
-};
-#endif
-
-#ifdef CONFIG_AM335X_USB1
-static void am33xx_otg1_set_phy_power(u8 on)
-{
- am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
-}
-
-struct omap_musb_board_data otg1_board_data = {
- .set_phy_power = am33xx_otg1_set_phy_power,
-};
-
-static struct musb_hdrc_platform_data otg1_plat = {
- .mode = CONFIG_AM335X_USB1_MODE,
- .config = &musb_config,
- .power = 50,
- .platform_ops = &musb_dsps_ops,
- .board_data = &otg1_board_data,
-};
-#endif
-#endif
-
-int arch_misc_init(void)
-{
-#ifdef CONFIG_AM335X_USB0
- musb_register(&otg0_plat, &otg0_board_data,
- (void *)USB0_OTG_BASE);
-#endif
-#ifdef CONFIG_AM335X_USB1
- musb_register(&otg1_plat, &otg1_board_data,
- (void *)USB1_OTG_BASE);
-#endif
- return 0;
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/*
- * In the case of non-SPL based booting we'll want to call these
- * functions a tiny bit later as it will require gd to be set and cleared
- * and that's not true in s_init in this case so we cannot do it there.
- */
-int board_early_init_f(void)
-{
- prcm_init();
- set_mux_conf_regs();
-
- return 0;
-}
-
-/*
- * This function is the place to do per-board things such as ramp up the
- * MPU clock frequency.
- */
-__weak void am33xx_spl_board_init(void)
-{
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
-static void rtc32k_enable(void)
-{
- struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(RTC_KICK0R_WE, &rtc->kick0r);
- writel(RTC_KICK1R_WE, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-#endif
-
-static void uart_soft_reset(void)
-{
- struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
- u32 regval;
-
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_RESET;
- writel(regval, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_SMART_IDLE_EN;
- writel(regval, &uart_base->uartsyscfg);
-}
-
-static void watchdog_disable(void)
-{
- struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-}
-
-void s_init(void)
-{
- /*
- * The ROM will only have set up sufficient pinmux to allow for the
- * first 4KiB NOR to be read, we must finish doing what we know of
- * the NOR mux in this space in order to continue.
- */
-#ifdef CONFIG_NOR_BOOT
- enable_norboot_pin_mux();
-#endif
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
- watchdog_disable();
- set_uart_mux_conf();
- setup_clocks_for_console();
- uart_soft_reset();
-#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- gd->have_console = 1;
-#elif defined(CONFIG_SPL_BUILD)
- gd = &gdata;
- preloader_console_init();
-#endif
-#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
- /* Enable RTC32K clock */
- rtc32k_enable();
-#endif
-#ifdef CONFIG_SPL_BUILD
- board_early_init_f();
- sdram_init();
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
deleted file mode 100644
index ec7d468..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * clock.c
- *
- * Clock initialization for AM33XX boards.
- * Derived from OMAP4 boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-
-static void setup_post_dividers(const struct dpll_regs *dpll_regs,
- const struct dpll_params *params)
-{
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, dpll_regs->cm_div_m3_dpll);
- if (params->m4 >= 0)
- writel(params->m4, dpll_regs->cm_div_m4_dpll);
- if (params->m5 >= 0)
- writel(params->m5, dpll_regs->cm_div_m5_dpll);
- if (params->m6 >= 0)
- writel(params->m6, dpll_regs->cm_div_m6_dpll);
-}
-
-static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
-{
- clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
-{
- if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
- (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for 0x%x\n",
- dpll_regs->cm_clkmode_dpll);
- hang();
- }
-}
-
-static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
-{
- clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
-{
- if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
- (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("Bypassing DPLL failed 0x%x\n",
- dpll_regs->cm_clkmode_dpll);
- }
-}
-
-static void bypass_dpll(const struct dpll_regs *dpll_regs)
-{
- do_bypass_dpll(dpll_regs);
- wait_for_bypass(dpll_regs);
-}
-
-void do_setup_dpll(const struct dpll_regs *dpll_regs,
- const struct dpll_params *params)
-{
- u32 temp;
-
- if (!params)
- return;
-
- temp = readl(dpll_regs->cm_clksel_dpll);
-
- bypass_dpll(dpll_regs);
-
- /* Set M & N */
- temp &= ~CM_CLKSEL_DPLL_M_MASK;
- temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
-
- temp &= ~CM_CLKSEL_DPLL_N_MASK;
- temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
-
- writel(temp, dpll_regs->cm_clksel_dpll);
-
- setup_post_dividers(dpll_regs, params);
-
- /* Wait till the DPLL locks */
- do_lock_dpll(dpll_regs);
- wait_for_lock(dpll_regs);
-}
-
-static void setup_dplls(void)
-{
- const struct dpll_params *params;
-
- params = get_dpll_core_params();
- do_setup_dpll(&dpll_core_regs, params);
-
- params = get_dpll_mpu_params();
- do_setup_dpll(&dpll_mpu_regs, params);
-
- params = get_dpll_per_params();
- do_setup_dpll(&dpll_per_regs, params);
- writel(0x300, &cmwkup->clkdcoldodpllper);
-
- params = get_dpll_ddr_params();
- do_setup_dpll(&dpll_ddr_regs, params);
-}
-
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
- u32 bound = LDELAY;
-
- while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
- (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock enable failed for 0x%p idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
- u32 wait_for_enable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %p\n", clkctrl_addr);
- if (wait_for_enable)
- wait_for_clk_enable(clkctrl_addr);
-}
-
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %p\n", clkctrl_reg);
-}
-
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
-{
- u32 i, max = 100;
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
- enable_clock_domain(clk_domains[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
- enable_clock_module(clk_modules_explicit_en[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-}
-
-/*
- * Before scaling up the clocks we need to have the PMIC scale up the
- * voltages first. This will be dependent on which PMIC is in use
- * and in some cases we may not be scaling things up at all and thus not
- * need to do anything here.
- */
-__weak void scale_vcores(void)
-{
-}
-
-void prcm_init()
-{
- enable_basic_clocks();
- scale_vcores();
- setup_dplls();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
deleted file mode 100644
index 92142c8..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * clock_am33xx.c
- *
- * clocks for AM33XX based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define OSC (V_OSCK/1000000)
-
-struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
-struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
-struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
-struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
-
-const struct dpll_regs dpll_mpu_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x88,
- .cm_idlest_dpll = CM_WKUP + 0x20,
- .cm_clksel_dpll = CM_WKUP + 0x2C,
- .cm_div_m2_dpll = CM_WKUP + 0xA8,
-};
-
-const struct dpll_regs dpll_core_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x90,
- .cm_idlest_dpll = CM_WKUP + 0x5C,
- .cm_clksel_dpll = CM_WKUP + 0x68,
- .cm_div_m4_dpll = CM_WKUP + 0x80,
- .cm_div_m5_dpll = CM_WKUP + 0x84,
- .cm_div_m6_dpll = CM_WKUP + 0xD8,
-};
-
-const struct dpll_regs dpll_per_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x8C,
- .cm_idlest_dpll = CM_WKUP + 0x70,
- .cm_clksel_dpll = CM_WKUP + 0x9C,
- .cm_div_m2_dpll = CM_WKUP + 0xAC,
-};
-
-const struct dpll_regs dpll_ddr_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x94,
- .cm_idlest_dpll = CM_WKUP + 0x34,
- .cm_clksel_dpll = CM_WKUP + 0x40,
- .cm_div_m2_dpll = CM_WKUP + 0xA0,
-};
-
-struct dpll_params dpll_mpu_opp100 = {
- CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core_opp100 = {
- 1000, OSC-1, -1, -1, 10, 8, 4};
-const struct dpll_params dpll_mpu = {
- MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
- 50, OSC-1, -1, -1, 1, 1, 1};
-const struct dpll_params dpll_per = {
- 960, OSC-1, 5, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_mpu_params(void)
-{
- return &dpll_mpu;
-}
-
-const struct dpll_params *get_dpll_core_params(void)
-{
- return &dpll_core;
-}
-
-const struct dpll_params *get_dpll_per_params(void)
-{
- return &dpll_per;
-}
-
-void setup_clocks_for_console(void)
-{
- clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
- clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
- clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&cmper->uart1clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&cmper->uart2clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&cmper->uart3clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&cmper->uart4clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&cmper->uart5clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
-void enable_basic_clocks(void)
-{
- u32 *const clk_domains[] = {
- &cmper->l3clkstctrl,
- &cmper->l4fwclkstctrl,
- &cmper->l3sclkstctrl,
- &cmper->l4lsclkstctrl,
- &cmwkup->wkclkstctrl,
- &cmper->emiffwclkctrl,
- &cmrtc->clkstctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en[] = {
- &cmper->l3clkctrl,
- &cmper->l4lsclkctrl,
- &cmper->l4fwclkctrl,
- &cmwkup->wkl4wkclkctrl,
- &cmper->l3instrclkctrl,
- &cmper->l4hsclkctrl,
- &cmwkup->wkgpio0clkctrl,
- &cmwkup->wkctrlclkctrl,
- &cmper->timer2clkctrl,
- &cmper->gpmcclkctrl,
- &cmper->elmclkctrl,
- &cmper->mmc0clkctrl,
- &cmper->mmc1clkctrl,
- &cmwkup->wkup_i2c0ctrl,
- &cmper->gpio1clkctrl,
- &cmper->gpio2clkctrl,
- &cmper->gpio3clkctrl,
- &cmper->i2c1clkctrl,
- &cmper->cpgmac0clkctrl,
- &cmper->spi0clkctrl,
- &cmrtc->rtcclkctrl,
- &cmper->usb0clkctrl,
- &cmper->emiffwclkctrl,
- &cmper->emifclkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-
- /* Select the Master osc 24 MHZ as Timer2 clock source */
- writel(0x1, &cmdpll->clktimer2clk);
-}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
deleted file mode 100644
index 31188c8..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * clock_am43xx.c
- *
- * clocks for AM43XX based boards
- * Derived from AM33XX based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-
-struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
-struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
-struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
-
-const struct dpll_regs dpll_mpu_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x560,
- .cm_idlest_dpll = CM_WKUP + 0x564,
- .cm_clksel_dpll = CM_WKUP + 0x56c,
- .cm_div_m2_dpll = CM_WKUP + 0x570,
-};
-
-const struct dpll_regs dpll_core_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x520,
- .cm_idlest_dpll = CM_WKUP + 0x524,
- .cm_clksel_dpll = CM_WKUP + 0x52C,
- .cm_div_m4_dpll = CM_WKUP + 0x538,
- .cm_div_m5_dpll = CM_WKUP + 0x53C,
- .cm_div_m6_dpll = CM_WKUP + 0x540,
-};
-
-const struct dpll_regs dpll_per_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x5E0,
- .cm_idlest_dpll = CM_WKUP + 0x5E4,
- .cm_clksel_dpll = CM_WKUP + 0x5EC,
- .cm_div_m2_dpll = CM_WKUP + 0x5F0,
-};
-
-const struct dpll_regs dpll_ddr_regs = {
- .cm_clkmode_dpll = CM_WKUP + 0x5A0,
- .cm_idlest_dpll = CM_WKUP + 0x5A4,
- .cm_clksel_dpll = CM_WKUP + 0x5AC,
- .cm_div_m2_dpll = CM_WKUP + 0x5B0,
- .cm_div_m4_dpll = CM_WKUP + 0x5B8,
-};
-
-void setup_clocks_for_console(void)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
-
- /* Do not add any spl_debug prints in this function */
- clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
- /* Enable UART0 */
- clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
- (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
- clkctrl = readl(&cmwkup->wkup_uart0ctrl);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- }
-}
-
-void enable_basic_clocks(void)
-{
- u32 *const clk_domains[] = {
- &cmper->l3clkstctrl,
- &cmper->l3sclkstctrl,
- &cmper->l4lsclkstctrl,
- &cmwkup->wkclkstctrl,
- &cmper->emifclkstctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en[] = {
- &cmper->l3clkctrl,
- &cmper->l4lsclkctrl,
- &cmper->l4fwclkctrl,
- &cmwkup->wkl4wkclkctrl,
- &cmper->l3instrclkctrl,
- &cmper->l4hsclkctrl,
- &cmwkup->wkgpio0clkctrl,
- &cmwkup->wkctrlclkctrl,
- &cmper->timer2clkctrl,
- &cmper->gpmcclkctrl,
- &cmper->elmclkctrl,
- &cmper->mmc0clkctrl,
- &cmper->mmc1clkctrl,
- &cmwkup->wkup_i2c0ctrl,
- &cmper->gpio1clkctrl,
- &cmper->gpio2clkctrl,
- &cmper->gpio3clkctrl,
- &cmper->gpio4clkctrl,
- &cmper->gpio5clkctrl,
- &cmper->i2c1clkctrl,
- &cmper->cpgmac0clkctrl,
- &cmper->emiffwclkctrl,
- &cmper->emifclkctrl,
- &cmper->otfaemifclkctrl,
- &cmper->qspiclkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-
- /* Select the Master osc clk as Timer2 clock source */
- writel(0x1, &cmdpll->clktimer2clk);
-}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
deleted file mode 100644
index 9b5a47b..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * clock_ti814x.c
- *
- * Clocks for TI814X based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* PRCM */
-#define PRCM_MOD_EN 0x2
-
-/* CLK_SRC */
-#define OSC_SRC0 0
-#define OSC_SRC1 1
-
-#define L3_OSC_SRC OSC_SRC0
-
-#define OSC_0_FREQ 20
-
-#define DCO_HS2_MIN 500
-#define DCO_HS2_MAX 1000
-#define DCO_HS1_MIN 1000
-#define DCO_HS1_MAX 2000
-
-#define SELFREQDCO_HS2 0x00000801
-#define SELFREQDCO_HS1 0x00001001
-
-#define MPU_N 0x1
-#define MPU_M 0x3C
-#define MPU_M2 1
-#define MPU_CLKCTRL 0x1
-
-#define L3_N 19
-#define L3_M 880
-#define L3_M2 4
-#define L3_CLKCTRL 0x801
-
-#define DDR_N 19
-#define DDR_M 666
-#define DDR_M2 2
-#define DDR_CLKCTRL 0x801
-
-/* ADPLLJ register values */
-#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
-#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
-#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
-#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
-#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
-#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
-#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
-#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
-#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
-#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
- ADPLLJ_CLKCTRL_CLKOUTEN | \
- ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
- ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
-
-#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
-#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
-#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
- ADPLLJ_STATUS_FREQLOCK)
-#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
-#define ADPLLJ_STATUS_BYPASS (1 << 0)
-#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
- ADPLLJ_STATUS_BYPASS)
-
-#define ADPLLJ_TENABLE_ENB (1 << 0)
-#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
-
-#define ADPLLJ_M2NDIV_M2SHIFT 16
-
-#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
-#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
-#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
-
-struct ad_pll {
- unsigned int pwrctrl;
- unsigned int clkctrl;
- unsigned int tenable;
- unsigned int tenablediv;
- unsigned int m2ndiv;
- unsigned int mn2div;
- unsigned int fracdiv;
- unsigned int bwctrl;
- unsigned int fracctrl;
- unsigned int status;
- unsigned int m3div;
- unsigned int rampctrl;
-};
-
-#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
-
-#define ENET_CLKCTRL_CMPL 0x30000
-
-#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
-
-struct sata_pll {
- unsigned int pllcfg0;
- unsigned int pllcfg1;
- unsigned int pllcfg2;
- unsigned int pllcfg3;
- unsigned int pllcfg4;
- unsigned int pllstatus;
- unsigned int rxstatus;
- unsigned int txstatus;
- unsigned int testcfg;
-};
-
-#define SEL_IN_FREQ (0x1 << 31)
-#define DIGCLRZ (0x1 << 30)
-#define ENDIGLDO (0x1 << 4)
-#define APLL_CP_CURR (0x1 << 3)
-#define ENBGSC_REF (0x1 << 2)
-#define ENPLLLDO (0x1 << 1)
-#define ENPLL (0x1 << 0)
-
-#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
-#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
-#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
-#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
- ENPLLLDO | ENPLL)
-
-#define PLL_LOCK (0x1 << 0)
-
-#define ENSATAMODE (0x1 << 31)
-#define PLLREFSEL (0x1 << 30)
-#define MDIVINT (0x4b << 18)
-#define EN_CLKAUX (0x1 << 5)
-#define EN_CLK125M (0x1 << 4)
-#define EN_CLK100M (0x1 << 3)
-#define EN_CLK50M (0x1 << 2)
-
-#define SATA_PLLCFG1 (ENSATAMODE | \
- PLLREFSEL | \
- MDIVINT | \
- EN_CLKAUX | \
- EN_CLK125M | \
- EN_CLK100M | \
- EN_CLK50M)
-
-#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
-#define PLLDO_EN_LDO_STABLE (0x1 << 11)
-#define PLLDO_EN_BUF_CUR (0x1 << 7)
-#define PLLDO_EN_LP (0x1 << 6)
-#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
-
-#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
- PLLDO_EN_LDO_STABLE | \
- PLLDO_EN_BUF_CUR | \
- PLLDO_EN_LP | \
- PLLDO_CTRL_TRIM_1_4V)
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
-
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
-{
- /* HSMMC1 */
- writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
- while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Ethernet */
- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
- ;
- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
- while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
- ;
-
- /* RTC clocks */
- writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
- while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
- ;
-}
-
-/*
- * select the HS1 or HS2 for DCO Freq
- * return : CLKCTRL
- */
-static u32 pll_dco_freq_sel(u32 clkout_dco)
-{
- if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
- return SELFREQDCO_HS2;
- else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
- return SELFREQDCO_HS1;
- else
- return -1;
-}
-
-/*
- * select the sigma delta config
- * return: sigma delta val
- */
-static u32 pll_sigma_delta_val(u32 clkout_dco)
-{
- u32 sig_val = 0;
-
- sig_val = (clkout_dco + 225) / 250;
- sig_val = sig_val << 24;
-
- return sig_val;
-}
-
-/*
- * configure individual ADPLLJ
- */
-static void pll_config(u32 base, u32 n, u32 m, u32 m2,
- u32 clkctrl_val, int adpllj)
-{
- const struct ad_pll *adpll = (struct ad_pll *)base;
- u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
- u32 sig_val = 0, hs_mod = 0;
-
- m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
- mn2val = m;
-
- /* calculate clkout_dco */
- clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
-
- /* sigma delta & Hs mode selection skip for ADPLLS*/
- if (adpllj) {
- sig_val = pll_sigma_delta_val(clkout_dco);
- hs_mod = pll_dco_freq_sel(clkout_dco);
- }
-
- /* by-pass pll */
- read_clkctrl = readl(&adpll->clkctrl);
- writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
- while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
- != ADPLLJ_STATUS_BYPASSANDACK)
- ;
-
- /* clear TINITZ */
- read_clkctrl = readl(&adpll->clkctrl);
- writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
- /*
- * ref_clk = 20/(n + 1);
- * clkout_dco = ref_clk * m;
- * clk_out = clkout_dco/m2;
- */
- read_clkctrl = readl(&adpll->clkctrl) &
- ~(ADPLLJ_CLKCTRL_LPMODE |
- ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
- ADPLLJ_CLKCTRL_REGM4XEN);
- writel(m2nval, &adpll->m2ndiv);
- writel(mn2val, &adpll->mn2div);
-
- /* Skip for modena(ADPLLS) */
- if (adpllj) {
- writel(sig_val, &adpll->fracdiv);
- writel((read_clkctrl | hs_mod), &adpll->clkctrl);
- }
-
- /* Load M2, N2 dividers of ADPLL */
- writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
- writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
-
- /* Load M, N dividers of ADPLL */
- writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
- writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
-
- /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
- read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
- if (adpllj)
- writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
- &adpll->clkctrl);
-
- /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
- read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
- writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
- /* Wait for phase and freq lock */
- while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
- ADPLLJ_STATUS_PHSFRQLOCK)
- ;
-}
-
-static void unlock_pll_control_mmr(void)
-{
- /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
- writel(0x1EDA4C3D, 0x481C5040);
- writel(0x2FF1AC2B, 0x48140060);
- writel(0xF757FDC0, 0x48140064);
- writel(0xE2BC3A6D, 0x48140068);
- writel(0x1EBF131D, 0x4814006c);
- writel(0x6F361E05, 0x48140070);
-}
-
-static void mpu_pll_config(void)
-{
- pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
-}
-
-static void l3_pll_config(void)
-{
- u32 l3_osc_src, rd_osc_src = 0;
-
- l3_osc_src = L3_OSC_SRC;
- rd_osc_src = readl(OSC_SRC_CTRL);
-
- if (OSC_SRC0 == l3_osc_src)
- writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
- else
- writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
-
- pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
- pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
-}
-
-void sata_pll_config(void)
-{
- /*
- * This sequence for configuring the SATA PLL
- * resident in the control module is documented
- * in TI8148 TRM section 21.3.1
- */
- writel(SATA_PLLCFG1, &spll->pllcfg1);
- udelay(50);
-
- writel(SATA_PLLCFG3, &spll->pllcfg3);
- udelay(50);
-
- writel(SATA_PLLCFG0_1, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_2, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_3, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_4, &spll->pllcfg0);
- udelay(50);
-
- while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
- ;
-}
-
-void enable_dmm_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
- writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
- writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
- while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
- while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
- ;
- while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
- ;
- writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
- while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
- ;
-}
-
-void setup_clocks_for_console(void)
-{
- unlock_pll_control_mmr();
- /* UART0 */
- writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
- while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
- ;
-}
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void prcm_init(void)
-{
- /* Enable the control module */
- writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
- /* Configure PLLs */
- mpu_pll_config();
- l3_pll_config();
- sata_pll_config();
-
- /* Enable the required peripherals */
- enable_per_clocks();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
deleted file mode 100644
index ace4a5a..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * clock_ti816x.c
- *
- * Clocks for TI816X based boards
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * Based on TI-PSP-04.00.02.14 :
- *
- * Copyright (C) 2009, Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#include <asm/emif.h>
-
-#define CM_PLL_BASE (CTRL_BASE + 0x0400)
-
-/* Main PLL */
-#define MAIN_N 64
-#define MAIN_P 0x1
-#define MAIN_INTFREQ1 0x8
-#define MAIN_FRACFREQ1 0x800000
-#define MAIN_MDIV1 0x2
-#define MAIN_INTFREQ2 0xE
-#define MAIN_FRACFREQ2 0x0
-#define MAIN_MDIV2 0x1
-#define MAIN_INTFREQ3 0x8
-#define MAIN_FRACFREQ3 0xAAAAB0
-#define MAIN_MDIV3 0x3
-#define MAIN_INTFREQ4 0x9
-#define MAIN_FRACFREQ4 0x55554F
-#define MAIN_MDIV4 0x3
-#define MAIN_INTFREQ5 0x9
-#define MAIN_FRACFREQ5 0x374BC6
-#define MAIN_MDIV5 0xC
-#define MAIN_MDIV6 0x48
-#define MAIN_MDIV7 0x4
-
-/* DDR PLL */
-#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x4
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x3
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
-#define DDR_N 50
-#define DDR_P 0x1
-#define DDR_MDIV1 0x2
-#define DDR_INTFREQ2 0x9
-#define DDR_FRACFREQ2 0x0
-#define DDR_MDIV2 0x19
-#define DDR_INTFREQ3 0x13
-#define DDR_FRACFREQ3 0x800000
-#define DDR_MDIV3 0x2
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x2
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#endif
-
-#define CONTROL_STATUS (CTRL_BASE + 0x40)
-#define DDR_RCD (CTRL_BASE + 0x070C)
-#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
-#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
-#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
-
-#define INTCPS_SYSCONFIG 0x48200010
-#define CM_SYSCLK10_CLKSEL 0x48180324
-
-struct cm_pll {
- unsigned int mainpll_ctrl; /* offset 0x400 */
- unsigned int mainpll_pwd;
- unsigned int mainpll_freq1;
- unsigned int mainpll_div1;
- unsigned int mainpll_freq2;
- unsigned int mainpll_div2;
- unsigned int mainpll_freq3;
- unsigned int mainpll_div3;
- unsigned int mainpll_freq4;
- unsigned int mainpll_div4;
- unsigned int mainpll_freq5;
- unsigned int mainpll_div5;
- unsigned int resv0[1];
- unsigned int mainpll_div6;
- unsigned int resv1[1];
- unsigned int mainpll_div7;
- unsigned int ddrpll_ctrl; /* offset 0x440 */
- unsigned int ddrpll_pwd;
- unsigned int resv2[1];
- unsigned int ddrpll_div1;
- unsigned int ddrpll_freq2;
- unsigned int ddrpll_div2;
- unsigned int ddrpll_freq3;
- unsigned int ddrpll_div3;
- unsigned int ddrpll_freq4;
- unsigned int ddrpll_div4;
- unsigned int ddrpll_freq5;
- unsigned int ddrpll_div5;
- unsigned int videopll_ctrl; /* offset 0x470 */
- unsigned int videopll_pwd;
- unsigned int videopll_freq1;
- unsigned int videopll_div1;
- unsigned int videopll_freq2;
- unsigned int videopll_div2;
- unsigned int videopll_freq3;
- unsigned int videopll_div3;
- unsigned int resv3[4];
- unsigned int audiopll_ctrl; /* offset 0x4A0 */
- unsigned int audiopll_pwd;
- unsigned int resv4[2];
- unsigned int audiopll_freq2;
- unsigned int audiopll_div2;
- unsigned int audiopll_freq3;
- unsigned int audiopll_div3;
- unsigned int audiopll_freq4;
- unsigned int audiopll_div4;
- unsigned int audiopll_freq5;
- unsigned int audiopll_div5;
-};
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
-const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
-void enable_dmm_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
- writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
- writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
-
- /* Wait for clocks to be active */
- while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
- ;
- /* Wait for emif0 to be fully functional, including OCP */
- while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
- ;
- /* Wait for emif1 to be fully functional, including OCP */
- while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
- ;
-
- writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
- /* Wait for dmm to be fully functional, including OCP */
- while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
- ;
-
- /* Enable Tiled Access */
- writel(0x80000000, DMM_PAT_BASE_ADDR);
-}
-
-/* assume delay is aprox at least 1us */
-static void ddr_delay(int d)
-{
- int i;
-
- /*
- * read a control register.
- * this is a bit more delay and cannot be optimized by the compiler
- * assuming one read takes 200 cycles and A8 is runing 1 GHz
- * somewhat conservative setting
- */
- for (i = 0; i < 50*d; i++)
- readl(CONTROL_STATUS);
-}
-
-static void main_pll_init_ti816x(void)
-{
- u32 main_pll_ctrl = 0;
-
- /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFFB;
- main_pll_ctrl |= BIT(2);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Enable PLL by setting BIT3 in its ctrl reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFF7;
- main_pll_ctrl |= BIT(3);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Write the values of N,P in the CTRL reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFF;
- main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Power up clock1-7 */
- writel(0x0, &cmpll->mainpll_pwd);
-
- /* Program the freq and divider values for clock1-7 */
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
- &cmpll->mainpll_freq1);
- writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
- &cmpll->mainpll_freq2);
- writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
- &cmpll->mainpll_freq3);
- writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
- &cmpll->mainpll_freq4);
- writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
- &cmpll->mainpll_freq5);
- writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
-
- writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
-
- writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
-
- /* Wait for PLL to lock */
- while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
- ;
-
- /* Put the PLL in normal mode, disable bypass */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFFB;
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-}
-
-static void ddr_pll_bypass_ti816x(void)
-{
- u32 ddr_pll_ctrl = 0;
-
- /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFFFFFFFB;
- ddr_pll_ctrl |= BIT(2);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-}
-
-static void ddr_pll_init_ti816x(void)
-{
- u32 ddr_pll_ctrl = 0;
- /* Enable PLL by setting BIT3 in its ctrl reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFFFFFFF7;
- ddr_pll_ctrl |= BIT(3);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
- /* Write the values of N,P in the CTRL reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFF;
- ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
- ddr_delay(10);
-
- /* Power up clock1-5 */
- writel(0x0, &cmpll->ddrpll_pwd);
-
- /* Program the freq and divider values for clock1-3 */
- writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
- ddr_delay(1);
- writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
- writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
- &cmpll->ddrpll_freq2);
- writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
- writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
- ddr_delay(1);
- writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
- ddr_delay(1);
- writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
- &cmpll->ddrpll_freq3);
- ddr_delay(1);
- writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
- &cmpll->ddrpll_freq3);
-
- ddr_delay(5);
-
- /* Wait for PLL to lock */
- while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
- ;
-
- /* Power up RCD */
- writel(BIT(0), DDR_RCD);
-}
-
-static void peripheral_enable(void)
-{
- /* Wake-up the l3_slow clock */
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
-
- /*
- * Note on Timers:
- * There are 8 timers(0-7) out of which timer 0 is a secure timer.
- * Timer 0 mux should not be changed
- *
- * To access the timer registers we need the to be
- * enabled which is what we do in the first step
- */
-
- /* Enable timer1 */
- writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
- /* Select timer1 clock to be CLKIN (27MHz) */
- writel(BIT(1), CM_TIMER1_CLKSEL);
-
- /* Wait for timer1 to be ON-ACTIVE */
- while (((readl(&cmalwon->l3slowclkstctrl)
- & (0x80000<<1))>>20) != 1)
- ;
- /* Wait for timer1 to be enabled */
- while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
- ;
- /* Active posted mode */
- writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
- while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
- ;
- /* Start timer1 */
- writel(BIT(0), (DM_TIMER1_BASE + 0x38));
-
- /* eFuse */
- writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
- while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
- ;
-
- /* Enable gpio0 */
- writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
- while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
- ;
- writel((BIT(8)), &cmalwon->gpio0clkctrl);
-
- /* Enable spi */
- writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
- while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable i2c0 */
- writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
- while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable ethernet0 */
- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
-
- /* Enable hsmmc */
- writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
- while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
- ;
-}
-
-void setup_clocks_for_console(void)
-{
- /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
- writel(0x0, CM_SYSCLK10_CLKSEL);
-
- ddr_pll_bypass_ti816x();
-
- /* Enable uart0-2 */
- writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
- while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
- while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
- while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
- ;
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
- ;
-}
-
-void prcm_init(void)
-{
- /* Enable the control */
- writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
- main_pll_init_ti816x();
- ddr_pll_init_ti816x();
-
- /*
- * With clk freqs setup to desired values,
- * enable the required peripherals
- */
- peripheral_enable();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
deleted file mode 100644
index 5294d16..0000000
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
deleted file mode 100644
index fc66872..0000000
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * DDR Configuration for AM33xx devices.
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-
-/**
- * Base address for EMIF instances
- */
-static struct emif_reg_struct *emif_reg[2] = {
- (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
- (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
-
-/**
- * Base addresses for DDR PHY cmd/data regs
- */
-static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
- (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
- (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
-
-static struct ddr_data_regs *ddr_data_reg[2] = {
- (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
- (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
-
-/**
- * Base address for ddr io control instances
- */
-static struct ddr_cmdtctrl *ioctrl_reg = {
- (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
-
-static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
-{
- u32 mr;
-
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
-
- mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
- debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
- if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
- ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
- ((mr & 0xff000000) >> 24) == (mr & 0xff))
- return mr & 0xff;
- else
- return mr;
-}
-
-static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
-{
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
- writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
-}
-
-static void configure_mr(int nr, u32 cs)
-{
- u32 mr_addr;
-
- while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
- ;
- set_mr(nr, cs, LPDDR2_MR10, 0x56);
-
- set_mr(nr, cs, LPDDR2_MR1, 0x43);
- set_mr(nr, cs, LPDDR2_MR2, 0x2);
-
- mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(nr, cs, mr_addr, 0x2);
-}
-
-/*
- * Configure EMIF4D5 registers and MR registers
- */
-void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
-{
- writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
- writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
- writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
- writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
-
- writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
- writel(regs->emif_rd_wr_lvl_rmp_win,
- &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
- writel(regs->emif_rd_wr_lvl_rmp_ctl,
- &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
- writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
- writel(regs->emif_rd_wr_exec_thresh,
- &emif_reg[nr]->emif_rd_wr_exec_thresh);
-
- /*
- * for most SOCs these registers won't need to be changed so only
- * write to these registers if someone explicitly has set the
- * register's value.
- */
- if(regs->emif_cos_config) {
- writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
- writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
- writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
- writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
- }
-
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
- writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
-
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
- configure_mr(nr, 0);
- configure_mr(nr, 1);
- }
-}
-
-/**
- * Configure SDRAM
- */
-void config_sdram(const struct emif_regs *regs, int nr)
-{
- if (regs->zq_config) {
- /*
- * A value of 0x2800 for the REF CTRL will give us
- * about 570us for a delay, which will be long enough
- * to configure things.
- */
- writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
- writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- }
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-}
-
-/**
- * Set SDRAM timings
- */
-void set_sdram_timings(const struct emif_regs *regs, int nr)
-{
- writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
- writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
- writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
- writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
- writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
- writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
-}
-
-void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
-}
-
-/*
- * Configure EXT PHY registers
- */
-static void ext_phy_settings(const struct emif_regs *regs, int nr)
-{
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- const u32 *ext_phy_ctrl_const_regs;
- u32 i = 0;
- u32 size;
-
- ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base =
- (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
-
- if (!size)
- return;
-
- for (i = 0; i < size; i++) {
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- }
-}
-
-/**
- * Configure DDR PHY
- */
-void config_ddr_phy(const struct emif_regs *regs, int nr)
-{
- /*
- * disable initialization and refreshes for now until we
- * finish programming EMIF regs.
- */
- setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
- EMIF_REG_INITREF_DIS_MASK);
-
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif_reg[nr]->emif_ddr_phy_ctrl_1);
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
-
- if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
- ext_phy_settings(regs, nr);
-}
-
-/**
- * Configure DDR CMD control registers
- */
-void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
-{
- if (!cmd)
- return;
-
- writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
- writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
-
- writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
- writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
-
- writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
- writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
-}
-
-/**
- * Configure DDR DATA registers
- */
-void config_ddr_data(const struct ddr_data *data, int nr)
-{
- int i;
-
- if (!data)
- return;
-
- for (i = 0; i < DDR_DATA_REGS_NR; i++) {
- writel(data->datardsratio0,
- &(ddr_data_reg[nr]+i)->dt0rdsratio0);
- writel(data->datawdsratio0,
- &(ddr_data_reg[nr]+i)->dt0wdsratio0);
- writel(data->datawiratio0,
- &(ddr_data_reg[nr]+i)->dt0wiratio0);
- writel(data->datagiratio0,
- &(ddr_data_reg[nr]+i)->dt0giratio0);
- writel(data->datafwsratio0,
- &(ddr_data_reg[nr]+i)->dt0fwsratio0);
- writel(data->datawrsratio0,
- &(ddr_data_reg[nr]+i)->dt0wrsratio0);
- }
-}
-
-void config_io_ctrl(const struct ctrl_ioregs *ioregs)
-{
- if (!ioregs)
- return;
-
- writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
- writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
- writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
- writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
- writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
-#ifdef CONFIG_AM43XX
- writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
- writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
- writel(ioregs->emif_sdram_config_ext,
- &ioctrl_reg->emif_sdram_config_ext);
-#endif
-}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
deleted file mode 100644
index 8b7527c..0000000
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * emif4.c
- *
- * AM33XX emif4 configuration file
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- sdram_init();
-#endif
-
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#ifdef CONFIG_TI81XX
-static struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)DMM_BASE;
-#endif
-#ifndef CONFIG_TI816X
-static struct vtp_reg *vtpreg[2] = {
- (struct vtp_reg *)VTP0_CTRL_ADDR,
- (struct vtp_reg *)VTP1_CTRL_ADDR};
-#endif
-#ifdef CONFIG_AM33XX
-static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-#endif
-#ifdef CONFIG_AM43XX
-static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-static struct cm_device_inst *cm_device =
- (struct cm_device_inst *)CM_DEVICE_INST;
-#endif
-
-#ifdef CONFIG_TI81XX
-void config_dmm(const struct dmm_lisa_map_regs *regs)
-{
- enable_dmm_clocks();
-
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
-}
-#endif
-
-#ifndef CONFIG_TI816X
-static void config_vtp(int nr)
-{
- writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
- &vtpreg[nr]->vtp0ctrlreg);
- writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
- &vtpreg[nr]->vtp0ctrlreg);
- writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
- &vtpreg[nr]->vtp0ctrlreg);
-
- /* Poll for READY */
- while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
- VTP_CTRL_READY)
- ;
-}
-#endif
-
-void __weak ddr_pll_config(unsigned int ddrpll_m)
-{
-}
-
-void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
- const struct ddr_data *data, const struct cmd_control *ctrl,
- const struct emif_regs *regs, int nr)
-{
- ddr_pll_config(pll);
-#ifndef CONFIG_TI816X
- config_vtp(nr);
-#endif
- config_cmd_ctrl(ctrl, nr);
-
- config_ddr_data(data, nr);
-#ifdef CONFIG_AM33XX
- config_io_ctrl(ioregs);
-
- /* Set CKE to be controlled by EMIF/DDR PHY */
- writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
-#endif
-#ifdef CONFIG_AM43XX
- writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
- while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
- ;
- writel(0x80000000, &ddrctrl->ddrioctrl);
-
- config_io_ctrl(ioregs);
-
- /* Set CKE to be controlled by EMIF/DDR PHY */
- writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
-#endif
-
- /* Program EMIF instance */
- config_ddr_phy(regs, nr);
- set_sdram_timings(regs, nr);
- if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
- config_sdram_emif4d5(regs, nr);
- else
- config_sdram(regs, nr);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c
deleted file mode 100644
index 2ded472..0000000
--- a/arch/arm/cpu/armv7/am33xx/mux.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/*
- * Configure the pin mux for the module
- */
-void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
-{
- int i;
-
- if (!mod_pin_mux)
- return;
-
- for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
- MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
-}
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
deleted file mode 100644
index 781d83f..0000000
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * sys_info.c
- *
- * System information functions
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <power/tps65910.h>
-#include <linux/compiler.h>
-
-struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
-
-/**
- * get_cpu_rev(void) - extract rev info
- */
-u32 get_cpu_rev(void)
-{
- u32 id;
- u32 rev;
-
- id = readl(DEVICE_ID);
- rev = (id >> 28) & 0xff;
-
- return rev;
-}
-
-/**
- * get_cpu_type(void) - extract cpu info
- */
-u32 get_cpu_type(void)
-{
- u32 id = 0;
- u32 partnum;
-
- id = readl(DEVICE_ID);
- partnum = (id >> 12) & 0xffff;
-
- return partnum;
-}
-
-/**
- * get_board_rev() - setup to pass kernel board revision information
- * returns: 0 for the ATAG REVISION tag value.
- */
-u32 __weak get_board_rev(void)
-{
- return 0;
-}
-
-/**
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (DEVICE_MASK);
- return mode >>= 8;
-}
-
-/**
- * get_sysboot_value(void) - return SYS_BOOT[4:0]
- */
-u32 get_sysboot_value(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
- return mode;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-static char *cpu_revs[] = {
- "1.0",
- "2.0",
- "2.1"};
-
-
-static char *dev_types[] = {
- "TST",
- "EMU",
- "HS",
- "GP"};
-
-/**
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- char *cpu_s, *sec_s, *rev_s;
-
- switch (get_cpu_type()) {
- case AM335X:
- cpu_s = "AM335X";
- break;
- case TI81XX:
- cpu_s = "TI81XX";
- break;
- default:
- cpu_s = "Unknown CPU type";
- break;
- }
-
- if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
- rev_s = cpu_revs[get_cpu_rev()];
- else
- rev_s = "?";
-
- if (get_device_type() < ARRAY_SIZE(dev_types))
- sec_s = dev_types[get_device_type()];
- else
- sec_s = "?";
-
- printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_AM33XX
-int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
-{
- int sil_rev;
-
- sil_rev = readl(&cdev->deviceid) >> 28;
-
- if (sil_rev == 1)
- /* PG 2.0, efuse may not be set. */
- return MPUPLL_M_800;
- else if (sil_rev >= 2) {
- /* Check what the efuse says our max speed is. */
- int efuse_arm_mpu_max_freq;
- efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
- switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
- case AM335X_ZCZ_1000:
- return MPUPLL_M_1000;
- case AM335X_ZCZ_800:
- return MPUPLL_M_800;
- case AM335X_ZCZ_720:
- return MPUPLL_M_720;
- case AM335X_ZCZ_600:
- case AM335X_ZCE_600:
- return MPUPLL_M_600;
- case AM335X_ZCZ_300:
- case AM335X_ZCE_300:
- return MPUPLL_M_300;
- }
- }
-
- /* PG 1.0 or otherwise unknown, use the PG1.0 max */
- return MPUPLL_M_720;
-}
-
-int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
-{
- /* For PG2.1 and later, we have one set of values. */
- if (sil_rev >= 2) {
- switch (frequency) {
- case MPUPLL_M_1000:
- return TPS65910_OP_REG_SEL_1_3_2_5;
- case MPUPLL_M_800:
- return TPS65910_OP_REG_SEL_1_2_6;
- case MPUPLL_M_720:
- return TPS65910_OP_REG_SEL_1_2_0;
- case MPUPLL_M_600:
- case MPUPLL_M_300:
- return TPS65910_OP_REG_SEL_1_1_3;
- }
- }
-
- /* Default to PG1.0/PG2.0 values. */
- return TPS65910_OP_REG_SEL_1_1_3;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
deleted file mode 100644
index 07cf267..0000000
--- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- *(.vectors)
- arch/arm/cpu/armv7/start.o (.text)
- *(.text*)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- } >.sram
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 0588e2b..3db31c0 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -1,23 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <div64.h>
+#include <bootstage.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_HZ_CLOCK
+static inline u32 read_cntfrq(void)
+{
+ u32 frq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
+ return frq;
+}
+#endif
+
int timer_init(void)
{
gd->arch.tbl = 0;
gd->arch.tbu = 0;
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
-
+#ifdef CONFIG_SYS_HZ_CLOCK
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#else
+ gd->arch.timer_rate_hz = read_cntfrq();
+#endif
return 0;
}
@@ -34,22 +47,9 @@
}
-ulong get_timer(ulong base)
+ulong timer_get_boot_us(void)
{
- return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long endtime;
-
- endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
- 1000UL);
-
- endtime += get_ticks();
-
- while (get_ticks() < endtime)
- ;
+ return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
}
ulong get_tbclk(void)
diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile
deleted file mode 100644
index 885dcee..0000000
--- a/arch/arm/cpu/armv7/armada-xp/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o
diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/cpu/armv7/armada-xp/cpu.c
deleted file mode 100644
index 1cf70a9..0000000
--- a/arch/arm/cpu/armv7/armada-xp/cpu.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
-
-static struct mbus_win windows[] = {
- /* PCIE MEM address space */
- { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
-
- /* PCIE IO address space */
- { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
-
- /* SPI */
- { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_SPIFLASH },
-
- /* NOR */
- { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_BOOTROM },
-};
-
-void reset_cpu(unsigned long ignored)
-{
- struct mvebu_system_registers *reg =
- (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
-
- writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
- writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
- while (1)
- ;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
- u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
-
- puts("SoC: ");
-
- switch (devid) {
- case SOC_MV78460_ID:
- puts("MV78460-");
- break;
- default:
- puts("Unknown-");
- break;
- }
-
- switch (revid) {
- case 1:
- puts("A0\n");
- break;
- case 2:
- puts("B0\n");
- break;
- default:
- puts("??\n");
- break;
- }
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-/*
- * This function initialize Controller DRAM Fastpath windows.
- * It takes the CS size information from the 0x1500 scratch registers
- * and sets the correct windows sizes and base addresses accordingly.
- *
- * These values are set in the scratch registers by the Marvell
- * DDR3 training code, which is executed by the BootROM before the
- * main payload (U-Boot) is executed. This training code is currently
- * only available in the Marvell U-Boot version. It needs to be
- * ported to mainline U-Boot SPL at some point.
- */
-static void update_sdram_window_sizes(void)
-{
- u64 base = 0;
- u32 size, temp;
- int i;
-
- for (i = 0; i < SDRAM_MAX_CS; i++) {
- size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
- if (size != 0) {
- size |= ~(SDRAM_ADDR_MASK);
-
- /* Set Base Address */
- temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
- writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
-
- /*
- * Check if out of max window size and resize
- * the window
- */
- temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
- ~(SDRAM_ADDR_MASK)) | 1;
- temp |= (size & SDRAM_ADDR_MASK);
- writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
-
- base += ((u64)size + 1);
- } else {
- /*
- * Disable window if not used, otherwise this
- * leads to overlapping enabled windows with
- * pretty strange results
- */
- clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
- }
- }
-}
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- /* Linux expects the internal registers to be at 0xf1000000 */
- writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
-
- /*
- * We need to call mvebu_mbus_probe() before calling
- * update_sdram_window_sizes() as it disables all previously
- * configured mbus windows and then configures them as
- * required for U-Boot. Calling update_sdram_window_sizes()
- * without this configuration will not work, as the internal
- * registers can't be accessed reliably because of potenial
- * double mapping.
- * After updating the SDRAM access windows we need to call
- * mvebu_mbus_probe() again, as this now correctly configures
- * the SDRAM areas that are later used by the MVEBU drivers
- * (e.g. USB, NETA).
- */
-
- /*
- * First disable all windows
- */
- mvebu_mbus_probe(NULL, 0);
-
- /*
- * Now the SDRAM access windows can be reconfigured using
- * the information in the SDRAM scratch pad registers
- */
- update_sdram_window_sizes();
-
- /*
- * Finally the mbus windows can be configured with the
- * updated SDRAM sizes
- */
- mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
-
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
- /* Nothing yet, perhaps we need something here later */
- return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
- mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
- mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
- mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
- mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
-
- return 0;
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile
deleted file mode 100644
index f4f35a4..0000000
--- a/arch/arm/cpu/armv7/at91/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2013
-# Bo Shen <voice.shen@atmel.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
-obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
deleted file mode 100644
index 2cdddb2..0000000
--- a/arch/arm/cpu/armv7/at91/clock.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
- case AT91_PMC_MCKR_CSS_MAIN:
- return gd->arch.main_clk_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLA:
- return gd->arch.plla_rate_hz;
- }
-
- return 0;
-}
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 18) & 0x7f;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else {
- freq = 0;
- }
-
- return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
- unsigned freq, mckr;
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
- unsigned tmp;
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = readl(&pmc->mcfr);
- } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
- tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
- }
-#endif
- gd->arch.main_clk_rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = readl(&pmc->mckr);
-
- /* plla divisor by 2 */
- if (mckr & (1 << 12))
- gd->arch.plla_rate_hz >>= 1;
-
- gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->arch.mck_rate_hz;
-
- /* prescale */
- freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
-
- switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
- case AT91_PMC_MCKR_MDIV_2:
- gd->arch.mck_rate_hz = freq / 2;
- break;
- case AT91_PMC_MCKR_MDIV_3:
- gd->arch.mck_rate_hz = freq / 3;
- break;
- case AT91_PMC_MCKR_MDIV_4:
- gd->arch.mck_rate_hz = freq / 4;
- break;
- default:
- break;
- }
-
- gd->arch.cpu_clk_rate_hz = freq;
-
- return 0;
-}
-
-void at91_plla_init(u32 pllar)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- writel(pllar, &pmc->pllar);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
- ;
-}
-
-void at91_mck_init(u32 mckr)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 tmp;
-
- tmp = readl(&pmc->mckr);
- tmp &= ~(AT91_PMC_MCKR_CSS_MASK |
- AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_2);
- tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
- AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_2);
- writel(tmp, &pmc->mckr);
-
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
- ;
-}
-
-void at91_periph_clk_enable(int id)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 regval;
-
- if (id > AT91_PMC_PCR_PID_MASK)
- return;
-
- regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
-
- writel(regval, &pmc->pcr);
-}
-
-void at91_periph_clk_disable(int id)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 regval;
-
- if (id > AT91_PMC_PCR_PID_MASK)
- return;
-
- regval = AT91_PMC_PCR_CMD_WRITE | id;
-
- writel(regval, &pmc->pcr);
-}
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
deleted file mode 100644
index db60308..0000000
--- a/arch/arm/cpu/armv7/at91/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
deleted file mode 100644
index 8d86f97..0000000
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbu.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_gpbr.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-void arch_preboot_os(void)
-{
- ulong cpiv;
- at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
- cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
-
- /*
- * Disable PITC
- * Add 0x1000 to current counter to stop it faster
- * without waiting for wrapping back to 0
- */
- writel(cpiv + 0x1000, &pit->mr);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- char buf[32];
-
- printf("CPU: %s\n", get_cpu_name());
- printf("Crystal frequency: %8s MHz\n",
- strmhz(buf, get_main_clk_rate()));
- printf("CPU clock : %8s MHz\n",
- strmhz(buf, get_cpu_clk_rate()));
- printf("Master clock : %8s MHz\n",
- strmhz(buf, get_mck_clk_rate()));
-
- return 0;
-}
-#endif
-
-void enable_caches(void)
-{
- icache_enable();
- dcache_enable();
-}
-
-unsigned int get_chip_id(void)
-{
- return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
-}
-
-unsigned int get_extension_chip_id(void)
-{
- return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
-}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
deleted file mode 100644
index b30e79b..0000000
--- a/arch/arm/cpu/armv7/at91/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-
-/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
-{
- at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
-
- writel(AT91_RSTC_KEY
- | AT91_RSTC_CR_PROCRST /* Processor Reset */
- | AT91_RSTC_CR_PERRST /* Peripheral Reset */
-#ifdef CONFIG_AT91RESET_EXTRST
- | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
-#endif
- , &rstc->cr);
- /* never reached */
- do { } while (1);
-}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
deleted file mode 100644
index 78ecfc8..0000000
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (C) 2012-2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sama5d3.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-unsigned int has_emac()
-{
- return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
-}
-
-unsigned int has_gmac()
-{
- return !cpu_is_sama5d31();
-}
-
-unsigned int has_lcdc()
-{
- return !cpu_is_sama5d35();
-}
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_sama5d3())
- switch (extension_id) {
- case ARCH_EXID_SAMA5D31:
- return "SAMA5D31";
- case ARCH_EXID_SAMA5D33:
- return "SAMA5D33";
- case ARCH_EXID_SAMA5D34:
- return "SAMA5D34";
- case ARCH_EXID_SAMA5D35:
- return "SAMA5D35";
- case ARCH_EXID_SAMA5D36:
- return "SAMA5D36";
- default:
- return "Unknown CPU type";
- }
- else
- return "Unknown CPU type";
-}
-
-void at91_serial0_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART0);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART1);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
- at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART2);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
- at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_DBGU);
-}
-
-#if defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
-
- if (cs_mask & (1 << 0))
- at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
- if (cs_mask & (1 << 1))
- at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
- if (cs_mask & (1 << 2))
- at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
- if (cs_mask & (1 << 3))
- at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void at91_mci_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
- at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
- at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
-#ifdef CONFIG_ATMEL_MCI_8BIT
- at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
- at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
- at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
- at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
-#endif
- at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_MCI0);
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_EMAC);
-}
-
-void at91_gmac_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
-
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
-
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_GMAC);
-}
-#endif
-
-#ifdef CONFIG_LCD
-void at91_lcd_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
-
- /* The lower 16-bit of LCD only available on Port A */
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-void at91_udp_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable UPLL clock */
- writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
- /* Enable UDPHS clock */
- at91_periph_clk_enable(ATMEL_ID_UDPHS);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c
deleted file mode 100644
index 2708097..0000000
--- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sama5d4.h>
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_sama5d4())
- switch (extension_id) {
- case ARCH_EXID_SAMA5D41:
- return "SAMA5D41";
- case ARCH_EXID_SAMA5D42:
- return "SAMA5D42";
- case ARCH_EXID_SAMA5D43:
- return "SAMA5D43";
- case ARCH_EXID_SAMA5D44:
- return "SAMA5D44";
- default:
- return "Unknown CPU type";
- }
- else
- return "Unknown CPU type";
-}
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
deleted file mode 100644
index 19bf80b..0000000
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <div64.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * We're using the SAMA5D3x PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- * (See the relevant data sheets to understand that this really works)
- *
- * We do also mimic the typical powerpc way of incrementing
- * two 32 bit registers called tbl and tbu.
- *
- * Those registers increment at 1/16 the main clock rate.
- */
-
-#define TIMER_LOAD_VAL 0xfffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/*
- * Use the PITC in full 32 bit incrementing mode
- */
-int timer_init(void)
-{
- at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
- /* Enable PITC Clock */
- at91_periph_clk_enable(ATMEL_ID_PIT);
-
- /* Enable PITC */
- writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
- gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
-
- gd->arch.tbu = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
- ulong now = readl(&pit->piir);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/armv7/bcm235xx/Makefile b/arch/arm/cpu/armv7/bcm235xx/Makefile
new file mode 100644
index 0000000..3d09126
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013 Broadcom Corporation.
+
+obj-y += clk-core.o
+obj-y += clk-bcm235xx.o
+obj-y += clk-sdio.o
+obj-y += clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y += clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
new file mode 100644
index 0000000..39217c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+/*
+ *
+ * bcm235xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K 1000
+#define CLOCK_1M (CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+ .clk = { \
+ .name = #clk_name, \
+ .parent = clk_parent, \
+ .rate = clk_rate, \
+ .div = clk_div, \
+ .ops = &ref_clk_ops, \
+ }, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
+DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
+DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
+DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
+DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
+DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
+DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
+DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
+DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
+DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
+DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
+
+struct refclk_lkup {
+ struct refclk *procclk;
+ const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+ MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+ MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+ MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+ MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+ int i;
+ struct refclk_lkup *tblp = refclk_str_tbl;
+ for (i = 0; i < refclk_entries; i++, tblp++) {
+ if (!(strcmp(name, tblp->name)))
+ return tblp->procclk;
+ }
+ return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 208 * CLOCK_1M,
+ 312 * CLOCK_1M,
+ 312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 78 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 78 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 26 * CLOCK_1M,
+ 39 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 78 * CLOCK_1M
+};
+
+unsigned long esub_freq_tbl[8] = {
+ 78 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 208 * CLOCK_1M,
+ 208 * CLOCK_1M,
+ 208 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+ .gate = HW_SW_GATE(0x0358, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a28, 0, 3),
+ .div = DIVIDER(0x0a28, 4, 14),
+ .trig = TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+ .gate = HW_SW_GATE(0x035c, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a2c, 0, 3),
+ .div = DIVIDER(0x0a2c, 4, 14),
+ .trig = TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+ .gate = HW_SW_GATE(0x0364, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a34, 0, 3),
+ .div = DIVIDER(0x0a34, 4, 14),
+ .trig = TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+ .gate = HW_SW_GATE(0x0360, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a30, 0, 3),
+ .div = DIVIDER(0x0a30, 4, 14),
+ .trig = TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+ .gate = HW_SW_GATE(0x0458, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_104m",
+ "ref_104m",
+ "var_13m",
+ "ref_13m"),
+ .sel = SELECTOR(0x0a64, 0, 3),
+ .trig = TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+ .gate = HW_SW_GATE(0x045c, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_104m",
+ "ref_104m",
+ "var_13m",
+ "ref_13m"),
+ .sel = SELECTOR(0x0a68, 0, 3),
+ .trig = TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+ .gate = HW_SW_GATE(0x0484, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_104m",
+ "ref_104m",
+ "var_13m",
+ "ref_13m"),
+ .sel = SELECTOR(0x0a84, 0, 3),
+ .trig = TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+ .clk = {
+ .name = "kpm_ccu_clk",
+ .ops = &ccu_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .num_policy_masks = 1,
+ .policy_freq_offset = 0x00000008,
+ .freq_bit_shift = 8,
+ .policy_ctl_offset = 0x0000000c,
+ .policy0_mask_offset = 0x00000010,
+ .policy1_mask_offset = 0x00000014,
+ .policy2_mask_offset = 0x00000018,
+ .policy3_mask_offset = 0x0000001c,
+ .lvm_en_offset = 0x00000034,
+ .freq_id = 2,
+ .freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+ .clk = {
+ .name = "kps_ccu_clk",
+ .ops = &ccu_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .num_policy_masks = 1,
+ .policy_freq_offset = 0x00000008,
+ .freq_bit_shift = 8,
+ .policy_ctl_offset = 0x0000000c,
+ .policy0_mask_offset = 0x00000010,
+ .policy1_mask_offset = 0x00000014,
+ .policy2_mask_offset = 0x00000018,
+ .policy3_mask_offset = 0x0000001c,
+ .lvm_en_offset = 0x00000034,
+ .freq_id = 2,
+ .freq_tbl = slave_axi_freq_tbl,
+};
+
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+ .clk = {
+ .name = "esub_ccu_clk",
+ .ops = &ccu_clk_ops,
+ .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+ },
+ .num_policy_masks = 1,
+ .policy_freq_offset = 0x00000008,
+ .freq_bit_shift = 8,
+ .policy_ctl_offset = 0x0000000c,
+ .policy0_mask_offset = 0x00000010,
+ .policy1_mask_offset = 0x00000014,
+ .policy2_mask_offset = 0x00000018,
+ .policy3_mask_offset = 0x0000001c,
+ .lvm_en_offset = 0x00000034,
+ .freq_id = 2,
+ .freq_tbl = esub_freq_tbl,
+};
+#endif
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+ .clk = {
+ .name = "usb_otg_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &usb_otg_ahb_data,
+};
+
+static struct bus_clock sdio1_ahb_clk = {
+ .clk = {
+ .name = "sdio1_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+ .clk = {
+ .name = "sdio2_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+ .clk = {
+ .name = "sdio3_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+ .clk = {
+ .name = "sdio4_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+ .clk = {
+ .name = "bsc1_apb_clk",
+ .parent = &kps_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .freq_tbl = slave_apb_freq_tbl,
+ .data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+ .clk = {
+ .name = "bsc2_apb_clk",
+ .parent = &kps_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .freq_tbl = slave_apb_freq_tbl,
+ .data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+ .clk = {
+ .name = "bsc3_apb_clk",
+ .parent = &kps_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .freq_tbl = slave_apb_freq_tbl,
+ .data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+ .clk = {
+ .name = "sdio1_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+ .clk = {
+ .name = "sdio2_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+ .clk = {
+ .name = "sdio3_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+ .clk = {
+ .name = "sdio4_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+ .clk = {
+ .name = "sdio1_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+ .clk = {
+ .name = "sdio2_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+ .clk = {
+ .name = "sdio3_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+ .clk = {
+ .name = "sdio4_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+ .clk = {
+ .name = "bsc1_clk",
+ .parent = &ref_13m.clk,
+ .rate = 13 * CLOCK_1M,
+ .div = 1,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+ .clk = {
+ .name = "bsc2_clk",
+ .parent = &ref_13m.clk,
+ .rate = 13 * CLOCK_1M,
+ .div = 1,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+ .clk = {
+ .name = "bsc3_clk",
+ .parent = &ref_13m.clk,
+ .rate = 13 * CLOCK_1M,
+ .div = 1,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+ /* Peripheral clocks */
+ CLK_LK(sdio1),
+ CLK_LK(sdio2),
+ CLK_LK(sdio3),
+ CLK_LK(sdio4),
+ CLK_LK(sdio1_sleep),
+ CLK_LK(sdio2_sleep),
+ CLK_LK(sdio3_sleep),
+ CLK_LK(sdio4_sleep),
+ CLK_LK(bsc1),
+ CLK_LK(bsc2),
+ CLK_LK(bsc3),
+ /* Bus clocks */
+ CLK_LK(usb_otg_ahb),
+ CLK_LK(sdio1_ahb),
+ CLK_LK(sdio2_ahb),
+ CLK_LK(sdio3_ahb),
+ CLK_LK(sdio4_ahb),
+ CLK_LK(bsc1_apb),
+ CLK_LK(bsc2_apb),
+ CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+ CLK_LK(esub_ccu),
+#endif
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
new file mode 100644
index 0000000..1b3f36a
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+ int ret;
+ char *bscstr, *apbstr;
+
+ switch ((u32) base) {
+ case PMU_BSC_BASE_ADDR:
+ /* PMU clock is always enabled */
+ return 0;
+ case BSC1_BASE_ADDR:
+ bscstr = "bsc1_clk";
+ apbstr = "bsc1_apb_clk";
+ break;
+ case BSC2_BASE_ADDR:
+ bscstr = "bsc2_clk";
+ apbstr = "bsc2_apb_clk";
+ break;
+ case BSC3_BASE_ADDR:
+ bscstr = "bsc3_clk";
+ apbstr = "bsc3_apb_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ /* Note that the bus clock must be enabled first */
+
+ ret = clk_get_and_enable(apbstr);
+ if (ret)
+ return ret;
+
+ ret = clk_get_and_enable(bscstr);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
new file mode 100644
index 0000000..72f8eb7
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+/*
+ *
+ * bcm235xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
+#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
+#define POLICY_CTL_GO 1 /* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL 4 /* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+ int ret = 0;
+ struct clk *c;
+
+ debug("%s: %s\n", __func__, clkstr);
+
+ c = clk_get(clkstr);
+ if (c) {
+ ret = clk_enable(c);
+ if (ret)
+ return ret;
+ } else {
+ printf("%s: Couldn't find %s\n", __func__, clkstr);
+ return -EINVAL;
+ }
+ return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear). Delay
+ * a microsecond after each read of the register. Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+ unsigned int tries;
+ u32 bit_mask = 1 << bit;
+
+ for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+ u32 val;
+ bool bit_val;
+
+ val = readl(base + offset);
+ bit_val = (val & bit_mask) ? 1 : 0;
+ if (bit_val == want)
+ return 0; /* success */
+ udelay(1);
+ }
+
+ debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+ __func__, base + offset, bit, want);
+
+ return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+ int ret = 0;
+ u32 reg;
+ struct peri_clock *peri_clk = to_peri_clk(c);
+ struct peri_clk_data *cd = peri_clk->data;
+ struct bcm_clk_gate *gate = &cd->gate;
+ void *base = (void *)c->ccu_clk_mgr_base;
+
+
+ debug("%s: %s\n", __func__, c->name);
+
+ clk_get_rate(c); /* Make sure rate and sel are filled in */
+
+ /* enable access */
+ writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+ if (enable) {
+ debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+ __func__, c->name, c->rate, c->div, c->sel,
+ c->parent->rate);
+
+ /*
+ * clkgate - only software controllable gates are
+ * supported by u-boot which includes all clocks
+ * that matter. This avoids bringing in a lot of extra
+ * complexity as done in the kernel framework.
+ */
+ if (gate_exists(gate)) {
+ reg = readl(base + cd->gate.offset);
+ reg |= (1 << cd->gate.en_bit);
+ writel(reg, base + cd->gate.offset);
+ }
+
+ /* div and pll select */
+ if (divider_exists(&cd->div)) {
+ reg = readl(base + cd->div.offset);
+ bitfield_replace(reg, cd->div.shift, cd->div.width,
+ c->div - 1);
+ writel(reg, base + cd->div.offset);
+ }
+
+ /* frequency selector */
+ if (selector_exists(&cd->sel)) {
+ reg = readl(base + cd->sel.offset);
+ bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+ c->sel);
+ writel(reg, base + cd->sel.offset);
+ }
+
+ /* trigger */
+ if (trigger_exists(&cd->trig)) {
+ writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+ /* wait for trigger status bit to go to 0 */
+ ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+ if (ret)
+ return ret;
+ }
+
+ /* wait for running (status_bit = 1) */
+ ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+ if (ret)
+ return ret;
+ } else {
+ debug("%s disable clock %s\n", __func__, c->name);
+
+ /* clkgate */
+ reg = readl(base + cd->gate.offset);
+ reg &= ~(1 << cd->gate.en_bit);
+ writel(reg, base + cd->gate.offset);
+
+ /* wait for stop (status_bit = 0) */
+ ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+ }
+
+ /* disable access */
+ writel(0, base + WR_ACCESS_OFFSET);
+
+ return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+ int ret = 0;
+ int i;
+ unsigned long diff;
+ unsigned long new_rate = 0, div = 1;
+ struct peri_clock *peri_clk = to_peri_clk(c);
+ struct peri_clk_data *cd = peri_clk->data;
+ const char **clock;
+
+ debug("%s: %s\n", __func__, c->name);
+ diff = rate;
+
+ i = 0;
+ for (clock = cd->clocks; *clock; clock++, i++) {
+ struct refclk *ref = refclk_str_to_clk(*clock);
+ if (!ref) {
+ printf("%s: Lookup of %s failed\n", __func__, *clock);
+ return -EINVAL;
+ }
+
+ /* round to the new rate */
+ div = ref->clk.rate / rate;
+ if (div == 0)
+ div = 1;
+
+ new_rate = ref->clk.rate / div;
+
+ /* get the min diff */
+ if (abs(new_rate - rate) < diff) {
+ diff = abs(new_rate - rate);
+ c->sel = i;
+ c->parent = &ref->clk;
+ c->rate = new_rate;
+ c->div = div;
+ }
+ }
+
+ debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+ c->name, c->rate, c->div, c->sel, c->parent->rate);
+ return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+ struct peri_clock *peri_clk = to_peri_clk(c);
+ struct peri_clk_data *cd = peri_clk->data;
+ void *base = (void *)c->ccu_clk_mgr_base;
+ int div = 1;
+ const char **clock;
+ struct refclk *ref;
+ u32 reg;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (selector_exists(&cd->sel)) {
+ reg = readl(base + cd->sel.offset);
+ c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+ } else {
+ /*
+ * For peri clocks that don't have a selector, the single
+ * reference clock will always exist at index 0.
+ */
+ c->sel = 0;
+ }
+
+ if (divider_exists(&cd->div)) {
+ reg = readl(base + cd->div.offset);
+ div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+ div += 1;
+ }
+
+ clock = cd->clocks;
+ ref = refclk_str_to_clk(clock[c->sel]);
+ if (!ref) {
+ printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+ return 0;
+ }
+
+ c->parent = &ref->clk;
+ c->div = div;
+ c->rate = c->parent->rate / c->div;
+ debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+ c->parent->rate, div, c->sel, c->rate);
+
+ return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+ .enable = peri_clk_enable,
+ .set_rate = peri_clk_set_rate,
+ .get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+ struct ccu_clock *ccu_clk = to_ccu_clk(c);
+ void *base = (void *)c->ccu_clk_mgr_base;
+ int ret = 0;
+ u32 reg;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (!enable)
+ return -EINVAL; /* CCU clock cannot shutdown */
+
+ /* enable access */
+ writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+ /* config enable for policy engine */
+ writel(1, base + ccu_clk->lvm_en_offset);
+
+ /* wait for bit to go to 0 */
+ ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+ if (ret)
+ return ret;
+
+ /* freq ID */
+ if (!ccu_clk->freq_bit_shift)
+ ccu_clk->freq_bit_shift = 8;
+
+ /* Set frequency id for each of the 4 policies */
+ reg = ccu_clk->freq_id |
+ (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+ (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+ (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+ writel(reg, base + ccu_clk->policy_freq_offset);
+
+ /* enable all clock mask */
+ writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+ writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+ writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+ writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+ if (ccu_clk->num_policy_masks == 2) {
+ writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+ writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+ writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+ writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+ }
+
+ /* start policy engine */
+ reg = readl(base + ccu_clk->policy_ctl_offset);
+ reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+ writel(reg, base + ccu_clk->policy_ctl_offset);
+
+ /* wait till started */
+ ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+ if (ret)
+ return ret;
+
+ /* disable access */
+ writel(0, base + WR_ACCESS_OFFSET);
+
+ return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+ struct ccu_clock *ccu_clk = to_ccu_clk(c);
+ debug("%s: %s\n", __func__, c->name);
+ c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+ return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+ .enable = ccu_clk_enable,
+ .get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+ struct bus_clock *bus_clk = to_bus_clk(c);
+ struct bus_clk_data *cd = bus_clk->data;
+ void *base = (void *)c->ccu_clk_mgr_base;
+ int ret = 0;
+ u32 reg;
+
+ debug("%s: %s\n", __func__, c->name);
+ /* enable access */
+ writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+ /* enable gating */
+ reg = readl(base + cd->gate.offset);
+ if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+ debug("%s already %s\n", c->name,
+ enable ? "enabled" : "disabled");
+ else {
+ int want = (enable) ? 1 : 0;
+ reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+ if (enable)
+ reg |= (1 << cd->gate.en_bit);
+ else
+ reg &= ~(1 << cd->gate.en_bit);
+
+ writel(reg, base + cd->gate.offset);
+ ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+ want);
+ if (ret)
+ return ret;
+ }
+
+ /* disable access */
+ writel(0, base + WR_ACCESS_OFFSET);
+
+ return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+ struct bus_clock *bus_clk = to_bus_clk(c);
+ struct ccu_clock *ccu_clk;
+
+ debug("%s: %s\n", __func__, c->name);
+ ccu_clk = to_ccu_clk(c->parent);
+
+ c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+ c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+ return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+ .enable = bus_clk_enable,
+ .get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+ debug("%s: %s\n", __func__, c->name);
+ return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+ .enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+ debug("%s:\n", __func__);
+ return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+ int i;
+ struct clk_lookup *clk_tblp;
+
+ debug("%s: %s\n", __func__, con_id);
+
+ clk_tblp = arch_clk_tbl;
+ for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+ if (clk_tblp->con_id) {
+ if (!con_id || strcmp(clk_tblp->con_id, con_id))
+ continue;
+ return clk_tblp->clk;
+ }
+ }
+ return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+ int ret = 0;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (!c->ops || !c->ops->enable)
+ return -1;
+
+ /* enable parent clock first */
+ if (c->parent)
+ ret = clk_enable(c->parent);
+
+ if (ret)
+ return ret;
+
+ if (!c->use_cnt)
+ ret = c->ops->enable(c, 1);
+ c->use_cnt++;
+
+ return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+ debug("%s: %s\n", __func__, c->name);
+ if (!c->ops || !c->ops->enable)
+ return;
+
+ if (c->use_cnt > 0) {
+ c->use_cnt--;
+ if (c->use_cnt == 0)
+ c->ops->enable(c, 0);
+ }
+
+ /* disable parent */
+ if (c->parent)
+ clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+ unsigned long rate;
+
+ if (!c || !c->ops || !c->ops->get_rate)
+ return 0;
+ debug("%s: %s\n", __func__, c->name);
+
+ rate = c->ops->get_rate(c);
+ debug("%s: rate = %ld\n", __func__, rate);
+ return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+ int ret;
+
+ if (!c || !c->ops || !c->ops->set_rate)
+ return -EINVAL;
+ debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+
+ if (c->use_cnt)
+ return -EINVAL;
+
+ ret = c->ops->set_rate(c, rate);
+
+ return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.h b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
new file mode 100644
index 0000000..ac475b6
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
@@ -0,0 +1,490 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+ printf("Write [0x%p] = 0x%08x\n", addr, val);
+ *(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+ u32 val = *(u32 *)addr;
+ printf("Read [0x%p] = 0x%08x\n", addr, val);
+ return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+ const char *dev_id;
+ const char *con_id;
+ struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+ int (*enable)(struct clk *c, int enable);
+ int (*set_rate)(struct clk *c, unsigned long rate);
+ unsigned long (*get_rate)(struct clk *c);
+ unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+ int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+struct clk {
+ struct clk *parent;
+ const char *name;
+ int use_cnt;
+ unsigned long rate; /* in HZ */
+
+ /* programmable divider. 0 means fixed ratio to parent clock */
+ unsigned long div;
+
+ struct clk_src *src;
+ struct clk_ops *ops;
+
+ unsigned long ccu_clk_mgr_base;
+ int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX ((u32)U8_MAX)
+
+#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
+#define BAD_CLK_NAME ((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE U64_MAX
+
+/*
+ * Utility macros for object flag management. If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div) (!divider_is_fixed(div) && \
+ (div)->frac_width > 0)
+
+#define selector_exists(sel) ((sel)->width != 0)
+#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+ bcm_clk_none, /* undefined clock type */
+ bcm_clk_bus,
+ bcm_clk_core,
+ bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ * A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ * Enabling or disabling clocks with this type of gate is
+ * managed automatically by the hardware. Such clocks can be
+ * considered by the software to be enabled. The current status
+ * of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ * Auto-gating is not available for this type of clock.
+ * Instead, software manages whether it's enabled by setting or
+ * clearing the enable bit. The current gate status of a gate
+ * under software control can be read from the gate status bit.
+ * To ensure a change to the gating status is complete, the
+ * status bit can be polled to verify that the gate has entered
+ * the desired state.
+ * - selectable hardware or software gating
+ * Gating for this type of clock can be configured to be either
+ * under software or hardware control. Which type is in use is
+ * determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+ u32 offset; /* gate register offset */
+ u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
+ u32 en_bit; /* 0: disable; 1: enable */
+ u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
+ u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ * HW means this gate can be auto-gated
+ * SW means the state of this gate can be software controlled
+ * NO_DISABLE means this gate is (only) enabled if under software control
+ * SW_MANAGED means the status of this gate is under software control
+ * ENABLED means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .hw_sw_sel_bit = (_hw_sw_sel_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
+ FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
+ FLAG(GATE, EXISTS), \
+ }
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .hw_sw_sel_bit = (_hw_sw_sel_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
+ FLAG(GATE, EXISTS), \
+ }
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .hw_sw_sel_bit = (_hw_sw_sel_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
+ FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
+ }
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
+ FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
+ }
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
+ }
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock. Each divider can be either fixed or
+ * variable. If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider. If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register. The position of the field in the
+ * register is defined by its offset and width. The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider. Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point. Most variable dividers have zero
+ * fractional bits. Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only. (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values. A scaled value is one that's
+ * been left-shifted by the fractional width of a divider. Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified. To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate). In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+ union {
+ struct { /* variable divider */
+ u32 offset; /* divider register offset */
+ u32 shift; /* field shift */
+ u32 width; /* field width */
+ u32 frac_width; /* field fraction width */
+
+ u64 scaled_div; /* scaled divider value */
+ };
+ u32 fixed; /* non-zero fixed divider value */
+ };
+ u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ * EXISTS means this divider exists
+ * FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value) \
+ { \
+ .fixed = (_value), \
+ .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
+ }
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width) \
+ { \
+ .offset = (_offset), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .scaled_div = BAD_SCALED_DIV_VALUE, \
+ .flags = FLAG(DIV, EXISTS), \
+ }
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
+ { \
+ .offset = (_offset), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .frac_width = (_frac_width), \
+ .scaled_div = BAD_SCALED_DIV_VALUE, \
+ .flags = FLAG(DIV, EXISTS), \
+ }
+
+/*
+ * Clocks may have multiple "parent" clocks. If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use. The selected clock is indicated in a
+ * sub-field of a 32-bit selector register. The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks. Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+ u32 offset; /* selector register offset */
+ u32 shift; /* field shift */
+ u32 width; /* field width */
+
+ u32 parent_count; /* number of entries in parent_sel[] */
+ u32 *parent_sel; /* array of parent selector values */
+ u8 clk_index; /* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width) \
+ { \
+ .offset = (_offset), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .clk_index = BAD_CLK_INDEX, \
+ }
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger. A trigger is defined by a single
+ * bit within a register. To signal a change, a 1 is written into
+ * that bit. To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger. In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+ u32 offset; /* trigger register offset */
+ u32 bit; /* trigger bit */
+ u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ * EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit) \
+ { \
+ .offset = (_offset), \
+ .bit = (_bit), \
+ .flags = FLAG(TRIG, EXISTS), \
+ }
+
+struct bus_clk_data {
+ struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+ struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+ struct bcm_clk_gate gate;
+ struct bcm_clk_trig pre_trig;
+ struct bcm_clk_div pre_div;
+ struct bcm_clk_trig trig;
+ struct bcm_clk_div div;
+ struct bcm_clk_sel sel;
+ const char *clocks[]; /* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...) { __VA_ARGS__, NULL, }
+#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
+
+struct refclk {
+ struct clk clk;
+};
+
+struct peri_clock {
+ struct clk clk;
+ struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+ struct clk clk;
+
+ int num_policy_masks;
+ unsigned long policy_freq_offset;
+ int freq_bit_shift; /* 8 for most CCUs */
+ unsigned long policy_ctl_offset;
+ unsigned long policy0_mask_offset;
+ unsigned long policy1_mask_offset;
+ unsigned long policy2_mask_offset;
+ unsigned long policy3_mask_offset;
+ unsigned long policy0_mask2_offset;
+ unsigned long policy1_mask2_offset;
+ unsigned long policy2_mask2_offset;
+ unsigned long policy3_mask2_offset;
+ unsigned long lvm_en_offset;
+
+ int freq_id;
+ unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+ struct clk clk;
+ struct bus_clk_data *data;
+ unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+ struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+ return a == b;
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+ return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+ return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+ return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+ return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+ return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+int clk_get_and_enable(char *clkstr);
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
new file mode 100644
index 0000000..618af70
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD 0xA5A500
+
+#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
+
+#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
+
+#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
+#define ESW_SYS_DIV_DIV_MASK 0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
+#define ESW_SYS_DIV_DIV_SELECT 0x4
+#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
+
+#define PLL_MAX_RETRY 100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+ int rc = -1;
+ int retry_count = 0;
+ rc = clk_get_and_enable("esub_ccu_clk");
+
+ /* Enable Access to CCU registers */
+ writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+ writel(readl(PLLE_POST_RESETB_ADDR) &
+ ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+ PLLE_POST_RESETB_ADDR);
+
+ /* Take PLL out of reset and put into normal mode */
+ writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+ PLLE_RESETB_ADDR);
+
+ /* Wait for PLL lock */
+ rc = -1;
+ while (retry_count < PLL_MAX_RETRY) {
+ udelay(100);
+ if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+ rc = 0;
+ break;
+ }
+ retry_count++;
+ }
+
+ if (rc == -1) {
+ printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+ __func__);
+ return -1;
+ }
+
+ writel(readl(PLLE_POST_RESETB_ADDR) |
+ PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+ PLLE_POST_RESETB_ADDR);
+
+ /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+ writel((readl(ESW_SYS_DIV_ADDR) &
+ ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+ ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+ ESW_SYS_DIV_ADDR);
+
+ writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+ ESW_SYS_DIV_ADDR);
+
+ /* Wait for trigger complete */
+ rc = -1;
+ retry_count = 0;
+ while (retry_count < PLL_MAX_RETRY) {
+ udelay(100);
+ if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+ rc = 0;
+ break;
+ }
+ retry_count++;
+ }
+
+ if (rc == -1) {
+ printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+ __func__);
+ return -1;
+ }
+
+ /* switch Esub AXI clock to 208MHz */
+ writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+ ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+ ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+ ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+ ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+ ESUB_AXI_DIV_DEBUG_ADDR);
+
+ writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+ ESUB_AXI_DIV_DEBUG_ADDR);
+
+ /* Wait for trigger complete */
+ rc = -1;
+ retry_count = 0;
+ while (retry_count < PLL_MAX_RETRY) {
+ udelay(100);
+ if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+ rc = 0;
+ break;
+ }
+ retry_count++;
+ }
+
+ if (rc == -1) {
+ printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+ __func__);
+ return -1;
+ }
+
+ /* Disable Access to CCU registers */
+ writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+ return rc;
+}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
new file mode 100644
index 0000000..f2ba354
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+ int ret;
+ struct clk *c;
+
+ char *clkstr;
+ char *slpstr;
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case CONFIG_SYS_SDIO_BASE0:
+ clkstr = CONFIG_SYS_SDIO0 "_clk";
+ ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+ break;
+ case CONFIG_SYS_SDIO_BASE1:
+ clkstr = CONFIG_SYS_SDIO1 "_clk";
+ ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+ break;
+ case CONFIG_SYS_SDIO_BASE2:
+ clkstr = CONFIG_SYS_SDIO2 "_clk";
+ ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+ break;
+ case CONFIG_SYS_SDIO_BASE3:
+ clkstr = CONFIG_SYS_SDIO3 "_clk";
+ ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ ret = clk_get_and_enable(ahbstr);
+ if (ret)
+ return ret;
+
+ ret = clk_get_and_enable(slpstr);
+ if (ret)
+ return ret;
+
+ c = clk_get(clkstr);
+ if (c) {
+ ret = clk_set_rate(c, rate);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(c);
+ if (ret)
+ return ret;
+ } else {
+ printf("%s: Couldn't find %s\n", __func__, clkstr);
+ return -EINVAL;
+ }
+ *actual_ratep = rate;
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
new file mode 100644
index 0000000..f604aec
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case HSOTG_BASE_ADDR:
+ ahbstr = "usb_otg_ahb_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ return clk_get_and_enable(ahbstr);
+}
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile
index f24aeb3..e509997 100644
--- a/arch/arm/cpu/armv7/bcm281xx/Makefile
+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -1,8 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += reset.o
obj-y += clk-core.o
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index 7e25255..8f6260e 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
@@ -12,7 +11,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
index ba55d0a..1b3f36a 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
@@ -1,12 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c
index d442583..6a36f94 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
@@ -12,7 +11,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <bitfield.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
@@ -479,9 +478,9 @@
{
unsigned long rate;
- debug("%s: %s\n", __func__, c->name);
if (!c || !c->ops || !c->ops->get_rate)
return 0;
+ debug("%s: %s\n", __func__, c->name);
rate = c->ops->get_rate(c);
debug("%s: rate = %ld\n", __func__, rate);
@@ -493,9 +492,9 @@
{
int ret;
- debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (!c || !c->ops || !c->ops->set_rate)
return -EINVAL;
+ debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (c->use_cnt)
return -EINVAL;
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h
index 4a694d7..a736ae9 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-core.h
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/stddef.h>
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
index b0b92b9..618af70 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
@@ -1,12 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
index 49badcb..f2ba354 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
@@ -1,12 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
index 1d7c5af..f604aec 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c
index 3beb0ed..fbdeea4 100644
--- a/arch/arm/cpu/armv7/bcm281xx/reset.c
+++ b/arch/arm/cpu/armv7/bcm281xx/reset.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/bcmcygnus/Makefile b/arch/arm/cpu/armv7/bcmcygnus/Makefile
index 04afcf9..3496bcd 100644
--- a/arch/arm/cpu/armv7/bcmcygnus/Makefile
+++ b/arch/arm/cpu/armv7/bcmcygnus/Makefile
@@ -1,7 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2014 Broadcom Corporation.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += reset.o
diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c
index 53ecc0c..7f3f405 100644
--- a/arch/arm/cpu/armv7/bcmcygnus/reset.c
+++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/bcmnsp/Makefile b/arch/arm/cpu/armv7/bcmnsp/Makefile
index 04afcf9..3496bcd 100644
--- a/arch/arm/cpu/armv7/bcmnsp/Makefile
+++ b/arch/arm/cpu/armv7/bcmnsp/Makefile
@@ -1,7 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2014 Broadcom Corporation.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += reset.o
diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c
index d79d9aa..674166d 100644
--- a/arch/arm/cpu/armv7/bcmnsp/reset.c
+++ b/arch/arm/cpu/armv7/bcmnsp/reset.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 0f9d837..99484c2 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -1,32 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/types.h>
#include <common.h>
#include <asm/armv7.h>
#include <asm/utils.h>
-#define ARMV7_DCACHE_INVAL_ALL 1
-#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
-#define ARMV7_DCACHE_INVAL_RANGE 3
-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
+#define ARMV7_DCACHE_INVAL_RANGE 1
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
#ifndef CONFIG_SYS_DCACHE_OFF
-/*
- * Write the level and type you want to Cache Size Selection Register(CSSELR)
- * to get size details from Current Cache Size ID Register(CCSIDR)
- */
-static void set_csselr(u32 level, u32 type)
-{
- u32 csselr = level << 1 | type;
- /* Write to Cache Size Selection Register(CSSELR) */
- asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
-}
+/* Asm functions from cache_v7_asm.S */
+void v7_flush_dcache_all(void);
+void v7_invalidate_dcache_all(void);
static u32 get_ccsidr(void)
{
@@ -37,118 +27,6 @@
return ccsidr;
}
-static u32 get_clidr(void)
-{
- u32 clidr;
-
- /* Read current CP15 Cache Level ID Register */
- asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
- return clidr;
-}
-
-static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /* Invalidate data/unified cache line by set/way */
- asm volatile (" mcr p15, 0, %0, c7, c6, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- CP15DSB;
-}
-
-static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /*
- * Clean & Invalidate data/unified
- * cache line by set/way
- */
- asm volatile (" mcr p15, 0, %0, c7, c14, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- CP15DSB;
-}
-
-static void v7_maint_dcache_level_setway(u32 level, u32 operation)
-{
- u32 ccsidr;
- u32 num_sets, num_ways, log2_line_len, log2_num_ways;
- u32 way_shift;
-
- set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
-
- ccsidr = get_ccsidr();
-
- log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
- CCSIDR_LINE_SIZE_OFFSET) + 2;
- /* Converting from words to bytes */
- log2_line_len += 2;
-
- num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
- CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
- num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
- CCSIDR_NUM_SETS_OFFSET) + 1;
- /*
- * According to ARMv7 ARM number of sets and number of ways need
- * not be a power of 2
- */
- log2_num_ways = log_2_n_round_up(num_ways);
-
- way_shift = (32 - log2_num_ways);
- if (operation == ARMV7_DCACHE_INVAL_ALL) {
- v7_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
- v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- }
-}
-
-static void v7_maint_dcache_all(u32 operation)
-{
- u32 level, cache_type, level_start_bit = 0;
- u32 clidr = get_clidr();
-
- for (level = 0; level < 7; level++) {
- cache_type = (clidr >> level_start_bit) & 0x7;
- if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
- (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
- (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
- v7_maint_dcache_level_setway(level, operation);
- level_start_bit += 3;
- }
-}
-
static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
{
u32 mva;
@@ -165,27 +43,8 @@
{
u32 mva;
- /*
- * If start address is not aligned to cache-line do not
- * invalidate the first cache-line
- */
- if (start & (line_len - 1)) {
- printf("ERROR: %s - start address is not aligned - 0x%08x\n",
- __func__, start);
- /* move to next cache line */
- start = (start + line_len - 1) & ~(line_len - 1);
- }
-
- /*
- * If stop address is not aligned to cache-line do not
- * invalidate the last cache-line
- */
- if (stop & (line_len - 1)) {
- printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
- __func__, stop);
- /* align to the beginning of this cache line */
- stop &= ~(line_len - 1);
- }
+ if (!check_cache_range(start, stop))
+ return;
for (mva = start; mva < stop; mva = mva + line_len) {
/* DCIMVAC - Invalidate data cache by MVA to PoC */
@@ -215,7 +74,7 @@
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ dsb();
}
/* Invalidate TLB */
@@ -228,14 +87,14 @@
/* Invalidate entire instruction TLB */
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
+ dsb();
/* Full system ISB - make sure the instruction stream sees it */
- CP15ISB;
+ isb();
}
void invalidate_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+ v7_invalidate_dcache_all();
v7_outer_cache_inval_all();
}
@@ -246,7 +105,7 @@
*/
void flush_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
+ v7_flush_dcache_all();
v7_outer_cache_flush_all();
}
@@ -257,6 +116,8 @@
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
+ check_cache_range(start, stop);
+
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
v7_outer_cache_inval_range(start, stop);
@@ -269,6 +130,8 @@
*/
void flush_dcache_range(unsigned long start, unsigned long stop)
{
+ check_cache_range(start, stop);
+
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
v7_outer_cache_flush_range(start, stop);
@@ -286,15 +149,6 @@
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-
-/*
- * Flush range from all levels of d-cache/unified-cache used:
- * Affects the range [start, start + size - 1]
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -316,10 +170,6 @@
{
}
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
-
void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
}
@@ -343,10 +193,10 @@
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
+ dsb();
/* ISB - make sure the instruction stream sees it */
- CP15ISB;
+ isb();
}
#else
void invalidate_icache_all(void)
diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S
new file mode 100644
index 0000000..e38d72f
--- /dev/null
+++ b/arch/arm/cpu/armv7/cache_v7_asm.S
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <linux/sizes.h>
+#include <asm/system.h>
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#define ARM(x...)
+#define THUMB(x...) x
+#else
+#define ARM(x...) x
+#define THUMB(x...)
+#endif
+
+/*
+ * v7_flush_dcache_all()
+ *
+ * Flush the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(__v7_flush_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq finished @ if loc is 0, then no need to clean
+start_flush_levels:
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_flush_dcache_all)
+
+ENTRY(v7_flush_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_flush_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_flush_dcache_all)
+
+/*
+ * v7_invalidate_dcache_all()
+ *
+ * Invalidate the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from __v7_flush_dcache_all above with
+ * mcr p15, 0, r11, c7, c14, 2
+ * Replaced with:
+ * mcr p15, 0, r11, c7, c6, 2
+ */
+ENTRY(__v7_invalidate_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq inval_finished @ if loc is 0, then no need to clean
+ mov r10, #0 @ start clean at cache level 0
+inval_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt inval_skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+inval_loop1:
+ mov r9, r7 @ create working copy of max index
+inval_loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge inval_loop2
+ subs r4, r4, #1 @ decrement the way
+ bge inval_loop1
+inval_skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt inval_levels
+inval_finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_invalidate_dcache_all)
+
+ENTRY(v7_invalidate_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_invalidate_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_invalidate_dcache_all)
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 6c82c3b..68036d6 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -1,14 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# If armv7-a is not supported by GCC fall-back to armv5, which is
-# supported by more tool-chains
-PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
# On supported platforms we set the bit which causes us to trap on unaligned
# memory access. This is the opposite of what the compiler expects to be
diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c
new file mode 100644
index 0000000..0ac4e7b
--- /dev/null
+++ b/arch/arm/cpu/armv7/cp15.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Texas Insturments
+ */
+
+/*
+ * CP15 specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/armv7.h>
+#include <linux/compiler.h>
+
+void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
+}
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
+}
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7e..44f2757 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2008 Texas Insturments
*
@@ -7,8 +8,6 @@
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
@@ -24,7 +23,7 @@
void __weak cpu_cache_initialization(void){}
-int cleanup_before_linux(void)
+int cleanup_before_linux_select(int flags)
{
/*
* this function is called just before we call linux
@@ -36,30 +35,39 @@
disable_interrupts();
#endif
- /*
- * Turn off I-cache and invalidate it
- */
- icache_disable();
- invalidate_icache_all();
+ if (flags & CBL_DISABLE_CACHES) {
+ /*
+ * turn off D-cache
+ * dcache_disable() in turn flushes the d-cache and disables MMU
+ */
+ dcache_disable();
+ v7_outer_cache_disable();
- /*
- * turn off D-cache
- * dcache_disable() in turn flushes the d-cache and disables MMU
- */
- dcache_disable();
- v7_outer_cache_disable();
+ /*
+ * After D-cache is flushed and before it is disabled there may
+ * be some new valid entries brought into the cache. We are
+ * sure that these lines are not dirty and will not affect our
+ * execution. (because unwinding the call-stack and setting a
+ * bit in CP15 SCTRL is all we did during this. We have not
+ * pushed anything on to the stack. Neither have we affected
+ * any static data) So just invalidate the entire d-cache again
+ * to avoid coherency problems for kernel
+ */
+ invalidate_dcache_all();
- /*
- * After D-cache is flushed and before it is disabled there may
- * be some new valid entries brought into the cache. We are sure
- * that these lines are not dirty and will not affect our execution.
- * (because unwinding the call-stack and setting a bit in CP15 SCTRL
- * is all we did during this. We have not pushed anything on to the
- * stack. Neither have we affected any static data)
- * So just invalidate the entire d-cache again to avoid coherency
- * problems for kernel
- */
- invalidate_dcache_all();
+ icache_disable();
+ invalidate_icache_all();
+ } else {
+ /*
+ * Turn off I-cache and invalidate it
+ */
+ icache_disable();
+ invalidate_icache_all();
+
+ flush_dcache_all();
+ invalidate_icache_all();
+ icache_enable();
+ }
/*
* Some CPU need more cache attention before starting the kernel.
@@ -68,3 +76,8 @@
return 0;
}
+
+int cleanup_before_linux(void)
+{
+ return cleanup_before_linux_select(CBL_ALL);
+}
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
deleted file mode 100644
index 7fcb5d2..0000000
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-if ARCH_EXYNOS
-
-choice
- prompt "EXYNOS board select"
-
-config TARGET_SMDKV310
- select SUPPORT_SPL
- bool "Exynos4210 SMDKV310 board"
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_TRATS
- bool "Exynos4210 Trats board"
-
-config TARGET_S5PC210_UNIVERSAL
- bool "EXYNOS4210 Universal C210 board"
-
-config TARGET_ORIGEN
- bool "Exynos4412 Origen board"
- select SUPPORT_SPL
-
-config TARGET_TRATS2
- bool "Exynos4412 Trat2 board"
-
-config TARGET_ODROID
- bool "Exynos4412 Odroid board"
-
-config TARGET_ODROID_XU3
- bool "Exynos5422 Odroid board"
- select OF_CONTROL
-
-config TARGET_ARNDALE
- bool "Exynos5250 Arndale board"
- select CPU_V7_HAS_NONSEC
- select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_SMDK5250
- bool "SMDK5250 board"
- select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_SNOW
- bool "Snow board"
- select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_SMDK5420
- bool "SMDK5420 board"
- select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_PEACH_PI
- bool "Peach Pi board"
- select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_PEACH_PIT
- bool "Peach Pit board"
- select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
-
-endchoice
-
-config SYS_SOC
- default "exynos"
-
-source "board/samsung/smdkv310/Kconfig"
-source "board/samsung/trats/Kconfig"
-source "board/samsung/universal_c210/Kconfig"
-source "board/samsung/origen/Kconfig"
-source "board/samsung/trats2/Kconfig"
-source "board/samsung/odroid/Kconfig"
-source "board/samsung/arndale/Kconfig"
-source "board/samsung/smdk5250/Kconfig"
-source "board/samsung/smdk5420/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
deleted file mode 100644
index e207bd6..0000000
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Copyright (C) 2009 Samsung Electronics
-# Minkyu Kang <mk7.kang@samsung.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
-obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
-obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y += spl_boot.o
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
deleted file mode 100644
index b31c13b..0000000
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ /dev/null
@@ -1,1733 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/periph.h>
-
-#define PLL_DIV_1024 1024
-#define PLL_DIV_65535 65535
-#define PLL_DIV_65536 65536
-
-/* *
- * This structure is to store the src bit, div bit and prediv bit
- * positions of the peripheral clocks of the src and div registers
- */
-struct clk_bit_info {
- int8_t src_bit;
- int8_t div_bit;
- int8_t prediv_bit;
-};
-
-/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
- {0, 0, -1},
- {4, 4, -1},
- {8, 8, -1},
- {12, 12, -1},
- {0, 0, 8},
- {4, 16, 24},
- {8, 0, 8},
- {12, 16, 24},
- {-1, -1, -1},
- {16, 0, 8},
- {20, 16, 24},
- {24, 0, 8},
- {0, 0, 4},
- {4, 12, 16},
- {-1, -1, -1},
- {-1, -1, -1},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
-};
-
-/* Epll Clock division values to achive different frequency output */
-static struct set_epll_con_val exynos5_epll_div[] = {
- { 192000000, 0, 48, 3, 1, 0 },
- { 180000000, 0, 45, 3, 1, 0 },
- { 73728000, 1, 73, 3, 3, 47710 },
- { 67737600, 1, 90, 4, 3, 20762 },
- { 49152000, 0, 49, 3, 3, 9961 },
- { 45158400, 0, 45, 3, 3, 10381 },
- { 180633600, 0, 45, 3, 1, 10381 }
-};
-
-/* exynos: return pll clock frequency */
-static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
-{
- unsigned long m, p, s = 0, mask, fout;
- unsigned int div;
- unsigned int freq;
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- * BPLL_CON: MIDV [25:16]: Exynos5
- */
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
- pllreg == SPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ;
-
- if (pllreg == EPLL || pllreg == RPLL) {
- k = k & 0xffff;
- /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
- } else if (pllreg == VPLL) {
- k = k & 0xfff;
-
- /*
- * Exynos4210
- * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
- *
- * Exynos4412
- * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
- *
- * Exynos5250
- * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
- */
- if (proid_is_exynos4210())
- div = PLL_DIV_1024;
- else if (proid_is_exynos4412())
- div = PLL_DIV_65535;
- else if (proid_is_exynos5250() || proid_is_exynos5420()
- || proid_is_exynos5800())
- div = PLL_DIV_65536;
- else
- return 0;
-
- fout = (m + k / div) * (freq / (p * (1 << s)));
- } else {
- /*
- * Exynos4412 / Exynos5250
- * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
- *
- * Exynos4210
- * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
- */
- if (proid_is_exynos4210())
- fout = m * (freq / (p * (1 << (s - 1))));
- else
- fout = m * (freq / (p * (1 << s)));
- }
- return fout;
-}
-
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
-/* exynos4x12: return pll clock frequency */
-static unsigned long exynos4x12_get_pll_clk(int pllreg)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
-/* exynos5: return pll clock frequency */
-static unsigned long exynos5_get_pll_clk(int pllreg)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long r, k = 0, fout;
- unsigned int pll_div2_sel, fout_sel;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- case BPLL:
- r = readl(&clk->bpll_con0);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- fout = exynos_get_pll_clk(pllreg, r, k);
-
- /* According to the user manual, in EVT1 MPLL and BPLL always gives
- * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
- if (pllreg == MPLL || pllreg == BPLL) {
- pll_div2_sel = readl(&clk->pll_div2_sel);
-
- switch (pllreg) {
- case MPLL:
- fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
- & MPLL_FOUT_SEL_MASK;
- break;
- case BPLL:
- fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
- & BPLL_FOUT_SEL_MASK;
- break;
- default:
- fout_sel = -1;
- break;
- }
-
- if (fout_sel == 0)
- fout /= 2;
- }
-
- return fout;
-}
-
-static unsigned long exynos5_get_periph_rate(int peripheral)
-{
- struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
- unsigned long sclk, sub_clk;
- unsigned int src, div, sub_div;
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- src = readl(&clk->src_peric0);
- div = readl(&clk->div_peric0);
- break;
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- src = readl(&clk->src_peric0);
- div = readl(&clk->div_peric3);
- break;
- case PERIPH_ID_I2S0:
- src = readl(&clk->src_mau);
- div = readl(&clk->div_mau);
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric1);
- break;
- case PERIPH_ID_SPI2:
- src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric2);
- break;
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- src = readl(&clk->sclk_src_isp);
- div = readl(&clk->sclk_div_isp);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- src = readl(&clk->src_fsys);
- div = readl(&clk->div_fsys1);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- sclk = exynos5_get_pll_clk(MPLL);
- sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
- & 0x7) + 1;
- div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
- & 0x7) + 1;
- return (sclk / sub_div) / div;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- };
-
- src = (src >> bit_info->src_bit) & 0xf;
-
- switch (src) {
- case EXYNOS_SRC_MPLL:
- sclk = exynos5_get_pll_clk(MPLL);
- break;
- case EXYNOS_SRC_EPLL:
- sclk = exynos5_get_pll_clk(EPLL);
- break;
- case EXYNOS_SRC_VPLL:
- sclk = exynos5_get_pll_clk(VPLL);
- break;
- default:
- return 0;
- }
-
- /* Ratio clock division for this peripheral */
- sub_div = (div >> bit_info->div_bit) & 0xf;
- sub_clk = sclk / (sub_div + 1);
-
- /* Pre-ratio clock division for SDMMC0 and 2 */
- if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
- div = (div >> bit_info->prediv_bit) & 0xff;
- return sub_clk / (div + 1);
- }
-
- return sub_clk;
-}
-
-unsigned long clock_get_periph_rate(int peripheral)
-{
- if (cpu_is_exynos5())
- return exynos5_get_periph_rate(peripheral);
- else
- return 0;
-}
-
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- case BPLL:
- r = readl(&clk->bpll_con0);
- break;
- case RPLL:
- r = readl(&clk->rpll_con0);
- k = readl(&clk->rpll_con1);
- break;
- case SPLL:
- r = readl(&clk->spll_con0);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
-/* exynos4: return ARM clock frequency */
-static unsigned long exynos4_get_arm_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long armclk;
- unsigned int core_ratio;
- unsigned int core2_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
- core_ratio = (div >> 0) & 0x7;
- core2_ratio = (div >> 28) & 0x7;
-
- armclk = get_pll_clk(APLL) / (core_ratio + 1);
- armclk /= (core2_ratio + 1);
-
- return armclk;
-}
-
-/* exynos4x12: return ARM clock frequency */
-static unsigned long exynos4x12_get_arm_clk(void)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long armclk;
- unsigned int core_ratio;
- unsigned int core2_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
- core_ratio = (div >> 0) & 0x7;
- core2_ratio = (div >> 28) & 0x7;
-
- armclk = get_pll_clk(APLL) / (core_ratio + 1);
- armclk /= (core2_ratio + 1);
-
- return armclk;
-}
-
-/* exynos5: return ARM clock frequency */
-static unsigned long exynos5_get_arm_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long armclk;
- unsigned int arm_ratio;
- unsigned int arm2_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
- arm_ratio = (div >> 0) & 0x7;
- arm2_ratio = (div >> 28) & 0x7;
-
- armclk = get_pll_clk(APLL) / (arm_ratio + 1);
- armclk /= (arm2_ratio + 1);
-
- return armclk;
-}
-
-/* exynos4: return pwm clock frequency */
-static unsigned long exynos4_get_pwm_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- if (s5p_get_cpu_rev() == 0) {
- /*
- * CLK_SRC_PERIL0
- * PWM_SEL [27:24]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> 24) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL3
- * PWM_RATIO [3:0]
- */
- ratio = readl(&clk->div_peril3);
- ratio = ratio & 0xf;
- } else if (s5p_get_cpu_rev() == 1) {
- sclk = get_pll_clk(MPLL);
- ratio = 8;
- } else
- return 0;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* exynos4x12: return pwm clock frequency */
-static unsigned long exynos4x12_get_pwm_clk(void)
-{
- unsigned long pclk, sclk;
- unsigned int ratio;
-
- sclk = get_pll_clk(MPLL);
- ratio = 8;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* exynos5420: return pwm clock frequency */
-static unsigned long exynos5420_get_pwm_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int ratio;
-
- /*
- * CLK_DIV_PERIC0
- * PWM_RATIO [31:28]
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> 28) & 0xf;
- sclk = get_pll_clk(MPLL);
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* exynos4: return uart clock frequency */
-static unsigned long exynos4_get_uart_clk(int dev_index)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIL0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- * UART5_SEL [23:20]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- * UART5_RATIO [23:20]
- */
- ratio = readl(&clk->div_peril0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* exynos4x12: return uart clock frequency */
-static unsigned long exynos4x12_get_uart_clk(int dev_index)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIL0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- */
- ratio = readl(&clk->div_peril0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* exynos5: return uart clock frequency */
-static unsigned long exynos5_get_uart_clk(int dev_index)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIC0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- * UART5_SEL [23:20]
- */
- sel = readl(&clk->src_peric0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIC0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- * UART5_RATIO [23:20]
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* exynos5420: return uart clock frequency */
-static unsigned long exynos5420_get_uart_clk(int dev_index)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIC0
- * UART0_SEL [6:4]
- * UART1_SEL [10:8]
- * UART2_SEL [14:12]
- * UART3_SEL [18:16]
- * generalised calculation as follows
- * sel = (sel >> ((dev_index * 4) + 4)) & mask;
- */
- sel = readl(&clk->src_peric0);
- sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
-
- if (sel == 0x3)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x6)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(RPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIC0
- * UART0_RATIO [11:8]
- * UART1_RATIO [15:12]
- * UART2_RATIO [19:16]
- * UART3_RATIO [23:20]
- * generalised calculation as follows
- * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-static unsigned long exynos4_get_mmc_clk(int dev_index)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio, pre_ratio;
- int shift = 0;
-
- sel = readl(&clk->src_fsys);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- switch (dev_index) {
- case 0:
- case 1:
- ratio = readl(&clk->div_fsys1);
- pre_ratio = readl(&clk->div_fsys1);
- break;
- case 2:
- case 3:
- ratio = readl(&clk->div_fsys2);
- pre_ratio = readl(&clk->div_fsys2);
- break;
- case 4:
- ratio = readl(&clk->div_fsys3);
- pre_ratio = readl(&clk->div_fsys3);
- break;
- default:
- return 0;
- }
-
- if (dev_index == 1 || dev_index == 3)
- shift = 16;
-
- ratio = (ratio >> shift) & 0xf;
- pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
- uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
- return uclk;
-}
-
-static unsigned long exynos5_get_mmc_clk(int dev_index)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio, pre_ratio;
- int shift = 0;
-
- sel = readl(&clk->src_fsys);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- switch (dev_index) {
- case 0:
- case 1:
- ratio = readl(&clk->div_fsys1);
- pre_ratio = readl(&clk->div_fsys1);
- break;
- case 2:
- case 3:
- ratio = readl(&clk->div_fsys2);
- pre_ratio = readl(&clk->div_fsys2);
- break;
- default:
- return 0;
- }
-
- if (dev_index == 1 || dev_index == 3)
- shift = 16;
-
- ratio = (ratio >> shift) & 0xf;
- pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
- uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
- return uclk;
-}
-
-static unsigned long exynos5420_get_mmc_clk(int dev_index)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio;
-
- /*
- * CLK_SRC_FSYS
- * MMC0_SEL [10:8]
- * MMC1_SEL [14:12]
- * MMC2_SEL [18:16]
- * generalised calculation as follows
- * sel = (sel >> ((dev_index * 4) + 8)) & mask
- */
- sel = readl(&clk->src_fsys);
- sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
-
- if (sel == 0x3)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x4)
- sclk = get_pll_clk(SPLL);
- else if (sel == 0x6)
- sclk = get_pll_clk(EPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_RATIO [9:0]
- * MMC1_RATIO [19:10]
- * MMC2_RATIO [29:20]
- * generalised calculation as follows
- * ratio = (ratio >> (dev_index * 10)) & mask
- */
- ratio = readl(&clk->div_fsys1);
- ratio = (ratio >> (dev_index * 10)) & 0x3ff;
-
- uclk = (sclk / (ratio + 1));
-
- return uclk;
-}
-
-/* exynos4: set the mmc clock */
-static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned int addr, clear_bit, set_bit;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- * CLK_DIV_FSYS3
- * MMC4_RATIO [3:0]
- */
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- clear_bit = MASK_PRE_RATIO(dev_index);
- set_bit = SET_PRE_RATIO(dev_index, div);
- } else if (dev_index == 4) {
- addr = (unsigned int)&clk->div_fsys3;
- dev_index -= 4;
- /* MMC4 is controlled with the MMC4_RATIO value */
- clear_bit = MASK_RATIO(dev_index);
- set_bit = SET_RATIO(dev_index, div);
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- clear_bit = MASK_PRE_RATIO(dev_index);
- set_bit = SET_PRE_RATIO(dev_index, div);
- }
-
- clrsetbits_le32(addr, clear_bit, set_bit);
-}
-
-/* exynos5: set the mmc clock */
-static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- */
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
-/* exynos5: set the mmc clock */
-static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned int addr;
- unsigned int shift;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_RATIO [9:0]
- * MMC1_RATIO [19:10]
- * MMC2_RATIO [29:20]
- */
- addr = (unsigned int)&clk->div_fsys1;
- shift = dev_index * 10;
-
- clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
-}
-
-/* get_lcd_clk: return lcd clock frequency */
-static unsigned long exynos4_get_lcd_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- */
- sel = readl(&clk->src_lcd0);
- sel = sel & 0xf;
-
- /*
- * 0x6: SCLK_MPLL
- * 0x7: SCLK_EPLL
- * 0x8: SCLK_VPLL
- */
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- */
- ratio = readl(&clk->div_lcd0);
- ratio = ratio & 0xf;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* get_lcd_clk: return lcd clock frequency */
-static unsigned long exynos5_get_lcd_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- */
- sel = readl(&clk->src_disp1_0);
- sel = sel & 0xf;
-
- /*
- * 0x6: SCLK_MPLL
- * 0x7: SCLK_EPLL
- * 0x8: SCLK_VPLL
- */
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- */
- ratio = readl(&clk->div_disp1_0);
- ratio = ratio & 0xf;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-static unsigned long exynos5420_get_lcd_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_DISP10
- * FIMD1_SEL [4]
- * 0: SCLK_RPLL
- * 1: SCLK_SPLL
- */
- sel = readl(&clk->src_disp10);
- sel &= (1 << 4);
-
- if (sel)
- sclk = get_pll_clk(SPLL);
- else
- sclk = get_pll_clk(RPLL);
-
- /*
- * CLK_DIV_DISP10
- * FIMD1_RATIO [3:0]
- */
- ratio = readl(&clk->div_disp10);
- ratio = ratio & 0xf;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-void exynos4_set_lcd_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- /*
- * CLK_GATE_BLOCK
- * CLK_CAM [0]
- * CLK_TV [1]
- * CLK_MFC [2]
- * CLK_G3D [3]
- * CLK_LCD0 [4]
- * CLK_LCD1 [5]
- * CLK_GPS [7]
- */
- setbits_le32(&clk->gate_block, 1 << 4);
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- * MDNIE0_SEL [7:4]
- * MDNIE_PWM0_SEL [8:11]
- * MIPI0_SEL [12:15]
- * set lcd0 src clock 0x6: SCLK_MPLL
- */
- clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
-
- /*
- * CLK_GATE_IP_LCD0
- * CLK_FIMD0 [0]
- * CLK_MIE0 [1]
- * CLK_MDNIE0 [2]
- * CLK_DSIM0 [3]
- * CLK_SMMUFIMD0 [4]
- * CLK_PPMULCD0 [5]
- * Gating all clocks for FIMD0
- */
- setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- * MDNIE0_RATIO [7:4]
- * MDNIE_PWM0_RATIO [11:8]
- * MDNIE_PWM_PRE_RATIO [15:12]
- * MIPI0_RATIO [19:16]
- * MIPI0_PRE_RATIO [23:20]
- * set fimd ratio
- */
- clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
-}
-
-void exynos5_set_lcd_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- /*
- * CLK_GATE_BLOCK
- * CLK_CAM [0]
- * CLK_TV [1]
- * CLK_MFC [2]
- * CLK_G3D [3]
- * CLK_LCD0 [4]
- * CLK_LCD1 [5]
- * CLK_GPS [7]
- */
- setbits_le32(&clk->gate_block, 1 << 4);
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- * MDNIE0_SEL [7:4]
- * MDNIE_PWM0_SEL [8:11]
- * MIPI0_SEL [12:15]
- * set lcd0 src clock 0x6: SCLK_MPLL
- */
- clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
-
- /*
- * CLK_GATE_IP_LCD0
- * CLK_FIMD0 [0]
- * CLK_MIE0 [1]
- * CLK_MDNIE0 [2]
- * CLK_DSIM0 [3]
- * CLK_SMMUFIMD0 [4]
- * CLK_PPMULCD0 [5]
- * Gating all clocks for FIMD0
- */
- setbits_le32(&clk->gate_ip_disp1, 1 << 0);
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- * MDNIE0_RATIO [7:4]
- * MDNIE_PWM0_RATIO [11:8]
- * MDNIE_PWM_PRE_RATIO [15:12]
- * MIPI0_RATIO [19:16]
- * MIPI0_PRE_RATIO [23:20]
- * set fimd ratio
- */
- clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
-}
-
-void exynos5420_set_lcd_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned int cfg;
-
- /*
- * CLK_SRC_DISP10
- * FIMD1_SEL [4]
- * 0: SCLK_RPLL
- * 1: SCLK_SPLL
- */
- cfg = readl(&clk->src_disp10);
- cfg &= ~(0x1 << 4);
- cfg |= (0 << 4);
- writel(cfg, &clk->src_disp10);
-
- /*
- * CLK_DIV_DISP10
- * FIMD1_RATIO [3:0]
- */
- cfg = readl(&clk->div_disp10);
- cfg &= ~(0xf << 0);
- cfg |= (0 << 0);
- writel(cfg, &clk->div_disp10);
-}
-
-void exynos4_set_mipi_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- * MDNIE0_SEL [7:4]
- * MDNIE_PWM0_SEL [8:11]
- * MIPI0_SEL [12:15]
- * set mipi0 src clock 0x6: SCLK_MPLL
- */
- clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
-
- /*
- * CLK_SRC_MASK_LCD0
- * FIMD0_MASK [0]
- * MDNIE0_MASK [4]
- * MDNIE_PWM0_MASK [8]
- * MIPI0_MASK [12]
- * set src mask mipi0 0x1: Unmask
- */
- setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
-
- /*
- * CLK_GATE_IP_LCD0
- * CLK_FIMD0 [0]
- * CLK_MIE0 [1]
- * CLK_MDNIE0 [2]
- * CLK_DSIM0 [3]
- * CLK_SMMUFIMD0 [4]
- * CLK_PPMULCD0 [5]
- * Gating all clocks for MIPI0
- */
- setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- * MDNIE0_RATIO [7:4]
- * MDNIE_PWM0_RATIO [11:8]
- * MDNIE_PWM_PRE_RATIO [15:12]
- * MIPI0_RATIO [19:16]
- * MIPI0_PRE_RATIO [23:20]
- * set mipi ratio
- */
- clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
-}
-
-/*
- * I2C
- *
- * exynos5: obtaining the I2C clock
- */
-static unsigned long exynos5_get_i2c_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long aclk_66, aclk_66_pre, sclk;
- unsigned int ratio;
-
- sclk = get_pll_clk(MPLL);
-
- ratio = (readl(&clk->div_top1)) >> 24;
- ratio &= 0x7;
- aclk_66_pre = sclk / (ratio + 1);
- ratio = readl(&clk->div_top0);
- ratio &= 0x7;
- aclk_66 = aclk_66_pre / (ratio + 1);
- return aclk_66;
-}
-
-int exynos5_set_epll_clk(unsigned long rate)
-{
- unsigned int epll_con, epll_con_k;
- unsigned int i;
- unsigned int lockcnt;
- unsigned int start;
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- epll_con = readl(&clk->epll_con0);
- epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
- EPLL_CON0_LOCK_DET_EN_SHIFT) |
- EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
- EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
- EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
-
- for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
- if (exynos5_epll_div[i].freq_out == rate)
- break;
- }
-
- if (i == ARRAY_SIZE(exynos5_epll_div))
- return -1;
-
- epll_con_k = exynos5_epll_div[i].k_dsm << 0;
- epll_con |= exynos5_epll_div[i].en_lock_det <<
- EPLL_CON0_LOCK_DET_EN_SHIFT;
- epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
- epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
- epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
-
- /*
- * Required period ( in cycles) to genarate a stable clock output.
- * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
- * frequency input (as per spec)
- */
- lockcnt = 3000 * exynos5_epll_div[i].p_div;
-
- writel(lockcnt, &clk->epll_lock);
- writel(epll_con, &clk->epll_con0);
- writel(epll_con_k, &clk->epll_con1);
-
- start = get_timer(0);
-
- while (!(readl(&clk->epll_con0) &
- (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
- if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
- debug("%s: Timeout waiting for EPLL lock\n", __func__);
- return -1;
- }
- }
- return 0;
-}
-
-int exynos5_set_i2s_clk_source(unsigned int i2s_id)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
-
- if (i2s_id == 0) {
- setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
- clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
- (CLK_SRC_SCLK_EPLL));
- setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
- } else if (i2s_id == 1) {
- clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
- (CLK_SRC_SCLK_EPLL));
- } else {
- return -1;
- }
- return 0;
-}
-
-int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
- unsigned int dst_frq,
- unsigned int i2s_id)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int div;
-
- if ((dst_frq == 0) || (src_frq == 0)) {
- debug("%s: Invalid requency input for prescaler\n", __func__);
- debug("src frq = %d des frq = %d ", src_frq, dst_frq);
- return -1;
- }
-
- div = (src_frq / dst_frq);
- if (i2s_id == 0) {
- if (div > AUDIO_0_RATIO_MASK) {
- debug("%s: Frequency ratio is out of range\n",
- __func__);
- debug("src frq = %d des frq = %d ", src_frq, dst_frq);
- return -1;
- }
- clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
- (div & AUDIO_0_RATIO_MASK));
- } else if(i2s_id == 1) {
- if (div > AUDIO_1_RATIO_MASK) {
- debug("%s: Frequency ratio is out of range\n",
- __func__);
- debug("src frq = %d des frq = %d ", src_frq, dst_frq);
- return -1;
- }
- clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
- (div & AUDIO_1_RATIO_MASK));
- } else {
- return -1;
- }
- return 0;
-}
-
-/**
- * Linearly searches for the most accurate main and fine stage clock scalars
- * (divisors) for a specified target frequency and scalar bit sizes by checking
- * all multiples of main_scalar_bits values. Will always return scalars up to or
- * slower than target.
- *
- * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
- * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
- * @param input_freq Clock frequency to be scaled in Hz
- * @param target_freq Desired clock frequency in Hz
- * @param best_fine_scalar Pointer to store the fine stage divisor
- *
- * @return best_main_scalar Main scalar for desired frequency or -1 if none
- * found
- */
-static int clock_calc_best_scalar(unsigned int main_scaler_bits,
- unsigned int fine_scalar_bits, unsigned int input_rate,
- unsigned int target_rate, unsigned int *best_fine_scalar)
-{
- int i;
- int best_main_scalar = -1;
- unsigned int best_error = target_rate;
- const unsigned int cap = (1 << fine_scalar_bits) - 1;
- const unsigned int loops = 1 << main_scaler_bits;
-
- debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
- target_rate, cap);
-
- assert(best_fine_scalar != NULL);
- assert(main_scaler_bits <= fine_scalar_bits);
-
- *best_fine_scalar = 1;
-
- if (input_rate == 0 || target_rate == 0)
- return -1;
-
- if (target_rate >= input_rate)
- return 1;
-
- for (i = 1; i <= loops; i++) {
- const unsigned int effective_div =
- max(min(input_rate / i / target_rate, cap), 1U);
- const unsigned int effective_rate = input_rate / i /
- effective_div;
- const int error = target_rate - effective_rate;
-
- debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
- effective_rate, error);
-
- if (error >= 0 && error <= best_error) {
- best_error = error;
- best_main_scalar = i;
- *best_fine_scalar = effective_div;
- }
- }
-
- return best_main_scalar;
-}
-
-static int exynos5_set_spi_clk(enum periph_id periph_id,
- unsigned int rate)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- int main;
- unsigned int fine;
- unsigned shift, pre_shift;
- unsigned mask = 0xff;
- u32 *reg;
-
- main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
- if (main < 0) {
- debug("%s: Cannot set clock rate for periph %d",
- __func__, periph_id);
- return -1;
- }
- main = main - 1;
- fine = fine - 1;
-
- switch (periph_id) {
- case PERIPH_ID_SPI0:
- reg = &clk->div_peric1;
- shift = 0;
- pre_shift = 8;
- break;
- case PERIPH_ID_SPI1:
- reg = &clk->div_peric1;
- shift = 16;
- pre_shift = 24;
- break;
- case PERIPH_ID_SPI2:
- reg = &clk->div_peric2;
- shift = 0;
- pre_shift = 8;
- break;
- case PERIPH_ID_SPI3:
- reg = &clk->sclk_div_isp;
- shift = 0;
- pre_shift = 4;
- break;
- case PERIPH_ID_SPI4:
- reg = &clk->sclk_div_isp;
- shift = 12;
- pre_shift = 16;
- break;
- default:
- debug("%s: Unsupported peripheral ID %d\n", __func__,
- periph_id);
- return -1;
- }
- clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
- clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
-
- return 0;
-}
-
-static int exynos5420_set_spi_clk(enum periph_id periph_id,
- unsigned int rate)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- int main;
- unsigned int fine;
- unsigned shift, pre_shift;
- unsigned div_mask = 0xf, pre_div_mask = 0xff;
- u32 *reg;
- u32 *pre_reg;
-
- main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
- if (main < 0) {
- debug("%s: Cannot set clock rate for periph %d",
- __func__, periph_id);
- return -1;
- }
- main = main - 1;
- fine = fine - 1;
-
- switch (periph_id) {
- case PERIPH_ID_SPI0:
- reg = &clk->div_peric1;
- shift = 20;
- pre_reg = &clk->div_peric4;
- pre_shift = 8;
- break;
- case PERIPH_ID_SPI1:
- reg = &clk->div_peric1;
- shift = 24;
- pre_reg = &clk->div_peric4;
- pre_shift = 16;
- break;
- case PERIPH_ID_SPI2:
- reg = &clk->div_peric1;
- shift = 28;
- pre_reg = &clk->div_peric4;
- pre_shift = 24;
- break;
- case PERIPH_ID_SPI3:
- reg = &clk->div_isp1;
- shift = 16;
- pre_reg = &clk->div_isp1;
- pre_shift = 0;
- break;
- case PERIPH_ID_SPI4:
- reg = &clk->div_isp1;
- shift = 20;
- pre_reg = &clk->div_isp1;
- pre_shift = 8;
- break;
- default:
- debug("%s: Unsupported peripheral ID %d\n", __func__,
- periph_id);
- return -1;
- }
-
- clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
- clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
- (fine & pre_div_mask) << pre_shift);
-
- return 0;
-}
-
-static unsigned long exynos4_get_i2c_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long sclk, aclk_100;
- unsigned int ratio;
-
- sclk = get_pll_clk(APLL);
-
- ratio = (readl(&clk->div_top)) >> 4;
- ratio &= 0xf;
- aclk_100 = sclk / (ratio + 1);
- return aclk_100;
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pll_clk(pllreg);
- return exynos5_get_pll_clk(pllreg);
- } else {
- if (proid_is_exynos4412())
- return exynos4x12_get_pll_clk(pllreg);
- return exynos4_get_pll_clk(pllreg);
- }
-}
-
-unsigned long get_arm_clk(void)
-{
- if (cpu_is_exynos5())
- return exynos5_get_arm_clk();
- else {
- if (proid_is_exynos4412())
- return exynos4x12_get_arm_clk();
- return exynos4_get_arm_clk();
- }
-}
-
-unsigned long get_i2c_clk(void)
-{
- if (cpu_is_exynos5()) {
- return exynos5_get_i2c_clk();
- } else if (cpu_is_exynos4()) {
- return exynos4_get_i2c_clk();
- } else {
- debug("I2C clock is not set for this CPU\n");
- return 0;
- }
-}
-
-unsigned long get_pwm_clk(void)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pwm_clk();
- return clock_get_periph_rate(PERIPH_ID_PWM0);
- } else {
- if (proid_is_exynos4412())
- return exynos4x12_get_pwm_clk();
- return exynos4_get_pwm_clk();
- }
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_uart_clk(dev_index);
- return exynos5_get_uart_clk(dev_index);
- } else {
- if (proid_is_exynos4412())
- return exynos4x12_get_uart_clk(dev_index);
- return exynos4_get_uart_clk(dev_index);
- }
-}
-
-unsigned long get_mmc_clk(int dev_index)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_mmc_clk(dev_index);
- return exynos5_get_mmc_clk(dev_index);
- } else {
- return exynos4_get_mmc_clk(dev_index);
- }
-}
-
-void set_mmc_clk(int dev_index, unsigned int div)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- exynos5420_set_mmc_clk(dev_index, div);
- else
- exynos5_set_mmc_clk(dev_index, div);
- } else {
- exynos4_set_mmc_clk(dev_index, div);
- }
-}
-
-unsigned long get_lcd_clk(void)
-{
- if (cpu_is_exynos4())
- return exynos4_get_lcd_clk();
- else {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
- }
-}
-
-void set_lcd_clk(void)
-{
- if (cpu_is_exynos4())
- exynos4_set_lcd_clk();
- else {
- if (proid_is_exynos5250())
- exynos5_set_lcd_clk();
- else if (proid_is_exynos5420() || proid_is_exynos5800())
- exynos5420_set_lcd_clk();
- }
-}
-
-void set_mipi_clk(void)
-{
- if (cpu_is_exynos4())
- exynos4_set_mipi_clk();
-}
-
-int set_spi_clk(int periph_id, unsigned int rate)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_set_spi_clk(periph_id, rate);
- return exynos5_set_spi_clk(periph_id, rate);
- } else {
- return 0;
- }
-}
-
-int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
- unsigned int i2s_id)
-{
- if (cpu_is_exynos5())
- return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
- else
- return 0;
-}
-
-int set_i2s_clk_source(unsigned int i2s_id)
-{
- if (cpu_is_exynos5())
- return exynos5_set_i2s_clk_source(i2s_id);
- else
- return 0;
-}
-
-int set_epll_clk(unsigned long rate)
-{
- if (cpu_is_exynos5())
- return exynos5_set_epll_clk(rate);
- else
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h
deleted file mode 100644
index fce502f..0000000
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Clock initialization routines
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __EXYNOS_CLOCK_INIT_H
-#define __EXYNOS_CLOCK_INIT_H
-
-enum {
-#ifdef CONFIG_EXYNOS5420
- MEM_TIMINGS_MSR_COUNT = 5,
-#else
- MEM_TIMINGS_MSR_COUNT = 4,
-#endif
-};
-
-/* These are the ratio's for configuring ARM clock */
-struct arm_clk_ratios {
- unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
-
- unsigned apll_mdiv;
- unsigned apll_pdiv;
- unsigned apll_sdiv;
-
- unsigned arm2_ratio;
- unsigned apll_ratio;
- unsigned pclk_dbg_ratio;
- unsigned atb_ratio;
- unsigned periph_ratio;
- unsigned acp_ratio;
- unsigned cpud_ratio;
- unsigned arm_ratio;
-};
-
-/* These are the memory timings for a particular memory type and speed */
-struct mem_timings {
- enum mem_manuf mem_manuf; /* Memory manufacturer */
- enum ddr_mode mem_type; /* Memory type */
- unsigned frequency_mhz; /* Frequency of memory in MHz */
-
- /* Here follow the timing parameters for the selected memory */
- unsigned apll_mdiv;
- unsigned apll_pdiv;
- unsigned apll_sdiv;
- unsigned mpll_mdiv;
- unsigned mpll_pdiv;
- unsigned mpll_sdiv;
- unsigned cpll_mdiv;
- unsigned cpll_pdiv;
- unsigned cpll_sdiv;
- unsigned gpll_mdiv;
- unsigned gpll_pdiv;
- unsigned gpll_sdiv;
- unsigned epll_mdiv;
- unsigned epll_pdiv;
- unsigned epll_sdiv;
- unsigned vpll_mdiv;
- unsigned vpll_pdiv;
- unsigned vpll_sdiv;
- unsigned bpll_mdiv;
- unsigned bpll_pdiv;
- unsigned bpll_sdiv;
- unsigned kpll_mdiv;
- unsigned kpll_pdiv;
- unsigned kpll_sdiv;
- unsigned dpll_mdiv;
- unsigned dpll_pdiv;
- unsigned dpll_sdiv;
- unsigned ipll_mdiv;
- unsigned ipll_pdiv;
- unsigned ipll_sdiv;
- unsigned spll_mdiv;
- unsigned spll_pdiv;
- unsigned spll_sdiv;
- unsigned rpll_mdiv;
- unsigned rpll_pdiv;
- unsigned rpll_sdiv;
- unsigned pclk_cdrex_ratio;
- unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
-
- unsigned timing_ref;
- unsigned timing_row;
- unsigned timing_data;
- unsigned timing_power;
-
- /* DQS, DQ, DEBUG offsets */
- unsigned phy0_dqs;
- unsigned phy1_dqs;
- unsigned phy0_dq;
- unsigned phy1_dq;
- unsigned phy0_tFS;
- unsigned phy1_tFS;
- unsigned phy0_pulld_dqs;
- unsigned phy1_pulld_dqs;
-
- unsigned lpddr3_ctrl_phy_reset;
- unsigned ctrl_start_point;
- unsigned ctrl_inc;
- unsigned ctrl_start;
- unsigned ctrl_dll_on;
- unsigned ctrl_ref;
-
- unsigned ctrl_force;
- unsigned ctrl_rdlat;
- unsigned ctrl_bstlen;
-
- unsigned fp_resync;
- unsigned iv_size;
- unsigned dfi_init_start;
- unsigned aref_en;
-
- unsigned rd_fetch;
-
- unsigned zq_mode_dds;
- unsigned zq_mode_term;
- unsigned zq_mode_noterm; /* 1 to allow termination disable */
-
- unsigned memcontrol;
- unsigned memconfig;
-
- unsigned membaseconfig0;
- unsigned membaseconfig1;
- unsigned prechconfig_tp_cnt;
- unsigned dpwrdn_cyc;
- unsigned dsref_cyc;
- unsigned concontrol;
- /* Channel and Chip Selection */
- uint8_t dmc_channels; /* number of memory channels */
- uint8_t chips_per_channel; /* number of chips per channel */
- uint8_t chips_to_configure; /* number of chips to configure */
- uint8_t send_zq_init; /* 1 to send this command */
- unsigned impedance; /* drive strength impedeance */
- uint8_t gate_leveling_enable; /* check gate leveling is enabled */
- uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
-};
-
-/**
- * Get the correct memory timings for our selected memory type and speed.
- *
- * This function can be called from SPL or the main U-Boot.
- *
- * @return pointer to the memory timings that we should use
- */
-struct mem_timings *clock_get_mem_timings(void);
-
-/*
- * Initialize clock for the device
- */
-void system_clock_init(void);
-
-/*
- * Set clock divisor value for booting from EMMC.
- */
-void emmc_boot_clk_div_set(void);
-#endif
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
deleted file mode 100644
index 3161090..0000000
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Clock Initialization for board based on EXYNOS4210
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include "common_setup.h"
-#include "exynos4_setup.h"
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-void system_clock_init(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
-
- sdelay(0x10000);
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
- writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
- writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
- writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
- writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
- writel(CLK_SRC_CAM_VAL, &clk->src_cam);
- writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
- writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
- writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
-
- sdelay(0x10000);
-
- writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
- writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
- writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
- writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
- writel(CLK_DIV_TOP_VAL, &clk->div_top);
- writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
- writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
- writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
- writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
- writel(CLK_DIV_CAM_VAL, &clk->div_cam);
- writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
- writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
- writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
-
- /* Set PLL locktime */
- writel(PLL_LOCKTIME, &clk->apll_lock);
- writel(PLL_LOCKTIME, &clk->mpll_lock);
- writel(PLL_LOCKTIME, &clk->epll_lock);
- writel(PLL_LOCKTIME, &clk->vpll_lock);
-
- writel(APLL_CON1_VAL, &clk->apll_con1);
- writel(APLL_CON0_VAL, &clk->apll_con0);
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- writel(MPLL_CON0_VAL, &clk->mpll_con0);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- writel(EPLL_CON0_VAL, &clk->epll_con0);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- writel(VPLL_CON0_VAL, &clk->vpll_con0);
-
- sdelay(0x30000);
-}
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
deleted file mode 100644
index 0aff3d0..0000000
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * Clock setup for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/dwmmc.h>
-
-#include "clock_init.h"
-#include "common_setup.h"
-#include "exynos5_setup.h"
-
-#define FSYS1_MMC0_DIV_MASK 0xff0f
-#define FSYS1_MMC0_DIV_VAL 0x0701
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct arm_clk_ratios arm_clk_ratios[] = {
-#ifdef CONFIG_EXYNOS5420
- {
- .arm_freq_mhz = 900,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x2,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x6,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x0,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }
-#else
- {
- .arm_freq_mhz = 600,
-
- .apll_mdiv = 0xc8,
- .apll_pdiv = 0x4,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x2,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x1,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 800,
-
- .apll_mdiv = 0x64,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x3,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1000,
-
- .apll_mdiv = 0x7d,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x4,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1200,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x5,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1400,
-
- .apll_mdiv = 0xaf,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1700,
-
- .apll_mdiv = 0x1a9,
- .apll_pdiv = 0x6,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }
-#endif
-};
-
-struct mem_timings mem_timings[] = {
-#ifdef CONFIG_EXYNOS5420
- {
- .mem_manuf = MEM_MANUF_SAMSUNG,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
-
- /* MPLL @800MHz*/
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x1,
- /* CPLL @666MHz */
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x1,
- /* EPLL @600MHz */
- .epll_mdiv = 0x64,
- .epll_pdiv = 0x2,
- .epll_sdiv = 0x1,
- /* VPLL @430MHz */
- .vpll_mdiv = 0xd7,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
- /* BPLL @800MHz */
- .bpll_mdiv = 0xc8,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x1,
- /* KPLL @600MHz */
- .kpll_mdiv = 0x190,
- .kpll_pdiv = 0x4,
- .kpll_sdiv = 0x2,
- /* DPLL @600MHz */
- .dpll_mdiv = 0x190,
- .dpll_pdiv = 0x4,
- .dpll_sdiv = 0x2,
- /* IPLL @370MHz */
- .ipll_mdiv = 0xb9,
- .ipll_pdiv = 0x3,
- .ipll_sdiv = 0x2,
- /* SPLL @400MHz */
- .spll_mdiv = 0xc8,
- .spll_pdiv = 0x3,
- .spll_sdiv = 0x2,
- /* RPLL @70.5Mhz */
- .rpll_mdiv = 0x5E,
- .rpll_pdiv = 0x2,
- .rpll_sdiv = 0x4,
-
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
- 0x00000c70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x6836650f,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a26,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x8,
- .phy1_tFS = 0x8,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x7,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 1,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_DISABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
- DMC_MEMCONFIGX_CHIP_COL_10 |
- DMC_MEMCONFIGX_CHIP_ROW_15 |
- DMC_MEMCONFIGX_CHIP_BANK_8,
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 1,
- .chips_per_channel = 1,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .gate_leveling_enable = 1,
- .read_leveling_enable = 0,
- }
-#else
- {
- .mem_manuf = MEM_MANUF_ELPIDA,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
-
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010042, 0x00000d70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x4,
- .phy1_tFS = 0x4,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x7,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 0,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_ENABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGX_CHIP_COL_10 |
- DMC_MEMCONFIGX_CHIP_ROW_15 |
- DMC_MEMCONFIGX_CHIP_BANK_8,
- .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
- .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 2,
- .chips_per_channel = 2,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .impedance = IMP_OUTPUT_DRV_30_OHM,
- .gate_leveling_enable = 0,
- }, {
- .mem_manuf = MEM_MANUF_SAMSUNG,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
-
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010000, 0x00000d70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x8,
- .phy1_tFS = 0x8,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x5,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 1,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_ENABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGX_CHIP_COL_10 |
- DMC_MEMCONFIGX_CHIP_ROW_15 |
- DMC_MEMCONFIGX_CHIP_BANK_8,
- .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
- .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 2,
- .chips_per_channel = 2,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .impedance = IMP_OUTPUT_DRV_40_OHM,
- .gate_leveling_enable = 1,
- }
-#endif
-};
-
-/**
- * Get the required memory type and speed (SPL version).
- *
- * In SPL we have no device tree, so we use the machine parameters
- *
- * @param mem_type Returns memory type
- * @param frequency_mhz Returns memory speed in MHz
- * @param arm_freq Returns ARM clock speed in MHz
- * @param mem_manuf Return Memory Manufacturer name
- */
-static void clock_get_mem_selection(enum ddr_mode *mem_type,
- unsigned *frequency_mhz, unsigned *arm_freq,
- enum mem_manuf *mem_manuf)
-{
- struct spl_machine_param *params;
-
- params = spl_get_machine_params();
- *mem_type = params->mem_type;
- *frequency_mhz = params->frequency_mhz;
- *arm_freq = params->arm_freq_mhz;
- *mem_manuf = params->mem_manuf;
-}
-
-/* Get the ratios for setting ARM clock */
-struct arm_clk_ratios *get_arm_ratios(void)
-{
- struct arm_clk_ratios *arm_ratio;
- enum ddr_mode mem_type;
- enum mem_manuf mem_manuf;
- unsigned frequency_mhz, arm_freq;
- int i;
-
- clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf);
-
- for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
- i++, arm_ratio++) {
- if (arm_ratio->arm_freq_mhz == arm_freq)
- return arm_ratio;
- }
-
- /* will hang if failed to find clock ratio */
- while (1)
- ;
-
- return NULL;
-}
-
-struct mem_timings *clock_get_mem_timings(void)
-{
- struct mem_timings *mem;
- enum ddr_mode mem_type;
- enum mem_manuf mem_manuf;
- unsigned frequency_mhz, arm_freq;
- int i;
-
- clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf);
- for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
- i++, mem++) {
- if (mem->mem_type == mem_type &&
- mem->frequency_mhz == frequency_mhz &&
- mem->mem_manuf == mem_manuf)
- return mem;
- }
-
- /* will hang if failed to find memory timings */
- while (1)
- ;
-
- return NULL;
-}
-
-static void exynos5250_system_clock_init(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- struct mem_timings *mem;
- struct arm_clk_ratios *arm_clk_ratio;
- u32 val, tmp;
-
- mem = clock_get_mem_timings();
- arm_clk_ratio = get_arm_ratios();
-
- clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | MUX_APLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_core1);
- } while ((val | MUX_MPLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
- tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
- | MUX_GPLL_SEL_MASK;
- do {
- val = readl(&clk->mux_stat_top2);
- } while ((val | tmp) != val);
-
- clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cdrex);
- } while ((val | MUX_BPLL_SEL_MASK) != val);
-
- /* PLL locktime */
- writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
- writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
- writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
- writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
- writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
- writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
- writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
-
- writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
-
- writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | HPM_SEL_SCLK_MPLL) != val);
-
- val = arm_clk_ratio->arm2_ratio << 28
- | arm_clk_ratio->apll_ratio << 24
- | arm_clk_ratio->pclk_dbg_ratio << 20
- | arm_clk_ratio->atb_ratio << 16
- | arm_clk_ratio->periph_ratio << 12
- | arm_clk_ratio->acp_ratio << 8
- | arm_clk_ratio->cpud_ratio << 4
- | arm_clk_ratio->arm_ratio;
- writel(val, &clk->div_cpu0);
- do {
- val = readl(&clk->div_stat_cpu0);
- } while (0 != val);
-
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- do {
- val = readl(&clk->div_stat_cpu1);
- } while (0 != val);
-
- /* Set APLL */
- writel(APLL_CON1_VAL, &clk->apll_con1);
- val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
- arm_clk_ratio->apll_sdiv);
- writel(val, &clk->apll_con0);
- while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
- ;
-
- /* Set MPLL */
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
- writel(val, &clk->mpll_con0);
- while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set BPLL */
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
- writel(val, &clk->bpll_con0);
- while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
- writel(val, &clk->cpll_con0);
- while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set GPLL */
- writel(GPLL_CON1_VAL, &clk->gpll_con1);
- val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
- writel(val, &clk->gpll_con0);
- while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set EPLL */
- writel(EPLL_CON2_VAL, &clk->epll_con2);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
- writel(val, &clk->epll_con0);
- while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set VPLL */
- writel(VPLL_CON2_VAL, &clk->vpll_con2);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
- writel(val, &clk->vpll_con0);
- while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
- ;
-
- writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
- writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
- while (readl(&clk->div_stat_core0) != 0)
- ;
-
- writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
- while (readl(&clk->div_stat_core1) != 0)
- ;
-
- writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
- while (readl(&clk->div_stat_sysrgt) != 0)
- ;
-
- writel(CLK_DIV_ACP_VAL, &clk->div_acp);
- while (readl(&clk->div_stat_acp) != 0)
- ;
-
- writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
- while (readl(&clk->div_stat_syslft) != 0)
- ;
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(TOP2_VAL, &clk->src_top2);
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
-
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
- while (readl(&clk->div_stat_top0))
- ;
-
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
- while (readl(&clk->div_stat_top1))
- ;
-
- writel(CLK_SRC_LEX_VAL, &clk->src_lex);
- while (1) {
- val = readl(&clk->mux_stat_lex);
- if (val == (val | 1))
- break;
- }
-
- writel(CLK_DIV_LEX_VAL, &clk->div_lex);
- while (readl(&clk->div_stat_lex))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
- while (readl(&clk->div_stat_r1x))
- ;
-
- writel(CLK_REG_DISABLE, &clk->src_cdrex);
-
- writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
- while (readl(&clk->div_stat_cdrex))
- ;
-
- val = readl(&clk->src_cpu);
- val |= CLK_SRC_CPU_VAL;
- writel(val, &clk->src_cpu);
-
- val = readl(&clk->src_top2);
- val |= CLK_SRC_TOP2_VAL;
- writel(val, &clk->src_top2);
-
- val = readl(&clk->src_core1);
- val |= CLK_SRC_CORE1_VAL;
- writel(val, &clk->src_core1);
-
- writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
- while (readl(&clk->div_stat_fsys0))
- ;
-
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
-
- writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
- writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
- writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
- writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
-
- writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
- writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
- writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
-
- /* FIMD1 SRC CLK SELECTION */
- writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
-
- val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
- | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
- | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
- | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
- writel(val, &clk->div_fsys2);
-}
-
-static void exynos5420_system_clock_init(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- struct mem_timings *mem;
- struct arm_clk_ratios *arm_clk_ratio;
- u32 val;
-
- mem = clock_get_mem_timings();
- arm_clk_ratio = get_arm_ratios();
-
- /* PLL locktime */
- writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
- writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
- writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
- writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
- writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
- writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
- writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
- writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
- writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
- writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
- writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
-
- setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
-
- writel(0, &clk->src_top6);
-
- writel(0, &clk->src_cdrex);
- writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
- writel(HPM_RATIO, &clk->div_cpu1);
- writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
-
- /* switch A15 clock source to OSC clock before changing APLL */
- clrbits_le32(&clk->src_cpu, APLL_FOUT);
-
- /* Set APLL */
- writel(APLL_CON1_VAL, &clk->apll_con1);
- val = set_pll(arm_clk_ratio->apll_mdiv,
- arm_clk_ratio->apll_pdiv,
- arm_clk_ratio->apll_sdiv);
- writel(val, &clk->apll_con0);
- while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* now it is safe to switch to APLL */
- setbits_le32(&clk->src_cpu, APLL_FOUT);
-
- writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
- writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
-
- /* switch A7 clock source to OSC clock before changing KPLL */
- clrbits_le32(&clk->src_kfc, KPLL_FOUT);
-
- /* Set KPLL*/
- writel(KPLL_CON1_VAL, &clk->kpll_con1);
- val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
- writel(val, &clk->kpll_con0);
- while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* now it is safe to switch to KPLL */
- setbits_le32(&clk->src_kfc, KPLL_FOUT);
-
- /* Set MPLL */
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
- writel(val, &clk->mpll_con0);
- while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set DPLL */
- writel(DPLL_CON1_VAL, &clk->dpll_con1);
- val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
- writel(val, &clk->dpll_con0);
- while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set EPLL */
- writel(EPLL_CON2_VAL, &clk->epll_con2);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
- writel(val, &clk->epll_con0);
- while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
- writel(val, &clk->cpll_con0);
- while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set IPLL */
- writel(IPLL_CON1_VAL, &clk->ipll_con1);
- val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
- writel(val, &clk->ipll_con0);
- while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set VPLL */
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
- writel(val, &clk->vpll_con0);
- while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set BPLL */
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
- writel(val, &clk->bpll_con0);
- while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set SPLL */
- writel(SPLL_CON1_VAL, &clk->spll_con1);
- val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
- writel(val, &clk->spll_con0);
- while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set RPLL */
- writel(RPLL_CON2_VAL, &clk->rpll_con2);
- writel(RPLL_CON1_VAL, &clk->rpll_con1);
- val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
- writel(val, &clk->rpll_con0);
- while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
- ;
-
- writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
- writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
- writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
-
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
- writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
-
- writel(0, &clk->src_top10);
- writel(0, &clk->src_top11);
- writel(0, &clk->src_top12);
-
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
- writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
- writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
-
- /* DISP1 BLK CLK SELECTION */
- writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
- writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
-
- /* AUDIO BLK */
- writel(AUDIO0_SEL_EPLL, &clk->src_mau);
- writel(DIV_MAU_VAL, &clk->div_mau);
-
- /* FSYS */
- writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
- writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
- writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
-
- writel(CLK_SRC_ISP_VAL, &clk->src_isp);
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
-
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
- writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
-
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
- writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
- writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
- writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
- writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
-
- writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
-
- writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
- writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
- writel(CLK_DIV_G2D, &clk->div_g2d);
-
- writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
- writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
- writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
-}
-
-void system_clock_init(void)
-{
- if (proid_is_exynos5420() || proid_is_exynos5800())
- exynos5420_system_clock_init();
- else
- exynos5250_system_clock_init();
-}
-
-void clock_init_dp_clock(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- /* DP clock enable */
- setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
-
- /* We run DP at 267 Mhz */
- setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
-}
-
-/*
- * Set clock divisor value for booting from EMMC.
- * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
- */
-void emmc_boot_clk_div_set(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int div_mmc;
-
- div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
- div_mmc |= FSYS1_MMC0_DIV_VAL;
- writel(div_mmc, (unsigned int) &clk->div_fsys1);
-}
diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h
deleted file mode 100644
index e6318c0..0000000
--- a/arch/arm/cpu/armv7/exynos/common_setup.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Common APIs for EXYNOS based board
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#define DMC_OFFSET 0x10000
-
-/*
- * Memory initialization
- *
- * @param reset Reset PHY during initialization.
- */
-void mem_ctrl_init(int reset);
-
- /* System Clock initialization */
-void system_clock_init(void);
-
-/*
- * Init subsystems according to the reset status
- *
- * @return 0 for a normal boot, non-zero for a resume
- */
-int do_lowlevel_init(void);
-
-void sdelay(unsigned long);
diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk
deleted file mode 100644
index ee0d2da..0000000
--- a/arch/arm/cpu/armv7/exynos/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-SPL_OBJCFLAGS += -j .machine_param
diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
deleted file mode 100644
index 9b6ee69..0000000
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Mem setup common file for different types of DDR present on Exynos boards.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/spl.h>
-
-#include "clock_init.h"
-#include "common_setup.h"
-#include "exynos5_setup.h"
-
-#define ZQ_INIT_TIMEOUT 10000
-
-int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
- uint32_t *phy1_con16, uint32_t *phy0_con17,
- uint32_t *phy1_con17)
-{
- unsigned long val = 0;
- int i;
-
- /*
- * ZQ Calibration:
- * Select Driver Strength,
- * long calibration for manual calibration
- */
- val = PHY_CON16_RESET_VAL;
- val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
- val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
- val |= ZQ_CLK_DIV_EN;
- writel(val, phy0_con16);
- writel(val, phy1_con16);
-
- /* Disable termination */
- if (mem->zq_mode_noterm)
- val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
- writel(val, phy0_con16);
- writel(val, phy1_con16);
-
- /* ZQ_MANUAL_START: Enable */
- val |= ZQ_MANUAL_STR;
- writel(val, phy0_con16);
- writel(val, phy1_con16);
-
- /* ZQ_MANUAL_START: Disable */
- val &= ~ZQ_MANUAL_STR;
-
- /*
- * Since we are manaully calibrating the ZQ values,
- * we are looping for the ZQ_init to complete.
- */
- i = ZQ_INIT_TIMEOUT;
- while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
- i--;
- }
- if (!i)
- return -1;
- writel(val, phy0_con16);
-
- i = ZQ_INIT_TIMEOUT;
- while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
- i--;
- }
- if (!i)
- return -1;
- writel(val, phy1_con16);
-
- return 0;
-}
-
-void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
-{
- unsigned long val;
-
- if (mode == DDR_MODE_DDR3) {
- val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
- writel(val, phycontrol0);
- }
-
- /* Update DLL Information: Force DLL Resyncronization */
- val = readl(phycontrol0);
- val |= FP_RSYNC;
- writel(val, phycontrol0);
-
- /* Reset Force DLL Resyncronization */
- val = readl(phycontrol0);
- val &= ~FP_RSYNC;
- writel(val, phycontrol0);
-}
-
-void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
-{
- int channel, chip;
-
- for (channel = 0; channel < mem->dmc_channels; channel++) {
- unsigned long mask;
-
- mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- int i;
-
- mask |= chip << DIRECT_CMD_CHIP_SHIFT;
-
- /* Sending NOP command */
- writel(DIRECT_CMD_NOP | mask, directcmd);
-
- /*
- * TODO(alim.akhtar@samsung.com): Do we need these
- * delays? This one and the next were not there for
- * DDR3.
- */
- sdelay(0x10000);
-
- /* Sending EMRS/MRS commands */
- for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
- writel(mem->direct_cmd_msr[i] | mask,
- directcmd);
- sdelay(0x10000);
- }
-
- if (mem->send_zq_init) {
- /* Sending ZQINIT command */
- writel(DIRECT_CMD_ZQINIT | mask,
- directcmd);
-
- sdelay(10000);
- }
- }
- }
-}
-
-void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
-{
- int channel, chip;
-
- for (channel = 0; channel < mem->dmc_channels; channel++) {
- unsigned long mask;
-
- mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
- for (chip = 0; chip < mem->chips_per_channel; chip++) {
- mask |= chip << DIRECT_CMD_CHIP_SHIFT;
-
- /* PALL (all banks precharge) CMD */
- writel(DIRECT_CMD_PALL | mask, directcmd);
- sdelay(0x10000);
- }
- }
-}
-
-void mem_ctrl_init(int reset)
-{
- struct spl_machine_param *param = spl_get_machine_params();
- struct mem_timings *mem;
- int ret;
-
- mem = clock_get_mem_timings();
-
- /* If there are any other memory variant, add their init call below */
- if (param->mem_type == DDR_MODE_DDR3) {
- ret = ddr3_mem_ctrl_init(mem, reset);
- if (ret) {
- /* will hang if failed to init memory control */
- while (1)
- ;
- }
- } else {
- /* will hang if unknow memory type */
- while (1)
- ;
- }
-}
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
deleted file mode 100644
index 7c0b12a..0000000
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ /dev/null
@@ -1,866 +0,0 @@
-/*
- * DDR3 mem setup file for board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/power.h>
-#include "common_setup.h"
-#include "exynos5_setup.h"
-#include "clock_init.h"
-
-#define TIMEOUT_US 10000
-#define NUM_BYTE_LANES 4
-#define DEFAULT_DQS 8
-#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
- || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
-
-#ifdef CONFIG_EXYNOS5250
-static void reset_phy_ctrl(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
- writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
-}
-
-int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
-{
- unsigned int val;
- struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
- struct exynos5_dmc *dmc;
- int i;
-
- phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
- phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
- + DMC_OFFSET);
- dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
-
- if (reset)
- reset_phy_ctrl();
-
- /* Set Impedance Output Driver */
- val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
- (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
- (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
- (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
- writel(val, &phy0_ctrl->phy_con39);
- writel(val, &phy1_ctrl->phy_con39);
-
- /* Set Read Latency and Burst Length for PHY0 and PHY1 */
- val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
- (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
- writel(val, &phy0_ctrl->phy_con42);
- writel(val, &phy1_ctrl->phy_con42);
-
- /* ZQ Calibration */
- if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
- &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
- return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
-
- /* DQ Signal */
- writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
- writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
-
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
- | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
- &dmc->concontrol);
-
- update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
-
- /* DQS Signal */
- writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
- writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
-
- writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
- writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
-
- writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
- writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
-
- val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- /* Start DLL locking */
- writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
- &phy0_ctrl->phy_con12);
- writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
- &phy1_ctrl->phy_con12);
-
- update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
-
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &dmc->concontrol);
-
- /* Memory Channel Inteleaving Size */
- writel(mem->iv_size, &dmc->ivcontrol);
-
- writel(mem->memconfig, &dmc->memconfig0);
- writel(mem->memconfig, &dmc->memconfig1);
- writel(mem->membaseconfig0, &dmc->membaseconfig0);
- writel(mem->membaseconfig1, &dmc->membaseconfig1);
-
- /* Precharge Configuration */
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &dmc->prechconfig);
-
- /* Power Down mode Configuration */
- writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
- mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
- &dmc->pwrdnconfig);
-
- /* TimingRow, TimingData, TimingPower and Timingaref
- * values as per Memory AC parameters
- */
- writel(mem->timing_ref, &dmc->timingref);
- writel(mem->timing_row, &dmc->timingrow);
- writel(mem->timing_data, &dmc->timingdata);
- writel(mem->timing_power, &dmc->timingpower);
-
- /* Send PALL command */
- dmc_config_prech(mem, &dmc->directcmd);
-
- /* Send NOP, MRS and ZQINIT commands */
- dmc_config_mrs(mem, &dmc->directcmd);
-
- if (mem->gate_leveling_enable) {
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- val |= BYTE_RDLVL_EN;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = (mem->ctrl_start_point <<
- PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
- (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- val |= RDLVL_GATE_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- val |= BYTE_RDLVL_EN;
- val |= CTRL_SHGATE;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = PHY_CON1_RESET_VAL;
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy0_ctrl->phy_con1);
- writel(val, &phy1_ctrl->phy_con1);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
- i = TIMEOUT_US;
- while ((readl(&dmc->phystatus) &
- (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
- (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
-
- writel(0, &phy0_ctrl->phy_con14);
- writel(0, &phy1_ctrl->phy_con14);
-
- val = (mem->ctrl_start_point <<
- PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
- (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
- (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
- }
-
- /* Send PALL command */
- dmc_config_prech(mem, &dmc->directcmd);
-
- writel(mem->memcontrol, &dmc->memcontrol);
-
- /* Set DMC Concontrol and enable auto-refresh counter */
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
- | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_EXYNOS5420
-/**
- * RAM address to use in the test.
- *
- * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
- * interleaves channels every 128 bytes). This will allow us to evaluate all of
- * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
- * chip per channel (4GB) system. We can't test the 2nd chip since we need to
- * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't
- * critical because the 1st and 2nd chip have very similar timings (they'd
- * better have similar timings, since there's only a single adjustment that is
- * shared by both chips).
- */
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
-
-/* Test pattern with which RAM will be tested */
-static const unsigned int test_pattern[] = {
- 0x5a5a5a5a,
- 0xa5a5a5a5,
- 0xf0f0f0f0,
- 0x0f0f0f0f,
-};
-
-/**
- * This function is a test vector for sw read leveling,
- * it compares the read data with the written data.
- *
- * @param ch DMC channel number
- * @param byte_lane which DQS byte offset,
- * possible values are 0,1,2,3
- * @return TRUE if memory was good, FALSE if not.
- */
-static bool dmc_valid_window_test_vector(int ch, int byte_lane)
-{
- unsigned int read_data;
- unsigned int mask;
- int i;
-
- mask = 0xFF << (8 * byte_lane);
-
- for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
- read_data = readl(test_addr + i * 4 + ch * 0x80);
- if ((read_data & mask) != (test_pattern[i] & mask))
- return false;
- }
-
- return true;
-}
-
-/**
- * This function returns current read offset value.
- *
- * @param phy_ctrl pointer to the current phy controller
- */
-static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
- *phy_ctrl)
-{
- return readl(&phy_ctrl->phy_con4);
-}
-
-/**
- * This function performs resync, so that slave DLL is updated.
- *
- * @param phy_ctrl pointer to the current phy controller
- */
-static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
-{
- setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
- clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
-}
-
-/**
- * This function sets read offset value register with 'offset'.
- *
- * ...we also call call ddr_phy_set_do_resync().
- *
- * @param phy_ctrl pointer to the current phy controller
- * @param offset offset to read DQS
- */
-static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
- unsigned int offset)
-{
- writel(offset, &phy_ctrl->phy_con4);
- ddr_phy_set_do_resync(phy_ctrl);
-}
-
-/**
- * Convert a 2s complement byte to a byte with a sign bit.
- *
- * NOTE: you shouldn't use normal math on the number returned by this function.
- * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted
- * to do math and get the average of 10 and -10 (should be 0):
- * 0x8a + 0xa = 0x94 (-108)
- * 0x94 / 2 = 0xca (-54)
- * ...and 0xca = sign bit plus 0x4a, or -74
- *
- * Also note that you lose the ability to represent -128 since there are two
- * representations of 0.
- *
- * @param b The byte to convert in two's complement.
- * @return The 7-bit value + sign bit.
- */
-
-unsigned char make_signed_byte(signed char b)
-{
- if (b < 0)
- return 0x80 | -b;
- else
- return b;
-}
-
-/**
- * Test various shifts starting at 'start' and going to 'end'.
- *
- * For each byte lane, we'll walk through shift starting at 'start' and going
- * to 'end' (inclusive). When we are finally able to read the test pattern
- * we'll store the value in the results array.
- *
- * @param phy_ctrl pointer to the current phy controller
- * @param ch channel number
- * @param start the start shift. -127 to 127
- * @param end the end shift. -127 to 127
- * @param results we'll store results for each byte lane.
- */
-
-void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
- int start, int end, int results[NUM_BYTE_LANES])
-{
- int incr = (start < end) ? 1 : -1;
- int byte_lane;
-
- for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
- int shift;
-
- dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
- results[byte_lane] = DEFAULT_DQS;
-
- for (shift = start; shift != (end + incr); shift += incr) {
- unsigned int byte_offsetr;
- unsigned int offsetr;
-
- byte_offsetr = make_signed_byte(shift);
-
- offsetr = dmc_get_read_offset_value(phy_ctrl);
- offsetr &= ~(0xFF << (8 * byte_lane));
- offsetr |= (byte_offsetr << (8 * byte_lane));
- dmc_set_read_offset_value(phy_ctrl, offsetr);
-
- if (dmc_valid_window_test_vector(ch, byte_lane)) {
- results[byte_lane] = shift;
- break;
- }
- }
- }
-}
-
-/**
- * This function performs SW read leveling to compensate DQ-DQS skew at
- * receiver it first finds the optimal read offset value on each DQS
- * then applies the value to PHY.
- *
- * Read offset value has its min margin and max margin. If read offset
- * value exceeds its min or max margin, read data will have corruption.
- * To avoid this we are doing sw read leveling.
- *
- * SW read leveling is:
- * 1> Finding offset value's left_limit and right_limit
- * 2> and calculate its center value
- * 3> finally programs that center value to PHY
- * 4> then PHY gets its optimal offset value.
- *
- * @param phy_ctrl pointer to the current phy controller
- * @param ch channel number
- * @param coarse_lock_val The coarse lock value read from PHY_CON13.
- * (0 - 0x7f)
- */
-static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
- int ch, unsigned int coarse_lock_val)
-{
- unsigned int offsetr_cent;
- int byte_lane;
- int left_limit;
- int right_limit;
- int left[NUM_BYTE_LANES];
- int right[NUM_BYTE_LANES];
- int i;
-
- /* Fill the memory with test patterns */
- for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
- writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
-
- /* Figure out the limits we'll test with; keep -127 < limit < 127 */
- left_limit = DEFAULT_DQS - coarse_lock_val;
- right_limit = DEFAULT_DQS + coarse_lock_val;
- if (right_limit > 127)
- right_limit = 127;
-
- /* Fill in the location where reads were OK from left and right */
- test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
- test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
-
- /* Make a final value by taking the center between the left and right */
- offsetr_cent = 0;
- for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
- int temp_center;
- unsigned int vmwc;
-
- temp_center = (left[byte_lane] + right[byte_lane]) / 2;
- vmwc = make_signed_byte(temp_center);
- offsetr_cent |= vmwc << (8 * byte_lane);
- }
- dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
-}
-
-int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- struct exynos5420_power *power =
- (struct exynos5420_power *)samsung_get_base_power();
- struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
- struct exynos5420_dmc *drex0, *drex1;
- struct exynos5420_tzasc *tzasc0, *tzasc1;
- struct exynos5_power *pmu;
- uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
- uint32_t lock0_info, lock1_info;
- int chip;
- int i;
-
- phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
- phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
- + DMC_OFFSET);
- drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
- drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
- + DMC_OFFSET);
- tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
- tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
- + DMC_OFFSET);
- pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
-
- if (CONFIG_NR_DRAM_BANKS > 4) {
- /* Need both controllers. */
- mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
- mem->chips_per_channel = 2;
- mem->chips_to_configure = 2;
- } else {
- /* 2GB requires a single controller */
- mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
- }
-
- /* Enable PAUSE for DREX */
- setbits_le32(&clk->pause, ENABLE_BIT);
-
- /* Enable BYPASS mode */
- setbits_le32(&clk->bpll_con1, BYPASS_EN);
-
- writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
- do {
- val = readl(&clk->mux_stat_cdrex);
- val &= BPLL_SEL_MASK;
- } while (val != FOUTBPLL);
-
- clrbits_le32(&clk->bpll_con1, BYPASS_EN);
-
- /* Specify the DDR memory type as DDR3 */
- val = readl(&phy0_ctrl->phy_con0);
- val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- writel(val, &phy0_ctrl->phy_con0);
-
- val = readl(&phy1_ctrl->phy_con0);
- val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- writel(val, &phy1_ctrl->phy_con0);
-
- /* Set Read Latency and Burst Length for PHY0 and PHY1 */
- val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
- (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
- writel(val, &phy0_ctrl->phy_con42);
- writel(val, &phy1_ctrl->phy_con42);
-
- val = readl(&phy0_ctrl->phy_con26);
- val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
- val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
- writel(val, &phy0_ctrl->phy_con26);
-
- val = readl(&phy1_ctrl->phy_con26);
- val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
- val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
- writel(val, &phy1_ctrl->phy_con26);
-
- /*
- * Set Driver strength for CK, CKE, CS & CA to 0x7
- * Set Driver strength for Data Slice 0~3 to 0x7
- */
- val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
- (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
- val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
- (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
- writel(val, &phy0_ctrl->phy_con39);
- writel(val, &phy1_ctrl->phy_con39);
-
- /* ZQ Calibration */
- if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
- &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
- return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
-
- clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
- clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
-
- /* DQ Signal */
- val = readl(&phy0_ctrl->phy_con14);
- val |= mem->phy0_pulld_dqs;
- writel(val, &phy0_ctrl->phy_con14);
- val = readl(&phy1_ctrl->phy_con14);
- val |= mem->phy1_pulld_dqs;
- writel(val, &phy1_ctrl->phy_con14);
-
- val = MEM_TERM_EN | PHY_TERM_EN;
- writel(val, &drex0->phycontrol0);
- writel(val, &drex1->phycontrol0);
-
- writel(mem->concontrol |
- (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &drex0->concontrol);
- writel(mem->concontrol |
- (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &drex1->concontrol);
-
- do {
- val = readl(&drex0->phystatus);
- } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
- do {
- val = readl(&drex1->phystatus);
- } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
-
- clrbits_le32(&drex0->concontrol, DFI_INIT_START);
- clrbits_le32(&drex1->concontrol, DFI_INIT_START);
-
- update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
- update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
-
- /*
- * Set Base Address:
- * 0x2000_0000 ~ 0x5FFF_FFFF
- * 0x6000_0000 ~ 0x9FFF_FFFF
- */
- /* MEMBASECONFIG0 */
- val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
- DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig0);
- writel(val, &tzasc1->membaseconfig0);
-
- /* MEMBASECONFIG1 */
- val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
- DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig1);
- writel(val, &tzasc1->membaseconfig1);
-
- /*
- * Memory Channel Inteleaving Size
- * Ares Channel interleaving = 128 bytes
- */
- /* MEMCONFIG0/1 */
- writel(mem->memconfig, &tzasc0->memconfig0);
- writel(mem->memconfig, &tzasc1->memconfig0);
- writel(mem->memconfig, &tzasc0->memconfig1);
- writel(mem->memconfig, &tzasc1->memconfig1);
-
- /* Precharge Configuration */
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &drex0->prechconfig0);
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &drex1->prechconfig0);
-
- /*
- * TimingRow, TimingData, TimingPower and Timingaref
- * values as per Memory AC parameters
- */
- writel(mem->timing_ref, &drex0->timingref);
- writel(mem->timing_ref, &drex1->timingref);
- writel(mem->timing_row, &drex0->timingrow0);
- writel(mem->timing_row, &drex1->timingrow0);
- writel(mem->timing_data, &drex0->timingdata0);
- writel(mem->timing_data, &drex1->timingdata0);
- writel(mem->timing_power, &drex0->timingpower0);
- writel(mem->timing_power, &drex1->timingpower0);
-
- if (reset) {
- /*
- * Send NOP, MRS and ZQINIT commands
- * Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
- * corruption as DRAM content is lost after DRAM reset
- */
- dmc_config_mrs(mem, &drex0->directcmd);
- dmc_config_mrs(mem, &drex1->directcmd);
- }
-
- /*
- * Get PHY_CON13 from both phys. Gate CLKM around reading since
- * PHY_CON13 is glitchy when CLKM is running. We're paranoid and
- * wait until we get a "fine lock", though a coarse lock is probably
- * OK (we only use the coarse numbers below). We try to gate the
- * clock for as short a time as possible in case SDRAM is somehow
- * sensitive. sdelay(10) in the loop is arbitrary to make sure
- * there is some time for PHY_CON13 to get updated. In practice
- * no delay appears to be needed.
- */
- val = readl(&clk->gate_bus_cdrex);
- while (true) {
- writel(val & ~0x1, &clk->gate_bus_cdrex);
- lock0_info = readl(&phy0_ctrl->phy_con13);
- writel(val, &clk->gate_bus_cdrex);
-
- if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
- break;
-
- sdelay(10);
- }
- while (true) {
- writel(val & ~0x2, &clk->gate_bus_cdrex);
- lock1_info = readl(&phy1_ctrl->phy_con13);
- writel(val, &clk->gate_bus_cdrex);
-
- if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
- break;
-
- sdelay(10);
- }
-
- if (!reset) {
- /*
- * During Suspend-Resume & S/W-Reset, as soon as PMU releases
- * pad retention, CKE goes high. This causes memory contents
- * not to be retained during DRAM initialization. Therfore,
- * there is a new control register(0x100431e8[28]) which lets us
- * release pad retention and retain the memory content until the
- * initialization is complete.
- */
- writel(PAD_RETENTION_DRAM_COREBLK_VAL,
- &power->pad_retention_dram_coreblk_option);
- do {
- val = readl(&power->pad_retention_dram_status);
- } while (val != 0x1);
-
- /*
- * CKE PAD retention disables DRAM self-refresh mode.
- * Send auto refresh command for DRAM refresh.
- */
- for (i = 0; i < 128; i++) {
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- writel(DIRECT_CMD_REFA |
- (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(DIRECT_CMD_REFA |
- (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
- }
- }
- }
-
- if (mem->gate_leveling_enable) {
- writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
- writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
-
- setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
- setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = readl(&phy0_ctrl->phy_con1);
- val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
- writel(val, &phy0_ctrl->phy_con1);
-
- val = readl(&phy1_ctrl->phy_con1);
- val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
- writel(val, &phy1_ctrl->phy_con1);
-
- n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
- n_lock_r = readl(&phy0_ctrl->phy_con12);
- n_lock_r &= ~CTRL_DLL_ON;
- n_lock_r |= n_lock_w_phy0;
- writel(n_lock_r, &phy0_ctrl->phy_con12);
-
- n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
- n_lock_r = readl(&phy1_ctrl->phy_con12);
- n_lock_r &= ~CTRL_DLL_ON;
- n_lock_r |= n_lock_w_phy1;
- writel(n_lock_r, &phy1_ctrl->phy_con12);
-
- val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
- }
-
- setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
- setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
-
- setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
- setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
-
- val = readl(&phy0_ctrl->phy_con1);
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy0_ctrl->phy_con1);
-
- val = readl(&phy1_ctrl->phy_con1);
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy1_ctrl->phy_con1);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
- i = TIMEOUT_US;
- while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
- RDLVL_COMPLETE_CHO) && (i > 0)) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
- i = TIMEOUT_US;
- while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
- RDLVL_COMPLETE_CHO) && (i > 0)) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
-
- writel(0, &phy0_ctrl->phy_con14);
- writel(0, &phy1_ctrl->phy_con14);
-
- val = (0x3 << DIRECT_CMD_BANK_SHIFT);
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
- }
-
- /* Common Settings for Leveling */
- val = PHY_CON12_RESET_VAL;
- writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
- writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
-
- setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
- setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
- }
-
- /*
- * Do software read leveling
- *
- * Do this before we turn on auto refresh since the auto refresh can
- * be in conflict with the resync operation that's part of setting
- * read leveling.
- */
- if (!reset) {
- /* restore calibrated value after resume */
- dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
- dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
- } else {
- software_find_read_offset(phy0_ctrl, 0,
- CTRL_LOCK_COARSE(lock0_info));
- software_find_read_offset(phy1_ctrl, 1,
- CTRL_LOCK_COARSE(lock1_info));
- /* save calibrated value to restore after resume */
- writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
- writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
- }
-
- /* Send PALL command */
- dmc_config_prech(mem, &drex0->directcmd);
- dmc_config_prech(mem, &drex1->directcmd);
-
- writel(mem->memcontrol, &drex0->memcontrol);
- writel(mem->memcontrol, &drex1->memcontrol);
-
- /*
- * Set DMC Concontrol: Enable auto-refresh counter, provide
- * read data fetch cycles and enable DREX auto set powerdown
- * for input buffer of I/O in none read memory state.
- */
- writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
- DMC_CONCONTROL_IO_PD_CON(0x2),
- &drex0->concontrol);
- writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
- DMC_CONCONTROL_IO_PD_CON(0x2),
- &drex1->concontrol);
-
- /*
- * Enable Clock Gating Control for DMC
- * this saves around 25 mw dmc power as compared to the power
- * consumption without these bits enabled
- */
- setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
- setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
-
- /*
- * As per Exynos5800 UM ver 0.00 section 17.13.2.1
- * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
- * support the PHY initiated update. And it is recommended to set
- * this field to 1'b1 during initialization
- *
- * When we apply PHY-initiated mode, DLL lock value is determined
- * once at DMC init time and not updated later when we change the MIF
- * voltage based on ASV group in kernel. Applying MC-initiated mode
- * makes sure that DLL tracing is ON so that silicon is able to
- * compensate the voltage variation.
- */
- val = readl(&drex0->concontrol);
- val |= CONCONTROL_UPDATE_MODE;
- writel(val , &drex0->concontrol);
- val = readl(&drex1->concontrol);
- val |= CONCONTROL_UPDATE_MODE;
- writel(val , &drex1->concontrol);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h
deleted file mode 100644
index b633e56..0000000
--- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * Machine Specific Values for EXYNOS4012 based board
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ORIGEN_SETUP_H
-#define _ORIGEN_SETUP_H
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-#ifdef CONFIG_CLK_800_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_200_200
-#define DRAM_CLK_200
-#endif
-#ifdef CONFIG_CLK_1000_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_400_200
-#define DRAM_CLK_400
-#endif
-
-/* Bus Configuration Register Address */
-#define ASYNC_CONFIG 0x10010350
-
-/* CLK_SRC_CPU */
-#define MUX_HPM_SEL_MOUTAPLL 0x0
-#define MUX_HPM_SEL_SCLKMPLL 0x1
-#define MUX_CORE_SEL_MOUTAPLL 0x0
-#define MUX_CORE_SEL_SCLKMPLL 0x1
-#define MUX_MPLL_SEL_FILPLL 0x0
-#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
-#define MUX_APLL_SEL_FILPLL 0x0
-#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
- | (MUX_CORE_SEL_MOUTAPLL << 16) \
- | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
- | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
-
-/* CLK_DIV_CPU0 */
-#define APLL_RATIO 0x0
-#define PCLK_DBG_RATIO 0x1
-#define ATB_RATIO 0x3
-#define PERIPH_RATIO 0x3
-#define COREM1_RATIO 0x7
-#define COREM0_RATIO 0x3
-#define CORE_RATIO 0x0
-#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (COREM1_RATIO << 8) \
- | (COREM0_RATIO << 4) \
- | (CORE_RATIO << 0))
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x0
-#define COPY_RATIO 0x3
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
-
-/* CLK_SRC_DMC */
-#define MUX_PWI_SEL_XXTI 0x0
-#define MUX_PWI_SEL_XUSBXTI 0x1
-#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
-#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
-#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
-#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
-#define MUX_PWI_SEL_SCLKMPLL 0x6
-#define MUX_PWI_SEL_SCLKEPLL 0x7
-#define MUX_PWI_SEL_SCLKVPLL 0x8
-#define MUX_DPHY_SEL_SCLKMPLL 0x0
-#define MUX_DPHY_SEL_SCLKAPLL 0x1
-#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
-#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
-#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
- | (MUX_DPHY_SEL_SCLKMPLL << 8) \
- | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
-
-/* CLK_DIV_DMC0 */
-#define CORE_TIMERS_RATIO 0x1
-#define COPY2_RATIO 0x3
-#define DMCP_RATIO 0x1
-#define DMCD_RATIO 0x1
-#define DMC_RATIO 0x1
-#define DPHY_RATIO 0x1
-#define ACP_PCLK_RATIO 0x1
-#define ACP_RATIO 0x3
-#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
- | (COPY2_RATIO << 24) \
- | (DMCP_RATIO << 20) \
- | (DMCD_RATIO << 16) \
- | (DMC_RATIO << 12) \
- | (DPHY_RATIO << 8) \
- | (ACP_PCLK_RATIO << 4) \
- | (ACP_RATIO << 0))
-
-/* CLK_DIV_DMC1 */
-#define DPM_RATIO 0x1
-#define DVSEM_RATIO 0x1
-#define PWI_RATIO 0x1
-#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
- | (DVSEM_RATIO << 16) \
- | (PWI_RATIO << 8))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ONENAND_SEL_ACLK_133 0x0
-#define MUX_ONENAND_SEL_ACLK_160 0x1
-#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
-#define MUX_VPLL_SEL_FINPLL 0x0
-#define MUX_VPLL_SEL_FOUTVPLL 0x1
-#define MUX_EPLL_SEL_FINPLL 0x0
-#define MUX_EPLL_SEL_FOUTEPLL 0x1
-#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
-#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
-#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
- | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
- | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
- | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
- | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
- | (MUX_VPLL_SEL_FINPLL << 8) \
- | (MUX_EPLL_SEL_FINPLL << 4)\
- | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
-
-/* CLK_SRC_TOP1 */
-#define VPLLSRC_SEL_FINPLL 0x0
-#define VPLLSRC_SEL_SCLKHDMI24M 0x1
-#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
-
-/* CLK_DIV_TOP */
-#define ONENAND_RATIO 0x0
-#define ACLK_133_RATIO 0x5
-#define ACLK_160_RATIO 0x4
-#define ACLK_100_RATIO 0x7
-#define ACLK_200_RATIO 0x3
-#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
- | (ACLK_133_RATIO << 12)\
- | (ACLK_160_RATIO << 8) \
- | (ACLK_100_RATIO << 4) \
- | (ACLK_200_RATIO << 0))
-
-/* CLK_SRC_LEFTBUS */
-#define MUX_GDL_SEL_SCLKMPLL 0x0
-#define MUX_GDL_SEL_SCLKAPLL 0x1
-#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
-
-/* CLK_DIV_LEFTBUS */
-#define GPL_RATIO 0x1
-#define GDL_RATIO 0x3
-#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
-
-/* CLK_SRC_RIGHTBUS */
-#define MUX_GDR_SEL_SCLKMPLL 0x0
-#define MUX_GDR_SEL_SCLKAPLL 0x1
-#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
-
-/* CLK_DIV_RIGHTBUS */
-#define GPR_RATIO 0x1
-#define GDR_RATIO 0x3
-#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
-
-/* CLK_SRS_FSYS: 6 = SCLKMPLL */
-#define SATA_SEL_SCLKMPLL 0
-#define SATA_SEL_SCLKAPLL 1
-
-#define MMC_SEL_XXTI 0
-#define MMC_SEL_XUSBXTI 1
-#define MMC_SEL_SCLK_HDMI24M 2
-#define MMC_SEL_SCLK_USBPHY0 3
-#define MMC_SEL_SCLK_USBPHY1 4
-#define MMC_SEL_SCLK_HDMIPHY 5
-#define MMC_SEL_SCLKMPLL 6
-#define MMC_SEL_SCLKEPLL 7
-#define MMC_SEL_SCLKVPLL 8
-
-#define MMCC0_SEL MMC_SEL_SCLKMPLL
-#define MMCC1_SEL MMC_SEL_SCLKMPLL
-#define MMCC2_SEL MMC_SEL_SCLKMPLL
-#define MMCC3_SEL MMC_SEL_SCLKMPLL
-#define MMCC4_SEL MMC_SEL_SCLKMPLL
-#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
- | (MMCC4_SEL << 16) \
- | (MMCC3_SEL << 12) \
- | (MMCC2_SEL << 8) \
- | (MMCC1_SEL << 4) \
- | (MMCC0_SEL << 0))
-
-/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
-/* CLK_DIV_FSYS1 */
-#define MMC0_RATIO 0xF
-#define MMC0_PRE_RATIO 0x0
-#define MMC1_RATIO 0xF
-#define MMC1_PRE_RATIO 0x0
-#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
- | (MMC1_RATIO << 16) \
- | (MMC0_PRE_RATIO << 8) \
- | (MMC0_RATIO << 0))
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO 0xF
-#define MMC2_PRE_RATIO 0x0
-#define MMC3_RATIO 0xF
-#define MMC3_PRE_RATIO 0x0
-#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
- | (MMC3_RATIO << 16) \
- | (MMC2_PRE_RATIO << 8) \
- | (MMC2_RATIO << 0))
-
-/* CLK_DIV_FSYS3 */
-#define MMC4_RATIO 0xF
-#define MMC4_PRE_RATIO 0x0
-#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
- | (MMC4_RATIO << 0))
-
-/* CLK_SRC_PERIL0 */
-#define UART_SEL_XXTI 0
-#define UART_SEL_XUSBXTI 1
-#define UART_SEL_SCLK_HDMI24M 2
-#define UART_SEL_SCLK_USBPHY0 3
-#define UART_SEL_SCLK_USBPHY1 4
-#define UART_SEL_SCLK_HDMIPHY 5
-#define UART_SEL_SCLKMPLL 6
-#define UART_SEL_SCLKEPLL 7
-#define UART_SEL_SCLKVPLL 8
-
-#define UART0_SEL UART_SEL_SCLKMPLL
-#define UART1_SEL UART_SEL_SCLKMPLL
-#define UART2_SEL UART_SEL_SCLKMPLL
-#define UART3_SEL UART_SEL_SCLKMPLL
-#define UART4_SEL UART_SEL_SCLKMPLL
-#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL << 0))
-
-/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
-/* CLK_DIV_PERIL0 */
-#define UART0_RATIO 7
-#define UART1_RATIO 7
-#define UART2_RATIO 7
-#define UART3_RATIO 7
-#define UART4_RATIO 7
-#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
- | (UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO << 0))
-
-/* Clock Source CAM/FIMC */
-/* CLK_SRC_CAM */
-#define CAM0_SEL_XUSBXTI 1
-#define CAM1_SEL_XUSBXTI 1
-#define CSIS0_SEL_XUSBXTI 1
-#define CSIS1_SEL_XUSBXTI 1
-
-#define FIMC_SEL_SCLKMPLL 6
-#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
-
-#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
- | (CSIS0_SEL_XUSBXTI << 24) \
- | (CAM1_SEL_XUSBXTI << 20) \
- | (CAM0_SEL_XUSBXTI << 16) \
- | (FIMC3_LCLK_SEL << 12) \
- | (FIMC2_LCLK_SEL << 8) \
- | (FIMC1_LCLK_SEL << 4) \
- | (FIMC0_LCLK_SEL << 0))
-
-/* SCLK CAM */
-/* CLK_DIV_CAM */
-#define FIMC0_LCLK_RATIO 4
-#define FIMC1_LCLK_RATIO 4
-#define FIMC2_LCLK_RATIO 4
-#define FIMC3_LCLK_RATIO 4
-#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
- | (FIMC2_LCLK_RATIO << 8) \
- | (FIMC1_LCLK_RATIO << 4) \
- | (FIMC0_LCLK_RATIO << 0))
-
-/* SCLK MFC */
-/* CLK_SRC_MFC */
-#define MFC_SEL_MPLL 0
-#define MOUTMFC_0 0
-#define MFC_SEL MOUTMFC_0
-#define MFC_0_SEL MFC_SEL_MPLL
-#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
-
-
-/* CLK_DIV_MFC */
-#define MFC_RATIO 3
-#define CLK_DIV_MFC_VAL (MFC_RATIO)
-
-/* SCLK G3D */
-/* CLK_SRC_G3D */
-#define G3D_SEL_MPLL 0
-#define MOUTG3D_0 0
-#define G3D_SEL MOUTG3D_0
-#define G3D_0_SEL G3D_SEL_MPLL
-#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
-
-/* CLK_DIV_G3D */
-#define G3D_RATIO 1
-#define CLK_DIV_G3D_VAL (G3D_RATIO)
-
-/* SCLK LCD0 */
-/* CLK_SRC_LCD0 */
-#define FIMD_SEL_SCLKMPLL 6
-#define MDNIE0_SEL_XUSBXTI 1
-#define MDNIE_PWM0_SEL_XUSBXTI 1
-#define MIPI0_SEL_XUSBXTI 1
-#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
- | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
- | (MDNIE0_SEL_XUSBXTI << 4) \
- | (FIMD_SEL_SCLKMPLL << 0))
-
-/* CLK_DIV_LCD0 */
-#define FIMD0_RATIO 4
-#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
-
-/* Required period to generate a stable clock output */
-/* PLL_LOCK_TIME */
-#define PLL_LOCKTIME 0x1C20
-
-/* PLL Values */
-#define DISABLE 0
-#define ENABLE 1
-#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
- | (mdiv << 16) \
- | (pdiv << 8) \
- | (sdiv << 0))
-
-/* APLL_CON0 */
-#define APLL_MDIV 0xFA
-#define APLL_PDIV 0x6
-#define APLL_SDIV 0x1
-#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
-
-/* APLL_CON1 */
-#define APLL_AFC_ENB 0x1
-#define APLL_AFC 0xC
-#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
-
-/* MPLL_CON0 */
-#define MPLL_MDIV 0xC8
-#define MPLL_PDIV 0x6
-#define MPLL_SDIV 0x1
-#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
-
-/* MPLL_CON1 */
-#define MPLL_AFC_ENB 0x0
-#define MPLL_AFC 0x1C
-#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
-
-/* EPLL_CON0 */
-#define EPLL_MDIV 0x30
-#define EPLL_PDIV 0x3
-#define EPLL_SDIV 0x2
-#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
-
-/* EPLL_CON1 */
-#define EPLL_K 0x0
-#define EPLL_CON1_VAL (EPLL_K >> 0)
-
-/* VPLL_CON0 */
-#define VPLL_MDIV 0x35
-#define VPLL_PDIV 0x3
-#define VPLL_SDIV 0x2
-#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
-
-/* VPLL_CON1 */
-#define VPLL_SSCG_EN DISABLE
-#define VPLL_SEL_PF_DN_SPREAD 0x0
-#define VPLL_MRR 0x11
-#define VPLL_MFR 0x0
-#define VPLL_K 0x400
-#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
- | (VPLL_SEL_PF_DN_SPREAD << 29) \
- | (VPLL_MRR << 24) \
- | (VPLL_MFR << 16) \
- | (VPLL_K << 0))
-
-/* DMC */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_ZQ 0x0a000000
-#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
-#define MEM_TIMINGS_MSR_COUNT 4
-#define CTRL_START (1 << 0)
-#define CTRL_DLL_ON (1 << 1)
-#define AREF_EN (1 << 5)
-#define DRV_TYPE (1 << 6)
-
-struct mem_timings {
- unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
- unsigned timingref;
- unsigned timingrow;
- unsigned timingdata;
- unsigned timingpower;
- unsigned zqcontrol;
- unsigned control0;
- unsigned control1;
- unsigned control2;
- unsigned concontrol;
- unsigned prechconfig;
- unsigned memcontrol;
- unsigned memconfig0;
- unsigned memconfig1;
- unsigned dll_resync;
- unsigned dll_on;
-};
-
-/* MIU */
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
-#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
-#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
-#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
-#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
-#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
-#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
-#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
-
-#ifdef CONFIG_ORIGEN
-/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
-#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
-#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
-#endif
-
-#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
-#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
-#define INTERLEAVE_ADDR_MAP_EN 0x00000001
-
-#ifdef CONFIG_MIU_1BIT_INTERLEAVED
-/* Interleave_bit0: 0xC*/
-#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
-#endif
-#ifdef CONFIG_MIU_2BIT_INTERLEAVED
-/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
-#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
-#endif
-#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
-#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
-#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
-#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
-/* Enable SME0 and SME1*/
-#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
-
-#define FORCE_DLL_RESYNC 3
-#define DLL_CONTROL_ON 1
-
-#define DIRECT_CMD1 0x00020000
-#define DIRECT_CMD2 0x00030000
-#define DIRECT_CMD3 0x00010002
-#define DIRECT_CMD4 0x00000328
-
-#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
-#define CTRL_ZQ_START (0x1 << 1)
-#define CTRL_ZQ_DIV (0 << 4)
-#define CTRL_ZQ_MODE_DDS (0x7 << 8)
-#define CTRL_ZQ_MODE_TERM (0x2 << 11)
-#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
-#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
-#define CTRL_DCC (0xE38 << 20)
-#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
- | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
- | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
- | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
-
-#define ASYNC (0 << 0)
-#define CLK_RATIO (1 << 1)
-#define DIV_PIPE (1 << 3)
-#define AWR_ON (1 << 4)
-#define AREF_DISABLE (0 << 5)
-#define DRV_TYPE_DISABLE (0 << 6)
-#define CHIP0_NOT_EMPTY (0 << 8)
-#define CHIP1_NOT_EMPTY (0 << 9)
-#define DQ_SWAP_DISABLE (0 << 10)
-#define QOS_FAST_DISABLE (0 << 11)
-#define RD_FETCH (0x3 << 12)
-#define TIMEOUT_LEVEL0 (0xFFF << 16)
-#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
- | AREF_DISABLE | DRV_TYPE_DISABLE\
- | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
- | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
- | RD_FETCH | TIMEOUT_LEVEL0)
-
-#define CLK_STOP_DISABLE (0 << 1)
-#define DPWRDN_DISABLE (0 << 2)
-#define DPWRDN_TYPE (0 << 3)
-#define TP_DISABLE (0 << 4)
-#define DSREF_DIABLE (0 << 5)
-#define ADD_LAT_PALL (1 << 6)
-#define MEM_TYPE_DDR3 (0x6 << 8)
-#define MEM_WIDTH_32 (0x2 << 12)
-#define NUM_CHIP_2 (1 << 16)
-#define BL_8 (0x3 << 20)
-#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
- | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
- | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
- | NUM_CHIP_2 | BL_8)
-
-
-#define CHIP_BANK_8 (0x3 << 0)
-#define CHIP_ROW_14 (0x2 << 4)
-#define CHIP_COL_10 (0x3 << 8)
-#define CHIP_MAP_INTERLEAVED (1 << 12)
-#define CHIP_MASK (0xe0 << 16)
-#ifdef CONFIG_MIU_LINEAR
-#define CHIP0_BASE (0x40 << 24)
-#define CHIP1_BASE (0x60 << 24)
-#else
-#define CHIP0_BASE (0x20 << 24)
-#define CHIP1_BASE (0x40 << 24)
-#endif
-#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
- | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
-#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
- | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
-
-#define TP_CNT (0xff << 24)
-#define PRECHCONFIG TP_CNT
-
-#define CTRL_OFF (0 << 0)
-#define CTRL_DLL_OFF (0 << 1)
-#define CTRL_HALF (0 << 2)
-#define CTRL_DFDQS (1 << 3)
-#define DQS_DELAY (0 << 4)
-#define CTRL_START_POINT (0x10 << 8)
-#define CTRL_INC (0x10 << 16)
-#define CTRL_FORCE (0x71 << 24)
-#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
- | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
- | CTRL_INC | CTRL_FORCE)
-
-#define CTRL_SHIFTC (0x6 << 0)
-#define CTRL_REF (8 << 4)
-#define CTRL_SHGATE (1 << 29)
-#define TERM_READ_EN (1 << 30)
-#define TERM_WRITE_EN (1 << 31)
-#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
- | TERM_READ_EN | TERM_WRITE_EN)
-
-#define CONTROL2_VAL 0x00000000
-
-#ifdef CONFIG_ORIGEN
-#define TIMINGREF_VAL 0x000000BB
-#define TIMINGROW_VAL 0x4046654f
-#define TIMINGDATA_VAL 0x46400506
-#define TIMINGPOWER_VAL 0x52000A3C
-#else
-#define TIMINGREF_VAL 0x000000BC
-#ifdef DRAM_CLK_330
-#define TIMINGROW_VAL 0x3545548d
-#define TIMINGDATA_VAL 0x45430506
-#define TIMINGPOWER_VAL 0x4439033c
-#endif
-#ifdef DRAM_CLK_400
-#define TIMINGROW_VAL 0x45430506
-#define TIMINGDATA_VAL 0x56500506
-#define TIMINGPOWER_VAL 0x5444033d
-#endif
-#endif
-#endif
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
deleted file mode 100644
index 2eea48a..0000000
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ /dev/null
@@ -1,944 +0,0 @@
-/*
- * Machine Specific Values for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SMDK5250_SETUP_H
-#define _SMDK5250_SETUP_H
-
-#include <config.h>
-#include <asm/arch/dmc.h>
-
-#define NOT_AVAILABLE 0
-#define DATA_MASK 0xFFFFF
-
-#define ENABLE_BIT 0x1
-#define DISABLE_BIT 0x0
-#define CA_SWAP_EN (1 << 0)
-
-/* Set PLL */
-#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-
-/* MEMCONTROL register bit fields */
-#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
-#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
-#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
-#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
-#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
-#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
-#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
-
-#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
-#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
-#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
-
-#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
-
-#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
-#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
-
-#define DMC_MEMCONTROL_BL_8 (3 << 20)
-#define DMC_MEMCONTROL_BL_4 (2 << 20)
-
-#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
-
-#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
-
-/* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
-#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
-#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
-#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
-#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
-#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
-
-#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
-#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
-#define DMC_MEMBASECONFIG_VAL(x) ( \
- DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
- DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
-)
-
-/*
- * As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more.
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK 0x7C0
-
-#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
-#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
-
-#define DMC_PRECHCONFIG_VAL 0xFF000000
-#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
-
-#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
-#define DFI_INIT_START (1 << 28)
-#define EMPTY (1 << 8)
-#define AREF_EN (1 << 5)
-
-#define DFI_INIT_COMPLETE_CHO (1 << 2)
-#define DFI_INIT_COMPLETE_CH1 (1 << 3)
-
-#define RDLVL_COMPLETE_CHO (1 << 14)
-#define RDLVL_COMPLETE_CH1 (1 << 15)
-
-#define CLK_STOP_EN (1 << 0)
-#define DPWRDN_EN (1 << 1)
-#define DSREF_EN (1 << 5)
-
-/* COJCONTROL register bit fields */
-#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
-#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
-#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
-#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
-#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
-#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
-#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
-#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
-#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
-
-#define DMC_CONCONTROL_VAL 0x1FFF2101
-
-#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
- | DMC_CONCONTROL_AREF_EN_ENABLE \
- | DMC_CONCONTROL_IO_PD_CON_ENABLE
-
-#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x2
-#define COPY_RATIO 0x0
-
-/* CLK_DIV_CPU1 = 0x00000003 */
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
- | (COPY_RATIO))
-
-/* CLK_SRC_CORE0 */
-#define CLK_SRC_CORE0_VAL 0x00000000
-
-/* CLK_SRC_CORE1 */
-#define CLK_SRC_CORE1_VAL 0x100
-
-/* CLK_DIV_CORE0 */
-#define CLK_DIV_CORE0_VAL 0x00120000
-
-/* CLK_DIV_CORE1 */
-#define CLK_DIV_CORE1_VAL 0x07070700
-
-/* CLK_DIV_SYSRGT */
-#define CLK_DIV_SYSRGT_VAL 0x00000111
-
-/* CLK_DIV_ACP */
-#define CLK_DIV_ACP_VAL 0x12
-
-/* CLK_DIV_SYSLFT */
-#define CLK_DIV_SYSLFT_VAL 0x00000311
-
-#define MUX_APLL_SEL_MASK (1 << 0)
-#define MUX_MPLL_SEL_MASK (1 << 8)
-#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
-#define MUX_CPLL_SEL_MASK (1 << 8)
-#define MUX_EPLL_SEL_MASK (1 << 12)
-#define MUX_VPLL_SEL_MASK (1 << 16)
-#define MUX_GPLL_SEL_MASK (1 << 28)
-#define MUX_BPLL_SEL_MASK (1 << 0)
-#define MUX_HPM_SEL_MASK (1 << 20)
-#define HPM_SEL_SCLK_MPLL (1 << 21)
-#define PLL_LOCKED (1 << 29)
-#define APLL_CON0_LOCKED (1 << 29)
-#define MPLL_CON0_LOCKED (1 << 29)
-#define BPLL_CON0_LOCKED (1 << 29)
-#define CPLL_CON0_LOCKED (1 << 29)
-#define EPLL_CON0_LOCKED (1 << 29)
-#define GPLL_CON0_LOCKED (1 << 29)
-#define VPLL_CON0_LOCKED (1 << 29)
-#define CLK_REG_DISABLE 0x0
-#define TOP2_VAL 0x0110000
-
-/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
-#define SPI0_ISP_SEL 6
-#define SPI1_ISP_SEL 6
-#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
- | (SPI0_ISP_SEL << 0)
-
-/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
-#define SPI0_ISP_RATIO 0xf
-#define SPI1_ISP_RATIO 0xf
-#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
- | (SPI0_ISP_RATIO << 0)
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO_MASK 0xf
-#define MMC2_RATIO_VAL 0x3
-#define MMC2_RATIO_OFFSET 0
-
-#define MMC2_PRE_RATIO_MASK 0xff
-#define MMC2_PRE_RATIO_VAL 0x9
-#define MMC2_PRE_RATIO_OFFSET 8
-
-#define MMC3_RATIO_MASK 0xf
-#define MMC3_RATIO_VAL 0x1
-#define MMC3_RATIO_OFFSET 16
-
-#define MMC3_PRE_RATIO_MASK 0xff
-#define MMC3_PRE_RATIO_VAL 0x0
-#define MMC3_PRE_RATIO_OFFSET 24
-
-/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL 0x0
-
-/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL 0x10
-
-/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL 0x10
-
-/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL 0x10
-
-/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL 0x1
-
-/* CLK_SRC_KFC */
-#define SRC_KFC_HPM_SEL (1 << 15)
-
-/* CLK_SRC_KFC */
-#define CLK_SRC_KFC_VAL 0x00008001
-
-/* CLK_DIV_KFC */
-#define CLK_DIV_KFC_VAL 0x03300110
-
-/* CLK_DIV2_RATIO */
-#define CLK_DIV2_RATIO 0x10111150
-
-/* CLK_DIV4_RATIO */
-#define CLK_DIV4_RATIO 0x00000003
-
-/* CLK_DIV_G2D */
-#define CLK_DIV_G2D 0x00000010
-
-/*
- * DIV_DISP1_0
- * For DP, divisor should be 2
- */
-#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
-
-/* CLK_GATE_IP_DISP1 */
-#define CLK_GATE_DP1_ALLOW (1 << 4)
-
-/* AUDIO CLK SEL */
-#define AUDIO0_SEL_EPLL (0x6 << 28)
-#define AUDIO0_RATIO 0x5
-#define PCM0_RATIO 0x3
-#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
-
-/* CLK_SRC_CDREX */
-#define MUX_MCLK_CDR_MSPLL (1 << 4)
-#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
-#define BPLL_SEL_MASK 0x7
-#define FOUTBPLL 2
-
-#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
-#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
-
-#define PHY_CON0_RESET_VAL 0x17020a40
-#define P0_CMD_EN (1 << 14)
-#define BYTE_RDLVL_EN (1 << 13)
-#define CTRL_SHGATE (1 << 8)
-
-#define PHY_CON1_RESET_VAL 0x09210100
-#define RDLVL_PASS_ADJ_VAL 0x6
-#define RDLVL_PASS_ADJ_OFFSET 16
-#define CTRL_GATEDURADJ_MASK (0xf << 20)
-#define READ_LEVELLING_DDR3 0x0100
-
-#define PHY_CON2_RESET_VAL 0x00010004
-#define INIT_DESKEW_EN (1 << 6)
-#define DLL_DESKEW_EN (1 << 12)
-#define RDLVL_GATE_EN (1 << 24)
-#define RDLVL_EN (1 << 25)
-#define RDLVL_INCR_ADJ (0x1 << 16)
-
-/* DREX_PAUSE */
-#define DREX_PAUSE_EN (1 << 0)
-
-#define BYPASS_EN (1 << 22)
-
-/* MEMMORY VAL */
-#define PHY_CON0_VAL 0x17021A00
-
-#define PHY_CON12_RESET_VAL 0x10100070
-#define PHY_CON12_VAL 0x10107F50
-#define CTRL_START (1 << 6)
-#define CTRL_DLL_ON (1 << 5)
-#define CTRL_LOCK_COARSE_OFFSET 10
-#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
-#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
- CTRL_LOCK_COARSE_OFFSET)
-#define CTRL_FORCE_MASK (0x7F << 8)
-#define CTRL_FINE_LOCKED 0x7
-
-#define CTRL_OFFSETD_RESET_VAL 0x8
-#define CTRL_OFFSETD_VAL 0x7F
-
-#define CTRL_OFFSETR0 0x7F
-#define CTRL_OFFSETR1 0x7F
-#define CTRL_OFFSETR2 0x7F
-#define CTRL_OFFSETR3 0x7F
-#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
- CTRL_OFFSETR1 << 8 | \
- CTRL_OFFSETR2 << 16 | \
- CTRL_OFFSETR3 << 24)
-#define PHY_CON4_RESET_VAL 0x08080808
-
-#define CTRL_OFFSETW0 0x7F
-#define CTRL_OFFSETW1 0x7F
-#define CTRL_OFFSETW2 0x7F
-#define CTRL_OFFSETW3 0x7F
-#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
- CTRL_OFFSETW1 << 8 | \
- CTRL_OFFSETW2 << 16 | \
- CTRL_OFFSETW3 << 24)
-#define PHY_CON6_RESET_VAL 0x08080808
-
-#define PHY_CON14_RESET_VAL 0x001F0000
-#define CTRL_PULLD_DQS 0xF
-#define CTRL_PULLD_DQS_OFFSET 0
-
-/* ZQ Configurations */
-#define PHY_CON16_RESET_VAL 0x08000304
-
-#define ZQ_CLK_EN (1 << 27)
-#define ZQ_CLK_DIV_EN (1 << 18)
-#define ZQ_MANUAL_STR (1 << 1)
-#define ZQ_DONE (1 << 0)
-#define ZQ_MODE_DDS_OFFSET 24
-
-#define CTRL_RDLVL_GATE_ENABLE 1
-#define CTRL_RDLVL_GATE_DISABLE 0
-#define CTRL_RDLVL_DATA_ENABLE 2
-
-/* Direct Command */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_PALL 0x01000000
-#define DIRECT_CMD_ZQINIT 0x0a000000
-#define DIRECT_CMD_CHANNEL_SHIFT 28
-#define DIRECT_CMD_CHIP_SHIFT 20
-#define DIRECT_CMD_BANK_SHIFT 16
-#define DIRECT_CMD_REFA (5 << 24)
-#define DIRECT_CMD_MRS1 0x71C00
-#define DIRECT_CMD_MRS2 0x10BFC
-#define DIRECT_CMD_MRS3 0x0050C
-#define DIRECT_CMD_MRS4 0x00868
-#define DIRECT_CMD_MRS5 0x00C04
-
-/* Drive Strength */
-#define IMPEDANCE_48_OHM 4
-#define IMPEDANCE_40_OHM 5
-#define IMPEDANCE_34_OHM 6
-#define IMPEDANCE_30_OHM 7
-#define PHY_CON39_VAL_48_OHM 0x09240924
-#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
-#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
-#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
-
-#define CTRL_BSTLEN_OFFSET 8
-#define CTRL_RDLAT_OFFSET 0
-
-#define CMD_DEFAULT_LPDDR3 0xF
-#define CMD_DEFUALT_OFFSET 0
-#define T_WRDATA_EN 0x7
-#define T_WRDATA_EN_DDR3 0x8
-#define T_WRDATA_EN_OFFSET 16
-#define T_WRDATA_EN_MASK 0x1f
-
-#define PHY_CON31_VAL 0x0C183060
-#define PHY_CON32_VAL 0x60C18306
-#define PHY_CON33_VAL 0x00000030
-
-#define PHY_CON31_RESET_VAL 0x0
-#define PHY_CON32_RESET_VAL 0x0
-#define PHY_CON33_RESET_VAL 0x0
-
-#define SL_DLL_DYN_CON_EN (1 << 1)
-#define FP_RESYNC (1 << 3)
-#define CTRL_START (1 << 6)
-
-#define DMC_AREF_EN (1 << 5)
-#define DMC_CONCONTROL_EMPTY (1 << 8)
-#define DFI_INIT_START (1 << 28)
-
-#define DMC_MEMCONTROL_VAL 0x00312700
-#define CLK_STOP_EN (1 << 0)
-#define DPWRDN_EN (1 << 1)
-#define DSREF_EN (1 << 5)
-
-#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
-#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
-#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
-#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
-#define CHIP_BASE_OFFSET 16
-
-#define MEMCONFIG_VAL 0x1323
-#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
-#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
-
-#define TIMINGAREF_VAL 0x5d
-#define TIMINGROW_VAL 0x345A8692
-#define TIMINGDATA_VAL 0x3630065C
-#define TIMINGPOWER_VAL 0x50380336
-#define DFI_INIT_COMPLETE (1 << 3)
-
-#define BRBRSVCONTROL_VAL 0x00000033
-#define BRBRSVCONFIG_VAL 0x88778877
-
-/* Clock Gating Control (CGCONTROL) register */
-#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
-#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
-#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
-#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
-#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
- BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
-
-/* DMC PHY Control0 register */
-#define PHY_CONTROL0_RESET_VAL 0x0
-#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
-#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
-#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
-#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
-
-/* Driver strength for CK, CKE, CS & CA */
-#define IMP_OUTPUT_DRV_40_OHM 0x5
-#define IMP_OUTPUT_DRV_30_OHM 0x7
-#define DA_3_DS_OFFSET 25
-#define DA_2_DS_OFFSET 22
-#define DA_1_DS_OFFSET 19
-#define DA_0_DS_OFFSET 16
-#define CA_CK_DRVR_DS_OFFSET 9
-#define CA_CKE_DRVR_DS_OFFSET 6
-#define CA_CS_DRVR_DS_OFFSET 3
-#define CA_ADR_DRVR_DS_OFFSET 0
-
-#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
-#define PHY_CON42_CTRL_RDLAT_SHIFT 0
-
-/*
- * Definitions that differ with SoC's.
- * Below is the part defining macros for Exynos5250.
- * Else part introduces macros for Exynos5420.
- */
-#ifndef CONFIG_EXYNOS5420
-
-/* APLL_CON1 */
-#define APLL_CON1_VAL (0x00203800)
-
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x00203800)
-
-/* CPLL_CON1 */
-#define CPLL_CON1_VAL (0x00203800)
-
-/* DPLL_CON1 */
-#define DPLL_CON1_VAL (NOT_AVAILABLE)
-
-/* GPLL_CON1 */
-#define GPLL_CON1_VAL (0x00203800)
-
-/* EPLL_CON1, CON2 */
-#define EPLL_CON1_VAL 0x00000000
-#define EPLL_CON2_VAL 0x00000080
-
-/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x00000000
-#define VPLL_CON2_VAL 0x00000080
-
-/* RPLL_CON1, CON2 */
-#define RPLL_CON1_VAL NOT_AVAILABLE
-#define RPLL_CON2_VAL NOT_AVAILABLE
-
-/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x00203800
-
-/* SPLL_CON1 */
-#define SPLL_CON1_VAL NOT_AVAILABLE
-
-/* IPLL_CON1 */
-#define IPLL_CON1_VAL NOT_AVAILABLE
-
-/* KPLL_CON1 */
-#define KPLL_CON1_VAL NOT_AVAILABLE
-
-/* CLK_SRC_ISP */
-#define CLK_SRC_ISP_VAL NOT_AVAILABLE
-#define CLK_DIV_ISP0_VAL 0x31
-#define CLK_DIV_ISP1_VAL 0x0
-
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x66666
-#define CLK_DIV_FSYS0_VAL 0x0BB00000
-#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
-#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
-
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 0
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
-/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_VAL 0x1
-
-/* CLK_DIV_CDREX */
-#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
-#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
-
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
-
-#define MCLK_CDREX2_RATIO 0x0
-#define ACLK_EFCON_RATIO 0x1
-#define MCLK_DPHY_RATIO 0x1
-#define MCLK_CDREX_RATIO 0x1
-#define ACLK_C2C_200_RATIO 0x1
-#define C2C_CLK_400_RATIO 0x1
-#define PCLK_CDREX_RATIO 0x1
-#define ACLK_CDREX_RATIO 0x1
-
-#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
- | (C2C_CLK_400_RATIO << 6) \
- | (PCLK_CDREX_RATIO << 4) \
- | (ACLK_CDREX_RATIO))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ACLK_300_GSCL_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID_SEL 0x0
-#define MUX_ACLK_400_G3D_MID_SEL 0x0
-#define MUX_ACLK_333_SEL 0x0
-#define MUX_ACLK_300_DISP1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID_SEL 0x0
-#define MUX_ACLK_200_SEL 0x0
-#define MUX_ACLK_166_SEL 0x0
-#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
- | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
- | (MUX_ACLK_400_G3D_MID_SEL << 20) \
- | (MUX_ACLK_333_SEL << 16) \
- | (MUX_ACLK_300_DISP1_SEL << 15) \
- | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
- | (MUX_ACLK_200_SEL << 12) \
- | (MUX_ACLK_166_SEL << 8))
-
-/* CLK_SRC_TOP1 */
-#define MUX_ACLK_400_G3D_SEL 0x1
-#define MUX_ACLK_400_ISP_SEL 0x0
-#define MUX_ACLK_400_IOP_SEL 0x0
-#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
-#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
- |(MUX_ACLK_400_ISP_SEL << 24) \
- |(MUX_ACLK_400_IOP_SEL << 20) \
- |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
- |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
- |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
-
-/* CLK_SRC_TOP2 */
-#define MUX_GPLL_SEL 0x1
-#define MUX_BPLL_USER_SEL 0x0
-#define MUX_MPLL_USER_SEL 0x0
-#define MUX_VPLL_SEL 0x1
-#define MUX_EPLL_SEL 0x1
-#define MUX_CPLL_SEL 0x1
-#define VPLLSRC_SEL 0x0
-#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
- | (MUX_BPLL_USER_SEL << 24) \
- | (MUX_MPLL_USER_SEL << 20) \
- | (MUX_VPLL_SEL << 16) \
- | (MUX_EPLL_SEL << 12) \
- | (MUX_CPLL_SEL << 8) \
- | (VPLLSRC_SEL))
-/* CLK_SRC_TOP3 */
-#define MUX_ACLK_333_SUB_SEL 0x1
-#define MUX_ACLK_400_SUB_SEL 0x1
-#define MUX_ACLK_266_ISP_SUB_SEL 0x1
-#define MUX_ACLK_266_GPS_SUB_SEL 0x0
-#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
-#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
-#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
- | (MUX_ACLK_400_SUB_SEL << 20) \
- | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
- | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
- | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
- | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
- | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
- | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
-
-#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
-#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
-#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
-#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
-
-/* CLK_DIV_TOP0 */
-#define ACLK_300_DISP1_RATIO 0x2
-#define ACLK_400_G3D_RATIO 0x0
-#define ACLK_333_RATIO 0x0
-#define ACLK_266_RATIO 0x2
-#define ACLK_200_RATIO 0x3
-#define ACLK_166_RATIO 0x1
-#define ACLK_133_RATIO 0x1
-#define ACLK_66_RATIO 0x5
-
-#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
- | (ACLK_400_G3D_RATIO << 24) \
- | (ACLK_333_RATIO << 20) \
- | (ACLK_266_RATIO << 16) \
- | (ACLK_200_RATIO << 12) \
- | (ACLK_166_RATIO << 8) \
- | (ACLK_133_RATIO << 4) \
- | (ACLK_66_RATIO))
-
-/* CLK_DIV_TOP1 */
-#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
-#define ACLK_66_PRE_RATIO 0x1
-#define ACLK_400_ISP_RATIO 0x1
-#define ACLK_400_IOP_RATIO 0x1
-#define ACLK_300_GSCL_RATIO 0x2
-
-#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
- | (ACLK_66_PRE_RATIO << 24) \
- | (ACLK_400_ISP_RATIO << 20) \
- | (ACLK_400_IOP_RATIO << 16) \
- | (ACLK_300_GSCL_RATIO << 12))
-
-#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
-
-/* PLL Lock Value Factor */
-#define PLL_LOCK_FACTOR 250
-#define PLL_X_LOCK_FACTOR 3000
-
-/* CLK_SRC_PERIC0 */
-#define PWM_SEL 6
-#define UART3_SEL 6
-#define UART2_SEL 6
-#define UART1_SEL 6
-#define UART0_SEL 6
-/* SRC_CLOCK = SCLK_MPLL */
-#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL))
-
-/* CLK_SRC_PERIC1 */
-/* SRC_CLOCK = SCLK_MPLL */
-#define SPI0_SEL 6
-#define SPI1_SEL 6
-#define SPI2_SEL 6
-#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
- | (SPI1_SEL << 20) \
- | (SPI0_SEL << 16))
-
-/* CLK_DIV_PERIL0 */
-#define UART5_RATIO 7
-#define UART4_RATIO 7
-#define UART3_RATIO 7
-#define UART2_RATIO 7
-#define UART1_RATIO 7
-#define UART0_RATIO 7
-
-#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO))
-/* CLK_DIV_PERIC1 */
-#define SPI1_RATIO 0x7
-#define SPI0_RATIO 0xf
-#define SPI1_SUB_RATIO 0x0
-#define SPI0_SUB_RATIO 0x0
-#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
- | ((SPI1_RATIO << 16) \
- | (SPI0_SUB_RATIO << 8) \
- | (SPI0_RATIO << 0)))
-
-/* CLK_DIV_PERIC2 */
-#define SPI2_RATIO 0xf
-#define SPI2_SUB_RATIO 0x0
-#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
- | (SPI2_RATIO << 0))
-
-/* CLK_DIV_PERIC3 */
-#define PWM_RATIO 8
-#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
-
-
-/* CLK_DIV_PERIC4 */
-#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
-
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x6
-#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
-
-#define APLL_FOUT (1 << 0)
-#define KPLL_FOUT NOT_AVAILABLE
-
-#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
-
-#else
-#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
-
-/* APLL_CON1 */
-#define APLL_CON1_VAL (0x0020F300)
-
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x0020F300)
-
-
-/* CPLL_CON1 */
-#define CPLL_CON1_VAL 0x0020f300
-
-/* DPLL_CON1 */
-#define DPLL_CON1_VAL (0x0020F300)
-
-/* GPLL_CON1 */
-#define GPLL_CON1_VAL (NOT_AVAILABLE)
-
-
-/* EPLL_CON1, CON2 */
-#define EPLL_CON1_VAL 0x00000000
-#define EPLL_CON2_VAL 0x00000080
-
-/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x0020f300
-#define VPLL_CON2_VAL NOT_AVAILABLE
-
-/* RPLL_CON1, CON2 */
-#define RPLL_CON1_VAL 0x00000000
-#define RPLL_CON2_VAL 0x00000080
-
-/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x0020f300
-
-/* SPLL_CON1 */
-#define SPLL_CON1_VAL 0x0020f300
-
-/* IPLL_CON1 */
-#define IPLL_CON1_VAL 0x00000080
-
-/* KPLL_CON1 */
-#define KPLL_CON1_VAL 0x200000
-
-/* CLK_SRC_ISP */
-#define CLK_SRC_ISP_VAL 0x33366000
-#define CLK_DIV_ISP0_VAL 0x13131300
-#define CLK_DIV_ISP1_VAL 0xbb110202
-
-
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x33033300
-#define CLK_DIV_FSYS0_VAL 0x0
-#define CLK_DIV_FSYS1_VAL 0x04f13c4f
-#define CLK_DIV_FSYS2_VAL 0x041d0000
-
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 1
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
-/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_VAL 0x00000011
-
-/* CLK_DIV_CDREX */
-#define CLK_DIV_CDREX0_VAL 0x30010100
-#define CLK_DIV_CDREX1_VAL 0x300
-
-#define CLK_DIV_CDREX_VAL 0x17010100
-
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL 0x01440020
-
-/* CLK_SRC_TOP */
-#define CLK_SRC_TOP0_VAL 0x12221222
-#define CLK_SRC_TOP1_VAL 0x00100200
-#define CLK_SRC_TOP2_VAL 0x11101000
-#define CLK_SRC_TOP3_VAL 0x11111111
-#define CLK_SRC_TOP4_VAL 0x11110111
-#define CLK_SRC_TOP5_VAL 0x11111101
-#define CLK_SRC_TOP6_VAL 0x11110111
-#define CLK_SRC_TOP7_VAL 0x00022200
-
-/* CLK_DIV_TOP */
-#define CLK_DIV_TOP0_VAL 0x23712311
-#define CLK_DIV_TOP1_VAL 0x13100B00
-#define CLK_DIV_TOP2_VAL 0x11101100
-
-/* PLL Lock Value Factor */
-#define PLL_LOCK_FACTOR 200
-#define PLL_X_LOCK_FACTOR 3000
-
-/* CLK_SRC_PERIC0 */
-#define SPDIF_SEL 1
-#define PWM_SEL 3
-#define UART4_SEL 3
-#define UART3_SEL 3
-#define UART2_SEL 3
-#define UART1_SEL 3
-#define UART0_SEL 3
-/* SRC_CLOCK = SCLK_RPLL */
-#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
- | (PWM_SEL << 24) \
- | (UART4_SEL << 20) \
- | (UART3_SEL << 16) \
- | (UART2_SEL << 12) \
- | (UART1_SEL << 8) \
- | (UART0_SEL << 4))
-
-/* CLK_SRC_PERIC1 */
-/* SRC_CLOCK = SCLK_EPLL */
-#define SPI0_SEL 6
-#define SPI1_SEL 6
-#define SPI2_SEL 6
-#define AUDIO0_SEL 6
-#define AUDIO1_SEL 6
-#define AUDIO2_SEL 6
-#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
- | (SPI1_SEL << 24) \
- | (SPI0_SEL << 20) \
- | (AUDIO2_SEL << 16) \
- | (AUDIO2_SEL << 12) \
- | (AUDIO2_SEL << 8))
-
-/* CLK_DIV_PERIC0 */
-#define PWM_RATIO 8
-#define UART4_RATIO 9
-#define UART3_RATIO 9
-#define UART2_RATIO 9
-#define UART1_RATIO 9
-#define UART0_RATIO 9
-
-#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
- | (UART4_RATIO << 24) \
- | (UART3_RATIO << 20) \
- | (UART2_RATIO << 16) \
- | (UART1_RATIO << 12) \
- | (UART0_RATIO << 8))
-/* CLK_DIV_PERIC1 */
-#define SPI2_RATIO 0x1
-#define SPI1_RATIO 0x1
-#define SPI0_RATIO 0x1
-#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
- | (SPI1_RATIO << 24) \
- | (SPI0_RATIO << 20))
-
-/* CLK_DIV_PERIC2 */
-#define PCM2_RATIO 0x3
-#define PCM1_RATIO 0x3
-#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
- | (PCM1_RATIO << 16))
-
-/* CLK_DIV_PERIC3 */
-#define AUDIO2_RATIO 0x5
-#define AUDIO1_RATIO 0x5
-#define AUDIO0_RATIO 0x5
-#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
- | (AUDIO1_RATIO << 24) \
- | (AUDIO0_RATIO << 20))
-
-/* CLK_DIV_PERIC4 */
-#define SPI2_PRE_RATIO 0x2
-#define SPI1_PRE_RATIO 0x2
-#define SPI0_PRE_RATIO 0x2
-#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
- | (SPI1_PRE_RATIO << 16) \
- | (SPI0_PRE_RATIO << 8))
-
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x10666600
-#define CLK_DIV_DISP1_0_VAL 0x01050211
-
-#define APLL_FOUT (1 << 0)
-#define KPLL_FOUT (1 << 0)
-
-#define CLK_DIV_CPERI1_VAL 0x3f3f0000
-#endif
-
-struct mem_timings;
-
-/* Errors that we can encourter in low-level setup */
-enum {
- SETUP_ERR_OK,
- SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
- SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
-};
-
-/*
- * Memory variant specific initialization code for DDR3
- *
- * @param mem Memory timings for this memory type.
- * @param reset Reset DDR PHY during initialization.
- * @return 0 if ok, SETUP_ERR_... if there is a problem
- */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
-
-/* Memory variant specific initialization code for LPDDR3 */
-void lpddr3_mem_ctrl_init(void);
-
-/*
- * Configure ZQ I/O interface
- *
- * @param mem Memory timings for this memory type.
- * @param phy0_con16 Register address for dmc_phy0->phy_con16
- * @param phy1_con16 Register address for dmc_phy1->phy_con16
- * @param phy0_con17 Register address for dmc_phy0->phy_con17
- * @param phy1_con17 Register address for dmc_phy1->phy_con17
- * @return 0 if ok, -1 on error
- */
-int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
- uint32_t *phy1_con16, uint32_t *phy0_con17,
- uint32_t *phy1_con17);
-/*
- * Send NOP and MRS/EMRS Direct commands
- *
- * @param mem Memory timings for this memory type.
- * @param directcmd Register address for dmc_phy->directcmd
- */
-void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
-
-/*
- * Send PALL Direct commands
- *
- * @param mem Memory timings for this memory type.
- * @param directcmd Register address for dmc_phy->directcmd
- */
-void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
-
-/*
- * Reset the DLL. This function is common between DDR3 and LPDDR2.
- * However, the reset value is different. So we are passing a flag
- * ddr_mode to distinguish between LPDDR2 and DDR3.
- *
- * @param phycontrol0 Register address for dmc_phy->phycontrol0
- * @param ddr_mode Type of DDR memory
- */
-void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
-#endif
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
deleted file mode 100644
index 83e1dcf..0000000
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Lowlevel setup for EXYNOS5 based board
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/power.h>
-#include <asm/arch/tzpc.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pinmux.h>
-#include "common_setup.h"
-
-/* These are the things we can do during low-level init */
-enum {
- DO_WAKEUP = 1 << 0,
- DO_CLOCKS = 1 << 1,
- DO_MEM_RESET = 1 << 2,
- DO_UART = 1 << 3,
- DO_POWER = 1 << 4,
-};
-
-int do_lowlevel_init(void)
-{
- uint32_t reset_status;
- int actions = 0;
-
- arch_cpu_init();
-
- reset_status = get_reset_status();
-
- switch (reset_status) {
- case S5P_CHECK_SLEEP:
- actions = DO_CLOCKS | DO_WAKEUP;
- break;
- case S5P_CHECK_DIDLE:
- case S5P_CHECK_LPA:
- actions = DO_WAKEUP;
- break;
- default:
- /* This is a normal boot (not a wake from sleep) */
- actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
- }
-
- if (actions & DO_POWER)
- set_ps_hold_ctrl();
-
- if (actions & DO_CLOCKS) {
- system_clock_init();
- mem_ctrl_init(actions & DO_MEM_RESET);
- tzpc_init();
- }
-
- return actions & DO_WAKEUP;
-}
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
deleted file mode 100644
index 94d0297..0000000
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ /dev/null
@@ -1,894 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics.
- * Abhilash Kesavan <a.kesavan@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <asm/gpio.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/sromc.h>
-
-static void exynos5_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS5_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS5_GPIO_D00;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS5_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS5_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
- for (i = start; i < start + count; i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static void exynos5420_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS5420_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS5420_GPIO_A04;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS5420_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS5420_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
-
- for (i = start; i < start + count; i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static int exynos5_mmc_config(int peripheral, int flags)
-{
- int i, start, start_ext, gpio_func = 0;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS5_GPIO_C00;
- start_ext = EXYNOS5_GPIO_C10;
- gpio_func = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SDMMC1:
- start = EXYNOS5_GPIO_C20;
- start_ext = 0;
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS5_GPIO_C30;
- start_ext = EXYNOS5_GPIO_C43;
- gpio_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC3:
- start = EXYNOS5_GPIO_C40;
- start_ext = 0;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
- debug("SDMMC device %d does not support 8bit mode",
- peripheral);
- return -1;
- }
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i <= (start_ext + 3); i++) {
- gpio_cfg_pin(i, gpio_func);
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
- for (i = start; i < (start + 2); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- for (i = (start + 3); i <= (start + 6); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
-
- return 0;
-}
-
-static int exynos5420_mmc_config(int peripheral, int flags)
-{
- int i, start = 0, start_ext = 0;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS5420_GPIO_C00;
- start_ext = EXYNOS5420_GPIO_C30;
- break;
- case PERIPH_ID_SDMMC1:
- start = EXYNOS5420_GPIO_C10;
- start_ext = EXYNOS5420_GPIO_D14;
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS5420_GPIO_C20;
- start_ext = 0;
- break;
- default:
- start = 0;
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
- debug("SDMMC device %d does not support 8bit mode",
- peripheral);
- return -1;
- }
-
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i <= (start_ext + 3); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
-
- for (i = start; i < (start + 3); i++) {
- /*
- * MMC0 is intended to be used for eMMC. The
- * card detect pin is used as a VDDEN signal to
- * power on the eMMC. The 5420 iROM makes
- * this same assumption.
- */
- if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
-#ifndef CONFIG_SPL_BUILD
- gpio_request(i, "sdmmc0_vdden");
-#endif
- gpio_set_value(i, 1);
- gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
- } else {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
-
- for (i = (start + 3); i <= (start + 6); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
-
- return 0;
-}
-
-static void exynos5_sromc_config(int flags)
-{
- int i;
-
- /*
- * SROM:CS1 and EBI
- *
- * GPY0[0] SROM_CSn[0]
- * GPY0[1] SROM_CSn[1](2)
- * GPY0[2] SROM_CSn[2]
- * GPY0[3] SROM_CSn[3]
- * GPY0[4] EBI_OEn(2)
- * GPY0[5] EBI_EEn(2)
- *
- * GPY1[0] EBI_BEn[0](2)
- * GPY1[1] EBI_BEn[1](2)
- * GPY1[2] SROM_WAIT(2)
- * GPY1[3] EBI_DATA_RDn(2)
- */
- gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
- S5P_GPIO_FUNC(2));
- gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
- gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
-
- for (i = 0; i < 4; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
-
- /*
- * EBI: 8 Addrss Lines
- *
- * GPY3[0] EBI_ADDR[0](2)
- * GPY3[1] EBI_ADDR[1](2)
- * GPY3[2] EBI_ADDR[2](2)
- * GPY3[3] EBI_ADDR[3](2)
- * GPY3[4] EBI_ADDR[4](2)
- * GPY3[5] EBI_ADDR[5](2)
- * GPY3[6] EBI_ADDR[6](2)
- * GPY3[7] EBI_ADDR[7](2)
- *
- * EBI: 16 Data Lines
- *
- * GPY5[0] EBI_DATA[0](2)
- * GPY5[1] EBI_DATA[1](2)
- * GPY5[2] EBI_DATA[2](2)
- * GPY5[3] EBI_DATA[3](2)
- * GPY5[4] EBI_DATA[4](2)
- * GPY5[5] EBI_DATA[5](2)
- * GPY5[6] EBI_DATA[6](2)
- * GPY5[7] EBI_DATA[7](2)
- *
- * GPY6[0] EBI_DATA[8](2)
- * GPY6[1] EBI_DATA[9](2)
- * GPY6[2] EBI_DATA[10](2)
- * GPY6[3] EBI_DATA[11](2)
- * GPY6[4] EBI_DATA[12](2)
- * GPY6[5] EBI_DATA[13](2)
- * GPY6[6] EBI_DATA[14](2)
- * GPY6[7] EBI_DATA[15](2)
- */
- for (i = 0; i < 8; i++) {
- gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
-
- gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
-
- gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
- }
-}
-
-static void exynos5_i2c_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
- break;
- }
-}
-
-static void exynos5420_i2c_config(int peripheral)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C8:
- gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C9:
- gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C10:
- gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
- break;
- }
-}
-
-static void exynos5_i2s_config(int peripheral)
-{
- int i;
-
- switch (peripheral) {
- case PERIPH_ID_I2S0:
- for (i = 0; i < 5; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
- break;
- case PERIPH_ID_I2S1:
- for (i = 0; i < 5; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
- break;
- }
-}
-
-void exynos5_spi_config(int peripheral)
-{
- int cfg = 0, pin = 0, i;
-
- switch (peripheral) {
- case PERIPH_ID_SPI0:
- cfg = S5P_GPIO_FUNC(0x2);
- pin = EXYNOS5_GPIO_A20;
- break;
- case PERIPH_ID_SPI1:
- cfg = S5P_GPIO_FUNC(0x2);
- pin = EXYNOS5_GPIO_A24;
- break;
- case PERIPH_ID_SPI2:
- cfg = S5P_GPIO_FUNC(0x5);
- pin = EXYNOS5_GPIO_B11;
- break;
- case PERIPH_ID_SPI3:
- cfg = S5P_GPIO_FUNC(0x2);
- pin = EXYNOS5_GPIO_F10;
- break;
- case PERIPH_ID_SPI4:
- for (i = 0; i < 2; i++) {
- gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
- }
- break;
- }
- if (peripheral != PERIPH_ID_SPI4) {
- for (i = pin; i < pin + 4; i++)
- gpio_cfg_pin(i, cfg);
- }
-}
-
-void exynos5420_spi_config(int peripheral)
-{
- int cfg, pin, i;
-
- switch (peripheral) {
- case PERIPH_ID_SPI0:
- pin = EXYNOS5420_GPIO_A20;
- cfg = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SPI1:
- pin = EXYNOS5420_GPIO_A24;
- cfg = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SPI2:
- pin = EXYNOS5420_GPIO_B11;
- cfg = S5P_GPIO_FUNC(0x5);
- break;
- case PERIPH_ID_SPI3:
- pin = EXYNOS5420_GPIO_F10;
- cfg = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SPI4:
- cfg = 0;
- pin = 0;
- break;
- default:
- cfg = 0;
- pin = 0;
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
-
- if (peripheral != PERIPH_ID_SPI4) {
- for (i = pin; i < pin + 4; i++)
- gpio_cfg_pin(i, cfg);
- } else {
- for (i = 0; i < 2; i++) {
- gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
- S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
- S5P_GPIO_FUNC(0x4));
- }
- }
-}
-
-static int exynos5_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos5_uart_config(peripheral);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- return exynos5_mmc_config(peripheral, flags);
- case PERIPH_ID_SROMC:
- exynos5_sromc_config(flags);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- exynos5_i2c_config(peripheral, flags);
- break;
- case PERIPH_ID_I2S0:
- case PERIPH_ID_I2S1:
- exynos5_i2s_config(peripheral);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- exynos5_spi_config(peripheral);
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static int exynos5420_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos5420_uart_config(peripheral);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- return exynos5420_mmc_config(peripheral, flags);
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- exynos5420_spi_config(peripheral);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- case PERIPH_ID_I2C8:
- case PERIPH_ID_I2C9:
- case PERIPH_ID_I2C10:
- exynos5420_i2c_config(peripheral);
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static void exynos4_i2c_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
- break;
- }
-}
-
-static int exynos4_mmc_config(int peripheral, int flags)
-{
- int i, start = 0, start_ext = 0;
- unsigned int func, ext_func;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS4_GPIO_K00;
- start_ext = EXYNOS4_GPIO_K13;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS4_GPIO_K20;
- start_ext = EXYNOS4_GPIO_K33;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC4:
- start = EXYNOS4_GPIO_K00;
- start_ext = EXYNOS4_GPIO_K13;
- func = S5P_GPIO_FUNC(0x3);
- ext_func = S5P_GPIO_FUNC(0x4);
- break;
- default:
- return -1;
- }
- for (i = start; i < (start + 7); i++) {
- if (i == (start + 2))
- continue;
- gpio_cfg_pin(i, func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- /* SDMMC2 do not use 8bit mode at exynos4 */
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, ext_func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
-
- return 0;
-}
-
-static void exynos4_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS4_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS4_GPIO_A04;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS4_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS4_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
- for (i = start; i < (start + count); i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static void exynos4x12_i2c_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
- break;
- }
-}
-
-static int exynos4x12_mmc_config(int peripheral, int flags)
-{
- int i, start = 0, start_ext = 0;
- unsigned int func, ext_func;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS4X12_GPIO_K00;
- start_ext = EXYNOS4X12_GPIO_K13;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS4X12_GPIO_K20;
- start_ext = EXYNOS4X12_GPIO_K33;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC4:
- start = EXYNOS4X12_GPIO_K00;
- start_ext = EXYNOS4X12_GPIO_K13;
- func = S5P_GPIO_FUNC(0x3);
- ext_func = S5P_GPIO_FUNC(0x4);
- break;
- default:
- return -1;
- }
- for (i = start; i < (start + 7); i++) {
- if (i == (start + 2))
- continue;
- gpio_cfg_pin(i, func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, ext_func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
-
- return 0;
-}
-
-static void exynos4x12_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS4X12_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS4X12_GPIO_A04;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS4X12_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS4X12_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
- for (i = start; i < (start + count); i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static int exynos4_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos4_uart_config(peripheral);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- exynos4_i2c_config(peripheral, flags);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC4:
- return exynos4_mmc_config(peripheral, flags);
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC3:
- debug("SDMMC device %d not implemented\n", peripheral);
- return -1;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static int exynos4x12_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos4x12_uart_config(peripheral);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- exynos4x12_i2c_config(peripheral, flags);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC4:
- return exynos4x12_mmc_config(peripheral, flags);
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC3:
- debug("SDMMC device %d not implemented\n", peripheral);
- return -1;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-int exynos_pinmux_config(int peripheral, int flags)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_pinmux_config(peripheral, flags);
- else if (proid_is_exynos5250())
- return exynos5_pinmux_config(peripheral, flags);
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_pinmux_config(peripheral, flags);
- else
- return exynos4_pinmux_config(peripheral, flags);
- }
-
- debug("pinmux functionality not supported\n");
-
- return -1;
-}
-
-#ifdef CONFIG_OF_CONTROL
-static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
-{
- int err;
- u32 cell[3];
-
- err = fdtdec_get_int_array(blob, node, "interrupts", cell,
- ARRAY_SIZE(cell));
- if (err) {
- debug(" invalid peripheral id\n");
- return PERIPH_ID_NONE;
- }
-
- return cell[1];
-}
-
-static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
-{
- int err;
- u32 cell[3];
-
- err = fdtdec_get_int_array(blob, node, "interrupts", cell,
- ARRAY_SIZE(cell));
- if (err)
- return PERIPH_ID_NONE;
-
- return cell[1];
-}
-
-int pinmux_decode_periph_id(const void *blob, int node)
-{
- if (cpu_is_exynos5())
- return exynos5_pinmux_decode_periph_id(blob, node);
- else if (cpu_is_exynos4())
- return exynos4_pinmux_decode_periph_id(blob, node);
-
- return PERIPH_ID_NONE;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
deleted file mode 100644
index 1520d64..0000000
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/power.h>
-
-static void exynos4_mipi_phy_control(unsigned int dev_index,
- unsigned int enable)
-{
- struct exynos4_power *pmu =
- (struct exynos4_power *)samsung_get_base_power();
- unsigned int addr, cfg = 0;
-
- if (dev_index == 0)
- addr = (unsigned int)&pmu->mipi_phy0_control;
- else
- addr = (unsigned int)&pmu->mipi_phy1_control;
-
-
- cfg = readl(addr);
- if (enable)
- cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
- else
- cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
-
- writel(cfg, addr);
-}
-
-void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
-{
- if (cpu_is_exynos4())
- exynos4_mipi_phy_control(dev_index, enable);
-}
-
-void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBHOST_PHY */
- setbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- } else {
- /* Disabling USBHOST_PHY */
- clrbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- }
-}
-
-void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
-{
- struct exynos4412_power *power =
- (struct exynos4412_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBHOST_PHY */
- setbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- setbits_le32(&power->hsic1_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- setbits_le32(&power->hsic2_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- } else {
- /* Disabling USBHOST_PHY */
- clrbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- clrbits_le32(&power->hsic1_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- clrbits_le32(&power->hsic2_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- }
-}
-
-void set_usbhost_phy_ctrl(unsigned int enable)
-{
- if (cpu_is_exynos5())
- exynos5_set_usbhost_phy_ctrl(enable);
- else if (cpu_is_exynos4())
- if (proid_is_exynos4412())
- exynos4412_set_usbhost_phy_ctrl(enable);
-}
-
-static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBDRD_PHY */
- setbits_le32(&power->usbdrd_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- } else {
- /* Disabling USBDRD_PHY */
- clrbits_le32(&power->usbdrd_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- }
-}
-
-void set_usbdrd_phy_ctrl(unsigned int enable)
-{
- if (cpu_is_exynos5())
- exynos5_set_usbdrd_phy_ctrl(enable);
-}
-
-static void exynos5_dp_phy_control(unsigned int enable)
-{
- unsigned int cfg;
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- cfg = readl(&power->dptx_phy_control);
- if (enable)
- cfg |= EXYNOS_DP_PHY_ENABLE;
- else
- cfg &= ~EXYNOS_DP_PHY_ENABLE;
-
- writel(cfg, &power->dptx_phy_control);
-}
-
-void set_dp_phy_ctrl(unsigned int enable)
-{
- if (cpu_is_exynos5())
- exynos5_dp_phy_control(enable);
-}
-
-static void exynos5_set_ps_hold_ctrl(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- /* Set PS-Hold high */
- setbits_le32(&power->ps_hold_control,
- EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
-}
-
-/*
- * Set ps_hold data driving value high
- * This enables the machine to stay powered on
- * after the initial power-on condition goes away
- * (e.g. power button).
- */
-void set_ps_hold_ctrl(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_ps_hold_ctrl();
-}
-
-
-static void exynos5_set_xclkout(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- /* use xxti for xclk out */
- clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
- PMU_DEBUG_XXTI);
-}
-
-void set_xclkout(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_xclkout();
-}
-
-/* Enables hardware tripping to power off the system when TMU fails */
-void set_hw_thermal_trip(void)
-{
- if (cpu_is_exynos5()) {
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
- setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
- }
-}
-
-static uint32_t exynos5_get_reset_status(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- return power->inform1;
-}
-
-static uint32_t exynos4_get_reset_status(void)
-{
- struct exynos4_power *power =
- (struct exynos4_power *)samsung_get_base_power();
-
- return power->inform1;
-}
-
-uint32_t get_reset_status(void)
-{
- if (cpu_is_exynos5())
- return exynos5_get_reset_status();
- else
- return exynos4_get_reset_status();
-}
-
-static void exynos5_power_exit_wakeup(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
- typedef void (*resume_func)(void);
-
- ((resume_func)power->inform0)();
-}
-
-static void exynos4_power_exit_wakeup(void)
-{
- struct exynos4_power *power =
- (struct exynos4_power *)samsung_get_base_power();
- typedef void (*resume_func)(void);
-
- ((resume_func)power->inform0)();
-}
-
-void power_exit_wakeup(void)
-{
- if (cpu_is_exynos5())
- exynos5_power_exit_wakeup();
- else
- exynos4_power_exit_wakeup();
-}
-
-unsigned int get_boot_mode(void)
-{
- unsigned int om_pin = samsung_get_base_power();
-
- return readl(om_pin) & OM_PIN_MASK;
-}
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
deleted file mode 100644
index 8c7d7d8..0000000
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-enum l2_cache_params {
- CACHE_TAG_RAM_SETUP = (1 << 9),
- CACHE_DATA_RAM_SETUP = (1 << 5),
- CACHE_TAG_RAM_LATENCY = (2 << 6),
- CACHE_DATA_RAM_LATENCY = (2 << 0)
-};
-
-void reset_cpu(ulong addr)
-{
- writel(0x1, samsung_get_base_swreset());
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-/*
- * Set L2 cache parameters
- */
-static void exynos5_set_l2cache_params(void)
-{
- unsigned int val = 0;
-
- asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
-
- val |= CACHE_TAG_RAM_SETUP |
- CACHE_DATA_RAM_SETUP |
- CACHE_TAG_RAM_LATENCY |
- CACHE_DATA_RAM_LATENCY;
-
- asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
-}
-
-/*
- * Sets L2 cache related parameters before enabling data cache
- */
-void v7_outer_cache_enable(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_l2cache_params();
-}
-#endif
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
deleted file mode 100644
index bc237c9..0000000
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/power.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/spi.h>
-
-#include "common_setup.h"
-#include "clock_init.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Index into irom ptr table */
-enum index {
- MMC_INDEX,
- EMMC44_INDEX,
- EMMC44_END_INDEX,
- SPI_INDEX,
- USB_INDEX,
-};
-
-/* IROM Function Pointers Table */
-u32 irom_ptr_table[] = {
- [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
- [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
- [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
- -EMMC4.4 end boot operation */
- [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
- [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
- };
-
-void *get_irom_func(int index)
-{
- return (void *)*(u32 *)irom_ptr_table[index];
-}
-
-#ifdef CONFIG_USB_BOOTING
-/*
- * Set/clear program flow prediction and return the previous state.
- */
-static int config_branch_prediction(int set_cr_z)
-{
- unsigned int cr;
-
- /* System Control Register: 11th bit Z Branch prediction enable */
- cr = get_cr();
- set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
-
- return cr & CR_Z;
-}
-#endif
-
-#ifdef CONFIG_SPI_BOOTING
-static void spi_rx_tx(struct exynos_spi *regs, int todo,
- void *dinp, void const *doutp, int i)
-{
- uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
- int rx_lvl, tx_lvl;
- uint out_bytes, in_bytes;
-
- out_bytes = todo;
- in_bytes = todo;
- setbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
- writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
-
- while (in_bytes) {
- uint32_t spi_sts;
- int temp;
-
- spi_sts = readl(®s->spi_sts);
- rx_lvl = ((spi_sts >> 15) & 0x7f);
- tx_lvl = ((spi_sts >> 6) & 0x7f);
- while (tx_lvl < 32 && out_bytes) {
- temp = 0xffffffff;
- writel(temp, ®s->tx_data);
- out_bytes -= 4;
- tx_lvl += 4;
- }
- while (rx_lvl >= 4 && in_bytes) {
- temp = readl(®s->rx_data);
- if (rxp)
- *rxp++ = temp;
- in_bytes -= 4;
- rx_lvl -= 4;
- }
- }
-}
-
-/*
- * Copy uboot from spi flash to RAM
- *
- * @parma uboot_size size of u-boot to copy
- * @param uboot_addr address in u-boot to copy
- */
-static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
-{
- int upto, todo;
- int i, timeout = 100;
- struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
-
- set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
- /* set the spi1 GPIO */
- exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
-
- /* set pktcnt and enable it */
- writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
- /* set FB_CLK_SEL */
- writel(SPI_FB_DELAY_180, ®s->fb_clk);
- /* set CH_WIDTH and BUS_WIDTH as word */
- setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
- SPI_MODE_BUS_WIDTH_WORD);
- clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
-
- /* clear rx and tx channel if set priveously */
- clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
-
- setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN |
- SPI_RX_BYTE_SWAP |
- SPI_RX_HWORD_SWAP);
-
- /* do a soft reset */
- setbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
-
- /* now set rx and tx channel ON */
- setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
- clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
-
- /* Send read instruction (0x3h) followed by a 24 bit addr */
- writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data);
-
- /* waiting for TX done */
- while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) {
- if (!timeout) {
- debug("SPI TIMEOUT\n");
- break;
- }
- timeout--;
- }
-
- for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
- todo = min(uboot_size - upto, (unsigned int)(1 << 15));
- spi_rx_tx(regs, todo, (void *)(uboot_addr),
- (void *)(SPI_FLASH_UBOOT_POS), i);
- }
-
- setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
-
- /*
- * Let put controller mode to BYTE as
- * SPI driver does not support WORD mode yet
- */
- clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
- SPI_MODE_BUS_WIDTH_WORD);
- writel(0, ®s->swap_cfg);
-
- /*
- * Flush spi tx, rx fifos and reset the SPI controller
- * and clear rx/tx channel
- */
- clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
-}
-#endif
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
- unsigned int bootmode = BOOT_MODE_OM;
-
- u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
- u32 offset = 0, size = 0;
-#ifdef CONFIG_SPI_BOOTING
- struct spl_machine_param *param = spl_get_machine_params();
-#endif
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
- void (*end_bootop_from_emmc)(void);
-#endif
-#ifdef CONFIG_USB_BOOTING
- int is_cr_z_set;
- unsigned int sec_boot_check;
-
- /*
- * Note that older hardware (before Exynos5800) does not expect any
- * arguments, but it does not hurt to pass them, so a common function
- * prototype is used.
- */
- u32 (*usb_copy)(u32 num_of_block, u32 *dst);
-
- /* Read iRAM location to check for secondary USB boot mode */
- sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
- if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
- bootmode = BOOT_MODE_USB;
-#endif
-
- if (bootmode == BOOT_MODE_OM)
- bootmode = get_boot_mode();
-
- switch (bootmode) {
-#ifdef CONFIG_SPI_BOOTING
- case BOOT_MODE_SERIAL:
- /* Customised function to copy u-boot from SF */
- exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
- break;
-#endif
- case BOOT_MODE_SD:
- offset = BL2_START_OFFSET;
- size = BL2_SIZE_BLOC_COUNT;
- copy_bl2 = get_irom_func(MMC_INDEX);
- break;
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- case BOOT_MODE_EMMC:
- /* Set the FSYS1 clock divisor value for EMMC boot */
- emmc_boot_clk_div_set();
-
- copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
- end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
-
- copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
- end_bootop_from_emmc();
- break;
-#endif
-#ifdef CONFIG_USB_BOOTING
- case BOOT_MODE_USB:
- /*
- * iROM needs program flow prediction to be disabled
- * before copy from USB device to RAM
- */
- is_cr_z_set = config_branch_prediction(0);
- usb_copy = get_irom_func(USB_INDEX);
- usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
- config_branch_prediction(is_cr_z_set);
- break;
-#endif
- default:
- break;
- }
-
- if (copy_bl2)
- copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
-}
-
-void memzero(void *s, size_t n)
-{
- char *ptr = s;
- size_t i;
-
- for (i = 0; i < n; i++)
- *ptr++ = '\0';
-}
-
-/**
- * Set up the U-Boot global_data pointer
- *
- * This sets the address of the global data, and sets up basic values.
- *
- * @param gdp Value to give to gd
- */
-static void setup_global_data(gd_t *gdp)
-{
- gd = gdp;
- memzero((void *)gd, sizeof(gd_t));
- gd->flags |= GD_FLG_RELOC;
- gd->baudrate = CONFIG_BAUDRATE;
- gd->have_console = 1;
-}
-
-void board_init_f(unsigned long bootflag)
-{
- __aligned(8) gd_t local_gd;
- __attribute__((noreturn)) void (*uboot)(void);
-
- setup_global_data(&local_gd);
-
- if (do_lowlevel_init())
- power_exit_wakeup();
-
- copy_uboot_to_ram();
-
- /* Jump to U-Boot image */
- uboot = (void *)CONFIG_SYS_TEXT_BASE;
- (*uboot)();
- /* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- /* Function attribute is no-return */
- /* This Function never executes */
- while (1)
- ;
-}
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c
deleted file mode 100644
index ad12445..0000000
--- a/arch/arm/cpu/armv7/exynos/system.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/system.h>
-
-static void exynos5_set_usbhost_mode(unsigned int mode)
-{
- struct exynos5_sysreg *sysreg =
- (struct exynos5_sysreg *)samsung_get_base_sysreg();
-
- /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
- if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
- setbits_le32(&sysreg->usb20phy_cfg,
- USB20_PHY_CFG_HOST_LINK_EN);
- } else {
- clrbits_le32(&sysreg->usb20phy_cfg,
- USB20_PHY_CFG_HOST_LINK_EN);
- }
-}
-
-void set_usbhost_mode(unsigned int mode)
-{
- if (cpu_is_exynos5())
- exynos5_set_usbhost_mode(mode);
-}
-
-static void exynos4_set_system_display(void)
-{
- struct exynos4_sysreg *sysreg =
- (struct exynos4_sysreg *)samsung_get_base_sysreg();
- unsigned int cfg = 0;
-
- /*
- * system register path set
- * 0: MIE/MDNIE
- * 1: FIMD Bypass
- */
- cfg = readl(&sysreg->display_ctrl);
- cfg |= (1 << 1);
- writel(cfg, &sysreg->display_ctrl);
-}
-
-static void exynos5_set_system_display(void)
-{
- struct exynos5_sysreg *sysreg =
- (struct exynos5_sysreg *)samsung_get_base_sysreg();
- unsigned int cfg = 0;
-
- /*
- * system register path set
- * 0: MIE/MDNIE
- * 1: FIMD Bypass
- */
- cfg = readl(&sysreg->disp1blk_cfg);
- cfg |= (1 << 15);
- writel(cfg, &sysreg->disp1blk_cfg);
-}
-
-void set_system_display_ctrl(void)
-{
- if (cpu_is_exynos4())
- exynos4_set_system_display();
- else
- exynos5_set_system_display();
-}
diff --git a/arch/arm/cpu/armv7/exynos/tzpc.c b/arch/arm/cpu/armv7/exynos/tzpc.c
deleted file mode 100644
index 395077c..0000000
--- a/arch/arm/cpu/armv7/exynos/tzpc.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Lowlevel setup for SMDK5250 board based on S5PC520
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/tzpc.h>
-#include <asm/io.h>
-
-/* Setting TZPC[TrustZone Protection Controller] */
-void tzpc_init(void)
-{
- struct exynos_tzpc *tzpc;
- unsigned int addr, start = 0, end = 0;
-
- start = samsung_get_base_tzpc();
-
- if (cpu_is_exynos5())
- end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
- else if (cpu_is_exynos4())
- end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
-
- for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
- tzpc = (struct exynos_tzpc *)addr;
-
- if (addr == start)
- writel(R0SIZE, &tzpc->r0size);
-
- writel(DECPROTXSET, &tzpc->decprot0set);
- writel(DECPROTXSET, &tzpc->decprot1set);
-
- if (cpu_is_exynos5() && (addr == end))
- break;
-
- writel(DECPROTXSET, &tzpc->decprot2set);
- writel(DECPROTXSET, &tzpc->decprot3set);
- }
-}
diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile
deleted file mode 100644
index 876099d..0000000
--- a/arch/arm/cpu/armv7/highbank/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := timer.o
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
deleted file mode 100644
index d56bf21..0000000
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- *
- * Based on arm926ejs/mx27/timer.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-armv7/systimer.h>
-
-#undef SYSTIMER_BASE
-#define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
-
-static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
-
-/*
- * Start the timer
- */
-int timer_init(void)
-{
- /*
- * Setup timer0
- */
- writel(0, &systimer_base->timer0control);
- writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
- writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
- writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
- &systimer_base->timer0control);
-
- return 0;
-
-}
diff --git a/arch/arm/cpu/armv7/iproc-common/Makefile b/arch/arm/cpu/armv7/iproc-common/Makefile
index c071a17..6f5c837 100644
--- a/arch/arm/cpu/armv7/iproc-common/Makefile
+++ b/arch/arm/cpu/armv7/iproc-common/Makefile
@@ -1,8 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2014 Broadcom Corporation.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += armpll.o
obj-y += hwinit-common.o
diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c
index 49b61bf..efa3d9e 100644
--- a/arch/arm/cpu/armv7/iproc-common/armpll.c
+++ b/arch/arm/cpu/armv7/iproc-common/armpll.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
index 7131524..8bf06a3 100644
--- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/iproc-common/timer.c b/arch/arm/cpu/armv7/iproc-common/timer.c
index 373d8ec..aaa767d 100644
--- a/arch/arm/cpu/armv7/iproc-common/timer.c
+++ b/arch/arm/cpu/armv7/iproc-common/timer.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
deleted file mode 100644
index 134ae87..0000000
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-if ARCH_KEYSTONE
-
-choice
- prompt "TI Keystone board select"
-
-config TARGET_K2HK_EVM
- bool "TI Keystone 2 Kepler/Hawking EVM"
-
-config TARGET_K2E_EVM
- bool "TI Keystone 2 Edison EVM"
-
-config TARGET_K2L_EVM
- bool "TI Keystone 2 Lamar EVM"
-
-endchoice
-
-config SYS_SOC
- default "keystone"
-
-source "board/ti/ks2_evm/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
deleted file mode 100644
index ed030db..0000000
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2012-2014
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += init.o
-obj-y += psc.o
-obj-y += clock.o
-obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
-obj-$(CONFIG_SOC_K2E) += clock-k2e.o
-obj-$(CONFIG_SOC_K2L) += clock-k2l.o
-obj-y += cmd_clock.o
-obj-y += cmd_mon.o
-obj-y += msmc.o
-obj-y += ddr3.o cmd_ddr3.o
-obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
deleted file mode 100644
index 31f6661..0000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2e.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Keystone2: get clk rate for K2E
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD850,
- SPD1000,
- SPD1250,
- SPD1350,
- SPD1400,
- SPD1500,
- SPD1400,
- SPD1350,
- SPD1250,
- SPD1000,
- SPD850,
- SPD800
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll: pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(KS2_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = KS2_PASSPLLCTL0;
- break;
- case DDR3_PLL:
- ret = external_clk[ddr3_clk];
- reg = KS2_DDR3APLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
-
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
deleted file mode 100644
index 1591960..0000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Keystone2: get clk rate for K2HK
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
- [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
- [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll: pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(KS2_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = KS2_PASSPLLCTL0;
- break;
- case TETRIS_PLL:
- ret = external_clk[tetris_clk];
- reg = KS2_ARMPLLCTL0;
- break;
- case DDR3A_PLL:
- ret = external_clk[ddr3a_clk];
- reg = KS2_DDR3APLLCTL0;
- break;
- case DDR3B_PLL:
- ret = external_clk[ddr3b_clk];
- reg = KS2_DDR3BPLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
-
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
- case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
- case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
deleted file mode 100644
index 1c5e4d5..0000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2l.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Keystone2: get clk rate for K2L
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll: pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(KS2_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = KS2_PASSPLLCTL0;
- break;
- case TETRIS_PLL:
- ret = external_clk[tetris_clk];
- reg = KS2_ARMPLLCTL0;
- break;
- case DDR3_PLL:
- ret = external_clk[ddr3_clk];
- reg = KS2_DDR3APLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
- case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
deleted file mode 100644
index d13fbc1..0000000
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Keystone2: pll initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-#define MAX_SPEEDS 13
-
-static void wait_for_completion(const struct pll_init_data *data)
-{
- int i;
- for (i = 0; i < 100; i++) {
- sdelay(450);
- if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
- break;
- }
-}
-
-void init_pll(const struct pll_init_data *data)
-{
- u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
-
- pllm = data->pll_m - 1;
- plld = (data->pll_d - 1) & PLL_DIV_MASK;
- pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
-
- if (data->pll == MAIN_PLL) {
- /* The requered delay before main PLL configuration */
- sdelay(210000);
-
- tmp = pllctl_reg_read(data->pll, secctl);
-
- if (tmp & (PLLCTL_BYPASS)) {
- setbits_le32(keystone_pll_regs[data->pll].reg1,
- BIT(MAIN_ENSAT_OFFSET));
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
-
- pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- sdelay(21000);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- } else {
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
- }
-
- pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
-
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLLM_MULT_HI_SMASK, (pllm << 6));
-
- /* Set the BWADJ (12 bit field) */
- tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_BWADJ_LO_SMASK,
- (tmp_ctl << PLL_BWADJ_LO_SHIFT));
- clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
- PLL_BWADJ_HI_MASK,
- (tmp_ctl >> 8));
-
- /*
- * Set the pll divider (6 bit field) *
- * PLLD[5:0] is located in MAINPLLCTL0
- */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_DIV_MASK, plld);
-
- /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
- pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
- (pllod << PLL_CLKOD_SHIFT));
- wait_for_completion(data);
-
- pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
- pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
- pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
- pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
- pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
-
- pllctl_reg_setbits(data->pll, alnctl, 0x1f);
-
- /*
- * Set GOSET bit in PLLCMD to initiate the GO operation
- * to change the divide
- */
- pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
- sdelay(1500); /* wait for the phase adj */
- wait_for_completion(data);
-
- /* Reset PLL */
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
-
- pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
-
- tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-
-#ifndef CONFIG_SOC_K2E
- } else if (data->pll == TETRIS_PLL) {
- bwadj = pllm >> 1;
- /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
- * only applicable for Kepler
- */
- clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
- /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(keystone_pll_regs[data->pll].reg1 ,
- PLL_PLLRST | PLLCTL_ENSAT);
-
- /*
- * 3 Program PLLM and PLLD in PLLCTL0 register
- * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
- * PLLCTL1 register. BWADJ value must be set
- * to ((PLLM + 1) >> 1) – 1)
- */
- tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << 6) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
- /*
- * 5 Wait for at least 5 us based on the reference
- * clock (PLL reset time)
- */
- sdelay(21000); /* Wait for a minimum of 7 us*/
-
- /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
- /*
- * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
- * (PLL lock time)
- */
- sdelay(105000);
- /* 8 disable bypass */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
- * only applicable for Kepler
- */
- setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
- } else {
- setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
- /*
- * process keeps state of Bypass bit while programming
- * all other DDR PLL settings
- */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
- tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
-
- /*
- * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
- * bypass disabled
- */
- bwadj = pllm >> 1;
- tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << PLL_MULT_SHIFT) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
-
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-
- /* Reset bit: bit 14 for both DDR3 & PASS PLL */
- tmp = PLL_PLLRST;
- /* Set RESET bit = 1 */
- setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- /* Wait for a minimum of 7 us*/
- sdelay(21000);
- /* Clear RESET bit */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- sdelay(105000);
-
- /* clear BYPASS (Enable PLL Mode) */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- }
-
- /*
- * This is required to provide a delay between multiple
- * consequent PPL configurations
- */
- sdelay(210000);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
-
-static int get_max_speed(u32 val, int *speeds)
-{
- int j;
-
- if (!val)
- return speeds[0];
-
- for (j = 1; j < MAX_SPEEDS; j++) {
- if (val == 1)
- return speeds[j];
- val >>= 1;
- }
-
- return SPD800;
-}
-
-#ifdef CONFIG_SOC_K2HK
-static u32 read_efuse_bootrom(void)
-{
- return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
- __raw_readl(KS2_REV1_DEVSPEED);
-}
-#else
-static inline u32 read_efuse_bootrom(void)
-{
- return __raw_readl(KS2_EFUSE_BOOTROM);
-}
-#endif
-
-inline int get_max_dev_speed(void)
-{
- return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
-}
-
-#ifndef CONFIG_SOC_K2E
-inline int get_max_arm_speed(void)
-{
- return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
-}
-#endif
-
-void pass_pll_pa_clk_enable(void)
-{
- u32 reg;
-
- reg = readl(keystone_pll_regs[PASS_PLL].reg1);
-
- reg |= PLLCTL_PAPLL;
- writel(reg, keystone_pll_regs[PASS_PLL].reg1);
-
- /* wait till clock is enabled */
- sdelay(15000);
-}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
deleted file mode 100644
index af1b701..0000000
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * keystone2: commands for clocks
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/psc_defs.h>
-
-struct pll_init_data cmd_pll_data = {
- .pll = MAIN_PLL,
- .pll_m = 16,
- .pll_d = 1,
- .pll_od = 2,
-};
-
-int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 5)
- goto pll_cmd_usage;
-
- if (strncmp(argv[1], "pa", 2) == 0)
- cmd_pll_data.pll = PASS_PLL;
-#ifndef CONFIG_SOC_K2E
- else if (strncmp(argv[1], "arm", 3) == 0)
- cmd_pll_data.pll = TETRIS_PLL;
-#endif
-#ifdef CONFIG_SOC_K2HK
- else if (strncmp(argv[1], "ddr3a", 5) == 0)
- cmd_pll_data.pll = DDR3A_PLL;
- else if (strncmp(argv[1], "ddr3b", 5) == 0)
- cmd_pll_data.pll = DDR3B_PLL;
-#else
- else if (strncmp(argv[1], "ddr3", 4) == 0)
- cmd_pll_data.pll = DDR3_PLL;
-#endif
- else
- goto pll_cmd_usage;
-
- cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
- cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
- cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
-
- printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
- cmd_pll_data.pll, cmd_pll_data.pll_m,
- cmd_pll_data.pll_d, cmd_pll_data.pll_od);
- init_pll(&cmd_pll_data);
-
- return 0;
-
-pll_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- pllset, 5, 0, do_pll_cmd,
- "set pll multiplier and pre divider",
- PLLSET_CMD_LIST " <mult> <div> <OD>\n"
-);
-
-int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int clk;
- unsigned int freq;
-
- if (argc != 2)
- goto getclk_cmd_usage;
-
- clk = simple_strtoul(argv[1], NULL, 10);
-
- freq = clk_get_rate(clk);
- printf("clock index [%d] - frequency %u\n", clk, freq);
- return 0;
-
-getclk_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- getclk, 2, 0, do_getclk_cmd,
- "get clock rate",
- "<clk index>\n"
- "The indexes for clocks:\n"
- CLOCK_INDEXES_LIST
-);
-
-int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int psc_module;
- int res;
-
- if (argc != 3)
- goto psc_cmd_usage;
-
- psc_module = simple_strtoul(argv[1], NULL, 10);
- if (strcmp(argv[2], "en") == 0) {
- res = psc_enable_module(psc_module);
- printf("psc_enable_module(%d) - %s\n", psc_module,
- (res) ? "ERROR" : "OK");
- return 0;
- }
-
- if (strcmp(argv[2], "di") == 0) {
- res = psc_disable_module(psc_module);
- printf("psc_disable_module(%d) - %s\n", psc_module,
- (res) ? "ERROR" : "OK");
- return 0;
- }
-
- if (strcmp(argv[2], "domain") == 0) {
- res = psc_disable_domain(psc_module);
- printf("psc_disable_domain(%d) - %s\n", psc_module,
- (res) ? "ERROR" : "OK");
- return 0;
- }
-
-psc_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- psc, 3, 0, do_psc_cmd,
- "<enable/disable psc module os disable domain>",
- "<mod/domain index> <en|di|domain>\n"
- "Intended to control Power and Sleep Controller (PSC) domains and\n"
- "modules. The module or domain index exectly corresponds to ones\n"
- "listed in official TRM. For instance, to enable MSMC RAM clock\n"
- "domain use command: psc 14 en.\n"
-);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
deleted file mode 100644
index ea78ad8..0000000
--- a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Keystone2: DDR3 test commands
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr3.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
-
-#define DDR_REMAP_ADDR 0x80000000
-#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
-
-#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
- CONFIG_STACKSIZE) >> 17) - 2)
-
-#define DDR_TEST_BURST_SIZE 1024
-
-static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
-{
- u32 index_start, value, index;
-
- index_start = start_address;
-
- while (1) {
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel(index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- if (quick)
- continue;
-
- /* Write a pattern for complementary values */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel((u32)~index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != ~index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2)
- __raw_writew((u16)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2) {
- value = __raw_readw(index);
- if (value != (u16)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readw(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1)
- __raw_writeb((u8)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1) {
- value = __raw_readb(index);
- if (value != (u8)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readb(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
- }
-
- puts("ddr memory test PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
-{
- u32 index, value, index2, value2;
-
- for (index = address1, index2 = address2;
- index < address1 + size;
- index += 4, index2 += 4) {
- value = __raw_readl(index);
- value2 = __raw_readl(index2);
-
- if (value != value2) {
- printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
- index, value, index2, value2);
-
- return -1;
- }
- }
-
- puts("ddr memory compare PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
-{
- u32 value1, value2, value3;
-
- puts("Disabling DDR ECC ...\n");
- ddr3_disable_ecc(base);
-
- value1 = __raw_readl(address);
- value2 = value1 ^ ecc_err;
- __raw_writel(value2, address);
-
- value3 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
- address, value1, value2, ecc_err, value3);
-
- __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
- base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
- puts("Enabling DDR ECC ...\n");
- ddr3_enable_ecc(base, 1);
-
- value1 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
-
- ddr3_check_ecc_int(base);
- return 0;
-}
-
-static int do_ddr_test(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- u32 start_addr, end_addr, size, ecc_err;
-
- if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
- if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
- puts("ECC RMW isn't supported for this SOC\n");
- return 1;
- }
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- ecc_err = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1))) {
- puts("Invalid address!\n");
- return cmd_usage(cmdtp);
- }
-
- ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
- start_addr, ecc_err);
- return 0;
- }
-
- if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
- ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
- return cmd_usage(cmdtp);
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- end_addr = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
- (end_addr < CONFIG_SYS_SDRAM_BASE) ||
- (end_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
- puts("Invalid start or end address!\n");
- return cmd_usage(cmdtp);
- }
-
- puts("Please wait ...\n");
- if (argc == 5) {
- size = simple_strtoul(argv[4], NULL, 16);
- ddr_memory_compare(start_addr, end_addr, size);
- } else {
- ddr_memory_test(start_addr, end_addr, 0);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
- "DDR3 test",
- "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
- " address to end address\n"
- "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
- " compare DDR data of (size) bytes from start address to end\n"
- " address\n"
- "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
- " in DDR data at <addr>, the command will read a 32-bit data\n"
- " from <addr>, and write (data ^ bit_err) back to <addr>\n"
-);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/cpu/armv7/keystone/cmd_mon.c
deleted file mode 100644
index f9f58a3..0000000
--- a/arch/arm/cpu/armv7/keystone/cmd_mon.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * K2HK: secure kernel command file
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-asm(".arch_extension sec\n\t");
-
-static int mon_install(u32 addr, u32 dpsc, u32 freq)
-{
- int result;
-
- __asm__ __volatile__ (
- "stmfd r13!, {lr}\n"
- "mov r0, %1\n"
- "mov r1, %2\n"
- "mov r2, %3\n"
- "blx r0\n"
- "ldmfd r13!, {lr}\n"
- : "=&r" (result)
- : "r" (addr), "r" (dpsc), "r" (freq)
- : "cc", "r0", "r1", "r2", "memory");
- return result;
-}
-
-static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 addr, dpsc_base = 0x1E80000, freq;
- int rcode = 0;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- freq = clk_get_rate(sys_clk0_6_clk);
-
- addr = simple_strtoul(argv[1], NULL, 16);
-
- rcode = mon_install(addr, dpsc_base, freq);
- printf("## installed monitor, freq [%d], status %d\n",
- freq, rcode);
-
- return 0;
-}
-
-U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
- "Install boot kernel at 'addr'",
- ""
-);
-
-static void core_spin(void)
-{
- while (1)
- ; /* forever */;
-}
-
-int mon_power_on(int core_id, void *ep)
-{
- int result;
-
- asm volatile (
- "stmfd r13!, {lr}\n"
- "mov r1, %1\n"
- "mov r2, %2\n"
- "mov r0, #0\n"
- "smc #0\n"
- "ldmfd r13!, {lr}\n"
- : "=&r" (result)
- : "r" (core_id), "r" (ep)
- : "cc", "r0", "r1", "r2", "memory");
- return result;
-}
-
-int mon_power_off(int core_id)
-{
- int result;
-
- asm volatile (
- "stmfd r13!, {lr}\n"
- "mov r1, %1\n"
- "mov r0, #1\n"
- "smc #1\n"
- "ldmfd r13!, {lr}\n"
- : "=&r" (result)
- : "r" (core_id)
- : "cc", "r0", "r1", "memory");
- return result;
-}
-
-int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int rcode = 0, core_id, on;
- void (*fn)(void);
-
- fn = core_spin;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- core_id = simple_strtoul(argv[1], NULL, 16);
- on = simple_strtoul(argv[2], NULL, 16);
-
- if (on)
- rcode = mon_power_on(core_id, fn);
- else
- rcode = mon_power_off(core_id);
-
- if (on) {
- if (!rcode)
- printf("core %d powered on successfully\n", core_id);
- else
- printf("core %d power on failure\n", core_id);
- } else {
- printf("core %d powered off successfully\n", core_id);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
- "Power On/Off secondary core",
- "mon_power <coreid> <oper>\n"
- "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
- ""
-);
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
deleted file mode 100644
index 923906a..0000000
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <asm/arch/msmc.h>
-#include <asm/arch/ddr3.h>
-#include <asm/arch/psc_defs.h>
-
-#include <asm/ti-common/ti-edma3.h>
-
-#define DDR3_EDMA_BLK_SIZE_SHIFT 10
-#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
-#define DDR3_EDMA_BCNT 0x8000
-#define DDR3_EDMA_CCNT 1
-#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
-#define DDR3_EDMA_SLOT_NUM 1
-
-void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
-{
- unsigned int tmp;
-
- while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
- & 0x00000001) != 0x00000001)
- ;
-
- __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
-
- tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
- tmp &= ~(phy_cfg->pgcr1_mask);
- tmp |= phy_cfg->pgcr1_val;
- __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
-
- __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
- __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
- __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
- __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
-
- tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
- tmp &= ~(phy_cfg->dcr_mask);
- tmp |= phy_cfg->dcr_val;
- __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
-
- __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
- __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
- __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
- __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
- __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
- __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
- __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
- __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
-
- __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
- __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
- __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
-
- __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
- while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
- ;
-
- __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
- while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
- ;
-}
-
-void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
-{
- __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
- __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
- __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
- __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
- __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
- __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
- __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
-}
-
-int ddr3_ecc_support_rmw(u32 base)
-{
- u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
-
- /* Check the DDR3 controller ID reg if the controllers
- supports ECC RMW or not */
- if (value == 0x40461C02)
- return 1;
-
- return 0;
-}
-
-static void ddr3_ecc_config(u32 base, u32 value)
-{
- u32 data;
-
- __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
- udelay(100000); /* delay required to synchronize across clock domains */
-
- if (value & KS2_DDR3_ECC_EN) {
- /* Clear the 1-bit error count */
- data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
- __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
-
- /* enable the ECC interrupt */
- __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
- KS2_DDR3_WR_ECC_ERR_SYS,
- base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
-
- /* Clear the ECC error interrupt status */
- __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
- KS2_DDR3_WR_ECC_ERR_SYS,
- base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
- }
-}
-
-static void ddr3_reset_data(u32 base, u32 ddr3_size)
-{
- u32 mpax[2];
- u32 seg_num;
- u32 seg, blks, dst, edma_blks;
- struct edma3_slot_config slot;
- struct edma3_channel_config edma_channel;
- u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
-
- /* Setup an edma to copy the 1k block to the entire DDR */
- puts("\nClear entire DDR3 memory to enable ECC\n");
-
- /* save the SES MPAX regs */
- msmc_get_ses_mpax(8, 0, mpax);
-
- /* setup edma slot 1 configuration */
- slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
- EDMA3_SLOPT_COMP_CODE(0) |
- EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
- slot.bcnt = DDR3_EDMA_BCNT;
- slot.acnt = DDR3_EDMA_BLK_SIZE;
- slot.ccnt = DDR3_EDMA_CCNT;
- slot.src_bidx = 0;
- slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
- slot.src_cidx = 0;
- slot.dst_cidx = 0;
- slot.link = EDMA3_PARSET_NULL_LINK;
- slot.bcntrld = 0;
- edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
-
- /* configure quik edma channel */
- edma_channel.slot = DDR3_EDMA_SLOT_NUM;
- edma_channel.chnum = 0;
- edma_channel.complete_code = 0;
- /* event trigger after dst update */
- edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
- qedma3_start(KS2_EDMA0_BASE, &edma_channel);
-
- /* DDR3 size in segments (4KB seg size) */
- seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
-
- for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
- /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
- access slave interface so that edma driver can access */
- msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
-
- if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
- edma_blks = KS2_MSMC_MAP_SEG_NUM <<
- (KS2_MSMC_SEG_SIZE_SHIFT
- - DDR3_EDMA_BLK_SIZE_SHIFT);
- else
- edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
- - DDR3_EDMA_BLK_SIZE_SHIFT);
-
- /* Use edma driver to scrub 2GB DDR memory */
- for (dst = base, blks = 0; blks < edma_blks;
- blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
- edma3_set_src_addr(KS2_EDMA0_BASE,
- edma_channel.slot, (u32)edma_src);
- edma3_set_dest_addr(KS2_EDMA0_BASE,
- edma_channel.slot, (u32)dst);
-
- while (edma3_check_for_transfer(KS2_EDMA0_BASE,
- &edma_channel))
- udelay(10);
- }
- }
-
- qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
-
- /* restore the SES MPAX regs */
- msmc_set_ses_mpax(8, 0, mpax);
-}
-
-static void ddr3_ecc_init_range(u32 base)
-{
- u32 ecc_val = KS2_DDR3_ECC_EN;
- u32 rmw = ddr3_ecc_support_rmw(base);
-
- if (rmw)
- ecc_val |= KS2_DDR3_ECC_RMW_EN;
-
- __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
- ddr3_ecc_config(base, ecc_val);
-}
-
-void ddr3_enable_ecc(u32 base, int test)
-{
- u32 ecc_val = KS2_DDR3_ECC_ENABLE;
- u32 rmw = ddr3_ecc_support_rmw(base);
-
- if (test)
- ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
-
- if (!rmw) {
- if (!test)
- /* by default, disable ecc when rmw = 0 and no
- ecc test */
- ecc_val = 0;
- } else {
- ecc_val |= KS2_DDR3_ECC_RMW_EN;
- }
-
- ddr3_ecc_config(base, ecc_val);
-}
-
-void ddr3_disable_ecc(u32 base)
-{
- ddr3_ecc_config(base, 0);
-}
-
-#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
-static void cic_init(u32 base)
-{
- /* Disable CIC global interrupts */
- __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
-
- /* Set to normal mode, no nesting, no priority hold */
- __raw_writel(0, base + KS2_CIC_CTRL);
- __raw_writel(0, base + KS2_CIC_HOST_CTRL);
-
- /* Enable CIC global interrupts */
- __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
-}
-
-static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
-{
- /* Map the system interrupt to a CIC channel */
- __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
-
- /* Enable CIC system interrupt */
- __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
-
- /* Enable CIC Host interrupt */
- __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
-}
-
-static void ddr3_map_ecc_cic2_irq(u32 base)
-{
- cic_init(base);
- cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
- KS2_CIC2_DDR3_ECC_IRQ_NUM);
-}
-#endif
-
-void ddr3_init_ecc(u32 base)
-{
- u32 ddr3_size;
-
- if (!ddr3_ecc_support_rmw(base)) {
- ddr3_disable_ecc(base);
- return;
- }
-
- ddr3_ecc_init_range(base);
- ddr3_size = ddr3_get_size();
- ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
-
- /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
-#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
- ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
-#endif
- ddr3_enable_ecc(base, 0);
-}
-
-void ddr3_check_ecc_int(u32 base)
-{
- char *env;
- int ecc_test = 0;
- u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
-
- env = getenv("ecc_test");
- if (env)
- ecc_test = simple_strtol(env, NULL, 0);
-
- if (value & KS2_DDR3_WR_ECC_ERR_SYS)
- puts("DDR3 ECC write error interrupted\n");
-
- if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
- puts("DDR3 ECC 2-bit error interrupted\n");
-
- if (!ecc_test) {
- puts("Reseting the device ...\n");
- reset_cpu(0);
- }
- }
-
- value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
- if (value) {
- printf("1-bit ECC err count: 0x%x\n", value);
- value = __raw_readl(base +
- KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
- printf("1-bit ECC err address log: 0x%x\n", value);
- }
-}
-
-void ddr3_reset_ddrphy(void)
-{
- u32 tmp;
-
- /* Assert DDR3A PHY reset */
- tmp = readl(KS2_DDR3APLLCTL1);
- tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
- writel(tmp, KS2_DDR3APLLCTL1);
-
- /* wait 10us to catch the reset */
- udelay(10);
-
- /* Release DDR3A PHY reset */
- tmp = readl(KS2_DDR3APLLCTL1);
- tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
- __raw_writel(tmp, KS2_DDR3APLLCTL1);
-}
-
-#ifdef CONFIG_SOC_K2HK
-/**
- * ddr3_reset_workaround - reset workaround in case if leveling error
- * detected for PG 1.0 and 1.1 k2hk SoCs
- */
-void ddr3_err_reset_workaround(void)
-{
- unsigned int tmp;
- unsigned int tmp_a;
- unsigned int tmp_b;
-
- /*
- * Check for PGSR0 error bits of DDR3 PHY.
- * Check for WLERR, QSGERR, WLAERR,
- * RDERR, WDERR, REERR, WEERR error to see if they are set or not
- */
- tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
- tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
-
- if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
- printf("DDR Leveling Error Detected!\n");
- printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
- printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
-
- /*
- * Write Keys to KICK registers to enable writes to registers
- * in boot config space
- */
- __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
- __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
-
- /*
- * Move DDR3A Module out of reset isolation by setting
- * MDCTL23[12] = 0
- */
- tmp_a = __raw_readl(KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
-
- tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
- __raw_writel(tmp_a, KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
-
- /*
- * Move DDR3B Module out of reset isolation by setting
- * MDCTL24[12] = 0
- */
- tmp_b = __raw_readl(KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
- tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
- __raw_writel(tmp_b, KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
-
- /*
- * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
- * to RSTCTRL and RSTCFG
- */
- tmp = __raw_readl(KS2_RSTCTRL);
- tmp &= KS2_RSTCTRL_MASK;
- tmp |= KS2_RSTCTRL_KEY;
- __raw_writel(tmp, KS2_RSTCTRL);
-
- /*
- * Set PLL Controller to drive hard reset on SW trigger by
- * setting RSTCFG[13] = 0
- */
- tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
- tmp &= ~KS2_RSTYPE_PLL_SOFT;
- __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
-
- reset_cpu(0);
- }
-}
-#endif
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
deleted file mode 100644
index c96845c..0000000
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Keystone2: Architecture initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <asm/arch/msmc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/psc_defs.h>
-
-#define MAX_PCI_PORTS 2
-enum pci_mode {
- ENDPOINT,
- LEGACY_ENDPOINT,
- ROOTCOMPLEX,
-};
-
-#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
-#define DEVCFG_MODE_SHIFT 1
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
- __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
-}
-
-#ifdef CONFIG_SOC_K2L
-void osr_init(void)
-{
- u32 i;
- u32 j;
- u32 val;
- u32 base = KS2_OSR_CFG_BASE;
- u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
-
- /* Enable the OSR clock domain */
- psc_enable_module(KS2_LPSC_OSR);
-
- /* Disable OSR ECC check for all the ram banks */
- for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
- val = i | KS2_OSR_ECC_VEC_TRIG_RD |
- (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
-
- writel(val , base + KS2_OSR_ECC_VEC);
-
- /**
- * wait till read is done.
- * Print should be added after earlyprintk support is added.
- */
- for (j = 0; j < 10000; j++) {
- val = readl(base + KS2_OSR_ECC_VEC);
- if (val & KS2_OSR_ECC_VEC_RD_DONE)
- break;
- }
-
- ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
- KS2_OSR_ECC_CTRL_CHK;
-
- writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
- writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
- }
-
- /* Reset OSR memory to all zeros */
- for (i = 0; i < KS2_OSR_SIZE; i += 4)
- writel(0, KS2_OSR_DATA_BASE + i);
-
- /* Enable OSR ECC check for all the ram banks */
- for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
- writel(ecc_ctrl[i] |
- KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
-}
-#endif
-
-/* Function to set up PCIe mode */
-static void config_pcie_mode(int pcie_port, enum pci_mode mode)
-{
- u32 val = __raw_readl(KS2_DEVCFG);
-
- if (pcie_port >= MAX_PCI_PORTS)
- return;
-
- /**
- * each pci port has two bits for mode and it starts at
- * bit 1. So use port number to get the right bit position.
- */
- pcie_port <<= 1;
- val &= ~(DEVCFG_MODE_MASK << pcie_port);
- val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
- __raw_writel(val, KS2_DEVCFG);
-}
-
-int arch_cpu_init(void)
-{
- chip_configuration_unlock();
- icache_enable();
-
- msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
-
- /* Initialize the PCIe-0 to work as Root Complex */
- config_pcie_mode(0, ROOTCOMPLEX);
-#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
- /* Initialize the PCIe-1 to work as Root Complex */
- config_pcie_mode(1, ROOTCOMPLEX);
-#endif
-#ifdef CONFIG_SOC_K2L
- osr_init();
-#endif
-
- /*
- * just initialise the COM2 port so that TI specific
- * UART register PWREMU_MGMT is initialized. Linux UART
- * driver doesn't handle this.
- */
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
- u32 tmp;
-
- tmp = *rstctrl & KS2_RSTCTRL_MASK;
- *rstctrl = tmp | KS2_RSTCTRL_KEY;
-
- *rstctrl &= KS2_RSTCTRL_SWRST;
-
- for (;;)
- ;
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
deleted file mode 100644
index 11a9357..0000000
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Keystone EVM : Board initialization
- *
- * (C) Copyright 2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mon.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/hardware.h>
-
-/**
- * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
- * @ptr - array of data
- * @length - lenght of data array
- */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
- u32 i;
-
- if (!(readl(KS2_DEVSTAT) & 0x1))
- for (i = 0; i < length; i++, ptr++)
- *ptr = cpu_to_be32(*ptr);
-
- return 0;
-}
-
-static int turn_off_myself(void)
-{
- printf("Turning off ourselves\r\n");
- mon_power_off(0);
-
- psc_disable_module(KS2_LPSC_TETRIS);
- psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
-
- asm volatile ("isb\n"
- "dsb\n"
- "wfi\n");
-
- printf("What! Should not see that\n");
- return 0;
-}
-
-static void turn_off_all_dsps(int num_dsps)
-{
- int i;
-
- for (i = 0; i < num_dsps; i++) {
- if (psc_disable_module(i + KS2_LPSC_GEM_0))
- printf("Cannot disable module for #%d DSP", i);
-
- if (psc_disable_domain(i + 8))
- printf("Cannot disable domain for #%d DSP", i);
- }
-}
-
-int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- return turn_off_myself();
-}
-
-U_BOOT_CMD(
- killme, 1, 0, do_killme_cmd,
- "turn off main ARM core",
- "turn off main ARM core. Should not live after that :(\n"
-);
-
-int misc_init_r(void)
-{
- char *env;
- long ks2_debug = 0;
-
- env = getenv("ks2_debug");
-
- if (env)
- ks2_debug = simple_strtol(env, NULL, 0);
-
- if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
- turn_off_all_dsps(KS2_NUM_DSPS);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
deleted file mode 100644
index 7899141..0000000
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * MSMC controller utilities
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/msmc.h>
-
-struct mpax {
- u32 mpaxl;
- u32 mpaxh;
-};
-
-struct msms_regs {
- u32 pid;
- u32 _res_04;
- u32 smcerrar;
- u32 smcerrxr;
- u32 smedcc;
- u32 smcea;
- u32 smsecc;
- u32 smpfar;
- u32 smpfxr;
- u32 smpfr;
- u32 smpfcr;
- u32 _res_2c;
- u32 sbndc[8];
- u32 sbndm;
- u32 sbnde;
- u32 _res_58;
- u32 cfglck;
- u32 cfgulck;
- u32 cfglckstat;
- u32 sms_mpax_lck;
- u32 sms_mpax_ulck;
- u32 sms_mpax_lckstat;
- u32 ses_mpax_lck;
- u32 ses_mpax_ulck;
- u32 ses_mpax_lckstat;
- u32 smestat;
- u32 smirstat;
- u32 smirc;
- u32 smiestat;
- u32 smiec;
- u32 _res_94_c0[12];
- u32 smncerrar;
- u32 smncerrxr;
- u32 smncea;
- u32 _res_d0_1fc[76];
- struct mpax sms[16][8];
- struct mpax ses[16][8];
-};
-
-
-void msmc_share_all_segments(int priv_id)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
- int j;
-
- for (j = 0; j < 8; j++) {
- msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
- msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
- }
-}
-
-void msmc_map_ses_segment(int priv_id, int ses_pair,
- u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
- msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
- (size & 0x1f) | 0x80;
- msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
-}
-
-void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
- *mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
- *mpax = msmc->ses[priv_id][ses_pair].mpaxh;
-}
-
-void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
- msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
- msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
-}
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
deleted file mode 100644
index 237e776..0000000
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Keystone: PSC configuration module
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/psc_defs.h>
-
-int psc_delay(void)
-{
- udelay(10);
- return 10;
-}
-
-/*
- * FUNCTION PURPOSE: Wait for end of transitional state
- *
- * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
- * to be complete.
- *
- * Since this is boot loader code it is *ASSUMED* that interrupts
- * are disabled and no other core is mucking around with the psc
- * at the same time.
- *
- * Returns 0 when the domain is free. Returns -1 if a timeout
- * occurred waiting for the completion.
- */
-int psc_wait(u32 domain_num)
-{
- u32 retry;
- u32 ptstat;
-
- /*
- * Do nothing if the power domain is in transition. This should never
- * happen since the boot code is the only software accesses psc.
- * It's still remotely possible that the hardware state machines
- * initiate transitions.
- * Don't trap if the domain (or a module in this domain) is
- * stuck in transition.
- */
- retry = 0;
-
- do {
- ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT);
- ptstat = ptstat & (1 << domain_num);
- } while ((ptstat != 0) && ((retry += psc_delay()) <
- PSC_PTSTAT_TIMEOUT_LIMIT));
-
- if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
- return -1;
-
- return 0;
-}
-
-u32 psc_get_domain_num(u32 mod_num)
-{
- u32 domain_num;
-
- /* Get the power domain associated with the module number */
- domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
- domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
-
- return domain_num;
-}
-
-/*
- * FUNCTION PURPOSE: Power up/down a module
- *
- * DESCRIPTION: Powers up/down the requested module and the associated power
- * domain if required. No action is taken it the module is
- * already powered up/down.
- *
- * This only controls modules. The domain in which the module
- * resides will be left in the power on state. Multiple modules
- * can exist in a power domain, so powering down the domain based
- * on a single module is not done.
- *
- * Returns 0 on success, -1 if the module can't be powered up, or
- * if there is a timeout waiting for the transition.
- */
-int psc_set_state(u32 mod_num, u32 state)
-{
- u32 domain_num;
- u32 pdctl;
- u32 mdctl;
- u32 ptcmd;
- u32 reset_iso;
- u32 v;
-
- /*
- * Get the power domain associated with the module number, and reset
- * isolation functionality
- */
- v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
- domain_num = PSC_REG_MDCFG_GET_PD(v);
- reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
-
- /* Wait for the status of the domain/module to be non-transitional */
- if (psc_wait(domain_num) != 0)
- return -1;
-
- /*
- * Perform configuration even if the current status matches the
- * existing state
- *
- * Set the next state of the power domain to on. It's OK if the domain
- * is always on. This code will not ever power down a domain, so no
- * change is made if the new state is power down.
- */
- if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
- pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
- pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
- PSC_REG_VAL_PDCTL_NEXT_ON);
- __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
- }
-
- /* Set the next state for the module to enabled/disabled */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
- mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
- __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
- /* Trigger the enable */
- ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
- ptcmd |= (u32)(1<<domain_num);
- __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
-
- /* Wait on the complete */
- return psc_wait(domain_num);
-}
-
-/*
- * FUNCTION PURPOSE: Power up a module
- *
- * DESCRIPTION: Powers up the requested module and the associated power domain
- * if required. No action is taken it the module is already
- * powered up.
- *
- * Returns 0 on success, -1 if the module can't be powered up, or
- * if there is a timeout waiting for the transition.
- */
-int psc_enable_module(u32 mod_num)
-{
- u32 mdctl;
-
- /* Set the bit to apply reset */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
- return 0;
-
- return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
-}
-
-/*
- * FUNCTION PURPOSE: Power down a module
- *
- * DESCRIPTION: Powers down the requested module.
- *
- * Returns 0 on success, -1 on failure or timeout.
- */
-int psc_disable_module(u32 mod_num)
-{
- u32 mdctl;
-
- /* Set the bit to apply reset */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- if ((mdctl & 0x3f) == 0)
- return 0;
- mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
- __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
- return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
-}
-
-/*
- * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
- *
- * DESCRIPTION: The reset isolation enable bit is set. The state of the module
- * is not changed. Returns 0 if the module config showed that
- * reset isolation is supported. Returns 1 otherwise. This is not
- * an error, but setting the bit in mdctl has no effect.
- */
-int psc_set_reset_iso(u32 mod_num)
-{
- u32 v;
- u32 mdctl;
-
- /* Set the reset isolation bit */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
- __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
- v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
- if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
- return 0;
-
- return 1;
-}
-
-/*
- * FUNCTION PURPOSE: Disable a power domain
- *
- * DESCRIPTION: The power domain is disabled
- */
-int psc_disable_domain(u32 domain_num)
-{
- u32 pdctl;
- u32 ptcmd;
-
- pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
- pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
- pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
- __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
-
- ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
- ptcmd |= (u32)(1 << domain_num);
- __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
-
- return psc_wait(domain_num);
-}
diff --git a/arch/arm/cpu/armv7/kona-common/Makefile b/arch/arm/cpu/armv7/kona-common/Makefile
index da225cb..56de3d1 100644
--- a/arch/arm/cpu/armv7/kona-common/Makefile
+++ b/arch/arm/cpu/armv7/kona-common/Makefile
@@ -1,9 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += s_init.o
obj-y += hwinit-common.o
obj-y += clk-stubs.o
+obj-${CONFIG_KONA_RESET_S} += reset.o
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index fa10802..2dfa3f7 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index 2b3a840..8783893 100644
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/kona-common/reset.S b/arch/arm/cpu/armv7/kona-common/reset.S
new file mode 100644
index 0000000..eea835b
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/reset.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, =0x35001f00
+ ldr r2, [r1]
+ ldr r4, =0x80000000
+ and r4, r2, r4
+ ldr r3, =0xA5A500
+ orr r4, r4, r3
+ orr r4, r4, #0x1
+
+ str r4, [r1]
+
+ ldr r1, =0x35001f04
+ ldr r2, [r1]
+ ldr r4, =0x80000000
+ and r4, r2, r4
+ str r4, [r1]
+
+_loop_forever:
+ b _loop_forever
diff --git a/arch/arm/cpu/armv7/kona-common/s_init.c b/arch/arm/cpu/armv7/kona-common/s_init.c
index 6066a73..778b917 100644
--- a/arch/arm/cpu/armv7/kona-common/s_init.c
+++ b/arch/arm/cpu/armv7/kona-common/s_init.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index f1aea05..ba4b374 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* A lowlevel_init function that sets up the stack to call a C function to
* perform further init.
@@ -7,20 +8,36 @@
*
* Author :
* Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
-ENTRY(lowlevel_init)
+.pushsection .text.s_init, "ax"
+WEAK(s_init)
+ bx lr
+ENDPROC(s_init)
+.popsection
+
+.pushsection .text.lowlevel_init, "ax"
+WEAK(lowlevel_init)
/*
- * Setup a temporary stack
+ * Setup a temporary stack. Global data is not available yet.
*/
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ ldr sp, =CONFIG_SPL_STACK
+#else
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
+#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#ifdef CONFIG_SPL_DM
+ mov r9, #0
+#else
+ /*
+ * Set up global data for boards that still need it. This will be
+ * removed soon.
+ */
#ifdef CONFIG_SPL_BUILD
ldr r9, =gdata
#else
@@ -28,14 +45,26 @@
bic sp, sp, #7
mov r9, sp
#endif
+#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
*/
push {ip, lr}
/*
- * go setup pll, mux, memory
+ * Call the very early init function. This should do only the
+ * absolute bare minimum to get started. It should not:
+ *
+ * - set up DRAM
+ * - use global_data
+ * - clear BSS
+ * - try to start a console
+ *
+ * For boards with SPL this should be empty since SPL can do all of
+ * this init in the SPL board_init_f() function which is called
+ * immediately after this.
*/
bl s_init
pop {ip, pc}
ENDPROC(lowlevel_init)
+.popsection
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
new file mode 100644
index 0000000..5d6a711
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -0,0 +1,109 @@
+config ARCH_LS1021A
+ bool
+ select SYS_FSL_DDR_BE if SYS_FSL_DDR
+ select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A008407
+ select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_HAS_CCI400
+ select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+ imply CMD_PCI
+ imply SCSI
+ imply SCSI_AHCI
+
+menu "LS102xA architecture"
+ depends on ARCH_LS1021A
+
+config FSL_PCIE_COMPAT
+ string "PCIe compatible of Kernel DT"
+ depends on PCIE_LAYERSCAPE
+ default "fsl,ls1021a-pcie" if ARCH_LS1021A
+ help
+ This compatible is used to find pci controller node in Kernel DT
+ to complete fixup.
+
+config LS1_DEEP_SLEEP
+ bool "Deep sleep"
+ depends on ARCH_LS1021A
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for LS102xA"
+ depends on ARCH_LS1021A
+ default 2
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
+config SECURE_BOOT
+ bool "Secure Boot"
+ help
+ Enable Freescale Secure Boot feature. Normally selected
+ by defconfig. If unsure, do not change.
+
+config SYS_CCI400_OFFSET
+ hex "Offset for CCI400 base"
+ depends on SYS_FSL_HAS_CCI400
+ default 0x180000
+ help
+ Offset for CCI400 base.
+ CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
+config SYS_FSL_ERRATUM_A008997
+ bool
+ help
+ Workaround for USB PHY erratum A008997
+
+config SYS_FSL_ERRATUM_A009007
+ bool
+ help
+ Workaround for USB PHY erratum A009007
+
+config SYS_FSL_ERRATUM_A009008
+ bool
+ help
+ Workaround for USB PHY erratum A009008
+
+config SYS_FSL_ERRATUM_A009798
+ bool
+ help
+ Workaround for USB PHY erratum A009798
+
+config SYS_FSL_ERRATUM_A010315
+ bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_HAS_CCI400
+ bool
+
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
+config SYS_FSL_IFC_BANK_COUNT
+ int "Maximum banks of Integrated flash controller"
+ depends on ARCH_LS1021A
+ default 8
+
+config SYS_FSL_ERRATUM_A008407
+ bool
+
+endmenu
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2e6a207..0c1596f 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -8,7 +8,12 @@
obj-y += clock.o
obj-y += timer.o
obj-y += fsl_epu.o
+obj-y += soc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
+
+ifdef CONFIG_ARMV7_PSCI
+obj-y += psci.o ls102xa_psci.o
+endif
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 8f80c61..30c7b37 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -19,10 +18,6 @@
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
- u32 ccr;
-#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
@@ -74,10 +69,7 @@
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_be32(&ifc_regs->ifc_ccr);
- ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
- sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+ sys_info->freq_localbus = sys_info->freq_systembus;
#endif
}
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ce2d92f..7c4018e 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,21 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/cache.h>
+#include <asm/system.h>
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
+#include <config.h>
+#include <fsl_wdog.h>
#include "fsl_epu.h"
+#define DCSR_RCPM2_BLOCK_OFFSET 0x223000
+#define DCSR_RCPM2_CPMFSMCR0 0x400
+#define DCSR_RCPM2_CPMFSMSR0 0x404
+#define DCSR_RCPM2_CPMFSMCR1 0x414
+#define DCSR_RCPM2_CPMFSMSR1 0x418
+#define CPMFSMSR_FSM_STATE_MASK 0x7f
+
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Bit[1] of the descriptor indicates the descriptor type,
+ * and bit[0] indicates whether the descriptor is valid.
+ */
+#define PMD_TYPE_TABLE 0x3
+#define PMD_TYPE_SECT 0x1
+
+/* AttrIndx[2:0] */
+#define PMD_ATTRINDX(t) ((t) << 2)
+
+/* Section */
+#define PMD_SECT_AF (1 << 10)
+
+#define BLOCK_SIZE_L1 (1UL << 30)
+#define BLOCK_SIZE_L2 (1UL << 21)
+
+/* TTBCR flags */
+#define TTBCR_EAE (1 << 31)
+#define TTBCR_T0SZ(x) ((x) << 0)
+#define TTBCR_T1SZ(x) ((x) << 16)
+#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC (0 << 8)
+#define TTBCR_IRGN0_WBWA (1 << 8)
+#define TTBCR_IRGN0_WT (2 << 8)
+#define TTBCR_IRGN0_WBNWA (3 << 8)
+#define TTBCR_IRGN0_MASK (3 << 8)
+#define TTBCR_ORGN0_NC (0 << 10)
+#define TTBCR_ORGN0_WBWA (1 << 10)
+#define TTBCR_ORGN0_WT (2 << 10)
+#define TTBCR_ORGN0_WBNWA (3 << 10)
+#define TTBCR_ORGN0_MASK (3 << 10)
+#define TTBCR_SHARED_NON (0 << 12)
+#define TTBCR_SHARED_OUTER (2 << 12)
+#define TTBCR_SHARED_INNER (3 << 12)
+#define TTBCR_EPD0 (0 << 7)
+#define TTBCR (TTBCR_SHARED_NON | \
+ TTBCR_ORGN0_NC | \
+ TTBCR_IRGN0_NC | \
+ TTBCR_USING_TTBR0 | \
+ TTBCR_EAE)
+
+/*
+ * Memory region attributes for LPAE (defined in pgtable):
+ *
+ * n = AttrIndx[2:0]
+ *
+ * n MAIR
+ * UNCACHED 000 00000000
+ * BUFFERABLE 001 01000100
+ * DEV_WC 001 01000100
+ * WRITETHROUGH 010 10101010
+ * WRITEBACK 011 11101110
+ * DEV_CACHED 011 11101110
+ * DEV_SHARED 100 00000100
+ * DEV_NONSHARED 100 00000100
+ * unused 101
+ * unused 110
+ * WRITEALLOC 111 11111111
+ */
+#define MT_MAIR0 0xeeaa4400
+#define MT_MAIR1 0xff000004
+#define MT_STRONLY_ORDER 0
+#define MT_NORMAL_NC 1
+#define MT_DEVICE_MEM 4
+#define MT_NORMAL 7
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
+{
+ u32 value = phy_addr | PMD_TYPE_TABLE;
+
+ page_table[2 * index] = value;
+ page_table[2 * index + 1] = 0;
+}
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
+ u32 memory_type)
+{
+ u64 value;
+
+ value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ page_table[2 * index] = value & 0xFFFFFFFF;
+ page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
+}
+
+/*
+ * Start MMU after DDR is available, we create MMU table in DRAM.
+ * The base address of TTLB is gd->arch.tlb_addr. We use two
+ * levels of translation tables here to cover 40-bit address space.
+ *
+ * The TTLBs are located at PHY 2G~4G.
+ *
+ * VA mapping:
+ *
+ * ------- <---- 0GB
+ * | |
+ * | |
+ * |-------| <---- 0x24000000
+ * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
+ * |-------| <---- 0x300000000
+ * | |
+ * |-------| <---- 0x34000000
+ * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
+ * |-------| <---- 0x40000000
+ * | |
+ * |-------| <---- 0x80000000 DDR0 space start
+ * |\\\\\\\|
+ *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
+ * |\\\\\\\|
+ * ------- <---- 4GB DDR0 space end
+ */
+static void mmu_setup(void)
+{
+ u32 *level0_table = (u32 *)gd->arch.tlb_addr;
+ u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
+ u64 va_start = 0;
+ u32 reg;
+ int i;
+
+ /* Level 0 Table 2-3 are used to map DDR */
+ set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
+ set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
+ /* Level 0 Table 1 is used to map device */
+ set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
+ /* Level 0 Table 0 is used to map device including PCIe MEM */
+ set_pgtable(level0_table, 0, (u32)level1_table);
+
+ /* Level 1 has 512 entries */
+ for (i = 0; i < 512; i++) {
+ /* Mapping for PCIe 1 */
+ if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ /* Mapping for PCIe 2 */
+ else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ else
+ set_pgsection(level1_table, i,
+ va_start,
+ MT_DEVICE_MEM);
+ va_start += BLOCK_SIZE_L2;
+ }
+
+ asm volatile("dsb sy;isb");
+ asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
+ : : "r" (TTBCR) : "memory");
+ asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
+ : : "r" ((u32)level0_table), "r" (0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
+ : : "r" (MT_MAIR0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
+ : : "r" (MT_MAIR1) : "memory");
+
+ /* Set the access control to all-supervisor */
+ asm volatile("mcr p15, 0, %0, c3, c0, 0"
+ : : "r" (~0));
+
+ /* Enable the mmu */
+ reg = get_cr();
+ set_cr(reg | CR_M);
+}
+
+/*
+ * This function is called from lib/board.c. It recreates MMU
+ * table in main memory. MMU and i/d-cache are enabled here.
+ */
+void enable_caches(void)
+{
+ /* Invalidate all TLB */
+ mmu_page_table_flush(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ /* Set up and enable mmu */
+ mmu_setup();
+
+ /* Invalidate & Enable d-cache */
+ invalidate_dcache_all();
+ set_cr(get_cr() | CR_C);
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+
+uint get_svr(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ return in_be32(&gur->svr);
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
@@ -78,16 +287,6 @@
}
#endif
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
#ifdef CONFIG_FSL_ESDHC
int cpu_mmc_init(bd_t *bis)
{
@@ -107,6 +306,28 @@
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *rcpm2_base =
+ (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 state;
+
+ /*
+ * The RCPM FSM state may not be reset after power-on.
+ * So, reset them.
+ */
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+ }
+
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+ }
/*
* After wakeup from deep sleep, Clear EPU registers
@@ -115,10 +336,12 @@
*/
fsl_epu_clean(epu_base);
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
return 0;
}
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
/* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
@@ -133,5 +356,36 @@
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
+
+ /*
+ * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
+ * So add a delay to wait bootrom execute WFE.
+ */
+ udelay(1);
+
+ asm volatile("sev");
}
#endif
+
+void reset_cpu(ulong addr)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ clrbits_be16(&wdog->wcr, WCR_SRS);
+
+ while (1) {
+ /*
+ * Let the watchdog trigger
+ */
+ }
+}
+
+void arch_preboot_os(void)
+{
+ unsigned long ctrl;
+
+ /* Disable PL1 Physical Timer */
+ asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
+ ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+ asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 989780d..8bf9c42 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/processor.h>
@@ -15,6 +14,8 @@
#include <fsl_esdhc.h>
#endif
#include <tsec.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -27,29 +28,26 @@
char phy[16];
int phy_node;
int i = 0;
- int enet_id = 0;
uint32_t ph;
+ char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
- while ((dev = eth_get_dev_by_index(i++)) != NULL) {
- if (strstr(dev->name, "eTSEC1"))
- enet_id = 0;
- else if (strstr(dev->name, "eTSEC2"))
- enet_id = 1;
- else if (strstr(dev->name, "eTSEC3"))
- enet_id = 2;
- else
+ for (; i < ARRAY_SIZE(name); i++) {
+ dev = eth_get_dev_by_name(name[i]);
+ if (dev) {
+ sprintf(enet, "ethernet%d", i);
+ sprintf(phy, "enet%d_rgmii_phy", i);
+ } else {
continue;
+ }
priv = dev->priv;
if (priv->flags & TSEC_SGMII)
continue;
- sprintf(enet, "ethernet%d", enet_id);
enet_path = fdt_get_alias(fdt, enet);
if (!enet_path)
continue;
- sprintf(phy, "enet%d_rgmii_phy", enet_id);
phy_path = fdt_get_alias(fdt, phy);
if (!phy_path)
continue;
@@ -66,8 +64,8 @@
do_fixup_by_path(fdt, enet_path, "phy-connection-type",
phy_string_for_interface(
PHY_INTERFACE_MODE_RGMII_ID),
- sizeof(phy_string_for_interface(
- PHY_INTERFACE_MODE_RGMII_ID)),
+ strlen(phy_string_for_interface(
+ PHY_INTERFACE_MODE_RGMII_ID)) + 1,
1);
}
}
@@ -77,10 +75,23 @@
int off;
int val;
const char *sysclk_path;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr;
+ svr = in_be32(&gur->svr);
unsigned long busclk = get_bus_freq(0);
- fdt_fixup_ethernet(blob);
+ /* delete crypto node if not on an E-processor */
+ if (!IS_E_PROCESSOR(svr))
+ fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+ else {
+ ccsr_sec_t __iomem *sec;
+
+ sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+ }
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -107,6 +118,25 @@
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
+#define UBOOT_HEAD_LEN 0x1000
+ /*
+ * Reserved memory in SD boot deep sleep case.
+ * Second stage uboot binary and malloc space should be reserved.
+ * If the memory they occupied has not been reserved, then this
+ * space would be used by kernel and overwritten in uboot when
+ * deep sleep resume, which cause deep sleep failed.
+ * Since second uboot binary has a head, that space need to be
+ * reserved either(assuming its size is less than 0x1000).
+ */
+ off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
+ CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
+ UBOOT_HEAD_LEN);
+ if (off < 0)
+ printf("Failed to reserve memory for SD boot deep sleep: %s\n",
+ fdt_strerror(off));
+#endif
+
#if defined(CONFIG_FSL_ESDHC)
fdt_fixup_esdhc(blob, bd);
#endif
@@ -133,4 +163,17 @@
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
"clock-frequency", busclk / 2, 1);
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+ off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
+ CONFIG_SYS_IFC_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#else
+ off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
+ QSPI0_BASE_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
+ DSPI1_BASE_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#endif
}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
index 6212640..e31a4fb 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -9,6 +8,163 @@
#include "fsl_epu.h"
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+ /*
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
+ * SCU8 triger EVT2, and SCU11 triger EVT9
+ */
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+ /* EPACR (Event Processor Action Control Registers) */
+ {EPACR0 + EPACR_STRIDE * 0, 0},
+ {EPACR0 + EPACR_STRIDE * 1, 0},
+ {EPACR0 + EPACR_STRIDE * 2, 0},
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+ {EPACR0 + EPACR_STRIDE * 4, 0},
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+ {EPACR0 + EPACR_STRIDE * 6, 0},
+ {EPACR0 + EPACR_STRIDE * 7, 0},
+ {EPACR0 + EPACR_STRIDE * 8, 0},
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+ {EPACR0 + EPACR_STRIDE * 11, 0},
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+ {EPXTRIGCR, 0x0000FFDF},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+/**
+ * fsl_epu_setup - Setup EPU registers to default values
+ */
+void fsl_epu_setup(void *epu_base)
+{
+ struct fsm_reg_vals *data = epu_default_val;
+
+ if (!epu_base || !data)
+ return;
+
+ while (data->offset != FSM_END_FLAG) {
+ out_be32(epu_base + data->offset, data->value);
+ data++;
+ }
+}
+
/**
* fsl_epu_clean - Clear EPU registers
*/
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
index d658aad..711eea5 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_EPU_H
@@ -63,6 +62,14 @@
#define EPCTR31 0xA7C
#define EPCTR_STRIDE FSL_STRIDE_4B
+#define FSM_END_FLAG 0xFFFFFFFFUL
+
+struct fsm_reg_vals {
+ u32 offset;
+ u32 value;
+};
+
+void fsl_epu_setup(void *epu_base);
void fsl_epu_clean(void *epu_base);
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index 9b78acb..caf51e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -1,13 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_ls102xa.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include "fsl_ls1_serdes.h"
@@ -23,9 +22,15 @@
u64 ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!(serdes1_prtcl_map & (1ULL << NONE)))
+ fsl_serdes_init();
+
ret |= (1ULL << device) & serdes1_prtcl_map;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!(serdes2_prtcl_map & (1ULL << NONE)))
+ fsl_serdes_init();
+
ret |= (1ULL << device) & serdes2_prtcl_map;
#endif
@@ -87,19 +92,24 @@
serdes_prtcl_map |= (1ULL << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1ULL << NONE);
+
return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
- serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+ if (!(serdes1_prtcl_map & (1ULL << NONE)))
+ serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+ if (!(serdes2_prtcl_map & (1ULL << NONE)))
+ serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
index 834aa53..7382aef 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_LS1_SERDES_H
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
new file mode 100644
index 0000000..bb169aa
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <fsl_immap.h>
+#include "fsl_epu.h"
+
+#define __secure __attribute__((section("._secure.text")))
+
+#define CCSR_GICD_CTLR 0x1000
+#define CCSR_GICC_CTLR 0x2000
+#define DCSR_RCPM_CG1CR0 0x31c
+#define DCSR_RCPM_CSTTACR0 0xb00
+#define DCFG_CRSTSR_WDRFR 0x8
+#define DDR_RESV_LEN 128
+
+#ifdef CONFIG_LS1_DEEP_SLEEP
+/*
+ * DDR controller initialization training breaks the first 128 bytes of DDR,
+ * save them so that the bootloader can restore them while resuming.
+ */
+static void __secure ls1_save_ddr_head(void)
+{
+ const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+ char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ int i;
+
+ out_le32(&scfg->sparecr[2], dest);
+
+ for (i = 0; i < DDR_RESV_LEN; i++)
+ *dest++ = *src++;
+}
+
+static void __secure ls1_fsm_setup(void)
+{
+ void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
+
+ out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
+ out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
+
+ fsl_epu_setup((void *)dcsr_epu_base);
+
+ /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
+ out_be32(dcsr_epu_base + EPECR0, 0x5);
+ out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
+}
+
+static void __secure ls1_deepsleep_irq_cfg(void)
+{
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
+
+ /* Mask interrupts from GIC */
+ out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
+ out_be32(&rcpm->nirqoutr, 0x0ffffffff);
+ /* Mask deep sleep wake-up interrupts while entering deep sleep */
+ out_be32(&rcpm->dsimskr, 0x0ffffffff);
+
+ ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
+ /*
+ * Workaround: There is bug of register ippdexpcr1, when read it always
+ * returns zero, so its value is saved to a scrachpad register to be
+ * read, that is why we don't read it from register ippdexpcr1 itself.
+ */
+ ippdexpcr1 = in_le32(&scfg->sparecr[7]);
+ out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
+
+ if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
+ pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
+ SCFG_PMCINTECR_ETSECRXG1 |
+ SCFG_PMCINTECR_ETSECERRG0 |
+ SCFG_PMCINTECR_ETSECERRG1;
+
+ if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
+ pmcintecr |= SCFG_PMCINTECR_GPIO;
+
+ if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
+ pmcintecr |= SCFG_PMCINTECR_LPUART;
+
+ if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
+ pmcintecr |= SCFG_PMCINTECR_FTM;
+
+ /* Always set external IRQ pins as wakeup source */
+ pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
+
+ out_be32(&scfg->pmcintlecr, 0);
+ /* Clear PMC interrupt status */
+ out_be32(&scfg->pmcintsr, 0xffffffff);
+ /* Enable wakeup interrupt during deep sleep */
+ out_be32(&scfg->pmcintecr, pmcintecr);
+}
+
+static void __secure ls1_delay(unsigned int loop)
+{
+ while (loop--) {
+ int i = 1000;
+ while (i--)
+ ;
+ }
+}
+
+static void __secure ls1_start_fsm(void)
+{
+ void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ /* Set HRSTCR */
+ setbits_be32(&scfg->hrstcr, 0x80000000);
+
+ /* Place DDR controller in self refresh mode */
+ setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
+
+ ls1_delay(2000);
+
+ /* Set EVT4_B to lock the signal MCKE down */
+ out_be32(dcsr_epu_base + EPECR0, 0x0);
+
+ ls1_delay(2000);
+
+ out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
+ out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
+
+ /* Enable all EPU Counters */
+ setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
+
+ /* Enable SCU15 */
+ setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
+
+ /* Enter WFI mode, and EPU FSM will start */
+ __asm__ __volatile__ ("wfi" : : : "memory");
+
+ /* NEVER ENTER HERE */
+ while (1)
+ ;
+}
+
+static void __secure ls1_deep_sleep(u32 entry_point)
+{
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+#ifdef QIXIS_BASE
+ u32 tmp;
+ void *qixis_base = (void *)QIXIS_BASE;
+#endif
+
+ /* Enable cluster to enter the PCL10 state */
+ out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
+
+ /* Save the first 128 bytes of DDR data */
+ ls1_save_ddr_head();
+
+ /* Save the kernel resume entry */
+ out_le32(&scfg->sparecr[3], entry_point);
+
+ /* Request to put cluster 0 in PCL10 state */
+ setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
+
+ /* Setup the registers of the EPU FSM for deep sleep */
+ ls1_fsm_setup();
+
+#ifdef QIXIS_BASE
+ /* Connect the EVENT button to IRQ in FPGA */
+ tmp = in_8(qixis_base + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ out_8(qixis_base + QIXIS_CTL_SYS, tmp);
+
+ /* Enable deep sleep signals in FPGA */
+ tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
+ tmp |= QIXIS_PWR_CTL2_PCTL;
+ out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
+
+ /* Pull down PCIe RST# */
+ tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
+ tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
+ out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
+#endif
+
+ /* Enable Warm Device Reset */
+ setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
+ setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
+
+ /* Disable QE */
+ setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
+
+ ls1_deepsleep_irq_cfg();
+
+ psci_v7_flush_dcache_all();
+
+ ls1_start_fsm();
+}
+
+#else
+static void __secure ls1_sleep(void)
+{
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+
+#ifdef QIXIS_BASE
+ u32 tmp;
+ void *qixis_base = (void *)QIXIS_BASE;
+
+ /* Connect the EVENT button to IRQ in FPGA */
+ tmp = in_8(qixis_base + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ out_8(qixis_base + QIXIS_CTL_SYS, tmp);
+#endif
+
+ /* Enable cluster to enter the PCL10 state */
+ out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
+
+ setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
+
+ __asm__ __volatile__ ("wfi" : : : "memory");
+}
+#endif
+
+void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
+{
+#ifdef CONFIG_LS1_DEEP_SLEEP
+ ls1_deep_sleep(entry_point);
+#else
+ ls1_sleep();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
index cc53910..8c030be 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
new file mode 100644
index 0000000..531cfb0
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/arch-armv7/generictimer.h>
+#include <asm/psci.h>
+
+#define RCPM_TWAITSR 0x04C
+
+#define SCFG_CORE0_SFT_RST 0x130
+#define SCFG_CORESRENCR 0x204
+
+#define DCFG_CCSR_RSTCR 0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ 0x2
+#define DCFG_CCSR_BRR 0x0E4
+#define DCFG_CCSR_SCRATCHRW1 0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+ .align 5
+
+#define ONE_MS (COUNTER_FREQUENCY / 1000)
+#define RESET_WAIT (30 * ONE_MS)
+
+.globl psci_version
+psci_version:
+ movw r0, #0
+ movt r0, #1
+
+ bx lr
+
+_ls102x_psci_supported_table:
+ .word ARM_PSCI_0_2_FN_PSCI_VERSION
+ .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_CPU_SUSPEND
+ .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_CPU_OFF
+ .word PSCI_FN_CPU_OFF_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_CPU_ON
+ .word PSCI_FN_CPU_ON_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_AFFINITY_INFO
+ .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_SYSTEM_OFF
+ .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_SYSTEM_RESET
+ .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+ .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+ .word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
+ .word 0
+ .word ARM_PSCI_RET_NI
+
+.globl psci_features
+psci_features:
+ adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+ cmp r3, #0
+ beq out_psci_features
+ cmp r1, r3
+ addne r2, r2, #8
+ bne 1b
+
+out_psci_features:
+ ldr r0, [r2, #4]
+ bx lr
+
+@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
+@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
+@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
+@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
+LENTRY(psci_check_target_cpu_id)
+ @ Get the real CPU number
+ and r4, r1, #0xff
+ mov r0, #ARM_PSCI_RET_INVAL
+
+ @ Bit[31:24], bits must be zero.
+ tst r1, #0xff000000
+ bxne lr
+
+ @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
+ tst r1, #0xff0000
+ bxne lr
+
+ @ Affinity level 1 - Processors: should be in 0xf00 format.
+ lsr r1, r1, #8
+ teq r1, #0xf
+ bxne lr
+
+ @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
+ cmp r4, #2
+ bxge lr
+
+ mov r0, #ARM_PSCI_RET_SUCCESS
+ bx lr
+ENDPROC(psci_check_target_cpu_id)
+
+ @ r1 = target CPU
+ @ r2 = target PC
+.globl psci_cpu_on
+psci_cpu_on:
+ push {r4, r5, r6, lr}
+
+ @ Clear and Get the correct CPU number
+ @ r1 = 0xf01
+ bl psci_check_target_cpu_id
+ cmp r0, #ARM_PSCI_RET_INVAL
+ beq out_psci_cpu_on
+
+ mov r0, r4
+ mov r1, r2
+ mov r2, r3
+ bl psci_save
+ mov r1, r4
+
+ @ Get DCFG base address
+ movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+ @ Detect target CPU state
+ ldr r2, [r4, #DCFG_CCSR_BRR]
+ rev r2, r2
+ lsr r2, r2, r1
+ ands r2, r2, #1
+ beq holdoff_release
+
+ @ Reset target CPU
+ @ Get SCFG base address
+ movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
+ movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+
+ @ Enable CORE Soft Reset
+ movw r5, #0
+ movt r5, #(1 << 15)
+ rev r5, r5
+ str r5, [r0, #SCFG_CORESRENCR]
+
+ @ Get CPUx offset register
+ mov r6, #0x4
+ mul r6, r6, r1
+ add r2, r0, r6
+
+ @ Do reset on target CPU
+ movw r5, #0
+ movt r5, #(1 << 15)
+ rev r5, r5
+ str r5, [r2, #SCFG_CORE0_SFT_RST]
+
+ @ Wait target CPU up
+ timer_wait r2, RESET_WAIT
+
+ @ Disable CORE soft reset
+ mov r5, #0
+ str r5, [r0, #SCFG_CORESRENCR]
+
+holdoff_release:
+ @ Release on target CPU
+ ldr r2, [r4, #DCFG_CCSR_BRR]
+ mov r6, #1
+ lsl r6, r6, r1 @ 32 bytes per CPU
+
+ rev r6, r6
+ orr r2, r2, r6
+ str r2, [r4, #DCFG_CCSR_BRR]
+
+ @ Set secondary boot entry
+ ldr r6, =psci_cpu_entry
+ rev r6, r6
+ str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
+
+ isb
+ dsb
+
+ @ Return
+ mov r0, #ARM_PSCI_RET_SUCCESS
+
+out_psci_cpu_on:
+ pop {r4, r5, r6, lr}
+ bx lr
+
+.globl psci_cpu_off
+psci_cpu_off:
+ bl psci_cpu_off_common
+
+1: wfi
+ b 1b
+
+.globl psci_affinity_info
+psci_affinity_info:
+ push {lr}
+
+ mov r0, #ARM_PSCI_RET_INVAL
+
+ @ Verify Affinity level
+ cmp r2, #0
+ bne out_affinity_info
+
+ bl psci_check_target_cpu_id
+ cmp r0, #ARM_PSCI_RET_INVAL
+ beq out_affinity_info
+ mov r1, r4
+
+ @ Get RCPM base address
+ movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
+ movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+ mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+ @ Detect target CPU state
+ ldr r2, [r4, #RCPM_TWAITSR]
+ rev r2, r2
+ lsr r2, r2, r1
+ ands r2, r2, #1
+ beq out_affinity_info
+
+ mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+ pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+ @ Get DCFG base address
+ movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+ mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+ rev r2, r2
+ str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+ b 1b
+
+.globl psci_system_suspend
+psci_system_suspend:
+ push {lr}
+
+ bl ls1_system_suspend
+
+ pop {pc}
+
+ .popsection
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
new file mode 100644
index 0000000..448d951
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <fsl_csu.h>
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
+unsigned int get_soc_major_rev(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
+
+ return major;
+}
+
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+ 0xF << 6,
+ SCFG_USB_TXVREFTUNE << 6);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+ SCFG_USB_SQRXTUNE_MASK << 23);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
+ SCFG_USB_PCSTXSWINGFULL_MASK,
+ SCFG_USB_PCSTXSWINGFULL_VAL);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+ void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
+void s_init(void)
+{
+}
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void)
+{
+ int i;
+
+ for (i = PCIE1; i <= PCIE2; i++)
+ if (!is_serdes_configured(i)) {
+ debug("PCIe%d: disabled all R/W permission!\n", i);
+ set_pcie_ns_access(i, 0);
+ }
+}
+#endif
+
+int arch_soc_init(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
+ unsigned int major;
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+ /* Configure Little endian for SAI, ASRC and SPDIF */
+ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
+ /*
+ * Enable snoop requests and DVM message requests for
+ * All the slave insterfaces.
+ */
+ out_le32(&cci->slave[0].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+ out_le32(&cci->slave[1].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+ out_le32(&cci->slave[2].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ major = get_soc_major_rev();
+ if (major == SOC_MAJOR_VER_1_0) {
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override
+ * Register All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+ /* Workaround for the issue that DDR could not respond to
+ * barrier transaction which is generated by executing DSB/ISB
+ * instruction. Set CCI-400 control override register to
+ * terminate the barrier transaction. After DDR is initialized,
+ * allow barrier transaction to DDR again */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+ }
+
+ /* Enable all the snoop signal for various masters */
+ out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+ SCFG_SNPCNFGCR_DCU_RD_WR |
+ SCFG_SNPCNFGCR_SATA_RD_WR |
+ SCFG_SNPCNFGCR_USB3_RD_WR |
+ SCFG_SNPCNFGCR_DBG_RD_WR |
+ SCFG_SNPCNFGCR_EDMA_SNP);
+
+ /*
+ * Memory controller require a register write before being enabled.
+ * Affects: DDR
+ * Register: EDDRTQCFG
+ * Description: Memory controller performance is not optimal with
+ * default internal target queue register values.
+ * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+ */
+ out_be32(&scfg->eddrtqcfg, 0x63b20042);
+
+ /* Erratum */
+ erratum_a009008();
+ erratum_a009798();
+ erratum_a008997();
+ erratum_a009007();
+
+ return 0;
+}
+
+int ls102xa_smmu_stream_id_init(void)
+{
+ ls1021x_config_caam_stream_id(sec_liodn_tbl,
+ ARRAY_SIZE(sec_liodn_tbl));
+
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 1dfbf54..308536c 100644
--- a/arch/arm/cpu/armv7/ls102xa/spl.c
+++ b/arch/arm/cpu/armv7/ls102xa/spl.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -14,20 +13,3 @@
#endif
return BOOT_DEVICE_NAND;
}
-
-u32 spl_boot_mode(void)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
-#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
-#else
- return MMCSD_MODE_RAW;
-#endif
- case BOOT_DEVICE_NAND:
- return 0;
- default:
- puts("spl: error: unsupported device\n");
- hang();
- }
-}
diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c
index 11b17b2..e79360a 100644
--- a/arch/arm/cpu/armv7/ls102xa/timer.c
+++ b/arch/arm/cpu/armv7/ls102xa/timer.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -56,12 +55,13 @@
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
- unsigned long ctrl, val, freq;
+ unsigned long ctrl, freq;
+ unsigned long long val;
/* Enable System Counter */
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
- freq = GENERIC_TIMER_CLK;
+ freq = COUNTER_FREQUENCY;
asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
/* Set PL1 Physical Timer Ctrl */
@@ -90,14 +90,9 @@
return now;
}
-unsigned long get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
unsigned long get_timer(ulong base)
{
- return get_timer_masked() - base;
+ return tick_to_time(get_ticks()) - base;
}
/* delay x useconds and preserve advance timstamp value */
diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c
new file mode 100644
index 0000000..7adecff
--- /dev/null
+++ b/arch/arm/cpu/armv7/mpu_v7r.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cortex-R Memory Protection Unit specific code
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/armv7.h>
+#include <asm/system.h>
+#include <asm/barriers.h>
+#include <linux/compiler.h>
+
+#include <asm/armv7_mpu.h>
+
+/* MPU Type register definitions */
+#define MPUIR_S_SHIFT 0
+#define MPUIR_S_MASK BIT(MPUIR_S_SHIFT)
+#define MPUIR_DREGION_SHIFT 8
+#define MPUIR_DREGION_MASK (0xff << 8)
+
+/**
+ * Note:
+ * The Memory Protection Unit(MPU) allows to partition memory into regions
+ * and set individual protection attributes for each region. In absence
+ * of MPU a default map[1] will take effect. make sure to run this code
+ * from a region which has execution permissions by default.
+ * [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
+ */
+
+void disable_mpu(void)
+{
+ u32 reg;
+
+ reg = get_cr();
+ reg &= ~CR_M;
+ dsb();
+ set_cr(reg);
+ isb();
+}
+
+void enable_mpu(void)
+{
+ u32 reg;
+
+ reg = get_cr();
+ reg |= CR_M;
+ dsb();
+ set_cr(reg);
+ isb();
+}
+
+int mpu_enabled(void)
+{
+ return get_cr() & CR_M;
+}
+
+void mpu_config(struct mpu_region_config *rgn)
+{
+ u32 attr, val;
+
+ attr = get_attr_encoding(rgn->mr_attr);
+
+ /* MPU Region Number Register */
+ asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no));
+
+ /* MPU Region Base Address Register */
+ asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr));
+
+ /* MPU Region Size and Enable Register */
+ if (rgn->reg_size)
+ val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION;
+ else
+ val = DISABLE_REGION;
+ asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val));
+
+ /* MPU Region Access Control Register */
+ val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr;
+ asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val));
+}
+
+void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
+{
+ u32 num, i;
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num));
+ num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT;
+ /* Regions to be configured cannot be greater than available regions */
+ if (num < num_rgns)
+ num_rgns = num;
+ /**
+ * Assuming dcache might not be enabled at this point, disabling
+ * and invalidating only icache.
+ */
+ icache_disable();
+ invalidate_icache_all();
+
+ disable_mpu();
+
+ for (i = 0; i < num_rgns; i++)
+ mpu_config(&rgns[i]);
+
+ enable_mpu();
+
+ icache_enable();
+}
+
+void enable_caches(void)
+{
+ /*
+ * setup_mpu_regions() might have enabled Icache. So add a check
+ * before enabling Icache
+ */
+ if (!icache_status())
+ icache_enable();
+ dcache_enable();
+}
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
deleted file mode 100644
index d021842..0000000
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := soc.o clock.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
deleted file mode 100644
index bf52f0d..0000000
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ /dev/null
@@ -1,949 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <div64.h>
-#include <asm/arch/sys_proto.h>
-
-enum pll_clocks {
- PLL1_CLOCK = 0,
- PLL2_CLOCK,
- PLL3_CLOCK,
-#ifdef CONFIG_MX53
- PLL4_CLOCK,
-#endif
- PLL_CLOCKS,
-};
-
-struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
- [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
- [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
- [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-#ifdef CONFIG_MX53
- [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
-#endif
-};
-
-#define AHB_CLK_ROOT 133333333
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 /* Actual pd+1 */
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 5
-#define ARM_DIV_MAX 8
-#define IPG_DIV_MAX 4
-#define AHB_DIV_MAX 8
-#define EMI_DIV_MAX 8
-#define NFC_DIV_MAX 8
-
-#define MX5_CBCMR 0x00015154
-#define MX5_CBCDR 0x02888945
-
-struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
-};
-
-const struct fixed_pll_mfd fixed_mfd[] = {
- {MXC_HCLK, 24 * 16},
-};
-
-struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
-};
-
-#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(ref_clk) \
- ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define MAX_DDR_CLK 420000000
-#define NFC_CLK_MAX 34000000
-
-struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
-
-void set_usboh3_clk(void)
-{
- clrsetbits_le32(&mxc_ccm->cscmr1,
- MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
- MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
- clrsetbits_le32(&mxc_ccm->cscdr1,
- MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
- MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
- MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
- MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
-}
-
-void enable_usboh3_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR2,
- MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR2_USBOH3_60M(cg));
-}
-
-#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- u32 mask;
-
-#if defined(CONFIG_MX51)
- if (i2c_num > 1)
-#elif defined(CONFIG_MX53)
- if (i2c_num > 2)
-#endif
- return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK <<
- (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
- if (enable)
- setbits_le32(&mxc_ccm->CCGR1, mask);
- else
- clrbits_le32(&mxc_ccm->CCGR1, mask);
- return 0;
-}
-#endif
-
-void set_usb_phy_clk(void)
-{
- clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
-#if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR2,
- MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR2_USB_PHY(cg));
-}
-
-void enable_usb_phy2_clk(bool enable)
-{
- /* i.MX51 has a single USB PHY clock, so do nothing here. */
-}
-#elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR4_USB_PHY1(cg));
-}
-
-void enable_usb_phy2_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR4_USB_PHY2(cg));
-}
-#endif
-
-/*
- * Calculate the frequency of PLLn.
- */
-static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
-{
- uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
- uint64_t refclk, temp;
- int32_t mfn_abs;
-
- ctrl = readl(&pll->ctrl);
-
- if (ctrl & MXC_DPLLC_CTL_HFSM) {
- mfn = readl(&pll->hfs_mfn);
- mfd = readl(&pll->hfs_mfd);
- op = readl(&pll->hfs_op);
- } else {
- mfn = readl(&pll->mfn);
- mfd = readl(&pll->mfd);
- op = readl(&pll->op);
- }
-
- mfd &= MXC_DPLLC_MFD_MFD_MASK;
- mfn &= MXC_DPLLC_MFN_MFN_MASK;
- pdf = op & MXC_DPLLC_OP_PDF_MASK;
- mfi = MXC_DPLLC_OP_MFI_RD(op);
-
- /* 21.2.3 */
- if (mfi < 5)
- mfi = 5;
-
- /* Sign extend */
- if (mfn >= 0x04000000) {
- mfn |= 0xfc000000;
- mfn_abs = -mfn;
- } else
- mfn_abs = mfn;
-
- refclk = infreq * 2;
- if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
- refclk *= 2;
-
- do_div(refclk, pdf + 1);
- temp = refclk * mfn_abs;
- do_div(temp, mfd + 1);
- ret = refclk * mfi;
-
- if ((int)mfn < 0)
- ret -= temp;
- else
- ret += temp;
-
- return ret;
-}
-
-#ifdef CONFIG_MX51
-/*
- * This function returns the Frequency Pre-Multiplier clock.
- */
-static u32 get_fpm(void)
-{
- u32 mult;
- u32 ccr = readl(&mxc_ccm->ccr);
-
- if (ccr & MXC_CCM_CCR_FPM_MULT)
- mult = 1024;
- else
- mult = 512;
-
- return MXC_CLK32 * mult;
-}
-#endif
-
-/*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 ccsr = readl(&mxc_ccm->ccsr);
-
- if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
- ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
- ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
-#endif
- else
- ret_val = MXC_HCLK;
-
- return ret_val;
-}
-
-/*
- * Get mcu main rate
- */
-u32 get_mcu_main_clk(void)
-{
- u32 reg, freq;
-
- reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
- freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- return freq / (reg + 1);
-}
-
-/*
- * Get the rate of peripheral's root clock.
- */
-u32 get_periph_clk(void)
-{
- u32 reg;
-
- reg = readl(&mxc_ccm->cbcdr);
- if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
- reg = readl(&mxc_ccm->cbcmr);
- switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
- case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
- case 2:
- return get_lp_apm();
- default:
- return 0;
- }
- /* NOTREACHED */
-}
-
-/*
- * Get the rate of ipg clock.
- */
-static u32 get_ipg_clk(void)
-{
- uint32_t freq, reg, div;
-
- freq = get_ahb_clk();
-
- reg = readl(&mxc_ccm->cbcdr);
- div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
-
- return freq / div;
-}
-
-/*
- * Get the rate of ipg_per clock.
- */
-static u32 get_ipg_per_clk(void)
-{
- u32 freq, pred1, pred2, podf;
-
- if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
- return get_ipg_clk();
-
- if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
- freq = get_lp_apm();
- else
- freq = get_periph_clk();
- podf = readl(&mxc_ccm->cbcdr);
- pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
- pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
- podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
- return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/* Get the output clock rate of a standard PLL MUX for peripherals. */
-static u32 get_standard_pll_sel_clk(u32 clk_sel)
-{
- u32 freq = 0;
-
- switch (clk_sel & 0x3) {
- case 0:
- freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- break;
- case 1:
- freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
- break;
- case 2:
- freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
- break;
- case 3:
- freq = get_lp_apm();
- break;
- }
-
- return freq;
-}
-
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
-{
- unsigned int clk_sel, freq, reg, pred, podf;
-
- reg = readl(&mxc_ccm->cscmr1);
- clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
- freq = get_standard_pll_sel_clk(clk_sel);
-
- reg = readl(&mxc_ccm->cscdr1);
- pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
- podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
- freq /= (pred + 1) * (podf + 1);
-
- return freq;
-}
-
-/*
- * get cspi clock rate.
- */
-static u32 imx_get_cspiclk(void)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
- u32 cscmr1 = readl(&mxc_ccm->cscmr1);
- u32 cscdr2 = readl(&mxc_ccm->cscdr2);
-
- pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
- pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
- clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
- freq = get_standard_pll_sel_clk(clk_sel);
- ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
- return ret_val;
-}
-
-/*
- * get esdhc clock rate.
- */
-static u32 get_esdhc_clk(u32 port)
-{
- u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
- u32 cscmr1 = readl(&mxc_ccm->cscmr1);
- u32 cscdr1 = readl(&mxc_ccm->cscdr1);
-
- switch (port) {
- case 0:
- clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
- pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
- podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
- break;
- case 1:
- clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
- pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
- podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
- break;
- case 2:
- if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
- return get_esdhc_clk(1);
- else
- return get_esdhc_clk(0);
- case 3:
- if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
- return get_esdhc_clk(1);
- else
- return get_esdhc_clk(0);
- default:
- break;
- }
-
- freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
- return freq;
-}
-
-static u32 get_axi_a_clk(void)
-{
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
-
- return get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_axi_b_clk(void)
-{
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
-
- return get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_emi_slow_clk(void)
-{
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
-
- if (emi_clk_sel)
- return get_ahb_clk() / (pdf + 1);
-
- return get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_ddr_clk(void)
-{
- u32 ret_val = 0;
- u32 cbcmr = readl(&mxc_ccm->cbcmr);
- u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
-#ifdef CONFIG_MX51
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
- u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
-
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- ret_val /= ddr_clk_podf + 1;
-
- return ret_val;
- }
-#endif
- switch (ddr_clk_sel) {
- case 0:
- ret_val = get_axi_a_clk();
- break;
- case 1:
- ret_val = get_axi_b_clk();
- break;
- case 2:
- ret_val = get_emi_slow_clk();
- break;
- case 3:
- ret_val = get_ahb_clk();
- break;
- default:
- break;
- }
-
- return ret_val;
-}
-
-/*
- * The API of get mxc clocks.
- */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_AHB_CLK:
- return get_ahb_clk();
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_IPG_PERCLK:
- case MXC_I2C_CLK:
- return get_ipg_per_clk();
- case MXC_UART_CLK:
- return get_uart_clk();
- case MXC_CSPI_CLK:
- return imx_get_cspiclk();
- case MXC_ESDHC_CLK:
- return get_esdhc_clk(0);
- case MXC_ESDHC2_CLK:
- return get_esdhc_clk(1);
- case MXC_ESDHC3_CLK:
- return get_esdhc_clk(2);
- case MXC_ESDHC4_CLK:
- return get_esdhc_clk(3);
- case MXC_FEC_CLK:
- return get_ipg_clk();
- case MXC_SATA_CLK:
- return get_ahb_clk();
- case MXC_DDR_CLK:
- return get_ddr_clk();
- default:
- break;
- }
- return -EINVAL;
-}
-
-u32 imx_get_uartclk(void)
-{
- return get_uart_clk();
-}
-
-u32 imx_get_fecclk(void)
-{
- return get_ipg_clk();
-}
-
-static int gcd(int m, int n)
-{
- int t;
- while (m > 0) {
- if (n > m) {
- t = m;
- m = n;
- n = t;
- } /* swap */
- m -= n;
- }
- return n;
-}
-
-/*
- * This is to calculate various parameters based on reference clock and
- * targeted clock based on the equation:
- * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
- * This calculation is based on a fixed MFD value for simplicity.
- */
-static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
-{
- u64 pd, mfi = 1, mfn, mfd, t1;
- u32 n_target = target;
- u32 n_ref = ref, i;
-
- /*
- * Make sure targeted freq is in the valid range.
- * Otherwise the following calculation might be wrong!!!
- */
- if (n_target < PLL_FREQ_MIN(ref) ||
- n_target > PLL_FREQ_MAX(ref)) {
- printf("Targeted peripheral clock should be"
- "within [%d - %d]\n",
- PLL_FREQ_MIN(ref) / SZ_DEC_1M,
- PLL_FREQ_MAX(ref) / SZ_DEC_1M);
- return -EINVAL;
- }
-
- for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
- if (fixed_mfd[i].ref_clk_hz == ref) {
- mfd = fixed_mfd[i].mfd;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(fixed_mfd))
- return -EINVAL;
-
- /* Use n_target and n_ref to avoid overflow */
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- t1 = n_target * pd;
- do_div(t1, (4 * n_ref));
- mfi = t1;
- if (mfi > PLL_MFI_MAX)
- return -EINVAL;
- else if (mfi < 5)
- continue;
- break;
- }
- /*
- * Now got pd and mfi already
- *
- * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
- */
- t1 = n_target * pd;
- do_div(t1, 4);
- t1 -= n_ref * mfi;
- t1 *= mfd;
- do_div(t1, n_ref);
- mfn = t1;
- debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
- ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
- i = 1;
- if (mfn != 0)
- i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- do_div(mfn, i);
- pll->mfn = (u32)mfn;
- do_div(mfd, i);
- pll->mfd = (u32)mfd;
-
- return 0;
-}
-
-#define calc_div(tgt_clk, src_clk, limit) ({ \
- u32 v = 0; \
- if (((src_clk) % (tgt_clk)) <= 100) \
- v = (src_clk) / (tgt_clk); \
- else \
- v = ((src_clk) / (tgt_clk)) + 1;\
- if (v > limit) \
- v = limit; \
- (v - 1); \
- })
-
-#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
- { \
- writel(0x1232, &pll->ctrl); \
- writel(0x2, &pll->config); \
- writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->op); \
- writel(fn, &(pll->mfn)); \
- writel((fd) - 1, &pll->mfd); \
- writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->hfs_op); \
- writel(fn, &pll->hfs_mfn); \
- writel((fd) - 1, &pll->hfs_mfd); \
- writel(0x1232, &pll->ctrl); \
- while (!readl(&pll->ctrl) & 0x1) \
- ;\
- }
-
-static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
-{
- u32 ccsr = readl(&mxc_ccm->ccsr);
- struct mxc_pll_reg *pll = mxc_plls[index];
-
- switch (index) {
- case PLL1_CLOCK:
- /* Switch ARM to PLL2 clock */
- writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
- case PLL2_CLOCK:
- /* Switch to pll2 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
- case PLL3_CLOCK:
- /* Switch to pll3 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
-#ifdef CONFIG_MX53
- case PLL4_CLOCK:
- /* Switch to pll4 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* Config CPU clock */
-static int config_core_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- /* The case that periph uses PLL1 is not considered here */
- ret = calc_pll_params(ref, freq, &pll_param);
- if (ret != 0) {
- printf("Error:Can't find pll parameters: %d\n", ret);
- return ret;
- }
-
- return config_pll_clk(PLL1_CLOCK, &pll_param);
-}
-
-static int config_nfc_clk(u32 nfc_clk)
-{
- u32 parent_rate = get_emi_slow_clk();
- u32 div;
-
- if (nfc_clk == 0)
- return -EINVAL;
- div = parent_rate / nfc_clk;
- if (div == 0)
- div++;
- if (parent_rate / div > NFC_CLK_MAX)
- div++;
- clrsetbits_le32(&mxc_ccm->cbcdr,
- MXC_CCM_CBCDR_NFC_PODF_MASK,
- MXC_CCM_CBCDR_NFC_PODF(div - 1));
- while (readl(&mxc_ccm->cdhipr) != 0)
- ;
- return 0;
-}
-
-void enable_nfc_clk(unsigned char enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR5,
- MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR5_EMI_ENFC(cg));
-}
-
-#ifdef CONFIG_FSL_IIM
-void enable_efuse_prog_supply(bool enable)
-{
- if (enable)
- setbits_le32(&mxc_ccm->cgpr,
- MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
- else
- clrbits_le32(&mxc_ccm->cgpr,
- MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
-}
-#endif
-
-/* Config main_bus_clock for periphs */
-static int config_periph_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- ret = calc_pll_params(ref, freq, &pll_param);
- if (ret != 0) {
- printf("Error:Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
- switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
- readl(&mxc_ccm->cbcmr))) {
- case 0:
- return config_pll_clk(PLL1_CLOCK, &pll_param);
- break;
- case 1:
- return config_pll_clk(PLL3_CLOCK, &pll_param);
- break;
- default:
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static int config_ddr_clk(u32 emi_clk)
-{
- u32 clk_src;
- s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = readl(&mxc_ccm->cbcmr);
-
- if (emi_clk > MAX_DDR_CLK) {
- printf("Warning:DDR clock should not exceed %d MHz\n",
- MAX_DDR_CLK / SZ_DEC_1M);
- emi_clk = MAX_DDR_CLK;
- }
-
- clk_src = get_periph_clk();
- /* Find DDR clock input */
- clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
- switch (clk_sel) {
- case 0:
- shift = 16;
- break;
- case 1:
- shift = 19;
- break;
- case 2:
- shift = 22;
- break;
- case 3:
- shift = 10;
- break;
- default:
- return -EINVAL;
- }
-
- if ((clk_src % emi_clk) < 10000000)
- div = clk_src / emi_clk;
- else
- div = (clk_src / emi_clk) + 1;
- if (div > 8)
- div = 8;
-
- clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
- while (readl(&mxc_ccm->cdhipr) != 0)
- ;
- writel(0x0, &mxc_ccm->ccdr);
-
- return 0;
-}
-
-/*
- * This function assumes the expected core clock has to be changed by
- * modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
- * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
- * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
- * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
- * it sets the register based on these values along with the dividers.
- * Note 1) There is no value checking for the passed-in divider values
- * so the caller has to make sure those values are sensible.
- * 2) Also adjust the NFC divider such that the NFC clock doesn't
- * exceed NFC_CLK_MAX.
- * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
- * 177MHz for higher voltage, this function fixes the max to 133MHz.
- * 4) This function should not have allowed diag_printf() calls since
- * the serial driver has been stoped. But leave then here to allow
- * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- */
-int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
-{
- freq *= SZ_DEC_1M;
-
- switch (clk) {
- case MXC_ARM_CLK:
- if (config_core_clk(ref, freq))
- return -EINVAL;
- break;
- case MXC_PERIPH_CLK:
- if (config_periph_clk(ref, freq))
- return -EINVAL;
- break;
- case MXC_DDR_CLK:
- if (config_ddr_clk(freq))
- return -EINVAL;
- break;
- case MXC_NFC_CLK:
- if (config_nfc_clk(freq))
- return -EINVAL;
- break;
- default:
- printf("Warning:Unsupported or invalid clock type\n");
- }
-
- return 0;
-}
-
-#ifdef CONFIG_MX53
-/*
- * The clock for the external interface can be set to use internal clock
- * if fuse bank 4, row 3, bit 2 is set.
- * This is an undocumented feature and it was confirmed by Freescale's support:
- * Fuses (but not pins) may be used to configure SATA clocks.
- * Particularly the i.MX53 Fuse_Map contains the next information
- * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
- * '00' - 100MHz (External)
- * '01' - 50MHz (External)
- * '10' - 120MHz, internal (USB PHY)
- * '11' - Reserved
-*/
-void mxc_set_sata_internal_clock(void)
-{
- u32 *tmp_base =
- (u32 *)(IIM_BASE_ADDR + 0x180c);
-
- set_usb_phy_clk();
-
- clrsetbits_le32(tmp_base, 0x6, 0x4);
-}
-#endif
-
-/*
- * Dump some core clockes.
- */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 freq;
-
- freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- printf("PLL1 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
- printf("PLL2 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
- printf("PLL3 %8d MHz\n", freq / 1000000);
-#ifdef CONFIG_MX53
- freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
- printf("PLL4 %8d MHz\n", freq / 1000000);
-#endif
-
- printf("\n");
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
- return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
- "display clocks",
- ""
-);
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
deleted file mode 100644
index f5bc672..0000000
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <linux/linkage.h>
-
-.section ".text.init", "x"
-
-.macro init_arm_erratum
- /* ARM erratum ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-.endm
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- ldr r0, =0xC0 | /* tag RAM */ \
- 0x4 | /* data RAM */ \
- 1 << 24 | /* disable write allocate delay */ \
- 1 << 23 | /* disable write allocate combine */ \
- 1 << 22 /* disable write allocate */
-
-#if defined(CONFIG_MX51)
- ldr r3, [r4, #ROM_SI_REV]
- cmp r3, #0x10
-
- /* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #1 << 25
-#endif
-
- mcr 15, 1, r0, c9, c0, 2
-
- /* enable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- orr r0, r0, #2
- mcr 15, 0, r0, c1, c0, 1
-
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
-.endm /* init_aips */
-
-/* M4IF setup */
-.macro init_m4if
-#ifdef CONFIG_MX51
- /* VPU and IPU given higher priority (0x4)
- * IPU accesses with ID=0x1 given highest priority (=0xA)
- */
- ldr r0, =M4IF_BASE_ADDR
-
- ldr r1, =0x00000203
- str r1, [r0, #0x40]
-
- str r4, [r0, #0x44]
-
- ldr r1, =0x00120125
- str r1, [r0, #0x9C]
-
- ldr r1, =0x001901A3
- str r1, [r0, #0x48]
-
-#endif
-.endm /* init_m4if */
-
-.macro setup_pll pll, freq
- ldr r0, =\pll
- adr r2, W_DP_\freq
- bl setup_pll_func
-.endm
-
-#define W_DP_OP 0
-#define W_DP_MFD 4
-#define W_DP_MFN 8
-
-setup_pll_func:
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- ldr r1, [r2, #W_DP_OP]
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, [r2, #W_DP_MFD]
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, [r2, #W_DP_MFN]
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
-1: ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-
- /* r10 saved upper lr */
- mov pc, lr
-
-.macro setup_pll_errata pll, freq
- ldr r2, =\pll
- str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
- ldr r1, =0x00001236
- str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
-1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
- ands r1, r1, #0x1
- beq 1b
-
- ldr r5, \freq
- str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
- str r5, [r2, #PLL_DP_HFS_MFN]
-
- mov r1, #0x1
- str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
-
-2: ldr r1, [r2, #PLL_DP_CONFIG]
- tst r1, #1
- bne 2b
-
- ldr r1, =100 /* Wait at least 4 us */
-3: subs r1, r1, #1
- bge 3b
-
- mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-.endm
-
-.macro init_clock
-#if defined (CONFIG_MX51)
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r4, [r0, #CLKCTL_CCGR1]
- str r4, [r0, #CLKCTL_CCGR2]
- str r4, [r0, #CLKCTL_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
-#if defined(CONFIG_MX51_PLL_ERRATA)
- setup_pll PLL1_BASE_ADDR, 864
- setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
-#else
- setup_pll PLL1_BASE_ADDR, 800
-#endif
-
- setup_pll PLL3_BASE_ADDR, 665
-
- /* Switch peripheral to PLL 3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #CLKCTL_CBCDR]
- setup_pll PLL2_BASE_ADDR, 665
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
-
- setup_pll PLL3_BASE_ADDR, 216
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000725
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
-
- /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r3, [r4, #ROM_SI_REV]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
-
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1 */
- str r4, [r0, #CLKCTL_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =CONFIG_SYS_CLKTL_CBCDR
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #CLKCTL_CSCDR1]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- str r4, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-#else /* CONFIG_MX53 */
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r4, [r0, #CLKCTL_CCGR1]
- str r4, [r0, #CLKCTL_CCGR2]
- str r4, [r0, #CLKCTL_CCGR3]
- str r4, [r0, #CLKCTL_CCGR7]
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x0F00030F
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
- setup_pll PLL1_BASE_ADDR, 800
-
- setup_pll PLL3_BASE_ADDR, 400
-
- /* Switch peripheral to PLL3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00015154
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02898945
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL2_BASE_ADDR, 400
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00888945
- str r1, [r0, #CLKCTL_CBCDR]
-
- ldr r1, =0x00016154
- str r1, [r0, #CLKCTL_CBCMR]
-
- /*change uart clk parent to pll2*/
- ldr r1, [r0, #CLKCTL_CSCMR1]
- and r1, r1, #0xfcffffff
- orr r1, r1, #0x01000000
- str r1, [r0, #CLKCTL_CSCMR1]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL3_BASE_ADDR, 216
-
- setup_pll PLL4_BASE_ADDR, 455
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000124
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1. */
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCSR]
-
- /* make uart div=6 */
- ldr r1, [r0, #CLKCTL_CSCDR1]
- and r1, r1, #0xffffffc0
- orr r1, r1, #0x0a
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
- str r1, [r0, #CLKCTL_CCGR7]
-
- mov r1, #0x00000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-
-#endif /* CONFIG_MX53 */
-.endm
-
-ENTRY(lowlevel_init)
- mov r10, lr
- mov r4, #0 /* Fix R4 to 0 */
-
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
- ldr r0, =GPIO1_BASE_ADDR
- ldr r1, [r0, #0x0]
- orr r1, r1, #1 << 23
- str r1, [r0, #0x0]
- ldr r1, [r0, #0x4]
- orr r1, r1, #1 << 23
- str r1, [r0, #0x4]
-#endif
-
- init_arm_erratum
-
- init_l2cc
-
- init_aips
-
- init_m4if
-
- init_clock
-
- mov pc, r10
-ENDPROC(lowlevel_init)
-
-/* Board level setting value */
-#if defined(CONFIG_MX51_PLL_ERRATA)
-W_DP_864: .word DP_OP_864
- .word DP_MFD_864
- .word DP_MFN_864
-W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
-#else
-W_DP_800: .word DP_OP_800
- .word DP_MFD_800
- .word DP_MFN_800
-#endif
-#if defined(CONFIG_MX51)
-W_DP_665: .word DP_OP_665
- .word DP_MFD_665
- .word DP_MFN_665
-#endif
-W_DP_216: .word DP_OP_216
- .word DP_MFD_216
- .word DP_MFN_216
-W_DP_400: .word DP_OP_400
- .word DP_MFD_400
- .word DP_MFN_400
-W_DP_455: .word DP_OP_455
- .word DP_MFD_455
- .word DP_MFN_455
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
deleted file mode 100644
index 3753c14..0000000
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
-
-#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
-#error "CPU_TYPE not defined"
-#endif
-
-u32 get_cpu_rev(void)
-{
-#ifdef CONFIG_MX51
- int system_rev = 0x51000;
-#else
- int system_rev = 0x53000;
-#endif
- int reg = __raw_readl(ROM_SI_REV);
-
-#if defined(CONFIG_MX51)
- switch (reg) {
- case 0x02:
- system_rev |= CHIP_REV_1_1;
- break;
- case 0x10:
- if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev |= CHIP_REV_2_5;
- else
- system_rev |= CHIP_REV_2_0;
- break;
- case 0x20:
- system_rev |= CHIP_REV_3_0;
- break;
- default:
- system_rev |= CHIP_REV_1_0;
- break;
- }
-#else
- if (reg < 0x20)
- system_rev |= CHIP_REV_1_0;
- else
- system_rev |= reg;
-#endif
- return system_rev;
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- return get_cpu_rev();
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- int i;
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
-
- for (i = 0; i < 6; i++)
- mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif
-
-#ifdef CONFIG_MX53
-void boot_mode_apply(unsigned cfg_val)
-{
- writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
-}
-/*
- * cfg_val will be used for
- * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- *
- * If bit 28 of LPGR is set upon watchdog reset,
- * bits[25:0] of LPGR will move to SBMR.
- */
-const struct boot_mode soc_boot_modes[] = {
- {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
- /* usb or serial download */
- {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
- {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
- {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
- {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
- {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
- {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
- /* 4 bit bus width */
- {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
- {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
- {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
- {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
- {NULL, 0},
-};
-#endif
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
deleted file mode 100644
index bf6effc..0000000
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := soc.o clock.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
-obj-$(CONFIG_SECURE_BOOT) += hab.o
-obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
deleted file mode 100644
index 055f44e..0000000
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ /dev/null
@@ -1,856 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-enum pll_clocks {
- PLL_SYS, /* System PLL */
- PLL_BUS, /* System Bus PLL*/
- PLL_USBOTG, /* OTG USB PLL */
- PLL_ENET, /* ENET PLL */
-};
-
-struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-#ifdef CONFIG_MXC_OCOTP
-void enable_ocotp_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR2);
- if (enable)
- reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- else
- reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- __raw_writel(reg, &imx_ccm->CCGR2);
-}
-#endif
-
-#ifdef CONFIG_NAND_MXS
-void setup_gpmi_io_clk(u32 cfg)
-{
- /* Disable clocks per ERR007177 from MX6 errata */
- clrbits_le32(&imx_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
-
- clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- clrsetbits_le32(&imx_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- cfg);
-
- setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
- setbits_le32(&imx_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
-}
-#endif
-
-void enable_usboh3_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_USBOH3_MASK;
- else
- reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
- __raw_writel(reg, &imx_ccm->CCGR6);
-
-}
-
-#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
-void enable_enet_clk(unsigned char enable)
-{
- u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
-
- if (enable)
- setbits_le32(&imx_ccm->CCGR1, mask);
- else
- clrbits_le32(&imx_ccm->CCGR1, mask);
-}
-#endif
-
-#ifdef CONFIG_MXC_UART
-void enable_uart_clk(unsigned char enable)
-{
- u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
-
- if (enable)
- setbits_le32(&imx_ccm->CCGR5, mask);
- else
- clrbits_le32(&imx_ccm->CCGR5, mask);
-}
-#endif
-
-#ifdef CONFIG_SPI
-/* spi_num can be from 0 - 4 */
-int enable_cspi_clock(unsigned char enable, unsigned spi_num)
-{
- u32 mask;
-
- if (spi_num > 4)
- return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
- if (enable)
- setbits_le32(&imx_ccm->CCGR1, mask);
- else
- clrbits_le32(&imx_ccm->CCGR1, mask);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MMC
-int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
-{
- u32 mask;
-
- if (bus_num > 3)
- return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
- if (enable)
- setbits_le32(&imx_ccm->CCGR6, mask);
- else
- clrbits_le32(&imx_ccm->CCGR6, mask);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- u32 reg;
- u32 mask;
-
- if (i2c_num > 2)
- return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK
- << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
- reg = __raw_readl(&imx_ccm->CCGR2);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, &imx_ccm->CCGR2);
- return 0;
-}
-#endif
-
-/* spi_num can be from 0 - SPI_MAX_NUM */
-int enable_spi_clk(unsigned char enable, unsigned spi_num)
-{
- u32 reg;
- u32 mask;
-
- if (spi_num > SPI_MAX_NUM)
- return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
- reg = __raw_readl(&imx_ccm->CCGR1);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, &imx_ccm->CCGR1);
- return 0;
-}
-static u32 decode_pll(enum pll_clocks pll, u32 infreq)
-{
- u32 div;
-
- switch (pll) {
- case PLL_SYS:
- div = __raw_readl(&imx_ccm->analog_pll_sys);
- div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
-
- return (infreq * div) >> 1;
- case PLL_BUS:
- div = __raw_readl(&imx_ccm->analog_pll_528);
- div &= BM_ANADIG_PLL_528_DIV_SELECT;
-
- return infreq * (20 + (div << 1));
- case PLL_USBOTG:
- div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
- div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
-
- return infreq * (20 + (div << 1));
- case PLL_ENET:
- div = __raw_readl(&imx_ccm->analog_pll_enet);
- div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
-
- return 25000000 * (div + (div >> 1) + 1);
- default:
- return 0;
- }
- /* NOTREACHED */
-}
-static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
-{
- u32 div;
- u64 freq;
-
- switch (pll) {
- case PLL_BUS:
- if (pfd_num == 3) {
- /* No PFD3 on PPL2 */
- return 0;
- }
- div = __raw_readl(&imx_ccm->analog_pfd_528);
- freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case PLL_USBOTG:
- div = __raw_readl(&imx_ccm->analog_pfd_480);
- freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
- break;
- default:
- /* No PFD on other PLL */
- return 0;
- }
-
- return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
- ANATOP_PFD_FRAC_SHIFT(pfd_num));
-}
-
-static u32 get_mcu_main_clk(void)
-{
- u32 reg, freq;
-
- reg = __raw_readl(&imx_ccm->cacrr);
- reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
- reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
-
- return freq / (reg + 1);
-}
-
-u32 get_periph_clk(void)
-{
- u32 reg, freq = 0;
-
- reg = __raw_readl(&imx_ccm->cbcdr);
- if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- reg = __raw_readl(&imx_ccm->cbcmr);
- reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
- reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
-
- switch (reg) {
- case 0:
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- break;
- case 1:
- case 2:
- freq = MXC_HCLK;
- break;
- default:
- break;
- }
- } else {
- reg = __raw_readl(&imx_ccm->cbcmr);
- reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
- reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
-
- switch (reg) {
- case 0:
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
- break;
- default:
- break;
- }
- }
-
- return freq;
-}
-
-static u32 get_ipg_clk(void)
-{
- u32 reg, ipg_podf;
-
- reg = __raw_readl(&imx_ccm->cbcdr);
- reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
- ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
-
- return get_ahb_clk() / (ipg_podf + 1);
-}
-
-static u32 get_ipg_per_clk(void)
-{
- u32 reg, perclk_podf;
-
- reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
- return MXC_HCLK; /* OSC 24Mhz */
-#endif
- perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
-
- return get_ipg_clk() / (perclk_podf + 1);
-}
-
-static u32 get_uart_clk(void)
-{
- u32 reg, uart_podf;
- u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
- reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
- freq = MXC_HCLK;
-#endif
- reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
- uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
-
- return freq / (uart_podf + 1);
-}
-
-static u32 get_cspi_clk(void)
-{
- u32 reg, cspi_podf;
-
- reg = __raw_readl(&imx_ccm->cscdr2);
- reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
- cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
-
- return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
-}
-
-static u32 get_axi_clk(void)
-{
- u32 root_freq, axi_podf;
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-
- axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
- axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
-
- if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
- if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- else
- root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
- } else
- root_freq = get_periph_clk();
-
- return root_freq / (axi_podf + 1);
-}
-
-static u32 get_emi_slow_clk(void)
-{
- u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
-
- cscmr1 = __raw_readl(&imx_ccm->cscmr1);
- emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
- emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
- emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
- emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
-
- switch (emi_clk_sel) {
- case 0:
- root_freq = get_axi_clk();
- break;
- case 1:
- root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- break;
- case 2:
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 3:
- root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- }
-
- return root_freq / (emi_slow_podf + 1);
-}
-
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-static u32 get_mmdc_ch0_clk(void)
-{
- u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 freq, podf;
-
- podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
- >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
-
- switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
- case 0:
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
- }
-
- return freq / (podf + 1);
-
-}
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
- MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
- return get_periph_clk() / (mmdc_ch0_podf + 1);
-}
-#endif
-
-#ifdef CONFIG_MX6SX
-/* qspi_num can be from 0 - 1 */
-void enable_qspi_clk(int qspi_num)
-{
- u32 reg = 0;
- /* Enable QuadSPI clock */
- switch (qspi_num) {
- case 0:
- /* disable the clock gate */
- clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
-
- /* set 50M : (50 = 396 / 2 / 4) */
- reg = readl(&imx_ccm->cscmr1);
- reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
- MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
- reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
- (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
- writel(reg, &imx_ccm->cscmr1);
-
- /* enable the clock gate */
- setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
- break;
- case 1:
- /*
- * disable the clock gate
- * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
- * disable both of them.
- */
- clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
-
- /* set 50M : (50 = 396 / 2 / 4) */
- reg = readl(&imx_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
- reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
- MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
- writel(reg, &imx_ccm->cs2cdr);
-
- /*enable the clock gate*/
- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
-{
- u32 reg = 0;
- s32 timeout = 100000;
-
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
- if (freq < ENET_25MHZ || freq > ENET_125MHZ)
- return -EINVAL;
-
- reg = readl(&anatop->pll_enet);
- reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= freq;
-
- if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
- (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
- reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
- writel(reg, &anatop->pll_enet);
- while (timeout--) {
- if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
- break;
- }
- if (timeout < 0)
- return -ETIMEDOUT;
- }
-
- /* Enable FEC clock */
- reg |= BM_ANADIG_PLL_ENET_ENABLE;
- reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
- writel(reg, &anatop->pll_enet);
-
-#ifdef CONFIG_MX6SX
- /*
- * Set enet ahb clock to 200MHz
- * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
- */
- reg = readl(&imx_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
- | MXC_CCM_CHSCCDR_ENET_PODF_MASK
- | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
- /* PLL2 PFD2 */
- reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
- /* Div = 2*/
- reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
- reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
- writel(reg, &imx_ccm->chsccdr);
-
- /* Enable enet system clock */
- reg = readl(&imx_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_ENET_MASK;
- writel(reg, &imx_ccm->CCGR3);
-#endif
- return 0;
-}
-#endif
-
-static u32 get_usdhc_clk(u32 port)
-{
- u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
- u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
- u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
-
- switch (port) {
- case 0:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
-
- break;
- case 1:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
-
- break;
- case 2:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
-
- break;
- case 3:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
-
- break;
- default:
- break;
- }
-
- if (clk_sel)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
- else
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
-
- return root_freq / (usdhc_podf + 1);
-}
-
-u32 imx_get_uartclk(void)
-{
- return get_uart_clk();
-}
-
-u32 imx_get_fecclk(void)
-{
- return mxc_get_clock(MXC_IPG_CLK);
-}
-
-static int enable_enet_pll(uint32_t en)
-{
- struct mxc_ccm_reg *const imx_ccm
- = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
- s32 timeout = 100000;
- u32 reg = 0;
-
- /* Enable PLLs */
- reg = readl(&imx_ccm->analog_pll_enet);
- reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
- writel(reg, &imx_ccm->analog_pll_enet);
- reg |= BM_ANADIG_PLL_SYS_ENABLE;
- while (timeout--) {
- if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
- break;
- }
- if (timeout <= 0)
- return -EIO;
- reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
- writel(reg, &imx_ccm->analog_pll_enet);
- reg |= en;
- writel(reg, &imx_ccm->analog_pll_enet);
- return 0;
-}
-
-#ifndef CONFIG_MX6SX
-static void ungate_sata_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* Enable SATA clock. */
- setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
-}
-#endif
-
-static void ungate_pcie_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* Enable PCIe clock. */
- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
-
-#ifndef CONFIG_MX6SX
-int enable_sata_clock(void)
-{
- ungate_sata_clock();
- return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
-}
-
-void disable_sata_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
-}
-#endif
-
-int enable_pcie_clock(void)
-{
- struct anatop_regs *anatop_regs =
- (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 lvds1_clk_sel;
-
- /*
- * Here be dragons!
- *
- * The register ANATOP_MISC1 is not documented in the Freescale
- * MX6RM. The register that is mapped in the ANATOP space and
- * marked as ANATOP_MISC1 is actually documented in the PMU section
- * of the datasheet as PMU_MISC1.
- *
- * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
- * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
- * for PCI express link that is clocked from the i.MX6.
- */
-#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
-#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
-#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
-#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
-#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
-
- if (is_cpu_type(MXC_CPU_MX6SX))
- lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
- else
- lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
-
- clrsetbits_le32(&anatop_regs->ana_misc1,
- ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
- ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
- ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
-
- /* PCIe reference clock sourced from AXI. */
- clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
-
- /* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
- ungate_sata_clock();
-#endif
- ungate_pcie_clock();
-
- return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
- BM_ANADIG_PLL_ENET_ENABLE_PCIE);
-}
-
-#ifdef CONFIG_SECURE_BOOT
-void hab_caam_clock_enable(unsigned char enable)
-{
- u32 reg;
-
- /* CG4 ~ CG6, CAAM clocks */
- reg = __raw_readl(&imx_ccm->CCGR0);
- if (enable)
- reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- else
- reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- __raw_writel(reg, &imx_ccm->CCGR0);
-
- /* EMI slow clk */
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
- else
- reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- __raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
-static void enable_pll3(void)
-{
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
- /* make sure pll3 is enabled */
- if ((readl(&anatop->usb1_pll_480_ctrl) &
- BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
- /* enable pll's power */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
- &anatop->usb1_pll_480_ctrl_set);
- writel(0x80, &anatop->ana_misc2_clr);
- /* wait for pll lock */
- while ((readl(&anatop->usb1_pll_480_ctrl) &
- BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
- ;
- /* disable bypass */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
- &anatop->usb1_pll_480_ctrl_clr);
- /* enable pll output */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
- &anatop->usb1_pll_480_ctrl_set);
- }
-}
-
-void enable_thermal_clk(void)
-{
- enable_pll3();
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_PER_CLK:
- return get_periph_clk();
- case MXC_AHB_CLK:
- return get_ahb_clk();
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_IPG_PERCLK:
- case MXC_I2C_CLK:
- return get_ipg_per_clk();
- case MXC_UART_CLK:
- return get_uart_clk();
- case MXC_CSPI_CLK:
- return get_cspi_clk();
- case MXC_AXI_CLK:
- return get_axi_clk();
- case MXC_EMI_SLOW_CLK:
- return get_emi_slow_clk();
- case MXC_DDR_CLK:
- return get_mmdc_ch0_clk();
- case MXC_ESDHC_CLK:
- return get_usdhc_clk(0);
- case MXC_ESDHC2_CLK:
- return get_usdhc_clk(1);
- case MXC_ESDHC3_CLK:
- return get_usdhc_clk(2);
- case MXC_ESDHC4_CLK:
- return get_usdhc_clk(3);
- case MXC_SATA_CLK:
- return get_ahb_clk();
- default:
- printf("Unsupported MXC CLK: %d\n", clk);
- break;
- }
-
- return 0;
-}
-
-/*
- * Dump some core clockes.
- */
-int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 freq;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
- printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- printf("PLL_BUS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- printf("PLL_OTG %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, MXC_HCLK);
- printf("PLL_NET %8d MHz\n", freq / 1000000);
-
- printf("\n");
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
- printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
- printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
- printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
-
- return 0;
-}
-
-#ifndef CONFIG_MX6SX
-void enable_ipu_clock(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-}
-#endif
-/***************************************************/
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
- "display clocks",
- ""
-);
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
deleted file mode 100644
index 7a9b03a..0000000
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright (C) 2014 Gateworks Corporation
- * Author: Tim Harvey <tharvey@gateworks.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/types.h>
-
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-/* Configure MX6DQ mmdc iomux */
-void mx6dq_dram_iocfg(unsigned width,
- const struct mx6dq_iomux_ddr_regs *ddr,
- const struct mx6dq_iomux_grp_regs *grp)
-{
- volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
- volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
-
- /* DDR IO Type */
- mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
- mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
-
- /* Clock */
- mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
- mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
-
- /* Address */
- mx6_ddr_iomux->dram_cas = ddr->dram_cas;
- mx6_ddr_iomux->dram_ras = ddr->dram_ras;
- mx6_grp_iomux->grp_addds = grp->grp_addds;
-
- /* Control */
- mx6_ddr_iomux->dram_reset = ddr->dram_reset;
- mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
- mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
- mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
- mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
- mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
- mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
-
- /* Data Strobes */
- mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
- mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
- mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
- mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
- mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
- mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
- mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
- }
-
- /* Data */
- mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
- mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
- mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
- if (width >= 32) {
- mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
- mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
- }
- if (width >= 64) {
- mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
- mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
- mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
- mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
- }
- mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
- mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
- mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
- mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
- mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
- mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
- }
-}
-#endif
-
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
-/* Configure MX6SDL mmdc iomux */
-void mx6sdl_dram_iocfg(unsigned width,
- const struct mx6sdl_iomux_ddr_regs *ddr,
- const struct mx6sdl_iomux_grp_regs *grp)
-{
- volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
- volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
-
- /* DDR IO Type */
- mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
- mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
-
- /* Clock */
- mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
- mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
-
- /* Address */
- mx6_ddr_iomux->dram_cas = ddr->dram_cas;
- mx6_ddr_iomux->dram_ras = ddr->dram_ras;
- mx6_grp_iomux->grp_addds = grp->grp_addds;
-
- /* Control */
- mx6_ddr_iomux->dram_reset = ddr->dram_reset;
- mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
- mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
- mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
- mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
- mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
- mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
-
- /* Data Strobes */
- mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
- mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
- mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
- mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
- mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
- mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
- mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
- }
-
- /* Data */
- mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
- mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
- mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
- if (width >= 32) {
- mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
- mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
- }
- if (width >= 64) {
- mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
- mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
- mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
- mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
- }
- mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
- mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
- mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
- mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
- mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
- mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
- }
-}
-#endif
-
-/*
- * Configure mx6 mmdc registers based on:
- * - board-specific memory configuration
- * - board-specific calibration data
- * - ddr3 chip details
- *
- * The various calculations here are derived from the Freescale
- * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
- * configuration registers based on memory system and memory chip parameters.
- *
- * The defaults here are those which were specified in the spreadsheet.
- * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
- * section titled MMDC initialization
- */
-#define MR(val, ba, cmd, cs1) \
- ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
- const struct mx6_mmdc_calibration *calib,
- const struct mx6_ddr3_cfg *ddr3_cfg)
-{
- volatile struct mmdc_p_regs *mmdc0;
- volatile struct mmdc_p_regs *mmdc1;
- u32 val;
- u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
- u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
- u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
- u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
- u16 cs0_end;
- u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
- u8 coladdr;
- int clkper; /* clock period in picoseconds */
- int clock; /* clock freq in mHz */
- int cs;
-
- mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-
- /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
- clock = 528;
- tcwl = 4;
- }
- /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
- else {
- clock = 400;
- tcwl = 3;
- }
- clkper = (1000 * 1000) / clock; /* pico seconds */
- todtlon = tcwl;
- taxpd = tcwl;
- tanpd = tcwl;
-
- switch (ddr3_cfg->density) {
- case 1: /* 1Gb per chip */
- trfc = DIV_ROUND_UP(110000, clkper) - 1;
- txs = DIV_ROUND_UP(120000, clkper) - 1;
- break;
- case 2: /* 2Gb per chip */
- trfc = DIV_ROUND_UP(160000, clkper) - 1;
- txs = DIV_ROUND_UP(170000, clkper) - 1;
- break;
- case 4: /* 4Gb per chip */
- trfc = DIV_ROUND_UP(260000, clkper) - 1;
- txs = DIV_ROUND_UP(270000, clkper) - 1;
- break;
- case 8: /* 8Gb per chip */
- trfc = DIV_ROUND_UP(350000, clkper) - 1;
- txs = DIV_ROUND_UP(360000, clkper) - 1;
- break;
- default:
- /* invalid density */
- puts("invalid chip density\n");
- hang();
- break;
- }
- txpr = txs;
-
- switch (ddr3_cfg->mem_speed) {
- case 800:
- txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
- }
- break;
- case 1066:
- txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(37500, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
- }
- break;
- case 1333:
- txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(45000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
- }
- break;
- case 1600:
- txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
- }
- break;
- default:
- puts("invalid memory speed\n");
- hang();
- break;
- }
- txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
- tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
- taonpd = DIV_ROUND_UP(2000, clkper) - 1;
- tcksrx = tcksre;
- taofpd = taonpd;
- twr = DIV_ROUND_UP(15000, clkper) - 1;
- tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
- trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
- tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
- tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
- trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
- twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
- trcd = trp;
- trtp = twtr;
- cs0_end = 4 * sysinfo->cs_density - 1;
-
- debug("density:%d Gb (%d Gb per chip)\n",
- sysinfo->cs_density, ddr3_cfg->density);
- debug("clock: %dMHz (%d ps)\n", clock, clkper);
- debug("memspd:%d\n", ddr3_cfg->mem_speed);
- debug("tcke=%d\n", tcke);
- debug("tcksrx=%d\n", tcksrx);
- debug("tcksre=%d\n", tcksre);
- debug("taofpd=%d\n", taofpd);
- debug("taonpd=%d\n", taonpd);
- debug("todtlon=%d\n", todtlon);
- debug("tanpd=%d\n", tanpd);
- debug("taxpd=%d\n", taxpd);
- debug("trfc=%d\n", trfc);
- debug("txs=%d\n", txs);
- debug("txp=%d\n", txp);
- debug("txpdll=%d\n", txpdll);
- debug("tfaw=%d\n", tfaw);
- debug("tcl=%d\n", tcl);
- debug("trcd=%d\n", trcd);
- debug("trp=%d\n", trp);
- debug("trc=%d\n", trc);
- debug("tras=%d\n", tras);
- debug("twr=%d\n", twr);
- debug("tmrd=%d\n", tmrd);
- debug("tcwl=%d\n", tcwl);
- debug("tdllk=%d\n", tdllk);
- debug("trtp=%d\n", trtp);
- debug("twtr=%d\n", twtr);
- debug("trrd=%d\n", trrd);
- debug("txpr=%d\n", txpr);
- debug("cs0_end=%d\n", cs0_end);
- debug("ncs=%d\n", sysinfo->ncs);
- debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
- debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
- debug("SRT=%d\n", ddr3_cfg->SRT);
- debug("tcl=%d\n", tcl);
- debug("twr=%d\n", twr);
-
- /*
- * board-specific configuration:
- * These values are determined empirically and vary per board layout
- * see:
- * appnote, ddr3 spreadsheet
- */
- mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
- mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
- mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
- mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
- mmdc0->mprddlctl = calib->p0_mprddlctl;
- mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
- if (sysinfo->dsize > 1) {
- mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
- mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
- mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
- mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
- mmdc1->mprddlctl = calib->p1_mprddlctl;
- mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
- }
-
- /* Read data DQ Byte0-3 delay */
- mmdc0->mprddqby0dl = 0x33333333;
- mmdc0->mprddqby1dl = 0x33333333;
- if (sysinfo->dsize > 0) {
- mmdc0->mprddqby2dl = 0x33333333;
- mmdc0->mprddqby3dl = 0x33333333;
- }
-
- if (sysinfo->dsize > 1) {
- mmdc1->mprddqby0dl = 0x33333333;
- mmdc1->mprddqby1dl = 0x33333333;
- mmdc1->mprddqby2dl = 0x33333333;
- mmdc1->mprddqby3dl = 0x33333333;
- }
-
- /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
- val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
- mmdc0->mpodtctrl = val;
- if (sysinfo->dsize > 1)
- mmdc1->mpodtctrl = val;
-
- /* complete calibration */
- val = (1 << 11); /* Force measurement on delay-lines */
- mmdc0->mpmur0 = val;
- if (sysinfo->dsize > 1)
- mmdc1->mpmur0 = val;
-
- /* Step 1: configuration request */
- mmdc0->mdscr = (u32)(1 << 15); /* config request */
-
- /* Step 2: Timing configuration */
- mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
- (txpdll << 9) | (tfaw << 4) | tcl;
- mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
- (tras << 16) | (1 << 15) /* trpa */ |
- (twr << 9) | (tmrd << 5) | tcwl;
- mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
- mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
- (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
- mmdc0->mdasp = cs0_end; /* CS addressing */
-
- /* Step 3: Configure DDR type */
- mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
- (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
- (sysinfo->ralat << 6);
-
- /* Step 4: Configure delay while leaving reset */
- mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
- (sysinfo->rst_to_cke << 0);
-
- /* Step 5: Configure DDR physical parameters (density and burst len) */
- coladdr = ddr3_cfg->coladdr;
- if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
- coladdr += 4;
- else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
- coladdr += 1;
- mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
- (coladdr - 9) << 20 | /* COL */
- (1 << 19) | /* Burst Length = 8 for DDR3 */
- (sysinfo->dsize << 16); /* DDR data bus size */
-
- /* Step 6: Perform ZQ calibration */
- val = 0xa1390001; /* one-time HW ZQ calib */
- mmdc0->mpzqhwctrl = val;
- if (sysinfo->dsize > 1)
- mmdc1->mpzqhwctrl = val;
-
- /* Step 7: Enable MMDC with desired chip select */
- mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
- ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
-
- /* Step 8: Write Mode Registers to Init DDR3 devices */
- for (cs = 0; cs < sysinfo->ncs; cs++) {
- /* MR2 */
- val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
- ((tcwl - 3) & 3) << 3;
- mmdc0->mdscr = MR(val, 2, 3, cs);
- /* MR3 */
- mmdc0->mdscr = MR(0, 3, 3, cs);
- /* MR1 */
- val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
- ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
- mmdc0->mdscr = MR(val, 1, 3, cs);
- /* MR0 */
- val = ((tcl - 1) << 4) | /* CAS */
- (1 << 8) | /* DLL Reset */
- ((twr - 3) << 9); /* Write Recovery */
- mmdc0->mdscr = MR(val, 0, 3, cs);
- /* ZQ calibration */
- val = (1 << 10);
- mmdc0->mdscr = MR(val, 0, 4, cs);
- }
-
- /* Step 10: Power down control and self-refresh */
- mmdc0->mdpdc = (tcke & 0x7) << 16 |
- 5 << 12 | /* PWDT_1: 256 cycles */
- 5 << 8 | /* PWDT_0: 256 cycles */
- 1 << 7 | /* SLOW_PD */
- 1 << 6 | /* BOTH_CS_PD */
- (tcksrx & 0x7) << 3 |
- (tcksre & 0x7);
- mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
-
- /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
- val = 0xa1390003;
- mmdc0->mpzqhwctrl = val;
- if (sysinfo->dsize > 1)
- mmdc1->mpzqhwctrl = val;
-
- /* Step 12: Configure and activate periodic refresh */
- mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
- (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
-
- /* Step 13: Deassert config request - init complete */
- mmdc0->mdscr = 0x00000000;
-
- /* wait for auto-ZQ calibration to complete */
- mdelay(1);
-}
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
deleted file mode 100644
index 8dee595..0000000
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/arch/hab.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-/* -------- start of HAB API updates ------------*/
-
-#define hab_rvt_report_event_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
-)
-
-#define hab_rvt_report_status_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
-)
-
-#define hab_rvt_authenticate_image_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
-)
-
-#define hab_rvt_entry_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
-)
-
-#define hab_rvt_exit_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
-)
-
-#define IVT_SIZE 0x20
-#define ALIGN_SIZE 0x1000
-#define CSF_PAD_SIZE 0x2000
-#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
-#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
-#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
-
-/*
- * +------------+ 0x0 (DDR_UIMAGE_START) -
- * | Header | |
- * +------------+ 0x40 |
- * | | |
- * | | |
- * | | |
- * | | |
- * | Image Data | |
- * . | |
- * . | > Stuff to be authenticated ----+
- * . | | |
- * | | | |
- * | | | |
- * +------------+ | |
- * | | | |
- * | Fill Data | | |
- * | | | |
- * +------------+ Align to ALIGN_SIZE | |
- * | IVT | | |
- * +------------+ + IVT_SIZE - |
- * | | |
- * | CSF DATA | <---------------------------------------------------------+
- * | |
- * +------------+
- * | |
- * | Fill Data |
- * | |
- * +------------+ + CSF_PAD_SIZE
- */
-
-bool is_hab_enabled(void)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[0];
- struct fuse_bank0_regs *fuse =
- (struct fuse_bank0_regs *)bank->fuse_regs;
- uint32_t reg = readl(&fuse->cfg5);
-
- return (reg & 0x2) == 0x2;
-}
-
-void display_event(uint8_t *event_data, size_t bytes)
-{
- uint32_t i;
-
- if (!(event_data && bytes > 0))
- return;
-
- for (i = 0; i < bytes; i++) {
- if (i == 0)
- printf("\t0x%02x", event_data[i]);
- else if ((i % 8) == 0)
- printf("\n\t0x%02x", event_data[i]);
- else
- printf(" 0x%02x", event_data[i]);
- }
-}
-
-int get_hab_status(void)
-{
- uint32_t index = 0; /* Loop index */
- uint8_t event_data[128]; /* Event data buffer */
- size_t bytes = sizeof(event_data); /* Event size in bytes */
- enum hab_config config = 0;
- enum hab_state state = 0;
- hab_rvt_report_event_t *hab_rvt_report_event;
- hab_rvt_report_status_t *hab_rvt_report_status;
-
- hab_rvt_report_event = hab_rvt_report_event_p;
- hab_rvt_report_status = hab_rvt_report_status_p;
-
- if (is_hab_enabled())
- puts("\nSecure boot enabled\n");
- else
- puts("\nSecure boot disabled\n");
-
- /* Check HAB status */
- if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
- printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
- config, state);
-
- /* Display HAB Error events */
- while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
- &bytes) == HAB_SUCCESS) {
- puts("\n");
- printf("--------- HAB Event %d -----------------\n",
- index + 1);
- puts("event data:\n");
- display_event(event_data, bytes);
- puts("\n");
- bytes = sizeof(event_data);
- index++;
- }
- }
- /* Display message if no HAB events are found */
- else {
- printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
- config, state);
- puts("No HAB Events Found!\n\n");
- }
- return 0;
-}
-
-uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
-{
- uint32_t load_addr = 0;
- size_t bytes;
- ptrdiff_t ivt_offset = 0;
- int result = 0;
- ulong start;
- hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
- hab_rvt_entry_t *hab_rvt_entry;
- hab_rvt_exit_t *hab_rvt_exit;
-
- hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
- hab_rvt_entry = hab_rvt_entry_p;
- hab_rvt_exit = hab_rvt_exit_p;
-
- if (is_hab_enabled()) {
- printf("\nAuthenticate image from DDR location 0x%x...\n",
- ddr_start);
-
- hab_caam_clock_enable(1);
-
- if (hab_rvt_entry() == HAB_SUCCESS) {
- /* If not already aligned, Align to ALIGN_SIZE */
- ivt_offset = (image_size + ALIGN_SIZE - 1) &
- ~(ALIGN_SIZE - 1);
-
- start = ddr_start;
- bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
-#ifdef DEBUG
- printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
- ivt_offset, ddr_start + ivt_offset);
- puts("Dumping IVT\n");
- print_buffer(ddr_start + ivt_offset,
- (void *)(ddr_start + ivt_offset),
- 4, 0x8, 0);
-
- puts("Dumping CSF Header\n");
- print_buffer(ddr_start + ivt_offset+IVT_SIZE,
- (void *)(ddr_start + ivt_offset+IVT_SIZE),
- 4, 0x10, 0);
-
- get_hab_status();
-
- puts("\nCalling authenticate_image in ROM\n");
- printf("\tivt_offset = 0x%x\n", ivt_offset);
- printf("\tstart = 0x%08lx\n", start);
- printf("\tbytes = 0x%x\n", bytes);
-#endif
- /*
- * If the MMU is enabled, we have to notify the ROM
- * code, or it won't flush the caches when needed.
- * This is done, by setting the "pu_irom_mmu_enabled"
- * word to 1. You can find its address by looking in
- * the ROM map. This is critical for
- * authenticate_image(). If MMU is enabled, without
- * setting this bit, authentication will fail and may
- * crash.
- */
- /* Check MMU enabled */
- if (get_cr() & CR_M) {
- if (is_cpu_type(MXC_CPU_MX6Q) ||
- is_cpu_type(MXC_CPU_MX6D)) {
- /*
- * This won't work on Rev 1.0.0 of
- * i.MX6Q/D, since their ROM doesn't
- * do cache flushes. don't think any
- * exist, so we ignore them.
- */
- writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO)) {
- writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6SL)) {
- writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
- }
- }
-
- load_addr = (uint32_t)hab_rvt_authenticate_image(
- HAB_CID_UBOOT,
- ivt_offset, (void **)&start,
- (size_t *)&bytes, NULL);
- if (hab_rvt_exit() != HAB_SUCCESS) {
- puts("hab exit function fail\n");
- load_addr = 0;
- }
- } else {
- puts("hab entry function fail\n");
- }
-
- hab_caam_clock_enable(0);
-
- get_hab_status();
- } else {
- puts("hab fuse not enabled\n");
- }
-
- if ((!is_hab_enabled()) || (load_addr != 0))
- result = 1;
-
- return result;
-}
-
-int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if ((argc != 1)) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- get_hab_status();
-
- return 0;
-}
-
-static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- ulong addr, ivt_offset;
- int rcode = 0;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[1], NULL, 16);
- ivt_offset = simple_strtoul(argv[2], NULL, 16);
-
- rcode = authenticate_image(addr, ivt_offset);
-
- return rcode;
-}
-
-U_BOOT_CMD(
- hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
- "display HAB status",
- ""
- );
-
-U_BOOT_CMD(
- hab_auth_img, 3, 0, do_authenticate_image,
- "authenticate image via HAB",
- "addr ivt_offset\n"
- "addr - image hex address\n"
- "ivt_offset - hex offset of IVT in the image"
- );
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
deleted file mode 100644
index 9f034d6..0000000
--- a/arch/arm/cpu/armv7/mx6/mp.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2014
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/imx-regs.h>
-
-#define MAX_CPUS 4
-static struct src *src = (struct src *)SRC_BASE_ADDR;
-
-static uint32_t cpu_reset_mask[MAX_CPUS] = {
- 0, /* We don't really want to modify the cpu0 */
- SRC_SCR_CORE_1_RESET_MASK,
- SRC_SCR_CORE_2_RESET_MASK,
- SRC_SCR_CORE_3_RESET_MASK
-};
-
-static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
- 0, /* We don't really want to modify the cpu0 */
- SRC_SCR_CORE_1_ENABLE_MASK,
- SRC_SCR_CORE_2_ENABLE_MASK,
- SRC_SCR_CORE_3_ENABLE_MASK
-};
-
-int cpu_reset(int nr)
-{
- /* Software reset of the CPU N */
- src->scr |= cpu_reset_mask[nr];
- return 0;
-}
-
-int cpu_status(int nr)
-{
- printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
- return 0;
-}
-
-int cpu_release(int nr, int argc, char *const argv[])
-{
- uint32_t boot_addr;
-
- boot_addr = simple_strtoul(argv[0], NULL, 16);
-
- switch (nr) {
- case 1:
- src->gpr3 = boot_addr;
- break;
- case 2:
- src->gpr5 = boot_addr;
- break;
- case 3:
- src->gpr7 = boot_addr;
- break;
- default:
- return 1;
- }
-
- /* CPU N is ready to start */
- src->scr |= cpu_ctrl_mask[nr];
-
- return 0;
-}
-
-int is_core_valid(unsigned int core)
-{
- uint32_t nr_cores = get_nr_cpus();
-
- if (core > nr_cores)
- return 0;
-
- return 1;
-}
-
-int cpu_disable(int nr)
-{
- /* Disable the CPU N */
- src->scr &= ~cpu_ctrl_mask[nr];
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
deleted file mode 100644
index 5f5f497..0000000
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/bootm.h>
-#include <asm/pl310.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/dma.h>
-#include <stdbool.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/bootm.h>
-#include <dm.h>
-#include <imx_thermal.h>
-
-enum ldo_reg {
- LDO_ARM,
- LDO_SOC,
- LDO_PU,
-};
-
-struct scu_regs {
- u32 ctrl;
- u32 config;
- u32 status;
- u32 invalidate;
- u32 fpga_rev;
-};
-
-#if defined(CONFIG_IMX6_THERMAL)
-static const struct imx_thermal_plat imx6_thermal_plat = {
- .regs = (void *)ANATOP_BASE_ADDR,
- .fuse_bank = 1,
- .fuse_word = 6,
-};
-
-U_BOOT_DEVICE(imx6_thermal) = {
- .name = "imx_thermal",
- .platdata = &imx6_thermal_plat,
-};
-#endif
-
-u32 get_nr_cpus(void)
-{
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- return readl(&scu->config) & 3;
-}
-
-u32 get_cpu_rev(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 reg = readl(&anatop->digprog_sololite);
- u32 type = ((reg >> 16) & 0xff);
-
- if (type != MXC_CPU_MX6SL) {
- reg = readl(&anatop->digprog);
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- u32 cfg = readl(&scu->config) & 3;
- type = ((reg >> 16) & 0xff);
- if (type == MXC_CPU_MX6DL) {
- if (!cfg)
- type = MXC_CPU_MX6SOLO;
- }
-
- if (type == MXC_CPU_MX6Q) {
- if (cfg == 1)
- type = MXC_CPU_MX6D;
- }
-
- }
- reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- u32 cpurev = get_cpu_rev();
- u32 type = ((cpurev >> 12) & 0xff);
- if (type == MXC_CPU_MX6SOLO)
- cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
-
- if (type == MXC_CPU_MX6D)
- cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
-
- return cpurev;
-}
-#endif
-
-void init_aips(void)
-{
- struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
- struct aipstz_regs *aips3;
-#endif
-
- aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
- aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_MX6SX
- aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
-#endif
-
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips1->mprot0);
- writel(0x77777777, &aips1->mprot1);
- writel(0x77777777, &aips2->mprot0);
- writel(0x77777777, &aips2->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips1->opacr0);
- writel(0x00000000, &aips1->opacr1);
- writel(0x00000000, &aips1->opacr2);
- writel(0x00000000, &aips1->opacr3);
- writel(0x00000000, &aips1->opacr4);
- writel(0x00000000, &aips2->opacr0);
- writel(0x00000000, &aips2->opacr1);
- writel(0x00000000, &aips2->opacr2);
- writel(0x00000000, &aips2->opacr3);
- writel(0x00000000, &aips2->opacr4);
-
-#ifdef CONFIG_MX6SX
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips3->mprot0);
- writel(0x77777777, &aips3->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips3->opacr0);
- writel(0x00000000, &aips3->opacr1);
- writel(0x00000000, &aips3->opacr2);
- writel(0x00000000, &aips3->opacr3);
- writel(0x00000000, &aips3->opacr4);
-#endif
-}
-
-static void clear_ldo_ramp(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg;
-
- /* ROM may modify LDO ramp up time according to fuse setting, so in
- * order to be in the safe side we neeed to reset these settings to
- * match the reset value: 0'b00
- */
- reg = readl(&anatop->ana_misc2);
- reg &= ~(0x3f << 24);
- writel(reg, &anatop->ana_misc2);
-}
-
-/*
- * Set the PMU_REG_CORE register
- *
- * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
- * Possible values are from 0.725V to 1.450V in steps of
- * 0.025V (25mV).
- */
-static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 val, step, old, reg = readl(&anatop->reg_core);
- u8 shift;
-
- if (mv < 725)
- val = 0x00; /* Power gated off */
- else if (mv > 1450)
- val = 0x1F; /* Power FET switched full on. No regulation */
- else
- val = (mv - 700) / 25;
-
- clear_ldo_ramp();
-
- switch (ldo) {
- case LDO_SOC:
- shift = 18;
- break;
- case LDO_PU:
- shift = 9;
- break;
- case LDO_ARM:
- shift = 0;
- break;
- default:
- return -EINVAL;
- }
-
- old = (reg & (0x1F << shift)) >> shift;
- step = abs(val - old);
- if (step == 0)
- return 0;
-
- reg = (reg & ~(0x1F << shift)) | (val << shift);
- writel(reg, &anatop->reg_core);
-
- /*
- * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
- * step
- */
- udelay(3 * step);
-
- return 0;
-}
-
-static void imx_set_wdog_powerdown(bool enable)
-{
- struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
- struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
-
- /* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
-}
-
-static void set_ahb_rate(u32 val)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg, div;
-
- div = get_periph_clk() / val - 1;
- reg = readl(&mxc_ccm->cbcdr);
-
- writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
- (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
-}
-
-static void clear_mmdc_ch_mask(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* Clear MMDC channel mask */
- writel(0, &mxc_ccm->ccdr);
-}
-
-#ifdef CONFIG_MX6SL
-static void set_preclk_from_osc(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg;
-
- reg = readl(&mxc_ccm->cscmr1);
- reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
- writel(reg, &mxc_ccm->cscmr1);
-}
-#endif
-
-int arch_cpu_init(void)
-{
- init_aips();
-
- /* Need to clear MMDC_CHx_MASK to make warm reset work. */
- clear_mmdc_ch_mask();
-
- /*
- * When low freq boot is enabled, ROM will not set AHB
- * freq, so we need to ensure AHB freq is 132MHz in such
- * scenario.
- */
- if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
- set_ahb_rate(132000000);
-
- /* Set perclk to source from OSC 24MHz */
-#if defined(CONFIG_MX6SL)
- set_preclk_from_osc();
-#endif
-
- imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
-
-#ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
- mxs_dma_init();
-#endif
-
- return 0;
-}
-
-int board_postclk_init(void)
-{
- set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
-
- return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
- enum dcache_option option = DCACHE_WRITEBACK;
-#endif
-
- /* Avoid random hang when download by usb */
- invalidate_dcache_all();
-
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-
- /* Enable caching on OCRAM and ROM */
- mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
- ROMCP_ARB_END_ADDR,
- option);
- mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
- IRAM_SIZE,
- option);
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
-
- u32 value = readl(&fuse->mac_addr_high);
- mac[0] = (value >> 8);
- mac[1] = value ;
-
- value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
-
-}
-#endif
-
-void boot_mode_apply(unsigned cfg_val)
-{
- unsigned reg;
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- writel(cfg_val, &psrc->gpr9);
- reg = readl(&psrc->gpr10);
- if (cfg_val)
- reg |= 1 << 28;
- else
- reg &= ~(1 << 28);
- writel(reg, &psrc->gpr10);
-}
-/*
- * cfg_val will be used for
- * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
- * instead of SBMR1 to determine the boot device.
- */
-const struct boot_mode soc_boot_modes[] = {
- {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
- /* reserved value should start rom usb */
- {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
- {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
- {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
- {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
- {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
- {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
- /* 4 bit bus width */
- {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
- {NULL, 0},
-};
-
-void s_init(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 mask480;
- u32 mask528;
- u32 reg, periph1, periph2;
-
- if (is_cpu_type(MXC_CPU_MX6SX))
- return;
-
- /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
- * to make sure PFD is working right, otherwise, PFDs may
- * not output clock after reset, MX6DL and MX6SL have added 396M pfd
- * workaround in ROM code, as bus clock need it
- */
-
- mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
- ANATOP_PFD_CLKGATE_MASK(1) |
- ANATOP_PFD_CLKGATE_MASK(2) |
- ANATOP_PFD_CLKGATE_MASK(3);
- mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
- ANATOP_PFD_CLKGATE_MASK(3);
-
- reg = readl(&ccm->cbcmr);
- periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
- >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
- periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
- >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
-
- /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
- if ((periph2 != 0x2) && (periph1 != 0x2))
- mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
-
- if ((periph2 != 0x1) && (periph1 != 0x1) &&
- (periph2 != 0x3) && (periph1 != 0x3))
- mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
-
- writel(mask480, &anatop->pfd_480_set);
- writel(mask528, &anatop->pfd_528_set);
- writel(mask480, &anatop->pfd_480_clr);
- writel(mask528, &anatop->pfd_528_clr);
-}
-
-#ifdef CONFIG_IMX_HDMI
-void imx_enable_hdmi_phy(void)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
-
-void imx_setup_hdmi(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- int reg;
-
- /* Turn on HDMI PHY clock */
- reg = readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
- MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
- reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
- MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
- MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
- reg |= (CHSCCDR_PODF_DIVIDE_BY_3
- << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- |(CHSCCDR_IPU_PRE_CLK_540M_PFD
- << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-}
-#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
-void v7_outer_cache_enable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- unsigned int val;
-
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
- }
-#endif
-
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x132, &pl310->pl310_tag_latency_ctrl);
- writel(0x132, &pl310->pl310_data_latency_ctrl);
-
- val = readl(&pl310->pl310_prefetch_ctrl);
-
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
-
- /*
- * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
- * But according to ARM PL310 errata: 752271
- * ID: 752271: Double linefill feature can cause data corruption
- * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
- * Workaround: The only workaround to this erratum is to disable the
- * double linefill feature. This is the default behavior.
- */
-
-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
- writel(val, &pl310->pl310_prefetch_ctrl);
-
- val = readl(&pl310->pl310_power_ctrl);
- val |= L2X0_DYNAMIC_CLK_GATING_EN;
- val |= L2X0_STNDBY_MODE_EN;
- writel(val, &pl310->pl310_power_ctrl);
-
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
-void v7_outer_cache_disable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
-
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 30d81db..1773fae 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* code for switching cores into non-secure state and into HYP mode
*
* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
@@ -37,7 +36,7 @@
/*
* secure monitor handler
- * U-boot calls this "software interrupt" in start.S
+ * U-Boot calls this "software interrupt" in start.S
* This is executed on a "smc" instruction, we use a "smc #0" to switch
* to non-secure state.
* r0, r1, r2: passed to the callee
@@ -49,8 +48,27 @@
mcr p15, 0, r5, c12, c0, 1
isb
- @ Obtain a secure stack, and configure the PSCI backend
+ @ Obtain a secure stack
+ bl psci_stack_setup
+
+ @ Configure the PSCI backend
+ push {r0, r1, r2, ip}
bl psci_arch_init
+ pop {r0, r1, r2, ip}
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_773022
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 1)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_774769
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 25)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
#endif
mrc p15, 0, r5, c1, c1, 0 @ read SCR
@@ -62,6 +80,8 @@
#ifdef CONFIG_ARMV7_VIRT
orreq r5, r5, #0x100 @ allow HVC instruction
moveq r6, #HYP_MODE @ Enter the kernel as HYP
+ mrseq r3, sp_svc
+ msreq sp_hyp, r3 @ migrate SP
#endif
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
@@ -169,11 +189,11 @@
* we do this here instead.
* But first check if we have the generic timer.
*/
-#ifdef CONFIG_TIMER_CLK_FREQ
+#ifdef COUNTER_FREQUENCY
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
- ldreq r1, =CONFIG_TIMER_CLK_FREQ
+ ldreq r1, =COUNTER_FREQUENCY
mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
#endif
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
deleted file mode 100644
index 7695e16..0000000
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := reset.o
-obj-y += timer.o
-obj-y += utils.o
-
-ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
-obj-y += hwinit-common.o
-obj-y += clocks-common.o
-obj-y += emif-common.o
-obj-y += vc.o
-obj-y += abb.o
-endif
-
-ifneq ($(CONFIG_OMAP54XX),)
-obj-y += pipe3-phy.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
-endif
-
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
-obj-y += omap-cache.o
-endif
-
-ifeq ($(CONFIG_OMAP34XX),)
-obj-y += boot-common.o
-obj-y += lowlevel_init.o
-endif
-
-obj-y += mem-common.o
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c
deleted file mode 100644
index a0add66..0000000
--- a/arch/arm/cpu/armv7/omap-common/abb.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Adaptive Body Bias programming sequence for OMAP family
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-
-__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
-{
- return -1;
-}
-
-static void abb_setup_timings(u32 setup)
-{
- u32 sys_rate, sr2_cnt, clk_cycles;
-
- /*
- * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
- * transition and must be programmed with the correct time at boot.
- * The value programmed into the register is the number of SYS_CLK
- * clock cycles that match a given wall time profiled for the ldo.
- * This value depends on:
- * settling time of ldo in micro-seconds (varies per OMAP family),
- * of clock cycles per SYS_CLK period (varies per OMAP family),
- * the SYS_CLK frequency in MHz (varies per board)
- * The formula is:
- *
- * ldo settling time (in micro-seconds)
- * SR2_WTCNT_VALUE = ------------------------------------------
- * (# system clock cycles) * (sys_clk period)
- *
- * Put another way:
- *
- * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
- *
- * To avoid dividing by zero multiply both "# clock cycles" and
- * "settling time" by 10 such that the final result is the one we want.
- */
-
- /* calculate SR2_WTCNT_VALUE */
- sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
- clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
- sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
-
- setbits_le32(setup,
- sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
-}
-
-void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
- u32 txdone, u32 txdone_mask, u32 opp)
-{
- u32 abb_type_mask, opp_sel_mask;
-
- /* sanity check */
- if (!setup || !control || !txdone)
- return;
-
- /* setup ABB only in case of Fast or Slow OPP */
- switch (opp) {
- case OMAP_ABB_FAST_OPP:
- abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
- opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
- break;
- case OMAP_ABB_SLOW_OPP:
- abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
- opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
- break;
- default:
- return;
- }
-
- /*
- * For some OMAP silicons additional setup for LDOVBB register is
- * required. This is determined by data retrieved from corresponding
- * OPP EFUSE register. Data, which is retrieved from EFUSE - is
- * ABB enable/disable flag and VSET value, which must be copied
- * to LDOVBB register. If function call fails - return quietly,
- * it means no ABB is required for such silicon.
- *
- * For silicons, which don't require LDOVBB setup "fuse" and
- * "ldovbb" offsets are not defined. ABB will be initialized in
- * the common way for them.
- */
- if (fuse && ldovbb) {
- if (abb_setup_ldovbb(fuse, ldovbb))
- return;
- }
-
- /* clear ABB registers */
- writel(0, setup);
- writel(0, control);
-
- /* configure timings, based on oscillator value */
- abb_setup_timings(setup);
-
- /* clear pending interrupts before setup */
- setbits_le32(txdone, txdone_mask);
-
- /* select ABB type */
- setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
-
- /* initiate ABB ldo change */
- setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
-
- /* wait until transition complete */
- if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
- puts("Error: ABB txdone is not set\n");
-
- /* clear ABB tranxdone */
- setbits_le32(txdone, txdone_mask);
-}
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
deleted file mode 100644
index 00a1082..0000000
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * boot-common.c
- *
- * Common bootmode functions for omap based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <spl.h>
-#include <asm/omap_common.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <watchdog.h>
-#include <scsi.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void save_omap_boot_params(void)
-{
- u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
- u8 boot_device;
- u32 dev_desc, dev_data;
-
- if ((rom_params < NON_SECURE_SRAM_START) ||
- (rom_params > NON_SECURE_SRAM_END))
- return;
-
- /*
- * rom_params can be type casted to omap_boot_parameters and
- * used. But it not correct to assume that romcode structure
- * encoding would be same as u-boot. So use the defined offsets.
- */
- boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
-
-#if defined(BOOT_DEVICE_NAND_I2C)
- /*
- * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
- * Otherwise the SPL boot IF can't handle this device correctly.
- * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
- * Draco leads to this boot-device passed to SPL from the BootROM.
- */
- if (boot_device == BOOT_DEVICE_NAND_I2C)
- boot_device = BOOT_DEVICE_NAND;
-#endif
- gd->arch.omap_boot_params.omap_bootdevice = boot_device;
-
- gd->arch.omap_boot_params.ch_flags =
- *((u8 *)(rom_params + CH_FLAGS_OFFSET));
-
- if ((boot_device >= MMC_BOOT_DEVICES_START) &&
- (boot_device <= MMC_BOOT_DEVICES_END)) {
-#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \
- !defined(CONFIG_AM43XX)
- if ((omap_hw_init_context() ==
- OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
- gd->arch.omap_boot_params.omap_bootmode =
- *((u8 *)(rom_params + BOOT_MODE_OFFSET));
- } else
-#endif
- {
- dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
- dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
- gd->arch.omap_boot_params.omap_bootmode =
- *((u32 *)(dev_data + BOOT_MODE_OFFSET));
- }
- }
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- /*
- * We get different values for QSPI_1 and QSPI_4 being used, but
- * don't actually care about this difference. Rather than
- * mangle the later code, if we're coming in as QSPI_4 just
- * change to the QSPI_1 value.
- */
- if (gd->arch.omap_boot_params.omap_bootdevice == 11)
- gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI;
-#endif
-}
-
-#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_device(void)
-{
- return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
-}
-
-u32 spl_boot_mode(void)
-{
- u32 val = gd->arch.omap_boot_params.omap_bootmode;
-
- if (val == MMCSD_MODE_RAW)
- return MMCSD_MODE_RAW;
- else if (val == MMCSD_MODE_FS)
- return MMCSD_MODE_FS;
- else
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- return MMCSD_MODE_EMMCBOOT;
-#else
- return MMCSD_MODE_UNDEFINED;
-#endif
-}
-
-void spl_board_init(void)
-{
-#ifdef CONFIG_SPL_NAND_SUPPORT
- gpmc_init();
-#endif
-#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
- arch_misc_init();
-#endif
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-#ifdef CONFIG_AM33XX
- am33xx_spl_board_init();
-#endif
-}
-
-int board_mmc_init(bd_t *bis)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0, -1, -1);
- break;
- case BOOT_DEVICE_MMC2:
- case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(1, 0, 0, -1, -1);
- break;
- }
- return 0;
-}
-
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- typedef void __noreturn (*image_entry_noargs_t)(u32 *);
- image_entry_noargs_t image_entry =
- (image_entry_noargs_t) spl_image->entry_point;
-
- debug("image entry point: 0x%X\n", spl_image->entry_point);
- /* Pass the saved boot_params from rom code */
- image_entry((u32 *)&gd->arch.omap_boot_params);
-}
-#endif
-
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void arch_preboot_os(void)
-{
- ahci_reset(DWC_AHSATA_BASE);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
deleted file mode 100644
index 8e7411d..0000000
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/*
- *
- * Clock initialization for OMAP4
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * Based on previous work by:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Rajendra Nayak <rnayak@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <i2c.h>
-#include <asm/omap_common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-#include <asm/emif.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif
-
-const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 20000000, /* 20 MHz */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 27000000, /* 27 MHz */
- 38400000, /* 38.4 MHz */
-};
-
-static inline u32 __get_sys_clk_index(void)
-{
- s8 ind;
- /*
- * For ES1 the ROM code calibration of sys clock is not reliable
- * due to hw issue. So, use hard-coded value. If this value is not
- * correct for any board over-ride this function in board file
- * From ES2.0 onwards you will get this information from
- * CM_SYS_CLKSEL
- */
- if (omap_revision() == OMAP4430_ES1_0)
- ind = OMAP_SYS_CLK_IND_38_4_MHZ;
- else {
- /* SYS_CLKSEL - 1 to match the dpll param array indices */
- ind = (readl((*prcm)->cm_sys_clksel) &
- CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- }
- return ind;
-}
-
-u32 get_sys_clk_index(void)
- __attribute__ ((weak, alias("__get_sys_clk_index")));
-
-u32 get_sys_clk_freq(void)
-{
- u8 index = get_sys_clk_index();
- return sys_clk_array[index];
-}
-
-void setup_post_dividers(u32 const base, const struct dpll_params *params)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->m4_h11 >= 0)
- writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
- if (params->m5_h12 >= 0)
- writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
- if (params->m6_h13 >= 0)
- writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
- if (params->m7_h14 >= 0)
- writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
- if (params->h21 >= 0)
- writel(params->h21, &dpll_regs->cm_div_h21_dpll);
- if (params->h22 >= 0)
- writel(params->h22, &dpll_regs->cm_div_h22_dpll);
- if (params->h23 >= 0)
- writel(params->h23, &dpll_regs->cm_div_h23_dpll);
- if (params->h24 >= 0)
- writel(params->h24, &dpll_regs->cm_div_h24_dpll);
-}
-
-static inline void do_bypass_dpll(u32 const base)
-{
- struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
-
- clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_FAST_RELOCK_BYPASS <<
- CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_bypass(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
- LDELAY)) {
- printf("Bypassing DPLL failed %x\n", base);
- }
-}
-
-static inline void do_lock_dpll(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_lock(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
- &dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for %x\n", base);
- hang();
- }
-}
-
-inline u32 check_for_lock(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
- u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
-
- return lock;
-}
-
-const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->mpu[sysclk_ind];
-}
-
-const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->core[sysclk_ind];
-}
-
-const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->per[sysclk_ind];
-}
-
-const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->iva[sysclk_ind];
-}
-
-const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->usb[sysclk_ind];
-}
-
-const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
-{
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->abe[sysclk_ind];
-#else
- return dpll_data->abe;
-#endif
-}
-
-static const struct dpll_params *get_ddr_dpll_params
- (struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- if (!dpll_data->ddr)
- return NULL;
- return &dpll_data->ddr[sysclk_ind];
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static const struct dpll_params *get_gmac_dpll_params
- (struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- if (!dpll_data->gmac)
- return NULL;
- return &dpll_data->gmac[sysclk_ind];
-}
-#endif
-
-static void do_setup_dpll(u32 const base, const struct dpll_params *params,
- u8 lock, char *dpll)
-{
- u32 temp, M, N;
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!params)
- return;
-
- temp = readl(&dpll_regs->cm_clksel_dpll);
-
- if (check_for_lock(base)) {
- /*
- * The Dpll has already been locked by rom code using CH.
- * Check if M,N are matching with Ideal nominal opp values.
- * If matches, skip the rest otherwise relock.
- */
- M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
- N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
- if ((M != (params->m)) || (N != (params->n))) {
- debug("\n %s Dpll locked, but not for ideal M = %d,"
- "N = %d values, current values are M = %d,"
- "N= %d" , dpll, params->m, params->n,
- M, N);
- } else {
- /* Dpll locked with ideal values for nominal opps. */
- debug("\n %s Dpll already locked with ideal"
- "nominal opp values", dpll);
- goto setup_post_dividers;
- }
- }
-
- bypass_dpll(base);
-
- /* Set M & N */
- temp &= ~CM_CLKSEL_DPLL_M_MASK;
- temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
-
- temp &= ~CM_CLKSEL_DPLL_N_MASK;
- temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
-
- writel(temp, &dpll_regs->cm_clksel_dpll);
-
- /* Lock */
- if (lock)
- do_lock_dpll(base);
-
-setup_post_dividers:
- setup_post_dividers(base, params);
-
- /* Wait till the DPLL locks */
- if (lock)
- wait_for_lock(base);
-}
-
-u32 omap_ddr_clk(void)
-{
- u32 ddr_clk, sys_clk_khz, omap_rev, divider;
- const struct dpll_params *core_dpll_params;
-
- omap_rev = omap_revision();
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
- core_dpll_params = get_core_dpll_params(*dplls_data);
-
- debug("sys_clk %d\n ", sys_clk_khz * 1000);
-
- /* Find Core DPLL locked frequency first */
- ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
- (core_dpll_params->n + 1);
-
- if (omap_rev < OMAP5430_ES1_0) {
- /*
- * DDR frequency is PHY_ROOT_CLK/2
- * PHY_ROOT_CLK = Fdpll/2/M2
- */
- divider = 4;
- } else {
- /*
- * DDR frequency is PHY_ROOT_CLK
- * PHY_ROOT_CLK = Fdpll/2/M2
- */
- divider = 2;
- }
-
- ddr_clk = ddr_clk / divider / core_dpll_params->m2;
- ddr_clk *= 1000; /* convert to Hz */
- debug("ddr_clk %d\n ", ddr_clk);
-
- return ddr_clk;
-}
-
-/*
- * Lock MPU dpll
- *
- * Resulting MPU frequencies:
- * 4430 ES1.0 : 600 MHz
- * 4430 ES2.x : 792 MHz (OPP Turbo)
- * 4460 : 920 MHz (OPP Turbo) - DCC disabled
- */
-void configure_mpu_dpll(void)
-{
- const struct dpll_params *params;
- struct dpll_regs *mpu_dpll_regs;
- u32 omap_rev;
- omap_rev = omap_revision();
-
- /*
- * DCC and clock divider settings for 4460.
- * DCC is required, if more than a certain frequency is required.
- * For, 4460 > 1GHZ.
- * 5430 > 1.4GHZ.
- */
- if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
- mpu_dpll_regs =
- (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
- bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
- clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
- clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
- CM_CLKSEL_DCC_EN_MASK);
- }
-
- params = get_mpu_dpll_params(*dplls_data);
-
- do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
- debug("MPU DPLL locked\n");
-}
-
-#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
-static void setup_usb_dpll(void)
-{
- const struct dpll_params *params;
- u32 sys_clk_khz, sd_div, num, den;
-
- sys_clk_khz = get_sys_clk_freq() / 1000;
- /*
- * USB:
- * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
- * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
- * - where CLKINP is sys_clk in MHz
- * Use CLKINP in KHz and adjust the denominator accordingly so
- * that we have enough accuracy and at the same time no overflow
- */
- params = get_usb_dpll_params(*dplls_data);
- num = params->m * sys_clk_khz;
- den = (params->n + 1) * 250 * 1000;
- num += den - 1;
- sd_div = num / den;
- clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
- CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
- sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
-
- /* Now setup the dpll with the regular function */
- do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
-}
-#endif
-
-static void setup_dplls(void)
-{
- u32 temp;
- const struct dpll_params *params;
-
- debug("setup_dplls\n");
-
- /* CORE dpll */
- params = get_core_dpll_params(*dplls_data); /* default - safest */
- /*
- * Do not lock the core DPLL now. Just set it up.
- * Core DPLL will be locked after setting up EMIF
- * using the FREQ_UPDATE method(freq_update_core())
- */
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
- do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
- DPLL_NO_LOCK, "core");
- else
- do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
- DPLL_LOCK, "core");
- /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
- temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
- (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
- (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
- writel(temp, (*prcm)->cm_clksel_core);
- debug("Core DPLL configured\n");
-
- /* lock PER dpll */
- params = get_per_dpll_params(*dplls_data);
- do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
- params, DPLL_LOCK, "per");
- debug("PER DPLL locked\n");
-
- /* MPU dpll */
- configure_mpu_dpll();
-
-#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
- setup_usb_dpll();
-#endif
- params = get_ddr_dpll_params(*dplls_data);
- do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
- params, DPLL_LOCK, "ddr");
-
-#ifdef CONFIG_DRIVER_TI_CPSW
- params = get_gmac_dpll_params(*dplls_data);
- do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
- DPLL_LOCK, "gmac");
-#endif
-}
-
-u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
-{
- u32 offset_code;
-
- volt_offset -= pmic->base_offset;
-
- offset_code = (volt_offset + pmic->step - 1) / pmic->step;
-
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- return offset_code + pmic->start_code;
-}
-
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
-{
- u32 offset_code;
- u32 offset = volt_mv;
- int ret = 0;
-
- if (!volt_mv)
- return;
-
- pmic->pmic_bus_init();
- /* See if we can first get the GPIO if needed */
- if (pmic->gpio_en)
- ret = gpio_request(pmic->gpio, "PMIC_GPIO");
-
- if (ret < 0) {
- printf("%s: gpio %d request failed %d\n", __func__,
- pmic->gpio, ret);
- return;
- }
-
- /* Pull the GPIO low to select SET0 register, while we program SET1 */
- if (pmic->gpio_en)
- gpio_direction_output(pmic->gpio, 0);
-
- /* convert to uV for better accuracy in the calculations */
- offset *= 1000;
-
- offset_code = get_offset_code(offset, pmic);
-
- debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
- offset_code);
-
- if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
- printf("Scaling voltage failed for 0x%x\n", vcore_reg);
-
- if (pmic->gpio_en)
- gpio_direction_output(pmic->gpio, 1);
-}
-
-static u32 optimize_vcore_voltage(struct volts const *v)
-{
- u32 val;
- if (!v->value)
- return 0;
- if (!v->efuse.reg)
- return v->value;
-
- switch (v->efuse.reg_bits) {
- case 16:
- val = readw(v->efuse.reg);
- break;
- case 32:
- val = readl(v->efuse.reg);
- break;
- default:
- printf("Error: efuse 0x%08x bits=%d unknown\n",
- v->efuse.reg, v->efuse.reg_bits);
- return v->value;
- }
-
- if (!val) {
- printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
- v->efuse.reg, v->efuse.reg_bits, v->value);
- return v->value;
- }
-
- debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
- __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
- return val;
-}
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-void scale_vcores(struct vcores_data const *vcores)
-{
- u32 val;
-
- val = optimize_vcore_voltage(&vcores->core);
- do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
-
- val = optimize_vcore_voltage(&vcores->mpu);
- do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
-
- /* Configure MPU ABB LDO after scale */
- abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
- (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
- (*prcm)->prm_abbldo_mpu_setup,
- (*prcm)->prm_abbldo_mpu_ctrl,
- (*prcm)->prm_irqstatus_mpu_2,
- OMAP_ABB_MPU_TXDONE_MASK,
- OMAP_ABB_FAST_OPP);
-
- val = optimize_vcore_voltage(&vcores->mm);
- do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
-
- val = optimize_vcore_voltage(&vcores->gpu);
- do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
-
- val = optimize_vcore_voltage(&vcores->eve);
- do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
-
- val = optimize_vcore_voltage(&vcores->iva);
- do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
-}
-
-static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %x\n", clkctrl_reg);
-}
-
-static inline void wait_for_clk_enable(u32 clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
- u32 bound = LDELAY;
-
- while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
- (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
-
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock enable failed for 0x%x idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-
-static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
- u32 wait_for_enable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %x\n", clkctrl_addr);
- if (wait_for_enable)
- wait_for_clk_enable(clkctrl_addr);
-}
-
-void freq_update_core(void)
-{
- u32 freq_config1 = 0;
- const struct dpll_params *core_dpll_params;
- u32 omap_rev = omap_revision();
-
- core_dpll_params = get_core_dpll_params(*dplls_data);
- /* Put EMIF clock domain in sw wakeup mode */
- enable_clock_domain((*prcm)->cm_memif_clkstctrl,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
-
- freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
- SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
-
- freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
- SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
-
- freq_config1 |= (core_dpll_params->m2 <<
- SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
- SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
-
- writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
- if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
- (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
- puts("FREQ UPDATE procedure failed!!");
- hang();
- }
-
- /*
- * Putting EMIF in HW_AUTO is seen to be causing issues with
- * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
- * in OMAP5430 ES1.0 silicon
- */
- if (omap_rev != OMAP5430_ES1_0) {
- /* Put EMIF clock domain back in hw auto mode */
- enable_clock_domain((*prcm)->cm_memif_clkstctrl,
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
- }
-}
-
-void bypass_dpll(u32 const base)
-{
- do_bypass_dpll(base);
- wait_for_bypass(base);
-}
-
-void lock_dpll(u32 const base)
-{
- do_lock_dpll(base);
- wait_for_lock(base);
-}
-
-void setup_clocks_for_console(void)
-{
- /* Do not add any spl_debug prints in this function */
- clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
- /* Enable all UARTs - console will be on one of them */
- clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-}
-
-void do_enable_clocks(u32 const *clk_domains,
- u32 const *clk_modules_hw_auto,
- u32 const *clk_modules_explicit_en,
- u8 wait_for_enable)
-{
- u32 i, max = 100;
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
- enable_clock_domain(clk_domains[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in HW_AUTO */
- for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
- enable_clock_module(clk_modules_hw_auto[i],
- MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
- wait_for_enable);
- };
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
- enable_clock_module(clk_modules_explicit_en[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-
- /* Put the clock domains in HW_AUTO mode now */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
- enable_clock_domain(clk_domains[i],
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- }
-}
-
-void prcm_init(void)
-{
- switch (omap_hw_init_context()) {
- case OMAP_INIT_CONTEXT_SPL:
- case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
- enable_basic_clocks();
- timer_init();
- scale_vcores(*omap_vcores);
- setup_dplls();
- setup_warmreset_time();
- break;
- default:
- break;
- }
-
- if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
- enable_basic_uboot_clocks();
-}
-
-void gpi2c_init(void)
-{
- static int gpi2c = 1;
-
- if (gpi2c) {
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
- gpi2c = 0;
- }
-}
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
deleted file mode 100644
index e601ba1..0000000
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ /dev/null
@@ -1,1359 +0,0 @@
-/*
- * EMIF programming
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/emif.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/utils.h>
-#include <linux/compiler.h>
-
-static int emif1_enabled = -1, emif2_enabled = -1;
-
-void set_lpmode_selfrefresh(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 reg;
-
- reg = readl(&emif->emif_pwr_mgmt_ctrl);
- reg &= ~EMIF_REG_LP_MODE_MASK;
- reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
- reg &= ~EMIF_REG_SR_TIM_MASK;
- writel(reg, &emif->emif_pwr_mgmt_ctrl);
-
- /* dummy read for the new SR_TIM to be loaded */
- readl(&emif->emif_pwr_mgmt_ctrl);
-}
-
-void force_emif_self_refresh()
-{
- set_lpmode_selfrefresh(EMIF1_BASE);
- set_lpmode_selfrefresh(EMIF2_BASE);
-}
-
-inline u32 emif_num(u32 base)
-{
- if (base == EMIF1_BASE)
- return 1;
- else if (base == EMIF2_BASE)
- return 2;
- else
- return 0;
-}
-
-static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
-{
- u32 mr;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
- if (omap_revision() == OMAP4430_ES2_0)
- mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
- else
- mr = readl(&emif->emif_lpddr2_mode_reg_data);
- debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
- cs, mr_addr, mr);
- if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
- ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
- ((mr & 0xff000000) >> 24) == (mr & 0xff))
- return mr & 0xff;
- else
- return mr;
-}
-
-static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
- writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
-}
-
-void emif_reset_phy(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 iodft;
-
- iodft = readl(&emif->emif_iodft_tlgc);
- iodft |= EMIF_REG_RESET_PHY_MASK;
- writel(iodft, &emif->emif_iodft_tlgc);
-}
-
-static void do_lpddr2_init(u32 base, u32 cs)
-{
- u32 mr_addr;
- const struct lpddr2_mr_regs *mr_regs;
-
- get_lpddr2_mr_regs(&mr_regs);
- /* Wait till device auto initialization is complete */
- while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
- ;
- set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
- /*
- * tZQINIT = 1 us
- * Enough loops assuming a maximum of 2GHz
- */
-
- sdelay(2000);
-
- set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
- set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
-
- /*
- * Enable refresh along with writing MR2
- * Encoding of RL in MR2 is (RL - 2)
- */
- mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, mr_regs->mr2);
-
- if (mr_regs->mr3 > 0)
- set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
-}
-
-static void lpddr2_init(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /* Not NVM */
- clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
-
- /*
- * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
- * when EMIF_SDRAM_CONFIG register is written
- */
- setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
-
- /*
- * Set the SDRAM_CONFIG and PHY_CTRL for the
- * un-locked frequency & default RL
- */
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
-
- do_ext_phy_settings(base, regs);
-
- do_lpddr2_init(base, CS0);
- if (regs->sdram_config & EMIF_REG_EBANK_MASK)
- do_lpddr2_init(base, CS1);
-
- writel(regs->sdram_config, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-
- /* Enable refresh now */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
-
- }
-
-__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
-{
-}
-
-void emif_update_timings(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
- writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
- writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
- writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
- if (omap_revision() == OMAP4430_ES1_0) {
- /* ES1 bug EMIF should be in force idle during freq_update */
- writel(0, &emif->emif_pwr_mgmt_ctrl);
- } else {
- writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
- writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
- }
- writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
- writel(regs->zq_config, &emif->emif_zq_config);
- writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-
- if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
- &emif->emif_l3_config);
- } else if (omap_revision() >= OMAP4460_ES1_0) {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
- &emif->emif_l3_config);
- } else {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
- &emif->emif_l3_config);
- }
-}
-
-static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /* keep sdram in self-refresh */
- writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
- & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
- __udelay(130);
-
- /*
- * Set invert_clkout (if activated)--DDR_PHYCTRL_1
- * Invert clock adds an additional half cycle delay on the
- * command interface. The additional half cycle, is usually
- * meant to enable leveling in the situation that DQS is later
- * than CK on the board.It also helps provide some additional
- * margin for leveling.
- */
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif->emif_ddr_phy_ctrl_1);
-
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif->emif_ddr_phy_ctrl_1_shdw);
- __udelay(130);
-
- writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
- & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
-
- /* Launch Full leveling */
- writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
- /* Wait till full leveling is complete */
- readl(&emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
-
- /* Read data eye leveling no of samples */
- config_data_eye_leveling_samples(base);
-
- /*
- * Launch 8 incremental WR_LVL- to compensate for
- * PHY limitation.
- */
- writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
- &emif->emif_rd_wr_lvl_ctl);
-
- __udelay(130);
-
- /* Launch Incremental leveling */
- writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
-}
-
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
- if (is_omap54xx())
- omap5_ddr3_leveling(base, regs);
-}
-
-static void ddr3_init(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /*
- * Set SDRAM_CONFIG and PHY control registers to locked frequency
- * and RL =7. As the default values of the Mode Registers are not
- * defined, contents of mode Registers must be fully initialized.
- * H/W takes care of this initialization
- */
- writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
-
- /* Update timing registers */
- writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
- writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
- writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
-
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
- writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
-
- /*
- * The same sequence should work on OMAP5432 as well. But strange that
- * it is not working
- */
- if (is_dra7xx()) {
- do_ext_phy_settings(base, regs);
- writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- } else {
- writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- do_ext_phy_settings(base, regs);
- }
-
- /* enable leveling */
- writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
-
- ddr3_leveling(base, regs);
-}
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-
-/*
- * Organization and refresh requirements for LPDDR2 devices of different
- * types and densities. Derived from JESD209-2 section 2.4
- */
-const struct lpddr2_addressing addressing_table[] = {
- /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
- {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
- {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
- {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
- {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
- {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
- {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
- {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
- {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
- {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
- {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
-};
-
-static const u32 lpddr2_density_2_size_in_mbytes[] = {
- 8, /* 64Mb */
- 16, /* 128Mb */
- 32, /* 256Mb */
- 64, /* 512Mb */
- 128, /* 1Gb */
- 256, /* 2Gb */
- 512, /* 4Gb */
- 1024, /* 8Gb */
- 2048, /* 16Gb */
- 4096 /* 32Gb */
-};
-
-/*
- * Calculate the period of DDR clock from frequency value and set the
- * denominator and numerator in global variables for easy access later
- */
-static void set_ddr_clk_period(u32 freq)
-{
- /*
- * period = 1/freq
- * period_in_ns = 10^9/freq
- */
- *T_num = 1000000000;
- *T_den = freq;
- cancel_out(T_num, T_den, 200);
-
-}
-
-/*
- * Convert time in nano seconds to number of cycles of DDR clock
- */
-static inline u32 ns_2_cycles(u32 ns)
-{
- return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
-}
-
-/*
- * ns_2_cycles with the difference that the time passed is 2 times the actual
- * value(to avoid fractions). The cycles returned is for the original value of
- * the timing parameter
- */
-static inline u32 ns_x2_2_cycles(u32 ns)
-{
- return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
-}
-
-/*
- * Find addressing table index based on the device's type(S2 or S4) and
- * density
- */
-s8 addressing_table_index(u8 type, u8 density, u8 width)
-{
- u8 index;
- if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
- return -1;
-
- /*
- * Look at the way ADDR_TABLE_INDEX* values have been defined
- * in emif.h compared to LPDDR2_DENSITY_* values
- * The table is layed out in the increasing order of density
- * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
- * at the end
- */
- if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
- index = ADDR_TABLE_INDEX1GS2;
- else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
- index = ADDR_TABLE_INDEX2GS2;
- else
- index = density;
-
- debug("emif: addressing table index %d\n", index);
-
- return index;
-}
-
-/*
- * Find the the right timing table from the array of timing
- * tables of the device using DDR clock frequency
- */
-static const struct lpddr2_ac_timings *get_timings_table(const struct
- lpddr2_ac_timings const *const *device_timings,
- u32 freq)
-{
- u32 i, temp, freq_nearest;
- const struct lpddr2_ac_timings *timings = 0;
-
- emif_assert(freq <= MAX_LPDDR2_FREQ);
- emif_assert(device_timings);
-
- /*
- * Start with the maximum allowed frequency - that is always safe
- */
- freq_nearest = MAX_LPDDR2_FREQ;
- /*
- * Find the timings table that has the max frequency value:
- * i. Above or equal to the DDR frequency - safe
- * ii. The lowest that satisfies condition (i) - optimal
- */
- for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
- temp = device_timings[i]->max_freq;
- if ((temp >= freq) && (temp <= freq_nearest)) {
- freq_nearest = temp;
- timings = device_timings[i];
- }
- }
- debug("emif: timings table: %d\n", freq_nearest);
- return timings;
-}
-
-/*
- * Finds the value of emif_sdram_config_reg
- * All parameters are programmed based on the device on CS0.
- * If there is a device on CS1, it will be same as that on CS0 or
- * it will be NVM. We don't support NVM yet.
- * If cs1_device pointer is NULL it is assumed that there is no device
- * on CS1
- */
-static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
- const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 RL)
-{
- u32 config_reg = 0;
-
- config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
- config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
- EMIF_REG_IBANK_POS_SHIFT;
-
- config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
-
- config_reg |= RL << EMIF_REG_CL_SHIFT;
-
- config_reg |= addressing->row_sz[cs0_device->io_width] <<
- EMIF_REG_ROWSIZE_SHIFT;
-
- config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
-
- config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
- EMIF_REG_EBANK_SHIFT;
-
- config_reg |= addressing->col_sz[cs0_device->io_width] <<
- EMIF_REG_PAGESIZE_SHIFT;
-
- return config_reg;
-}
-
-static u32 get_sdram_ref_ctrl(u32 freq,
- const struct lpddr2_addressing *addressing)
-{
- u32 ref_ctrl = 0, val = 0, freq_khz;
- freq_khz = freq / 1000;
- /*
- * refresh rate to be set is 'tREFI * freq in MHz
- * division by 10000 to account for khz and x10 in t_REFI_us_x10
- */
- val = addressing->t_REFI_us_x10 * freq_khz / 10000;
- ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
-
- return ref_ctrl;
-}
-
-static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck,
- const struct lpddr2_addressing *addressing)
-{
- u32 tim1 = 0, val = 0;
- val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
- tim1 |= val << EMIF_REG_T_WTR_SHIFT;
-
- if (addressing->num_banks == BANKS8)
- val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
- (4 * (*T_num)) - 1;
- else
- val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
-
- tim1 |= val << EMIF_REG_T_RRD_SHIFT;
-
- val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
- tim1 |= val << EMIF_REG_T_RC_SHIFT;
-
- val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
- tim1 |= val << EMIF_REG_T_RAS_SHIFT;
-
- val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
- tim1 |= val << EMIF_REG_T_WR_SHIFT;
-
- val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
- tim1 |= val << EMIF_REG_T_RCD_SHIFT;
-
- val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
- tim1 |= val << EMIF_REG_T_RP_SHIFT;
-
- return tim1;
-}
-
-static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck)
-{
- u32 tim2 = 0, val = 0;
- val = max(min_tck->tCKE, timings->tCKE) - 1;
- tim2 |= val << EMIF_REG_T_CKE_SHIFT;
-
- val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
- tim2 |= val << EMIF_REG_T_RTP_SHIFT;
-
- /*
- * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
- * same value
- */
- val = ns_2_cycles(timings->tXSR) - 1;
- tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
- tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
-
- val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
- tim2 |= val << EMIF_REG_T_XP_SHIFT;
-
- return tim2;
-}
-
-static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck,
- const struct lpddr2_addressing *addressing)
-{
- u32 tim3 = 0, val = 0;
- val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
- tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
-
- val = ns_2_cycles(timings->tRFCab) - 1;
- tim3 |= val << EMIF_REG_T_RFC_SHIFT;
-
- val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
- tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
-
- val = ns_2_cycles(timings->tZQCS) - 1;
- tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
-
- val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
- tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
-
- return tim3;
-}
-
-static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 volt_ramp)
-{
- u32 zq = 0, val = 0;
- if (volt_ramp)
- val =
- EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
- addressing->t_REFI_us_x10;
- else
- val =
- EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
- addressing->t_REFI_us_x10;
- zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
-
- zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
-
- zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
-
- zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
-
- /*
- * Assuming that two chipselects have a single calibration resistor
- * If there are indeed two calibration resistors, then this flag should
- * be enabled to take advantage of dual calibration feature.
- * This data should ideally come from board files. But considering
- * that none of the boards today have calibration resistors per CS,
- * it would be an unnecessary overhead.
- */
- zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
-
- zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
-
- zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
-
- return zq;
-}
-
-static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 is_derated)
-{
- u32 alert = 0, interval;
- interval =
- TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
- if (is_derated)
- interval *= 4;
- alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
-
- alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
-
- alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
-
- alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
-
- alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
-
- alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
-
- return alert;
-}
-
-static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
-{
- u32 idle = 0, val = 0;
- if (volt_ramp)
- val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
- else
- /*Maximum value in normal conditions - suggested by hw team */
- val = 0x1FF;
- idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
-
- idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
-
- return idle;
-}
-
-static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
-{
- u32 phy = 0, val = 0;
-
- phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
-
- if (freq <= 100000000)
- val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
- else if (freq <= 200000000)
- val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
- else
- val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
- phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
-
- /* Other fields are constant magic values. Hardcode them together */
- phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
- EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
-
- return phy;
-}
-
-static u32 get_emif_mem_size(u32 base)
-{
- u32 size_mbytes = 0, temp;
- struct emif_device_details dev_details;
- struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- u32 emif_nr = emif_num(base);
-
- emif_reset_phy(base);
- dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
- &cs0_dev_details);
- dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
- &cs1_dev_details);
- emif_reset_phy(base);
-
- if (dev_details.cs0_device_details) {
- temp = dev_details.cs0_device_details->density;
- size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
- }
-
- if (dev_details.cs1_device_details) {
- temp = dev_details.cs1_device_details->density;
- size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
- }
- /* convert to bytes */
- return size_mbytes << 20;
-}
-
-/* Gets the encoding corresponding to a given DMM section size */
-u32 get_dmm_section_size_map(u32 section_size)
-{
- /*
- * Section size mapping:
- * 0x0: 16-MiB section
- * 0x1: 32-MiB section
- * 0x2: 64-MiB section
- * 0x3: 128-MiB section
- * 0x4: 256-MiB section
- * 0x5: 512-MiB section
- * 0x6: 1-GiB section
- * 0x7: 2-GiB section
- */
- section_size >>= 24; /* divide by 16 MB */
- return log_2_n_round_down(section_size);
-}
-
-static void emif_calculate_regs(
- const struct emif_device_details *emif_dev_details,
- u32 freq, struct emif_regs *regs)
-{
- u32 temp, sys_freq;
- const struct lpddr2_addressing *addressing;
- const struct lpddr2_ac_timings *timings;
- const struct lpddr2_min_tck *min_tck;
- const struct lpddr2_device_details *cs0_dev_details =
- emif_dev_details->cs0_device_details;
- const struct lpddr2_device_details *cs1_dev_details =
- emif_dev_details->cs1_device_details;
- const struct lpddr2_device_timings *cs0_dev_timings =
- emif_dev_details->cs0_device_timings;
-
- emif_assert(emif_dev_details);
- emif_assert(regs);
- /*
- * You can not have a device on CS1 without one on CS0
- * So configuring EMIF without a device on CS0 doesn't
- * make sense
- */
- emif_assert(cs0_dev_details);
- emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
- /*
- * If there is a device on CS1 it should be same type as CS0
- * (or NVM. But NVM is not supported in this driver yet)
- */
- emif_assert((cs1_dev_details == NULL) ||
- (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
- (cs0_dev_details->type == cs1_dev_details->type));
- emif_assert(freq <= MAX_LPDDR2_FREQ);
-
- set_ddr_clk_period(freq);
-
- /*
- * The device on CS0 is used for all timing calculations
- * There is only one set of registers for timings per EMIF. So, if the
- * second CS(CS1) has a device, it should have the same timings as the
- * device on CS0
- */
- timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
- emif_assert(timings);
- min_tck = cs0_dev_timings->min_tck;
-
- temp = addressing_table_index(cs0_dev_details->type,
- cs0_dev_details->density,
- cs0_dev_details->io_width);
-
- emif_assert((temp >= 0));
- addressing = &(addressing_table[temp]);
- emif_assert(addressing);
-
- sys_freq = get_sys_clk_freq();
-
- regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
- cs1_dev_details,
- addressing, RL_BOOT);
-
- regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
- cs1_dev_details,
- addressing, RL_FINAL);
-
- regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
-
- regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
-
- regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
-
- regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
-
- regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
-
- regs->temp_alert_config =
- get_temp_alert_config(cs1_dev_details, addressing, 0);
-
- regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
- LPDDR2_VOLTAGE_STABLE);
-
- regs->emif_ddr_phy_ctlr_1_init =
- get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
-
- regs->emif_ddr_phy_ctlr_1 =
- get_ddr_phy_ctrl_1(freq, RL_FINAL);
-
- regs->freq = freq;
-
- print_timing_reg(regs->sdram_config_init);
- print_timing_reg(regs->sdram_config);
- print_timing_reg(regs->ref_ctrl);
- print_timing_reg(regs->sdram_tim1);
- print_timing_reg(regs->sdram_tim2);
- print_timing_reg(regs->sdram_tim3);
- print_timing_reg(regs->read_idle_ctrl);
- print_timing_reg(regs->temp_alert_config);
- print_timing_reg(regs->zq_config);
- print_timing_reg(regs->emif_ddr_phy_ctlr_1);
- print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
-}
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-const char *get_lpddr2_type(u8 type_id)
-{
- switch (type_id) {
- case LPDDR2_TYPE_S4:
- return "LPDDR2-S4";
- case LPDDR2_TYPE_S2:
- return "LPDDR2-S2";
- default:
- return NULL;
- }
-}
-
-const char *get_lpddr2_io_width(u8 width_id)
-{
- switch (width_id) {
- case LPDDR2_IO_WIDTH_8:
- return "x8";
- case LPDDR2_IO_WIDTH_16:
- return "x16";
- case LPDDR2_IO_WIDTH_32:
- return "x32";
- default:
- return NULL;
- }
-}
-
-const char *get_lpddr2_manufacturer(u32 manufacturer)
-{
- switch (manufacturer) {
- case LPDDR2_MANUFACTURER_SAMSUNG:
- return "Samsung";
- case LPDDR2_MANUFACTURER_QIMONDA:
- return "Qimonda";
- case LPDDR2_MANUFACTURER_ELPIDA:
- return "Elpida";
- case LPDDR2_MANUFACTURER_ETRON:
- return "Etron";
- case LPDDR2_MANUFACTURER_NANYA:
- return "Nanya";
- case LPDDR2_MANUFACTURER_HYNIX:
- return "Hynix";
- case LPDDR2_MANUFACTURER_MOSEL:
- return "Mosel";
- case LPDDR2_MANUFACTURER_WINBOND:
- return "Winbond";
- case LPDDR2_MANUFACTURER_ESMT:
- return "ESMT";
- case LPDDR2_MANUFACTURER_SPANSION:
- return "Spansion";
- case LPDDR2_MANUFACTURER_SST:
- return "SST";
- case LPDDR2_MANUFACTURER_ZMOS:
- return "ZMOS";
- case LPDDR2_MANUFACTURER_INTEL:
- return "Intel";
- case LPDDR2_MANUFACTURER_NUMONYX:
- return "Numonyx";
- case LPDDR2_MANUFACTURER_MICRON:
- return "Micron";
- default:
- return NULL;
- }
-}
-
-static void display_sdram_details(u32 emif_nr, u32 cs,
- struct lpddr2_device_details *device)
-{
- const char *mfg_str;
- const char *type_str;
- char density_str[10];
- u32 density;
-
- debug("EMIF%d CS%d\t", emif_nr, cs);
-
- if (!device) {
- debug("None\n");
- return;
- }
-
- mfg_str = get_lpddr2_manufacturer(device->manufacturer);
- type_str = get_lpddr2_type(device->type);
-
- density = lpddr2_density_2_size_in_mbytes[device->density];
- if ((density / 1024 * 1024) == density) {
- density /= 1024;
- sprintf(density_str, "%d GB", density);
- } else
- sprintf(density_str, "%d MB", density);
- if (mfg_str && type_str)
- debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
-}
-
-static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
- struct lpddr2_device_details *lpddr2_device)
-{
- u32 mr = 0, temp;
-
- mr = get_mr(base, cs, LPDDR2_MR0);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
- if (temp) {
- /* Not SDRAM */
- return 0;
- }
- temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
-
- if (temp) {
- /* DNV supported - But DNV is only supported for NVM */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR4);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR5);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- if (!get_lpddr2_manufacturer(mr)) {
- /* Manufacturer not identified */
- return 0;
- }
- lpddr2_device->manufacturer = mr;
-
- mr = get_mr(base, cs, LPDDR2_MR6);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR7);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR8);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
- if (!get_lpddr2_type(temp)) {
- /* Not SDRAM */
- return 0;
- }
- lpddr2_device->type = temp;
-
- temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
- if (temp > LPDDR2_DENSITY_32Gb) {
- /* Density not supported */
- return 0;
- }
- lpddr2_device->density = temp;
-
- temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
- if (!get_lpddr2_io_width(temp)) {
- /* IO width unsupported value */
- return 0;
- }
- lpddr2_device->io_width = temp;
-
- /*
- * If all the above tests pass we should
- * have a device on this chip-select
- */
- return 1;
-}
-
-struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
- struct lpddr2_device_details *lpddr2_dev_details)
-{
- u32 phy;
- u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
-
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- if (!lpddr2_dev_details)
- return NULL;
-
- /* Do the minimum init for mode register accesses */
- if (!(running_from_sdram() || warm_reset())) {
- phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
- writel(phy, &emif->emif_ddr_phy_ctrl_1);
- }
-
- if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
- return NULL;
-
- display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
-
- return lpddr2_dev_details;
-}
-#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
-
-static void do_sdram_init(u32 base)
-{
- const struct emif_regs *regs;
- u32 in_sdram, emif_nr;
-
- debug(">>do_sdram_init() %x\n", base);
-
- in_sdram = running_from_sdram();
- emif_nr = (base == EMIF1_BASE) ? 1 : 2;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
- emif_get_reg_dump(emif_nr, ®s);
- if (!regs) {
- debug("EMIF: reg dump not provided\n");
- return;
- }
-#else
- /*
- * The user has not provided the register values. We need to
- * calculate it based on the timings and the DDR frequency
- */
- struct emif_device_details dev_details;
- struct emif_regs calculated_regs;
-
- /*
- * Get device details:
- * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
- * - Obtained from user otherwise
- */
- struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- emif_reset_phy(base);
- dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
- &cs0_dev_details);
- dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
- &cs1_dev_details);
- emif_reset_phy(base);
-
- /* Return if no devices on this EMIF */
- if (!dev_details.cs0_device_details &&
- !dev_details.cs1_device_details) {
- return;
- }
-
- /*
- * Get device timings:
- * - Default timings specified by JESD209-2 if
- * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
- * - Obtained from user otherwise
- */
- emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
- &dev_details.cs1_device_timings);
-
- /* Calculate the register values */
- emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
- regs = &calculated_regs;
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
- /*
- * Initializing the LPDDR2 device can not happen from SDRAM.
- * Changing the timing registers in EMIF can happen(going from one
- * OPP to another)
- */
- if (!(in_sdram || warm_reset())) {
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
- lpddr2_init(base, regs);
- else
- ddr3_init(base, regs);
- }
- if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
- set_lpmode_selfrefresh(base);
- emif_reset_phy(base);
- ddr3_leveling(base, regs);
- }
-
- /* Write to the shadow registers */
- emif_update_timings(base, regs);
-
- debug("<<do_sdram_init() %x\n", base);
-}
-
-void emif_post_init_config(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 omap_rev = omap_revision();
-
- /* reset phy on ES2.0 */
- if (omap_rev == OMAP4430_ES2_0)
- emif_reset_phy(base);
-
- /* Put EMIF back in smart idle on ES1.0 */
- if (omap_rev == OMAP4430_ES1_0)
- writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
-}
-
-void dmm_init(u32 base)
-{
- const struct dmm_lisa_map_regs *lisa_map_regs;
- u32 i, section, valid;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
- emif_get_dmm_regs(&lisa_map_regs);
-#else
- u32 emif1_size, emif2_size, mapped_size, section_map = 0;
- u32 section_cnt, sys_addr;
- struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
-
- mapped_size = 0;
- section_cnt = 3;
- sys_addr = CONFIG_SYS_SDRAM_BASE;
- emif1_size = get_emif_mem_size(EMIF1_BASE);
- emif2_size = get_emif_mem_size(EMIF2_BASE);
- debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
-
- if (!emif1_size && !emif2_size)
- return;
-
- /* symmetric interleaved section */
- if (emif1_size && emif2_size) {
- mapped_size = min(emif1_size, emif2_size);
- section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
- section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= (sys_addr >> 24) <<
- EMIF_SYS_ADDR_SHIFT;
- section_map |= get_dmm_section_size_map(mapped_size * 2)
- << EMIF_SYS_SIZE_SHIFT;
- lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
- emif1_size -= mapped_size;
- emif2_size -= mapped_size;
- sys_addr += (mapped_size * 2);
- section_cnt--;
- }
-
- /*
- * Single EMIF section(we can have a maximum of 1 single EMIF
- * section- either EMIF1 or EMIF2 or none, but not both)
- */
- if (emif1_size) {
- section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
- section_map |= get_dmm_section_size_map(emif1_size)
- << EMIF_SYS_SIZE_SHIFT;
- /* only MSB */
- section_map |= (mapped_size >> 24) <<
- EMIF_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
- section_cnt--;
- }
- if (emif2_size) {
- section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
- section_map |= get_dmm_section_size_map(emif2_size) <<
- EMIF_SYS_SIZE_SHIFT;
- /* only MSB */
- section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
- section_cnt--;
- }
-
- if (section_cnt == 2) {
- /* Only 1 section - either symmetric or single EMIF */
- lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
- lis_map_regs_calculated.dmm_lisa_map_2 = 0;
- lis_map_regs_calculated.dmm_lisa_map_1 = 0;
- } else {
- /* 2 sections - 1 symmetric, 1 single EMIF */
- lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
- lis_map_regs_calculated.dmm_lisa_map_1 = 0;
- }
-
- /* TRAP for invalid TILER mappings in section 0 */
- lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
-
- if (omap_revision() >= OMAP4460_ES1_0)
- lis_map_regs_calculated.is_ma_present = 1;
-
- lisa_map_regs = &lis_map_regs_calculated;
-#endif
- struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)base;
-
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- writel(lisa_map_regs->dmm_lisa_map_3,
- &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(lisa_map_regs->dmm_lisa_map_2,
- &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(lisa_map_regs->dmm_lisa_map_1,
- &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(lisa_map_regs->dmm_lisa_map_0,
- &hw_lisa_map_regs->dmm_lisa_map_0);
-
- if (lisa_map_regs->is_ma_present) {
- hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)MA_BASE;
-
- writel(lisa_map_regs->dmm_lisa_map_3,
- &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(lisa_map_regs->dmm_lisa_map_2,
- &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(lisa_map_regs->dmm_lisa_map_1,
- &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(lisa_map_regs->dmm_lisa_map_0,
- &hw_lisa_map_regs->dmm_lisa_map_0);
- }
-
- /*
- * EMIF should be configured only when
- * memory is mapped on it. Using emif1_enabled
- * and emif2_enabled variables for this.
- */
- emif1_enabled = 0;
- emif2_enabled = 0;
- for (i = 0; i < 4; i++) {
- section = __raw_readl(DMM_BASE + i*4);
- valid = (section & EMIF_SDRC_MAP_MASK) >>
- (EMIF_SDRC_MAP_SHIFT);
- if (valid == 3) {
- emif1_enabled = 1;
- emif2_enabled = 1;
- break;
- }
-
- if (valid == 1)
- emif1_enabled = 1;
-
- if (valid == 2)
- emif2_enabled = 1;
- }
-}
-
-static void do_bug0039_workaround(u32 base)
-{
- u32 val, i, clkctrl;
- struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
- const struct read_write_regs *bug_00339_regs;
- u32 iterations;
- u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
- u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
-
- if (is_dra7xx())
- phy_status_base++;
-
- bug_00339_regs = get_bug_regs(&iterations);
-
- /* Put EMIF in to idle */
- clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
- __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
-
- /* Copy the phy status registers in to phy ctrl shadow registers */
- for (i = 0; i < iterations; i++) {
- val = __raw_readl(phy_status_base +
- bug_00339_regs[i].read_reg - 1);
-
- __raw_writel(val, phy_ctrl_base +
- ((bug_00339_regs[i].write_reg - 1) << 1));
-
- __raw_writel(val, phy_ctrl_base +
- (bug_00339_regs[i].write_reg << 1) - 1);
- }
-
- /* Disable leveling */
- writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
-
- __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
-}
-
-/*
- * SDRAM initialization:
- * SDRAM initialization has two parts:
- * 1. Configuring the SDRAM device
- * 2. Update the AC timings related parameters in the EMIF module
- * (1) should be done only once and should not be done while we are
- * running from SDRAM.
- * (2) can and should be done more than once if OPP changes.
- * Particularly, this may be needed when we boot without SPL and
- * and using Configuration Header(CH). ROM code supports only at 50% OPP
- * at boot (low power boot). So u-boot has to switch to OPP100 and update
- * the frequency. So,
- * Doing (1) and (2) makes sense - first time initialization
- * Doing (2) and not (1) makes sense - OPP change (when using CH)
- * Doing (1) and not (2) doen't make sense
- * See do_sdram_init() for the details
- */
-void sdram_init(void)
-{
- u32 in_sdram, size_prog, size_detect;
- u32 sdram_type = emif_sdram_type();
-
- debug(">>sdram_init()\n");
-
- if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
- return;
-
- in_sdram = running_from_sdram();
- debug("in_sdram = %d\n", in_sdram);
-
- if (!in_sdram) {
- if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
- bypass_dpll((*prcm)->cm_clkmode_dpll_core);
- else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
- writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
- }
-
- if (!in_sdram)
- dmm_init(DMM_BASE);
-
- if (emif1_enabled)
- do_sdram_init(EMIF1_BASE);
-
- if (emif2_enabled)
- do_sdram_init(EMIF2_BASE);
-
- if (!(in_sdram || warm_reset())) {
- if (emif1_enabled)
- emif_post_init_config(EMIF1_BASE);
- if (emif2_enabled)
- emif_post_init_config(EMIF2_BASE);
- }
-
- /* for the shadow registers to take effect */
- if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
- freq_update_core();
-
- /* Do some testing after the init */
- if (!in_sdram) {
- size_prog = omap_sdram_size();
- size_prog = log_2_n_round_down(size_prog);
- size_prog = (1 << size_prog);
-
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- size_prog);
- /* Compare with the size programmed */
- if (size_detect != size_prog) {
- printf("SDRAM: identified size not same as expected"
- " size identified: %x expected: %x\n",
- size_detect,
- size_prog);
- } else
- debug("get_ram_size() successful");
- }
-
- if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
- (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
- if (emif1_enabled)
- do_bug0039_workaround(EMIF1_BASE);
- if (emif2_enabled)
- do_bug0039_workaround(EMIF2_BASE);
- }
-
- debug("<<sdram_init()\n");
-}
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
deleted file mode 100644
index dd52e93..0000000
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- *
- * Common functions for OMAP4/5 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <spl.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/sizes.h>
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-#include <linux/compiler.h>
-#include <asm/system.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
-{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
- for (i = 0; i < size; i++, pad++)
- writew(pad->val, base + pad->offset);
-}
-
-static void set_mux_conf_regs(void)
-{
- switch (omap_hw_init_context()) {
- case OMAP_INIT_CONTEXT_SPL:
- set_muxconf_regs_essential();
- break;
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
- break;
- case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
- set_muxconf_regs_essential();
- break;
- }
-}
-
-u32 cortex_rev(void)
-{
-
- unsigned int rev;
-
- /* Read Main ID Register (MIDR) */
- asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
-
- return rev;
-}
-
-static void omap_rev_string(void)
-{
- u32 omap_rev = omap_revision();
- u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
- u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
- u32 major_rev = (omap_rev & 0x00000F00) >> 8;
- u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
-
- if (soc_variant)
- printf("OMAP");
- else
- printf("DRA");
- printf("%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
-}
-
-#ifdef CONFIG_SPL_BUILD
-void spl_display_print(void)
-{
- omap_rev_string();
-}
-#endif
-
-void __weak srcomp_enable(void)
-{
-}
-
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * SOC specific cpu init
- */
-int arch_cpu_init(void)
-{
- save_omap_boot_params();
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * Routine: s_init
- * Description: Does early system init of watchdog, muxing, andclocks
- * Watchdog disable is done always. For the rest what gets done
- * depends on the boot mode in which this function is executed
- * 1. s_init of SPL running from SRAM
- * 2. s_init of U-Boot running from FLASH
- * 3. s_init of U-Boot loaded to SDRAM by SPL
- * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
- * Configuration Header feature
- * Please have a look at the respective functions to see what gets
- * done in each of these cases
- * This function is called with SRAM stack.
- */
-void s_init(void)
-{
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
- init_omap_revision();
- hw_data_init();
-
-#ifdef CONFIG_SPL_BUILD
- if (warm_reset() &&
- (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
- force_emif_self_refresh();
-#endif
- watchdog_init();
- set_mux_conf_regs();
-#ifdef CONFIG_SPL_BUILD
- srcomp_enable();
- setup_clocks_for_console();
-
- gd = &gdata;
-
- preloader_console_init();
- do_io_settings();
-#endif
- prcm_init();
-#ifdef CONFIG_SPL_BUILD
-#ifdef CONFIG_BOARD_EARLY_INIT_F
- board_early_init_f();
-#endif
- /* For regular u-boot sdram_init() is called from dram_init() */
- sdram_init();
-#endif
-}
-
-/*
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- */
-void wait_for_command_complete(struct watchdog *wd_base)
-{
- int pending = 1;
- do {
- pending = readl(&wd_base->wwps);
- } while (pending);
-}
-
-/*
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- */
-void watchdog_init(void)
-{
- struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
-
- writel(WD_UNLOCK1, &wd2_base->wspr);
- wait_for_command_complete(wd2_base);
- writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-
-/*
- * This function finds the SDRAM size available in the system
- * based on DMM section configurations
- * This is needed because the size of memory installed may be
- * different on different versions of the board
- */
-u32 omap_sdram_size(void)
-{
- u32 section, i, valid;
- u64 sdram_start = 0, sdram_end = 0, addr,
- size, total_size = 0, trap_size = 0, trap_start = 0;
-
- for (i = 0; i < 4; i++) {
- section = __raw_readl(DMM_BASE + i*4);
- valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
- (EMIF_SDRC_ADDRSPC_SHIFT);
- addr = section & EMIF_SYS_ADDR_MASK;
-
- /* See if the address is valid */
- if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
- (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
- size = ((section & EMIF_SYS_SIZE_MASK) >>
- EMIF_SYS_SIZE_SHIFT);
- size = 1 << size;
- size *= SZ_16M;
-
- if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
- if (!sdram_start || (addr < sdram_start))
- sdram_start = addr;
- if (!sdram_end || ((addr + size) > sdram_end))
- sdram_end = addr + size;
- } else {
- trap_size = size;
- trap_start = addr;
- }
- }
- }
-
- if ((trap_start >= sdram_start) && (trap_start < sdram_end))
- total_size = (sdram_end - sdram_start) - (trap_size);
- else
- total_size = sdram_end - sdram_start;
-
- return total_size;
-}
-
-
-/*
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- */
-int dram_init(void)
-{
- sdram_init();
- gd->ram_size = omap_sdram_size();
- return 0;
-}
-
-/*
- * Print board information
- */
-int checkboard(void)
-{
- puts(sysinfo.board_string);
- return 0;
-}
-
-/*
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- return (readl((*ctrl)->control_status) &
- (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- puts("CPU : ");
- omap_rev_string();
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
deleted file mode 100644
index 86c0e42..0000000
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/omap.h>
-#include <asm/omap_common.h>
-#include <asm/arch/spl.h>
-#include <linux/linkage.h>
-
-ENTRY(save_boot_params)
- ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
- str r0, [r1]
- bx lr
-ENDPROC(save_boot_params)
-
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
- @ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
- @ call ROM Code API to set control register
- POP {r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
deleted file mode 100644
index fc4290c..0000000
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Mansoor Ahamed <mansoor.ahamed@ti.com>
- *
- * Initial Code from:
- * Manikandan Pillai <mani.pillai@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-#include <linux/mtd/omap_gpmc.h>
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_OMAP34XX)
-/********************************************************
- * mem_ok() - test used to see if timings are correct
- * for a part. Helps in guessing which part
- * we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
- u32 val1, val2, addr;
- u32 pattern = 0x12345678;
-
- addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
- writel(0x0, addr + 0x400); /* clear pos A */
- writel(pattern, addr); /* pattern to pos B */
- writel(0x0, addr + 4); /* remove pattern off the bus */
- val1 = readl(addr + 0x400); /* get pos A value */
- val2 = readl(addr); /* get val2 */
- writel(0x0, addr + 0x400); /* clear pos A */
-
- if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
- return 0;
- else
- return 1;
-}
-#endif
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
- u32 size)
-{
- writel(0, &cs->config7);
- sdelay(1000);
- /* Delay for settling */
- writel(gpmc_config[0], &cs->config1);
- writel(gpmc_config[1], &cs->config2);
- writel(gpmc_config[2], &cs->config3);
- writel(gpmc_config[3], &cs->config4);
- writel(gpmc_config[4], &cs->config5);
- writel(gpmc_config[5], &cs->config6);
- /* Enable the config */
- writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
- (1 << 6)), &cs->config7);
- sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
- /* putting a blanket check on GPMC based on ZeBu for now */
- gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_NOR)
-/* configure GPMC for NOR */
- const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
- STNOR_GPMC_CONFIG2,
- STNOR_GPMC_CONFIG3,
- STNOR_GPMC_CONFIG4,
- STNOR_GPMC_CONFIG5,
- STNOR_GPMC_CONFIG6,
- STNOR_GPMC_CONFIG7
- };
- u32 base = CONFIG_SYS_FLASH_BASE;
- u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
- /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
- /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
- /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
- /* min 16MB */ GPMC_SIZE_16M)));
-#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
-/* configure GPMC for NAND */
- const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
- M_NAND_GPMC_CONFIG2,
- M_NAND_GPMC_CONFIG3,
- M_NAND_GPMC_CONFIG4,
- M_NAND_GPMC_CONFIG5,
- M_NAND_GPMC_CONFIG6,
- 0
- };
- u32 base = CONFIG_SYS_NAND_BASE;
- u32 size = GPMC_SIZE_16M;
-
-#elif defined(CONFIG_CMD_ONENAND)
- const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
- ONENAND_GPMC_CONFIG2,
- ONENAND_GPMC_CONFIG3,
- ONENAND_GPMC_CONFIG4,
- ONENAND_GPMC_CONFIG5,
- ONENAND_GPMC_CONFIG6,
- 0
- };
- u32 size = GPMC_SIZE_128M;
- u32 base = CONFIG_SYS_ONENAND_BASE;
-#else
- const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
- u32 size = 0;
- u32 base = 0;
-#endif
- /* global settings */
- writel(0x00000008, &gpmc_cfg->sysconfig);
- writel(0x00000000, &gpmc_cfg->irqstatus);
- writel(0x00000000, &gpmc_cfg->irqenable);
- /* disable timeout, set a safe reset value */
- writel(0x00001ff0, &gpmc_cfg->timeout_control);
-#ifdef CONFIG_NOR
- writel(0x00000200, &gpmc_cfg->config);
-#else
- writel(0x00000012, &gpmc_cfg->config);
-#endif
- /*
- * Disable the GPMC0 config set by ROM code
- */
- writel(0, &gpmc_cfg->cs[0].config7);
- sdelay(1000);
- /* enable chip-select specific configurations */
- if (base != 0)
- enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
-}
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c
deleted file mode 100644
index 579bebf..0000000
--- a/arch/arm/cpu/armv7/omap-common/omap-cache.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *
- * Common functions for OMAP4/5 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/cache.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ARMV7_DCACHE_WRITEBACK 0xe
-#define ARMV7_DOMAIN_CLIENT 1
-#define ARMV7_DOMAIN_MASK (0x3 << 0)
-
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
- bd_t *bd = gd->bd;
- int i;
-
- u32 start = bd->bi_dram[bank].start >> 20;
- u32 size = bd->bi_dram[bank].size >> 20;
- u32 end = start + size;
-
- debug("%s: bank: %d\n", __func__, bank);
- for (i = start; i < end; i++)
- set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-}
-
-void arm_init_domains(void)
-{
- u32 reg;
-
- reg = get_dacr();
- /*
- * Set DOMAIN to client access so that all permissions
- * set in pagetables are validated by the mmu.
- */
- reg &= ~ARMV7_DOMAIN_MASK;
- reg |= ARMV7_DOMAIN_CLIENT;
- set_dacr(reg);
-}
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
deleted file mode 100644
index b71d769..0000000
--- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <sata.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include "pipe3-phy.h"
-
-/* PLLCTRL Registers */
-#define PLL_STATUS 0x00000004
-#define PLL_GO 0x00000008
-#define PLL_CONFIGURATION1 0x0000000C
-#define PLL_CONFIGURATION2 0x00000010
-#define PLL_CONFIGURATION3 0x00000014
-#define PLL_CONFIGURATION4 0x00000020
-
-#define PLL_REGM_MASK 0x001FFE00
-#define PLL_REGM_SHIFT 9
-#define PLL_REGM_F_MASK 0x0003FFFF
-#define PLL_REGM_F_SHIFT 0
-#define PLL_REGN_MASK 0x000001FE
-#define PLL_REGN_SHIFT 1
-#define PLL_SELFREQDCO_MASK 0x0000000E
-#define PLL_SELFREQDCO_SHIFT 1
-#define PLL_SD_MASK 0x0003FC00
-#define PLL_SD_SHIFT 10
-#define SET_PLL_GO 0x1
-#define PLL_TICOPWDN BIT(16)
-#define PLL_LDOPWDN BIT(15)
-#define PLL_LOCK 0x2
-#define PLL_IDLE 0x1
-
-/* PHY POWER CONTROL Register */
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
-
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
-
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
-
-
-#define PLL_IDLE_TIME 100 /* in milliseconds */
-#define PLL_LOCK_TIME 100 /* in milliseconds */
-
-static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
-{
- return __raw_readl(addr + offset);
-}
-
-static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
- u32 data)
-{
- __raw_writel(data, addr + offset);
-}
-
-static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
- *pipe3)
-{
- u32 rate;
- struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
-
- rate = get_sys_clk_freq();
-
- for (; dpll_map->rate; dpll_map++) {
- if (rate == dpll_map->rate)
- return &dpll_map->params;
- }
-
- printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
- __func__, rate);
- return NULL;
-}
-
-
-static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_LOCK_TIME;
-
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (val & PLL_LOCK)
- break;
- } while (--timeout);
-
- if (!(val & PLL_LOCK)) {
- printf("%s: DPLL failed to lock\n", __func__);
- return -EBUSY;
- }
-
- return 0;
-}
-
-static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
-{
- u32 val;
- struct pipe3_dpll_params *dpll_params;
-
- dpll_params = omap_pipe3_get_dpll_params(phy);
- if (!dpll_params) {
- printf("%s: Invalid DPLL parameters\n", __func__);
- return -EINVAL;
- }
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGN_MASK;
- val |= dpll_params->n << PLL_REGN_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val &= ~PLL_SELFREQDCO_MASK;
- val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGM_MASK;
- val |= dpll_params->m << PLL_REGM_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
- val &= ~PLL_REGM_F_MASK;
- val |= dpll_params->mf << PLL_REGM_F_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
- val &= ~PLL_SD_MASK;
- val |= dpll_params->sd << PLL_SD_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
-
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- return omap_pipe3_wait_lock(phy);
-}
-
-static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
-{
- u32 val, rate;
-
- val = readl(phy->power_reg);
-
- rate = get_sys_clk_freq();
- rate = rate/1000000;
-
- if (on) {
- val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- val |= rate <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
- } else {
- val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- }
-
- writel(val, phy->power_reg);
-}
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy)
-{
- int ret;
- u32 val;
-
- /* Program the DPLL only if not locked */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (!(val & PLL_LOCK)) {
- ret = omap_pipe3_dpll_program(phy);
- if (ret)
- return ret;
- } else {
- /* else just bring it out of IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- if (val & PLL_IDLE) {
- val &= ~PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base,
- PLL_CONFIGURATION2, val);
- ret = omap_pipe3_wait_lock(phy);
- if (ret)
- return ret;
- }
- }
-
- /* Power up the PHY */
- omap_control_phy_power(phy, 1);
-
- return 0;
-}
-
-int phy_pipe3_power_off(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_IDLE_TIME;
-
- /* Power down the PHY */
- omap_control_phy_power(phy, 0);
-
- /* Put DPLL in IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- /* wait for LDO and Oscillator to power down */
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
- break;
- } while (--timeout);
-
- if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
- printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
- __func__, val);
- return -EBUSY;
- }
-
- return 0;
-}
-
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
deleted file mode 100644
index 441f49a..0000000
--- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OMAP_PIPE3_PHY_H
-#define __OMAP_PIPE3_PHY_H
-
-struct pipe3_dpll_params {
- u16 m;
- u8 n;
- u8 freq:3;
- u8 sd;
- u32 mf;
-};
-
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-struct omap_pipe3 {
- void __iomem *pll_ctrl_base;
- void __iomem *power_reg;
- struct pipe3_dpll_map *dpll_map;
-};
-
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy);
-int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
-
-#endif /* __OMAP_PIPE3_PHY_H */
diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c
deleted file mode 100644
index 91ad031..0000000
--- a/arch/arm/cpu/armv7/omap-common/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *
- * Common layer for reset related functionality of OMAP based socs.
- *
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <linux/compiler.h>
-
-void __weak reset_cpu(unsigned long ignored)
-{
- writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
-}
-
-u32 __weak warm_reset(void)
-{
- return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
-}
-
-void __weak setup_warmreset_time(void)
-{
-}
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
deleted file mode 100644
index d18bc50..0000000
--- a/arch/arm/cpu/armv7/omap-common/sata.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TI SATA platform driver
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <scsi.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sata.h>
-#include <sata.h>
-#include <asm/io.h>
-#include "pipe3-phy.h"
-
-static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
- {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
- { }, /* Terminator */
-};
-
-struct omap_pipe3 sata_phy = {
- .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
- /* .power_reg is updated at runtime */
- .dpll_map = dpll_map_sata,
-};
-
-int init_sata(int dev)
-{
- int ret;
- u32 val;
-
- u32 const clk_domains_sata[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_sata[] = {
- (*prcm)->cm_l3init_ocp2scp3_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_sata[] = {
- (*prcm)->cm_l3init_sata_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_sata,
- clk_modules_hw_auto_sata,
- clk_modules_explicit_en_sata,
- 0);
-
- /* Enable optional functional clock for SATA */
- setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
- SATA_CLKCTRL_OPTFCLKEN_MASK);
-
- sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
-
- /* Power up the PHY */
- phy_pipe3_power_on(&sata_phy);
-
- /* Enable SATA module, No Idle, No Standby */
- val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
- writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
-
- ret = ahci_init(DWC_AHSATA_BASE);
-
- return ret;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-/* On OMAP platforms SATA provides the SCSI subsystem */
-void scsi_init(void)
-{
- init_sata(0);
- scsi_scan(1);
-}
-
-void scsi_bus_reset(void)
-{
- ahci_reset(DWC_AHSATA_BASE);
- ahci_init(DWC_AHSATA_BASE);
-}
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
deleted file mode 100644
index 032bd2c..0000000
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Moahmmed Khasim <khasim@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
-
-/*
- * Nothing really to do with interrupts, just starts up a counter.
- */
-
-#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
-#define TIMER_OVERFLOW_VAL 0xffffffff
-#define TIMER_LOAD_VAL 0
-
-int timer_init(void)
-{
- /* start the counter ticking up, reload value on overflow */
- writel(TIMER_LOAD_VAL, &timer_base->tldr);
- /* enable timer */
- writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
- &timer_base->tclr);
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- unsigned long now, last = readl(&timer_base->tcrr);
-
- while (tmo > 0) {
- now = readl(&timer_base->tcrr);
- if (last > now) /* count up timer overflow */
- tmo -= TIMER_OVERFLOW_VAL - last + now + 1;
- else
- tmo -= now - last;
- last = now;
- }
-}
-
-ulong get_timer_masked(void)
-{
- /* current tick value */
- ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
- if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
- /* move stamp fordward with absoulte diff ticks */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else { /* we have rollover of incrementer */
- gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
- CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
deleted file mode 100644
index ccd0c83..0000000
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- *(.vectors)
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*_i2c_*)));
- } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
deleted file mode 100644
index 1696c2d..0000000
--- a/arch/arm/cpu/armv7/omap-common/utils.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2011 Linaro Limited
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-static void do_cancel_out(u32 *num, u32 *den, u32 factor)
-{
- while (1) {
- if (((*num)/factor*factor == (*num)) &&
- ((*den)/factor*factor == (*den))) {
- (*num) /= factor;
- (*den) /= factor;
- } else
- break;
- }
-}
-
-/*
- * Cancel out the denominator and numerator of a fraction
- * to get smaller numerator and denominator.
- */
-void cancel_out(u32 *num, u32 *den, u32 den_limit)
-{
- do_cancel_out(num, den, 2);
- do_cancel_out(num, den, 3);
- do_cancel_out(num, den, 5);
- do_cancel_out(num, den, 7);
- do_cancel_out(num, den, 11);
- do_cancel_out(num, den, 13);
- do_cancel_out(num, den, 17);
- while ((*den) > den_limit) {
- *num /= 2;
- /*
- * Round up the denominator so that the final fraction
- * (num/den) is always <= the desired value
- */
- *den = (*den + 1) / 2;
- }
-}
-
-void __weak usb_fake_mac_from_die_id(u32 *id)
-{
- uint8_t device_mac[6];
-
- if (!getenv("usbethaddr")) {
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = id[3] & 0xff;
- device_mac[2] = id[2] & 0xff;
- device_mac[3] = id[1] & 0xff;
- device_mac[4] = id[0] & 0xff;
- device_mac[5] = (id[0] >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
-}
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c
deleted file mode 100644
index a68f1d1..0000000
--- a/arch/arm/cpu/armv7/omap-common/vc.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Voltage Controller implementation for OMAP
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Nishanth Menon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
-
-/*
- * Define Master code if there are multiple masters on the I2C_SR bus.
- * Normally not required
- */
-#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE
-#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0
-#endif
-
-/* Register defines and masks for VC IP Block */
-/* PRM_VC_CFG_I2C_MODE */
-#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6)
-#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4)
-#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3)
-#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0
-#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3
-
-/* PRM_VC_CFG_I2C_CLK */
-#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24
-#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF
-#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16
-#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF
-#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
-#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
-#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
-#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
-
-/* PRM_VC_VAL_BYPASS */
-#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24)
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
-#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
-#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
-#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
-#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
-
-/**
- * omap_vc_init() - Initialization for Voltage controller
- * @speed_khz: I2C buspeed in KHz
- */
-static void omap_vc_init(u16 speed_khz)
-{
- u32 val;
- u32 sys_clk_khz, cycles_hi, cycles_low;
-
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
- if (speed_khz > 400) {
- puts("higher speed requested - throttle to 400Khz\n");
- speed_khz = 400;
- }
-
- /*
- * Setup the dedicated I2C controller for Voltage Control
- * I2C clk - high period 40% low period 60%
- */
- speed_khz /= 10;
- cycles_hi = sys_clk_khz * 4 / speed_khz;
- cycles_low = sys_clk_khz * 6 / speed_khz;
- /* values to be set in register - less by 5 & 7 respectively */
- cycles_hi -= 5;
- cycles_low -= 7;
- val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
- (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
- writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
-
- val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
- PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
- /* No HS mode for now */
- val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
- writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
-}
-
-/**
- * omap_vc_bypass_send_value() - Send a data using VC Bypass command
- * @sa: 7 bit I2C slave address of the PMIC
- * @reg_addr: I2C register address(8 bit) address in PMIC
- * @reg_data: what 8 bit data to write
- */
-int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
-{
- /*
- * Unfortunately we need to loop here instead of a defined time
- * use arbitary large value
- */
- u32 timeout = 0xFFFF;
- u32 reg_val;
-
- sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
- reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
- reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
-
- /* program VC to send data */
- reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
- reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
- reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
- writel(reg_val, (*prcm)->prm_vc_val_bypass);
-
- /* Signal VC to send data */
- writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
- (*prcm)->prm_vc_val_bypass);
-
- /* Wait on VC to complete transmission */
- do {
- reg_val = readl((*prcm)->prm_vc_val_bypass) &
- PRM_VC_VAL_BYPASS_VALID_BIT;
- if (!reg_val)
- break;
-
- sdelay(100);
- } while (--timeout);
-
- /* Optional: cleanup PRM_IRQSTATUS_Ax */
- /* In case we can do something about it in future.. */
- if (!timeout)
- return -1;
-
- /* All good.. */
- return 0;
-}
-
-void sri2c_init(void)
-{
- static int sri2c = 1;
-
- if (sri2c) {
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
- sri2c = 0;
- }
- return;
-}
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
deleted file mode 100644
index a029379..0000000
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ /dev/null
@@ -1,122 +0,0 @@
-if OMAP34XX
-
-choice
- prompt "OMAP3 board select"
-
-config TARGET_AM3517_EVM
- bool "AM3517 EVM"
- select SUPPORT_SPL
-
-config TARGET_MT_VENTOUX
- bool "TeeJet Mt.Ventoux"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_SDP3430
- bool "TI OMAP3430 SDP"
-
-config TARGET_OMAP3_BEAGLE
- bool "TI OMAP3 BeagleBoard"
- select SUPPORT_SPL
-
-config TARGET_CM_T35
- bool "CompuLab CM-T3530 and CM-T3730 boards"
- select SUPPORT_SPL
-
-config TARGET_CM_T3517
- bool "CompuLab CM-T3517 boards"
-
-config TARGET_DEVKIT8000
- bool "TimLL OMAP3 Devkit8000"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_EVM
- bool "TI OMAP3 EVM"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_EVM_QUICK_MMC
- bool "TI OMAP3 EVM Quick MMC"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_EVM_QUICK_NAND
- bool "TI OMAP3 EVM Quick NAND"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_IGEP00X0
- bool "IGEP"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_OVERO
- bool "OMAP35xx Gumstix Overo"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_ZOOM1
- bool "TI Zoom1"
-
-config TARGET_AM3517_CRANE
- bool "am3517_crane"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_PANDORA
- bool "OMAP3 Pandora"
-
-config TARGET_ECO5PK
- bool "ECO5PK"
- select SUPPORT_SPL
-
-config TARGET_DIG297
- bool "DIG297"
-
-config TARGET_TRICORDER
- bool "Tricorder"
- select SUPPORT_SPL
-
-config TARGET_MCX
- bool "MCX"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_LOGIC
- bool "OMAP3 Logic"
-
-config TARGET_OMAP3_MVBLX
- bool "OMAP3 MVBLX"
-
-config TARGET_NOKIA_RX51
- bool "Nokia RX51"
-
-config TARGET_TAO3530
- bool "TAO3530"
- select SUPPORT_SPL
-
-config TARGET_TWISTER
- bool "Twister"
- select SUPPORT_SPL
-
-endchoice
-
-config SYS_SOC
- default "omap3"
-
-source "board/logicpd/am3517evm/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/sdp3430/Kconfig"
-source "board/ti/beagle/Kconfig"
-source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t3517/Kconfig"
-source "board/timll/devkit8000/Kconfig"
-source "board/ti/evm/Kconfig"
-source "board/isee/igep00x0/Kconfig"
-source "board/overo/Kconfig"
-source "board/logicpd/zoom1/Kconfig"
-source "board/ti/am3517crane/Kconfig"
-source "board/pandora/Kconfig"
-source "board/8dtech/eco5pk/Kconfig"
-source "board/comelit/dig297/Kconfig"
-source "board/corscience/tricorder/Kconfig"
-source "board/htkw/mcx/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
-source "board/nokia/rx51/Kconfig"
-source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
deleted file mode 100644
index cf86046..0000000
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := lowlevel_init.o
-
-obj-y += board.o
-obj-y += clock.o
-obj-y += sys_info.o
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
-endif
-
-obj-$(CONFIG_DRIVER_TI_EMAC) += emac.o
-obj-$(CONFIG_EMIF4) += emif4.o
-obj-$(CONFIG_SDRC) += sdrc.o
-obj-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o
diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c
deleted file mode 100644
index 74dd105..0000000
--- a/arch/arm/cpu/armv7/omap3/am35x_musb.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file configures the internal USB PHY in AM35X.
- *
- * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
- *
- * Based on omap_phy_internal.c code from Linux by
- * Hema HK <hemahk@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/am35x_def.h>
-
-void am35x_musb_reset(void)
-{
- /* Reset the musb interface */
- clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
- 0, USBOTGSS_SW_RST);
- clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
- USBOTGSS_SW_RST, 0);
-}
-
-void am35x_musb_phy_power(u8 on)
-{
- unsigned long start = get_timer(0);
-
- if (on) {
- /*
- * Start the on-chip PHY and its PLL.
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
- CONF2_PHY_PLLON);
-
- debug("Waiting for PHY clock good...\n");
- while (!(readl(&am35x_scm_general_regs->devconf2)
- & CONF2_PHYCLKGD)) {
-
- if (get_timer(start) > CONFIG_SYS_HZ / 10) {
- printf("musb PHY clock good timed out\n");
- break;
- }
- }
- } else {
- /*
- * Power down the on-chip PHY.
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_PHY_PLLON,
- CONF2_PHYPWRDN | CONF2_OTGPWRDN);
- }
-}
-
-void am35x_musb_clear_irq(void)
-{
- clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
- 0, USBOTGSS_INT_CLR);
- readl(&am35x_scm_general_regs->lvl_intr_clr);
-}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
deleted file mode 100644
index 53a9e5d..0000000
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- *
- * Common board functions for OMAP3 based boards.
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <dm.h>
-#include <mmc.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/cache.h>
-#include <asm/armv7.h>
-#include <asm/gpio.h>
-#include <asm/omap_common.h>
-#include <asm/arch/mmc_host_def.h>
-#include <i2c.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Declarations */
-extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
-#ifndef CONFIG_SYS_L2CACHE_OFF
-static void omap3_invalidate_l2_cache_secure(void);
-#endif
-
-#ifdef CONFIG_DM_GPIO
-static const struct omap_gpio_platdata omap34xx_gpio[] = {
- { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-U_BOOT_DEVICES(am33xx_gpios) = {
- { "gpio_omap", &omap34xx_gpio[0] },
- { "gpio_omap", &omap34xx_gpio[1] },
- { "gpio_omap", &omap34xx_gpio[2] },
- { "gpio_omap", &omap34xx_gpio[3] },
- { "gpio_omap", &omap34xx_gpio[4] },
- { "gpio_omap", &omap34xx_gpio[5] },
-};
-
-#else
-
-static const struct gpio_bank gpio_bank_34xx[6] = {
- { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
-
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-/*
-* We use static variables because global data is not ready yet.
-* Initialized data is available in SPL right from the beginning.
-* We would not typically need to save these parameters in regular
-* U-Boot. This is needed only in SPL at the moment.
-*/
-u32 omap3_boot_device = BOOT_DEVICE_NAND;
-
-/* auto boot mode detection is not possible for OMAP3 - hard code */
-u32 spl_boot_mode(void)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC2:
- return MMCSD_MODE_RAW;
- case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_FS;
- break;
- default:
- puts("spl: ERROR: unknown device - can't select boot mode\n");
- hang();
- }
-}
-
-u32 spl_boot_device(void)
-{
- return omap3_boot_device;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0, -1, -1);
- break;
- case BOOT_DEVICE_MMC2:
- case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(1, 0, 0, -1, -1);
- break;
- }
- return 0;
-}
-
-void spl_board_init(void)
-{
-#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
- gpmc_init();
-#endif
-#ifdef CONFIG_SPL_I2C_SUPPORT
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-}
-#endif /* CONFIG_SPL_BUILD */
-
-
-/******************************************************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- * (GP Device only)
- *****************************************************************************/
-void secure_unlock_mem(void)
-{
- struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
- struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
- struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
- struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
- struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
-
- /* Protection Module Register Target APE (PM_RT) */
- writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
- writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
- writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
- writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
-
- writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
- writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
- writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
-
- writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
- writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
- writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
- writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
-
- /* IVA Changes */
- writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
- writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
- writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
-
- /* SDRC region 0 public */
- writel(UNLOCK_1, &sms_base->rg_att0);
-}
-
-/******************************************************************************
- * Routine: secureworld_exit()
- * Description: If chip is EMU and boot type is external
- * configure secure registers and exit secure world
- * general use.
- *****************************************************************************/
-void secureworld_exit(void)
-{
- unsigned long i;
-
- /* configure non-secure access control register */
- __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
- /* enabling co-processor CP10 and CP11 accesses in NS world */
- __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
- /*
- * allow allocation of locked TLBs and L2 lines in NS world
- * allow use of PLE registers in NS world also
- */
- __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
-
- /* Enable ASA in ACR register */
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-
- /* Exiting secure world */
- __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
-}
-
-/******************************************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP/EMU(special) type, unlock the SRAM for
- * general use.
- *****************************************************************************/
-void try_unlock_memory(void)
-{
- int mode;
- int in_sdram = is_running_in_sdram();
-
- /*
- * if GP device unlock device SRAM for general use
- * secure code breaks for Secure/Emulation device - HS/E/T
- */
- mode = get_device_type();
- if (mode == GP_DEVICE)
- secure_unlock_mem();
-
- /*
- * If device is EMU and boot is XIP external booting
- * Unlock firewalls and disable L2 and put chip
- * out of secure world
- *
- * Assuming memories are unlocked by the demon who put us in SDRAM
- */
- if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
- && (!in_sdram)) {
- secure_unlock_mem();
- secureworld_exit();
- }
-
- return;
-}
-
-/******************************************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with SRAM stack.
- *****************************************************************************/
-void s_init(void)
-{
- int in_sdram = is_running_in_sdram();
-
- watchdog_init();
-
- try_unlock_memory();
-
- /* Errata workarounds */
- omap3_setup_aux_cr();
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
- /* Invalidate L2-cache from secure mode */
- omap3_invalidate_l2_cache_secure();
-#endif
-
- set_muxconf_regs();
- sdelay(100);
-
- prcm_init();
-
- per_clocks_enable();
-
-#ifdef CONFIG_USB_EHCI_OMAP
- ehci_clocks_enable();
-#endif
-
-#ifdef CONFIG_SPL_BUILD
- gd = &gdata;
-
- preloader_console_init();
-
- timer_init();
-#endif
-
- if (!in_sdram)
- mem_init();
-}
-
-/*
- * Routine: misc_init_r
- * Description: A basic misc_init_r that just displays the die ID
- */
-int __weak misc_init_r(void)
-{
- dieid_num_r();
-
- return 0;
-}
-
-/******************************************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- *****************************************************************************/
-static void wait_for_command_complete(struct watchdog *wd_base)
-{
- int pending = 1;
- do {
- pending = readl(&wd_base->wwps);
- } while (pending);
-}
-
-/******************************************************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************************************************/
-void watchdog_init(void)
-{
- struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /*
- * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
- * either taken care of by ROM (HS/EMU) or not accessible (GP).
- * We need to take care of WD2-MPU or take a PRCM reset. WD3
- * should not be running and does not generate a PRCM reset.
- */
-
- setbits_le32(&prcm_base->fclken_wkup, 0x20);
- setbits_le32(&prcm_base->iclken_wkup, 0x20);
- wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
-
- writel(WD_UNLOCK1, &wd2_base->wspr);
- wait_for_command_complete(wd2_base);
- writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void abort(void)
-{
-}
-
-#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
-/******************************************************************************
- * OMAP3 specific command to switch between NAND HW and SW ecc
- *****************************************************************************/
-static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc < 2 || argc > 3)
- goto usage;
-
- if (strncmp(argv[1], "hw", 2) == 0) {
- if (argc == 2) {
- omap_nand_switch_ecc(1, 1);
- } else {
- if (strncmp(argv[2], "hamming", 7) == 0)
- omap_nand_switch_ecc(1, 1);
- else if (strncmp(argv[2], "bch8", 4) == 0)
- omap_nand_switch_ecc(1, 8);
- else
- goto usage;
- }
- } else if (strncmp(argv[1], "sw", 2) == 0) {
- omap_nand_switch_ecc(0, 0);
- } else {
- goto usage;
- }
-
- return 0;
-
-usage:
- printf ("Usage: nandecc %s\n", cmdtp->usage);
- return 1;
-}
-
-U_BOOT_CMD(
- nandecc, 3, 1, do_switch_ecc,
- "switch OMAP3 NAND ECC calculation algorithm",
- "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
- " 8-bit BCH\n"
- " ecc calculation (second parameter may"
- " be omitted).\n"
- "nandecc sw - Switch to NAND software ecc algorithm."
-);
-
-#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-/**
- * Print board information
- */
-int checkboard (void)
-{
- char *mem_s ;
-
- if (is_mem_sdr())
- mem_s = "mSDR";
- else
- mem_s = "LPDDR";
-
- printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
- sysinfo.nand_string);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_BOARDINFO */
-
-static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
-{
- u32 i, num_params = *parameters;
- u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
-
- /*
- * copy the parameters to an un-cached area to avoid coherency
- * issues
- */
- for (i = 0; i < num_params; i++) {
- __raw_writel(*parameters, sram_scratch_space);
- parameters++;
- sram_scratch_space++;
- }
-
- /* Now make the PPA call */
- do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
-}
-
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
-{
- u32 acr;
-
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
-
- if (get_device_type() == GP_DEVICE) {
- omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
- acr);
- } else {
- struct emu_hal_params emu_romcode_params;
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = acr;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
- }
-}
-
-static void omap3_setup_aux_cr(void)
-{
- /* Workaround for Cortex-A8 errata: #454179 #430973
- * Set "IBE" bit
- * Set "Disable Branch Size Mispredicts" bit
- * Workaround for erratum #621766
- * Enable L1NEON bit
- * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
- */
- omap3_update_aux_cr_secure(0xE0, 0);
-}
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
- u32 acr;
-
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
-
- /* Write ACR - affects non-secure banked bits */
- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
-/* Invalidate the entire L2 cache from secure mode */
-static void omap3_invalidate_l2_cache_secure(void)
-{
- if (get_device_type() == GP_DEVICE) {
- omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
- 0);
- } else {
- struct emu_hal_params emu_romcode_params;
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = 0;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
- (u32 *)&emu_romcode_params);
- }
-}
-
-void v7_outer_cache_enable(void)
-{
- /* Set L2EN */
- omap3_update_aux_cr_secure(0x2, 0);
-
- /*
- * On some revisions L2EN bit is banked on some revisions it's not
- * No harm in setting both banked bits(in fact this is required
- * by an erratum)
- */
- omap3_update_aux_cr(0x2, 0);
-}
-
-void omap3_outer_cache_disable(void)
-{
- /* Clear L2EN */
- omap3_update_aux_cr_secure(0, 0x2);
-
- /*
- * On some revisions L2EN bit is banked on some revisions it's not
- * No harm in clearing both banked bits(in fact this is required
- * by an erratum)
- */
- omap3_update_aux_cr(0, 0x2);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
deleted file mode 100644
index 529ad9a..0000000
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ /dev/null
@@ -1,790 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and OMAP3 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clocks_omap3.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <environment.h>
-#include <command.h>
-
-/******************************************************************************
- * get_sys_clk_speed() - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *****************************************************************************/
-u32 get_osc_clk_speed(void)
-{
- u32 start, cstart, cend, cdiff, cdiv, val;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- struct prm *prm_base = (struct prm *)PRM_BASE;
- struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
- struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
-
- val = readl(&prm_base->clksrc_ctrl);
-
- if (val & SYSCLKDIV_2)
- cdiv = 2;
- else
- cdiv = 1;
-
- /* enable timer2 */
- val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
-
- /* select sys_clk for GPT1 */
- writel(val, &prcm_base->clksel_wkup);
-
- /* Enable I and F Clocks for GPT1 */
- val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
- writel(val, &prcm_base->iclken_wkup);
-
- val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
- writel(val, &prcm_base->fclken_wkup);
-
- writel(0, &gpt1_base->tldr); /* start counting at 0 */
- writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
-
- /* enable 32kHz source, determine sys_clk via gauging */
-
- /* start time in 20 cycles */
- start = 20 + readl(&s32k_base->s32k_cr);
-
- /* dead loop till start time */
- while (readl(&s32k_base->s32k_cr) < start);
-
- /* get start sys_clk count */
- cstart = readl(&gpt1_base->tcrr);
-
- /* wait for 40 cycles */
- while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
- cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
- cdiff *= cdiv;
-
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return S38_4M;
- else if (cdiff > 15200)
- return S26M;
- else if (cdiff > 13000)
- return S24M;
- else if (cdiff > 9000)
- return S19_2M;
- else if (cdiff > 7600)
- return S13M;
- else
- return S12M;
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- * input oscillator clock frequency.
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
- switch(osc_clk) {
- case S38_4M:
- *sys_clkin_sel = 4;
- break;
- case S26M:
- *sys_clkin_sel = 3;
- break;
- case S19_2M:
- *sys_clkin_sel = 2;
- break;
- case S13M:
- *sys_clkin_sel = 1;
- break;
- case S12M:
- default:
- *sys_clkin_sel = 0;
- }
-}
-
-/*
- * OMAP34XX/35XX specific functions
- */
-
-static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_core_dpll_param();
- void (*f_lock_pll) (u32, u32, u32, u32);
- int xip_safe, p0, p1, p2, p3;
-
- xip_safe = is_running_in_sram();
-
- /* Moving to the right sysclk and ES rev base */
- ptr = ptr + (3 * clk_index) + sil_index;
-
- if (xip_safe) {
- /*
- * CORE DPLL
- */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
- LDELAY);
-
- /*
- * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
- * work. write another value and then default value.
- */
-
- /* CM_CLKSEL1_EMU[DIV_DPLL3] */
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x001F0000, (CORE_M3X2 + 1) << 16) ;
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x001F0000, CORE_M3X2 << 16);
-
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0xF8000000, ptr->m2 << 27);
-
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x07FF0000, ptr->m << 16);
-
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x00007F00, ptr->n << 8);
-
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
-
- /* SSI */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000003, CORE_L3_DIV);
- /* GFX */
- clrsetbits_le32(&prcm_base->clksel_gfx,
- 0x00000007, GFX_DIV);
- /* RESET MGR */
- clrsetbits_le32(&prcm_base->clksel_wkup,
- 0x00000006, WKUP_RSM << 1);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x000000F0, ptr->fsel << 4);
- /* LOCK MODE */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
- LDELAY);
- } else if (is_running_in_flash()) {
- /*
- * if running from flash, jump to small relocated code
- * area in SRAM.
- */
- f_lock_pll = (void *) (SRAM_CLK_CODE);
-
- p0 = readl(&prcm_base->clken_pll);
- clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
-
- p1 = readl(&prcm_base->clksel1_pll);
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&p1, 0x00000040);
-
- p2 = readl(&prcm_base->clksel_core);
- /* SSI */
- clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
-
- p3 = (u32)&prcm_base->idlest_ckgen;
-
- (*f_lock_pll) (p0, p1, p2, p3);
- }
-}
-
-static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_per_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr = ptr + clk_index;
-
- /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
- wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
- /*
- * Errata 1.50 Workaround for OMAP3 ES1.0 only
- * If using default divisors, write default divisor + 1
- * and then the actual divisor value
- */
- /* M6 */
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x1F000000, (PER_M6X2 + 1) << 24);
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x1F000000, PER_M6X2 << 24);
- /* M5 */
- clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
- clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
- /* M4 */
- clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
- clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
- /* M3 */
- clrsetbits_le32(&prcm_base->clksel_dss,
- 0x00001F00, (PER_M3X2 + 1) << 8);
- clrsetbits_le32(&prcm_base->clksel_dss,
- 0x00001F00, PER_M3X2 << 8);
- /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
- clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
- /* Workaround end */
-
- /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
- clrsetbits_le32(&prcm_base->clksel2_pll,
- 0x0007FF00, ptr->m << 8);
-
- /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
-
- /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
-
- /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
- wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
-}
-
-static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr = ptr + clk_index;
-
- /* PER2 DPLL (DPLL5) */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
- wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- /* set M2 (usbtll_fck) */
- clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
- /* set m (11-bit multiplier) */
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
- /* set n (7-bit divider)*/
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
- /* FREQSEL */
- clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
- /* lock mode */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
- wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
-}
-
-static void mpu_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
-
- /* Moving to the right sysclk and ES rev base */
- ptr = ptr + (3 * clk_index) + sil_index;
-
- /* MPU DPLL (unlocked already) */
-
- /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
- 0x0000001F, ptr->m2);
-
- /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
- 0x0007FF00, ptr->m << 8);
-
- /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
- 0x0000007F, ptr->n);
-
- /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x000000F0, ptr->fsel << 4);
-}
-
-static void iva_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
-
- /* Moving to the right sysclk and ES rev base */
- ptr = ptr + (3 * clk_index) + sil_index;
-
- /* IVA DPLL */
- /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2,
- 0x00000007, PLL_STOP);
- wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
-
- /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
- 0x0000001F, ptr->m2);
-
- /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
- 0x0007FF00, ptr->m << 8);
-
- /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
- 0x0000007F, ptr->n);
-
- /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2,
- 0x000000F0, ptr->fsel << 4);
-
- /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2,
- 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
-}
-
-/*
- * OMAP3630 specific functions
- */
-
-static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
- void (*f_lock_pll) (u32, u32, u32, u32);
- int xip_safe, p0, p1, p2, p3;
-
- xip_safe = is_running_in_sram();
-
- /* Moving it to the right sysclk base */
- ptr += clk_index;
-
- if (xip_safe) {
- /* CORE DPLL */
-
- /* Select relock bypass: CM_CLKEN_PLL[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
- LDELAY);
-
- /* CM_CLKSEL1_EMU[DIV_DPLL3] */
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x001F0000, CORE_M3X2 << 16);
-
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0xF8000000, ptr->m2 << 27);
-
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x07FF0000, ptr->m << 16);
-
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x00007F00, ptr->n << 8);
-
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
-
- /* SSI */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000003, CORE_L3_DIV);
- /* GFX */
- clrsetbits_le32(&prcm_base->clksel_gfx,
- 0x00000007, GFX_DIV_36X);
- /* RESET MGR */
- clrsetbits_le32(&prcm_base->clksel_wkup,
- 0x00000006, WKUP_RSM << 1);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x000000F0, ptr->fsel << 4);
- /* LOCK MODE */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
- LDELAY);
- } else if (is_running_in_flash()) {
- /*
- * if running from flash, jump to small relocated code
- * area in SRAM.
- */
- f_lock_pll = (void *) (SRAM_CLK_CODE);
-
- p0 = readl(&prcm_base->clken_pll);
- clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
-
- p1 = readl(&prcm_base->clksel1_pll);
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&p1, 0x00000040);
-
- p2 = readl(&prcm_base->clksel_core);
- /* SSI */
- clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
-
- p3 = (u32)&prcm_base->idlest_ckgen;
-
- (*f_lock_pll) (p0, p1, p2, p3);
- }
-}
-
-static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- struct dpll_per_36x_param *ptr;
-
- ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr += clk_index;
-
- /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
- wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
- /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
- clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
-
- /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
- clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
-
- /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
- clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
-
- /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
- clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
-
- /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
-
- /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
- clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
-
- /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
-
- /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
- clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
-
- /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
- wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
-}
-
-static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr = ptr + clk_index;
-
- /* PER2 DPLL (DPLL5) */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
- wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- /* set M2 (usbtll_fck) */
- clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
- /* set m (11-bit multiplier) */
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
- /* set n (7-bit divider)*/
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
- /* lock mode */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
- wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
-}
-
-static void mpu_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
-
- /* Moving to the right sysclk */
- ptr += clk_index;
-
- /* MPU DPLL (unlocked already */
-
- /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
-
- /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
-
- /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
-}
-
-static void iva_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
-
- /* Moving to the right sysclk */
- ptr += clk_index;
-
- /* IVA DPLL */
- /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
- wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
-
- /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
-
- /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
-
- /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
-
- /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
- u32 osc_clk = 0, sys_clkin_sel;
- u32 clk_index, sil_index = 0;
- struct prm *prm_base = (struct prm *)PRM_BASE;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /*
- * Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- /* set input crystal speed */
- clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if (sys_clkin_sel > 2) {
- /* input clock divider */
- clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
- clk_index = sys_clkin_sel / 2;
- } else {
- /* input clock divider */
- clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
- clk_index = sys_clkin_sel;
- }
-
- if (get_cpu_family() == CPU_OMAP36XX) {
- /*
- * In warm reset conditions on OMAP36xx/AM/DM37xx
- * the rom code incorrectly sets the DPLL4 clock
- * input divider to /6.5. Section 3.5.3.3.3.2.1 of
- * the AM/DM37x TRM explains that the /6.5 divider
- * is used only when the input clock is 13MHz.
- *
- * If the part is in this cpu family *and* the input
- * clock *is not* 13 MHz, then reset the DPLL4 clock
- * input divider to /1 as it should never set to /6.5
- * in this case.
- */
- if (sys_clkin_sel != 1) { /* 13 MHz */
- /* Bit 8: DPLL4_CLKINP_DIV */
- clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
- }
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOW_POWER_BYPASS);
- wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
- LDELAY);
-
- dpll3_init_36xx(0, clk_index);
- dpll4_init_36xx(0, clk_index);
- dpll5_init_36xx(0, clk_index);
- iva_init_36xx(0, clk_index);
- mpu_init_36xx(0, clk_index);
-
- /* Lock MPU DPLL to set frequency */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOCK);
- wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
- LDELAY);
- } else {
- /*
- * The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- if (((get_cpu_family() == CPU_OMAP34XX)
- && (get_cpu_rev() >= CPU_3XX_ES20)) ||
- (get_cpu_family() == CPU_AM35XX))
- sil_index = 1;
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOW_POWER_BYPASS);
- wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
- LDELAY);
-
- dpll3_init_34xx(sil_index, clk_index);
- dpll4_init_34xx(sil_index, clk_index);
- dpll5_init_34xx(sil_index, clk_index);
- if (get_cpu_family() != CPU_AM35XX)
- iva_init_34xx(sil_index, clk_index);
-
- mpu_init_34xx(sil_index, clk_index);
-
- /* Lock MPU DPLL to set frequency */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOCK);
- wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
- LDELAY);
- }
-
- /* Set up GPTimers to sys_clk source only */
- setbits_le32(&prcm_base->clksel_per, 0x000000FF);
- setbits_le32(&prcm_base->clksel_wkup, 1);
-
- sdelay(5000);
-}
-
-/*
- * Enable usb ehci uhh, tll clocks
- */
-void ehci_clocks_enable(void)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- setbits_le32(&prcm_base->iclken_usbhost, 1);
- /*
- * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
- * and USBHOST_120M_FCLK (USBHOST_FCLK2)
- */
- setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
- /* Enable USBTTL_ICLK */
- setbits_le32(&prcm_base->iclken3_core, 0x00000004);
- /* Enable USBTTL_FCLK */
- setbits_le32(&prcm_base->fclken3_core, 0x00000004);
-}
-
-/******************************************************************************
- * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
- *****************************************************************************/
-void per_clocks_enable(void)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /* Enable GP2 timer. */
- setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
- setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
- setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
-
-#ifdef CONFIG_SYS_NS16550
- /* Enable UART1 clocks */
- setbits_le32(&prcm_base->fclken1_core, 0x00002000);
- setbits_le32(&prcm_base->iclken1_core, 0x00002000);
-
- /* UART 3 Clocks */
- setbits_le32(&prcm_base->fclken_per, 0x00000800);
- setbits_le32(&prcm_base->iclken_per, 0x00000800);
-#endif
-
-#ifdef CONFIG_OMAP3_GPIO_2
- setbits_le32(&prcm_base->fclken_per, 0x00002000);
- setbits_le32(&prcm_base->iclken_per, 0x00002000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_3
- setbits_le32(&prcm_base->fclken_per, 0x00004000);
- setbits_le32(&prcm_base->iclken_per, 0x00004000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_4
- setbits_le32(&prcm_base->fclken_per, 0x00008000);
- setbits_le32(&prcm_base->iclken_per, 0x00008000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_5
- setbits_le32(&prcm_base->fclken_per, 0x00010000);
- setbits_le32(&prcm_base->iclken_per, 0x00010000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_6
- setbits_le32(&prcm_base->fclken_per, 0x00020000);
- setbits_le32(&prcm_base->iclken_per, 0x00020000);
-#endif
-
-#ifdef CONFIG_SYS_I2C_OMAP34XX
- /* Turn on all 3 I2C clocks */
- setbits_le32(&prcm_base->fclken1_core, 0x00038000);
- setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
-#endif
- /* Enable the ICLK for 32K Sync Timer as its used in udelay */
- setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
-
- if (get_cpu_family() != CPU_AM35XX)
- out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
-
- out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
- out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
- out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
- out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
- out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
- out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
- out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
- if (get_cpu_family() != CPU_AM35XX) {
- out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
- out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
- }
-
- sdelay(1000);
-}
diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk
deleted file mode 100644
index ad44d63..0000000
--- a/arch/arm/cpu/armv7/omap3/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# (C) Copyright 2010
-# Texas Instruments, <www.ti.com>
-#
-# Aneesh V <aneesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap3/emac.c b/arch/arm/cpu/armv7/omap3/emac.c
deleted file mode 100644
index 37f4b8b..0000000
--- a/arch/arm/cpu/armv7/omap3/emac.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *
- * DaVinci EMAC initialization.
- *
- * (C) Copyright 2011, Ilya Yanok, Emcraft Systems
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/am35x_def.h>
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- u32 reset;
-
- /* ensure that the module is out of reset */
- reset = readl(&am35x_scm_general_regs->ip_sw_reset);
- reset &= ~CPGMACSS_SW_RST;
- writel(reset, &am35x_scm_general_regs->ip_sw_reset);
-
- return davinci_emac_initialize();
-}
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
deleted file mode 100644
index a2aadc9..0000000
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Author :
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on mem.c and sdrc.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/emif4.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-extern omap3_sysinfo sysinfo;
-
-static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- * - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
- return 0;
-}
-
-/*
- * get_sdr_cs_size -
- * - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size = 0;
-
- /* TODO: Calculate the size based on EMIF4 configuration */
- if (cs == CS0)
- size = CONFIG_SYS_CS0_SIZE;
-
- return size;
-}
-
-/*
- * get_sdr_cs_offset -
- * - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
- u32 offset = 0;
-
- return offset;
-}
-
-/*
- * do_emif4_init -
- * - Init the emif4 module for DDR access
- * - Early init routines, called from flash or SRAM.
- */
-static void do_emif4_init(void)
-{
- unsigned int regval;
- /* Set the DDR PHY parameters in PHY ctrl registers */
- regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
- EMIF4_DDR1_EXT_STRB_DIS);
- writel(regval, &emif4_base->ddr_phyctrl1);
- writel(regval, &emif4_base->ddr_phyctrl1_shdw);
- writel(0, &emif4_base->ddr_phyctrl2);
-
- /* Reset the DDR PHY and wait till completed */
- regval = readl(&emif4_base->sdram_iodft_tlgc);
- regval |= (1<<10);
- writel(regval, &emif4_base->sdram_iodft_tlgc);
- /*Wait till that bit clears*/
- while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
- /*Re-verify the DDR PHY status*/
- while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
-
- regval |= (1<<0);
- writel(regval, &emif4_base->sdram_iodft_tlgc);
- /* Set SDR timing registers */
- regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
- EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
- EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
- EMIF4_TIM1_T_RP);
- writel(regval, &emif4_base->sdram_time1);
- writel(regval, &emif4_base->sdram_time1_shdw);
-
- regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
- EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
- EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
- writel(regval, &emif4_base->sdram_time2);
- writel(regval, &emif4_base->sdram_time2_shdw);
-
- regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
- writel(regval, &emif4_base->sdram_time3);
- writel(regval, &emif4_base->sdram_time3_shdw);
-
- /* Set the PWR control register */
- regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
- EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
- writel(regval, &emif4_base->sdram_pwr_mgmt);
- writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
-
- /* Set the DDR refresh rate control register */
- regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
- writel(regval, &emif4_base->sdram_refresh_ctrl);
- writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
-
- /* set the SDRAM configuration register */
- regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
- EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
- EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
- EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
- EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
- EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
- writel(regval, &emif4_base->sdram_config);
-}
-
-/*
- * dram_init -
- * - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
- size1 = get_sdr_cs_size(CS1);
-
- gd->ram_size = size0 + size1;
- return 0;
-}
-
-void dram_init_banksize (void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- size1 = get_sdr_cs_size(CS1);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-}
-
-/*
- * mem_init() -
- * - Initialize memory subsystem
- */
-void mem_init(void)
-{
- do_emif4_init();
-}
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
deleted file mode 100644
index 78577b1..0000000
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ /dev/null
@@ -1,498 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Initial Code by:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks_omap3.h>
-#include <linux/linkage.h>
-
-#ifdef CONFIG_SPL_BUILD
-ENTRY(save_boot_params)
- ldr r4, =omap3_boot_device
- ldr r5, [r0, #0x4]
- and r5, r5, #0xff
- str r5, [r4]
- bx lr
-ENDPROC(save_boot_params)
-#endif
-
-ENTRY(omap3_gp_romcode_call)
- PUSH {r4-r12, lr} @ Save all registers from ROM code!
- MOV r12, r0 @ Copy the Service ID in R12
- MOV r0, r1 @ Copy parameter to R0
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c10, 5 @ DMB
- .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
- @ because we use -march=armv5
- POP {r4-r12, pc}
-ENDPROC(omap3_gp_romcode_call)
-
-/*
- * Funtion for making PPA HAL API calls in secure devices
- * Input:
- * R0 - Service ID
- * R1 - paramer list
- */
-ENTRY(do_omap3_emu_romcode_call)
- PUSH {r4-r12, lr} @ Save all registers from ROM code!
- MOV r12, r0 @ Copy the Secure Service ID in R12
- MOV r3, r1 @ Copy the pointer to va_list in R3
- MOV r1, #0 @ Process ID - 0
- MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
- @ to va_list in R3
- MOV r6, #0xFF @ Indicate new Task call
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c10, 5 @ DMB
- .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
- @ because we use -march=armv5
- POP {r4-r12, pc}
-ENDPROC(do_omap3_emu_romcode_call)
-
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-ENTRY(cpy_clk_code)
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* copy from start of go_to_speed... */
- adr r2, lowlevel_init /* ... up to start of low_level_init */
-next2:
- ldmia r0!, {r3 - r10} /* copy from source address [r0] */
- stmia r1!, {r3 - r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo next2
- mov pc, lr /* back to caller */
-ENDPROC(cpy_clk_code)
-
-/* ***************************************************************************
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = CM_CLKEN_PLL-bypass value
- * R1 = CM_CLKSEL1_PLL-m, n, and divider values
- * R2 = CM_CLKSEL_CORE-divider values
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- * Note: If core unlocks/relocks and SDRAM is running fast already it gets
- * confused. A reset of the controller gets it back. Taking away its
- * L3 when its not in self refresh seems bad for it. Normally, this
- * code runs from flash before SDR is init so that should be ok.
- ****************************************************************************/
-ENTRY(go_to_speed)
- stmfd sp!, {r4 - r6}
-
- /* move into fast relock bypass */
- ldr r4, pll_ctl_add
- str r0, [r4]
-wait1:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- beq wait1 /* if lock, loop */
-
- /* set new dpll dividers _after_ in bypass */
- ldr r5, pll_div_add1
- str r1, [r5] /* set m, n, m2 */
- ldr r5, pll_div_add2
- str r2, [r5] /* set l3/l4/.. dividers*/
- ldr r5, pll_div_add3 /* wkup */
- ldr r2, pll_div_val3 /* rsm val */
- str r2, [r5]
- ldr r5, pll_div_add4 /* gfx */
- ldr r2, pll_div_val4
- str r2, [r5]
- ldr r5, pll_div_add5 /* emu */
- ldr r2, pll_div_val5
- str r2, [r5]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r5, flash_cfg3_addr
- ldr r2, flash_cfg3_val
- str r2, [r5]
- ldr r5, flash_cfg4_addr
- ldr r2, flash_cfg4_val
- str r2, [r5]
- ldr r5, flash_cfg5_addr
- ldr r2, flash_cfg5_val
- str r2, [r5]
- ldr r5, flash_cfg1_addr
- ldr r2, [r5]
- orr r2, r2, #0x3 /* up gpmc divider */
- str r2, [r5]
-
- /* lock DPLL3 and wait a bit */
- orr r0, r0, #0x7 /* set up for lock mode */
- str r0, [r4] /* lock */
- nop /* ARM slow at this point working at sys_clk */
- nop
- nop
- nop
-wait2:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- bne wait2 /* if lock, loop */
- nop
- nop
- nop
- nop
- ldmfd sp!, {r4 - r6}
- mov pc, lr /* back to caller, locked */
-ENDPROC(go_to_speed)
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
-flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
-flash_cfg3_val:
- .word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
-flash_cfg4_val:
- .word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
- .word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_div_add1:
- .word CM_CLKSEL1_PLL
-pll_div_add2:
- .word CM_CLKSEL_CORE
-pll_div_add3:
- .word CM_CLKSEL_WKUP
-pll_div_val3:
- .word (WKUP_RSM << 1)
-pll_div_add4:
- .word CM_CLKSEL_GFX
-pll_div_val4:
- .word (GFX_DIV << 0)
-pll_div_add5:
- .word CM_CLKSEL1_EMU
-pll_div_val5:
- .word CLSEL1_EMU_VAL
-
-#endif
-
-ENTRY(lowlevel_init)
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash ip register */
- mov ip, lr /* save link reg across call */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-/*
- * No need to copy/exec the clock code - DPLL adjust already done
- * in NAND/oneNAND Boot.
- */
- ldr r1, =SRAM_CLK_CODE
- bl cpy_clk_code
-#endif /* NAND Boot */
- mov lr, ip /* restore link reg */
- ldr ip, [sp] /* restore save ip */
- /* tail-call s_init to setup pll, mux, memory */
- b s_init
-
-ENDPROC(lowlevel_init)
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-/* DPLL(1-4) PARAM TABLES */
-
-/*
- * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
-/* ES2 */
-.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
-/* 3410 */
-.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
-/* ES2 */
-.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
-/* 3410 */
-.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
-/* ES2 */
-.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
-/* 3410 */
-.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
-/* ES2 */
-.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
-/* 3410 */
-.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
-/* ES2 */
-.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
-/* 3410 */
-.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
- adr r0, mpu_dpll_param
- mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
-/* ES2 */
-.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
-/* 3410 */
-.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
-/* ES2 */
-.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
-/* 3410 */
-.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
-/* ES2 */
-.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
-/* 3410 */
-.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
-/* ES2 */
-.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
-/* 3410 */
-.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
-/* ES2 */
-.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
-/* 3410 */
-.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
- adr r0, iva_dpll_param
- mov pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
-/* ES2 */
-.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
-/* 3410 */
-.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
-/* ES2 */
-.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
-/* 3410 */
-.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
-/* ES2 */
-.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
-/* 3410 */
-.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
-/* ES2 */
-.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
-/* 3410 */
-.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
-/* ES2 */
-.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
-/* 3410 */
-.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
- adr r0, core_dpll_param
- mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
-
-/* 13MHz */
-.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
-
-/* 19.2MHz */
-.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
-
-/* 26MHz */
-.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
-
-/* 38.4MHz */
-.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
-
-.globl get_per_dpll_param
-get_per_dpll_param:
- adr r0, per_dpll_param
- mov pc, lr
-
-/* PER2 DPLL values */
-per2_dpll_param:
-/* 12MHz */
-.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
-
-/* 13MHz */
-.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
-
-/* 19.2MHz */
-.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
-
-/* 26MHz */
-.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
-
-/* 38.4MHz */
-.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
-
-.globl get_per2_dpll_param
-get_per2_dpll_param:
- adr r0, per2_dpll_param
- mov pc, lr
-
-/*
- * Tables for 36XX/37XX devices
- *
- */
-mpu_36x_dpll_param:
-/* 12MHz */
-.word 50, 0, 0, 1
-/* 13MHz */
-.word 600, 12, 0, 1
-/* 19.2MHz */
-.word 125, 3, 0, 1
-/* 26MHz */
-.word 300, 12, 0, 1
-/* 38.4MHz */
-.word 125, 7, 0, 1
-
-iva_36x_dpll_param:
-/* 12MHz */
-.word 130, 2, 0, 1
-/* 13MHz */
-.word 20, 0, 0, 1
-/* 19.2MHz */
-.word 325, 11, 0, 1
-/* 26MHz */
-.word 10, 0, 0, 1
-/* 38.4MHz */
-.word 325, 23, 0, 1
-
-core_36x_dpll_param:
-/* 12MHz */
-.word 100, 2, 0, 1
-/* 13MHz */
-.word 400, 12, 0, 1
-/* 19.2MHz */
-.word 375, 17, 0, 1
-/* 26MHz */
-.word 200, 12, 0, 1
-/* 38.4MHz */
-.word 375, 35, 0, 1
-
-per_36x_dpll_param:
-/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
-.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
-.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
-.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
-.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
-.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
-
-per2_36x_dpll_param:
-/* 12MHz */
-.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
-/* 13MHz */
-.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
-/* 19.2MHz */
-.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
-/* 26MHz */
-.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
-/* 38.4MHz */
-.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
-
-
-ENTRY(get_36x_mpu_dpll_param)
- adr r0, mpu_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_mpu_dpll_param)
-
-ENTRY(get_36x_iva_dpll_param)
- adr r0, iva_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_iva_dpll_param)
-
-ENTRY(get_36x_core_dpll_param)
- adr r0, core_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_core_dpll_param)
-
-ENTRY(get_36x_per_dpll_param)
- adr r0, per_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_per_dpll_param)
-
-ENTRY(get_36x_per2_dpll_param)
- adr r0, per2_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_per2_dpll_param)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
deleted file mode 100644
index 7a29131..0000000
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Functions related to OMAP3 SDRC.
- *
- * This file has been created after exctracting and consolidating
- * the SDRC related content from mem.c and board.c, also created
- * generic init function (mem_init).
- *
- * Copyright (C) 2004-2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * Copyright (C) 2011
- * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
- *
- * Author :
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Original implementation by (mem.c, board.c) :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-extern omap3_sysinfo sysinfo;
-
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- * - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
- if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
- return 1;
- return 0;
-}
-
-/*
- * make_cs1_contiguous -
- * - When we have CS1 populated we want to have it mapped after cs0 to allow
- * command line mem=xyz use all memory with out discontinuous support
- * compiled in. We could do it in the ATAG, but there really is two banks...
- */
-void make_cs1_contiguous(void)
-{
- u32 size, a_add_low, a_add_high;
-
- size = get_sdr_cs_size(CS0);
- size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
- a_add_high = (size & 3) << 8; /* set up low field */
- a_add_low = (size & 0x3C) >> 2; /* set up high field */
- writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
-
-/*
- * get_sdr_cs_size -
- * - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size;
-
- /* get ram size field */
- size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
- size &= 0x3FF; /* remove unwanted bits */
- size <<= 21; /* multiply by 2 MiB to find size in MB */
- return size;
-}
-
-/*
- * get_sdr_cs_offset -
- * - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
- u32 offset;
-
- if (!cs)
- return 0;
-
- offset = readl(&sdrc_base->cs_cfg);
- offset = (offset & 15) << 27 | (offset & 0x300) << 17;
-
- return offset;
-}
-
-/*
- * write_sdrc_timings -
- * - Takes CS and associated timings and initalize SDRAM
- * - Test CS to make sure it's OK for use
- */
-static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
- struct board_sdrc_timings *timings)
-{
- /* Setup timings we got from the board. */
- writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
- writel(timings->ctrla, &sdrc_actim_base->ctrla);
- writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
- writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(timings->mr, &sdrc_base->cs[cs].mr);
-
- /*
- * Test ram in this bank
- * Disable if bad or not present
- */
- if (!mem_ok(cs))
- writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
-/*
- * do_sdrc_init -
- * - Code called once in C-Stack only context for CS0 and with early being
- * true and a possible 2nd time depending on memory configuration from
- * stack+global context.
- */
-void do_sdrc_init(u32 cs, u32 early)
-{
- struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
- struct board_sdrc_timings timings;
-
- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
- sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-
- /*
- * When called in the early context this may be SPL and we will
- * need to set all of the timings. This ends up being board
- * specific so we call a helper function to take care of this
- * for us. Otherwise, to be safe, we need to copy the settings
- * from the first bank to the second. We will setup CS0,
- * then set cs_cfg to the appropriate value then try and
- * setup CS1.
- */
-#ifdef CONFIG_SPL_BUILD
- get_board_mem_timings(&timings);
-#endif
- if (early) {
- /* reset sdrc controller */
- writel(SOFTRESET, &sdrc_base->sysconfig);
- wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
- 12000000);
- writel(0, &sdrc_base->sysconfig);
-
- /* setup sdrc to ball mux */
- writel(SDRC_SHARING, &sdrc_base->sharing);
-
- /* Disable Power Down of CKE because of 1 CKE on combo part */
- writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
- &sdrc_base->power);
-
- writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
- sdelay(0x20000);
-#ifdef CONFIG_SPL_BUILD
- write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
- make_cs1_contiguous();
- write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
-#endif
-
- }
-
- /*
- * If we aren't using SPL we have been loaded by some
- * other means which may not have correctly initialized
- * both CS0 and CS1 (such as some older versions of x-loader)
- * so we may be asked now to setup CS1.
- */
- if (cs == CS1) {
- timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
- timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
- timings.ctrla = readl(&sdrc_actim_base0->ctrla);
- timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
- timings.mr = readl(&sdrc_base->cs[CS0].mr);
- write_sdrc_timings(cs, sdrc_actim_base1, &timings);
- }
-}
-
-/*
- * dram_init -
- * - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * We always need to have cs_cfg point at where the second
- * bank would be, if present. Failure to do so can lead to
- * strange situations where memory isn't detected and
- * configured correctly. CS0 will already have been setup
- * at this point.
- */
- make_cs1_contiguous();
- do_sdrc_init(CS1, NOT_EARLY);
- size1 = get_sdr_cs_size(CS1);
-
- gd->ram_size = size0 + size1;
-
- return 0;
-}
-
-void dram_init_banksize (void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- size1 = get_sdr_cs_size(CS1);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-}
-
-/*
- * mem_init -
- * - Init the sdrc chip,
- * - Selects CS0 and CS1,
- */
-void mem_init(void)
-{
- /* only init up first bank here */
- do_sdrc_init(CS0, EARLY_INIT);
-}
diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
deleted file mode 100644
index db6de09..0000000
--- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Tom Rini <trini@ti.com>
- *
- * Initial Code from:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Jian Zhang <jzhang@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/mtd/nand.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-
-static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
-
-/* nand_command: Send a flash command to the flash chip */
-static void nand_command(u8 command)
-{
- writeb(command, &gpmc_config->cs[0].nand_cmd);
-
- if (command == NAND_CMD_RESET) {
- unsigned char ret_val;
- writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
- do {
- /* Wait until ready */
- ret_val = readl(&gpmc_config->cs[0].nand_dat);
- } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
- }
-}
-
-/*
- * Many boards will want to know the results of the NAND_CMD_READID command
- * in order to decide what to do about DDR initialization. This function
- * allows us to do that very early and to pass those results back to the
- * board so it can make whatever decisions need to be made.
- */
-void identify_nand_chip(int *mfr, int *id)
-{
- /* Make sure that we have setup GPMC for NAND correctly. */
- writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
- writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
- writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
- writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
- writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
- writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
-
- /*
- * Enable the config. The CS size goes in bits 11:8. We set
- * bit 6 to enable the CS and the base address goes into bits 5:0.
- */
- writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
- ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
- &gpmc_config->cs[0].config7);
-
- sdelay(2000);
-
- /* Issue a RESET and then READID */
- nand_command(NAND_CMD_RESET);
- nand_command(NAND_CMD_READID);
-
- /* Set the address to read to 0x0 */
- writeb(0x0, &gpmc_config->cs[0].nand_adr);
-
- /* Read off the manufacturer and device id. */
- *mfr = readb(&gpmc_config->cs[0].nand_dat);
- *id = readb(&gpmc_config->cs[0].nand_dat);
-}
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
deleted file mode 100644
index bbb65bb..0000000
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h> /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/bootm.h>
-
-#include <i2c.h>
-#include <linux/compiler.h>
-
-extern omap3_sysinfo sysinfo;
-static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-static char *rev_s[CPU_3XX_MAX_REV] = {
- "1.0",
- "2.0",
- "2.1",
- "3.0",
- "3.1",
- "UNKNOWN",
- "UNKNOWN",
- "3.1.2"};
-
-/* this is the revision table for 37xx CPUs */
-static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
- "1.0",
- "1.1",
- "1.2"};
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-/*****************************************************************
- * get_dieid(u32 *id) - read die ID
- *****************************************************************/
-void get_dieid(u32 *id)
-{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
-
- id[3] = readl(&id_base->die_id_0);
- id[2] = readl(&id_base->die_id_1);
- id[1] = readl(&id_base->die_id_2);
- id[0] = readl(&id_base->die_id_3);
-}
-
-/*****************************************************************
- * dieid_num_r(void) - read and set die ID
- *****************************************************************/
-void dieid_num_r(void)
-{
- char *uid_s, die_id[34];
- u32 id[4];
-
- memset(die_id, 0, sizeof(die_id));
-
- uid_s = getenv("dieid#");
-
- if (uid_s == NULL) {
- get_dieid(id);
- sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
- setenv("dieid#", die_id);
- uid_s = die_id;
- }
-
- printf("Die ID #%s\n", uid_s);
-}
-
-/******************************************
- * get_cpu_type(void) - extract cpu info
- ******************************************/
-u32 get_cpu_type(void)
-{
- return readl(&ctrl_base->ctrl_omap_stat);
-}
-
-/******************************************
- * get_cpu_id(void) - extract cpu id
- * returns 0 for ES1.0, cpuid otherwise
- ******************************************/
-u32 get_cpu_id(void)
-{
- struct ctrl_id *id_base;
- u32 cpuid = 0;
-
- /*
- * On ES1.0 the IDCODE register is not exposed on L4
- * so using CPU ID to differentiate between ES1.0 and > ES1.0.
- */
- __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
- if ((cpuid & 0xf) == 0x0) {
- return 0;
- } else {
- /* Decode the IDs on > ES1.0 */
- id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
-
- cpuid = readl(&id_base->idcode);
- }
-
- return cpuid;
-}
-
-/******************************************
- * get_cpu_family(void) - extract cpu info
- ******************************************/
-u32 get_cpu_family(void)
-{
- u16 hawkeye;
- u32 cpu_family;
- u32 cpuid = get_cpu_id();
-
- if (cpuid == 0)
- return CPU_OMAP34XX;
-
- hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
- switch (hawkeye) {
- case HAWKEYE_OMAP34XX:
- cpu_family = CPU_OMAP34XX;
- break;
- case HAWKEYE_AM35XX:
- cpu_family = CPU_AM35XX;
- break;
- case HAWKEYE_OMAP36XX:
- cpu_family = CPU_OMAP36XX;
- break;
- default:
- cpu_family = CPU_OMAP34XX;
- }
-
- return cpu_family;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 cpuid = get_cpu_id();
-
- if (cpuid == 0)
- return CPU_3XX_ES10;
- else
- return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
-}
-
-/*****************************************************************
- * get_sku_id(void) - read sku_id to get info on max clock rate
- *****************************************************************/
-u32 get_sku_id(void)
-{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
- return readl(&id_base->sku_id) & SKUID_CLK_MASK;
-}
-
-/***************************************************************************
- * get_gpmc0_base() - Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- * - for u-boot we currently map:
- * -- 0 to nothing,
- * -- 4 to flash
- * -- 8 to enent
- * -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
- u32 b;
-
- b = readl(&gpmc_cfg->cs[0].config7);
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return b;
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
- return WIDTH_16BIT;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
- *************************************************************************/
-u32 __weak get_board_rev(void)
-{
- return 0x20;
-}
-
-/********************************************************
- * get_base(); get upper addr of current execution
- *******************************************************/
-static u32 get_base(void)
-{
- u32 val;
-
- __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
- val &= 0xF0000000;
- val >>= 28;
- return val;
-}
-
-/********************************************************
- * is_running_in_flash() - tell if currently running in
- * FLASH.
- *******************************************************/
-u32 is_running_in_flash(void)
-{
- if (get_base() < 4)
- return 1; /* in FLASH */
-
- return 0; /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- * is_running_in_sram() - tell if currently running in
- * SRAM.
- *******************************************************/
-u32 is_running_in_sram(void)
-{
- if (get_base() == 4)
- return 1; /* in SRAM */
-
- return 0; /* running in FLASH or SDRAM */
-}
-
-/********************************************************
- * is_running_in_sdram() - tell if currently running in
- * SDRAM.
- *******************************************************/
-u32 is_running_in_sdram(void)
-{
- if (get_base() > 4)
- return 1; /* in SDRAM */
-
- return 0; /* running in SRAM or FLASH */
-}
-
-/***************************************************************
- * get_boot_type() - Is this an XIP type device or a stream one
- * bits 4-0 specify type. Bit 5 says mem/perif
- ***************************************************************/
-u32 get_boot_type(void)
-{
- return (readl(&ctrl_base->status) & SYSBOOT_MASK);
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-/**
- * Print CPU information
- */
-int print_cpuinfo (void)
-{
- char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
-
- switch (get_cpu_family()) {
- case CPU_OMAP34XX:
- cpu_family_s = "OMAP";
- switch (get_cpu_type()) {
- case OMAP3503:
- cpu_s = "3503";
- break;
- case OMAP3515:
- cpu_s = "3515";
- break;
- case OMAP3525:
- cpu_s = "3525";
- break;
- case OMAP3530:
- cpu_s = "3530";
- break;
- default:
- cpu_s = "35XX";
- break;
- }
- if ((get_cpu_rev() >= CPU_3XX_ES31) &&
- (get_sku_id() == SKUID_CLK_720MHZ))
- max_clk = "720 MHz";
- else
- max_clk = "600 MHz";
-
- break;
- case CPU_AM35XX:
- cpu_family_s = "AM";
- switch (get_cpu_type()) {
- case AM3505:
- cpu_s = "3505";
- break;
- case AM3517:
- cpu_s = "3517";
- break;
- default:
- cpu_s = "35XX";
- break;
- }
- max_clk = "600 Mhz";
- break;
- case CPU_OMAP36XX:
- cpu_family_s = "OMAP";
- switch (get_cpu_type()) {
- case OMAP3730:
- cpu_s = "3630/3730";
- break;
- default:
- cpu_s = "36XX/37XX";
- break;
- }
- max_clk = "1 Ghz";
- break;
- default:
- cpu_family_s = "OMAP";
- cpu_s = "35XX";
- max_clk = "600 Mhz";
- }
-
- switch (get_device_type()) {
- case TST_DEVICE:
- sec_s = "TST";
- break;
- case EMU_DEVICE:
- sec_s = "EMU";
- break;
- case HS_DEVICE:
- sec_s = "HS";
- break;
- case GP_DEVICE:
- sec_s = "GP";
- break;
- default:
- sec_s = "?";
- }
-
- if (CPU_OMAP36XX == get_cpu_family())
- printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
- cpu_family_s, cpu_s, sec_s,
- rev_s_37xx[get_cpu_rev()], max_clk);
- else
- printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
- cpu_family_s, cpu_s, sec_s,
- rev_s[get_cpu_rev()], max_clk);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
deleted file mode 100644
index eccf897..0000000
--- a/arch/arm/cpu/armv7/omap4/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if OMAP44XX
-
-choice
- prompt "OMAP4 board select"
-
-config TARGET_DUOVERO
- bool "OMAP4430 Gumstix Duovero"
-
-config TARGET_OMAP4_PANDA
- bool "TI OMAP4 PandaBoard"
-
-config TARGET_OMAP4_SDP4430
- bool "TI OMAP4 SDP4430"
-
-endchoice
-
-config SYS_SOC
- default "omap4"
-
-source "board/gumstix/duovero/Kconfig"
-source "board/ti/panda/Kconfig"
-source "board/ti/sdp4430/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
deleted file mode 100644
index 76a032a..0000000
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += sdram_elpida.o
-obj-y += hwinit.o
-obj-y += emif.o
-obj-y += prcm-regs.o
-obj-y += hw_data.o
diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk
deleted file mode 100644
index ad44d63..0000000
--- a/arch/arm/cpu/armv7/omap4/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# (C) Copyright 2010
-# Texas Instruments, <www.ti.com>
-#
-# Aneesh V <aneesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
deleted file mode 100644
index e89032b..0000000
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * EMIF programming
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
-u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
-#endif
-
-#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
- .max_freq = 400000000,
- .RL = 6,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 15,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
- .max_freq = 200000000,
- .RL = 3,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 20,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-/*
- * Min tCK values specified by JESD209-2
- * Min tCK specifies the minimum duration of some AC timing parameters in terms
- * of the number of cycles. If the calculated number of cycles based on the
- * absolute time value is less than the min tCK value, min tCK value should
- * be used instead. This typically happens at low frequencies.
- */
-static const struct lpddr2_min_tck min_tck_jedec = {
- .tRL = 3,
- .tRP_AB = 3,
- .tRCD = 3,
- .tWR = 3,
- .tRAS_MIN = 3,
- .tRRD = 2,
- .tWTR = 2,
- .tXP = 2,
- .tRTP = 2,
- .tCKE = 3,
- .tCKESR = 3,
- .tFAW = 8
-};
-
-static const struct lpddr2_ac_timings const*
- jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
- &timings_jedec_200_mhz,
- &timings_jedec_400_mhz
-};
-
-static const struct lpddr2_device_timings jedec_default_timings = {
- .ac_timings = jedec_ac_timings,
- .min_tck = &min_tck_jedec
-};
-
-void emif_get_device_timings(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings)
-{
- /* Assume Identical devices on EMIF1 & EMIF2 */
- *cs0_device_timings = &jedec_default_timings;
- *cs1_device_timings = &jedec_default_timings;
-}
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
deleted file mode 100644
index 029533c..0000000
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
- *
- * HW data initialization for OMAP4
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clock.h>
-#include <asm/omap_gpio.h>
-#include <asm/io.h>
-
-struct prcm_regs const **prcm =
- (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
-struct dplls const **dplls_data =
- (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
-struct vcores_data const **omap_vcores =
- (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
-struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
-
-/*
- * The M & N values in the following tables are created using the
- * following tool:
- * tools/omap/clocks_get_m_n.c
- * Please use this tool for creating the table for any new frequency.
- */
-
-/*
- * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
- * OMAP4460 OPP_NOM frequency
- */
-static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
- {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/*
- * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
- * OMAP4430 OPP_TURBO frequency
- * OMAP4470 OPP_NOM frequency
- */
-static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/*
- * dpll locked at 1200 MHz - MPU clk at 600 MHz
- * OMAP4430 OPP_NOM frequency
- */
-static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OMAP4460 OPP_NOM frequency */
-/* OMAP4470 OPP_NOM (Low Power) frequency */
-static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OMAP4430 ES1 OPP_NOM frequency */
-static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
- {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
- {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
- {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
- {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
- {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OMAP4430 ES2.X OPP_NOM frequency */
-static const struct dpll_params
- core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
- {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
- {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
- {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
- {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
- {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
- {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-struct dplls omap4430_dplls_es1 = {
- .mpu = mpu_dpll_params_1200mhz,
- .core = core_dpll_params_es1_1524mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4430_dplls_es20 = {
- .mpu = mpu_dpll_params_1200mhz,
- .core = core_dpll_params_es2_1600mhz_ddr200mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4430_dplls = {
- .mpu = mpu_dpll_params_1200mhz,
- .core = core_dpll_params_1600mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4460_dplls = {
- .mpu = mpu_dpll_params_1400mhz,
- .core = core_dpll_params_1600mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4470_dplls = {
- .mpu = mpu_dpll_params_1600mhz,
- .core = core_dpll_params_1600mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct pmic_data twl6030_4430es1 = {
- .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
- .step = 12660, /* 12.66 mV represented in uV */
- /* The code starts at 1 not 0 */
- .start_code = 1,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
-struct pmic_data twl6030 = {
- .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
- .step = 12660, /* 12.66 mV represented in uV */
- /* The code starts at 1 not 0 */
- .start_code = 1,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-struct pmic_data tps62361 = {
- .base_offset = TPS62361_BASE_VOLT_MV,
- .step = 10000, /* 10 mV represented in uV */
- .start_code = 0,
- .gpio = TPS62361_VSEL0_GPIO,
- .gpio_en = 1,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-struct vcores_data omap4430_volts_es1 = {
- .mpu.value = 1325,
- .mpu.addr = SMPS_REG_ADDR_VCORE1,
- .mpu.pmic = &twl6030_4430es1,
-
- .core.value = 1200,
- .core.addr = SMPS_REG_ADDR_VCORE3,
- .core.pmic = &twl6030_4430es1,
-
- .mm.value = 1200,
- .mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &twl6030_4430es1,
-};
-
-struct vcores_data omap4430_volts = {
- .mpu.value = 1325,
- .mpu.addr = SMPS_REG_ADDR_VCORE1,
- .mpu.pmic = &twl6030,
-
- .core.value = 1200,
- .core.addr = SMPS_REG_ADDR_VCORE3,
- .core.pmic = &twl6030,
-
- .mm.value = 1200,
- .mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &twl6030,
-};
-
-struct vcores_data omap4460_volts = {
- .mpu.value = 1203,
- .mpu.addr = TPS62361_REG_ADDR_SET1,
- .mpu.pmic = &tps62361,
-
- .core.value = 1200,
- .core.addr = SMPS_REG_ADDR_VCORE1,
- .core.pmic = &twl6030,
-
- .mm.value = 1200,
- .mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &twl6030,
-};
-
-/*
- * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
- * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
- */
-struct vcores_data omap4470_volts = {
- .mpu.value = 1202,
- .mpu.addr = SMPS_REG_ADDR_SMPS1,
- .mpu.pmic = &twl6030,
-
- .core.value = 1126,
- .core.addr = SMPS_REG_ADDR_SMPS2,
- .core.pmic = &twl6030,
-
- .mm.value = 1139,
- .mm.addr = SMPS_REG_ADDR_SMPS5,
- .mm.pmic = &twl6030,
-};
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- (*prcm)->cm_l4per_clkstctrl,
- (*prcm)->cm_l3init_clkstctrl,
- (*prcm)->cm_memif_clkstctrl,
- (*prcm)->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3_gpmc_clkctrl,
- (*prcm)->cm_memif_emif_1_clkctrl,
- (*prcm)->cm_memif_emif_2_clkctrl,
- (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
- (*prcm)->cm_wkup_gpio1_clkctrl,
- (*prcm)->cm_l4per_gpio2_clkctrl,
- (*prcm)->cm_l4per_gpio3_clkctrl,
- (*prcm)->cm_l4per_gpio4_clkctrl,
- (*prcm)->cm_l4per_gpio5_clkctrl,
- (*prcm)->cm_l4per_gpio6_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_wkup_gptimer1_clkctrl,
- (*prcm)->cm_l3init_hsmmc1_clkctrl,
- (*prcm)->cm_l3init_hsmmc2_clkctrl,
- (*prcm)->cm_l4per_gptimer2_clkctrl,
- (*prcm)->cm_wkup_wdtimer2_clkctrl,
- (*prcm)->cm_l4per_uart3_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- /* Enable optional 48M functional clock for USB PHY */
- setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
- USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3init_hsusbotg_clkctrl,
- (*prcm)->cm_l3init_usbphy_clkctrl,
- (*prcm)->cm_l3init_usbphy_clkctrl,
- (*prcm)->cm_clksel_usb_60mhz,
- (*prcm)->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_l4per_mcspi1_clkctrl,
- (*prcm)->cm_l4per_i2c1_clkctrl,
- (*prcm)->cm_l4per_i2c2_clkctrl,
- (*prcm)->cm_l4per_i2c3_clkctrl,
- (*prcm)->cm_l4per_i2c4_clkctrl,
- (*prcm)->cm_l3init_hsusbhost_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-void hw_data_init(void)
-{
- u32 omap_rev = omap_revision();
-
- (*prcm) = &omap4_prcm;
-
- switch (omap_rev) {
-
- case OMAP4430_ES1_0:
- *dplls_data = &omap4430_dplls_es1;
- *omap_vcores = &omap4430_volts_es1;
- break;
-
- case OMAP4430_ES2_0:
- *dplls_data = &omap4430_dplls_es20;
- *omap_vcores = &omap4430_volts;
- break;
-
- case OMAP4430_ES2_1:
- case OMAP4430_ES2_2:
- case OMAP4430_ES2_3:
- *dplls_data = &omap4430_dplls;
- *omap_vcores = &omap4430_volts;
- break;
-
- case OMAP4460_ES1_0:
- case OMAP4460_ES1_1:
- *dplls_data = &omap4460_dplls;
- *omap_vcores = &omap4460_volts;
- break;
-
- case OMAP4470_ES1_0:
- *dplls_data = &omap4470_dplls;
- *omap_vcores = &omap4470_volts;
- break;
-
- default:
- printf("\n INVALID OMAP REVISION ");
- }
-
- *ctrl = &omap4_ctrl;
-}
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
deleted file mode 100644
index db16548..0000000
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- *
- * Common functions for OMAP4 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/sizes.h>
-#include <asm/emif.h>
-#include <asm/arch/gpio.h>
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-
-static const struct gpio_bank gpio_bank_44xx[6] = {
- { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Some tuning of IOs for optimal power and performance
- */
-void do_io_settings(void)
-{
- u32 lpddr2io;
-
- u32 omap4_rev = omap_revision();
-
- if (omap4_rev == OMAP4430_ES1_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
- else if (omap4_rev == OMAP4430_ES2_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
- else
- lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
-
- /* EMIF1 */
- writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
- writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
- /* No pull for GR10 as per hw team's recommendation */
- writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- (*ctrl)->control_lpddr2io1_2);
- writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
-
- /* EMIF2 */
- writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
- writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
- /* No pull for GR10 as per hw team's recommendation */
- writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- (*ctrl)->control_lpddr2io2_2);
- writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
-
- /*
- * Some of these settings (TRIM values) come from eFuse and are
- * in turn programmed in the eFuse at manufacturing time after
- * calibration of the device. Do the software over-ride only if
- * the device is not correctly trimmed
- */
- if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- (*ctrl)->control_ldosram_iva_voltage_ctrl);
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- (*ctrl)->control_ldosram_mpu_voltage_ctrl);
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- (*ctrl)->control_ldosram_core_voltage_ctrl);
- }
-
- /*
- * Over-ride the register
- * i. unconditionally for all 4430
- * ii. only if un-trimmed for 4460
- */
- if (!readl((*ctrl)->control_efuse_1))
- writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
-
- if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
- writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
-}
-#endif /* CONFIG_SPL_BUILD */
-
-/* dummy fuction for omap4 */
-void config_data_eye_leveling_samples(u32 emif_base)
-{
-}
-
-void init_omap_revision(void)
-{
- /*
- * For some of the ES2/ES1 boards ID_CODE is not reliable:
- * Also, ES1 and ES2 have different ARM revisions
- * So use ARM revision for identification
- */
- unsigned int arm_rev = cortex_rev();
-
- switch (arm_rev) {
- case MIDR_CORTEX_A9_R0P1:
- *omap_si_rev = OMAP4430_ES1_0;
- break;
- case MIDR_CORTEX_A9_R1P2:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP4_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = OMAP4430_ES2_0;
- break;
- case OMAP4_CONTROL_ID_CODE_ES2_1:
- *omap_si_rev = OMAP4430_ES2_1;
- break;
- case OMAP4_CONTROL_ID_CODE_ES2_2:
- *omap_si_rev = OMAP4430_ES2_2;
- break;
- default:
- *omap_si_rev = OMAP4430_ES2_0;
- break;
- }
- break;
- case MIDR_CORTEX_A9_R1P3:
- *omap_si_rev = OMAP4430_ES2_3;
- break;
- case MIDR_CORTEX_A9_R2P10:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP4470_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP4470_ES1_0;
- break;
- case OMAP4460_CONTROL_ID_CODE_ES1_1:
- *omap_si_rev = OMAP4460_ES1_1;
- break;
- case OMAP4460_CONTROL_ID_CODE_ES1_0:
- default:
- *omap_si_rev = OMAP4460_ES1_0;
- break;
- }
- break;
- default:
- *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
- break;
- }
-}
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
-{
- set_pl310_ctrl_reg(1);
-}
-
-void v7_outer_cache_disable(void)
-{
- set_pl310_ctrl_reg(0);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
deleted file mode 100644
index 1ed146b..0000000
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- *
- * HW regs data for OMAP4
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/omap_common.h>
-
-struct prcm_regs const omap4_prcm = {
- /* cm1.ckgen */
- .cm_clksel_core = 0x4a004100,
- .cm_clksel_abe = 0x4a004108,
- .cm_dll_ctrl = 0x4a004110,
- .cm_clkmode_dpll_core = 0x4a004120,
- .cm_idlest_dpll_core = 0x4a004124,
- .cm_autoidle_dpll_core = 0x4a004128,
- .cm_clksel_dpll_core = 0x4a00412c,
- .cm_div_m2_dpll_core = 0x4a004130,
- .cm_div_m3_dpll_core = 0x4a004134,
- .cm_div_m4_dpll_core = 0x4a004138,
- .cm_div_m5_dpll_core = 0x4a00413c,
- .cm_div_m6_dpll_core = 0x4a004140,
- .cm_div_m7_dpll_core = 0x4a004144,
- .cm_ssc_deltamstep_dpll_core = 0x4a004148,
- .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
- .cm_emu_override_dpll_core = 0x4a004150,
- .cm_clkmode_dpll_mpu = 0x4a004160,
- .cm_idlest_dpll_mpu = 0x4a004164,
- .cm_autoidle_dpll_mpu = 0x4a004168,
- .cm_clksel_dpll_mpu = 0x4a00416c,
- .cm_div_m2_dpll_mpu = 0x4a004170,
- .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
- .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
- .cm_bypclk_dpll_mpu = 0x4a00419c,
- .cm_clkmode_dpll_iva = 0x4a0041a0,
- .cm_idlest_dpll_iva = 0x4a0041a4,
- .cm_autoidle_dpll_iva = 0x4a0041a8,
- .cm_clksel_dpll_iva = 0x4a0041ac,
- .cm_div_m4_dpll_iva = 0x4a0041b8,
- .cm_div_m5_dpll_iva = 0x4a0041bc,
- .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
- .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
- .cm_bypclk_dpll_iva = 0x4a0041dc,
- .cm_clkmode_dpll_abe = 0x4a0041e0,
- .cm_idlest_dpll_abe = 0x4a0041e4,
- .cm_autoidle_dpll_abe = 0x4a0041e8,
- .cm_clksel_dpll_abe = 0x4a0041ec,
- .cm_div_m2_dpll_abe = 0x4a0041f0,
- .cm_div_m3_dpll_abe = 0x4a0041f4,
- .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
- .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
- .cm_clkmode_dpll_ddrphy = 0x4a004220,
- .cm_idlest_dpll_ddrphy = 0x4a004224,
- .cm_autoidle_dpll_ddrphy = 0x4a004228,
- .cm_clksel_dpll_ddrphy = 0x4a00422c,
- .cm_div_m2_dpll_ddrphy = 0x4a004230,
- .cm_div_m4_dpll_ddrphy = 0x4a004238,
- .cm_div_m5_dpll_ddrphy = 0x4a00423c,
- .cm_div_m6_dpll_ddrphy = 0x4a004240,
- .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
- .cm_shadow_freq_config1 = 0x4a004260,
- .cm_mpu_mpu_clkctrl = 0x4a004320,
-
- /* cm1.dsp */
- .cm_dsp_clkstctrl = 0x4a004400,
- .cm_dsp_dsp_clkctrl = 0x4a004420,
-
- /* cm1.abe */
- .cm1_abe_clkstctrl = 0x4a004500,
- .cm1_abe_l4abe_clkctrl = 0x4a004520,
- .cm1_abe_aess_clkctrl = 0x4a004528,
- .cm1_abe_pdm_clkctrl = 0x4a004530,
- .cm1_abe_dmic_clkctrl = 0x4a004538,
- .cm1_abe_mcasp_clkctrl = 0x4a004540,
- .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
- .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
- .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
- .cm1_abe_slimbus_clkctrl = 0x4a004560,
- .cm1_abe_timer5_clkctrl = 0x4a004568,
- .cm1_abe_timer6_clkctrl = 0x4a004570,
- .cm1_abe_timer7_clkctrl = 0x4a004578,
- .cm1_abe_timer8_clkctrl = 0x4a004580,
- .cm1_abe_wdt3_clkctrl = 0x4a004588,
-
- /* cm2.ckgen */
- .cm_clksel_mpu_m3_iss_root = 0x4a008100,
- .cm_clksel_usb_60mhz = 0x4a008104,
- .cm_scale_fclk = 0x4a008108,
- .cm_core_dvfs_perf1 = 0x4a008110,
- .cm_core_dvfs_perf2 = 0x4a008114,
- .cm_core_dvfs_perf3 = 0x4a008118,
- .cm_core_dvfs_perf4 = 0x4a00811c,
- .cm_core_dvfs_current = 0x4a008124,
- .cm_iva_dvfs_perf_tesla = 0x4a008128,
- .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
- .cm_iva_dvfs_perf_abe = 0x4a008130,
- .cm_iva_dvfs_current = 0x4a008138,
- .cm_clkmode_dpll_per = 0x4a008140,
- .cm_idlest_dpll_per = 0x4a008144,
- .cm_autoidle_dpll_per = 0x4a008148,
- .cm_clksel_dpll_per = 0x4a00814c,
- .cm_div_m2_dpll_per = 0x4a008150,
- .cm_div_m3_dpll_per = 0x4a008154,
- .cm_div_m4_dpll_per = 0x4a008158,
- .cm_div_m5_dpll_per = 0x4a00815c,
- .cm_div_m6_dpll_per = 0x4a008160,
- .cm_div_m7_dpll_per = 0x4a008164,
- .cm_ssc_deltamstep_dpll_per = 0x4a008168,
- .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
- .cm_emu_override_dpll_per = 0x4a008170,
- .cm_clkmode_dpll_usb = 0x4a008180,
- .cm_idlest_dpll_usb = 0x4a008184,
- .cm_autoidle_dpll_usb = 0x4a008188,
- .cm_clksel_dpll_usb = 0x4a00818c,
- .cm_div_m2_dpll_usb = 0x4a008190,
- .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
- .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
- .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
- .cm_clkmode_dpll_unipro = 0x4a0081c0,
- .cm_idlest_dpll_unipro = 0x4a0081c4,
- .cm_autoidle_dpll_unipro = 0x4a0081c8,
- .cm_clksel_dpll_unipro = 0x4a0081cc,
- .cm_div_m2_dpll_unipro = 0x4a0081d0,
- .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
- .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
-
- /* cm2.core */
- .cm_l3_1_clkstctrl = 0x4a008700,
- .cm_l3_1_dynamicdep = 0x4a008708,
- .cm_l3_1_l3_1_clkctrl = 0x4a008720,
- .cm_l3_2_clkstctrl = 0x4a008800,
- .cm_l3_2_dynamicdep = 0x4a008808,
- .cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_gpmc_clkctrl = 0x4a008828,
- .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
- .cm_mpu_m3_clkstctrl = 0x4a008900,
- .cm_mpu_m3_staticdep = 0x4a008904,
- .cm_mpu_m3_dynamicdep = 0x4a008908,
- .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
- .cm_sdma_clkstctrl = 0x4a008a00,
- .cm_sdma_staticdep = 0x4a008a04,
- .cm_sdma_dynamicdep = 0x4a008a08,
- .cm_sdma_sdma_clkctrl = 0x4a008a20,
- .cm_memif_clkstctrl = 0x4a008b00,
- .cm_memif_dmm_clkctrl = 0x4a008b20,
- .cm_memif_emif_fw_clkctrl = 0x4a008b28,
- .cm_memif_emif_1_clkctrl = 0x4a008b30,
- .cm_memif_emif_2_clkctrl = 0x4a008b38,
- .cm_memif_dll_clkctrl = 0x4a008b40,
- .cm_memif_emif_h1_clkctrl = 0x4a008b50,
- .cm_memif_emif_h2_clkctrl = 0x4a008b58,
- .cm_memif_dll_h_clkctrl = 0x4a008b60,
- .cm_c2c_clkstctrl = 0x4a008c00,
- .cm_c2c_staticdep = 0x4a008c04,
- .cm_c2c_dynamicdep = 0x4a008c08,
- .cm_c2c_sad2d_clkctrl = 0x4a008c20,
- .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
- .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
- .cm_l4cfg_clkstctrl = 0x4a008d00,
- .cm_l4cfg_dynamicdep = 0x4a008d08,
- .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
- .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
- .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
- .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
- .cm_l3instr_clkstctrl = 0x4a008e00,
- .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
- .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
- .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
- .cm_ivahd_clkstctrl = 0x4a008f00,
-
- /* cm2.ivahd */
- .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
- .cm_ivahd_sl2_clkctrl = 0x4a008f28,
-
- /* cm2.cam */
- .cm_cam_clkstctrl = 0x4a009000,
- .cm_cam_iss_clkctrl = 0x4a009020,
- .cm_cam_fdif_clkctrl = 0x4a009028,
-
- /* cm2.dss */
- .cm_dss_clkstctrl = 0x4a009100,
- .cm_dss_dss_clkctrl = 0x4a009120,
-
- /* cm2.sgx */
- .cm_sgx_clkstctrl = 0x4a009200,
- .cm_sgx_sgx_clkctrl = 0x4a009220,
-
- /* cm2.l3init */
- .cm_l3init_clkstctrl = 0x4a009300,
- .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
- .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
- .cm_l3init_hsi_clkctrl = 0x4a009338,
- .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
- .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
- .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
- .cm_l3init_p1500_clkctrl = 0x4a009378,
- .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
- .cm_l3init_usbphy_clkctrl = 0x4a0093e0,
-
- /* cm2.l4per */
- .cm_l4per_clkstctrl = 0x4a009400,
- .cm_l4per_dynamicdep = 0x4a009408,
- .cm_l4per_adc_clkctrl = 0x4a009420,
- .cm_l4per_gptimer10_clkctrl = 0x4a009428,
- .cm_l4per_gptimer11_clkctrl = 0x4a009430,
- .cm_l4per_gptimer2_clkctrl = 0x4a009438,
- .cm_l4per_gptimer3_clkctrl = 0x4a009440,
- .cm_l4per_gptimer4_clkctrl = 0x4a009448,
- .cm_l4per_gptimer9_clkctrl = 0x4a009450,
- .cm_l4per_elm_clkctrl = 0x4a009458,
- .cm_l4per_gpio2_clkctrl = 0x4a009460,
- .cm_l4per_gpio3_clkctrl = 0x4a009468,
- .cm_l4per_gpio4_clkctrl = 0x4a009470,
- .cm_l4per_gpio5_clkctrl = 0x4a009478,
- .cm_l4per_gpio6_clkctrl = 0x4a009480,
- .cm_l4per_hdq1w_clkctrl = 0x4a009488,
- .cm_l4per_hecc1_clkctrl = 0x4a009490,
- .cm_l4per_hecc2_clkctrl = 0x4a009498,
- .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
- .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
- .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
- .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
- .cm_l4per_l4per_clkctrl = 0x4a0094c0,
- .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
- .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
- .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
- .cm_l4per_mgate_clkctrl = 0x4a0094e8,
- .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
- .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
- .cm_l4per_mcspi3_clkctrl = 0x4a009500,
- .cm_l4per_mcspi4_clkctrl = 0x4a009508,
- .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
- .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
- .cm_l4per_msprohg_clkctrl = 0x4a009530,
- .cm_l4per_slimbus2_clkctrl = 0x4a009538,
- .cm_l4per_uart1_clkctrl = 0x4a009540,
- .cm_l4per_uart2_clkctrl = 0x4a009548,
- .cm_l4per_uart3_clkctrl = 0x4a009550,
- .cm_l4per_uart4_clkctrl = 0x4a009558,
- .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
- .cm_l4per_i2c5_clkctrl = 0x4a009568,
- .cm_l4sec_clkstctrl = 0x4a009580,
- .cm_l4sec_staticdep = 0x4a009584,
- .cm_l4sec_dynamicdep = 0x4a009588,
- .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
- .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
- .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
- .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
- .cm_l4sec_rng_clkctrl = 0x4a0095c0,
- .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
- .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
-
- /* l4 wkup regs */
- .cm_abe_pll_ref_clksel = 0x4a30610c,
- .cm_sys_clksel = 0x4a306110,
- .cm_wkup_clkstctrl = 0x4a307800,
- .cm_wkup_l4wkup_clkctrl = 0x4a307820,
- .cm_wkup_wdtimer1_clkctrl = 0x4a307828,
- .cm_wkup_wdtimer2_clkctrl = 0x4a307830,
- .cm_wkup_gpio1_clkctrl = 0x4a307838,
- .cm_wkup_gptimer1_clkctrl = 0x4a307840,
- .cm_wkup_gptimer12_clkctrl = 0x4a307848,
- .cm_wkup_synctimer_clkctrl = 0x4a307850,
- .cm_wkup_usim_clkctrl = 0x4a307858,
- .cm_wkup_sarram_clkctrl = 0x4a307860,
- .cm_wkup_keyboard_clkctrl = 0x4a307878,
- .cm_wkup_rtc_clkctrl = 0x4a307880,
- .cm_wkup_bandgap_clkctrl = 0x4a307888,
- .prm_vc_val_bypass = 0x4a307ba0,
- .prm_vc_cfg_channel = 0x4a307ba4,
- .prm_vc_cfg_i2c_mode = 0x4a307ba8,
- .prm_vc_cfg_i2c_clk = 0x4a307bac,
-};
-
-struct omap_sys_ctrl_regs const omap4_ctrl = {
- .control_id_code = 0x4A002204,
- .control_std_fuse_opp_bgap = 0x4a002260,
- .control_status = 0x4a0022c4,
- .control_ldosram_iva_voltage_ctrl = 0x4A002320,
- .control_ldosram_mpu_voltage_ctrl = 0x4A002324,
- .control_ldosram_core_voltage_ctrl = 0x4A002328,
- .control_usbotghs_ctrl = 0x4A00233C,
- .control_padconf_core_base = 0x4A100000,
- .control_pbiaslite = 0x4A100600,
- .control_lpddr2io1_0 = 0x4A100638,
- .control_lpddr2io1_1 = 0x4A10063C,
- .control_lpddr2io1_2 = 0x4A100640,
- .control_lpddr2io1_3 = 0x4A100644,
- .control_lpddr2io2_0 = 0x4A100648,
- .control_lpddr2io2_1 = 0x4A10064C,
- .control_lpddr2io2_2 = 0x4A100650,
- .control_lpddr2io2_3 = 0x4A100654,
- .control_efuse_1 = 0x4A100700,
- .control_efuse_2 = 0x4A100704,
- .control_padconf_wkup_base = 0x4A31E000,
-};
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
deleted file mode 100644
index 4462c72..0000000
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Timing and Organization details of the Elpida parts used in OMAP4
- * SDPs and Panda
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-
-/*
- * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
- * SDP and Panda. Since the parts used and geometry are identical for
- * SDP and Panda for a given OMAP4 revision, this information is kept
- * here instead of being in board directory. However the key functions
- * exported are weakly linked so that they can be over-ridden in the board
- * directory if there is a OMAP4 board in the future that uses a different
- * memory device or geometry.
- *
- * For any new board with different memory devices over-ride one or more
- * of the following functions as per the CONFIG flags you intend to enable:
- * - emif_get_reg_dump()
- * - emif_get_dmm_regs()
- * - emif_get_device_details()
- * - emif_get_device_timings()
- */
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
- .sdram_config_init = 0x80000eb9,
- .sdram_config = 0x80001ab9,
- .ref_ctrl = 0x0000030c,
- .sdram_tim1 = 0x08648311,
- .sdram_tim2 = 0x101b06ca,
- .sdram_tim3 = 0x0048a19f,
- .read_idle_ctrl = 0x000501ff,
- .zq_config = 0x500b3214,
- .temp_alert_config = 0xd8016893,
- .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
- .emif_ddr_phy_ctlr_1 = 0x049ff808
-};
-
-const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
- .sdram_config_init = 0x80000eb1,
- .sdram_config = 0x80001ab1,
- .ref_ctrl = 0x000005cd,
- .sdram_tim1 = 0x10cb0622,
- .sdram_tim2 = 0x20350d52,
- .sdram_tim3 = 0x00b1431f,
- .read_idle_ctrl = 0x000501ff,
- .zq_config = 0x500b3214,
- .temp_alert_config = 0x58016893,
- .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
- .emif_ddr_phy_ctlr_1 = 0x049ff418
-};
-
-const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
- .sdram_config_init = 0x80800eb2,
- .sdram_config = 0x80801ab2,
- .ref_ctrl = 0x00000618,
- .sdram_tim1 = 0x10eb0662,
- .sdram_tim2 = 0x20370dd2,
- .sdram_tim3 = 0x00b1c33f,
- .read_idle_ctrl = 0x000501ff,
- .zq_config = 0x500b3215,
- .temp_alert_config = 0x58016893,
- .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
- .emif_ddr_phy_ctlr_1 = 0x049ff418
-};
-
-const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
- .sdram_config_init = 0x80000eb9,
- .sdram_config = 0x80001ab9,
- .ref_ctrl = 0x00000618,
- .sdram_tim1 = 0x10eb0662,
- .sdram_tim2 = 0x20370dd2,
- .sdram_tim3 = 0x00b1c33f,
- .read_idle_ctrl = 0x000501ff,
- .zq_config = 0xd00b3214,
- .temp_alert_config = 0xd8016893,
- .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
- .emif_ddr_phy_ctlr_1 = 0x049ff418
-};
-
-const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
- .dmm_lisa_map_0 = 0xFF020100,
- .dmm_lisa_map_1 = 0,
- .dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80540300,
- .is_ma_present = 0x0
-};
-
-const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
- .dmm_lisa_map_0 = 0xFF020100,
- .dmm_lisa_map_1 = 0,
- .dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80640300,
- .is_ma_present = 0x0
-};
-
-const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
- .dmm_lisa_map_0 = 0xFF020100,
- .dmm_lisa_map_1 = 0,
- .dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80640300,
- .is_ma_present = 0x1
-};
-
-static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
-{
- u32 omap4_rev = omap_revision();
-
- /* Same devices and geometry on both EMIFs */
- if (omap4_rev == OMAP4430_ES1_0)
- *regs = &emif_regs_elpida_380_mhz_1cs;
- else if (omap4_rev == OMAP4430_ES2_0)
- *regs = &emif_regs_elpida_200_mhz_2cs;
- else if (omap4_rev < OMAP4470_ES1_0)
- *regs = &emif_regs_elpida_400_mhz_2cs;
- else
- *regs = &emif_regs_elpida_400_mhz_1cs;
-}
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
- __attribute__((weak, alias("emif_get_reg_dump_sdp")));
-
-static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
- **dmm_lisa_regs)
-{
- u32 omap_rev = omap_revision();
-
- if (omap_rev == OMAP4430_ES1_0)
- *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
- else if (omap_rev < OMAP4460_ES1_0)
- *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
- else
- *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
-}
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
- __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
-
-#else
-
-static const struct lpddr2_device_details elpida_2G_S4_details = {
- .type = LPDDR2_TYPE_S4,
- .density = LPDDR2_DENSITY_2Gb,
- .io_width = LPDDR2_IO_WIDTH_32,
- .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
-};
-
-static const struct lpddr2_device_details elpida_4G_S4_details = {
- .type = LPDDR2_TYPE_S4,
- .density = LPDDR2_DENSITY_4Gb,
- .io_width = LPDDR2_IO_WIDTH_32,
- .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
-};
-
-struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
- struct lpddr2_device_details *lpddr2_dev_details)
-{
- u32 omap_rev = omap_revision();
-
- /* EMIF1 & EMIF2 have identical configuration */
- if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
- && (cs == CS1)) {
- /* Nothing connected on CS1 for 4430/4470 ES1.0 */
- return NULL;
- } else if (omap_rev < OMAP4470_ES1_0) {
- /* In all other 4430/4460 cases Elpida 2G device */
- *lpddr2_dev_details = elpida_2G_S4_details;
- } else {
- /* 4470: 4G device */
- *lpddr2_dev_details = elpida_4G_S4_details;
- }
- return lpddr2_dev_details;
-}
-
-struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
- struct lpddr2_device_details *lpddr2_dev_details)
- __attribute__((weak, alias("emif_get_device_details_sdp")));
-
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
- .max_freq = 400000000,
- .RL = 6,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 15,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
- .max_freq = 333000000,
- .RL = 5,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 15,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
- .max_freq = 200000000,
- .RL = 3,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 20,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-static const struct lpddr2_min_tck min_tck_elpida = {
- .tRL = 3,
- .tRP_AB = 3,
- .tRCD = 3,
- .tWR = 3,
- .tRAS_MIN = 3,
- .tRRD = 2,
- .tWTR = 2,
- .tXP = 2,
- .tRTP = 2,
- .tCKE = 3,
- .tCKESR = 3,
- .tFAW = 8
-};
-
-static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
- &timings_elpida_200_mhz,
- &timings_elpida_333_mhz,
- &timings_elpida_400_mhz
-};
-
-static const struct lpddr2_device_timings elpida_2G_S4_timings = {
- .ac_timings = elpida_ac_timings,
- .min_tck = &min_tck_elpida,
-};
-
-void emif_get_device_timings_sdp(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings)
-{
- u32 omap_rev = omap_revision();
-
- /* Identical devices on EMIF1 & EMIF2 */
- *cs0_device_timings = &elpida_2G_S4_timings;
-
- if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
- *cs1_device_timings = NULL;
- else
- *cs1_device_timings = &elpida_2G_S4_timings;
-}
-
-void emif_get_device_timings(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings)
- __attribute__((weak, alias("emif_get_device_timings_sdp")));
-
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
-
-const struct lpddr2_mr_regs mr_regs = {
- .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
- .mr2 = 0x4,
- .mr3 = -1,
- .mr10 = MR10_ZQ_ZQINIT,
- .mr16 = MR16_REF_FULL_ARRAY
-};
-
-void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
-{
- *regs = &mr_regs;
-}
-
-__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
-{
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
deleted file mode 100644
index aca862d..0000000
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if OMAP54XX
-
-choice
- prompt "OMAP5 board select"
-
-config TARGET_CM_T54
- bool "CompuLab CM-T54"
-
-config TARGET_OMAP5_UEVM
- bool "TI OMAP5 uEVM board"
-
-config TARGET_DRA7XX_EVM
- bool "TI DRA7XX"
-
-config TARGET_BEAGLE_X15
- bool "BeagleBoard X15"
-
-endchoice
-
-config SYS_SOC
- default "omap5"
-
-source "board/compulab/cm_t54/Kconfig"
-source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/dra7xx/Kconfig"
-source "board/ti/beagle_x15/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
deleted file mode 100644
index 64c6879..0000000
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += hwinit.o
-obj-y += emif.o
-obj-y += sdram.o
-obj-y += prcm-regs.o
-obj-y += hw_data.o
-obj-y += abb.o
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
deleted file mode 100644
index 3bf8897..0000000
--- a/arch/arm/cpu/armv7/omap5/abb.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Adaptive Body Bias programming sequence for OMAP5 family
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/io.h>
-
-/*
- * Setup LDOVBB for OMAP5.
- * On OMAP5+ some ABB settings are fused. They are handled
- * in the following way:
- *
- * 1. corresponding EFUSE register contains ABB enable bit
- * and VSET value
- * 2. If ABB enable bit is set to 1, than ABB should be
- * enabled, otherwise ABB should be disabled
- * 3. If ABB is enabled, than VSET value should be copied
- * to corresponding MUX control register
- */
-s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
-{
- u32 vset;
- u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
- u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
-
- if (!is_omap54xx()) {
- /* DRA7 */
- fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
- fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
- }
- /*
- * ABB parameters must be properly fused
- * otherwise ABB should be disabled
- */
- vset = readl(fuse);
- if (!(vset & fuse_enable_mask))
- return -1;
-
- /* prepare VSET value for LDOVBB mux register */
- vset &= fuse_vset_mask;
- vset >>= ffs(fuse_vset_mask) - 1;
- vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
- vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
-
- /* setup LDOVBB using fused value */
- clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
deleted file mode 100644
index ef2725a..0000000
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# Aneesh V <annesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c
deleted file mode 100644
index b1203a3..0000000
--- a/arch/arm/cpu/armv7/omap5/emif.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * EMIF programming
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com> for OMAP4
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
-#endif
-
-#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
- .max_freq = 532000000,
- .RL = 8,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 15,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-/*
- * Min tCK values specified by JESD209-2
- * Min tCK specifies the minimum duration of some AC timing parameters in terms
- * of the number of cycles. If the calculated number of cycles based on the
- * absolute time value is less than the min tCK value, min tCK value should
- * be used instead. This typically happens at low frequencies.
- */
-static const struct lpddr2_min_tck min_tck_jedec = {
- .tRL = 3,
- .tRP_AB = 3,
- .tRCD = 3,
- .tWR = 3,
- .tRAS_MIN = 3,
- .tRRD = 2,
- .tWTR = 2,
- .tXP = 2,
- .tRTP = 2,
- .tCKE = 3,
- .tCKESR = 3,
- .tFAW = 8
-};
-
-static const struct lpddr2_ac_timings const*
- jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
- &timings_jedec_532_mhz
-};
-
-static const struct lpddr2_device_timings jedec_default_timings = {
- .ac_timings = jedec_ac_timings,
- .min_tck = &min_tck_jedec
-};
-
-void emif_get_device_timings(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings)
-{
- /* Assume Identical devices on EMIF1 & EMIF2 */
- *cs0_device_timings = &jedec_default_timings;
- *cs1_device_timings = NULL;
-}
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
deleted file mode 100644
index 95f1686..0000000
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ /dev/null
@@ -1,664 +0,0 @@
-/*
- *
- * HW data initialization for OMAP5
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <palmas.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clock.h>
-#include <asm/omap_gpio.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-
-struct prcm_regs const **prcm =
- (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
-struct dplls const **dplls_data =
- (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
-struct vcores_data const **omap_vcores =
- (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
-struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
-
-/* OPP HIGH FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
- {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP NOM FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
- {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
-static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
- {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
- {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
- {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
- {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
- {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
- {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
- {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
- {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
- {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
- {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
- {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
- {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
- {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
- {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
- {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
- {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
- {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
- {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
- {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
- {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
- {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
- {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
- {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
- {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-/* ABE M & N values with sysclk2(22.5792 MHz) as input */
-static const struct dpll_params
- abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
- {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
- {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
- {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
- {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
- {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-struct dplls omap5_dplls_es1 = {
- .mpu = mpu_dpll_params_800mhz,
- .core = core_dpll_params_2128mhz_ddr532,
- .per = per_dpll_params_768mhz,
- .iva = iva_dpll_params_2330mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap5_dplls_es2 = {
- .mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_ddr532_es2,
- .per = per_dpll_params_768mhz_es2,
- .iva = iva_dpll_params_2330mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls dra7xx_dplls = {
- .mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_dra7xx,
- .per = per_dpll_params_768mhz_dra7xx,
- .abe = abe_dpll_params_sysclk2_361267khz,
- .iva = iva_dpll_params_2330mhz_dra7xx,
- .usb = usb_dpll_params_1920mhz,
- .ddr = ddr_dpll_params_2128mhz,
- .gmac = gmac_dpll_params_2000mhz,
-};
-
-struct dplls dra72x_dplls = {
- .mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_dra7xx,
- .per = per_dpll_params_768mhz_dra7xx,
- .abe = abe_dpll_params_sysclk2_361267khz,
- .iva = iva_dpll_params_2330mhz_dra7xx,
- .usb = usb_dpll_params_1920mhz,
- .ddr = ddr_dpll_params_2664mhz,
- .gmac = gmac_dpll_params_2000mhz,
-};
-
-struct pmic_data palmas = {
- .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
- .step = 10000, /* 10 mV represented in uV */
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- .start_code = 6,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-struct pmic_data tps659038 = {
- .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
- .step = 10000, /* 10 mV represented in uV */
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- .start_code = 6,
- .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
- .pmic_bus_init = gpi2c_init,
- .pmic_write = palmas_i2c_write_u8,
-};
-
-struct vcores_data omap5430_volts = {
- .mpu.value = VDD_MPU,
- .mpu.addr = SMPS_REG_ADDR_12_MPU,
- .mpu.pmic = &palmas,
-
- .core.value = VDD_CORE,
- .core.addr = SMPS_REG_ADDR_8_CORE,
- .core.pmic = &palmas,
-
- .mm.value = VDD_MM,
- .mm.addr = SMPS_REG_ADDR_45_IVA,
- .mm.pmic = &palmas,
-};
-
-struct vcores_data omap5430_volts_es2 = {
- .mpu.value = VDD_MPU_ES2,
- .mpu.addr = SMPS_REG_ADDR_12_MPU,
- .mpu.pmic = &palmas,
-
- .core.value = VDD_CORE_ES2,
- .core.addr = SMPS_REG_ADDR_8_CORE,
- .core.pmic = &palmas,
-
- .mm.value = VDD_MM_ES2,
- .mm.addr = SMPS_REG_ADDR_45_IVA,
- .mm.pmic = &palmas,
-};
-
-struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA752,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
-
- .eve.value = VDD_EVE_DRA752,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
-
- .gpu.value = VDD_GPU_DRA752,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
-
- .core.value = VDD_CORE_DRA752,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value = VDD_IVA_DRA752,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8,
- .iva.pmic = &tps659038,
-};
-
-struct vcores_data dra722_volts = {
- .mpu.value = 1000,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = 0x23,
- .mpu.pmic = &tps659038,
-
- .eve.value = 1000,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = 0x2f,
- .eve.pmic = &tps659038,
-
- .gpu.value = 1000,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = 0x2f,
- .gpu.pmic = &tps659038,
-
- .core.value = 1000,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = 0x27,
- .core.pmic = &tps659038,
-
- .iva.value = 1000,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = 0x2f,
- .iva.pmic = &tps659038,
-};
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- (*prcm)->cm_l4per_clkstctrl,
- (*prcm)->cm_l3init_clkstctrl,
- (*prcm)->cm_memif_clkstctrl,
- (*prcm)->cm_l4cfg_clkstctrl,
-#ifdef CONFIG_DRIVER_TI_CPSW
- (*prcm)->cm_gmac_clkstctrl,
-#endif
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3_gpmc_clkctrl,
- (*prcm)->cm_memif_emif_1_clkctrl,
- (*prcm)->cm_memif_emif_2_clkctrl,
- (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
- (*prcm)->cm_wkup_gpio1_clkctrl,
- (*prcm)->cm_l4per_gpio2_clkctrl,
- (*prcm)->cm_l4per_gpio3_clkctrl,
- (*prcm)->cm_l4per_gpio4_clkctrl,
- (*prcm)->cm_l4per_gpio5_clkctrl,
- (*prcm)->cm_l4per_gpio6_clkctrl,
- (*prcm)->cm_l4per_gpio7_clkctrl,
- (*prcm)->cm_l4per_gpio8_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_wkup_gptimer1_clkctrl,
- (*prcm)->cm_l3init_hsmmc1_clkctrl,
- (*prcm)->cm_l3init_hsmmc2_clkctrl,
- (*prcm)->cm_l4per_gptimer2_clkctrl,
- (*prcm)->cm_wkup_wdtimer2_clkctrl,
- (*prcm)->cm_l4per_uart3_clkctrl,
- (*prcm)->cm_l4per_i2c1_clkctrl,
-#ifdef CONFIG_DRIVER_TI_CPSW
- (*prcm)->cm_gmac_gmac_clkctrl,
-#endif
-
-#ifdef CONFIG_TI_QSPI
- (*prcm)->cm_l4per_qspi_clkctrl,
-#endif
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Set the correct clock dividers for mmc */
- setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
- setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-
-#ifdef CONFIG_TI_QSPI
- setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
-#endif
-
- /* Enable SCRM OPT clocks for PER and CORE dpll */
- setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_PER_MASK);
- setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_CORE_MASK);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_l4per_mcspi1_clkctrl,
- (*prcm)->cm_l4per_i2c2_clkctrl,
- (*prcm)->cm_l4per_i2c3_clkctrl,
- (*prcm)->cm_l4per_i2c4_clkctrl,
- (*prcm)->cm_l4per_i2c5_clkctrl,
- (*prcm)->cm_l3init_hsusbhost_clkctrl,
- (*prcm)->cm_l3init_fsusb_clkctrl,
- 0
- };
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-const struct ctrl_ioregs ioregs_omap5430 = {
- .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
-};
-
-const struct ctrl_ioregs ioregs_omap5432_es1 = {
- .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- .ctrl_lpddr2ch = 0x0,
- .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
- .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
- .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
- .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-};
-
-const struct ctrl_ioregs ioregs_omap5432_es2 = {
- .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
- .ctrl_lpddr2ch = 0x0,
- .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
- .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
- .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
- .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
- .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-};
-
-const struct ctrl_ioregs ioregs_dra7xx_es1 = {
- .ctrl_ddrch = 0x40404040,
- .ctrl_lpddr2ch = 0x40404040,
- .ctrl_ddr3ch = 0x80808080,
- .ctrl_ddrio_0 = 0xA2084210,
- .ctrl_ddrio_1 = 0x84210840,
- .ctrl_ddrio_2 = 0x84210000,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
- .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-const struct ctrl_ioregs ioregs_dra72x_es1 = {
- .ctrl_ddrch = 0x40404040,
- .ctrl_lpddr2ch = 0x40404040,
- .ctrl_ddr3ch = 0x60606080,
- .ctrl_ddrio_0 = 0xA2084210,
- .ctrl_ddrio_1 = 0x84210840,
- .ctrl_ddrio_2 = 0x84210000,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
- .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-void __weak hw_data_init(void)
-{
- u32 omap_rev = omap_revision();
-
- switch (omap_rev) {
-
- case OMAP5430_ES1_0:
- case OMAP5432_ES1_0:
- *prcm = &omap5_es1_prcm;
- *dplls_data = &omap5_dplls_es1;
- *omap_vcores = &omap5430_volts;
- *ctrl = &omap5_ctrl;
- break;
-
- case OMAP5430_ES2_0:
- case OMAP5432_ES2_0:
- *prcm = &omap5_es2_prcm;
- *dplls_data = &omap5_dplls_es2;
- *omap_vcores = &omap5430_volts_es2;
- *ctrl = &omap5_ctrl;
- break;
-
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- *prcm = &dra7xx_prcm;
- *dplls_data = &dra7xx_dplls;
- *omap_vcores = &dra752_volts;
- *ctrl = &dra7xx_ctrl;
- break;
-
- case DRA722_ES1_0:
- *prcm = &dra7xx_prcm;
- *dplls_data = &dra72x_dplls;
- *omap_vcores = &dra722_volts;
- *ctrl = &dra7xx_ctrl;
- break;
-
- default:
- printf("\n INVALID OMAP REVISION ");
- }
-}
-
-void get_ioregs(const struct ctrl_ioregs **regs)
-{
- u32 omap_rev = omap_revision();
-
- switch (omap_rev) {
- case OMAP5430_ES1_0:
- case OMAP5430_ES2_0:
- *regs = &ioregs_omap5430;
- break;
- case OMAP5432_ES1_0:
- *regs = &ioregs_omap5432_es1;
- break;
- case OMAP5432_ES2_0:
- *regs = &ioregs_omap5432_es2;
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- *regs = &ioregs_dra7xx_es1;
- break;
- case DRA722_ES1_0:
- *regs = &ioregs_dra72x_es1;
- break;
-
- default:
- printf("\n INVALID OMAP REVISION ");
- }
-}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
deleted file mode 100644
index a8a474a..0000000
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- *
- * Functions for omap5 based boards.
- *
- * (C) Copyright 2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- * Sricharan <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
-#include <linux/sizes.h>
-#include <asm/utils.h>
-#include <asm/arch/gpio.h>
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-
-static struct gpio_bank gpio_bank_54xx[8] = {
- { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
-
-#ifdef CONFIG_SPL_BUILD
-/* LPDDR2 specific IO settings */
-static void io_settings_lpddr2(void)
-{
- const struct ctrl_ioregs *ioregs;
-
- get_ioregs(&ioregs);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
- writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
- writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
- writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
-}
-
-/* DDR3 specific IO settings */
-static void io_settings_ddr3(void)
-{
- u32 io_settings = 0;
- const struct ctrl_ioregs *ioregs;
-
- get_ioregs(&ioregs);
- writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
-
- writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
-
- writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
- writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
- writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
-
- /* omap5432 does not use lpddr2 */
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
-
- writel(ioregs->ctrl_emif_sdram_config_ext,
- (*ctrl)->control_emif1_sdram_config_ext);
- writel(ioregs->ctrl_emif_sdram_config_ext,
- (*ctrl)->control_emif2_sdram_config_ext);
-
- if (is_omap54xx()) {
- /* Disable DLL select */
- io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
- & 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif1_sdram_config);
-
- io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
- & 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif2_sdram_config);
- } else {
- writel(ioregs->ctrl_ddr_ctrl_ext_0,
- (*ctrl)->control_ddr_control_ext_0);
- }
-}
-
-/*
- * Some tuning of IOs for optimal power and performance
- */
-void do_io_settings(void)
-{
- u32 io_settings = 0, mask = 0;
-
- /* Impedance settings EMMC, C2C 1,2, hsi2 */
- mask = (ds_mask << 2) | (ds_mask << 8) |
- (ds_mask << 16) | (ds_mask << 18);
- io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
- (~mask);
- io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
- (ds_45_ohm << 18) | (ds_60_ohm << 2);
- writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
-
- /* Impedance settings Mcspi2 */
- mask = (ds_mask << 30);
- io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
- (~mask);
- io_settings |= (ds_60_ohm << 30);
- writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
-
- /* Impedance settings C2C 3,4 */
- mask = (ds_mask << 14) | (ds_mask << 16);
- io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
- (~mask);
- io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
- writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
-
- /* Slew rate settings EMMC, C2C 1,2 */
- mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
- (~mask);
- io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
- writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
-
- /* Slew rate settings hsi2, Mcspi2 */
- mask = (sc_mask << 24) | (sc_mask << 28);
- io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
- (~mask);
- io_settings |= (sc_fast << 28) | (sc_fast << 24);
- writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
-
- /* Slew rate settings C2C 3,4 */
- mask = (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
- (~mask);
- io_settings |= (sc_na << 16) | (sc_na << 18);
- writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
-
- /* impedance and slew rate settings for usb */
- mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
- (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
- io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
- (~mask);
- io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
- (ds_60_ohm << 23) | (sc_fast << 20) |
- (sc_fast << 17) | (sc_fast << 14);
- writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
-
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
- io_settings_lpddr2();
- else
- io_settings_ddr3();
-}
-
-static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
- {0x45, 0x1}, /* 12 MHz */
- {-1, -1}, /* 13 MHz */
- {0x63, 0x2}, /* 16.8 MHz */
- {0x57, 0x2}, /* 19.2 MHz */
- {0x20, 0x1}, /* 26 MHz */
- {-1, -1}, /* 27 MHz */
- {0x41, 0x3} /* 38.4 MHz */
-};
-
-void srcomp_enable(void)
-{
- u32 srcomp_value, mul_factor, div_factor, clk_val, i;
- u32 sysclk_ind = get_sys_clk_index();
- u32 omap_rev = omap_revision();
-
- if (!is_omap54xx())
- return;
-
- mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
- div_factor = srcomp_parameters[sysclk_ind].divide_factor;
-
- for (i = 0; i < 4; i++) {
- srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &=
- ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
- srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
- (div_factor << DIVIDE_FACTOR_XS_SHIFT);
- writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
- }
-
- if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
- clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
- clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
- writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
-
- for (i = 0; i < 4; i++) {
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~PWRDWN_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
-
- while (((readl((*ctrl)->control_srcomp_north_side + i*4)
- & SRCODE_READ_XS_MASK) >>
- SRCODE_READ_XS_SHIFT) == 0)
- ;
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~OVERRIDE_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
- }
- } else {
- srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
- DIVIDE_FACTOR_XS_MASK);
- srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
- (div_factor << DIVIDE_FACTOR_XS_SHIFT);
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
- for (i = 0; i < 4; i++) {
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~OVERRIDE_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
- }
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value &= ~OVERRIDE_XS_MASK;
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
- clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
- clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
- writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
-
- clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
- clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
- writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
-
- for (i = 0; i < 4; i++) {
- while (((readl((*ctrl)->control_srcomp_north_side + i*4)
- & SRCODE_READ_XS_MASK) >>
- SRCODE_READ_XS_SHIFT) == 0)
- ;
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
- }
-
- while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
- SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
- ;
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
- }
-}
-#endif
-
-void config_data_eye_leveling_samples(u32 emif_base)
-{
- const struct ctrl_ioregs *ioregs;
-
- get_ioregs(&ioregs);
-
- /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
- if (emif_base == EMIF1_BASE)
- writel(ioregs->ctrl_emif_sdram_config_ext_final,
- (*ctrl)->control_emif1_sdram_config_ext);
- else if (emif_base == EMIF2_BASE)
- writel(ioregs->ctrl_emif_sdram_config_ext_final,
- (*ctrl)->control_emif2_sdram_config_ext);
-}
-
-void init_omap_revision(void)
-{
- /*
- * For some of the ES2/ES1 boards ID_CODE is not reliable:
- * Also, ES1 and ES2 have different ARM revisions
- * So use ARM revision for identification
- */
- unsigned int rev = cortex_rev();
-
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP5430_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP5430_ES1_0;
- if (rev == MIDR_CORTEX_A15_R2P2)
- *omap_si_rev = OMAP5430_ES2_0;
- break;
- case OMAP5432_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP5432_ES1_0;
- if (rev == MIDR_CORTEX_A15_R2P2)
- *omap_si_rev = OMAP5432_ES2_0;
- break;
- case OMAP5430_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = OMAP5430_ES2_0;
- break;
- case OMAP5432_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = OMAP5432_ES2_0;
- break;
- case DRA752_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = DRA752_ES1_0;
- break;
- case DRA752_CONTROL_ID_CODE_ES1_1:
- *omap_si_rev = DRA752_ES1_1;
- break;
- case DRA722_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = DRA722_ES1_0;
- break;
- default:
- *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
- }
-}
-
-void reset_cpu(ulong ignored)
-{
- u32 omap_rev = omap_revision();
-
- /*
- * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
- * So use cold reset in case instead.
- */
- if (omap_rev == OMAP5430_ES1_0)
- writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
- else
- writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
-}
-
-u32 warm_reset(void)
-{
- return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
-}
-
-void setup_warmreset_time(void)
-{
- u32 rst_time, rst_val;
-
-#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
- rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
-#else
- rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
-#endif
- rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
-
- if (rst_time > RSTTIME1_MASK)
- rst_time = RSTTIME1_MASK;
-
- rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
- rst_val |= rst_time;
- writel(rst_val, (*prcm)->prm_rsttime);
-}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
deleted file mode 100644
index 0745d42..0000000
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ /dev/null
@@ -1,981 +0,0 @@
-/*
- *
- * HW regs data for OMAP5 Soc
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/omap_common.h>
-
-struct prcm_regs const omap5_es1_prcm = {
- /* cm1.ckgen */
- .cm_clksel_core = 0x4a004100,
- .cm_clksel_abe = 0x4a004108,
- .cm_dll_ctrl = 0x4a004110,
- .cm_clkmode_dpll_core = 0x4a004120,
- .cm_idlest_dpll_core = 0x4a004124,
- .cm_autoidle_dpll_core = 0x4a004128,
- .cm_clksel_dpll_core = 0x4a00412c,
- .cm_div_m2_dpll_core = 0x4a004130,
- .cm_div_m3_dpll_core = 0x4a004134,
- .cm_div_h11_dpll_core = 0x4a004138,
- .cm_div_h12_dpll_core = 0x4a00413c,
- .cm_div_h13_dpll_core = 0x4a004140,
- .cm_div_h14_dpll_core = 0x4a004144,
- .cm_ssc_deltamstep_dpll_core = 0x4a004148,
- .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
- .cm_emu_override_dpll_core = 0x4a004150,
- .cm_div_h22_dpllcore = 0x4a004154,
- .cm_div_h23_dpll_core = 0x4a004158,
- .cm_clkmode_dpll_mpu = 0x4a004160,
- .cm_idlest_dpll_mpu = 0x4a004164,
- .cm_autoidle_dpll_mpu = 0x4a004168,
- .cm_clksel_dpll_mpu = 0x4a00416c,
- .cm_div_m2_dpll_mpu = 0x4a004170,
- .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
- .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
- .cm_bypclk_dpll_mpu = 0x4a00419c,
- .cm_clkmode_dpll_iva = 0x4a0041a0,
- .cm_idlest_dpll_iva = 0x4a0041a4,
- .cm_autoidle_dpll_iva = 0x4a0041a8,
- .cm_clksel_dpll_iva = 0x4a0041ac,
- .cm_div_h11_dpll_iva = 0x4a0041b8,
- .cm_div_h12_dpll_iva = 0x4a0041bc,
- .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
- .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
- .cm_bypclk_dpll_iva = 0x4a0041dc,
- .cm_clkmode_dpll_abe = 0x4a0041e0,
- .cm_idlest_dpll_abe = 0x4a0041e4,
- .cm_autoidle_dpll_abe = 0x4a0041e8,
- .cm_clksel_dpll_abe = 0x4a0041ec,
- .cm_div_m2_dpll_abe = 0x4a0041f0,
- .cm_div_m3_dpll_abe = 0x4a0041f4,
- .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
- .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
- .cm_clkmode_dpll_ddrphy = 0x4a004220,
- .cm_idlest_dpll_ddrphy = 0x4a004224,
- .cm_autoidle_dpll_ddrphy = 0x4a004228,
- .cm_clksel_dpll_ddrphy = 0x4a00422c,
- .cm_div_m2_dpll_ddrphy = 0x4a004230,
- .cm_div_h11_dpll_ddrphy = 0x4a004238,
- .cm_div_h12_dpll_ddrphy = 0x4a00423c,
- .cm_div_h13_dpll_ddrphy = 0x4a004240,
- .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
- .cm_shadow_freq_config1 = 0x4a004260,
- .cm_mpu_mpu_clkctrl = 0x4a004320,
-
- /* cm1.dsp */
- .cm_dsp_clkstctrl = 0x4a004400,
- .cm_dsp_dsp_clkctrl = 0x4a004420,
-
- /* cm1.abe */
- .cm1_abe_clkstctrl = 0x4a004500,
- .cm1_abe_l4abe_clkctrl = 0x4a004520,
- .cm1_abe_aess_clkctrl = 0x4a004528,
- .cm1_abe_pdm_clkctrl = 0x4a004530,
- .cm1_abe_dmic_clkctrl = 0x4a004538,
- .cm1_abe_mcasp_clkctrl = 0x4a004540,
- .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
- .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
- .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
- .cm1_abe_slimbus_clkctrl = 0x4a004560,
- .cm1_abe_timer5_clkctrl = 0x4a004568,
- .cm1_abe_timer6_clkctrl = 0x4a004570,
- .cm1_abe_timer7_clkctrl = 0x4a004578,
- .cm1_abe_timer8_clkctrl = 0x4a004580,
- .cm1_abe_wdt3_clkctrl = 0x4a004588,
-
- /* cm2.ckgen */
- .cm_clksel_mpu_m3_iss_root = 0x4a008100,
- .cm_clksel_usb_60mhz = 0x4a008104,
- .cm_scale_fclk = 0x4a008108,
- .cm_core_dvfs_perf1 = 0x4a008110,
- .cm_core_dvfs_perf2 = 0x4a008114,
- .cm_core_dvfs_perf3 = 0x4a008118,
- .cm_core_dvfs_perf4 = 0x4a00811c,
- .cm_core_dvfs_current = 0x4a008124,
- .cm_iva_dvfs_perf_tesla = 0x4a008128,
- .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
- .cm_iva_dvfs_perf_abe = 0x4a008130,
- .cm_iva_dvfs_current = 0x4a008138,
- .cm_clkmode_dpll_per = 0x4a008140,
- .cm_idlest_dpll_per = 0x4a008144,
- .cm_autoidle_dpll_per = 0x4a008148,
- .cm_clksel_dpll_per = 0x4a00814c,
- .cm_div_m2_dpll_per = 0x4a008150,
- .cm_div_m3_dpll_per = 0x4a008154,
- .cm_div_h11_dpll_per = 0x4a008158,
- .cm_div_h12_dpll_per = 0x4a00815c,
- .cm_div_h14_dpll_per = 0x4a008164,
- .cm_ssc_deltamstep_dpll_per = 0x4a008168,
- .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
- .cm_emu_override_dpll_per = 0x4a008170,
- .cm_clkmode_dpll_usb = 0x4a008180,
- .cm_idlest_dpll_usb = 0x4a008184,
- .cm_autoidle_dpll_usb = 0x4a008188,
- .cm_clksel_dpll_usb = 0x4a00818c,
- .cm_div_m2_dpll_usb = 0x4a008190,
- .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
- .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
- .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
- .cm_clkmode_dpll_unipro = 0x4a0081c0,
- .cm_idlest_dpll_unipro = 0x4a0081c4,
- .cm_autoidle_dpll_unipro = 0x4a0081c8,
- .cm_clksel_dpll_unipro = 0x4a0081cc,
- .cm_div_m2_dpll_unipro = 0x4a0081d0,
- .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
- .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
-
- /* cm2.core */
- .cm_coreaon_bandgap_clkctrl = 0x4a008648,
- .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
- .cm_l3_1_clkstctrl = 0x4a008700,
- .cm_l3_1_dynamicdep = 0x4a008708,
- .cm_l3_1_l3_1_clkctrl = 0x4a008720,
- .cm_l3_2_clkstctrl = 0x4a008800,
- .cm_l3_2_dynamicdep = 0x4a008808,
- .cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_gpmc_clkctrl = 0x4a008828,
- .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
- .cm_mpu_m3_clkstctrl = 0x4a008900,
- .cm_mpu_m3_staticdep = 0x4a008904,
- .cm_mpu_m3_dynamicdep = 0x4a008908,
- .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
- .cm_sdma_clkstctrl = 0x4a008a00,
- .cm_sdma_staticdep = 0x4a008a04,
- .cm_sdma_dynamicdep = 0x4a008a08,
- .cm_sdma_sdma_clkctrl = 0x4a008a20,
- .cm_memif_clkstctrl = 0x4a008b00,
- .cm_memif_dmm_clkctrl = 0x4a008b20,
- .cm_memif_emif_fw_clkctrl = 0x4a008b28,
- .cm_memif_emif_1_clkctrl = 0x4a008b30,
- .cm_memif_emif_2_clkctrl = 0x4a008b38,
- .cm_memif_dll_clkctrl = 0x4a008b40,
- .cm_memif_emif_h1_clkctrl = 0x4a008b50,
- .cm_memif_emif_h2_clkctrl = 0x4a008b58,
- .cm_memif_dll_h_clkctrl = 0x4a008b60,
- .cm_c2c_clkstctrl = 0x4a008c00,
- .cm_c2c_staticdep = 0x4a008c04,
- .cm_c2c_dynamicdep = 0x4a008c08,
- .cm_c2c_sad2d_clkctrl = 0x4a008c20,
- .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
- .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
- .cm_l4cfg_clkstctrl = 0x4a008d00,
- .cm_l4cfg_dynamicdep = 0x4a008d08,
- .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
- .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
- .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
- .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
- .cm_l3instr_clkstctrl = 0x4a008e00,
- .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
- .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
- .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
-
- /* cm2.ivahd */
- .cm_ivahd_clkstctrl = 0x4a008f00,
- .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
- .cm_ivahd_sl2_clkctrl = 0x4a008f28,
-
- /* cm2.cam */
- .cm_cam_clkstctrl = 0x4a009000,
- .cm_cam_iss_clkctrl = 0x4a009020,
- .cm_cam_fdif_clkctrl = 0x4a009028,
-
- /* cm2.dss */
- .cm_dss_clkstctrl = 0x4a009100,
- .cm_dss_dss_clkctrl = 0x4a009120,
-
- /* cm2.sgx */
- .cm_sgx_clkstctrl = 0x4a009200,
- .cm_sgx_sgx_clkctrl = 0x4a009220,
-
- /* cm2.l3init */
- .cm_l3init_clkstctrl = 0x4a009300,
- .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
- .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
- .cm_l3init_hsi_clkctrl = 0x4a009338,
- .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
- .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
- .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
- .cm_l3init_p1500_clkctrl = 0x4a009378,
- .cm_l3init_sata_clkctrl = 0x4a009388,
- .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
- .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
- .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
-
- /* cm2.l4per */
- .cm_l4per_clkstctrl = 0x4a009400,
- .cm_l4per_dynamicdep = 0x4a009408,
- .cm_l4per_adc_clkctrl = 0x4a009420,
- .cm_l4per_gptimer10_clkctrl = 0x4a009428,
- .cm_l4per_gptimer11_clkctrl = 0x4a009430,
- .cm_l4per_gptimer2_clkctrl = 0x4a009438,
- .cm_l4per_gptimer3_clkctrl = 0x4a009440,
- .cm_l4per_gptimer4_clkctrl = 0x4a009448,
- .cm_l4per_gptimer9_clkctrl = 0x4a009450,
- .cm_l4per_elm_clkctrl = 0x4a009458,
- .cm_l4per_gpio2_clkctrl = 0x4a009460,
- .cm_l4per_gpio3_clkctrl = 0x4a009468,
- .cm_l4per_gpio4_clkctrl = 0x4a009470,
- .cm_l4per_gpio5_clkctrl = 0x4a009478,
- .cm_l4per_gpio6_clkctrl = 0x4a009480,
- .cm_l4per_hdq1w_clkctrl = 0x4a009488,
- .cm_l4per_hecc1_clkctrl = 0x4a009490,
- .cm_l4per_hecc2_clkctrl = 0x4a009498,
- .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
- .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
- .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
- .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
- .cm_l4per_l4per_clkctrl = 0x4a0094c0,
- .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
- .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
- .cm_l4per_mgate_clkctrl = 0x4a0094e8,
- .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
- .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
- .cm_l4per_mcspi3_clkctrl = 0x4a009500,
- .cm_l4per_mcspi4_clkctrl = 0x4a009508,
- .cm_l4per_gpio7_clkctrl = 0x4a009510,
- .cm_l4per_gpio8_clkctrl = 0x4a009518,
- .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
- .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
- .cm_l4per_msprohg_clkctrl = 0x4a009530,
- .cm_l4per_slimbus2_clkctrl = 0x4a009538,
- .cm_l4per_uart1_clkctrl = 0x4a009540,
- .cm_l4per_uart2_clkctrl = 0x4a009548,
- .cm_l4per_uart3_clkctrl = 0x4a009550,
- .cm_l4per_uart4_clkctrl = 0x4a009558,
- .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
- .cm_l4per_i2c5_clkctrl = 0x4a009568,
- .cm_l4per_uart5_clkctrl = 0x4a009570,
- .cm_l4per_uart6_clkctrl = 0x4a009578,
- .cm_l4sec_clkstctrl = 0x4a009580,
- .cm_l4sec_staticdep = 0x4a009584,
- .cm_l4sec_dynamicdep = 0x4a009588,
- .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
- .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
- .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
- .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
- .cm_l4sec_rng_clkctrl = 0x4a0095c0,
- .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
- .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
-
- /* l4 wkup regs */
- .cm_abe_pll_ref_clksel = 0x4ae0610c,
- .cm_sys_clksel = 0x4ae06110,
- .cm_wkup_clkstctrl = 0x4ae07800,
- .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
- .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
- .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
- .cm_wkup_gpio1_clkctrl = 0x4ae07838,
- .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
- .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
- .cm_wkup_synctimer_clkctrl = 0x4ae07850,
- .cm_wkup_usim_clkctrl = 0x4ae07858,
- .cm_wkup_sarram_clkctrl = 0x4ae07860,
- .cm_wkup_keyboard_clkctrl = 0x4ae07878,
- .cm_wkup_rtc_clkctrl = 0x4ae07880,
- .cm_wkup_bandgap_clkctrl = 0x4ae07888,
- .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
- .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
- .prm_rstctrl = 0x4ae07b00,
- .prm_rstst = 0x4ae07b04,
- .prm_rsttime = 0x4ae07b08,
- .prm_vc_val_bypass = 0x4ae07ba0,
- .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
- .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
-
- /* SCRM stuff, used by some boards */
- .scrm_auxclk0 = 0x4ae0a310,
- .scrm_auxclk1 = 0x4ae0a314,
-};
-
-struct omap_sys_ctrl_regs const omap5_ctrl = {
- .control_status = 0x4A002134,
- .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
- .control_phy_power_usb = 0x4A002370,
- .control_phy_power_sata = 0x4A002374,
- .control_padconf_core_base = 0x4A002800,
- .control_paconf_global = 0x4A002DA0,
- .control_paconf_mode = 0x4A002DA4,
- .control_smart1io_padconf_0 = 0x4A002DA8,
- .control_smart1io_padconf_1 = 0x4A002DAC,
- .control_smart1io_padconf_2 = 0x4A002DB0,
- .control_smart2io_padconf_0 = 0x4A002DB4,
- .control_smart2io_padconf_1 = 0x4A002DB8,
- .control_smart2io_padconf_2 = 0x4A002DBC,
- .control_smart3io_padconf_0 = 0x4A002DC0,
- .control_smart3io_padconf_1 = 0x4A002DC4,
- .control_pbias = 0x4A002E00,
- .control_i2c_0 = 0x4A002E04,
- .control_camera_rx = 0x4A002E08,
- .control_hdmi_tx_phy = 0x4A002E0C,
- .control_uniportm = 0x4A002E10,
- .control_dsiphy = 0x4A002E14,
- .control_mcbsplp = 0x4A002E18,
- .control_usb2phycore = 0x4A002E1C,
- .control_hdmi_1 = 0x4A002E20,
- .control_hsi = 0x4A002E24,
- .control_ddr3ch1_0 = 0x4A002E30,
- .control_ddr3ch2_0 = 0x4A002E34,
- .control_ddrch1_0 = 0x4A002E38,
- .control_ddrch1_1 = 0x4A002E3C,
- .control_ddrch2_0 = 0x4A002E40,
- .control_ddrch2_1 = 0x4A002E44,
- .control_lpddr2ch1_0 = 0x4A002E48,
- .control_lpddr2ch1_1 = 0x4A002E4C,
- .control_ddrio_0 = 0x4A002E50,
- .control_ddrio_1 = 0x4A002E54,
- .control_ddrio_2 = 0x4A002E58,
- .control_hyst_1 = 0x4A002E5C,
- .control_usbb_hsic_control = 0x4A002E60,
- .control_c2c = 0x4A002E64,
- .control_core_control_spare_rw = 0x4A002E68,
- .control_core_control_spare_r = 0x4A002E6C,
- .control_core_control_spare_r_c0 = 0x4A002E70,
- .control_srcomp_north_side = 0x4A002E74,
- .control_srcomp_south_side = 0x4A002E78,
- .control_srcomp_east_side = 0x4A002E7C,
- .control_srcomp_west_side = 0x4A002E80,
- .control_srcomp_code_latch = 0x4A002E84,
- .control_port_emif1_sdram_config = 0x4AE0C110,
- .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
- .control_port_emif2_sdram_config = 0x4AE0C118,
- .control_emif1_sdram_config_ext = 0x4AE0C144,
- .control_emif2_sdram_config_ext = 0x4AE0C148,
- .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318,
- .control_padconf_wkup_base = 0x4AE0C800,
- .control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
- .control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
- .control_padconf_mode = 0x4AE0CDA8,
- .control_xtal_oscillator = 0x4AE0CDAC,
- .control_i2c_2 = 0x4AE0CDB0,
- .control_ckobuffer = 0x4AE0CDB4,
- .control_wkup_control_spare_rw = 0x4AE0CDB8,
- .control_wkup_control_spare_r = 0x4AE0CDBC,
- .control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
- .control_srcomp_east_side_wkup = 0x4AE0CDC4,
- .control_efuse_1 = 0x4AE0CDC8,
- .control_efuse_2 = 0x4AE0CDCC,
- .control_efuse_3 = 0x4AE0CDD0,
- .control_efuse_4 = 0x4AE0CDD4,
- .control_efuse_5 = 0x4AE0CDD8,
- .control_efuse_6 = 0x4AE0CDDC,
- .control_efuse_7 = 0x4AE0CDE0,
- .control_efuse_8 = 0x4AE0CDE4,
- .control_efuse_9 = 0x4AE0CDE8,
- .control_efuse_10 = 0x4AE0CDEC,
- .control_efuse_11 = 0x4AE0CDF0,
- .control_efuse_12 = 0x4AE0CDF4,
- .control_efuse_13 = 0x4AE0CDF8,
-};
-
-struct omap_sys_ctrl_regs const dra7xx_ctrl = {
- .control_status = 0x4A002134,
- .control_phy_power_usb = 0x4A002370,
- .control_phy_power_sata = 0x4A002374,
- .control_core_mac_id_0_lo = 0x4A002514,
- .control_core_mac_id_0_hi = 0x4A002518,
- .control_core_mac_id_1_lo = 0x4A00251C,
- .control_core_mac_id_1_hi = 0x4A002520,
- .control_core_mmr_lock1 = 0x4A002540,
- .control_core_mmr_lock2 = 0x4A002544,
- .control_core_mmr_lock3 = 0x4A002548,
- .control_core_mmr_lock4 = 0x4A00254C,
- .control_core_mmr_lock5 = 0x4A002550,
- .control_core_control_io1 = 0x4A002554,
- .control_core_control_io2 = 0x4A002558,
- .control_paconf_global = 0x4A002DA0,
- .control_paconf_mode = 0x4A002DA4,
- .control_smart1io_padconf_0 = 0x4A002DA8,
- .control_smart1io_padconf_1 = 0x4A002DAC,
- .control_smart1io_padconf_2 = 0x4A002DB0,
- .control_smart2io_padconf_0 = 0x4A002DB4,
- .control_smart2io_padconf_1 = 0x4A002DB8,
- .control_smart2io_padconf_2 = 0x4A002DBC,
- .control_smart3io_padconf_0 = 0x4A002DC0,
- .control_smart3io_padconf_1 = 0x4A002DC4,
- .control_pbias = 0x4A002E00,
- .control_i2c_0 = 0x4A002E04,
- .control_camera_rx = 0x4A002E08,
- .control_hdmi_tx_phy = 0x4A002E0C,
- .control_uniportm = 0x4A002E10,
- .control_dsiphy = 0x4A002E14,
- .control_mcbsplp = 0x4A002E18,
- .control_usb2phycore = 0x4A002E1C,
- .control_hdmi_1 = 0x4A002E20,
- .control_hsi = 0x4A002E24,
- .control_ddr3ch1_0 = 0x4A002E30,
- .control_ddr3ch2_0 = 0x4A002E34,
- .control_ddrch1_0 = 0x4A002E38,
- .control_ddrch1_1 = 0x4A002E3C,
- .control_ddrch2_0 = 0x4A002E40,
- .control_ddrch2_1 = 0x4A002E44,
- .control_lpddr2ch1_0 = 0x4A002E48,
- .control_lpddr2ch1_1 = 0x4A002E4C,
- .control_ddrio_0 = 0x4A002E50,
- .control_ddrio_1 = 0x4A002E54,
- .control_ddrio_2 = 0x4A002E58,
- .control_hyst_1 = 0x4A002E5C,
- .control_usbb_hsic_control = 0x4A002E60,
- .control_c2c = 0x4A002E64,
- .control_core_control_spare_rw = 0x4A002E68,
- .control_core_control_spare_r = 0x4A002E6C,
- .control_core_control_spare_r_c0 = 0x4A002E70,
- .control_srcomp_north_side = 0x4A002E74,
- .control_srcomp_south_side = 0x4A002E78,
- .control_srcomp_east_side = 0x4A002E7C,
- .control_srcomp_west_side = 0x4A002E80,
- .control_srcomp_code_latch = 0x4A002E84,
- .control_ddr_control_ext_0 = 0x4A002E88,
- .control_padconf_core_base = 0x4A003400,
- .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20,
- .control_port_emif1_sdram_config = 0x4AE0C110,
- .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
- .control_port_emif2_sdram_config = 0x4AE0C118,
- .control_emif1_sdram_config_ext = 0x4AE0C144,
- .control_emif2_sdram_config_ext = 0x4AE0C148,
- .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158,
- .control_padconf_mode = 0x4AE0C5A0,
- .control_xtal_oscillator = 0x4AE0C5A4,
- .control_i2c_2 = 0x4AE0C5A8,
- .control_ckobuffer = 0x4AE0C5AC,
- .control_wkup_control_spare_rw = 0x4AE0C5B0,
- .control_wkup_control_spare_r = 0x4AE0C5B4,
- .control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
- .control_srcomp_east_side_wkup = 0x4AE0C5BC,
- .control_efuse_1 = 0x4AE0C5C8,
- .control_efuse_2 = 0x4AE0C5CC,
- .control_efuse_3 = 0x4AE0C5D0,
- .control_efuse_4 = 0x4AE0C5D4,
- .control_efuse_13 = 0x4AE0C5F0,
-};
-
-struct prcm_regs const omap5_es2_prcm = {
- /* cm1.ckgen */
- .cm_clksel_core = 0x4a004100,
- .cm_clksel_abe = 0x4a004108,
- .cm_dll_ctrl = 0x4a004110,
- .cm_clkmode_dpll_core = 0x4a004120,
- .cm_idlest_dpll_core = 0x4a004124,
- .cm_autoidle_dpll_core = 0x4a004128,
- .cm_clksel_dpll_core = 0x4a00412c,
- .cm_div_m2_dpll_core = 0x4a004130,
- .cm_div_m3_dpll_core = 0x4a004134,
- .cm_div_h11_dpll_core = 0x4a004138,
- .cm_div_h12_dpll_core = 0x4a00413c,
- .cm_div_h13_dpll_core = 0x4a004140,
- .cm_div_h14_dpll_core = 0x4a004144,
- .cm_ssc_deltamstep_dpll_core = 0x4a004148,
- .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
- .cm_div_h21_dpll_core = 0x4a004150,
- .cm_div_h22_dpllcore = 0x4a004154,
- .cm_div_h23_dpll_core = 0x4a004158,
- .cm_div_h24_dpll_core = 0x4a00415c,
- .cm_clkmode_dpll_mpu = 0x4a004160,
- .cm_idlest_dpll_mpu = 0x4a004164,
- .cm_autoidle_dpll_mpu = 0x4a004168,
- .cm_clksel_dpll_mpu = 0x4a00416c,
- .cm_div_m2_dpll_mpu = 0x4a004170,
- .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
- .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
- .cm_bypclk_dpll_mpu = 0x4a00419c,
- .cm_clkmode_dpll_iva = 0x4a0041a0,
- .cm_idlest_dpll_iva = 0x4a0041a4,
- .cm_autoidle_dpll_iva = 0x4a0041a8,
- .cm_clksel_dpll_iva = 0x4a0041ac,
- .cm_div_h11_dpll_iva = 0x4a0041b8,
- .cm_div_h12_dpll_iva = 0x4a0041bc,
- .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
- .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
- .cm_bypclk_dpll_iva = 0x4a0041dc,
- .cm_clkmode_dpll_abe = 0x4a0041e0,
- .cm_idlest_dpll_abe = 0x4a0041e4,
- .cm_autoidle_dpll_abe = 0x4a0041e8,
- .cm_clksel_dpll_abe = 0x4a0041ec,
- .cm_div_m2_dpll_abe = 0x4a0041f0,
- .cm_div_m3_dpll_abe = 0x4a0041f4,
- .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
- .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
- .cm_clkmode_dpll_ddrphy = 0x4a004220,
- .cm_idlest_dpll_ddrphy = 0x4a004224,
- .cm_autoidle_dpll_ddrphy = 0x4a004228,
- .cm_clksel_dpll_ddrphy = 0x4a00422c,
- .cm_div_m2_dpll_ddrphy = 0x4a004230,
- .cm_div_h11_dpll_ddrphy = 0x4a004238,
- .cm_div_h12_dpll_ddrphy = 0x4a00423c,
- .cm_div_h13_dpll_ddrphy = 0x4a004240,
- .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
- .cm_shadow_freq_config1 = 0x4a004260,
- .cm_mpu_mpu_clkctrl = 0x4a004320,
-
- /* cm1.dsp */
- .cm_dsp_clkstctrl = 0x4a004400,
- .cm_dsp_dsp_clkctrl = 0x4a004420,
-
- /* cm1.abe */
- .cm1_abe_clkstctrl = 0x4a004500,
- .cm1_abe_l4abe_clkctrl = 0x4a004520,
- .cm1_abe_aess_clkctrl = 0x4a004528,
- .cm1_abe_pdm_clkctrl = 0x4a004530,
- .cm1_abe_dmic_clkctrl = 0x4a004538,
- .cm1_abe_mcasp_clkctrl = 0x4a004540,
- .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
- .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
- .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
- .cm1_abe_slimbus_clkctrl = 0x4a004560,
- .cm1_abe_timer5_clkctrl = 0x4a004568,
- .cm1_abe_timer6_clkctrl = 0x4a004570,
- .cm1_abe_timer7_clkctrl = 0x4a004578,
- .cm1_abe_timer8_clkctrl = 0x4a004580,
- .cm1_abe_wdt3_clkctrl = 0x4a004588,
-
- /* cm2.ckgen */
- .cm_clksel_mpu_m3_iss_root = 0x4a008100,
- .cm_clksel_usb_60mhz = 0x4a008104,
- .cm_scale_fclk = 0x4a008108,
- .cm_core_dvfs_perf1 = 0x4a008110,
- .cm_core_dvfs_perf2 = 0x4a008114,
- .cm_core_dvfs_perf3 = 0x4a008118,
- .cm_core_dvfs_perf4 = 0x4a00811c,
- .cm_core_dvfs_current = 0x4a008124,
- .cm_iva_dvfs_perf_tesla = 0x4a008128,
- .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
- .cm_iva_dvfs_perf_abe = 0x4a008130,
- .cm_iva_dvfs_current = 0x4a008138,
- .cm_clkmode_dpll_per = 0x4a008140,
- .cm_idlest_dpll_per = 0x4a008144,
- .cm_autoidle_dpll_per = 0x4a008148,
- .cm_clksel_dpll_per = 0x4a00814c,
- .cm_div_m2_dpll_per = 0x4a008150,
- .cm_div_m3_dpll_per = 0x4a008154,
- .cm_div_h11_dpll_per = 0x4a008158,
- .cm_div_h12_dpll_per = 0x4a00815c,
- .cm_div_h13_dpll_per = 0x4a008160,
- .cm_div_h14_dpll_per = 0x4a008164,
- .cm_ssc_deltamstep_dpll_per = 0x4a008168,
- .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
- .cm_emu_override_dpll_per = 0x4a008170,
- .cm_clkmode_dpll_usb = 0x4a008180,
- .cm_idlest_dpll_usb = 0x4a008184,
- .cm_autoidle_dpll_usb = 0x4a008188,
- .cm_clksel_dpll_usb = 0x4a00818c,
- .cm_div_m2_dpll_usb = 0x4a008190,
- .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
- .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
- .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
- .cm_clkmode_dpll_unipro = 0x4a0081c0,
- .cm_idlest_dpll_unipro = 0x4a0081c4,
- .cm_autoidle_dpll_unipro = 0x4a0081c8,
- .cm_clksel_dpll_unipro = 0x4a0081cc,
- .cm_div_m2_dpll_unipro = 0x4a0081d0,
- .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
- .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
- .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
- .cm_coreaon_bandgap_clkctrl = 0x4a008648,
- .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
-
- /* cm2.core */
- .cm_l3_1_clkstctrl = 0x4a008700,
- .cm_l3_1_dynamicdep = 0x4a008708,
- .cm_l3_1_l3_1_clkctrl = 0x4a008720,
- .cm_l3_2_clkstctrl = 0x4a008800,
- .cm_l3_2_dynamicdep = 0x4a008808,
- .cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_gpmc_clkctrl = 0x4a008828,
- .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
- .cm_mpu_m3_clkstctrl = 0x4a008900,
- .cm_mpu_m3_staticdep = 0x4a008904,
- .cm_mpu_m3_dynamicdep = 0x4a008908,
- .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
- .cm_sdma_clkstctrl = 0x4a008a00,
- .cm_sdma_staticdep = 0x4a008a04,
- .cm_sdma_dynamicdep = 0x4a008a08,
- .cm_sdma_sdma_clkctrl = 0x4a008a20,
- .cm_memif_clkstctrl = 0x4a008b00,
- .cm_memif_dmm_clkctrl = 0x4a008b20,
- .cm_memif_emif_fw_clkctrl = 0x4a008b28,
- .cm_memif_emif_1_clkctrl = 0x4a008b30,
- .cm_memif_emif_2_clkctrl = 0x4a008b38,
- .cm_memif_dll_clkctrl = 0x4a008b40,
- .cm_memif_emif_h1_clkctrl = 0x4a008b50,
- .cm_memif_emif_h2_clkctrl = 0x4a008b58,
- .cm_memif_dll_h_clkctrl = 0x4a008b60,
- .cm_c2c_clkstctrl = 0x4a008c00,
- .cm_c2c_staticdep = 0x4a008c04,
- .cm_c2c_dynamicdep = 0x4a008c08,
- .cm_c2c_sad2d_clkctrl = 0x4a008c20,
- .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
- .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
- .cm_l4cfg_clkstctrl = 0x4a008d00,
- .cm_l4cfg_dynamicdep = 0x4a008d08,
- .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
- .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
- .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
- .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
- .cm_l3instr_clkstctrl = 0x4a008e00,
- .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
- .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
- .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
- .cm_l4per_clkstctrl = 0x4a009000,
- .cm_l4per_dynamicdep = 0x4a009008,
- .cm_l4per_adc_clkctrl = 0x4a009020,
- .cm_l4per_gptimer10_clkctrl = 0x4a009028,
- .cm_l4per_gptimer11_clkctrl = 0x4a009030,
- .cm_l4per_gptimer2_clkctrl = 0x4a009038,
- .cm_l4per_gptimer3_clkctrl = 0x4a009040,
- .cm_l4per_gptimer4_clkctrl = 0x4a009048,
- .cm_l4per_gptimer9_clkctrl = 0x4a009050,
- .cm_l4per_elm_clkctrl = 0x4a009058,
- .cm_l4per_gpio2_clkctrl = 0x4a009060,
- .cm_l4per_gpio3_clkctrl = 0x4a009068,
- .cm_l4per_gpio4_clkctrl = 0x4a009070,
- .cm_l4per_gpio5_clkctrl = 0x4a009078,
- .cm_l4per_gpio6_clkctrl = 0x4a009080,
- .cm_l4per_hdq1w_clkctrl = 0x4a009088,
- .cm_l4per_hecc1_clkctrl = 0x4a009090,
- .cm_l4per_hecc2_clkctrl = 0x4a009098,
- .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
- .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
- .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
- .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
- .cm_l4per_l4per_clkctrl = 0x4a0090c0,
- .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
- .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
- .cm_l4per_mgate_clkctrl = 0x4a0090e8,
- .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
- .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
- .cm_l4per_mcspi3_clkctrl = 0x4a009100,
- .cm_l4per_mcspi4_clkctrl = 0x4a009108,
- .cm_l4per_gpio7_clkctrl = 0x4a009110,
- .cm_l4per_gpio8_clkctrl = 0x4a009118,
- .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
- .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
- .cm_l4per_msprohg_clkctrl = 0x4a009130,
- .cm_l4per_slimbus2_clkctrl = 0x4a009138,
- .cm_l4per_uart1_clkctrl = 0x4a009140,
- .cm_l4per_uart2_clkctrl = 0x4a009148,
- .cm_l4per_uart3_clkctrl = 0x4a009150,
- .cm_l4per_uart4_clkctrl = 0x4a009158,
- .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
- .cm_l4per_i2c5_clkctrl = 0x4a009168,
- .cm_l4per_uart5_clkctrl = 0x4a009170,
- .cm_l4per_uart6_clkctrl = 0x4a009178,
- .cm_l4sec_clkstctrl = 0x4a009180,
- .cm_l4sec_staticdep = 0x4a009184,
- .cm_l4sec_dynamicdep = 0x4a009188,
- .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
- .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
- .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
- .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
- .cm_l4sec_rng_clkctrl = 0x4a0091c0,
- .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
- .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
-
- /* cm2.ivahd */
- .cm_ivahd_clkstctrl = 0x4a009200,
- .cm_ivahd_ivahd_clkctrl = 0x4a009220,
- .cm_ivahd_sl2_clkctrl = 0x4a009228,
-
- /* cm2.cam */
- .cm_cam_clkstctrl = 0x4a009300,
- .cm_cam_iss_clkctrl = 0x4a009320,
- .cm_cam_fdif_clkctrl = 0x4a009328,
-
- /* cm2.dss */
- .cm_dss_clkstctrl = 0x4a009400,
- .cm_dss_dss_clkctrl = 0x4a009420,
-
- /* cm2.sgx */
- .cm_sgx_clkstctrl = 0x4a009500,
- .cm_sgx_sgx_clkctrl = 0x4a009520,
-
- /* cm2.l3init */
- .cm_l3init_clkstctrl = 0x4a009600,
-
- /* cm2.l3init */
- .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
- .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
- .cm_l3init_hsi_clkctrl = 0x4a009638,
- .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
- .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
- .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
- .cm_l3init_p1500_clkctrl = 0x4a009678,
- .cm_l3init_sata_clkctrl = 0x4a009688,
- .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
- .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
- .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
- .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
-
- /* prm irqstatus regs */
- .prm_irqstatus_mpu_2 = 0x4ae06014,
-
- /* l4 wkup regs */
- .cm_abe_pll_ref_clksel = 0x4ae0610c,
- .cm_sys_clksel = 0x4ae06110,
- .cm_wkup_clkstctrl = 0x4ae07900,
- .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
- .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
- .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
- .cm_wkup_gpio1_clkctrl = 0x4ae07938,
- .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
- .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
- .cm_wkup_synctimer_clkctrl = 0x4ae07950,
- .cm_wkup_usim_clkctrl = 0x4ae07958,
- .cm_wkup_sarram_clkctrl = 0x4ae07960,
- .cm_wkup_keyboard_clkctrl = 0x4ae07978,
- .cm_wkup_rtc_clkctrl = 0x4ae07980,
- .cm_wkup_bandgap_clkctrl = 0x4ae07988,
- .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
- .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
- .prm_rstctrl = 0x4ae07c00,
- .prm_rstst = 0x4ae07c04,
- .prm_rsttime = 0x4ae07c08,
- .prm_vc_val_bypass = 0x4ae07ca0,
- .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
- .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
-
- .prm_abbldo_mpu_setup = 0x4ae07cdc,
- .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
-
- /* SCRM stuff, used by some boards */
- .scrm_auxclk0 = 0x4ae0a310,
- .scrm_auxclk1 = 0x4ae0a314,
-};
-
-struct prcm_regs const dra7xx_prcm = {
- /* cm1.ckgen */
- .cm_clksel_core = 0x4a005100,
- .cm_clksel_abe = 0x4a005108,
- .cm_dll_ctrl = 0x4a005110,
- .cm_clkmode_dpll_core = 0x4a005120,
- .cm_idlest_dpll_core = 0x4a005124,
- .cm_autoidle_dpll_core = 0x4a005128,
- .cm_clksel_dpll_core = 0x4a00512c,
- .cm_div_m2_dpll_core = 0x4a005130,
- .cm_div_m3_dpll_core = 0x4a005134,
- .cm_div_h11_dpll_core = 0x4a005138,
- .cm_div_h12_dpll_core = 0x4a00513c,
- .cm_div_h13_dpll_core = 0x4a005140,
- .cm_div_h14_dpll_core = 0x4a005144,
- .cm_ssc_deltamstep_dpll_core = 0x4a005148,
- .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
- .cm_div_h21_dpll_core = 0x4a005150,
- .cm_div_h22_dpllcore = 0x4a005154,
- .cm_div_h23_dpll_core = 0x4a005158,
- .cm_div_h24_dpll_core = 0x4a00515c,
- .cm_clkmode_dpll_mpu = 0x4a005160,
- .cm_idlest_dpll_mpu = 0x4a005164,
- .cm_autoidle_dpll_mpu = 0x4a005168,
- .cm_clksel_dpll_mpu = 0x4a00516c,
- .cm_div_m2_dpll_mpu = 0x4a005170,
- .cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
- .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
- .cm_bypclk_dpll_mpu = 0x4a00519c,
- .cm_clkmode_dpll_iva = 0x4a0051a0,
- .cm_idlest_dpll_iva = 0x4a0051a4,
- .cm_autoidle_dpll_iva = 0x4a0051a8,
- .cm_clksel_dpll_iva = 0x4a0051ac,
- .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
- .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
- .cm_bypclk_dpll_iva = 0x4a0051dc,
- .cm_clkmode_dpll_abe = 0x4a0051e0,
- .cm_idlest_dpll_abe = 0x4a0051e4,
- .cm_autoidle_dpll_abe = 0x4a0051e8,
- .cm_clksel_dpll_abe = 0x4a0051ec,
- .cm_div_m2_dpll_abe = 0x4a0051f0,
- .cm_div_m3_dpll_abe = 0x4a0051f4,
- .cm_ssc_deltamstep_dpll_abe = 0x4a005208,
- .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
- .cm_clkmode_dpll_ddrphy = 0x4a005210,
- .cm_idlest_dpll_ddrphy = 0x4a005214,
- .cm_autoidle_dpll_ddrphy = 0x4a005218,
- .cm_clksel_dpll_ddrphy = 0x4a00521c,
- .cm_div_m2_dpll_ddrphy = 0x4a005220,
- .cm_div_h11_dpll_ddrphy = 0x4a005228,
- .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
- .cm_clkmode_dpll_dsp = 0x4a005234,
- .cm_shadow_freq_config1 = 0x4a005260,
- .cm_clkmode_dpll_gmac = 0x4a0052a8,
- .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640,
- .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
-
- /* cm1.mpu */
- .cm_mpu_mpu_clkctrl = 0x4a005320,
-
- /* cm1.dsp */
- .cm_dsp_clkstctrl = 0x4a005400,
- .cm_dsp_dsp_clkctrl = 0x4a005420,
-
- /* prm irqstatus regs */
- .prm_irqstatus_mpu_2 = 0x4ae06014,
-
- /* cm2.ckgen */
- .cm_clksel_usb_60mhz = 0x4a008104,
- .cm_clkmode_dpll_per = 0x4a008140,
- .cm_idlest_dpll_per = 0x4a008144,
- .cm_autoidle_dpll_per = 0x4a008148,
- .cm_clksel_dpll_per = 0x4a00814c,
- .cm_div_m2_dpll_per = 0x4a008150,
- .cm_div_m3_dpll_per = 0x4a008154,
- .cm_div_h11_dpll_per = 0x4a008158,
- .cm_div_h12_dpll_per = 0x4a00815c,
- .cm_div_h13_dpll_per = 0x4a008160,
- .cm_div_h14_dpll_per = 0x4a008164,
- .cm_ssc_deltamstep_dpll_per = 0x4a008168,
- .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
- .cm_clkmode_dpll_usb = 0x4a008180,
- .cm_idlest_dpll_usb = 0x4a008184,
- .cm_autoidle_dpll_usb = 0x4a008188,
- .cm_clksel_dpll_usb = 0x4a00818c,
- .cm_div_m2_dpll_usb = 0x4a008190,
- .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
- .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
- .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
- .cm_clkmode_dpll_pcie_ref = 0x4a008200,
- .cm_clkmode_apll_pcie = 0x4a00821c,
- .cm_idlest_apll_pcie = 0x4a008220,
- .cm_div_m2_apll_pcie = 0x4a008224,
- .cm_clkvcoldo_apll_pcie = 0x4a008228,
-
- /* cm2.core */
- .cm_l3_1_clkstctrl = 0x4a008700,
- .cm_l3_1_dynamicdep = 0x4a008708,
- .cm_l3_1_l3_1_clkctrl = 0x4a008720,
- .cm_l3_gpmc_clkctrl = 0x4a008728,
- .cm_mpu_m3_clkstctrl = 0x4a008900,
- .cm_mpu_m3_staticdep = 0x4a008904,
- .cm_mpu_m3_dynamicdep = 0x4a008908,
- .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
- .cm_sdma_clkstctrl = 0x4a008a00,
- .cm_sdma_staticdep = 0x4a008a04,
- .cm_sdma_dynamicdep = 0x4a008a08,
- .cm_sdma_sdma_clkctrl = 0x4a008a20,
- .cm_memif_clkstctrl = 0x4a008b00,
- .cm_memif_dmm_clkctrl = 0x4a008b20,
- .cm_memif_emif_fw_clkctrl = 0x4a008b28,
- .cm_memif_emif_1_clkctrl = 0x4a008b30,
- .cm_memif_emif_2_clkctrl = 0x4a008b38,
- .cm_memif_dll_clkctrl = 0x4a008b40,
- .cm_l4cfg_clkstctrl = 0x4a008d00,
- .cm_l4cfg_dynamicdep = 0x4a008d08,
- .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
- .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
- .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
- .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
- .cm_l3instr_clkstctrl = 0x4a008e00,
- .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
- .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
- .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
-
- /* cm2.ivahd */
- .cm_ivahd_clkstctrl = 0x4a008f00,
- .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
- .cm_ivahd_sl2_clkctrl = 0x4a008f28,
-
- /* cm2.cam */
- .cm_cam_clkstctrl = 0x4a009000,
- .cm_cam_vip1_clkctrl = 0x4a009020,
- .cm_cam_vip2_clkctrl = 0x4a009028,
- .cm_cam_vip3_clkctrl = 0x4a009030,
- .cm_cam_lvdsrx_clkctrl = 0x4a009038,
- .cm_cam_csi1_clkctrl = 0x4a009040,
- .cm_cam_csi2_clkctrl = 0x4a009048,
-
- /* cm2.dss */
- .cm_dss_clkstctrl = 0x4a009100,
- .cm_dss_dss_clkctrl = 0x4a009120,
-
- /* cm2.sgx */
- .cm_sgx_clkstctrl = 0x4a009200,
- .cm_sgx_sgx_clkctrl = 0x4a009220,
-
- /* cm2.l3init */
- .cm_l3init_clkstctrl = 0x4a009300,
-
- /* cm2.l3init */
- .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
- .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
- .cm_l3init_hsusbhost_clkctrl = 0x4a009340,
- .cm_l3init_hsusbotg_clkctrl = 0x4a009348,
- .cm_l3init_hsusbtll_clkctrl = 0x4a009350,
- .cm_l3init_sata_clkctrl = 0x4a009388,
- .cm_gmac_clkstctrl = 0x4a0093c0,
- .cm_gmac_gmac_clkctrl = 0x4a0093d0,
- .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
- .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
- .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0,
-
- /* cm2.l4per */
- .cm_l4per_clkstctrl = 0x4a009700,
- .cm_l4per_dynamicdep = 0x4a009708,
- .cm_l4per_gptimer10_clkctrl = 0x4a009728,
- .cm_l4per_gptimer11_clkctrl = 0x4a009730,
- .cm_l4per_gptimer2_clkctrl = 0x4a009738,
- .cm_l4per_gptimer3_clkctrl = 0x4a009740,
- .cm_l4per_gptimer4_clkctrl = 0x4a009748,
- .cm_l4per_gptimer9_clkctrl = 0x4a009750,
- .cm_l4per_elm_clkctrl = 0x4a009758,
- .cm_l4per_gpio2_clkctrl = 0x4a009760,
- .cm_l4per_gpio3_clkctrl = 0x4a009768,
- .cm_l4per_gpio4_clkctrl = 0x4a009770,
- .cm_l4per_gpio5_clkctrl = 0x4a009778,
- .cm_l4per_gpio6_clkctrl = 0x4a009780,
- .cm_l4per_hdq1w_clkctrl = 0x4a009788,
- .cm_l4per_i2c1_clkctrl = 0x4a0097a0,
- .cm_l4per_i2c2_clkctrl = 0x4a0097a8,
- .cm_l4per_i2c3_clkctrl = 0x4a0097b0,
- .cm_l4per_i2c4_clkctrl = 0x4a0097b8,
- .cm_l4per_l4per_clkctrl = 0x4a0097c0,
- .cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
- .cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
- .cm_l4per_mcspi3_clkctrl = 0x4a009800,
- .cm_l4per_mcspi4_clkctrl = 0x4a009808,
- .cm_l4per_gpio7_clkctrl = 0x4a009810,
- .cm_l4per_gpio8_clkctrl = 0x4a009818,
- .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
- .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
- .cm_l4per_qspi_clkctrl = 0x4a009838,
- .cm_l4per_uart1_clkctrl = 0x4a009840,
- .cm_l4per_uart2_clkctrl = 0x4a009848,
- .cm_l4per_uart3_clkctrl = 0x4a009850,
- .cm_l4per_uart4_clkctrl = 0x4a009858,
- .cm_l4per_uart5_clkctrl = 0x4a009870,
- .cm_l4sec_clkstctrl = 0x4a009880,
- .cm_l4sec_staticdep = 0x4a009884,
- .cm_l4sec_dynamicdep = 0x4a009888,
- .cm_l4sec_aes1_clkctrl = 0x4a0098a0,
- .cm_l4sec_aes2_clkctrl = 0x4a0098a8,
- .cm_l4sec_des3des_clkctrl = 0x4a0098b0,
- .cm_l4sec_rng_clkctrl = 0x4a0098c0,
- .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
- .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
-
- /* l4 wkup regs */
- .cm_abe_pll_ref_clksel = 0x4ae0610c,
- .cm_sys_clksel = 0x4ae06110,
- .cm_abe_pll_sys_clksel = 0x4ae06118,
- .cm_wkup_clkstctrl = 0x4ae07800,
- .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
- .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
- .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
- .cm_wkup_gpio1_clkctrl = 0x4ae07838,
- .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
- .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
- .cm_wkup_sarram_clkctrl = 0x4ae07860,
- .cm_wkup_keyboard_clkctrl = 0x4ae07878,
- .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
- .prm_rstctrl = 0x4ae07d00,
- .prm_rstst = 0x4ae07d04,
- .prm_rsttime = 0x4ae07d08,
- .prm_vc_val_bypass = 0x4ae07da0,
- .prm_vc_cfg_i2c_mode = 0x4ae07db4,
- .prm_vc_cfg_i2c_clk = 0x4ae07db8,
-
- .prm_abbldo_mpu_setup = 0x4AE07DDC,
- .prm_abbldo_mpu_ctrl = 0x4AE07DE0,
-};
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
deleted file mode 100644
index 7d8cec0..0000000
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/*
- * Timing and Organization details of the ddr device parts used in OMAP5
- * EVM
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-
-/*
- * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
- * EVM. Since the parts used and geometry are identical for
- * evm for a given OMAP5 revision, this information is kept
- * here instead of being in board directory. However the key functions
- * exported are weakly linked so that they can be over-ridden in the board
- * directory if there is a OMAP5 board in the future that uses a different
- * memory device or geometry.
- *
- * For any new board with different memory devices over-ride one or more
- * of the following functions as per the CONFIG flags you intend to enable:
- * - emif_get_reg_dump()
- * - emif_get_dmm_regs()
- * - emif_get_device_details()
- * - emif_get_device_timings()
- */
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-const struct emif_regs emif_regs_532_mhz_2cs = {
- .sdram_config_init = 0x80800EBA,
- .sdram_config = 0x808022BA,
- .ref_ctrl = 0x0000081A,
- .sdram_tim1 = 0x772F6873,
- .sdram_tim2 = 0x304a129a,
- .sdram_tim3 = 0x02f7e45f,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x000b3215,
- .temp_alert_config = 0x08000a05,
- .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
- .emif_ddr_phy_ctlr_1 = 0x0E28420d,
- .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
- .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
- .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
- .emif_ddr_ext_phy_ctrl_5 = 0x04010040
-};
-
-const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
- .sdram_config_init = 0x80800EBA,
- .sdram_config = 0x808022BA,
- .ref_ctrl = 0x0000081A,
- .sdram_tim1 = 0x772F6873,
- .sdram_tim2 = 0x304a129a,
- .sdram_tim3 = 0x02f7e45f,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x100b3215,
- .temp_alert_config = 0x08000a05,
- .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
- .emif_ddr_phy_ctlr_1 = 0x0E30400d,
- .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
- .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
- .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
- .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
-};
-
-const struct emif_regs emif_regs_266_mhz_2cs = {
- .sdram_config_init = 0x80800EBA,
- .sdram_config = 0x808022BA,
- .ref_ctrl = 0x0000040D,
- .sdram_tim1 = 0x2A86B419,
- .sdram_tim2 = 0x1025094A,
- .sdram_tim3 = 0x026BA22F,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x000b3215,
- .temp_alert_config = 0x08000a05,
- .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
- .emif_ddr_phy_ctlr_1 = 0x0E28420d,
- .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
- .emif_ddr_ext_phy_ctrl_3 = 0x14829052,
- .emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
- .emif_ddr_ext_phy_ctrl_5 = 0x04010040
-};
-
-const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x0,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0020420A,
- .emif_ddr_phy_ctlr_1 = 0x0024420A,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x0,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x1007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0030400A,
- .emif_ddr_phy_ctlr_1 = 0x0034400A,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x40000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851ab2,
- .sdram_config = 0x61851ab2,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
- .emif_ddr_phy_ctlr_1 = 0x0E24400A,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
- .emif_ddr_phy_ctlr_1 = 0x0E24400A,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851AB2,
- .sdram_config = 0x61851AB2,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
- .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
- .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-/*
- * DRA752 EVM board has 1.5 GB of memory
- * EMIF1 --> 2Gb * 2 = 512MB
- * EMIF2 --> 2Gb * 4 = 1GB
- * so mapping 1GB interleaved and 512MB non-interleaved
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x80640300,
- .dmm_lisa_map_2 = 0xC0500220,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-/*
- * DRA752 EVM EMIF1 ONLY CONFIGURATION
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80500100,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-/*
- * DRA752 EVM EMIF2 ONLY CONFIGURATION
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80600200,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-/*
- * DRA722 EVM EMIF1 CONFIGURATION
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80600100,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
-{
- switch (omap_revision()) {
- case OMAP5430_ES1_0:
- *regs = &emif_regs_532_mhz_2cs;
- break;
- case OMAP5432_ES1_0:
- *regs = &emif_regs_ddr3_532_mhz_1cs;
- break;
- case OMAP5430_ES2_0:
- *regs = &emif_regs_532_mhz_2cs_es2;
- break;
- case OMAP5432_ES2_0:
- *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- switch (emif_nr) {
- case 1:
- *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
- break;
- case 2:
- *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
- break;
- }
- break;
- case DRA722_ES1_0:
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
- break;
- default:
- *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
- }
-}
-
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
- __attribute__((weak, alias("emif_get_reg_dump_sdp")));
-
-static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
- **dmm_lisa_regs)
-{
- switch (omap_revision()) {
- case OMAP5430_ES1_0:
- case OMAP5430_ES2_0:
- case OMAP5432_ES1_0:
- case OMAP5432_ES2_0:
- *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
- break;
- case DRA722_ES1_0:
- default:
- *dmm_lisa_regs = &lisa_map_2G_x_2;
- }
-
-}
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
- __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
-#else
-
-static const struct lpddr2_device_details dev_4G_S4_details = {
- .type = LPDDR2_TYPE_S4,
- .density = LPDDR2_DENSITY_4Gb,
- .io_width = LPDDR2_IO_WIDTH_32,
- .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
-};
-
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
-{
- /* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = dev_4G_S4_details;
- *cs1_device_details = dev_4G_S4_details;
-}
-
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
- __attribute__((weak, alias("emif_get_device_details_sdp")));
-
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-const u32 ext_phy_ctrl_const_base[] = {
- 0x01004010,
- 0x00001004,
- 0x04010040,
- 0x01004010,
- 0x00001004,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x80080080,
- 0x00800800,
- 0x08102040,
- 0x00000001,
- 0x540A8150,
- 0xA81502a0,
- 0x002A0540,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000077,
- 0x0
-};
-
-const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
- 0x01004010,
- 0x00001004,
- 0x04010040,
- 0x01004010,
- 0x00001004,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x80080080,
- 0x00800800,
- 0x08102040,
- 0x00000002,
- 0x0,
- 0x0,
- 0x0,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000057,
- 0x0
-};
-
-const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
- 0x50D4350D,
- 0x00000D43,
- 0x04010040,
- 0x01004010,
- 0x00001004,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x80080080,
- 0x00800800,
- 0x08102040,
- 0x00000002,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000057,
- 0x0
-};
-
-const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00000000,
- 0x00600020,
- 0x40010080,
- 0x08102040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00000000,
- 0x00600020,
- 0x40010080,
- 0x08102040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-const u32
-dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
- 0x00A400A4,
- 0x00390039,
- 0x00320032,
- 0x00320032,
- 0x00320032,
- 0x00440044,
- 0x00550055,
- 0x00550055,
- 0x00550055,
- 0x00550055,
- 0x007F007F,
- 0x004D004D,
- 0x00430043,
- 0x00560056,
- 0x00540054,
- 0x00600060,
- 0x0,
- 0x00600020,
- 0x40010080,
- 0x08102040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-const struct lpddr2_mr_regs mr_regs = {
- .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
- .mr2 = 0x6,
- .mr3 = 0x1,
- .mr10 = MR10_ZQ_ZQINIT,
- .mr16 = MR16_REF_FULL_ARRAY
-};
-
-void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
- const u32 **regs,
- u32 *size)
-{
- switch (omap_revision()) {
- case OMAP5430_ES1_0:
- case OMAP5430_ES2_0:
- *regs = ext_phy_ctrl_const_base;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
- break;
- case OMAP5432_ES1_0:
- *regs = ddr3_ext_phy_ctrl_const_base_es1;
- *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
- break;
- case OMAP5432_ES2_0:
- *regs = ddr3_ext_phy_ctrl_const_base_es2;
- *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- if (emif_nr == 1) {
- *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
- *size =
- ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
- } else {
- *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
- *size =
- ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
- }
- break;
- case DRA722_ES1_0:
- *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
- *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
- break;
- default:
- *regs = ddr3_ext_phy_ctrl_const_base_es2;
- *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
-
- }
-}
-
-void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
-{
- *regs = &mr_regs;
-}
-
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
-{
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 emif_nr;
- const u32 *ext_phy_ctrl_const_regs;
- u32 i = 0;
- u32 size;
-
- emif_nr = (base == EMIF1_BASE) ? 1 : 2;
-
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- emif_get_ext_phy_ctrl_const_regs(emif_nr,
- &ext_phy_ctrl_const_regs, &size);
-
- for (i = 0; i < size; i++) {
- writel(ext_phy_ctrl_const_regs[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_regs[i],
- emif_ext_phy_ctrl_base++);
- }
-}
-
-#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
- .max_freq = 532000000,
- .RL = 8,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 15,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
-static const struct lpddr2_min_tck min_tck = {
- .tRL = 3,
- .tRP_AB = 3,
- .tRCD = 3,
- .tWR = 3,
- .tRAS_MIN = 3,
- .tRRD = 2,
- .tWTR = 2,
- .tXP = 2,
- .tRTP = 2,
- .tCKE = 3,
- .tCKESR = 3,
- .tFAW = 8
-};
-
-static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
- &timings_jedec_532_mhz
-};
-
-static const struct lpddr2_device_timings dev_4G_S4_timings = {
- .ac_timings = ac_timings,
- .min_tck = &min_tck,
-};
-
-/*
- * List of status registers to be controlled back to control registers
- * after initial leveling
- * readreg, writereg
- */
-const struct read_write_regs omap5_bug_00339_regs[] = {
- { 8, 5 },
- { 9, 6 },
- { 10, 7 },
- { 14, 8 },
- { 15, 9 },
- { 16, 10 },
- { 11, 2 },
- { 12, 3 },
- { 13, 4 },
- { 17, 11 },
- { 18, 12 },
- { 19, 13 },
-};
-
-const struct read_write_regs dra_bug_00339_regs[] = {
- { 7, 7 },
- { 8, 8 },
- { 9, 9 },
- { 10, 10 },
- { 11, 11 },
- { 12, 2 },
- { 13, 3 },
- { 14, 4 },
- { 15, 5 },
- { 16, 6 },
- { 17, 12 },
- { 18, 13 },
- { 19, 14 },
- { 20, 15 },
- { 21, 16 },
- { 22, 17 },
- { 23, 18 },
- { 24, 19 },
- { 25, 20 },
- { 26, 21}
-};
-
-const struct read_write_regs *get_bug_regs(u32 *iterations)
-{
- const struct read_write_regs *bug_00339_regs_ptr = NULL;
-
- switch (omap_revision()) {
- case OMAP5430_ES1_0:
- case OMAP5430_ES2_0:
- case OMAP5432_ES1_0:
- case OMAP5432_ES2_0:
- bug_00339_regs_ptr = omap5_bug_00339_regs;
- *iterations = sizeof(omap5_bug_00339_regs)/
- sizeof(omap5_bug_00339_regs[0]);
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA722_ES1_0:
- bug_00339_regs_ptr = dra_bug_00339_regs;
- *iterations = sizeof(dra_bug_00339_regs)/
- sizeof(dra_bug_00339_regs[0]);
- break;
- default:
- printf("\n Error: UnKnown SOC");
- }
-
- return bug_00339_regs_ptr;
-}
-
-void emif_get_device_timings_sdp(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings)
-{
- /* Identical devices on EMIF1 & EMIF2 */
- *cs0_device_timings = &dev_4G_S4_timings;
- *cs1_device_timings = &dev_4G_S4_timings;
-}
-
-void emif_get_device_timings(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings)
- __attribute__((weak, alias("emif_get_device_timings_sdp")));
-
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c
new file mode 100644
index 0000000..a328b2b
--- /dev/null
+++ b/arch/arm/cpu/armv7/psci-common.c
@@ -0,0 +1,46 @@
+/*
+ * Common PSCI functions
+ *
+ * Copyright (C) 2016 Chen-Yu Tsai
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <asm/armv7.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <linux/linkage.h>
+
+static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
+static u32 psci_context_id[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
+
+void __secure psci_save(int cpu, u32 pc, u32 context_id)
+{
+ psci_target_pc[cpu] = pc;
+ psci_context_id[cpu] = context_id;
+ dsb();
+}
+
+u32 __secure psci_get_target_pc(int cpu)
+{
+ return psci_target_pc[cpu];
+}
+
+u32 __secure psci_get_context_id(int cpu)
+{
+ return psci_context_id[cpu];
+}
+
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bf11a34..983cd90 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -17,6 +17,7 @@
#include <config.h>
#include <linux/linkage.h>
+#include <asm/macro.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
@@ -45,20 +46,62 @@
ENDPROC(default_psci_vector)
.weak default_psci_vector
+ENTRY(psci_version)
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
+.weak psci_affinity_info
.weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
@@ -69,6 +112,42 @@
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
+ .word ARM_PSCI_0_2_FN_PSCI_VERSION
+ .word psci_version
+ .word ARM_PSCI_0_2_FN_CPU_SUSPEND
+ .word psci_cpu_suspend
+ .word ARM_PSCI_0_2_FN_CPU_OFF
+ .word psci_cpu_off
+ .word ARM_PSCI_0_2_FN_CPU_ON
+ .word psci_cpu_on
+ .word ARM_PSCI_0_2_FN_AFFINITY_INFO
+ .word psci_affinity_info
+ .word ARM_PSCI_0_2_FN_MIGRATE
+ .word psci_migrate
+ .word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
+ .word psci_migrate_info_type
+ .word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
+ .word psci_migrate_info_up_cpu
+ .word ARM_PSCI_0_2_FN_SYSTEM_OFF
+ .word psci_system_off
+ .word ARM_PSCI_0_2_FN_SYSTEM_RESET
+ .word psci_system_reset
+ .word ARM_PSCI_1_0_FN_PSCI_FEATURES
+ .word psci_features
+ .word ARM_PSCI_1_0_FN_CPU_FREEZE
+ .word psci_cpu_freeze
+ .word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+ .word psci_cpu_default_suspend
+ .word ARM_PSCI_1_0_FN_NODE_HW_STATE
+ .word psci_node_hw_state
+ .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+ .word psci_system_suspend
+ .word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+ .word psci_set_suspend_mode
+ .word ARM_PSCI_1_0_FN_STAT_RESIDENCY
+ .word psi_stat_residency
+ .word ARM_PSCI_1_0_FN_STAT_COUNT
+ .word psci_stat_count
.word 0
.word 0
@@ -99,4 +178,170 @@
pop {r4-r7, lr}
movs pc, lr @ Return to the kernel
+@ Requires dense and single-cluster CPU ID space
+ENTRY(psci_get_cpu_id)
+ mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
+ and r0, r0, #0xff /* return CPU ID in cluster */
+ bx lr
+ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
+
+/* Imported from Linux kernel */
+ENTRY(psci_v7_flush_dcache_all)
+ stmfd sp!, {r4-r5, r7, r9-r11, lr}
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ ands r3, r0, #0x7000000 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
+ beq finished @ if loc is 0, then no need to clean
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt skip @ skip if no cache, or just i-cache
+ mrs r9, cpsr @ make cssr&csidr read atomic
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ msr cpsr_c, r9
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
+ orr r11, r11, r9, lsl r2 @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ ldmfd sp!, {r4-r5, r7, r9-r11, lr}
+ bx lr
+ENDPROC(psci_v7_flush_dcache_all)
+
+ENTRY(psci_disable_smp)
+ mrc p15, 0, r0, c1, c0, 1 @ ACTLR
+ bic r0, r0, #(1 << 6) @ Clear SMP bit
+ mcr p15, 0, r0, c1, c0, 1 @ ACTLR
+ isb
+ dsb
+ bx lr
+ENDPROC(psci_disable_smp)
+.weak psci_disable_smp
+
+ENTRY(psci_enable_smp)
+ mrc p15, 0, r0, c1, c0, 1 @ ACTLR
+ orr r0, r0, #(1 << 6) @ Set SMP bit
+ mcr p15, 0, r0, c1, c0, 1 @ ACTLR
+ isb
+ bx lr
+ENDPROC(psci_enable_smp)
+.weak psci_enable_smp
+
+ENTRY(psci_cpu_off_common)
+ push {lr}
+
+ bl psci_v7_flush_dcache_all
+
+ clrex @ Why???
+
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR
+ bic r0, r0, #(1 << 2) @ Clear C bit
+ mcr p15, 0, r0, c1, c0, 0 @ SCTLR
+ isb
+ dsb
+
+ bl psci_v7_flush_dcache_all
+
+ clrex @ Why???
+
+ bl psci_disable_smp
+
+ pop {lr}
+ bx lr
+ENDPROC(psci_cpu_off_common)
+
+@ The stacks are allocated in reverse order, i.e.
+@ the stack for CPU0 has the highest memory address.
+@
+@ -------------------- __secure_stack_end
+@ | CPU0 target PC |
+@ |------------------|
+@ | |
+@ | CPU0 stack |
+@ | |
+@ |------------------| __secure_stack_end - 1KB
+@ | . |
+@ | . |
+@ | . |
+@ | . |
+@ -------------------- __secure_stack_start
+@
+@ This expects CPU ID in r0 and returns stack top in r0
+LENTRY(psci_get_cpu_stack_top)
+ @ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT)
+ ldr r3, =__secure_stack_end
+ sub r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT
+ sub r0, r0, #4 @ Save space for target PC
+ bx lr
+ENDPROC(psci_get_cpu_stack_top)
+
+@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
+@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
+@ this function.
+ENTRY(psci_stack_setup)
+ mov r6, lr
+ mov r7, r0
+ bl psci_get_cpu_id @ CPU ID => r0
+ bl psci_get_cpu_stack_top @ stack top => r0
+ mov sp, r0
+ mov r0, r7
+ bx r6
+ENDPROC(psci_stack_setup)
+
+ENTRY(psci_arch_init)
+ mov pc, lr
+ENDPROC(psci_arch_init)
+.weak psci_arch_init
+
+ENTRY(psci_arch_cpu_entry)
+ mov pc, lr
+ENDPROC(psci_arch_cpu_entry)
+.weak psci_arch_cpu_entry
+
+ENTRY(psci_cpu_entry)
+ bl psci_enable_smp
+
+ bl _nonsec_init
+
+ bl psci_stack_setup
+
+ bl psci_arch_cpu_entry
+
+ bl psci_get_cpu_id @ CPU ID => r0
+ mov r2, r0 @ CPU ID => r2
+ bl psci_get_context_id @ context id => r0
+ mov r1, r0 @ context id => r1
+ mov r0, r2 @ CPU ID => r0
+ bl psci_get_target_pc @ target PC => r0
+ b _do_nonsec_entry
+ENDPROC(psci_cpu_entry)
+
.popsection
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
deleted file mode 100644
index 6d94199..0000000
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-if RMOBILE
-
-choice
- prompt "Renesus ARM SoCs board select"
-
-config TARGET_ARMADILLO_800EVA
- bool "armadillo 800 eva board"
-
-config TARGET_GOSE
- bool "Gose board"
-
-config TARGET_KOELSCH
- bool "Koelsch board"
-
-config TARGET_LAGER
- bool "Lager board"
-
-config TARGET_KZM9G
- bool "KZM9D board"
-
-config TARGET_ALT
- bool "Alt board"
-
-endchoice
-
-config SYS_SOC
- default "rmobile"
-
-config RMOBILE_EXTRAM_BOOT
- bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
- default n
-
-source "board/atmark-techno/armadillo-800eva/Kconfig"
-source "board/renesas/gose/Kconfig"
-source "board/renesas/koelsch/Kconfig"
-source "board/renesas/lager/Kconfig"
-source "board/kmc/kzm9g/Kconfig"
-source "board/renesas/alt/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
deleted file mode 100644
index 647e426..0000000
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu_info.o
-obj-y += emac.o
-
-obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
-obj-$(CONFIG_GLOBAL_TIMER) += timer.o
-obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
-obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
-obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
-obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
-obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/board.c b/arch/arm/cpu/armv7/rmobile/board.c
deleted file mode 100644
index d91bc26..0000000
--- a/arch/arm/cpu/armv7/rmobile/board.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-
-int checkboard(void)
-{
- printf("Board: %s\n", sysinfo.board_string);
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
deleted file mode 100644
index dfe8950..0000000
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-
-u32 rmobile_get_cpu_type(void)
-{
- u32 id;
- u32 type;
- struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
-
- id = readl(hpb->cccr);
- type = (id >> 8) & 0xFF;
-
- return type;
-}
-
-u32 rmobile_get_cpu_rev(void)
-{
- u32 id;
- u32 rev;
- struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
-
- id = readl(hpb->cccr);
- rev = (id >> 4) & 0xF;
-
- return rev;
-}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
deleted file mode 100644
index 42ee30f..0000000
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
- *
- * Copyright (C) 2013,2014 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-#include <common.h>
-#include <asm/io.h>
-
-#define PRR 0xFF000044
-
-u32 rmobile_get_cpu_type(void)
-{
- return (readl(PRR) & 0x00007F00) >> 8;
-}
-
-u32 rmobile_get_cpu_rev_integer(void)
-{
- return ((readl(PRR) & 0x000000F0) >> 4) + 1;
-}
-
-u32 rmobile_get_cpu_rev_fraction(void)
-{
- return readl(PRR) & 0x0000000F;
-}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
deleted file mode 100644
index 186b4b5..0000000
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-
-u32 rmobile_get_cpu_type(void)
-{
- u32 id;
- u32 type;
- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
-
- id = readl(&hpb->cccr);
- type = (id >> 8) & 0xFF;
-
- return type;
-}
-
-u32 rmobile_get_cpu_rev_integer(void)
-{
- u32 id;
- u32 rev;
- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
-
- id = readl(&hpb->cccr);
- rev = ((id >> 4) & 0xF) + 1;
-
- return rev;
-}
-
-u32 rmobile_get_cpu_rev_fraction(void)
-{
- u32 id;
- u32 rev;
- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
-
- id = readl(&hpb->cccr);
- rev = id & 0xF;
-
- return rev;
-}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
deleted file mode 100644
index d47c47c..0000000
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- icache_enable();
- return 0;
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- dcache_enable();
-}
-#endif
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-static u32 __rmobile_get_cpu_type(void)
-{
- return 0x0;
-}
-u32 rmobile_get_cpu_type(void)
- __attribute__((weak, alias("__rmobile_get_cpu_type")));
-
-static u32 __rmobile_get_cpu_rev_integer(void)
-{
- return 0;
-}
-u32 rmobile_get_cpu_rev_integer(void)
- __attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
-
-static u32 __rmobile_get_cpu_rev_fraction(void)
-{
- return 0;
-}
-u32 rmobile_get_cpu_rev_fraction(void)
- __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
-
-/* CPU infomation table */
-static const struct {
- u16 cpu_type;
- u8 cpu_name[10];
-} rmobile_cpuinfo[] = {
- { 0x37, "SH73A0" },
- { 0x40, "R8A7740" },
- { 0x45, "R8A7790" },
- { 0x47, "R8A7791" },
- { 0x4B, "R8A7793" },
- { 0x4C, "R8A7794" },
- { 0x0, "CPU" },
-};
-
-int print_cpuinfo(void)
-{
- int i = 0;
- u32 cpu_type = rmobile_get_cpu_type();
- for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) {
- if (rmobile_cpuinfo[i].cpu_type == cpu_type) {
- printf("CPU: Renesas Electronics %s rev %d.%d\n",
- rmobile_cpuinfo[i].cpu_name,
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
- }
- }
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/rmobile/emac.c b/arch/arm/cpu/armv7/rmobile/emac.c
deleted file mode 100644
index 0710cfd..0000000
--- a/arch/arm/cpu/armv7/rmobile/emac.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * RMOBILE EtherMAC initialization.
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <netdev.h>
-
-int cpu_eth_init(bd_t *bis)
-{
- int ret = -ENODEV;
-#ifdef CONFIG_SH_ETHER
- ret = sh_eth_initialize(bis);
-#endif
- return ret;
-}
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
deleted file mode 100644
index 0d65440..0000000
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
- ldr r0, =MERAM_BASE
- mov r1, #0x0
- str r1, [r0]
-
- mrc p15, 0, r0, c0, c0, 5
- ands r0, r0, #0xF
- beq lowlevel_init__
- b wait_interrupt
-
- .pool
- .align 4
-
-wait_interrupt:
-#ifdef ICCICR
- ldr r1, =ICCICR
- mov r2, #0x0
- str r2, [r1]
- mov r2, #0xF0
- adds r1, r1, #4 /* ICCPMR */
- str r2, [r1]
- ldr r1, =ICCICR
- mov r2, #0x1
- str r2, [r1]
-#endif
-
-wait_loop:
- .long 0xE320F003 /* wfi */
-
- ldr r2, [r1, #0xC]
- str r2, [r1, #0x10]
-
- ldr r0, =MERAM_BASE
- ldr r2, [r0]
- cmp r2, #0
- movne pc, r2
-
- b wait_loop
-
-wait_loop_end:
- .pool
- .align 4
-
-lowlevel_init__:
-
- mov r0, #0x200000
-
-loop0:
- subs r0, r0, #1
- bne loop0
-
- ldr sp, MERAM_STACK
- b s_init
-
- .pool
- .align 4
-
-ENDPROC(lowlevel_init)
- .ltorg
-
-MERAM_STACK:
- .word LOW_LEVEL_MERAM_STACK
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
deleted file mode 100644
index d47546a..0000000
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
- * This file is lager low level initialize.
- *
- * Copyright (C) 2013, 2014 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
- mrc p15, 0, r4, c0, c0, 5 /* mpidr */
- orr r4, r4, r4, lsr #6
- and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
-
- b do_lowlevel_init
-
- .pool
-
-/*
- * CPU ID #1-#3 come here
- */
- .align 4
-do_cpu_waiting:
- ldr r1, =0xe6180000 /* sysc */
-1: ldr r0, [r1, #0x20] /* sbar */
- tst r0, r0
- beq 1b
- bx r0
-
-/*
- * Only CPU ID #0 comes here
- */
- .align 4
-do_lowlevel_init:
- ldr r2, =0xFF000044 /* PRR */
- ldr r1, [r2]
- and r1, r1, #0x7F00
- lsrs r1, r1, #8
- cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
- beq _exit_init_l2_a15
-
- /* surpress wfe if ca15 */
- tst r4, #4
- mrceq p15, 0, r0, c1, c0, 1 /* actlr */
- orreq r0, r0, #(1<<7)
- mcreq p15, 0, r0, c1, c0, 1
-
- /* and set l2 latency */
- mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
- and r0, r0, #0xf00
- lsr r0, r0, #8
- tst r0, #1 /* only need for cluster 0 */
- bne _exit_init_l2_a15
-
- mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
- and r1, r0, #7
- cmp r1, #3 /* has already been set up */
- bicne r0, r0, #0xe7
- orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
-#if defined(CONFIG_R8A7790)
- orrne r0, r0, #0x20 /* L2CTLR[5] */
-#endif
- mcrne p15, 1, r0, c9, c0, 2
-_exit_init_l2_a15:
- ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
- sub sp, r3, #4
- str lr, [sp]
-
- /* initialize system */
- bl s_init
-
- ldr lr, [sp]
- mov pc, lr
- nop
-ENDPROC(lowlevel_init)
- .ltorg
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
deleted file mode 100644
index 1259062..0000000
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+++ /dev/null
@@ -1,829 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
- * This file is r8a7790 processor support - PFC hardware block.
- *
- * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Magnus Damm
- * Copyright (C) 2012 Renesas Solutions Corp.
- * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-#include "pfc-r8a7790.h"
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
- FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
- FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
- FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
- FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
- FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
- FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
- FN_IP3_14_12, FN_IP3_17_15,
-
- /* GPSR1 */
- FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
- FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
- FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
- FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
- FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
- FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
- FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
-
- /* GPSR2 */
- FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
- FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
- FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
- FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
- FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
- FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
- FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
-
- /* GPSR3 */
- FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
- FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
- FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
- FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
- FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
- FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
- FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
-
- /* GPSR4 */
- FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
- FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
- FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
- FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
- FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
- FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
- FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
- FN_IP14_15_12, FN_IP14_18_16,
-
- /* GPSR5 */
- FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
- FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
- FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
- FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
- FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
- FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
- FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
-
- /* IPSR0 - IPSR5 */
- /* IPSR6 */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
- FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
- FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
- FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
- FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
- FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
- FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
- FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
- FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
- FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
- FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
- FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
- FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
- FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
- FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
- FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
- FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
- FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
- FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
- FN_STP_IVCXO27_1_B, FN_HRX0_F,
-
- /* IPSR7 */
- FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
- FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
- FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
- FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
- FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
- FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
- FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
- FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
- FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
- FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
- FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
- FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
- FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
- FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
- FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
- FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
- FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
- FN_MII_RXD2,
-
- /* IPSR8 - IPSR16 */
-
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIF1_4,
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- FN_SEL_SCIFB1_4,
- FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- FN_SEL_SOF1_0, FN_SEL_SOF1_1,
- FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
- FN_SEL_SSI6_0, FN_SEL_SSI6_1,
- FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
- FN_SEL_VI3_0, FN_SEL_VI3_1,
- FN_SEL_VI2_0, FN_SEL_VI2_1,
- FN_SEL_VI1_0, FN_SEL_VI1_1,
- FN_SEL_VI0_0, FN_SEL_VI0_1,
- FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
- FN_SEL_LBS_0, FN_SEL_LBS_1,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_SOF3_0, FN_SEL_SOF3_1,
- FN_SEL_SOF0_0, FN_SEL_SOF0_1,
-
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
- FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- FN_SEL_ADI_0, FN_SEL_ADI_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
- FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
- FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
- FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
- FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
-
- FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
- FN_SEL_IIC0_0, FN_SEL_IIC0_1,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC2_4,
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
- FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
- FN_SEL_I2C2_4,
- FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
-
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
- VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
- DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
- SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
- INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
- DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
- MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
- SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
- ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
- TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
- SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
- STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
- SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
- STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
- SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
- RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
- TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
- RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
- STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
- ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
- STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
-
- ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
- SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
- RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
- ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
- HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
- SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
- STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
- ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
- TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
- SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
- GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
- STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
- PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
- PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
- AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
- ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
- VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
- MII_RXD2_MARK,
-
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_IPSR_DATA(IP6_2_0, DACK0),
- PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
- PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
- PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP6_8_6, DACK1),
- PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
- PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
- PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP6_13_11, DACK2),
- PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
- PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
- PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
- PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
- PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
- PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
- PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
- PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
-
- PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
- PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
- PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
- PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
- PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
- PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
- PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_18_16, PWM0),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_21_19, PWM1),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
- PINMUX_IPSR_DATA(IP7_24_22, PWM2),
- PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
- PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
- PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
- PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
- PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
- PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
- PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
- PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
- PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
- PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
- PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
-
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- /*IPSR0 - IPSR5*/
- /*IPSR6*/
- GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
- GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
- GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
- GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
- GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
- GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
- GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
- GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
- GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
- GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
- GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
- GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
- GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
- GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
- GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
- GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
- GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
- GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
- GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
- GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
- GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
- GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
-
- /*IPSR7*/
- GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
- GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
- GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
- GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
- GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
- GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
- GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
- GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
- GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
- GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
- GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
- GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
- GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
- GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
- GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
- GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
- GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
- GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
- /*IPSR8 - IPSR16*/
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP3_17_15,
- GP_0_30_FN, FN_IP3_14_12,
- GP_0_29_FN, FN_IP3_11_8,
- GP_0_28_FN, FN_IP3_7_4,
- GP_0_27_FN, FN_IP3_3_0,
- GP_0_26_FN, FN_IP2_28_26,
- GP_0_25_FN, FN_IP2_25_22,
- GP_0_24_FN, FN_IP2_21_18,
- GP_0_23_FN, FN_IP2_17_15,
- GP_0_22_FN, FN_IP2_14_12,
- GP_0_21_FN, FN_IP2_11_9,
- GP_0_20_FN, FN_IP2_8_6,
- GP_0_19_FN, FN_IP2_5_3,
- GP_0_18_FN, FN_IP2_2_0,
- GP_0_17_FN, FN_IP1_29_28,
- GP_0_16_FN, FN_IP1_27_26,
- GP_0_15_FN, FN_IP1_25_22,
- GP_0_14_FN, FN_IP1_21_18,
- GP_0_13_FN, FN_IP1_17_15,
- GP_0_12_FN, FN_IP1_14_12,
- GP_0_11_FN, FN_IP1_11_8,
- GP_0_10_FN, FN_IP1_7_4,
- GP_0_9_FN, FN_IP1_3_0,
- GP_0_8_FN, FN_IP0_30_27,
- GP_0_7_FN, FN_IP0_26_23,
- GP_0_6_FN, FN_IP0_22_20,
- GP_0_5_FN, FN_IP0_19_16,
- GP_0_4_FN, FN_IP0_15_12,
- GP_0_3_FN, FN_IP0_11_9,
- GP_0_2_FN, FN_IP0_8_6,
- GP_0_1_FN, FN_IP0_5_3,
- GP_0_0_FN, FN_IP0_2_0 }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- GP_1_29_FN, FN_IP6_13_11,
- GP_1_28_FN, FN_IP6_10_9,
- GP_1_27_FN, FN_IP6_8_6,
- GP_1_26_FN, FN_IP6_5_3,
- GP_1_25_FN, FN_IP6_2_0,
- GP_1_24_FN, FN_IP5_29_27,
- GP_1_23_FN, FN_IP5_26_24,
- GP_1_22_FN, FN_IP5_23_21,
- GP_1_21_FN, FN_IP5_20_18,
- GP_1_20_FN, FN_IP5_17_15,
- GP_1_19_FN, FN_IP5_14_13,
- GP_1_18_FN, FN_IP5_12_10,
- GP_1_17_FN, FN_IP5_9_6,
- GP_1_16_FN, FN_IP5_5_3,
- GP_1_15_FN, FN_IP5_2_0,
- GP_1_14_FN, FN_IP4_29_27,
- GP_1_13_FN, FN_IP4_26_24,
- GP_1_12_FN, FN_IP4_23_21,
- GP_1_11_FN, FN_IP4_20_18,
- GP_1_10_FN, FN_IP4_17_15,
- GP_1_9_FN, FN_IP4_14_12,
- GP_1_8_FN, FN_IP4_11_9,
- GP_1_7_FN, FN_IP4_8_6,
- GP_1_6_FN, FN_IP4_5_3,
- GP_1_5_FN, FN_IP4_2_0,
- GP_1_4_FN, FN_IP3_31_29,
- GP_1_3_FN, FN_IP3_28_26,
- GP_1_2_FN, FN_IP3_25_23,
- GP_1_1_FN, FN_IP3_22_20,
- GP_1_0_FN, FN_IP3_19_18, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- 0, 0,
- 0, 0,
- GP_2_29_FN, FN_IP7_15_13,
- GP_2_28_FN, FN_IP7_12_10,
- GP_2_27_FN, FN_IP7_9_8,
- GP_2_26_FN, FN_IP7_7_6,
- GP_2_25_FN, FN_IP7_5_3,
- GP_2_24_FN, FN_IP7_2_0,
- GP_2_23_FN, FN_IP6_31_29,
- GP_2_22_FN, FN_IP6_28_26,
- GP_2_21_FN, FN_IP6_25_23,
- GP_2_20_FN, FN_IP6_22_20,
- GP_2_19_FN, FN_IP6_19_17,
- GP_2_18_FN, FN_IP6_16_14,
- GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
- GP_2_16_FN, FN_IP8_27,
- GP_2_15_FN, FN_IP8_26,
- GP_2_14_FN, FN_IP8_25_24,
- GP_2_13_FN, FN_IP8_23_22,
- GP_2_12_FN, FN_IP8_21_20,
- GP_2_11_FN, FN_IP8_19_18,
- GP_2_10_FN, FN_IP8_17_16,
- GP_2_9_FN, FN_IP8_15_14,
- GP_2_8_FN, FN_IP8_13_12,
- GP_2_7_FN, FN_IP8_11_10,
- GP_2_6_FN, FN_IP8_9_8,
- GP_2_5_FN, FN_IP8_7_6,
- GP_2_4_FN, FN_IP8_5_4,
- GP_2_3_FN, FN_IP8_3_2,
- GP_2_2_FN, FN_IP8_1_0,
- GP_2_1_FN, FN_IP7_30_29,
- GP_2_0_FN, FN_IP7_28_27 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP11_21_18,
- GP_3_30_FN, FN_IP11_17_15,
- GP_3_29_FN, FN_IP11_14_13,
- GP_3_28_FN, FN_IP11_12_11,
- GP_3_27_FN, FN_IP11_10_9,
- GP_3_26_FN, FN_IP11_8_7,
- GP_3_25_FN, FN_IP11_6_5,
- GP_3_24_FN, FN_IP11_4,
- GP_3_23_FN, FN_IP11_3_0,
- GP_3_22_FN, FN_IP10_29_26,
- GP_3_21_FN, FN_IP10_25_23,
- GP_3_20_FN, FN_IP10_22_19,
- GP_3_19_FN, FN_IP10_18_15,
- GP_3_18_FN, FN_IP10_14_11,
- GP_3_17_FN, FN_IP10_10_7,
- GP_3_16_FN, FN_IP10_6_4,
- GP_3_15_FN, FN_IP10_3_0,
- GP_3_14_FN, FN_IP9_31_28,
- GP_3_13_FN, FN_IP9_27_26,
- GP_3_12_FN, FN_IP9_25_24,
- GP_3_11_FN, FN_IP9_23_22,
- GP_3_10_FN, FN_IP9_21_20,
- GP_3_9_FN, FN_IP9_19_18,
- GP_3_8_FN, FN_IP9_17_16,
- GP_3_7_FN, FN_IP9_15_12,
- GP_3_6_FN, FN_IP9_11_8,
- GP_3_5_FN, FN_IP9_7_6,
- GP_3_4_FN, FN_IP9_5_4,
- GP_3_3_FN, FN_IP9_3_2,
- GP_3_2_FN, FN_IP9_1_0,
- GP_3_1_FN, FN_IP8_30_29,
- GP_3_0_FN, FN_IP8_28 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP14_18_16,
- GP_4_30_FN, FN_IP14_15_12,
- GP_4_29_FN, FN_IP14_11_9,
- GP_4_28_FN, FN_IP14_8_6,
- GP_4_27_FN, FN_IP14_5_3,
- GP_4_26_FN, FN_IP14_2_0,
- GP_4_25_FN, FN_IP13_30_29,
- GP_4_24_FN, FN_IP13_28_26,
- GP_4_23_FN, FN_IP13_25_23,
- GP_4_22_FN, FN_IP13_22_19,
- GP_4_21_FN, FN_IP13_18_16,
- GP_4_20_FN, FN_IP13_15_13,
- GP_4_19_FN, FN_IP13_12_10,
- GP_4_18_FN, FN_IP13_9_7,
- GP_4_17_FN, FN_IP13_6_3,
- GP_4_16_FN, FN_IP13_2_0,
- GP_4_15_FN, FN_IP12_30_28,
- GP_4_14_FN, FN_IP12_27_25,
- GP_4_13_FN, FN_IP12_24_23,
- GP_4_12_FN, FN_IP12_22_20,
- GP_4_11_FN, FN_IP12_19_17,
- GP_4_10_FN, FN_IP12_16_14,
- GP_4_9_FN, FN_IP12_13_11,
- GP_4_8_FN, FN_IP12_10_8,
- GP_4_7_FN, FN_IP12_7_6,
- GP_4_6_FN, FN_IP12_5_4,
- GP_4_5_FN, FN_IP12_3_2,
- GP_4_4_FN, FN_IP12_1_0,
- GP_4_3_FN, FN_IP11_31_30,
- GP_4_2_FN, FN_IP11_29_27,
- GP_4_1_FN, FN_IP11_26_24,
- GP_4_0_FN, FN_IP11_23_22 }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- GP_5_31_FN, FN_IP7_24_22,
- GP_5_30_FN, FN_IP7_21_19,
- GP_5_29_FN, FN_IP7_18_16,
- GP_5_28_FN, FN_DU_DOTCLKIN2,
- GP_5_27_FN, FN_IP7_26_25,
- GP_5_26_FN, FN_DU_DOTCLKIN0,
- GP_5_25_FN, FN_AVS2,
- GP_5_24_FN, FN_AVS1,
- GP_5_23_FN, FN_USB2_OVC,
- GP_5_22_FN, FN_USB2_PWEN,
- GP_5_21_FN, FN_IP16_7,
- GP_5_20_FN, FN_IP16_6,
- GP_5_19_FN, FN_USB0_OVC_VBUS,
- GP_5_18_FN, FN_USB0_PWEN,
- GP_5_17_FN, FN_IP16_5_3,
- GP_5_16_FN, FN_IP16_2_0,
- GP_5_15_FN, FN_IP15_29_28,
- GP_5_14_FN, FN_IP15_27_26,
- GP_5_13_FN, FN_IP15_25_23,
- GP_5_12_FN, FN_IP15_22_20,
- GP_5_11_FN, FN_IP15_19_18,
- GP_5_10_FN, FN_IP15_17_16,
- GP_5_9_FN, FN_IP15_15_14,
- GP_5_8_FN, FN_IP15_13_12,
- GP_5_7_FN, FN_IP15_11_9,
- GP_5_6_FN, FN_IP15_8_6,
- GP_5_5_FN, FN_IP15_5_3,
- GP_5_4_FN, FN_IP15_2_0,
- GP_5_3_FN, FN_IP14_30_28,
- GP_5_2_FN, FN_IP14_27_25,
- GP_5_1_FN, FN_IP14_24_22,
- GP_5_0_FN, FN_IP14_21_19 }
- },
-
- /*IPSR0 - IPSR5*/
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
- /* IP6_31_29 [3] */
- FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
- FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
- /* IP6_28_26 [3] */
- FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
- FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
- /* IP6_25_23 [3] */
- FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
- FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
- /* IP6_22_20 [3] */
- FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
- FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
- /* IP6_19_17 [3] */
- FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
- FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
- /* IP6_16_14 [3] */
- FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
- FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
- FN_SCL2_CIS_E, 0,
- /* IP6_13_11 [3] */
- FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
- FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
- /* IP6_10_9 [2] */
- FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
- /* IP6_8_6 [3] */
- FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
- FN_SSI_SDATA8_C, 0, 0, 0,
- /* IP6_5_3 [3] */
- FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
- FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
- /* IP6_2_0 [3] */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
- /* IP7_31 [1] */
- 0, 0,
- /* IP7_30_29 [2] */
- FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
- FN_MII_RXD2,
- /* IP7_28_27 [2] */
- FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
- /* IP7_26_25 [2] */
- FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
- /* IP7_24_22 [3] */
- FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
- 0, 0, 0,
- /* IP7_21_19 [3] */
- FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
- FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
- /* IP7_18_16 [3] */
- FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
- FN_GLO_SS_C, 0, 0, 0,
- /* IP7_15_13 [3] */
- FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
- FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
- /* IP7_12_10 [3] */
- FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
- FN_GLO_SCLK_C, 0, 0, 0,
- /* IP7_9_8 [2] */
- FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
- /* IP7_7_6 [2] */
- FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
- /* IP7_5_3 [3] */
- FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
- 0, 0, 0,
- /* IP7_2_0 [3] */
- FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
- FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
- },
- /*IPSR8 - IPSR16*/
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- GP_1_29_IN, GP_1_29_OUT,
- GP_1_28_IN, GP_1_28_OUT,
- GP_1_27_IN, GP_1_27_OUT,
- GP_1_26_IN, GP_1_26_OUT,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
- 0, 0,
- 0, 0,
- GP_2_29_IN, GP_2_29_OUT,
- GP_2_28_IN, GP_2_28_OUT,
- GP_2_27_IN, GP_2_27_OUT,
- GP_2_26_IN, GP_2_26_OUT,
- GP_2_25_IN, GP_2_25_OUT,
- GP_2_24_IN, GP_2_24_OUT,
- GP_2_23_IN, GP_2_23_OUT,
- GP_2_22_IN, GP_2_22_OUT,
- GP_2_21_IN, GP_2_21_OUT,
- GP_2_20_IN, GP_2_20_OUT,
- GP_2_19_IN, GP_2_19_OUT,
- GP_2_18_IN, GP_2_18_OUT,
- GP_2_17_IN, GP_2_17_OUT,
- GP_2_16_IN, GP_2_16_OUT,
- GP_2_15_IN, GP_2_15_OUT,
- GP_2_14_IN, GP_2_14_OUT,
- GP_2_13_IN, GP_2_13_OUT,
- GP_2_12_IN, GP_2_12_OUT,
- GP_2_11_IN, GP_2_11_OUT,
- GP_2_10_IN, GP_2_10_OUT,
- GP_2_9_IN, GP_2_9_OUT,
- GP_2_8_IN, GP_2_8_OUT,
- GP_2_7_IN, GP_2_7_OUT,
- GP_2_6_IN, GP_2_6_OUT,
- GP_2_5_IN, GP_2_5_OUT,
- GP_2_4_IN, GP_2_4_OUT,
- GP_2_3_IN, GP_2_3_OUT,
- GP_2_2_IN, GP_2_2_OUT,
- GP_2_1_IN, GP_2_1_OUT,
- GP_2_0_IN, GP_2_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, GP_1_29_DATA, GP_1_28_DATA,
- GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
- 0, 0, GP_2_29_DATA, GP_2_28_DATA,
- GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
- GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
- GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
- GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
- GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
- GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
- GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
- },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
- { },
-};
-
-static struct pinmux_info r8a7790_pinmux_info = {
- .name = "r8a7790_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7790_pinmux_init(void)
-{
- register_pinmux(&r8a7790_pinmux_info);
-}
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
deleted file mode 100644
index a13317b..0000000
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __PFC_R8A7790_H__
-#define __PFC_R8A7790_H__
-
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT2(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx)
-
-#if defined(CONFIG_R8A7790)
-#define CPU_32_PORT1(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx) \
-/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT1(fn, pfx##_1_, sfx), \
- CPU_32_PORT2(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_32_PORT(fn, pfx##_5_, sfx)
-
-#elif defined(CONFIG_R8A7791)
-#define CPU_32_PORT1(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
-
-/*
- * GP_0_0_DATA -> GP_7_25_DATA
- * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
- * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
- */
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT1(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_32_PORT(fn, pfx##_5_, sfx), \
- CPU_32_PORT(fn, pfx##_6_, sfx), \
- CPU_32_PORT1(fn, pfx##_7_, sfx)
-#else
-#error "NO support"
-#endif
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-#endif /* __PFC_R8A7790_H__ */
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
deleted file mode 100644
index 46d6e60..0000000
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
+++ /dev/null
@@ -1,1117 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-#include "pfc-r8a7790.h"
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
- FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
- FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
- FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
- FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
- FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
-
- /* GPSR1 */
- FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
- FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
- FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
- FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
- FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
- FN_IP3_21_20,
-
- /* GPSR2 */
- FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
- FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
- FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
- FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
- FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
- FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
- FN_IP6_5_3, FN_IP6_7_6,
-
- /* GPSR3 */
- FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
- FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
- FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
- FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
- FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
- FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
- FN_IP9_18_17,
-
- /* GPSR4 */
- FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
- FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
- FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
- FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
- FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
- FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
- FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
- FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
-
- /* GPSR5 */
- FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
- FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
- FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
- FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
- FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
- FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
- FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
-
- /* GPSR6 */
- FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
- FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
- FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
- FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
- FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
- FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
-
- /* GPSR7 */
- FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
- FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
- FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
- FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
- FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
- FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
-
- /* IPSR0 - IPSR10 */
-
- /* IPSR11 */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
- FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
- FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
- FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
- FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
- FN_VI1_DATA7, FN_AVB_MDC,
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
-
- /* IPSR12 */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
-
- /* IPSR13 */
- /* MOD_SEL */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
- FN_SEL_HSCIF1_4,
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
-
- /* MOD_SEL2 */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- FN_SEL_SCIF0_4,
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-
- /* MOD_SEL3 */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
-
- /* MOD_SEL4 */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
- FN_SEL_SCIF2_4,
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
- FN_SEL_SOF2_4,
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- EX_CS0_N_MARK, RD_N_MARK,
-
- AUDIO_CLKA_MARK,
-
- VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
- VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
- VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
-
- /* IPSR0 IPSR10 */
- /* IPSR11 */
- VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
- VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
- VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
- SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
- VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
- TX4_B_MARK, SCIFA4_TXD_B_MARK,
- VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
- RX4_B_MARK, SCIFA4_RXD_B_MARK,
- VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
- VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
- VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
- VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
- VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
- VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
- VI1_DATA7_MARK, AVB_MDC_MARK,
- ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
- ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
-
- /* IPSR12 */
- ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
- ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
- ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
- SCL2_D_MARK, MSIOF1_RXD_E_MARK,
- ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
- SDA2_D_MARK, MSIOF1_SCK_E_MARK,
- ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
- CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
- ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
- CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
- ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
- ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
- ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
- ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
- STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
- ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
- STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
- ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
-
- /* IPSR13 */
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- /* OTHER IPSR0 - IPSR10 */
- /* IPSR11 */
- PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
- PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
- PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
- PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
- PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
- PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
- PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
- PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
- PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
- PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
- PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
- PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
- PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
-
- /* IPSR12 */
- PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
- PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
- PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
- PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
- PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
- PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
- PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
- PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
- PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
- PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
- PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
-
- /* IPSR13 - IPSR16 */
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- /* OTHER, IPSR0 - IPSR10 */
- /* IPSR11 */
- GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
- GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
- GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
- GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
- GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
- GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
- GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
- GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
- GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
- GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
- GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
- GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
- GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
- GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
- GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
- GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
- GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
- GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
- GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
- GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
- GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
- GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
- GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
-
- /* IPSR12 */
- GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
- GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
- GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
- GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
- GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
- GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
- GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
- GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
- GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
- GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
- GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
- GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
- GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
- GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
- GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
- GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
- GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
- GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
- GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
-
- /* IPSR13 - IPSR16 */
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP1_22_20,
- GP_0_30_FN, FN_IP1_19_17,
- GP_0_29_FN, FN_IP1_16_14,
- GP_0_28_FN, FN_IP1_13_11,
- GP_0_27_FN, FN_IP1_10_8,
- GP_0_26_FN, FN_IP1_7_6,
- GP_0_25_FN, FN_IP1_5_4,
- GP_0_24_FN, FN_IP1_3_2,
- GP_0_23_FN, FN_IP1_1_0,
- GP_0_22_FN, FN_IP0_30_29,
- GP_0_21_FN, FN_IP0_28_27,
- GP_0_20_FN, FN_IP0_26_25,
- GP_0_19_FN, FN_IP0_24_23,
- GP_0_18_FN, FN_IP0_22_21,
- GP_0_17_FN, FN_IP0_20_19,
- GP_0_16_FN, FN_IP0_18_16,
- GP_0_15_FN, FN_IP0_15,
- GP_0_14_FN, FN_IP0_14,
- GP_0_13_FN, FN_IP0_13,
- GP_0_12_FN, FN_IP0_12,
- GP_0_11_FN, FN_IP0_11,
- GP_0_10_FN, FN_IP0_10,
- GP_0_9_FN, FN_IP0_9,
- GP_0_8_FN, FN_IP0_8,
- GP_0_7_FN, FN_IP0_7,
- GP_0_6_FN, FN_IP0_6,
- GP_0_5_FN, FN_IP0_5,
- GP_0_4_FN, FN_IP0_4,
- GP_0_3_FN, FN_IP0_3,
- GP_0_2_FN, FN_IP0_2,
- GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0, }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_FN, FN_IP3_21_20,
- GP_1_24_FN, FN_IP3_19_18,
- GP_1_23_FN, FN_IP3_17_16,
- GP_1_22_FN, FN_IP3_15_14,
- GP_1_21_FN, FN_IP3_13_12,
- GP_1_20_FN, FN_IP3_11_9,
- GP_1_19_FN, FN_RD_N,
- GP_1_18_FN, FN_IP3_8_6,
- GP_1_17_FN, FN_IP3_5_3,
- GP_1_16_FN, FN_IP3_2_0,
- GP_1_15_FN, FN_IP2_29_27,
- GP_1_14_FN, FN_IP2_26_25,
- GP_1_13_FN, FN_IP2_24_23,
- GP_1_12_FN, FN_EX_CS0_N,
- GP_1_11_FN, FN_IP2_22_21,
- GP_1_10_FN, FN_IP2_20_19,
- GP_1_9_FN, FN_IP2_18_16,
- GP_1_8_FN, FN_IP2_15_13,
- GP_1_7_FN, FN_IP2_12_10,
- GP_1_6_FN, FN_IP2_9_7,
- GP_1_5_FN, FN_IP2_6_5,
- GP_1_4_FN, FN_IP2_4_3,
- GP_1_3_FN, FN_IP2_2_0,
- GP_1_2_FN, FN_IP1_31_29,
- GP_1_1_FN, FN_IP1_28_26,
- GP_1_0_FN, FN_IP1_25_23, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_IP6_7_6,
- GP_2_30_FN, FN_IP6_5_3,
- GP_2_29_FN, FN_IP6_2_0,
- GP_2_28_FN, FN_AUDIO_CLKA,
- GP_2_27_FN, FN_IP5_31_29,
- GP_2_26_FN, FN_IP5_28_26,
- GP_2_25_FN, FN_IP5_25_24,
- GP_2_24_FN, FN_IP5_23_22,
- GP_2_23_FN, FN_IP5_21_20,
- GP_2_22_FN, FN_IP5_19_17,
- GP_2_21_FN, FN_IP5_16_15,
- GP_2_20_FN, FN_IP5_14_12,
- GP_2_19_FN, FN_IP5_11_9,
- GP_2_18_FN, FN_IP5_8_6,
- GP_2_17_FN, FN_IP5_5_3,
- GP_2_16_FN, FN_IP5_2_0,
- GP_2_15_FN, FN_IP4_30_28,
- GP_2_14_FN, FN_IP4_27_26,
- GP_2_13_FN, FN_IP4_25_24,
- GP_2_12_FN, FN_IP4_23_22,
- GP_2_11_FN, FN_IP4_21,
- GP_2_10_FN, FN_IP4_20,
- GP_2_9_FN, FN_IP4_19,
- GP_2_8_FN, FN_IP4_18_16,
- GP_2_7_FN, FN_IP4_15_13,
- GP_2_6_FN, FN_IP4_12_10,
- GP_2_5_FN, FN_IP4_9_8,
- GP_2_4_FN, FN_IP4_7_5,
- GP_2_3_FN, FN_IP4_4_2,
- GP_2_2_FN, FN_IP4_1_0,
- GP_2_1_FN, FN_IP3_30_28,
- GP_2_0_FN, FN_IP3_27_25 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP9_18_17,
- GP_3_30_FN, FN_IP9_16,
- GP_3_29_FN, FN_IP9_15_13,
- GP_3_28_FN, FN_IP9_12,
- GP_3_27_FN, FN_IP9_11,
- GP_3_26_FN, FN_IP9_10_8,
- GP_3_25_FN, FN_IP9_7,
- GP_3_24_FN, FN_IP9_6,
- GP_3_23_FN, FN_IP9_5_3,
- GP_3_22_FN, FN_IP9_2_0,
- GP_3_21_FN, FN_IP8_30_28,
- GP_3_20_FN, FN_IP8_27_26,
- GP_3_19_FN, FN_IP8_25_24,
- GP_3_18_FN, FN_IP8_23_21,
- GP_3_17_FN, FN_IP8_20_18,
- GP_3_16_FN, FN_IP8_17_15,
- GP_3_15_FN, FN_IP8_14_12,
- GP_3_14_FN, FN_IP8_11_9,
- GP_3_13_FN, FN_IP8_8_6,
- GP_3_12_FN, FN_IP8_5_3,
- GP_3_11_FN, FN_IP8_2_0,
- GP_3_10_FN, FN_IP7_29_27,
- GP_3_9_FN, FN_IP7_26_24,
- GP_3_8_FN, FN_IP7_23_21,
- GP_3_7_FN, FN_IP7_20_19,
- GP_3_6_FN, FN_IP7_18_17,
- GP_3_5_FN, FN_IP7_16_15,
- GP_3_4_FN, FN_IP7_14_13,
- GP_3_3_FN, FN_IP7_12_11,
- GP_3_2_FN, FN_IP7_10_9,
- GP_3_1_FN, FN_IP7_8_6,
- GP_3_0_FN, FN_IP7_5_3 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP15_5_4,
- GP_4_30_FN, FN_IP15_3_2,
- GP_4_29_FN, FN_IP15_1_0,
- GP_4_28_FN, FN_IP11_8_6,
- GP_4_27_FN, FN_IP11_5_3,
- GP_4_26_FN, FN_IP11_2_0,
- GP_4_25_FN, FN_IP10_31_29,
- GP_4_24_FN, FN_IP10_28_27,
- GP_4_23_FN, FN_IP10_26_25,
- GP_4_22_FN, FN_IP10_24_22,
- GP_4_21_FN, FN_IP10_21_19,
- GP_4_20_FN, FN_IP10_18_17,
- GP_4_19_FN, FN_IP10_16_15,
- GP_4_18_FN, FN_IP10_14_12,
- GP_4_17_FN, FN_IP10_11_9,
- GP_4_16_FN, FN_IP10_8_6,
- GP_4_15_FN, FN_IP10_5_3,
- GP_4_14_FN, FN_IP10_2_0,
- GP_4_13_FN, FN_IP9_31_29,
- GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
- GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
- GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
- GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
- GP_4_8_FN, FN_IP9_28_27,
- GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
- GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
- GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
- GP_4_4_FN, FN_IP9_26_25,
- GP_4_3_FN, FN_IP9_24_23,
- GP_4_2_FN, FN_IP9_22_21,
- GP_4_1_FN, FN_IP9_20_19,
- GP_4_0_FN, FN_VI0_CLK }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- GP_5_31_FN, FN_IP3_24_22,
- GP_5_30_FN, FN_IP13_9_7,
- GP_5_29_FN, FN_IP13_6_5,
- GP_5_28_FN, FN_IP13_4_3,
- GP_5_27_FN, FN_IP13_2_0,
- GP_5_26_FN, FN_IP12_29_27,
- GP_5_25_FN, FN_IP12_26_24,
- GP_5_24_FN, FN_IP12_23_22,
- GP_5_23_FN, FN_IP12_21_20,
- GP_5_22_FN, FN_IP12_19_18,
- GP_5_21_FN, FN_IP12_17_16,
- GP_5_20_FN, FN_IP12_15_13,
- GP_5_19_FN, FN_IP12_12_10,
- GP_5_18_FN, FN_IP12_9_7,
- GP_5_17_FN, FN_IP12_6_4,
- GP_5_16_FN, FN_IP12_3_2,
- GP_5_15_FN, FN_IP12_1_0,
- GP_5_14_FN, FN_IP11_31_30,
- GP_5_13_FN, FN_IP11_29_28,
- GP_5_12_FN, FN_IP11_27,
- GP_5_11_FN, FN_IP11_26,
- GP_5_10_FN, FN_IP11_25,
- GP_5_9_FN, FN_IP11_24,
- GP_5_8_FN, FN_IP11_23,
- GP_5_7_FN, FN_IP11_22,
- GP_5_6_FN, FN_IP11_21,
- GP_5_5_FN, FN_IP11_20,
- GP_5_4_FN, FN_IP11_19,
- GP_5_3_FN, FN_IP11_18_17,
- GP_5_2_FN, FN_IP11_16_15,
- GP_5_1_FN, FN_IP11_14_12,
- GP_5_0_FN, FN_IP11_11_9 }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- GP_6_29_FN, FN_IP14_31_29,
- GP_6_28_FN, FN_IP14_28_26,
- GP_6_27_FN, FN_IP14_25_23,
- GP_6_26_FN, FN_IP14_22_20,
- GP_6_25_FN, FN_IP14_19_17,
- GP_6_24_FN, FN_IP14_16_14,
- GP_6_23_FN, FN_IP14_13_11,
- GP_6_22_FN, FN_IP14_10_8,
- GP_6_21_FN, FN_IP14_7,
- GP_6_20_FN, FN_IP14_6,
- GP_6_19_FN, FN_IP14_5,
- GP_6_18_FN, FN_IP14_4,
- GP_6_17_FN, FN_IP14_3,
- GP_6_16_FN, FN_IP14_2,
- GP_6_15_FN, FN_IP14_1_0,
- GP_6_14_FN, FN_IP13_30_28,
- GP_6_13_FN, FN_IP13_27,
- GP_6_12_FN, FN_IP13_26,
- GP_6_11_FN, FN_IP13_25,
- GP_6_10_FN, FN_IP13_24_23,
- GP_6_9_FN, FN_IP13_22,
- 0, 0,
- GP_6_7_FN, FN_IP13_21_19,
- GP_6_6_FN, FN_IP13_18_16,
- GP_6_5_FN, FN_IP13_15,
- GP_6_4_FN, FN_IP13_14,
- GP_6_3_FN, FN_IP13_13,
- GP_6_2_FN, FN_IP13_12,
- GP_6_1_FN, FN_IP13_11,
- GP_6_0_FN, FN_IP13_10 }
- },
- { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_FN, FN_USB1_PWEN,
- GP_7_24_FN, FN_USB0_OVC,
- GP_7_23_FN, FN_USB0_PWEN,
- GP_7_22_FN, FN_IP15_14_12,
- GP_7_21_FN, FN_IP15_11_9,
- GP_7_20_FN, FN_IP15_8_6,
- GP_7_19_FN, FN_IP7_2_0,
- GP_7_18_FN, FN_IP6_29_27,
- GP_7_17_FN, FN_IP6_26_24,
- GP_7_16_FN, FN_IP6_23_21,
- GP_7_15_FN, FN_IP6_20_19,
- GP_7_14_FN, FN_IP6_18_16,
- GP_7_13_FN, FN_IP6_15_14,
- GP_7_12_FN, FN_IP6_13_12,
- GP_7_11_FN, FN_IP6_11_10,
- GP_7_10_FN, FN_IP6_9_8,
- GP_7_9_FN, FN_IP16_11_10,
- GP_7_8_FN, FN_IP16_9_8,
- GP_7_7_FN, FN_IP16_7_6,
- GP_7_6_FN, FN_IP16_5_3,
- GP_7_5_FN, FN_IP16_2_0,
- GP_7_4_FN, FN_IP15_29_27,
- GP_7_3_FN, FN_IP15_26_24,
- GP_7_2_FN, FN_IP15_23_21,
- GP_7_1_FN, FN_IP15_20_18,
- GP_7_0_FN, FN_IP15_17_15 }
- },
- /* IPSR0 - IPSR10 */
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 3, 3, 3, 3, 3) {
- /* IP11_31_30 [2] */
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
- /* IP11_29_28 [2] */
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
- /* IP11_27 [1] */
- FN_VI1_DATA7, FN_AVB_MDC,
- /* IP11_26 [1] */
- FN_VI1_DATA6, FN_AVB_MAGIC,
- /* IP11_25 [1] */
- FN_VI1_DATA5, FN_AVB_RX_DV,
- /* IP11_24 [1] */
- FN_VI1_DATA4, FN_AVB_MDIO,
- /* IP11_23 [1] */
- FN_VI1_DATA3, FN_AVB_RX_ER,
- /* IP11_22 [1] */
- FN_VI1_DATA2, FN_AVB_RXD7,
- /* IP11_21 [1] */
- FN_VI1_DATA1, FN_AVB_RXD6,
- /* IP11_20 [1] */
- FN_VI1_DATA0, FN_AVB_RXD5,
- /* IP11_19 [1] */
- FN_VI1_CLK, FN_AVB_RXD4,
- /* IP11_18_17 [2] */
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
- /* IP11_16_15 [2] */
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
- /* IP11_14_12 [3] */
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
- FN_RX4_B, FN_SCIFA4_RXD_B,
- 0, 0, 0,
- /* IP11_11_9 [3] */
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
- FN_TX4_B, FN_SCIFA4_TXD_B,
- 0, 0, 0,
- /* IP11_8_6 [3] */
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
- /* IP11_5_3 [3] */
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- 0, 0, 0,
- /* IP11_2_0 [3] */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
- /* IP12_31_30 [2] */
- 0, 0, 0, 0,
- /* IP12_29_27 [3] */
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
- 0, 0, 0,
- /* IP12_26_24 [3] */
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- 0, 0, 0,
- /* IP12_23_22 [2] */
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
- /* IP12_21_20 [2] */
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
- /* IP12_19_18 [2] */
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
- /* IP12_17_16 [2] */
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- /* IP12_15_13 [3] */
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- 0, 0, 0,
- /* IP12_12_10 [3] */
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- 0, 0, 0,
- /* IP12_9_7 [3] */
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
- FN_SDA2_D, FN_MSIOF1_SCK_E,
- 0, 0, 0,
- /* IP12_6_4 [3] */
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- 0, 0, 0,
- /* IP12_3_2 [2] */
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- /* IP12_1_0 [2] */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
- },
-
- /* IPSR13 - IPSR16 */
-
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
- 3, 2, 2, 2, 1, 2, 2, 2) {
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF1 [2] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- /* SEL_SCIFB [2] */
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- /* SEL_SCIFB2 [2] */
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
- FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- /* SEL_SCIFB1 [3] */
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
- FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- 0, 0, 0, 0,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* SEL_SCFA [1] */
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- /* SEL_QSP [1] */
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- /* SEL_SSI7 [1] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- /* SEL_HSCIF1 [3] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
- FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_VI1 [2] */
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_TMU [1] */
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- /* SEL_LBS [2] */
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_SOF0 [2] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 3, 2, 1, 1, 2, 2,
- 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
- /* SEL_SCIF0 [3] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
- FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF [1] */
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- /* SEL_CAN0 [3] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- 0, 0,
- /* SEL_CAN1 [2] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIFA2 [1] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- /* SEL_SCIF4 [2] */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_ADG [1] */
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- /* SEL_FM [3] */
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
- FN_SEL_FM_3, FN_SEL_FM_4,
- 0, 0, 0,
- /* SEL_SCIFA5 [2] */
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_GPS [2] */
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- /* SEL_SCIFA4 [2] */
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
- /* SEL_SCIFA3 [2] */
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
- /* SEL_SIM [1] */
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 2, 2, 3, 2, 2, 2, 1) {
- /* SEL_HSCIF2 [2] */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- /* SEL_CANCLK [2] */
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- /* SEL_IIC8 [2] */
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
- /* SEL_IIC7 [2] */
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
- /* SEL_IIC4 [2] */
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
- /* SEL_IIC3 [2] */
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- /* SEL_SCIF3 [2] */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* SEL_MMC [1] */
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- /* SEL_SCIF5 [1] */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_IIC2 [2] */
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- /* SEL_IIC1 [3] */
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- 0, 0, 0,
- /* SEL_IIC0 [2] */
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [1] */
- 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- 3, 2, 2, 1, 1, 1, 1, 3, 2,
- 2, 3, 1, 1, 1, 2, 2, 2, 2) {
- /* SEL_SOF1 [3] */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- 0, 0, 0,
- /* SEL_HSCIF0 [2] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
- /* SEL_DIS [2] */
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_RAD [1] */
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- /* SEL_SCIF2 [3] */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
- FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_SOF2 [3] */
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
- FN_SEL_SOF2_3, FN_SEL_SOF2_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI1 [1] */
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- /* SEL_SSI0 [1] */
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- /* SEL_SSP [2] */
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_IN, GP_7_25_OUT,
- GP_7_24_IN, GP_7_24_OUT,
- GP_7_23_IN, GP_7_23_OUT,
- GP_7_22_IN, GP_7_22_OUT,
- GP_7_21_IN, GP_7_21_OUT,
- GP_7_20_IN, GP_7_20_OUT,
- GP_7_19_IN, GP_7_19_OUT,
- GP_7_18_IN, GP_7_18_OUT,
- GP_7_17_IN, GP_7_17_OUT,
- GP_7_16_IN, GP_7_16_OUT,
- GP_7_15_IN, GP_7_15_OUT,
- GP_7_14_IN, GP_7_14_OUT,
- GP_7_13_IN, GP_7_13_OUT,
- GP_7_12_IN, GP_7_12_OUT,
- GP_7_11_IN, GP_7_11_OUT,
- GP_7_10_IN, GP_7_10_OUT,
- GP_7_9_IN, GP_7_9_OUT,
- GP_7_8_IN, GP_7_8_OUT,
- GP_7_7_IN, GP_7_7_OUT,
- GP_7_6_IN, GP_7_6_OUT,
- GP_7_5_IN, GP_7_5_OUT,
- GP_7_4_IN, GP_7_4_OUT,
- GP_7_3_IN, GP_7_3_OUT,
- GP_7_2_IN, GP_7_2_OUT,
- GP_7_1_IN, GP_7_1_OUT,
- GP_7_0_IN, GP_7_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
- { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_7_25_DATA, GP_7_24_DATA,
- GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
- GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
- GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
- GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
- GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7791_pinmux_info = {
- .name = "r8a7791_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7791_pinmux_init(void)
-{
- register_pinmux(&r8a7791_pinmux_info);
-}
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c
deleted file mode 100644
index 03c27ad..0000000
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c
+++ /dev/null
@@ -1,1926 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT1(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
-
-/*
- * GP_0_0_DATA -> GP_7_25_DATA
- * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
- * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
- */
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT1(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_32_PORT(fn, pfx##_5_, sfx), \
- CPU_32_PORT(fn, pfx##_6_, sfx), \
- CPU_32_PORT1(fn, pfx##_7_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
- FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
- FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
- FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
- FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
- FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
-
- /* GPSR1 */
- FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
- FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
- FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
- FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
- FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
- FN_IP3_21_20,
-
- /* GPSR2 */
- FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
- FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
- FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
- FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
- FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
- FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
- FN_IP6_5_3, FN_IP6_7_6,
-
- /* GPSR3 */
- FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
- FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
- FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
- FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
- FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
- FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
- FN_IP9_18_17,
-
- /* GPSR4 */
- FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
- FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
- FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
- FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
- FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
- FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
- FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
- FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
-
- /* GPSR5 */
- FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
- FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
- FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
- FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
- FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
- FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
- FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
-
- /* GPSR6 */
- FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
- FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
- FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
- FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
- FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
- FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
-
- /* GPSR7 */
- FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
- FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
- FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
- FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
- FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
- FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
-
- /* IPSR 0 -5 */
-
- /* IPSR6 */
- FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
- FN_SCIF_CLK, FN_BPFCLK_E,
- FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
- FN_SCIFA2_RXD, FN_FMIN_E,
- FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
- FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
- FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
- FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
- FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
- FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
- FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
- FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
- FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
- FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
-
- /* IPSR7 - IPSR10 */
-
- /* IPSR11 */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
- FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
- FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
- FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
- FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
- FN_VI1_DATA7, FN_AVB_MDC,
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
-
- /* IPSR12 */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
-
- /* IPSR13 */
- FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
- FN_ADICLK_B, FN_MSIOF0_SS1_C,
- FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
- FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
- FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
- FN_ADICHS2_B, FN_MSIOF0_TXD_C,
- FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
- FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
- FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
- FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
- FN_SCIFA5_TXD_B, FN_TX3_C,
- FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
- FN_SCIFA5_RXD_B, FN_RX3_C,
- FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
- FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
- FN_SD1_DATA3, FN_IERX_B,
- FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
-
- /* IPSR14 */
- FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
- FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
- FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
- FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
- FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
- FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
- FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
- FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
- FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
- FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
- FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
- FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
- FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
- FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
-
- /* IPSR15 */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
- FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
- FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
- FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
- FN_PWM5_B, FN_SCIFA3_TXD_C,
- FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
- FN_VI1_G6_B, FN_SCIFA3_RXD_C,
- FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
- FN_VI1_G7_B, FN_SCIFA3_SCK_C,
- FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
- FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
- FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
- FN_TCLK2, FN_VI1_DATA3_C,
- FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
- FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
-
- /* IPSR16 */
- FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
- FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
- FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
- FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
-
- /* MOD_SEL */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
- FN_SEL_HSCIF1_4,
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
-
- /* MOD_SEL2 */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- FN_SEL_SCIF0_4,
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-
- /* MOD_SEL3 */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
-
- /* MOD_SEL4 */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
- FN_SEL_SCIF2_4,
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
- FN_SEL_SOF2_4,
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- EX_CS0_N_MARK, RD_N_MARK,
-
- AUDIO_CLKA_MARK,
-
- VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
- VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
- VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
-
- /* IPSR0 - 5 */
-
- /* IPSR6 */
- AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
- SCIF_CLK_MARK, BPFCLK_E_MARK,
- AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
- SCIFA2_RXD_MARK, FMIN_E_MARK,
- AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
- IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
- IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
- IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
- IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
- IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
- MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
- IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
- IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
- SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
- IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
- GPS_CLK_C_MARK, GPS_CLK_D_MARK,
- IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
- GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
-
- /* IPSR7 - 10 */
-
- /* IPSR11 */
- VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
- VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
- VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
- SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
- VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
- TX4_B_MARK, SCIFA4_TXD_B_MARK,
- VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
- RX4_B_MARK, SCIFA4_RXD_B_MARK,
- VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
- VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
- VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
- VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
- VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
- VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
- VI1_DATA7_MARK, AVB_MDC_MARK,
- ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
- ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
-
- /* IPSR12 */
- ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
- ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
- ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
- SCL2_D_MARK, MSIOF1_RXD_E_MARK,
- ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
- SDA2_D_MARK, MSIOF1_SCK_E_MARK,
- ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
- CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
- ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
- CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
- ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
- ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
- ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
- ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
- STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
- ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
- STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
- ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
-
- /* IPSR13 */
- STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
- ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
- STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
- STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
- STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
- ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
- SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
- SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
- SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
- SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
- SCIFA5_TXD_B_MARK, TX3_C_MARK,
- SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
- SCIFA5_RXD_B_MARK, RX3_C_MARK,
- SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
- SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
- SD1_DATA3_MARK, IERX_B_MARK,
- SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
-
- /* IPSR14 */
- SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
- SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
- SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
- SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
- SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
- SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
- MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
- VI1_CLK_C_MARK, VI1_G0_B_MARK,
- MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
- VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
- MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
- MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
- MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
- VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
- MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
- VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
-
- /* IPSR15 */
- SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
- SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
- SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
- GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
- PWM5_B_MARK, SCIFA3_TXD_C_MARK,
- GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
- VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
- GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
- VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
- HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
- TCLK1_MARK, VI1_DATA1_C_MARK,
- HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
- HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
- TCLK2_MARK, VI1_DATA3_C_MARK,
- HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
- CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
- HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
- CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
-
- /* IPSR16 */
- HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
- GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
- HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
- GLO_SS_C_MARK, VI1_DATA7_C_MARK,
- HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
- HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
- HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
- PINMUX_DATA(RD_N_MARK, FN_RD_N),
- PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
- PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
- PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
- PINMUX_DATA(VI0_DATA0_VI0_B1_MARK, FN_VI0_DATA0_VI0_B1),
- PINMUX_DATA(VI0_DATA0_VI0_B2_MARK, FN_VI0_DATA0_VI0_B2),
- PINMUX_DATA(VI0_DATA0_VI0_B4_MARK, FN_VI0_DATA0_VI0_B4),
- PINMUX_DATA(VI0_DATA0_VI0_B5_MARK, FN_VI0_DATA0_VI0_B5),
- PINMUX_DATA(VI0_DATA0_VI0_B6_MARK, FN_VI0_DATA0_VI0_B6),
- PINMUX_DATA(VI0_DATA0_VI0_B7_MARK, FN_VI0_DATA0_VI0_B7),
- PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
- PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
- PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
-
- /* IPSR0 - 5 */
-
- /* IPSR6 */
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
- PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
- PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
- PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
- PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
- PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
- PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
- PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
- PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
- PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
- PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
- PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
- PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
- PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
-
- /* IPSR7 - 10 */
-
- /* IPSR11 */
- PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
- PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
- PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
- PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
- PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
- PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
- PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
- PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
- PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
- PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
- PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
- PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
- PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
-
- /* IPSR12 */
- PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
- PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
- PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
- PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
- PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
- PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
- PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
- PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
- PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
- PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
- PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
-
- /* IPSR13 */
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
- PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
- PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
- PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
- PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
- PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
- PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
- PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
- PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
- PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
- PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
- PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
- PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
- PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
- PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
- PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
- PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
- PINMUX_IPSR_DATA(IP13_30_28, PWM0),
- PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
- PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
-
- /* IPSR14 */
- PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
- PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
- PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
- PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
- PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
- PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
- PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
- PINMUX_IPSR_DATA(IP14_4, MMC_D0),
- PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
- PINMUX_IPSR_DATA(IP14_5, MMC_D1),
- PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
- PINMUX_IPSR_DATA(IP14_6, MMC_D2),
- PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
- PINMUX_IPSR_DATA(IP14_7, MMC_D3),
- PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
- PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
- PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
- PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
- PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
- PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
- PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
- PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
- PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
-
- /* IPSR15 */
- PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
- PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
- PINMUX_IPSR_DATA(IP15_11_9, PWM5),
- PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
- PINMUX_IPSR_DATA(IP15_14_12, PWM6),
- PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
- PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
-
- /* IPSR16 */
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
- PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
- PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
- PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
- PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
- PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
- PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- GPIO_FN(EX_CS0_N), GPIO_FN(RD_N), GPIO_FN(AUDIO_CLKA),
- GPIO_FN(VI0_CLK), GPIO_FN(VI0_DATA0_VI0_B0),
- GPIO_FN(VI0_DATA0_VI0_B1), GPIO_FN(VI0_DATA0_VI0_B2),
- GPIO_FN(VI0_DATA0_VI0_B4), GPIO_FN(VI0_DATA0_VI0_B5),
- GPIO_FN(VI0_DATA0_VI0_B6), GPIO_FN(VI0_DATA0_VI0_B7),
- GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
-
- /* IPSR0 - 5 */
-
- /* IPSR6 */
- GPIO_FN(AUDIO_CLKB), GPIO_FN(STP_OPWM_0_B), GPIO_FN(MSIOF1_SCK_B),
- GPIO_FN(SCIF_CLK), GPIO_FN(BPFCLK_E),
- GPIO_FN(AUDIO_CLKC), GPIO_FN(SCIFB0_SCK_C),
- GPIO_FN(MSIOF1_SYNC_B), GPIO_FN(RX2),
- GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN_E),
- GPIO_FN(AUDIO_CLKOUT), GPIO_FN(MSIOF1_SS1_B),
- GPIO_FN(TX2), GPIO_FN(SCIFA2_TXD),
- GPIO_FN(IRQ0), GPIO_FN(SCIFB1_RXD_D), GPIO_FN(INTC_IRQ0_N),
- GPIO_FN(IRQ1), GPIO_FN(SCIFB1_SCK_C), GPIO_FN(INTC_IRQ1_N),
- GPIO_FN(IRQ2), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(INTC_IRQ2_N),
- GPIO_FN(IRQ3), GPIO_FN(SCL4_C),
- GPIO_FN(MSIOF2_TXD_E), GPIO_FN(INTC_IRQ3_N),
- GPIO_FN(IRQ4), GPIO_FN(HRX1_C), GPIO_FN(SDA4_C),
- GPIO_FN(MSIOF2_RXD_E), GPIO_FN(INTC_IRQ4_N),
- GPIO_FN(IRQ5), GPIO_FN(HTX1_C), GPIO_FN(SCL1_E), GPIO_FN(MSIOF2_SCK_E),
- GPIO_FN(IRQ6), GPIO_FN(HSCK1_C), GPIO_FN(MSIOF1_SS2_B),
- GPIO_FN(SDA1_E), GPIO_FN(MSIOF2_SYNC_E),
- GPIO_FN(IRQ7), GPIO_FN(HCTS1_N_C), GPIO_FN(MSIOF1_TXD_B),
- GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D),
- GPIO_FN(IRQ8), GPIO_FN(HRTS1_N_C), GPIO_FN(MSIOF1_RXD_B),
- GPIO_FN(GPS_SIGN_C), GPIO_FN(GPS_SIGN_D),
-
- /* IPSR7 - 10 */
-
- /* IPSR11 */
- GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
- GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
- GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
- GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
- GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
- GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
- GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
- GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
- GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
- GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
- GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
- GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
- GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
- GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
- GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
- GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
- GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
- GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
- GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
- GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
- GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
- GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
- GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
-
- /* IPSR12 */
- GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
- GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
- GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
- GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
- GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
- GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
- GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
- GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
- GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
- GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
- GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
- GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
- GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
- GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
- GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
- GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
- GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
- GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
- GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
-
- /* IPSR13 */
- GPIO_FN(STP_ISD_0), GPIO_FN(AVB_TX_ER), GPIO_FN(SCIFB2_SCK_C),
- GPIO_FN(ADICLK_B), GPIO_FN(MSIOF0_SS1_C),
- GPIO_FN(STP_ISEN_0), GPIO_FN(AVB_TX_CLK),
- GPIO_FN(ADICHS0_B), GPIO_FN(MSIOF0_SS2_C),
- GPIO_FN(STP_ISSYNC_0), GPIO_FN(AVB_COL),
- GPIO_FN(ADICHS1_B), GPIO_FN(MSIOF0_RXD_C),
- GPIO_FN(STP_OPWM_0), GPIO_FN(AVB_GTX_CLK), GPIO_FN(PWM0_B),
- GPIO_FN(ADICHS2_B), GPIO_FN(MSIOF0_TXD_C),
- GPIO_FN(SD0_CLK), GPIO_FN(SPCLK_B),
- GPIO_FN(SD0_CMD), GPIO_FN(MOSI_IO0_B),
- GPIO_FN(SD0_DATA0), GPIO_FN(MISO_IO1_B),
- GPIO_FN(SD0_DATA1), GPIO_FN(IO2_B),
- GPIO_FN(SD0_DATA2), GPIO_FN(IO3_B), GPIO_FN(SD0_DATA3), GPIO_FN(SSL_B),
- GPIO_FN(SD0_CD), GPIO_FN(MMC_D6_B),
- GPIO_FN(SIM0_RST_B), GPIO_FN(CAN0_RX_F),
- GPIO_FN(SCIFA5_TXD_B), GPIO_FN(TX3_C),
- GPIO_FN(SD0_WP), GPIO_FN(MMC_D7_B),
- GPIO_FN(SIM0_D_B), GPIO_FN(CAN0_TX_F),
- GPIO_FN(SCIFA5_RXD_B), GPIO_FN(RX3_C),
- GPIO_FN(SD1_CMD), GPIO_FN(REMOCON_B),
- GPIO_FN(SD1_DATA0), GPIO_FN(SPEEDIN_B),
- GPIO_FN(SD1_DATA1), GPIO_FN(IETX_B),
- GPIO_FN(SD1_DATA2), GPIO_FN(IECLK_B),
- GPIO_FN(SD1_DATA3), GPIO_FN(IERX_B),
- GPIO_FN(SD1_CD), GPIO_FN(PWM0), GPIO_FN(TPU_TO0), GPIO_FN(SCL1_C),
-
- /* IPSR14 */
- GPIO_FN(SD1_WP), GPIO_FN(PWM1_B), GPIO_FN(SDA1_C),
- GPIO_FN(SD2_CLK), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CMD), GPIO_FN(MMC_CMD),
- GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D0),
- GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D1),
- GPIO_FN(SD2_DATA2), GPIO_FN(MMC_D2),
- GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D3),
- GPIO_FN(SD2_CD), GPIO_FN(MMC_D4), GPIO_FN(SCL8_C),
- GPIO_FN(TX5_B), GPIO_FN(SCIFA5_TXD_C),
- GPIO_FN(SD2_WP), GPIO_FN(MMC_D5), GPIO_FN(SDA8_C),
- GPIO_FN(RX5_B), GPIO_FN(SCIFA5_RXD_C),
- GPIO_FN(MSIOF0_SCK), GPIO_FN(RX2_C), GPIO_FN(ADIDATA),
- GPIO_FN(VI1_CLK_C), GPIO_FN(VI1_G0_B),
- GPIO_FN(MSIOF0_SYNC), GPIO_FN(TX2_C), GPIO_FN(ADICS_SAMP),
- GPIO_FN(VI1_CLKENB_C), GPIO_FN(VI1_G1_B),
- GPIO_FN(MSIOF0_TXD), GPIO_FN(ADICLK),
- GPIO_FN(VI1_FIELD_C), GPIO_FN(VI1_G2_B),
- GPIO_FN(MSIOF0_RXD), GPIO_FN(ADICHS0),
- GPIO_FN(VI1_DATA0_C), GPIO_FN(VI1_G3_B),
- GPIO_FN(MSIOF0_SS1), GPIO_FN(MMC_D6), GPIO_FN(ADICHS1), GPIO_FN(TX0_E),
- GPIO_FN(VI1_HSYNC_N_C), GPIO_FN(SCL7_C), GPIO_FN(VI1_G4_B),
- GPIO_FN(MSIOF0_SS2), GPIO_FN(MMC_D7), GPIO_FN(ADICHS2), GPIO_FN(RX0_E),
- GPIO_FN(VI1_VSYNC_N_C), GPIO_FN(SDA7_C), GPIO_FN(VI1_G5_B),
-
- /* IPSR15 */
- GPIO_FN(SIM0_RST), GPIO_FN(IETX), GPIO_FN(CAN1_TX_D),
- GPIO_FN(SIM0_CLK), GPIO_FN(IECLK), GPIO_FN(CAN_CLK_C),
- GPIO_FN(SIM0_D), GPIO_FN(IERX), GPIO_FN(CAN1_RX_D),
- GPIO_FN(GPS_CLK), GPIO_FN(DU1_DOTCLKIN_C), GPIO_FN(AUDIO_CLKB_B),
- GPIO_FN(PWM5_B), GPIO_FN(SCIFA3_TXD_C),
- GPIO_FN(GPS_SIGN), GPIO_FN(TX4_C),
- GPIO_FN(SCIFA4_TXD_C), GPIO_FN(PWM5),
- GPIO_FN(VI1_G6_B), GPIO_FN(SCIFA3_RXD_C),
- GPIO_FN(GPS_MAG), GPIO_FN(RX4_C), GPIO_FN(SCIFA4_RXD_C), GPIO_FN(PWM6),
- GPIO_FN(VI1_G7_B), GPIO_FN(SCIFA3_SCK_C),
- GPIO_FN(HCTS0_N), GPIO_FN(SCIFB0_CTS_N), GPIO_FN(GLO_I0_C),
- GPIO_FN(TCLK1), GPIO_FN(VI1_DATA1_C),
- GPIO_FN(HRTS0_N), GPIO_FN(SCIFB0_RTS_N),
- GPIO_FN(GLO_I1_C), GPIO_FN(VI1_DATA2_C),
- GPIO_FN(HSCK0), GPIO_FN(SCIFB0_SCK),
- GPIO_FN(GLO_Q0_C), GPIO_FN(CAN_CLK),
- GPIO_FN(TCLK2), GPIO_FN(VI1_DATA3_C),
- GPIO_FN(HRX0), GPIO_FN(SCIFB0_RXD), GPIO_FN(GLO_Q1_C),
- GPIO_FN(CAN0_RX_B), GPIO_FN(VI1_DATA4_C),
- GPIO_FN(HTX0), GPIO_FN(SCIFB0_TXD), GPIO_FN(GLO_SCLK_C),
- GPIO_FN(CAN0_TX_B), GPIO_FN(VI1_DATA5_C),
-
- /* IPSR16 */
- GPIO_FN(HRX1), GPIO_FN(SCIFB1_RXD), GPIO_FN(VI1_R0_B),
- GPIO_FN(GLO_SDATA_C), GPIO_FN(VI1_DATA6_C),
- GPIO_FN(HTX1), GPIO_FN(SCIFB1_TXD), GPIO_FN(VI1_R1_B),
- GPIO_FN(GLO_SS_C), GPIO_FN(VI1_DATA7_C),
- GPIO_FN(HSCK1), GPIO_FN(SCIFB1_SCK),
- GPIO_FN(MLB_CK), GPIO_FN(GLO_RFON_C),
- GPIO_FN(HCTS1_N), GPIO_FN(SCIFB1_CTS_N),
- GPIO_FN(MLB_SIG), GPIO_FN(CAN1_TX_B),
- GPIO_FN(HRTS1_N), GPIO_FN(SCIFB1_RTS_N),
- GPIO_FN(MLB_DAT), GPIO_FN(CAN1_RX_B),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP1_22_20,
- GP_0_30_FN, FN_IP1_19_17,
- GP_0_29_FN, FN_IP1_16_14,
- GP_0_28_FN, FN_IP1_13_11,
- GP_0_27_FN, FN_IP1_10_8,
- GP_0_26_FN, FN_IP1_7_6,
- GP_0_25_FN, FN_IP1_5_4,
- GP_0_24_FN, FN_IP1_3_2,
- GP_0_23_FN, FN_IP1_1_0,
- GP_0_22_FN, FN_IP0_30_29,
- GP_0_21_FN, FN_IP0_28_27,
- GP_0_20_FN, FN_IP0_26_25,
- GP_0_19_FN, FN_IP0_24_23,
- GP_0_18_FN, FN_IP0_22_21,
- GP_0_17_FN, FN_IP0_20_19,
- GP_0_16_FN, FN_IP0_18_16,
- GP_0_15_FN, FN_IP0_15,
- GP_0_14_FN, FN_IP0_14,
- GP_0_13_FN, FN_IP0_13,
- GP_0_12_FN, FN_IP0_12,
- GP_0_11_FN, FN_IP0_11,
- GP_0_10_FN, FN_IP0_10,
- GP_0_9_FN, FN_IP0_9,
- GP_0_8_FN, FN_IP0_8,
- GP_0_7_FN, FN_IP0_7,
- GP_0_6_FN, FN_IP0_6,
- GP_0_5_FN, FN_IP0_5,
- GP_0_4_FN, FN_IP0_4,
- GP_0_3_FN, FN_IP0_3,
- GP_0_2_FN, FN_IP0_2,
- GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0, }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_FN, FN_IP3_21_20,
- GP_1_24_FN, FN_IP3_19_18,
- GP_1_23_FN, FN_IP3_17_16,
- GP_1_22_FN, FN_IP3_15_14,
- GP_1_21_FN, FN_IP3_13_12,
- GP_1_20_FN, FN_IP3_11_9,
- GP_1_19_FN, FN_RD_N,
- GP_1_18_FN, FN_IP3_8_6,
- GP_1_17_FN, FN_IP3_5_3,
- GP_1_16_FN, FN_IP3_2_0,
- GP_1_15_FN, FN_IP2_29_27,
- GP_1_14_FN, FN_IP2_26_25,
- GP_1_13_FN, FN_IP2_24_23,
- GP_1_12_FN, FN_EX_CS0_N,
- GP_1_11_FN, FN_IP2_22_21,
- GP_1_10_FN, FN_IP2_20_19,
- GP_1_9_FN, FN_IP2_18_16,
- GP_1_8_FN, FN_IP2_15_13,
- GP_1_7_FN, FN_IP2_12_10,
- GP_1_6_FN, FN_IP2_9_7,
- GP_1_5_FN, FN_IP2_6_5,
- GP_1_4_FN, FN_IP2_4_3,
- GP_1_3_FN, FN_IP2_2_0,
- GP_1_2_FN, FN_IP1_31_29,
- GP_1_1_FN, FN_IP1_28_26,
- GP_1_0_FN, FN_IP1_25_23, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_IP6_7_6,
- GP_2_30_FN, FN_IP6_5_3,
- GP_2_29_FN, FN_IP6_2_0,
- GP_2_28_FN, FN_AUDIO_CLKA,
- GP_2_27_FN, FN_IP5_31_29,
- GP_2_26_FN, FN_IP5_28_26,
- GP_2_25_FN, FN_IP5_25_24,
- GP_2_24_FN, FN_IP5_23_22,
- GP_2_23_FN, FN_IP5_21_20,
- GP_2_22_FN, FN_IP5_19_17,
- GP_2_21_FN, FN_IP5_16_15,
- GP_2_20_FN, FN_IP5_14_12,
- GP_2_19_FN, FN_IP5_11_9,
- GP_2_18_FN, FN_IP5_8_6,
- GP_2_17_FN, FN_IP5_5_3,
- GP_2_16_FN, FN_IP5_2_0,
- GP_2_15_FN, FN_IP4_30_28,
- GP_2_14_FN, FN_IP4_27_26,
- GP_2_13_FN, FN_IP4_25_24,
- GP_2_12_FN, FN_IP4_23_22,
- GP_2_11_FN, FN_IP4_21,
- GP_2_10_FN, FN_IP4_20,
- GP_2_9_FN, FN_IP4_19,
- GP_2_8_FN, FN_IP4_18_16,
- GP_2_7_FN, FN_IP4_15_13,
- GP_2_6_FN, FN_IP4_12_10,
- GP_2_5_FN, FN_IP4_9_8,
- GP_2_4_FN, FN_IP4_7_5,
- GP_2_3_FN, FN_IP4_4_2,
- GP_2_2_FN, FN_IP4_1_0,
- GP_2_1_FN, FN_IP3_30_28,
- GP_2_0_FN, FN_IP3_27_25 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP9_18_17,
- GP_3_30_FN, FN_IP9_16,
- GP_3_29_FN, FN_IP9_15_13,
- GP_3_28_FN, FN_IP9_12,
- GP_3_27_FN, FN_IP9_11,
- GP_3_26_FN, FN_IP9_10_8,
- GP_3_25_FN, FN_IP9_7,
- GP_3_24_FN, FN_IP9_6,
- GP_3_23_FN, FN_IP9_5_3,
- GP_3_22_FN, FN_IP9_2_0,
- GP_3_21_FN, FN_IP8_30_28,
- GP_3_20_FN, FN_IP8_27_26,
- GP_3_19_FN, FN_IP8_25_24,
- GP_3_18_FN, FN_IP8_23_21,
- GP_3_17_FN, FN_IP8_20_18,
- GP_3_16_FN, FN_IP8_17_15,
- GP_3_15_FN, FN_IP8_14_12,
- GP_3_14_FN, FN_IP8_11_9,
- GP_3_13_FN, FN_IP8_8_6,
- GP_3_12_FN, FN_IP8_5_3,
- GP_3_11_FN, FN_IP8_2_0,
- GP_3_10_FN, FN_IP7_29_27,
- GP_3_9_FN, FN_IP7_26_24,
- GP_3_8_FN, FN_IP7_23_21,
- GP_3_7_FN, FN_IP7_20_19,
- GP_3_6_FN, FN_IP7_18_17,
- GP_3_5_FN, FN_IP7_16_15,
- GP_3_4_FN, FN_IP7_14_13,
- GP_3_3_FN, FN_IP7_12_11,
- GP_3_2_FN, FN_IP7_10_9,
- GP_3_1_FN, FN_IP7_8_6,
- GP_3_0_FN, FN_IP7_5_3 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP15_5_4,
- GP_4_30_FN, FN_IP15_3_2,
- GP_4_29_FN, FN_IP15_1_0,
- GP_4_28_FN, FN_IP11_8_6,
- GP_4_27_FN, FN_IP11_5_3,
- GP_4_26_FN, FN_IP11_2_0,
- GP_4_25_FN, FN_IP10_31_29,
- GP_4_24_FN, FN_IP10_28_27,
- GP_4_23_FN, FN_IP10_26_25,
- GP_4_22_FN, FN_IP10_24_22,
- GP_4_21_FN, FN_IP10_21_19,
- GP_4_20_FN, FN_IP10_18_17,
- GP_4_19_FN, FN_IP10_16_15,
- GP_4_18_FN, FN_IP10_14_12,
- GP_4_17_FN, FN_IP10_11_9,
- GP_4_16_FN, FN_IP10_8_6,
- GP_4_15_FN, FN_IP10_5_3,
- GP_4_14_FN, FN_IP10_2_0,
- GP_4_13_FN, FN_IP9_31_29,
- GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
- GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
- GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
- GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
- GP_4_8_FN, FN_IP9_28_27,
- GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
- GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
- GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
- GP_4_4_FN, FN_IP9_26_25,
- GP_4_3_FN, FN_IP9_24_23,
- GP_4_2_FN, FN_IP9_22_21,
- GP_4_1_FN, FN_IP9_20_19,
- GP_4_0_FN, FN_VI0_CLK }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- GP_5_31_FN, FN_IP3_24_22,
- GP_5_30_FN, FN_IP13_9_7,
- GP_5_29_FN, FN_IP13_6_5,
- GP_5_28_FN, FN_IP13_4_3,
- GP_5_27_FN, FN_IP13_2_0,
- GP_5_26_FN, FN_IP12_29_27,
- GP_5_25_FN, FN_IP12_26_24,
- GP_5_24_FN, FN_IP12_23_22,
- GP_5_23_FN, FN_IP12_21_20,
- GP_5_22_FN, FN_IP12_19_18,
- GP_5_21_FN, FN_IP12_17_16,
- GP_5_20_FN, FN_IP12_15_13,
- GP_5_19_FN, FN_IP12_12_10,
- GP_5_18_FN, FN_IP12_9_7,
- GP_5_17_FN, FN_IP12_6_4,
- GP_5_16_FN, FN_IP12_3_2,
- GP_5_15_FN, FN_IP12_1_0,
- GP_5_14_FN, FN_IP11_31_30,
- GP_5_13_FN, FN_IP11_29_28,
- GP_5_12_FN, FN_IP11_27,
- GP_5_11_FN, FN_IP11_26,
- GP_5_10_FN, FN_IP11_25,
- GP_5_9_FN, FN_IP11_24,
- GP_5_8_FN, FN_IP11_23,
- GP_5_7_FN, FN_IP11_22,
- GP_5_6_FN, FN_IP11_21,
- GP_5_5_FN, FN_IP11_20,
- GP_5_4_FN, FN_IP11_19,
- GP_5_3_FN, FN_IP11_18_17,
- GP_5_2_FN, FN_IP11_16_15,
- GP_5_1_FN, FN_IP11_14_12,
- GP_5_0_FN, FN_IP11_11_9 }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- GP_6_29_FN, FN_IP14_31_29,
- GP_6_28_FN, FN_IP14_28_26,
- GP_6_27_FN, FN_IP14_25_23,
- GP_6_26_FN, FN_IP14_22_20,
- GP_6_25_FN, FN_IP14_19_17,
- GP_6_24_FN, FN_IP14_16_14,
- GP_6_23_FN, FN_IP14_13_11,
- GP_6_22_FN, FN_IP14_10_8,
- GP_6_21_FN, FN_IP14_7,
- GP_6_20_FN, FN_IP14_6,
- GP_6_19_FN, FN_IP14_5,
- GP_6_18_FN, FN_IP14_4,
- GP_6_17_FN, FN_IP14_3,
- GP_6_16_FN, FN_IP14_2,
- GP_6_15_FN, FN_IP14_1_0,
- GP_6_14_FN, FN_IP13_30_28,
- GP_6_13_FN, FN_IP13_27,
- GP_6_12_FN, FN_IP13_26,
- GP_6_11_FN, FN_IP13_25,
- GP_6_10_FN, FN_IP13_24_23,
- GP_6_9_FN, FN_IP13_22,
- 0, 0,
- GP_6_7_FN, FN_IP13_21_19,
- GP_6_6_FN, FN_IP13_18_16,
- GP_6_5_FN, FN_IP13_15,
- GP_6_4_FN, FN_IP13_14,
- GP_6_3_FN, FN_IP13_13,
- GP_6_2_FN, FN_IP13_12,
- GP_6_1_FN, FN_IP13_11,
- GP_6_0_FN, FN_IP13_10 }
- },
- { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_FN, FN_USB1_PWEN,
- GP_7_24_FN, FN_USB0_OVC,
- GP_7_23_FN, FN_USB0_PWEN,
- GP_7_22_FN, FN_IP15_14_12,
- GP_7_21_FN, FN_IP15_11_9,
- GP_7_20_FN, FN_IP15_8_6,
- GP_7_19_FN, FN_IP7_2_0,
- GP_7_18_FN, FN_IP6_29_27,
- GP_7_17_FN, FN_IP6_26_24,
- GP_7_16_FN, FN_IP6_23_21,
- GP_7_15_FN, FN_IP6_20_19,
- GP_7_14_FN, FN_IP6_18_16,
- GP_7_13_FN, FN_IP6_15_14,
- GP_7_12_FN, FN_IP6_13_12,
- GP_7_11_FN, FN_IP6_11_10,
- GP_7_10_FN, FN_IP6_9_8,
- GP_7_9_FN, FN_IP16_11_10,
- GP_7_8_FN, FN_IP16_9_8,
- GP_7_7_FN, FN_IP16_7_6,
- GP_7_6_FN, FN_IP16_5_3,
- GP_7_5_FN, FN_IP16_2_0,
- GP_7_4_FN, FN_IP15_29_27,
- GP_7_3_FN, FN_IP15_26_24,
- GP_7_2_FN, FN_IP15_23_21,
- GP_7_1_FN, FN_IP15_20_18,
- GP_7_0_FN, FN_IP15_17_15 }
- },
-
- /* IPSR0 - 5 */
-
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
- /* IP6_31_30 [2] */
- 0, 0, 0, 0,
- /* IP6_29_27 [3] */
- FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
- FN_GPS_SIGN_C, FN_GPS_SIGN_D,
- 0, 0, 0,
- /* IP6_26_24 [3] */
- FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
- FN_GPS_CLK_C, FN_GPS_CLK_D,
- 0, 0, 0,
- /* IP6_23_21 [3] */
- FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
- FN_SDA1_E, FN_MSIOF2_SYNC_E,
- 0, 0, 0,
- /* IP6_20_19 [2] */
- FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
- /* IP6_18_16 [3] */
- FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
- 0, 0, 0,
- /* IP6_15_14 [2] */
- FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
- /* IP6_13_12 [2] */
- FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
- /* IP6_11_10 [2] */
- FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
- /* IP6_9_8 [2] */
- FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
- /* IP6_7_6 [2] */
- FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
- /* IP6_5_3 [3] */
- FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
- FN_SCIFA2_RXD, FN_FMIN_E,
- 0, 0,
- /* IP6_2_0 [3] */
- FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
- FN_SCIF_CLK, 0, FN_BPFCLK_E,
- 0, 0, }
- },
-
- /* IPSR7 - 10 */
-
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 3, 3, 3, 3, 3) {
- /* IP11_31_30 [2] */
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
- /* IP11_29_28 [2] */
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
- /* IP11_27 [1] */
- FN_VI1_DATA7, FN_AVB_MDC,
- /* IP11_26 [1] */
- FN_VI1_DATA6, FN_AVB_MAGIC,
- /* IP11_25 [1] */
- FN_VI1_DATA5, FN_AVB_RX_DV,
- /* IP11_24 [1] */
- FN_VI1_DATA4, FN_AVB_MDIO,
- /* IP11_23 [1] */
- FN_VI1_DATA3, FN_AVB_RX_ER,
- /* IP11_22 [1] */
- FN_VI1_DATA2, FN_AVB_RXD7,
- /* IP11_21 [1] */
- FN_VI1_DATA1, FN_AVB_RXD6,
- /* IP11_20 [1] */
- FN_VI1_DATA0, FN_AVB_RXD5,
- /* IP11_19 [1] */
- FN_VI1_CLK, FN_AVB_RXD4,
- /* IP11_18_17 [2] */
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
- /* IP11_16_15 [2] */
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
- /* IP11_14_12 [3] */
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
- FN_RX4_B, FN_SCIFA4_RXD_B,
- 0, 0, 0,
- /* IP11_11_9 [3] */
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
- FN_TX4_B, FN_SCIFA4_TXD_B,
- 0, 0, 0,
- /* IP11_8_6 [3] */
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
- /* IP11_5_3 [3] */
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- 0, 0, 0,
- /* IP11_2_0 [3] */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
- /* IP12_31_30 [2] */
- 0, 0, 0, 0,
- /* IP12_29_27 [3] */
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
- 0, 0, 0,
- /* IP12_26_24 [3] */
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- 0, 0, 0,
- /* IP12_23_22 [2] */
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
- /* IP12_21_20 [2] */
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
- /* IP12_19_18 [2] */
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
- /* IP12_17_16 [2] */
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- /* IP12_15_13 [3] */
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- 0, 0, 0,
- /* IP12_12_10 [3] */
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- 0, 0, 0,
- /* IP12_9_7 [3] */
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
- FN_SDA2_D, FN_MSIOF1_SCK_E,
- 0, 0, 0,
- /* IP12_6_4 [3] */
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- 0, 0, 0,
- /* IP12_3_2 [2] */
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- /* IP12_1_0 [2] */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
- },
- { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
- 3, 2, 2, 3) {
- /* IP13_31 [1] */
- 0, 0,
- /* IP13_30_28 [3] */
- FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
- 0, 0, 0, 0,
- /* IP13_27 [1] */
- FN_SD1_DATA3, FN_IERX_B,
- /* IP13_26 [1] */
- FN_SD1_DATA2, FN_IECLK_B,
- /* IP13_25 [1] */
- FN_SD1_DATA1, FN_IETX_B,
- /* IP13_24_23 [2] */
- FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
- /* IP13_22 [1] */
- FN_SD1_CMD, FN_REMOCON_B,
- /* IP13_21_19 [3] */
- FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
- FN_SCIFA5_RXD_B, FN_RX3_C,
- 0, 0,
- /* IP13_18_16 [3] */
- FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
- FN_SCIFA5_TXD_B, FN_TX3_C,
- 0, 0,
- /* IP13_15 [1] */
- FN_SD0_DATA3, FN_SSL_B,
- /* IP13_14 [1] */
- FN_SD0_DATA2, FN_IO3_B,
- /* IP13_13 [1] */
- FN_SD0_DATA1, FN_IO2_B,
- /* IP13_12 [1] */
- FN_SD0_DATA0, FN_MISO_IO1_B,
- /* IP13_11 [1] */
- FN_SD0_CMD, FN_MOSI_IO0_B,
- /* IP13_10 [1] */
- FN_SD0_CLK, FN_SPCLK_B,
- /* IP13_9_7 [3] */
- FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
- FN_ADICHS2_B, FN_MSIOF0_TXD_C,
- 0, 0, 0,
- /* IP13_6_5 [2] */
- FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
- /* IP13_4_3 [2] */
- FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
- /* IP13_2_0 [3] */
- FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
- FN_ADICLK_B, FN_MSIOF0_SS1_C,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
- /* IP14_31_29 [3] */
- FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
- FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
- /* IP14_28_26 [3] */
- FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
- FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
- /* IP14_25_23 [3] */
- FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
- 0, 0, 0,
- /* IP14_22_20 [3] */
- FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
- 0, 0, 0,
- /* IP14_19_17 [3] */
- FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
- FN_VI1_CLKENB_C, FN_VI1_G1_B,
- 0, 0,
- /* IP14_16_14 [3] */
- FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
- FN_VI1_CLK_C, FN_VI1_G0_B,
- 0, 0,
- /* IP14_13_11 [3] */
- FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
- 0, 0, 0,
- /* IP14_10_8 [3] */
- FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
- 0, 0, 0,
- /* IP14_7 [1] */
- FN_SD2_DATA3, FN_MMC_D3,
- /* IP14_6 [1] */
- FN_SD2_DATA2, FN_MMC_D2,
- /* IP14_5 [1] */
- FN_SD2_DATA1, FN_MMC_D1,
- /* IP14_4 [1] */
- FN_SD2_DATA0, FN_MMC_D0,
- /* IP14_3 [1] */
- FN_SD2_CMD, FN_MMC_CMD,
- /* IP14_2 [1] */
- FN_SD2_CLK, FN_MMC_CLK,
- /* IP14_1_0 [2] */
- FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
- /* IP15_31_30 [2] */
- 0, 0, 0, 0,
- /* IP15_29_27 [3] */
- FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
- FN_CAN0_TX_B, FN_VI1_DATA5_C,
- 0, 0,
- /* IP15_26_24 [3] */
- FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
- FN_CAN0_RX_B, FN_VI1_DATA4_C,
- 0, 0,
- /* IP15_23_21 [3] */
- FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
- FN_TCLK2, FN_VI1_DATA3_C, 0,
- /* IP15_20_18 [3] */
- FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
- 0, 0, 0,
- /* IP15_17_15 [3] */
- FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
- FN_TCLK1, FN_VI1_DATA1_C,
- 0, 0,
- /* IP15_14_12 [3] */
- FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
- FN_VI1_G7_B, FN_SCIFA3_SCK_C,
- 0, 0,
- /* IP15_11_9 [3] */
- FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
- FN_VI1_G6_B, FN_SCIFA3_RXD_C,
- 0, 0,
- /* IP15_8_6 [3] */
- FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
- FN_PWM5_B, FN_SCIFA3_TXD_C,
- 0, 0, 0,
- /* IP15_5_4 [2] */
- FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
- /* IP15_3_2 [2] */
- FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
- /* IP15_1_0 [2] */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
- /* IP16_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_15_12 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_11_10 [2] */
- FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
- /* IP16_9_8 [2] */
- FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
- /* IP16_7_6 [2] */
- FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
- /* IP16_5_3 [3] */
- FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
- FN_GLO_SS_C, FN_VI1_DATA7_C,
- 0, 0, 0,
- /* IP16_2_0 [3] */
- FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
- FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
- 3, 2, 2, 2, 1, 2, 2, 2) {
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF1 [2] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- /* SEL_SCIFB [2] */
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- /* SEL_SCIFB2 [2] */
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
- FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- /* SEL_SCIFB1 [3] */
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
- FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- 0, 0, 0, 0,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* SEL_SCFA [1] */
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- /* SEL_QSP [1] */
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- /* SEL_SSI7 [1] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- /* SEL_HSCIF1 [3] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
- FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_VI1 [2] */
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_TMU [1] */
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- /* SEL_LBS [2] */
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_SOF0 [2] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 3, 2, 1, 1, 2, 2,
- 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
- /* SEL_SCIF0 [3] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
- FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF [1] */
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- /* SEL_CAN0 [3] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- 0, 0,
- /* SEL_CAN1 [2] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIFA2 [1] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- /* SEL_SCIF4 [2] */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_ADG [1] */
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- /* SEL_FM [3] */
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
- FN_SEL_FM_3, FN_SEL_FM_4,
- 0, 0, 0,
- /* SEL_SCIFA5 [2] */
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_GPS [2] */
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- /* SEL_SCIFA4 [2] */
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
- /* SEL_SCIFA3 [2] */
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
- /* SEL_SIM [1] */
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 2, 2, 3, 2, 2, 2, 1) {
- /* SEL_HSCIF2 [2] */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- /* SEL_CANCLK [2] */
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- /* SEL_IIC8 [2] */
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
- /* SEL_IIC7 [2] */
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
- /* SEL_IIC4 [2] */
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
- /* SEL_IIC3 [2] */
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- /* SEL_SCIF3 [2] */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* SEL_MMC [1] */
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- /* SEL_SCIF5 [1] */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_IIC2 [2] */
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- /* SEL_IIC1 [3] */
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- 0, 0, 0,
- /* SEL_IIC0 [2] */
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [1] */
- 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- 3, 2, 2, 1, 1, 1, 1, 3, 2,
- 2, 3, 1, 1, 1, 2, 2, 2, 2) {
- /* SEL_SOF1 [3] */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- 0, 0, 0,
- /* SEL_HSCIF0 [2] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
- /* SEL_DIS [2] */
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_RAD [1] */
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- /* SEL_SCIF2 [3] */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
- FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_SOF2 [3] */
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
- FN_SEL_SOF2_3, FN_SEL_SOF2_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI1 [1] */
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- /* SEL_SSI0 [1] */
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- /* SEL_SSP [2] */
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_IN, GP_7_25_OUT,
- GP_7_24_IN, GP_7_24_OUT,
- GP_7_23_IN, GP_7_23_OUT,
- GP_7_22_IN, GP_7_22_OUT,
- GP_7_21_IN, GP_7_21_OUT,
- GP_7_20_IN, GP_7_20_OUT,
- GP_7_19_IN, GP_7_19_OUT,
- GP_7_18_IN, GP_7_18_OUT,
- GP_7_17_IN, GP_7_17_OUT,
- GP_7_16_IN, GP_7_16_OUT,
- GP_7_15_IN, GP_7_15_OUT,
- GP_7_14_IN, GP_7_14_OUT,
- GP_7_13_IN, GP_7_13_OUT,
- GP_7_12_IN, GP_7_12_OUT,
- GP_7_11_IN, GP_7_11_OUT,
- GP_7_10_IN, GP_7_10_OUT,
- GP_7_9_IN, GP_7_9_OUT,
- GP_7_8_IN, GP_7_8_OUT,
- GP_7_7_IN, GP_7_7_OUT,
- GP_7_6_IN, GP_7_6_OUT,
- GP_7_5_IN, GP_7_5_OUT,
- GP_7_4_IN, GP_7_4_OUT,
- GP_7_3_IN, GP_7_3_OUT,
- GP_7_2_IN, GP_7_2_OUT,
- GP_7_1_IN, GP_7_1_OUT,
- GP_7_0_IN, GP_7_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
- { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_7_25_DATA, GP_7_24_DATA,
- GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
- GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
- GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
- GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
- GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7793_pinmux_info = {
- .name = "r8a7793_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_CAN1_RX_B,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7793_pinmux_init(void)
-{
- register_pinmux(&r8a7793_pinmux_info);
-}
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
deleted file mode 100644
index e123663..0000000
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+++ /dev/null
@@ -1,1513 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
- * This file is r8a7794 processor support - PFC hardware block.
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_26_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
-
-#define CPU_28_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
- PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
-
-/*
- * GP_0_0_DATA -> GP_6_25_DATA
- * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
- * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
- * GP6[29]),GP6[30],GP6[31])
- */
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_26_PORT(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_28_PORT(fn, pfx##_5_, sfx), \
- CPU_26_PORT(fn, pfx##_6_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
- FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
- FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
- FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
- FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
- FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
- FN_IP2_17_16,
-
- /* GPSR1 */
- FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
- FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
- FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
- FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
- FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
-
- /* GPSR2 */
- FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
- FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
- FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
- FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
- FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
- FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
- FN_IP6_5_4, FN_IP6_7_6,
-
- /* GPSR3 */
- FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
- FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
- FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
- FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
- FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
- FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
- FN_IP8_22_20,
-
- /* GPSR4 */
- FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
- FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
- FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
- FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
- FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
- FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
- FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
-
- /* GPSR5 */
- FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
- FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
- FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
- FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
- FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
- FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
-
- /* GPSR6 */
- FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
- FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
- FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
- FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
- FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
-
- /*
- * From IPSR0 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
- FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
- FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
- FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
- FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
- FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
- FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
- FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
- FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
- FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
- FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
- FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
- FN_ADIDATA, FN_AD_DI,
-
- /* IPSR7 */
- FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
- FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
- FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
- FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
- FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
- FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
- FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
- FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
- FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
- FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
- FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
- FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
- FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
-
- /* IPSR8 */
- FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
- FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
- FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
- FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
- FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
- FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
- FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
- FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
- FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
- FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
- FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
- FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
- FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
- FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
- FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
- FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
- FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
- FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
- FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
- FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
- FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
- FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
- FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
- FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
- FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
- FN_ADICLK_B, FN_AD_CLK_B,
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-
- /* MOD_SEL */
- FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
- FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
- FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
- FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
- FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
- FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
- FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
- FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
- FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
- FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
- FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
- FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
- FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
- FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
-
- /* MOD_SEL2 */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
- FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
- FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
- FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
- FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
- FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
- FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
- FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
- FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
- FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
- FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
- FN_SEL_RDS_2, FN_SEL_RDS_3,
-
- /* MOD_SEL3 */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
- FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
- FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
- FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
- FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
- FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
- FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
- FN_SEL_SSI9_1,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
- A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
-
- SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
- SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
-
- SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
- SD1_DATA2_MARK, SD1_DATA3_MARK,
-
- /*
- * From IPSR0 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
- DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
- DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
- CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
- AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
- VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
- AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
- VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
- AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
- I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
- VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
- AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
- IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
- I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
- VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
- ADIDATA_MARK, AD_DI_MARK,
-
- /* IPSR7 */
- ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
- AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
- MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
- AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
- CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
- ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
- AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
- MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
- ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
- SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
- IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
- VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
- SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
- AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
- SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
- DREQ0_N_MARK, SCIFB1_RXD_MARK,
-
- /* IPSR8 */
- ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
- AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
- I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
- HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
- AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
- SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
- HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
- AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
- HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
- I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
- AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
- SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
- CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
- DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
- I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
- TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
- I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
- FMCLK_C_MARK, RDS_CLK_MARK,
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
- CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
- DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
- SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
- SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
- DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
- SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
- CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
- DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
- DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
- AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
- MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
- PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
- ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
- PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_DATA(A2_MARK, FN_A2),
- PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
- PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
- PINMUX_DATA(DACK0_MARK, FN_DACK0),
- PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
- PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
- PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
- PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
- PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
- PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
- PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
- PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
- PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
- PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
- PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
- PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
- PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
- PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
- PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
- PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
- PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
- PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
-
- /*
- * From IPSR0 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
- PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
- PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
- PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
- PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
- PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
- PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
- PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
- PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
- PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
- PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
- PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
- PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
- PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
- PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
- PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
- PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
- PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
- PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
- PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
- PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
- PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
- PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
- PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
- PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
- PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
- PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
- PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
- PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
- PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
- PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
- PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
- PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
-
- /* IPSR7 */
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
- PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
- PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
- PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
- PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
- PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
- PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
- PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
- PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
- PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
- PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
- PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
-
- /* IPSR8 */
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
- PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
- PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
- PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
- PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
- PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
- PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
- PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP8_19_17, PWM5),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
- PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
- PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
- PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
- PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
- PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
- PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
- PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
- PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
- PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
- PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
- PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
- PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
- PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
- PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
- PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
- PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
- PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
- PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
- PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
- PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
- PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
- PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
- PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
- GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
- GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
- GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
- GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
- GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
- GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
-
- /*
- * From IPSR0 to IPSR5 have been removed because they does not use
- */
-
- /* IPSR6 */
- GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
- GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
- GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
- GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
- GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
- GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
- GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
- GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
- GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
- GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
- GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
- GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
- GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
- GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
- GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
- GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
- GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
- GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
- GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
- GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
-
- /* IPSR7 */
- GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
- GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
- GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
- GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
- GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
- GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
- GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
- GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
- GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
- GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
- GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
- GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
- GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
- GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
- GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
- GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
- GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
- GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
- GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
- GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
- GPIO_FN(SCIFB1_RXD),
-
- /* IPSR8 */
- GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
- GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
- GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
- GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
- GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
- GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
- GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
- GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
- GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
- GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
- GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
- GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
- GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
- GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
- GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
- GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
- GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
- GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
- GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
- GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
- GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
- GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
- GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
- GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
- GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
- GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
- GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
- GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
- GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
- GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
- GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
- GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
- GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
- GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
- GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
- GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
- GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
- GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
- GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
- GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
- GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP2_17_16,
- GP_0_30_FN, FN_IP2_15_14,
- GP_0_29_FN, FN_IP2_13_12,
- GP_0_28_FN, FN_IP2_11_10,
- GP_0_27_FN, FN_IP2_9_8,
- GP_0_26_FN, FN_IP2_7_6,
- GP_0_25_FN, FN_IP2_5_4,
- GP_0_24_FN, FN_IP2_3_2,
- GP_0_23_FN, FN_IP2_1_0,
- GP_0_22_FN, FN_IP1_31_30,
- GP_0_21_FN, FN_IP1_29_28,
- GP_0_20_FN, FN_IP1_27,
- GP_0_19_FN, FN_IP1_26,
- GP_0_18_FN, FN_A2,
- GP_0_17_FN, FN_IP1_24,
- GP_0_16_FN, FN_IP1_23_22,
- GP_0_15_FN, FN_IP1_21_20,
- GP_0_14_FN, FN_IP1_19_18,
- GP_0_13_FN, FN_IP1_17_15,
- GP_0_12_FN, FN_IP1_14_13,
- GP_0_11_FN, FN_IP1_12_11,
- GP_0_10_FN, FN_IP1_10_8,
- GP_0_9_FN, FN_IP1_7_6,
- GP_0_8_FN, FN_IP1_5_4,
- GP_0_7_FN, FN_IP1_3_2,
- GP_0_6_FN, FN_IP1_1_0,
- GP_0_5_FN, FN_IP0_31_30,
- GP_0_4_FN, FN_IP0_29_28,
- GP_0_3_FN, FN_IP0_27_26,
- GP_0_2_FN, FN_IP0_25,
- GP_0_1_FN, FN_IP0_24,
- GP_0_0_FN, FN_IP0_23_22, }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_FN, FN_DACK0,
- GP_1_24_FN, FN_IP7_31,
- GP_1_23_FN, FN_IP4_1_0,
- GP_1_22_FN, FN_WE1_N,
- GP_1_21_FN, FN_WE0_N,
- GP_1_20_FN, FN_IP3_31,
- GP_1_19_FN, FN_IP3_30,
- GP_1_18_FN, FN_IP3_29_27,
- GP_1_17_FN, FN_IP3_26_24,
- GP_1_16_FN, FN_IP3_23_21,
- GP_1_15_FN, FN_IP3_20_18,
- GP_1_14_FN, FN_IP3_17_15,
- GP_1_13_FN, FN_IP3_14_13,
- GP_1_12_FN, FN_IP3_12,
- GP_1_11_FN, FN_IP3_11,
- GP_1_10_FN, FN_IP3_10,
- GP_1_9_FN, FN_IP3_9_8,
- GP_1_8_FN, FN_IP3_7_6,
- GP_1_7_FN, FN_IP3_5_4,
- GP_1_6_FN, FN_IP3_3_2,
- GP_1_5_FN, FN_IP3_1_0,
- GP_1_4_FN, FN_IP2_31_30,
- GP_1_3_FN, FN_IP2_29_27,
- GP_1_2_FN, FN_IP2_26_24,
- GP_1_1_FN, FN_IP2_23_21,
- GP_1_0_FN, FN_IP2_20_18, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_IP6_7_6,
- GP_2_30_FN, FN_IP6_5_4,
- GP_2_29_FN, FN_IP6_3_2,
- GP_2_28_FN, FN_IP6_1_0,
- GP_2_27_FN, FN_IP5_31_30,
- GP_2_26_FN, FN_IP5_29_28,
- GP_2_25_FN, FN_IP5_27_26,
- GP_2_24_FN, FN_IP5_25_24,
- GP_2_23_FN, FN_IP5_23_22,
- GP_2_22_FN, FN_IP5_21_20,
- GP_2_21_FN, FN_IP5_19_18,
- GP_2_20_FN, FN_IP5_17_16,
- GP_2_19_FN, FN_IP5_15_14,
- GP_2_18_FN, FN_IP5_13_12,
- GP_2_17_FN, FN_IP5_11_9,
- GP_2_16_FN, FN_IP5_8_6,
- GP_2_15_FN, FN_IP5_5_4,
- GP_2_14_FN, FN_IP5_3_2,
- GP_2_13_FN, FN_IP5_1_0,
- GP_2_12_FN, FN_IP4_31_30,
- GP_2_11_FN, FN_IP4_29_28,
- GP_2_10_FN, FN_IP4_27_26,
- GP_2_9_FN, FN_IP4_25_23,
- GP_2_8_FN, FN_IP4_22_20,
- GP_2_7_FN, FN_IP4_19_18,
- GP_2_6_FN, FN_IP4_17_16,
- GP_2_5_FN, FN_IP4_15_14,
- GP_2_4_FN, FN_IP4_13_12,
- GP_2_3_FN, FN_IP4_11_10,
- GP_2_2_FN, FN_IP4_9_8,
- GP_2_1_FN, FN_IP4_7_5,
- GP_2_0_FN, FN_IP4_4_2 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP8_22_20,
- GP_3_30_FN, FN_IP8_19_17,
- GP_3_29_FN, FN_IP8_16_15,
- GP_3_28_FN, FN_IP8_14_12,
- GP_3_27_FN, FN_IP8_11_9,
- GP_3_26_FN, FN_IP8_8_6,
- GP_3_25_FN, FN_IP8_5_3,
- GP_3_24_FN, FN_IP8_2_0,
- GP_3_23_FN, FN_IP7_29_27,
- GP_3_22_FN, FN_IP7_26_24,
- GP_3_21_FN, FN_IP7_23_21,
- GP_3_20_FN, FN_IP7_20_18,
- GP_3_19_FN, FN_IP7_17_15,
- GP_3_18_FN, FN_IP7_14_12,
- GP_3_17_FN, FN_IP7_11_9,
- GP_3_16_FN, FN_IP7_8_6,
- GP_3_15_FN, FN_IP7_5_3,
- GP_3_14_FN, FN_IP7_2_0,
- GP_3_13_FN, FN_IP6_31_29,
- GP_3_12_FN, FN_IP6_28_26,
- GP_3_11_FN, FN_IP6_25_23,
- GP_3_10_FN, FN_IP6_22_20,
- GP_3_9_FN, FN_IP6_19_17,
- GP_3_8_FN, FN_IP6_16,
- GP_3_7_FN, FN_IP6_15,
- GP_3_6_FN, FN_IP6_14,
- GP_3_5_FN, FN_IP6_13,
- GP_3_4_FN, FN_IP6_12,
- GP_3_3_FN, FN_IP6_11,
- GP_3_2_FN, FN_IP6_10,
- GP_3_1_FN, FN_IP6_9,
- GP_3_0_FN, FN_IP6_8 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP11_17_16,
- GP_4_30_FN, FN_IP11_15_14,
- GP_4_29_FN, FN_IP11_13_11,
- GP_4_28_FN, FN_IP11_10_8,
- GP_4_27_FN, FN_IP11_7_6,
- GP_4_26_FN, FN_IP11_5_3,
- GP_4_25_FN, FN_IP11_2_0,
- GP_4_24_FN, FN_IP10_31_30,
- GP_4_23_FN, FN_IP10_29_27,
- GP_4_22_FN, FN_IP10_26_24,
- GP_4_21_FN, FN_IP10_23_21,
- GP_4_20_FN, FN_IP10_20_18,
- GP_4_19_FN, FN_IP10_17_15,
- GP_4_18_FN, FN_IP10_14_12,
- GP_4_17_FN, FN_IP10_11_9,
- GP_4_16_FN, FN_IP10_8_6,
- GP_4_15_FN, FN_IP10_5_3,
- GP_4_14_FN, FN_IP10_2_0,
- GP_4_13_FN, FN_IP9_30_28,
- GP_4_12_FN, FN_IP9_27_25,
- GP_4_11_FN, FN_IP9_24_22,
- GP_4_10_FN, FN_IP9_21_19,
- GP_4_9_FN, FN_IP9_18_17,
- GP_4_8_FN, FN_IP9_16_15,
- GP_4_7_FN, FN_IP9_14_12,
- GP_4_6_FN, FN_IP9_11_9,
- GP_4_5_FN, FN_IP9_8_6,
- GP_4_4_FN, FN_IP9_5_3,
- GP_4_3_FN, FN_IP9_2_0,
- GP_4_2_FN, FN_IP8_31_29,
- GP_4_1_FN, FN_IP8_28_26,
- GP_4_0_FN, FN_IP8_25_23 }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_27_FN, FN_USB1_OVC,
- GP_5_26_FN, FN_USB1_PWEN,
- GP_5_25_FN, FN_USB0_OVC,
- GP_5_24_FN, FN_USB0_PWEN,
- GP_5_23_FN, FN_IP13_26_24,
- GP_5_22_FN, FN_IP13_23_21,
- GP_5_21_FN, FN_IP13_20_18,
- GP_5_20_FN, FN_IP13_17_15,
- GP_5_19_FN, FN_IP13_14_12,
- GP_5_18_FN, FN_IP13_11_9,
- GP_5_17_FN, FN_IP13_8_6,
- GP_5_16_FN, FN_IP13_5_3,
- GP_5_15_FN, FN_IP13_2_0,
- GP_5_14_FN, FN_IP12_29_27,
- GP_5_13_FN, FN_IP12_26_24,
- GP_5_12_FN, FN_IP12_23_21,
- GP_5_11_FN, FN_IP12_20_18,
- GP_5_10_FN, FN_IP12_17_15,
- GP_5_9_FN, FN_IP12_14_13,
- GP_5_8_FN, FN_IP12_12_11,
- GP_5_7_FN, FN_IP12_10_9,
- GP_5_6_FN, FN_IP12_8_6,
- GP_5_5_FN, FN_IP12_5_3,
- GP_5_4_FN, FN_IP12_2_0,
- GP_5_3_FN, FN_IP11_29_27,
- GP_5_2_FN, FN_IP11_26_24,
- GP_5_1_FN, FN_IP11_23_21,
- GP_5_0_FN, FN_IP11_20_18 }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_25_FN, FN_IP0_21_20,
- GP_6_24_FN, FN_IP0_19_18,
- GP_6_23_FN, FN_IP0_17,
- GP_6_22_FN, FN_IP0_16,
- GP_6_21_FN, FN_IP0_15,
- GP_6_20_FN, FN_IP0_14,
- GP_6_19_FN, FN_IP0_13,
- GP_6_18_FN, FN_IP0_12,
- GP_6_17_FN, FN_IP0_11,
- GP_6_16_FN, FN_IP0_10,
- GP_6_15_FN, FN_IP0_9_8,
- GP_6_14_FN, FN_IP0_0,
- GP_6_13_FN, FN_SD1_DATA3,
- GP_6_12_FN, FN_SD1_DATA2,
- GP_6_11_FN, FN_SD1_DATA1,
- GP_6_10_FN, FN_SD1_DATA0,
- GP_6_9_FN, FN_SD1_CMD,
- GP_6_8_FN, FN_SD1_CLK,
- GP_6_7_FN, FN_SD0_WP,
- GP_6_6_FN, FN_SD0_CD,
- GP_6_5_FN, FN_SD0_DATA3,
- GP_6_4_FN, FN_SD0_DATA2,
- GP_6_3_FN, FN_SD0_DATA1,
- GP_6_2_FN, FN_SD0_DATA0,
- GP_6_1_FN, FN_SD0_CMD,
- GP_6_0_FN, FN_SD0_CLK }
- },
-
- /*
- * From IPSR0 to IPSR5 have been removed because they does not use.
- */
-
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 2, 2) {
- /* IP6_31_29 [3] */
- FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
- FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
- /* IP6_28_26 [3] */
- FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
- FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
- /* IP6_25_23 [3] */
- FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
- FN_AVB_COL, 0, 0, 0,
- /* IP6_22_20 [3] */
- FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
- FN_AVB_RX_ER, 0, 0, 0,
- /* IP6_19_17 [3] */
- FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
- FN_AVB_RXD7, 0, 0, 0,
- /* IP6_16 [1] */
- FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
- /* IP6_15 [1] */
- FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
- /* IP6_14 [1] */
- FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
- /* IP6_13 [1] */
- FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
- /* IP6_12 [1] */
- FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
- /* IP6_11 [1] */
- FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
- /* IP6_10 [1] */
- FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
- /* IP6_9 [1] */
- FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
- /* IP6_8 [1] */
- FN_VI0_CLK, FN_AVB_RX_CLK,
- /* IP6_7_6 [2] */
- FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
- /* IP6_5_4 [2] */
- FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
- /* IP6_3_2 [2] */
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
- /* IP6_1_0 [2] */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
- /* IP7_31 [1] */
- FN_DREQ0_N, FN_SCIFB1_RXD,
- /* IP7_30 [1] */
- 0, 0,
- /* IP7_29_27 [3] */
- FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
- FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
- /* IP7_26_24 [3] */
- FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
- FN_SSI_SCK6_B, 0, 0, 0,
- /* IP7_23_21 [3] */
- FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
- FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
- /* IP7_20_18 [3] */
- FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
- FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
- /* IP7_17_15 [3] */
- FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
- FN_SSI_SCK5_B, 0, 0, 0,
- /* IP7_14_12 [3] */
- FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
- FN_AVB_TXD4, FN_ADICHS2, 0, 0,
- /* IP7_11_9 [3] */
- FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
- FN_AVB_TXD3, FN_ADICHS1, 0, 0,
- /* IP7_8_6 [3] */
- FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
- FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
- /* IP7_5_3 [3] */
- FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
- FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
- /* IP7_2_0 [3] */
- FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
- FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
- /* IP8_31_29 [3] */
- FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
- FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
- /* IP8_28_26 [3] */
- FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
- FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
- /* IP8_25_23 [3] */
- FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
- FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
- /* IP8_22_20 [3] */
- FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
- FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
- /* IP8_19_17 [3] */
- FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
- FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
- /* IP8_16_15 [2] */
- FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
- /* IP8_14_12 [3] */
- FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
- FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
- /* IP8_11_9 [3] */
- FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
- FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
- /* IP8_8_6 [3] */
- FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
- FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
- /* IP8_5_3 [3] */
- FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
- FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
- /* IP8_2_0 [3] */
- FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
- FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
- },
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
- /* IP11_31_30 [2] */
- 0, 0, 0, 0,
- /* IP11_29_27 [3] */
- FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
- FN_AD_CLK_B, 0, 0, 0,
- /* IP11_26_24 [3] */
- FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
- FN_AD_DO_B, 0, 0, 0,
- /* IP11_23_21 [3] */
- FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
- FN_AD_DI_B, FN_PCMWE_N, 0, 0,
- /* IP11_20_18 [3] */
- FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
- FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
- /* IP11_17_16 [2] */
- FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
- /* IP11_15_14 [2] */
- FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
- /* IP11_13_11 [3] */
- FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
- /* IP11_10_8 [3] */
- FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
- FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
- /* IP11_7_6 [2] */
- FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
- FN_CAN_DEBUGOUT13,
- /* IP11_5_3 [3] */
- FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
- FN_CAN_DEBUGOUT12, 0, 0, 0,
- /* IP11_2_0 [3] */
- FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- FN_CAN_DEBUGOUT11, 0, 0, 0, }
- },
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
- 2, 1) {
- /* SEL_ADG [2] */
- FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
- /* SEL_ADI [1] */
- FN_SEL_ADI_0, FN_SEL_ADI_1,
- /* SEL_CAN [2] */
- FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
- /* SEL_DARC [3] */
- FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
- FN_SEL_DARC_4, 0, 0, 0,
- /* SEL_DR0 [1] */
- FN_SEL_DR0_0, FN_SEL_DR0_1,
- /* SEL_DR1 [1] */
- FN_SEL_DR1_0, FN_SEL_DR1_1,
- /* SEL_DR2 [1] */
- FN_SEL_DR2_0, FN_SEL_DR2_1,
- /* SEL_DR3 [1] */
- FN_SEL_DR3_0, FN_SEL_DR3_1,
- /* SEL_ETH [1] */
- FN_SEL_ETH_0, FN_SEL_ETH_1,
- /* SLE_FSN [1] */
- FN_SEL_FSN_0, FN_SEL_FSN_1,
- /* SEL_IC200 [3] */
- FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
- FN_SEL_I2C00_4, 0, 0, 0,
- /* SEL_I2C01 [3] */
- FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
- FN_SEL_I2C01_4, 0, 0, 0,
- /* SEL_I2C02 [3] */
- FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
- FN_SEL_I2C02_4, 0, 0, 0,
- /* SEL_I2C03 [3] */
- FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
- FN_SEL_I2C03_4, 0, 0, 0,
- /* SEL_I2C04 [3] */
- FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
- FN_SEL_I2C04_4, 0, 0, 0,
- /* SEL_IIC00 [2] */
- FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
- /* SEL_AVB [1] */
- FN_SEL_AVB_0, FN_SEL_AVB_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
- 2, 2, 2, 1, 1, 2) {
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* SEL_IIC0 [2] */
- FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
- /* SEL_LBS [1] */
- FN_SEL_LBS_0, FN_SEL_LBS_1,
- /* SEL_MSI1 [1] */
- FN_SEL_MSI1_0, FN_SEL_MSI1_1,
- /* SEL_MSI2 [1] */
- FN_SEL_MSI2_0, FN_SEL_MSI2_1,
- /* SEL_RAD [1] */
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- /* SEL_SCIFA0 [2] */
- FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
- FN_SEL_SCIFA0_3,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
- /* SEL_SCIFA2 [1] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- /* SEL_SCIFA3 [1] */
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
- /* SEL_SCIFA4 [2] */
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
- FN_SEL_SCIFA4_3,
- /* SEL_SCIFA5 [2] */
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_SCIFA5_3,
- /* SEL_SPDM [1] */
- FN_SEL_SPDM_0, FN_SEL_SPDM_1,
- /* SEL_TMU [1] */
- FN_SEL_TMU_0, FN_SEL_TMU_1,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_CAN0 [2] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- /* SEL_CAN1 [2] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- /* SEL_HSCIF0 [1] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
- /* SEL_HSCIF1 [1] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* SEL_RDS [2] */
- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
- /* SEL_SCIF0 [2] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- /* SEL_SCIF1 [2] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
- /* SEL_SCIF2 [2] */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
- /* SEL_SCIF3 [1] */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
- /* SEL_SCIF4 [3] */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
- FN_SEL_SCIF4_4, 0, 0, 0,
- /* SEL_SCIF5 [2] */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
- /* SEL_SSI1 [1] */
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- /* SEL_SSI2 [1] */
- FN_SEL_SSI2_0, FN_SEL_SSI2_1,
- /* SEL_SSI4 [1] */
- FN_SEL_SSI4_0, FN_SEL_SSI4_1,
- /* SEL_SSI5 [1] */
- FN_SEL_SSI5_0, FN_SEL_SSI5_1,
- /* SEL_SSI6 [1] */
- FN_SEL_SSI6_0, FN_SEL_SSI6_1,
- /* SEL_SSI7 [1] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- /* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_27_IN, GP_5_27_OUT,
- GP_5_26_IN, GP_5_26_OUT,
- GP_5_25_IN, GP_5_25_OUT,
- GP_5_24_IN, GP_5_24_OUT,
- GP_5_23_IN, GP_5_23_OUT,
- GP_5_22_IN, GP_5_22_OUT,
- GP_5_21_IN, GP_5_21_OUT,
- GP_5_20_IN, GP_5_20_OUT,
- GP_5_19_IN, GP_5_19_OUT,
- GP_5_18_IN, GP_5_18_OUT,
- GP_5_17_IN, GP_5_17_OUT,
- GP_5_16_IN, GP_5_16_OUT,
- GP_5_15_IN, GP_5_15_OUT,
- GP_5_14_IN, GP_5_14_OUT,
- GP_5_13_IN, GP_5_13_OUT,
- GP_5_12_IN, GP_5_12_OUT,
- GP_5_11_IN, GP_5_11_OUT,
- GP_5_10_IN, GP_5_10_OUT,
- GP_5_9_IN, GP_5_9_OUT,
- GP_5_8_IN, GP_5_8_OUT,
- GP_5_7_IN, GP_5_7_OUT,
- GP_5_6_IN, GP_5_6_OUT,
- GP_5_5_IN, GP_5_5_OUT,
- GP_5_4_IN, GP_5_4_OUT,
- GP_5_3_IN, GP_5_3_OUT,
- GP_5_2_IN, GP_5_2_OUT,
- GP_5_1_IN, GP_5_1_OUT,
- GP_5_0_IN, GP_5_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_25_IN, GP_6_25_OUT,
- GP_6_24_IN, GP_6_24_OUT,
- GP_6_23_IN, GP_6_23_OUT,
- GP_6_22_IN, GP_6_22_OUT,
- GP_6_21_IN, GP_6_21_OUT,
- GP_6_20_IN, GP_6_20_OUT,
- GP_6_19_IN, GP_6_19_OUT,
- GP_6_18_IN, GP_6_18_OUT,
- GP_6_17_IN, GP_6_17_OUT,
- GP_6_16_IN, GP_6_16_OUT,
- GP_6_15_IN, GP_6_15_OUT,
- GP_6_14_IN, GP_6_14_OUT,
- GP_6_13_IN, GP_6_13_OUT,
- GP_6_12_IN, GP_6_12_OUT,
- GP_6_11_IN, GP_6_11_OUT,
- GP_6_10_IN, GP_6_10_OUT,
- GP_6_9_IN, GP_6_9_OUT,
- GP_6_8_IN, GP_6_8_OUT,
- GP_6_7_IN, GP_6_7_OUT,
- GP_6_6_IN, GP_6_6_OUT,
- GP_6_5_IN, GP_6_5_OUT,
- GP_6_4_IN, GP_6_4_OUT,
- GP_6_3_IN, GP_6_3_OUT,
- GP_6_2_IN, GP_6_2_OUT,
- GP_6_1_IN, GP_6_1_OUT,
- GP_6_0_IN, GP_6_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
- 0, 0, 0, 0,
- GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
- GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
- GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
- GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
- GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
- GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
- GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
- },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_6_25_DATA, GP_6_24_DATA,
- GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
- GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
- GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
- GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
- GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
- GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7794_pinmux_info = {
- .name = "r8a7794_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_AD_CLK_B,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7794_pinmux_init(void)
-{
- register_pinmux(&r8a7794_pinmux_info);
-}
diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c
deleted file mode 100644
index 04700e7..0000000
--- a/arch/arm/cpu/armv7/rmobile/timer.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * (C) Copyright 2012 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch-armv7/globaltimer.h>
-#include <asm/arch/rmobile.h>
-
-static struct globaltimer *global_timer = \
- (struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
-static u64 get_cpu_global_timer(void)
-{
- u32 low, high;
- u64 timer;
-
- u32 old = readl(&global_timer->cnt_h);
- while (1) {
- low = readl(&global_timer->cnt_l);
- high = readl(&global_timer->cnt_h);
- if (old == high)
- break;
- else
- old = high;
- }
-
- timer = high;
- return (u64)((timer << 32) | low);
-}
-
-static u64 get_time_us(void)
-{
- u64 timer = get_cpu_global_timer();
-
- timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
- do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
- return timer;
-}
-
-static ulong get_time_ms(void)
-{
- u64 us = get_time_us();
-
- do_div(us, 1000);
- return us;
-}
-
-int timer_init(void)
-{
- writel(0x01, &global_timer->ctl);
- return 0;
-}
-
-void __udelay(unsigned long usec)
-{
- u64 start, current;
- u64 wait;
-
- start = get_cpu_global_timer();
- wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
- do {
- current = get_cpu_global_timer();
- } while ((current - start) < wait);
-}
-
-ulong get_timer(ulong base)
-{
- return get_time_ms() - base;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_cpu_global_timer();
-}
-
-ulong get_tbclk(void)
-{
- return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
-}
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index f571d8a..12cf804 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2009 Samsung Electronics
# Minkyu Kang <mk7.kang@samsung.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += cpu_info.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
index a8d91e7..5f4076d 100644
--- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c
+++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
@@ -1,13 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* Default is s5pc100 */
unsigned int s5p_cpu_id = 0xC100;
/* Default is EVT1 */
@@ -30,11 +32,17 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
- char buf[32];
+ const char *cpu_model;
+ int len;
- printf("CPU:\t%s%X@%sMHz\n",
- s5p_get_cpu_name(), s5p_cpu_id,
- strmhz(buf, get_arm_clk()));
+ /* For SoC with no real CPU ID in naming convention. */
+ cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len);
+ if (cpu_model)
+ printf("CPU: %.*s @ ", len, cpu_model);
+ else
+ printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+
+ print_freq(get_arm_clk(), "\n");
return 0;
}
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c
index b8805c8..6b9e865 100644
--- a/arch/arm/cpu/armv7/s5p-common/pwm.c
+++ b/arch/arm/cpu/armv7/s5p-common/pwm.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Samsung Electronics
*
* Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c
index 806456f..0fc1709 100644
--- a/arch/arm/cpu/armv7/s5p-common/sromc.c
+++ b/arch/arm/cpu/armv7/s5p-common/sromc.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c
index 949abb1..0048cd8 100644
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2009 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
* Inki Dae <inki.dae@samsung.com>
* Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -12,11 +11,15 @@
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <asm/arch/clk.h>
+
+/* Use the old PWM interface for now */
+#undef CONFIG_DM_PWM
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long get_current_tick(void);
+static void reset_timer_masked(void);
/* macro to read the 16 bit timer */
static inline struct s5p_timer *s5p_get_base_timer(void)
@@ -104,7 +107,7 @@
;
}
-void reset_timer_masked(void)
+static void reset_timer_masked(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
deleted file mode 100644
index 6288134..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-if ARCH_S5PC1XX
-
-choice
- prompt "S5PC1XX board select"
-
-config TARGET_S5P_GONI
- bool "S5P Goni board"
- select OF_CONTROL if !SPL_BUILD
-
-config TARGET_SMDKC100
- bool "Support smdkc100 board"
- select OF_CONTROL if !SPL_BUILD
-
-endchoice
-
-config SYS_SOC
- default "s5pc1xx"
-
-source "board/samsung/goni/Kconfig"
-source "board/samsung/smdkc100/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
deleted file mode 100644
index 9f43ded..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cache.o
-obj-y += reset.o
-
-obj-y += clock.o
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c
deleted file mode 100644
index 51af299..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2014 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Robert Baldyga <r.baldyga@samsung.com>
- *
- * based on arch/arm/cpu/armv7/omap3/cache.S
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- dcache_enable();
-}
-
-void disable_caches(void)
-{
- dcache_disable();
-}
-#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
-{
- __asm(
- "push {r0, r1, r2, lr}\n\t"
- "mrc 15, 0, r3, cr1, cr0, 1\n\t"
- "orr r3, r3, #2\n\t"
- "mcr 15, 0, r3, cr1, cr0, 1\n\t"
- "pop {r1, r2, r3, pc}"
- );
-}
-
-void v7_outer_cache_disable(void)
-{
- __asm(
- "push {r0, r1, r2, lr}\n\t"
- "mrc 15, 0, r3, cr1, cr0, 1\n\t"
- "bic r3, r3, #2\n\t"
- "mcr 15, 0, r3, cr1, cr0, 1\n\t"
- "pop {r1, r2, r3, pc}"
- );
-}
-#endif
diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
deleted file mode 100644
index 3da0071..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/clock.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-
-#define CLK_M 0
-#define CLK_D 1
-#define CLK_P 2
-
-#ifndef CONFIG_SYS_CLK_FREQ_C100
-#define CONFIG_SYS_CLK_FREQ_C100 12000000
-#endif
-#ifndef CONFIG_SYS_CLK_FREQ_C110
-#define CONFIG_SYS_CLK_FREQ_C110 24000000
-#endif
-
-/* s5pc110: return pll clock frequency */
-static unsigned long s5pc100_get_pll_clk(int pllreg)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, mask, fout;
- unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con);
- break;
- case MPLL:
- r = readl(&clk->mpll_con);
- break;
- case EPLL:
- r = readl(&clk->epll_con);
- break;
- case HPLL:
- r = readl(&clk->hpll_con);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [23:16]
- * EPLL_CON: MIDV [23:16]
- * HPLL_CON: MIDV [23:16]
- */
- if (pllreg == APLL)
- mask = 0x3ff;
- else
- mask = 0x0ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- freq = CONFIG_SYS_CLK_FREQ_C100;
- fout = m * (freq / (p * (1 << s)));
-
- return fout;
-}
-
-/* s5pc100: return pll clock frequency */
-static unsigned long s5pc110_get_pll_clk(int pllreg)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, mask, fout;
- unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con);
- break;
- case MPLL:
- r = readl(&clk->mpll_con);
- break;
- case EPLL:
- r = readl(&clk->epll_con);
- break;
- case VPLL:
- r = readl(&clk->vpll_con);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- */
- if (pllreg == APLL || pllreg == MPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ_C110;
- if (pllreg == APLL) {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
- } else
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- fout = m * (freq / (p * (1 << s)));
-
- return fout;
-}
-
-/* s5pc110: return ARM clock frequency */
-static unsigned long s5pc110_get_arm_clk(void)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long dout_apll, armclk;
- unsigned int apll_ratio;
-
- div = readl(&clk->div0);
-
- /* APLL_RATIO: [2:0] */
- apll_ratio = div & 0x7;
-
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
- armclk = dout_apll;
-
- return armclk;
-}
-
-/* s5pc100: return ARM clock frequency */
-static unsigned long s5pc100_get_arm_clk(void)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long dout_apll, armclk;
- unsigned int apll_ratio, arm_ratio;
-
- div = readl(&clk->div0);
-
- /* ARM_RATIO: [6:4] */
- arm_ratio = (div >> 4) & 0x7;
- /* APLL_RATIO: [0] */
- apll_ratio = div & 0x1;
-
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
- armclk = dout_apll / (arm_ratio + 1);
-
- return armclk;
-}
-
-/* s5pc100: return HCLKD0 frequency */
-static unsigned long get_hclk(void)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long hclkd0;
- uint div, d0_bus_ratio;
-
- div = readl(&clk->div0);
- /* D0_BUS_RATIO: [10:8] */
- d0_bus_ratio = (div >> 8) & 0x7;
-
- hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
-
- return hclkd0;
-}
-
-/* s5pc100: return PCLKD1 frequency */
-static unsigned long get_pclkd1(void)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long d1_bus, pclkd1;
- uint div, d1_bus_ratio, pclkd1_ratio;
-
- div = readl(&clk->div0);
- /* D1_BUS_RATIO: [14:12] */
- d1_bus_ratio = (div >> 12) & 0x7;
- /* PCLKD1_RATIO: [18:16] */
- pclkd1_ratio = (div >> 16) & 0x7;
-
- /* ASYNC Mode */
- d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
- pclkd1 = d1_bus / (pclkd1_ratio + 1);
-
- return pclkd1;
-}
-
-/* s5pc110: return HCLKs frequency */
-static unsigned long get_hclk_sys(int dom)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long hclk;
- unsigned int div;
- unsigned int offset;
- unsigned int hclk_sys_ratio;
-
- if (dom == CLK_M)
- return get_hclk();
-
- div = readl(&clk->div0);
-
- /*
- * HCLK_MSYS_RATIO: [10:8]
- * HCLK_DSYS_RATIO: [19:16]
- * HCLK_PSYS_RATIO: [27:24]
- */
- offset = 8 + (dom << 0x3);
-
- hclk_sys_ratio = (div >> offset) & 0xf;
-
- hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
-
- return hclk;
-}
-
-/* s5pc110: return PCLKs frequency */
-static unsigned long get_pclk_sys(int dom)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long pclk;
- unsigned int div;
- unsigned int offset;
- unsigned int pclk_sys_ratio;
-
- div = readl(&clk->div0);
-
- /*
- * PCLK_MSYS_RATIO: [14:12]
- * PCLK_DSYS_RATIO: [22:20]
- * PCLK_PSYS_RATIO: [30:28]
- */
- offset = 12 + (dom << 0x3);
-
- pclk_sys_ratio = (div >> offset) & 0x7;
-
- pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
-
- return pclk;
-}
-
-/* s5pc110: return peripheral clock frequency */
-static unsigned long s5pc110_get_pclk(void)
-{
- return get_pclk_sys(CLK_P);
-}
-
-/* s5pc100: return peripheral clock frequency */
-static unsigned long s5pc100_get_pclk(void)
-{
- return get_pclkd1();
-}
-
-/* s5pc1xx: return uart clock frequency */
-static unsigned long s5pc1xx_get_uart_clk(int dev_index)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_pclk();
- else
- return s5pc100_get_pclk();
-}
-
-/* s5pc1xx: return pwm clock frequency */
-static unsigned long s5pc1xx_get_pwm_clk(void)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_pclk();
- else
- return s5pc100_get_pclk();
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_pll_clk(pllreg);
- else
- return s5pc100_get_pll_clk(pllreg);
-}
-
-unsigned long get_arm_clk(void)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_arm_clk();
- else
- return s5pc100_get_arm_clk();
-}
-
-unsigned long get_pwm_clk(void)
-{
- return s5pc1xx_get_pwm_clk();
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
- return s5pc1xx_get_uart_clk(dev_index);
-}
-
-void set_mmc_clk(int dev_index, unsigned int div)
-{
- /* Do NOTHING */
-}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
deleted file mode 100644
index bd74f2b..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/reset.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/cpu.h>
-#include <linux/linkage.h>
-
-#define S5PC100_SWRESET 0xE0200000
-#define S5PC110_SWRESET 0xE0102000
-
-ENTRY(reset_cpu)
- ldr r1, =S5PC100_PRO_ID
- ldr r2, [r1]
- ldr r4, =0x00010000
- and r4, r2, r4
- cmp r4, #0
- bne 110f
- /* S5PC100 */
- ldr r1, =S5PC100_SWRESET
- ldr r2, =0xC100
- b 200f
-110: /* S5PC110 */
- ldr r1, =S5PC110_SWRESET
- mov r2, #1
-200:
- str r2, [r1]
-_loop_forever:
- b _loop_forever
-ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/sctlr.S b/arch/arm/cpu/armv7/sctlr.S
new file mode 100644
index 0000000..bd56e41
--- /dev/null
+++ b/arch/arm/cpu/armv7/sctlr.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Routines to access the system control register
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * void allow_unaligned(void) - allow unaligned access
+ *
+ * This routine clears the aligned flag in the system control register.
+ * After calling this routine unaligned access does no longer lead to a
+ * data abort but is handled by the CPU.
+ */
+ENTRY(allow_unaligned)
+ mrc p15, 0, r0, c1, c0, 0 @ load system control register
+ bic r0, r0, #2 @ clear aligned flag
+ mcr p15, 0, r0, c1, c0, 0 @ write system control register
+ bx lr @ return
+ENDPROC(allow_unaligned)
diff --git a/arch/arm/cpu/armv7/smccc-call.S b/arch/arm/cpu/armv7/smccc-call.S
new file mode 100644
index 0000000..eae69e3
--- /dev/null
+++ b/arch/arm/cpu/armv7/smccc-call.S
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015, Linaro Limited
+ */
+#include <linux/linkage.h>
+
+#include <asm/opcodes-sec.h>
+#include <asm/opcodes-virt.h>
+
+ .section .text.efi_runtime
+
+#define UNWIND(x...)
+ /*
+ * Wrap c macros in asm macros to delay expansion until after the
+ * SMCCC asm macro is expanded.
+ */
+ .macro SMCCC_SMC
+ __SMC(0)
+ .endm
+
+ .macro SMCCC_HVC
+ __HVC(0)
+ .endm
+
+ .macro SMCCC instr
+UNWIND( .fnstart)
+ mov r12, sp
+ push {r4-r7}
+UNWIND( .save {r4-r7})
+ ldm r12, {r4-r7}
+ \instr
+ pop {r4-r7}
+ ldr r12, [sp, #(4 * 4)]
+ stm r12, {r0-r3}
+ bx lr
+UNWIND( .fnend)
+ .endm
+
+/*
+ * void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
+ * unsigned long a3, unsigned long a4, unsigned long a5,
+ * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
+ * struct arm_smccc_quirk *quirk)
+ */
+ENTRY(__arm_smccc_smc)
+ SMCCC SMCCC_SMC
+ENDPROC(__arm_smccc_smc)
+
+/*
+ * void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
+ * unsigned long a3, unsigned long a4, unsigned long a5,
+ * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
+ * struct arm_smccc_quirk *quirk)
+ */
+ENTRY(__arm_smccc_hvc)
+ SMCCC SMCCC_HVC
+ENDPROC(__arm_smccc_hvc)
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
deleted file mode 100644
index 8b6e108..0000000
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2012 Altera Corporation <www.altera.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
- fpga_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
deleted file mode 100644
index fa3b93a..0000000
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ /dev/null
@@ -1,560 +0,0 @@
-/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
-static void cm_wait_for_lock(uint32_t mask)
-{
- register uint32_t inter_val;
- uint32_t retry = 0;
- do {
- inter_val = readl(&clock_manager_base->inter) & mask;
- if (inter_val == mask)
- retry++;
- else
- retry = 0;
- if (retry >= 10)
- break;
- } while (1);
-}
-
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
- while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
- ;
-}
-
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
- writel(val, &clock_manager_base->bypass);
- cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
- writel(val, &clock_manager_base->ctrl);
- cm_wait_for_fsm();
-}
-
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
- uint32_t reg_address, uint32_t mask)
-{
- /* poll until phase is zero */
- while (readl(reg_address) & mask)
- ;
-
- writel(value, reg_address);
-
- while (readl(reg_address) & mask)
- ;
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * Assert/deassert outreset all.
- * Take all pll's out of bypass
- * Clear safe mode
- * set source main and peripheral clocks
- * Ungate clocks
- */
-
-void cm_basic_init(const cm_config_t *cfg)
-{
- uint32_t start, timeout;
-
- /* Start by being paranoid and gate all sw managed clocks */
-
- /*
- * We need to disable nandclk
- * and then do another apb access before disabling
- * gatting off the rest of the periperal clocks.
- */
- writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
- readl(&clock_manager_base->per_pll.en),
- &clock_manager_base->per_pll.en);
-
- /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
- writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
- CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
- CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
- CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
- CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
- CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
- &clock_manager_base->main_pll.en);
-
- writel(0, &clock_manager_base->sdr_pll.en);
-
- /* now we can gate off the rest of the peripheral clocks */
- writel(0, &clock_manager_base->per_pll.en);
-
- /* Put all plls in bypass */
- cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
- CLKMGR_BYPASS_MAINPLL);
-
- /* Put all plls VCO registers back to reset value. */
- writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
- ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->main_pll.vco);
- writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
- ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->per_pll.vco);
- writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
- ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->sdr_pll.vco);
-
- /*
- * The clocks to the flash devices and the L4_MAIN clocks can
- * glitch when coming out of safe mode if their source values
- * are different from their reset value. So the trick it to
- * put them back to their reset state, and change input
- * after exiting safe mode but before ungating the clocks.
- */
- writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
- &clock_manager_base->per_pll.src);
- writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
- &clock_manager_base->main_pll.l4src);
-
- /* read back for the required 5 us delay. */
- readl(&clock_manager_base->main_pll.vco);
- readl(&clock_manager_base->per_pll.vco);
- readl(&clock_manager_base->sdr_pll.vco);
-
-
- /*
- * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
- * with numerator and denominator.
- */
- writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
- writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
- writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
-
- /*
- * Time starts here
- * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
- */
- start = get_timer(0);
- /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
- timeout = 7;
-
- /* main mpu */
- writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
-
- /* main main clock */
- writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
-
- /* main for dbg */
- writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
-
- /* main for cfgs2fuser0clk */
- writel(cfg->cfg2fuser0clk,
- &clock_manager_base->main_pll.cfgs2fuser0clk);
-
- /* Peri emac0 50 MHz default to RMII */
- writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
-
- /* Peri emac1 50 MHz default to RMII */
- writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
-
- /* Peri QSPI */
- writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
-
- writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
-
- /* Peri pernandsdmmcclk */
- writel(cfg->mainnandsdmmcclk,
- &clock_manager_base->main_pll.mainnandsdmmcclk);
-
- writel(cfg->pernandsdmmcclk,
- &clock_manager_base->per_pll.pernandsdmmcclk);
-
- /* Peri perbaseclk */
- writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
-
- /* Peri s2fuser1clk */
- writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
-
- /* 7 us must have elapsed before we can enable the VCO */
- while (get_timer(start) < timeout)
- ;
-
- /* Enable vco */
- /* main pll vco */
- writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->main_pll.vco);
-
- /* periferal pll */
- writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->per_pll.vco);
-
- /* sdram pll vco */
- writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->sdr_pll.vco);
-
- /* L3 MP and L3 SP */
- writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
-
- writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
-
- writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
-
- /* L4 MP, L4 SP, can0, and can1 */
- writel(cfg->perdiv, &clock_manager_base->per_pll.div);
-
- writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
-
-#define LOCKED_MASK \
- (CLKMGR_INTER_SDRPLLLOCKED_MASK | \
- CLKMGR_INTER_PERPLLLOCKED_MASK | \
- CLKMGR_INTER_MAINPLLLOCKED_MASK)
-
- cm_wait_for_lock(LOCKED_MASK);
-
- /* write the sdram clock counters before toggling outreset all */
- writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
- &clock_manager_base->sdr_pll.ddrdqsclk);
-
- writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
- &clock_manager_base->sdr_pll.ddr2xdqsclk);
-
- writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
- &clock_manager_base->sdr_pll.ddrdqclk);
-
- writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
- &clock_manager_base->sdr_pll.s2fuser2clk);
-
- /*
- * after locking, but before taking out of bypass
- * assert/deassert outresetall
- */
- uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
-
- /* assert main outresetall */
- writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->main_pll.vco);
-
- uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
-
- /* assert pheriph outresetall */
- writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->per_pll.vco);
-
- /* assert sdram outresetall */
- writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
- &clock_manager_base->sdr_pll.vco);
-
- /* deassert main outresetall */
- writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->main_pll.vco);
-
- /* deassert pheriph outresetall */
- writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->per_pll.vco);
-
- /* deassert sdram outresetall */
- writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->sdr_pll.vco);
-
- /*
- * now that we've toggled outreset all, all the clocks
- * are aligned nicely; so we can change any phase.
- */
- cm_write_with_phase(cfg->ddrdqsclk,
- (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
-
- /* SDRAM DDR2XDQSCLK */
- cm_write_with_phase(cfg->ddr2xdqsclk,
- (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
-
- cm_write_with_phase(cfg->ddrdqclk,
- (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
-
- cm_write_with_phase(cfg->s2fuser2clk,
- (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
-
- /* Take all three PLLs out of bypass when safe mode is cleared. */
- cm_write_bypass(0);
-
- /* clear safe mode */
- cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
-
- /*
- * now that safe mode is clear with clocks gated
- * it safe to change the source mux for the flashes the the L4_MAIN
- */
- writel(cfg->persrc, &clock_manager_base->per_pll.src);
- writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
-
- /* Now ungate non-hw-managed clocks */
- writel(~0, &clock_manager_base->main_pll.en);
- writel(~0, &clock_manager_base->per_pll.en);
- writel(~0, &clock_manager_base->sdr_pll.en);
-
- /* Clear the loss of lock bits (write 1 to clear) */
- writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
- CLKMGR_INTER_MAINPLLLOST_MASK,
- &clock_manager_base->inter);
-}
-
-static unsigned int cm_get_main_vco_clk_hz(void)
-{
- uint32_t reg, clock;
-
- /* get the main VCO clock */
- reg = readl(&clock_manager_base->main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ;
- clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
- CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
- clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
- CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
-
- return clock;
-}
-
-static unsigned int cm_get_per_vco_clk_hz(void)
-{
- uint32_t reg, clock = 0;
-
- /* identify PER PLL clock source */
- reg = readl(&clock_manager_base->per_pll.vco);
- reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
- CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
- if (reg == CLKMGR_VCO_SSRC_EOSC1)
- clock = CONFIG_HPS_CLK_OSC1_HZ;
- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
- clock = CONFIG_HPS_CLK_OSC2_HZ;
- else if (reg == CLKMGR_VCO_SSRC_F2S)
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-
- /* get the PER VCO clock */
- reg = readl(&clock_manager_base->per_pll.vco);
- clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
- CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
- clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
- CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
-
- return clock;
-}
-
-unsigned long cm_get_mpu_clk_hz(void)
-{
- uint32_t reg, clock;
-
- clock = cm_get_main_vco_clk_hz();
-
- /* get the MPU clock */
- reg = readl(&clock_manager_base->altera.mpuclk);
- clock /= (reg + 1);
- reg = readl(&clock_manager_base->main_pll.mpuclk);
- clock /= (reg + 1);
- return clock;
-}
-
-unsigned long cm_get_sdram_clk_hz(void)
-{
- uint32_t reg, clock = 0;
-
- /* identify SDRAM PLL clock source */
- reg = readl(&clock_manager_base->sdr_pll.vco);
- reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
- CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
- if (reg == CLKMGR_VCO_SSRC_EOSC1)
- clock = CONFIG_HPS_CLK_OSC1_HZ;
- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
- clock = CONFIG_HPS_CLK_OSC2_HZ;
- else if (reg == CLKMGR_VCO_SSRC_F2S)
- clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
-
- /* get the SDRAM VCO clock */
- reg = readl(&clock_manager_base->sdr_pll.vco);
- clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
- CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
- clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
- CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
-
- /* get the SDRAM (DDR_DQS) clock */
- reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
- reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
- clock /= (reg + 1);
-
- return clock;
-}
-
-unsigned int cm_get_l4_sp_clk_hz(void)
-{
- uint32_t reg, clock = 0;
-
- /* identify the source of L4 SP clock */
- reg = readl(&clock_manager_base->main_pll.l4src);
- reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
- CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
-
- if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
- clock = cm_get_main_vco_clk_hz();
-
- /* get the clock prior L4 SP divider (main clk) */
- reg = readl(&clock_manager_base->altera.mainclk);
- clock /= (reg + 1);
- reg = readl(&clock_manager_base->main_pll.mainclk);
- clock /= (reg + 1);
- } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
- clock = cm_get_per_vco_clk_hz();
-
- /* get the clock prior L4 SP divider (periph_base_clk) */
- reg = readl(&clock_manager_base->per_pll.perbaseclk);
- clock /= (reg + 1);
- }
-
- /* get the L4 SP clock which supplied to UART */
- reg = readl(&clock_manager_base->main_pll.maindiv);
- reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
- clock = clock / (1 << reg);
-
- return clock;
-}
-
-unsigned int cm_get_mmc_controller_clk_hz(void)
-{
- uint32_t reg, clock = 0;
-
- /* identify the source of MMC clock */
- reg = readl(&clock_manager_base->per_pll.src);
- reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
- CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
-
- if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
- } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
- clock = cm_get_main_vco_clk_hz();
-
- /* get the SDMMC clock */
- reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
- clock /= (reg + 1);
- } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
- clock = cm_get_per_vco_clk_hz();
-
- /* get the SDMMC clock */
- reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
- clock /= (reg + 1);
- }
-
- /* further divide by 4 as we have fixed divider at wrapper */
- clock /= 4;
- return clock;
-}
-
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
- uint32_t reg, clock = 0;
-
- /* identify the source of QSPI clock */
- reg = readl(&clock_manager_base->per_pll.src);
- reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
- CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
-
- if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
- } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
- clock = cm_get_main_vco_clk_hz();
-
- /* get the qspi clock */
- reg = readl(&clock_manager_base->main_pll.mainqspiclk);
- clock /= (reg + 1);
- } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
- clock = cm_get_per_vco_clk_hz();
-
- /* get the qspi clock */
- reg = readl(&clock_manager_base->per_pll.perqspiclk);
- clock /= (reg + 1);
- }
-
- return clock;
-}
-
-unsigned int cm_get_spi_controller_clk_hz(void)
-{
- uint32_t reg, clock = 0;
-
- clock = cm_get_per_vco_clk_hz();
-
- /* get the clock prior L4 SP divider (periph_base_clk) */
- reg = readl(&clock_manager_base->per_pll.perbaseclk);
- clock /= (reg + 1);
-
- return clock;
-}
-
-static void cm_print_clock_quick_summary(void)
-{
- printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
- printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
- printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
- printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
- printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
- printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
- printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
- printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
- printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
- printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
-}
-
-int set_cpu_clk_info(void)
-{
- /* Calculate the clock frequencies required for drivers */
- cm_get_l4_sp_clk_hz();
- cm_get_mmc_controller_clk_hz();
-
- gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
- gd->bd->bi_dsp_freq = 0;
- gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-
- return 0;
-}
-
-int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- cm_print_clock_quick_summary();
- return 0;
-}
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
- "display clocks",
- ""
-);
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
deleted file mode 100644
index 2a99c72..0000000
--- a/arch/arm/cpu/armv7/socfpga/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot.img
-endif
-
-# Added for handoff support
-PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD)
diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
deleted file mode 100644
index 43fd2fe..0000000
--- a/arch/arm/cpu/armv7/socfpga/fpga_manager.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- * All rights reserved.
- *
- * This file contains only support functions used also by the SoCFPGA
- * platform code, the real meat is located in drivers/fpga/socfpga.c .
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/fpga_manager.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
-
-static struct socfpga_fpga_manager *fpgamgr_regs =
- (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-
-/* Check whether FPGA Init_Done signal is high */
-static int is_fpgamgr_initdone_high(void)
-{
- unsigned long val;
-
- val = readl(&fpgamgr_regs->gpio_ext_porta);
- return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
-}
-
-/* Get the FPGA mode */
-int fpgamgr_get_mode(void)
-{
- unsigned long val;
-
- val = readl(&fpgamgr_regs->stat);
- return val & FPGAMGRREGS_STAT_MODE_MASK;
-}
-
-/* Check whether FPGA is ready to be accessed */
-int fpgamgr_test_fpga_ready(void)
-{
- /* Check for init done signal */
- if (!is_fpgamgr_initdone_high())
- return 0;
-
- /* Check again to avoid false glitches */
- if (!is_fpgamgr_initdone_high())
- return 0;
-
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
- return 0;
-
- return 1;
-}
-
-/* Poll until FPGA is ready to be accessed or timeout occurred */
-int fpgamgr_poll_fpga_ready(void)
-{
- unsigned long i;
-
- /* If FPGA is blank, wait till WD invoke warm reset */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- /* check for init done signal */
- if (!is_fpgamgr_initdone_high())
- continue;
- /* check again to avoid false glitches */
- if (!is_fpgamgr_initdone_high())
- continue;
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
deleted file mode 100644
index 0be643c..0000000
--- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/freeze_controller.h>
-#include <asm/arch/timer.h>
-#include <asm/errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct socfpga_freeze_controller *freeze_controller_base =
- (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
-
-/*
- * Default state from cold reset is FREEZE_ALL; the global
- * flag is set to TRUE to indicate the IO banks are frozen
- */
-static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
- = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
- FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
-
-/* Freeze HPS IOs */
-void sys_mgr_frzctrl_freeze_req(void)
-{
- u32 ioctrl_reg_offset;
- u32 reg_value;
- u32 reg_cfg_mask;
- u32 channel_id;
-
- /* select software FSM */
- writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
-
- /* Freeze channel 0 to 2 */
- for (channel_id = 0; channel_id <= 2; channel_id++) {
- ioctrl_reg_offset = (u32)(
- &freeze_controller_base->vioctrl + channel_id);
-
- /*
- * Assert active low enrnsl, plniotri
- * and niotri signals
- */
- reg_cfg_mask =
- SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
- | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
- | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
- clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
-
- /*
- * Note: Delay for 20ns at min
- * Assert active low bhniotri signal and de-assert
- * active high csrdone
- */
- reg_cfg_mask
- = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
- | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
- clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
-
- /* Set global flag to indicate channel is frozen */
- frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
- }
-
- /* Freeze channel 3 */
- /*
- * Assert active low enrnsl, plniotri and
- * niotri signals
- */
- reg_cfg_mask
- = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
- | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
- | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
- clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
-
- /*
- * assert active low bhniotri & nfrzdrv signals,
- * de-assert active high csrdone and assert
- * active high frzreg and nfrzdrv signals
- */
- reg_value = readl(&freeze_controller_base->hioctrl);
- reg_cfg_mask
- = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
- | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
- reg_value
- = (reg_value & ~reg_cfg_mask)
- | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
- | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
- writel(reg_value, &freeze_controller_base->hioctrl);
-
- /*
- * assert active high reinit signal and de-assert
- * active high pllbiasen signals
- */
- reg_value = readl(&freeze_controller_base->hioctrl);
- reg_value
- = (reg_value &
- ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
- | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
- writel(reg_value, &freeze_controller_base->hioctrl);
-
- /* Set global flag to indicate channel is frozen */
- frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
-}
-
-/* Unfreeze/Thaw HPS IOs */
-void sys_mgr_frzctrl_thaw_req(void)
-{
- u32 ioctrl_reg_offset;
- u32 reg_cfg_mask;
- u32 reg_value;
- u32 channel_id;
-
- /* select software FSM */
- writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
-
- /* Thaw channel 0 to 2 */
- for (channel_id = 0; channel_id <= 2; channel_id++) {
- ioctrl_reg_offset
- = (u32)(&freeze_controller_base->vioctrl + channel_id);
-
- /*
- * Assert active low bhniotri signal and
- * de-assert active high csrdone
- */
- reg_cfg_mask
- = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
- | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
- setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
-
- /*
- * Note: Delay for 20ns at min
- * de-assert active low plniotri and niotri signals
- */
- reg_cfg_mask
- = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
- | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
- setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
-
- /*
- * Note: Delay for 20ns at min
- * de-assert active low enrnsl signal
- */
- setbits_le32(ioctrl_reg_offset,
- SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
-
- /* Set global flag to indicate channel is thawed */
- frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
- }
-
- /* Thaw channel 3 */
- /* de-assert active high reinit signal */
- clrbits_le32(&freeze_controller_base->hioctrl,
- SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
-
- /*
- * Note: Delay for 40ns at min
- * assert active high pllbiasen signals
- */
- setbits_le32(&freeze_controller_base->hioctrl,
- SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
-
- /*
- * Delay 1000 intosc. intosc is based on eosc1
- * Use worst case which is fatest eosc1=50MHz, delay required
- * is 1/50MHz * 1000 = 20us
- */
- udelay(20);
-
- /*
- * de-assert active low bhniotri signals,
- * assert active high csrdone and nfrzdrv signal
- */
- reg_value = readl(&freeze_controller_base->hioctrl);
- reg_value = (reg_value
- | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
- | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
- & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
- writel(reg_value, &freeze_controller_base->hioctrl);
-
- /*
- * Delay 33 intosc
- * Use worst case which is fatest eosc1=50MHz, delay required
- * is 1/50MHz * 33 = 660ns ~= 1us
- */
- udelay(1);
-
- /* de-assert active low plniotri and niotri signals */
- reg_cfg_mask
- = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
- | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
-
- setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
-
- /*
- * Note: Delay for 40ns at min
- * de-assert active high frzreg signal
- */
- clrbits_le32(&freeze_controller_base->hioctrl,
- SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
-
- /*
- * Note: Delay for 40ns at min
- * de-assert active low enrnsl signal
- */
- setbits_le32(&freeze_controller_base->hioctrl,
- SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
-
- /* Set global flag to indicate channel is thawed */
- frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
-}
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
deleted file mode 100644
index afed773..0000000
--- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
- /* Remap */
-#ifdef CONFIG_SPL_BUILD
- /*
- * SPL : configure the remap (L3 NIC-301 GPV)
- * so the on-chip RAM at lower memory instead ROM.
- */
- ldr r0, =SOCFPGA_L3REGS_ADDRESS
- mov r1, #0x19
- str r1, [r0]
-#else
- /*
- * U-Boot : configure the remap (L3 NIC-301 GPV)
- * so the SDRAM at lower memory instead on-chip RAM.
- */
- ldr r0, =SOCFPGA_L3REGS_ADDRESS
- mov r1, #0x2
- str r1, [r0]
-
- /* Private components security */
-
- /*
- * U-Boot : configure private timer, global timer and cpu
- * component access as non secure for kernel stage (as required
- * by kernel)
- */
- mrc p15,4,r0,c15,c0,0
- add r1, r0, #0x54
- ldr r2, [r1]
- orr r2, r2, #0xff
- orr r2, r2, #0xf00
- str r2, [r1]
-#endif /* #ifdef CONFIG_SPL_BUILD */
- mov pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
deleted file mode 100644
index 7873c38..0000000
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <altera.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <watchdog.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
-#include <asm/arch/dwmmc.h>
-#include <asm/arch/nic301.h>
-#include <asm/arch/scu.h>
-#include <asm/pl310.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
- (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-static struct nic301_registers *nic301_regs =
- (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct scu_registers *scu_regs =
- (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_DESIGNWARE_ETH
-int cpu_eth_init(bd_t *bis)
-{
-#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
- const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
- const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-#else
-#error "Incorrect CONFIG_EMAC_BASE value!"
-#endif
-
- /* Initialize EMAC. This needs to be done at least once per boot. */
-
- /*
- * Putting the EMAC controller to reset when configuring the PHY
- * interface select at System Manager
- */
- socfpga_emac_reset(1);
-
- /* Clearing emac0 PHY interface select to 0 */
- clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
- /* configure to PHY interface select choosed */
- setbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
-
- /* Release the EMAC controller from reset */
- socfpga_emac_reset(0);
-
- /* initialize and register the emac */
- return designware_initialize(CONFIG_EMAC_BASE,
- CONFIG_PHY_INTERFACE_MODE);
-}
-#endif
-
-#ifdef CONFIG_DWMMC
-/*
- * Initializes MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
- return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
- CONFIG_HPS_SDMMC_BUSWIDTH, 0);
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- puts("CPU: Altera SoCFPGA Platform\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
-defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
- {
- /* Family */
- Altera_SoCFPGA,
- /* Interface type */
- fast_passive_parallel,
- /* No limitation as additional data will be ignored */
- -1,
- /* No device function table */
- NULL,
- /* Base interface address specified in driver */
- NULL,
- /* No cookie implementation */
- 0
- },
-};
-
-/* add device descriptor to FPGA device table */
-static void socfpga_fpga_add(void)
-{
- int i;
- fpga_init();
- for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
- fpga_add(fpga_altera, &altera_fpga[i]);
-}
-#else
-static inline void socfpga_fpga_add(void) {}
-#endif
-
-int arch_cpu_init(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
- /*
- * In case the watchdog is enabled, make sure to (re-)configure it
- * so that the defined timeout is valid. Otherwise the SPL (Perloader)
- * timeout value is still active which might too short for Linux
- * booting.
- */
- hw_watchdog_init();
-#else
- /*
- * If the HW watchdog is NOT enabled, make sure it is not running,
- * for example because it was enabled in the preloader. This might
- * trigger a watchdog-triggered reboot of Linux kernel later.
- */
- socfpga_watchdog_reset();
-#endif
-
- return 0;
-}
-
-/*
- * Convert all NIC-301 AMBA slaves from secure to non-secure
- */
-static void socfpga_nic301_slave_ns(void)
-{
- writel(0x1, &nic301_regs->lwhps2fpgaregs);
- writel(0x1, &nic301_regs->hps2fpgaregs);
- writel(0x1, &nic301_regs->acp);
- writel(0x1, &nic301_regs->rom);
- writel(0x1, &nic301_regs->ocram);
- writel(0x1, &nic301_regs->sdrdata);
-}
-
-static uint32_t iswgrp_handoff[8];
-
-int arch_early_init_r(void)
-{
- int i;
- for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
- iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
-
- socfpga_bridges_reset(1);
- socfpga_nic301_slave_ns();
-
- /*
- * Private components security:
- * U-Boot : configure private timer, global timer and cpu component
- * access as non secure for kernel stage (as required by Linux)
- */
- setbits_le32(&scu_regs->sacr, 0xfff);
-
- /* Configure the L2 controller to make SDRAM start at 0 */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
- writel(0x2, &nic301_regs->remap);
-#else
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
- writel(0x1, &pl310->pl310_addr_filter_start);
-#endif
-
- /* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
-
-#ifdef CONFIG_DESIGNWARE_SPI
- /* Get Designware SPI controller out of reset */
- socfpga_spim_enable();
-#endif
-
- return 0;
-}
-
-static void socfpga_sdram_apply_static_cfg(void)
-{
- const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
- const uint32_t applymask = 0x8;
- uint32_t val = readl(staticcfg) | applymask;
-
- /*
- * SDRAM staticcfg register specific:
- * When applying the register setting, the CPU must not access
- * SDRAM. Luckily for us, we can abuse i-cache here to help us
- * circumvent the SDRAM access issue. The idea is to make sure
- * that the code is in one full i-cache line by branching past
- * it and back. Once it is in the i-cache, we execute the core
- * of the code and apply the register settings.
- *
- * The code below uses 7 instructions, while the Cortex-A9 has
- * 32-byte cachelines, thus the limit is 8 instructions total.
- */
- asm volatile(
- ".align 5 \n"
- " b 2f \n"
- "1: str %0, [%1] \n"
- " dsb \n"
- " isb \n"
- " b 3f \n"
- "2: b 1b \n"
- "3: nop \n"
- : : "r"(val), "r"(staticcfg) : "memory", "cc");
-}
-
-int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 2)
- return CMD_RET_USAGE;
-
- argv++;
-
- switch (*argv[0]) {
- case 'e': /* Enable */
- writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
- socfpga_sdram_apply_static_cfg();
- writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
- writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
- writel(iswgrp_handoff[1], &nic301_regs->remap);
- break;
- case 'd': /* Disable */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
- writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
- socfpga_sdram_apply_static_cfg();
- writel(0, &reset_manager_base->brg_mod_reset);
- writel(1, &nic301_regs->remap);
- break;
- default:
- return CMD_RET_USAGE;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- bridge, 2, 1, do_bridge,
- "SoCFPGA HPS FPGA bridge control",
- "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
- "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
- ""
-);
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
deleted file mode 100644
index 25921e7..0000000
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/fpga_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
-void socfpga_watchdog_reset(void)
-{
- /* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_PERMODRST_L4WD0_LSB);
-
- /* deassert watchdog from reset (watchdog in not running state) */
- clrbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_PERMODRST_L4WD0_LSB);
-}
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
- /* request a warm reset */
- writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
- &reset_manager_base->ctrl);
- /*
- * infinite loop here as watchdog will trigger and reset
- * the processor
- */
- while (1)
- ;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, &reset_manager_base->per_mod_reset);
-}
-
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
- /* For SoCFPGA-VT, this is NOP. */
-}
-#else
-
-#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
-#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
-#define L3REGS_REMAP_OCRAM_MASK 0x01
-
-void socfpga_bridges_reset(int enable)
-{
- const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
- L3REGS_REMAP_HPS2FPGA_MASK |
- L3REGS_REMAP_OCRAM_MASK;
-
- if (enable) {
- /* brdmodrst */
- writel(0xffffffff, &reset_manager_base->brg_mod_reset);
- } else {
- /* Check signal from FPGA. */
- if (fpgamgr_poll_fpga_ready()) {
- /* FPGA not ready. Wait for watchdog timeout. */
- printf("%s: fpga not ready, hanging.\n", __func__);
- hang();
- }
-
- /* brdmodrst */
- writel(0, &reset_manager_base->brg_mod_reset);
-
- /* Remap the bridges into memory map */
- writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
- }
-}
-#endif
-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- if (enable) {
- setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
- setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
- } else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
-#endif
- }
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
- (1 << RSTMGR_PERMODRST_SPIM1_LSB));
-}
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c
deleted file mode 100644
index a820b1b..0000000
--- a/arch/arm/cpu/armv7/socfpga/scan_manager.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/freeze_controller.h>
-#include <asm/arch/scan_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct socfpga_scan_manager *scan_manager_base =
- (void *)(SOCFPGA_SCANMGR_ADDRESS);
-static const struct socfpga_freeze_controller *freeze_controller_base =
- (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
-
-/*
- * Function to check IO scan chain engine status and wait if the engine is
- * is active. Poll the IO scan chain engine till maximum iteration reached.
- */
-static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
-{
- uint32_t scanmgr_status;
-
- scanmgr_status = readl(&scan_manager_base->stat);
-
- /* Poll the engine until the scan engine is inactive */
- while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
- (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
- max_iter--;
- if (max_iter > 0)
- scanmgr_status = readl(&scan_manager_base->stat);
- else
- return 0;
- }
- return 1;
-}
-
-/* Program HPS IO Scan Chain */
-uint32_t scan_mgr_io_scan_chain_prg(
- uint32_t io_scan_chain_id,
- uint32_t io_scan_chain_len_in_bits,
- const uint32_t *iocsr_scan_chain)
-{
- uint16_t tdi_tdo_header;
- uint32_t io_program_iter;
- uint32_t io_scan_chain_data_residual;
- uint32_t residual;
- uint32_t i;
- uint32_t index = 0;
-
- /*
- * De-assert reinit if the IO scan chain is intended for HIO. In
- * this, its the chain 3.
- */
- if (io_scan_chain_id == 3)
- clrbits_le32(&freeze_controller_base->hioctrl,
- SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
-
- /*
- * Check if the scan chain engine is inactive and the
- * WFIFO is empty before enabling the IO scan chain
- */
- if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
- return 1;
-
- /*
- * Enable IO Scan chain based on scan chain id
- * Note: only one chain can be enabled at a time
- */
- setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
-
- /*
- * Calculate number of iteration needed for full 128-bit (4 x32-bits)
- * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
- */
- io_program_iter = io_scan_chain_len_in_bits >>
- IO_SCAN_CHAIN_128BIT_SHIFT;
- io_scan_chain_data_residual = io_scan_chain_len_in_bits &
- IO_SCAN_CHAIN_128BIT_MASK;
-
- /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
- tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
- (TDI_TDO_MAX_PAYLOAD << TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
-
- /* Program IO scan chain in 128-bit iteration */
- for (i = 0; i < io_program_iter; i++) {
- /* write TDI_TDO packet header to scan manager */
- writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte);
-
- /* calculate array index. Multiply by 4 as write 4 x 32bits */
- index = i * 4;
-
- /* write 4 successive 32-bit IO scan chain data into WFIFO */
- writel(iocsr_scan_chain[index],
- &scan_manager_base->fifo_quad_byte);
- writel(iocsr_scan_chain[index + 1],
- &scan_manager_base->fifo_quad_byte);
- writel(iocsr_scan_chain[index + 2],
- &scan_manager_base->fifo_quad_byte);
- writel(iocsr_scan_chain[index + 3],
- &scan_manager_base->fifo_quad_byte);
-
- /*
- * Check if the scan chain engine has completed the
- * IO scan chain data shifting
- */
- if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
- goto error;
- }
-
- /* Calculate array index for final TDI_TDO packet */
- index = io_program_iter * 4;
-
- /* Final TDI_TDO packet if any */
- if (io_scan_chain_data_residual) {
- /*
- * Calculate number of quad bytes FIFO write
- * needed for the final TDI_TDO packet
- */
- io_program_iter = io_scan_chain_data_residual >>
- IO_SCAN_CHAIN_32BIT_SHIFT;
-
- /*
- * Construct TDI_TDO packet for remaining IO
- * scan chain (2 bytes)
- */
- tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
- ((io_scan_chain_data_residual - 1) <<
- TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
-
- /*
- * Program the last part of IO scan chain write TDI_TDO packet
- * header (2 bytes) to scan manager
- */
- writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte);
-
- for (i = 0; i < io_program_iter; i++) {
- /*
- * write remaining scan chain data into scan
- * manager WFIFO with 4 bytes write
- */
- writel(iocsr_scan_chain[index + i],
- &scan_manager_base->fifo_quad_byte);
- }
-
- index += io_program_iter;
- residual = io_scan_chain_data_residual &
- IO_SCAN_CHAIN_32BIT_MASK;
-
- if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
- /*
- * write the last 4B scan chain data
- * into scan manager WFIFO
- */
- writel(iocsr_scan_chain[index],
- &scan_manager_base->fifo_quad_byte);
- } else {
- /*
- * write the remaining 1 - 3 bytes scan chain
- * data into scan manager WFIFO byte by byte
- * to prevent JTAG engine shifting unused data
- * from the FIFO and mistaken the data as a
- * valid command (even though unused bits are
- * set to 0, but just to prevent hardware
- * glitch)
- */
- for (i = 0; i < residual; i += 8) {
- writel(((iocsr_scan_chain[index] >> i)
- & IO_SCAN_CHAIN_BYTE_MASK),
- &scan_manager_base->fifo_single_byte);
- }
- }
-
- /*
- * Check if the scan chain engine has completed the
- * IO scan chain data shifting
- */
- if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
- goto error;
- }
-
- /* Disable IO Scan chain when configuration done*/
- clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
- return 0;
-
-error:
- /* Disable IO Scan chain when error detected */
- clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
- return 1;
-}
-
-int scan_mgr_configure_iocsr(void)
-{
- int status = 0;
-
- /* configure the IOCSR through scan chain */
- status |= scan_mgr_io_scan_chain_prg(0,
- CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table);
- status |= scan_mgr_io_scan_chain_prg(1,
- CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table);
- status |= scan_mgr_io_scan_chain_prg(2,
- CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table);
- status |= scan_mgr_io_scan_chain_prg(3,
- CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table);
- return status;
-}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
deleted file mode 100644
index bd9f338..0000000
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <version.h>
-#include <image.h>
-#include <asm/arch/reset_manager.h>
-#include <spl.h>
-#include <asm/arch/system_manager.h>
-#include <asm/arch/freeze_controller.h>
-#include <asm/arch/clock_manager.h>
-#include <asm/arch/scan_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MAIN_VCO_BASE ( \
- (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
- CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
- CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define PERI_VCO_BASE ( \
- (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
- CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
- CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
- CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define SDR_VCO_BASE ( \
- (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
- CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
- CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
- CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_RAM;
-}
-
-/*
- * Board initialization after bss clearance
- */
-void spl_board_init(void)
-{
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
- cm_config_t cm_default_cfg = {
- /* main group */
- MAIN_VCO_BASE,
- (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
- CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
- CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
- CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
- CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
- /* peripheral group */
- PERI_VCO_BASE,
- (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
- CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
- CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
- CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
- CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
- CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
- CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
- CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
- CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
- CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
- /* sdram pll group */
- SDR_VCO_BASE,
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
- };
-
- debug("Freezing all I/O banks\n");
- /* freeze all IO banks */
- sys_mgr_frzctrl_freeze_req();
-
- debug("Reconfigure Clock Manager\n");
- /* reconfigure the PLLs */
- cm_basic_init(&cm_default_cfg);
-
- /* configure the IOCSR / IO buffer settings */
- if (scan_mgr_configure_iocsr())
- hang();
-
- /* configure the pin muxing through system manager */
- sysmgr_pinmux_init();
-#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
-
- /* de-assert reset for peripherals and bridges based on handoff */
- reset_deassert_peripherals_handoff();
-
- debug("Unfreezing/Thaw all I/O banks\n");
- /* unfreeze / thaw all IO banks */
- sys_mgr_frzctrl_thaw_req();
-
- /* enable console uart printing */
- preloader_console_init();
-}
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
deleted file mode 100644
index 11f7bad..0000000
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/system_manager.h>
-#include <asm/arch/fpga_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
-/*
- * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
- * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
- * CONFIG_SYSMGR_ISWGRP_HANDOFF.
- */
-static void populate_sysmgr_fpgaintf_module(void)
-{
- uint32_t handoff_val = 0;
-
- /* ISWGRP_HANDOFF_FPGAINTF */
- writel(0, &sysmgr_regs->iswgrp_handoff[2]);
-
- /* Enable the signal for those HPS peripherals that use FPGA. */
- if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
- handoff_val |= SYSMGR_FPGAINTF_NAND;
- if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
- handoff_val |= SYSMGR_FPGAINTF_EMAC1;
- if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
- handoff_val |= SYSMGR_FPGAINTF_SDMMC;
- if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
- handoff_val |= SYSMGR_FPGAINTF_EMAC0;
- if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
- handoff_val |= SYSMGR_FPGAINTF_SPIM0;
- if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
- handoff_val |= SYSMGR_FPGAINTF_SPIM1;
-
- /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
- based on pinmux setting */
- setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
-
- handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
- if (fpgamgr_test_fpga_ready()) {
- /* Enable the required signals only */
- writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
- }
-}
-
-/*
- * Configure all the pin muxes
- */
-void sysmgr_pinmux_init(void)
-{
- uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
- int i;
-
- for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
- writel(sys_mgr_init_table[i], regs);
- regs += sizeof(regs);
- }
-
- populate_sysmgr_fpgaintf_module();
-}
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
deleted file mode 100644
index 253cde3..0000000
--- a/arch/arm/cpu/armv7/socfpga/timer.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer.h>
-
-#define TIMER_LOAD_VAL 0xFFFFFFFF
-
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
-
-/*
- * Timer initialization
- */
-int timer_init(void)
-{
- writel(TIMER_LOAD_VAL, &timer_base->load_val);
- writel(TIMER_LOAD_VAL, &timer_base->curr_val);
- writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
deleted file mode 100644
index 569fa41..0000000
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.vectors)
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- } >.sdram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss : {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fdc05b9..0cb6dd3 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
*
@@ -9,31 +10,45 @@
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
#include <asm/system.h>
#include <linux/linkage.h>
+#include <asm/armv7.h>
/*************************************************************************
*
* Startup Code (reset vector)
*
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
+ * Do important init only if we don't start from memory!
+ * Setup memory and board specific bits prior to relocation.
+ * Relocate armboot to ram. Setup stack.
*
*************************************************************************/
.globl reset
+ .globl save_boot_params_ret
+ .type save_boot_params_ret,%function
+#ifdef CONFIG_ARMV7_LPAE
+ .global switch_to_hypervisor_ret
+#endif
reset:
- bl save_boot_params
+ /* Allow the board to save important registers */
+ b save_boot_params
+save_boot_params_ret:
+#ifdef CONFIG_ARMV7_LPAE
+/*
+ * check for Hypervisor support
+ */
+ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
+ and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
+ cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+ beq switch_to_hypervisor
+switch_to_hypervisor_ret:
+#endif
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
@@ -52,21 +67,27 @@
* Continue to use ROM code vector only in OMAP4 spl)
*/
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
- /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
- mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
+ /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
+ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
bic r0, #CR_V @ V = 0
- mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
+ mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
+#ifdef CONFIG_HAS_VBAR
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
+#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_CPU_V7A
bl cpu_init_cp15
+#endif
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
bl cpu_init_crit
#endif
+#endif
bl _main
@@ -96,10 +117,17 @@
*
*************************************************************************/
ENTRY(save_boot_params)
- bx lr @ back to my caller
+ b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params
+#ifdef CONFIG_ARMV7_LPAE
+ENTRY(switch_to_hypervisor)
+ b switch_to_hypervisor_ret
+ENDPROC(switch_to_hypervisor)
+ .weak switch_to_hypervisor
+#endif
+
/*************************************************************************
*
* cpu_init_cp15
@@ -163,10 +191,137 @@
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
- mov pc, lr @ back to my caller
+#ifdef CONFIG_ARM_ERRATA_845369
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 22 @ set bit #22
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+ mov r5, lr @ Store my Caller
+ mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
+ mov r3, r1, lsr #20 @ get variant field
+ and r3, r3, #0xf @ r3 has CPU variant
+ and r4, r1, #0xf @ r4 has CPU revision
+ mov r2, r3, lsl #4 @ shift variant field for combined value
+ orr r2, r4, r2 @ r2 has combined CPU variant + revision
+
+/* Early stack for ERRATA that needs into call C code */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ ldr r0, =(CONFIG_SPL_STACK)
+#else
+ ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+ bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
+ mov sp, r0
+
+#ifdef CONFIG_ARM_ERRATA_798870
+ cmp r2, #0x30 @ Applies to lower than R3p0
+ bge skip_errata_798870 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_798870 @ skip if not affected rev
+
+ mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
+ orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_l2aux_ctrl
+ isb @ Recommended ISB after l2actlr update
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_801819
+ cmp r2, #0x24 @ Applies to lt including R2p4
+ bgt skip_errata_801819 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_801819 @ skip if not affected rev
+ mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
+ and r0, r0, #1 << 3 @ check REVIDR[3]
+ cmp r0, #1 << 3
+ beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
+
+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
+ orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
+ @ lines allocate in the L1 or L2 cache.
+ orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
+ @ lines allocate in the L1 cache.
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_801819:
+#endif
+
+#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
+ orr r0, r0, #1 << 0 @ Enable invalidates of BTB
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
+ cmp r2, #0x21 @ Only on < r2p1
+ orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+#endif
+
+#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715)
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
+#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715
+ orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA
+#else
+ cmp r2, #0x21 @ Only on < r2p1
+ orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
+#endif
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
+ cmp r2, #0x21 @ Only on < r2p1
+ orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
+
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_725233
+ mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
+
+ cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
+ orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
+
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_l2aux_ctrl
+ pop {r1-r5} @ Restore the cpu info - fall through
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_852421
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 24 @ set bit #24
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_852423
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 12 @ set bit #12
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+ mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers
diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile
index 95641d3..3be5eba 100644
--- a/arch/arm/cpu/armv7/stv0991/Makefile
+++ b/arch/arm/cpu/armv7/stv0991/Makefile
@@ -1,9 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
#
-# (C) Copyright 2014
-# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
+# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
obj-y := timer.o clock.o pinmux.o reset.o
obj-y += lowlevel.o
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c
index 70b8a8d..1e35dee 100644
--- a/arch/arm/cpu/armv7/stv0991/clock.c
+++ b/arch/arm/cpu/armv7/stv0991/clock.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <asm/io.h>
@@ -33,7 +32,9 @@
/* Clock selection for ethernet tx_clk & rx_clk*/
writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
| ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
-
+ break;
+ case QSPI_CLOCK_CFG:
+ writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
break;
default:
break;
diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S
index 6dafba3..218ac70 100644
--- a/arch/arm/cpu/armv7/stv0991/lowlevel.S
+++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 stmicroelectronics
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c
index 1d086a2..6c44ffe 100644
--- a/arch/arm/cpu/armv7/stv0991/pinmux.c
+++ b/arch/arm/cpu/armv7/stv0991/pinmux.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <asm/io.h>
@@ -55,6 +54,11 @@
ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
break;
+ case QSPI_CS_CLK_PAD:
+ writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
+ CFG_FLASH_CS_NC, &stv0991_creg->mux13);
+ writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
+ CFG_FLASH_CLK, &stv0991_creg->mux13);
default:
break;
}
diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c
index 3384b32..d4b3ab7 100644
--- a/arch/arm/cpu/armv7/stv0991/reset.c
+++ b/arch/arm/cpu/armv7/stv0991/reset.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
index 8654b8b..d1b763d 100644
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ b/arch/arm/cpu/armv7/stv0991/timer.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
@@ -22,6 +21,8 @@
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
+static ulong get_timer_masked(void);
+
int timer_init(void)
{
/* Timer1 clock configuration */
@@ -74,7 +75,7 @@
;
}
-ulong get_timer_masked(void)
+static ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
@@ -90,11 +91,6 @@
return timestamp;
}
-void udelay_masked(unsigned long usec)
-{
- return udelay(usec);
-}
-
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 3b6ae47..1d40d6a 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -1,38 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
#
# Based on some other Makefile
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
obj-y += timer.o
-obj-y += board.o
-obj-y += clock.o
-obj-y += pinmux.o
-obj-$(CONFIG_MACH_SUN6I) += prcm.o
-obj-$(CONFIG_MACH_SUN8I) += prcm.o
-obj-$(CONFIG_MACH_SUN6I) += p2wi.o
-obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
-obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
+
+obj-$(CONFIG_MACH_SUN6I) += tzpc.o
+obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
ifndef CONFIG_SPL_BUILD
-obj-y += cpu_info.o
-ifdef CONFIG_ARMV7_PSCI
-obj-y += psci.o
-endif
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
-obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
-ifdef CONFIG_SPL_FEL
-obj-y += start.o
-endif
+obj-y += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
deleted file mode 100644
index 9b3e80c..0000000
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * Some init for sunxi platform.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <serial.h>
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#endif
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-
-#include <linux/compiler.h>
-
-#ifdef CONFIG_SPL_BUILD
-/* Pointer to the global data structure for SPL */
-DECLARE_GLOBAL_DATA_PTR;
-
-/* The sunxi internal brom will try to loader external bootloader
- * from mmc0, nand flash, mmc2.
- * Unfortunately we can't check how SPL was loaded so assume
- * it's always the first SD/MMC controller
- */
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(void)
-{
- return MMCSD_MODE_RAW;
-}
-#endif
-
-int gpio_init(void)
-{
-#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
- /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
-#endif
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
- sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
- sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
-#else
-#error Unsupported console port number. Please fix pin mux settings in board.c
-#endif
-
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
- static const struct sunxi_wdog *wdog =
- &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
-
- while (1) {
- /* sun5i sometimes gets stuck without this */
- writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
- }
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
- static const struct sunxi_wdog *wdog =
- ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_CFG_RESET, &wdog->cfg);
- writel(WDT_MODE_EN, &wdog->mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
-#endif
-}
-
-/* do some early init */
-void s_init(void)
-{
-#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
- /* Magic (undocmented) value taken from boot0, without this DRAM
- * access gets messed up (seems cache related) */
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-#endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
-
- clock_init();
- timer_init();
- gpio_init();
- i2c_init_board();
-
-#ifdef CONFIG_SPL_BUILD
- gd = &gdata;
- preloader_console_init();
-
-#ifdef CONFIG_SPL_I2C_SUPPORT
- /* Needed early by sunxi_board_init if PMU is enabled */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- sunxi_board_init();
-#endif
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- __maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
- gpio_direction_output(CONFIG_MACPWR, 1);
- mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_EMAC
- rc = sunxi_emac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize emac\n");
- return rc;
- }
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
- rc = sunxi_gmac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize gmac\n");
- return rc;
- }
-#endif
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
deleted file mode 100644
index 47fb70f..0000000
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h&g
