arch/arm/dts/meson-t7.dtsi - manifest_repos/u-boot - Git at Google

 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
  * licensing only applies to this file, and not this project as a
  * whole.
  *
  *  a) This library is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
  *     This library is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
  *     obtaining a copy of this software and associated documentation
  *     files (the "Software"), to deal in the Software without
  *     restriction, including without limitation the rights to use,
  *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     sell copies of the Software, and to permit persons to whom the
  *     Software is furnished to do so, subject to the following
  *     conditions:
  *
  *     The above copyright notice and this permission notice shall be
  *     included in all copies or substantial portions of the Software.
  *
  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */

 #include "meson-t7-series.dtsi"
 #include <dt-bindings/gpio/meson-t7-gpio.h>
 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
 #include <dt-bindings/pwm/pwm.h>
 #include <dt-bindings/pwm/meson.h>

 / {
 	compatible = "amlogic,meson-t7";

 	vpu {
 		compatible = "amlogic, vpu-t7";
 		status = "okay";
 		/*clocks = <&clkc CLKID_VAPB_MUX>,
 		 *	<&clkc CLKID_VPU_INTR>,
 		 *	<&clkc CLKID_VPU_P0_COMP>,
 		 *	<&clkc CLKID_VPU_P1_COMP>,
 		 *	<&clkc CLKID_VPU_MUX>;
 		 *clock-names = "vapb_clk",
 		 *	"vpu_intr_gate",
 		 *	"vpu_clk0",
 		 *	"vpu_clk1",
 		 *	"vpu_clk";
 		 */
 		clk_level = <7>;
 		/* 0: 100.0M    1: 166.7M    2: 200.0M    3: 250.0M */
 		/* 4: 333.3M    5: 400.0M    6: 500.0M    7: 666.7M */
 	};

 	fb {
 		status = "okay";
 		logo_addr = "0x7f800000";
 	};

 	pinctrl_periphs: pinctrl@fe004000 {
 		compatible = "amlogic,meson-t7-periphs-pinctrl";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		gpio: bank@fe004000 {
 			reg = <0x0 0xfe004000 0x0 0x0064>,
 			      <0x0 0xfe0040c0 0x0 0x0220>;
 			reg-names = "mux",
 				    "gpio";
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&pinctrl_periphs 0 0 157>;
 		};
 	};

 	i2c_gpio_0: i2c-gpio-0 {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		compatible = "i2c-gpio";
 		status = "okay";
 		gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
 			<&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */

 		i2c-gpio,delay-us = <5>;
 		is_odpin = <1>;
 	};

 	pwm_ab: pwm@fe058000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe058000  0x0 0x20>,
 			<0x0 0xfe000180  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};

 	pwm_cd: pwm@fe05a000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe05a000  0x0 0x20>,
 			<0x0 0xfe000184  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};

 	pwm_ef: pwm@fe05c000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe05c000  0x0 0x20>,
 			<0x0 0xfe000188  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};

 	pwmao_ab: pwm@fe05e000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe05e000  0x0 0x20>,
 			<0x0 0xfe0001a0  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};

 	pwmao_cd: pwm@fe060000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe060000  0x0 0x20>,
 			<0x0 0xfe0001a4  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};

 	pwmao_ef: pwm@fe030000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe030000  0x0 0x20>,
 			<0x0 0xfe0001a8  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};

 	pwmao_gh: pwm@fe032000 {
 		compatible = "amlogic,meson-v2-pwm";
 		reg = <0x0 0xfe032000  0x0 0x20>,
 			<0x0 0xfe0001ac  0x0 0x04>;
 		#pwm-cells = <3>;
 		status = "disabled";
 	};
 };

 &ethmac {
 	compatible = "amlogic,t7-eth-dwmac";
 	reg = <0x0 0xfdc00000 0x0 0x10000
 		0x0 0xFE024000 0x0 0x8
 		0x0 0xFE028000 0x0 0xa0>;
 	reg-names = "eth_base", "eth_top", "eth_cfg";
 	phy_cntl1 = <0x41054147>;
 	internal_phy = <1>;
 	mc_val = <0x4be04>;
 	cali_val = <0x80000>;
 	reset-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_HIGH>;
 	analog_ver = <1>;
 	pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
 	analog_val = <0x20200000 0x0000c000 0x00000023>;
 	chip_num = <3>;
 	//tx_amp_src = <0xfe005b30>;
 //	clocks = <&clkc CLKID_ETH_CORE>,
 //		 <&clkc CLKID_FCLK_DIV2>,
 //		 <&clkc CLKID_MPLL2>;
 //	clock-names = "stmmaceth", "clkin0", "clkin1";

 	mdio0: mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "snps,dwmac-mdio";
 	};
 };

 &periphs {

 	eth-phy-mux {
 		compatible = "mdio-mux-mmioreg", "mdio-mux";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0x0 0x15c 0x0 0x4>;
 		mux-mask = <0xffffffff>;
 		mdio-parent-bus = <&mdio0>;

 		internal_mdio: mdio@e40908ff {
 			reg = <0xe40908ff>;
 			#address-cells = <1>;
 			#size-cells = <0>;

 			internal_phy: ethernet-phy@8 {
 				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
 				reg = <8>;
 				max-speed = <100>;
 			};
 		};

 		external_mdio: mdio@2009087f {
 			reg = <0x2009087f>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 	};
 };

 &saradc {
 	compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
 	clocks = <&xtal>,
 		 <&clkc CLKID_SARADC_MUX>,
 		 <&clkc CLKID_SARADC_DIV>,
 		 <&clkc CLKID_SAR_ADC_GATE>;
 	clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
 };

 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
 		    <&clkc CLKID_SD_EMMC_A_DIV>,
 			<&clkc CLKID_SD_EMMC_A_GATE>,
 			<&clkc CLKID_FCLK_DIV2>,
 			<&clkc CLKID_XTAL>;
 			clock-names = "mux", "div", "gate", "clkin", "xtal";
 };

 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
 		    <&clkc CLKID_SD_EMMC_B_DIV>,
 			<&clkc CLKID_SD_EMMC_B_GATE>,
 			<&clkc CLKID_FCLK_DIV2>,
 			<&clkc CLKID_XTAL>;
 			clock-names = "mux", "div", "gate", "clkin", "xtal";
 };

 &sd_emmc_c {
 	clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
 			<&clkc CLKID_SD_EMMC_C_DIV>,
 			<&clkc CLKID_SD_EMMC_C_GATE>,
 			<&clkc CLKID_GP0_PLL>,
 			<&clkc CLKID_XTAL>;
 			clock-names = "mux", "div", "gate", "clkin", "xtal";
 };

 &nand {
 	clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
 			<&clkc CLKID_SD_EMMC_C_DIV>,
 			<&clkc CLKID_SD_EMMC_C_GATE>,
 			<&clkc CLKID_FCLK_DIV2>,
 			<&clkc CLKID_XTAL>;
 	clock-names = "mux", "div", "gate", "fdiv2", "xtal";
 };

 &spicc0 {
 	clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
 	clock-names = "async", "async-gate";
 	assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
 	assigned-clock-rates = <0>, <200000000>;
 	/* =PM_SPICC0, must set to power on */
 	pm-id = <42>;
 };

 &spicc1 {
 	clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>;
 	clock-names = "async", "async-gate";
 	assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>;
 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
 	assigned-clock-rates = <0>, <200000000>;
 	/* =PM_SPICC1, must set to power on */
 	pm-id = <43>;
 };

 &spicc2 {
 	clocks = <&clkc CLKID_SPICC_C_DIV>, <&clkc CLKID_SPICC_C_GATE>;
 	clock-names = "async", "async-gate";
 	assigned-clocks = <&clkc CLKID_SPICC_C_MUX>, <&clkc CLKID_SPICC_C_DIV>;
 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
 	assigned-clock-rates = <0>, <200000000>;
 	/* =PM_SPICC2, must set to power on */
 	pm-id = <44>;
 };

 &spicc3 {
 	clocks = <&clkc CLKID_SPICC_D_DIV>, <&clkc CLKID_SPICC_D_GATE>;
 	clock-names = "async", "async-gate";
 	assigned-clocks = <&clkc CLKID_SPICC_D_MUX>, <&clkc CLKID_SPICC_D_DIV>;
 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
 	assigned-clock-rates = <0>, <200000000>;
 	/* =PM_SPICC3, must set to power on */
 	pm-id = <45>;
 };

 &spicc4 {
 	clocks = <&clkc CLKID_SPICC_E_DIV>, <&clkc CLKID_SPICC_E_GATE>;
 	clock-names = "async", "async-gate";
 	assigned-clocks = <&clkc CLKID_SPICC_E_MUX>, <&clkc CLKID_SPICC_E_DIV>;
 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
 	assigned-clock-rates = <0>, <200000000>;
 	/* =PM_SPICC4, must set to power on */
 	pm-id = <46>;
 };

 &spicc5 {
 	clocks = <&clkc CLKID_SPICC_F_DIV>, <&clkc CLKID_SPICC_F_GATE>;
 	clock-names = "async", "async-gate";
 	assigned-clocks = <&clkc CLKID_SPICC_F_MUX>, <&clkc CLKID_SPICC_F_DIV>;
 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
 	assigned-clock-rates = <0>, <200000000>;
 	/* =PM_SPICC5, must set to power on */
 	pm-id = <47>;
 };

 &pinctrl_periphs {
 	i2c0_pins1:i2c0_pins1 {
 		mux {
 			groups = "i2c0_sda_t",
 				"i2c0_sck_t";
 			function = "i2c0";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c0_pins2:i2c0_pins2 {
 		mux {
 			groups = "i2c0_sda_h",
 				"i2c0_sck_h";
 			function = "i2c0";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c1_pins1:i2c1_pins1 {
 		mux {
 			groups = "i2c1_sda",
 				"i2c1_sck";
 			function = "i2c1";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c2_pins1:i2c2_pins1 {
 		mux {
 			groups = "i2c2_sda_x",
 				"i2c2_sck_x";
 			function = "i2c2";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c2_pins2:i2c2_pins2 {
 		mux {
 			groups = "i2c2_sda_t",
 				"i2c2_sck_t";
 			function = "i2c2";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c2_pins3:i2c2_pins3 {
 		mux {
 			groups = "i2c2_sda_m",
 				"i2c2_sck_m";
 			function = "i2c2";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c3_pins1:i2c3_pins1 {
 		mux {
 			groups = "i2c3_sda_m",
 				"i2c3_sck_m";
 			function = "i2c3";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c3_pins2:i2c3_pins2 {
 		mux {
 			groups = "i2c3_sda_h",
 				"i2c3_sck_h";
 			function = "i2c3";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c4_pins1:i2c4_pins1 {
 		mux {
 			groups = "i2c4_sda_y",
 				"i2c4_sck_y";
 			function = "i2c4";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c4_pins2:i2c4_pins2 {
 		mux {
 			groups = "i2c4_sda_h",
 				"i2c4_sck_h";
 			function = "i2c4";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c5_pins1:i2c5_pins1 {
 		mux {
 			groups = "i2c5_sda",
 				"i2c5_sck";
 			function = "i2c5";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c0_ao_pins1:i2c0_ao_pins1 {
 		mux {
 			groups = "i2c0_ao_sda_d",
 				"i2c0_ao_sck_d";
 			function = "i2c0_ao";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c0_ao_pins2:i2c0_ao_pins2 {
 		mux {
 			groups = "i2c0_ao_sda_e",
 				"i2c0_ao_sck_e";
 			function = "i2c0_ao";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	i2c1_ao_pins1:i2c1_ao_pins1 {
 		mux {
 			groups = "i2c1_ao_sda",
 				"i2c1_ao_sck";
 			function = "i2c1_ao";
 			drive-strength = <3>;
 			bias-disable;
 		};
 	};

 	jtag_a_pins:jtag_a_pin {
 		mux {
 			groups = "jtag_a_clk",
 			"jtag_a_tms",
 			"jtag_a_tdi",
 			"jtag_a_tdo";
 			function = "jtag_a";
 		};
 	};

 	jtag_b_pins:jtag_b_pin {
 		mux {
 			groups = "jtag_b_clk",
 			"jtag_b_tms",
 			"jtag_b_tdi",
 			"jtag_b_tdo";
 			function = "jtag_b";
 		};
 	};

 	swd_a_pins:swd_a_pin {
 		mux {
 			groups = "swclk",
 			"swdio";
 			function = "sw";
 		};
 	};

 	emmc_pins: emmc {
 		mux {
 			groups = "emmc_nand_d0",
 				"emmc_nand_d1",
 				"emmc_nand_d2",
 				"emmc_nand_d3",
 				"emmc_nand_d4",
 				"emmc_nand_d5",
 				"emmc_nand_d6",
 				"emmc_nand_d7",
 				"emmc_clk",
 				"emmc_cmd";
 			function = "emmc";
 			bias-pull-up;
 			input-enable;
 		};
 		mux1 {
 			groups = "emmc_nand_ds";
 			function = "emmc";
 			input-enable;
 			bias-pull-down;
 		};
 	};

 	emmc_clk_gate_pins: emmc_clk_gate {
 		mux {
 			groups = "emmc_clk";
 			function = "emmc";
 			bias-pull-down;
 		};
 	};

 	all_nand_pins: all_nand_pins {
 		mux {
 			groups =  "emmc_nand_d0",
 				"emmc_nand_d1",
 				"emmc_nand_d2",
 				"emmc_nand_d3",
 				"emmc_nand_d4",
 				"emmc_nand_d5",
 				"emmc_nand_d6",
 				"emmc_nand_d7",
 				"nand_ce0",
 				"nand_ale",
 				"nand_cle",
 				"nand_wen_clk",
 				"nand_ren_wr";
 			function = "nand";
 			input-enable;
 		};
 	};

 	nand_cs_pins: nand_cs {
 		mux {
 			groups = "nand_ce0";
 			function = "nand";
 		};
 	};

 	sdcard_pins: sdcard {
 		mux {
 			groups = "sdcard_d0",
 				"sdcard_d1",
 				"sdcard_d2",
 				"sdcard_d3",
 				"sdcard_cmd";
 			function = "sdcard";
 			bias-pull-up;
 			input-enable;
 			drive-strength = <4>;
 		};
 		mux1 {
 			groups ="sdcard_clk";
 			function = "sdcard";
 			bias-pull-up;
 			output-high;
 			drive-strength = <4>;
 		};
 	};

 	sdcard_clk_gate_pins: sdcard_clk_gate {
 		mux {
 			groups = "sdcard_clk";
 			function = "sdcard";
 			bias-pull-down;
 		};
 	};

 	to_sduart_pins: to_sduart_pins{
 		mux {
 			groups = "uart_b_rx_c", "uart_b_tx_c";
 			function = "uart_b";
 			bias-pull-up;
 			input-enable;
 		};
 	};

 	sd_to_uart_pins: sd_to_uart_pins{
 		mux {
 			groups = "uart_b_rx_d", "uart_b_tx_d";
 			function = "uart_b";
 			bias-pull-up;
 			input-enable;
 		};
 	};

 	spicc0_pins: spicc0_pins {
 		mux {
 			groups = "spi0_mosi",
 				 "spi0_miso",
 				 //"spi0_ss0",used as GPIOT_21
 				 "spi0_sclk";
 			function = "spi0";
 			drive-strength = <2>;
 		};
 	};

 	spicc1_pins_1: spicc1_pins_1 {
 		mux {
 			groups = "spi1_mosi_c",
 				 "spi1_miso_c",
 				 //"spi1_ss0_c",used as GPIOC_3
 				 "spi1_sclk_c";
 			function = "spi1";
 			drive-strength = <2>;
 		};
 	};

 	spicc1_pins_2: spicc1_pins_2 {
 		mux {
 			groups = "spi1_mosi_m",
 				 "spi1_miso_m",
 				 //"spi1_ss0_m",used as GPIOM_11
 				 "spi1_sclk_m";
 			function = "spi1";
 			drive-strength = <2>;
 		};
 	};

 	spicc2_pins: spicc2_pins {
 		mux {
 			groups = "spi2_mosi",
 				 "spi2_miso",
 				 //"spi2_ss0",used as GPIOY_3
 				 "spi2_sclk";
 			function = "spi2";
 			drive-strength = <2>;
 		};
 	};

 	spicc3_pins: spicc3_pins {
 		mux {
 			groups = "spi3_mosi",
 				 "spi3_miso",
 				 //"spi3_ss0",used as GPIOT_9
 				 "spi3_sclk";
 			function = "spi3";
 			drive-strength = <2>;
 		};
 	};

 	spicc4_pins: spicc4_pins {
 		mux {
 			groups = "spi4_mosi",
 				 "spi4_miso",
 				 //"spi4_ss0",used as GPIOZ_3
 				 "spi4_sclk";
 			function = "spi4";
 			drive-strength = <2>;
 		};
 	};

 	spicc5_pins: spicc5_pins {
 		mux {
 			groups = "spi5_mosi",
 				 "spi5_miso",
 				 //"spi5_ss0",used as GPIOZ_7
 				 "spi5_sclk";
 			function = "spi5";
 			drive-strength = <2>;
 		};
 	};

 	spifc_pins: spifc_pins {
 		mux {
 			groups = "nor_d",
 				 "nor_q",
 				 "nor_c",
 				 "nor_hold",
 				 "nor_wp";
 			function = "nor";
 			drive-strength = <3>;
 		};
 	};

 	pwm_a_pins: pwm_a_pins {
 		mux {
 			groups = "pwm_a";
 			function = "pwm_a";
 		};
 	};

 	pwm_b_pins: pwm_b_pins {
 		mux {
 			groups = "pwm_b";
 			function = "pwm_b";
 		};
 	};

 	pwm_c_pins: pwm_c_pins {
 		mux {
 			groups = "pwm_c";
 			function = "pwm_c";
 		};
 	};

 	pwm_d_pins: pwm_d_pins {
 		mux {
 			groups = "pwm_d";
 			function = "pwm_d";
 		};
 	};

 	pwm_e_pins: pwm_e_pins {
 		mux {
 			groups = "pwm_e";
 			function = "pwm_e";
 		};
 	};

 	pwm_f_pins: pwm_f_pins {
 		mux {
 			groups = "pwm_f";
 			function = "pwm_f";
 		};
 	};

 	pwm_ao_a_pins: pwm_ao_a_pins {
 		mux {
 			groups = "pwm_ao_a";
 			function = "pwm_ao_a";
 		};
 	};

 	pwm_ao_b_pins: pwm_ao_b_pins {
 		mux {
 			groups = "pwm_ao_b";
 			function = "pwm_ao_b";
 		};
 	};

 	pwm_ao_c_pins1: pwm_ao_c_pins1 {
 		mux {
 			groups = "pwm_ao_c_d";
 			function = "pwm_ao_c";
 		};
 	};

 	pwm_ao_c_pins2: pwm_ao_c_pins2 {
 		mux {
 			groups = "pwm_ao_c_e";
 			function = "pwm_ao_c";
 		};
 	};

 	pwm_ao_c_hiz_pins: pwm_ao_c_hiz_pins {
 		mux {
 			groups = "pwm_ao_c_hiz";
 			function = "pwm_ao_c";
 		};
 	};

 	pwm_ao_d_pins: pwm_ao_d_pins {
 		mux {
 			groups = "pwm_ao_d";
 			function = "pwm_ao_d";
 		};
 	};

 	pwm_ao_e_pins: pwm_ao_e_pins {
 		mux {
 			groups = "pwm_ao_e";
 			function = "pwm_ao_e";
 		};
 	};

 	pwm_ao_f_pins: pwm_ao_f_pins {
 		mux {
 			groups = "pwm_ao_f";
 			function = "pwm_ao_f";
 		};
 	};

 	pwm_ao_g_pins1: pwm_ao_g_pins1 {
 		mux {
 			groups = "pwm_ao_g_d11";
 			function = "pwm_ao_g";
 		};
 	};

 	pwm_ao_g_pins2: pwm_ao_g_pins2 {
 		mux {
 			groups = "pwm_ao_g_d7";
 			function = "pwm_ao_g";
 		};
 	};

 	pwm_ao_g_pins3: pwm_ao_g_pins3 {
 		mux {
 			groups = "pwm_ao_g_e";
 			function = "pwm_ao_g";
 		};
 	};

 	pwm_ao_g_hiz_pins: pwm_ao_g_hiz_pins {
 		mux {
 			groups = "pwm_ao_g_hiz";
 			function = "pwm_ao_g";
 		};
 	};

 	pwm_ao_h_pins1: pwm_ao_h_pins1 {
 		mux {
 			groups = "pwm_ao_h_d5";
 			function = "pwm_ao_h";
 		};
 	};

 	pwm_ao_h_pins2: pwm_ao_d_pins2 {
 		mux {
 			groups = "pwm_ao_h_d10";
 			function = "pwm_ao_h";
 		};
 	};

 	external_eth_rmii_pins: external_eth_rmii_pins {
 		mux {
 			groups = "eth_mdio",
 				"eth_mdc",
 				"eth_rgmii_rx_clk",
 				"eth_rx_dv",
 				"eth_rxd0",
 				"eth_rxd1",
 				"eth_txen",
 				"eth_txd0",
 				"eth_txd1";
 			function = "eth";
 			drive-strength = <3>;
 		};
 	};

 	external_eth_rgmii_pins: external_eth_rgmii_pins {
 		mux {
 			groups = "eth_mdio",
 				"eth_mdc",
 				"eth_rgmii_rx_clk",
 				"eth_rx_dv",
 				"eth_rxd0",
 				"eth_rxd1",
 				"eth_rxd2_rgmii",
 				"eth_rxd3_rgmii",
 				"eth_rgmii_tx_clk",
 				"eth_txen",
 				"eth_txd0",
 				"eth_txd1",
 				"eth_txd2_rgmii",
 				"eth_txd3_rgmii";
 			function = "eth";
 			drive-strength = <3>;
 		};
 	};
 };
	/*
	* Copyright (c) 2016 Endless Computers, Inc.
	* Author: Carlo Caione <carlo@endlessm.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This library is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This library is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include "meson-t7-series.dtsi"
	#include <dt-bindings/gpio/meson-t7-gpio.h>
	#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
	#include <dt-bindings/pwm/pwm.h>
	#include <dt-bindings/pwm/meson.h>

	/ {
	compatible = "amlogic,meson-t7";

	vpu {
	compatible = "amlogic, vpu-t7";
	status = "okay";
	/*clocks = <&clkc CLKID_VAPB_MUX>,
	* <&clkc CLKID_VPU_INTR>,
	* <&clkc CLKID_VPU_P0_COMP>,
	* <&clkc CLKID_VPU_P1_COMP>,
	* <&clkc CLKID_VPU_MUX>;
	*clock-names = "vapb_clk",
	* "vpu_intr_gate",
	* "vpu_clk0",
	* "vpu_clk1",
	* "vpu_clk";
	*/
	clk_level = <7>;
	/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
	/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
	};

	fb {
	status = "okay";
	logo_addr = "0x7f800000";
	};

	pinctrl_periphs: pinctrl@fe004000 {
	compatible = "amlogic,meson-t7-periphs-pinctrl";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio: bank@fe004000 {
	reg = <0x0 0xfe004000 0x0 0x0064>,
	<0x0 0xfe0040c0 0x0 0x0220>;
	reg-names = "mux",
	"gpio";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl_periphs 0 0 157>;
	};
	};

	i2c_gpio_0: i2c-gpio-0 {
	#address-cells = <1>;
	#size-cells = <0>;

	compatible = "i2c-gpio";
	status = "okay";
	gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
	<&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */

	i2c-gpio,delay-us = <5>;
	is_odpin = <1>;
	};

	pwm_ab: pwm@fe058000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe058000 0x0 0x20>,
	<0x0 0xfe000180 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm_cd: pwm@fe05a000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe05a000 0x0 0x20>,
	<0x0 0xfe000184 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwm_ef: pwm@fe05c000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe05c000 0x0 0x20>,
	<0x0 0xfe000188 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwmao_ab: pwm@fe05e000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe05e000 0x0 0x20>,
	<0x0 0xfe0001a0 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwmao_cd: pwm@fe060000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe060000 0x0 0x20>,
	<0x0 0xfe0001a4 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwmao_ef: pwm@fe030000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe030000 0x0 0x20>,
	<0x0 0xfe0001a8 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	pwmao_gh: pwm@fe032000 {
	compatible = "amlogic,meson-v2-pwm";
	reg = <0x0 0xfe032000 0x0 0x20>,
	<0x0 0xfe0001ac 0x0 0x04>;
	#pwm-cells = <3>;
	status = "disabled";
	};
	};

	&ethmac {
	compatible = "amlogic,t7-eth-dwmac";
	reg = <0x0 0xfdc00000 0x0 0x10000
	0x0 0xFE024000 0x0 0x8
	0x0 0xFE028000 0x0 0xa0>;
	reg-names = "eth_base", "eth_top", "eth_cfg";
	phy_cntl1 = <0x41054147>;
	internal_phy = <1>;
	mc_val = <0x4be04>;
	cali_val = <0x80000>;
	reset-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_HIGH>;
	analog_ver = <1>;
	pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
	analog_val = <0x20200000 0x0000c000 0x00000023>;
	chip_num = <3>;
	//tx_amp_src = <0xfe005b30>;
	// clocks = <&clkc CLKID_ETH_CORE>,
	// <&clkc CLKID_FCLK_DIV2>,
	// <&clkc CLKID_MPLL2>;
	// clock-names = "stmmaceth", "clkin0", "clkin1";

	mdio0: mdio {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dwmac-mdio";
	};
	};

	&periphs {

	eth-phy-mux {
	compatible = "mdio-mux-mmioreg", "mdio-mux";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x15c 0x0 0x4>;
	mux-mask = <0xffffffff>;
	mdio-parent-bus = <&mdio0>;

	internal_mdio: mdio@e40908ff {
	reg = <0xe40908ff>;
	#address-cells = <1>;
	#size-cells = <0>;

	internal_phy: ethernet-phy@8 {
	compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
	reg = <8>;
	max-speed = <100>;
	};
	};

	external_mdio: mdio@2009087f {
	reg = <0x2009087f>;
	#address-cells = <1>;
	#size-cells = <0>;
	};
	};
	};

	&saradc {
	compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>,
	<&clkc CLKID_SARADC_MUX>,
	<&clkc CLKID_SARADC_DIV>,
	<&clkc CLKID_SAR_ADC_GATE>;
	clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
	};

	&sd_emmc_a {
	clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
	<&clkc CLKID_SD_EMMC_A_DIV>,
	<&clkc CLKID_SD_EMMC_A_GATE>,
	<&clkc CLKID_FCLK_DIV2>,
	<&clkc CLKID_XTAL>;
	clock-names = "mux", "div", "gate", "clkin", "xtal";
	};

	&sd_emmc_b {
	clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
	<&clkc CLKID_SD_EMMC_B_DIV>,
	<&clkc CLKID_SD_EMMC_B_GATE>,
	<&clkc CLKID_FCLK_DIV2>,
	<&clkc CLKID_XTAL>;
	clock-names = "mux", "div", "gate", "clkin", "xtal";
	};

	&sd_emmc_c {
	clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
	<&clkc CLKID_SD_EMMC_C_DIV>,
	<&clkc CLKID_SD_EMMC_C_GATE>,
	<&clkc CLKID_GP0_PLL>,
	<&clkc CLKID_XTAL>;
	clock-names = "mux", "div", "gate", "clkin", "xtal";
	};

	&nand {
	clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
	<&clkc CLKID_SD_EMMC_C_DIV>,
	<&clkc CLKID_SD_EMMC_C_GATE>,
	<&clkc CLKID_FCLK_DIV2>,
	<&clkc CLKID_XTAL>;
	clock-names = "mux", "div", "gate", "fdiv2", "xtal";
	};

	&spicc0 {
	clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
	clock-names = "async", "async-gate";
	assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
	assigned-clock-rates = <0>, <200000000>;
	/* =PM_SPICC0, must set to power on */
	pm-id = <42>;
	};

	&spicc1 {
	clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>;
	clock-names = "async", "async-gate";
	assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>;
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
	assigned-clock-rates = <0>, <200000000>;
	/* =PM_SPICC1, must set to power on */
	pm-id = <43>;
	};

	&spicc2 {
	clocks = <&clkc CLKID_SPICC_C_DIV>, <&clkc CLKID_SPICC_C_GATE>;
	clock-names = "async", "async-gate";
	assigned-clocks = <&clkc CLKID_SPICC_C_MUX>, <&clkc CLKID_SPICC_C_DIV>;
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
	assigned-clock-rates = <0>, <200000000>;
	/* =PM_SPICC2, must set to power on */
	pm-id = <44>;
	};

	&spicc3 {
	clocks = <&clkc CLKID_SPICC_D_DIV>, <&clkc CLKID_SPICC_D_GATE>;
	clock-names = "async", "async-gate";
	assigned-clocks = <&clkc CLKID_SPICC_D_MUX>, <&clkc CLKID_SPICC_D_DIV>;
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
	assigned-clock-rates = <0>, <200000000>;
	/* =PM_SPICC3, must set to power on */
	pm-id = <45>;
	};

	&spicc4 {
	clocks = <&clkc CLKID_SPICC_E_DIV>, <&clkc CLKID_SPICC_E_GATE>;
	clock-names = "async", "async-gate";
	assigned-clocks = <&clkc CLKID_SPICC_E_MUX>, <&clkc CLKID_SPICC_E_DIV>;
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
	assigned-clock-rates = <0>, <200000000>;
	/* =PM_SPICC4, must set to power on */
	pm-id = <46>;
	};

	&spicc5 {
	clocks = <&clkc CLKID_SPICC_F_DIV>, <&clkc CLKID_SPICC_F_GATE>;
	clock-names = "async", "async-gate";
	assigned-clocks = <&clkc CLKID_SPICC_F_MUX>, <&clkc CLKID_SPICC_F_DIV>;
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
	assigned-clock-rates = <0>, <200000000>;
	/* =PM_SPICC5, must set to power on */
	pm-id = <47>;
	};

	&pinctrl_periphs {
	i2c0_pins1:i2c0_pins1 {
	mux {
	groups = "i2c0_sda_t",
	"i2c0_sck_t";
	function = "i2c0";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c0_pins2:i2c0_pins2 {
	mux {
	groups = "i2c0_sda_h",
	"i2c0_sck_h";
	function = "i2c0";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c1_pins1:i2c1_pins1 {
	mux {
	groups = "i2c1_sda",
	"i2c1_sck";
	function = "i2c1";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c2_pins1:i2c2_pins1 {
	mux {
	groups = "i2c2_sda_x",
	"i2c2_sck_x";
	function = "i2c2";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c2_pins2:i2c2_pins2 {
	mux {
	groups = "i2c2_sda_t",
	"i2c2_sck_t";
	function = "i2c2";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c2_pins3:i2c2_pins3 {
	mux {
	groups = "i2c2_sda_m",
	"i2c2_sck_m";
	function = "i2c2";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c3_pins1:i2c3_pins1 {
	mux {
	groups = "i2c3_sda_m",
	"i2c3_sck_m";
	function = "i2c3";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c3_pins2:i2c3_pins2 {
	mux {
	groups = "i2c3_sda_h",
	"i2c3_sck_h";
	function = "i2c3";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c4_pins1:i2c4_pins1 {
	mux {
	groups = "i2c4_sda_y",
	"i2c4_sck_y";
	function = "i2c4";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c4_pins2:i2c4_pins2 {
	mux {
	groups = "i2c4_sda_h",
	"i2c4_sck_h";
	function = "i2c4";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c5_pins1:i2c5_pins1 {
	mux {
	groups = "i2c5_sda",
	"i2c5_sck";
	function = "i2c5";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c0_ao_pins1:i2c0_ao_pins1 {
	mux {
	groups = "i2c0_ao_sda_d",
	"i2c0_ao_sck_d";
	function = "i2c0_ao";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c0_ao_pins2:i2c0_ao_pins2 {
	mux {
	groups = "i2c0_ao_sda_e",
	"i2c0_ao_sck_e";
	function = "i2c0_ao";
	drive-strength = <3>;
	bias-disable;
	};
	};

	i2c1_ao_pins1:i2c1_ao_pins1 {
	mux {
	groups = "i2c1_ao_sda",
	"i2c1_ao_sck";
	function = "i2c1_ao";
	drive-strength = <3>;
	bias-disable;
	};
	};

	jtag_a_pins:jtag_a_pin {
	mux {
	groups = "jtag_a_clk",
	"jtag_a_tms",
	"jtag_a_tdi",
	"jtag_a_tdo";
	function = "jtag_a";
	};
	};

	jtag_b_pins:jtag_b_pin {
	mux {
	groups = "jtag_b_clk",
	"jtag_b_tms",
	"jtag_b_tdi",
	"jtag_b_tdo";
	function = "jtag_b";
	};
	};

	swd_a_pins:swd_a_pin {
	mux {
	groups = "swclk",
	"swdio";
	function = "sw";
	};
	};

	emmc_pins: emmc {
	mux {
	groups = "emmc_nand_d0",
	"emmc_nand_d1",
	"emmc_nand_d2",
	"emmc_nand_d3",
	"emmc_nand_d4",
	"emmc_nand_d5",
	"emmc_nand_d6",
	"emmc_nand_d7",
	"emmc_clk",
	"emmc_cmd";
	function = "emmc";
	bias-pull-up;
	input-enable;
	};
	mux1 {
	groups = "emmc_nand_ds";
	function = "emmc";
	input-enable;
	bias-pull-down;
	};
	};

	emmc_clk_gate_pins: emmc_clk_gate {
	mux {
	groups = "emmc_clk";
	function = "emmc";
	bias-pull-down;
	};
	};

	all_nand_pins: all_nand_pins {
	mux {
	groups = "emmc_nand_d0",
	"emmc_nand_d1",
	"emmc_nand_d2",
	"emmc_nand_d3",
	"emmc_nand_d4",
	"emmc_nand_d5",
	"emmc_nand_d6",
	"emmc_nand_d7",
	"nand_ce0",
	"nand_ale",
	"nand_cle",
	"nand_wen_clk",
	"nand_ren_wr";
	function = "nand";
	input-enable;
	};
	};

	nand_cs_pins: nand_cs {
	mux {
	groups = "nand_ce0";
	function = "nand";
	};
	};

	sdcard_pins: sdcard {
	mux {
	groups = "sdcard_d0",
	"sdcard_d1",
	"sdcard_d2",
	"sdcard_d3",
	"sdcard_cmd";
	function = "sdcard";
	bias-pull-up;
	input-enable;
	drive-strength = <4>;
	};
	mux1 {
	groups ="sdcard_clk";
	function = "sdcard";
	bias-pull-up;
	output-high;
	drive-strength = <4>;
	};
	};

	sdcard_clk_gate_pins: sdcard_clk_gate {
	mux {
	groups = "sdcard_clk";
	function = "sdcard";
	bias-pull-down;
	};
	};

	to_sduart_pins: to_sduart_pins{
	mux {
	groups = "uart_b_rx_c", "uart_b_tx_c";
	function = "uart_b";
	bias-pull-up;
	input-enable;
	};
	};

	sd_to_uart_pins: sd_to_uart_pins{
	mux {
	groups = "uart_b_rx_d", "uart_b_tx_d";
	function = "uart_b";
	bias-pull-up;
	input-enable;
	};
	};

	spicc0_pins: spicc0_pins {
	mux {
	groups = "spi0_mosi",
	"spi0_miso",
	//"spi0_ss0",used as GPIOT_21
	"spi0_sclk";
	function = "spi0";
	drive-strength = <2>;
	};
	};

	spicc1_pins_1: spicc1_pins_1 {
	mux {
	groups = "spi1_mosi_c",
	"spi1_miso_c",
	//"spi1_ss0_c",used as GPIOC_3
	"spi1_sclk_c";
	function = "spi1";
	drive-strength = <2>;
	};
	};

	spicc1_pins_2: spicc1_pins_2 {
	mux {
	groups = "spi1_mosi_m",
	"spi1_miso_m",
	//"spi1_ss0_m",used as GPIOM_11
	"spi1_sclk_m";
	function = "spi1";
	drive-strength = <2>;
	};
	};

	spicc2_pins: spicc2_pins {
	mux {
	groups = "spi2_mosi",
	"spi2_miso",
	//"spi2_ss0",used as GPIOY_3
	"spi2_sclk";
	function = "spi2";
	drive-strength = <2>;
	};
	};

	spicc3_pins: spicc3_pins {
	mux {
	groups = "spi3_mosi",
	"spi3_miso",
	//"spi3_ss0",used as GPIOT_9
	"spi3_sclk";
	function = "spi3";
	drive-strength = <2>;
	};
	};

	spicc4_pins: spicc4_pins {
	mux {
	groups = "spi4_mosi",
	"spi4_miso",
	//"spi4_ss0",used as GPIOZ_3
	"spi4_sclk";
	function = "spi4";
	drive-strength = <2>;
	};
	};

	spicc5_pins: spicc5_pins {
	mux {
	groups = "spi5_mosi",
	"spi5_miso",
	//"spi5_ss0",used as GPIOZ_7
	"spi5_sclk";
	function = "spi5";
	drive-strength = <2>;
	};
	};

	spifc_pins: spifc_pins {
	mux {
	groups = "nor_d",
	"nor_q",
	"nor_c",
	"nor_hold",
	"nor_wp";
	function = "nor";
	drive-strength = <3>;
	};
	};

	pwm_a_pins: pwm_a_pins {
	mux {
	groups = "pwm_a";
	function = "pwm_a";
	};
	};

	pwm_b_pins: pwm_b_pins {
	mux {
	groups = "pwm_b";
	function = "pwm_b";
	};
	};

	pwm_c_pins: pwm_c_pins {
	mux {
	groups = "pwm_c";
	function = "pwm_c";
	};
	};

	pwm_d_pins: pwm_d_pins {
	mux {
	groups = "pwm_d";
	function = "pwm_d";
	};
	};

	pwm_e_pins: pwm_e_pins {
	mux {
	groups = "pwm_e";
	function = "pwm_e";
	};
	};

	pwm_f_pins: pwm_f_pins {
	mux {
	groups = "pwm_f";
	function = "pwm_f";
	};
	};

	pwm_ao_a_pins: pwm_ao_a_pins {
	mux {
	groups = "pwm_ao_a";
	function = "pwm_ao_a";
	};
	};

	pwm_ao_b_pins: pwm_ao_b_pins {
	mux {
	groups = "pwm_ao_b";
	function = "pwm_ao_b";
	};
	};

	pwm_ao_c_pins1: pwm_ao_c_pins1 {
	mux {
	groups = "pwm_ao_c_d";
	function = "pwm_ao_c";
	};
	};

	pwm_ao_c_pins2: pwm_ao_c_pins2 {
	mux {
	groups = "pwm_ao_c_e";
	function = "pwm_ao_c";
	};
	};

	pwm_ao_c_hiz_pins: pwm_ao_c_hiz_pins {
	mux {
	groups = "pwm_ao_c_hiz";
	function = "pwm_ao_c";
	};
	};

	pwm_ao_d_pins: pwm_ao_d_pins {
	mux {
	groups = "pwm_ao_d";
	function = "pwm_ao_d";
	};
	};

	pwm_ao_e_pins: pwm_ao_e_pins {
	mux {
	groups = "pwm_ao_e";
	function = "pwm_ao_e";
	};
	};

	pwm_ao_f_pins: pwm_ao_f_pins {
	mux {
	groups = "pwm_ao_f";
	function = "pwm_ao_f";
	};
	};

	pwm_ao_g_pins1: pwm_ao_g_pins1 {
	mux {
	groups = "pwm_ao_g_d11";
	function = "pwm_ao_g";
	};
	};

	pwm_ao_g_pins2: pwm_ao_g_pins2 {
	mux {
	groups = "pwm_ao_g_d7";
	function = "pwm_ao_g";
	};
	};

	pwm_ao_g_pins3: pwm_ao_g_pins3 {
	mux {
	groups = "pwm_ao_g_e";
	function = "pwm_ao_g";
	};
	};

	pwm_ao_g_hiz_pins: pwm_ao_g_hiz_pins {
	mux {
	groups = "pwm_ao_g_hiz";
	function = "pwm_ao_g";
	};
	};

	pwm_ao_h_pins1: pwm_ao_h_pins1 {
	mux {
	groups = "pwm_ao_h_d5";
	function = "pwm_ao_h";
	};
	};

	pwm_ao_h_pins2: pwm_ao_d_pins2 {
	mux {
	groups = "pwm_ao_h_d10";
	function = "pwm_ao_h";
	};
	};

	external_eth_rmii_pins: external_eth_rmii_pins {
	mux {
	groups = "eth_mdio",
	"eth_mdc",
	"eth_rgmii_rx_clk",
	"eth_rx_dv",
	"eth_rxd0",
	"eth_rxd1",
	"eth_txen",
	"eth_txd0",
	"eth_txd1";
	function = "eth";
	drive-strength = <3>;
	};
	};

	external_eth_rgmii_pins: external_eth_rgmii_pins {
	mux {
	groups = "eth_mdio",
	"eth_mdc",
	"eth_rgmii_rx_clk",
	"eth_rx_dv",
	"eth_rxd0",
	"eth_rxd1",
	"eth_rxd2_rgmii",
	"eth_rxd3_rgmii",
	"eth_rgmii_tx_clk",
	"eth_txen",
	"eth_txd0",
	"eth_txd1",
	"eth_txd2_rgmii",
	"eth_txd3_rgmii";
	function = "eth";
	drive-strength = <3>;
	};
	};
	};