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Googler25e92cf2023-12-13 10:05:01 +00001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6/** \brief LPDDR4_2D training firmware message block structure
7 *
8 * Please refer to the Training Firmware App Note for futher information about
9 * the usage for Message Block.
10 */
11typedef struct _PMU_SMB_LPDDR4_2D_t {
12 uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
13 // Reserved00[0:4] RFU, must be zero
14 //
15 // Reserved00[5] = Quick Rd2D during 1D Training
16 // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
17 // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
18 //
19 // Reserved00[6] = Enable High Effort WrDQ1D
20 // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
21 // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
22 //
23 // Reserved00[7] = Optimize for the special hard macros in TSMC28.
24 // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
25 // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
26 uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
27 // Contains various global options for training.
28 //
29 // Bit fields:
30 //
31 // MsgMisc[0] MTESTEnable
32 // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
33 // 0x0 = Do not pulse primary digital test output bump
34 //
35 // MsgMisc[1] SimulationOnlyReset
36 // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
37 // Must never be set to 1 in silicon.
38 // 0x0 = Use reset pulse length specifed by JEDEC standard
39 //
40 // MsgMisc[2] SimulationOnlyTraining
41 // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
42 // Must never be set to 1 in silicon.
43 // 0x0 = Use standard training duration.
44 //
45 // MsgMisc[3] Disable Boot Clock
46 // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
47 // 0x0 = Use Boot Frequency Clock
48 //
49 // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
50 // Stage Completion messages, as well as training completion and error messages are
51 // Still sent depending on HdtCtrl setting.
52 //
53 // MsgMisc[5] PerByteMaxRdLat
54 // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
55 // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
56 //
57 // MsgMisc[7-6] RFU, must be zero
58 //
59 // Notes:
60 //
61 // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
62 uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
63 // PMU firmware revision ID
64 // After training is run, this address will contain the revision ID of the firmware
65 uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
66 // Must be set to the target Pstate to be trained
67 // 0x0 = Pstate 0
68 // 0x1 = Pstate 1
69 // 0x2 = Pstate 2
70 // 0x3 = Pstate 3
71 // All other encodings are reserved
72 uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
73 // Set according to whether target Pstate uses PHY PLL bypass
74 // 0x0 = PHY PLL is enabled for target Pstate
75 // 0x1 = PHY PLL is bypassed for target Pstate
76 uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
77 // DDR data rate for the target Pstate in units of MT/s.
78 // For example enter 0x0640 for DDR1600.
79 uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
80 // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
81 // 0x1 = 1:1
82 // 0x2 = 1:2
83 // 0x4 = 1:4
84 uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
85 // Must be programmed to match the precision resistor connected to Phy BP_ZN
86 // 0x00 = Do not program. Use current CSR value.
87 // 0xf0 = 240 Ohm (recommended value)
88 // 0x78 = 120 Ohm
89 // 0x28 = 40 Ohm
90 // All other values are reserved.
91 //
92 uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
93 // Must be programmed to the termination impedance in ohms used by PHY during reads.
94 //
95 // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
96 //
97 // See PHY databook for legal termination impedance values.
98 //
99 // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
100 uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
101 // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
102 //
103 // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
104 //
105 // See PHY databook for legal R_on driver impedance values.
106 //
107 // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
108 uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
109 // Must be programmed with the Vref level to be used by the PHY during reads
110 //
111 // The units of this field are a percentage of VDDQ according to the following equation:
112 //
113 // Receiver Vref = VDDQ*PhyVref[6:0]/128
114 //
115 // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
116 //
117 // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
118 uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
119 // Lp4 specific options for training.
120 //
121 // Bit fields:
122 //
123 // Lp4Misc[0] Enable dfi_reset_n
124 //
125 // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
126 // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
127 //
128 // 0x1 = Enables dfi_reset_n to control memreset after training.
129 // PHY Internal registers control memreset during training only.
130 // To ensure that no glitches occur on BP_MEMRESET at the end of training,
131 // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
132 //
133 // Lp4Misc[7-1] RFU, must be zero
134 uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
135 // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
136 //
137 // Reserved0E[0:3]: bitTimeControl
138 // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
139 // 0 = 288 bits per point (legacy behavior)
140 // 1 = 576 bits per point
141 // 2 = 1.125 kilobits per point
142 // …
143 // 15 = 9 megabits per point
144 //
145 // Reserved0E[4]: Exhaustive2D
146 // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
147 // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
148 //
149 // Reserved0E[5:7]: RFU, must be 0
150 uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
151 // This field will be set if training fails on any rank.
152 // 0x0 = No failures
153 // non-zero = one or more ranks failed training
154 uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
155 // Controls the training steps to be run. Each bit corresponds to a training step.
156 //
157 // If the bit is set to 1, the training step will run.
158 // If the bit is set to 0, the training step will be skipped.
159 //
160 // Training step to bit mapping:
161 // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
162 // SequenceCtrl[1] = RFU, must be zero
163 // SequenceCtrl[2] = RFU, must be zero
164 // SequenceCtrl[3] = RFU, must be zero
165 // SequenceCtrl[4] = RFU, must be zero
166 // SequenceCtrl[5] = Run rd2D - 2d read dqs training
167 // SequenceCtrl[6] = Run wr2D - 2d write dq training
168 // SequenceCtrl[7] = RFU, must be zero
169 // SequenceCtrl[8] = RFU, must be zero
170 // SequenceCtrl[9] = RFU, must be zero
171 // SequenceCtrl[11-10] = RFU, must be zero
172 // SequenceCtrl[12] = RFU, must be zero
173 // SequenceCtrl[15-13] = RFU, must be zero
174 uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
175 // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
176 //
177 // 0x05 = Detailed debug messages (e.g. Eye delays)
178 // 0x0A = Coarse debug messages (e.g. rank information)
179 // 0xC8 = Stage completion
180 // 0xC9 = Assertion messages
181 // 0xFF = Firmware completion messages only
182 //
183 // See Training App Note for more detailed information on what messages are included for each threshold.
184 //
185 uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
186 // This field is reserved and must be programmed to 0x00.
187 uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
188 // This field is reserved and must be programmed to 0x00.
189 uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
190 // This field is reserved and must be programmed to 0x00.
191 uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
192 // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
193 //
194 // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
195 uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
196 // This field is reserved and must be programmed to 0x00.
197 uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
198 // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
199 //
200 // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
201 // Use MR<0:17>_B0 for rank 0 channel B
202 // Use MR<0:17>_A1 for rank 1 channel A
203 // Use MR<0:17>_B1 for rank 1 channel B
204 //
205 // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
206 //
207 // It is recommended in most LPDDR4 system configurations to set this to 1.
208 //
209 // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
210 //
211 uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
212
213 uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
214 // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
215 // Used by 2D stages: Rd2D, Wr2D
216 //
217 // Reserved1A[0-3]: Rd2D Voltage Range
218 // 0 = Training will search all phy vref(DQ) settings
219 // 1 = limit to +/-2 %VDDQ from phyVref
220 // 2 = limit to +/-4 %VDDQ from phyVref
221 // …
222 // 15 = limit to +/-30% VDDQ from phyVref
223 //
224 // Reserved1A[4-7]: Wr2D Voltage Range
225 // 0 = Training will search all dram vref(DQ) settings
226 // 1 = limit to +/-2 %VDDQ from MR14
227 // 2 = limit to +/-4 %VDDQ from MR14
228 // …
229 // 15 = limit to +/-30% VDDQ from MR14
230 uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
231 // CA training option bit field
232 // [0] CA VREF Setting
233 // 1 = Set MR12 from internal register
234 // 0 = Set MR12 from message block
235 // [1-7] RFU must be zero
236 uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
237 // X8 mode configuration:
238 // 0x0 = x16 configuration for all devices
239 // 0xF = x8 configuration for all devices
240 // All other values are RFU
241 uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
242 // Bit fields, if 2D read training enabled, then use these additional options:
243 // [0] DFE
244 // 1 = Run rx2D with DFE
245 // 0 = Run rx2D with DFE off
246 // [1-2] Voltage Step Size (2^n)
247 // 3 = 8 DAC settings between checked values
248 // 2 = 4 DAC settings between checked values
249 // 1 = 2 DAC settings between checked values
250 // 0 = 1 DAC settings between checked values
251 // [3-4] Delay Step Size (2^n)
252 // 3 = 8 LCDL delays between checked values
253 // 2 = 4 LCDL delays between checked values
254 // 1 = 2 LCDL delays between checked values
255 // 0 = 1 LCDL delays between checked values
256 // [5-7] RFU, must be zero
257 //
258 uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
259 // Bit fields, if 2D write training is enabled, then use these additional options:
260 // [0] FFE
261 // 1 = Train tx2D with FFE
262 // 0 = Train tx2D with FFE off
263 // [1-2] Voltage Step Size (2^n)
264 // 3 = 8 DAC settings between checked values
265 // 2 = 4 DAC settings between checked values
266 // 1 = 2 DAC settings between checked values
267 // 0 = 1 DAC settings between checked values
268 // [3-4] Delay Step Size (2^n)
269 // 3 = 8 LCDL delays between checked values
270 // 2 = 4 LCDL delays between checked values
271 // 1 = 2 LCDL delays between checked values
272 // 0 = 1 LCDL delays between checked values
273 // [5-7] RFU, must be zero
274 //
275 uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
276 // Bitmap that designates the phy's vref source for every pstate
277 // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
278 // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
279 uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
280 // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
281 uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
282 // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
283 uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
284 // Override PhyConfig csr.
285 // 0x0: Use hardware csr value for PhyConfing (recommended)
286 // Other values: Use value for PhyConfig instead of Hardware value.
287 //
288 uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
289 // Total number of DQ bits enabled in PHY Channel A
290 uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
291 // Indicates presence of DRAM at each chip select for PHY channel A.
292 //
293 // 0x1 = CS0 is populated with DRAM
294 // 0x3 = CS0 and CS1 are populated with DRAM
295 //
296 // All other encodings are illegal
297 //
298 int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
299 // This is a signed integer value.
300 // Read to read critical delay difference from cs 1 to cs 0 on Channel A
301 // See PUB Databook section 8.2 for details on use of CDD values.
302 int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
303 // This is a signed integer value.
304 // Read to read critical delay difference from cs 0 to cs 1 on Channel A
305 // See PUB Databook section 8.2 for details on use of CDD values.
306 int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
307 // This is a signed integer value.
308 // Read to write critical delay difference from cs 1 to cs 1 on Channel A
309 // See PUB Databook section 8.2 for details on use of CDD values.
310 int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
311 // This is a signed integer value.
312 // Read to write critical delay difference from cs 1 to cs 0 on Channel A
313 // See PUB Databook section 8.2 for details on use of CDD values.
314 int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
315 // This is a signed integer value.
316 // Read to write critical delay difference from cs 0 to cs 1 on Channel A
317 // See PUB Databook section 8.2 for details on use of CDD values.
318 int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
319 // This is a signed integer value.
320 // Read to write critical delay difference from cs0 to cs 0 on Channel A
321 // See PUB Databook section 8.2 for details on use of CDD values.
322 int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
323 // This is a signed integer value.
324 // Write to read critical delay difference from cs 1 to cs 1 on Channel A
325 // See PUB Databook section 8.2 for details on use of CDD values.
326 int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
327 // This is a signed integer value.
328 // Write to read critical delay difference from cs 1 to cs 0 on Channel A
329 // See PUB Databook section 8.2 for details on use of CDD values.
330 int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
331 // This is a signed integer value.
332 // Write to read critical delay difference from cs 0 to cs 1 on Channel A
333 // See PUB Databook section 8.2 for details on use of CDD values.
334 int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
335 // This is a signed integer value.
336 // Write to read critical delay difference from cs 0 to cs 0 on Channel A
337 // See PUB Databook section 8.2 for details on use of CDD values.
338 int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
339 // This is a signed integer value.
340 // Write to write critical delay difference from cs 1 to cs 0 on Channel A
341 // See PUB Databook section 8.2 for details on use of CDD values.
342 int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
343 // This is a signed integer value.
344 // Write to write critical delay difference from cs 0 to cs 1 on Channel A
345 // See PUB Databook section 8.2 for details on use of CDD values.
346 uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
347 // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
348 uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
349 // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
350 uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
351 // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
352 uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
353 // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
354 uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
355 // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
356 uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
357 // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
358 uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
359 // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
360 uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
361 // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
362 uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
363 // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
364 uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
365 // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
366 uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
367 // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
368 uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
369 // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
370 uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
371 // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
372 uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
373 // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
374 uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
375 // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
376 uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
377 // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
378 uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
379 // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
380 uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
381 // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
382 uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
383 // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
384 uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
385 // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
386 uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
387 // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
388 uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
389 // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
390 uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
391 // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
392 uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
393 // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
394 uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
395 // Terminating Rank for CA bus on Channel A
396 // 0x0 = Rank 0 is terminating rank
397 // 0x1 = Rank 1 is terminating rank
398 uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
399
400 uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
401
402 uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
403 // Trained DQ Vref setting for Ch A Rank 0
404 uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
405 // Trained DQ Vref setting for Ch A Rank 1
406 uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
407 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
408 uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
409 // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
410 uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
411 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
412 uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
413 // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
414 uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
415 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
416 uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
417 // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
418 uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
419 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
420 uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
421 // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
422 uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
423 // Total number of DQ bits enabled in PHY Channel B
424 uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
425 // Indicates presence of DRAM at each chip select for PHY channel B.
426 //
427 // 0x0 = No chip selects are populated with DRAM
428 // 0x1 = CS0 is populated with DRAM
429 // 0x3 = CS0 and CS1 are populated with DRAM
430 //
431 // All other encodings are illegal
432 //
433 int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
434 // This is a signed integer value.
435 // Read to read critical delay difference from cs 1 to cs 0 on Channel B
436 // See PUB Databook section 8.2 for details on use of CDD values.
437 int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
438 // This is a signed integer value.
439 // Read to read critical delay difference from cs 0 to cs 1 on Channel B
440 // See PUB Databook section 8.2 for details on use of CDD values.
441 int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
442 // This is a signed integer value.
443 // Read to write critical delay difference from cs 1 to cs 1 on Channel B
444 // See PUB Databook section 8.2 for details on use of CDD values.
445 int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
446 // This is a signed integer value.
447 // Read to write critical delay difference from cs 1 to cs 0 on Channel B
448 // See PUB Databook section 8.2 for details on use of CDD values.
449 int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
450 // This is a signed integer value.
451 // Read to write critical delay difference from cs 0 to cs 1 on Channel B
452 // See PUB Databook section 8.2 for details on use of CDD values.
453 int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
454 // This is a signed integer value.
455 // Read to write critical delay difference from cs01 to cs 0 on Channel B
456 // See PUB Databook section 8.2 for details on use of CDD values.
457 int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
458 // This is a signed integer value.
459 // Write to read critical delay difference from cs 1 to cs 1 on Channel B
460 // See PUB Databook section 8.2 for details on use of CDD values.
461 int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
462 // This is a signed integer value.
463 // Write to read critical delay difference from cs 1 to cs 0 on Channel B
464 // See PUB Databook section 8.2 for details on use of CDD values.
465 int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
466 // This is a signed integer value.
467 // Write to read critical delay difference from cs 0 to cs 1 on Channel B
468 // See PUB Databook section 8.2 for details on use of CDD values.
469 int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
470 // This is a signed integer value.
471 // Write to read critical delay difference from cs 0 to cs 0 on Channel B
472 // See PUB Databook section 8.2 for details on use of CDD values.
473 int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
474 // This is a signed integer value.
475 // Write to write critical delay difference from cs 1 to cs 0 on Channel B
476 // See PUB Databook section 8.2 for details on use of CDD values.
477 int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
478 // This is a signed integer value.
479 // Write to write critical delay difference from cs 0 to cs 1 on Channel B
480 // See PUB Databook section 8.2 for details on use of CDD values.
481 uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
482 // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
483 uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
484 // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
485 uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
486 // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
487 uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
488 // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
489 uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
490 // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
491 uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
492 // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
493 uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
494 // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
495 uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
496 // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
497 uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
498 // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
499 uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
500 // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
501 uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
502 // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
503 uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
504 // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
505 uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
506 // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
507 uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
508 // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
509 uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
510 // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
511 uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
512 // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
513 uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
514 // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
515 uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
516 // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
517 uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
518 // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
519 uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
520 // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
521 uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
522 // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
523 uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
524 // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
525 uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
526 // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
527 uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
528 // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
529 uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
530 // Terminating Rank for CA bus on Channel B
531 // 0x0 = Rank 0 is terminating rank
532 // 0x1 = Rank 1 is terminating rank
533 uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
534
535 uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
536
537 uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
538 // Trained DQ Vref setting for Ch B Rank 0
539 uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
540 // Trained DQ Vref setting for Ch B Rank 1
541 uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
542 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
543 uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
544 // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
545 uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
546 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
547 uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
548 // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
549 uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
550 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
551 uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
552 // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
553 uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
554 // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
555 uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
556 // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
557} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;