Googler | 695f9d9 | 2023-09-11 15:38:29 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
| 3 | * |
| 4 | * Based on: |
| 5 | * |
| 6 | * ---------------------------------------------------------------------------- |
| 7 | * |
| 8 | * dm644x_emac.h |
| 9 | * |
| 10 | * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM |
| 11 | * |
| 12 | * Copyright (C) 2005 Texas Instruments. |
| 13 | * |
| 14 | * ---------------------------------------------------------------------------- |
| 15 | * |
| 16 | * SPDX-License-Identifier: GPL-2.0+ |
| 17 | * |
| 18 | * Modifications: |
| 19 | * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. |
| 20 | */ |
| 21 | |
| 22 | #ifndef _DM644X_EMAC_H_ |
| 23 | #define _DM644X_EMAC_H_ |
| 24 | |
| 25 | #include <asm/arch/hardware.h> |
| 26 | |
| 27 | #ifdef CONFIG_SOC_DM365 |
| 28 | #define EMAC_BASE_ADDR (0x01d07000) |
| 29 | #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) |
| 30 | #define EMAC_WRAPPER_RAM_ADDR (0x01d08000) |
| 31 | #define EMAC_MDIO_BASE_ADDR (0x01d0b000) |
| 32 | #define DAVINCI_EMAC_VERSION2 |
| 33 | #elif defined(CONFIG_SOC_DA8XX) |
| 34 | #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE |
| 35 | #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE |
| 36 | #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE |
| 37 | #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE |
| 38 | #define DAVINCI_EMAC_VERSION2 |
| 39 | #else |
| 40 | #define EMAC_BASE_ADDR (0x01c80000) |
| 41 | #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) |
| 42 | #define EMAC_WRAPPER_RAM_ADDR (0x01c82000) |
| 43 | #define EMAC_MDIO_BASE_ADDR (0x01c84000) |
| 44 | #endif |
| 45 | |
| 46 | #ifdef CONFIG_SOC_DM646X |
| 47 | #define DAVINCI_EMAC_VERSION2 |
| 48 | #define DAVINCI_EMAC_GIG_ENABLE |
| 49 | #endif |
| 50 | |
| 51 | #ifdef CONFIG_SOC_DM646X |
| 52 | /* MDIO module input frequency */ |
| 53 | #define EMAC_MDIO_BUS_FREQ 76500000 |
| 54 | /* MDIO clock output frequency */ |
| 55 | #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ |
| 56 | #elif defined(CONFIG_SOC_DM365) |
| 57 | /* MDIO module input frequency */ |
| 58 | #define EMAC_MDIO_BUS_FREQ 121500000 |
| 59 | /* MDIO clock output frequency */ |
| 60 | #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ |
| 61 | #elif defined(CONFIG_SOC_DA8XX) |
| 62 | /* MDIO module input frequency */ |
| 63 | #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) |
| 64 | /* MDIO clock output frequency */ |
| 65 | #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ |
| 66 | #else |
| 67 | /* MDIO module input frequency */ |
| 68 | #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ |
| 69 | /* MDIO clock output frequency */ |
| 70 | #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ |
| 71 | #endif |
| 72 | |
| 73 | #define PHY_KSZ8873 (0x00221450) |
| 74 | int ksz8873_is_phy_connected(int phy_addr); |
| 75 | int ksz8873_get_link_speed(int phy_addr); |
| 76 | int ksz8873_init_phy(int phy_addr); |
| 77 | int ksz8873_auto_negotiate(int phy_addr); |
| 78 | |
| 79 | #define PHY_LXT972 (0x001378e2) |
| 80 | int lxt972_is_phy_connected(int phy_addr); |
| 81 | int lxt972_get_link_speed(int phy_addr); |
| 82 | int lxt972_init_phy(int phy_addr); |
| 83 | int lxt972_auto_negotiate(int phy_addr); |
| 84 | |
| 85 | #define PHY_DP83848 (0x20005c90) |
| 86 | int dp83848_is_phy_connected(int phy_addr); |
| 87 | int dp83848_get_link_speed(int phy_addr); |
| 88 | int dp83848_init_phy(int phy_addr); |
| 89 | int dp83848_auto_negotiate(int phy_addr); |
| 90 | |
| 91 | #define PHY_ET1011C (0x282f013) |
| 92 | int et1011c_get_link_speed(int phy_addr); |
| 93 | |
| 94 | #endif /* _DM644X_EMAC_H_ */ |