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Googler15b35d92022-10-03 17:48:21 +08001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
Googlere00b8eb2019-07-08 16:37:07 -07002/*
Googler695f9d92023-09-11 15:38:29 +08003 * arch/arm/include/asm/arch-g12b/usb.h
4 *
5 * Copyright (C) 2020 Amlogic, Inc. All rights reserved.
6 *
Googler15b35d92022-10-03 17:48:21 +08007 */
Googlere00b8eb2019-07-08 16:37:07 -07008
9#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
10#define __ARCH_ARM_MESON_USB_H_U_BOOT__
11
12#include <common.h>
13#include <asm/types.h>
14#include <asm/arch/io.h>
Googler695f9d92023-09-11 15:38:29 +080015/*
16#define USB_PHY_PORT_A (0x40000)
17#define USB_PHY_PORT_B (0xc0000)
18#define USB_PHY_PORT_C (0x100000)
19#define USB_PHY_PORT_D (0x140000)
20#define USB_PHY_PORT_MSK (0x1f0000) */
Googlere00b8eb2019-07-08 16:37:07 -070021
Googler695f9d92023-09-11 15:38:29 +080022#define USB_PHY_PORT_A 0x000000
23#define USB_PHY_PORT_B 0x100000
24#define USB_PHY_PORT_C 0x200000
25#define USB_PHY_PORT_D 0x300000
26#define USB_PHY_PORT_MSK 0x300000
27#define USB_PHY_PORT_MAX 2
Googlere00b8eb2019-07-08 16:37:07 -070028
Googler695f9d92023-09-11 15:38:29 +080029#define PREI_USB_PHY_REG_A 0xc0000000
30#define PREI_USB_PHY_REG_B 0xc0000020
31//#define PREI_USB_PHY_REG_C 0x2210
32//#define PREI_USB_PHY_REG_D 0x2218
33typedef struct usb_peri_reg {
34 volatile uint32_t config;
35 volatile uint32_t ctrl;
36 volatile uint32_t endp_intr;
37 volatile uint32_t adp_bc;
38 volatile uint32_t dbg_uart;
39 volatile uint32_t test;
40 volatile uint32_t tune;
41 volatile uint32_t reserved;
42} usb_peri_reg_t;
Googlere00b8eb2019-07-08 16:37:07 -070043
Googler695f9d92023-09-11 15:38:29 +080044typedef union usb_config_data {
45 /** raw register data */
46 uint32_t d32;
47 /** register bits */
48 struct {
49 unsigned clk_en:1;
50 unsigned clk_sel:3;
51 unsigned clk_div:7;
52 unsigned reserved0:4;
53 unsigned clk_32k_alt_sel:1;
54 unsigned reserved1:15;
55 unsigned test_trig:1;
Googlere00b8eb2019-07-08 16:37:07 -070056 } b;
Googler695f9d92023-09-11 15:38:29 +080057} usb_config_data_t;
Googlere00b8eb2019-07-08 16:37:07 -070058
Googler695f9d92023-09-11 15:38:29 +080059typedef union usb_ctrl_data {
60 /** raw register data */
61 uint32_t d32;
62 /** register bits */
63 struct {
64 unsigned soft_prst:1;
65 unsigned soft_hreset:1;
66 unsigned ss_scaledown_mode:2;
67 unsigned clk_det_rst:1;
68 unsigned intr_sel:1;
69 unsigned reserved:2;
70 unsigned clk_detected:1;
71 unsigned sof_sent_rcvd_tgl:1;
72 unsigned sof_toggle_out:1;
73 unsigned not_used:4;
74 unsigned por:1;
75 unsigned sleepm:1;
76 unsigned txbitstuffennh:1;
77 unsigned txbitstuffenn:1;
78 unsigned commononn:1;
79 unsigned refclksel:2;
80 unsigned fsel:3;
81 unsigned portreset:1;
82 unsigned thread_id:6;
Googlere00b8eb2019-07-08 16:37:07 -070083 } b;
Googler695f9d92023-09-11 15:38:29 +080084} usb_ctrl_data_t;
Googlere00b8eb2019-07-08 16:37:07 -070085
Googler695f9d92023-09-11 15:38:29 +080086typedef union usb_endp_intr_data {
87 /** raw register data */
88 uint32_t d32;
89 /** register bits */
90 struct {
91 unsigned int0:1;
92 unsigned int1:1;
93 unsigned int2:1;
94 unsigned int3:1;
95 unsigned int4:1;
96 unsigned int5:1;
97 unsigned int6:1;
98 unsigned int7:1;
99 unsigned int8:1;
100 unsigned int9:1;
101 unsigned int10:1;
102 unsigned int11:1;
103 unsigned int12:1;
104 unsigned int13:1;
105 unsigned int14:1;
106 unsigned int15:1;
107 unsigned int16:1;
108 unsigned int17:1;
109 unsigned int18:1;
110 unsigned int19:1;
111 unsigned int20:1;
112 unsigned int21:1;
113 unsigned int22:1;
114 unsigned int23:1;
115 unsigned int24:1;
116 unsigned int25:1;
117 unsigned int26:1;
118 unsigned int27:1;
119 unsigned int28:1;
120 unsigned int29:1;
121 unsigned int30:1;
122 unsigned int31:1;
Googlere00b8eb2019-07-08 16:37:07 -0700123 } b;
Googler695f9d92023-09-11 15:38:29 +0800124} usb_endp_intr_data_t;
125
126typedef union usb_adp_bc_data {
127 /** raw register data */
128 uint32_t d32;
129 /** register bits */
130 struct {
131 unsigned vbusvldextsel:1;
132 unsigned vbusvldext:1;
133 unsigned otgdisable:1;
134 unsigned idpullup:1;
135 unsigned drvvbus:1;
136 unsigned adp_prb_en:1;
137 unsigned adp_dischrg:1;
138 unsigned adp_chrg:1;
139 unsigned sessend:1;
140 unsigned device_sess_vld:1;
141 unsigned bvalid:1;
142 unsigned avalid:1;
143 unsigned iddig:1;
144 unsigned vbusvalid:1;
145 unsigned adp_probe:1;
146 unsigned adp_sense:1;
147 unsigned aca_enable:1;
148 unsigned dcd_enable:1;
149 unsigned vdatdetenb:1;
150 unsigned vdatsrcenb:1;
151 unsigned chrgsel:1;
152 unsigned chg_det:1;
153 unsigned aca_pin_range_c:1;
154 unsigned aca_pin_range_b:1;
155 unsigned aca_pin_range_a:1;
156 unsigned aca_pin_gnd:1;
157 unsigned aca_pin_float:1;
158 unsigned not_used:5;
159 } b;
160} usb_adp_bc_data_t;
161
162typedef union usb_dbg_uart_data {
163 /** raw register data */
164 uint32_t d32;
165 /** register bits */
166 struct {
167 unsigned bypass_sel:1;
168 unsigned bypass_dm_en:1;
169 unsigned bypass_dp_en:1;
170 unsigned bypass_dm_data:1;
171 unsigned bypass_dp_data:1;
172 unsigned fsv_minus:1;
173 unsigned fsv_plus:1;
174 unsigned burn_in_test:1;
175 unsigned loopbackenb:1;
176 unsigned set_iddq:1;
177 unsigned ate_reset:1;
178 unsigned reserved:4;
179 unsigned not_used:17;
180 } b;
181} usb_dbg_uart_data_t;
182
183typedef union phy_test_data {
184 /** raw register data */
185 uint32_t d32;
186 /** register bits */
187 struct {
188 unsigned data_in:4;
189 unsigned data_in_en:4;
190 unsigned addr:4;
191 unsigned data_out_sel:1;
192 unsigned clk:1;
193 unsigned vatestenb:2;
194 unsigned data_out:4;
195 unsigned not_used:12;
196 } b;
197} phy_test_data_t;
198
199typedef union phy_tune_data {
200 /** raw register data */
201 uint32_t d32;
202 /** register bits */
203 struct {
204 unsigned tx_res_tune:2;
205 unsigned tx_hsxv_tune:2;
206 unsigned tx_vref_tune:4;
207 unsigned tx_rise_tune:2;
208 unsigned tx_preemp_pulse_tune:1;
209 unsigned tx_preemp_amp_tune:2;
210 unsigned tx_fsls_tune:4;
211 unsigned sqrx_tune:3;
212 unsigned otg_tune:3;
213 unsigned comp_dis_tune:3;
214 unsigned not_used:6;
215 } b;
216} phy_tune_data_t;
217
218
219/*
220 * Clock source index must sync with chip's spec
221 * M1/M2/M3/M6/M8 are different!
222 * This is only for M8
223 */
224#define USB_PHY_CLK_SEL_XTAL 0
225
226#define USB_PHY_A_INTR_BIT (1 << 30)
227#define USB_PHY_B_INTR_BIT (1 << 31)
Googlere00b8eb2019-07-08 16:37:07 -0700228
229/* usb id mode, only after M2
230 mode = 0 : HARDWARE
231 mode = 1 : SW_HOST
232 mode = 2 : SW_DEVICE
233 */
234#define USB_ID_MODE_HARDWARE (1)
235#define USB_ID_MODE_SW_HOST (2)
236#define USB_ID_MODE_SW_DEVICE (3)
Googlere00b8eb2019-07-08 16:37:07 -0700237
Googler695f9d92023-09-11 15:38:29 +0800238typedef struct amlogic_usb_config{
239 /* clock info */
240 int clk_selecter; // usb USB_PHY_CLOCK_SEL_xxx
241 int pll_divider; // when other/ddr/demod pll used, fill this
242
243 /* controller */
244 unsigned int base_addr;
245
246 /* role */
247 int id_mode; // only used after M2
248
249 /* vbus call back */
250 void (* set_vbus_power)(char is_power_on);
251
252 /* battery charging detect call back */
253 int(* battery_charging_det_cb)(char bc_mode);
254#define BC_MODE_UNKNOWN 0
255#define BC_MODE_SDP 1 /* Standard Downstream Port */
256#define BC_MODE_DCP 2 /* Dedicated Charging Port */
257#define BC_MODE_CDP 3 /* Charging Downstream Port */
258
259}amlogic_usb_config_t;
260
261#define BOARD_USB_MODE_HOST 0
262#define BOARD_USB_MODE_SLAVE 1
263#define BOARD_USB_MODE_CHARGER 2
264#define BOARD_USB_MODE_MAX 3
265amlogic_usb_config_t * board_usb_start(int mode,int index);
266int board_usb_stop(int mode,int index);
267void board_usb_init(amlogic_usb_config_t * usb_cfg,int mode);
268int get_usb_count(void);
269#endif //__ARCH_ARM_MESON_USB_H_U_BOOT__