// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 Synaptics Incorporated
 *
 * Author: Jisheng Zhang <jszhang@kernel.org>
 *
 */

#include <linux/clk-provider.h>

#include "clk.h"

static struct clk_onecell_data gateclk_data;
static struct clk_onecell_data clk_data;

static const struct gateclk_desc as370_gates[] __initconst = {
	{ "tspsysclk",		"perifsysclk",	0, CLK_IGNORE_UNUSED },
	{ "usb0coreclk",	"perifsysclk",	1 },
	{ "sdiosysclk",		"perifsysclk",	2 },
	{ "pcie0sys",		"perifsysclk",	3 },
	{ "pcie1sys",		"perifsysclk",	4 },
	{ "nfcsysclk",		"perifsysclk",	5 },
	{ "emmcsysclk",		"perifsysclk",	6 },
	{ "pbridgecoreclk",	"perifsysclk",	7 },
};

static void __init as370_gateclk_setup(struct device_node *np)
{
	int n = ARRAY_SIZE(as370_gates);

	berlin_gateclk_setup(np, as370_gates, &gateclk_data, n);
}
CLK_OF_DECLARE(as370_gateclk, "syna,as370-gateclk", as370_gateclk_setup);

static const struct clk_desc as370_descs[] __initconst = {
	{ "cpufastrefclk",		0x0, CLK_IS_CRITICAL },
	{ "memfastrefclk",		0x4 },
	{ "cfgclk",			0x8, CLK_IS_CRITICAL },
	{ "perifsysclk",		0xc, CLK_IS_CRITICAL },
	{ "atbclk",			0x10 },
	{ "aviosysclk",			0x14, CLK_IS_CRITICAL },
	{ "apbcoreclk",			0x18, CLK_IS_CRITICAL },
	{ "nnasysclk",			0x1c },
	{ "nnacoreclk",			0x20 },
	{ "emmcclk",			0x24 },
	{ "sd0clk",			0x28 },
	{ "pcie_500m_txtestclk",	0x2c },
	{ "pcie_250m_pipetestClk1",	0x30 },
	{ "pcie_250m_pipetestClk2",	0x34 },
	{ "pcie_500m_rxtestclk",	0x38 },
	{ "pcie_serdestestclk",		0x3c },
	{ "nfceccclk",			0x40 },
	{ "nfccoreclk",			0x44 },
	{ "usbOtg60mtestclk",		0x48 },
	{ "usbOtg50mtestclk",		0x4c },
	{ "usbOtg12mtestclk",		0x50 },
	{ "usbOtg480mtestclk",		0x54 },
	{ "bcmclk",			0x58, CLK_IS_CRITICAL },
};

static void __init as370_clk_setup(struct device_node *np)
{
	int n = ARRAY_SIZE(as370_descs);

	berlin_clk_setup(np, as370_descs, &clk_data, n);
}
CLK_OF_DECLARE(as370_clk, "syna,as370-clk", as370_clk_setup);