/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2019 Synaptics Incorporated */

#ifndef mipiPipeCore_h
#define mipiPipeCore_h (){}

#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif


//////
///
/// $INTERFACE TG_PL                                    (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 X                    (P)
///               %unsigned 13 start                     0x0
///               %unsigned 13 end                       0x0
///               %%        6          # Stuffing bits...
///     @ 0x00004 Y                    (P)
///               %unsigned 12 start                     0x0
///               %unsigned 12 end                       0x0
///                                    ###
///                                    * Horizontal and Vertical Start and End values for a plane
///                                    ###
///               %%        8          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      50b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TG_PL
#define h_TG_PL (){}

    #define     RA_TG_PL_X                                     0x0000

    #define     BA_TG_PL_X_start                               0x0000
    #define     B16TG_PL_X_start                               0x0000
    #define   LSb32TG_PL_X_start                                  0
    #define   LSb16TG_PL_X_start                                  0
    #define       bTG_PL_X_start                               13
    #define   MSK32TG_PL_X_start                                  0x00001FFF

    #define     BA_TG_PL_X_end                                 0x0001
    #define     B16TG_PL_X_end                                 0x0000
    #define   LSb32TG_PL_X_end                                    13
    #define   LSb16TG_PL_X_end                                    13
    #define       bTG_PL_X_end                                 13
    #define   MSK32TG_PL_X_end                                    0x03FFE000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PL_Y                                     0x0004

    #define     BA_TG_PL_Y_start                               0x0004
    #define     B16TG_PL_Y_start                               0x0004
    #define   LSb32TG_PL_Y_start                                  0
    #define   LSb16TG_PL_Y_start                                  0
    #define       bTG_PL_Y_start                               12
    #define   MSK32TG_PL_Y_start                                  0x00000FFF

    #define     BA_TG_PL_Y_end                                 0x0005
    #define     B16TG_PL_Y_end                                 0x0004
    #define   LSb32TG_PL_Y_end                                    12
    #define   LSb16TG_PL_Y_end                                    12
    #define       bTG_PL_Y_end                                 12
    #define   MSK32TG_PL_Y_end                                    0x00FFF000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TG_PL {
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PL_X_start(r32)                          _BFGET_(r32,12, 0)
    #define   SET32TG_PL_X_start(r32,v)                        _BFSET_(r32,12, 0,v)
    #define   GET16TG_PL_X_start(r16)                          _BFGET_(r16,12, 0)
    #define   SET16TG_PL_X_start(r16,v)                        _BFSET_(r16,12, 0,v)

    #define   GET32TG_PL_X_end(r32)                            _BFGET_(r32,25,13)
    #define   SET32TG_PL_X_end(r32,v)                          _BFSET_(r32,25,13,v)

    #define     w32TG_PL_X                                     {\
            UNSG32 uX_start                                    : 13;\
            UNSG32 uX_end                                      : 13;\
            UNSG32 RSVDx0_b26                                  :  6;\
          }
    union { UNSG32 u32TG_PL_X;
            struct w32TG_PL_X;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PL_Y_start(r32)                          _BFGET_(r32,11, 0)
    #define   SET32TG_PL_Y_start(r32,v)                        _BFSET_(r32,11, 0,v)
    #define   GET16TG_PL_Y_start(r16)                          _BFGET_(r16,11, 0)
    #define   SET16TG_PL_Y_start(r16,v)                        _BFSET_(r16,11, 0,v)

    #define   GET32TG_PL_Y_end(r32)                            _BFGET_(r32,23,12)
    #define   SET32TG_PL_Y_end(r32,v)                          _BFSET_(r32,23,12,v)

    #define     w32TG_PL_Y                                     {\
            UNSG32 uY_start                                    : 12;\
            UNSG32 uY_end                                      : 12;\
            UNSG32 RSVDx4_b24                                  :  8;\
          }
    union { UNSG32 u32TG_PL_Y;
            struct w32TG_PL_Y;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TG_PL;

    typedef union  T32TG_PL_X
          { UNSG32 u32;
            struct w32TG_PL_X;
                 } T32TG_PL_X;
    typedef union  T32TG_PL_Y
          { UNSG32 u32;
            struct w32TG_PL_Y;
                 } T32TG_PL_Y;
    ///////////////////////////////////////////////////////////

    typedef union  TTG_PL_X
          { UNSG32 u32[1];
            struct {
            struct w32TG_PL_X;
                   };
                 } TTG_PL_X;
    typedef union  TTG_PL_Y
          { UNSG32 u32[1];
            struct {
            struct w32TG_PL_Y;
                   };
                 } TTG_PL_Y;

    ///////////////////////////////////////////////////////////
     SIGN32 TG_PL_drvrd(SIE_TG_PL *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TG_PL_drvwr(SIE_TG_PL *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TG_PL_reset(SIE_TG_PL *p);
     SIGN32 TG_PL_cmp  (SIE_TG_PL *p, SIE_TG_PL *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TG_PL_check(p,pie,pfx,hLOG) TG_PL_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TG_PL_print(p,    pfx,hLOG) TG_PL_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TG_PL
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE TG_PRG                                   (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL                 (P)
///               %unsigned 2  mode                      0x2
///                                    ###
///                                    * Generates the hcnt and vcnt with the sref. The different modes programmable are : 0 = free running mode, 1 = sync mode, 2= Semi sync mode
///                                    ###
///               %unsigned 8  lwin                      0xF
///                                    ###
///                                    * Used in generation of lock sync and lock active for resetting hcnt and vcnt in TG
///                                    ###
///               %unsigned 12 frst                      0x0
///                                    ###
///                                    * Position during vertical blanking time at which frame reset is generated
///                                    ###
///               %unsigned 10 freeze                    0x0
///                                    ###
///                                    * Freeze controls for TG; this register should be used by SW when it wants to modify the plane position/size registers so that HW does not pick-up the intermediate values written.
///                                    ###
///     @ 0x00004 CTRL1                (P)
///               %unsigned 2  sync_ctrl                 0x0
///                                    ###
///                                    * To provide low latency for pass-through where the latency requirement is less than one frame
///                                    * [0] : Enable Bit. For low latency pass-through, enable this bit to 1’b1. Default it is zero.
///                                    * [1] : The SW will get active video start event from Cypress and then it will program SYNC bit SYNC_CTRL[1] to 1’b1 in VPP for low latency graphics (RGB) pass through.
///                                    ###
///               %unsigned 9  res_change_en             0x0
///                                    ###
///                                    * Enable bits for dynamic resolution change of registers used for generating timing signals
///                                    * [0] – enable bit for Htotal/Vtotal programmable register
///                                    * [1] - enable bit for VX programmable register
///                                    * [2] - enable bit for Hsync (start & end) programmable register
///                                    * [3] - enable bit for Vsync (startY & endY) programmable register
///                                    * [4] - enable bit for Plane0 (startX & endX) programmable register
///                                    * [5] - enable bit for Plane0 (startY & endY) programmable register
///                                    * [6] - enable bit for Field (startX & endX) programmable register
///                                    * [7] - enable bit for Field (startY & endY) programmable register
///                                    * [8] - enable bit for Vsync (startX & endX) programmable register
///                                    ###
///               %%        21         # Stuffing bits...
///     @ 0x00008 Total                (P)
///               %unsigned 12 vertical                  0x0
///                                    ###
///                                    * Vertical Total values (in lines).
///                                    ###
///               %unsigned 13 horizontal                0x0
///                                    ###
///                                    * Horizontal Total values (in pixels)
///                                    ###
///               %%        7          # Stuffing bits...
///     @ 0x0000C Initial              (P)
///               %unsigned 13 xi                        0x0
///                                    ###
///                                    * Initial Horizontal position value
///                                    ###
///               %unsigned 12 yi                        0x0
///                                    ###
///                                    * Initial Vertical position value
///                                    ###
///               %%        7          # Stuffing bits...
///     @ 0x00010 HSYNC                (P)
///               %unsigned 13 h_start                   0x0
///                                    ###
///                                    * Horizontal Start value indicated for Hsync position
///                                    ###
///               %unsigned 13 h_end                     0x0
///                                    ###
///                                    * Horizontal End value indicated for Hsync position
///                                    ###
///               %%        6          # Stuffing bits...
///     @ 0x00014 VSYNC                (P)
///               %unsigned 12 v_start                   0x0
///                                    ###
///                                    * Vertical Start value indicated for Vsync position
///                                    ###
///               %unsigned 12 v_end                     0x0
///                                    ###
///                                    * Vertical End value indicated for Vsync position
///                                    ###
///               %%        8          # Stuffing bits...
///     @ 0x00018 VS                   (P)
///               %unsigned 13 h_start                   0x0
///                                    ###
///                                    * Horizontal Start value indicated for Vsync position
///                                    ###
///               %unsigned 13 h_end                     0x0
///                                    ###
///                                    * Horizontal End value indicated for Vsync position
///                                    ###
///               %%        6          # Stuffing bits...
///     @ 0x0001C FT                   (P)
///               %unsigned 8  frame                     0x0
///                                    ###
///                                    * Frame total value
///                                    ###
///               %%        24         # Stuffing bits...
///     @ 0x00020 VX                   (P)
///               %unsigned 13 vx                        0x0
///                                    ###
///                                    * Horizontal positions at which vertical active data
///                                    ###
///               %%        19         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      36B, bits:     190b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TG_PRG
#define h_TG_PRG (){}

    #define     RA_TG_PRG_CTRL                                 0x0000

    #define     BA_TG_PRG_CTRL_mode                            0x0000
    #define     B16TG_PRG_CTRL_mode                            0x0000
    #define   LSb32TG_PRG_CTRL_mode                               0
    #define   LSb16TG_PRG_CTRL_mode                               0
    #define       bTG_PRG_CTRL_mode                            2
    #define   MSK32TG_PRG_CTRL_mode                               0x00000003

    #define     BA_TG_PRG_CTRL_lwin                            0x0000
    #define     B16TG_PRG_CTRL_lwin                            0x0000
    #define   LSb32TG_PRG_CTRL_lwin                               2
    #define   LSb16TG_PRG_CTRL_lwin                               2
    #define       bTG_PRG_CTRL_lwin                            8
    #define   MSK32TG_PRG_CTRL_lwin                               0x000003FC

    #define     BA_TG_PRG_CTRL_frst                            0x0001
    #define     B16TG_PRG_CTRL_frst                            0x0000
    #define   LSb32TG_PRG_CTRL_frst                               10
    #define   LSb16TG_PRG_CTRL_frst                               10
    #define       bTG_PRG_CTRL_frst                            12
    #define   MSK32TG_PRG_CTRL_frst                               0x003FFC00

    #define     BA_TG_PRG_CTRL_freeze                          0x0002
    #define     B16TG_PRG_CTRL_freeze                          0x0002
    #define   LSb32TG_PRG_CTRL_freeze                             22
    #define   LSb16TG_PRG_CTRL_freeze                             6
    #define       bTG_PRG_CTRL_freeze                          10
    #define   MSK32TG_PRG_CTRL_freeze                             0xFFC00000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_CTRL1                                0x0004

    #define     BA_TG_PRG_CTRL1_sync_ctrl                      0x0004
    #define     B16TG_PRG_CTRL1_sync_ctrl                      0x0004
    #define   LSb32TG_PRG_CTRL1_sync_ctrl                         0
    #define   LSb16TG_PRG_CTRL1_sync_ctrl                         0
    #define       bTG_PRG_CTRL1_sync_ctrl                      2
    #define   MSK32TG_PRG_CTRL1_sync_ctrl                         0x00000003

    #define     BA_TG_PRG_CTRL1_res_change_en                  0x0004
    #define     B16TG_PRG_CTRL1_res_change_en                  0x0004
    #define   LSb32TG_PRG_CTRL1_res_change_en                     2
    #define   LSb16TG_PRG_CTRL1_res_change_en                     2
    #define       bTG_PRG_CTRL1_res_change_en                  9
    #define   MSK32TG_PRG_CTRL1_res_change_en                     0x000007FC
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_Total                                0x0008

    #define     BA_TG_PRG_Total_vertical                       0x0008
    #define     B16TG_PRG_Total_vertical                       0x0008
    #define   LSb32TG_PRG_Total_vertical                          0
    #define   LSb16TG_PRG_Total_vertical                          0
    #define       bTG_PRG_Total_vertical                       12
    #define   MSK32TG_PRG_Total_vertical                          0x00000FFF

    #define     BA_TG_PRG_Total_horizontal                     0x0009
    #define     B16TG_PRG_Total_horizontal                     0x0008
    #define   LSb32TG_PRG_Total_horizontal                        12
    #define   LSb16TG_PRG_Total_horizontal                        12
    #define       bTG_PRG_Total_horizontal                     13
    #define   MSK32TG_PRG_Total_horizontal                        0x01FFF000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_Initial                              0x000C

    #define     BA_TG_PRG_Initial_xi                           0x000C
    #define     B16TG_PRG_Initial_xi                           0x000C
    #define   LSb32TG_PRG_Initial_xi                              0
    #define   LSb16TG_PRG_Initial_xi                              0
    #define       bTG_PRG_Initial_xi                           13
    #define   MSK32TG_PRG_Initial_xi                              0x00001FFF

    #define     BA_TG_PRG_Initial_yi                           0x000D
    #define     B16TG_PRG_Initial_yi                           0x000C
    #define   LSb32TG_PRG_Initial_yi                              13
    #define   LSb16TG_PRG_Initial_yi                              13
    #define       bTG_PRG_Initial_yi                           12
    #define   MSK32TG_PRG_Initial_yi                              0x01FFE000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_HSYNC                                0x0010

    #define     BA_TG_PRG_HSYNC_h_start                        0x0010
    #define     B16TG_PRG_HSYNC_h_start                        0x0010
    #define   LSb32TG_PRG_HSYNC_h_start                           0
    #define   LSb16TG_PRG_HSYNC_h_start                           0
    #define       bTG_PRG_HSYNC_h_start                        13
    #define   MSK32TG_PRG_HSYNC_h_start                           0x00001FFF

    #define     BA_TG_PRG_HSYNC_h_end                          0x0011
    #define     B16TG_PRG_HSYNC_h_end                          0x0010
    #define   LSb32TG_PRG_HSYNC_h_end                             13
    #define   LSb16TG_PRG_HSYNC_h_end                             13
    #define       bTG_PRG_HSYNC_h_end                          13
    #define   MSK32TG_PRG_HSYNC_h_end                             0x03FFE000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_VSYNC                                0x0014

    #define     BA_TG_PRG_VSYNC_v_start                        0x0014
    #define     B16TG_PRG_VSYNC_v_start                        0x0014
    #define   LSb32TG_PRG_VSYNC_v_start                           0
    #define   LSb16TG_PRG_VSYNC_v_start                           0
    #define       bTG_PRG_VSYNC_v_start                        12
    #define   MSK32TG_PRG_VSYNC_v_start                           0x00000FFF

    #define     BA_TG_PRG_VSYNC_v_end                          0x0015
    #define     B16TG_PRG_VSYNC_v_end                          0x0014
    #define   LSb32TG_PRG_VSYNC_v_end                             12
    #define   LSb16TG_PRG_VSYNC_v_end                             12
    #define       bTG_PRG_VSYNC_v_end                          12
    #define   MSK32TG_PRG_VSYNC_v_end                             0x00FFF000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_VS                                   0x0018

    #define     BA_TG_PRG_VS_h_start                           0x0018
    #define     B16TG_PRG_VS_h_start                           0x0018
    #define   LSb32TG_PRG_VS_h_start                              0
    #define   LSb16TG_PRG_VS_h_start                              0
    #define       bTG_PRG_VS_h_start                           13
    #define   MSK32TG_PRG_VS_h_start                              0x00001FFF

    #define     BA_TG_PRG_VS_h_end                             0x0019
    #define     B16TG_PRG_VS_h_end                             0x0018
    #define   LSb32TG_PRG_VS_h_end                                13
    #define   LSb16TG_PRG_VS_h_end                                13
    #define       bTG_PRG_VS_h_end                             13
    #define   MSK32TG_PRG_VS_h_end                                0x03FFE000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_FT                                   0x001C

    #define     BA_TG_PRG_FT_frame                             0x001C
    #define     B16TG_PRG_FT_frame                             0x001C
    #define   LSb32TG_PRG_FT_frame                                0
    #define   LSb16TG_PRG_FT_frame                                0
    #define       bTG_PRG_FT_frame                             8
    #define   MSK32TG_PRG_FT_frame                                0x000000FF
    ///////////////////////////////////////////////////////////
    #define     RA_TG_PRG_VX                                   0x0020

    #define     BA_TG_PRG_VX_vx                                0x0020
    #define     B16TG_PRG_VX_vx                                0x0020
    #define   LSb32TG_PRG_VX_vx                                   0
    #define   LSb16TG_PRG_VX_vx                                   0
    #define       bTG_PRG_VX_vx                                13
    #define   MSK32TG_PRG_VX_vx                                   0x00001FFF
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TG_PRG {
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_CTRL_mode(r32)                       _BFGET_(r32, 1, 0)
    #define   SET32TG_PRG_CTRL_mode(r32,v)                     _BFSET_(r32, 1, 0,v)
    #define   GET16TG_PRG_CTRL_mode(r16)                       _BFGET_(r16, 1, 0)
    #define   SET16TG_PRG_CTRL_mode(r16,v)                     _BFSET_(r16, 1, 0,v)

    #define   GET32TG_PRG_CTRL_lwin(r32)                       _BFGET_(r32, 9, 2)
    #define   SET32TG_PRG_CTRL_lwin(r32,v)                     _BFSET_(r32, 9, 2,v)
    #define   GET16TG_PRG_CTRL_lwin(r16)                       _BFGET_(r16, 9, 2)
    #define   SET16TG_PRG_CTRL_lwin(r16,v)                     _BFSET_(r16, 9, 2,v)

    #define   GET32TG_PRG_CTRL_frst(r32)                       _BFGET_(r32,21,10)
    #define   SET32TG_PRG_CTRL_frst(r32,v)                     _BFSET_(r32,21,10,v)

    #define   GET32TG_PRG_CTRL_freeze(r32)                     _BFGET_(r32,31,22)
    #define   SET32TG_PRG_CTRL_freeze(r32,v)                   _BFSET_(r32,31,22,v)
    #define   GET16TG_PRG_CTRL_freeze(r16)                     _BFGET_(r16,15, 6)
    #define   SET16TG_PRG_CTRL_freeze(r16,v)                   _BFSET_(r16,15, 6,v)

    #define     w32TG_PRG_CTRL                                 {\
            UNSG32 uCTRL_mode                                  :  2;\
            UNSG32 uCTRL_lwin                                  :  8;\
            UNSG32 uCTRL_frst                                  : 12;\
            UNSG32 uCTRL_freeze                                : 10;\
          }
    union { UNSG32 u32TG_PRG_CTRL;
            struct w32TG_PRG_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_CTRL1_sync_ctrl(r32)                 _BFGET_(r32, 1, 0)
    #define   SET32TG_PRG_CTRL1_sync_ctrl(r32,v)               _BFSET_(r32, 1, 0,v)
    #define   GET16TG_PRG_CTRL1_sync_ctrl(r16)                 _BFGET_(r16, 1, 0)
    #define   SET16TG_PRG_CTRL1_sync_ctrl(r16,v)               _BFSET_(r16, 1, 0,v)

    #define   GET32TG_PRG_CTRL1_res_change_en(r32)             _BFGET_(r32,10, 2)
    #define   SET32TG_PRG_CTRL1_res_change_en(r32,v)           _BFSET_(r32,10, 2,v)
    #define   GET16TG_PRG_CTRL1_res_change_en(r16)             _BFGET_(r16,10, 2)
    #define   SET16TG_PRG_CTRL1_res_change_en(r16,v)           _BFSET_(r16,10, 2,v)

    #define     w32TG_PRG_CTRL1                                {\
            UNSG32 uCTRL1_sync_ctrl                            :  2;\
            UNSG32 uCTRL1_res_change_en                        :  9;\
            UNSG32 RSVDx4_b11                                  : 21;\
          }
    union { UNSG32 u32TG_PRG_CTRL1;
            struct w32TG_PRG_CTRL1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_Total_vertical(r32)                  _BFGET_(r32,11, 0)
    #define   SET32TG_PRG_Total_vertical(r32,v)                _BFSET_(r32,11, 0,v)
    #define   GET16TG_PRG_Total_vertical(r16)                  _BFGET_(r16,11, 0)
    #define   SET16TG_PRG_Total_vertical(r16,v)                _BFSET_(r16,11, 0,v)

    #define   GET32TG_PRG_Total_horizontal(r32)                _BFGET_(r32,24,12)
    #define   SET32TG_PRG_Total_horizontal(r32,v)              _BFSET_(r32,24,12,v)

    #define     w32TG_PRG_Total                                {\
            UNSG32 uTotal_vertical                             : 12;\
            UNSG32 uTotal_horizontal                           : 13;\
            UNSG32 RSVDx8_b25                                  :  7;\
          }
    union { UNSG32 u32TG_PRG_Total;
            struct w32TG_PRG_Total;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_Initial_xi(r32)                      _BFGET_(r32,12, 0)
    #define   SET32TG_PRG_Initial_xi(r32,v)                    _BFSET_(r32,12, 0,v)
    #define   GET16TG_PRG_Initial_xi(r16)                      _BFGET_(r16,12, 0)
    #define   SET16TG_PRG_Initial_xi(r16,v)                    _BFSET_(r16,12, 0,v)

    #define   GET32TG_PRG_Initial_yi(r32)                      _BFGET_(r32,24,13)
    #define   SET32TG_PRG_Initial_yi(r32,v)                    _BFSET_(r32,24,13,v)

    #define     w32TG_PRG_Initial                              {\
            UNSG32 uInitial_xi                                 : 13;\
            UNSG32 uInitial_yi                                 : 12;\
            UNSG32 RSVDxC_b25                                  :  7;\
          }
    union { UNSG32 u32TG_PRG_Initial;
            struct w32TG_PRG_Initial;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_HSYNC_h_start(r32)                   _BFGET_(r32,12, 0)
    #define   SET32TG_PRG_HSYNC_h_start(r32,v)                 _BFSET_(r32,12, 0,v)
    #define   GET16TG_PRG_HSYNC_h_start(r16)                   _BFGET_(r16,12, 0)
    #define   SET16TG_PRG_HSYNC_h_start(r16,v)                 _BFSET_(r16,12, 0,v)

    #define   GET32TG_PRG_HSYNC_h_end(r32)                     _BFGET_(r32,25,13)
    #define   SET32TG_PRG_HSYNC_h_end(r32,v)                   _BFSET_(r32,25,13,v)

    #define     w32TG_PRG_HSYNC                                {\
            UNSG32 uHSYNC_h_start                              : 13;\
            UNSG32 uHSYNC_h_end                                : 13;\
            UNSG32 RSVDx10_b26                                 :  6;\
          }
    union { UNSG32 u32TG_PRG_HSYNC;
            struct w32TG_PRG_HSYNC;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_VSYNC_v_start(r32)                   _BFGET_(r32,11, 0)
    #define   SET32TG_PRG_VSYNC_v_start(r32,v)                 _BFSET_(r32,11, 0,v)
    #define   GET16TG_PRG_VSYNC_v_start(r16)                   _BFGET_(r16,11, 0)
    #define   SET16TG_PRG_VSYNC_v_start(r16,v)                 _BFSET_(r16,11, 0,v)

    #define   GET32TG_PRG_VSYNC_v_end(r32)                     _BFGET_(r32,23,12)
    #define   SET32TG_PRG_VSYNC_v_end(r32,v)                   _BFSET_(r32,23,12,v)

    #define     w32TG_PRG_VSYNC                                {\
            UNSG32 uVSYNC_v_start                              : 12;\
            UNSG32 uVSYNC_v_end                                : 12;\
            UNSG32 RSVDx14_b24                                 :  8;\
          }
    union { UNSG32 u32TG_PRG_VSYNC;
            struct w32TG_PRG_VSYNC;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_VS_h_start(r32)                      _BFGET_(r32,12, 0)
    #define   SET32TG_PRG_VS_h_start(r32,v)                    _BFSET_(r32,12, 0,v)
    #define   GET16TG_PRG_VS_h_start(r16)                      _BFGET_(r16,12, 0)
    #define   SET16TG_PRG_VS_h_start(r16,v)                    _BFSET_(r16,12, 0,v)

    #define   GET32TG_PRG_VS_h_end(r32)                        _BFGET_(r32,25,13)
    #define   SET32TG_PRG_VS_h_end(r32,v)                      _BFSET_(r32,25,13,v)

    #define     w32TG_PRG_VS                                   {\
            UNSG32 uVS_h_start                                 : 13;\
            UNSG32 uVS_h_end                                   : 13;\
            UNSG32 RSVDx18_b26                                 :  6;\
          }
    union { UNSG32 u32TG_PRG_VS;
            struct w32TG_PRG_VS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_FT_frame(r32)                        _BFGET_(r32, 7, 0)
    #define   SET32TG_PRG_FT_frame(r32,v)                      _BFSET_(r32, 7, 0,v)
    #define   GET16TG_PRG_FT_frame(r16)                        _BFGET_(r16, 7, 0)
    #define   SET16TG_PRG_FT_frame(r16,v)                      _BFSET_(r16, 7, 0,v)

    #define     w32TG_PRG_FT                                   {\
            UNSG32 uFT_frame                                   :  8;\
            UNSG32 RSVDx1C_b8                                  : 24;\
          }
    union { UNSG32 u32TG_PRG_FT;
            struct w32TG_PRG_FT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_PRG_VX_vx(r32)                           _BFGET_(r32,12, 0)
    #define   SET32TG_PRG_VX_vx(r32,v)                         _BFSET_(r32,12, 0,v)
    #define   GET16TG_PRG_VX_vx(r16)                           _BFGET_(r16,12, 0)
    #define   SET16TG_PRG_VX_vx(r16,v)                         _BFSET_(r16,12, 0,v)

    #define     w32TG_PRG_VX                                   {\
            UNSG32 uVX_vx                                      : 13;\
            UNSG32 RSVDx20_b13                                 : 19;\
          }
    union { UNSG32 u32TG_PRG_VX;
            struct w32TG_PRG_VX;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TG_PRG;

    typedef union  T32TG_PRG_CTRL
          { UNSG32 u32;
            struct w32TG_PRG_CTRL;
                 } T32TG_PRG_CTRL;
    typedef union  T32TG_PRG_CTRL1
          { UNSG32 u32;
            struct w32TG_PRG_CTRL1;
                 } T32TG_PRG_CTRL1;
    typedef union  T32TG_PRG_Total
          { UNSG32 u32;
            struct w32TG_PRG_Total;
                 } T32TG_PRG_Total;
    typedef union  T32TG_PRG_Initial
          { UNSG32 u32;
            struct w32TG_PRG_Initial;
                 } T32TG_PRG_Initial;
    typedef union  T32TG_PRG_HSYNC
          { UNSG32 u32;
            struct w32TG_PRG_HSYNC;
                 } T32TG_PRG_HSYNC;
    typedef union  T32TG_PRG_VSYNC
          { UNSG32 u32;
            struct w32TG_PRG_VSYNC;
                 } T32TG_PRG_VSYNC;
    typedef union  T32TG_PRG_VS
          { UNSG32 u32;
            struct w32TG_PRG_VS;
                 } T32TG_PRG_VS;
    typedef union  T32TG_PRG_FT
          { UNSG32 u32;
            struct w32TG_PRG_FT;
                 } T32TG_PRG_FT;
    typedef union  T32TG_PRG_VX
          { UNSG32 u32;
            struct w32TG_PRG_VX;
                 } T32TG_PRG_VX;
    ///////////////////////////////////////////////////////////

    typedef union  TTG_PRG_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_CTRL;
                   };
                 } TTG_PRG_CTRL;
    typedef union  TTG_PRG_CTRL1
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_CTRL1;
                   };
                 } TTG_PRG_CTRL1;
    typedef union  TTG_PRG_Total
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_Total;
                   };
                 } TTG_PRG_Total;
    typedef union  TTG_PRG_Initial
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_Initial;
                   };
                 } TTG_PRG_Initial;
    typedef union  TTG_PRG_HSYNC
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_HSYNC;
                   };
                 } TTG_PRG_HSYNC;
    typedef union  TTG_PRG_VSYNC
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_VSYNC;
                   };
                 } TTG_PRG_VSYNC;
    typedef union  TTG_PRG_VS
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_VS;
                   };
                 } TTG_PRG_VS;
    typedef union  TTG_PRG_FT
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_FT;
                   };
                 } TTG_PRG_FT;
    typedef union  TTG_PRG_VX
          { UNSG32 u32[1];
            struct {
            struct w32TG_PRG_VX;
                   };
                 } TTG_PRG_VX;

    ///////////////////////////////////////////////////////////
     SIGN32 TG_PRG_drvrd(SIE_TG_PRG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TG_PRG_drvwr(SIE_TG_PRG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TG_PRG_reset(SIE_TG_PRG *p);
     SIGN32 TG_PRG_cmp  (SIE_TG_PRG *p, SIE_TG_PRG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TG_PRG_check(p,pie,pfx,hLOG) TG_PRG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TG_PRG_print(p,    pfx,hLOG) TG_PRG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TG_PRG
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE TG                      biu              (4,4)
///     ###
///     * Register specification of interface Timing Generator
///     * There are two counters in the timing generator module. hCntr (from 1 to SIZE_X) and vCntr (from 1 to SIZE_Y).
///     * When start, the initial value will be loaded to the xCnt and yCnt
///     ###
///     # # ----------------------------------------------------------
///     @ 0x00000 INIT                 (P)
///               %unsigned 16 Y                         0x1
///                                    ###
///                                    * Initial Y value which will be used to load Y counter when tg is enabled.
///                                    ###
///               %unsigned 16 X                         0x1
///                                    ###
///                                    * Initial X value which will be used to load X counter when tg is enabled.
///                                    * A whole frame scan size.
///                                    ###
///     @ 0x00004 SIZE                 (P)
///               %unsigned 16 Y                         0x465
///                                    ###
///                                    * Total scan lines per frame.
///                                    ###
///               %unsigned 16 X                         0x898
///                                    ###
///                                    * Total scan clock cycles per line.
///                                    * Hsync
///                                    ###
///     @ 0x00008 HS                   (P)
///               %unsigned 16 FE                        0x1
///                                    ###
///                                    * Hsync front edge. The first pixel position of hsync pulse.
///                                    ###
///               %unsigned 16 BE                        0x2C
///                                    ###
///                                    * Hsync back edge. The last pixel position of hsync pulse.
///                                    * HS = hCntr>=FE & hCntr<=BE
///                                    * HBlanking
///                                    ###
///     @ 0x0000C HB                   (P)
///               %unsigned 16 FE                        0x841
///                                    ###
///                                    * Hblank front edge. The first pixel position of the hBlank pulse. SIZEX-HFP = 2200-88+1
///                                    ###
///               %unsigned 16 BE                        0xC0
///                                    ###
///                                    * Hblank back edge. The last pixel position of the hBlank pulse. HPW + HBP = 44+148
///                                    * HB = hCntr>=FE || hCntr<=BE.
///                                    ###
///     @ 0x00010 HB_CR                (P)
///               %unsigned 16 FE                        0x841
///                                    ###
///                                    * Hblank front edge. The first pixel position of the hBlank pulse. SIZEX-HFP = 2200-88+1
///                                    ###
///               %unsigned 16 BE                        0xC0
///                                    ###
///                                    * Hblank back edge. The last pixel position of the hBlank pulse. HPW + HBP = 44+148
///                                    * HB_CR = hCntr>=FE || hCntr<=BE.
///                                    ###
///     @ 0x00014 HB_CR2               (P)
///               %unsigned 16 FE                        0x841
///                                    ###
///                                    * Hblank front edge. The first pixel position of the hBlank pulse. SIZEX-HFP = 2200-88+1
///                                    * Note : to be programmed with different value (only when cropping is required). Else to be programmed same as HB FE (above register)
///                                    ###
///               %unsigned 16 BE                        0xC0
///                                    ###
///                                    * Hblank back edge. The last pixel position of the hBlank pulse. HPW + HBP = 44+148
///                                    * Note : to be programmed with different value (only when cropping is required). Else to be programmed same as HB BE (above register)
///                                    * HB = hCntr>=FE || hCntr<=BE.
///                                    * VS0 defines the first first pixel position of the first VSYNC (progressive or interlace mode) pulse.
///                                    * For example
///                                    * 1080i60, the VTP is the last pixel of the last line. So set both VLCNT0 and VPCNT0 to 0.
///                                    ###
///     @ 0x00018 VS0                  (P)
///               %unsigned 16 FE                        0x1
///                                    ###
///                                    * Vsync pulse front edge.
///                                    * Vsync will be asserted at the beginning of this line.
///                                    ###
///               %unsigned 16 BE                        0x5
///                                    ###
///                                    * Vsync pulse back edge.
///                                    * Vsycn pulse will be de-asserted after the end of this line.
///                                    * Vsync = (vCntr>=FE & vCntr<=BE)
///                                    * Vsync pulse 1
///                                    * defines the first pixel position of the second vSync pulse. For example
///                                    * 1080i60, the VTP is pixel 1100 of line 563. So set both VLCNT2=563. and VPCNT2 to 1100.
///                                    ###
///     @ 0x0001C VS1                  (P)
///               %unsigned 16 FE                        0x233
///                                    ###
///                                    * Vsync pulse 1 front edge line position.
///                                    * Vsync pulse 1 will be asserted at the middle of this line.
///                                    ###
///               %unsigned 16 BE                        0x238
///                                    ###
///                                    * Vsync pulse 1 back edge line position.
///                                    * Vsync pulse 1 will be de-asserted at the middle of this line.
///                                    * Vsync1 = (vCntr>=FE & hCntr>SIZEX/2) & (vCntr<=BE & hCntr<=SIZEX/2)
///                                    * Vertical blanking.
///                                    * VB0 parameter definietion
///                                    ###
///     @ 0x00020 VB0                  (P)
///               %unsigned 16 FE                        0x462
///                                    ###
///                                    * Vblank front edge line position
///                                    * The first line of the vertical blanking.
///                                    ###
///               %unsigned 16 BE                        0x29
///                                    ###
///                                    * Vblank back edge line position
///                                    * the last line number of the vertical blanking
///                                    * The default value is used for 1080p case.
///                                    * Vblank0 = vCntr>=FE || vCntr<=BE
///                                    ###
///     @ 0x00024 VB0_CR               (P)
///               %unsigned 16 FE                        0x462
///                                    ###
///                                    * Vblank front edge line position
///                                    * The first line of the vertical blanking.
///                                    ###
///               %unsigned 16 BE                        0x29
///                                    ###
///                                    * Vblank back edge line position
///                                    * the last line number of the vertical blanking
///                                    * The default value is used for 1080p case.
///                                    * Vblank0_CR = vCntr>=FE || vCntr<=BE
///                                    ###
///     @ 0x00028 VB0_CR2              (P)
///               %unsigned 16 FE                        0x462
///                                    ###
///                                    * Vblank front edge line position
///                                    * The first line of the vertical blanking.
///                                    * Note : to be programmed with different value only when cropping is required. Else to be programmed same as VB0 FE (above register)
///                                    ###
///               %unsigned 16 BE                        0x29
///                                    ###
///                                    * Vblank back edge line position
///                                    * the last line number of the vertical blanking
///                                    * The default value is used for 1080p case.
///                                    * Note : to be programmed with different value only when cropping is required. Else to be programmed same as VB0 BE (above register)
///                                    * Vblank0 = vCntr>=FE || vCntr<=BE
///                                    ###
///     @ 0x0002C VB1                  (P)
///               %unsigned 16 FE                        0x231
///                                    ###
///                                    * Vblank front edge line postion
///                                    * The first line number of VB1.
///                                    ###
///               %unsigned 16 BE                        0x247
///                                    ###
///                                    * Vblank back edge line postion
///                                    * the last line numer of VB1.
///                                    * VB1 = (vCntr>=FE & vCntr<=BE)
///                                    * SCAN mode
///                                    ###
///     @ 0x00030 SCAN                 (P)
///               %unsigned 1  MODE                      0x0
///                                    : PROG                      0x0
///                                    : INTER                     0x1
///                                                 ###
///                                                 * Frame done interrupt position
///                                                 ###
///               %%        31         # Stuffing bits...
///     @ 0x00034 INTPOS               (P)
///               %unsigned 16 FRAME                     0x465
///                                    ###
///                                    * Frame interrupt status will be set at the end of this line.
///                                    * Program 0 to this register will disable frame interrupt.
///                                    ###
///               %unsigned 16 FIELD                     0x233
///                                    ###
///                                    * Field interrupt status will be set at the end of this line.
///                                    * Program 0 to this register will disable field interrupt.
///                                    * MODE
///                                    ###
///     @ 0x00038 MODE                 (P)
///               %unsigned 1  EN                        0x0
///                                    : MASTER                    0x0
///                                    : SLAVE                     0x1
///                                                 ###
///                                                 * In master mode, TG drive the control signal.
///                                                 * In slave mode, TG take the external hsync and vsync, it generate the internal sync and blank signal based on the programmed register and external hsync and vsync.
///                                                 * HREF input for slave mode.
///                                                 ###
///               %%        31         # Stuffing bits...
///     @ 0x0003C HVREF                (P)
///               %unsigned 1  SEL                       0x0
///                                    : SYNC                      0x0
///                                    : BLANK                     0x1
///                                                 ###
///                                                 * In slave mode, tg will sync to the external tg generated HREF/VREF which could be HSYBC/VSYNC or HBLANK/VBLANK. Currently only HSYNC/VSYNC is supported.
///                                                 * HSYNC and VSYNC have to be come in pair.
///                                                 ###
///               %unsigned 1  POL                       0x0
///                                    : NEG_PULSE                 0x0
///                                    : POS_PULSE                 0x1
///                                                 ###
///                                                 * 0 : indicate the input HREF/VREF are negative pulses
///                                                 * 1: indicate the input HREF/VREFare positive pulses.
///                                                 * HREF and VREF have to be the same polarity.
///                                                 * End of TG register group
///                                                 ###
///               %%        30         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      64B, bits:     420b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_TG
#define h_TG (){}

    #define     RA_TG_INIT                                     0x0000

    #define     BA_TG_INIT_Y                                   0x0000
    #define     B16TG_INIT_Y                                   0x0000
    #define   LSb32TG_INIT_Y                                      0
    #define   LSb16TG_INIT_Y                                      0
    #define       bTG_INIT_Y                                   16
    #define   MSK32TG_INIT_Y                                      0x0000FFFF

    #define     BA_TG_INIT_X                                   0x0002
    #define     B16TG_INIT_X                                   0x0002
    #define   LSb32TG_INIT_X                                      16
    #define   LSb16TG_INIT_X                                      0
    #define       bTG_INIT_X                                   16
    #define   MSK32TG_INIT_X                                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_SIZE                                     0x0004

    #define     BA_TG_SIZE_Y                                   0x0004
    #define     B16TG_SIZE_Y                                   0x0004
    #define   LSb32TG_SIZE_Y                                      0
    #define   LSb16TG_SIZE_Y                                      0
    #define       bTG_SIZE_Y                                   16
    #define   MSK32TG_SIZE_Y                                      0x0000FFFF

    #define     BA_TG_SIZE_X                                   0x0006
    #define     B16TG_SIZE_X                                   0x0006
    #define   LSb32TG_SIZE_X                                      16
    #define   LSb16TG_SIZE_X                                      0
    #define       bTG_SIZE_X                                   16
    #define   MSK32TG_SIZE_X                                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_HS                                       0x0008

    #define     BA_TG_HS_FE                                    0x0008
    #define     B16TG_HS_FE                                    0x0008
    #define   LSb32TG_HS_FE                                       0
    #define   LSb16TG_HS_FE                                       0
    #define       bTG_HS_FE                                    16
    #define   MSK32TG_HS_FE                                       0x0000FFFF

    #define     BA_TG_HS_BE                                    0x000A
    #define     B16TG_HS_BE                                    0x000A
    #define   LSb32TG_HS_BE                                       16
    #define   LSb16TG_HS_BE                                       0
    #define       bTG_HS_BE                                    16
    #define   MSK32TG_HS_BE                                       0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_HB                                       0x000C

    #define     BA_TG_HB_FE                                    0x000C
    #define     B16TG_HB_FE                                    0x000C
    #define   LSb32TG_HB_FE                                       0
    #define   LSb16TG_HB_FE                                       0
    #define       bTG_HB_FE                                    16
    #define   MSK32TG_HB_FE                                       0x0000FFFF

    #define     BA_TG_HB_BE                                    0x000E
    #define     B16TG_HB_BE                                    0x000E
    #define   LSb32TG_HB_BE                                       16
    #define   LSb16TG_HB_BE                                       0
    #define       bTG_HB_BE                                    16
    #define   MSK32TG_HB_BE                                       0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_HB_CR                                    0x0010

    #define     BA_TG_HB_CR_FE                                 0x0010
    #define     B16TG_HB_CR_FE                                 0x0010
    #define   LSb32TG_HB_CR_FE                                    0
    #define   LSb16TG_HB_CR_FE                                    0
    #define       bTG_HB_CR_FE                                 16
    #define   MSK32TG_HB_CR_FE                                    0x0000FFFF

    #define     BA_TG_HB_CR_BE                                 0x0012
    #define     B16TG_HB_CR_BE                                 0x0012
    #define   LSb32TG_HB_CR_BE                                    16
    #define   LSb16TG_HB_CR_BE                                    0
    #define       bTG_HB_CR_BE                                 16
    #define   MSK32TG_HB_CR_BE                                    0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_HB_CR2                                   0x0014

    #define     BA_TG_HB_CR2_FE                                0x0014
    #define     B16TG_HB_CR2_FE                                0x0014
    #define   LSb32TG_HB_CR2_FE                                   0
    #define   LSb16TG_HB_CR2_FE                                   0
    #define       bTG_HB_CR2_FE                                16
    #define   MSK32TG_HB_CR2_FE                                   0x0000FFFF

    #define     BA_TG_HB_CR2_BE                                0x0016
    #define     B16TG_HB_CR2_BE                                0x0016
    #define   LSb32TG_HB_CR2_BE                                   16
    #define   LSb16TG_HB_CR2_BE                                   0
    #define       bTG_HB_CR2_BE                                16
    #define   MSK32TG_HB_CR2_BE                                   0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_VS0                                      0x0018

    #define     BA_TG_VS0_FE                                   0x0018
    #define     B16TG_VS0_FE                                   0x0018
    #define   LSb32TG_VS0_FE                                      0
    #define   LSb16TG_VS0_FE                                      0
    #define       bTG_VS0_FE                                   16
    #define   MSK32TG_VS0_FE                                      0x0000FFFF

    #define     BA_TG_VS0_BE                                   0x001A
    #define     B16TG_VS0_BE                                   0x001A
    #define   LSb32TG_VS0_BE                                      16
    #define   LSb16TG_VS0_BE                                      0
    #define       bTG_VS0_BE                                   16
    #define   MSK32TG_VS0_BE                                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_VS1                                      0x001C

    #define     BA_TG_VS1_FE                                   0x001C
    #define     B16TG_VS1_FE                                   0x001C
    #define   LSb32TG_VS1_FE                                      0
    #define   LSb16TG_VS1_FE                                      0
    #define       bTG_VS1_FE                                   16
    #define   MSK32TG_VS1_FE                                      0x0000FFFF

    #define     BA_TG_VS1_BE                                   0x001E
    #define     B16TG_VS1_BE                                   0x001E
    #define   LSb32TG_VS1_BE                                      16
    #define   LSb16TG_VS1_BE                                      0
    #define       bTG_VS1_BE                                   16
    #define   MSK32TG_VS1_BE                                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_VB0                                      0x0020

    #define     BA_TG_VB0_FE                                   0x0020
    #define     B16TG_VB0_FE                                   0x0020
    #define   LSb32TG_VB0_FE                                      0
    #define   LSb16TG_VB0_FE                                      0
    #define       bTG_VB0_FE                                   16
    #define   MSK32TG_VB0_FE                                      0x0000FFFF

    #define     BA_TG_VB0_BE                                   0x0022
    #define     B16TG_VB0_BE                                   0x0022
    #define   LSb32TG_VB0_BE                                      16
    #define   LSb16TG_VB0_BE                                      0
    #define       bTG_VB0_BE                                   16
    #define   MSK32TG_VB0_BE                                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_VB0_CR                                   0x0024

    #define     BA_TG_VB0_CR_FE                                0x0024
    #define     B16TG_VB0_CR_FE                                0x0024
    #define   LSb32TG_VB0_CR_FE                                   0
    #define   LSb16TG_VB0_CR_FE                                   0
    #define       bTG_VB0_CR_FE                                16
    #define   MSK32TG_VB0_CR_FE                                   0x0000FFFF

    #define     BA_TG_VB0_CR_BE                                0x0026
    #define     B16TG_VB0_CR_BE                                0x0026
    #define   LSb32TG_VB0_CR_BE                                   16
    #define   LSb16TG_VB0_CR_BE                                   0
    #define       bTG_VB0_CR_BE                                16
    #define   MSK32TG_VB0_CR_BE                                   0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_VB0_CR2                                  0x0028

    #define     BA_TG_VB0_CR2_FE                               0x0028
    #define     B16TG_VB0_CR2_FE                               0x0028
    #define   LSb32TG_VB0_CR2_FE                                  0
    #define   LSb16TG_VB0_CR2_FE                                  0
    #define       bTG_VB0_CR2_FE                               16
    #define   MSK32TG_VB0_CR2_FE                                  0x0000FFFF

    #define     BA_TG_VB0_CR2_BE                               0x002A
    #define     B16TG_VB0_CR2_BE                               0x002A
    #define   LSb32TG_VB0_CR2_BE                                  16
    #define   LSb16TG_VB0_CR2_BE                                  0
    #define       bTG_VB0_CR2_BE                               16
    #define   MSK32TG_VB0_CR2_BE                                  0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_VB1                                      0x002C

    #define     BA_TG_VB1_FE                                   0x002C
    #define     B16TG_VB1_FE                                   0x002C
    #define   LSb32TG_VB1_FE                                      0
    #define   LSb16TG_VB1_FE                                      0
    #define       bTG_VB1_FE                                   16
    #define   MSK32TG_VB1_FE                                      0x0000FFFF

    #define     BA_TG_VB1_BE                                   0x002E
    #define     B16TG_VB1_BE                                   0x002E
    #define   LSb32TG_VB1_BE                                      16
    #define   LSb16TG_VB1_BE                                      0
    #define       bTG_VB1_BE                                   16
    #define   MSK32TG_VB1_BE                                      0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_SCAN                                     0x0030

    #define     BA_TG_SCAN_MODE                                0x0030
    #define     B16TG_SCAN_MODE                                0x0030
    #define   LSb32TG_SCAN_MODE                                   0
    #define   LSb16TG_SCAN_MODE                                   0
    #define       bTG_SCAN_MODE                                1
    #define   MSK32TG_SCAN_MODE                                   0x00000001
    #define        TG_SCAN_MODE_PROG                                        0x0
    #define        TG_SCAN_MODE_INTER                                       0x1
    ///////////////////////////////////////////////////////////
    #define     RA_TG_INTPOS                                   0x0034

    #define     BA_TG_INTPOS_FRAME                             0x0034
    #define     B16TG_INTPOS_FRAME                             0x0034
    #define   LSb32TG_INTPOS_FRAME                                0
    #define   LSb16TG_INTPOS_FRAME                                0
    #define       bTG_INTPOS_FRAME                             16
    #define   MSK32TG_INTPOS_FRAME                                0x0000FFFF

    #define     BA_TG_INTPOS_FIELD                             0x0036
    #define     B16TG_INTPOS_FIELD                             0x0036
    #define   LSb32TG_INTPOS_FIELD                                16
    #define   LSb16TG_INTPOS_FIELD                                0
    #define       bTG_INTPOS_FIELD                             16
    #define   MSK32TG_INTPOS_FIELD                                0xFFFF0000
    ///////////////////////////////////////////////////////////
    #define     RA_TG_MODE                                     0x0038

    #define     BA_TG_MODE_EN                                  0x0038
    #define     B16TG_MODE_EN                                  0x0038
    #define   LSb32TG_MODE_EN                                     0
    #define   LSb16TG_MODE_EN                                     0
    #define       bTG_MODE_EN                                  1
    #define   MSK32TG_MODE_EN                                     0x00000001
    #define        TG_MODE_EN_MASTER                                        0x0
    #define        TG_MODE_EN_SLAVE                                         0x1
    ///////////////////////////////////////////////////////////
    #define     RA_TG_HVREF                                    0x003C

    #define     BA_TG_HVREF_SEL                                0x003C
    #define     B16TG_HVREF_SEL                                0x003C
    #define   LSb32TG_HVREF_SEL                                   0
    #define   LSb16TG_HVREF_SEL                                   0
    #define       bTG_HVREF_SEL                                1
    #define   MSK32TG_HVREF_SEL                                   0x00000001
    #define        TG_HVREF_SEL_SYNC                                        0x0
    #define        TG_HVREF_SEL_BLANK                                       0x1

    #define     BA_TG_HVREF_POL                                0x003C
    #define     B16TG_HVREF_POL                                0x003C
    #define   LSb32TG_HVREF_POL                                   1
    #define   LSb16TG_HVREF_POL                                   1
    #define       bTG_HVREF_POL                                1
    #define   MSK32TG_HVREF_POL                                   0x00000002
    #define        TG_HVREF_POL_NEG_PULSE                                   0x0
    #define        TG_HVREF_POL_POS_PULSE                                   0x1
    ///////////////////////////////////////////////////////////

    typedef struct SIE_TG {
    ///////////////////////////////////////////////////////////
    #define   GET32TG_INIT_Y(r32)                              _BFGET_(r32,15, 0)
    #define   SET32TG_INIT_Y(r32,v)                            _BFSET_(r32,15, 0,v)
    #define   GET16TG_INIT_Y(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_INIT_Y(r16,v)                            _BFSET_(r16,15, 0,v)

    #define   GET32TG_INIT_X(r32)                              _BFGET_(r32,31,16)
    #define   SET32TG_INIT_X(r32,v)                            _BFSET_(r32,31,16,v)
    #define   GET16TG_INIT_X(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_INIT_X(r16,v)                            _BFSET_(r16,15, 0,v)

    #define     w32TG_INIT                                     {\
            UNSG32 uINIT_Y                                     : 16;\
            UNSG32 uINIT_X                                     : 16;\
          }
    union { UNSG32 u32TG_INIT;
            struct w32TG_INIT;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_SIZE_Y(r32)                              _BFGET_(r32,15, 0)
    #define   SET32TG_SIZE_Y(r32,v)                            _BFSET_(r32,15, 0,v)
    #define   GET16TG_SIZE_Y(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_SIZE_Y(r16,v)                            _BFSET_(r16,15, 0,v)

    #define   GET32TG_SIZE_X(r32)                              _BFGET_(r32,31,16)
    #define   SET32TG_SIZE_X(r32,v)                            _BFSET_(r32,31,16,v)
    #define   GET16TG_SIZE_X(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_SIZE_X(r16,v)                            _BFSET_(r16,15, 0,v)

    #define     w32TG_SIZE                                     {\
            UNSG32 uSIZE_Y                                     : 16;\
            UNSG32 uSIZE_X                                     : 16;\
          }
    union { UNSG32 u32TG_SIZE;
            struct w32TG_SIZE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_HS_FE(r32)                               _BFGET_(r32,15, 0)
    #define   SET32TG_HS_FE(r32,v)                             _BFSET_(r32,15, 0,v)
    #define   GET16TG_HS_FE(r16)                               _BFGET_(r16,15, 0)
    #define   SET16TG_HS_FE(r16,v)                             _BFSET_(r16,15, 0,v)

    #define   GET32TG_HS_BE(r32)                               _BFGET_(r32,31,16)
    #define   SET32TG_HS_BE(r32,v)                             _BFSET_(r32,31,16,v)
    #define   GET16TG_HS_BE(r16)                               _BFGET_(r16,15, 0)
    #define   SET16TG_HS_BE(r16,v)                             _BFSET_(r16,15, 0,v)

    #define     w32TG_HS                                       {\
            UNSG32 uHS_FE                                      : 16;\
            UNSG32 uHS_BE                                      : 16;\
          }
    union { UNSG32 u32TG_HS;
            struct w32TG_HS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_HB_FE(r32)                               _BFGET_(r32,15, 0)
    #define   SET32TG_HB_FE(r32,v)                             _BFSET_(r32,15, 0,v)
    #define   GET16TG_HB_FE(r16)                               _BFGET_(r16,15, 0)
    #define   SET16TG_HB_FE(r16,v)                             _BFSET_(r16,15, 0,v)

    #define   GET32TG_HB_BE(r32)                               _BFGET_(r32,31,16)
    #define   SET32TG_HB_BE(r32,v)                             _BFSET_(r32,31,16,v)
    #define   GET16TG_HB_BE(r16)                               _BFGET_(r16,15, 0)
    #define   SET16TG_HB_BE(r16,v)                             _BFSET_(r16,15, 0,v)

    #define     w32TG_HB                                       {\
            UNSG32 uHB_FE                                      : 16;\
            UNSG32 uHB_BE                                      : 16;\
          }
    union { UNSG32 u32TG_HB;
            struct w32TG_HB;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_HB_CR_FE(r32)                            _BFGET_(r32,15, 0)
    #define   SET32TG_HB_CR_FE(r32,v)                          _BFSET_(r32,15, 0,v)
    #define   GET16TG_HB_CR_FE(r16)                            _BFGET_(r16,15, 0)
    #define   SET16TG_HB_CR_FE(r16,v)                          _BFSET_(r16,15, 0,v)

    #define   GET32TG_HB_CR_BE(r32)                            _BFGET_(r32,31,16)
    #define   SET32TG_HB_CR_BE(r32,v)                          _BFSET_(r32,31,16,v)
    #define   GET16TG_HB_CR_BE(r16)                            _BFGET_(r16,15, 0)
    #define   SET16TG_HB_CR_BE(r16,v)                          _BFSET_(r16,15, 0,v)

    #define     w32TG_HB_CR                                    {\
            UNSG32 uHB_CR_FE                                   : 16;\
            UNSG32 uHB_CR_BE                                   : 16;\
          }
    union { UNSG32 u32TG_HB_CR;
            struct w32TG_HB_CR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_HB_CR2_FE(r32)                           _BFGET_(r32,15, 0)
    #define   SET32TG_HB_CR2_FE(r32,v)                         _BFSET_(r32,15, 0,v)
    #define   GET16TG_HB_CR2_FE(r16)                           _BFGET_(r16,15, 0)
    #define   SET16TG_HB_CR2_FE(r16,v)                         _BFSET_(r16,15, 0,v)

    #define   GET32TG_HB_CR2_BE(r32)                           _BFGET_(r32,31,16)
    #define   SET32TG_HB_CR2_BE(r32,v)                         _BFSET_(r32,31,16,v)
    #define   GET16TG_HB_CR2_BE(r16)                           _BFGET_(r16,15, 0)
    #define   SET16TG_HB_CR2_BE(r16,v)                         _BFSET_(r16,15, 0,v)

    #define     w32TG_HB_CR2                                   {\
            UNSG32 uHB_CR2_FE                                  : 16;\
            UNSG32 uHB_CR2_BE                                  : 16;\
          }
    union { UNSG32 u32TG_HB_CR2;
            struct w32TG_HB_CR2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_VS0_FE(r32)                              _BFGET_(r32,15, 0)
    #define   SET32TG_VS0_FE(r32,v)                            _BFSET_(r32,15, 0,v)
    #define   GET16TG_VS0_FE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VS0_FE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define   GET32TG_VS0_BE(r32)                              _BFGET_(r32,31,16)
    #define   SET32TG_VS0_BE(r32,v)                            _BFSET_(r32,31,16,v)
    #define   GET16TG_VS0_BE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VS0_BE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define     w32TG_VS0                                      {\
            UNSG32 uVS0_FE                                     : 16;\
            UNSG32 uVS0_BE                                     : 16;\
          }
    union { UNSG32 u32TG_VS0;
            struct w32TG_VS0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_VS1_FE(r32)                              _BFGET_(r32,15, 0)
    #define   SET32TG_VS1_FE(r32,v)                            _BFSET_(r32,15, 0,v)
    #define   GET16TG_VS1_FE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VS1_FE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define   GET32TG_VS1_BE(r32)                              _BFGET_(r32,31,16)
    #define   SET32TG_VS1_BE(r32,v)                            _BFSET_(r32,31,16,v)
    #define   GET16TG_VS1_BE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VS1_BE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define     w32TG_VS1                                      {\
            UNSG32 uVS1_FE                                     : 16;\
            UNSG32 uVS1_BE                                     : 16;\
          }
    union { UNSG32 u32TG_VS1;
            struct w32TG_VS1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_VB0_FE(r32)                              _BFGET_(r32,15, 0)
    #define   SET32TG_VB0_FE(r32,v)                            _BFSET_(r32,15, 0,v)
    #define   GET16TG_VB0_FE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VB0_FE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define   GET32TG_VB0_BE(r32)                              _BFGET_(r32,31,16)
    #define   SET32TG_VB0_BE(r32,v)                            _BFSET_(r32,31,16,v)
    #define   GET16TG_VB0_BE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VB0_BE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define     w32TG_VB0                                      {\
            UNSG32 uVB0_FE                                     : 16;\
            UNSG32 uVB0_BE                                     : 16;\
          }
    union { UNSG32 u32TG_VB0;
            struct w32TG_VB0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_VB0_CR_FE(r32)                           _BFGET_(r32,15, 0)
    #define   SET32TG_VB0_CR_FE(r32,v)                         _BFSET_(r32,15, 0,v)
    #define   GET16TG_VB0_CR_FE(r16)                           _BFGET_(r16,15, 0)
    #define   SET16TG_VB0_CR_FE(r16,v)                         _BFSET_(r16,15, 0,v)

    #define   GET32TG_VB0_CR_BE(r32)                           _BFGET_(r32,31,16)
    #define   SET32TG_VB0_CR_BE(r32,v)                         _BFSET_(r32,31,16,v)
    #define   GET16TG_VB0_CR_BE(r16)                           _BFGET_(r16,15, 0)
    #define   SET16TG_VB0_CR_BE(r16,v)                         _BFSET_(r16,15, 0,v)

    #define     w32TG_VB0_CR                                   {\
            UNSG32 uVB0_CR_FE                                  : 16;\
            UNSG32 uVB0_CR_BE                                  : 16;\
          }
    union { UNSG32 u32TG_VB0_CR;
            struct w32TG_VB0_CR;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_VB0_CR2_FE(r32)                          _BFGET_(r32,15, 0)
    #define   SET32TG_VB0_CR2_FE(r32,v)                        _BFSET_(r32,15, 0,v)
    #define   GET16TG_VB0_CR2_FE(r16)                          _BFGET_(r16,15, 0)
    #define   SET16TG_VB0_CR2_FE(r16,v)                        _BFSET_(r16,15, 0,v)

    #define   GET32TG_VB0_CR2_BE(r32)                          _BFGET_(r32,31,16)
    #define   SET32TG_VB0_CR2_BE(r32,v)                        _BFSET_(r32,31,16,v)
    #define   GET16TG_VB0_CR2_BE(r16)                          _BFGET_(r16,15, 0)
    #define   SET16TG_VB0_CR2_BE(r16,v)                        _BFSET_(r16,15, 0,v)

    #define     w32TG_VB0_CR2                                  {\
            UNSG32 uVB0_CR2_FE                                 : 16;\
            UNSG32 uVB0_CR2_BE                                 : 16;\
          }
    union { UNSG32 u32TG_VB0_CR2;
            struct w32TG_VB0_CR2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_VB1_FE(r32)                              _BFGET_(r32,15, 0)
    #define   SET32TG_VB1_FE(r32,v)                            _BFSET_(r32,15, 0,v)
    #define   GET16TG_VB1_FE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VB1_FE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define   GET32TG_VB1_BE(r32)                              _BFGET_(r32,31,16)
    #define   SET32TG_VB1_BE(r32,v)                            _BFSET_(r32,31,16,v)
    #define   GET16TG_VB1_BE(r16)                              _BFGET_(r16,15, 0)
    #define   SET16TG_VB1_BE(r16,v)                            _BFSET_(r16,15, 0,v)

    #define     w32TG_VB1                                      {\
            UNSG32 uVB1_FE                                     : 16;\
            UNSG32 uVB1_BE                                     : 16;\
          }
    union { UNSG32 u32TG_VB1;
            struct w32TG_VB1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_SCAN_MODE(r32)                           _BFGET_(r32, 0, 0)
    #define   SET32TG_SCAN_MODE(r32,v)                         _BFSET_(r32, 0, 0,v)
    #define   GET16TG_SCAN_MODE(r16)                           _BFGET_(r16, 0, 0)
    #define   SET16TG_SCAN_MODE(r16,v)                         _BFSET_(r16, 0, 0,v)

    #define     w32TG_SCAN                                     {\
            UNSG32 uSCAN_MODE                                  :  1;\
            UNSG32 RSVDx30_b1                                  : 31;\
          }
    union { UNSG32 u32TG_SCAN;
            struct w32TG_SCAN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_INTPOS_FRAME(r32)                        _BFGET_(r32,15, 0)
    #define   SET32TG_INTPOS_FRAME(r32,v)                      _BFSET_(r32,15, 0,v)
    #define   GET16TG_INTPOS_FRAME(r16)                        _BFGET_(r16,15, 0)
    #define   SET16TG_INTPOS_FRAME(r16,v)                      _BFSET_(r16,15, 0,v)

    #define   GET32TG_INTPOS_FIELD(r32)                        _BFGET_(r32,31,16)
    #define   SET32TG_INTPOS_FIELD(r32,v)                      _BFSET_(r32,31,16,v)
    #define   GET16TG_INTPOS_FIELD(r16)                        _BFGET_(r16,15, 0)
    #define   SET16TG_INTPOS_FIELD(r16,v)                      _BFSET_(r16,15, 0,v)

    #define     w32TG_INTPOS                                   {\
            UNSG32 uINTPOS_FRAME                               : 16;\
            UNSG32 uINTPOS_FIELD                               : 16;\
          }
    union { UNSG32 u32TG_INTPOS;
            struct w32TG_INTPOS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_MODE_EN(r32)                             _BFGET_(r32, 0, 0)
    #define   SET32TG_MODE_EN(r32,v)                           _BFSET_(r32, 0, 0,v)
    #define   GET16TG_MODE_EN(r16)                             _BFGET_(r16, 0, 0)
    #define   SET16TG_MODE_EN(r16,v)                           _BFSET_(r16, 0, 0,v)

    #define     w32TG_MODE                                     {\
            UNSG32 uMODE_EN                                    :  1;\
            UNSG32 RSVDx38_b1                                  : 31;\
          }
    union { UNSG32 u32TG_MODE;
            struct w32TG_MODE;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32TG_HVREF_SEL(r32)                           _BFGET_(r32, 0, 0)
    #define   SET32TG_HVREF_SEL(r32,v)                         _BFSET_(r32, 0, 0,v)
    #define   GET16TG_HVREF_SEL(r16)                           _BFGET_(r16, 0, 0)
    #define   SET16TG_HVREF_SEL(r16,v)                         _BFSET_(r16, 0, 0,v)

    #define   GET32TG_HVREF_POL(r32)                           _BFGET_(r32, 1, 1)
    #define   SET32TG_HVREF_POL(r32,v)                         _BFSET_(r32, 1, 1,v)
    #define   GET16TG_HVREF_POL(r16)                           _BFGET_(r16, 1, 1)
    #define   SET16TG_HVREF_POL(r16,v)                         _BFSET_(r16, 1, 1,v)

    #define     w32TG_HVREF                                    {\
            UNSG32 uHVREF_SEL                                  :  1;\
            UNSG32 uHVREF_POL                                  :  1;\
            UNSG32 RSVDx3C_b2                                  : 30;\
          }
    union { UNSG32 u32TG_HVREF;
            struct w32TG_HVREF;
          };
    ///////////////////////////////////////////////////////////
    } SIE_TG;

    typedef union  T32TG_INIT
          { UNSG32 u32;
            struct w32TG_INIT;
                 } T32TG_INIT;
    typedef union  T32TG_SIZE
          { UNSG32 u32;
            struct w32TG_SIZE;
                 } T32TG_SIZE;
    typedef union  T32TG_HS
          { UNSG32 u32;
            struct w32TG_HS;
                 } T32TG_HS;
    typedef union  T32TG_HB
          { UNSG32 u32;
            struct w32TG_HB;
                 } T32TG_HB;
    typedef union  T32TG_HB_CR
          { UNSG32 u32;
            struct w32TG_HB_CR;
                 } T32TG_HB_CR;
    typedef union  T32TG_HB_CR2
          { UNSG32 u32;
            struct w32TG_HB_CR2;
                 } T32TG_HB_CR2;
    typedef union  T32TG_VS0
          { UNSG32 u32;
            struct w32TG_VS0;
                 } T32TG_VS0;
    typedef union  T32TG_VS1
          { UNSG32 u32;
            struct w32TG_VS1;
                 } T32TG_VS1;
    typedef union  T32TG_VB0
          { UNSG32 u32;
            struct w32TG_VB0;
                 } T32TG_VB0;
    typedef union  T32TG_VB0_CR
          { UNSG32 u32;
            struct w32TG_VB0_CR;
                 } T32TG_VB0_CR;
    typedef union  T32TG_VB0_CR2
          { UNSG32 u32;
            struct w32TG_VB0_CR2;
                 } T32TG_VB0_CR2;
    typedef union  T32TG_VB1
          { UNSG32 u32;
            struct w32TG_VB1;
                 } T32TG_VB1;
    typedef union  T32TG_SCAN
          { UNSG32 u32;
            struct w32TG_SCAN;
                 } T32TG_SCAN;
    typedef union  T32TG_INTPOS
          { UNSG32 u32;
            struct w32TG_INTPOS;
                 } T32TG_INTPOS;
    typedef union  T32TG_MODE
          { UNSG32 u32;
            struct w32TG_MODE;
                 } T32TG_MODE;
    typedef union  T32TG_HVREF
          { UNSG32 u32;
            struct w32TG_HVREF;
                 } T32TG_HVREF;
    ///////////////////////////////////////////////////////////

    typedef union  TTG_INIT
          { UNSG32 u32[1];
            struct {
            struct w32TG_INIT;
                   };
                 } TTG_INIT;
    typedef union  TTG_SIZE
          { UNSG32 u32[1];
            struct {
            struct w32TG_SIZE;
                   };
                 } TTG_SIZE;
    typedef union  TTG_HS
          { UNSG32 u32[1];
            struct {
            struct w32TG_HS;
                   };
                 } TTG_HS;
    typedef union  TTG_HB
          { UNSG32 u32[1];
            struct {
            struct w32TG_HB;
                   };
                 } TTG_HB;
    typedef union  TTG_HB_CR
          { UNSG32 u32[1];
            struct {
            struct w32TG_HB_CR;
                   };
                 } TTG_HB_CR;
    typedef union  TTG_HB_CR2
          { UNSG32 u32[1];
            struct {
            struct w32TG_HB_CR2;
                   };
                 } TTG_HB_CR2;
    typedef union  TTG_VS0
          { UNSG32 u32[1];
            struct {
            struct w32TG_VS0;
                   };
                 } TTG_VS0;
    typedef union  TTG_VS1
          { UNSG32 u32[1];
            struct {
            struct w32TG_VS1;
                   };
                 } TTG_VS1;
    typedef union  TTG_VB0
          { UNSG32 u32[1];
            struct {
            struct w32TG_VB0;
                   };
                 } TTG_VB0;
    typedef union  TTG_VB0_CR
          { UNSG32 u32[1];
            struct {
            struct w32TG_VB0_CR;
                   };
                 } TTG_VB0_CR;
    typedef union  TTG_VB0_CR2
          { UNSG32 u32[1];
            struct {
            struct w32TG_VB0_CR2;
                   };
                 } TTG_VB0_CR2;
    typedef union  TTG_VB1
          { UNSG32 u32[1];
            struct {
            struct w32TG_VB1;
                   };
                 } TTG_VB1;
    typedef union  TTG_SCAN
          { UNSG32 u32[1];
            struct {
            struct w32TG_SCAN;
                   };
                 } TTG_SCAN;
    typedef union  TTG_INTPOS
          { UNSG32 u32[1];
            struct {
            struct w32TG_INTPOS;
                   };
                 } TTG_INTPOS;
    typedef union  TTG_MODE
          { UNSG32 u32[1];
            struct {
            struct w32TG_MODE;
                   };
                 } TTG_MODE;
    typedef union  TTG_HVREF
          { UNSG32 u32[1];
            struct {
            struct w32TG_HVREF;
                   };
                 } TTG_HVREF;

    ///////////////////////////////////////////////////////////
     SIGN32 TG_drvrd(SIE_TG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 TG_drvwr(SIE_TG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void TG_reset(SIE_TG *p);
     SIGN32 TG_cmp  (SIE_TG *p, SIE_TG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define TG_check(p,pie,pfx,hLOG) TG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define TG_print(p,    pfx,hLOG) TG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: TG
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE BITMAP40                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 SEL                  (P)
///               %unsigned 6  BIT_POS0                  0x0
///               %unsigned 6  BIT_POS1                  0x1
///               %unsigned 6  BIT_POS2                  0x2
///               %unsigned 6  BIT_POS3                  0x3
///               %unsigned 6  BIT_POS4                  0x4
///               %%        2          # Stuffing bits...
///     # 0x00004 SEL1
///               %unsigned 6  BIT_POS5                  0x5
///               %unsigned 6  BIT_POS6                  0x6
///               %unsigned 6  BIT_POS7                  0x7
///               %unsigned 6  BIT_POS8                  0x8
///               %unsigned 6  BIT_POS9                  0x9
///               %%        2          # Stuffing bits...
///     # 0x00008 SEL2
///               %unsigned 6  BIT_POS10                 0xA
///               %unsigned 6  BIT_POS11                 0xB
///               %unsigned 6  BIT_POS12                 0xC
///               %unsigned 6  BIT_POS13                 0xD
///               %unsigned 6  BIT_POS14                 0xE
///               %%        2          # Stuffing bits...
///     # 0x0000C SEL3
///               %unsigned 6  BIT_POS15                 0xF
///               %unsigned 6  BIT_POS16                 0x10
///               %unsigned 6  BIT_POS17                 0x11
///               %unsigned 6  BIT_POS18                 0x12
///               %unsigned 6  BIT_POS19                 0x13
///               %%        2          # Stuffing bits...
///     # 0x00010 SEL4
///               %unsigned 6  BIT_POS20                 0x14
///               %unsigned 6  BIT_POS21                 0x15
///               %unsigned 6  BIT_POS22                 0x16
///               %unsigned 6  BIT_POS23                 0x17
///               %unsigned 6  BIT_POS24                 0x18
///               %%        2          # Stuffing bits...
///     # 0x00014 SEL5
///               %unsigned 6  BIT_POS25                 0x19
///               %unsigned 6  BIT_POS26                 0x1A
///               %unsigned 6  BIT_POS27                 0x1B
///               %unsigned 6  BIT_POS28                 0x1C
///               %unsigned 6  BIT_POS29                 0x1D
///               %%        2          # Stuffing bits...
///     # 0x00018 SEL6
///               %unsigned 6  BIT_POS30                 0x1E
///               %unsigned 6  BIT_POS31                 0x1F
///               %unsigned 6  BIT_POS32                 0x20
///               %unsigned 6  BIT_POS33                 0x21
///               %unsigned 6  BIT_POS34                 0x22
///               %%        2          # Stuffing bits...
///     # 0x0001C SEL7
///               %unsigned 6  BIT_POS35                 0x23
///               %unsigned 6  BIT_POS36                 0x24
///               %unsigned 6  BIT_POS37                 0x25
///               %unsigned 6  BIT_POS38                 0x26
///               %unsigned 6  BIT_POS39                 0x27
///                                    ###
///                                    * Specifies mapping of new bit locations within 40 bit data from Read Client which need to be used to form pixels for Inverse Scan mode.
///                                    * Normal dHub data order:
///                                    * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in LSB
///                                    * Inverse Scan dHub data order:
///                                    * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in MSB
///                                    * Following different data orders can be generated to be presented to first UPS in the pipe.
///                                    ###
///               %%        2          # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      32B, bits:     240b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITMAP40
#define h_BITMAP40 (){}

    #define     RA_BITMAP40_SEL                                0x0000

    #define     BA_BITMAP40_SEL_BIT_POS0                       0x0000
    #define     B16BITMAP40_SEL_BIT_POS0                       0x0000
    #define   LSb32BITMAP40_SEL_BIT_POS0                          0
    #define   LSb16BITMAP40_SEL_BIT_POS0                          0
    #define       bBITMAP40_SEL_BIT_POS0                       6
    #define   MSK32BITMAP40_SEL_BIT_POS0                          0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS1                       0x0000
    #define     B16BITMAP40_SEL_BIT_POS1                       0x0000
    #define   LSb32BITMAP40_SEL_BIT_POS1                          6
    #define   LSb16BITMAP40_SEL_BIT_POS1                          6
    #define       bBITMAP40_SEL_BIT_POS1                       6
    #define   MSK32BITMAP40_SEL_BIT_POS1                          0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS2                       0x0001
    #define     B16BITMAP40_SEL_BIT_POS2                       0x0000
    #define   LSb32BITMAP40_SEL_BIT_POS2                          12
    #define   LSb16BITMAP40_SEL_BIT_POS2                          12
    #define       bBITMAP40_SEL_BIT_POS2                       6
    #define   MSK32BITMAP40_SEL_BIT_POS2                          0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS3                       0x0002
    #define     B16BITMAP40_SEL_BIT_POS3                       0x0002
    #define   LSb32BITMAP40_SEL_BIT_POS3                          18
    #define   LSb16BITMAP40_SEL_BIT_POS3                          2
    #define       bBITMAP40_SEL_BIT_POS3                       6
    #define   MSK32BITMAP40_SEL_BIT_POS3                          0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS4                       0x0003
    #define     B16BITMAP40_SEL_BIT_POS4                       0x0002
    #define   LSb32BITMAP40_SEL_BIT_POS4                          24
    #define   LSb16BITMAP40_SEL_BIT_POS4                          8
    #define       bBITMAP40_SEL_BIT_POS4                       6
    #define   MSK32BITMAP40_SEL_BIT_POS4                          0x3F000000

    #define     RA_BITMAP40_SEL1                               0x0004

    #define     BA_BITMAP40_SEL_BIT_POS5                       0x0004
    #define     B16BITMAP40_SEL_BIT_POS5                       0x0004
    #define   LSb32BITMAP40_SEL_BIT_POS5                          0
    #define   LSb16BITMAP40_SEL_BIT_POS5                          0
    #define       bBITMAP40_SEL_BIT_POS5                       6
    #define   MSK32BITMAP40_SEL_BIT_POS5                          0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS6                       0x0004
    #define     B16BITMAP40_SEL_BIT_POS6                       0x0004
    #define   LSb32BITMAP40_SEL_BIT_POS6                          6
    #define   LSb16BITMAP40_SEL_BIT_POS6                          6
    #define       bBITMAP40_SEL_BIT_POS6                       6
    #define   MSK32BITMAP40_SEL_BIT_POS6                          0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS7                       0x0005
    #define     B16BITMAP40_SEL_BIT_POS7                       0x0004
    #define   LSb32BITMAP40_SEL_BIT_POS7                          12
    #define   LSb16BITMAP40_SEL_BIT_POS7                          12
    #define       bBITMAP40_SEL_BIT_POS7                       6
    #define   MSK32BITMAP40_SEL_BIT_POS7                          0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS8                       0x0006
    #define     B16BITMAP40_SEL_BIT_POS8                       0x0006
    #define   LSb32BITMAP40_SEL_BIT_POS8                          18
    #define   LSb16BITMAP40_SEL_BIT_POS8                          2
    #define       bBITMAP40_SEL_BIT_POS8                       6
    #define   MSK32BITMAP40_SEL_BIT_POS8                          0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS9                       0x0007
    #define     B16BITMAP40_SEL_BIT_POS9                       0x0006
    #define   LSb32BITMAP40_SEL_BIT_POS9                          24
    #define   LSb16BITMAP40_SEL_BIT_POS9                          8
    #define       bBITMAP40_SEL_BIT_POS9                       6
    #define   MSK32BITMAP40_SEL_BIT_POS9                          0x3F000000

    #define     RA_BITMAP40_SEL2                               0x0008

    #define     BA_BITMAP40_SEL_BIT_POS10                      0x0008
    #define     B16BITMAP40_SEL_BIT_POS10                      0x0008
    #define   LSb32BITMAP40_SEL_BIT_POS10                         0
    #define   LSb16BITMAP40_SEL_BIT_POS10                         0
    #define       bBITMAP40_SEL_BIT_POS10                      6
    #define   MSK32BITMAP40_SEL_BIT_POS10                         0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS11                      0x0008
    #define     B16BITMAP40_SEL_BIT_POS11                      0x0008
    #define   LSb32BITMAP40_SEL_BIT_POS11                         6
    #define   LSb16BITMAP40_SEL_BIT_POS11                         6
    #define       bBITMAP40_SEL_BIT_POS11                      6
    #define   MSK32BITMAP40_SEL_BIT_POS11                         0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS12                      0x0009
    #define     B16BITMAP40_SEL_BIT_POS12                      0x0008
    #define   LSb32BITMAP40_SEL_BIT_POS12                         12
    #define   LSb16BITMAP40_SEL_BIT_POS12                         12
    #define       bBITMAP40_SEL_BIT_POS12                      6
    #define   MSK32BITMAP40_SEL_BIT_POS12                         0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS13                      0x000A
    #define     B16BITMAP40_SEL_BIT_POS13                      0x000A
    #define   LSb32BITMAP40_SEL_BIT_POS13                         18
    #define   LSb16BITMAP40_SEL_BIT_POS13                         2
    #define       bBITMAP40_SEL_BIT_POS13                      6
    #define   MSK32BITMAP40_SEL_BIT_POS13                         0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS14                      0x000B
    #define     B16BITMAP40_SEL_BIT_POS14                      0x000A
    #define   LSb32BITMAP40_SEL_BIT_POS14                         24
    #define   LSb16BITMAP40_SEL_BIT_POS14                         8
    #define       bBITMAP40_SEL_BIT_POS14                      6
    #define   MSK32BITMAP40_SEL_BIT_POS14                         0x3F000000

    #define     RA_BITMAP40_SEL3                               0x000C

    #define     BA_BITMAP40_SEL_BIT_POS15                      0x000C
    #define     B16BITMAP40_SEL_BIT_POS15                      0x000C
    #define   LSb32BITMAP40_SEL_BIT_POS15                         0
    #define   LSb16BITMAP40_SEL_BIT_POS15                         0
    #define       bBITMAP40_SEL_BIT_POS15                      6
    #define   MSK32BITMAP40_SEL_BIT_POS15                         0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS16                      0x000C
    #define     B16BITMAP40_SEL_BIT_POS16                      0x000C
    #define   LSb32BITMAP40_SEL_BIT_POS16                         6
    #define   LSb16BITMAP40_SEL_BIT_POS16                         6
    #define       bBITMAP40_SEL_BIT_POS16                      6
    #define   MSK32BITMAP40_SEL_BIT_POS16                         0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS17                      0x000D
    #define     B16BITMAP40_SEL_BIT_POS17                      0x000C
    #define   LSb32BITMAP40_SEL_BIT_POS17                         12
    #define   LSb16BITMAP40_SEL_BIT_POS17                         12
    #define       bBITMAP40_SEL_BIT_POS17                      6
    #define   MSK32BITMAP40_SEL_BIT_POS17                         0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS18                      0x000E
    #define     B16BITMAP40_SEL_BIT_POS18                      0x000E
    #define   LSb32BITMAP40_SEL_BIT_POS18                         18
    #define   LSb16BITMAP40_SEL_BIT_POS18                         2
    #define       bBITMAP40_SEL_BIT_POS18                      6
    #define   MSK32BITMAP40_SEL_BIT_POS18                         0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS19                      0x000F
    #define     B16BITMAP40_SEL_BIT_POS19                      0x000E
    #define   LSb32BITMAP40_SEL_BIT_POS19                         24
    #define   LSb16BITMAP40_SEL_BIT_POS19                         8
    #define       bBITMAP40_SEL_BIT_POS19                      6
    #define   MSK32BITMAP40_SEL_BIT_POS19                         0x3F000000

    #define     RA_BITMAP40_SEL4                               0x0010

    #define     BA_BITMAP40_SEL_BIT_POS20                      0x0010
    #define     B16BITMAP40_SEL_BIT_POS20                      0x0010
    #define   LSb32BITMAP40_SEL_BIT_POS20                         0
    #define   LSb16BITMAP40_SEL_BIT_POS20                         0
    #define       bBITMAP40_SEL_BIT_POS20                      6
    #define   MSK32BITMAP40_SEL_BIT_POS20                         0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS21                      0x0010
    #define     B16BITMAP40_SEL_BIT_POS21                      0x0010
    #define   LSb32BITMAP40_SEL_BIT_POS21                         6
    #define   LSb16BITMAP40_SEL_BIT_POS21                         6
    #define       bBITMAP40_SEL_BIT_POS21                      6
    #define   MSK32BITMAP40_SEL_BIT_POS21                         0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS22                      0x0011
    #define     B16BITMAP40_SEL_BIT_POS22                      0x0010
    #define   LSb32BITMAP40_SEL_BIT_POS22                         12
    #define   LSb16BITMAP40_SEL_BIT_POS22                         12
    #define       bBITMAP40_SEL_BIT_POS22                      6
    #define   MSK32BITMAP40_SEL_BIT_POS22                         0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS23                      0x0012
    #define     B16BITMAP40_SEL_BIT_POS23                      0x0012
    #define   LSb32BITMAP40_SEL_BIT_POS23                         18
    #define   LSb16BITMAP40_SEL_BIT_POS23                         2
    #define       bBITMAP40_SEL_BIT_POS23                      6
    #define   MSK32BITMAP40_SEL_BIT_POS23                         0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS24                      0x0013
    #define     B16BITMAP40_SEL_BIT_POS24                      0x0012
    #define   LSb32BITMAP40_SEL_BIT_POS24                         24
    #define   LSb16BITMAP40_SEL_BIT_POS24                         8
    #define       bBITMAP40_SEL_BIT_POS24                      6
    #define   MSK32BITMAP40_SEL_BIT_POS24                         0x3F000000

    #define     RA_BITMAP40_SEL5                               0x0014

    #define     BA_BITMAP40_SEL_BIT_POS25                      0x0014
    #define     B16BITMAP40_SEL_BIT_POS25                      0x0014
    #define   LSb32BITMAP40_SEL_BIT_POS25                         0
    #define   LSb16BITMAP40_SEL_BIT_POS25                         0
    #define       bBITMAP40_SEL_BIT_POS25                      6
    #define   MSK32BITMAP40_SEL_BIT_POS25                         0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS26                      0x0014
    #define     B16BITMAP40_SEL_BIT_POS26                      0x0014
    #define   LSb32BITMAP40_SEL_BIT_POS26                         6
    #define   LSb16BITMAP40_SEL_BIT_POS26                         6
    #define       bBITMAP40_SEL_BIT_POS26                      6
    #define   MSK32BITMAP40_SEL_BIT_POS26                         0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS27                      0x0015
    #define     B16BITMAP40_SEL_BIT_POS27                      0x0014
    #define   LSb32BITMAP40_SEL_BIT_POS27                         12
    #define   LSb16BITMAP40_SEL_BIT_POS27                         12
    #define       bBITMAP40_SEL_BIT_POS27                      6
    #define   MSK32BITMAP40_SEL_BIT_POS27                         0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS28                      0x0016
    #define     B16BITMAP40_SEL_BIT_POS28                      0x0016
    #define   LSb32BITMAP40_SEL_BIT_POS28                         18
    #define   LSb16BITMAP40_SEL_BIT_POS28                         2
    #define       bBITMAP40_SEL_BIT_POS28                      6
    #define   MSK32BITMAP40_SEL_BIT_POS28                         0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS29                      0x0017
    #define     B16BITMAP40_SEL_BIT_POS29                      0x0016
    #define   LSb32BITMAP40_SEL_BIT_POS29                         24
    #define   LSb16BITMAP40_SEL_BIT_POS29                         8
    #define       bBITMAP40_SEL_BIT_POS29                      6
    #define   MSK32BITMAP40_SEL_BIT_POS29                         0x3F000000

    #define     RA_BITMAP40_SEL6                               0x0018

    #define     BA_BITMAP40_SEL_BIT_POS30                      0x0018
    #define     B16BITMAP40_SEL_BIT_POS30                      0x0018
    #define   LSb32BITMAP40_SEL_BIT_POS30                         0
    #define   LSb16BITMAP40_SEL_BIT_POS30                         0
    #define       bBITMAP40_SEL_BIT_POS30                      6
    #define   MSK32BITMAP40_SEL_BIT_POS30                         0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS31                      0x0018
    #define     B16BITMAP40_SEL_BIT_POS31                      0x0018
    #define   LSb32BITMAP40_SEL_BIT_POS31                         6
    #define   LSb16BITMAP40_SEL_BIT_POS31                         6
    #define       bBITMAP40_SEL_BIT_POS31                      6
    #define   MSK32BITMAP40_SEL_BIT_POS31                         0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS32                      0x0019
    #define     B16BITMAP40_SEL_BIT_POS32                      0x0018
    #define   LSb32BITMAP40_SEL_BIT_POS32                         12
    #define   LSb16BITMAP40_SEL_BIT_POS32                         12
    #define       bBITMAP40_SEL_BIT_POS32                      6
    #define   MSK32BITMAP40_SEL_BIT_POS32                         0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS33                      0x001A
    #define     B16BITMAP40_SEL_BIT_POS33                      0x001A
    #define   LSb32BITMAP40_SEL_BIT_POS33                         18
    #define   LSb16BITMAP40_SEL_BIT_POS33                         2
    #define       bBITMAP40_SEL_BIT_POS33                      6
    #define   MSK32BITMAP40_SEL_BIT_POS33                         0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS34                      0x001B
    #define     B16BITMAP40_SEL_BIT_POS34                      0x001A
    #define   LSb32BITMAP40_SEL_BIT_POS34                         24
    #define   LSb16BITMAP40_SEL_BIT_POS34                         8
    #define       bBITMAP40_SEL_BIT_POS34                      6
    #define   MSK32BITMAP40_SEL_BIT_POS34                         0x3F000000

    #define     RA_BITMAP40_SEL7                               0x001C

    #define     BA_BITMAP40_SEL_BIT_POS35                      0x001C
    #define     B16BITMAP40_SEL_BIT_POS35                      0x001C
    #define   LSb32BITMAP40_SEL_BIT_POS35                         0
    #define   LSb16BITMAP40_SEL_BIT_POS35                         0
    #define       bBITMAP40_SEL_BIT_POS35                      6
    #define   MSK32BITMAP40_SEL_BIT_POS35                         0x0000003F

    #define     BA_BITMAP40_SEL_BIT_POS36                      0x001C
    #define     B16BITMAP40_SEL_BIT_POS36                      0x001C
    #define   LSb32BITMAP40_SEL_BIT_POS36                         6
    #define   LSb16BITMAP40_SEL_BIT_POS36                         6
    #define       bBITMAP40_SEL_BIT_POS36                      6
    #define   MSK32BITMAP40_SEL_BIT_POS36                         0x00000FC0

    #define     BA_BITMAP40_SEL_BIT_POS37                      0x001D
    #define     B16BITMAP40_SEL_BIT_POS37                      0x001C
    #define   LSb32BITMAP40_SEL_BIT_POS37                         12
    #define   LSb16BITMAP40_SEL_BIT_POS37                         12
    #define       bBITMAP40_SEL_BIT_POS37                      6
    #define   MSK32BITMAP40_SEL_BIT_POS37                         0x0003F000

    #define     BA_BITMAP40_SEL_BIT_POS38                      0x001E
    #define     B16BITMAP40_SEL_BIT_POS38                      0x001E
    #define   LSb32BITMAP40_SEL_BIT_POS38                         18
    #define   LSb16BITMAP40_SEL_BIT_POS38                         2
    #define       bBITMAP40_SEL_BIT_POS38                      6
    #define   MSK32BITMAP40_SEL_BIT_POS38                         0x00FC0000

    #define     BA_BITMAP40_SEL_BIT_POS39                      0x001F
    #define     B16BITMAP40_SEL_BIT_POS39                      0x001E
    #define   LSb32BITMAP40_SEL_BIT_POS39                         24
    #define   LSb16BITMAP40_SEL_BIT_POS39                         8
    #define       bBITMAP40_SEL_BIT_POS39                      6
    #define   MSK32BITMAP40_SEL_BIT_POS39                         0x3F000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITMAP40 {
    ///////////////////////////////////////////////////////////
    #define   GET32BITMAP40_SEL_BIT_POS0(r32)                  _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS0(r32,v)                _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS0(r16)                  _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS0(r16,v)                _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS1(r32)                  _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS1(r32,v)                _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS1(r16)                  _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS1(r16,v)                _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS2(r32)                  _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS2(r32,v)                _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS3(r32)                  _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS3(r32,v)                _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS3(r16)                  _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS3(r16,v)                _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS4(r32)                  _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS4(r32,v)                _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS4(r16)                  _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS4(r16,v)                _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL                                {\
            UNSG32 uSEL_BIT_POS0                               :  6;\
            UNSG32 uSEL_BIT_POS1                               :  6;\
            UNSG32 uSEL_BIT_POS2                               :  6;\
            UNSG32 uSEL_BIT_POS3                               :  6;\
            UNSG32 uSEL_BIT_POS4                               :  6;\
            UNSG32 RSVDx0_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL;
            struct w32BITMAP40_SEL;
          };
    #define   GET32BITMAP40_SEL_BIT_POS5(r32)                  _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS5(r32,v)                _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS5(r16)                  _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS5(r16,v)                _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS6(r32)                  _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS6(r32,v)                _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS6(r16)                  _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS6(r16,v)                _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS7(r32)                  _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS7(r32,v)                _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS8(r32)                  _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS8(r32,v)                _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS8(r16)                  _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS8(r16,v)                _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS9(r32)                  _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS9(r32,v)                _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS9(r16)                  _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS9(r16,v)                _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL1                               {\
            UNSG32 uSEL_BIT_POS5                               :  6;\
            UNSG32 uSEL_BIT_POS6                               :  6;\
            UNSG32 uSEL_BIT_POS7                               :  6;\
            UNSG32 uSEL_BIT_POS8                               :  6;\
            UNSG32 uSEL_BIT_POS9                               :  6;\
            UNSG32 RSVDx4_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL1;
            struct w32BITMAP40_SEL1;
          };
    #define   GET32BITMAP40_SEL_BIT_POS10(r32)                 _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS10(r32,v)               _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS10(r16)                 _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS10(r16,v)               _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS11(r32)                 _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS11(r32,v)               _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS11(r16)                 _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS11(r16,v)               _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS12(r32)                 _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS12(r32,v)               _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS13(r32)                 _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS13(r32,v)               _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS13(r16)                 _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS13(r16,v)               _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS14(r32)                 _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS14(r32,v)               _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS14(r16)                 _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS14(r16,v)               _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL2                               {\
            UNSG32 uSEL_BIT_POS10                              :  6;\
            UNSG32 uSEL_BIT_POS11                              :  6;\
            UNSG32 uSEL_BIT_POS12                              :  6;\
            UNSG32 uSEL_BIT_POS13                              :  6;\
            UNSG32 uSEL_BIT_POS14                              :  6;\
            UNSG32 RSVDx8_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL2;
            struct w32BITMAP40_SEL2;
          };
    #define   GET32BITMAP40_SEL_BIT_POS15(r32)                 _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS15(r32,v)               _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS15(r16)                 _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS15(r16,v)               _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS16(r32)                 _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS16(r32,v)               _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS16(r16)                 _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS16(r16,v)               _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS17(r32)                 _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS17(r32,v)               _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS18(r32)                 _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS18(r32,v)               _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS18(r16)                 _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS18(r16,v)               _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS19(r32)                 _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS19(r32,v)               _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS19(r16)                 _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS19(r16,v)               _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL3                               {\
            UNSG32 uSEL_BIT_POS15                              :  6;\
            UNSG32 uSEL_BIT_POS16                              :  6;\
            UNSG32 uSEL_BIT_POS17                              :  6;\
            UNSG32 uSEL_BIT_POS18                              :  6;\
            UNSG32 uSEL_BIT_POS19                              :  6;\
            UNSG32 RSVDxC_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL3;
            struct w32BITMAP40_SEL3;
          };
    #define   GET32BITMAP40_SEL_BIT_POS20(r32)                 _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS20(r32,v)               _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS20(r16)                 _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS20(r16,v)               _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS21(r32)                 _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS21(r32,v)               _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS21(r16)                 _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS21(r16,v)               _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS22(r32)                 _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS22(r32,v)               _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS23(r32)                 _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS23(r32,v)               _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS23(r16)                 _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS23(r16,v)               _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS24(r32)                 _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS24(r32,v)               _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS24(r16)                 _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS24(r16,v)               _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL4                               {\
            UNSG32 uSEL_BIT_POS20                              :  6;\
            UNSG32 uSEL_BIT_POS21                              :  6;\
            UNSG32 uSEL_BIT_POS22                              :  6;\
            UNSG32 uSEL_BIT_POS23                              :  6;\
            UNSG32 uSEL_BIT_POS24                              :  6;\
            UNSG32 RSVDx10_b30                                 :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL4;
            struct w32BITMAP40_SEL4;
          };
    #define   GET32BITMAP40_SEL_BIT_POS25(r32)                 _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS25(r32,v)               _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS25(r16)                 _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS25(r16,v)               _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS26(r32)                 _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS26(r32,v)               _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS26(r16)                 _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS26(r16,v)               _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS27(r32)                 _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS27(r32,v)               _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS28(r32)                 _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS28(r32,v)               _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS28(r16)                 _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS28(r16,v)               _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS29(r32)                 _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS29(r32,v)               _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS29(r16)                 _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS29(r16,v)               _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL5                               {\
            UNSG32 uSEL_BIT_POS25                              :  6;\
            UNSG32 uSEL_BIT_POS26                              :  6;\
            UNSG32 uSEL_BIT_POS27                              :  6;\
            UNSG32 uSEL_BIT_POS28                              :  6;\
            UNSG32 uSEL_BIT_POS29                              :  6;\
            UNSG32 RSVDx14_b30                                 :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL5;
            struct w32BITMAP40_SEL5;
          };
    #define   GET32BITMAP40_SEL_BIT_POS30(r32)                 _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS30(r32,v)               _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS30(r16)                 _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS30(r16,v)               _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS31(r32)                 _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS31(r32,v)               _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS31(r16)                 _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS31(r16,v)               _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS32(r32)                 _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS32(r32,v)               _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS33(r32)                 _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS33(r32,v)               _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS33(r16)                 _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS33(r16,v)               _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS34(r32)                 _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS34(r32,v)               _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS34(r16)                 _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS34(r16,v)               _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL6                               {\
            UNSG32 uSEL_BIT_POS30                              :  6;\
            UNSG32 uSEL_BIT_POS31                              :  6;\
            UNSG32 uSEL_BIT_POS32                              :  6;\
            UNSG32 uSEL_BIT_POS33                              :  6;\
            UNSG32 uSEL_BIT_POS34                              :  6;\
            UNSG32 RSVDx18_b30                                 :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL6;
            struct w32BITMAP40_SEL6;
          };
    #define   GET32BITMAP40_SEL_BIT_POS35(r32)                 _BFGET_(r32, 5, 0)
    #define   SET32BITMAP40_SEL_BIT_POS35(r32,v)               _BFSET_(r32, 5, 0,v)
    #define   GET16BITMAP40_SEL_BIT_POS35(r16)                 _BFGET_(r16, 5, 0)
    #define   SET16BITMAP40_SEL_BIT_POS35(r16,v)               _BFSET_(r16, 5, 0,v)

    #define   GET32BITMAP40_SEL_BIT_POS36(r32)                 _BFGET_(r32,11, 6)
    #define   SET32BITMAP40_SEL_BIT_POS36(r32,v)               _BFSET_(r32,11, 6,v)
    #define   GET16BITMAP40_SEL_BIT_POS36(r16)                 _BFGET_(r16,11, 6)
    #define   SET16BITMAP40_SEL_BIT_POS36(r16,v)               _BFSET_(r16,11, 6,v)

    #define   GET32BITMAP40_SEL_BIT_POS37(r32)                 _BFGET_(r32,17,12)
    #define   SET32BITMAP40_SEL_BIT_POS37(r32,v)               _BFSET_(r32,17,12,v)

    #define   GET32BITMAP40_SEL_BIT_POS38(r32)                 _BFGET_(r32,23,18)
    #define   SET32BITMAP40_SEL_BIT_POS38(r32,v)               _BFSET_(r32,23,18,v)
    #define   GET16BITMAP40_SEL_BIT_POS38(r16)                 _BFGET_(r16, 7, 2)
    #define   SET16BITMAP40_SEL_BIT_POS38(r16,v)               _BFSET_(r16, 7, 2,v)

    #define   GET32BITMAP40_SEL_BIT_POS39(r32)                 _BFGET_(r32,29,24)
    #define   SET32BITMAP40_SEL_BIT_POS39(r32,v)               _BFSET_(r32,29,24,v)
    #define   GET16BITMAP40_SEL_BIT_POS39(r16)                 _BFGET_(r16,13, 8)
    #define   SET16BITMAP40_SEL_BIT_POS39(r16,v)               _BFSET_(r16,13, 8,v)

    #define     w32BITMAP40_SEL7                               {\
            UNSG32 uSEL_BIT_POS35                              :  6;\
            UNSG32 uSEL_BIT_POS36                              :  6;\
            UNSG32 uSEL_BIT_POS37                              :  6;\
            UNSG32 uSEL_BIT_POS38                              :  6;\
            UNSG32 uSEL_BIT_POS39                              :  6;\
            UNSG32 RSVDx1C_b30                                 :  2;\
          }
    union { UNSG32 u32BITMAP40_SEL7;
            struct w32BITMAP40_SEL7;
          };
    ///////////////////////////////////////////////////////////
    } SIE_BITMAP40;

    typedef union  T32BITMAP40_SEL
          { UNSG32 u32;
            struct w32BITMAP40_SEL;
                 } T32BITMAP40_SEL;
    typedef union  T32BITMAP40_SEL1
          { UNSG32 u32;
            struct w32BITMAP40_SEL1;
                 } T32BITMAP40_SEL1;
    typedef union  T32BITMAP40_SEL2
          { UNSG32 u32;
            struct w32BITMAP40_SEL2;
                 } T32BITMAP40_SEL2;
    typedef union  T32BITMAP40_SEL3
          { UNSG32 u32;
            struct w32BITMAP40_SEL3;
                 } T32BITMAP40_SEL3;
    typedef union  T32BITMAP40_SEL4
          { UNSG32 u32;
            struct w32BITMAP40_SEL4;
                 } T32BITMAP40_SEL4;
    typedef union  T32BITMAP40_SEL5
          { UNSG32 u32;
            struct w32BITMAP40_SEL5;
                 } T32BITMAP40_SEL5;
    typedef union  T32BITMAP40_SEL6
          { UNSG32 u32;
            struct w32BITMAP40_SEL6;
                 } T32BITMAP40_SEL6;
    typedef union  T32BITMAP40_SEL7
          { UNSG32 u32;
            struct w32BITMAP40_SEL7;
                 } T32BITMAP40_SEL7;
    ///////////////////////////////////////////////////////////

    typedef union  TBITMAP40_SEL
          { UNSG32 u32[8];
            struct {
            struct w32BITMAP40_SEL;
            struct w32BITMAP40_SEL1;
            struct w32BITMAP40_SEL2;
            struct w32BITMAP40_SEL3;
            struct w32BITMAP40_SEL4;
            struct w32BITMAP40_SEL5;
            struct w32BITMAP40_SEL6;
            struct w32BITMAP40_SEL7;
                   };
                 } TBITMAP40_SEL;

    ///////////////////////////////////////////////////////////
     SIGN32 BITMAP40_drvrd(SIE_BITMAP40 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITMAP40_drvwr(SIE_BITMAP40 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITMAP40_reset(SIE_BITMAP40 *p);
     SIGN32 BITMAP40_cmp  (SIE_BITMAP40 *p, SIE_BITMAP40 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITMAP40_check(p,pie,pfx,hLOG) BITMAP40_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITMAP40_print(p,    pfx,hLOG) BITMAP40_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITMAP40
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE BITMAP20                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 SEL                  (P)
///               %unsigned 5  BIT_POS0                  0x0
///               %unsigned 5  BIT_POS1                  0x1
///               %unsigned 5  BIT_POS2                  0x2
///               %unsigned 5  BIT_POS3                  0x3
///               %unsigned 5  BIT_POS4                  0x4
///               %unsigned 5  BIT_POS5                  0x5
///               %%        2          # Stuffing bits...
///     # 0x00004 SEL1
///               %unsigned 5  BIT_POS6                  0x6
///               %unsigned 5  BIT_POS7                  0x7
///               %unsigned 5  BIT_POS8                  0x8
///               %unsigned 5  BIT_POS9                  0x9
///               %unsigned 5  BIT_POS10                 0xA
///               %unsigned 5  BIT_POS11                 0xB
///               %%        2          # Stuffing bits...
///     # 0x00008 SEL2
///               %unsigned 5  BIT_POS12                 0xC
///               %unsigned 5  BIT_POS13                 0xD
///               %unsigned 5  BIT_POS14                 0xE
///               %unsigned 5  BIT_POS15                 0xF
///               %unsigned 5  BIT_POS16                 0x10
///               %unsigned 5  BIT_POS17                 0x11
///               %%        2          # Stuffing bits...
///     # 0x0000C SEL3
///               %unsigned 5  BIT_POS18                 0x12
///               %unsigned 5  BIT_POS19                 0x13
///                                    ###
///                                    * Specifies mapping of new bit locations within 20 bit data from Read Client which need to be used to form pixels for Inverse Scan mode.
///                                    * Normal dHub data order:
///                                    * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in LSB
///                                    * Inverse Scan dHub data order:
///                                    * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in MSB
///                                    * Following different data orders can be generated to be presented to first UPS in the pipe.
///                                    ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:     100b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITMAP20
#define h_BITMAP20 (){}

    #define     RA_BITMAP20_SEL                                0x0000

    #define     BA_BITMAP20_SEL_BIT_POS0                       0x0000
    #define     B16BITMAP20_SEL_BIT_POS0                       0x0000
    #define   LSb32BITMAP20_SEL_BIT_POS0                          0
    #define   LSb16BITMAP20_SEL_BIT_POS0                          0
    #define       bBITMAP20_SEL_BIT_POS0                       5
    #define   MSK32BITMAP20_SEL_BIT_POS0                          0x0000001F

    #define     BA_BITMAP20_SEL_BIT_POS1                       0x0000
    #define     B16BITMAP20_SEL_BIT_POS1                       0x0000
    #define   LSb32BITMAP20_SEL_BIT_POS1                          5
    #define   LSb16BITMAP20_SEL_BIT_POS1                          5
    #define       bBITMAP20_SEL_BIT_POS1                       5
    #define   MSK32BITMAP20_SEL_BIT_POS1                          0x000003E0

    #define     BA_BITMAP20_SEL_BIT_POS2                       0x0001
    #define     B16BITMAP20_SEL_BIT_POS2                       0x0000
    #define   LSb32BITMAP20_SEL_BIT_POS2                          10
    #define   LSb16BITMAP20_SEL_BIT_POS2                          10
    #define       bBITMAP20_SEL_BIT_POS2                       5
    #define   MSK32BITMAP20_SEL_BIT_POS2                          0x00007C00

    #define     BA_BITMAP20_SEL_BIT_POS3                       0x0001
    #define     B16BITMAP20_SEL_BIT_POS3                       0x0000
    #define   LSb32BITMAP20_SEL_BIT_POS3                          15
    #define   LSb16BITMAP20_SEL_BIT_POS3                          15
    #define       bBITMAP20_SEL_BIT_POS3                       5
    #define   MSK32BITMAP20_SEL_BIT_POS3                          0x000F8000

    #define     BA_BITMAP20_SEL_BIT_POS4                       0x0002
    #define     B16BITMAP20_SEL_BIT_POS4                       0x0002
    #define   LSb32BITMAP20_SEL_BIT_POS4                          20
    #define   LSb16BITMAP20_SEL_BIT_POS4                          4
    #define       bBITMAP20_SEL_BIT_POS4                       5
    #define   MSK32BITMAP20_SEL_BIT_POS4                          0x01F00000

    #define     BA_BITMAP20_SEL_BIT_POS5                       0x0003
    #define     B16BITMAP20_SEL_BIT_POS5                       0x0002
    #define   LSb32BITMAP20_SEL_BIT_POS5                          25
    #define   LSb16BITMAP20_SEL_BIT_POS5                          9
    #define       bBITMAP20_SEL_BIT_POS5                       5
    #define   MSK32BITMAP20_SEL_BIT_POS5                          0x3E000000

    #define     RA_BITMAP20_SEL1                               0x0004

    #define     BA_BITMAP20_SEL_BIT_POS6                       0x0004
    #define     B16BITMAP20_SEL_BIT_POS6                       0x0004
    #define   LSb32BITMAP20_SEL_BIT_POS6                          0
    #define   LSb16BITMAP20_SEL_BIT_POS6                          0
    #define       bBITMAP20_SEL_BIT_POS6                       5
    #define   MSK32BITMAP20_SEL_BIT_POS6                          0x0000001F

    #define     BA_BITMAP20_SEL_BIT_POS7                       0x0004
    #define     B16BITMAP20_SEL_BIT_POS7                       0x0004
    #define   LSb32BITMAP20_SEL_BIT_POS7                          5
    #define   LSb16BITMAP20_SEL_BIT_POS7                          5
    #define       bBITMAP20_SEL_BIT_POS7                       5
    #define   MSK32BITMAP20_SEL_BIT_POS7                          0x000003E0

    #define     BA_BITMAP20_SEL_BIT_POS8                       0x0005
    #define     B16BITMAP20_SEL_BIT_POS8                       0x0004
    #define   LSb32BITMAP20_SEL_BIT_POS8                          10
    #define   LSb16BITMAP20_SEL_BIT_POS8                          10
    #define       bBITMAP20_SEL_BIT_POS8                       5
    #define   MSK32BITMAP20_SEL_BIT_POS8                          0x00007C00

    #define     BA_BITMAP20_SEL_BIT_POS9                       0x0005
    #define     B16BITMAP20_SEL_BIT_POS9                       0x0004
    #define   LSb32BITMAP20_SEL_BIT_POS9                          15
    #define   LSb16BITMAP20_SEL_BIT_POS9                          15
    #define       bBITMAP20_SEL_BIT_POS9                       5
    #define   MSK32BITMAP20_SEL_BIT_POS9                          0x000F8000

    #define     BA_BITMAP20_SEL_BIT_POS10                      0x0006
    #define     B16BITMAP20_SEL_BIT_POS10                      0x0006
    #define   LSb32BITMAP20_SEL_BIT_POS10                         20
    #define   LSb16BITMAP20_SEL_BIT_POS10                         4
    #define       bBITMAP20_SEL_BIT_POS10                      5
    #define   MSK32BITMAP20_SEL_BIT_POS10                         0x01F00000

    #define     BA_BITMAP20_SEL_BIT_POS11                      0x0007
    #define     B16BITMAP20_SEL_BIT_POS11                      0x0006
    #define   LSb32BITMAP20_SEL_BIT_POS11                         25
    #define   LSb16BITMAP20_SEL_BIT_POS11                         9
    #define       bBITMAP20_SEL_BIT_POS11                      5
    #define   MSK32BITMAP20_SEL_BIT_POS11                         0x3E000000

    #define     RA_BITMAP20_SEL2                               0x0008

    #define     BA_BITMAP20_SEL_BIT_POS12                      0x0008
    #define     B16BITMAP20_SEL_BIT_POS12                      0x0008
    #define   LSb32BITMAP20_SEL_BIT_POS12                         0
    #define   LSb16BITMAP20_SEL_BIT_POS12                         0
    #define       bBITMAP20_SEL_BIT_POS12                      5
    #define   MSK32BITMAP20_SEL_BIT_POS12                         0x0000001F

    #define     BA_BITMAP20_SEL_BIT_POS13                      0x0008
    #define     B16BITMAP20_SEL_BIT_POS13                      0x0008
    #define   LSb32BITMAP20_SEL_BIT_POS13                         5
    #define   LSb16BITMAP20_SEL_BIT_POS13                         5
    #define       bBITMAP20_SEL_BIT_POS13                      5
    #define   MSK32BITMAP20_SEL_BIT_POS13                         0x000003E0

    #define     BA_BITMAP20_SEL_BIT_POS14                      0x0009
    #define     B16BITMAP20_SEL_BIT_POS14                      0x0008
    #define   LSb32BITMAP20_SEL_BIT_POS14                         10
    #define   LSb16BITMAP20_SEL_BIT_POS14                         10
    #define       bBITMAP20_SEL_BIT_POS14                      5
    #define   MSK32BITMAP20_SEL_BIT_POS14                         0x00007C00

    #define     BA_BITMAP20_SEL_BIT_POS15                      0x0009
    #define     B16BITMAP20_SEL_BIT_POS15                      0x0008
    #define   LSb32BITMAP20_SEL_BIT_POS15                         15
    #define   LSb16BITMAP20_SEL_BIT_POS15                         15
    #define       bBITMAP20_SEL_BIT_POS15                      5
    #define   MSK32BITMAP20_SEL_BIT_POS15                         0x000F8000

    #define     BA_BITMAP20_SEL_BIT_POS16                      0x000A
    #define     B16BITMAP20_SEL_BIT_POS16                      0x000A
    #define   LSb32BITMAP20_SEL_BIT_POS16                         20
    #define   LSb16BITMAP20_SEL_BIT_POS16                         4
    #define       bBITMAP20_SEL_BIT_POS16                      5
    #define   MSK32BITMAP20_SEL_BIT_POS16                         0x01F00000

    #define     BA_BITMAP20_SEL_BIT_POS17                      0x000B
    #define     B16BITMAP20_SEL_BIT_POS17                      0x000A
    #define   LSb32BITMAP20_SEL_BIT_POS17                         25
    #define   LSb16BITMAP20_SEL_BIT_POS17                         9
    #define       bBITMAP20_SEL_BIT_POS17                      5
    #define   MSK32BITMAP20_SEL_BIT_POS17                         0x3E000000

    #define     RA_BITMAP20_SEL3                               0x000C

    #define     BA_BITMAP20_SEL_BIT_POS18                      0x000C
    #define     B16BITMAP20_SEL_BIT_POS18                      0x000C
    #define   LSb32BITMAP20_SEL_BIT_POS18                         0
    #define   LSb16BITMAP20_SEL_BIT_POS18                         0
    #define       bBITMAP20_SEL_BIT_POS18                      5
    #define   MSK32BITMAP20_SEL_BIT_POS18                         0x0000001F

    #define     BA_BITMAP20_SEL_BIT_POS19                      0x000C
    #define     B16BITMAP20_SEL_BIT_POS19                      0x000C
    #define   LSb32BITMAP20_SEL_BIT_POS19                         5
    #define   LSb16BITMAP20_SEL_BIT_POS19                         5
    #define       bBITMAP20_SEL_BIT_POS19                      5
    #define   MSK32BITMAP20_SEL_BIT_POS19                         0x000003E0
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITMAP20 {
    ///////////////////////////////////////////////////////////
    #define   GET32BITMAP20_SEL_BIT_POS0(r32)                  _BFGET_(r32, 4, 0)
    #define   SET32BITMAP20_SEL_BIT_POS0(r32,v)                _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP20_SEL_BIT_POS0(r16)                  _BFGET_(r16, 4, 0)
    #define   SET16BITMAP20_SEL_BIT_POS0(r16,v)                _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP20_SEL_BIT_POS1(r32)                  _BFGET_(r32, 9, 5)
    #define   SET32BITMAP20_SEL_BIT_POS1(r32,v)                _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP20_SEL_BIT_POS1(r16)                  _BFGET_(r16, 9, 5)
    #define   SET16BITMAP20_SEL_BIT_POS1(r16,v)                _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP20_SEL_BIT_POS2(r32)                  _BFGET_(r32,14,10)
    #define   SET32BITMAP20_SEL_BIT_POS2(r32,v)                _BFSET_(r32,14,10,v)
    #define   GET16BITMAP20_SEL_BIT_POS2(r16)                  _BFGET_(r16,14,10)
    #define   SET16BITMAP20_SEL_BIT_POS2(r16,v)                _BFSET_(r16,14,10,v)

    #define   GET32BITMAP20_SEL_BIT_POS3(r32)                  _BFGET_(r32,19,15)
    #define   SET32BITMAP20_SEL_BIT_POS3(r32,v)                _BFSET_(r32,19,15,v)

    #define   GET32BITMAP20_SEL_BIT_POS4(r32)                  _BFGET_(r32,24,20)
    #define   SET32BITMAP20_SEL_BIT_POS4(r32,v)                _BFSET_(r32,24,20,v)
    #define   GET16BITMAP20_SEL_BIT_POS4(r16)                  _BFGET_(r16, 8, 4)
    #define   SET16BITMAP20_SEL_BIT_POS4(r16,v)                _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP20_SEL_BIT_POS5(r32)                  _BFGET_(r32,29,25)
    #define   SET32BITMAP20_SEL_BIT_POS5(r32,v)                _BFSET_(r32,29,25,v)
    #define   GET16BITMAP20_SEL_BIT_POS5(r16)                  _BFGET_(r16,13, 9)
    #define   SET16BITMAP20_SEL_BIT_POS5(r16,v)                _BFSET_(r16,13, 9,v)

    #define     w32BITMAP20_SEL                                {\
            UNSG32 uSEL_BIT_POS0                               :  5;\
            UNSG32 uSEL_BIT_POS1                               :  5;\
            UNSG32 uSEL_BIT_POS2                               :  5;\
            UNSG32 uSEL_BIT_POS3                               :  5;\
            UNSG32 uSEL_BIT_POS4                               :  5;\
            UNSG32 uSEL_BIT_POS5                               :  5;\
            UNSG32 RSVDx0_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP20_SEL;
            struct w32BITMAP20_SEL;
          };
    #define   GET32BITMAP20_SEL_BIT_POS6(r32)                  _BFGET_(r32, 4, 0)
    #define   SET32BITMAP20_SEL_BIT_POS6(r32,v)                _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP20_SEL_BIT_POS6(r16)                  _BFGET_(r16, 4, 0)
    #define   SET16BITMAP20_SEL_BIT_POS6(r16,v)                _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP20_SEL_BIT_POS7(r32)                  _BFGET_(r32, 9, 5)
    #define   SET32BITMAP20_SEL_BIT_POS7(r32,v)                _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP20_SEL_BIT_POS7(r16)                  _BFGET_(r16, 9, 5)
    #define   SET16BITMAP20_SEL_BIT_POS7(r16,v)                _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP20_SEL_BIT_POS8(r32)                  _BFGET_(r32,14,10)
    #define   SET32BITMAP20_SEL_BIT_POS8(r32,v)                _BFSET_(r32,14,10,v)
    #define   GET16BITMAP20_SEL_BIT_POS8(r16)                  _BFGET_(r16,14,10)
    #define   SET16BITMAP20_SEL_BIT_POS8(r16,v)                _BFSET_(r16,14,10,v)

    #define   GET32BITMAP20_SEL_BIT_POS9(r32)                  _BFGET_(r32,19,15)
    #define   SET32BITMAP20_SEL_BIT_POS9(r32,v)                _BFSET_(r32,19,15,v)

    #define   GET32BITMAP20_SEL_BIT_POS10(r32)                 _BFGET_(r32,24,20)
    #define   SET32BITMAP20_SEL_BIT_POS10(r32,v)               _BFSET_(r32,24,20,v)
    #define   GET16BITMAP20_SEL_BIT_POS10(r16)                 _BFGET_(r16, 8, 4)
    #define   SET16BITMAP20_SEL_BIT_POS10(r16,v)               _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP20_SEL_BIT_POS11(r32)                 _BFGET_(r32,29,25)
    #define   SET32BITMAP20_SEL_BIT_POS11(r32,v)               _BFSET_(r32,29,25,v)
    #define   GET16BITMAP20_SEL_BIT_POS11(r16)                 _BFGET_(r16,13, 9)
    #define   SET16BITMAP20_SEL_BIT_POS11(r16,v)               _BFSET_(r16,13, 9,v)

    #define     w32BITMAP20_SEL1                               {\
            UNSG32 uSEL_BIT_POS6                               :  5;\
            UNSG32 uSEL_BIT_POS7                               :  5;\
            UNSG32 uSEL_BIT_POS8                               :  5;\
            UNSG32 uSEL_BIT_POS9                               :  5;\
            UNSG32 uSEL_BIT_POS10                              :  5;\
            UNSG32 uSEL_BIT_POS11                              :  5;\
            UNSG32 RSVDx4_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP20_SEL1;
            struct w32BITMAP20_SEL1;
          };
    #define   GET32BITMAP20_SEL_BIT_POS12(r32)                 _BFGET_(r32, 4, 0)
    #define   SET32BITMAP20_SEL_BIT_POS12(r32,v)               _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP20_SEL_BIT_POS12(r16)                 _BFGET_(r16, 4, 0)
    #define   SET16BITMAP20_SEL_BIT_POS12(r16,v)               _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP20_SEL_BIT_POS13(r32)                 _BFGET_(r32, 9, 5)
    #define   SET32BITMAP20_SEL_BIT_POS13(r32,v)               _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP20_SEL_BIT_POS13(r16)                 _BFGET_(r16, 9, 5)
    #define   SET16BITMAP20_SEL_BIT_POS13(r16,v)               _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP20_SEL_BIT_POS14(r32)                 _BFGET_(r32,14,10)
    #define   SET32BITMAP20_SEL_BIT_POS14(r32,v)               _BFSET_(r32,14,10,v)
    #define   GET16BITMAP20_SEL_BIT_POS14(r16)                 _BFGET_(r16,14,10)
    #define   SET16BITMAP20_SEL_BIT_POS14(r16,v)               _BFSET_(r16,14,10,v)

    #define   GET32BITMAP20_SEL_BIT_POS15(r32)                 _BFGET_(r32,19,15)
    #define   SET32BITMAP20_SEL_BIT_POS15(r32,v)               _BFSET_(r32,19,15,v)

    #define   GET32BITMAP20_SEL_BIT_POS16(r32)                 _BFGET_(r32,24,20)
    #define   SET32BITMAP20_SEL_BIT_POS16(r32,v)               _BFSET_(r32,24,20,v)
    #define   GET16BITMAP20_SEL_BIT_POS16(r16)                 _BFGET_(r16, 8, 4)
    #define   SET16BITMAP20_SEL_BIT_POS16(r16,v)               _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP20_SEL_BIT_POS17(r32)                 _BFGET_(r32,29,25)
    #define   SET32BITMAP20_SEL_BIT_POS17(r32,v)               _BFSET_(r32,29,25,v)
    #define   GET16BITMAP20_SEL_BIT_POS17(r16)                 _BFGET_(r16,13, 9)
    #define   SET16BITMAP20_SEL_BIT_POS17(r16,v)               _BFSET_(r16,13, 9,v)

    #define     w32BITMAP20_SEL2                               {\
            UNSG32 uSEL_BIT_POS12                              :  5;\
            UNSG32 uSEL_BIT_POS13                              :  5;\
            UNSG32 uSEL_BIT_POS14                              :  5;\
            UNSG32 uSEL_BIT_POS15                              :  5;\
            UNSG32 uSEL_BIT_POS16                              :  5;\
            UNSG32 uSEL_BIT_POS17                              :  5;\
            UNSG32 RSVDx8_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP20_SEL2;
            struct w32BITMAP20_SEL2;
          };
    #define   GET32BITMAP20_SEL_BIT_POS18(r32)                 _BFGET_(r32, 4, 0)
    #define   SET32BITMAP20_SEL_BIT_POS18(r32,v)               _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP20_SEL_BIT_POS18(r16)                 _BFGET_(r16, 4, 0)
    #define   SET16BITMAP20_SEL_BIT_POS18(r16,v)               _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP20_SEL_BIT_POS19(r32)                 _BFGET_(r32, 9, 5)
    #define   SET32BITMAP20_SEL_BIT_POS19(r32,v)               _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP20_SEL_BIT_POS19(r16)                 _BFGET_(r16, 9, 5)
    #define   SET16BITMAP20_SEL_BIT_POS19(r16,v)               _BFSET_(r16, 9, 5,v)

    #define     w32BITMAP20_SEL3                               {\
            UNSG32 uSEL_BIT_POS18                              :  5;\
            UNSG32 uSEL_BIT_POS19                              :  5;\
            UNSG32 RSVDxC_b10                                  : 22;\
          }
    union { UNSG32 u32BITMAP20_SEL3;
            struct w32BITMAP20_SEL3;
          };
    ///////////////////////////////////////////////////////////
    } SIE_BITMAP20;

    typedef union  T32BITMAP20_SEL
          { UNSG32 u32;
            struct w32BITMAP20_SEL;
                 } T32BITMAP20_SEL;
    typedef union  T32BITMAP20_SEL1
          { UNSG32 u32;
            struct w32BITMAP20_SEL1;
                 } T32BITMAP20_SEL1;
    typedef union  T32BITMAP20_SEL2
          { UNSG32 u32;
            struct w32BITMAP20_SEL2;
                 } T32BITMAP20_SEL2;
    typedef union  T32BITMAP20_SEL3
          { UNSG32 u32;
            struct w32BITMAP20_SEL3;
                 } T32BITMAP20_SEL3;
    ///////////////////////////////////////////////////////////

    typedef union  TBITMAP20_SEL
          { UNSG32 u32[4];
            struct {
            struct w32BITMAP20_SEL;
            struct w32BITMAP20_SEL1;
            struct w32BITMAP20_SEL2;
            struct w32BITMAP20_SEL3;
                   };
                 } TBITMAP20_SEL;

    ///////////////////////////////////////////////////////////
     SIGN32 BITMAP20_drvrd(SIE_BITMAP20 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITMAP20_drvwr(SIE_BITMAP20 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITMAP20_reset(SIE_BITMAP20 *p);
     SIGN32 BITMAP20_cmp  (SIE_BITMAP20 *p, SIE_BITMAP20 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITMAP20_check(p,pie,pfx,hLOG) BITMAP20_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITMAP20_print(p,    pfx,hLOG) BITMAP20_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITMAP20
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE BITMAP32                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 SEL                  (P)
///               %unsigned 5  BIT_POS0                  0x0
///               %unsigned 5  BIT_POS1                  0x1
///               %unsigned 5  BIT_POS2                  0x2
///               %unsigned 5  BIT_POS3                  0x3
///               %unsigned 5  BIT_POS4                  0x4
///               %unsigned 5  BIT_POS5                  0x5
///               %%        2          # Stuffing bits...
///     # 0x00004 SEL1
///               %unsigned 5  BIT_POS6                  0x6
///               %unsigned 5  BIT_POS7                  0x7
///               %unsigned 5  BIT_POS8                  0x8
///               %unsigned 5  BIT_POS9                  0x9
///               %unsigned 5  BIT_POS10                 0xA
///               %unsigned 5  BIT_POS11                 0xB
///               %%        2          # Stuffing bits...
///     # 0x00008 SEL2
///               %unsigned 5  BIT_POS12                 0xC
///               %unsigned 5  BIT_POS13                 0xD
///               %unsigned 5  BIT_POS14                 0xE
///               %unsigned 5  BIT_POS15                 0xF
///               %unsigned 5  BIT_POS16                 0x10
///               %unsigned 5  BIT_POS17                 0x11
///               %%        2          # Stuffing bits...
///     # 0x0000C SEL3
///               %unsigned 5  BIT_POS18                 0x12
///               %unsigned 5  BIT_POS19                 0x13
///               %unsigned 5  BIT_POS20                 0x14
///               %unsigned 5  BIT_POS21                 0x15
///               %unsigned 5  BIT_POS22                 0x16
///               %unsigned 5  BIT_POS23                 0x17
///               %%        2          # Stuffing bits...
///     # 0x00010 SEL4
///               %unsigned 5  BIT_POS24                 0x18
///               %unsigned 5  BIT_POS25                 0x19
///               %unsigned 5  BIT_POS26                 0x1A
///               %unsigned 5  BIT_POS27                 0x1B
///               %unsigned 5  BIT_POS28                 0x1C
///               %unsigned 5  BIT_POS29                 0x1D
///               %%        2          # Stuffing bits...
///     # 0x00014 SEL5
///               %unsigned 5  BIT_POS30                 0x1E
///               %unsigned 5  BIT_POS31                 0x1F
///                                    ###
///                                    * Specifies mapping of 32 bit data from Read Client which need to be used to form pixels for Inverse Scan mode.
///                                    ###
///               %%        22         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      24B, bits:     160b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITMAP32
#define h_BITMAP32 (){}

    #define     RA_BITMAP32_SEL                                0x0000

    #define     BA_BITMAP32_SEL_BIT_POS0                       0x0000
    #define     B16BITMAP32_SEL_BIT_POS0                       0x0000
    #define   LSb32BITMAP32_SEL_BIT_POS0                          0
    #define   LSb16BITMAP32_SEL_BIT_POS0                          0
    #define       bBITMAP32_SEL_BIT_POS0                       5
    #define   MSK32BITMAP32_SEL_BIT_POS0                          0x0000001F

    #define     BA_BITMAP32_SEL_BIT_POS1                       0x0000
    #define     B16BITMAP32_SEL_BIT_POS1                       0x0000
    #define   LSb32BITMAP32_SEL_BIT_POS1                          5
    #define   LSb16BITMAP32_SEL_BIT_POS1                          5
    #define       bBITMAP32_SEL_BIT_POS1                       5
    #define   MSK32BITMAP32_SEL_BIT_POS1                          0x000003E0

    #define     BA_BITMAP32_SEL_BIT_POS2                       0x0001
    #define     B16BITMAP32_SEL_BIT_POS2                       0x0000
    #define   LSb32BITMAP32_SEL_BIT_POS2                          10
    #define   LSb16BITMAP32_SEL_BIT_POS2                          10
    #define       bBITMAP32_SEL_BIT_POS2                       5
    #define   MSK32BITMAP32_SEL_BIT_POS2                          0x00007C00

    #define     BA_BITMAP32_SEL_BIT_POS3                       0x0001
    #define     B16BITMAP32_SEL_BIT_POS3                       0x0000
    #define   LSb32BITMAP32_SEL_BIT_POS3                          15
    #define   LSb16BITMAP32_SEL_BIT_POS3                          15
    #define       bBITMAP32_SEL_BIT_POS3                       5
    #define   MSK32BITMAP32_SEL_BIT_POS3                          0x000F8000

    #define     BA_BITMAP32_SEL_BIT_POS4                       0x0002
    #define     B16BITMAP32_SEL_BIT_POS4                       0x0002
    #define   LSb32BITMAP32_SEL_BIT_POS4                          20
    #define   LSb16BITMAP32_SEL_BIT_POS4                          4
    #define       bBITMAP32_SEL_BIT_POS4                       5
    #define   MSK32BITMAP32_SEL_BIT_POS4                          0x01F00000

    #define     BA_BITMAP32_SEL_BIT_POS5                       0x0003
    #define     B16BITMAP32_SEL_BIT_POS5                       0x0002
    #define   LSb32BITMAP32_SEL_BIT_POS5                          25
    #define   LSb16BITMAP32_SEL_BIT_POS5                          9
    #define       bBITMAP32_SEL_BIT_POS5                       5
    #define   MSK32BITMAP32_SEL_BIT_POS5                          0x3E000000

    #define     RA_BITMAP32_SEL1                               0x0004

    #define     BA_BITMAP32_SEL_BIT_POS6                       0x0004
    #define     B16BITMAP32_SEL_BIT_POS6                       0x0004
    #define   LSb32BITMAP32_SEL_BIT_POS6                          0
    #define   LSb16BITMAP32_SEL_BIT_POS6                          0
    #define       bBITMAP32_SEL_BIT_POS6                       5
    #define   MSK32BITMAP32_SEL_BIT_POS6                          0x0000001F

    #define     BA_BITMAP32_SEL_BIT_POS7                       0x0004
    #define     B16BITMAP32_SEL_BIT_POS7                       0x0004
    #define   LSb32BITMAP32_SEL_BIT_POS7                          5
    #define   LSb16BITMAP32_SEL_BIT_POS7                          5
    #define       bBITMAP32_SEL_BIT_POS7                       5
    #define   MSK32BITMAP32_SEL_BIT_POS7                          0x000003E0

    #define     BA_BITMAP32_SEL_BIT_POS8                       0x0005
    #define     B16BITMAP32_SEL_BIT_POS8                       0x0004
    #define   LSb32BITMAP32_SEL_BIT_POS8                          10
    #define   LSb16BITMAP32_SEL_BIT_POS8                          10
    #define       bBITMAP32_SEL_BIT_POS8                       5
    #define   MSK32BITMAP32_SEL_BIT_POS8                          0x00007C00

    #define     BA_BITMAP32_SEL_BIT_POS9                       0x0005
    #define     B16BITMAP32_SEL_BIT_POS9                       0x0004
    #define   LSb32BITMAP32_SEL_BIT_POS9                          15
    #define   LSb16BITMAP32_SEL_BIT_POS9                          15
    #define       bBITMAP32_SEL_BIT_POS9                       5
    #define   MSK32BITMAP32_SEL_BIT_POS9                          0x000F8000

    #define     BA_BITMAP32_SEL_BIT_POS10                      0x0006
    #define     B16BITMAP32_SEL_BIT_POS10                      0x0006
    #define   LSb32BITMAP32_SEL_BIT_POS10                         20
    #define   LSb16BITMAP32_SEL_BIT_POS10                         4
    #define       bBITMAP32_SEL_BIT_POS10                      5
    #define   MSK32BITMAP32_SEL_BIT_POS10                         0x01F00000

    #define     BA_BITMAP32_SEL_BIT_POS11                      0x0007
    #define     B16BITMAP32_SEL_BIT_POS11                      0x0006
    #define   LSb32BITMAP32_SEL_BIT_POS11                         25
    #define   LSb16BITMAP32_SEL_BIT_POS11                         9
    #define       bBITMAP32_SEL_BIT_POS11                      5
    #define   MSK32BITMAP32_SEL_BIT_POS11                         0x3E000000

    #define     RA_BITMAP32_SEL2                               0x0008

    #define     BA_BITMAP32_SEL_BIT_POS12                      0x0008
    #define     B16BITMAP32_SEL_BIT_POS12                      0x0008
    #define   LSb32BITMAP32_SEL_BIT_POS12                         0
    #define   LSb16BITMAP32_SEL_BIT_POS12                         0
    #define       bBITMAP32_SEL_BIT_POS12                      5
    #define   MSK32BITMAP32_SEL_BIT_POS12                         0x0000001F

    #define     BA_BITMAP32_SEL_BIT_POS13                      0x0008
    #define     B16BITMAP32_SEL_BIT_POS13                      0x0008
    #define   LSb32BITMAP32_SEL_BIT_POS13                         5
    #define   LSb16BITMAP32_SEL_BIT_POS13                         5
    #define       bBITMAP32_SEL_BIT_POS13                      5
    #define   MSK32BITMAP32_SEL_BIT_POS13                         0x000003E0

    #define     BA_BITMAP32_SEL_BIT_POS14                      0x0009
    #define     B16BITMAP32_SEL_BIT_POS14                      0x0008
    #define   LSb32BITMAP32_SEL_BIT_POS14                         10
    #define   LSb16BITMAP32_SEL_BIT_POS14                         10
    #define       bBITMAP32_SEL_BIT_POS14                      5
    #define   MSK32BITMAP32_SEL_BIT_POS14                         0x00007C00

    #define     BA_BITMAP32_SEL_BIT_POS15                      0x0009
    #define     B16BITMAP32_SEL_BIT_POS15                      0x0008
    #define   LSb32BITMAP32_SEL_BIT_POS15                         15
    #define   LSb16BITMAP32_SEL_BIT_POS15                         15
    #define       bBITMAP32_SEL_BIT_POS15                      5
    #define   MSK32BITMAP32_SEL_BIT_POS15                         0x000F8000

    #define     BA_BITMAP32_SEL_BIT_POS16                      0x000A
    #define     B16BITMAP32_SEL_BIT_POS16                      0x000A
    #define   LSb32BITMAP32_SEL_BIT_POS16                         20
    #define   LSb16BITMAP32_SEL_BIT_POS16                         4
    #define       bBITMAP32_SEL_BIT_POS16                      5
    #define   MSK32BITMAP32_SEL_BIT_POS16                         0x01F00000

    #define     BA_BITMAP32_SEL_BIT_POS17                      0x000B
    #define     B16BITMAP32_SEL_BIT_POS17                      0x000A
    #define   LSb32BITMAP32_SEL_BIT_POS17                         25
    #define   LSb16BITMAP32_SEL_BIT_POS17                         9
    #define       bBITMAP32_SEL_BIT_POS17                      5
    #define   MSK32BITMAP32_SEL_BIT_POS17                         0x3E000000

    #define     RA_BITMAP32_SEL3                               0x000C

    #define     BA_BITMAP32_SEL_BIT_POS18                      0x000C
    #define     B16BITMAP32_SEL_BIT_POS18                      0x000C
    #define   LSb32BITMAP32_SEL_BIT_POS18                         0
    #define   LSb16BITMAP32_SEL_BIT_POS18                         0
    #define       bBITMAP32_SEL_BIT_POS18                      5
    #define   MSK32BITMAP32_SEL_BIT_POS18                         0x0000001F

    #define     BA_BITMAP32_SEL_BIT_POS19                      0x000C
    #define     B16BITMAP32_SEL_BIT_POS19                      0x000C
    #define   LSb32BITMAP32_SEL_BIT_POS19                         5
    #define   LSb16BITMAP32_SEL_BIT_POS19                         5
    #define       bBITMAP32_SEL_BIT_POS19                      5
    #define   MSK32BITMAP32_SEL_BIT_POS19                         0x000003E0

    #define     BA_BITMAP32_SEL_BIT_POS20                      0x000D
    #define     B16BITMAP32_SEL_BIT_POS20                      0x000C
    #define   LSb32BITMAP32_SEL_BIT_POS20                         10
    #define   LSb16BITMAP32_SEL_BIT_POS20                         10
    #define       bBITMAP32_SEL_BIT_POS20                      5
    #define   MSK32BITMAP32_SEL_BIT_POS20                         0x00007C00

    #define     BA_BITMAP32_SEL_BIT_POS21                      0x000D
    #define     B16BITMAP32_SEL_BIT_POS21                      0x000C
    #define   LSb32BITMAP32_SEL_BIT_POS21                         15
    #define   LSb16BITMAP32_SEL_BIT_POS21                         15
    #define       bBITMAP32_SEL_BIT_POS21                      5
    #define   MSK32BITMAP32_SEL_BIT_POS21                         0x000F8000

    #define     BA_BITMAP32_SEL_BIT_POS22                      0x000E
    #define     B16BITMAP32_SEL_BIT_POS22                      0x000E
    #define   LSb32BITMAP32_SEL_BIT_POS22                         20
    #define   LSb16BITMAP32_SEL_BIT_POS22                         4
    #define       bBITMAP32_SEL_BIT_POS22                      5
    #define   MSK32BITMAP32_SEL_BIT_POS22                         0x01F00000

    #define     BA_BITMAP32_SEL_BIT_POS23                      0x000F
    #define     B16BITMAP32_SEL_BIT_POS23                      0x000E
    #define   LSb32BITMAP32_SEL_BIT_POS23                         25
    #define   LSb16BITMAP32_SEL_BIT_POS23                         9
    #define       bBITMAP32_SEL_BIT_POS23                      5
    #define   MSK32BITMAP32_SEL_BIT_POS23                         0x3E000000

    #define     RA_BITMAP32_SEL4                               0x0010

    #define     BA_BITMAP32_SEL_BIT_POS24                      0x0010
    #define     B16BITMAP32_SEL_BIT_POS24                      0x0010
    #define   LSb32BITMAP32_SEL_BIT_POS24                         0
    #define   LSb16BITMAP32_SEL_BIT_POS24                         0
    #define       bBITMAP32_SEL_BIT_POS24                      5
    #define   MSK32BITMAP32_SEL_BIT_POS24                         0x0000001F

    #define     BA_BITMAP32_SEL_BIT_POS25                      0x0010
    #define     B16BITMAP32_SEL_BIT_POS25                      0x0010
    #define   LSb32BITMAP32_SEL_BIT_POS25                         5
    #define   LSb16BITMAP32_SEL_BIT_POS25                         5
    #define       bBITMAP32_SEL_BIT_POS25                      5
    #define   MSK32BITMAP32_SEL_BIT_POS25                         0x000003E0

    #define     BA_BITMAP32_SEL_BIT_POS26                      0x0011
    #define     B16BITMAP32_SEL_BIT_POS26                      0x0010
    #define   LSb32BITMAP32_SEL_BIT_POS26                         10
    #define   LSb16BITMAP32_SEL_BIT_POS26                         10
    #define       bBITMAP32_SEL_BIT_POS26                      5
    #define   MSK32BITMAP32_SEL_BIT_POS26                         0x00007C00

    #define     BA_BITMAP32_SEL_BIT_POS27                      0x0011
    #define     B16BITMAP32_SEL_BIT_POS27                      0x0010
    #define   LSb32BITMAP32_SEL_BIT_POS27                         15
    #define   LSb16BITMAP32_SEL_BIT_POS27                         15
    #define       bBITMAP32_SEL_BIT_POS27                      5
    #define   MSK32BITMAP32_SEL_BIT_POS27                         0x000F8000

    #define     BA_BITMAP32_SEL_BIT_POS28                      0x0012
    #define     B16BITMAP32_SEL_BIT_POS28                      0x0012
    #define   LSb32BITMAP32_SEL_BIT_POS28                         20
    #define   LSb16BITMAP32_SEL_BIT_POS28                         4
    #define       bBITMAP32_SEL_BIT_POS28                      5
    #define   MSK32BITMAP32_SEL_BIT_POS28                         0x01F00000

    #define     BA_BITMAP32_SEL_BIT_POS29                      0x0013
    #define     B16BITMAP32_SEL_BIT_POS29                      0x0012
    #define   LSb32BITMAP32_SEL_BIT_POS29                         25
    #define   LSb16BITMAP32_SEL_BIT_POS29                         9
    #define       bBITMAP32_SEL_BIT_POS29                      5
    #define   MSK32BITMAP32_SEL_BIT_POS29                         0x3E000000

    #define     RA_BITMAP32_SEL5                               0x0014

    #define     BA_BITMAP32_SEL_BIT_POS30                      0x0014
    #define     B16BITMAP32_SEL_BIT_POS30                      0x0014
    #define   LSb32BITMAP32_SEL_BIT_POS30                         0
    #define   LSb16BITMAP32_SEL_BIT_POS30                         0
    #define       bBITMAP32_SEL_BIT_POS30                      5
    #define   MSK32BITMAP32_SEL_BIT_POS30                         0x0000001F

    #define     BA_BITMAP32_SEL_BIT_POS31                      0x0014
    #define     B16BITMAP32_SEL_BIT_POS31                      0x0014
    #define   LSb32BITMAP32_SEL_BIT_POS31                         5
    #define   LSb16BITMAP32_SEL_BIT_POS31                         5
    #define       bBITMAP32_SEL_BIT_POS31                      5
    #define   MSK32BITMAP32_SEL_BIT_POS31                         0x000003E0
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITMAP32 {
    ///////////////////////////////////////////////////////////
    #define   GET32BITMAP32_SEL_BIT_POS0(r32)                  _BFGET_(r32, 4, 0)
    #define   SET32BITMAP32_SEL_BIT_POS0(r32,v)                _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP32_SEL_BIT_POS0(r16)                  _BFGET_(r16, 4, 0)
    #define   SET16BITMAP32_SEL_BIT_POS0(r16,v)                _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP32_SEL_BIT_POS1(r32)                  _BFGET_(r32, 9, 5)
    #define   SET32BITMAP32_SEL_BIT_POS1(r32,v)                _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP32_SEL_BIT_POS1(r16)                  _BFGET_(r16, 9, 5)
    #define   SET16BITMAP32_SEL_BIT_POS1(r16,v)                _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP32_SEL_BIT_POS2(r32)                  _BFGET_(r32,14,10)
    #define   SET32BITMAP32_SEL_BIT_POS2(r32,v)                _BFSET_(r32,14,10,v)
    #define   GET16BITMAP32_SEL_BIT_POS2(r16)                  _BFGET_(r16,14,10)
    #define   SET16BITMAP32_SEL_BIT_POS2(r16,v)                _BFSET_(r16,14,10,v)

    #define   GET32BITMAP32_SEL_BIT_POS3(r32)                  _BFGET_(r32,19,15)
    #define   SET32BITMAP32_SEL_BIT_POS3(r32,v)                _BFSET_(r32,19,15,v)

    #define   GET32BITMAP32_SEL_BIT_POS4(r32)                  _BFGET_(r32,24,20)
    #define   SET32BITMAP32_SEL_BIT_POS4(r32,v)                _BFSET_(r32,24,20,v)
    #define   GET16BITMAP32_SEL_BIT_POS4(r16)                  _BFGET_(r16, 8, 4)
    #define   SET16BITMAP32_SEL_BIT_POS4(r16,v)                _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP32_SEL_BIT_POS5(r32)                  _BFGET_(r32,29,25)
    #define   SET32BITMAP32_SEL_BIT_POS5(r32,v)                _BFSET_(r32,29,25,v)
    #define   GET16BITMAP32_SEL_BIT_POS5(r16)                  _BFGET_(r16,13, 9)
    #define   SET16BITMAP32_SEL_BIT_POS5(r16,v)                _BFSET_(r16,13, 9,v)

    #define     w32BITMAP32_SEL                                {\
            UNSG32 uSEL_BIT_POS0                               :  5;\
            UNSG32 uSEL_BIT_POS1                               :  5;\
            UNSG32 uSEL_BIT_POS2                               :  5;\
            UNSG32 uSEL_BIT_POS3                               :  5;\
            UNSG32 uSEL_BIT_POS4                               :  5;\
            UNSG32 uSEL_BIT_POS5                               :  5;\
            UNSG32 RSVDx0_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP32_SEL;
            struct w32BITMAP32_SEL;
          };
    #define   GET32BITMAP32_SEL_BIT_POS6(r32)                  _BFGET_(r32, 4, 0)
    #define   SET32BITMAP32_SEL_BIT_POS6(r32,v)                _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP32_SEL_BIT_POS6(r16)                  _BFGET_(r16, 4, 0)
    #define   SET16BITMAP32_SEL_BIT_POS6(r16,v)                _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP32_SEL_BIT_POS7(r32)                  _BFGET_(r32, 9, 5)
    #define   SET32BITMAP32_SEL_BIT_POS7(r32,v)                _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP32_SEL_BIT_POS7(r16)                  _BFGET_(r16, 9, 5)
    #define   SET16BITMAP32_SEL_BIT_POS7(r16,v)                _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP32_SEL_BIT_POS8(r32)                  _BFGET_(r32,14,10)
    #define   SET32BITMAP32_SEL_BIT_POS8(r32,v)                _BFSET_(r32,14,10,v)
    #define   GET16BITMAP32_SEL_BIT_POS8(r16)                  _BFGET_(r16,14,10)
    #define   SET16BITMAP32_SEL_BIT_POS8(r16,v)                _BFSET_(r16,14,10,v)

    #define   GET32BITMAP32_SEL_BIT_POS9(r32)                  _BFGET_(r32,19,15)
    #define   SET32BITMAP32_SEL_BIT_POS9(r32,v)                _BFSET_(r32,19,15,v)

    #define   GET32BITMAP32_SEL_BIT_POS10(r32)                 _BFGET_(r32,24,20)
    #define   SET32BITMAP32_SEL_BIT_POS10(r32,v)               _BFSET_(r32,24,20,v)
    #define   GET16BITMAP32_SEL_BIT_POS10(r16)                 _BFGET_(r16, 8, 4)
    #define   SET16BITMAP32_SEL_BIT_POS10(r16,v)               _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP32_SEL_BIT_POS11(r32)                 _BFGET_(r32,29,25)
    #define   SET32BITMAP32_SEL_BIT_POS11(r32,v)               _BFSET_(r32,29,25,v)
    #define   GET16BITMAP32_SEL_BIT_POS11(r16)                 _BFGET_(r16,13, 9)
    #define   SET16BITMAP32_SEL_BIT_POS11(r16,v)               _BFSET_(r16,13, 9,v)

    #define     w32BITMAP32_SEL1                               {\
            UNSG32 uSEL_BIT_POS6                               :  5;\
            UNSG32 uSEL_BIT_POS7                               :  5;\
            UNSG32 uSEL_BIT_POS8                               :  5;\
            UNSG32 uSEL_BIT_POS9                               :  5;\
            UNSG32 uSEL_BIT_POS10                              :  5;\
            UNSG32 uSEL_BIT_POS11                              :  5;\
            UNSG32 RSVDx4_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP32_SEL1;
            struct w32BITMAP32_SEL1;
          };
    #define   GET32BITMAP32_SEL_BIT_POS12(r32)                 _BFGET_(r32, 4, 0)
    #define   SET32BITMAP32_SEL_BIT_POS12(r32,v)               _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP32_SEL_BIT_POS12(r16)                 _BFGET_(r16, 4, 0)
    #define   SET16BITMAP32_SEL_BIT_POS12(r16,v)               _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP32_SEL_BIT_POS13(r32)                 _BFGET_(r32, 9, 5)
    #define   SET32BITMAP32_SEL_BIT_POS13(r32,v)               _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP32_SEL_BIT_POS13(r16)                 _BFGET_(r16, 9, 5)
    #define   SET16BITMAP32_SEL_BIT_POS13(r16,v)               _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP32_SEL_BIT_POS14(r32)                 _BFGET_(r32,14,10)
    #define   SET32BITMAP32_SEL_BIT_POS14(r32,v)               _BFSET_(r32,14,10,v)
    #define   GET16BITMAP32_SEL_BIT_POS14(r16)                 _BFGET_(r16,14,10)
    #define   SET16BITMAP32_SEL_BIT_POS14(r16,v)               _BFSET_(r16,14,10,v)

    #define   GET32BITMAP32_SEL_BIT_POS15(r32)                 _BFGET_(r32,19,15)
    #define   SET32BITMAP32_SEL_BIT_POS15(r32,v)               _BFSET_(r32,19,15,v)

    #define   GET32BITMAP32_SEL_BIT_POS16(r32)                 _BFGET_(r32,24,20)
    #define   SET32BITMAP32_SEL_BIT_POS16(r32,v)               _BFSET_(r32,24,20,v)
    #define   GET16BITMAP32_SEL_BIT_POS16(r16)                 _BFGET_(r16, 8, 4)
    #define   SET16BITMAP32_SEL_BIT_POS16(r16,v)               _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP32_SEL_BIT_POS17(r32)                 _BFGET_(r32,29,25)
    #define   SET32BITMAP32_SEL_BIT_POS17(r32,v)               _BFSET_(r32,29,25,v)
    #define   GET16BITMAP32_SEL_BIT_POS17(r16)                 _BFGET_(r16,13, 9)
    #define   SET16BITMAP32_SEL_BIT_POS17(r16,v)               _BFSET_(r16,13, 9,v)

    #define     w32BITMAP32_SEL2                               {\
            UNSG32 uSEL_BIT_POS12                              :  5;\
            UNSG32 uSEL_BIT_POS13                              :  5;\
            UNSG32 uSEL_BIT_POS14                              :  5;\
            UNSG32 uSEL_BIT_POS15                              :  5;\
            UNSG32 uSEL_BIT_POS16                              :  5;\
            UNSG32 uSEL_BIT_POS17                              :  5;\
            UNSG32 RSVDx8_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP32_SEL2;
            struct w32BITMAP32_SEL2;
          };
    #define   GET32BITMAP32_SEL_BIT_POS18(r32)                 _BFGET_(r32, 4, 0)
    #define   SET32BITMAP32_SEL_BIT_POS18(r32,v)               _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP32_SEL_BIT_POS18(r16)                 _BFGET_(r16, 4, 0)
    #define   SET16BITMAP32_SEL_BIT_POS18(r16,v)               _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP32_SEL_BIT_POS19(r32)                 _BFGET_(r32, 9, 5)
    #define   SET32BITMAP32_SEL_BIT_POS19(r32,v)               _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP32_SEL_BIT_POS19(r16)                 _BFGET_(r16, 9, 5)
    #define   SET16BITMAP32_SEL_BIT_POS19(r16,v)               _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP32_SEL_BIT_POS20(r32)                 _BFGET_(r32,14,10)
    #define   SET32BITMAP32_SEL_BIT_POS20(r32,v)               _BFSET_(r32,14,10,v)
    #define   GET16BITMAP32_SEL_BIT_POS20(r16)                 _BFGET_(r16,14,10)
    #define   SET16BITMAP32_SEL_BIT_POS20(r16,v)               _BFSET_(r16,14,10,v)

    #define   GET32BITMAP32_SEL_BIT_POS21(r32)                 _BFGET_(r32,19,15)
    #define   SET32BITMAP32_SEL_BIT_POS21(r32,v)               _BFSET_(r32,19,15,v)

    #define   GET32BITMAP32_SEL_BIT_POS22(r32)                 _BFGET_(r32,24,20)
    #define   SET32BITMAP32_SEL_BIT_POS22(r32,v)               _BFSET_(r32,24,20,v)
    #define   GET16BITMAP32_SEL_BIT_POS22(r16)                 _BFGET_(r16, 8, 4)
    #define   SET16BITMAP32_SEL_BIT_POS22(r16,v)               _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP32_SEL_BIT_POS23(r32)                 _BFGET_(r32,29,25)
    #define   SET32BITMAP32_SEL_BIT_POS23(r32,v)               _BFSET_(r32,29,25,v)
    #define   GET16BITMAP32_SEL_BIT_POS23(r16)                 _BFGET_(r16,13, 9)
    #define   SET16BITMAP32_SEL_BIT_POS23(r16,v)               _BFSET_(r16,13, 9,v)

    #define     w32BITMAP32_SEL3                               {\
            UNSG32 uSEL_BIT_POS18                              :  5;\
            UNSG32 uSEL_BIT_POS19                              :  5;\
            UNSG32 uSEL_BIT_POS20                              :  5;\
            UNSG32 uSEL_BIT_POS21                              :  5;\
            UNSG32 uSEL_BIT_POS22                              :  5;\
            UNSG32 uSEL_BIT_POS23                              :  5;\
            UNSG32 RSVDxC_b30                                  :  2;\
          }
    union { UNSG32 u32BITMAP32_SEL3;
            struct w32BITMAP32_SEL3;
          };
    #define   GET32BITMAP32_SEL_BIT_POS24(r32)                 _BFGET_(r32, 4, 0)
    #define   SET32BITMAP32_SEL_BIT_POS24(r32,v)               _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP32_SEL_BIT_POS24(r16)                 _BFGET_(r16, 4, 0)
    #define   SET16BITMAP32_SEL_BIT_POS24(r16,v)               _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP32_SEL_BIT_POS25(r32)                 _BFGET_(r32, 9, 5)
    #define   SET32BITMAP32_SEL_BIT_POS25(r32,v)               _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP32_SEL_BIT_POS25(r16)                 _BFGET_(r16, 9, 5)
    #define   SET16BITMAP32_SEL_BIT_POS25(r16,v)               _BFSET_(r16, 9, 5,v)

    #define   GET32BITMAP32_SEL_BIT_POS26(r32)                 _BFGET_(r32,14,10)
    #define   SET32BITMAP32_SEL_BIT_POS26(r32,v)               _BFSET_(r32,14,10,v)
    #define   GET16BITMAP32_SEL_BIT_POS26(r16)                 _BFGET_(r16,14,10)
    #define   SET16BITMAP32_SEL_BIT_POS26(r16,v)               _BFSET_(r16,14,10,v)

    #define   GET32BITMAP32_SEL_BIT_POS27(r32)                 _BFGET_(r32,19,15)
    #define   SET32BITMAP32_SEL_BIT_POS27(r32,v)               _BFSET_(r32,19,15,v)

    #define   GET32BITMAP32_SEL_BIT_POS28(r32)                 _BFGET_(r32,24,20)
    #define   SET32BITMAP32_SEL_BIT_POS28(r32,v)               _BFSET_(r32,24,20,v)
    #define   GET16BITMAP32_SEL_BIT_POS28(r16)                 _BFGET_(r16, 8, 4)
    #define   SET16BITMAP32_SEL_BIT_POS28(r16,v)               _BFSET_(r16, 8, 4,v)

    #define   GET32BITMAP32_SEL_BIT_POS29(r32)                 _BFGET_(r32,29,25)
    #define   SET32BITMAP32_SEL_BIT_POS29(r32,v)               _BFSET_(r32,29,25,v)
    #define   GET16BITMAP32_SEL_BIT_POS29(r16)                 _BFGET_(r16,13, 9)
    #define   SET16BITMAP32_SEL_BIT_POS29(r16,v)               _BFSET_(r16,13, 9,v)

    #define     w32BITMAP32_SEL4                               {\
            UNSG32 uSEL_BIT_POS24                              :  5;\
            UNSG32 uSEL_BIT_POS25                              :  5;\
            UNSG32 uSEL_BIT_POS26                              :  5;\
            UNSG32 uSEL_BIT_POS27                              :  5;\
            UNSG32 uSEL_BIT_POS28                              :  5;\
            UNSG32 uSEL_BIT_POS29                              :  5;\
            UNSG32 RSVDx10_b30                                 :  2;\
          }
    union { UNSG32 u32BITMAP32_SEL4;
            struct w32BITMAP32_SEL4;
          };
    #define   GET32BITMAP32_SEL_BIT_POS30(r32)                 _BFGET_(r32, 4, 0)
    #define   SET32BITMAP32_SEL_BIT_POS30(r32,v)               _BFSET_(r32, 4, 0,v)
    #define   GET16BITMAP32_SEL_BIT_POS30(r16)                 _BFGET_(r16, 4, 0)
    #define   SET16BITMAP32_SEL_BIT_POS30(r16,v)               _BFSET_(r16, 4, 0,v)

    #define   GET32BITMAP32_SEL_BIT_POS31(r32)                 _BFGET_(r32, 9, 5)
    #define   SET32BITMAP32_SEL_BIT_POS31(r32,v)               _BFSET_(r32, 9, 5,v)
    #define   GET16BITMAP32_SEL_BIT_POS31(r16)                 _BFGET_(r16, 9, 5)
    #define   SET16BITMAP32_SEL_BIT_POS31(r16,v)               _BFSET_(r16, 9, 5,v)

    #define     w32BITMAP32_SEL5                               {\
            UNSG32 uSEL_BIT_POS30                              :  5;\
            UNSG32 uSEL_BIT_POS31                              :  5;\
            UNSG32 RSVDx14_b10                                 : 22;\
          }
    union { UNSG32 u32BITMAP32_SEL5;
            struct w32BITMAP32_SEL5;
          };
    ///////////////////////////////////////////////////////////
    } SIE_BITMAP32;

    typedef union  T32BITMAP32_SEL
          { UNSG32 u32;
            struct w32BITMAP32_SEL;
                 } T32BITMAP32_SEL;
    typedef union  T32BITMAP32_SEL1
          { UNSG32 u32;
            struct w32BITMAP32_SEL1;
                 } T32BITMAP32_SEL1;
    typedef union  T32BITMAP32_SEL2
          { UNSG32 u32;
            struct w32BITMAP32_SEL2;
                 } T32BITMAP32_SEL2;
    typedef union  T32BITMAP32_SEL3
          { UNSG32 u32;
            struct w32BITMAP32_SEL3;
                 } T32BITMAP32_SEL3;
    typedef union  T32BITMAP32_SEL4
          { UNSG32 u32;
            struct w32BITMAP32_SEL4;
                 } T32BITMAP32_SEL4;
    typedef union  T32BITMAP32_SEL5
          { UNSG32 u32;
            struct w32BITMAP32_SEL5;
                 } T32BITMAP32_SEL5;
    ///////////////////////////////////////////////////////////

    typedef union  TBITMAP32_SEL
          { UNSG32 u32[6];
            struct {
            struct w32BITMAP32_SEL;
            struct w32BITMAP32_SEL1;
            struct w32BITMAP32_SEL2;
            struct w32BITMAP32_SEL3;
            struct w32BITMAP32_SEL4;
            struct w32BITMAP32_SEL5;
                   };
                 } TBITMAP32_SEL;

    ///////////////////////////////////////////////////////////
     SIGN32 BITMAP32_drvrd(SIE_BITMAP32 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITMAP32_drvwr(SIE_BITMAP32 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITMAP32_reset(SIE_BITMAP32 *p);
     SIGN32 BITMAP32_cmp  (SIE_BITMAP32 *p, SIE_BITMAP32 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITMAP32_check(p,pie,pfx,hLOG) BITMAP32_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITMAP32_print(p,    pfx,hLOG) BITMAP32_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITMAP32
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE BITMAP16                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 SEL                  (P)
///               %unsigned 4  BIT_POS0                  0x0
///               %unsigned 4  BIT_POS1                  0x1
///               %unsigned 4  BIT_POS2                  0x2
///               %unsigned 4  BIT_POS3                  0x3
///               %unsigned 4  BIT_POS4                  0x4
///               %unsigned 4  BIT_POS5                  0x5
///               %unsigned 4  BIT_POS6                  0x6
///               %unsigned 4  BIT_POS7                  0x7
///     # 0x00004 SEL1
///               %unsigned 4  BIT_POS8                  0x8
///               %unsigned 4  BIT_POS9                  0x9
///               %unsigned 4  BIT_POS10                 0xA
///               %unsigned 4  BIT_POS11                 0xB
///               %unsigned 4  BIT_POS12                 0xC
///               %unsigned 4  BIT_POS13                 0xD
///               %unsigned 4  BIT_POS14                 0xE
///               %unsigned 4  BIT_POS15                 0xF
///                                    ###
///                                    * Specifies mapping of new bit locations within 16 bit data from Read Client which need to be used to form pixels for Inverse Scan mode.
///                                    * Normal dHub data order:
///                                    * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in LSB
///                                    * Inverse Scan dHub data order:
///                                    * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in MSB
///                                    * Following different data orders can be generated to be presented to first UPS in the pipe.
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      64b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITMAP16
#define h_BITMAP16 (){}

    #define     RA_BITMAP16_SEL                                0x0000

    #define     BA_BITMAP16_SEL_BIT_POS0                       0x0000
    #define     B16BITMAP16_SEL_BIT_POS0                       0x0000
    #define   LSb32BITMAP16_SEL_BIT_POS0                          0
    #define   LSb16BITMAP16_SEL_BIT_POS0                          0
    #define       bBITMAP16_SEL_BIT_POS0                       4
    #define   MSK32BITMAP16_SEL_BIT_POS0                          0x0000000F

    #define     BA_BITMAP16_SEL_BIT_POS1                       0x0000
    #define     B16BITMAP16_SEL_BIT_POS1                       0x0000
    #define   LSb32BITMAP16_SEL_BIT_POS1                          4
    #define   LSb16BITMAP16_SEL_BIT_POS1                          4
    #define       bBITMAP16_SEL_BIT_POS1                       4
    #define   MSK32BITMAP16_SEL_BIT_POS1                          0x000000F0

    #define     BA_BITMAP16_SEL_BIT_POS2                       0x0001
    #define     B16BITMAP16_SEL_BIT_POS2                       0x0000
    #define   LSb32BITMAP16_SEL_BIT_POS2                          8
    #define   LSb16BITMAP16_SEL_BIT_POS2                          8
    #define       bBITMAP16_SEL_BIT_POS2                       4
    #define   MSK32BITMAP16_SEL_BIT_POS2                          0x00000F00

    #define     BA_BITMAP16_SEL_BIT_POS3                       0x0001
    #define     B16BITMAP16_SEL_BIT_POS3                       0x0000
    #define   LSb32BITMAP16_SEL_BIT_POS3                          12
    #define   LSb16BITMAP16_SEL_BIT_POS3                          12
    #define       bBITMAP16_SEL_BIT_POS3                       4
    #define   MSK32BITMAP16_SEL_BIT_POS3                          0x0000F000

    #define     BA_BITMAP16_SEL_BIT_POS4                       0x0002
    #define     B16BITMAP16_SEL_BIT_POS4                       0x0002
    #define   LSb32BITMAP16_SEL_BIT_POS4                          16
    #define   LSb16BITMAP16_SEL_BIT_POS4                          0
    #define       bBITMAP16_SEL_BIT_POS4                       4
    #define   MSK32BITMAP16_SEL_BIT_POS4                          0x000F0000

    #define     BA_BITMAP16_SEL_BIT_POS5                       0x0002
    #define     B16BITMAP16_SEL_BIT_POS5                       0x0002
    #define   LSb32BITMAP16_SEL_BIT_POS5                          20
    #define   LSb16BITMAP16_SEL_BIT_POS5                          4
    #define       bBITMAP16_SEL_BIT_POS5                       4
    #define   MSK32BITMAP16_SEL_BIT_POS5                          0x00F00000

    #define     BA_BITMAP16_SEL_BIT_POS6                       0x0003
    #define     B16BITMAP16_SEL_BIT_POS6                       0x0002
    #define   LSb32BITMAP16_SEL_BIT_POS6                          24
    #define   LSb16BITMAP16_SEL_BIT_POS6                          8
    #define       bBITMAP16_SEL_BIT_POS6                       4
    #define   MSK32BITMAP16_SEL_BIT_POS6                          0x0F000000

    #define     BA_BITMAP16_SEL_BIT_POS7                       0x0003
    #define     B16BITMAP16_SEL_BIT_POS7                       0x0002
    #define   LSb32BITMAP16_SEL_BIT_POS7                          28
    #define   LSb16BITMAP16_SEL_BIT_POS7                          12
    #define       bBITMAP16_SEL_BIT_POS7                       4
    #define   MSK32BITMAP16_SEL_BIT_POS7                          0xF0000000

    #define     RA_BITMAP16_SEL1                               0x0004

    #define     BA_BITMAP16_SEL_BIT_POS8                       0x0004
    #define     B16BITMAP16_SEL_BIT_POS8                       0x0004
    #define   LSb32BITMAP16_SEL_BIT_POS8                          0
    #define   LSb16BITMAP16_SEL_BIT_POS8                          0
    #define       bBITMAP16_SEL_BIT_POS8                       4
    #define   MSK32BITMAP16_SEL_BIT_POS8                          0x0000000F

    #define     BA_BITMAP16_SEL_BIT_POS9                       0x0004
    #define     B16BITMAP16_SEL_BIT_POS9                       0x0004
    #define   LSb32BITMAP16_SEL_BIT_POS9                          4
    #define   LSb16BITMAP16_SEL_BIT_POS9                          4
    #define       bBITMAP16_SEL_BIT_POS9                       4
    #define   MSK32BITMAP16_SEL_BIT_POS9                          0x000000F0

    #define     BA_BITMAP16_SEL_BIT_POS10                      0x0005
    #define     B16BITMAP16_SEL_BIT_POS10                      0x0004
    #define   LSb32BITMAP16_SEL_BIT_POS10                         8
    #define   LSb16BITMAP16_SEL_BIT_POS10                         8
    #define       bBITMAP16_SEL_BIT_POS10                      4
    #define   MSK32BITMAP16_SEL_BIT_POS10                         0x00000F00

    #define     BA_BITMAP16_SEL_BIT_POS11                      0x0005
    #define     B16BITMAP16_SEL_BIT_POS11                      0x0004
    #define   LSb32BITMAP16_SEL_BIT_POS11                         12
    #define   LSb16BITMAP16_SEL_BIT_POS11                         12
    #define       bBITMAP16_SEL_BIT_POS11                      4
    #define   MSK32BITMAP16_SEL_BIT_POS11                         0x0000F000

    #define     BA_BITMAP16_SEL_BIT_POS12                      0x0006
    #define     B16BITMAP16_SEL_BIT_POS12                      0x0006
    #define   LSb32BITMAP16_SEL_BIT_POS12                         16
    #define   LSb16BITMAP16_SEL_BIT_POS12                         0
    #define       bBITMAP16_SEL_BIT_POS12                      4
    #define   MSK32BITMAP16_SEL_BIT_POS12                         0x000F0000

    #define     BA_BITMAP16_SEL_BIT_POS13                      0x0006
    #define     B16BITMAP16_SEL_BIT_POS13                      0x0006
    #define   LSb32BITMAP16_SEL_BIT_POS13                         20
    #define   LSb16BITMAP16_SEL_BIT_POS13                         4
    #define       bBITMAP16_SEL_BIT_POS13                      4
    #define   MSK32BITMAP16_SEL_BIT_POS13                         0x00F00000

    #define     BA_BITMAP16_SEL_BIT_POS14                      0x0007
    #define     B16BITMAP16_SEL_BIT_POS14                      0x0006
    #define   LSb32BITMAP16_SEL_BIT_POS14                         24
    #define   LSb16BITMAP16_SEL_BIT_POS14                         8
    #define       bBITMAP16_SEL_BIT_POS14                      4
    #define   MSK32BITMAP16_SEL_BIT_POS14                         0x0F000000

    #define     BA_BITMAP16_SEL_BIT_POS15                      0x0007
    #define     B16BITMAP16_SEL_BIT_POS15                      0x0006
    #define   LSb32BITMAP16_SEL_BIT_POS15                         28
    #define   LSb16BITMAP16_SEL_BIT_POS15                         12
    #define       bBITMAP16_SEL_BIT_POS15                      4
    #define   MSK32BITMAP16_SEL_BIT_POS15                         0xF0000000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITMAP16 {
    ///////////////////////////////////////////////////////////
    #define   GET32BITMAP16_SEL_BIT_POS0(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32BITMAP16_SEL_BIT_POS0(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16BITMAP16_SEL_BIT_POS0(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16BITMAP16_SEL_BIT_POS0(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP16_SEL_BIT_POS1(r32)                  _BFGET_(r32, 7, 4)
    #define   SET32BITMAP16_SEL_BIT_POS1(r32,v)                _BFSET_(r32, 7, 4,v)
    #define   GET16BITMAP16_SEL_BIT_POS1(r16)                  _BFGET_(r16, 7, 4)
    #define   SET16BITMAP16_SEL_BIT_POS1(r16,v)                _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP16_SEL_BIT_POS2(r32)                  _BFGET_(r32,11, 8)
    #define   SET32BITMAP16_SEL_BIT_POS2(r32,v)                _BFSET_(r32,11, 8,v)
    #define   GET16BITMAP16_SEL_BIT_POS2(r16)                  _BFGET_(r16,11, 8)
    #define   SET16BITMAP16_SEL_BIT_POS2(r16,v)                _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP16_SEL_BIT_POS3(r32)                  _BFGET_(r32,15,12)
    #define   SET32BITMAP16_SEL_BIT_POS3(r32,v)                _BFSET_(r32,15,12,v)
    #define   GET16BITMAP16_SEL_BIT_POS3(r16)                  _BFGET_(r16,15,12)
    #define   SET16BITMAP16_SEL_BIT_POS3(r16,v)                _BFSET_(r16,15,12,v)

    #define   GET32BITMAP16_SEL_BIT_POS4(r32)                  _BFGET_(r32,19,16)
    #define   SET32BITMAP16_SEL_BIT_POS4(r32,v)                _BFSET_(r32,19,16,v)
    #define   GET16BITMAP16_SEL_BIT_POS4(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16BITMAP16_SEL_BIT_POS4(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP16_SEL_BIT_POS5(r32)                  _BFGET_(r32,23,20)
    #define   SET32BITMAP16_SEL_BIT_POS5(r32,v)                _BFSET_(r32,23,20,v)
    #define   GET16BITMAP16_SEL_BIT_POS5(r16)                  _BFGET_(r16, 7, 4)
    #define   SET16BITMAP16_SEL_BIT_POS5(r16,v)                _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP16_SEL_BIT_POS6(r32)                  _BFGET_(r32,27,24)
    #define   SET32BITMAP16_SEL_BIT_POS6(r32,v)                _BFSET_(r32,27,24,v)
    #define   GET16BITMAP16_SEL_BIT_POS6(r16)                  _BFGET_(r16,11, 8)
    #define   SET16BITMAP16_SEL_BIT_POS6(r16,v)                _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP16_SEL_BIT_POS7(r32)                  _BFGET_(r32,31,28)
    #define   SET32BITMAP16_SEL_BIT_POS7(r32,v)                _BFSET_(r32,31,28,v)
    #define   GET16BITMAP16_SEL_BIT_POS7(r16)                  _BFGET_(r16,15,12)
    #define   SET16BITMAP16_SEL_BIT_POS7(r16,v)                _BFSET_(r16,15,12,v)

    #define     w32BITMAP16_SEL                                {\
            UNSG32 uSEL_BIT_POS0                               :  4;\
            UNSG32 uSEL_BIT_POS1                               :  4;\
            UNSG32 uSEL_BIT_POS2                               :  4;\
            UNSG32 uSEL_BIT_POS3                               :  4;\
            UNSG32 uSEL_BIT_POS4                               :  4;\
            UNSG32 uSEL_BIT_POS5                               :  4;\
            UNSG32 uSEL_BIT_POS6                               :  4;\
            UNSG32 uSEL_BIT_POS7                               :  4;\
          }
    union { UNSG32 u32BITMAP16_SEL;
            struct w32BITMAP16_SEL;
          };
    #define   GET32BITMAP16_SEL_BIT_POS8(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32BITMAP16_SEL_BIT_POS8(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16BITMAP16_SEL_BIT_POS8(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16BITMAP16_SEL_BIT_POS8(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP16_SEL_BIT_POS9(r32)                  _BFGET_(r32, 7, 4)
    #define   SET32BITMAP16_SEL_BIT_POS9(r32,v)                _BFSET_(r32, 7, 4,v)
    #define   GET16BITMAP16_SEL_BIT_POS9(r16)                  _BFGET_(r16, 7, 4)
    #define   SET16BITMAP16_SEL_BIT_POS9(r16,v)                _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP16_SEL_BIT_POS10(r32)                 _BFGET_(r32,11, 8)
    #define   SET32BITMAP16_SEL_BIT_POS10(r32,v)               _BFSET_(r32,11, 8,v)
    #define   GET16BITMAP16_SEL_BIT_POS10(r16)                 _BFGET_(r16,11, 8)
    #define   SET16BITMAP16_SEL_BIT_POS10(r16,v)               _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP16_SEL_BIT_POS11(r32)                 _BFGET_(r32,15,12)
    #define   SET32BITMAP16_SEL_BIT_POS11(r32,v)               _BFSET_(r32,15,12,v)
    #define   GET16BITMAP16_SEL_BIT_POS11(r16)                 _BFGET_(r16,15,12)
    #define   SET16BITMAP16_SEL_BIT_POS11(r16,v)               _BFSET_(r16,15,12,v)

    #define   GET32BITMAP16_SEL_BIT_POS12(r32)                 _BFGET_(r32,19,16)
    #define   SET32BITMAP16_SEL_BIT_POS12(r32,v)               _BFSET_(r32,19,16,v)
    #define   GET16BITMAP16_SEL_BIT_POS12(r16)                 _BFGET_(r16, 3, 0)
    #define   SET16BITMAP16_SEL_BIT_POS12(r16,v)               _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP16_SEL_BIT_POS13(r32)                 _BFGET_(r32,23,20)
    #define   SET32BITMAP16_SEL_BIT_POS13(r32,v)               _BFSET_(r32,23,20,v)
    #define   GET16BITMAP16_SEL_BIT_POS13(r16)                 _BFGET_(r16, 7, 4)
    #define   SET16BITMAP16_SEL_BIT_POS13(r16,v)               _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP16_SEL_BIT_POS14(r32)                 _BFGET_(r32,27,24)
    #define   SET32BITMAP16_SEL_BIT_POS14(r32,v)               _BFSET_(r32,27,24,v)
    #define   GET16BITMAP16_SEL_BIT_POS14(r16)                 _BFGET_(r16,11, 8)
    #define   SET16BITMAP16_SEL_BIT_POS14(r16,v)               _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP16_SEL_BIT_POS15(r32)                 _BFGET_(r32,31,28)
    #define   SET32BITMAP16_SEL_BIT_POS15(r32,v)               _BFSET_(r32,31,28,v)
    #define   GET16BITMAP16_SEL_BIT_POS15(r16)                 _BFGET_(r16,15,12)
    #define   SET16BITMAP16_SEL_BIT_POS15(r16,v)               _BFSET_(r16,15,12,v)

    #define     w32BITMAP16_SEL1                               {\
            UNSG32 uSEL_BIT_POS8                               :  4;\
            UNSG32 uSEL_BIT_POS9                               :  4;\
            UNSG32 uSEL_BIT_POS10                              :  4;\
            UNSG32 uSEL_BIT_POS11                              :  4;\
            UNSG32 uSEL_BIT_POS12                              :  4;\
            UNSG32 uSEL_BIT_POS13                              :  4;\
            UNSG32 uSEL_BIT_POS14                              :  4;\
            UNSG32 uSEL_BIT_POS15                              :  4;\
          }
    union { UNSG32 u32BITMAP16_SEL1;
            struct w32BITMAP16_SEL1;
          };
    ///////////////////////////////////////////////////////////
    } SIE_BITMAP16;

    typedef union  T32BITMAP16_SEL
          { UNSG32 u32;
            struct w32BITMAP16_SEL;
                 } T32BITMAP16_SEL;
    typedef union  T32BITMAP16_SEL1
          { UNSG32 u32;
            struct w32BITMAP16_SEL1;
                 } T32BITMAP16_SEL1;
    ///////////////////////////////////////////////////////////

    typedef union  TBITMAP16_SEL
          { UNSG32 u32[2];
            struct {
            struct w32BITMAP16_SEL;
            struct w32BITMAP16_SEL1;
                   };
                 } TBITMAP16_SEL;

    ///////////////////////////////////////////////////////////
     SIGN32 BITMAP16_drvrd(SIE_BITMAP16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITMAP16_drvwr(SIE_BITMAP16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITMAP16_reset(SIE_BITMAP16 *p);
     SIGN32 BITMAP16_cmp  (SIE_BITMAP16 *p, SIE_BITMAP16 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITMAP16_check(p,pie,pfx,hLOG) BITMAP16_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITMAP16_print(p,    pfx,hLOG) BITMAP16_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITMAP16
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE BITMAP12                                 (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 SEL                  (P)
///               %unsigned 4  BIT_POS0                  0x0
///               %unsigned 4  BIT_POS1                  0x1
///               %unsigned 4  BIT_POS2                  0x2
///               %unsigned 4  BIT_POS3                  0x3
///               %unsigned 4  BIT_POS4                  0x4
///               %unsigned 4  BIT_POS5                  0x5
///               %unsigned 4  BIT_POS6                  0x6
///               %unsigned 4  BIT_POS7                  0x7
///     # 0x00004 SEL1
///               %unsigned 4  BIT_POS8                  0x8
///               %unsigned 4  BIT_POS9                  0x9
///               %unsigned 4  BIT_POS10                 0xA
///               %unsigned 4  BIT_POS11                 0xB
///                                    ###
///                                    * Specifies mapping of new bit locations within 12 bit data from Read Client which need to be used to form pixels for Inverse Scan mode.
///                                    ###
///               %%        16         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       8B, bits:      48b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BITMAP12
#define h_BITMAP12 (){}

    #define     RA_BITMAP12_SEL                                0x0000

    #define     BA_BITMAP12_SEL_BIT_POS0                       0x0000
    #define     B16BITMAP12_SEL_BIT_POS0                       0x0000
    #define   LSb32BITMAP12_SEL_BIT_POS0                          0
    #define   LSb16BITMAP12_SEL_BIT_POS0                          0
    #define       bBITMAP12_SEL_BIT_POS0                       4
    #define   MSK32BITMAP12_SEL_BIT_POS0                          0x0000000F

    #define     BA_BITMAP12_SEL_BIT_POS1                       0x0000
    #define     B16BITMAP12_SEL_BIT_POS1                       0x0000
    #define   LSb32BITMAP12_SEL_BIT_POS1                          4
    #define   LSb16BITMAP12_SEL_BIT_POS1                          4
    #define       bBITMAP12_SEL_BIT_POS1                       4
    #define   MSK32BITMAP12_SEL_BIT_POS1                          0x000000F0

    #define     BA_BITMAP12_SEL_BIT_POS2                       0x0001
    #define     B16BITMAP12_SEL_BIT_POS2                       0x0000
    #define   LSb32BITMAP12_SEL_BIT_POS2                          8
    #define   LSb16BITMAP12_SEL_BIT_POS2                          8
    #define       bBITMAP12_SEL_BIT_POS2                       4
    #define   MSK32BITMAP12_SEL_BIT_POS2                          0x00000F00

    #define     BA_BITMAP12_SEL_BIT_POS3                       0x0001
    #define     B16BITMAP12_SEL_BIT_POS3                       0x0000
    #define   LSb32BITMAP12_SEL_BIT_POS3                          12
    #define   LSb16BITMAP12_SEL_BIT_POS3                          12
    #define       bBITMAP12_SEL_BIT_POS3                       4
    #define   MSK32BITMAP12_SEL_BIT_POS3                          0x0000F000

    #define     BA_BITMAP12_SEL_BIT_POS4                       0x0002
    #define     B16BITMAP12_SEL_BIT_POS4                       0x0002
    #define   LSb32BITMAP12_SEL_BIT_POS4                          16
    #define   LSb16BITMAP12_SEL_BIT_POS4                          0
    #define       bBITMAP12_SEL_BIT_POS4                       4
    #define   MSK32BITMAP12_SEL_BIT_POS4                          0x000F0000

    #define     BA_BITMAP12_SEL_BIT_POS5                       0x0002
    #define     B16BITMAP12_SEL_BIT_POS5                       0x0002
    #define   LSb32BITMAP12_SEL_BIT_POS5                          20
    #define   LSb16BITMAP12_SEL_BIT_POS5                          4
    #define       bBITMAP12_SEL_BIT_POS5                       4
    #define   MSK32BITMAP12_SEL_BIT_POS5                          0x00F00000

    #define     BA_BITMAP12_SEL_BIT_POS6                       0x0003
    #define     B16BITMAP12_SEL_BIT_POS6                       0x0002
    #define   LSb32BITMAP12_SEL_BIT_POS6                          24
    #define   LSb16BITMAP12_SEL_BIT_POS6                          8
    #define       bBITMAP12_SEL_BIT_POS6                       4
    #define   MSK32BITMAP12_SEL_BIT_POS6                          0x0F000000

    #define     BA_BITMAP12_SEL_BIT_POS7                       0x0003
    #define     B16BITMAP12_SEL_BIT_POS7                       0x0002
    #define   LSb32BITMAP12_SEL_BIT_POS7                          28
    #define   LSb16BITMAP12_SEL_BIT_POS7                          12
    #define       bBITMAP12_SEL_BIT_POS7                       4
    #define   MSK32BITMAP12_SEL_BIT_POS7                          0xF0000000

    #define     RA_BITMAP12_SEL1                               0x0004

    #define     BA_BITMAP12_SEL_BIT_POS8                       0x0004
    #define     B16BITMAP12_SEL_BIT_POS8                       0x0004
    #define   LSb32BITMAP12_SEL_BIT_POS8                          0
    #define   LSb16BITMAP12_SEL_BIT_POS8                          0
    #define       bBITMAP12_SEL_BIT_POS8                       4
    #define   MSK32BITMAP12_SEL_BIT_POS8                          0x0000000F

    #define     BA_BITMAP12_SEL_BIT_POS9                       0x0004
    #define     B16BITMAP12_SEL_BIT_POS9                       0x0004
    #define   LSb32BITMAP12_SEL_BIT_POS9                          4
    #define   LSb16BITMAP12_SEL_BIT_POS9                          4
    #define       bBITMAP12_SEL_BIT_POS9                       4
    #define   MSK32BITMAP12_SEL_BIT_POS9                          0x000000F0

    #define     BA_BITMAP12_SEL_BIT_POS10                      0x0005
    #define     B16BITMAP12_SEL_BIT_POS10                      0x0004
    #define   LSb32BITMAP12_SEL_BIT_POS10                         8
    #define   LSb16BITMAP12_SEL_BIT_POS10                         8
    #define       bBITMAP12_SEL_BIT_POS10                      4
    #define   MSK32BITMAP12_SEL_BIT_POS10                         0x00000F00

    #define     BA_BITMAP12_SEL_BIT_POS11                      0x0005
    #define     B16BITMAP12_SEL_BIT_POS11                      0x0004
    #define   LSb32BITMAP12_SEL_BIT_POS11                         12
    #define   LSb16BITMAP12_SEL_BIT_POS11                         12
    #define       bBITMAP12_SEL_BIT_POS11                      4
    #define   MSK32BITMAP12_SEL_BIT_POS11                         0x0000F000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BITMAP12 {
    ///////////////////////////////////////////////////////////
    #define   GET32BITMAP12_SEL_BIT_POS0(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32BITMAP12_SEL_BIT_POS0(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16BITMAP12_SEL_BIT_POS0(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16BITMAP12_SEL_BIT_POS0(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP12_SEL_BIT_POS1(r32)                  _BFGET_(r32, 7, 4)
    #define   SET32BITMAP12_SEL_BIT_POS1(r32,v)                _BFSET_(r32, 7, 4,v)
    #define   GET16BITMAP12_SEL_BIT_POS1(r16)                  _BFGET_(r16, 7, 4)
    #define   SET16BITMAP12_SEL_BIT_POS1(r16,v)                _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP12_SEL_BIT_POS2(r32)                  _BFGET_(r32,11, 8)
    #define   SET32BITMAP12_SEL_BIT_POS2(r32,v)                _BFSET_(r32,11, 8,v)
    #define   GET16BITMAP12_SEL_BIT_POS2(r16)                  _BFGET_(r16,11, 8)
    #define   SET16BITMAP12_SEL_BIT_POS2(r16,v)                _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP12_SEL_BIT_POS3(r32)                  _BFGET_(r32,15,12)
    #define   SET32BITMAP12_SEL_BIT_POS3(r32,v)                _BFSET_(r32,15,12,v)
    #define   GET16BITMAP12_SEL_BIT_POS3(r16)                  _BFGET_(r16,15,12)
    #define   SET16BITMAP12_SEL_BIT_POS3(r16,v)                _BFSET_(r16,15,12,v)

    #define   GET32BITMAP12_SEL_BIT_POS4(r32)                  _BFGET_(r32,19,16)
    #define   SET32BITMAP12_SEL_BIT_POS4(r32,v)                _BFSET_(r32,19,16,v)
    #define   GET16BITMAP12_SEL_BIT_POS4(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16BITMAP12_SEL_BIT_POS4(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP12_SEL_BIT_POS5(r32)                  _BFGET_(r32,23,20)
    #define   SET32BITMAP12_SEL_BIT_POS5(r32,v)                _BFSET_(r32,23,20,v)
    #define   GET16BITMAP12_SEL_BIT_POS5(r16)                  _BFGET_(r16, 7, 4)
    #define   SET16BITMAP12_SEL_BIT_POS5(r16,v)                _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP12_SEL_BIT_POS6(r32)                  _BFGET_(r32,27,24)
    #define   SET32BITMAP12_SEL_BIT_POS6(r32,v)                _BFSET_(r32,27,24,v)
    #define   GET16BITMAP12_SEL_BIT_POS6(r16)                  _BFGET_(r16,11, 8)
    #define   SET16BITMAP12_SEL_BIT_POS6(r16,v)                _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP12_SEL_BIT_POS7(r32)                  _BFGET_(r32,31,28)
    #define   SET32BITMAP12_SEL_BIT_POS7(r32,v)                _BFSET_(r32,31,28,v)
    #define   GET16BITMAP12_SEL_BIT_POS7(r16)                  _BFGET_(r16,15,12)
    #define   SET16BITMAP12_SEL_BIT_POS7(r16,v)                _BFSET_(r16,15,12,v)

    #define     w32BITMAP12_SEL                                {\
            UNSG32 uSEL_BIT_POS0                               :  4;\
            UNSG32 uSEL_BIT_POS1                               :  4;\
            UNSG32 uSEL_BIT_POS2                               :  4;\
            UNSG32 uSEL_BIT_POS3                               :  4;\
            UNSG32 uSEL_BIT_POS4                               :  4;\
            UNSG32 uSEL_BIT_POS5                               :  4;\
            UNSG32 uSEL_BIT_POS6                               :  4;\
            UNSG32 uSEL_BIT_POS7                               :  4;\
          }
    union { UNSG32 u32BITMAP12_SEL;
            struct w32BITMAP12_SEL;
          };
    #define   GET32BITMAP12_SEL_BIT_POS8(r32)                  _BFGET_(r32, 3, 0)
    #define   SET32BITMAP12_SEL_BIT_POS8(r32,v)                _BFSET_(r32, 3, 0,v)
    #define   GET16BITMAP12_SEL_BIT_POS8(r16)                  _BFGET_(r16, 3, 0)
    #define   SET16BITMAP12_SEL_BIT_POS8(r16,v)                _BFSET_(r16, 3, 0,v)

    #define   GET32BITMAP12_SEL_BIT_POS9(r32)                  _BFGET_(r32, 7, 4)
    #define   SET32BITMAP12_SEL_BIT_POS9(r32,v)                _BFSET_(r32, 7, 4,v)
    #define   GET16BITMAP12_SEL_BIT_POS9(r16)                  _BFGET_(r16, 7, 4)
    #define   SET16BITMAP12_SEL_BIT_POS9(r16,v)                _BFSET_(r16, 7, 4,v)

    #define   GET32BITMAP12_SEL_BIT_POS10(r32)                 _BFGET_(r32,11, 8)
    #define   SET32BITMAP12_SEL_BIT_POS10(r32,v)               _BFSET_(r32,11, 8,v)
    #define   GET16BITMAP12_SEL_BIT_POS10(r16)                 _BFGET_(r16,11, 8)
    #define   SET16BITMAP12_SEL_BIT_POS10(r16,v)               _BFSET_(r16,11, 8,v)

    #define   GET32BITMAP12_SEL_BIT_POS11(r32)                 _BFGET_(r32,15,12)
    #define   SET32BITMAP12_SEL_BIT_POS11(r32,v)               _BFSET_(r32,15,12,v)
    #define   GET16BITMAP12_SEL_BIT_POS11(r16)                 _BFGET_(r16,15,12)
    #define   SET16BITMAP12_SEL_BIT_POS11(r16,v)               _BFSET_(r16,15,12,v)

    #define     w32BITMAP12_SEL1                               {\
            UNSG32 uSEL_BIT_POS8                               :  4;\
            UNSG32 uSEL_BIT_POS9                               :  4;\
            UNSG32 uSEL_BIT_POS10                              :  4;\
            UNSG32 uSEL_BIT_POS11                              :  4;\
            UNSG32 RSVDx4_b16                                  : 16;\
          }
    union { UNSG32 u32BITMAP12_SEL1;
            struct w32BITMAP12_SEL1;
          };
    ///////////////////////////////////////////////////////////
    } SIE_BITMAP12;

    typedef union  T32BITMAP12_SEL
          { UNSG32 u32;
            struct w32BITMAP12_SEL;
                 } T32BITMAP12_SEL;
    typedef union  T32BITMAP12_SEL1
          { UNSG32 u32;
            struct w32BITMAP12_SEL1;
                 } T32BITMAP12_SEL1;
    ///////////////////////////////////////////////////////////

    typedef union  TBITMAP12_SEL
          { UNSG32 u32[2];
            struct {
            struct w32BITMAP12_SEL;
            struct w32BITMAP12_SEL1;
                   };
                 } TBITMAP12_SEL;

    ///////////////////////////////////////////////////////////
     SIGN32 BITMAP12_drvrd(SIE_BITMAP12 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BITMAP12_drvwr(SIE_BITMAP12 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BITMAP12_reset(SIE_BITMAP12 *p);
     SIGN32 BITMAP12_cmp  (SIE_BITMAP12 *p, SIE_BITMAP12 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BITMAP12_check(p,pie,pfx,hLOG) BITMAP12_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BITMAP12_print(p,    pfx,hLOG) BITMAP12_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BITMAP12
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE ReadClient              biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 Rd                   (P-)
///               %unsigned 1  start                     0x0
///                                    ###
///                                    * Start bit for the respective clients.
///                                    * 0 : No effect on hardware.
///                                    * 1 : start the client.
///                                    * The write 1 to this register is used to kick the hardware.
///                                    ###
///               %unsigned 1  clear                     0x0
///                                    ###
///                                    * 0 : Don't clear, normal state.
///                                    * 1 : Clear the asynchronous FIFO between the respective client and dHub.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00004 Word                 (P)
///               %unsigned 32 tot                       0x64
///                                    ###
///                                    * Specifies the total number of 128-bit words that have to be fetched from DDR for read Client. Should be programmed as:
///                                    * ceil( ohres*ovres*16 / 128 )
///                                    * Note : In case of resolution which is not integer multiple of 128, word total should be programmed as follows :
///                                    * For eg if ohres = 116, then (ohres*24/128) = 21.75. Then word total should be (22*ovres)
///                                    ###
///     @ 0x00008 NonStdRes            (P)
///               %unsigned 1  enable                    0x0
///                                    ###
///                                    * Enable for Read Client when resolution is not integer multiple of 16
///                                    ###
///               %unsigned 13 pixlineTot                0x64
///                                    ###
///                                    * Total number of pixels in a line (for Read Client)
///                                    ###
///               %unsigned 4  flushCnt                  0x5
///                                    ###
///                                    * Counter to determine the ready status of Read Client after end of line (only used when NonStdRes_enable = 1)
///                                    ###
///               %%        14         # Stuffing bits...
///     @ 0x0000C pack                 (P)
///               %unsigned 4  Sel                       0x0
///                                    ###
///                                    * PackSel for Read Client (For NNOB = 6)
///                                    * [0000] : 16 bit packing
///                                    * [0001] : 18 bit packing
///                                    * [0010] : 20 bit packing
///                                    * [0011] : 24 bit packing
///                                    * [0100] : 30 bit packing
///                                    * [0101] : 32 bit packing
///                                    * [0110] : 36 bit packing
///                                    * [0111] : 36 bit packing
///                                    * [1000] : 36 bit packing
///                                    ###
///               %%        28         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      56b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_ReadClient
#define h_ReadClient (){}

    #define     RA_ReadClient_Rd                               0x0000

    #define     BA_ReadClient_Rd_start                         0x0000
    #define     B16ReadClient_Rd_start                         0x0000
    #define   LSb32ReadClient_Rd_start                            0
    #define   LSb16ReadClient_Rd_start                            0
    #define       bReadClient_Rd_start                         1
    #define   MSK32ReadClient_Rd_start                            0x00000001

    #define     BA_ReadClient_Rd_clear                         0x0000
    #define     B16ReadClient_Rd_clear                         0x0000
    #define   LSb32ReadClient_Rd_clear                            1
    #define   LSb16ReadClient_Rd_clear                            1
    #define       bReadClient_Rd_clear                         1
    #define   MSK32ReadClient_Rd_clear                            0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_ReadClient_Word                             0x0004

    #define     BA_ReadClient_Word_tot                         0x0004
    #define     B16ReadClient_Word_tot                         0x0004
    #define   LSb32ReadClient_Word_tot                            0
    #define   LSb16ReadClient_Word_tot                            0
    #define       bReadClient_Word_tot                         32
    #define   MSK32ReadClient_Word_tot                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_ReadClient_NonStdRes                        0x0008

    #define     BA_ReadClient_NonStdRes_enable                 0x0008
    #define     B16ReadClient_NonStdRes_enable                 0x0008
    #define   LSb32ReadClient_NonStdRes_enable                    0
    #define   LSb16ReadClient_NonStdRes_enable                    0
    #define       bReadClient_NonStdRes_enable                 1
    #define   MSK32ReadClient_NonStdRes_enable                    0x00000001

    #define     BA_ReadClient_NonStdRes_pixlineTot             0x0008
    #define     B16ReadClient_NonStdRes_pixlineTot             0x0008
    #define   LSb32ReadClient_NonStdRes_pixlineTot                1
    #define   LSb16ReadClient_NonStdRes_pixlineTot                1
    #define       bReadClient_NonStdRes_pixlineTot             13
    #define   MSK32ReadClient_NonStdRes_pixlineTot                0x00003FFE

    #define     BA_ReadClient_NonStdRes_flushCnt               0x0009
    #define     B16ReadClient_NonStdRes_flushCnt               0x0008
    #define   LSb32ReadClient_NonStdRes_flushCnt                  14
    #define   LSb16ReadClient_NonStdRes_flushCnt                  14
    #define       bReadClient_NonStdRes_flushCnt               4
    #define   MSK32ReadClient_NonStdRes_flushCnt                  0x0003C000
    ///////////////////////////////////////////////////////////
    #define     RA_ReadClient_pack                             0x000C

    #define     BA_ReadClient_pack_Sel                         0x000C
    #define     B16ReadClient_pack_Sel                         0x000C
    #define   LSb32ReadClient_pack_Sel                            0
    #define   LSb16ReadClient_pack_Sel                            0
    #define       bReadClient_pack_Sel                         4
    #define   MSK32ReadClient_pack_Sel                            0x0000000F
    ///////////////////////////////////////////////////////////

    typedef struct SIE_ReadClient {
    ///////////////////////////////////////////////////////////
    #define   GET32ReadClient_Rd_start(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32ReadClient_Rd_start(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16ReadClient_Rd_start(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16ReadClient_Rd_start(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32ReadClient_Rd_clear(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32ReadClient_Rd_clear(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16ReadClient_Rd_clear(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16ReadClient_Rd_clear(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define     w32ReadClient_Rd                               {\
            UNSG32 uRd_start                                   :  1;\
            UNSG32 uRd_clear                                   :  1;\
            UNSG32 RSVDx0_b2                                   : 30;\
          }
    union { UNSG32 u32ReadClient_Rd;
            struct w32ReadClient_Rd;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32ReadClient_Word_tot(r32)                    _BFGET_(r32,31, 0)
    #define   SET32ReadClient_Word_tot(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32ReadClient_Word                             {\
            UNSG32 uWord_tot                                   : 32;\
          }
    union { UNSG32 u32ReadClient_Word;
            struct w32ReadClient_Word;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32ReadClient_NonStdRes_enable(r32)            _BFGET_(r32, 0, 0)
    #define   SET32ReadClient_NonStdRes_enable(r32,v)          _BFSET_(r32, 0, 0,v)
    #define   GET16ReadClient_NonStdRes_enable(r16)            _BFGET_(r16, 0, 0)
    #define   SET16ReadClient_NonStdRes_enable(r16,v)          _BFSET_(r16, 0, 0,v)

    #define   GET32ReadClient_NonStdRes_pixlineTot(r32)        _BFGET_(r32,13, 1)
    #define   SET32ReadClient_NonStdRes_pixlineTot(r32,v)      _BFSET_(r32,13, 1,v)
    #define   GET16ReadClient_NonStdRes_pixlineTot(r16)        _BFGET_(r16,13, 1)
    #define   SET16ReadClient_NonStdRes_pixlineTot(r16,v)      _BFSET_(r16,13, 1,v)

    #define   GET32ReadClient_NonStdRes_flushCnt(r32)          _BFGET_(r32,17,14)
    #define   SET32ReadClient_NonStdRes_flushCnt(r32,v)        _BFSET_(r32,17,14,v)

    #define     w32ReadClient_NonStdRes                        {\
            UNSG32 uNonStdRes_enable                           :  1;\
            UNSG32 uNonStdRes_pixlineTot                       : 13;\
            UNSG32 uNonStdRes_flushCnt                         :  4;\
            UNSG32 RSVDx8_b18                                  : 14;\
          }
    union { UNSG32 u32ReadClient_NonStdRes;
            struct w32ReadClient_NonStdRes;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32ReadClient_pack_Sel(r32)                    _BFGET_(r32, 3, 0)
    #define   SET32ReadClient_pack_Sel(r32,v)                  _BFSET_(r32, 3, 0,v)
    #define   GET16ReadClient_pack_Sel(r16)                    _BFGET_(r16, 3, 0)
    #define   SET16ReadClient_pack_Sel(r16,v)                  _BFSET_(r16, 3, 0,v)

    #define     w32ReadClient_pack                             {\
            UNSG32 upack_Sel                                   :  4;\
            UNSG32 RSVDxC_b4                                   : 28;\
          }
    union { UNSG32 u32ReadClient_pack;
            struct w32ReadClient_pack;
          };
    ///////////////////////////////////////////////////////////
    } SIE_ReadClient;

    typedef union  T32ReadClient_Rd
          { UNSG32 u32;
            struct w32ReadClient_Rd;
                 } T32ReadClient_Rd;
    typedef union  T32ReadClient_Word
          { UNSG32 u32;
            struct w32ReadClient_Word;
                 } T32ReadClient_Word;
    typedef union  T32ReadClient_NonStdRes
          { UNSG32 u32;
            struct w32ReadClient_NonStdRes;
                 } T32ReadClient_NonStdRes;
    typedef union  T32ReadClient_pack
          { UNSG32 u32;
            struct w32ReadClient_pack;
                 } T32ReadClient_pack;
    ///////////////////////////////////////////////////////////

    typedef union  TReadClient_Rd
          { UNSG32 u32[1];
            struct {
            struct w32ReadClient_Rd;
                   };
                 } TReadClient_Rd;
    typedef union  TReadClient_Word
          { UNSG32 u32[1];
            struct {
            struct w32ReadClient_Word;
                   };
                 } TReadClient_Word;
    typedef union  TReadClient_NonStdRes
          { UNSG32 u32[1];
            struct {
            struct w32ReadClient_NonStdRes;
                   };
                 } TReadClient_NonStdRes;
    typedef union  TReadClient_pack
          { UNSG32 u32[1];
            struct {
            struct w32ReadClient_pack;
                   };
                 } TReadClient_pack;

    ///////////////////////////////////////////////////////////
     SIGN32 ReadClient_drvrd(SIE_ReadClient *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 ReadClient_drvwr(SIE_ReadClient *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void ReadClient_reset(SIE_ReadClient *p);
     SIGN32 ReadClient_cmp  (SIE_ReadClient *p, SIE_ReadClient *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define ReadClient_check(p,pie,pfx,hLOG) ReadClient_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define ReadClient_print(p,    pfx,hLOG) ReadClient_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: ReadClient
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE WriteClient             biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 Wr                   (P-)
///               %unsigned 1  start                     0x0
///                                    ###
///                                    * Start bit for the respective clients.
///                                    * 0 : No effect on hardware.
///                                    * 1 : start the client.
///                                    * The write 1 to this register is used to kick the hardware.
///                                    ###
///               %unsigned 1  clear                     0x0
///                                    ###
///                                    * 0 : Don't clear, normal state.
///                                    * 1 : Clear the asynchronous FIFO between the respective client and dHub.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00004 pix                  (P)
///               %unsigned 32 tot                       0x64
///                                    ###
///                                    * Specifies the total number of pixels expected from input to write client. This is used to generate flush in Write client to write the partially formed 128-bit data (if any) to DDR.
///                                    * Should be programmed with (ovres*ohres).
///                                    ###
///     @ 0x00008 NonStdRes            (P)
///               %unsigned 1  enable                    0x0
///                                    ###
///                                    * Enable for Read Client when resolution is not integer multiple of 16
///                                    ###
///               %unsigned 13 pixlineTot                0x64
///                                    ###
///                                    * Total number of pixels in a line (for Write Client)
///                                    ###
///               %%        18         # Stuffing bits...
///     @ 0x0000C pack                 (P)
///               %unsigned 4  Sel                       0x0
///                                    ###
///                                    * PackSel for Write Client
///                                    * [0000] : 8 bit packing
///                                    * [0001] : 10 bit packing
///                                    * [0010] : 12 bit packing
///                                    * [0011] : 15 bit packing
///                                    * [0100] : 16 bit packing
///                                    * [0101] : 20 bit packing
///                                    * [0110] : 24 bit packing
///                                    * [0111] : 30 bit packing
///                                    * [1000] : 32 bit packing
///                                    ###
///               %%        28         # Stuffing bits...
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:      16B, bits:      52b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_WriteClient
#define h_WriteClient (){}

    #define     RA_WriteClient_Wr                              0x0000

    #define     BA_WriteClient_Wr_start                        0x0000
    #define     B16WriteClient_Wr_start                        0x0000
    #define   LSb32WriteClient_Wr_start                           0
    #define   LSb16WriteClient_Wr_start                           0
    #define       bWriteClient_Wr_start                        1
    #define   MSK32WriteClient_Wr_start                           0x00000001

    #define     BA_WriteClient_Wr_clear                        0x0000
    #define     B16WriteClient_Wr_clear                        0x0000
    #define   LSb32WriteClient_Wr_clear                           1
    #define   LSb16WriteClient_Wr_clear                           1
    #define       bWriteClient_Wr_clear                        1
    #define   MSK32WriteClient_Wr_clear                           0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_WriteClient_pix                             0x0004

    #define     BA_WriteClient_pix_tot                         0x0004
    #define     B16WriteClient_pix_tot                         0x0004
    #define   LSb32WriteClient_pix_tot                            0
    #define   LSb16WriteClient_pix_tot                            0
    #define       bWriteClient_pix_tot                         32
    #define   MSK32WriteClient_pix_tot                            0xFFFFFFFF
    ///////////////////////////////////////////////////////////
    #define     RA_WriteClient_NonStdRes                       0x0008

    #define     BA_WriteClient_NonStdRes_enable                0x0008
    #define     B16WriteClient_NonStdRes_enable                0x0008
    #define   LSb32WriteClient_NonStdRes_enable                   0
    #define   LSb16WriteClient_NonStdRes_enable                   0
    #define       bWriteClient_NonStdRes_enable                1
    #define   MSK32WriteClient_NonStdRes_enable                   0x00000001

    #define     BA_WriteClient_NonStdRes_pixlineTot            0x0008
    #define     B16WriteClient_NonStdRes_pixlineTot            0x0008
    #define   LSb32WriteClient_NonStdRes_pixlineTot               1
    #define   LSb16WriteClient_NonStdRes_pixlineTot               1
    #define       bWriteClient_NonStdRes_pixlineTot            13
    #define   MSK32WriteClient_NonStdRes_pixlineTot               0x00003FFE
    ///////////////////////////////////////////////////////////
    #define     RA_WriteClient_pack                            0x000C

    #define     BA_WriteClient_pack_Sel                        0x000C
    #define     B16WriteClient_pack_Sel                        0x000C
    #define   LSb32WriteClient_pack_Sel                           0
    #define   LSb16WriteClient_pack_Sel                           0
    #define       bWriteClient_pack_Sel                        4
    #define   MSK32WriteClient_pack_Sel                           0x0000000F
    ///////////////////////////////////////////////////////////

    typedef struct SIE_WriteClient {
    ///////////////////////////////////////////////////////////
    #define   GET32WriteClient_Wr_start(r32)                   _BFGET_(r32, 0, 0)
    #define   SET32WriteClient_Wr_start(r32,v)                 _BFSET_(r32, 0, 0,v)
    #define   GET16WriteClient_Wr_start(r16)                   _BFGET_(r16, 0, 0)
    #define   SET16WriteClient_Wr_start(r16,v)                 _BFSET_(r16, 0, 0,v)

    #define   GET32WriteClient_Wr_clear(r32)                   _BFGET_(r32, 1, 1)
    #define   SET32WriteClient_Wr_clear(r32,v)                 _BFSET_(r32, 1, 1,v)
    #define   GET16WriteClient_Wr_clear(r16)                   _BFGET_(r16, 1, 1)
    #define   SET16WriteClient_Wr_clear(r16,v)                 _BFSET_(r16, 1, 1,v)

    #define     w32WriteClient_Wr                              {\
            UNSG32 uWr_start                                   :  1;\
            UNSG32 uWr_clear                                   :  1;\
            UNSG32 RSVDx0_b2                                   : 30;\
          }
    union { UNSG32 u32WriteClient_Wr;
            struct w32WriteClient_Wr;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32WriteClient_pix_tot(r32)                    _BFGET_(r32,31, 0)
    #define   SET32WriteClient_pix_tot(r32,v)                  _BFSET_(r32,31, 0,v)

    #define     w32WriteClient_pix                             {\
            UNSG32 upix_tot                                    : 32;\
          }
    union { UNSG32 u32WriteClient_pix;
            struct w32WriteClient_pix;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32WriteClient_NonStdRes_enable(r32)           _BFGET_(r32, 0, 0)
    #define   SET32WriteClient_NonStdRes_enable(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16WriteClient_NonStdRes_enable(r16)           _BFGET_(r16, 0, 0)
    #define   SET16WriteClient_NonStdRes_enable(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32WriteClient_NonStdRes_pixlineTot(r32)       _BFGET_(r32,13, 1)
    #define   SET32WriteClient_NonStdRes_pixlineTot(r32,v)     _BFSET_(r32,13, 1,v)
    #define   GET16WriteClient_NonStdRes_pixlineTot(r16)       _BFGET_(r16,13, 1)
    #define   SET16WriteClient_NonStdRes_pixlineTot(r16,v)     _BFSET_(r16,13, 1,v)

    #define     w32WriteClient_NonStdRes                       {\
            UNSG32 uNonStdRes_enable                           :  1;\
            UNSG32 uNonStdRes_pixlineTot                       : 13;\
            UNSG32 RSVDx8_b14                                  : 18;\
          }
    union { UNSG32 u32WriteClient_NonStdRes;
            struct w32WriteClient_NonStdRes;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32WriteClient_pack_Sel(r32)                   _BFGET_(r32, 3, 0)
    #define   SET32WriteClient_pack_Sel(r32,v)                 _BFSET_(r32, 3, 0,v)
    #define   GET16WriteClient_pack_Sel(r16)                   _BFGET_(r16, 3, 0)
    #define   SET16WriteClient_pack_Sel(r16,v)                 _BFSET_(r16, 3, 0,v)

    #define     w32WriteClient_pack                            {\
            UNSG32 upack_Sel                                   :  4;\
            UNSG32 RSVDxC_b4                                   : 28;\
          }
    union { UNSG32 u32WriteClient_pack;
            struct w32WriteClient_pack;
          };
    ///////////////////////////////////////////////////////////
    } SIE_WriteClient;

    typedef union  T32WriteClient_Wr
          { UNSG32 u32;
            struct w32WriteClient_Wr;
                 } T32WriteClient_Wr;
    typedef union  T32WriteClient_pix
          { UNSG32 u32;
            struct w32WriteClient_pix;
                 } T32WriteClient_pix;
    typedef union  T32WriteClient_NonStdRes
          { UNSG32 u32;
            struct w32WriteClient_NonStdRes;
                 } T32WriteClient_NonStdRes;
    typedef union  T32WriteClient_pack
          { UNSG32 u32;
            struct w32WriteClient_pack;
                 } T32WriteClient_pack;
    ///////////////////////////////////////////////////////////

    typedef union  TWriteClient_Wr
          { UNSG32 u32[1];
            struct {
            struct w32WriteClient_Wr;
                   };
                 } TWriteClient_Wr;
    typedef union  TWriteClient_pix
          { UNSG32 u32[1];
            struct {
            struct w32WriteClient_pix;
                   };
                 } TWriteClient_pix;
    typedef union  TWriteClient_NonStdRes
          { UNSG32 u32[1];
            struct {
            struct w32WriteClient_NonStdRes;
                   };
                 } TWriteClient_NonStdRes;
    typedef union  TWriteClient_pack
          { UNSG32 u32[1];
            struct {
            struct w32WriteClient_pack;
                   };
                 } TWriteClient_pack;

    ///////////////////////////////////////////////////////////
     SIGN32 WriteClient_drvrd(SIE_WriteClient *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 WriteClient_drvwr(SIE_WriteClient *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void WriteClient_reset(SIE_WriteClient *p);
     SIGN32 WriteClient_cmp  (SIE_WriteClient *p, SIE_WriteClient *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define WriteClient_check(p,pie,pfx,hLOG) WriteClient_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define WriteClient_print(p,    pfx,hLOG) WriteClient_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: WriteClient
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE BETG                    biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 PL0
///               $TG_PL               PL0               REG
///                                    ###
///                                    * Plane 0 Related registers (for Base Plane)
///                                    ###
///     @ 0x00008                      (P)
///     # 0x00008 PL1
///               $TG_PL               PL1               REG
///                                    ###
///                                    * Plane 1 Related registers (for Main plane)
///                                    ###
///     @ 0x00010                      (P)
///     # 0x00010 PL2
///               $TG_PL               PL2               REG
///                                    ###
///                                    * Plane 2 Related registers (for PIP/Graphics1 Plane)
///                                    ###
///     @ 0x00018                      (P)
///     # 0x00018 PL3
///               $TG_PL               PL3               REG
///                                    ###
///                                    * Plane 3 Related registers (for Graphics2 Plane)
///                                    ###
///     @ 0x00020                      (P)
///     # 0x00020 PL4
///               $TG_PL               PL4               REG
///                                    ###
///                                    * Plane 4 Related registers (for FIX0 Plane)
///                                    ###
///     @ 0x00028                      (P)
///     # 0x00028 PL5
///               $TG_PL               PL5               REG
///                                    ###
///                                    * Plane 5 Related registers (for FIX1 Plane)
///                                    ###
///     @ 0x00030                      (P)
///     # 0x00030 PL6
///               $TG_PL               PL6               REG
///                                    ###
///                                    * Plane 6 Related registers (for FIX2 Plane)
///                                    ###
///     @ 0x00038                      (P)
///     # 0x00038 PL7
///               $TG_PL               PL7               REG
///                                    ###
///                                    * Plane 7 Related registers (for FIX3 Plane)
///                                    ###
///     @ 0x00040                      (P)
///     # 0x00040 PL8
///               $TG_PL               PL8               REG
///                                    ###
///                                    * Plane 8 Related registers (for overlay output read)
///                                    ###
///     @ 0x00048                      (P)
///     # 0x00048 PL1_CR
///               $TG_PL               PL1_CR            REG
///                                    ###
///                                    * Plane 1 Crop Related registers (for taking cropped input of Main Plane as Overlay Input)
///                                    ###
///     @ 0x00050                      (P)
///     # 0x00050 PL2_CR
///               $TG_PL               PL2_CR            REG
///                                    ###
///                                    * Plane 2 Crop Related registers (for taking cropped input of PIP/Graphics1 Plane as Overlay Input)
///                                    ###
///     @ 0x00058                      (P)
///     # 0x00058 PL3_CR
///               $TG_PL               PL3_CR            REG
///                                    ###
///                                    * Plane 3 Crop Related registers (for taking cropped input of Graphics-2 Plane as Overlay Input)
///                                    ###
///     @ 0x00060                      (P)
///     # 0x00060 PL4_CR
///               $TG_PL               PL4_CR            REG
///                                    ###
///                                    * Plane 4 Crop Related registers
///                                    ###
///     @ 0x00068                      (P)
///     # 0x00068 PL5_CR
///               $TG_PL               PL5_CR            REG
///                                    ###
///                                    * Plane 5 Crop Related registers
///                                    ###
///     @ 0x00070                      (P)
///     # 0x00070 PL6_CR
///               $TG_PL               PL6_CR            REG
///                                    ###
///                                    * Plane 6 Crop Related registers
///                                    ###
///     @ 0x00078                      (P)
///     # 0x00078 PL7_CR
///               $TG_PL               PL7_CR            REG
///                                    ###
///                                    * Plane 7 Crop Related registers
///                                    ###
///     @ 0x00080                      (P)
///     # 0x00080 PL8_CR
///               $TG_PL               PL8_CR            REG
///                                    ###
///                                    * Plane 8 Crop Related registers
///                                    ###
///     @ 0x00088                      (P)
///     # 0x00088 PL_FLD
///               $TG_PL               PL_FLD            REG
///                                    ###
///                                    * Field Related registers
///                                    ###
///     @ 0x00090                      (P)
///     # 0x00090 TG_PRG
///               $TG_PRG              TG_PRG            REG
///                                    ###
///                                    * Timing Generator programming registers
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     180B, bits:    1090b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_BETG
#define h_BETG (){}

    #define     RA_BETG_PL0                                    0x0000
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL1                                    0x0008
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL2                                    0x0010
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL3                                    0x0018
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL4                                    0x0020
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL5                                    0x0028
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL6                                    0x0030
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL7                                    0x0038
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL8                                    0x0040
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL1_CR                                 0x0048
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL2_CR                                 0x0050
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL3_CR                                 0x0058
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL4_CR                                 0x0060
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL5_CR                                 0x0068
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL6_CR                                 0x0070
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL7_CR                                 0x0078
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL8_CR                                 0x0080
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_PL_FLD                                 0x0088
    ///////////////////////////////////////////////////////////
    #define     RA_BETG_TG_PRG                                 0x0090
    ///////////////////////////////////////////////////////////

    typedef struct SIE_BETG {
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL0;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL1;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL2;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL3;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL4;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL5;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL6;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL7;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL8;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL1_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL2_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL3_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL4_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL5_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL6_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL7_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL8_CR;
    ///////////////////////////////////////////////////////////
              SIE_TG_PL                                        ie_PL_FLD;
    ///////////////////////////////////////////////////////////
              SIE_TG_PRG                                       ie_TG_PRG;
    ///////////////////////////////////////////////////////////
    } SIE_BETG;

    ///////////////////////////////////////////////////////////
     SIGN32 BETG_drvrd(SIE_BETG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 BETG_drvwr(SIE_BETG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void BETG_reset(SIE_BETG *p);
     SIGN32 BETG_cmp  (SIE_BETG *p, SIE_BETG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define BETG_check(p,pie,pfx,hLOG) BETG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define BETG_print(p,    pfx,hLOG) BETG_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: BETG
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE PIPE                                     (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000 CTRL0                (P-)
///               %unsigned 1  tg_start                  0x0
///                                    ###
///                                    * Start bit for tg
///                                    * 0 : No effect on hardware.
///                                    * 1 : start the client.
///                                    * The write 1 to this register is used to kick the hardware.
///                                    ###
///               %unsigned 1  tg_clear                  0x0
///                                    ###
///                                    * 0 : Don't clear, normal state.
///                                    * 1 : Clear tg
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00004 CTRL1                (P)
///               %unsigned 1  clken_ctrl0               0x1
///                                    ###
///                                    * Clock enable control for TG. Write 0 to make flow control independent of ready status from Read Client0
///                                    ###
///               %unsigned 1  clken_ctrl1               0x1
///                                    ###
///                                    * Clock enable control for TG. Write 0 to make flow control independent of ready status from Read Client1
///                                    ###
///               %unsigned 1  clken_ctrl2               0x1
///               %unsigned 1  clken_ctrl3               0x1
///               %unsigned 1  clken_ctrl4               0x1
///               %unsigned 1  bitMap_en                 0x0
///                                    ###
///                                    * Control bit to enable BITMAP
///                                    ###
///               %unsigned 1  crop_de_en                0x0
///                                    ###
///                                    * Enable for cropped de's to be used for cropped input read from Read Client's which is fed to DETILE-UPS420
///                                    * Write 1 to enable it. Default disabled.
///                                    ###
///               %unsigned 1  crop_de2_en               0x0
///                                    ###
///                                    * Enable for cropped de's to be used for cropped input support for 420-SemiPlanar Input for DETILE in PIP Plane .
///                                    * Note : crop_de_en bit should be high for this mode and DETILE TG to be programmed accordingly for Luma, Croma and DE (required to fetch data from Read Client)
///                                    * Write 1 to enable it. Default disabled.
///                                    ###
///               %unsigned 1  rdsel_422SP               0x0
///                                    ###
///                                    * Read select from read client (R0) for 422 SP format case
///                                    ###
///               %unsigned 1  rdsel_420SP               0x0
///                                    ###
///                                    * Read select from read client (R0/1) for 420 SP format case
///                                    ###
///               %unsigned 1  yuv420sp_2p1c             0x0
///                                    ###
///                                    * Switching between 2-pixels-1-cycle and 2-pixels-2-cycles modes for YUV420 (12-bit YcbCr 4:2:0)
///                                    * 1: Two pixels are read from PIPE and sent on DPI on every clock cycle
///                                    * 0: Two pixels are read from Client and sent on DPI on every alternate clock cycle
///                                    ###
///               %unsigned 1  eof_frst_mask             0x0
///               %unsigned 1  eof_frst_sel              0x0
///               %%        19         # Stuffing bits...
///     @ 0x00008 CTRL2                (P)
///               %unsigned 1  clken_rdcli0uf_all        0x0
///                                    ###
///                                    * TG Clock enable control in the event of Read Client #0 underflow. Underflow occurs when client gets exhausted of data.
///                                    * 0: Stops the TG Clock only if Read client #0 underflow event occurs during active period (~rdcli0_rdy && hde && vde)
///                                    * 1: Stops the TG clock if Read client #0 underflow event occurs during active or blanking period. No dependency on (hde && vde).
///                                    ###
///               %unsigned 1  clken_rdcli1uf_all        0x0
///                                    ###
///                                    * TG Clock enable control in the event of Read Client #1 underflow. Underflow occurs when client gets exhausted of data.
///                                    * 0x0: Stops the TG Clock only if Read client #1 underflow event occurs during active period (~rdcli1_rdy && hde && vde)
///                                    * 0x1: Stops the TG clock if Read client #1 underflow event occurs during active or blanking period. No dependency on (hde && vde).
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x0000C MTG                  (P)
///               %unsigned 1  cfg_rst                   0x0
///                                    ###
///                                    * Configurable reset to TG
///                                    ###
///               %unsigned 13 hcnt_rstval               0x0
///                                    ###
///                                    * H-Counter reset value
///                                    ###
///               %unsigned 12 vcnt_rstval               0x0
///                                    ###
///                                    * V-Counter reset value
///                                    ###
///               %unsigned 2  prog_line_dly             0x1
///                                    ###
///                                    * Programmable line delay
///                                    ###
///               %%        4          # Stuffing bits...
///     @ 0x00010 CTRL                 (P)
///               %unsigned 3  idata_ctrl                0x0
///                                    ###
///                                    * Input pixel data format
///                                    * [000]: 8b-YUV422, if rdSel_422SP=1
///                                    * RGB565-16bconfig1, if rdSel_422SP=0
///                                    * [001]: 10b-YUV422, , if rdSel_422SP=1
///                                    * RGB565-16bconfig2, if rdSel_422SP=0
///                                    * [010]: 12bYUV422, if rdSel_422SP=1
///                                    * 12bYUV420, if rdSel_420SP=1
///                                    * RGB656-16bconfig3, if rdSel_422SP=0 && rdSel_420SP=0
///                                    * [011]: RGB666-18bconfig1
///                                    * [100]: RGB666-18bconfig2
///                                    * [101]: RGB24
///                                    * [110]: RGB36
///                                    * [111]: RGB30
///                                    ###
///               %unsigned 1  sp_dwa_10b_normal_mode    0x0
///                                    ###
///                                    * 1: used for only sp DWA 10 bit format support in normal mode.
///                                    * 0: default path (other formats)
///                                    ###
///               %unsigned 1  sp_dwa_10b_inverse_mode   0x0
///                                    ###
///                                    * 1: used for only sp DWA 10 bit format support in inverse scan mode.
///                                    * 0: default path (other formats)
///                                    ###
///               %unsigned 1  cswap                     0x0
///                                    ###
///                                    * Component swap
///                                    ###
///               %unsigned 1  rdmain_initval0           0x0
///                                    ###
///                                    * Initiallization value for read Mask for MIPI Read Client's (420SP Cases)
///                                    ###
///               %unsigned 1  rdmain_initval1           0x1
///                                    ###
///                                    * Initiallization value for read Mask for MIPI Read Client's (420SP Cases)
///                                    ###
///               %unsigned 1  rd_mask_sftrst            0x0
///                                    ###
///                                    * Soft reset to initialize read mask. Write 1 to initialize read mask with rdmain_initval0
///                                    ###
///               %unsigned 1  yc_rdmask_sftrst          0x0
///                                    ###
///                                    * Soft reset to initialize read mask for alternate pixel. Write 1 to initialize read mask with 0
///                                    ###
///               %unsigned 1  bitmap40_bypass           0x0
///                                    ###
///                                    * Bypass bitmap40 control
///                                    ###
///               %unsigned 1  dpidataen_pol             0x0
///                                    ###
///                                    * dpidataen polarity control. Write 1 to make output port dpidataen active-low.
///                                    * THIS BIT SHOULD ONLY BE CONFIGURED BEFORE DSI HOST + DPHY POWER-UP PROGRAMMING SEQUENCE
///                                    ###
///               %unsigned 1  dpivsync_pol              0x0
///                                    ###
///                                    * dpivsync polarity control. Write 1 to make output port dpivsync active-low.
///                                    * THIS BIT SHOULD ONLY BE CONFIGURED BEFORE DSI HOST + DPHY POWER-UP PROGRAMMING SEQUENCE
///                                    ###
///               %unsigned 1  dpihsync_pol              0x0
///                                    ###
///                                    * dpihsync polarity polarity control. Write 1 to make output port dpihsync active-low.
///                                    * THIS BIT SHOULD ONLY BE CONFIGURED BEFORE DSI HOST + DPHY POWER-UP PROGRAMMING SEQUENCE
///                                    ###
///               %unsigned 1  dpishutd_pol              0x0
///                                    ###
///                                    * dpihshutd polarity control. Write 1 to make output port dpishutd active-low.
///                                    * THIS BIT SHOULD ONLY BE CONFIGURED BEFORE DSI HOST + DPHY POWER-UP PROGRAMMING SEQUENCE
///                                    ###
///               %unsigned 1  dpicolorm_pol             0x0
///                                    ###
///                                    * dpicolorm polarity control. Write 1 to make output port dpicolorm active-low.
///                                    * THIS BIT SHOULD ONLY BE CONFIGURED BEFORE DSI HOST + DPHY POWER-UP PROGRAMMING SEQUENCE
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00014 UFSTATUS             (WOC-)
///               %unsigned 1  rdcli0_uf                 0x0
///                                    ###
///                                    * This bit is set by hardware when underflow event occurs. Underflow event occurs when Read Client #0 gets exhausted of data. Underflow can occur during active period (hde && vde) or blanking period.
///                                    * Hardware sets this bit if underflow occurs in active period.
///                                    * Hardware sets this bit if underflow occurs in blanking period ONLY IF CTRL2_clken_rdcli0_uf_all bit is 1.
///                                    * This bit is cleared when software writes 1 to it.
///                                    ###
///               %unsigned 1  rdcli1_uf                 0x0
///                                    ###
///                                    * This bit is set by hardware when underflow event occurs. Underflow event occurs when Read Client #1 gets exhausted of data. Underflow can occur during active period (hde && vde) or blanking period.
///                                    * Hardware sets this bit if underflow occurs in active period.
///                                    * Hardware sets this bit if underflow occurs in blanking period ONLY IF CTRL2_clken_rdcli1_uf_all bit is 1.
///                                    * This bit is cleared when software writes 1 to it.
///                                    ###
///               %unsigned 1  dpite                     0x0
///               %%        29         # Stuffing bits...
///     @ 0x00018 DSI                  (P)
///               %unsigned 1  colormode                 0x0
///                                    ###
///                                    * Control Signal. It is used to switch between normal color and reduced color mode.
///                                    ###
///               %unsigned 1  shutdn                    0x0
///                                    ###
///                                    * Control Signal. It is used to shutdown the display.
///                                    ###
///               %unsigned 1  hw_updatecfg_on           0x0
///                                    ###
///                                    * Control Signal. This signal is used to indicate that the next frame will have new video configuration,through dpiupdatecfg hw pin
///                                    ###
///               %unsigned 1  hw_tear_effect_on         0x0
///                                    ###
///                                    * Control signal to activate Tearing Effect by Hardware
///                                    ###
///               %unsigned 1  force_pll_on              0x0
///                                    ###
///                                    * Control signal to pass force pll signal to AVPLL
///                                    ###
///               %unsigned 1  tear_request_pulse        0x0
///                                    ###
///                                    * activate Tearing Effect
///                                    ###
///               %unsigned 1  updatecfg_pulse           0x0
///                                    ###
///                                    * This signal is used to indicate that the next frame will have new video configuration
///                                    ###
///               %unsigned 1  edpi_mode                 0x0
///                                    ###
///                                    * Control to enable edpi mode for DSI
///                                    ###
///               %unsigned 1  tear_sftrst               0x0
///                                    ###
///                                    * Soft reset control to clear tear_wait -timeout
///                                    ###
///               %%        23         # Stuffing bits...
///     @ 0x0001C DPHY                 (P)
///               %unsigned 1  turn_disable_lane0        0x0
///                                    ###
///                                    * Disable turn around
///                                    ###
///               %unsigned 1  ftxstopmode_lane0         0x0
///                                    ###
///                                    * Force lane into tx mode and generate stop mode
///                                    ###
///               %unsigned 1  forcerxmode_lane0         0x0
///                                    ###
///                                    * Force lane into Rx mode and generate stop mode
///                                    ###
///               %unsigned 1  csr_cfgrstn               0x0
///                                    ###
///                                    * Reset input for CSR
///                                    ###
///               %%        28         # Stuffing bits...
///     @ 0x00020 INVSCAN              (P)
///               %unsigned 1  bitmap128_Rd0_en          0x0
///               %unsigned 1  bitmap128_Rd1_en          0x0
///                                    ###
///                                    * [1] : enable for H Inverse Scan.
///                                    * [0] : Default Value.
///                                    ###
///               %%        30         # Stuffing bits...
///     @ 0x00024 STATUS               (R-)
///               %unsigned 16 vcnt                      0x0
///                                    ###
///                                    * Vcount status for MIPI TG
///                                    ###
///               %%        16         # Stuffing bits...
///     @ 0x00028                      (P)
///     # 0x00028 TG
///               $BETG                TG                REG
///                                    ###
///                                    * TG programming
///                                    ###
///     @ 0x000DC                      (P)
///     # 0x000DC BITMAP40
///               $BITMAP40            BITMAP40          REG
///                                    ###
///                                    * Bit Map registers for bit mapping of Read Client output data
///                                    ###
///     @ 0x000FC                      (P)
///     # 0x000FC RdClient0
///               $ReadClient          RdClient0         REG
///                                    ###
///                                    * RdClient0 Programming
///                                    ###
///     @ 0x0010C                      (P)
///     # 0x0010C RdClient1
///               $ReadClient          RdClient1         REG
///                                    ###
///                                    * RdClient0 Programming
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     284B, bits:    1537b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_PIPE
#define h_PIPE (){}

    #define     RA_PIPE_CTRL0                                  0x0000

    #define     BA_PIPE_CTRL0_tg_start                         0x0000
    #define     B16PIPE_CTRL0_tg_start                         0x0000
    #define   LSb32PIPE_CTRL0_tg_start                            0
    #define   LSb16PIPE_CTRL0_tg_start                            0
    #define       bPIPE_CTRL0_tg_start                         1
    #define   MSK32PIPE_CTRL0_tg_start                            0x00000001

    #define     BA_PIPE_CTRL0_tg_clear                         0x0000
    #define     B16PIPE_CTRL0_tg_clear                         0x0000
    #define   LSb32PIPE_CTRL0_tg_clear                            1
    #define   LSb16PIPE_CTRL0_tg_clear                            1
    #define       bPIPE_CTRL0_tg_clear                         1
    #define   MSK32PIPE_CTRL0_tg_clear                            0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_CTRL1                                  0x0004

    #define     BA_PIPE_CTRL1_clken_ctrl0                      0x0004
    #define     B16PIPE_CTRL1_clken_ctrl0                      0x0004
    #define   LSb32PIPE_CTRL1_clken_ctrl0                         0
    #define   LSb16PIPE_CTRL1_clken_ctrl0                         0
    #define       bPIPE_CTRL1_clken_ctrl0                      1
    #define   MSK32PIPE_CTRL1_clken_ctrl0                         0x00000001

    #define     BA_PIPE_CTRL1_clken_ctrl1                      0x0004
    #define     B16PIPE_CTRL1_clken_ctrl1                      0x0004
    #define   LSb32PIPE_CTRL1_clken_ctrl1                         1
    #define   LSb16PIPE_CTRL1_clken_ctrl1                         1
    #define       bPIPE_CTRL1_clken_ctrl1                      1
    #define   MSK32PIPE_CTRL1_clken_ctrl1                         0x00000002

    #define     BA_PIPE_CTRL1_clken_ctrl2                      0x0004
    #define     B16PIPE_CTRL1_clken_ctrl2                      0x0004
    #define   LSb32PIPE_CTRL1_clken_ctrl2                         2
    #define   LSb16PIPE_CTRL1_clken_ctrl2                         2
    #define       bPIPE_CTRL1_clken_ctrl2                      1
    #define   MSK32PIPE_CTRL1_clken_ctrl2                         0x00000004

    #define     BA_PIPE_CTRL1_clken_ctrl3                      0x0004
    #define     B16PIPE_CTRL1_clken_ctrl3                      0x0004
    #define   LSb32PIPE_CTRL1_clken_ctrl3                         3
    #define   LSb16PIPE_CTRL1_clken_ctrl3                         3
    #define       bPIPE_CTRL1_clken_ctrl3                      1
    #define   MSK32PIPE_CTRL1_clken_ctrl3                         0x00000008

    #define     BA_PIPE_CTRL1_clken_ctrl4                      0x0004
    #define     B16PIPE_CTRL1_clken_ctrl4                      0x0004
    #define   LSb32PIPE_CTRL1_clken_ctrl4                         4
    #define   LSb16PIPE_CTRL1_clken_ctrl4                         4
    #define       bPIPE_CTRL1_clken_ctrl4                      1
    #define   MSK32PIPE_CTRL1_clken_ctrl4                         0x00000010

    #define     BA_PIPE_CTRL1_bitMap_en                        0x0004
    #define     B16PIPE_CTRL1_bitMap_en                        0x0004
    #define   LSb32PIPE_CTRL1_bitMap_en                           5
    #define   LSb16PIPE_CTRL1_bitMap_en                           5
    #define       bPIPE_CTRL1_bitMap_en                        1
    #define   MSK32PIPE_CTRL1_bitMap_en                           0x00000020

    #define     BA_PIPE_CTRL1_crop_de_en                       0x0004
    #define     B16PIPE_CTRL1_crop_de_en                       0x0004
    #define   LSb32PIPE_CTRL1_crop_de_en                          6
    #define   LSb16PIPE_CTRL1_crop_de_en                          6
    #define       bPIPE_CTRL1_crop_de_en                       1
    #define   MSK32PIPE_CTRL1_crop_de_en                          0x00000040

    #define     BA_PIPE_CTRL1_crop_de2_en                      0x0004
    #define     B16PIPE_CTRL1_crop_de2_en                      0x0004
    #define   LSb32PIPE_CTRL1_crop_de2_en                         7
    #define   LSb16PIPE_CTRL1_crop_de2_en                         7
    #define       bPIPE_CTRL1_crop_de2_en                      1
    #define   MSK32PIPE_CTRL1_crop_de2_en                         0x00000080

    #define     BA_PIPE_CTRL1_rdsel_422SP                      0x0005
    #define     B16PIPE_CTRL1_rdsel_422SP                      0x0004
    #define   LSb32PIPE_CTRL1_rdsel_422SP                         8
    #define   LSb16PIPE_CTRL1_rdsel_422SP                         8
    #define       bPIPE_CTRL1_rdsel_422SP                      1
    #define   MSK32PIPE_CTRL1_rdsel_422SP                         0x00000100

    #define     BA_PIPE_CTRL1_rdsel_420SP                      0x0005
    #define     B16PIPE_CTRL1_rdsel_420SP                      0x0004
    #define   LSb32PIPE_CTRL1_rdsel_420SP                         9
    #define   LSb16PIPE_CTRL1_rdsel_420SP                         9
    #define       bPIPE_CTRL1_rdsel_420SP                      1
    #define   MSK32PIPE_CTRL1_rdsel_420SP                         0x00000200

    #define     BA_PIPE_CTRL1_yuv420sp_2p1c                    0x0005
    #define     B16PIPE_CTRL1_yuv420sp_2p1c                    0x0004
    #define   LSb32PIPE_CTRL1_yuv420sp_2p1c                       10
    #define   LSb16PIPE_CTRL1_yuv420sp_2p1c                       10
    #define       bPIPE_CTRL1_yuv420sp_2p1c                    1
    #define   MSK32PIPE_CTRL1_yuv420sp_2p1c                       0x00000400

    #define     BA_PIPE_CTRL1_eof_frst_mask                    0x0005
    #define     B16PIPE_CTRL1_eof_frst_mask                    0x0004
    #define   LSb32PIPE_CTRL1_eof_frst_mask                       11
    #define   LSb16PIPE_CTRL1_eof_frst_mask                       11
    #define       bPIPE_CTRL1_eof_frst_mask                    1
    #define   MSK32PIPE_CTRL1_eof_frst_mask                       0x00000800

    #define     BA_PIPE_CTRL1_eof_frst_sel                     0x0005
    #define     B16PIPE_CTRL1_eof_frst_sel                     0x0004
    #define   LSb32PIPE_CTRL1_eof_frst_sel                        12
    #define   LSb16PIPE_CTRL1_eof_frst_sel                        12
    #define       bPIPE_CTRL1_eof_frst_sel                     1
    #define   MSK32PIPE_CTRL1_eof_frst_sel                        0x00001000
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_CTRL2                                  0x0008

    #define     BA_PIPE_CTRL2_clken_rdcli0uf_all               0x0008
    #define     B16PIPE_CTRL2_clken_rdcli0uf_all               0x0008
    #define   LSb32PIPE_CTRL2_clken_rdcli0uf_all                  0
    #define   LSb16PIPE_CTRL2_clken_rdcli0uf_all                  0
    #define       bPIPE_CTRL2_clken_rdcli0uf_all               1
    #define   MSK32PIPE_CTRL2_clken_rdcli0uf_all                  0x00000001

    #define     BA_PIPE_CTRL2_clken_rdcli1uf_all               0x0008
    #define     B16PIPE_CTRL2_clken_rdcli1uf_all               0x0008
    #define   LSb32PIPE_CTRL2_clken_rdcli1uf_all                  1
    #define   LSb16PIPE_CTRL2_clken_rdcli1uf_all                  1
    #define       bPIPE_CTRL2_clken_rdcli1uf_all               1
    #define   MSK32PIPE_CTRL2_clken_rdcli1uf_all                  0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_MTG                                    0x000C

    #define     BA_PIPE_MTG_cfg_rst                            0x000C
    #define     B16PIPE_MTG_cfg_rst                            0x000C
    #define   LSb32PIPE_MTG_cfg_rst                               0
    #define   LSb16PIPE_MTG_cfg_rst                               0
    #define       bPIPE_MTG_cfg_rst                            1
    #define   MSK32PIPE_MTG_cfg_rst                               0x00000001

    #define     BA_PIPE_MTG_hcnt_rstval                        0x000C
    #define     B16PIPE_MTG_hcnt_rstval                        0x000C
    #define   LSb32PIPE_MTG_hcnt_rstval                           1
    #define   LSb16PIPE_MTG_hcnt_rstval                           1
    #define       bPIPE_MTG_hcnt_rstval                        13
    #define   MSK32PIPE_MTG_hcnt_rstval                           0x00003FFE

    #define     BA_PIPE_MTG_vcnt_rstval                        0x000D
    #define     B16PIPE_MTG_vcnt_rstval                        0x000C
    #define   LSb32PIPE_MTG_vcnt_rstval                           14
    #define   LSb16PIPE_MTG_vcnt_rstval                           14
    #define       bPIPE_MTG_vcnt_rstval                        12
    #define   MSK32PIPE_MTG_vcnt_rstval                           0x03FFC000

    #define     BA_PIPE_MTG_prog_line_dly                      0x000F
    #define     B16PIPE_MTG_prog_line_dly                      0x000E
    #define   LSb32PIPE_MTG_prog_line_dly                         26
    #define   LSb16PIPE_MTG_prog_line_dly                         10
    #define       bPIPE_MTG_prog_line_dly                      2
    #define   MSK32PIPE_MTG_prog_line_dly                         0x0C000000
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_CTRL                                   0x0010

    #define     BA_PIPE_CTRL_idata_ctrl                        0x0010
    #define     B16PIPE_CTRL_idata_ctrl                        0x0010
    #define   LSb32PIPE_CTRL_idata_ctrl                           0
    #define   LSb16PIPE_CTRL_idata_ctrl                           0
    #define       bPIPE_CTRL_idata_ctrl                        3
    #define   MSK32PIPE_CTRL_idata_ctrl                           0x00000007

    #define     BA_PIPE_CTRL_sp_dwa_10b_normal_mode            0x0010
    #define     B16PIPE_CTRL_sp_dwa_10b_normal_mode            0x0010
    #define   LSb32PIPE_CTRL_sp_dwa_10b_normal_mode               3
    #define   LSb16PIPE_CTRL_sp_dwa_10b_normal_mode               3
    #define       bPIPE_CTRL_sp_dwa_10b_normal_mode            1
    #define   MSK32PIPE_CTRL_sp_dwa_10b_normal_mode               0x00000008

    #define     BA_PIPE_CTRL_sp_dwa_10b_inverse_mode           0x0010
    #define     B16PIPE_CTRL_sp_dwa_10b_inverse_mode           0x0010
    #define   LSb32PIPE_CTRL_sp_dwa_10b_inverse_mode              4
    #define   LSb16PIPE_CTRL_sp_dwa_10b_inverse_mode              4
    #define       bPIPE_CTRL_sp_dwa_10b_inverse_mode           1
    #define   MSK32PIPE_CTRL_sp_dwa_10b_inverse_mode              0x00000010

    #define     BA_PIPE_CTRL_cswap                             0x0010
    #define     B16PIPE_CTRL_cswap                             0x0010
    #define   LSb32PIPE_CTRL_cswap                                5
    #define   LSb16PIPE_CTRL_cswap                                5
    #define       bPIPE_CTRL_cswap                             1
    #define   MSK32PIPE_CTRL_cswap                                0x00000020

    #define     BA_PIPE_CTRL_rdmain_initval0                   0x0010
    #define     B16PIPE_CTRL_rdmain_initval0                   0x0010
    #define   LSb32PIPE_CTRL_rdmain_initval0                      6
    #define   LSb16PIPE_CTRL_rdmain_initval0                      6
    #define       bPIPE_CTRL_rdmain_initval0                   1
    #define   MSK32PIPE_CTRL_rdmain_initval0                      0x00000040

    #define     BA_PIPE_CTRL_rdmain_initval1                   0x0010
    #define     B16PIPE_CTRL_rdmain_initval1                   0x0010
    #define   LSb32PIPE_CTRL_rdmain_initval1                      7
    #define   LSb16PIPE_CTRL_rdmain_initval1                      7
    #define       bPIPE_CTRL_rdmain_initval1                   1
    #define   MSK32PIPE_CTRL_rdmain_initval1                      0x00000080

    #define     BA_PIPE_CTRL_rd_mask_sftrst                    0x0011
    #define     B16PIPE_CTRL_rd_mask_sftrst                    0x0010
    #define   LSb32PIPE_CTRL_rd_mask_sftrst                       8
    #define   LSb16PIPE_CTRL_rd_mask_sftrst                       8
    #define       bPIPE_CTRL_rd_mask_sftrst                    1
    #define   MSK32PIPE_CTRL_rd_mask_sftrst                       0x00000100

    #define     BA_PIPE_CTRL_yc_rdmask_sftrst                  0x0011
    #define     B16PIPE_CTRL_yc_rdmask_sftrst                  0x0010
    #define   LSb32PIPE_CTRL_yc_rdmask_sftrst                     9
    #define   LSb16PIPE_CTRL_yc_rdmask_sftrst                     9
    #define       bPIPE_CTRL_yc_rdmask_sftrst                  1
    #define   MSK32PIPE_CTRL_yc_rdmask_sftrst                     0x00000200

    #define     BA_PIPE_CTRL_bitmap40_bypass                   0x0011
    #define     B16PIPE_CTRL_bitmap40_bypass                   0x0010
    #define   LSb32PIPE_CTRL_bitmap40_bypass                      10
    #define   LSb16PIPE_CTRL_bitmap40_bypass                      10
    #define       bPIPE_CTRL_bitmap40_bypass                   1
    #define   MSK32PIPE_CTRL_bitmap40_bypass                      0x00000400

    #define     BA_PIPE_CTRL_dpidataen_pol                     0x0011
    #define     B16PIPE_CTRL_dpidataen_pol                     0x0010
    #define   LSb32PIPE_CTRL_dpidataen_pol                        11
    #define   LSb16PIPE_CTRL_dpidataen_pol                        11
    #define       bPIPE_CTRL_dpidataen_pol                     1
    #define   MSK32PIPE_CTRL_dpidataen_pol                        0x00000800

    #define     BA_PIPE_CTRL_dpivsync_pol                      0x0011
    #define     B16PIPE_CTRL_dpivsync_pol                      0x0010
    #define   LSb32PIPE_CTRL_dpivsync_pol                         12
    #define   LSb16PIPE_CTRL_dpivsync_pol                         12
    #define       bPIPE_CTRL_dpivsync_pol                      1
    #define   MSK32PIPE_CTRL_dpivsync_pol                         0x00001000

    #define     BA_PIPE_CTRL_dpihsync_pol                      0x0011
    #define     B16PIPE_CTRL_dpihsync_pol                      0x0010
    #define   LSb32PIPE_CTRL_dpihsync_pol                         13
    #define   LSb16PIPE_CTRL_dpihsync_pol                         13
    #define       bPIPE_CTRL_dpihsync_pol                      1
    #define   MSK32PIPE_CTRL_dpihsync_pol                         0x00002000

    #define     BA_PIPE_CTRL_dpishutd_pol                      0x0011
    #define     B16PIPE_CTRL_dpishutd_pol                      0x0010
    #define   LSb32PIPE_CTRL_dpishutd_pol                         14
    #define   LSb16PIPE_CTRL_dpishutd_pol                         14
    #define       bPIPE_CTRL_dpishutd_pol                      1
    #define   MSK32PIPE_CTRL_dpishutd_pol                         0x00004000

    #define     BA_PIPE_CTRL_dpicolorm_pol                     0x0011
    #define     B16PIPE_CTRL_dpicolorm_pol                     0x0010
    #define   LSb32PIPE_CTRL_dpicolorm_pol                        15
    #define   LSb16PIPE_CTRL_dpicolorm_pol                        15
    #define       bPIPE_CTRL_dpicolorm_pol                     1
    #define   MSK32PIPE_CTRL_dpicolorm_pol                        0x00008000
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_UFSTATUS                               0x0014

    #define     BA_PIPE_UFSTATUS_rdcli0_uf                     0x0014
    #define     B16PIPE_UFSTATUS_rdcli0_uf                     0x0014
    #define   LSb32PIPE_UFSTATUS_rdcli0_uf                        0
    #define   LSb16PIPE_UFSTATUS_rdcli0_uf                        0
    #define       bPIPE_UFSTATUS_rdcli0_uf                     1
    #define   MSK32PIPE_UFSTATUS_rdcli0_uf                        0x00000001

    #define     BA_PIPE_UFSTATUS_rdcli1_uf                     0x0014
    #define     B16PIPE_UFSTATUS_rdcli1_uf                     0x0014
    #define   LSb32PIPE_UFSTATUS_rdcli1_uf                        1
    #define   LSb16PIPE_UFSTATUS_rdcli1_uf                        1
    #define       bPIPE_UFSTATUS_rdcli1_uf                     1
    #define   MSK32PIPE_UFSTATUS_rdcli1_uf                        0x00000002

    #define     BA_PIPE_UFSTATUS_dpite                         0x0014
    #define     B16PIPE_UFSTATUS_dpite                         0x0014
    #define   LSb32PIPE_UFSTATUS_dpite                            2
    #define   LSb16PIPE_UFSTATUS_dpite                            2
    #define       bPIPE_UFSTATUS_dpite                         1
    #define   MSK32PIPE_UFSTATUS_dpite                            0x00000004
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_DSI                                    0x0018

    #define     BA_PIPE_DSI_colormode                          0x0018
    #define     B16PIPE_DSI_colormode                          0x0018
    #define   LSb32PIPE_DSI_colormode                             0
    #define   LSb16PIPE_DSI_colormode                             0
    #define       bPIPE_DSI_colormode                          1
    #define   MSK32PIPE_DSI_colormode                             0x00000001

    #define     BA_PIPE_DSI_shutdn                             0x0018
    #define     B16PIPE_DSI_shutdn                             0x0018
    #define   LSb32PIPE_DSI_shutdn                                1
    #define   LSb16PIPE_DSI_shutdn                                1
    #define       bPIPE_DSI_shutdn                             1
    #define   MSK32PIPE_DSI_shutdn                                0x00000002

    #define     BA_PIPE_DSI_hw_updatecfg_on                    0x0018
    #define     B16PIPE_DSI_hw_updatecfg_on                    0x0018
    #define   LSb32PIPE_DSI_hw_updatecfg_on                       2
    #define   LSb16PIPE_DSI_hw_updatecfg_on                       2
    #define       bPIPE_DSI_hw_updatecfg_on                    1
    #define   MSK32PIPE_DSI_hw_updatecfg_on                       0x00000004

    #define     BA_PIPE_DSI_hw_tear_effect_on                  0x0018
    #define     B16PIPE_DSI_hw_tear_effect_on                  0x0018
    #define   LSb32PIPE_DSI_hw_tear_effect_on                     3
    #define   LSb16PIPE_DSI_hw_tear_effect_on                     3
    #define       bPIPE_DSI_hw_tear_effect_on                  1
    #define   MSK32PIPE_DSI_hw_tear_effect_on                     0x00000008

    #define     BA_PIPE_DSI_force_pll_on                       0x0018
    #define     B16PIPE_DSI_force_pll_on                       0x0018
    #define   LSb32PIPE_DSI_force_pll_on                          4
    #define   LSb16PIPE_DSI_force_pll_on                          4
    #define       bPIPE_DSI_force_pll_on                       1
    #define   MSK32PIPE_DSI_force_pll_on                          0x00000010

    #define     BA_PIPE_DSI_tear_request_pulse                 0x0018
    #define     B16PIPE_DSI_tear_request_pulse                 0x0018
    #define   LSb32PIPE_DSI_tear_request_pulse                    5
    #define   LSb16PIPE_DSI_tear_request_pulse                    5
    #define       bPIPE_DSI_tear_request_pulse                 1
    #define   MSK32PIPE_DSI_tear_request_pulse                    0x00000020

    #define     BA_PIPE_DSI_updatecfg_pulse                    0x0018
    #define     B16PIPE_DSI_updatecfg_pulse                    0x0018
    #define   LSb32PIPE_DSI_updatecfg_pulse                       6
    #define   LSb16PIPE_DSI_updatecfg_pulse                       6
    #define       bPIPE_DSI_updatecfg_pulse                    1
    #define   MSK32PIPE_DSI_updatecfg_pulse                       0x00000040

    #define     BA_PIPE_DSI_edpi_mode                          0x0018
    #define     B16PIPE_DSI_edpi_mode                          0x0018
    #define   LSb32PIPE_DSI_edpi_mode                             7
    #define   LSb16PIPE_DSI_edpi_mode                             7
    #define       bPIPE_DSI_edpi_mode                          1
    #define   MSK32PIPE_DSI_edpi_mode                             0x00000080

    #define     BA_PIPE_DSI_tear_sftrst                        0x0019
    #define     B16PIPE_DSI_tear_sftrst                        0x0018
    #define   LSb32PIPE_DSI_tear_sftrst                           8
    #define   LSb16PIPE_DSI_tear_sftrst                           8
    #define       bPIPE_DSI_tear_sftrst                        1
    #define   MSK32PIPE_DSI_tear_sftrst                           0x00000100
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_DPHY                                   0x001C

    #define     BA_PIPE_DPHY_turn_disable_lane0                0x001C
    #define     B16PIPE_DPHY_turn_disable_lane0                0x001C
    #define   LSb32PIPE_DPHY_turn_disable_lane0                   0
    #define   LSb16PIPE_DPHY_turn_disable_lane0                   0
    #define       bPIPE_DPHY_turn_disable_lane0                1
    #define   MSK32PIPE_DPHY_turn_disable_lane0                   0x00000001

    #define     BA_PIPE_DPHY_ftxstopmode_lane0                 0x001C
    #define     B16PIPE_DPHY_ftxstopmode_lane0                 0x001C
    #define   LSb32PIPE_DPHY_ftxstopmode_lane0                    1
    #define   LSb16PIPE_DPHY_ftxstopmode_lane0                    1
    #define       bPIPE_DPHY_ftxstopmode_lane0                 1
    #define   MSK32PIPE_DPHY_ftxstopmode_lane0                    0x00000002

    #define     BA_PIPE_DPHY_forcerxmode_lane0                 0x001C
    #define     B16PIPE_DPHY_forcerxmode_lane0                 0x001C
    #define   LSb32PIPE_DPHY_forcerxmode_lane0                    2
    #define   LSb16PIPE_DPHY_forcerxmode_lane0                    2
    #define       bPIPE_DPHY_forcerxmode_lane0                 1
    #define   MSK32PIPE_DPHY_forcerxmode_lane0                    0x00000004

    #define     BA_PIPE_DPHY_csr_cfgrstn                       0x001C
    #define     B16PIPE_DPHY_csr_cfgrstn                       0x001C
    #define   LSb32PIPE_DPHY_csr_cfgrstn                          3
    #define   LSb16PIPE_DPHY_csr_cfgrstn                          3
    #define       bPIPE_DPHY_csr_cfgrstn                       1
    #define   MSK32PIPE_DPHY_csr_cfgrstn                          0x00000008
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_INVSCAN                                0x0020

    #define     BA_PIPE_INVSCAN_bitmap128_Rd0_en               0x0020
    #define     B16PIPE_INVSCAN_bitmap128_Rd0_en               0x0020
    #define   LSb32PIPE_INVSCAN_bitmap128_Rd0_en                  0
    #define   LSb16PIPE_INVSCAN_bitmap128_Rd0_en                  0
    #define       bPIPE_INVSCAN_bitmap128_Rd0_en               1
    #define   MSK32PIPE_INVSCAN_bitmap128_Rd0_en                  0x00000001

    #define     BA_PIPE_INVSCAN_bitmap128_Rd1_en               0x0020
    #define     B16PIPE_INVSCAN_bitmap128_Rd1_en               0x0020
    #define   LSb32PIPE_INVSCAN_bitmap128_Rd1_en                  1
    #define   LSb16PIPE_INVSCAN_bitmap128_Rd1_en                  1
    #define       bPIPE_INVSCAN_bitmap128_Rd1_en               1
    #define   MSK32PIPE_INVSCAN_bitmap128_Rd1_en                  0x00000002
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_STATUS                                 0x0024

    #define     BA_PIPE_STATUS_vcnt                            0x0024
    #define     B16PIPE_STATUS_vcnt                            0x0024
    #define   LSb32PIPE_STATUS_vcnt                               0
    #define   LSb16PIPE_STATUS_vcnt                               0
    #define       bPIPE_STATUS_vcnt                            16
    #define   MSK32PIPE_STATUS_vcnt                               0x0000FFFF
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_TG                                     0x0028
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_BITMAP40                               0x00DC
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_RdClient0                              0x00FC
    ///////////////////////////////////////////////////////////
    #define     RA_PIPE_RdClient1                              0x010C
    ///////////////////////////////////////////////////////////

    typedef struct SIE_PIPE {
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_CTRL0_tg_start(r32)                    _BFGET_(r32, 0, 0)
    #define   SET32PIPE_CTRL0_tg_start(r32,v)                  _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_CTRL0_tg_start(r16)                    _BFGET_(r16, 0, 0)
    #define   SET16PIPE_CTRL0_tg_start(r16,v)                  _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_CTRL0_tg_clear(r32)                    _BFGET_(r32, 1, 1)
    #define   SET32PIPE_CTRL0_tg_clear(r32,v)                  _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_CTRL0_tg_clear(r16)                    _BFGET_(r16, 1, 1)
    #define   SET16PIPE_CTRL0_tg_clear(r16,v)                  _BFSET_(r16, 1, 1,v)

    #define     w32PIPE_CTRL0                                  {\
            UNSG32 uCTRL0_tg_start                             :  1;\
            UNSG32 uCTRL0_tg_clear                             :  1;\
            UNSG32 RSVDx0_b2                                   : 30;\
          }
    union { UNSG32 u32PIPE_CTRL0;
            struct w32PIPE_CTRL0;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_CTRL1_clken_ctrl0(r32)                 _BFGET_(r32, 0, 0)
    #define   SET32PIPE_CTRL1_clken_ctrl0(r32,v)               _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_CTRL1_clken_ctrl0(r16)                 _BFGET_(r16, 0, 0)
    #define   SET16PIPE_CTRL1_clken_ctrl0(r16,v)               _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_CTRL1_clken_ctrl1(r32)                 _BFGET_(r32, 1, 1)
    #define   SET32PIPE_CTRL1_clken_ctrl1(r32,v)               _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_CTRL1_clken_ctrl1(r16)                 _BFGET_(r16, 1, 1)
    #define   SET16PIPE_CTRL1_clken_ctrl1(r16,v)               _BFSET_(r16, 1, 1,v)

    #define   GET32PIPE_CTRL1_clken_ctrl2(r32)                 _BFGET_(r32, 2, 2)
    #define   SET32PIPE_CTRL1_clken_ctrl2(r32,v)               _BFSET_(r32, 2, 2,v)
    #define   GET16PIPE_CTRL1_clken_ctrl2(r16)                 _BFGET_(r16, 2, 2)
    #define   SET16PIPE_CTRL1_clken_ctrl2(r16,v)               _BFSET_(r16, 2, 2,v)

    #define   GET32PIPE_CTRL1_clken_ctrl3(r32)                 _BFGET_(r32, 3, 3)
    #define   SET32PIPE_CTRL1_clken_ctrl3(r32,v)               _BFSET_(r32, 3, 3,v)
    #define   GET16PIPE_CTRL1_clken_ctrl3(r16)                 _BFGET_(r16, 3, 3)
    #define   SET16PIPE_CTRL1_clken_ctrl3(r16,v)               _BFSET_(r16, 3, 3,v)

    #define   GET32PIPE_CTRL1_clken_ctrl4(r32)                 _BFGET_(r32, 4, 4)
    #define   SET32PIPE_CTRL1_clken_ctrl4(r32,v)               _BFSET_(r32, 4, 4,v)
    #define   GET16PIPE_CTRL1_clken_ctrl4(r16)                 _BFGET_(r16, 4, 4)
    #define   SET16PIPE_CTRL1_clken_ctrl4(r16,v)               _BFSET_(r16, 4, 4,v)

    #define   GET32PIPE_CTRL1_bitMap_en(r32)                   _BFGET_(r32, 5, 5)
    #define   SET32PIPE_CTRL1_bitMap_en(r32,v)                 _BFSET_(r32, 5, 5,v)
    #define   GET16PIPE_CTRL1_bitMap_en(r16)                   _BFGET_(r16, 5, 5)
    #define   SET16PIPE_CTRL1_bitMap_en(r16,v)                 _BFSET_(r16, 5, 5,v)

    #define   GET32PIPE_CTRL1_crop_de_en(r32)                  _BFGET_(r32, 6, 6)
    #define   SET32PIPE_CTRL1_crop_de_en(r32,v)                _BFSET_(r32, 6, 6,v)
    #define   GET16PIPE_CTRL1_crop_de_en(r16)                  _BFGET_(r16, 6, 6)
    #define   SET16PIPE_CTRL1_crop_de_en(r16,v)                _BFSET_(r16, 6, 6,v)

    #define   GET32PIPE_CTRL1_crop_de2_en(r32)                 _BFGET_(r32, 7, 7)
    #define   SET32PIPE_CTRL1_crop_de2_en(r32,v)               _BFSET_(r32, 7, 7,v)
    #define   GET16PIPE_CTRL1_crop_de2_en(r16)                 _BFGET_(r16, 7, 7)
    #define   SET16PIPE_CTRL1_crop_de2_en(r16,v)               _BFSET_(r16, 7, 7,v)

    #define   GET32PIPE_CTRL1_rdsel_422SP(r32)                 _BFGET_(r32, 8, 8)
    #define   SET32PIPE_CTRL1_rdsel_422SP(r32,v)               _BFSET_(r32, 8, 8,v)
    #define   GET16PIPE_CTRL1_rdsel_422SP(r16)                 _BFGET_(r16, 8, 8)
    #define   SET16PIPE_CTRL1_rdsel_422SP(r16,v)               _BFSET_(r16, 8, 8,v)

    #define   GET32PIPE_CTRL1_rdsel_420SP(r32)                 _BFGET_(r32, 9, 9)
    #define   SET32PIPE_CTRL1_rdsel_420SP(r32,v)               _BFSET_(r32, 9, 9,v)
    #define   GET16PIPE_CTRL1_rdsel_420SP(r16)                 _BFGET_(r16, 9, 9)
    #define   SET16PIPE_CTRL1_rdsel_420SP(r16,v)               _BFSET_(r16, 9, 9,v)

    #define   GET32PIPE_CTRL1_yuv420sp_2p1c(r32)               _BFGET_(r32,10,10)
    #define   SET32PIPE_CTRL1_yuv420sp_2p1c(r32,v)             _BFSET_(r32,10,10,v)
    #define   GET16PIPE_CTRL1_yuv420sp_2p1c(r16)               _BFGET_(r16,10,10)
    #define   SET16PIPE_CTRL1_yuv420sp_2p1c(r16,v)             _BFSET_(r16,10,10,v)

    #define   GET32PIPE_CTRL1_eof_frst_mask(r32)               _BFGET_(r32,11,11)
    #define   SET32PIPE_CTRL1_eof_frst_mask(r32,v)             _BFSET_(r32,11,11,v)
    #define   GET16PIPE_CTRL1_eof_frst_mask(r16)               _BFGET_(r16,11,11)
    #define   SET16PIPE_CTRL1_eof_frst_mask(r16,v)             _BFSET_(r16,11,11,v)

    #define   GET32PIPE_CTRL1_eof_frst_sel(r32)                _BFGET_(r32,12,12)
    #define   SET32PIPE_CTRL1_eof_frst_sel(r32,v)              _BFSET_(r32,12,12,v)
    #define   GET16PIPE_CTRL1_eof_frst_sel(r16)                _BFGET_(r16,12,12)
    #define   SET16PIPE_CTRL1_eof_frst_sel(r16,v)              _BFSET_(r16,12,12,v)

    #define     w32PIPE_CTRL1                                  {\
            UNSG32 uCTRL1_clken_ctrl0                          :  1;\
            UNSG32 uCTRL1_clken_ctrl1                          :  1;\
            UNSG32 uCTRL1_clken_ctrl2                          :  1;\
            UNSG32 uCTRL1_clken_ctrl3                          :  1;\
            UNSG32 uCTRL1_clken_ctrl4                          :  1;\
            UNSG32 uCTRL1_bitMap_en                            :  1;\
            UNSG32 uCTRL1_crop_de_en                           :  1;\
            UNSG32 uCTRL1_crop_de2_en                          :  1;\
            UNSG32 uCTRL1_rdsel_422SP                          :  1;\
            UNSG32 uCTRL1_rdsel_420SP                          :  1;\
            UNSG32 uCTRL1_yuv420sp_2p1c                        :  1;\
            UNSG32 uCTRL1_eof_frst_mask                        :  1;\
            UNSG32 uCTRL1_eof_frst_sel                         :  1;\
            UNSG32 RSVDx4_b13                                  : 19;\
          }
    union { UNSG32 u32PIPE_CTRL1;
            struct w32PIPE_CTRL1;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_CTRL2_clken_rdcli0uf_all(r32)          _BFGET_(r32, 0, 0)
    #define   SET32PIPE_CTRL2_clken_rdcli0uf_all(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_CTRL2_clken_rdcli0uf_all(r16)          _BFGET_(r16, 0, 0)
    #define   SET16PIPE_CTRL2_clken_rdcli0uf_all(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_CTRL2_clken_rdcli1uf_all(r32)          _BFGET_(r32, 1, 1)
    #define   SET32PIPE_CTRL2_clken_rdcli1uf_all(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_CTRL2_clken_rdcli1uf_all(r16)          _BFGET_(r16, 1, 1)
    #define   SET16PIPE_CTRL2_clken_rdcli1uf_all(r16,v)        _BFSET_(r16, 1, 1,v)

    #define     w32PIPE_CTRL2                                  {\
            UNSG32 uCTRL2_clken_rdcli0uf_all                   :  1;\
            UNSG32 uCTRL2_clken_rdcli1uf_all                   :  1;\
            UNSG32 RSVDx8_b2                                   : 30;\
          }
    union { UNSG32 u32PIPE_CTRL2;
            struct w32PIPE_CTRL2;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_MTG_cfg_rst(r32)                       _BFGET_(r32, 0, 0)
    #define   SET32PIPE_MTG_cfg_rst(r32,v)                     _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_MTG_cfg_rst(r16)                       _BFGET_(r16, 0, 0)
    #define   SET16PIPE_MTG_cfg_rst(r16,v)                     _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_MTG_hcnt_rstval(r32)                   _BFGET_(r32,13, 1)
    #define   SET32PIPE_MTG_hcnt_rstval(r32,v)                 _BFSET_(r32,13, 1,v)
    #define   GET16PIPE_MTG_hcnt_rstval(r16)                   _BFGET_(r16,13, 1)
    #define   SET16PIPE_MTG_hcnt_rstval(r16,v)                 _BFSET_(r16,13, 1,v)

    #define   GET32PIPE_MTG_vcnt_rstval(r32)                   _BFGET_(r32,25,14)
    #define   SET32PIPE_MTG_vcnt_rstval(r32,v)                 _BFSET_(r32,25,14,v)

    #define   GET32PIPE_MTG_prog_line_dly(r32)                 _BFGET_(r32,27,26)
    #define   SET32PIPE_MTG_prog_line_dly(r32,v)               _BFSET_(r32,27,26,v)
    #define   GET16PIPE_MTG_prog_line_dly(r16)                 _BFGET_(r16,11,10)
    #define   SET16PIPE_MTG_prog_line_dly(r16,v)               _BFSET_(r16,11,10,v)

    #define     w32PIPE_MTG                                    {\
            UNSG32 uMTG_cfg_rst                                :  1;\
            UNSG32 uMTG_hcnt_rstval                            : 13;\
            UNSG32 uMTG_vcnt_rstval                            : 12;\
            UNSG32 uMTG_prog_line_dly                          :  2;\
            UNSG32 RSVDxC_b28                                  :  4;\
          }
    union { UNSG32 u32PIPE_MTG;
            struct w32PIPE_MTG;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_CTRL_idata_ctrl(r32)                   _BFGET_(r32, 2, 0)
    #define   SET32PIPE_CTRL_idata_ctrl(r32,v)                 _BFSET_(r32, 2, 0,v)
    #define   GET16PIPE_CTRL_idata_ctrl(r16)                   _BFGET_(r16, 2, 0)
    #define   SET16PIPE_CTRL_idata_ctrl(r16,v)                 _BFSET_(r16, 2, 0,v)

    #define   GET32PIPE_CTRL_sp_dwa_10b_normal_mode(r32)       _BFGET_(r32, 3, 3)
    #define   SET32PIPE_CTRL_sp_dwa_10b_normal_mode(r32,v)     _BFSET_(r32, 3, 3,v)
    #define   GET16PIPE_CTRL_sp_dwa_10b_normal_mode(r16)       _BFGET_(r16, 3, 3)
    #define   SET16PIPE_CTRL_sp_dwa_10b_normal_mode(r16,v)     _BFSET_(r16, 3, 3,v)

    #define   GET32PIPE_CTRL_sp_dwa_10b_inverse_mode(r32)      _BFGET_(r32, 4, 4)
    #define   SET32PIPE_CTRL_sp_dwa_10b_inverse_mode(r32,v)    _BFSET_(r32, 4, 4,v)
    #define   GET16PIPE_CTRL_sp_dwa_10b_inverse_mode(r16)      _BFGET_(r16, 4, 4)
    #define   SET16PIPE_CTRL_sp_dwa_10b_inverse_mode(r16,v)    _BFSET_(r16, 4, 4,v)

    #define   GET32PIPE_CTRL_cswap(r32)                        _BFGET_(r32, 5, 5)
    #define   SET32PIPE_CTRL_cswap(r32,v)                      _BFSET_(r32, 5, 5,v)
    #define   GET16PIPE_CTRL_cswap(r16)                        _BFGET_(r16, 5, 5)
    #define   SET16PIPE_CTRL_cswap(r16,v)                      _BFSET_(r16, 5, 5,v)

    #define   GET32PIPE_CTRL_rdmain_initval0(r32)              _BFGET_(r32, 6, 6)
    #define   SET32PIPE_CTRL_rdmain_initval0(r32,v)            _BFSET_(r32, 6, 6,v)
    #define   GET16PIPE_CTRL_rdmain_initval0(r16)              _BFGET_(r16, 6, 6)
    #define   SET16PIPE_CTRL_rdmain_initval0(r16,v)            _BFSET_(r16, 6, 6,v)

    #define   GET32PIPE_CTRL_rdmain_initval1(r32)              _BFGET_(r32, 7, 7)
    #define   SET32PIPE_CTRL_rdmain_initval1(r32,v)            _BFSET_(r32, 7, 7,v)
    #define   GET16PIPE_CTRL_rdmain_initval1(r16)              _BFGET_(r16, 7, 7)
    #define   SET16PIPE_CTRL_rdmain_initval1(r16,v)            _BFSET_(r16, 7, 7,v)

    #define   GET32PIPE_CTRL_rd_mask_sftrst(r32)               _BFGET_(r32, 8, 8)
    #define   SET32PIPE_CTRL_rd_mask_sftrst(r32,v)             _BFSET_(r32, 8, 8,v)
    #define   GET16PIPE_CTRL_rd_mask_sftrst(r16)               _BFGET_(r16, 8, 8)
    #define   SET16PIPE_CTRL_rd_mask_sftrst(r16,v)             _BFSET_(r16, 8, 8,v)

    #define   GET32PIPE_CTRL_yc_rdmask_sftrst(r32)             _BFGET_(r32, 9, 9)
    #define   SET32PIPE_CTRL_yc_rdmask_sftrst(r32,v)           _BFSET_(r32, 9, 9,v)
    #define   GET16PIPE_CTRL_yc_rdmask_sftrst(r16)             _BFGET_(r16, 9, 9)
    #define   SET16PIPE_CTRL_yc_rdmask_sftrst(r16,v)           _BFSET_(r16, 9, 9,v)

    #define   GET32PIPE_CTRL_bitmap40_bypass(r32)              _BFGET_(r32,10,10)
    #define   SET32PIPE_CTRL_bitmap40_bypass(r32,v)            _BFSET_(r32,10,10,v)
    #define   GET16PIPE_CTRL_bitmap40_bypass(r16)              _BFGET_(r16,10,10)
    #define   SET16PIPE_CTRL_bitmap40_bypass(r16,v)            _BFSET_(r16,10,10,v)

    #define   GET32PIPE_CTRL_dpidataen_pol(r32)                _BFGET_(r32,11,11)
    #define   SET32PIPE_CTRL_dpidataen_pol(r32,v)              _BFSET_(r32,11,11,v)
    #define   GET16PIPE_CTRL_dpidataen_pol(r16)                _BFGET_(r16,11,11)
    #define   SET16PIPE_CTRL_dpidataen_pol(r16,v)              _BFSET_(r16,11,11,v)

    #define   GET32PIPE_CTRL_dpivsync_pol(r32)                 _BFGET_(r32,12,12)
    #define   SET32PIPE_CTRL_dpivsync_pol(r32,v)               _BFSET_(r32,12,12,v)
    #define   GET16PIPE_CTRL_dpivsync_pol(r16)                 _BFGET_(r16,12,12)
    #define   SET16PIPE_CTRL_dpivsync_pol(r16,v)               _BFSET_(r16,12,12,v)

    #define   GET32PIPE_CTRL_dpihsync_pol(r32)                 _BFGET_(r32,13,13)
    #define   SET32PIPE_CTRL_dpihsync_pol(r32,v)               _BFSET_(r32,13,13,v)
    #define   GET16PIPE_CTRL_dpihsync_pol(r16)                 _BFGET_(r16,13,13)
    #define   SET16PIPE_CTRL_dpihsync_pol(r16,v)               _BFSET_(r16,13,13,v)

    #define   GET32PIPE_CTRL_dpishutd_pol(r32)                 _BFGET_(r32,14,14)
    #define   SET32PIPE_CTRL_dpishutd_pol(r32,v)               _BFSET_(r32,14,14,v)
    #define   GET16PIPE_CTRL_dpishutd_pol(r16)                 _BFGET_(r16,14,14)
    #define   SET16PIPE_CTRL_dpishutd_pol(r16,v)               _BFSET_(r16,14,14,v)

    #define   GET32PIPE_CTRL_dpicolorm_pol(r32)                _BFGET_(r32,15,15)
    #define   SET32PIPE_CTRL_dpicolorm_pol(r32,v)              _BFSET_(r32,15,15,v)
    #define   GET16PIPE_CTRL_dpicolorm_pol(r16)                _BFGET_(r16,15,15)
    #define   SET16PIPE_CTRL_dpicolorm_pol(r16,v)              _BFSET_(r16,15,15,v)

    #define     w32PIPE_CTRL                                   {\
            UNSG32 uCTRL_idata_ctrl                            :  3;\
            UNSG32 uCTRL_sp_dwa_10b_normal_mode                :  1;\
            UNSG32 uCTRL_sp_dwa_10b_inverse_mode               :  1;\
            UNSG32 uCTRL_cswap                                 :  1;\
            UNSG32 uCTRL_rdmain_initval0                       :  1;\
            UNSG32 uCTRL_rdmain_initval1                       :  1;\
            UNSG32 uCTRL_rd_mask_sftrst                        :  1;\
            UNSG32 uCTRL_yc_rdmask_sftrst                      :  1;\
            UNSG32 uCTRL_bitmap40_bypass                       :  1;\
            UNSG32 uCTRL_dpidataen_pol                         :  1;\
            UNSG32 uCTRL_dpivsync_pol                          :  1;\
            UNSG32 uCTRL_dpihsync_pol                          :  1;\
            UNSG32 uCTRL_dpishutd_pol                          :  1;\
            UNSG32 uCTRL_dpicolorm_pol                         :  1;\
            UNSG32 RSVDx10_b16                                 : 16;\
          }
    union { UNSG32 u32PIPE_CTRL;
            struct w32PIPE_CTRL;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_UFSTATUS_rdcli0_uf(r32)                _BFGET_(r32, 0, 0)
    #define   SET32PIPE_UFSTATUS_rdcli0_uf(r32,v)              _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_UFSTATUS_rdcli0_uf(r16)                _BFGET_(r16, 0, 0)
    #define   SET16PIPE_UFSTATUS_rdcli0_uf(r16,v)              _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_UFSTATUS_rdcli1_uf(r32)                _BFGET_(r32, 1, 1)
    #define   SET32PIPE_UFSTATUS_rdcli1_uf(r32,v)              _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_UFSTATUS_rdcli1_uf(r16)                _BFGET_(r16, 1, 1)
    #define   SET16PIPE_UFSTATUS_rdcli1_uf(r16,v)              _BFSET_(r16, 1, 1,v)

    #define   GET32PIPE_UFSTATUS_dpite(r32)                    _BFGET_(r32, 2, 2)
    #define   SET32PIPE_UFSTATUS_dpite(r32,v)                  _BFSET_(r32, 2, 2,v)
    #define   GET16PIPE_UFSTATUS_dpite(r16)                    _BFGET_(r16, 2, 2)
    #define   SET16PIPE_UFSTATUS_dpite(r16,v)                  _BFSET_(r16, 2, 2,v)

    #define     w32PIPE_UFSTATUS                               {\
            UNSG32 uUFSTATUS_rdcli0_uf                         :  1;\
            UNSG32 uUFSTATUS_rdcli1_uf                         :  1;\
            UNSG32 uUFSTATUS_dpite                             :  1;\
            UNSG32 RSVDx14_b3                                  : 29;\
          }
    union { UNSG32 u32PIPE_UFSTATUS;
            struct w32PIPE_UFSTATUS;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_DSI_colormode(r32)                     _BFGET_(r32, 0, 0)
    #define   SET32PIPE_DSI_colormode(r32,v)                   _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_DSI_colormode(r16)                     _BFGET_(r16, 0, 0)
    #define   SET16PIPE_DSI_colormode(r16,v)                   _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_DSI_shutdn(r32)                        _BFGET_(r32, 1, 1)
    #define   SET32PIPE_DSI_shutdn(r32,v)                      _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_DSI_shutdn(r16)                        _BFGET_(r16, 1, 1)
    #define   SET16PIPE_DSI_shutdn(r16,v)                      _BFSET_(r16, 1, 1,v)

    #define   GET32PIPE_DSI_hw_updatecfg_on(r32)               _BFGET_(r32, 2, 2)
    #define   SET32PIPE_DSI_hw_updatecfg_on(r32,v)             _BFSET_(r32, 2, 2,v)
    #define   GET16PIPE_DSI_hw_updatecfg_on(r16)               _BFGET_(r16, 2, 2)
    #define   SET16PIPE_DSI_hw_updatecfg_on(r16,v)             _BFSET_(r16, 2, 2,v)

    #define   GET32PIPE_DSI_hw_tear_effect_on(r32)             _BFGET_(r32, 3, 3)
    #define   SET32PIPE_DSI_hw_tear_effect_on(r32,v)           _BFSET_(r32, 3, 3,v)
    #define   GET16PIPE_DSI_hw_tear_effect_on(r16)             _BFGET_(r16, 3, 3)
    #define   SET16PIPE_DSI_hw_tear_effect_on(r16,v)           _BFSET_(r16, 3, 3,v)

    #define   GET32PIPE_DSI_force_pll_on(r32)                  _BFGET_(r32, 4, 4)
    #define   SET32PIPE_DSI_force_pll_on(r32,v)                _BFSET_(r32, 4, 4,v)
    #define   GET16PIPE_DSI_force_pll_on(r16)                  _BFGET_(r16, 4, 4)
    #define   SET16PIPE_DSI_force_pll_on(r16,v)                _BFSET_(r16, 4, 4,v)

    #define   GET32PIPE_DSI_tear_request_pulse(r32)            _BFGET_(r32, 5, 5)
    #define   SET32PIPE_DSI_tear_request_pulse(r32,v)          _BFSET_(r32, 5, 5,v)
    #define   GET16PIPE_DSI_tear_request_pulse(r16)            _BFGET_(r16, 5, 5)
    #define   SET16PIPE_DSI_tear_request_pulse(r16,v)          _BFSET_(r16, 5, 5,v)

    #define   GET32PIPE_DSI_updatecfg_pulse(r32)               _BFGET_(r32, 6, 6)
    #define   SET32PIPE_DSI_updatecfg_pulse(r32,v)             _BFSET_(r32, 6, 6,v)
    #define   GET16PIPE_DSI_updatecfg_pulse(r16)               _BFGET_(r16, 6, 6)
    #define   SET16PIPE_DSI_updatecfg_pulse(r16,v)             _BFSET_(r16, 6, 6,v)

    #define   GET32PIPE_DSI_edpi_mode(r32)                     _BFGET_(r32, 7, 7)
    #define   SET32PIPE_DSI_edpi_mode(r32,v)                   _BFSET_(r32, 7, 7,v)
    #define   GET16PIPE_DSI_edpi_mode(r16)                     _BFGET_(r16, 7, 7)
    #define   SET16PIPE_DSI_edpi_mode(r16,v)                   _BFSET_(r16, 7, 7,v)

    #define   GET32PIPE_DSI_tear_sftrst(r32)                   _BFGET_(r32, 8, 8)
    #define   SET32PIPE_DSI_tear_sftrst(r32,v)                 _BFSET_(r32, 8, 8,v)
    #define   GET16PIPE_DSI_tear_sftrst(r16)                   _BFGET_(r16, 8, 8)
    #define   SET16PIPE_DSI_tear_sftrst(r16,v)                 _BFSET_(r16, 8, 8,v)

    #define     w32PIPE_DSI                                    {\
            UNSG32 uDSI_colormode                              :  1;\
            UNSG32 uDSI_shutdn                                 :  1;\
            UNSG32 uDSI_hw_updatecfg_on                        :  1;\
            UNSG32 uDSI_hw_tear_effect_on                      :  1;\
            UNSG32 uDSI_force_pll_on                           :  1;\
            UNSG32 uDSI_tear_request_pulse                     :  1;\
            UNSG32 uDSI_updatecfg_pulse                        :  1;\
            UNSG32 uDSI_edpi_mode                              :  1;\
            UNSG32 uDSI_tear_sftrst                            :  1;\
            UNSG32 RSVDx18_b9                                  : 23;\
          }
    union { UNSG32 u32PIPE_DSI;
            struct w32PIPE_DSI;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_DPHY_turn_disable_lane0(r32)           _BFGET_(r32, 0, 0)
    #define   SET32PIPE_DPHY_turn_disable_lane0(r32,v)         _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_DPHY_turn_disable_lane0(r16)           _BFGET_(r16, 0, 0)
    #define   SET16PIPE_DPHY_turn_disable_lane0(r16,v)         _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_DPHY_ftxstopmode_lane0(r32)            _BFGET_(r32, 1, 1)
    #define   SET32PIPE_DPHY_ftxstopmode_lane0(r32,v)          _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_DPHY_ftxstopmode_lane0(r16)            _BFGET_(r16, 1, 1)
    #define   SET16PIPE_DPHY_ftxstopmode_lane0(r16,v)          _BFSET_(r16, 1, 1,v)

    #define   GET32PIPE_DPHY_forcerxmode_lane0(r32)            _BFGET_(r32, 2, 2)
    #define   SET32PIPE_DPHY_forcerxmode_lane0(r32,v)          _BFSET_(r32, 2, 2,v)
    #define   GET16PIPE_DPHY_forcerxmode_lane0(r16)            _BFGET_(r16, 2, 2)
    #define   SET16PIPE_DPHY_forcerxmode_lane0(r16,v)          _BFSET_(r16, 2, 2,v)

    #define   GET32PIPE_DPHY_csr_cfgrstn(r32)                  _BFGET_(r32, 3, 3)
    #define   SET32PIPE_DPHY_csr_cfgrstn(r32,v)                _BFSET_(r32, 3, 3,v)
    #define   GET16PIPE_DPHY_csr_cfgrstn(r16)                  _BFGET_(r16, 3, 3)
    #define   SET16PIPE_DPHY_csr_cfgrstn(r16,v)                _BFSET_(r16, 3, 3,v)

    #define     w32PIPE_DPHY                                   {\
            UNSG32 uDPHY_turn_disable_lane0                    :  1;\
            UNSG32 uDPHY_ftxstopmode_lane0                     :  1;\
            UNSG32 uDPHY_forcerxmode_lane0                     :  1;\
            UNSG32 uDPHY_csr_cfgrstn                           :  1;\
            UNSG32 RSVDx1C_b4                                  : 28;\
          }
    union { UNSG32 u32PIPE_DPHY;
            struct w32PIPE_DPHY;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_INVSCAN_bitmap128_Rd0_en(r32)          _BFGET_(r32, 0, 0)
    #define   SET32PIPE_INVSCAN_bitmap128_Rd0_en(r32,v)        _BFSET_(r32, 0, 0,v)
    #define   GET16PIPE_INVSCAN_bitmap128_Rd0_en(r16)          _BFGET_(r16, 0, 0)
    #define   SET16PIPE_INVSCAN_bitmap128_Rd0_en(r16,v)        _BFSET_(r16, 0, 0,v)

    #define   GET32PIPE_INVSCAN_bitmap128_Rd1_en(r32)          _BFGET_(r32, 1, 1)
    #define   SET32PIPE_INVSCAN_bitmap128_Rd1_en(r32,v)        _BFSET_(r32, 1, 1,v)
    #define   GET16PIPE_INVSCAN_bitmap128_Rd1_en(r16)          _BFGET_(r16, 1, 1)
    #define   SET16PIPE_INVSCAN_bitmap128_Rd1_en(r16,v)        _BFSET_(r16, 1, 1,v)

    #define     w32PIPE_INVSCAN                                {\
            UNSG32 uINVSCAN_bitmap128_Rd0_en                   :  1;\
            UNSG32 uINVSCAN_bitmap128_Rd1_en                   :  1;\
            UNSG32 RSVDx20_b2                                  : 30;\
          }
    union { UNSG32 u32PIPE_INVSCAN;
            struct w32PIPE_INVSCAN;
          };
    ///////////////////////////////////////////////////////////
    #define   GET32PIPE_STATUS_vcnt(r32)                       _BFGET_(r32,15, 0)
    #define   SET32PIPE_STATUS_vcnt(r32,v)                     _BFSET_(r32,15, 0,v)
    #define   GET16PIPE_STATUS_vcnt(r16)                       _BFGET_(r16,15, 0)
    #define   SET16PIPE_STATUS_vcnt(r16,v)                     _BFSET_(r16,15, 0,v)

    #define     w32PIPE_STATUS                                 {\
            UNSG32 uSTATUS_vcnt                                : 16;\
            UNSG32 RSVDx24_b16                                 : 16;\
          }
    union { UNSG32 u32PIPE_STATUS;
            struct w32PIPE_STATUS;
          };
    ///////////////////////////////////////////////////////////
              SIE_BETG                                         ie_TG;
    ///////////////////////////////////////////////////////////
              SIE_BITMAP40                                     ie_BITMAP40;
    ///////////////////////////////////////////////////////////
              SIE_ReadClient                                   ie_RdClient0;
    ///////////////////////////////////////////////////////////
              SIE_ReadClient                                   ie_RdClient1;
    ///////////////////////////////////////////////////////////
    } SIE_PIPE;

    typedef union  T32PIPE_CTRL0
          { UNSG32 u32;
            struct w32PIPE_CTRL0;
                 } T32PIPE_CTRL0;
    typedef union  T32PIPE_CTRL1
          { UNSG32 u32;
            struct w32PIPE_CTRL1;
                 } T32PIPE_CTRL1;
    typedef union  T32PIPE_CTRL2
          { UNSG32 u32;
            struct w32PIPE_CTRL2;
                 } T32PIPE_CTRL2;
    typedef union  T32PIPE_MTG
          { UNSG32 u32;
            struct w32PIPE_MTG;
                 } T32PIPE_MTG;
    typedef union  T32PIPE_CTRL
          { UNSG32 u32;
            struct w32PIPE_CTRL;
                 } T32PIPE_CTRL;
    typedef union  T32PIPE_UFSTATUS
          { UNSG32 u32;
            struct w32PIPE_UFSTATUS;
                 } T32PIPE_UFSTATUS;
    typedef union  T32PIPE_DSI
          { UNSG32 u32;
            struct w32PIPE_DSI;
                 } T32PIPE_DSI;
    typedef union  T32PIPE_DPHY
          { UNSG32 u32;
            struct w32PIPE_DPHY;
                 } T32PIPE_DPHY;
    typedef union  T32PIPE_INVSCAN
          { UNSG32 u32;
            struct w32PIPE_INVSCAN;
                 } T32PIPE_INVSCAN;
    typedef union  T32PIPE_STATUS
          { UNSG32 u32;
            struct w32PIPE_STATUS;
                 } T32PIPE_STATUS;
    ///////////////////////////////////////////////////////////

    typedef union  TPIPE_CTRL0
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_CTRL0;
                   };
                 } TPIPE_CTRL0;
    typedef union  TPIPE_CTRL1
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_CTRL1;
                   };
                 } TPIPE_CTRL1;
    typedef union  TPIPE_CTRL2
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_CTRL2;
                   };
                 } TPIPE_CTRL2;
    typedef union  TPIPE_MTG
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_MTG;
                   };
                 } TPIPE_MTG;
    typedef union  TPIPE_CTRL
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_CTRL;
                   };
                 } TPIPE_CTRL;
    typedef union  TPIPE_UFSTATUS
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_UFSTATUS;
                   };
                 } TPIPE_UFSTATUS;
    typedef union  TPIPE_DSI
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_DSI;
                   };
                 } TPIPE_DSI;
    typedef union  TPIPE_DPHY
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_DPHY;
                   };
                 } TPIPE_DPHY;
    typedef union  TPIPE_INVSCAN
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_INVSCAN;
                   };
                 } TPIPE_INVSCAN;
    typedef union  TPIPE_STATUS
          { UNSG32 u32[1];
            struct {
            struct w32PIPE_STATUS;
                   };
                 } TPIPE_STATUS;

    ///////////////////////////////////////////////////////////
     SIGN32 PIPE_drvrd(SIE_PIPE *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 PIPE_drvwr(SIE_PIPE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void PIPE_reset(SIE_PIPE *p);
     SIGN32 PIPE_cmp  (SIE_PIPE *p, SIE_PIPE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define PIPE_check(p,pie,pfx,hLOG) PIPE_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define PIPE_print(p,    pfx,hLOG) PIPE_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: PIPE
////////////////////////////////////////////////////////////

//////
///
/// $INTERFACE MIPI                    biu              (4,4)
///     # # ----------------------------------------------------------
///     @ 0x00000                      (P)
///     # 0x00000 PIPE
///               $PIPE                PIPE              REG
///                                    ###
///                                    * Register specifications for MIPI pipe processing
///                                    ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:     284B, bits:    1537b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MIPI
#define h_MIPI (){}

    #define     RA_MIPI_PIPE                                   0x0000
    ///////////////////////////////////////////////////////////

    typedef struct SIE_MIPI {
    ///////////////////////////////////////////////////////////
              SIE_PIPE                                         ie_PIPE;
    ///////////////////////////////////////////////////////////
    } SIE_MIPI;

    ///////////////////////////////////////////////////////////
     SIGN32 MIPI_drvrd(SIE_MIPI *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
     SIGN32 MIPI_drvwr(SIE_MIPI *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
       void MIPI_reset(SIE_MIPI *p);
     SIGN32 MIPI_cmp  (SIE_MIPI *p, SIE_MIPI *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
    #define MIPI_check(p,pie,pfx,hLOG) MIPI_cmp(p,pie,pfx,(void*)(hLOG),0,0)
    #define MIPI_print(p,    pfx,hLOG) MIPI_cmp(p,0,  pfx,(void*)(hLOG),0,0)

#endif
//////
/// ENDOFINTERFACE: MIPI
////////////////////////////////////////////////////////////


#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif
//////
/// ENDOFFILE: mipiPipeCore.h
////////////////////////////////////////////////////////////