[
    {
        "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
        "EventCode": "0x00",
        "Counter": "Fixed counter 1",
        "UMask": "0x1",
        "EventName": "INST_RETIRED.ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Instructions retired from execution.",
        "CounterHTOff": "Fixed counter 1"
    },
    {
        "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
        "EventCode": "0x00",
        "Counter": "Fixed counter 2",
        "UMask": "0x2",
        "EventName": "CPU_CLK_UNHALTED.THREAD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles when the thread is not in halt state",
        "CounterHTOff": "Fixed counter 2"
    },
    {
        "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
        "EventCode": "0x00",
        "Counter": "Fixed counter 3",
        "UMask": "0x3",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Reference cycles when the core is not in halt state.",
        "CounterHTOff": "Fixed counter 3"
    },
    {
        "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Thread cycles when thread is not in halt state",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xE6",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "BACLEARS.ANY",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LSD.UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of Uops delivered by the LSD.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
        "EventCode": "0x87",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ILD_STALL.LCP",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.",
        "EventCode": "0x0D",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "INT_MISC.RECOVERY_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x0D",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
        "EventCode": "0xA2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "RESOURCE_STALLS.ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Resource-related stall cycles",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
        "EventCode": "0xA2",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "RESOURCE_STALLS.SB",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
        "EventCode": "0x0E",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_ISSUED.ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x0E",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "UOPS_ISSUED.SLOW_LEA",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
        "EventCode": "0x0E",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_ISSUED.STALL_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
        "EventCode": "0x5E",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "RS_EVENTS.EMPTY_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5E",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EdgeDetect": "1",
        "EventName": "RS_EVENTS.EMPTY_END",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
        "EventCode": "0xCC",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Increments whenever there is an update to the LBR array.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of machine clears (nukes) of any type.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EdgeDetect": "1",
        "EventName": "MACHINE_CLEARS.COUNT",
        "SampleAfterValue": "100003",
        "BriefDescription": "Number of machine clears (nukes) of any type. ",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "MACHINE_CLEARS.SMC",
        "SampleAfterValue": "100003",
        "BriefDescription": "Self-modifying code (SMC) detected.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
        "EventCode": "0xC0",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "Errata": "SKL091, SKL044",
        "EventName": "INST_RETIRED.ANY_P",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of instructions retired. General Counter - architectural event",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "2",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",
        "EventCode": "0xC0",
        "Counter": "1",
        "UMask": "0x1",
        "Errata": "SKL091, SKL044",
        "EventName": "INST_RETIRED.PREC_DIST",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
        "CounterHTOff": "1"
    },
    {
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.",
        "EventCode": "0xC2",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Retirement slots used.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.",
        "EventCode": "0xC2",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_RETIRED.STALL_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles without actually retired uops.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
        "EventCode": "0xC2",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with less than 10 actually retired uops.",
        "CounterMask": "10",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.CONDITIONAL",
        "SampleAfterValue": "400009",
        "BriefDescription": "Conditional branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.NEAR_CALL",
        "SampleAfterValue": "100007",
        "BriefDescription": "Direct and indirect near call instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts all (macro) branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "SampleAfterValue": "400009",
        "BriefDescription": "All (macro) branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.NEAR_RETURN",
        "SampleAfterValue": "100007",
        "BriefDescription": "Return instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.NOT_TAKEN",
        "SampleAfterValue": "400009",
        "BriefDescription": "Not taken branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
        "SampleAfterValue": "400009",
        "BriefDescription": "Taken branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.FAR_BRANCH",
        "SampleAfterValue": "100007",
        "BriefDescription": "Far branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "2",
        "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "Errata": "SKL091",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
        "SampleAfterValue": "400009",
        "BriefDescription": "All (macro) branch instructions retired. ",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "BR_MISP_RETIRED.CONDITIONAL",
        "SampleAfterValue": "400009",
        "BriefDescription": "Mispredicted conditional branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
        "SampleAfterValue": "400009",
        "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "SampleAfterValue": "400009",
        "BriefDescription": "All mispredicted macro branch instructions retired.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
        "SampleAfterValue": "400009",
        "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "2",
        "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
        "SampleAfterValue": "400009",
        "BriefDescription": "Mispredicted macro branch instructions retired. ",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Number of uops to be executed per-thread each cycle.",
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_EXECUTED.THREAD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of uops executed from any thread.",
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_EXECUTED.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of uops executed on the core.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "UOPS_EXECUTED.X87",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of x87 uops dispatched.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
        "EventCode": "0xB1",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_EXECUTED.STALL_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
        "CounterMask": "2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
        "CounterMask": "3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA6",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA6",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA6",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA6",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA6",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA6",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 0",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 5",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 6",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
        "EventCode": "0xA1",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when uops are executed in port 7",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Total execution stalls.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
        "CounterMask": "8",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0xc",
        "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
        "CounterMask": "12",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
        "EventCode": "0x4C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LOAD_HIT_PRE.SW_PF",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap)\n\n - store forwarding is impossible due to u-arch limitations\n\n - preceding lock RMW operations are not forwarded\n\n - store has the no-forward bit set (uncacheable/page-split/masked stores)\n\n - all-blocking stores are used (mostly, fences and port I/O)\n\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "LD_BLOCKS.STORE_FORWARD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded .",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "LD_BLOCKS.NO_SR",
        "SampleAfterValue": "100003",
        "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
        "EventCode": "0x07",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
        "SampleAfterValue": "100003",
        "BriefDescription": "False dependencies in MOB due to partial compare on address.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x5",
        "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
        "CounterMask": "5",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
        "CounterMask": "16",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x14",
        "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
        "CounterMask": "20",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
        "SampleAfterValue": "2503",
        "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Number of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)",
        "EventCode": "0xC0",
        "Invert": "1",
        "Counter": "0,2,3",
        "UMask": "0x1",
        "Errata": "SKL091, SKL044",
        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of cycles using always true condition applied to  PEBS instructions retired event.",
        "CounterMask": "10",
        "CounterHTOff": "0,2,3"
    },
    {
        "EventCode": "0x14",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ARITH.DIVIDER_ACTIVE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LSD.CYCLES_ACTIVE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LSD.CYCLES_4_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC1",
        "Counter": "0,1,2,3",
        "UMask": "0x3f",
        "EventName": "OTHER_ASSISTS.ANY",
        "SampleAfterValue": "100003",
        "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register.\r\nFor more information, refer to ?Mixing Intel AVX and Intel SSE Code? section of the Optimization Guide.",
        "EventCode": "0x0E",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x00",
        "Counter": "Fixed counter 2",
        "UMask": "0x2",
        "AnyThread": "1",
        "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
        "CounterHTOff": "Fixed counter 2"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "AnyThread": "1",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "AnyThread": "1",
        "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
        "SampleAfterValue": "2503",
        "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x0D",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "AnyThread": "1",
        "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
        "CounterMask": "2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
        "CounterMask": "3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB1",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EdgeDetect": "1",
        "EventName": "CPU_CLK_UNHALTED.RING0_TRANS",
        "SampleAfterValue": "100007",
        "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
        "SampleAfterValue": "2503",
        "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "AnyThread": "1",
        "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
        "SampleAfterValue": "2503",
        "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
        "SampleAfterValue": "2503",
        "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]