blob: 719632908c89f6102f9caad4675df2d767d8b1ff [file] [log] [blame]
/*
* Stack-less Just-In-Time compiler
*
* Copyright 2013-2013 Tilera Corporation(jiwang@tilera.com). All rights reserved.
* Copyright 2009-2012 Zoltan Herczeg (hzmester@freemail.hu). All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE COPYRIGHT HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This code is owned by Tilera Corporation, and distributed as part
of multiple projects. In sljit, the code is under BSD licence. */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define BFD_RELOC(x) R_##x
/* Special registers. */
#define TREG_LR 55
#define TREG_SN 56
#define TREG_ZERO 63
/* Canonical name of each register. */
const char *const tilegx_register_names[] =
{
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
"r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
"sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero"
};
enum
{
R_NONE = 0,
R_TILEGX_NONE = 0,
R_TILEGX_64 = 1,
R_TILEGX_32 = 2,
R_TILEGX_16 = 3,
R_TILEGX_8 = 4,
R_TILEGX_64_PCREL = 5,
R_TILEGX_32_PCREL = 6,
R_TILEGX_16_PCREL = 7,
R_TILEGX_8_PCREL = 8,
R_TILEGX_HW0 = 9,
R_TILEGX_HW1 = 10,
R_TILEGX_HW2 = 11,
R_TILEGX_HW3 = 12,
R_TILEGX_HW0_LAST = 13,
R_TILEGX_HW1_LAST = 14,
R_TILEGX_HW2_LAST = 15,
R_TILEGX_COPY = 16,
R_TILEGX_GLOB_DAT = 17,
R_TILEGX_JMP_SLOT = 18,
R_TILEGX_RELATIVE = 19,
R_TILEGX_BROFF_X1 = 20,
R_TILEGX_JUMPOFF_X1 = 21,
R_TILEGX_JUMPOFF_X1_PLT = 22,
R_TILEGX_IMM8_X0 = 23,
R_TILEGX_IMM8_Y0 = 24,
R_TILEGX_IMM8_X1 = 25,
R_TILEGX_IMM8_Y1 = 26,
R_TILEGX_DEST_IMM8_X1 = 27,
R_TILEGX_MT_IMM14_X1 = 28,
R_TILEGX_MF_IMM14_X1 = 29,
R_TILEGX_MMSTART_X0 = 30,
R_TILEGX_MMEND_X0 = 31,
R_TILEGX_SHAMT_X0 = 32,
R_TILEGX_SHAMT_X1 = 33,
R_TILEGX_SHAMT_Y0 = 34,
R_TILEGX_SHAMT_Y1 = 35,
R_TILEGX_IMM16_X0_HW0 = 36,
R_TILEGX_IMM16_X1_HW0 = 37,
R_TILEGX_IMM16_X0_HW1 = 38,
R_TILEGX_IMM16_X1_HW1 = 39,
R_TILEGX_IMM16_X0_HW2 = 40,
R_TILEGX_IMM16_X1_HW2 = 41,
R_TILEGX_IMM16_X0_HW3 = 42,
R_TILEGX_IMM16_X1_HW3 = 43,
R_TILEGX_IMM16_X0_HW0_LAST = 44,
R_TILEGX_IMM16_X1_HW0_LAST = 45,
R_TILEGX_IMM16_X0_HW1_LAST = 46,
R_TILEGX_IMM16_X1_HW1_LAST = 47,
R_TILEGX_IMM16_X0_HW2_LAST = 48,
R_TILEGX_IMM16_X1_HW2_LAST = 49,
R_TILEGX_IMM16_X0_HW0_PCREL = 50,
R_TILEGX_IMM16_X1_HW0_PCREL = 51,
R_TILEGX_IMM16_X0_HW1_PCREL = 52,
R_TILEGX_IMM16_X1_HW1_PCREL = 53,
R_TILEGX_IMM16_X0_HW2_PCREL = 54,
R_TILEGX_IMM16_X1_HW2_PCREL = 55,
R_TILEGX_IMM16_X0_HW3_PCREL = 56,
R_TILEGX_IMM16_X1_HW3_PCREL = 57,
R_TILEGX_IMM16_X0_HW0_LAST_PCREL = 58,
R_TILEGX_IMM16_X1_HW0_LAST_PCREL = 59,
R_TILEGX_IMM16_X0_HW1_LAST_PCREL = 60,
R_TILEGX_IMM16_X1_HW1_LAST_PCREL = 61,
R_TILEGX_IMM16_X0_HW2_LAST_PCREL = 62,
R_TILEGX_IMM16_X1_HW2_LAST_PCREL = 63,
R_TILEGX_IMM16_X0_HW0_GOT = 64,
R_TILEGX_IMM16_X1_HW0_GOT = 65,
R_TILEGX_IMM16_X0_HW0_PLT_PCREL = 66,
R_TILEGX_IMM16_X1_HW0_PLT_PCREL = 67,
R_TILEGX_IMM16_X0_HW1_PLT_PCREL = 68,
R_TILEGX_IMM16_X1_HW1_PLT_PCREL = 69,
R_TILEGX_IMM16_X0_HW2_PLT_PCREL = 70,
R_TILEGX_IMM16_X1_HW2_PLT_PCREL = 71,
R_TILEGX_IMM16_X0_HW0_LAST_GOT = 72,
R_TILEGX_IMM16_X1_HW0_LAST_GOT = 73,
R_TILEGX_IMM16_X0_HW1_LAST_GOT = 74,
R_TILEGX_IMM16_X1_HW1_LAST_GOT = 75,
R_TILEGX_IMM16_X0_HW0_TLS_GD = 78,
R_TILEGX_IMM16_X1_HW0_TLS_GD = 79,
R_TILEGX_IMM16_X0_HW0_TLS_LE = 80,
R_TILEGX_IMM16_X1_HW0_TLS_LE = 81,
R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE = 82,
R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE = 83,
R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE = 84,
R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE = 85,
R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD = 86,
R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD = 87,
R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD = 88,
R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD = 89,
R_TILEGX_IMM16_X0_HW0_TLS_IE = 92,
R_TILEGX_IMM16_X1_HW0_TLS_IE = 93,
R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL = 94,
R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL = 95,
R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL = 96,
R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL = 97,
R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL = 98,
R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL = 99,
R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE = 100,
R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE = 101,
R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE = 102,
R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE = 103,
R_TILEGX_TLS_DTPMOD64 = 106,
R_TILEGX_TLS_DTPOFF64 = 107,
R_TILEGX_TLS_TPOFF64 = 108,
R_TILEGX_TLS_DTPMOD32 = 109,
R_TILEGX_TLS_DTPOFF32 = 110,
R_TILEGX_TLS_TPOFF32 = 111,
R_TILEGX_TLS_GD_CALL = 112,
R_TILEGX_IMM8_X0_TLS_GD_ADD = 113,
R_TILEGX_IMM8_X1_TLS_GD_ADD = 114,
R_TILEGX_IMM8_Y0_TLS_GD_ADD = 115,
R_TILEGX_IMM8_Y1_TLS_GD_ADD = 116,
R_TILEGX_TLS_IE_LOAD = 117,
R_TILEGX_IMM8_X0_TLS_ADD = 118,
R_TILEGX_IMM8_X1_TLS_ADD = 119,
R_TILEGX_IMM8_Y0_TLS_ADD = 120,
R_TILEGX_IMM8_Y1_TLS_ADD = 121,
R_TILEGX_GNU_VTINHERIT = 128,
R_TILEGX_GNU_VTENTRY = 129,
R_TILEGX_IRELATIVE = 130,
R_TILEGX_NUM = 131
};
typedef enum
{
TILEGX_PIPELINE_X0,
TILEGX_PIPELINE_X1,
TILEGX_PIPELINE_Y0,
TILEGX_PIPELINE_Y1,
TILEGX_PIPELINE_Y2,
} tilegx_pipeline;
typedef unsigned long long tilegx_bundle_bits;
/* These are the bits that determine if a bundle is in the X encoding. */
#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
enum
{
/* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
/* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
TILEGX_NUM_PIPELINE_ENCODINGS = 5,
/* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
/* Instructions take this many bytes. */
TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
/* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
/* Bundles should be aligned modulo this number of bytes. */
TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
(1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
/* Number of registers (some are magic, such as network I/O). */
TILEGX_NUM_REGISTERS = 64,
};
/* Make a few "tile_" variables to simplify common code between
architectures. */
typedef tilegx_bundle_bits tile_bundle_bits;
#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
/* 64-bit pattern for a { bpt ; nop } bundle. */
#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
typedef enum
{
TILEGX_OP_TYPE_REGISTER,
TILEGX_OP_TYPE_IMMEDIATE,
TILEGX_OP_TYPE_ADDRESS,
TILEGX_OP_TYPE_SPR
} tilegx_operand_type;
struct tilegx_operand
{
/* Is this operand a register, immediate or address? */
tilegx_operand_type type;
/* The default relocation type for this operand. */
signed int default_reloc : 16;
/* How many bits is this value? (used for range checking) */
unsigned int num_bits : 5;
/* Is the value signed? (used for range checking) */
unsigned int is_signed : 1;
/* Is this operand a source register? */
unsigned int is_src_reg : 1;
/* Is this operand written? (i.e. is it a destination register) */
unsigned int is_dest_reg : 1;
/* Is this operand PC-relative? */
unsigned int is_pc_relative : 1;
/* By how many bits do we right shift the value before inserting? */
unsigned int rightshift : 2;
/* Return the bits for this operand to be ORed into an existing bundle. */
tilegx_bundle_bits (*insert) (int op);
/* Extract this operand and return it. */
unsigned int (*extract) (tilegx_bundle_bits bundle);
};
typedef enum
{
TILEGX_OPC_BPT,
TILEGX_OPC_INFO,
TILEGX_OPC_INFOL,
TILEGX_OPC_LD4S_TLS,
TILEGX_OPC_LD_TLS,
TILEGX_OPC_MOVE,
TILEGX_OPC_MOVEI,
TILEGX_OPC_MOVELI,
TILEGX_OPC_PREFETCH,
TILEGX_OPC_PREFETCH_ADD_L1,
TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
TILEGX_OPC_PREFETCH_ADD_L2,
TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
TILEGX_OPC_PREFETCH_ADD_L3,
TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
TILEGX_OPC_PREFETCH_L1,
TILEGX_OPC_PREFETCH_L1_FAULT,
TILEGX_OPC_PREFETCH_L2,
TILEGX_OPC_PREFETCH_L2_FAULT,
TILEGX_OPC_PREFETCH_L3,
TILEGX_OPC_PREFETCH_L3_FAULT,
TILEGX_OPC_RAISE,
TILEGX_OPC_ADD,
TILEGX_OPC_ADDI,
TILEGX_OPC_ADDLI,
TILEGX_OPC_ADDX,
TILEGX_OPC_ADDXI,
TILEGX_OPC_ADDXLI,
TILEGX_OPC_ADDXSC,
TILEGX_OPC_AND,
TILEGX_OPC_ANDI,
TILEGX_OPC_BEQZ,
TILEGX_OPC_BEQZT,
TILEGX_OPC_BFEXTS,
TILEGX_OPC_BFEXTU,
TILEGX_OPC_BFINS,
TILEGX_OPC_BGEZ,
TILEGX_OPC_BGEZT,
TILEGX_OPC_BGTZ,
TILEGX_OPC_BGTZT,
TILEGX_OPC_BLBC,
TILEGX_OPC_BLBCT,
TILEGX_OPC_BLBS,
TILEGX_OPC_BLBST,
TILEGX_OPC_BLEZ,
TILEGX_OPC_BLEZT,
TILEGX_OPC_BLTZ,
TILEGX_OPC_BLTZT,
TILEGX_OPC_BNEZ,
TILEGX_OPC_BNEZT,
TILEGX_OPC_CLZ,
TILEGX_OPC_CMOVEQZ,
TILEGX_OPC_CMOVNEZ,
TILEGX_OPC_CMPEQ,
TILEGX_OPC_CMPEQI,
TILEGX_OPC_CMPEXCH,
TILEGX_OPC_CMPEXCH4,
TILEGX_OPC_CMPLES,
TILEGX_OPC_CMPLEU,
TILEGX_OPC_CMPLTS,
TILEGX_OPC_CMPLTSI,
TILEGX_OPC_CMPLTU,
TILEGX_OPC_CMPLTUI,
TILEGX_OPC_CMPNE,
TILEGX_OPC_CMUL,
TILEGX_OPC_CMULA,
TILEGX_OPC_CMULAF,
TILEGX_OPC_CMULF,
TILEGX_OPC_CMULFR,
TILEGX_OPC_CMULH,
TILEGX_OPC_CMULHR,
TILEGX_OPC_CRC32_32,
TILEGX_OPC_CRC32_8,
TILEGX_OPC_CTZ,
TILEGX_OPC_DBLALIGN,
TILEGX_OPC_DBLALIGN2,
TILEGX_OPC_DBLALIGN4,
TILEGX_OPC_DBLALIGN6,
TILEGX_OPC_DRAIN,
TILEGX_OPC_DTLBPR,
TILEGX_OPC_EXCH,
TILEGX_OPC_EXCH4,
TILEGX_OPC_FDOUBLE_ADD_FLAGS,
TILEGX_OPC_FDOUBLE_ADDSUB,
TILEGX_OPC_FDOUBLE_MUL_FLAGS,
TILEGX_OPC_FDOUBLE_PACK1,
TILEGX_OPC_FDOUBLE_PACK2,
TILEGX_OPC_FDOUBLE_SUB_FLAGS,
TILEGX_OPC_FDOUBLE_UNPACK_MAX,
TILEGX_OPC_FDOUBLE_UNPACK_MIN,
TILEGX_OPC_FETCHADD,
TILEGX_OPC_FETCHADD4,
TILEGX_OPC_FETCHADDGEZ,
TILEGX_OPC_FETCHADDGEZ4,
TILEGX_OPC_FETCHAND,
TILEGX_OPC_FETCHAND4,
TILEGX_OPC_FETCHOR,
TILEGX_OPC_FETCHOR4,
TILEGX_OPC_FINV,
TILEGX_OPC_FLUSH,
TILEGX_OPC_FLUSHWB,
TILEGX_OPC_FNOP,
TILEGX_OPC_FSINGLE_ADD1,
TILEGX_OPC_FSINGLE_ADDSUB2,
TILEGX_OPC_FSINGLE_MUL1,
TILEGX_OPC_FSINGLE_MUL2,
TILEGX_OPC_FSINGLE_PACK1,
TILEGX_OPC_FSINGLE_PACK2,
TILEGX_OPC_FSINGLE_SUB1,
TILEGX_OPC_ICOH,
TILEGX_OPC_ILL,
TILEGX_OPC_INV,
TILEGX_OPC_IRET,
TILEGX_OPC_J,
TILEGX_OPC_JAL,
TILEGX_OPC_JALR,
TILEGX_OPC_JALRP,
TILEGX_OPC_JR,
TILEGX_OPC_JRP,
TILEGX_OPC_LD,
TILEGX_OPC_LD1S,
TILEGX_OPC_LD1S_ADD,
TILEGX_OPC_LD1U,
TILEGX_OPC_LD1U_ADD,
TILEGX_OPC_LD2S,
TILEGX_OPC_LD2S_ADD,
TILEGX_OPC_LD2U,
TILEGX_OPC_LD2U_ADD,
TILEGX_OPC_LD4S,
TILEGX_OPC_LD4S_ADD,
TILEGX_OPC_LD4U,
TILEGX_OPC_LD4U_ADD,
TILEGX_OPC_LD_ADD,
TILEGX_OPC_LDNA,
TILEGX_OPC_LDNA_ADD,
TILEGX_OPC_LDNT,
TILEGX_OPC_LDNT1S,
TILEGX_OPC_LDNT1S_ADD,
TILEGX_OPC_LDNT1U,
TILEGX_OPC_LDNT1U_ADD,
TILEGX_OPC_LDNT2S,
TILEGX_OPC_LDNT2S_ADD,
TILEGX_OPC_LDNT2U,
TILEGX_OPC_LDNT2U_ADD,
TILEGX_OPC_LDNT4S,
TILEGX_OPC_LDNT4S_ADD,
TILEGX_OPC_LDNT4U,
TILEGX_OPC_LDNT4U_ADD,
TILEGX_OPC_LDNT_ADD,
TILEGX_OPC_LNK,
TILEGX_OPC_MF,
TILEGX_OPC_MFSPR,
TILEGX_OPC_MM,
TILEGX_OPC_MNZ,
TILEGX_OPC_MTSPR,
TILEGX_OPC_MUL_HS_HS,
TILEGX_OPC_MUL_HS_HU,
TILEGX_OPC_MUL_HS_LS,
TILEGX_OPC_MUL_HS_LU,
TILEGX_OPC_MUL_HU_HU,
TILEGX_OPC_MUL_HU_LS,
TILEGX_OPC_MUL_HU_LU,
TILEGX_OPC_MUL_LS_LS,
TILEGX_OPC_MUL_LS_LU,
TILEGX_OPC_MUL_LU_LU,
TILEGX_OPC_MULA_HS_HS,
TILEGX_OPC_MULA_HS_HU,
TILEGX_OPC_MULA_HS_LS,
TILEGX_OPC_MULA_HS_LU,
TILEGX_OPC_MULA_HU_HU,
TILEGX_OPC_MULA_HU_LS,
TILEGX_OPC_MULA_HU_LU,
TILEGX_OPC_MULA_LS_LS,
TILEGX_OPC_MULA_LS_LU,
TILEGX_OPC_MULA_LU_LU,
TILEGX_OPC_MULAX,
TILEGX_OPC_MULX,
TILEGX_OPC_MZ,
TILEGX_OPC_NAP,
TILEGX_OPC_NOP,
TILEGX_OPC_NOR,
TILEGX_OPC_OR,
TILEGX_OPC_ORI,
TILEGX_OPC_PCNT,
TILEGX_OPC_REVBITS,
TILEGX_OPC_REVBYTES,
TILEGX_OPC_ROTL,
TILEGX_OPC_ROTLI,
TILEGX_OPC_SHL,
TILEGX_OPC_SHL16INSLI,
TILEGX_OPC_SHL1ADD,
TILEGX_OPC_SHL1ADDX,
TILEGX_OPC_SHL2ADD,
TILEGX_OPC_SHL2ADDX,
TILEGX_OPC_SHL3ADD,
TILEGX_OPC_SHL3ADDX,
TILEGX_OPC_SHLI,
TILEGX_OPC_SHLX,
TILEGX_OPC_SHLXI,
TILEGX_OPC_SHRS,
TILEGX_OPC_SHRSI,
TILEGX_OPC_SHRU,
TILEGX_OPC_SHRUI,
TILEGX_OPC_SHRUX,
TILEGX_OPC_SHRUXI,
TILEGX_OPC_SHUFFLEBYTES,
TILEGX_OPC_ST,
TILEGX_OPC_ST1,
TILEGX_OPC_ST1_ADD,
TILEGX_OPC_ST2,
TILEGX_OPC_ST2_ADD,
TILEGX_OPC_ST4,
TILEGX_OPC_ST4_ADD,
TILEGX_OPC_ST_ADD,
TILEGX_OPC_STNT,
TILEGX_OPC_STNT1,
TILEGX_OPC_STNT1_ADD,
TILEGX_OPC_STNT2,
TILEGX_OPC_STNT2_ADD,
TILEGX_OPC_STNT4,
TILEGX_OPC_STNT4_ADD,
TILEGX_OPC_STNT_ADD,
TILEGX_OPC_SUB,
TILEGX_OPC_SUBX,
TILEGX_OPC_SUBXSC,
TILEGX_OPC_SWINT0,
TILEGX_OPC_SWINT1,
TILEGX_OPC_SWINT2,
TILEGX_OPC_SWINT3,
TILEGX_OPC_TBLIDXB0,
TILEGX_OPC_TBLIDXB1,
TILEGX_OPC_TBLIDXB2,
TILEGX_OPC_TBLIDXB3,
TILEGX_OPC_V1ADD,
TILEGX_OPC_V1ADDI,
TILEGX_OPC_V1ADDUC,
TILEGX_OPC_V1ADIFFU,
TILEGX_OPC_V1AVGU,
TILEGX_OPC_V1CMPEQ,
TILEGX_OPC_V1CMPEQI,
TILEGX_OPC_V1CMPLES,
TILEGX_OPC_V1CMPLEU,
TILEGX_OPC_V1CMPLTS,
TILEGX_OPC_V1CMPLTSI,
TILEGX_OPC_V1CMPLTU,
TILEGX_OPC_V1CMPLTUI,
TILEGX_OPC_V1CMPNE,
TILEGX_OPC_V1DDOTPU,
TILEGX_OPC_V1DDOTPUA,
TILEGX_OPC_V1DDOTPUS,
TILEGX_OPC_V1DDOTPUSA,
TILEGX_OPC_V1DOTP,
TILEGX_OPC_V1DOTPA,
TILEGX_OPC_V1DOTPU,
TILEGX_OPC_V1DOTPUA,
TILEGX_OPC_V1DOTPUS,
TILEGX_OPC_V1DOTPUSA,
TILEGX_OPC_V1INT_H,
TILEGX_OPC_V1INT_L,
TILEGX_OPC_V1MAXU,
TILEGX_OPC_V1MAXUI,
TILEGX_OPC_V1MINU,
TILEGX_OPC_V1MINUI,
TILEGX_OPC_V1MNZ,
TILEGX_OPC_V1MULTU,
TILEGX_OPC_V1MULU,
TILEGX_OPC_V1MULUS,
TILEGX_OPC_V1MZ,
TILEGX_OPC_V1SADAU,
TILEGX_OPC_V1SADU,
TILEGX_OPC_V1SHL,
TILEGX_OPC_V1SHLI,
TILEGX_OPC_V1SHRS,
TILEGX_OPC_V1SHRSI,
TILEGX_OPC_V1SHRU,
TILEGX_OPC_V1SHRUI,
TILEGX_OPC_V1SUB,
TILEGX_OPC_V1SUBUC,
TILEGX_OPC_V2ADD,
TILEGX_OPC_V2ADDI,
TILEGX_OPC_V2ADDSC,
TILEGX_OPC_V2ADIFFS,
TILEGX_OPC_V2AVGS,
TILEGX_OPC_V2CMPEQ,
TILEGX_OPC_V2CMPEQI,
TILEGX_OPC_V2CMPLES,
TILEGX_OPC_V2CMPLEU,
TILEGX_OPC_V2CMPLTS,
TILEGX_OPC_V2CMPLTSI,
TILEGX_OPC_V2CMPLTU,
TILEGX_OPC_V2CMPLTUI,
TILEGX_OPC_V2CMPNE,
TILEGX_OPC_V2DOTP,
TILEGX_OPC_V2DOTPA,
TILEGX_OPC_V2INT_H,
TILEGX_OPC_V2INT_L,
TILEGX_OPC_V2MAXS,
TILEGX_OPC_V2MAXSI,
TILEGX_OPC_V2MINS,
TILEGX_OPC_V2MINSI,
TILEGX_OPC_V2MNZ,
TILEGX_OPC_V2MULFSC,
TILEGX_OPC_V2MULS,
TILEGX_OPC_V2MULTS,
TILEGX_OPC_V2MZ,
TILEGX_OPC_V2PACKH,
TILEGX_OPC_V2PACKL,
TILEGX_OPC_V2PACKUC,
TILEGX_OPC_V2SADAS,
TILEGX_OPC_V2SADAU,
TILEGX_OPC_V2SADS,
TILEGX_OPC_V2SADU,
TILEGX_OPC_V2SHL,
TILEGX_OPC_V2SHLI,
TILEGX_OPC_V2SHLSC,
TILEGX_OPC_V2SHRS,
TILEGX_OPC_V2SHRSI,
TILEGX_OPC_V2SHRU,
TILEGX_OPC_V2SHRUI,
TILEGX_OPC_V2SUB,
TILEGX_OPC_V2SUBSC,
TILEGX_OPC_V4ADD,
TILEGX_OPC_V4ADDSC,
TILEGX_OPC_V4INT_H,
TILEGX_OPC_V4INT_L,
TILEGX_OPC_V4PACKSC,
TILEGX_OPC_V4SHL,
TILEGX_OPC_V4SHLSC,
TILEGX_OPC_V4SHRS,
TILEGX_OPC_V4SHRU,
TILEGX_OPC_V4SUB,
TILEGX_OPC_V4SUBSC,
TILEGX_OPC_WH64,
TILEGX_OPC_XOR,
TILEGX_OPC_XORI,
TILEGX_OPC_NONE
} tilegx_mnemonic;
enum
{
TILEGX_MAX_OPERANDS = 4 /* bfexts */
};
struct tilegx_opcode
{
/* The opcode mnemonic, e.g. "add" */
const char *name;
/* The enum value for this mnemonic. */
tilegx_mnemonic mnemonic;
/* A bit mask of which of the five pipes this instruction
is compatible with:
X0 0x01
X1 0x02
Y0 0x04
Y1 0x08
Y2 0x10 */
unsigned char pipes;
/* How many operands are there? */
unsigned char num_operands;
/* Which register does this write implicitly, or TREG_ZERO if none? */
unsigned char implicitly_written_register;
/* Can this be bundled with other instructions (almost always true). */
unsigned char can_bundle;
/* The description of the operands. Each of these is an
* index into the tilegx_operands[] table. */
unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
/* A mask of which bits have predefined values for each pipeline.
* This is useful for disassembly. */
tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS];
/* For each bit set in fixed_bit_masks, what the value is for this
* instruction. */
tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS];
};
/* Used for non-textual disassembly into structs. */
struct tilegx_decoded_instruction
{
const struct tilegx_opcode *opcode;
const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
long long operand_values[TILEGX_MAX_OPERANDS];
};
enum
{
ADDI_IMM8_OPCODE_X0 = 1,
ADDI_IMM8_OPCODE_X1 = 1,
ADDI_OPCODE_Y0 = 0,
ADDI_OPCODE_Y1 = 1,
ADDLI_OPCODE_X0 = 1,
ADDLI_OPCODE_X1 = 0,
ADDXI_IMM8_OPCODE_X0 = 2,
ADDXI_IMM8_OPCODE_X1 = 2,
ADDXI_OPCODE_Y0 = 1,
ADDXI_OPCODE_Y1 = 2,
ADDXLI_OPCODE_X0 = 2,
ADDXLI_OPCODE_X1 = 1,
ADDXSC_RRR_0_OPCODE_X0 = 1,
ADDXSC_RRR_0_OPCODE_X1 = 1,
ADDX_RRR_0_OPCODE_X0 = 2,
ADDX_RRR_0_OPCODE_X1 = 2,
ADDX_RRR_0_OPCODE_Y0 = 0,
ADDX_SPECIAL_0_OPCODE_Y1 = 0,
ADD_RRR_0_OPCODE_X0 = 3,
ADD_RRR_0_OPCODE_X1 = 3,
ADD_RRR_0_OPCODE_Y0 = 1,
ADD_SPECIAL_0_OPCODE_Y1 = 1,
ANDI_IMM8_OPCODE_X0 = 3,
ANDI_IMM8_OPCODE_X1 = 3,
ANDI_OPCODE_Y0 = 2,
ANDI_OPCODE_Y1 = 3,
AND_RRR_0_OPCODE_X0 = 4,
AND_RRR_0_OPCODE_X1 = 4,
AND_RRR_5_OPCODE_Y0 = 0,
AND_RRR_5_OPCODE_Y1 = 0,
BEQZT_BRANCH_OPCODE_X1 = 16,
BEQZ_BRANCH_OPCODE_X1 = 17,
BFEXTS_BF_OPCODE_X0 = 4,
BFEXTU_BF_OPCODE_X0 = 5,
BFINS_BF_OPCODE_X0 = 6,
BF_OPCODE_X0 = 3,
BGEZT_BRANCH_OPCODE_X1 = 18,
BGEZ_BRANCH_OPCODE_X1 = 19,
BGTZT_BRANCH_OPCODE_X1 = 20,
BGTZ_BRANCH_OPCODE_X1 = 21,
BLBCT_BRANCH_OPCODE_X1 = 22,
BLBC_BRANCH_OPCODE_X1 = 23,
BLBST_BRANCH_OPCODE_X1 = 24,
BLBS_BRANCH_OPCODE_X1 = 25,
BLEZT_BRANCH_OPCODE_X1 = 26,
BLEZ_BRANCH_OPCODE_X1 = 27,
BLTZT_BRANCH_OPCODE_X1 = 28,
BLTZ_BRANCH_OPCODE_X1 = 29,
BNEZT_BRANCH_OPCODE_X1 = 30,
BNEZ_BRANCH_OPCODE_X1 = 31,
BRANCH_OPCODE_X1 = 2,
CMOVEQZ_RRR_0_OPCODE_X0 = 5,
CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
CMOVNEZ_RRR_0_OPCODE_X0 = 6,
CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
CMPEQI_IMM8_OPCODE_X0 = 4,
CMPEQI_IMM8_OPCODE_X1 = 4,
CMPEQI_OPCODE_Y0 = 3,
CMPEQI_OPCODE_Y1 = 4,
CMPEQ_RRR_0_OPCODE_X0 = 7,
CMPEQ_RRR_0_OPCODE_X1 = 5,
CMPEQ_RRR_3_OPCODE_Y0 = 0,
CMPEQ_RRR_3_OPCODE_Y1 = 2,
CMPEXCH4_RRR_0_OPCODE_X1 = 6,
CMPEXCH_RRR_0_OPCODE_X1 = 7,
CMPLES_RRR_0_OPCODE_X0 = 8,
CMPLES_RRR_0_OPCODE_X1 = 8,
CMPLES_RRR_2_OPCODE_Y0 = 0,
CMPLES_RRR_2_OPCODE_Y1 = 0,
CMPLEU_RRR_0_OPCODE_X0 = 9,
CMPLEU_RRR_0_OPCODE_X1 = 9,
CMPLEU_RRR_2_OPCODE_Y0 = 1,
CMPLEU_RRR_2_OPCODE_Y1 = 1,
CMPLTSI_IMM8_OPCODE_X0 = 5,
CMPLTSI_IMM8_OPCODE_X1 = 5,
CMPLTSI_OPCODE_Y0 = 4,
CMPLTSI_OPCODE_Y1 = 5,
CMPLTS_RRR_0_OPCODE_X0 = 10,
CMPLTS_RRR_0_OPCODE_X1 = 10,
CMPLTS_RRR_2_OPCODE_Y0 = 2,
CMPLTS_RRR_2_OPCODE_Y1 = 2,
CMPLTUI_IMM8_OPCODE_X0 = 6,
CMPLTUI_IMM8_OPCODE_X1 = 6,
CMPLTU_RRR_0_OPCODE_X0 = 11,
CMPLTU_RRR_0_OPCODE_X1 = 11,
CMPLTU_RRR_2_OPCODE_Y0 = 3,
CMPLTU_RRR_2_OPCODE_Y1 = 3,
CMPNE_RRR_0_OPCODE_X0 = 12,
CMPNE_RRR_0_OPCODE_X1 = 12,
CMPNE_RRR_3_OPCODE_Y0 = 1,
CMPNE_RRR_3_OPCODE_Y1 = 3,
CMULAF_RRR_0_OPCODE_X0 = 13,
CMULA_RRR_0_OPCODE_X0 = 14,
CMULFR_RRR_0_OPCODE_X0 = 15,
CMULF_RRR_0_OPCODE_X0 = 16,
CMULHR_RRR_0_OPCODE_X0 = 17,
CMULH_RRR_0_OPCODE_X0 = 18,
CMUL_RRR_0_OPCODE_X0 = 19,
CNTLZ_UNARY_OPCODE_X0 = 1,
CNTLZ_UNARY_OPCODE_Y0 = 1,
CNTTZ_UNARY_OPCODE_X0 = 2,
CNTTZ_UNARY_OPCODE_Y0 = 2,
CRC32_32_RRR_0_OPCODE_X0 = 20,
CRC32_8_RRR_0_OPCODE_X0 = 21,
DBLALIGN2_RRR_0_OPCODE_X0 = 22,
DBLALIGN2_RRR_0_OPCODE_X1 = 13,
DBLALIGN4_RRR_0_OPCODE_X0 = 23,
DBLALIGN4_RRR_0_OPCODE_X1 = 14,
DBLALIGN6_RRR_0_OPCODE_X0 = 24,
DBLALIGN6_RRR_0_OPCODE_X1 = 15,
DBLALIGN_RRR_0_OPCODE_X0 = 25,
DRAIN_UNARY_OPCODE_X1 = 1,
DTLBPR_UNARY_OPCODE_X1 = 2,
EXCH4_RRR_0_OPCODE_X1 = 16,
EXCH_RRR_0_OPCODE_X1 = 17,
FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
FETCHADD4_RRR_0_OPCODE_X1 = 18,
FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
FETCHADD_RRR_0_OPCODE_X1 = 21,
FETCHAND4_RRR_0_OPCODE_X1 = 22,
FETCHAND_RRR_0_OPCODE_X1 = 23,
FETCHOR4_RRR_0_OPCODE_X1 = 24,
FETCHOR_RRR_0_OPCODE_X1 = 25,
FINV_UNARY_OPCODE_X1 = 3,
FLUSHWB_UNARY_OPCODE_X1 = 4,
FLUSH_UNARY_OPCODE_X1 = 5,
FNOP_UNARY_OPCODE_X0 = 3,
FNOP_UNARY_OPCODE_X1 = 6,
FNOP_UNARY_OPCODE_Y0 = 3,
FNOP_UNARY_OPCODE_Y1 = 8,
FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
ICOH_UNARY_OPCODE_X1 = 7,
ILL_UNARY_OPCODE_X1 = 8,
ILL_UNARY_OPCODE_Y1 = 9,
IMM8_OPCODE_X0 = 4,
IMM8_OPCODE_X1 = 3,
INV_UNARY_OPCODE_X1 = 9,
IRET_UNARY_OPCODE_X1 = 10,
JALRP_UNARY_OPCODE_X1 = 11,
JALRP_UNARY_OPCODE_Y1 = 10,
JALR_UNARY_OPCODE_X1 = 12,
JALR_UNARY_OPCODE_Y1 = 11,
JAL_JUMP_OPCODE_X1 = 0,
JRP_UNARY_OPCODE_X1 = 13,
JRP_UNARY_OPCODE_Y1 = 12,
JR_UNARY_OPCODE_X1 = 14,
JR_UNARY_OPCODE_Y1 = 13,
JUMP_OPCODE_X1 = 4,
J_JUMP_OPCODE_X1 = 1,
LD1S_ADD_IMM8_OPCODE_X1 = 7,
LD1S_OPCODE_Y2 = 0,
LD1S_UNARY_OPCODE_X1 = 15,
LD1U_ADD_IMM8_OPCODE_X1 = 8,
LD1U_OPCODE_Y2 = 1,
LD1U_UNARY_OPCODE_X1 = 16,
LD2S_ADD_IMM8_OPCODE_X1 = 9,
LD2S_OPCODE_Y2 = 2,
LD2S_UNARY_OPCODE_X1 = 17,
LD2U_ADD_IMM8_OPCODE_X1 = 10,
LD2U_OPCODE_Y2 = 3,
LD2U_UNARY_OPCODE_X1 = 18,
LD4S_ADD_IMM8_OPCODE_X1 = 11,
LD4S_OPCODE_Y2 = 1,
LD4S_UNARY_OPCODE_X1 = 19,
LD4U_ADD_IMM8_OPCODE_X1 = 12,
LD4U_OPCODE_Y2 = 2,
LD4U_UNARY_OPCODE_X1 = 20,
LDNA_UNARY_OPCODE_X1 = 21,
LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
LDNT1S_UNARY_OPCODE_X1 = 22,
LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
LDNT1U_UNARY_OPCODE_X1 = 23,
LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
LDNT2S_UNARY_OPCODE_X1 = 24,
LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
LDNT2U_UNARY_OPCODE_X1 = 25,
LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
LDNT4S_UNARY_OPCODE_X1 = 26,
LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
LDNT4U_UNARY_OPCODE_X1 = 27,
LDNT_ADD_IMM8_OPCODE_X1 = 19,
LDNT_UNARY_OPCODE_X1 = 28,
LD_ADD_IMM8_OPCODE_X1 = 20,
LD_OPCODE_Y2 = 3,
LD_UNARY_OPCODE_X1 = 29,
LNK_UNARY_OPCODE_X1 = 30,
LNK_UNARY_OPCODE_Y1 = 14,
LWNA_ADD_IMM8_OPCODE_X1 = 21,
MFSPR_IMM8_OPCODE_X1 = 22,
MF_UNARY_OPCODE_X1 = 31,
MM_BF_OPCODE_X0 = 7,
MNZ_RRR_0_OPCODE_X0 = 40,
MNZ_RRR_0_OPCODE_X1 = 26,
MNZ_RRR_4_OPCODE_Y0 = 2,
MNZ_RRR_4_OPCODE_Y1 = 2,
MODE_OPCODE_YA2 = 1,
MODE_OPCODE_YB2 = 2,
MODE_OPCODE_YC2 = 3,
MTSPR_IMM8_OPCODE_X1 = 23,
MULAX_RRR_0_OPCODE_X0 = 41,
MULAX_RRR_3_OPCODE_Y0 = 2,
MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
MULX_RRR_0_OPCODE_X0 = 52,
MULX_RRR_3_OPCODE_Y0 = 3,
MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
MZ_RRR_0_OPCODE_X0 = 63,
MZ_RRR_0_OPCODE_X1 = 27,
MZ_RRR_4_OPCODE_Y0 = 3,
MZ_RRR_4_OPCODE_Y1 = 3,
NAP_UNARY_OPCODE_X1 = 32,
NOP_UNARY_OPCODE_X0 = 5,
NOP_UNARY_OPCODE_X1 = 33,
NOP_UNARY_OPCODE_Y0 = 5,
NOP_UNARY_OPCODE_Y1 = 15,
NOR_RRR_0_OPCODE_X0 = 64,
NOR_RRR_0_OPCODE_X1 = 28,
NOR_RRR_5_OPCODE_Y0 = 1,
NOR_RRR_5_OPCODE_Y1 = 1,
ORI_IMM8_OPCODE_X0 = 7,
ORI_IMM8_OPCODE_X1 = 24,
OR_RRR_0_OPCODE_X0 = 65,
OR_RRR_0_OPCODE_X1 = 29,
OR_RRR_5_OPCODE_Y0 = 2,
OR_RRR_5_OPCODE_Y1 = 2,
PCNT_UNARY_OPCODE_X0 = 6,
PCNT_UNARY_OPCODE_Y0 = 6,
REVBITS_UNARY_OPCODE_X0 = 7,
REVBITS_UNARY_OPCODE_Y0 = 7,
REVBYTES_UNARY_OPCODE_X0 = 8,
REVBYTES_UNARY_OPCODE_Y0 = 8,
ROTLI_SHIFT_OPCODE_X0 = 1,
ROTLI_SHIFT_OPCODE_X1 = 1,
ROTLI_SHIFT_OPCODE_Y0 = 0,
ROTLI_SHIFT_OPCODE_Y1 = 0,
ROTL_RRR_0_OPCODE_X0 = 66,
ROTL_RRR_0_OPCODE_X1 = 30,
ROTL_RRR_6_OPCODE_Y0 = 0,
ROTL_RRR_6_OPCODE_Y1 = 0,
RRR_0_OPCODE_X0 = 5,
RRR_0_OPCODE_X1 = 5,
RRR_0_OPCODE_Y0 = 5,
RRR_0_OPCODE_Y1 = 6,
RRR_1_OPCODE_Y0 = 6,
RRR_1_OPCODE_Y1 = 7,
RRR_2_OPCODE_Y0 = 7,
RRR_2_OPCODE_Y1 = 8,
RRR_3_OPCODE_Y0 = 8,
RRR_3_OPCODE_Y1 = 9,
RRR_4_OPCODE_Y0 = 9,
RRR_4_OPCODE_Y1 = 10,
RRR_5_OPCODE_Y0 = 10,
RRR_5_OPCODE_Y1 = 11,
RRR_6_OPCODE_Y0 = 11,
RRR_6_OPCODE_Y1 = 12,
RRR_7_OPCODE_Y0 = 12,
RRR_7_OPCODE_Y1 = 13,
RRR_8_OPCODE_Y0 = 13,
RRR_9_OPCODE_Y0 = 14,
SHIFT_OPCODE_X0 = 6,
SHIFT_OPCODE_X1 = 6,
SHIFT_OPCODE_Y0 = 15,
SHIFT_OPCODE_Y1 = 14,
SHL16INSLI_OPCODE_X0 = 7,
SHL16INSLI_OPCODE_X1 = 7,
SHL1ADDX_RRR_0_OPCODE_X0 = 67,
SHL1ADDX_RRR_0_OPCODE_X1 = 31,
SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
SHL1ADD_RRR_0_OPCODE_X0 = 68,
SHL1ADD_RRR_0_OPCODE_X1 = 32,
SHL1ADD_RRR_1_OPCODE_Y0 = 0,
SHL1ADD_RRR_1_OPCODE_Y1 = 0,
SHL2ADDX_RRR_0_OPCODE_X0 = 69,
SHL2ADDX_RRR_0_OPCODE_X1 = 33,
SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
SHL2ADD_RRR_0_OPCODE_X0 = 70,
SHL2ADD_RRR_0_OPCODE_X1 = 34,
SHL2ADD_RRR_1_OPCODE_Y0 = 1,
SHL2ADD_RRR_1_OPCODE_Y1 = 1,
SHL3ADDX_RRR_0_OPCODE_X0 = 71,
SHL3ADDX_RRR_0_OPCODE_X1 = 35,
SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
SHL3ADD_RRR_0_OPCODE_X0 = 72,
SHL3ADD_RRR_0_OPCODE_X1 = 36,
SHL3ADD_RRR_1_OPCODE_Y0 = 2,
SHL3ADD_RRR_1_OPCODE_Y1 = 2,
SHLI_SHIFT_OPCODE_X0 = 2,
SHLI_SHIFT_OPCODE_X1 = 2,
SHLI_SHIFT_OPCODE_Y0 = 1,
SHLI_SHIFT_OPCODE_Y1 = 1,
SHLXI_SHIFT_OPCODE_X0 = 3,
SHLXI_SHIFT_OPCODE_X1 = 3,
SHLX_RRR_0_OPCODE_X0 = 73,
SHLX_RRR_0_OPCODE_X1 = 37,
SHL_RRR_0_OPCODE_X0 = 74,
SHL_RRR_0_OPCODE_X1 = 38,
SHL_RRR_6_OPCODE_Y0 = 1,
SHL_RRR_6_OPCODE_Y1 = 1,
SHRSI_SHIFT_OPCODE_X0 = 4,
SHRSI_SHIFT_OPCODE_X1 = 4,
SHRSI_SHIFT_OPCODE_Y0 = 2,
SHRSI_SHIFT_OPCODE_Y1 = 2,
SHRS_RRR_0_OPCODE_X0 = 75,
SHRS_RRR_0_OPCODE_X1 = 39,
SHRS_RRR_6_OPCODE_Y0 = 2,
SHRS_RRR_6_OPCODE_Y1 = 2,
SHRUI_SHIFT_OPCODE_X0 = 5,
SHRUI_SHIFT_OPCODE_X1 = 5,
SHRUI_SHIFT_OPCODE_Y0 = 3,
SHRUI_SHIFT_OPCODE_Y1 = 3,
SHRUXI_SHIFT_OPCODE_X0 = 6,
SHRUXI_SHIFT_OPCODE_X1 = 6,
SHRUX_RRR_0_OPCODE_X0 = 76,
SHRUX_RRR_0_OPCODE_X1 = 40,
SHRU_RRR_0_OPCODE_X0 = 77,
SHRU_RRR_0_OPCODE_X1 = 41,
SHRU_RRR_6_OPCODE_Y0 = 3,
SHRU_RRR_6_OPCODE_Y1 = 3,
SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
ST1_ADD_IMM8_OPCODE_X1 = 25,
ST1_OPCODE_Y2 = 0,
ST1_RRR_0_OPCODE_X1 = 42,
ST2_ADD_IMM8_OPCODE_X1 = 26,
ST2_OPCODE_Y2 = 1,
ST2_RRR_0_OPCODE_X1 = 43,
ST4_ADD_IMM8_OPCODE_X1 = 27,
ST4_OPCODE_Y2 = 2,
ST4_RRR_0_OPCODE_X1 = 44,
STNT1_ADD_IMM8_OPCODE_X1 = 28,
STNT1_RRR_0_OPCODE_X1 = 45,
STNT2_ADD_IMM8_OPCODE_X1 = 29,
STNT2_RRR_0_OPCODE_X1 = 46,
STNT4_ADD_IMM8_OPCODE_X1 = 30,
STNT4_RRR_0_OPCODE_X1 = 47,
STNT_ADD_IMM8_OPCODE_X1 = 31,
STNT_RRR_0_OPCODE_X1 = 48,
ST_ADD_IMM8_OPCODE_X1 = 32,
ST_OPCODE_Y2 = 3,
ST_RRR_0_OPCODE_X1 = 49,
SUBXSC_RRR_0_OPCODE_X0 = 79,
SUBXSC_RRR_0_OPCODE_X1 = 50,
SUBX_RRR_0_OPCODE_X0 = 80,
SUBX_RRR_0_OPCODE_X1 = 51,
SUBX_RRR_0_OPCODE_Y0 = 2,
SUBX_RRR_0_OPCODE_Y1 = 2,
SUB_RRR_0_OPCODE_X0 = 81,
SUB_RRR_0_OPCODE_X1 = 52,
SUB_RRR_0_OPCODE_Y0 = 3,
SUB_RRR_0_OPCODE_Y1 = 3,
SWINT0_UNARY_OPCODE_X1 = 34,
SWINT1_UNARY_OPCODE_X1 = 35,
SWINT2_UNARY_OPCODE_X1 = 36,
SWINT3_UNARY_OPCODE_X1 = 37,
TBLIDXB0_UNARY_OPCODE_X0 = 9,
TBLIDXB0_UNARY_OPCODE_Y0 = 9,
TBLIDXB1_UNARY_OPCODE_X0 = 10,
TBLIDXB1_UNARY_OPCODE_Y0 = 10,
TBLIDXB2_UNARY_OPCODE_X0 = 11,
TBLIDXB2_UNARY_OPCODE_Y0 = 11,
TBLIDXB3_UNARY_OPCODE_X0 = 12,
TBLIDXB3_UNARY_OPCODE_Y0 = 12,
UNARY_RRR_0_OPCODE_X0 = 82,
UNARY_RRR_0_OPCODE_X1 = 53,
UNARY_RRR_1_OPCODE_Y0 = 3,
UNARY_RRR_1_OPCODE_Y1 = 3,
V1ADDI_IMM8_OPCODE_X0 = 8,
V1ADDI_IMM8_OPCODE_X1 = 33,
V1ADDUC_RRR_0_OPCODE_X0 = 83,
V1ADDUC_RRR_0_OPCODE_X1 = 54,
V1ADD_RRR_0_OPCODE_X0 = 84,
V1ADD_RRR_0_OPCODE_X1 = 55,
V1ADIFFU_RRR_0_OPCODE_X0 = 85,
V1AVGU_RRR_0_OPCODE_X0 = 86,
V1CMPEQI_IMM8_OPCODE_X0 = 9,
V1CMPEQI_IMM8_OPCODE_X1 = 34,
V1CMPEQ_RRR_0_OPCODE_X0 = 87,
V1CMPEQ_RRR_0_OPCODE_X1 = 56,
V1CMPLES_RRR_0_OPCODE_X0 = 88,
V1CMPLES_RRR_0_OPCODE_X1 = 57,
V1CMPLEU_RRR_0_OPCODE_X0 = 89,
V1CMPLEU_RRR_0_OPCODE_X1 = 58,
V1CMPLTSI_IMM8_OPCODE_X0 = 10,
V1CMPLTSI_IMM8_OPCODE_X1 = 35,
V1CMPLTS_RRR_0_OPCODE_X0 = 90,
V1CMPLTS_RRR_0_OPCODE_X1 = 59,
V1CMPLTUI_IMM8_OPCODE_X0 = 11,
V1CMPLTUI_IMM8_OPCODE_X1 = 36,
V1CMPLTU_RRR_0_OPCODE_X0 = 91,
V1CMPLTU_RRR_0_OPCODE_X1 = 60,
V1CMPNE_RRR_0_OPCODE_X0 = 92,
V1CMPNE_RRR_0_OPCODE_X1 = 61,
V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
V1DDOTPU_RRR_0_OPCODE_X0 = 162,
V1DOTPA_RRR_0_OPCODE_X0 = 95,
V1DOTPUA_RRR_0_OPCODE_X0 = 163,
V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
V1DOTPUS_RRR_0_OPCODE_X0 = 97,
V1DOTPU_RRR_0_OPCODE_X0 = 164,
V1DOTP_RRR_0_OPCODE_X0 = 98,
V1INT_H_RRR_0_OPCODE_X0 = 99,
V1INT_H_RRR_0_OPCODE_X1 = 62,
V1INT_L_RRR_0_OPCODE_X0 = 100,
V1INT_L_RRR_0_OPCODE_X1 = 63,
V1MAXUI_IMM8_OPCODE_X0 = 12,
V1MAXUI_IMM8_OPCODE_X1 = 37,
V1MAXU_RRR_0_OPCODE_X0 = 101,
V1MAXU_RRR_0_OPCODE_X1 = 64,
V1MINUI_IMM8_OPCODE_X0 = 13,
V1MINUI_IMM8_OPCODE_X1 = 38,
V1MINU_RRR_0_OPCODE_X0 = 102,
V1MINU_RRR_0_OPCODE_X1 = 65,
V1MNZ_RRR_0_OPCODE_X0 = 103,
V1MNZ_RRR_0_OPCODE_X1 = 66,
V1MULTU_RRR_0_OPCODE_X0 = 104,
V1MULUS_RRR_0_OPCODE_X0 = 105,
V1MULU_RRR_0_OPCODE_X0 = 106,
V1MZ_RRR_0_OPCODE_X0 = 107,
V1MZ_RRR_0_OPCODE_X1 = 67,
V1SADAU_RRR_0_OPCODE_X0 = 108,
V1SADU_RRR_0_OPCODE_X0 = 109,
V1SHLI_SHIFT_OPCODE_X0 = 7,
V1SHLI_SHIFT_OPCODE_X1 = 7,
V1SHL_RRR_0_OPCODE_X0 = 110,
V1SHL_RRR_0_OPCODE_X1 = 68,
V1SHRSI_SHIFT_OPCODE_X0 = 8,
V1SHRSI_SHIFT_OPCODE_X1 = 8,
V1SHRS_RRR_0_OPCODE_X0 = 111,
V1SHRS_RRR_0_OPCODE_X1 = 69,
V1SHRUI_SHIFT_OPCODE_X0 = 9,
V1SHRUI_SHIFT_OPCODE_X1 = 9,
V1SHRU_RRR_0_OPCODE_X0 = 112,
V1SHRU_RRR_0_OPCODE_X1 = 70,
V1SUBUC_RRR_0_OPCODE_X0 = 113,
V1SUBUC_RRR_0_OPCODE_X1 = 71,
V1SUB_RRR_0_OPCODE_X0 = 114,
V1SUB_RRR_0_OPCODE_X1 = 72,
V2ADDI_IMM8_OPCODE_X0 = 14,
V2ADDI_IMM8_OPCODE_X1 = 39,
V2ADDSC_RRR_0_OPCODE_X0 = 115,
V2ADDSC_RRR_0_OPCODE_X1 = 73,
V2ADD_RRR_0_OPCODE_X0 = 116,
V2ADD_RRR_0_OPCODE_X1 = 74,
V2ADIFFS_RRR_0_OPCODE_X0 = 117,
V2AVGS_RRR_0_OPCODE_X0 = 118,
V2CMPEQI_IMM8_OPCODE_X0 = 15,
V2CMPEQI_IMM8_OPCODE_X1 = 40,
V2CMPEQ_RRR_0_OPCODE_X0 = 119,
V2CMPEQ_RRR_0_OPCODE_X1 = 75,
V2CMPLES_RRR_0_OPCODE_X0 = 120,
V2CMPLES_RRR_0_OPCODE_X1 = 76,
V2CMPLEU_RRR_0_OPCODE_X0 = 121,
V2CMPLEU_RRR_0_OPCODE_X1 = 77,
V2CMPLTSI_IMM8_OPCODE_X0 = 16,
V2CMPLTSI_IMM8_OPCODE_X1 = 41,
V2CMPLTS_RRR_0_OPCODE_X0 = 122,
V2CMPLTS_RRR_0_OPCODE_X1 = 78,
V2CMPLTUI_IMM8_OPCODE_X0 = 17,
V2CMPLTUI_IMM8_OPCODE_X1 = 42,
V2CMPLTU_RRR_0_OPCODE_X0 = 123,
V2CMPLTU_RRR_0_OPCODE_X1 = 79,
V2CMPNE_RRR_0_OPCODE_X0 = 124,
V2CMPNE_RRR_0_OPCODE_X1 = 80,
V2DOTPA_RRR_0_OPCODE_X0 = 125,
V2DOTP_RRR_0_OPCODE_X0 = 126,
V2INT_H_RRR_0_OPCODE_X0 = 127,
V2INT_H_RRR_0_OPCODE_X1 = 81,
V2INT_L_RRR_0_OPCODE_X0 = 128,
V2INT_L_RRR_0_OPCODE_X1 = 82,
V2MAXSI_IMM8_OPCODE_X0 = 18,
V2MAXSI_IMM8_OPCODE_X1 = 43,
V2MAXS_RRR_0_OPCODE_X0 = 129,
V2MAXS_RRR_0_OPCODE_X1 = 83,
V2MINSI_IMM8_OPCODE_X0 = 19,
V2MINSI_IMM8_OPCODE_X1 = 44,
V2MINS_RRR_0_OPCODE_X0 = 130,
V2MINS_RRR_0_OPCODE_X1 = 84,
V2MNZ_RRR_0_OPCODE_X0 = 131,
V2MNZ_RRR_0_OPCODE_X1 = 85,
V2MULFSC_RRR_0_OPCODE_X0 = 132,
V2MULS_RRR_0_OPCODE_X0 = 133,
V2MULTS_RRR_0_OPCODE_X0 = 134,
V2MZ_RRR_0_OPCODE_X0 = 135,
V2MZ_RRR_0_OPCODE_X1 = 86,
V2PACKH_RRR_0_OPCODE_X0 = 136,
V2PACKH_RRR_0_OPCODE_X1 = 87,
V2PACKL_RRR_0_OPCODE_X0 = 137,
V2PACKL_RRR_0_OPCODE_X1 = 88,
V2PACKUC_RRR_0_OPCODE_X0 = 138,
V2PACKUC_RRR_0_OPCODE_X1 = 89,
V2SADAS_RRR_0_OPCODE_X0 = 139,
V2SADAU_RRR_0_OPCODE_X0 = 140,
V2SADS_RRR_0_OPCODE_X0 = 141,
V2SADU_RRR_0_OPCODE_X0 = 142,
V2SHLI_SHIFT_OPCODE_X0 = 10,
V2SHLI_SHIFT_OPCODE_X1 = 10,
V2SHLSC_RRR_0_OPCODE_X0 = 143,
V2SHLSC_RRR_0_OPCODE_X1 = 90,
V2SHL_RRR_0_OPCODE_X0 = 144,
V2SHL_RRR_0_OPCODE_X1 = 91,
V2SHRSI_SHIFT_OPCODE_X0 = 11,
V2SHRSI_SHIFT_OPCODE_X1 = 11,
V2SHRS_RRR_0_OPCODE_X0 = 145,
V2SHRS_RRR_0_OPCODE_X1 = 92,
V2SHRUI_SHIFT_OPCODE_X0 = 12,
V2SHRUI_SHIFT_OPCODE_X1 = 12,
V2SHRU_RRR_0_OPCODE_X0 = 146,
V2SHRU_RRR_0_OPCODE_X1 = 93,
V2SUBSC_RRR_0_OPCODE_X0 = 147,
V2SUBSC_RRR_0_OPCODE_X1 = 94,
V2SUB_RRR_0_OPCODE_X0 = 148,
V2SUB_RRR_0_OPCODE_X1 = 95,
V4ADDSC_RRR_0_OPCODE_X0 = 149,
V4ADDSC_RRR_0_OPCODE_X1 = 96,
V4ADD_RRR_0_OPCODE_X0 = 150,
V4ADD_RRR_0_OPCODE_X1 = 97,
V4INT_H_RRR_0_OPCODE_X0 = 151,
V4INT_H_RRR_0_OPCODE_X1 = 98,
V4INT_L_RRR_0_OPCODE_X0 = 152,
V4INT_L_RRR_0_OPCODE_X1 = 99,
V4PACKSC_RRR_0_OPCODE_X0 = 153,
V4PACKSC_RRR_0_OPCODE_X1 = 100,
V4SHLSC_RRR_0_OPCODE_X0 = 154,
V4SHLSC_RRR_0_OPCODE_X1 = 101,
V4SHL_RRR_0_OPCODE_X0 = 155,
V4SHL_RRR_0_OPCODE_X1 = 102,
V4SHRS_RRR_0_OPCODE_X0 = 156,
V4SHRS_RRR_0_OPCODE_X1 = 103,
V4SHRU_RRR_0_OPCODE_X0 = 157,
V4SHRU_RRR_0_OPCODE_X1 = 104,
V4SUBSC_RRR_0_OPCODE_X0 = 158,
V4SUBSC_RRR_0_OPCODE_X1 = 105,
V4SUB_RRR_0_OPCODE_X0 = 159,
V4SUB_RRR_0_OPCODE_X1 = 106,
WH64_UNARY_OPCODE_X1 = 38,
XORI_IMM8_OPCODE_X0 = 20,
XORI_IMM8_OPCODE_X1 = 45,
XOR_RRR_0_OPCODE_X0 = 160,
XOR_RRR_0_OPCODE_X1 = 107,
XOR_RRR_5_OPCODE_Y0 = 3,
XOR_RRR_5_OPCODE_Y1 = 3
};
static __inline unsigned int
get_BFEnd_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 24)) & 0xf);
}
static __inline unsigned int
get_BFStart_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3f);
}
static __inline unsigned int
get_BrOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 37)) & 0x0001ffc0);
}
static __inline unsigned int
get_BrType_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 54)) & 0x1f);
}
static __inline unsigned int
get_Dest_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 43)) & 0x000000c0);
}
static __inline unsigned int
get_Dest_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 0)) & 0x3f);
}
static __inline unsigned int
get_Dest_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x3f);
}
static __inline unsigned int
get_Dest_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 0)) & 0x3f);
}
static __inline unsigned int
get_Dest_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x3f);
}
static __inline unsigned int
get_Imm16_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xffff);
}
static __inline unsigned int
get_Imm16_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xffff);
}
static __inline unsigned int
get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 20)) & 0xff);
}
static __inline unsigned int
get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 51)) & 0xff);
}
static __inline unsigned int
get_Imm8_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xff);
}
static __inline unsigned int
get_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xff);
}
static __inline unsigned int
get_Imm8_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xff);
}
static __inline unsigned int
get_Imm8_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xff);
}
static __inline unsigned int
get_JumpOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x7ffffff);
}
static __inline unsigned int
get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 58)) & 0x1);
}
static __inline unsigned int
get_MF_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3fff);
}
static __inline unsigned int
get_MT_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 37)) & 0x00003fc0);
}
static __inline unsigned int
get_Mode(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 62)) & 0x3);
}
static __inline unsigned int
get_Opcode_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 28)) & 0x7);
}
static __inline unsigned int
get_Opcode_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 59)) & 0x7);
}
static __inline unsigned int
get_Opcode_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 27)) & 0xf);
}
static __inline unsigned int
get_Opcode_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 58)) & 0xf);
}
static __inline unsigned int
get_Opcode_Y2(tilegx_bundle_bits n)
{
return (((n >> 26)) & 0x00000001) |
(((unsigned int)(n >> 56)) & 0x00000002);
}
static __inline unsigned int
get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3ff);
}
static __inline unsigned int
get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3ff);
}
static __inline unsigned int
get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3);
}
static __inline unsigned int
get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3);
}
static __inline unsigned int
get_ShAmt_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_ShAmt_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
get_ShAmt_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_ShAmt_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3ff);
}
static __inline unsigned int
get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3ff);
}
static __inline unsigned int
get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3);
}
static __inline unsigned int
get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3);
}
static __inline unsigned int
get_SrcA_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 6)) & 0x3f);
}
static __inline unsigned int
get_SrcA_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3f);
}
static __inline unsigned int
get_SrcA_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 6)) & 0x3f);
}
static __inline unsigned int
get_SrcA_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3f);
}
static __inline unsigned int
get_SrcA_Y2(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 20)) & 0x3f);
}
static __inline unsigned int
get_SrcBDest_Y2(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 51)) & 0x3f);
}
static __inline unsigned int
get_SrcB_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_SrcB_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
get_SrcB_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_SrcB_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline int
sign_extend(int n, int num_bits)
{
int shift = (int)(sizeof(int) * 8 - num_bits);
return (n << shift) >> shift;
}
static __inline tilegx_bundle_bits
create_BFEnd_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_BFOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xf) << 24);
}
static __inline tilegx_bundle_bits
create_BFStart_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 18);
}
static __inline tilegx_bundle_bits
create_BrOff_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
(((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
}
static __inline tilegx_bundle_bits
create_BrType_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
}
static __inline tilegx_bundle_bits
create_Dest_Imm8_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
(((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
}
static __inline tilegx_bundle_bits
create_Dest_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 0);
}
static __inline tilegx_bundle_bits
create_Dest_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
}
static __inline tilegx_bundle_bits
create_Dest_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 0);
}
static __inline tilegx_bundle_bits
create_Dest_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
}
static __inline tilegx_bundle_bits
create_Imm16_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xffff) << 12);
}
static __inline tilegx_bundle_bits
create_Imm16_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
}
static __inline tilegx_bundle_bits
create_Imm8OpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 20);
}
static __inline tilegx_bundle_bits
create_Imm8OpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xff)) << 51);
}
static __inline tilegx_bundle_bits
create_Imm8_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 12);
}
static __inline tilegx_bundle_bits
create_Imm8_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xff)) << 43);
}
static __inline tilegx_bundle_bits
create_Imm8_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 12);
}
static __inline tilegx_bundle_bits
create_Imm8_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xff)) << 43);
}
static __inline tilegx_bundle_bits
create_JumpOff_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
}
static __inline tilegx_bundle_bits
create_JumpOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x1)) << 58);
}
static __inline tilegx_bundle_bits
create_MF_Imm14_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
}
static __inline tilegx_bundle_bits
create_MT_Imm14_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
(((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
}
static __inline tilegx_bundle_bits
create_Mode(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3)) << 62);
}
static __inline tilegx_bundle_bits
create_Opcode_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x7) << 28);
}
static __inline tilegx_bundle_bits
create_Opcode_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x7)) << 59);
}
static __inline tilegx_bundle_bits
create_Opcode_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xf) << 27);
}
static __inline tilegx_bundle_bits
create_Opcode_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xf)) << 58);
}
static __inline tilegx_bundle_bits
create_Opcode_Y2(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x00000001) << 26) |
(((tilegx_bundle_bits)(n & 0x00000002)) << 56);
}
static __inline tilegx_bundle_bits
create_RRROpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3ff) << 18);
}
static __inline tilegx_bundle_bits
create_RRROpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
}
static __inline tilegx_bundle_bits
create_RRROpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3) << 18);
}
static __inline tilegx_bundle_bits
create_RRROpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3)) << 49);
}
static __inline tilegx_bundle_bits
create_ShAmt_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_ShAmt_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
static __inline tilegx_bundle_bits
create_ShAmt_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_ShAmt_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3ff) << 18);
}
static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
}
static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3) << 18);
}
static __inline tilegx_bundle_bits
create_ShiftOpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3)) << 49);
}
static __inline tilegx_bundle_bits
create_SrcA_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 6);
}
static __inline tilegx_bundle_bits
create_SrcA_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
}
static __inline tilegx_bundle_bits
create_SrcA_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 6);
}
static __inline tilegx_bundle_bits
create_SrcA_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
}
static __inline tilegx_bundle_bits
create_SrcA_Y2(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 20);
}
static __inline tilegx_bundle_bits
create_SrcBDest_Y2(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
}
static __inline tilegx_bundle_bits
create_SrcB_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_SrcB_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
static __inline tilegx_bundle_bits
create_SrcB_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_SrcB_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
static __inline tilegx_bundle_bits
create_UnaryOpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
const struct tilegx_opcode tilegx_opcodes[336] =
{
{ "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
{ { 0, }, { }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffffffff80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x286a44ae00000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
{ { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ff00fffULL,
0xfff807ff80000000ULL,
0x0000000078000fffULL,
0x3c0007ff80000000ULL,
0ULL
},
{
0x0000000040300fffULL,
0x181807ff80000000ULL,
0x0000000010000fffULL,
0x0c0007ff80000000ULL,
-1ULL
}
#endif
},
{ "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
{ { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc000000070000fffULL,
0xf80007ff80000000ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000070000fffULL,
0x380007ff80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1,
{ { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff80000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1858000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1,
{ { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff80000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x18a0000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
{ { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ffff000ULL,
0xfffff80000000000ULL,
0x00000000780ff000ULL,
0x3c07f80000000000ULL,
0ULL
},
{
0x000000005107f000ULL,
0x283bf80000000000ULL,
0x00000000500bf000ULL,
0x2c05f80000000000ULL,
-1ULL
}
#endif
},
{ "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
{ { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ff00fc0ULL,
0xfff807e000000000ULL,
0x0000000078000fc0ULL,
0x3c0007e000000000ULL,
0ULL
},
{
0x0000000040100fc0ULL,
0x180807e000000000ULL,
0x0000000000000fc0ULL,
0x040007e000000000ULL,
-1ULL
}
#endif
},
{ "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
{ { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc000000070000fc0ULL,
0xf80007e000000000ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000010000fc0ULL,
0x000007e000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286a801f80000000ULL,
-1ULL,
-1ULL,
0x41f8000004000000ULL
}
#endif
},
{ "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfff8001f80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1840001f80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfff8001f80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1838001f80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfff8001f80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1850001f80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfff8001f80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1848001f80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfff8001f80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1860001f80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xfff8001f80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1858001f80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286a801f80000000ULL,
-1ULL,
-1ULL,
0x41f8000004000000ULL
}
#endif
},
{ "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286a781f80000000ULL,
-1ULL,
-1ULL,
0x41f8000000000000ULL
}
#endif
},
{ "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286a901f80000000ULL,
-1ULL,
-1ULL,
0x43f8000004000000ULL
}
#endif
},
{ "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286a881f80000000ULL,
-1ULL,
-1ULL,
0x43f8000000000000ULL
}
#endif
},
{ "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286aa01f80000000ULL,
-1ULL,
-1ULL,
0x83f8000000000000ULL
}
#endif
},
{ "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
#ifndef DISASM_ONLY
{
0ULL,
0xfffff81f80000000ULL,
0ULL,
0ULL,
0xc3f8000004000000ULL
},
{
-1ULL,
0x286a981f80000000ULL,
-1ULL,
-1ULL,
0x81f8000004000000ULL
}
#endif
},
{ "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
{ { 0, }, { }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffffffff80000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x286a44ae80000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ffc0000ULL,
0xfffe000000000000ULL,
0x00000000780c0000ULL,
0x3c06000000000000ULL,
0ULL
},
{
0x00000000500c0000ULL,
0x2806000000000000ULL,
0x0000000028040000ULL,
0x1802000000000000ULL,
-1ULL
}
#endif
},
{ "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ff00000ULL,
0xfff8000000000000ULL,
0x0000000078000000ULL,
0x3c00000000000000ULL,
0ULL
},
{
0x0000000040100000ULL,
0x1808000000000000ULL,
0ULL,
0x0400000000000000ULL,
-1ULL
}
#endif
},
{ "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
{ { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc000000070000000ULL,
0xf800000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000010000000ULL,
0ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ffc0000ULL,
0xfffe000000000000ULL,
0x00000000780c0000ULL,
0x3c06000000000000ULL,
0ULL
},
{
0x0000000050080000ULL,
0x2804000000000000ULL,
0x0000000028000000ULL,
0x1800000000000000ULL,
-1ULL
}
#endif
},
{ "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ff00000ULL,
0xfff8000000000000ULL,
0x0000000078000000ULL,
0x3c00000000000000ULL,
0ULL
},
{
0x0000000040200000ULL,
0x1810000000000000ULL,
0x0000000008000000ULL,
0x0800000000000000ULL,
-1ULL
}
#endif
},
{ "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
{ { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc000000070000000ULL,
0xf800000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000020000000ULL,
0x0800000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ffc0000ULL,
0xfffe000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000050040000ULL,
0x2802000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ffc0000ULL,
0xfffe000000000000ULL,
0x00000000780c0000ULL,
0x3c06000000000000ULL,
0ULL
},
{
0x0000000050100000ULL,
0x2808000000000000ULL,
0x0000000050000000ULL,
0x2c00000000000000ULL,
-1ULL
}
#endif
},
{ "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007ff00000ULL,
0xfff8000000000000ULL,
0x0000000078000000ULL,
0x3c00000000000000ULL,
0ULL
},
{
0x0000000040300000ULL,
0x1818000000000000ULL,
0x0000000010000000ULL,
0x0c00000000000000ULL,
-1ULL
}
#endif
},
{ "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1440000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1400000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
{ { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007f000000ULL,
0ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000034000000ULL,
-1ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
{ { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007f000000ULL,
0ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000035000000ULL,
-1ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
{ { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0xc00000007f000000ULL,
0ULL,
0ULL,
0ULL,
0ULL
},
{
0x0000000036000000ULL,
-1ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x14c0000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1480000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1540000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1500000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x15c0000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1580000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
#ifndef DISASM_ONLY
{
0ULL,
0xffc0000000000000ULL,
0ULL,
0ULL,
0ULL
},
{
-1ULL,
0x1640000000000000ULL,
-1ULL,
-1ULL,
-1ULL
}
#endif
},
{ "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
{ { 0, }, { 7, 20