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<h5 class="subsubsection">9.35.3.3 Constants</h5>

<p><a name="index-Sparc-constants-1645"></a><a name="index-constants_002c-Sparc-1646"></a>
Several Sparc instructions take an immediate operand field for
which mnemonic names exist.  Two such examples are &lsquo;<samp><span class="samp">membar</span></samp>&rsquo;
and &lsquo;<samp><span class="samp">prefetch</span></samp>&rsquo;.  Another example are the set of V9
memory access instruction that allow specification of an
address space identifier.

   <p>The &lsquo;<samp><span class="samp">membar</span></samp>&rsquo; instruction specifies a memory barrier that is
the defined by the operand which is a bitmask.  The supported
mask mnemonics are:

     <ul>
<li>&lsquo;<samp><span class="samp">#Sync</span></samp>&rsquo; requests that all operations (including nonmemory
reference operations) appearing prior to the <code>membar</code> must have
been performed and the effects of any exceptions become visible before
any instructions after the <code>membar</code> may be initiated.  This
corresponds to <code>membar</code> cmask field bit 2.

     <li>&lsquo;<samp><span class="samp">#MemIssue</span></samp>&rsquo; requests that all memory reference operations
appearing prior to the <code>membar</code> must have been performed before
any memory operation after the <code>membar</code> may be initiated.  This
corresponds to <code>membar</code> cmask field bit 1.

     <li>&lsquo;<samp><span class="samp">#Lookaside</span></samp>&rsquo; requests that a store appearing prior to the
<code>membar</code> must complete before any load following the
<code>membar</code> referencing the same address can be initiated.  This
corresponds to <code>membar</code> cmask field bit 0.

     <li>&lsquo;<samp><span class="samp">#StoreStore</span></samp>&rsquo; defines that the effects of all stores appearing
prior to the <code>membar</code> instruction must be visible to all
processors before the effect of any stores following the
<code>membar</code>.  Equivalent to the deprecated <code>stbar</code> instruction. 
This corresponds to <code>membar</code> mmask field bit 3.

     <li>&lsquo;<samp><span class="samp">#LoadStore</span></samp>&rsquo; defines all loads appearing prior to the
<code>membar</code> instruction must have been performed before the effect
of any stores following the <code>membar</code> is visible to any other
processor.  This corresponds to <code>membar</code> mmask field bit 2.

     <li>&lsquo;<samp><span class="samp">#StoreLoad</span></samp>&rsquo; defines that the effects of all stores appearing
prior to the <code>membar</code> instruction must be visible to all
processors before loads following the <code>membar</code> may be performed. 
This corresponds to <code>membar</code> mmask field bit 1.

     <li>&lsquo;<samp><span class="samp">#LoadLoad</span></samp>&rsquo; defines that all loads appearing prior to the
<code>membar</code> instruction must have been performed before any loads
following the <code>membar</code> may be performed.  This corresponds to
<code>membar</code> mmask field bit 0.

   </ul>

   <p>These values can be ored together, for example:

<pre class="example">     membar #Sync
     membar #StoreLoad | #LoadLoad
     membar #StoreLoad | #StoreStore
</pre>
   <p>The <code>prefetch</code> and <code>prefetcha</code> instructions take a prefetch
function code.  The following prefetch function code constant
mnemonics are available:

     <ul>
<li>&lsquo;<samp><span class="samp">#n_reads</span></samp>&rsquo; requests a prefetch for several reads, and corresponds
to a prefetch function code of 0.

     <p>&lsquo;<samp><span class="samp">#one_read</span></samp>&rsquo; requests a prefetch for one read, and corresponds
to a prefetch function code of 1.

     <p>&lsquo;<samp><span class="samp">#n_writes</span></samp>&rsquo; requests a prefetch for several writes (and possibly
reads), and corresponds to a prefetch function code of 2.

     <p>&lsquo;<samp><span class="samp">#one_write</span></samp>&rsquo; requests a prefetch for one write, and corresponds
to a prefetch function code of 3.

     <p>&lsquo;<samp><span class="samp">#page</span></samp>&rsquo; requests a prefetch page, and corresponds to a prefetch
function code of 4.

     <p>&lsquo;<samp><span class="samp">#invalidate</span></samp>&rsquo; requests a prefetch invalidate, and corresponds to
a prefetch function code of 16.

     <p>&lsquo;<samp><span class="samp">#unified</span></samp>&rsquo; requests a prefetch to the nearest unified cache, and
corresponds to a prefetch function code of 17.

     <p>&lsquo;<samp><span class="samp">#n_reads_strong</span></samp>&rsquo; requests a strong prefetch for several reads,
and corresponds to a prefetch function code of 20.

     <p>&lsquo;<samp><span class="samp">#one_read_strong</span></samp>&rsquo; requests a strong prefetch for one read,
and corresponds to a prefetch function code of 21.

     <p>&lsquo;<samp><span class="samp">#n_writes_strong</span></samp>&rsquo; requests a strong prefetch for several writes,
and corresponds to a prefetch function code of 22.

     <p>&lsquo;<samp><span class="samp">#one_write_strong</span></samp>&rsquo; requests a strong prefetch for one write,
and corresponds to a prefetch function code of 23.

     <p>Onle one prefetch code may be specified.  Here are some examples:

     <pre class="example">          prefetch  [%l0 + %l2], #one_read
          prefetch  [%g2 + 8], #n_writes
          prefetcha [%g1] 0x8, #unified
          prefetcha [%o0 + 0x10] %asi, #n_reads
</pre>
     <p>The actual behavior of a given prefetch function code is processor
specific.  If a processor does not implement a given prefetch
function code, it will treat the prefetch instruction as a nop.

     <p>For instructions that accept an immediate address space identifier,
<code>as</code> provides many mnemonics corresponding to
V9 defined as well as UltraSPARC and Niagara extended values. 
For example, &lsquo;<samp><span class="samp">#ASI_P</span></samp>&rsquo; and &lsquo;<samp><span class="samp">#ASI_BLK_INIT_QUAD_LDD_AIUS</span></samp>&rsquo;. 
See the V9 and processor specific manuals for details.

   </ul>

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