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<h4 class="subsection">6.52.8 MIPS Paired-Single Support</h4>

<p>The MIPS64 architecture includes a number of instructions that
operate on pairs of single-precision floating-point values. 
Each pair is packed into a 64-bit floating-point register,
with one element being designated the &ldquo;upper half&rdquo; and
the other being designated the &ldquo;lower half&rdquo;.

 <p>GCC supports paired-single operations using both the generic
vector extensions (see <a href="Vector-Extensions.html#Vector-Extensions">Vector Extensions</a>) and a collection of
MIPS-specific built-in functions.  Both kinds of support are
enabled by the <samp><span class="option">-mpaired-single</span></samp> command-line option.

 <p>The vector type associated with paired-single values is usually
called <code>v2sf</code>.  It can be defined in C as follows:

<pre class="smallexample">     typedef float v2sf __attribute__ ((vector_size (8)));
</pre>
 <p><code>v2sf</code> values are initialized in the same way as aggregates. 
For example:

<pre class="smallexample">     v2sf a = {1.5, 9.1};
     v2sf b;
     float e, f;
     b = (v2sf) {e, f};
</pre>
 <p><em>Note:</em> The CPU's endianness determines which value is stored in
the upper half of a register and which value is stored in the lower half. 
On little-endian targets, the first value is the lower one and the second
value is the upper one.  The opposite order applies to big-endian targets. 
For example, the code above will set the lower half of <code>a</code> to
<code>1.5</code> on little-endian targets and <code>9.1</code> on big-endian targets.

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