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<h3 class="section">4.4 <samp><span class="command">ld</span></samp> and the ARM family</h3>

<p><a name="index-ARM-interworking-support-574"></a><a name="index-g_t_002d_002dsupport_002dold_002dcode-575"></a>For the ARM, <samp><span class="command">ld</span></samp> will generate code stubs to allow functions calls
between ARM and Thumb code.  These stubs only work with code that has
been compiled and assembled with the &lsquo;<samp><span class="samp">-mthumb-interwork</span></samp>&rsquo; command
line option.  If it is necessary to link with old ARM object files or
libraries, which have not been compiled with the -mthumb-interwork
option then the &lsquo;<samp><span class="samp">--support-old-code</span></samp>&rsquo; command line switch should be
given to the linker.  This will make it generate larger stub functions
which will work with non-interworking aware ARM code.  Note, however,
the linker does not support generating stubs for function calls to
non-interworking aware Thumb code.

   <p><a name="index-thumb-entry-point-576"></a><a name="index-entry-point_002c-thumb-577"></a><a name="index-g_t_002d_002dthumb_002dentry_003d_0040var_007bentry_007d-578"></a>The &lsquo;<samp><span class="samp">--thumb-entry</span></samp>&rsquo; switch is a duplicate of the generic
&lsquo;<samp><span class="samp">--entry</span></samp>&rsquo; switch, in that it sets the program's starting address. 
But it also sets the bottom bit of the address, so that it can be
branched to using a BX instruction, and the program will start
executing in Thumb mode straight away.

   <p><a name="index-PE-import-table-prefixing-579"></a><a name="index-g_t_002d_002duse_002dnul_002dprefixed_002dimport_002dtables-580"></a>The &lsquo;<samp><span class="samp">--use-nul-prefixed-import-tables</span></samp>&rsquo; switch is specifying, that
the import tables idata4 and idata5 have to be generated with a zero
elememt prefix for import libraries. This is the old style to generate
import tables. By default this option is turned off.

   <p><a name="index-BE8-581"></a><a name="index-g_t_002d_002dbe8-582"></a>The &lsquo;<samp><span class="samp">--be8</span></samp>&rsquo; switch instructs <samp><span class="command">ld</span></samp> to generate BE8 format
executables.  This option is only valid when linking big-endian objects. 
The resulting image will contain big-endian data and little-endian code.

   <p><a name="index-TARGET1-583"></a><a name="index-g_t_002d_002dtarget1_002drel-584"></a><a name="index-g_t_002d_002dtarget1_002dabs-585"></a>The &lsquo;<samp><span class="samp">R_ARM_TARGET1</span></samp>&rsquo; relocation is typically used for entries in the
&lsquo;<samp><span class="samp">.init_array</span></samp>&rsquo; section.  It is interpreted as either &lsquo;<samp><span class="samp">R_ARM_REL32</span></samp>&rsquo;
or &lsquo;<samp><span class="samp">R_ARM_ABS32</span></samp>&rsquo;, depending on the target.  The &lsquo;<samp><span class="samp">--target1-rel</span></samp>&rsquo;
and &lsquo;<samp><span class="samp">--target1-abs</span></samp>&rsquo; switches override the default.

   <p><a name="index-TARGET2-586"></a><a name="index-g_t_002d_002dtarget2_003d_0040var_007btype_007d-587"></a>The &lsquo;<samp><span class="samp">--target2=type</span></samp>&rsquo; switch overrides the default definition of the
&lsquo;<samp><span class="samp">R_ARM_TARGET2</span></samp>&rsquo; relocation.  Valid values for &lsquo;<samp><span class="samp">type</span></samp>&rsquo;, their
meanings, and target defaults are as follows:
     <dl>
<dt>&lsquo;<samp><span class="samp">rel</span></samp>&rsquo;<dd>&lsquo;<samp><span class="samp">R_ARM_REL32</span></samp>&rsquo; (arm*-*-elf, arm*-*-eabi)
<br><dt>&lsquo;<samp><span class="samp">abs</span></samp>&rsquo;<dd>&lsquo;<samp><span class="samp">R_ARM_ABS32</span></samp>&rsquo; (arm*-*-symbianelf)
<br><dt>&lsquo;<samp><span class="samp">got-rel</span></samp>&rsquo;<dd>&lsquo;<samp><span class="samp">R_ARM_GOT_PREL</span></samp>&rsquo; (arm*-*-linux, arm*-*-*bsd)
</dl>

   <p><a name="index-FIX_005fV4BX-588"></a><a name="index-g_t_002d_002dfix_002dv4bx-589"></a>The &lsquo;<samp><span class="samp">R_ARM_V4BX</span></samp>&rsquo; relocation (defined by the ARM AAELF
specification) enables objects compiled for the ARMv4 architecture to be
interworking-safe when linked with other objects compiled for ARMv4t, but
also allows pure ARMv4 binaries to be built from the same ARMv4 objects.

   <p>In the latter case, the switch <samp><span class="option">--fix-v4bx</span></samp> must be passed to the
linker, which causes v4t <code>BX rM</code> instructions to be rewritten as
<code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction.

   <p>In the former case, the switch should not be used, and &lsquo;<samp><span class="samp">R_ARM_V4BX</span></samp>&rsquo;
relocations are ignored.

   <p><a name="index-FIX_005fV4BX_005fINTERWORKING-590"></a><a name="index-g_t_002d_002dfix_002dv4bx_002dinterworking-591"></a>Replace <code>BX rM</code> instructions identified by &lsquo;<samp><span class="samp">R_ARM_V4BX</span></samp>&rsquo;
relocations with a branch to the following veneer:

<pre class="smallexample">     TST rM, #1
     MOVEQ PC, rM
     BX Rn
</pre>
   <p>This allows generation of libraries/applications that work on ARMv4 cores
and are still interworking safe.  Note that the above veneer clobbers the
condition flags, so may cause incorrect progrm behavior in rare cases.

   <p><a name="index-USE_005fBLX-592"></a><a name="index-g_t_002d_002duse_002dblx-593"></a>The &lsquo;<samp><span class="samp">--use-blx</span></samp>&rsquo; switch enables the linker to use ARM/Thumb
BLX instructions (available on ARMv5t and above) in various
situations. Currently it is used to perform calls via the PLT from Thumb
code using BLX rather than using BX and a mode-switching stub before
each PLT entry. This should lead to such calls executing slightly faster.

   <p>This option is enabled implicitly for SymbianOS, so there is no need to
specify it if you are using that target.

   <p><a name="index-VFP11_005fDENORM_005fFIX-594"></a><a name="index-g_t_002d_002dvfp11_002ddenorm_002dfix-595"></a>The &lsquo;<samp><span class="samp">--vfp11-denorm-fix</span></samp>&rsquo; switch enables a link-time workaround for a
bug in certain VFP11 coprocessor hardware, which sometimes allows
instructions with denorm operands (which must be handled by support code)
to have those operands overwritten by subsequent instructions before
the support code can read the intended values.

   <p>The bug may be avoided in scalar mode if you allow at least one
intervening instruction between a VFP11 instruction which uses a register
and another instruction which writes to the same register, or at least two
intervening instructions if vector mode is in use. The bug only affects
full-compliance floating-point mode: you do not need this workaround if
you are using "runfast" mode. Please contact ARM for further details.

   <p>This workaround is enabled for scalar code by default for
pre-ARMv7 architectures, but disabled by default for later
architectures. If you know you are not using buggy VFP11 hardware,
you can disable the workaround by specifying the linker option
&lsquo;<samp><span class="samp">--vfp-denorm-fix=none</span></samp>&rsquo;. If you are using VFP vector mode, you
should specify &lsquo;<samp><span class="samp">--vfp-denorm-fix=vector</span></samp>&rsquo;.

   <p>If the workaround is enabled, instructions are scanned for
potentially-troublesome sequences, and a veneer is created for each
such sequence which may trigger the erratum. The veneer consists of the
first instruction of the sequence and a branch back to the subsequent
instruction. The original instruction is then replaced with a branch to
the veneer. The extra cycles required to call and return from the veneer
are sufficient to avoid the erratum in both the scalar and vector cases.

   <p><a name="index-NO_005fENUM_005fSIZE_005fWARNING-596"></a><a name="index-g_t_002d_002dno_002denum_002dsize_002dwarning-597"></a>The <samp><span class="option">--no-enum-size-warning</span></samp> switch prevents the linker from
warning when linking object files that specify incompatible EABI
enumeration size attributes.  For example, with this switch enabled,
linking of an object file using 32-bit enumeration values with another
using enumeration values fitted into the smallest possible space will
not be diagnosed.

   <p><a name="index-NO_005fWCHAR_005fSIZE_005fWARNING-598"></a><a name="index-g_t_002d_002dno_002dwchar_002dsize_002dwarning-599"></a>The <samp><span class="option">--no-wchar-size-warning</span></samp> switch prevents the linker from
warning when linking object files that specify incompatible EABI
<code>wchar_t</code> size attributes.  For example, with this switch enabled,
linking of an object file using 32-bit <code>wchar_t</code> values with another
using 16-bit <code>wchar_t</code> values will not be diagnosed.

   <p><a name="index-PIC_005fVENEER-600"></a><a name="index-g_t_002d_002dpic_002dveneer-601"></a>The &lsquo;<samp><span class="samp">--pic-veneer</span></samp>&rsquo; switch makes the linker use PIC sequences for
ARM/Thumb interworking veneers, even if the rest of the binary
is not PIC.  This avoids problems on uClinux targets where
&lsquo;<samp><span class="samp">--emit-relocs</span></samp>&rsquo; is used to generate relocatable binaries.

   <p><a name="index-STUB_005fGROUP_005fSIZE-602"></a><a name="index-g_t_002d_002dstub_002dgroup_002dsize_003d_0040var_007bN_007d-603"></a>The linker will automatically generate and insert small sequences of
code into a linked ARM ELF executable whenever an attempt is made to
perform a function call to a symbol that is too far away.  The
placement of these sequences of instructions - called stubs - is
controlled by the command line option <samp><span class="option">--stub-group-size=N</span></samp>. 
The placement is important because a poor choice can create a need for
duplicate stubs, increasing the code sizw.  The linker will try to
group stubs together in order to reduce interruptions to the flow of
code, but it needs guidance as to how big these groups should be and
where they should be placed.

   <p>The value of &lsquo;<samp><span class="samp">N</span></samp>&rsquo;, the parameter to the
<samp><span class="option">--stub-group-size=</span></samp> option controls where the stub groups are
placed.  If it is negative then all stubs are placed after the first
branch that needs them.  If it is positive then the stubs can be
placed either before or after the branches that need them.  If the
value of &lsquo;<samp><span class="samp">N</span></samp>&rsquo; is 1 (either +1 or -1) then the linker will choose
exactly where to place groups of stubs, using its built in heuristics. 
A value of &lsquo;<samp><span class="samp">N</span></samp>&rsquo; greater than 1 (or smaller than -1) tells the
linker that a single group of stubs can service at most &lsquo;<samp><span class="samp">N</span></samp>&rsquo; bytes
from the input sections.

   <p>The default, if <samp><span class="option">--stub-group-size=</span></samp> is not specified, is
&lsquo;<samp><span class="samp">N = +1</span></samp>&rsquo;.

   <p>Farcalls stubs insertion is fully supported for the ARM-EABI target
only, because it relies on object files properties not present
otherwise.

   <p><a name="index-Cortex_002dA8-erratum-workaround-604"></a><a name="index-g_t_002d_002dfix_002dcortex_002da8-605"></a><a name="index-g_t_002d_002dno_002dfix_002dcortex_002da8-606"></a>The &lsquo;<samp><span class="samp">--fix-cortex-a8</span></samp>&rsquo; switch enables a link-time workaround for an erratum in certain Cortex-A8 processors.  The workaround is enabled by default if you are targeting the ARM v7-A architecture profile.  It can be enabled otherwise by specifying &lsquo;<samp><span class="samp">--fix-cortex-a8</span></samp>&rsquo;, or disabled unconditionally by specifying &lsquo;<samp><span class="samp">--no-fix-cortex-a8</span></samp>&rsquo;.

   <p>The erratum only affects Thumb-2 code.  Please contact ARM for further details.

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