#
# Unit masks for the Intel "Haswell" micro architecture
#
# See http://ark.intel.com/ for help in identifying Haswell based CPUs
#
include:i386/arch_perfmon
name:x02 type:mandatory default:0x2
	0x2 No unit mask
name:x03 type:mandatory default:0x3
	0x3 No unit mask
name:x1f type:mandatory default:0x1f
	0x1f No unit mask
name:x20 type:mandatory default:0x20
	0x20 No unit mask
name:x50 type:mandatory default:0x50
	0x50 No unit mask
name:misalign_mem_ref type:exclusive default:0x1
	0x1 extra: loads Speculative cache line split load uops dispatched to L1 cache
	0x2 extra: stores Speculative cache line split STA uops dispatched to L1 cache
name:dtlb_load_misses type:exclusive default:0x1
	0x1 extra: miss_causes_a_walk Load misses in all DTLB levels that cause page walks
	0xe extra: walk_completed  Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
	0x2 extra: walk_completed_4k Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).
	0x4 extra: walk_completed_2m_4m Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).
	0x10 extra: walk_duration Cycles when PMH is busy with page walks
	0x60 extra: stlb_hit Load operations that miss the first DTLB level but hit the second and do not cause page walks
	0x20 extra: stlb_hit_4k Load misses that miss the  DTLB and hit the STLB (4K)
	0x40 extra: stlb_hit_2m Load misses that miss the  DTLB and hit the STLB (2M)
	0x80 extra: pde_cache_miss DTLB demand load misses with low part of linear-to-physical address translation missed
name:uops_issued type:exclusive default:any
	0x1 extra: any Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)
	0x10 extra: flags_merge Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.
	0x20 extra: slow_lea Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
	0x40 extra: single_mul Number of Multiply packed/scalar single precision uops allocated
	0x1 extra:cmask=1,inv stall_cycles Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
	0x1 extra:cmask=1,inv,any core_stall_cycles Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads
name:l2_rqsts type:exclusive default:0x21
	0x21 extra: demand_data_rd_miss Demand Data Read miss L2, no rejects
	0x41 extra: demand_data_rd_hit Demand Data Read requests that hit L2 cache
	0x30 extra: l2_pf_miss L2 prefetch requests that miss L2 cache
	0x50 extra: l2_pf_hit L2 prefetch requests that hit L2 cache
	0xe1 extra: all_demand_data_rd Demand Data Read requests
	0xe2 extra: all_rfo RFO requests to L2 cache
	0xe4 extra: all_code_rd L2 code requests
	0xf8 extra: all_pf Requests from L2 hardware prefetchers
	0x42 extra: rfo_hit RFO requests that hit L2 cache
	0x22 extra: rfo_miss RFO requests that miss L2 cache
	0x44 extra: code_rd_hit L2 cache hits when fetching instructions, code reads.
	0x24 extra: code_rd_miss L2 cache misses when fetching instructions
	0x27 extra: all_demand_miss  Demand requests that miss L2 cache
	0xe7 extra: all_demand_references  Demand requests to L2 cache
	0x3f extra: miss  All requests that miss L2 cache
	0xff extra: references   All L2 requests
name:l1d_pend_miss type:exclusive default:pending
	0x1 extra: pending L1D miss oustandings duration in cycles
	0x1 extra:cmask=1 pending_cycles Cycles with L1D load Misses outstanding.
	0x1 extra:cmask=1,edge occurences This event counts the number of L1D misses outstanding, using an edge detect to count transitions.
name:dtlb_store_misses type:exclusive default:0x1
	0x1 extra: miss_causes_a_walk Store misses in all DTLB levels that cause page walks
	0xe extra: walk_completed Store misses in all DTLB levels that cause completed page walks
	0x2 extra: walk_completed_4k  Store miss in all TLB levels causes a page walk that completes. (4K)
	0x4 extra: walk_completed_2m_4m Store misses in all DTLB levels that cause completed page walks (2M/4M)
	0x10 extra: walk_duration Cycles when PMH is busy with page walks
	0x60 extra: stlb_hit Store operations that miss the first TLB level but hit the second and do not cause page walks
	0x20 extra: stlb_hit_4k Store misses that miss the  DTLB and hit the STLB (4K)
	0x40 extra: stlb_hit_2m Store misses that miss the  DTLB and hit the STLB (2M)
	0x80 extra: pde_cache_miss DTLB store misses with low part of linear-to-physical address translation missed
name:load_hit_pre type:exclusive default:0x1
	0x1 extra: sw_pf Not software-prefetch load dispatches that hit FB allocated for software prefetch
	0x2 extra: hw_pf Not software-prefetch load dispatches that hit FB allocated for hardware prefetch
name:tx_mem type:exclusive default:0x1
	0x1 extra: abort_conflict Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address
	0x2 extra: abort_capacity Number of times a transactional abort was signaled due to a data capacity limitation
	0x4 extra: abort_hle_store_to_elided_lock Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer
	0x8 extra: abort_hle_elision_buffer_not_empty Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.
	0x10 extra: abort_hle_elision_buffer_mismatch Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.
	0x20 extra: abort_hle_elision_buffer_unsupported_alignment Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.
	0x40 extra: abort_hle_elision_buffer_full Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.
name:move_elimination type:exclusive default:0x1
	0x1 extra: int_eliminated Number of integer Move Elimination candidate uops that were eliminated.
	0x2 extra: simd_eliminated Number of SIMD Move Elimination candidate uops that were eliminated.
	0x4 extra: int_not_eliminated Number of integer Move Elimination candidate uops that were not eliminated.
	0x8 extra: simd_not_eliminated Number of SIMD Move Elimination candidate uops that were not eliminated.
name:cpl_cycles type:exclusive default:ring0
	0x1 extra: ring0 Unhalted core cycles when the thread is in ring 0
	0x2 extra: ring123 Unhalted core cycles when thread is in rings 1, 2, or 3
	0x1 extra:cmask=1,edge ring0_trans Number of intervals between processor halts while thread is in ring 0
name:tx_exec type:exclusive default:0x1
	0x1 extra: misc1 Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution it may not always cause a transactional abort.
	0x2 extra: misc2 Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region
	0x4 extra: misc3 Counts the number of times an instruction execution caused the nest count supported to be exceeded
	0x8 extra: misc4 Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region
name:lock_cycles type:exclusive default:0x1
	0x1 extra: split_lock_uc_lock_duration Cycles when L1 and L2 are locked due to UC or split lock
	0x2 extra: cache_lock_duration Cycles when L1D is locked
name:idq type:exclusive default:0x2
	0x2 extra: empty Instruction Decode Queue (IDQ) empty cycles
	0x4 extra: mite_uops Uops delivered to Instruction Decode Queue (IDQ) from MITE path
	0x8 extra: dsb_uops Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
	0x10 extra: ms_dsb_uops Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
	0x20 extra: ms_mite_uops Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
	0x30 extra: ms_uops Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
	0x30 extra:cmask=1 ms_cycles Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
	0x4 extra:cmask=1 mite_cycles Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
	0x8 extra:cmask=1 dsb_cycles Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
	0x10 extra:cmask=1 ms_dsb_cycles Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
	0x10 extra:cmask=1,edge ms_dsb_occur Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy
	0x18 extra:cmask=4 all_dsb_cycles_4_uops Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
	0x18 extra:cmask=1 all_dsb_cycles_any_uops Cycles Decode Stream Buffer (DSB) is delivering any Uop
	0x24 extra:cmask=4 all_mite_cycles_4_uops Cycles MITE is delivering 4 Uops
	0x24 extra:cmask=1 all_mite_cycles_any_uops Cycles MITE is delivering any Uop
	0x3c extra: mite_all_uops Uops delivered to Instruction Decode Queue (IDQ) from MITE path
name:itlb_misses type:exclusive default:0x1
	0x1 extra: miss_causes_a_walk Misses at all ITLB levels that cause page walks
	0xe extra: walk_completed Misses in all ITLB levels that cause completed page walks
	0x2 extra: walk_completed_4k Code miss in all TLB levels causes a page walk that completes. (4K)
	0x4 extra: walk_completed_2m_4m Code miss in all TLB levels causes a page walk that completes. (2M/4M)
	0x10 extra: walk_duration Cycles when PMH is busy with page walks
	0x60 extra: stlb_hit Operations that miss the first ITLB level but hit the second and do not cause any page walks
	0x20 extra: stlb_hit_4k Core misses that miss the  DTLB and hit the STLB (4K)
	0x40 extra: stlb_hit_2m Code misses that miss the  DTLB and hit the STLB (2M)
name:ild_stall type:exclusive default:0x1
	0x1 extra: lcp Stalls caused by changing prefix length of the instruction.
	0x4 extra: iq_full Stall cycles because IQ is full
name:br_inst_exec type:exclusive default:0xff
	0xff extra: all_branches Speculative and retired  branches
	0x41 extra: nontaken_conditional Not taken macro-conditional branches
	0x81 extra: taken_conditional Taken speculative and retired macro-conditional branches
	0x82 extra: taken_direct_jump Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
	0x84 extra: taken_indirect_jump_non_call_ret Taken speculative and retired indirect branches excluding calls and returns
	0x88 extra: taken_indirect_near_return Taken speculative and retired indirect branches with return mnemonic
	0x90 extra: taken_direct_near_call Taken speculative and retired direct near calls
	0xa0 extra: taken_indirect_near_call Taken speculative and retired indirect calls
	0xc1 extra: all_conditional Speculative and retired macro-conditional branches
	0xc2 extra: all_direct_jmp Speculative and retired macro-unconditional branches excluding calls and indirects
	0xc4 extra: all_indirect_jump_non_call_ret Speculative and retired indirect branches excluding calls and returns
	0xc8 extra: all_indirect_near_return Speculative and retired indirect return branches.
	0xd0 extra: all_direct_near_call Speculative and retired direct near calls
name:br_misp_exec type:exclusive default:0xff
	0xff extra: all_branches Speculative and retired mispredicted macro conditional branches
	0x41 extra: nontaken_conditional Not taken speculative and retired mispredicted macro conditional branches
	0x81 extra: taken_conditional Taken speculative and retired mispredicted macro conditional branches
	0x84 extra: taken_indirect_jump_non_call_ret Taken speculative and retired mispredicted indirect branches excluding calls and returns
	0x88 extra: taken_return_near Taken speculative and retired mispredicted indirect branches with return mnemonic
	0xc1 extra: all_conditional Speculative and retired mispredicted macro conditional branches
	0xc4 extra: all_indirect_jump_non_call_ret Mispredicted indirect branches excluding calls and returns
	0xa0 extra: taken_indirect_near_call Taken speculative and retired mispredicted indirect calls
name:idq_uops_not_delivered type:exclusive default:core
	0x1 extra: core Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled
	0x1 extra:cmask=4 cycles_0_uops_deliv_core Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
	0x1 extra:cmask=3 cycles_le_1_uop_deliv_core Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 
	0x1 extra:cmask=2 cycles_le_2_uop_deliv_core Cycles with less than 2 uops delivered by the front end.
	0x1 extra:cmask=1 cycles_le_3_uop_deliv_core Cycles with less than 3 uops delivered by the front end.
	0x1 extra:cmask=1,inv cycles_fe_was_ok Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
name:uops_executed_port type:exclusive default:port_0
	0x1 extra: port_0 Cycles per thread when uops are executed in port 0
	0x2 extra: port_1 Cycles per thread when uops are executed in port 1
	0x4 extra: port_2 Cycles per thread when uops are executed in port 2
	0x8 extra: port_3 Cycles per thread when uops are executed in port 3
	0x10 extra: port_4 Cycles per thread when uops are executed in port 4
	0x20 extra: port_5 Cycles per thread when uops are executed in port 5
	0x40 extra: port_6 Cycles per thread when uops are executed in port 6
	0x80 extra: port_7 Cycles per thread when uops are executed in port 7
	0x1 extra:any port_0_core Cycles per core when uops are exectuted in port 0
	0x2 extra:any port_1_core Cycles per core when uops are exectuted in port 1
	0x4 extra:any port_2_core Cycles per core when uops are dispatched to port 2
	0x8 extra:any port_3_core Cycles per core when uops are dispatched to port 3
	0x10 extra:any port_4_core Cycles per core when uops are exectuted in port 4
	0x20 extra:any port_5_core Cycles per core when uops are exectuted in port 5
	0x40 extra:any port_6_core Cycles per core when uops are exectuted in port 6
	0x80 extra:any port_7_core Cycles per core when uops are dispatched to port 7
name:resource_stalls type:exclusive default:0x1
	0x1 extra: any Resource-related stall cycles
	0x4 extra: rs Cycles stalled due to no eligible RS entry available.
	0x8 extra: sb Cycles stalled due to no store buffers available. (not including draining form sync).
	0x10 extra: rob Cycles stalled due to re-order buffer full.
name:cycle_activity type:exclusive default:0x8
	0x8 extra:cmask=8 cycles_l1d_pending Cycles with pending L1 cache miss loads.
	0x2 extra:cmask=2 cycles_ldm_pending Cycles with pending memory loads.
	0x4 extra:cmask=4 cycles_no_execute Total execution stalls
	0x6 extra:cmask=6 stalls_ldm_pending Execution stalls due to memory subsystem.
name:offcore_requests type:exclusive default:0x2
	0x2 extra: demand_code_rd Cacheable and noncachaeble code read requests
	0x4 extra: demand_rfo Demand RFO requests including regular RFOs, locks, ItoM
	0x8 extra: all_data_rd Demand and prefetch data reads
name:uops_executed type:exclusive default:thread
	0x1 extra: thread Counts the number of uops to be executed per-thread each cycle.
	0x2 extra: core Number of uops executed on the core.
	0x1 extra:cmask=1,inv stall_cycles Counts number of cycles no uops were dispatched to be executed on this thread.
	0x1 extra:cmask=1,inv cycles_ge_1_uop_exec Cycles where at least 1 uop was executed per-thread
	0x1 extra:cmask=1,inv cycles_ge_2_uops_exec Cycles where at least 2 uops were executed per-thread
	0x1 extra:cmask=1,inv cycles_ge_3_uops_exec Cycles where at least 3 uops were executed per-thread
	0x1 extra:cmask=1,inv cycles_ge_4_uops_exec Cycles where at least 4 uops were executed per-thread
name:page_walker_loads type:exclusive default:0x11
	0x11 extra: ia32_dtlb_l1 Number of DTLB page walker hits in the L1+FB
	0x21 extra: ia32_itlb_l1 Number of ITLB page walker hits in the L1+FB
	0x12 extra: ia32_dtlb_l2 Number of DTLB page walker hits in the L2
	0x22 extra: ia32_itlb_l2 Number of ITLB page walker hits in the L2
	0x14 extra: ia32_dtlb_l3 Number of DTLB page walker hits in the L3 + XSNP
	0x24 extra: ia32_itlb_l3 Number of ITLB page walker hits in the L3 + XSNP
	0x18 extra: ia32_dtlb_memory Number of DTLB page walker hits in Memory
	0x28 extra: ia32_itlb_memory Number of ITLB page walker hits in Memory
name:tlb_flush type:exclusive default:0x1
	0x1 extra: dtlb_thread DTLB flush attempts of the thread-specific entries
	0x20 extra: stlb_any STLB flush attempts
name:other_assists type:exclusive default:0x8
	0x8 extra: avx_to_sse Number of transitions from AVX-256 to legacy SSE when penalty applicable.
	0x10 extra: sse_to_avx Number of transitions from SSE to AVX-256 when penalty applicable.
	0x40 extra: any_wb_assist Number of times any microcode assist is invoked by HW upon uop writeback.
name:uops_retired type:exclusive default:all
	0x1 extra: all Actually retired uops. 
	0x2 extra: retire_slots Retirement slots used. 
	0x1 extra:pebs all_ps Actually retired uops. (Precise Event - PEBS)
	0x2 extra:pebs retire_slots_ps Retirement slots used. (Precise Event - PEBS)
	0x1 extra:cmask=1,inv stall_cycles Cycles without actually retired uops. 
	0x1 extra:cmask=10,inv total_cycles Cycles with less than 10 actually retired uops. 
	0x1 extra:cmask=1,inv,any core_stall_cycles Cycles without actually retired uops. 
name:machine_clears type:exclusive default:0x2
	0x2 extra: memory_ordering Counts the number of machine clears due to memory order conflicts.
	0x4 extra: smc Self-modifying code (SMC) detected.
	0x20 extra: maskmov This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. 
name:br_inst_retired type:exclusive default:all_branches_ps
	0x1 extra: conditional Conditional branch instructions retired. 
	0x2 extra: near_call Direct and indirect near call instructions retired. 
	0x8 extra: near_return Return instructions retired. 
	0x10 extra: not_taken Not taken branch instructions retired. 
	0x20 extra: near_taken Taken branch instructions retired. 
	0x40 extra: far_branch Far branch instructions retired. 
	0x1 extra:pebs conditional_ps Conditional branch instructions retired. (Precise Event - PEBS)
	0x2 extra:pebs near_call_ps Direct and indirect near call instructions retired. (Precise Event - PEBS)
	0x4 extra:pebs all_branches_ps All (macro) branch instructions retired. (Precise Event - PEBS)
	0x8 extra:pebs near_return_ps Return instructions retired. (Precise Event - PEBS)
	0x20 extra:pebs near_taken_ps Taken branch instructions retired. (Precise Event - PEBS)
	0x2 extra: near_call_r3 Direct and indirect macro near call instructions retired (captured in ring 3). 
	0x2 extra:pebs near_call_r3_ps Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)
name:br_misp_retired type:exclusive default:all_branches_ps
	0x1 extra: conditional Mispredicted conditional branch instructions retired. 
	0x1 extra:pebs conditional_ps Mispredicted conditional branch instructions retired. (Precise Event - PEBS)
	0x4 extra:pebs all_branches_ps Mispredicted macro branch instructions retired. (Precise Event - PEBS)
	0x20 extra: near_taken number of near branch instructions retired that were mispredicted and taken. 
	0x20 extra:pebs near_taken_ps number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS)
name:hle_retired type:exclusive default:0x1
	0x1 extra: start Number of times an HLE execution started.
	0x2 extra: commit Number of times an HLE execution successfully committed
	0x4 extra: aborted Number of times an HLE execution aborted due to any reasons (multiple categories may count as one)
	0x8 extra: aborted_misc1 Number of times an HLE execution aborted due to 1 various memory events
	0x10 extra: aborted_misc2 Number of times an HLE execution aborted due to uncommon conditions
	0x20 extra: aborted_misc3 Number of times an HLE execution aborted due to HLE-unfriendly instructions
	0x40 extra: aborted_misc4 Number of times an HLE execution aborted due to incompatible memory type
	0x80 extra: aborted_misc5 Number of times an HLE execution aborted due to none of the previous categories (e.g. interrupt)
name:rtm_retired type:exclusive default:0x1
	0x1 extra: start Number of times an RTM execution started.
	0x2 extra: commit Number of times an RTM execution successfully committed
	0x4 extra: aborted Number of times an RTM execution aborted due to any reasons (multiple categories may count as one)
	0x8 extra: aborted_misc1 Number of times an RTM execution aborted due to various memory events
	0x10 extra: aborted_misc2 Number of times an RTM execution aborted due to uncommon conditions
	0x20 extra: aborted_misc3 Number of times an RTM execution aborted due to HLE-unfriendly instructions
	0x40 extra: aborted_misc4 Number of times an RTM execution aborted due to incompatible memory type
	0x80 extra: aborted_misc5 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)
name:fp_assist type:exclusive default:0x1e
	0x1e extra:cmask=1 any Cycles with any input/output SSE or FP assist
	0x2 extra: x87_output Number of X87 assists due to output value.
	0x4 extra: x87_input Number of X87 assists due to input value.
	0x8 extra: simd_output Number of SIMD FP assists due to Output values
	0x10 extra: simd_input Number of SIMD FP assists due to input values
name:mem_uops_retired type:exclusive default:all_loads
	0x11 extra: stlb_miss_loads Load uops with true STLB miss retired to architected path. 
	0x12 extra: stlb_miss_stores Store uops with true STLB miss retired to architected path. 
	0x21 extra: lock_loads Load uops with locked access retired to architected path. 
	0x41 extra: split_loads Line-splitted load uops retired to architected path. 
	0x42 extra: split_stores Line-splitted store uops retired to architected path. 
	0x81 extra: all_loads Load uops retired to architected path with filter on bits 0 and 1 applied. 
	0x82 extra: all_stores Store uops retired to architected path with filter on bits 0 and 1 applied. 
	0x11 extra:pebs stlb_miss_loads_ps Load uops with true STLB miss retired to architected path. (Precise Event - PEBS)
	0x12 extra:pebs stlb_miss_stores_ps Store uops true STLB miss retired to architected path. (Precise Event - PEBS)
	0x21 extra:pebs lock_loads_ps Load uops with locked access retired to architected path. (Precise Event - PEBS)
	0x41 extra:pebs split_loads_ps Line-splitted load uops retired to architected path. (Precise Event - PEBS)
	0x42 extra:pebs split_stores_ps Line-splitted store uops retired to architected path. (Precise Event - PEBS)
	0x81 extra:pebs all_loads_ps Load uops retired to architected path with filter on bits 0 and 1 applied. (Precise Event - PEBS)
	0x82 extra:pebs all_stores_ps Store uops retired to architected path with filter on bits 0 and 1 applied. (Precise Event - PEBS)
name:mem_load_uops_retired type:exclusive default:l1_hit
	0x1 extra: l1_hit Retired load uops with L1 cache hits as data sources. 
	0x2 extra: l2_hit Retired load uops with L2 cache hits as data sources. 
	0x4 extra: l3_hit Retired load uops which data sources were data hits in LLC without snoops required. 
	0x10 extra: l2_miss Miss in mid-level (L2) cache. Excludes Unknown data-source.
	0x40 extra: hit_lfb Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. 
	0x1 extra:pebs l1_hit_ps Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)
	0x2 extra:pebs l2_hit_ps Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)
	0x4 extra:pebs l3_hit_ps Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)
	0x40 extra:pebs hit_lfb_ps Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)
name:mem_load_uops_l3_hit_retired type:exclusive default:xsnp_miss
	0x1 extra: xsnp_miss Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. 
	0x2 extra: xsnp_hit Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. 
	0x4 extra: xsnp_hitm Retired load uops which data sources were HitM responses from shared LLC. 
	0x8 extra: xsnp_none Retired load uops which data sources were hits in LLC without snoops required. 
	0x1 extra:pebs xsnp_miss_ps Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)
	0x2 extra:pebs xsnp_hit_ps Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)
	0x4 extra:pebs xsnp_hitm_ps Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS)
	0x8 extra:pebs xsnp_none_ps Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS)
name:l2_trans type:exclusive default:0x80
	0x80 extra: all_requests Transactions accessing L2 pipe
	0x1 extra: demand_data_rd Demand Data Read requests that access L2 cache
	0x2 extra: rfo RFO requests that access L2 cache
	0x4 extra: code_rd L2 cache accesses when fetching instructions
	0x8 extra: all_pf L2 or LLC HW prefetches that access L2 cache
	0x10 extra: l1d_wb L1D writebacks that access L2 cache
	0x20 extra: l2_fill L2 fill requests that access L2 cache
	0x40 extra: l2_wb L2 writebacks that access L2 cache
name:l2_lines_in type:exclusive default:0x7
	0x7 extra: all L2 cache lines filling L2
	0x1 extra: i L2 cache lines in I state filling L2
	0x2 extra: s L2 cache lines in S state filling L2
	0x4 extra: e L2 cache lines in E state filling L2
name:l2_lines_out type:exclusive default:0x5
	0x5 extra: demand_clean Clean L2 cache lines evicted by demand
	0x6 extra: demand_dirty Dirty L2 cache lines evicted by demand