# TILEPro Events

event:0x00 counters:0,1,2,3 um:zero minimum:500 name:ZERO : Always zero - no event ever happens
event:0x01 counters:0,1,2,3 um:zero minimum:20000 name:ONE : Always one - an event occurs every cycle
event:0x02 counters:0,1,2,3 um:zero minimum:500 name:PASS_WRITTEN : The event indicates that the PASS SPR was written
event:0x03 counters:0,1,2,3 um:zero minimum:500 name:FAIL_WRITTEN : The event indicates that the FAIL SPR was written
event:0x04 counters:0,1,2,3 um:zero minimum:500 name:DONE_WRITTEN : The event indicates that the DONE SPR was written
event:0x06 counters:0,1,2,3 um:zero minimum:500 name:MP_BUNDLE_RETIRED : The event occurs when instruction bundle is retired.
event:0x07 counters:0,1,2,3 um:zero minimum:500 name:MP_BUNDLE_1_INSTR_RETIRED : The event occurs when an instruction bundle containing one valid instruction is retired.
event:0x08 counters:0,1,2,3 um:zero minimum:500 name:MP_BUNDLE_2_INSTR_RETIRED : The event occurs when an instruction bundle containing two valid instructions is retired.
event:0x09 counters:0,1,2,3 um:zero minimum:500 name:MP_BUNDLE_3_INSTR_RETIRED : The event occurs when an instruction bundle containing three valid instructions is retired.
event:0x0a counters:0,1,2,3 um:zero minimum:500 name:MP_UDN_READ_STALL : An event occurs every cycle that an instruction bundle is stalled on a UDN read. Multiple stall events may occur and be counted during the same cycle.
event:0x0b counters:0,1,2,3 um:zero minimum:500 name:MP_IDN_READ_STALL : An event occurs every cycle that an instruction bundle is stalled on a IDN read. Multiple stall events may occur and be counted during the same cycle.
event:0x0c counters:0,1,2,3 um:zero minimum:500 name:MP_SN_READ_STALL : An event occurs every cycle that an instruction bundle is stalled on a STN read. Multiple stall events may occur and be counted during the same cycle.
event:0x0d counters:0,1,2,3 um:zero minimum:500 name:MP_UDN_WRITE_STALL : An event occurs every cycle that an instruction bundle is stalled on a UDN write. Multiple stall events may occur and be counted during the same cycle.
event:0x0e counters:0,1,2,3 um:zero minimum:500 name:MP_IDN_WRITE_STALL : An event occurs every cycle that an instruction bundle is stalled on a IDN write. Multiple stall events may occur and be counted during the same cycle.
event:0x0f counters:0,1,2,3 um:zero minimum:500 name:MP_SN_WRITE_STALL : An event occurs every cycle that an instruction bundle is stalled on a STN write. Multiple stall events may occur and be counted during the same cycle.
event:0x10 counters:0,1,2,3 um:zero minimum:500 name:MP_DATA_CACHE_STALL : An event occurs every cycle that an instruction bundle is stalled on a data memory operation except for the cycles when a replay trap is being performed. Instructions that depend on the result of a load and are fired speculatively cause a reply trap if the request misses the L1 data cache and thus are not counted. The wait is 4 if the consumer of the load immediately follows the load or 3 if there is a cycle between the load issue and the consumer issue. Multiple stall events may occur and be counted during the same cycle.
event:0x11 counters:0,1,2,3 um:zero minimum:500 name:MP_INSTRUCTION_CACHE_STALL : An event occurs every cycle that an instruction bundle is stalled on a instruction memory operation. Multiple stall events may occur and be counted during the same cycle.
event:0x12 counters:0,1,2,3 um:zero minimum:500 name:MP_ICACHE_HIT_ISSUED : The event occurs when the fetch of an issued instruction hits the L1 Instruction cache.
event:0x13 counters:0,1,2,3 um:zero minimum:500 name:MP_ITLB_HIT_ISSUED : The event occurs when the fetch of an issued instruction hits the instruction TLB.
event:0x14 counters:0,1,2,3 um:zero minimum:500 name:MP_CONDITIONAL_BRANCH_MISSPREDICT : The event occurs when a conditional branch is misspredicted.
event:0x15 counters:0,1,2,3 um:zero minimum:500 name:MP_INDIRECT_BRANCH_MISSPREDICT : The event occurs when a register indirect branch is misspredicted.
event:0x16 counters:0,1,2,3 um:zero minimum:500 name:MP_CONDITIONAL_BRANCH_ISSUED : The event occurs when a conditional branch is issued.
event:0x17 counters:0,1,2,3 um:zero minimum:500 name:MP_INDIRECT_BRANCH_ISSUED : The event occurs when a register indirect branch is issued.
event:0x18 counters:0,1,2,3 um:zero minimum:500 name:MP_CACHE_BUSY_STALL : The event occurs when the cache system is busy, and a memory operation cannot be issued.
event:0x19 counters:0,1,2,3 um:zero minimum:500 name:MP_NAP_STALL : The event occurs every cycle a processor is stalled due to a nap instruction.
event:0x1a counters:0,1,2,3 um:zero minimum:500 name:MP_SPR_STALL : The event occurs every cycle a processor is stalled when executing an instruction that reads or writes an SPR.
event:0x1b counters:0,1,2,3 um:zero minimum:500 name:MP_ALU_STALL : The event occurs every cycle a processor is stalled because an operand is not available due to an arithmetic operation. For example, this event will occur when an instruction consuming the result of a multiply stall for one cycle waiting for the multiply result.
event:0x1c counters:0,1,2,3 um:zero minimum:500 name:MP_LOAD_MISS_REPLAY_TRAP : The event occurs every time an instruction consuming the result of a load issues within two cycles of the load instruction, and the load instruction misses in the L1 data cache.
event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TLB_CNT : The event occurs when a data memory operation is issued and the data translation lookaside buffer (DTLB) is used to translate the virtual address into the physical address.
event:0x1e counters:0,1,2,3 um:zero minimum:500 name:RD_CNT : The event occurs when a load is issued.
event:0x1f counters:0,1,2,3 um:zero minimum:500 name:WR_CNT : The event occurs when a store is issed.
event:0x20 counters:0,1,2,3 um:zero minimum:500 name:TLB_EXCEPTION : The event occurs when the address of a data stream memory operation causes a Data TLB Exception including TLB Misses and protection violations.
event:0x21 counters:0,1,2,3 um:zero minimum:500 name:RD_MISS : The event occurs when a load is issued and data is not returned from the level 1 data cache.
event:0x22 counters:0,1,2,3 um:zero minimum:500 name:WR_MISS : The event occurs when a store is issued and the 16-byte aligned block (level 1 data cache line size) containing the address is not present at the level 1 data cache.
event:0x23 counters:0,1,2,3 um:zero minimum:500 name:SNP_INC_RD_CNT : The event occurs when a read request is received from another Tile off the TDN and the Level 3 cache will track the share state.
event:0x24 counters:0,1,2,3 um:zero minimum:500 name:SNP_NINC_RD_CNT : The event occurs when a read request is received from another Tile off the TDN and the Level 3 cache will not track the share state.
event:0x25 counters:0,1,2,3 um:zero minimum:500 name:SNP_WR_CNT : The event occurs when a write (store or test-and-set) request is received from another Tile off the TDN.
event:0x26 counters:0,1,2,3 um:zero minimum:500 name:SNP_IO_RD_CNT : The event occurs when a read request is received from an IO device off the TDN.
event:0x27 counters:0,1,2,3 um:zero minimum:500 name:SNP_IO_WR_CNT : The event occurs when a write request is received from an IO device off the TDN.
event:0x28 counters:0,1,2,3 um:zero minimum:500 name:LOCAL_DRD_CNT : The event occurs when a data read request is received from the main processor and the Level 3 cache resides in the Tile.
event:0x29 counters:0,1,2,3 um:zero minimum:500 name:LOCAL_WR_CNT : The event occurs when a write (store or test-and-set) request is received from the main processor and the Level 3 cache resides in the Tile.
event:0x2a counters:0,1,2,3 um:zero minimum:500 name:LOCAL_IRD_CNT : The event occurs when an instruction read request is received from the main processor and the Level 3 cache resides in the Tile.
event:0x2b counters:0,1,2,3 um:zero minimum:500 name:REMOTE_DRD_CNT : The event occurs when a data read request is received from the main processor and the Level 3 cache resides in another Tile.
event:0x2c counters:0,1,2,3 um:zero minimum:500 name:REMOTE_WR_CNT : The event occurs when a write (store or test-and-set) request is received from the main processor and the Level 3 cache resides in another Tile.
event:0x2d counters:0,1,2,3 um:zero minimum:500 name:REMOTE_IRD_CNT : The event occurs when an instruction read request is received from the main processor and the Level 3 cache resides in another Tile.
event:0x2e counters:0,1,2,3 um:zero minimum:500 name:COH_INV_CNT : The event occurs when a coherence invalidation is received from another Tile off the VDN.
event:0x2f counters:0,1,2,3 um:zero minimum:500 name:SNP_INC_RD_MISS : The event occurs when a read request is received from another Tile off the TDN and misses the Level 3 cache. The level 3 cache will track the share state.
event:0x30 counters:0,1,2,3 um:zero minimum:500 name:SNP_NINC_RD_MISS : The event occurs when a read request is received from another Tile off the TDN and misses the Level 3 cache. The Level 3 cache will not track the share state.
event:0x31 counters:0,1,2,3 um:zero minimum:500 name:SNP_WR_MISS : The event occurs when a write (store or test-and-set) request is received from another Tile off the TDN and misses the Level 3 cache.
event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SNP_IO_RD_MISS : The event occurs when a read request is received from an IO device off the TDN and misses the Level 3 cache.
event:0x33 counters:0,1,2,3 um:zero minimum:500 name:SNP_IO_WR_MISS : The event occurs when a write request is received from an IO device off the TDN and misses the Level 3 cache.
event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOCAL_DRD_MISS : The event occurs when a data read request is received from the main processor and misses the Level 3 cache resided in the Tile.
event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOCAL_WR_MISS : The event occurs when a write (store or test-and-set) request is received from the main processor and misses the Level 3 cache resided in the Tile.
event:0x36 counters:0,1,2,3 um:zero minimum:500 name:LOCAL_IRD_MISS : The event occurs when an instruction read request is received from the main processor and misses the Level 3 cache resided in the Tile.
event:0x37 counters:0,1,2,3 um:zero minimum:500 name:REMOTE_DRD_MISS : The event occurs when a data read request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile.
event:0x38 counters:0,1,2,3 um:zero minimum:500 name:REMOTE_WR_MISS : The event occurs when a write (store or test-and-set) request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile.
event:0x39 counters:0,1,2,3 um:zero minimum:500 name:REMOTE_IRD_MISS : The event occurs when an instruction read request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile.
event:0x3a counters:0,1,2,3 um:zero minimum:500 name:COH_INV_HIT : The event occurs when a coherence invalidation is received from another Tile off the VDN and hits the level 2 cache.
event:0x3b counters:0,1,2,3 um:zero minimum:500 name:VIC_WB_CNT : The event occurs when a cache writeback to main memory, including victim writes or explicit flushes, leaves the Tile.
event:0x3c counters:0,1,2,3 um:zero minimum:500 name:TDN_STARVED : The event occurs when a snoop is received and the controller enters the TDN starved condition.
event:0x3d counters:0,1,2,3 um:zero minimum:500 name:DMA_STARVED : The event occurs when a DMA is received and the controller enters the starved condition.
event:0x3e counters:0,1,2,3 um:zero minimum:500 name:MDN_STARVED : The event occurs when the controller enters the MDN or VDN starved condition.
event:0x3f counters:0,1,2,3 um:zero minimum:500 name:RTF_STARVED : The event occurs when the controller enters the re-try FIFO starved condition.
event:0x40 counters:0,1,2,3 um:zero minimum:500 name:IREQ_STARVED : The event occurs when the controller enters the instruction stream starved condition.
event:0x41 counters:0,1,2,3 um:zero minimum:500 name:RRTF_STARVED : The event occurs when the controller enters the remote re-try FIFO starved condition.
event:0x54 counters:0,1,2,3 um:zero minimum:500 name:UDN_PKT_SNT : Main processor finished sending a packet to the UDN.
event:0x55 counters:0,1,2,3 um:zero minimum:500 name:UDN_SNT : UDN word sent to an output port.  Participating ports are selected with the UDN_EVT_PORT_SEL field.
event:0x56 counters:0,1,2,3 um:zero minimum:500 name:UDN_BUBBLE : Bubble detected on an output port.  A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch.  Participating ports are selected with the UDN_EVT_PORT_SEL field.
event:0x57 counters:0,1,2,3 um:zero minimum:500 name:UDN_CONGESTION : Out of credit on an output port.  Participating ports are selected with the UDN_EVT_PORT_SEL field.
event:0x58 counters:0,1,2,3 um:zero minimum:500 name:IDN_PKT_SNT : Main processor finished sending a packet to the IDN.
event:0x59 counters:0,1,2,3 um:zero minimum:500 name:IDN_SNT : IDN word sent to an output port.  Participating ports are selected with the IDN_EVT_PORT_SEL field.
event:0x5a counters:0,1,2,3 um:zero minimum:500 name:IDN_BUBBLE : Bubble detected on an output port.  A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch.  Participating ports are selected with the IDN_EVT_PORT_SEL field.
event:0x5b counters:0,1,2,3 um:zero minimum:500 name:IDN_CONGESTION : Out of credit on an output port.  Participating ports are selected with the IDN_EVT_PORT_SEL field.
event:0x5c counters:0,1,2,3 um:zero minimum:500 name:MDN_PKT_SNT : Main processor finished sending a packet to the MDN.
event:0x5d counters:0,1,2,3 um:zero minimum:500 name:MDN_SNT : MDN word sent to an output port.  Participating ports are selected with the MDN_EVT_PORT_SEL field.
event:0x5e counters:0,1,2,3 um:zero minimum:500 name:MDN_BUBBLE : Bubble detected on an output port.  A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch.  Participating ports are selected with the MDN_EVT_PORT_SEL field.
event:0x5f counters:0,1,2,3 um:zero minimum:500 name:MDN_CONGESTION : Out of credit on an output port.  Participating ports are selected with the MDN_EVT_PORT_SEL field.
event:0x60 counters:0,1,2,3 um:zero minimum:500 name:TDN_PKT_SNT : Main processor finished sending a packet to the TDN.
event:0x61 counters:0,1,2,3 um:zero minimum:500 name:TDN_SNT : TDN word sent to an output port.  Participating ports are selected with the TDN_EVT_PORT_SEL field.
event:0x62 counters:0,1,2,3 um:zero minimum:500 name:TDN_BUBBLE : Bubble detected on an output port.  A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch.  Participating ports are selected with the TDN_EVT_PORT_SEL field.
event:0x63 counters:0,1,2,3 um:zero minimum:500 name:TDN_CONGESTION : Out of credit on an output port.  Participating ports are selected with the TDN_EVT_PORT_SEL field.
event:0x64 counters:0,1,2,3 um:zero minimum:500 name:VDN_PKT_SNT : Main processor finished sending a packet to the VDN.
event:0x65 counters:0,1,2,3 um:zero minimum:500 name:VDN_SNT : VDN word sent to an output port.  Participating ports are selected with the VDN_EVT_PORT_SEL field.
event:0x66 counters:0,1,2,3 um:zero minimum:500 name:VDN_BUBBLE : Bubble detected on an output port.  A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch.  Participating ports are selected with the VDN_EVT_PORT_SEL field.
event:0x67 counters:0,1,2,3 um:zero minimum:500 name:VDN_CONGESTION : Out of credit on an output port.  Participating ports are selected with the VDN_EVT_PORT_SEL field.
event:0x68 counters:0,1,2,3 um:zero minimum:500 name:UDN_DMUX_STALL : UDN Demux stalled due to buffer full
event:0x69 counters:0,1,2,3 um:zero minimum:500 name:IDN_DMUX_STALL : IDN Demux stalled due to buffer full