| /* | |
| FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd. | |
| *************************************************************************** | |
| * * | |
| * FreeRTOS tutorial books are available in pdf and paperback. * | |
| * Complete, revised, and edited pdf reference manuals are also * | |
| * available. * | |
| * * | |
| * Purchasing FreeRTOS documentation will not only help you, by * | |
| * ensuring you get running as quickly as possible and with an * | |
| * in-depth knowledge of how to use FreeRTOS, it will also help * | |
| * the FreeRTOS project to continue with its mission of providing * | |
| * professional grade, cross platform, de facto standard solutions * | |
| * for microcontrollers - completely free of charge! * | |
| * * | |
| * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * | |
| * * | |
| * Thank you for using FreeRTOS, and thank you for your support! * | |
| * * | |
| *************************************************************************** | |
| This file is part of the FreeRTOS distribution. | |
| FreeRTOS is free software; you can redistribute it and/or modify it under | |
| the terms of the GNU General Public License (version 2) as published by the | |
| Free Software Foundation AND MODIFIED BY the FreeRTOS exception. | |
| >>>NOTE<<< The modification to the GPL is included to allow you to | |
| distribute a combined work that includes FreeRTOS without being obliged to | |
| provide the source code for proprietary components outside of the FreeRTOS | |
| kernel. FreeRTOS is distributed in the hope that it will be useful, but | |
| WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| more details. You should have received a copy of the GNU General Public | |
| License and the FreeRTOS license exception along with FreeRTOS; if not it | |
| can be viewed here: http://www.freertos.org/a00114.html and also obtained | |
| by writing to Richard Barry, contact details for whom are available on the | |
| FreeRTOS WEB site. | |
| 1 tab == 4 spaces! | |
| *************************************************************************** | |
| * * | |
| * Having a problem? Start by reading the FAQ "My application does * | |
| * not run, what could be wrong? * | |
| * * | |
| * http://www.FreeRTOS.org/FAQHelp.html * | |
| * * | |
| *************************************************************************** | |
| http://www.FreeRTOS.org - Documentation, training, latest information, | |
| license and contact details. | |
| http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, | |
| including FreeRTOS+Trace - an indispensable productivity tool. | |
| Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell | |
| the code with commercial support, indemnification, and middleware, under | |
| the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also | |
| provide a safety engineered and independently SIL3 certified version under | |
| the SafeRTOS brand: http://www.SafeRTOS.com. | |
| */ | |
| /*----------------------------------------------------------- | |
| * Implementation of functions defined in portable.h for the ARM CM0 port. | |
| *----------------------------------------------------------*/ | |
| /* Scheduler includes. */ | |
| #include "FreeRTOS.h" | |
| #include "task.h" | |
| /* Constants required to manipulate the NVIC. */ | |
| #define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 ) | |
| #define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 ) | |
| #define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 ) | |
| #define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 ) | |
| #define portNVIC_SYSTICK_CLK 0x00000004 | |
| #define portNVIC_SYSTICK_INT 0x00000002 | |
| #define portNVIC_SYSTICK_ENABLE 0x00000001 | |
| #define portNVIC_PENDSVSET 0x10000000 | |
| #define portMIN_INTERRUPT_PRIORITY ( 255UL ) | |
| #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) | |
| #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) | |
| /* Constants required to set up the initial stack. */ | |
| #define portINITIAL_XPSR ( 0x01000000 ) | |
| /* Each task maintains its own interrupt status in the critical nesting | |
| variable. */ | |
| static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; | |
| /* | |
| * Setup the timer to generate the tick interrupts. | |
| */ | |
| static void prvSetupTimerInterrupt( void ); | |
| /* | |
| * Exception handlers. | |
| */ | |
| void xPortPendSVHandler( void ) __attribute__ (( naked )); | |
| void xPortSysTickHandler( void ); | |
| void vPortSVCHandler( void ) __attribute__ (( naked )); | |
| /* | |
| * Start first task is a separate function so it can be tested in isolation. | |
| */ | |
| static void vPortStartFirstTask( void ) __attribute__ (( naked )); | |
| /*-----------------------------------------------------------*/ | |
| /* | |
| * See header file for description. | |
| */ | |
| portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) | |
| { | |
| /* Simulate the stack frame as it would be created by a context switch | |
| interrupt. */ | |
| pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ | |
| *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ | |
| pxTopOfStack--; | |
| *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ | |
| pxTopOfStack -= 6; /* LR, R12, R3..R1 */ | |
| *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ | |
| pxTopOfStack -= 8; /* R11..R4. */ | |
| return pxTopOfStack; | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortSVCHandler( void ) | |
| { | |
| __asm volatile ( | |
| " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ | |
| " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ | |
| " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ | |
| " add r0, r0, #16 \n" /* Move to the high registers. */ | |
| " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ | |
| " mov r8, r4 \n" | |
| " mov r9, r5 \n" | |
| " mov r10, r6 \n" | |
| " mov r11, r7 \n" | |
| " \n" | |
| " msr psp, r0 \n" /* Remember the new top of stack for the task. */ | |
| " \n" | |
| " sub r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ | |
| " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ | |
| " mov r1, r14 \n" /* OR R14 with 0x0d. */ | |
| " movs r0, #0x0d \n" | |
| " orr r1, r0 \n" | |
| " bx r1 \n" | |
| " \n" | |
| " .align 2 \n" | |
| "pxCurrentTCBConst2: .word pxCurrentTCB \n" | |
| ); | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortStartFirstTask( void ) | |
| { | |
| __asm volatile( | |
| " movs r0, #0x00 \n" /* Locate the top of stack. */ | |
| " ldr r0, [r0] \n" | |
| " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ | |
| " cpsie i \n" /* Globally enable interrupts. */ | |
| " svc 0 \n" /* System call to start first task. */ | |
| " nop \n" | |
| ); | |
| } | |
| /*-----------------------------------------------------------*/ | |
| /* | |
| * See header file for description. | |
| */ | |
| portBASE_TYPE xPortStartScheduler( void ) | |
| { | |
| /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */ | |
| *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; | |
| *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; | |
| /* Start the timer that generates the tick ISR. Interrupts are disabled | |
| here already. */ | |
| prvSetupTimerInterrupt(); | |
| /* Initialise the critical nesting count ready for the first task. */ | |
| uxCriticalNesting = 0; | |
| /* Start the first task. */ | |
| vPortStartFirstTask(); | |
| /* Should not get here! */ | |
| return 0; | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortEndScheduler( void ) | |
| { | |
| /* It is unlikely that the CM0 port will require this function as there | |
| is nothing to return to. */ | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortYieldFromISR( void ) | |
| { | |
| /* Set a PendSV to request a context switch. */ | |
| *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortEnterCritical( void ) | |
| { | |
| portDISABLE_INTERRUPTS(); | |
| uxCriticalNesting++; | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortExitCritical( void ) | |
| { | |
| uxCriticalNesting--; | |
| if( uxCriticalNesting == 0 ) | |
| { | |
| portENABLE_INTERRUPTS(); | |
| } | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void xPortPendSVHandler( void ) | |
| { | |
| /* This is a naked function. */ | |
| __asm volatile | |
| ( | |
| " mrs r0, psp \n" | |
| " \n" | |
| " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ | |
| " ldr r2, [r3] \n" | |
| " \n" | |
| " sub r0, r0, #32 \n" /* Make space for the remaining low registers. */ | |
| " str r0, [r2] \n" /* Save the new top of stack. */ | |
| " stmia r0!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */ | |
| " mov r4, r8 \n" /* Store the high registers. */ | |
| " mov r5, r9 \n" | |
| " mov r6, r10 \n" | |
| " mov r7, r11 \n" | |
| " stmia r0!, {r4-r7} \n" | |
| " \n" | |
| " push {r3, r14} \n" | |
| " cpsid i \n" | |
| " bl vTaskSwitchContext \n" | |
| " cpsie i \n" | |
| " pop {r2, r3} \n" /* lr goes in r3. r2 now holds tcb pointer. */ | |
| " \n" | |
| " ldr r1, [r2] \n" | |
| " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ | |
| " add r0, r0, #16 \n" /* Move to the high registers. */ | |
| " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ | |
| " mov r8, r4 \n" | |
| " mov r9, r5 \n" | |
| " mov r10, r6 \n" | |
| " mov r11, r7 \n" | |
| " \n" | |
| " msr psp, r0 \n" /* Remember the new top of stack for the task. */ | |
| " \n" | |
| " sub r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ | |
| " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ | |
| " \n" | |
| " bx r3 \n" | |
| " \n" | |
| " .align 2 \n" | |
| "pxCurrentTCBConst: .word pxCurrentTCB " | |
| ); | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void xPortSysTickHandler( void ) | |
| { | |
| unsigned long ulDummy; | |
| /* If using preemption, also force a context switch. */ | |
| #if configUSE_PREEMPTION == 1 | |
| *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; | |
| #endif | |
| ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); | |
| { | |
| vTaskIncrementTick(); | |
| } | |
| portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); | |
| } | |
| /*-----------------------------------------------------------*/ | |
| /* | |
| * Setup the systick timer to generate the tick interrupts at the required | |
| * frequency. | |
| */ | |
| void prvSetupTimerInterrupt( void ) | |
| { | |
| /* Configure SysTick to interrupt at the requested rate. */ | |
| *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; | |
| *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; | |
| } | |
| /*-----------------------------------------------------------*/ | |