/*
    FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.


    ***************************************************************************
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    ***************************************************************************


    This file is part of the FreeRTOS distribution.

    FreeRTOS is free software; you can redistribute it and/or modify it under
    the terms of the GNU General Public License (version 2) as published by the
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
    >>>NOTE<<< The modification to the GPL is included to allow you to
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    FreeRTOS WEB site.

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    ***************************************************************************
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*/

/*-----------------------------------------------------------
 * Implementation of functions defined in portable.h for the ARM CM3 port.
 *
 * This is a specialization for the Freescale Kxx series that uses
 * LPTMR instead of SYSTICK to generate portTICKs.
 *----------------------------------------------------------*/

/* Configuration */
#include "FreeRTOSConfig.h"

/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"

/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
defined.  The value should also ensure backward compatibility.
FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
#ifndef configKERNEL_INTERRUPT_PRIORITY
	#define configKERNEL_INTERRUPT_PRIORITY 255
#endif

/* Constants required to manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL		( ( volatile unsigned long *) 0xe000e010 )
#define portNVIC_SYSTICK_LOAD		( ( volatile unsigned long *) 0xe000e014 )
#define portNVIC_INT_CTRL			( ( volatile unsigned long *) 0xe000ed04 )
#define portNVIC_SYSPRI2			( ( volatile unsigned long *) 0xe000ed20 )
#define portNVIC_SYSTICK_CLK		0x00000004
#define portNVIC_SYSTICK_INT		0x00000002
#define portNVIC_SYSTICK_ENABLE		0x00000001
#define portNVIC_PENDSVSET			0x10000000
#define portNVIC_PENDSV_PRI			( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
#define portNVIC_SYSTICK_PRI		( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )

/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR			( 0x01000000 )

/* The priority used by the kernel is assigned to a variable to make access
from inline assembler easier. */
const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;

/* Each task maintains its own interrupt status in the critical nesting
variable. */
static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;

/*
 * Setup the timer to generate the tick interrupts.
 */
void prvSetupTimerInterrupt( void );

/*
 * Exception handlers.
 */
void xPortPendSVHandler( void ) __attribute__ (( naked ));
void xPortSysTickHandler( void );
void vPortSVCHandler( void ) __attribute__ (( naked ));

/*
 * Start first task is a separate function so it can be tested in isolation.
 */
static void prvPortStartFirstTask( void ) __attribute__ (( naked ));

/*-----------------------------------------------------------*/

/*
 * See header file for description.
 */
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */
	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
	pxTopOfStack--;
	*pxTopOfStack = ( portSTACK_TYPE ) pxCode;	/* PC */
	pxTopOfStack--;
	*pxTopOfStack = 0;	/* LR */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;	/* R0 */
	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */

	return pxTopOfStack;
}
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
					"	ldmia r0!, {r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
					"	msr psp, r0						\n" /* Restore the task stack pointer. */
					"	mov r0, #0 						\n"
					"	msr	basepri, r0					\n"
					"	orr r14, #0xd					\n"
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB\n"
				);
}
/*-----------------------------------------------------------*/

static void prvPortStartFirstTask( void )
{
	__asm volatile(
					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
					" ldr r0, [r0] 			\n"
					" ldr r0, [r0] 			\n"
					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
					" cpsie i				\n" /* Globally enable interrupts. */
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
/*-----------------------------------------------------------*/

/*
 * See header file for description.
 */
portBASE_TYPE xPortStartScheduler( void )
{
	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	prvSetupTimerInterrupt();

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;

	/* Start the first task. */
	prvPortStartFirstTask();

	/* Should not get here! */
	return 0;
}
/*-----------------------------------------------------------*/

void vPortEndScheduler( void )
{
	/* It is unlikely that the CM3 port will require this function as there
	is nothing to return to.  */
}
/*-----------------------------------------------------------*/

void vPortYieldFromISR( void )
{
	/* Set a PendSV to request a context switch. */
	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
}
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
	uxCriticalNesting--;
	if( uxCriticalNesting == 0 )
	{
		portENABLE_INTERRUPTS();
	}
}
/*-----------------------------------------------------------*/

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
	(
    "   clrex                               \n"
	"	mrs r0, psp							\n"
	"										\n"
	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
	"	ldr	r2, [r3]						\n"
	"										\n"
	"	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
	"										\n"
	"	stmdb sp!, {r3, r14}				\n"
	"	mov r0, %0							\n"
	"	msr basepri, r0						\n"
	"	bl vTaskSwitchContext				\n"
	"	mov r0, #0							\n"
	"	msr basepri, r0						\n"
	"	ldmia sp!, {r3, r14}				\n"
	"										\n"	/* Restore the context, including the critical nesting count. */
	"	ldr r1, [r3]						\n"
	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
	"	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
	"	msr psp, r0							\n"
	"	bx r14								\n"
	"										\n"
	"	.align 2							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
/*-----------------------------------------------------------*/

/* Constants required to manipulate the LPTMR. */

#define SIM_BASE				(0x40047000)
#define SIM_REGISTER(r)			( ( volatile unsigned long *) (SIM_BASE+(r)) )
#define portSIM_SOPT1			SIM_REGISTER( 0x0000 )
#define portSIM_SCGC5			SIM_REGISTER( 0x1038 )

#define SIM_SOPT1_OSC32KSEL_MASK	( ( (unsigned long) 0x3) << 18)
#define SIM_SOPT1_OSC32KSEL_RTC	( ( (unsigned long) 0x2) << 18)
#define SIM_SOPT1_OSC32KSEL_LPO	( ( (unsigned long) 0x3) << 18)

#define SIM_SCGC5_LPTIMER		( ( (unsigned long) 1) << 0)

#define LPT_BASE				(0x40040000)
#define LPT_REGISTER(r)			( ( volatile unsigned long *) (LPT_BASE+(r)) )
#define portLPTMR_CSR			LPT_REGISTER( 0x00 )
#define portLPTMR_PSR			LPT_REGISTER( 0x04 )
#define portLPTMR_CMR			LPT_REGISTER( 0x08 )
#define portLPTMR_CNR			LPT_REGISTER( 0x0C )

#define LPTMR_CSR_TEN			( ( (unsigned long) 1) << 0 )
#define LPTMR_CSR_TIE			( ( (unsigned long) 1) << 6 )
#define LPTMR_CSR_TCF			( ( (unsigned long) 1) << 7 )

#define LPTMR_PSR_PRESCALE_DIV_2	( ( (unsigned long) 0x0) << 3 )
#define LPTMR_PSR_PBYP	        ( ( (unsigned long) 0x1) << 2 )
#define LPTMR_PSR_PCS_ERCLK32K	( ( (unsigned long) 0x2) << 0 )
#define LPTMR_PSR_PCS_LPO	    ( ( (unsigned long) 0x1) << 0 )


/* The interrupt vector number for LPTMR differs between K24 and K60:
   K60 is 85 (0x55) = 2*32 + 21,  K24 is 58 (0x3A) = 1*32 + 26 */

#ifdef KINETIS_K24
#define LPTMR_ISR			(0x3A)
#else
#ifdef KINETIS_K60
#define LPTMR_ISR			(0x55)
#else
#error No recognized KINETIS_<MCU>
#endif
#endif

#define NVIC_ISER				(0xe000e100)
#define portNVIC_ISERW			( ( volatile unsigned long *) (NVIC_ISER+4*(LPTMR_ISR/32)) )
#define NVIC_ISERW_LPTMR		( ( (unsigned long) 1) << (LPTMR_ISR%32) )

#define NVIC_PRI				(0xe000e400)
#define portNVIC_LPTMR_PRI		( ( volatile unsigned char *) (NVIC_PRI+LPTMR_ISR) )

void lptmr_isr( void );
void lptmr_isr( void )
{
	unsigned long ulDummy;

	*(portLPTMR_CSR) |= LPTMR_CSR_TCF;

	/* If using preemption, also force a context switch. */
	#if configUSE_PREEMPTION == 1
		*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
	#endif

	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
	{
		vTaskIncrementTick();
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
}
/*-----------------------------------------------------------*/

/*
 * Setup the LPTMR to generate the tick interrupts at the required
 * frequency.  Assumes 32kHz RTC clock already enabled.
 */
void prvSetupTimerInterrupt( void )
{
	unsigned long ulDummy;
	unsigned long sopt1;

	/* Enable access to LPTMR */
	*(portSIM_SCGC5) |= SIM_SCGC5_LPTIMER;

	*(portNVIC_LPTMR_PRI) = configKERNEL_INTERRUPT_PRIORITY;

	/* Route the 32kHz RTC_XTAL to ERCLK32K */
	sopt1 = *(portSIM_SOPT1);
	sopt1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
	sopt1 |=  SIM_SOPT1_OSC32KSEL_RTC;
	*(portSIM_SOPT1) = sopt1;

	/* Configure LPTMR to interrupt at the requested rate. */
	*(portLPTMR_CSR) &= ~LPTMR_CSR_TEN;
	ulDummy = *(portLPTMR_CSR); (void)ulDummy;
	*(portLPTMR_CSR) |= (LPTMR_CSR_TCF | LPTMR_CSR_TIE);
	*(portLPTMR_PSR) =  (LPTMR_PSR_PRESCALE_DIV_2 | LPTMR_PSR_PCS_ERCLK32K);
	*(portLPTMR_CMR) = (32768/1024)/2 - 1;
	*(portNVIC_ISERW) |= NVIC_ISERW_LPTMR;
	*(portLPTMR_CSR) |=  LPTMR_CSR_TEN;
}
/*-----------------------------------------------------------*/

/*-----------------------------------------------------------*/

/*
 * Setup the LPTMR to generate the tick interrupts at the required
 * frequency.  Use the internal 1K LPO clock for Diags
 */
void prvSetupTimerInterruptLpo( void );
void prvSetupTimerInterruptLpo( void )
{
	unsigned long ulDummy;
	unsigned long sopt1;

	/* Enable access to LPTMR */
	*(portSIM_SCGC5) |= SIM_SCGC5_LPTIMER;

	*(portNVIC_LPTMR_PRI) = configKERNEL_INTERRUPT_PRIORITY;

	/* Route the LPO 1kHZ to ERCLK32K */
	sopt1 = *(portSIM_SOPT1);
	sopt1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
	sopt1 |=  SIM_SOPT1_OSC32KSEL_LPO;
	*(portSIM_SOPT1) = sopt1;

	/* Configure LPTMR to interrupt at the requested rate. */
	*(portLPTMR_CSR) &= ~LPTMR_CSR_TEN;
	ulDummy = *(portLPTMR_CSR); (void)ulDummy;
	*(portLPTMR_CSR) |= (LPTMR_CSR_TCF | LPTMR_CSR_TIE);
	*(portLPTMR_PSR) = (LPTMR_PSR_PBYP | LPTMR_PSR_PCS_LPO);
	*(portLPTMR_CMR) = 0;
	*(portNVIC_ISERW) |= NVIC_ISERW_LPTMR;
	*(portLPTMR_CSR) |=  LPTMR_CSR_TEN;

}
/*-----------------------------------------------------------*/