/* | |
FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd. | |
*************************************************************************** | |
* * | |
* FreeRTOS tutorial books are available in pdf and paperback. * | |
* Complete, revised, and edited pdf reference manuals are also * | |
* available. * | |
* * | |
* Purchasing FreeRTOS documentation will not only help you, by * | |
* ensuring you get running as quickly as possible and with an * | |
* in-depth knowledge of how to use FreeRTOS, it will also help * | |
* the FreeRTOS project to continue with its mission of providing * | |
* professional grade, cross platform, de facto standard solutions * | |
* for microcontrollers - completely free of charge! * | |
* * | |
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< * | |
* * | |
* Thank you for using FreeRTOS, and thank you for your support! * | |
* * | |
*************************************************************************** | |
This file is part of the FreeRTOS distribution. | |
FreeRTOS is free software; you can redistribute it and/or modify it under | |
the terms of the GNU General Public License (version 2) as published by the | |
Free Software Foundation AND MODIFIED BY the FreeRTOS exception. | |
>>>NOTE<<< The modification to the GPL is included to allow you to | |
distribute a combined work that includes FreeRTOS without being obliged to | |
provide the source code for proprietary components outside of the FreeRTOS | |
kernel. FreeRTOS is distributed in the hope that it will be useful, but | |
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
more details. You should have received a copy of the GNU General Public | |
License and the FreeRTOS license exception along with FreeRTOS; if not it | |
can be viewed here: http://www.freertos.org/a00114.html and also obtained | |
by writing to Richard Barry, contact details for whom are available on the | |
FreeRTOS WEB site. | |
1 tab == 4 spaces! | |
*************************************************************************** | |
* * | |
* Having a problem? Start by reading the FAQ "My application does * | |
* not run, what could be wrong? * | |
* * | |
* http://www.FreeRTOS.org/FAQHelp.html * | |
* * | |
*************************************************************************** | |
http://www.FreeRTOS.org - Documentation, training, latest information, | |
license and contact details. | |
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, | |
including FreeRTOS+Trace - an indispensable productivity tool. | |
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell | |
the code with commercial support, indemnification, and middleware, under | |
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also | |
provide a safety engineered and independently SIL3 certified version under | |
the SafeRTOS brand: http://www.SafeRTOS.com. | |
*/ | |
/*----------------------------------------------------------- | |
* Implementation of functions defined in portable.h for the ARM CM4F port. | |
*----------------------------------------------------------*/ | |
/* Scheduler includes. */ | |
#include "FreeRTOS.h" | |
#include "task.h" | |
#ifndef __TARGET_FPU_VFP | |
#error This port can only be used when the project options are configured to enable hardware floating point support. | |
#endif | |
#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 | |
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html | |
#endif | |
/* Constants required to manipulate the NVIC. */ | |
#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 ) | |
#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 ) | |
#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 ) | |
#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 ) | |
#define portNVIC_SYSTICK_CLK 0x00000004 | |
#define portNVIC_SYSTICK_INT 0x00000002 | |
#define portNVIC_SYSTICK_ENABLE 0x00000001 | |
#define portNVIC_PENDSVSET 0x10000000 | |
#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) | |
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) | |
/* Constants required to manipulate the VFP. */ | |
#define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */ | |
#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) | |
/* Constants required to set up the initial stack. */ | |
#define portINITIAL_XPSR ( 0x01000000 ) | |
#define portINITIAL_EXEC_RETURN ( 0xfffffffd ) | |
/* Each task maintains its own interrupt status in the critical nesting | |
variable. */ | |
static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; | |
/* | |
* Setup the timer to generate the tick interrupts. | |
*/ | |
static void prvSetupTimerInterrupt( void ); | |
/* | |
* Exception handlers. | |
*/ | |
void xPortPendSVHandler( void ); | |
void xPortSysTickHandler( void ); | |
void vPortSVCHandler( void ); | |
/* | |
* Start first task is a separate function so it can be tested in isolation. | |
*/ | |
static void prvStartFirstTask( void ); | |
/* | |
* Functions defined in portasm.s to enable the VFP. | |
*/ | |
static void prvEnableVFP( void ); | |
/*-----------------------------------------------------------*/ | |
/* | |
* See header file for description. | |
*/ | |
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) | |
{ | |
/* Simulate the stack frame as it would be created by a context switch | |
interrupt. */ | |
/* Offset added to account for the way the MCU uses the stack on entry/exit | |
of interrupts, and to ensure alignment. */ | |
pxTopOfStack--; | |
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */ | |
pxTopOfStack--; | |
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ | |
pxTopOfStack--; | |
*pxTopOfStack = 0; /* LR */ | |
/* Save code space by skipping register initialisation. */ | |
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ | |
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ | |
/* A save method is being used that requires each task to maintain its | |
own exec return value. */ | |
pxTopOfStack--; | |
*pxTopOfStack = portINITIAL_EXEC_RETURN; | |
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ | |
return pxTopOfStack; | |
} | |
/*-----------------------------------------------------------*/ | |
__asm void vPortSVCHandler( void ) | |
{ | |
PRESERVE8 | |
/* Get the location of the current TCB. */ | |
ldr r3, =pxCurrentTCB | |
ldr r1, [r3] | |
ldr r0, [r1] | |
/* Pop the core registers. */ | |
ldmia r0!, {r4-r11, r14} | |
msr psp, r0 | |
mov r0, #0 | |
msr basepri, r0 | |
bx r14 | |
} | |
/*-----------------------------------------------------------*/ | |
__asm void prvStartFirstTask( void ) | |
{ | |
PRESERVE8 | |
/* Use the NVIC offset register to locate the stack. */ | |
ldr r0, =0xE000ED08 | |
ldr r0, [r0] | |
ldr r0, [r0] | |
/* Set the msp back to the start of the stack. */ | |
msr msp, r0 | |
/* Globally enable interrupts. */ | |
cpsie i | |
/* Call SVC to start the first task. */ | |
svc 0 | |
nop | |
} | |
/*-----------------------------------------------------------*/ | |
__asm void prvEnableVFP( void ) | |
{ | |
PRESERVE8 | |
/* The FPU enable bits are in the CPACR. */ | |
ldr.w r0, =0xE000ED88 | |
ldr r1, [r0] | |
/* Enable CP10 and CP11 coprocessors, then save back. */ | |
orr r1, r1, #( 0xf << 20 ) | |
str r1, [r0] | |
bx r14 | |
nop | |
} | |
/*-----------------------------------------------------------*/ | |
/* | |
* See header file for description. | |
*/ | |
portBASE_TYPE xPortStartScheduler( void ) | |
{ | |
/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */ | |
*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; | |
*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; | |
/* Start the timer that generates the tick ISR. Interrupts are disabled | |
here already. */ | |
prvSetupTimerInterrupt(); | |
/* Initialise the critical nesting count ready for the first task. */ | |
uxCriticalNesting = 0; | |
/* Ensure the VFP is enabled - it should be anyway. */ | |
prvEnableVFP(); | |
/* Lazy save always. */ | |
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; | |
/* Start the first task. */ | |
prvStartFirstTask(); | |
/* Should not get here! */ | |
return 0; | |
} | |
/*-----------------------------------------------------------*/ | |
void vPortEndScheduler( void ) | |
{ | |
/* It is unlikely that the CM4F port will require this function as there | |
is nothing to return to. */ | |
} | |
/*-----------------------------------------------------------*/ | |
void vPortYieldFromISR( void ) | |
{ | |
/* Set a PendSV to request a context switch. */ | |
*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; | |
} | |
/*-----------------------------------------------------------*/ | |
void vPortEnterCritical( void ) | |
{ | |
portDISABLE_INTERRUPTS(); | |
uxCriticalNesting++; | |
} | |
/*-----------------------------------------------------------*/ | |
void vPortExitCritical( void ) | |
{ | |
uxCriticalNesting--; | |
if( uxCriticalNesting == 0 ) | |
{ | |
portENABLE_INTERRUPTS(); | |
} | |
} | |
/*-----------------------------------------------------------*/ | |
__asm void xPortPendSVHandler( void ) | |
{ | |
extern uxCriticalNesting; | |
extern pxCurrentTCB; | |
extern vTaskSwitchContext; | |
PRESERVE8 | |
mrs r0, psp | |
/* Get the location of the current TCB. */ | |
ldr r3, =pxCurrentTCB | |
ldr r2, [r3] | |
/* Is the task using the FPU context? If so, push high vfp registers. */ | |
tst r14, #0x10 | |
it eq | |
vstmdbeq r0!, {s16-s31} | |
/* Save the core registers. */ | |
stmdb r0!, {r4-r11, r14} | |
/* Save the new top of stack into the first member of the TCB. */ | |
str r0, [r2] | |
stmdb sp!, {r3, r14} | |
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY | |
msr basepri, r0 | |
bl vTaskSwitchContext | |
mov r0, #0 | |
msr basepri, r0 | |
ldmia sp!, {r3, r14} | |
/* The first item in pxCurrentTCB is the task top of stack. */ | |
ldr r1, [r3] | |
ldr r0, [r1] | |
/* Pop the core registers. */ | |
ldmia r0!, {r4-r11, r14} | |
/* Is the task using the FPU context? If so, pop the high vfp registers | |
too. */ | |
tst r14, #0x10 | |
it eq | |
vldmiaeq r0!, {s16-s31} | |
msr psp, r0 | |
bx r14 | |
nop | |
} | |
/*-----------------------------------------------------------*/ | |
void xPortSysTickHandler( void ) | |
{ | |
unsigned long ulDummy; | |
/* If using preemption, also force a context switch. */ | |
#if configUSE_PREEMPTION == 1 | |
*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; | |
#endif | |
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); | |
{ | |
vTaskIncrementTick(); | |
} | |
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); | |
} | |
/*-----------------------------------------------------------*/ | |
/* | |
* Setup the systick timer to generate the tick interrupts at the required | |
* frequency. | |
*/ | |
void prvSetupTimerInterrupt( void ) | |
{ | |
/* Configure SysTick to interrupt at the requested rate. */ | |
*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; | |
*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; | |
} | |
/*-----------------------------------------------------------*/ | |
__asm void vPortSetInterruptMask( void ) | |
{ | |
PRESERVE8 | |
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY | |
msr basepri, r0 | |
bx r14 | |
} | |
/*-----------------------------------------------------------*/ | |
__asm void vPortClearInterruptMask( void ) | |
{ | |
PRESERVE8 | |
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see | |
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */ | |
mov r0, #0 | |
msr basepri, r0 | |
bx r14 | |
} |