FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s

/*
    FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
	

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    ***************************************************************************


    This file is part of the FreeRTOS distribution.

    FreeRTOS is free software; you can redistribute it and/or modify it under
    the terms of the GNU General Public License (version 2) as published by the
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
    >>>NOTE<<< The modification to the GPL is included to allow you to
    distribute a combined work that includes FreeRTOS without being obliged to
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    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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    by writing to Richard Barry, contact details for whom are available on the
    FreeRTOS WEB site.

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    ***************************************************************************
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*/

#include <FreeRTOSConfig.h>

	RSEG    CODE:CODE(2)
	thumb

	EXTERN pxCurrentTCB
	EXTERN vTaskSwitchContext

	PUBLIC xPortPendSVHandler
	PUBLIC vPortSetInterruptMask
	PUBLIC vPortClearInterruptMask
	PUBLIC vPortSVCHandler
	PUBLIC vPortStartFirstTask
	PUBLIC vPortEnableVFP


/*-----------------------------------------------------------*/

xPortPendSVHandler:
	mrs r0, psp						
	
	/* Get the location of the current TCB. */
	ldr	r3, =pxCurrentTCB			
	ldr	r2, [r3]						

	/* Is the task using the FPU context?  If so, push high vfp registers. */
	tst r14, #0x10
	it eq
	vstmdbeq r0!, {s16-s31}

	/* Save the core registers. */
	stmdb r0!, {r4-r11, r14}				
	
	/* Save the new top of stack into the first member of the TCB. */
	str r0, [r2]
	
	stmdb sp!, {r3, r14}
	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
	msr basepri, r0
	bl vTaskSwitchContext			
	mov r0, #0
	msr basepri, r0
	ldmia sp!, {r3, r14}

	/* The first item in pxCurrentTCB is the task top of stack. */
	ldr r1, [r3]	
	ldr r0, [r1]
	
	/* Pop the core registers. */
	ldmia r0!, {r4-r11, r14}

	/* Is the task using the FPU context?  If so, pop the high vfp registers 
	too. */
	tst r14, #0x10
	it eq
	vldmiaeq r0!, {s16-s31}
	
	msr psp, r0						
	bx r14							


/*-----------------------------------------------------------*/

vPortSetInterruptMask:
	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
	msr BASEPRI, r0

	bx r14
	
/*-----------------------------------------------------------*/

vPortClearInterruptMask:
	/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
	mov r0, #0
	msr BASEPRI, r0

	bx r14

/*-----------------------------------------------------------*/

vPortSVCHandler:
	/* Get the location of the current TCB. */
	ldr	r3, =pxCurrentTCB
	ldr r1, [r3]
	ldr r0, [r1]
	/* Pop the core registers. */
	ldmia r0!, {r4-r11, r14}
	msr psp, r0
	mov r0, #0
	msr	basepri, r0	
	bx r14

/*-----------------------------------------------------------*/

vPortStartFirstTask:
	/* Use the NVIC offset register to locate the stack. */
	ldr r0, =0xE000ED08
	ldr r0, [r0]
	ldr r0, [r0]
	/* Set the msp back to the start of the stack. */
	msr msp, r0
	/* Call SVC to start the first task. */
	cpsie i
	svc 0

/*-----------------------------------------------------------*/

vPortEnableVFP:
	/* The FPU enable bits are in the CPACR. */
	ldr.w r0, =0xE000ED88
	ldr	r1, [r0]
	
	/* Enable CP10 and CP11 coprocessors, then save back. */
	orr	r1, r1, #( 0xf << 20 )
	str r1, [r0]
	bx	r14	
	


	END