Project import generated by Copybara.
NOKEYCHECK=True
GitOrigin-RevId: 129235ca60ad12b5181393f53029eeffcfbbf16f
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/File-Related-CLI-commands.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/File-Related-CLI-commands.c
new file mode 100644
index 0000000..12950cc
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/File-Related-CLI-commands.c
@@ -0,0 +1,568 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+
+#ifdef _WINDOWS_
+ #define snprintf _snprintf
+#endif
+
+#define cliNEW_LINE "\r\n"
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/*
+ * Print out information on a single file.
+ */
+static void prvCreateFileInfoString( char *pcBuffer, F_FIND *pxFindStruct );
+
+/*
+ * Copies an existing file into a newly created file.
+ */
+static portBASE_TYPE prvPerformCopy( const char *pcSourceFile,
+ int32_t lSourceFileLength,
+ const char *pcDestinationFile,
+ char *pxWriteBuffer,
+ size_t xWriteBufferLen );
+
+/*
+ * Implements the DIR command.
+ */
+static portBASE_TYPE prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the CD command.
+ */
+static portBASE_TYPE prvCDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the DEL command.
+ */
+static portBASE_TYPE prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the TYPE command.
+ */
+static portBASE_TYPE prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the COPY command.
+ */
+static portBASE_TYPE prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/* Structure that defines the DIR command line command, which lists all the
+files in the current directory. */
+static const CLI_Command_Definition_t xDIR =
+{
+ "dir", /* The command string to type. */
+ "\r\ndir:\r\n Lists the files in the current directory\r\n",
+ prvDIRCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the CD command line command, which changes the
+working directory. */
+static const CLI_Command_Definition_t xCD =
+{
+ "cd", /* The command string to type. */
+ "\r\ncd <dir name>:\r\n Changes the working directory\r\n",
+ prvCDCommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the TYPE command line command, which prints the
+contents of a file to the console. */
+static const CLI_Command_Definition_t xTYPE =
+{
+ "type", /* The command string to type. */
+ "\r\ntype <filename>:\r\n Prints file contents to the terminal\r\n",
+ prvTYPECommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the DEL command line command, which deletes a file. */
+static const CLI_Command_Definition_t xDEL =
+{
+ "del", /* The command string to type. */
+ "\r\ndel <filename>:\r\n deletes a file or directory\r\n",
+ prvDELCommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the COPY command line command, which deletes a file. */
+static const CLI_Command_Definition_t xCOPY =
+{
+ "copy", /* The command string to type. */
+ "\r\ncopy <source file> <dest file>:\r\n Copies <source file> to <dest file>\r\n",
+ prvCOPYCommand, /* The function to run. */
+ 2 /* Two parameters are expected. */
+};
+
+
+/*-----------------------------------------------------------*/
+
+void vRegisterFileSystemCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xDIR );
+ FreeRTOS_CLIRegisterCommand( &xCD );
+ FreeRTOS_CLIRegisterCommand( &xTYPE );
+ FreeRTOS_CLIRegisterCommand( &xDEL );
+ FreeRTOS_CLIRegisterCommand( &xCOPY );
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;
+static F_FILE *pxFile = NULL;
+int iChar;
+size_t xByte;
+size_t xColumns = 50U;
+
+ /* Ensure there is always a null terminator after each character written. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+
+ /* Ensure the buffer leaves space for the \r\n. */
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+ xWriteBufferLen -= strlen( cliNEW_LINE );
+
+ if( xWriteBufferLen < xColumns )
+ {
+ /* Ensure the loop that uses xColumns as an end condition does not
+ write off the end of the buffer. */
+ xColumns = xWriteBufferLen;
+ }
+
+ if( pxFile == NULL )
+ {
+ /* The file has not been opened yet. Find the file name. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to open the requested file. */
+ pxFile = f_open( pcParameter, "r" );
+ }
+
+ if( pxFile != NULL )
+ {
+ /* Read the next chunk of data from the file. */
+ for( xByte = 0; xByte < xColumns; xByte++ )
+ {
+ iChar = f_getc( pxFile );
+
+ if( iChar == -1 )
+ {
+ /* No more characters to return. */
+ f_close( pxFile );
+ pxFile = NULL;
+ break;
+ }
+ else
+ {
+ pcWriteBuffer[ xByte ] = ( char ) iChar;
+ }
+ }
+ }
+
+ if( pxFile == NULL )
+ {
+ /* Either the file was not opened, or all the data from the file has
+ been returned and the file is now closed. */
+ xReturn = pdFALSE;
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+size_t xStringLength;
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to move to the requested directory. */
+ ucReturned = f_chdir( pcParameter );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ sprintf( pcWriteBuffer, "In: " );
+ xStringLength = strlen( pcWriteBuffer );
+ f_getcwd( &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Error" );
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+static F_FIND *pxFindStruct = NULL;
+unsigned char ucReturned;
+portBASE_TYPE xReturn = pdFALSE;
+
+ /* This assumes pcWriteBuffer is long enough. */
+ ( void ) pcCommandString;
+
+ /* Ensure the buffer leaves space for the \r\n. */
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+ xWriteBufferLen -= strlen( cliNEW_LINE );
+
+ if( pxFindStruct == NULL )
+ {
+ /* This is the first time this function has been executed since the Dir
+ command was run. Create the find structure. */
+ pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );
+
+ if( pxFindStruct != NULL )
+ {
+ ucReturned = f_findfirst( "*.*", pxFindStruct );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ snprintf( pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );
+ }
+ }
+ else
+ {
+ snprintf( pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );
+ }
+ }
+ else
+ {
+ /* The find struct has already been created. Find the next file in
+ the directory. */
+ ucReturned = f_findnext( pxFindStruct );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* There are no more files. Free the find structure. */
+ vPortFree( pxFindStruct );
+ pxFindStruct = NULL;
+
+ /* No string to return. */
+ pcWriteBuffer[ 0 ] = 0x00;
+ }
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+
+ /* This function assumes xWriteBufferLen is large enough! */
+ ( void ) xWriteBufferLen;
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to delete the file. */
+ ucReturned = f_delete( pcParameter );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ sprintf( pcWriteBuffer, "%s was deleted", pcParameter );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Error" );
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+char *pcSourceFile, *pcDestinationFile;
+portBASE_TYPE xParameterStringLength;
+long lSourceLength, lDestinationLength = 0;
+
+ /* Obtain the name of the destination file. */
+ pcDestinationFile = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 2, /* Return the second parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcDestinationFile );
+
+ /* Obtain the name of the source file. */
+ pcSourceFile = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcSourceFile );
+
+ /* Terminate the string. */
+ pcSourceFile[ xParameterStringLength ] = 0x00;
+
+ /* See if the source file exists, obtain its length if it does. */
+ lSourceLength = f_filelength( pcSourceFile );
+
+ if( lSourceLength == 0 )
+ {
+ sprintf( pcWriteBuffer, "Source file does not exist" );
+ }
+ else
+ {
+ /* See if the destination file exists. */
+ lDestinationLength = f_filelength( pcDestinationFile );
+
+ if( lDestinationLength != 0 )
+ {
+ sprintf( pcWriteBuffer, "Error: Destination file already exists" );
+ }
+ }
+
+ /* Continue only if the source file exists and the destination file does
+ not exist. */
+ if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )
+ {
+ if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )
+ {
+ sprintf( pcWriteBuffer, "Copy made" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Error during copy" );
+ }
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvPerformCopy( const char *pcSourceFile,
+ int32_t lSourceFileLength,
+ const char *pcDestinationFile,
+ char *pxWriteBuffer,
+ size_t xWriteBufferLen )
+{
+int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;
+F_FILE *pxFile;
+portBASE_TYPE xReturn = pdPASS;
+
+ /* NOTE: Error handling has been omitted for clarity. */
+
+ while( lBytesRead < lSourceFileLength )
+ {
+ /* How many bytes are left? */
+ lBytesRemaining = lSourceFileLength - lBytesRead;
+
+ /* How many bytes should be read this time around the loop. Can't
+ read more bytes than will fit into the buffer. */
+ if( lBytesRemaining > ( long ) xWriteBufferLen )
+ {
+ lBytesToRead = ( long ) xWriteBufferLen;
+ }
+ else
+ {
+ lBytesToRead = lBytesRemaining;
+ }
+
+ /* Open the source file, seek past the data that has already been
+ read from the file, read the next block of data, then close the
+ file again so the destination file can be opened. */
+ pxFile = f_open( pcSourceFile, "r" );
+ if( pxFile != NULL )
+ {
+ f_seek( pxFile, lBytesRead, F_SEEK_SET );
+ f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );
+ f_close( pxFile );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ /* Open the destination file and write the block of data to the end of
+ the file. */
+ pxFile = f_open( pcDestinationFile, "a" );
+ if( pxFile != NULL )
+ {
+ f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );
+ f_close( pxFile );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ lBytesRead += lBytesToRead;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateFileInfoString( char *pcBuffer, F_FIND *pxFindStruct )
+{
+const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";
+const char * pcAttrib;
+
+ /* Point pcAttrib to a string that describes the file. */
+ if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )
+ {
+ pcAttrib = pcDirectory;
+ }
+ else if( pxFindStruct->attr & F_ATTR_READONLY )
+ {
+ pcAttrib = pcReadOnlyFile;
+ }
+ else
+ {
+ pcAttrib = pcWritableFile;
+ }
+
+ /* Create a string that includes the file name, the file size and the
+ attributes string. */
+ sprintf( pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, ( int ) pxFindStruct->filesize );
+}
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c
new file mode 100644
index 0000000..2ecec85
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c
@@ -0,0 +1,419 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+ #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+#endif
+
+/* Structure that defines the "run-time-stats" command line command. This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+ "run-time-stats", /* The command string to type. */
+ "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",
+ prvRunTimeStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command. This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+ "task-stats", /* The command string to type. */
+ "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",
+ prvTaskStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command. This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+ "echo-3-parameters",
+ "\r\necho-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n",
+ prvThreeParameterEchoCommand, /* The function to run. */
+ 3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command. This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+ "echo-parameters",
+ "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",
+ prvParameterEchoCommand, /* The function to run. */
+ -1 /* The user can enter any number of commands. */
+};
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ /* Structure that defines the "trace" command line command. This takes a single
+ parameter, which can be either "start" or "stop". */
+ static const CLI_Command_Definition_t xStartStopTrace =
+ {
+ "trace",
+ "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",
+ prvStartStopTraceCommand, /* The function to run. */
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */
+ };
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterSampleCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+
+ #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )
+ {
+ FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskList( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The three parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ if( lParameterNumber == 3L )
+ {
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ xReturn = pdFALSE;
+ lParameterNumber = 0L;
+ }
+ else
+ {
+ /* There are more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter != NULL )
+ {
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* There might be more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ else
+ {
+ /* No more parameters were found. Make sure the write buffer does
+ not contain a valid string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* No more data to return. */
+ xReturn = pdFALSE;
+
+ /* Start over the next time this command is executed. */
+ lParameterNumber = 0;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ const char *pcParameter;
+ portBASE_TYPE lParameterStringLength;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* There are only two valid parameter values. */
+ if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 )
+ {
+ /* Start or restart the trace. */
+ vTraceStop();
+ vTraceClear();
+ vTraceStart();
+
+ sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" );
+ }
+ else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 )
+ {
+ /* End the trace, if one is running. */
+ vTraceStop();
+ sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+ }
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+ }
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c
new file mode 100644
index 0000000..0aa8dc9
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c
@@ -0,0 +1,256 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * NOTE: This file uses a third party USB CDC driver.
+ */
+
+/* Standard includes. */
+#include "string.h"
+#include "stdio.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Example includes. */
+#include "FreeRTOS_CLI.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE 50
+
+#define cmdQUEUE_LENGTH 25
+
+/* DEL acts as a backspace. */
+#define cmdASCII_DEL ( 0x7F )
+
+#define cmdMAX_MUTEX_WAIT ( ( ( TickType_t ) 300 ) / ( portTICK_PERIOD_MS ) )
+
+#ifndef configCLI_BAUD_RATE
+ #define configCLI_BAUD_RATE 115200
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that implements the command console processing.
+ */
+static void prvUARTCommandConsoleTask( void *pvParameters );
+void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
+
+/*-----------------------------------------------------------*/
+
+/* Const messages output by the command console. */
+static const char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
+static const char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";
+static const char * const pcNewLine = "\r\n";
+
+SemaphoreHandle_t xTxMutex = NULL;
+static xComPortHandle xPort = 0;
+
+/*-----------------------------------------------------------*/
+
+void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority )
+{
+ /* Create the semaphore used to access the UART Tx. */
+ xTxMutex = xSemaphoreCreateMutex();
+ configASSERT( xTxMutex );
+
+ /* Create that task that handles the console itself. */
+ xTaskCreate( prvUARTCommandConsoleTask, /* The task that implements the command console. */
+ "CLI", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */
+ usStackSize, /* The size of the stack allocated to the task. */
+ NULL, /* The parameter is not used, so NULL is passed. */
+ uxPriority, /* The priority allocated to the task. */
+ NULL ); /* A handle is not required, so just pass NULL. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvUARTCommandConsoleTask( void *pvParameters )
+{
+signed char cRxedChar;
+uint8_t ucInputIndex = 0;
+char *pcOutputString;
+static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
+portBASE_TYPE xReturned;
+xComPortHandle xPort;
+
+ ( void ) pvParameters;
+
+ /* Obtain the address of the output buffer. Note there is no mutual
+ exclusion on this buffer as it is assumed only one command console interface
+ will be used at any one time. */
+ pcOutputString = FreeRTOS_CLIGetOutputBuffer();
+
+ /* Initialise the UART. */
+ xPort = xSerialPortInitMinimal( configCLI_BAUD_RATE, cmdQUEUE_LENGTH );
+
+ /* Send the welcome message. */
+ vSerialPutString( xPort, ( signed char * ) pcWelcomeMessage, strlen( pcWelcomeMessage ) );
+
+ for( ;; )
+ {
+ /* Wait for the next character. The while loop is used in case
+ INCLUDE_vTaskSuspend is not set to 1 - in which case portMAX_DELAY will
+ be a genuine block time rather than an infinite block time. */
+ while( xSerialGetChar( xPort, &cRxedChar, portMAX_DELAY ) != pdPASS );
+
+ /* Ensure exclusive access to the UART Tx. */
+ if( xSemaphoreTake( xTxMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+ {
+ /* Echo the character back. */
+ xSerialPutChar( xPort, cRxedChar, portMAX_DELAY );
+
+ /* Was it the end of the line? */
+ if( cRxedChar == '\n' || cRxedChar == '\r' )
+ {
+ /* Just to space the output from the input. */
+ vSerialPutString( xPort, ( signed char * ) pcNewLine, strlen( pcNewLine ) );
+
+ /* See if the command is empty, indicating that the last command
+ is to be executed again. */
+ if( ucInputIndex == 0 )
+ {
+ /* Copy the last command back into the input string. */
+ strcpy( cInputString, cLastInputString );
+ }
+
+ /* Pass the received command to the command interpreter. The
+ command interpreter is called repeatedly until it returns
+ pdFALSE (indicating there is no more output) as it might
+ generate more than one string. */
+ do
+ {
+ /* Get the next output string from the command interpreter. */
+ xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
+
+ /* Write the generated string to the UART. */
+ vSerialPutString( xPort, ( signed char * ) pcOutputString, strlen( pcOutputString ) );
+
+ } while( xReturned != pdFALSE );
+
+ /* All the strings generated by the input command have been
+ sent. Clear the input string ready to receive the next command.
+ Remember the command that was just processed first in case it is
+ to be processed again. */
+ strcpy( cLastInputString, cInputString );
+ ucInputIndex = 0;
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+ vSerialPutString( xPort, ( signed char * ) pcEndOfOutputMessage, strlen( pcEndOfOutputMessage ) );
+ }
+ else
+ {
+ if( cRxedChar == '\r' )
+ {
+ /* Ignore the character. */
+ }
+ else if( ( cRxedChar == '\b' ) || ( cRxedChar == cmdASCII_DEL ) )
+ {
+ /* Backspace was pressed. Erase the last character in the
+ string - if any. */
+ if( ucInputIndex > 0 )
+ {
+ ucInputIndex--;
+ cInputString[ ucInputIndex ] = '\0';
+ }
+ }
+ else
+ {
+ /* A character was entered. Add it to the string entered so
+ far. When a \n is entered the complete string will be
+ passed to the command interpreter. */
+ if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
+ {
+ if( ucInputIndex < cmdMAX_INPUT_SIZE )
+ {
+ cInputString[ ucInputIndex ] = cRxedChar;
+ ucInputIndex++;
+ }
+ }
+ }
+ }
+
+ /* Must ensure to give the mutex back. */
+ xSemaphoreGive( xTxMutex );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vOutputString( const char * const pcMessage )
+{
+ if( xSemaphoreTake( xTxMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+ {
+ vSerialPutString( xPort, ( signed char * ) pcMessage, strlen( pcMessage ) );
+ xSemaphoreGive( xTxMutex );
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UDP-Related-CLI-commands.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UDP-Related-CLI-commands.c
new file mode 100644
index 0000000..c638d0a
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UDP-Related-CLI-commands.c
@@ -0,0 +1,351 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+UDP includes, just to make the stats available to the CLI
+commands. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+/*
+ * Defines a command that prints out IP address information.
+ */
+static portBASE_TYPE prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that prints out the gathered demo debug stats.
+ */
+static portBASE_TYPE prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that sends an ICMP ping request to an IP address.
+ */
+static portBASE_TYPE prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/* Structure that defines the "ip-config" command line command. */
+static const CLI_Command_Definition_t xIPConfig =
+{
+ "ip-config",
+ "ip-config:\r\n Displays IP address configuration\r\n\r\n",
+ prvDisplayIPConfig,
+ 0
+};
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+ /* Structure that defines the "ip-debug-stats" command line command. */
+ static const CLI_Command_Definition_t xIPDebugStats =
+ {
+ "ip-debug-stats", /* The command string to type. */
+ "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n",
+ prvDisplayIPDebugStats, /* The function to run. */
+ 0 /* No parameters are expected. */
+ };
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+ /* Structure that defines the "ping" command line command. This takes an IP
+ address or host name and (optionally) the number of bytes to ping as
+ parameters. */
+ static const CLI_Command_Definition_t xPing =
+ {
+ "ping",
+ "ping <ipaddress> <optional:bytes to send>:\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n",
+ prvPingCommand, /* The function to run. */
+ -1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */
+ };
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+
+/*-----------------------------------------------------------*/
+
+void vRegisterUDPCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xIPConfig );
+
+ #if configINCLUDE_DEMO_DEBUG_STATS == 1
+ {
+ FreeRTOS_CLIRegisterCommand( &xIPDebugStats );
+ }
+ #endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+ #if ipconfigSUPPORT_OUTGOING_PINGS == 1
+ {
+ FreeRTOS_CLIRegisterCommand( &xPing );
+ }
+ #endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+}
+/*-----------------------------------------------------------*/
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+ static portBASE_TYPE prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ char * pcParameter;
+ portBASE_TYPE lParameterStringLength, xReturn;
+ uint32_t ulIPAddress, ulBytesToPing;
+ const uint32_t ulDefaultBytesToPing = 8UL;
+ char cBuffer[ 16 ];
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Start with an empty string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* Obtain the number of bytes to ping. */
+ pcParameter = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 2, /* Return the second parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter == NULL )
+ {
+ /* The number of bytes was not specified, so default it. */
+ ulBytesToPing = ulDefaultBytesToPing;
+ }
+ else
+ {
+ ulBytesToPing = atol( pcParameter );
+ }
+
+ /* Obtain the IP address string. */
+ pcParameter = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to obtain the IP address. If the first character is not a
+ digit, assume the host name has been passed in. */
+ if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) )
+ {
+ ulIPAddress = FreeRTOS_inet_addr( pcParameter );
+ }
+ else
+ {
+ /* Terminate the host name. */
+ pcParameter[ lParameterStringLength ] = 0x00;
+
+ /* Attempt to resolve host. */
+ ulIPAddress = FreeRTOS_gethostbyname( pcParameter );
+ }
+
+ /* Convert IP address, which may have come from a DNS lookup, to string. */
+ FreeRTOS_inet_ntoa( ulIPAddress, cBuffer );
+
+ if( ulIPAddress != 0 )
+ {
+ xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY );
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( xReturn == pdFALSE )
+ {
+ sprintf( pcWriteBuffer, "%s", "Could not send ping request\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, ( int ) xReturn );
+ }
+
+ return pdFALSE;
+ }
+ /*-----------------------------------------------------------*/
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+
+ static portBASE_TYPE prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ static portBASE_TYPE xIndex = -1;
+ extern xExampleDebugStatEntry_t xIPTraceValues[];
+ portBASE_TYPE xReturn;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ xIndex++;
+
+ if( xIndex < xExampleDebugStatEntries() )
+ {
+ sprintf( pcWriteBuffer, "%s %d\r\n", ( char * ) xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Reset the index for the next time it is called. */
+ xIndex = -1;
+
+ /* Ensure nothing remains in the write buffer. */
+ pcWriteBuffer[ 0 ] = 0x00;
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+ }
+ /*-----------------------------------------------------------*/
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+static portBASE_TYPE prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+static portBASE_TYPE xIndex = 0;
+portBASE_TYPE xReturn;
+uint32_t ulAddress;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ switch( xIndex )
+ {
+ case 0 :
+ FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL );
+ sprintf( pcWriteBuffer, "\r\nIP address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 1 :
+ FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL );
+ sprintf( pcWriteBuffer, "\r\nNet mask " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 2 :
+ FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL );
+ sprintf( pcWriteBuffer, "\r\nGateway address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 3 :
+ FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress );
+ sprintf( pcWriteBuffer, "\r\nDNS server address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ default :
+ ulAddress = 0;
+ sprintf( pcWriteBuffer, "\r\n\r\n" );
+ xReturn = pdFALSE;
+ xIndex = 0;
+ break;
+ }
+
+ if( ulAddress != 0 )
+ {
+ FreeRTOS_inet_ntoa( ulAddress, ( &( pcWriteBuffer[ strlen( pcWriteBuffer ) ] ) ) );
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_FAT_SL_Demos/CreateExampleFiles/File-system-demo.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_FAT_SL_Demos/CreateExampleFiles/File-system-demo.c
new file mode 100644
index 0000000..8d1f165
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_FAT_SL_Demos/CreateExampleFiles/File-system-demo.c
@@ -0,0 +1,359 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/* Standard includes. */
+#include <stdio.h>
+#include <string.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+
+/* 8.3 format, plus null terminator. */
+#define fsMAX_FILE_NAME_LEN 13
+
+/* The number of bytes read/written to the example files at a time. */
+#define fsRAM_BUFFER_SIZE 200
+
+/* The number of bytes written to the file that uses f_putc() and f_getc(). */
+#define fsPUTC_FILE_SIZE 100
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+void vCreateAndVerifySampleFiles( void );
+
+/*
+ * Create a set of example files in the root directory of the volume using
+ * f_write().
+ */
+static void prvCreateDemoFilesUsing_f_write( void );
+
+/*
+ * Use f_read() to read back and verify the files that were created by
+ * prvCreateDemoFilesUsing_f_write().
+ */
+static void prvVerifyDemoFileUsing_f_read( void );
+
+/*
+ * Create an example file in a sub-directory using f_putc().
+ */
+static void prvCreateDemoFileUsing_f_putc( void );
+
+/*
+ * Use f_getc() to read back and verify the file that was created by
+ * prvCreateDemoFileUsing_f_putc().
+ */
+static void prvVerifyDemoFileUsing_f_getc( void );
+
+/*-----------------------------------------------------------*/
+
+/* A buffer used to both create content to write to disk, and read content back
+from a disk. Note there is no mutual exclusion on this buffer. */
+static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];
+
+/* Names of directories that are created. */
+static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";
+
+/*-----------------------------------------------------------*/
+
+void vCreateAndVerifySampleFiles( void )
+{
+unsigned char ucStatus;
+
+ /* First create the volume. */
+ ucStatus = f_initvolume( ram_initfunc );
+
+ /* It is expected that the volume is not formatted. */
+ if( ucStatus == F_ERR_NOTFORMATTED )
+ {
+ /* Format the created volume. */
+ ucStatus = f_format( F_FAT12_MEDIA );
+ }
+
+ if( ucStatus == F_NO_ERROR )
+ {
+ /* Create a set of files using f_write(). */
+ prvCreateDemoFilesUsing_f_write();
+
+ /* Read back and verify the files that were created using f_write(). */
+ prvVerifyDemoFileUsing_f_read();
+
+ /* Create sub directories two deep then create a file using putc. */
+ prvCreateDemoFileUsing_f_putc();
+
+ /* Read back and verify the file created by
+ prvCreateDemoFileUsing_f_putc(). */
+ prvVerifyDemoFileUsing_f_getc();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFilesUsing_f_write( void )
+{
+portBASE_TYPE xFileNumber, xWriteNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+const portBASE_TYPE xMaxFiles = 5;
+long lItemsWritten;
+F_FILE *pxFile;
+
+ /* Create xMaxFiles files. Each created file will be
+ ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled
+ with a different repeating character. */
+ for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ )
+ {
+ /* Generate a file name. */
+ sprintf( cFileName, "root%03d.txt", ( int ) xFileNumber );
+
+ /* Obtain the current working directory and print out the file name and
+ the directory into which the file is being written. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+
+ /* Open the file, creating the file if it does not already exist. */
+ pxFile = f_open( cFileName, "w" );
+ configASSERT( pxFile );
+
+ /* Fill the RAM buffer with data that will be written to the file. This
+ is just a repeating ascii character that indicates the file number. */
+ memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );
+
+ /* Write the RAM buffer to the opened file a number of times. The
+ number of times the RAM buffer is written to the file depends on the
+ file number, so the length of each created file will be different. */
+ for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )
+ {
+ lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+ configASSERT( lItemsWritten == 1 );
+ }
+
+ /* Close the file so another file can be created. */
+ f_close( pxFile );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_read( void )
+{
+portBASE_TYPE xFileNumber, xReadNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+const portBASE_TYPE xMaxFiles = 5;
+long lItemsRead, lChar;
+F_FILE *pxFile;
+
+ /* Read back the files that were created by
+ prvCreateDemoFilesUsing_f_write(). */
+ for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ )
+ {
+ /* Generate the file name. */
+ sprintf( cFileName, "root%03d.txt", ( int ) xFileNumber );
+
+ /* Obtain the current working directory and print out the file name and
+ the directory from which the file is being read. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+
+ /* Open the file for reading. */
+ pxFile = f_open( cFileName, "r" );
+ configASSERT( pxFile );
+
+ /* Read the file into the RAM buffer, checking the file contents are as
+ expected. The size of the file depends on the file number. */
+ for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )
+ {
+ /* Start with the RAM buffer clear. */
+ memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );
+
+ lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+ configASSERT( lItemsRead == 1 );
+
+ /* Check the RAM buffer is filled with the expected data. Each
+ file contains a different repeating ascii character that indicates
+ the number of the file. */
+ for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )
+ {
+ configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );
+ }
+ }
+
+ /* Close the file. */
+ f_close( pxFile );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFileUsing_f_putc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+
+ /* Create a sub directory. */
+ ucReturn = f_mkdir( pcDirectory1 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Move into the created sub-directory. */
+ ucReturn = f_chdir( pcDirectory1 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+
+ /* Create a subdirectory in the new directory. */
+ ucReturn = f_mkdir( pcDirectory2 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Move into the directory just created - now two directories down from
+ the root. */
+ ucReturn = f_chdir( pcDirectory2 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ configASSERT( strcmp( cRAMBuffer, pcFullPath ) == 0 );
+
+ /* Generate the file name. */
+ sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+ /* Print out the file name and the directory into which the file is being
+ written. */
+ pxFile = f_open( cFileName, "w" );
+
+ /* Create a file 1 byte at a time. The file is filled with incrementing
+ ascii characters starting from '0'. */
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+ {
+ iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );
+ }
+
+ /* Finished so close the file. */
+ f_close( pxFile );
+
+ /* Move back to the root directory. */
+ ucReturn = f_chdir( "../.." );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ configASSERT( strcmp( cRAMBuffer, pcRoot ) == 0 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_getc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+ /* Move into the directory in which the file was created. */
+ ucReturn = f_chdir( pcFullPath );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ configASSERT( strcmp( cRAMBuffer, pcFullPath ) == 0 );
+
+ /* Generate the file name. */
+ sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+ /* This time the file is opened for reading. */
+ pxFile = f_open( cFileName, "r" );
+
+ /* Read the file 1 byte at a time. */
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+ {
+ iReturned = f_getc( pxFile );
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );
+ }
+
+ /* Finished so close the file. */
+ f_close( pxFile );
+
+ /* Move back to the root directory. */
+ ucReturn = f_chdir( "../.." );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+}
+
+
+
+
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c
new file mode 100644
index 0000000..09ee590
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c
@@ -0,0 +1,667 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+UDP includes, just to make the stats available to the CLI
+commands. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+ #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that prints out IP address information.
+ */
+static portBASE_TYPE prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that prints out the gathered demo debug stats.
+ */
+static portBASE_TYPE prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that sends an ICMP ping request to an IP address.
+ */
+static portBASE_TYPE prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+#endif
+
+/* Structure that defines the "ip-config" command line command. */
+static const CLI_Command_Definition_t xIPConfig =
+{
+ "ip-config",
+ "ip-config:\r\n Displays IP address configuration\r\n\r\n",
+ prvDisplayIPConfig,
+ 0
+};
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+ /* Structure that defines the "ip-debug-stats" command line command. */
+ static const CLI_Command_Definition_t xIPDebugStats =
+ {
+ "ip-debug-stats", /* The command string to type. */
+ "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n",
+ prvDisplayIPDebugStats, /* The function to run. */
+ 0 /* No parameters are expected. */
+ };
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+/* Structure that defines the "run-time-stats" command line command. This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+ "run-time-stats", /* The command string to type. */
+ "run-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n",
+ prvRunTimeStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command. This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+ "task-stats", /* The command string to type. */
+ "task-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n",
+ prvTaskStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command. This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+ "echo-3-parameters",
+ "echo-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n\r\n",
+ prvThreeParameterEchoCommand, /* The function to run. */
+ 3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command. This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+ "echo-parameters",
+ "echo-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n",
+ prvParameterEchoCommand, /* The function to run. */
+ -1 /* The user can enter any number of commands. */
+};
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+ /* Structure that defines the "ping" command line command. This takes an IP
+ address or host name and (optionally) the number of bytes to ping as
+ parameters. */
+ static const CLI_Command_Definition_t xPing =
+ {
+ "ping",
+ "ping <ipaddress> <optional:bytes to send>:\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n",
+ prvPingCommand, /* The function to run. */
+ -1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */
+ };
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ /* Structure that defines the "trace" command line command. This takes a single
+ parameter, which can be either "start" or "stop". */
+ static const CLI_Command_Definition_t xStartStopTrace =
+ {
+ "trace",
+ "trace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n",
+ prvStartStopTraceCommand, /* The function to run. */
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */
+ };
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xIPDebugStats );
+ FreeRTOS_CLIRegisterCommand( &xIPConfig );
+
+ #if ipconfigSUPPORT_OUTGOING_PINGS == 1
+ {
+ FreeRTOS_CLIRegisterCommand( &xPing );
+ }
+ #endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+ #if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskList( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The three parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ if( lParameterNumber == 3L )
+ {
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ xReturn = pdFALSE;
+ lParameterNumber = 0L;
+ }
+ else
+ {
+ /* There are more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter != NULL )
+ {
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* There might be more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ else
+ {
+ /* No more parameters were found. Make sure the write buffer does
+ not contain a valid string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* No more data to return. */
+ xReturn = pdFALSE;
+
+ /* Start over the next time this command is executed. */
+ lParameterNumber = 0;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+ static portBASE_TYPE prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ char * pcParameter;
+ portBASE_TYPE lParameterStringLength, xReturn;
+ uint32_t ulIPAddress, ulBytesToPing;
+ const uint32_t ulDefaultBytesToPing = 8UL;
+ char cBuffer[ 16 ];
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Start with an empty string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* Obtain the number of bytes to ping. */
+ pcParameter = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 2, /* Return the second parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter == NULL )
+ {
+ /* The number of bytes was not specified, so default it. */
+ ulBytesToPing = ulDefaultBytesToPing;
+ }
+ else
+ {
+ ulBytesToPing = atol( pcParameter );
+ }
+
+ /* Obtain the IP address string. */
+ pcParameter = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to obtain the IP address. If the first character is not a
+ digit, assume the host name has been passed in. */
+ if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) )
+ {
+ ulIPAddress = FreeRTOS_inet_addr( pcParameter );
+ }
+ else
+ {
+ /* Terminate the host name. */
+ pcParameter[ lParameterStringLength ] = 0x00;
+
+ /* Attempt to resolve host. */
+ ulIPAddress = FreeRTOS_gethostbyname( pcParameter );
+ }
+
+ /* Convert IP address, which may have come from a DNS lookup, to string. */
+ FreeRTOS_inet_ntoa( ulIPAddress, cBuffer );
+
+ if( ulIPAddress != 0 )
+ {
+ xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY );
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( xReturn == pdFALSE )
+ {
+ sprintf( pcWriteBuffer, "%s", "Could not send ping request\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, xReturn );
+ }
+
+ return pdFALSE;
+ }
+ /*-----------------------------------------------------------*/
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+
+ static portBASE_TYPE prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ static portBASE_TYPE xIndex = -1;
+ extern xExampleDebugStatEntry_t xIPTraceValues[];
+ portBASE_TYPE xReturn;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ xIndex++;
+
+ if( xIndex < xExampleDebugStatEntries() )
+ {
+ sprintf( pcWriteBuffer, "%s %d\r\n", xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Reset the index for the next time it is called. */
+ xIndex = -1;
+
+ /* Ensure nothing remains in the write buffer. */
+ pcWriteBuffer[ 0 ] = 0x00;
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+ }
+ /*-----------------------------------------------------------*/
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+static portBASE_TYPE prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+static portBASE_TYPE xIndex = 0;
+portBASE_TYPE xReturn;
+uint32_t ulAddress;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ switch( xIndex )
+ {
+ case 0 :
+ FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL );
+ sprintf( pcWriteBuffer, "\r\nIP address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 1 :
+ FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL );
+ sprintf( pcWriteBuffer, "\r\nNet mask " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 2 :
+ FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL );
+ sprintf( pcWriteBuffer, "\r\nGateway address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 3 :
+ FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress );
+ sprintf( pcWriteBuffer, "\r\nDNS server address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ default :
+ ulAddress = 0;
+ sprintf( pcWriteBuffer, "\r\n\r\n" );
+ xReturn = pdFALSE;
+ xIndex = 0;
+ break;
+ }
+
+ if( ulAddress != 0 )
+ {
+ FreeRTOS_inet_ntoa( ulAddress, &( pcWriteBuffer[ strlen( pcWriteBuffer ) ] ) );
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ const char *pcParameter;
+ portBASE_TYPE lParameterStringLength;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* There are only two valid parameter values. */
+ if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 )
+ {
+ /* Start or restart the trace. */
+ vTraceStop();
+ vTraceClear();
+ vTraceStart();
+
+ sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" );
+ }
+ else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 )
+ {
+ /* End the trace, if one is running. */
+ vTraceStop();
+ sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+ }
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+ }
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandInterpreter.h b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandInterpreter.h
new file mode 100644
index 0000000..164a5d3
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandInterpreter.h
@@ -0,0 +1,71 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef UDP_COMMAND_INTERPRETER_H
+#define UDP_COMMAND_INTERPRETER_H
+
+void vStartUDPCommandInterpreterTask( uint16_t usStackSize, uint32_t ulPort, unsigned portBASE_TYPE uxPriority );
+
+#endif /* UDP_COMMAND_INTERPRETER_H */
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandServer.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandServer.c
new file mode 100644
index 0000000..b8c5829
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandServer.c
@@ -0,0 +1,244 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+UDP includes. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+/* Demo app includes. */
+#include "UDPCommandInterpreter.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE 60
+
+/* Dimensions the buffer into which string outputs can be placed. */
+#define cmdMAX_OUTPUT_SIZE 1024
+
+/* Dimensions the buffer passed to the recvfrom() call. */
+#define cmdSOCKET_INPUT_BUFFER_SIZE 60
+
+/*
+ * The task that runs FreeRTOS+CLI.
+ */
+void vUDPCommandInterpreterTask( void *pvParameters );
+
+/*
+ * Open and configure the UDP socket.
+ */
+static xSocket_t prvOpenUDPServerSocket( uint16_t usPort );
+
+/*-----------------------------------------------------------*/
+
+void vStartUDPCommandInterpreterTask( uint16_t usStackSize, uint32_t ulPort, unsigned portBASE_TYPE uxPriority )
+{
+ xTaskCreate( vUDPCommandInterpreterTask, "CLI", usStackSize, ( void * ) ulPort, uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Task that provides the input and output for the FreeRTOS+CLI command
+ * interpreter. In this case a UDP port is used. See the URL in the comments
+ * within main.c for the location of the online documentation.
+ */
+void vUDPCommandInterpreterTask( void *pvParameters )
+{
+long lBytes, lByte;
+signed char cInChar, cInputIndex = 0;
+static char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ];
+portBASE_TYPE xMoreDataToFollow;
+struct freertos_sockaddr xClient;
+socklen_t xClientAddressLength = 0; /* This is required as a parameter to maintain the sendto() Berkeley sockets API - but it is not actually used so can take any value. */
+xSocket_t xSocket;
+
+ /* Just to prevent compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Attempt to open the socket. The port number is passed in the task
+ parameter. The strange casting is to remove compiler warnings on 32-bit
+ machines. */
+ xSocket = prvOpenUDPServerSocket( ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL );
+
+ if( xSocket != FREERTOS_INVALID_SOCKET )
+ {
+ for( ;; )
+ {
+ /* Wait for incoming data on the opened socket. */
+ lBytes = FreeRTOS_recvfrom( xSocket, ( void * ) cLocalBuffer, sizeof( cLocalBuffer ), 0, &xClient, &xClientAddressLength );
+
+ if( lBytes != FREERTOS_SOCKET_ERROR )
+ {
+ /* Process each received byte in turn. */
+ lByte = 0;
+ while( lByte < lBytes )
+ {
+ /* The next character in the input buffer. */
+ cInChar = cLocalBuffer[ lByte ];
+ lByte++;
+
+ /* Newline characters are taken as the end of the command
+ string. */
+ if( cInChar == '\n' )
+ {
+ /* Process the input string received prior to the
+ newline. */
+ do
+ {
+ /* Pass the string to FreeRTOS+CLI. */
+ xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE );
+
+ /* Send the output generated by the command's
+ implementation. */
+ FreeRTOS_sendto( xSocket, cOutputString, strlen( cOutputString ), 0, &xClient, xClientAddressLength );
+
+ } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */
+
+ /* All the strings generated by the command processing
+ have been sent. Clear the input string ready to receive
+ the next command. */
+ cInputIndex = 0;
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+ /* Transmit a spacer, just to make the command console
+ easier to read. */
+ FreeRTOS_sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, &xClient, xClientAddressLength );
+ }
+ else
+ {
+ if( cInChar == '\r' )
+ {
+ /* Ignore the character. Newlines are used to
+ detect the end of the input string. */
+ }
+ else if( cInChar == '\b' )
+ {
+ /* Backspace was pressed. Erase the last character
+ in the string - if any. */
+ if( cInputIndex > 0 )
+ {
+ cInputIndex--;
+ cInputString[ cInputIndex ] = '\0';
+ }
+ }
+ else
+ {
+ /* A character was entered. Add it to the string
+ entered so far. When a \n is entered the complete
+ string will be passed to the command interpreter. */
+ if( cInputIndex < cmdMAX_INPUT_SIZE )
+ {
+ cInputString[ cInputIndex ] = cInChar;
+ cInputIndex++;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* The socket could not be opened. */
+ vTaskDelete( NULL );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static xSocket_t prvOpenUDPServerSocket( uint16_t usPort )
+{
+struct freertos_sockaddr xServer;
+xSocket_t xSocket = FREERTOS_INVALID_SOCKET;
+
+ xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP );
+ if( xSocket != FREERTOS_INVALID_SOCKET)
+ {
+ /* Zero out the server structure. */
+ memset( ( void * ) &xServer, 0x00, sizeof( xServer ) );
+
+ /* Set family and port. */
+ xServer.sin_port = FreeRTOS_htons( usPort );
+
+ /* Bind the address to the socket. */
+ if( FreeRTOS_bind( xSocket, &xServer, sizeof( xServer ) ) == -1 )
+ {
+ FreeRTOS_closesocket( xSocket );
+ xSocket = FREERTOS_INVALID_SOCKET;
+ }
+ }
+
+ return xSocket;
+}
+
+
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c
new file mode 100644
index 0000000..e5eb00a
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c
@@ -0,0 +1,397 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+/******************************************************************************
+ *
+ * See the following web page for essential TwoEchoClient.c usage and
+ * configuration details:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml
+ *
+ ******************************************************************************/
+
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+UDP includes. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+/* Small delay used between attempts to obtain a zero copy buffer. */
+#define echoTINY_DELAY ( ( portTickType ) 2 )
+
+/* The echo tasks create a socket, send out a number of echo requests
+(listening for each echo reply), then close the socket again before
+starting over. This delay is used between each iteration to ensure the
+network does not get too congested. */
+#define echoLOOP_DELAY ( ( portTickType ) 250 / portTICK_RATE_MS )
+
+#if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1
+ /* When the trace recorder code is included user events are generated to
+ mark the sending and receiving of the echoed data (only in the zero copy
+ task. */
+ #define echoMARK_SEND_IN_TRACE_BUFFER( x ) vTraceUserEvent( x )
+ traceLabel xZeroCopySendEvent, xZeroCopyReceiveEvent;
+
+#else
+ /* When the trace recorder code is not included just #define away the call
+ to post the user event. */
+ #define echoMARK_SEND_IN_TRACE_BUFFER( x )
+ #define xZeroCopySendEvent 0
+ #define xZeroCopyReceiveEvent 0
+#endif
+
+/* The echo server is assumed to be on port 7, which is the standard echo
+protocol port. */
+#define echoECHO_PORT ( 7 )
+
+/*
+ * Uses a socket to send data to, then receive data from, the standard echo
+ * port number 7. prvEchoClientTask() uses the standard interface.
+ * prvZeroCopyEchoClientTask() uses the zero copy interface.
+ */
+static void prvEchoClientTask( void *pvParameters );
+static void prvZeroCopyEchoClientTask( void *pvParameters );
+
+/* The receive timeout is set shorter when the windows simulator is used
+because simulated time is slower than real time. */
+#ifdef _WINDOWS_
+ const portTickType xReceiveTimeOut = 50 / portTICK_RATE_MS;
+#else
+ const portTickType xReceiveTimeOut = 500 / portTICK_RATE_MS;
+#endif
+
+/*-----------------------------------------------------------*/
+
+void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority )
+{
+ /* Create the echo client task that does not use the zero copy interface. */
+ xTaskCreate( prvEchoClientTask, /* The function that implements the task. */
+ "Echo0", /* Just a text name for the task to aid debugging. */
+ usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */
+ NULL, /* The task parameter, not used in this case. */
+ uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */
+ NULL ); /* The task handle is not used. */
+
+ /* Create the echo client task that does use the zero copy interface. */
+ xTaskCreate( prvZeroCopyEchoClientTask, /* The function that implements the task. */
+ "Echo1", /* Just a text name for the task to aid debugging. */
+ usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */
+ NULL, /* The task parameter, not used in this case. */
+ uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */
+ NULL ); /* The task handle is not used. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvEchoClientTask( void *pvParameters )
+{
+xSocket_t xSocket;
+struct freertos_sockaddr xEchoServerAddress;
+char cTxString[ 25 ], cRxString[ 25 ]; /* Make sure the stack is large enough to hold these. Turn on stack overflow checking during debug to be sure. */
+int32_t lLoopCount = 0UL;
+const int32_t lMaxLoopCount = 50;
+volatile uint32_t ulRxCount = 0UL, ulTxCount = 0UL;
+uint32_t xAddressLength = sizeof( xEchoServerAddress );
+
+ /* Remove compiler warning about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Echo requests are sent to the echo server. The address of the echo
+ server is configured by the constants configECHO_SERVER_ADDR0 to
+ configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */
+ xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT );
+ xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0,
+ configECHO_SERVER_ADDR1,
+ configECHO_SERVER_ADDR2,
+ configECHO_SERVER_ADDR3 );
+
+ for( ;; )
+ {
+ /* Create a socket. */
+ xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP );
+ configASSERT( xSocket != FREERTOS_INVALID_SOCKET );
+
+ /* Set a time out so a missing reply does not cause the task to block
+ indefinitely. */
+ FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) );
+
+ /* Send a number of echo requests. */
+ for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ )
+ {
+ /* Create the string that is sent to the echo server. */
+ sprintf( cTxString, "Message number %u\r\n", ( unsigned int ) ulTxCount );
+
+ /* Send the string to the socket. ulFlags is set to 0, so the zero
+ copy interface is not used. That means the data from cTxString is
+ copied into a network buffer inside FreeRTOS_sendto(), and cTxString
+ can be reused as soon as FreeRTOS_sendto() has returned. 1 is added
+ to ensure the NULL string terminator is sent as part of the message. */
+ FreeRTOS_sendto( xSocket, /* The socket being sent to. */
+ ( void * ) cTxString, /* The data being sent. */
+ strlen( cTxString ) + 1,/* The length of the data being sent. */
+ 0, /* ulFlags with the FREERTOS_ZERO_COPY bit clear. */
+ &xEchoServerAddress, /* The destination address. */
+ sizeof( xEchoServerAddress ) );
+
+ /* Keep a count of how many echo requests have been transmitted so
+ it can be compared to the number of echo replies received. It would
+ be expected to loose at least one to an ARP message the first time
+ the connection is created. */
+ ulTxCount++;
+
+ /* Receive data echoed back to the socket. ulFlags is zero, so the
+ zero copy option is not being used and the received data will be
+ copied into the buffer pointed to by cRxString. xAddressLength is
+ not actually used (at the time of writing this comment, anyway) by
+ FreeRTOS_recvfrom(), but is set appropriately in case future
+ versions do use it. */
+ memset( ( void * ) cRxString, 0x00, sizeof( cRxString ) );
+ FreeRTOS_recvfrom( xSocket, /* The socket being received from. */
+ cRxString, /* The buffer into which the received data will be written. */
+ sizeof( cRxString ), /* The size of the buffer provided to receive the data. */
+ 0, /* ulFlags with the FREERTOS_ZERO_COPY bit clear. */
+ &xEchoServerAddress, /* The address from where the data was sent (the source address). */
+ &xAddressLength );
+
+ /* Compare the transmitted string to the received string. */
+ if( strcmp( cRxString, cTxString ) == 0 )
+ {
+ /* The echo reply was received without error. */
+ ulRxCount++;
+ }
+ };
+
+ /* Pause for a short while to ensure the network is not too
+ congested. */
+ vTaskDelay( echoLOOP_DELAY );
+
+ /* Close this socket before looping back to create another. */
+ FreeRTOS_closesocket( xSocket );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvZeroCopyEchoClientTask( void *pvParameters )
+{
+xSocket_t xSocket;
+struct freertos_sockaddr xEchoServerAddress;
+static char cTxString[ 40 ];
+int32_t lLoopCount = 0UL;
+volatile uint32_t ulRxCount = 0UL, ulTxCount = 0UL;
+uint32_t xAddressLength = sizeof( xEchoServerAddress );
+int32_t lReturned;
+uint8_t *pucUDPPayloadBuffer;
+
+const int32_t lMaxLoopCount = 50;
+const char * const pcStringToSend = "Zero copy message number";
+/* The buffer is large enough to hold the string, a number, and the string terminator. */
+const size_t xBufferLength = strlen( pcStringToSend ) + 15;
+
+ #if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1
+ {
+ /* When the trace recorder code is included user events are generated to
+ mark the sending and receiving of the echoed data (only in the zero copy
+ task). */
+ xZeroCopySendEvent = xTraceOpenLabel( "ZeroCopyTx" );
+ xZeroCopyReceiveEvent = xTraceOpenLabel( "ZeroCopyRx" );
+ }
+ #endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS */
+
+ /* Remove compiler warning about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Delay for a little while to ensure the task is out of synch with the
+ other echo task implemented above. */
+ vTaskDelay( echoLOOP_DELAY >> 1 );
+
+ /* Echo requests are sent to the echo server. The address of the echo
+ server is configured by the constants configECHO_SERVER_ADDR0 to
+ configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */
+ xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT );
+ xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0,
+ configECHO_SERVER_ADDR1,
+ configECHO_SERVER_ADDR2,
+ configECHO_SERVER_ADDR3 );
+
+ for( ;; )
+ {
+ /* Create a socket. */
+ xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP );
+ configASSERT( xSocket != FREERTOS_INVALID_SOCKET );
+
+ /* Set a time out so a missing reply does not cause the task to block
+ indefinitely. */
+ FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) );
+
+ /* Send a number of echo requests. */
+ for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ )
+ {
+ /* This task is going to send using the zero copy interface. The
+ data being sent is therefore written directly into a buffer that is
+ passed by reference into the FreeRTOS_sendto() function. First
+ obtain a buffer of adequate size from the IP stack. Although a max
+ delay is used, the actual delay will be capped to
+ ipconfigMAX_SEND_BLOCK_TIME_TICKS, hence the test to ensure a buffer
+ was actually obtained. */
+ pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xBufferLength, portMAX_DELAY );
+
+ if( pucUDPPayloadBuffer != NULL )
+ {
+ /* A buffer was successfully obtained. Create the string that is
+ sent to the echo server. Note the string is written directly
+ into the buffer obtained from the IP stack. */
+ sprintf( ( char * ) pucUDPPayloadBuffer, "%s %u\r\n", "Zero copy message number", ( unsigned int ) ulTxCount );
+
+ /* Also copy the string into a local buffer so it can be compared
+ with the string that is later received back from the echo server. */
+ strcpy( cTxString, ( char * ) pucUDPPayloadBuffer );
+
+ /* Pass the buffer into the send function. ulFlags has the
+ FREERTOS_ZERO_COPY bit set so the IP stack will take control of
+ the buffer, rather than copy data out of the buffer. */
+ echoMARK_SEND_IN_TRACE_BUFFER( xZeroCopySendEvent );
+ lReturned = FreeRTOS_sendto( xSocket, /* The socket being sent to. */
+ ( void * ) pucUDPPayloadBuffer, /* The buffer being passed into the IP stack. */
+ strlen( cTxString ) + 1, /* The length of the data being sent. Plus 1 to ensure the null terminator is part of the data. */
+ FREERTOS_ZERO_COPY, /* ulFlags with the zero copy bit is set. */
+ &xEchoServerAddress, /* Where the data is being sent. */
+ sizeof( xEchoServerAddress ) );
+
+ if( lReturned == 0 )
+ {
+ /* The send operation failed, so this task is still
+ responsible for the buffer obtained from the IP stack. To
+ ensure the buffer is not lost it must either be used again,
+ or, as in this case, returned to the IP stack using
+ FreeRTOS_ReleaseUDPPayloadBuffer(). pucUDPPayloadBuffer can
+ be safely re-used to receive from the socket below once the
+ buffer has been returned to the stack. */
+ FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer );
+ }
+ else
+ {
+ /* The send was successful so the IP stack is now managing
+ the buffer pointed to by pucUDPPayloadBuffer, and the IP
+ stack will return the buffer once it has been sent.
+ pucUDPPayloadBuffer can be safely re-used to receive from
+ the socket below. */
+ }
+
+ /* Keep a count of how many echo requests have been transmitted
+ so it can be compared to the number of echo replies received.
+ It would be expected to loose at least one to an ARP message the
+ first time the connection is created. */
+ ulTxCount++;
+
+ /* Receive data on the socket. ulFlags has the zero copy bit set
+ (FREERTOS_ZERO_COPY) indicating to the stack that a reference to
+ the received data should be passed out to this task using the
+ second parameter to the FreeRTOS_recvfrom() call. When this is
+ done the IP stack is no longer responsible for releasing the
+ buffer, and the task *must* return the buffer to the stack when
+ it is no longer needed. By default the receive block time is
+ portMAX_DELAY. */
+ echoMARK_SEND_IN_TRACE_BUFFER( xZeroCopyReceiveEvent );
+ lReturned = FreeRTOS_recvfrom( xSocket, /* The socket to receive from. */
+ ( void * ) &pucUDPPayloadBuffer, /* pucUDPPayloadBuffer will be set to point to the buffer that already contains the received data. */
+ 0, /* Ignored because the zero copy interface is being used. */
+ FREERTOS_ZERO_COPY, /* ulFlags with the FREERTOS_ZERO_COPY bit set. */
+ &xEchoServerAddress, /* The address from which the data was sent. */
+ &xAddressLength );
+
+ if( lReturned > 0 )
+ {
+ /* Compare the string sent to the echo server with the string
+ received back from the echo server. */
+ if( strcmp( ( char * ) pucUDPPayloadBuffer, cTxString ) == 0 )
+ {
+ /* The strings matched. */
+ ulRxCount++;
+ }
+
+ /* The buffer that contains the data passed out of the stack
+ *must* be returned to the stack. */
+ FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer );
+ }
+ }
+ }
+
+ /* Pause for a short while to ensure the network is not too
+ congested. */
+ vTaskDelay( echoLOOP_DELAY );
+
+ /* Close this socket before looping back to create another. */
+ FreeRTOS_closesocket( xSocket );
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h
new file mode 100644
index 0000000..c69748d
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h
@@ -0,0 +1,76 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef TWO_ECHO_CLIENTS_H
+#define TWO_ECHO_CLIENTS_H
+
+/*
+ * Create the two UDP echo client tasks. One task uses the standard interface
+ * to send to and receive from an echo server. The other task uses the zero
+ * copy interface to send to and receive from an echo server.
+ */
+void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority );
+
+#endif /* TWO_ECHO_CLIENTS_H */
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c
new file mode 100644
index 0000000..5562279
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c
@@ -0,0 +1,188 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * This file, along with DemoIPTrace.h, provides a basic example use of the
+ * FreeRTOS+UDP trace macros. The statistics gathered here can be viewed in
+ * the command line interface.
+ * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+UDP includes. */
+#include "FreeRTOS_UDP_IP.h"
+#include "DemoIPTrace.h"
+
+/* It is possible to remove the trace macros using the
+configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */
+#if configINCLUDE_DEMO_DEBUG_STATS == 1
+
+/*
+ * Each row in the xIPTraceValues[] table contains a pointer to a function that
+ * updates the value for that row. Rows that latch the lowest value point to
+ * this function (for example, this function can be used to latch the lowest
+ * number of network buffers that were available during the execution of the
+ * stack).
+ */
+static void prvStoreLowest( uint32_t *pulCurrentValue, uint32_t ulCount );
+
+/*
+ * Each row in the xIPTraceValues[] table contains a pointer to a function that
+ * updates the value for that row. Rows that simply increment an event count
+ * point to this function.
+ */
+static void prvIncrementEventCount( uint32_t *pulCurrentValue, uint32_t ulCount );
+
+
+xExampleDebugStatEntry_t xIPTraceValues[] =
+{
+ /* Comment out array entries to remove individual trace items. */
+
+ { iptraceID_NETWORK_INTERFACE_RECEIVE, ( const uint8_t * const ) "Packets received by the network interface", prvIncrementEventCount, 0 },
+ { iptraceID_NETWORK_INTERFACE_TRANSMIT, ( const uint8_t * const ) "Count of transmitted packets", prvIncrementEventCount, 0 },
+ { iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, ( const uint8_t * const ) "Count of packets dropped to generate ARP", prvIncrementEventCount, 0 },
+ { iptraceID_NETWORK_BUFFER_OBTAINED, ( const uint8_t * const ) "Lowest ever available network buffers", prvStoreLowest, 0xffffUL },
+ { iptraceID_NETWORK_EVENT_RECEIVED, ( const uint8_t * const ) "Lowest ever free space in network event queue", prvStoreLowest, 0xffffUL },
+ { iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, ( const uint8_t * const ) "Count of failed attempts to obtain a network buffer",prvIncrementEventCount, 0 },
+ { iptraceID_ARP_TABLE_ENTRY_EXPIRED, ( const uint8_t * const ) "Count of expired ARP entries", prvIncrementEventCount, 0 },
+ { iptraceID_FAILED_TO_CREATE_SOCKET, ( const uint8_t * const ) "Count of failures to create a socket", prvIncrementEventCount, 0 },
+ { iptraceID_RECVFROM_DISCARDING_BYTES, ( const uint8_t * const ) "Count of times recvfrom() has discarding bytes", prvIncrementEventCount, 0 },
+ { iptraceID_ETHERNET_RX_EVENT_LOST, ( const uint8_t * const ) "Count of lost Ethenret Rx events (event queue full?)",prvIncrementEventCount, 0 },
+ { iptraceID_STACK_TX_EVENT_LOST, ( const uint8_t * const ) "Count of lost IP stack events (event queue full?)", prvIncrementEventCount, 0 },
+ { ipconfigID_BIND_FAILED, ( const uint8_t * const ) "Count of failed calls to bind()", prvIncrementEventCount, 0 },
+ { iptraceID_RECVFROM_TIMEOUT, ( const uint8_t * const ) "Count of receive timeouts", prvIncrementEventCount, 0 },
+ { iptraceID_SENDTO_DATA_TOO_LONG, ( const uint8_t * const ) "Count of failed sends due to oversized payload", prvIncrementEventCount, 0 },
+ { iptraceID_SENDTO_SOCKET_NOT_BOUND, ( const uint8_t * const ) "Count of failed sends due to unbound socket", prvIncrementEventCount, 0 },
+ { iptraceID_NO_BUFFER_FOR_SENDTO, ( const uint8_t * const ) "Count of failed transmits due to timeout", prvIncrementEventCount, 0 },
+ { iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, ( const uint8_t * const ) "Number of times task had to wait to obtain a DMA Tx descriptor", prvIncrementEventCount, 0 },
+ { iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, ( const uint8_t * const ) "Failed to notify select group", prvIncrementEventCount, 0 }
+};
+
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xExampleDebugStatEntries( void )
+{
+ /* Return the number of entries in the xIPTraceValues[] table. */
+ return ( portBASE_TYPE ) ( sizeof( xIPTraceValues ) / sizeof( xExampleDebugStatEntry_t ) );
+}
+/*-----------------------------------------------------------*/
+
+void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue )
+{
+portBASE_TYPE xIndex;
+const portBASE_TYPE xEntries = sizeof( xIPTraceValues ) / sizeof( xExampleDebugStatEntry_t );
+
+ /* Update an entry in the xIPTraceValues[] table. Each row in the table
+ includes a pointer to a function that performs the actual update. This
+ function just executes the update function from that table row. */
+ for( xIndex = 0; xIndex < xEntries; xIndex++ )
+ {
+ if( xIPTraceValues[ xIndex ].ucIdentifier == ucIdentifier )
+ {
+ xIPTraceValues[ xIndex ].vPerformAction( &( xIPTraceValues[ xIndex ].ulData ), ulValue );
+ break;
+ }
+ }
+
+ configASSERT( xIndex != xEntries );
+}
+/*-----------------------------------------------------------*/
+
+static void prvIncrementEventCount( uint32_t *pulCurrentValue, uint32_t ulCount )
+{
+ /* Each row in the xIPTraceValues[] table contains a pointer to a function
+ that updates the value for that row. Rows that simply increment an event
+ count point to this function. */
+ ( void ) ulCount;
+ ( *pulCurrentValue )++;
+}
+/*-----------------------------------------------------------*/
+
+static void prvStoreLowest( uint32_t *pulCurrentValue, uint32_t ulCount )
+{
+ /* Each row in the xIPTraceValues[] table contains a pointer to a function
+ that updates the value for that row. Rows that latch the lowest value
+ point to this function (for example, this function can be used to latch
+ the lowest number of network buffers that were available during the
+ execution of the stack). */
+ if( ulCount < *pulCurrentValue )
+ {
+ *pulCurrentValue = ulCount;
+ }
+}
+/*-----------------------------------------------------------*/
+
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */
+
+
+
+
diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h
new file mode 100644
index 0000000..f474707
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h
@@ -0,0 +1,159 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * This file, along with DemoIPTrace.h, provides a basic example use of the
+ * FreeRTOS+UDP trace macros. The statistics gathered here can be viewed in
+ * the command line interface.
+ * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml
+ */
+
+#ifndef DEMO_IP_TRACE_MACROS_H
+#define DEMO_IP_TRACE_MACROS_H
+
+typedef void ( *vTraceAction_t )( uint32_t *, uint32_t );
+
+/* Type that defines each statistic being gathered. */
+typedef struct ExampleDebugStatEntry
+{
+ uint8_t ucIdentifier; /* Unique identifier for statistic. */
+ const uint8_t * const pucDescription; /* Text description for the statistic. */
+ vTraceAction_t vPerformAction; /* Action to perform when the statistic is updated (increment counter, store minimum value, store maximum value, etc. */
+ uint32_t ulData; /* The meaning of this data is dependent on the trace macro ID. */
+} xExampleDebugStatEntry_t;
+
+/* Unique identifiers used to locate the entry for each trace macro in the
+xIPTraceValues[] table defined in DemoIPTrace.c. */
+#define iptraceID_NETWORK_INTERFACE_RECEIVE 0
+#define iptraceID_NETWORK_INTERFACE_TRANSMIT 1
+#define iptraceID_PACKET_DROPPED_TO_GENERATE_ARP 2
+/* Do not change IDs above this line as the ID is shared with a FreeRTOS+Nabto
+demo. */
+#define iptraceID_NETWORK_BUFFER_OBTAINED 3
+#define iptraceID_NETWORK_BUFFER_OBTAINED_FROM_ISR 4
+#define iptraceID_NETWORK_EVENT_RECEIVED 5
+#define iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER 6
+#define iptraceID_ARP_TABLE_ENTRY_EXPIRED 7
+#define iptraceID_FAILED_TO_CREATE_SOCKET 8
+#define iptraceID_RECVFROM_DISCARDING_BYTES 9
+#define iptraceID_ETHERNET_RX_EVENT_LOST 10
+#define iptraceID_STACK_TX_EVENT_LOST 11
+#define ipconfigID_BIND_FAILED 12
+#define iptraceID_RECVFROM_TIMEOUT 13
+#define iptraceID_SENDTO_DATA_TOO_LONG 14
+#define iptraceID_SENDTO_SOCKET_NOT_BOUND 15
+#define iptraceID_NO_BUFFER_FOR_SENDTO 16
+#define iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR 17
+#define iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP 18
+
+/* It is possible to remove the trace macros using the
+configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */
+#if configINCLUDE_DEMO_DEBUG_STATS == 1
+
+ /* The trace macro definitions themselves. Any trace macros left undefined
+ will default to be empty macros. */
+ #define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )
+ #define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )
+
+ #define iptraceNETWORK_EVENT_RECEIVED( eEvent ) { \
+ uint16_t usSpace; \
+ usSpace = ( uint16_t ) uxQueueMessagesWaiting( xNetworkEventQueue ); \
+ /* Minus one as an event was removed before the space was queried. */ \
+ usSpace = ( ipconfigEVENT_QUEUE_LENGTH - usSpace ) - 1; \
+ vExampleDebugStatUpdate( iptraceID_NETWORK_EVENT_RECEIVED, usSpace ); \
+ }
+
+ #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER() vExampleDebugStatUpdate( iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, 0 )
+ #define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_ARP_TABLE_ENTRY_EXPIRED, 0 )
+ #define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, 0 )
+ #define iptraceFAILED_TO_CREATE_SOCKET() vExampleDebugStatUpdate( iptraceID_FAILED_TO_CREATE_SOCKET, 0 )
+ #define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded ) vExampleDebugStatUpdate( iptraceID_RECVFROM_DISCARDING_BYTES, 0 )
+ #define iptraceETHERNET_RX_EVENT_LOST() vExampleDebugStatUpdate( iptraceID_ETHERNET_RX_EVENT_LOST, 0 )
+ #define iptraceSTACK_TX_EVENT_LOST( xEvent ) vExampleDebugStatUpdate( iptraceID_STACK_TX_EVENT_LOST, 0 )
+ #define iptraceBIND_FAILED( xSocket, usPort ) vExampleDebugStatUpdate( ipconfigID_BIND_FAILED, 0 )
+ #define iptraceNETWORK_INTERFACE_TRANSMIT() vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_TRANSMIT, 0 )
+ #define iptraceRECVFROM_TIMEOUT() vExampleDebugStatUpdate( iptraceID_RECVFROM_TIMEOUT, 0 )
+ #define iptraceSENDTO_DATA_TOO_LONG() vExampleDebugStatUpdate( iptraceID_SENDTO_DATA_TOO_LONG, 0 )
+ #define iptraceSENDTO_SOCKET_NOT_BOUND() vExampleDebugStatUpdate( iptraceID_SENDTO_SOCKET_NOT_BOUND, 0 )
+ #define iptraceNO_BUFFER_FOR_SENDTO() vExampleDebugStatUpdate( iptraceID_NO_BUFFER_FOR_SENDTO, 0 )
+ #define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() vExampleDebugStatUpdate( iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, 0 )
+ #define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket ) vExampleDebugStatUpdate( iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, 0 )
+ #define iptraceNETWORK_INTERFACE_RECEIVE() vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_RECEIVE, 0 )
+
+ /*
+ * The function that updates a line in the xIPTraceValues table.
+ */
+ void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue );
+
+ /*
+ * Returns the number of entries in the xIPTraceValues table.
+ */
+ portBASE_TYPE xExampleDebugStatEntries( void );
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */
+
+
+#endif /* DEMO_IP_TRACE_MACROS_H */
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c
new file mode 100644
index 0000000..b67b9e4
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c
@@ -0,0 +1,419 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+Trace includes. */
+#include "trcUser.h"
+
+/*
+ * Writes trace data to a disk file when the trace recording is stopped.
+ * This function will simply overwrite any trace files that already exist.
+ */
+static void prvSaveTraceFile( void );
+
+/*
+ * Defines a command that returns a table showing the state of each task at the
+ * time the command is called.
+ */
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that returns a table showing how much time each task has
+ * spent in the Running state.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that expects exactly three parameters. Each of the three
+ * parameter are echoed back one at a time.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that can take a variable number of parameters. Each
+ * parameter is echoes back one at a time.
+ */
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that starts/stops events being recorded for offline viewing
+ * in FreeRTOS+Trace.
+ */
+static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/* Structure that defines the "run-time-stats" command line command. */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+ "run-time-stats", /* The command string to type. */
+ "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n",
+ prvRunTimeStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+ "task-stats", /* The command string to type. */
+ "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n",
+ prvTaskStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command. This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+ "echo_3_parameters",
+ "\r\necho_3_parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n\r\n",
+ prvThreeParameterEchoCommand, /* The function to run. */
+ 3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command. This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+ "echo_parameters",
+ "\r\necho_parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n",
+ prvParameterEchoCommand, /* The function to run. */
+ -1 /* The user can enter any number of commands. */
+};
+
+/* Structure that defines the "trace" command line command. This takes a single
+parameter, which can be either "start" or "stop". */
+static const CLI_Command_Definition_t xStartTrace =
+{
+ "trace",
+ "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n",
+ prvStartStopTraceCommand, /* The function to run. */
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */
+};
+
+/*-----------------------------------------------------------*/
+
+void vRegisterCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xStartTrace );
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskList( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE lParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The three parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, lParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ if( lParameterNumber == 3L )
+ {
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ xReturn = pdFALSE;
+ lParameterNumber = 0L;
+ }
+ else
+ {
+ /* There are more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE lParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter != NULL )
+ {
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, lParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* There might be more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ else
+ {
+ /* No more parameters were found. Make sure the write buffer does
+ not contain a valid string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* No more data to return. */
+ xReturn = pdFALSE;
+
+ /* Start over the next time this command is executed. */
+ lParameterNumber = 0;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE lParameterStringLength;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* There are only two valid parameter values. */
+ if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 )
+ {
+ /* Start or restart the trace. */
+ vTraceStop();
+ vTraceClear();
+ uiTraceStart();
+
+ sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" );
+ }
+ else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 )
+ {
+ /* End the trace, if one is running. */
+ vTraceStop();
+ sprintf( pcWriteBuffer, "Stopping trace recording and dumping log to disk.\r\n" );
+ prvSaveTraceFile();
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+ }
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSaveTraceFile( void )
+{
+FILE* pxOutputFile;
+
+ fopen_s( &pxOutputFile, "Trace.dump", "wb");
+
+ if( pxOutputFile != NULL )
+ {
+ fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile );
+ fclose( pxOutputFile );
+ printf( "\r\nTrace output saved to Trace.dump\r\n" );
+ }
+ else
+ {
+ printf( "\r\nFailed to create trace dump file\r\n" );
+ }
+}
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h
new file mode 100644
index 0000000..1c410dd
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h
@@ -0,0 +1,162 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <stdint.h>
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 0 ) /* This parameter has no effect when heap_3.c is included in the project. */
+#define configMAX_TASK_NAME_LEN ( 7 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY 2
+#define configTIMER_QUEUE_LENGTH 20
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+
+/* This demo makes use of one or more example stats formatting functions. These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form. See the notes in the implementation of vTaskList() within
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+
+/* Run time stats gathering definitions. */
+unsigned long ulGetRunTimeCounterValue( void );
+void vConfigureTimerForRunTimeStats( void );
+#define configGENERATE_RUN_TIME_STATS 1
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
+#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
+
+extern void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+/* The UDP port to use for incoming command inputs. The outgoing port is
+set to ( configUDP_CLI_PORT_NUMBER + 1 ). */
+#define configUDP_CLI_PORT_NUMBER 5001
+
+/* The size of the global output buffer that is available for use when there
+are multiple command interpreters running at once (for example, one on a UART
+and one on TCP/IP). This is done to prevent an output buffer being defined by
+each implementation - which would waste RAM. In this case, there is only one
+command interpreter running, and it has its own local output buffer, so the
+global buffer is just set to be one byte long as it is not used and should not
+take up unnecessary RAM. */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1
+
+
+/* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */
+#include "trcKernelPort.h"
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln
new file mode 100644
index 0000000..3f819af
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Visual C++ Express 2010
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|Win32 = Debug|Win32
+ Release|Win32 = Release|Win32
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url
new file mode 100644
index 0000000..8ee5a95
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url
@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c
new file mode 100644
index 0000000..0ecc0b1
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c
@@ -0,0 +1,141 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * Utility functions required to gather run time statistics. See:
+ * http://www.freertos.org/rtos-run-time-stats.html
+ *
+ * Note that this is a simulated port, where simulated time is a lot slower than
+ * real time, therefore the run time counter values have no real meaningful
+ * units.
+ *
+ * Also note that it is assumed this demo is going to be used for short periods
+ * of time only, and therefore timer overflows are not handled.
+*/
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+
+/* FreeRTOS+Trace includes. */
+#include "trcUser.h"
+
+/* Variables used in the creation of the run time stats time base. Run time
+stats record how much time each task spends in the Running state. */
+static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL;
+
+/*-----------------------------------------------------------*/
+
+void vConfigureTimerForRunTimeStats( void )
+{
+LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue;
+
+ /* Initialise the variables used to create the run time stats time base.
+ Run time stats record how much time each task spends in the Running
+ state. */
+
+ if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 )
+ {
+ llTicksPerHundedthMillisecond = 1;
+ }
+ else
+ {
+ /* How many times does the performance counter increment in 1/100th
+ millisecond. */
+ llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL;
+
+ /* What is the performance counter value now, this will be subtracted
+ from readings taken at run time. */
+ QueryPerformanceCounter( &liInitialRunTimeValue );
+ llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart;
+ }
+}
+/*-----------------------------------------------------------*/
+
+unsigned long ulGetRunTimeCounterValue( void )
+{
+LARGE_INTEGER liCurrentCount;
+unsigned long ulReturn;
+
+ /* What is the performance counter value now? */
+ QueryPerformanceCounter( &liCurrentCount );
+
+ /* Subtract the performance counter value reading taken when the
+ application started to get a count from that reference point, then
+ scale to (simulated) 1/100ths of a millisecond. */
+ if( llTicksPerHundedthMillisecond == 0 )
+ {
+ /* The trace macros can call this function before the kernel has been
+ started, in which case llTicksPerHundedthMillisecond will not have been
+ initialised. */
+ ulReturn = 0;
+ }
+ else
+ {
+ ulReturn = ( unsigned long ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond );
+ }
+
+ return ulReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h
new file mode 100644
index 0000000..a81aeb8
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h
@@ -0,0 +1,530 @@
+/*******************************************************************************
+ * Tracealyzer v2.6.0 Recorder Library
+ * Percepio AB, www.percepio.com
+ *
+ * trcConfig.h
+ *
+ * Configuration parameters for the trace recorder library. Before using the
+ * trace recorder library, please check that the default settings are
+ * appropriate for your system, and if necessary adjust these. Most likely, you
+ * will need to adjust the NTask, NISR, NQueue, NMutex and NSemaphore values to
+ * reflect the number of such objects in your system. These may be
+ * over-approximated, although larger values values implies more RAM usage.
+ *
+ * Terms of Use
+ * This software is copyright Percepio AB. The recorder library is free for
+ * use together with Percepio products. You may distribute the recorder library
+ * in its original form, including modifications in trcHardwarePort.c/.h
+ * given that these modification are clearly marked as your own modifications
+ * and documented in the initial comment section of these source files.
+ * This software is the intellectual property of Percepio AB and may not be
+ * sold or in other ways commercially redistributed without explicit written
+ * permission by Percepio AB.
+ *
+ * Disclaimer
+ * The trace tool and recorder library is being delivered to you AS IS and
+ * Percepio AB makes no warranty as to its use or performance. Percepio AB does
+ * not and cannot warrant the performance or results you may obtain by using the
+ * software or documentation. Percepio AB make no warranties, express or
+ * implied, as to noninfringement of third party rights, merchantability, or
+ * fitness for any particular purpose. In no event will Percepio AB, its
+ * technology partners, or distributors be liable to you for any consequential,
+ * incidental or special damages, including any lost profits or lost savings,
+ * even if a representative of Percepio AB has been advised of the possibility
+ * of such damages, or for any claim by any third party. Some jurisdictions do
+ * not allow the exclusion or limitation of incidental, consequential or special
+ * damages, or the exclusion of implied warranties or limitations on how long an
+ * implied warranty may last, so the above limitations may not apply to you.
+ *
+ * Copyright Percepio AB, 2013.
+ * www.percepio.com
+ ******************************************************************************/
+
+#ifndef TRCCONFIG_H
+#define TRCCONFIG_H
+
+/*******************************************************************************
+ * CONFIGURATION RELATED TO CAPACITY AND ALLOCATION
+ ******************************************************************************/
+
+/*******************************************************************************
+ * EVENT_BUFFER_SIZE
+ *
+ * Macro which should be defined as an integer value.
+ *
+ * This defines the capacity of the event buffer, i.e., the number of records
+ * it may store. Each registered event typically use one record (4 byte), but
+ * vTracePrintF may use multiple records depending on the number of data args.
+ ******************************************************************************/
+
+#define EVENT_BUFFER_SIZE 4000 /* Adjust wrt. to available RAM */
+
+
+/*******************************************************************************
+ * USE_LINKER_PRAGMA
+ *
+ * Macro which should be defined as an integer value, default is 0.
+ *
+ * If this is 1, the header file "recorderdata_linker_pragma.h" is included just
+ * before the declaration of RecorderData (in trcBase.c), i.e., the trace data
+ * structure. This allows the user to specify a pragma with linker options.
+ *
+ * Example (for IAR Embedded Workbench and NXP LPC17xx):
+ * #pragma location="AHB_RAM_MEMORY"
+ *
+ * This example instructs the IAR linker to place RecorderData in another RAM
+ * bank, the AHB RAM. This can also be used for other compilers with a similar
+ * pragmas for linker options.
+ *
+ * Note that this only applies if using static allocation, see below.
+ ******************************************************************************/
+
+#define USE_LINKER_PRAGMA 0
+
+
+/*******************************************************************************
+ * SYMBOL_TABLE_SIZE
+ *
+ * Macro which should be defined as an integer value.
+ *
+ * This defines the capacity of the symbol table, in bytes. This symbol table
+ * stores User Events labels and names of deleted tasks, queues, or other kernel
+ * objects. Note that the names of active objects not stored here but in the
+ * Object Table. Thus, if you don't use User Events or delete any kernel
+ * objects you set this to a very low value, e.g. 4, but not zero (0) since
+ * this causes a declaration of a zero-sized array, for which the C compiler
+ * behavior is not standardized and may cause misaligned data.
+ ******************************************************************************/
+#define SYMBOL_TABLE_SIZE 1000
+
+#if (SYMBOL_TABLE_SIZE == 0)
+#error "SYMBOL_TABLE_SIZE may not be zero!"
+#endif
+
+/*******************************************************************************
+ * USE_SEPARATE_USER_EVENT_BUFFER
+ *
+ * Macro which should be defined as an integer value.
+ * Default is zero (0).
+ *
+ * This enables and disables the use of the separate user event buffer.
+ *
+ * Note: When using the separate user event buffer, you may get an artificial
+ * task instance named "Unknown actor". This is added as a placeholder when the
+ * user event history is longer than the task scheduling history.
+ ******************************************************************************/
+#define USE_SEPARATE_USER_EVENT_BUFFER 0
+
+/*******************************************************************************
+ * USER_EVENT_BUFFER_SIZE
+ *
+ * Macro which should be defined as an integer value.
+ *
+ * This defines the capacity of the user event buffer, in number of slots.
+ * A single user event can use between 1 and X slots, depending on the data.
+ *
+ * Only in use if USE_SEPARATE_USER_EVENT_BUFFER is set to 1.
+ ******************************************************************************/
+#define USER_EVENT_BUFFER_SIZE 500
+
+/*******************************************************************************
+ * USER_EVENT_CHANNELS
+ *
+ * Macro which should be defined as an integer value.
+ *
+ * This defines the number of allowed user event channels.
+ *
+ * Only in use if USE_SEPARATE_USER_EVENT_BUFFER is set to 1.
+ ******************************************************************************/
+#define CHANNEL_FORMAT_PAIRS 32
+
+/*******************************************************************************
+ * NTask, NISR, NQueue, NSemaphore, NMutex
+ *
+ * A group of Macros which should be defined as an integer value of zero (0)
+ * or larger.
+ *
+ * This defines the capacity of the Object Property Table - the maximum number
+ * of objects active at any given point within each object class.
+ *
+ * NOTE: In case objects are deleted and created during runtime, this setting
+ * does not limit the total amount of objects, only the number of concurrently
+ * active objects.
+ *
+ * Using too small values will give an error message through the vTraceError
+ * routine, which makes the error message appear when opening the trace data
+ * in Tracealyzer. If you are using the recorder status monitor task,
+ * any error messages are displayed in console prints, assuming that the
+ * print macro has been defined properly (vConsolePrintMessage).
+ *
+ * It can be wise to start with very large values for these constants,
+ * unless you are very confident on these numbers. Then do a recording and
+ * check the actual usage in Tracealyzer. This is shown by selecting
+ * View -> Trace Details -> Resource Usage -> Object Table
+ *
+ * NOTE 2: Remember to account for all tasks and other objects created by
+ * the kernel, such as the IDLE task, any timer tasks, and any tasks created
+ * by other 3rd party software components, such as communication stacks.
+ * Moreover, one task slot is used to indicate "(startup)", i.e., a fictive
+ * task that represent the time before the scheduler starts.
+ * NTask should thus be at least 2-3 slots larger than your application task count.
+ *
+ ******************************************************************************/
+#define NTask 15
+#define NISR 15
+#define NQueue 15
+#define NSemaphore 15
+#define NMutex 15
+#define NTimer 15
+#define NEventGroup 15
+
+/* Maximum object name length for each class (includes zero termination) */
+#define NameLenTask 15
+#define NameLenISR 15
+#define NameLenQueue 15
+#define NameLenSemaphore 15
+#define NameLenMutex 15
+#define NameLenTimer 15
+#define NameLenEventGroup 15
+
+/******************************************************************************
+ * TRACE_DESCRIPTION
+ *
+ * Macro which should be defined as a string.
+ *
+ * This string is stored in the trace and displayed in Tracealyzer. Can be
+ * used to store, e.g., system version or build date. This is also used to store
+ * internal error messages from the recorder, which if occurs overwrites the
+ * value defined here. This may be maximum 256 chars.
+ *****************************************************************************/
+#define TRACE_DESCRIPTION "Tracealyzer Recorder Test Program"
+
+/******************************************************************************
+ * TRACE_DESCRIPTION_MAX_LENGTH
+ *
+ * The maximum length (including zero termination) for the TRACE_DESCRIPTION
+ * string. Since this string also is used for internal error messages from the
+ * recorder do not make it too short, as this may truncate the error messages.
+ * Default is 80.
+ * Maximum allowed length is 256 - the trace will fail to load if longer.
+ *****************************************************************************/
+#define TRACE_DESCRIPTION_MAX_LENGTH 80
+
+
+/******************************************************************************
+ * TRACE_DATA_ALLOCATION
+ *
+ * This defines how to allocate the recorder data structure, i.e., using a
+ * static declaration or using a dynamic allocation in runtime (malloc).
+ *
+ * Should be one of these two options:
+ * - TRACE_DATA_ALLOCATION_STATIC (default)
+ * - TRACE_DATA_ALLOCATION_DYNAMIC
+ *
+ * Using static allocation has the benefits of compile-time errors if the buffer
+ * is too large (too large constants in trcConfig.h) and no need to call the
+ * initialization routine (xTraceInitTraceData).
+ *
+ * Using dynamic allocation may give more flexibility in some cases.
+ *****************************************************************************/
+
+#define TRACE_DATA_ALLOCATION TRACE_DATA_ALLOCATION_STATIC
+
+
+/******************************************************************************
+ * CONFIGURATION REGARDING WHAT CODE/FEATURES TO INCLUDE
+ *****************************************************************************/
+
+/******************************************************************************
+ * USE_TRACE_ASSERT
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 0.
+ *
+ * If this is one (1), the TRACE_ASSERT macro will verify that a condition is
+ * true. If the condition is false, vTraceError() will be called.
+ *****************************************************************************/
+#define USE_TRACE_ASSERT 1
+
+/******************************************************************************
+ * INCLUDE_FLOAT_SUPPORT
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * If this is zero (0), all references to floating point values are removed,
+ * in case floating point values are not supported by the platform used.
+ * Floating point values are only used in vTracePrintF and its subroutines, to
+ * store float (%f) or double (%lf) argments.
+ *
+ * Note: vTracePrintF can still be used with integer and string arguments in
+ * either case.
+ *****************************************************************************/
+#define INCLUDE_FLOAT_SUPPORT 0
+
+/******************************************************************************
+ * INCLUDE_USER_EVENTS
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * If this is zero (0) the code for creating User Events is excluded to
+ * reduce code size. User Events are application-generated events, like
+ * "printf" but for the trace log instead of console output. User Events are
+ * much faster than a printf and can therefore be used in timing critical code.
+ * See vTraceUserEvent() and vTracePrintF() in trcUser.h
+ *
+ * Note that User Events are not displayed in FreeRTOS+Trace Free Edition.
+ *****************************************************************************/
+#define INCLUDE_USER_EVENTS 1
+
+/*****************************************************************************
+ * INCLUDE_READY_EVENTS
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * If this is zero (0), the code for recording Ready events is
+ * excluded. Note, this will make it impossible to calculate the correct
+ * response times.
+ *****************************************************************************/
+#define INCLUDE_READY_EVENTS 1
+
+/*****************************************************************************
+ * INCLUDE_NEW_TIME_EVENTS
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 0.
+ *
+ * If this is zero (1), events will be generated whenever the os clock is
+ * increased.
+ *****************************************************************************/
+#define INCLUDE_NEW_TIME_EVENTS 0
+
+/*****************************************************************************
+ * INCLUDE_ISR_TRACING
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * If this is zero (0), the code for recording Interrupt Service Routines is
+ * excluded to reduce code size.
+ *
+ * Note, if the kernel has no central interrupt dispatcher, recording ISRs
+ * require that you insert calls to vTraceStoreISRBegin and vTraceStoreISREnd
+ * in your interrupt handlers.
+ *****************************************************************************/
+#define INCLUDE_ISR_TRACING 1
+
+/******************************************************************************
+ * INCLUDE_OBJECT_DELETE
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * This must be enabled (1) if tasks, queues or other
+ * traced kernel objects are deleted at runtime. If no deletes are made, this
+ * can be set to 0 in order to exclude the delete-handling code.
+ *****************************************************************************/
+#define INCLUDE_OBJECT_DELETE 1
+
+/******************************************************************************
+ * INCLUDE_MEMMANG_EVENTS
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * This controls if malloc and free calls should be traced. Set this to zero to
+ * exclude malloc/free calls from the tracing.
+ *****************************************************************************/
+#define INCLUDE_MEMMANG_EVENTS 1
+
+/******************************************************************************
+ * CONFIGURATION RELATED TO BEHAVIOR
+ *****************************************************************************/
+
+/******************************************************************************
+ * TRACE_RECORDER_STORE_MODE
+ *
+ * Macro which should be defined as one of:
+ * - TRACE_STORE_MODE_RING_BUFFER
+ * - TRACE_STORE_MODE_STOP_WHEN_FULL
+ * Default is TRACE_STORE_MODE_RING_BUFFER.
+ *
+ * With TRACE_RECORDER_STORE_MODE set to TRACE_STORE_MODE_RING_BUFFER, the events are
+ * stored in a ring buffer, i.e., where the oldest events are overwritten when
+ * the buffer becomes full. This allows you to get the last events leading up
+ * to an interesting state, e.g., an error, without having a large trace buffer
+ * for string the whole run since startup. In this mode, the recorder can run
+ * "forever" as the buffer never gets full, i.e., in the sense that it always
+ * has room for more events.
+ *
+ * To fetch the trace in mode TRACE_STORE_MODE_RING_BUFFER, you need to first halt the
+ * system using your debugger and then do a RAM dump, or to explicitly stop the
+ * recorder using vTraceStop() and then store/upload the trace data using a
+ * task that you need to provide yourself. The trace data is found in the struct
+ * RecorderData, initialized in trcBase.c.
+ *
+ * Note that, if you upload the trace using a RAM dump, i.e., when the system is
+ * halted on a breakpoint or by a debugger command, there is no need to stop the
+ * recorder first.
+ *
+ * When TRACE_RECORDER_STORE_MODE is TRACE_STORE_MODE_STOP_WHEN_FULL, the recording is
+ * stopped when the buffer becomes full. When the recorder stops itself this way
+ * vTracePortEnd() is called which allows for custom actions, such as triggering
+ * a task that stores the trace buffer, i.e., in case taking a RAM dump
+ * using an on-chip debugger is not possible. In the Windows port, vTracePortEnd
+ * saves the trace to file directly, but this is not recommended in a real-time
+ * system since the scheduler is blocked during the processing of vTracePortEnd.
+ *****************************************************************************/
+
+#define TRACE_RECORDER_STORE_MODE TRACE_STORE_MODE_RING_BUFFER
+
+/******************************************************************************
+ * STOP_AFTER_N_EVENTS
+ *
+ * Macro which should be defined as an integer value, or not defined.
+ * Default is -1
+ *
+ * STOP_AFTER_N_EVENTS is intended for tests of the ring buffer mode (when
+ * RECORDER_STORE_MODE is STORE_MODE_RING_BUFFER). It stops the recording when
+ * the specified number of events has been observed. This value can be larger
+ * than the buffer size, to allow for test of the "wrapping around" that occurs
+ * in ring buffer mode . A negative value (or no definition of this macro)
+ * disables this feature.
+ *****************************************************************************/
+#define STOP_AFTER_N_EVENTS -1
+
+/******************************************************************************
+ * USE_IMPLICIT_IFE_RULES
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 1.
+ *
+ * ### Instance Finish Events (IFE) ###
+ *
+ * For tasks with "infinite" main loops (non-terminating tasks), the concept
+ * of a task instance has no clear definition, it is an application-specific
+ * thing. Tracealyzer allows you to define Instance Finish Events (IFEs),
+ * which marks the point in a cyclic task when the "task instance" ends.
+ * The IFE is a blocking kernel call, typically in the main loop of a task
+ * which typically reads a message queue, waits for a semaphore or performs
+ * an explicit delay.
+ *
+ * If USE_IMPLICIT_IFE_RULES is one (1), the kernel macros (trcKernelPort.h)
+ * will define what kernel calls are considered by default to be IFEs.
+ *
+ * However, Implicit IFEs only applies to blocking kernel calls. If a
+ * service reads a message without blocking, it does not create a new
+ * instance since no blocking occurred.
+ *
+ * Moreover, the actual IFE might sometimes be another blocking call. We
+ * therefore allow for user-defined Explicit IFEs by calling
+ *
+ * vTraceTaskInstanceIsFinished()
+ *
+ * right before the kernel call considered as IFE. This does not create an
+ * additional event but instead stores the service code and object handle
+ * of the IFE call as properties of the task.
+ *
+ * If using Explicit IFEs and the task also calls an Implicit IFE, this may
+ * result in additional incorrect task instances.
+ * This is solved by disabling the Implicit IFEs for the task, by adding
+ * a call to
+ *
+ * vTraceTaskSkipDefaultInstanceFinishedEvents()
+ *
+ * in the very beginning of that task. This allows you to combine Explicit IFEs
+ * for some tasks with Implicit IFEs for the rest of the tasks, if
+ * USE_IMPLICIT_IFE_RULES is 1.
+ *
+ * By setting USE_IMPLICIT_IFE_RULES to zero (0), the implicit IFEs are disabled
+ * for all tasks. Tasks will then be considered to have a single instance only,
+ * covering all execution fragments, unless you define an explicit IFE in each
+ * task by calling vTraceTaskInstanceIsFinished before the blocking call.
+ *****************************************************************************/
+#define USE_IMPLICIT_IFE_RULES 1
+
+
+/******************************************************************************
+ * USE_16BIT_OBJECT_HANDLES
+ *
+ * Macro which should be defined as either zero (0) or one (1).
+ * Default is 0.
+ *
+ * If set to 0 (zero), the recorder uses 8-bit handles to identify kernel
+ * objects such as tasks and queues. This limits the supported number of
+ * concurrently active objects to 255 of each type (object class).
+ *
+ * If set to 1 (one), the recorder uses 16-bit handles to identify kernel
+ * objects such as tasks and queues. This limits the supported number of
+ * concurrent objects to 65535 of each type (object class). However, since the
+ * object property table is limited to 64 KB, the practical limit is about
+ * 3000 objects in total.
+ *
+ * NOTE: An object with a high ID (> 255) will generate an extra event
+ * (= 4 byte) in the event buffer.
+ *
+ * NOTE: Some internal tables in the recorder gets larger when using 16-bit
+ * handles. The additional RAM usage is 5-10 byte plus 1 byte per kernel object
+ *, i.e., task, queue, semaphore, mutex, etc.
+ *****************************************************************************/
+#define USE_16BIT_OBJECT_HANDLES 0
+
+/****** Port Name ******************** Code ** Official ** OS Platform ******
+* PORT_APPLICATION_DEFINED -2 - -
+* PORT_NOT_SET -1 - -
+* PORT_HWIndependent 0 Yes Any
+* PORT_Win32 1 Yes FreeRTOS Win32
+* PORT_Atmel_AT91SAM7 2 No Any
+* PORT_Atmel_UC3A0 3 No Any
+* PORT_ARM_CortexM 4 Yes Any
+* PORT_Renesas_RX600 5 Yes Any
+* PORT_Microchip_dsPIC_AND_PIC24 6 Yes Any
+* PORT_TEXAS_INSTRUMENTS_TMS570 7 No Any
+* PORT_TEXAS_INSTRUMENTS_MSP430 8 No Any
+* PORT_MICROCHIP_PIC32 9 No Any
+* PORT_XILINX_PPC405 10 No FreeRTOS
+* PORT_XILINX_PPC440 11 No FreeRTOS
+* PORT_XILINX_MICROBLAZE 12 No Any
+* PORT_NXP_LPC210X 13 No Any
+*****************************************************************************/
+#define SELECTED_PORT PORT_Win32
+
+#if (SELECTED_PORT == PORT_NOT_SET)
+#error "You need to define SELECTED_PORT here!"
+#endif
+
+/******************************************************************************
+* USE_PRIMASK_CS (for Cortex M devices only)
+*
+* An integer constant that selects between two options for the critical
+* sections of the recorder library.
+ *
+* 0: The default FreeRTOS critical section (BASEPRI) - default setting
+* 1: Always disable ALL interrupts (using PRIMASK)
+ *
+* Option 0 uses the standard FreeRTOS macros for critical sections.
+* However, on Cortex-M devices they only disable interrupts with priorities
+* below a certain configurable level, while higher priority ISRs remain active.
+* Such high-priority ISRs may not use the recorder functions in this mode.
+*
+* Option 1 allows you to safely call the recorder from any ISR, independent of
+* the interrupt priority. This mode may however cause higher IRQ latencies
+* (some microseconds) since ALL configurable interrupts are disabled during
+* the recorder's critical sections in this mode, using the PRIMASK register.
+ ******************************************************************************/
+#define USE_PRIMASK_CS 0
+
+/******************************************************************************
+* HEAP_SIZE_BELOW_16M
+*
+* An integer constant that can be used to reduce the buffer usage of memory
+* allocation events (malloc/free). This value should be 1 if the heap size is
+* below 16 MB (2^24 byte), and you can live with addresses truncated to the
+* lower 24 bit. Otherwise set it to 0 to get the full 32-bit addresses.
+******************************************************************************/
+#define HEAP_SIZE_BELOW_16M 0
+
+#endif
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c
new file mode 100644
index 0000000..b5ea20e
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c
@@ -0,0 +1,259 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#pragma comment( lib, "ws2_32.lib" )
+
+/* Win32 includes. */
+#include <WinSock2.h>
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE 60
+
+/* Dimensions the buffer into which string outputs can be placed. */
+#define cmdMAX_OUTPUT_SIZE 1024
+
+/* Dimensions the buffer passed to the recvfrom() call. */
+#define cmdSOCKET_INPUT_BUFFER_SIZE 60
+
+/*
+ * Open and configure the UDP socket.
+ */
+static SOCKET prvOpenUDPSocket( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Task that provides the input and output for the FreeRTOS+CLI command
+ * interpreter. In this case a UDP port is used. See the URL in the comments
+ * within main.c for the location of the online documentation.
+ */
+void vUDPCommandInterpreterTask( void *pvParameters )
+{
+long lBytes, lByte;
+signed char cInChar, cInputIndex = 0;
+static signed char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ];
+portBASE_TYPE xMoreDataToFollow;
+volatile int iErrorCode = 0;
+struct sockaddr_in xClient;
+int xClientAddressLength = sizeof( struct sockaddr_in );
+SOCKET xSocket;
+
+ /* Just to prevent compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Attempt to open the socket. */
+ xSocket = prvOpenUDPSocket();
+
+ if( xSocket != INVALID_SOCKET )
+ {
+ for( ;; )
+ {
+ /* Wait for incoming data on the opened socket. */
+ lBytes = recvfrom( xSocket, cLocalBuffer, sizeof( cLocalBuffer ), 0, ( struct sockaddr * ) &xClient, &xClientAddressLength );
+
+ if( lBytes == SOCKET_ERROR )
+ {
+ /* Something went wrong, but it is not handled by this simple
+ example. */
+ iErrorCode = WSAGetLastError();
+ }
+ else
+ {
+ /* Process each received byte in turn. */
+ lByte = 0;
+ while( lByte < lBytes )
+ {
+ /* The next character in the input buffer. */
+ cInChar = cLocalBuffer[ lByte ];
+ lByte++;
+
+ /* Newline characters are taken as the end of the command
+ string. */
+ if( cInChar == '\n' )
+ {
+ /* Process the input string received prior to the
+ newline. */
+ do
+ {
+ /* Pass the string to FreeRTOS+CLI. */
+ xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE );
+
+ /* Send the output generated by the command's
+ implementation. */
+ sendto( xSocket, cOutputString, strlen( cOutputString ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
+
+ } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */
+
+ /* All the strings generated by the command processing
+ have been sent. Clear the input string ready to receive
+ the next command. */
+ cInputIndex = 0;
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+ /* Transmit a spacer, just to make the command console
+ easier to read. */
+ sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
+ }
+ else
+ {
+ if( cInChar == '\r' )
+ {
+ /* Ignore the character. Newlines are used to
+ detect the end of the input string. */
+ }
+ else if( cInChar == '\b' )
+ {
+ /* Backspace was pressed. Erase the last character
+ in the string - if any. */
+ if( cInputIndex > 0 )
+ {
+ cInputIndex--;
+ cInputString[ cInputIndex ] = '\0';
+ }
+ }
+ else
+ {
+ /* A character was entered. Add it to the string
+ entered so far. When a \n is entered the complete
+ string will be passed to the command interpreter. */
+ if( cInputIndex < cmdMAX_INPUT_SIZE )
+ {
+ cInputString[ cInputIndex ] = cInChar;
+ cInputIndex++;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* The socket could not be opened. */
+ vTaskDelete( NULL );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static SOCKET prvOpenUDPSocket( void )
+{
+WSADATA xWSAData;
+WORD wVersionRequested;
+struct sockaddr_in xServer;
+SOCKET xSocket = INVALID_SOCKET;
+
+ wVersionRequested = MAKEWORD( 2, 2 );
+
+ /* Prepare to use WinSock. */
+ if( WSAStartup( wVersionRequested, &xWSAData ) != 0 )
+ {
+ fprintf( stderr, "Could not open Windows connection.\n" );
+ }
+ else
+ {
+ xSocket = socket( AF_INET, SOCK_DGRAM, 0 );
+ if( xSocket == INVALID_SOCKET)
+ {
+ fprintf( stderr, "Could not create socket.\n" );
+ WSACleanup();
+ }
+ else
+ {
+ /* Zero out the server structure. */
+ memset( ( void * ) &xServer, 0x00, sizeof( struct sockaddr_in ) );
+
+ /* Set family and port. */
+ xServer.sin_family = AF_INET;
+ xServer.sin_port = htons( configUDP_CLI_PORT_NUMBER );
+
+ /* Assign the loopback address */
+ xServer.sin_addr.S_un.S_un_b.s_b1 = 127;
+ xServer.sin_addr.S_un.S_un_b.s_b2 = 0;
+ xServer.sin_addr.S_un.S_un_b.s_b3 = 0;
+ xServer.sin_addr.S_un.S_un_b.s_b4 = 1;
+
+ /* Bind the address to the socket. */
+ if( bind( xSocket, ( struct sockaddr * ) &xServer, sizeof( struct sockaddr_in ) ) == -1 )
+ {
+ fprintf( stderr, "Could not socket to port %d.\n", configUDP_CLI_PORT_NUMBER );
+ closesocket( xSocket );
+ xSocket = INVALID_SOCKET;
+ WSACleanup();
+ }
+ }
+ }
+
+ return xSocket;
+}
+
+
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new file mode 100644
index 0000000..e36a30f
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj
@@ -0,0 +1,166 @@
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new file mode 100644
index 0000000..42ab973
--- /dev/null
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@@ -0,0 +1,122 @@
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+ <Extensions>ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe</Extensions>
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diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.user
new file mode 100644
index 0000000..695b5c7
--- /dev/null
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diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c
new file mode 100644
index 0000000..7f868b8
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c
@@ -0,0 +1,302 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ ******************************************************************************
+ * -NOTE- The Win32 port is a simulation (or is that emulation?) only! Do not
+ * expect to get real time behaviour from the Win32 port or this demo
+ * application. It is provided as a convenient development and demonstration
+ * test bed only. This was tested using Windows XP on a dual core laptop.
+ *
+ * Windows will not be running the FreeRTOS simulator threads continuously, so
+ * the timing information in the FreeRTOS+Trace logs have no meaningful units.
+ * See the documentation page for the Windows simulator for an explanation of
+ * the slow timing:
+ * http://www.freertos.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html
+ * - READ THE WEB DOCUMENTATION FOR THIS PORT FOR MORE INFORMATION ON USING IT -
+ *
+ * Documentation for this demo can be found on:
+ * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml
+ ******************************************************************************
+ *
+ * This is a simple FreeRTOS Windows simulator project that makes it easy to
+ * evaluate FreeRTOS+CLI and FreeRTOS+Trace on a standard desktop PC, without
+ * any external hardware or interfaces being required.
+ *
+ * To keep everything as simple as possible, the command line interface is
+ * accessed through a UDP socket on the default Windows loopback IP address of
+ * 127.0.0.1. Full instructions are provided on the documentation page
+ * referenced above.
+ *
+ * Commands are provided to both start and stop a FreeRTOS+Trace recording.
+ * Stopping a recording will result in the recorded data being saved to the
+ * hard disk, ready for viewing in the FreeRTOS+Trace graphical user interface.
+ * Again, full instructions are provided on the documentation page referenced
+ * above.
+ *
+ * A queue send task and a queue receive task are defined in this file. The
+ * queue receive task spends most of its time blocked on the queue waiting for
+ * messages to arrive. The queue send task periodically sends a message to the
+ * queue, causing the queue receive task to exit the Blocked state. The
+ * priority of the queue receive task is above that of the queue send task, so
+ * it pre-empts the queue send task as soon as it leaves the Blocked state. It
+ * then consumes the message from the queue and prints "message received" to
+ * the screen before returning to block on the queue once again. This
+ * sequencing is clearly visible in the recorded FreeRTOS+Trace data.
+ *
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+#include "task.h"
+#include "queue.h"
+
+/* FreeRTOS+Trace includes. */
+#include "trcUser.h"
+
+/* Priorities at which the tasks are created. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* The rate at which data is sent to the queue. The (simulated) 250ms value is
+converted to ticks using the portTICK_RATE_MS constant. */
+#define mainQUEUE_SEND_FREQUENCY_MS ( 250 / portTICK_RATE_MS )
+
+/* The number of items the queue can hold. This is 1 as the receive task
+will remove items as they are added, meaning the send task should always find
+the queue empty. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue send and receive tasks as described in the comments at the top of
+ * this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * The task that implements the UDP command interpreter using FreeRTOS+CLI.
+ */
+extern void vUDPCommandInterpreterTask( void *pvParameters );
+
+/*
+ * Register commands that can be used with FreeRTOS+CLI through the UDP socket.
+ * The commands are defined in CLI-commands.c.
+ */
+extern void vRegisterCLICommands( void );
+
+/* The queue used by both tasks. */
+static xQueueHandle xQueue = NULL;
+
+/* The user trace event posted to the trace recording on each tick interrupt.
+Note tick events will not appear in the trace recording with regular period
+because this project runs in a Windows simulator, and does not therefore
+exhibit deterministic behaviour. */
+traceLabel xTickTraceUserEvent;
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+const uint32_t ulLongTime_ms = 250UL;
+
+ /* Initialise the trace recorder and create the label used to post user
+ events to the trace recording on each tick interrupt. */
+ vTraceInitTraceData();
+ xTickTraceUserEvent = xTraceOpenLabel( "tick" );
+
+ /* Create the queue used to pass messages from the queue send task to the
+ queue receive task. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+
+ /* Give the queue a name for the FreeRTOS+Trace log. */
+ vTraceSetQueueName( xQueue, "DemoQ" );
+
+ /* Start the two tasks as described in the comments at the top of this
+ file. */
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. Not actually used as a stack in the Win32 simulator port. */
+ NULL, /* The parameter passed to the task - not used in this example. */
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
+ NULL ); /* The task handle is not required, so NULL is passed. */
+
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* Create the task that handles the CLI on a UDP port. The port number
+ is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */
+ xTaskCreate( vUDPCommandInterpreterTask, "CLI", configMINIMAL_STACK_SIZE, NULL, mainUDP_CLI_TASK_PRIORITY, NULL );
+
+ /* Register commands with the FreeRTOS+CLI command interpreter. */
+ vRegisterCLICommands();
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the idle and/or
+ timer tasks to be created. See the memory management section on the
+ FreeRTOS web site for more details (this is standard text that is not not
+ really applicable to the Win32 simulator port). */
+ for( ;; )
+ {
+ Sleep( ulLongTime_ms );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+
+ /* Remove warning about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Place this task in the blocked state until it is time to run again.
+ While in the Blocked state this task will not consume any CPU time. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ write a message to the display. 0 is used as the block time so the
+ sending operation will not block - it shouldn't need to block as the
+ queue should always be empty at this point in the code, and it is an
+ error if it is not. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+
+ /* Remove warning about unused parameters. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, write the message to the
+ display before looping back to block on the queue again. */
+ if( ulReceivedValue == 100UL )
+ {
+ printf( "Message received!\r\n" );
+ ulReceivedValue = 0U;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+const unsigned long ulMSToSleep = 5;
+
+ /* This function is called on each cycle of the idle task if
+ configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU
+ load. */
+ Sleep( ulMSToSleep );
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+const unsigned long ulLongSleep = 1000UL;
+
+ taskDISABLE_INTERRUPTS();
+ for( ;; )
+ {
+ Sleep( ulLongSleep );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* Write a user event to the trace log.
+ Note tick events will not appear in the trace recording with regular period
+ because this project runs in a Windows simulator, and does not therefore
+ exhibit deterministic behaviour. */
+ vTraceUserEvent( xTickTraceUserEvent );
+}
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.txt
new file mode 100644
index 0000000..1a0cbcf
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.txt
@@ -0,0 +1,7 @@
+Directories:
+
++ FreeRTOS-Plus/Demo_Projects_Using_FreeRTOS_Simulator/FreeRTOS_Plus_CLI_with_Trace
+ contains a FreeRTOS windows simulator demo project for both FreeRTOS+CLI and
+ FreeRTOS+Trace. See http://www.FreeRTOS.org/trace for information on using
+ the project.
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOSConfig.h
new file mode 100644
index 0000000..46e67f0
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOSConfig.h
@@ -0,0 +1,135 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 0
+#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 0 ) /* This parameter has no effect when heap_3.c is included in the project. */
+#define configMAX_TASK_NAME_LEN ( 7 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY 2
+#define configTIMER_QUEUE_LENGTH 20
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+
+/* Run time stats gathering definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+
+extern void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+/* The TCP port used by both the secure client and the secure server. */
+#define configTCP_PORT_NUMBER 5001
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOS_Plus_CyaSSL.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOS_Plus_CyaSSL.sln
new file mode 100644
index 0000000..3f819af
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOS_Plus_CyaSSL.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Visual C++ Express 2010
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|Win32 = Debug|Win32
+ Release|Win32 = Release|Win32
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/READ_ME.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/READ_ME.url
new file mode 100644
index 0000000..c9b8dac
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/READ_ME.url
@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/FreeRTOS-Plus/CyaSSL/FreeRTOS_CyaSSL_Example.shtml
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPClientTask.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPClientTask.c
new file mode 100644
index 0000000..ee346e6
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPClientTask.c
@@ -0,0 +1,174 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#pragma comment( lib, "ws2_32.lib" )
+
+/* Win32 includes. */
+#include <WinSock2.h>
+
+/* CyaSSL includes. */
+#include "cyassl/ssl.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------*/
+
+/* The CyaSSL context for the client. */
+static CYASSL_CTX* xCyaSSL_ClientContext = NULL;
+
+/*-----------------------------------------------------------*/
+
+/* See the comments at the top of main.c. */
+void vSecureTCPClientTask( void *pvParameters )
+{
+SOCKET xClientSocket;
+struct sockaddr_in xConnection;
+CYASSL* xCyaSSL_Object;
+WORD wVersionRequested;
+WSADATA xWSAData;
+char cString[ 50 ];
+portBASE_TYPE lReturned;
+uint32_t ulCount = 0UL;
+
+ /* Remove compiler warning about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Prepare to use WinSock. */
+ wVersionRequested = MAKEWORD( 2, 2 );
+ configASSERT( WSAStartup( wVersionRequested, &xWSAData ) == 0 );
+
+ /* Set family and port for client socket. */
+ memset( ( void * ) &xConnection, 0x00, sizeof( struct sockaddr_in ) );
+ xConnection.sin_family = AF_INET;
+ xConnection.sin_addr.s_addr = inet_addr("127.0.0.1");
+ xConnection.sin_port = htons( configTCP_PORT_NUMBER );
+
+ /* Attempt to create a context that uses the TLS V1 server protocol. */
+ xCyaSSL_ClientContext = CyaSSL_CTX_new( CyaTLSv1_client_method() );
+ configASSERT( xCyaSSL_ClientContext );
+
+ /* Load the CA certificate. */
+ lReturned = CyaSSL_CTX_load_verify_locations( xCyaSSL_ClientContext, "ca-cert.pem", 0 );
+ configASSERT( lReturned == SSL_SUCCESS );
+
+ for( ;; )
+ {
+ /* Create the socket. */
+ xClientSocket = socket( AF_INET, SOCK_STREAM, 0 );
+ configASSERT( xClientSocket != INVALID_SOCKET );
+
+ /* Connect to the secure server. */
+ if( connect( xClientSocket, ( SOCKADDR * ) &xConnection, sizeof( xConnection ) ) == 0 )
+ {
+ /* The connect was successful. Create a CyaSSL object to associate
+ with this connection. */
+ xCyaSSL_Object = CyaSSL_new( xCyaSSL_ClientContext );
+
+ if( xCyaSSL_Object != NULL )
+ {
+ /* Associate the created CyaSSL object with the connected
+ socket. */
+ lReturned = CyaSSL_set_fd( xCyaSSL_Object, xClientSocket );
+ configASSERT( lReturned == SSL_SUCCESS );
+
+ /* The count is used to differentiate between messages sent to
+ the server, and to break out of the do while loop below. */
+ ulCount = 0UL;
+
+ do
+ {
+ /* Create the string that is sent to the secure server. */
+ sprintf( cString, "Message number %lu\r\n", ulCount );
+
+ /* The next line is the secure equivalent of the standard
+ sockets call:
+ lReturned = send( xClientSocket, cString, strlen( cString ) + 1, 0 ); */
+ lReturned = CyaSSL_write( xCyaSSL_Object, cString, strlen( cString ) + 1 );
+
+
+ /* Short delay to prevent the messages streaming up the
+ console too quickly. */
+ vTaskDelay( 50 );
+ ulCount++;
+
+ } while( ( lReturned != SOCKET_ERROR ) && ( ulCount < 10UL ) );
+ }
+
+ CyaSSL_free( xCyaSSL_Object );
+ closesocket( xClientSocket );
+
+ /* Delay for a short time before starting over. */
+ vTaskDelay( 250 );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPServerTask.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPServerTask.c
new file mode 100644
index 0000000..b226979
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPServerTask.c
@@ -0,0 +1,284 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#pragma comment( lib, "ws2_32.lib" )
+
+/* Win32 includes. */
+#include <WinSock2.h>
+
+/* CyaSSL includes. */
+#include "cyassl/ssl.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* This application is using the FreeRTOS Windows simulator, which uses the
+FreeRTOS scheduler to schedule FreeRTOS task within the Windows environment.
+The Windows envrionment must not be allowed to block any Windows threads that
+are running FreeRTOS tasks, unless the FreeRTOS task is running at the FreeRTOS
+idle priority. For simplicity, this demo uses the Windows TCP/IP stack, the
+API for which can cause Windows threads to block. Therefore, any FreeRTOS task
+that makes calls to the Windows TCP/IP stack must be assigned the idle prioity.
+Note this is only a restriction of the simulated Windows environment - real
+FreeRTOS ports do not have this restriction. */
+#define sstSECURE_CLIENT_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Open, configures and binds the server's TCP socket.
+ */
+static SOCKET prvOpenServerSocket( void );
+
+/*
+ * Prepare the CyaSSL library for use.
+ */
+static void prvInitialiseCyaSSL( void );
+
+/*
+ * The task that implements the client side of the connection.
+ */
+extern void vSecureTCPClientTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The CyaSSL context for the server. */
+static CYASSL_CTX* xCyaSSL_ServerContext = NULL;
+
+/*-----------------------------------------------------------*/
+
+/* See the comments at the top of main.c. */
+void vSecureTCPServerTask( void *pvParameters )
+{
+portBASE_TYPE xReturned;
+long lBytes;
+uint8_t cReceivedString[ 60 ];
+struct sockaddr_in xClient;
+int xClientAddressLength = sizeof( struct sockaddr_in );
+SOCKET xListeningSocket, xConnectedSocket;
+CYASSL* xCyaSSL_Object; /* Only one connection is accepted at a time, so only one object is needed at a time. */
+
+ /* Just to prevent compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Perform the initialisation necessary before CyaSSL can be used. */
+ prvInitialiseCyaSSL();
+ configASSERT( xCyaSSL_ServerContext );
+
+ /* Attempt to open the socket. */
+ xListeningSocket = prvOpenServerSocket();
+
+ /* Now the server socket has been created and the CyaSSL library has been
+ initialised, the task that implements the client side can be created. */
+ xTaskCreate( vSecureTCPClientTask, "Client", configMINIMAL_STACK_SIZE, NULL, sstSECURE_CLIENT_TASK_PRIORITY, NULL );
+
+ if( xListeningSocket != INVALID_SOCKET )
+ {
+ for( ;; )
+ {
+ /* Wait until the client connects. */
+ printf( "Waiting for new connection\r\n" );
+ xConnectedSocket = accept( xListeningSocket, ( struct sockaddr * ) &xClient, &xClientAddressLength );
+
+ if( xConnectedSocket != INVALID_SOCKET )
+ {
+ printf( "Connection established\r\n" );
+
+ /* A connection has been accepted by the server. Create a
+ CyaSSL object for use with the newly connected socket. */
+ xCyaSSL_Object = NULL;
+ xCyaSSL_Object = CyaSSL_new( xCyaSSL_ServerContext );
+
+ if( xCyaSSL_Object != NULL )
+ {
+ /* Associate the created CyaSSL object with the connected
+ socket. */
+ xReturned = CyaSSL_set_fd( xCyaSSL_Object, xConnectedSocket );
+ configASSERT( xReturned == SSL_SUCCESS );
+
+ do
+ {
+ /* The next line is the secure equivalent to the
+ standard sockets call:
+ lBytes = recv( xConnectedSocket, cReceivedString, 50, 0 ); */
+ lBytes = CyaSSL_read( xCyaSSL_Object, cReceivedString, sizeof( cReceivedString ) );
+
+ /* Print the received characters. */
+ if( lBytes > 0 )
+ {
+ printf( "Received by the secure server: %s\r\n", cReceivedString );
+ }
+
+ } while ( lBytes > 0 );
+
+ /* The connection was closed, close the socket and free the
+ CyaSSL object. */
+ closesocket( xConnectedSocket );
+ CyaSSL_free( xCyaSSL_Object );
+ printf( "Connection closed, back to start\r\n\r\n" );
+ }
+ }
+ }
+ }
+ else
+ {
+ /* The socket could not be opened. */
+ vTaskDelete( NULL );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static SOCKET prvOpenServerSocket( void )
+{
+WSADATA xWSAData;
+WORD wVersionRequested;
+struct sockaddr_in xConnection;
+SOCKET xSocket = INVALID_SOCKET;
+
+ wVersionRequested = MAKEWORD( 2, 2 );
+
+ /* Prepare to use WinSock. */
+ if( WSAStartup( wVersionRequested, &xWSAData ) != 0 )
+ {
+ fprintf( stderr, "Could not open Windows connection.\n" );
+ }
+ else
+ {
+ xSocket = socket( AF_INET, SOCK_STREAM, 0 );
+ if( xSocket == INVALID_SOCKET)
+ {
+ fprintf( stderr, "Could not create socket.\n" );
+ WSACleanup();
+ }
+ else
+ {
+ /* Zero out the server structure. */
+ memset( ( void * ) &xConnection, 0x00, sizeof( struct sockaddr_in ) );
+
+ xConnection.sin_family = AF_INET;
+ xConnection.sin_addr.s_addr = inet_addr("127.0.0.1");
+ xConnection.sin_port = htons( configTCP_PORT_NUMBER );
+
+ /* Bind the address to the socket. */
+ if( bind( xSocket, ( struct sockaddr * ) &xConnection, sizeof( struct sockaddr_in ) ) == -1 )
+ {
+ fprintf( stderr, "Could not socket to port %d.\n", configTCP_PORT_NUMBER );
+ closesocket( xSocket );
+ xSocket = INVALID_SOCKET;
+ WSACleanup();
+ }
+
+ if( listen( xSocket, 20 ) != 0 )
+ {
+ closesocket( xSocket );
+ xSocket = INVALID_SOCKET;
+ WSACleanup();
+ }
+ }
+ }
+
+ return xSocket;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCyaSSL( void )
+{
+int32_t iReturn;
+
+ #ifdef DEBUG_CYASSL
+ {
+ CyaSSL_Debugging_ON();
+ }
+ #endif
+
+ /* Initialise CyaSSL. This must be done before any other CyaSSL functions
+ are called. */
+ CyaSSL_Init();
+
+ /* Attempt to create a context that uses the TLS V1 server protocol. */
+ xCyaSSL_ServerContext = CyaSSL_CTX_new( CyaTLSv1_server_method() );
+
+ if( xCyaSSL_ServerContext != NULL )
+ {
+ /* Load the CA certificate. Real applications should ensure that
+ CyaSSL_CTX_load_verify_locations() returns SSL_SUCCESS before
+ proceeding. */
+ iReturn = CyaSSL_CTX_load_verify_locations( xCyaSSL_ServerContext, "ca-cert.pem", 0 );
+ configASSERT( iReturn == SSL_SUCCESS );
+
+ iReturn = CyaSSL_CTX_use_certificate_file( xCyaSSL_ServerContext, "server-cert.pem", SSL_FILETYPE_PEM );
+ configASSERT( iReturn == SSL_SUCCESS );
+
+ iReturn = CyaSSL_CTX_use_PrivateKey_file( xCyaSSL_ServerContext, "server-key.pem", SSL_FILETYPE_PEM );
+ configASSERT( iReturn == SSL_SUCCESS );
+ }
+}
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj
new file mode 100644
index 0000000..0290eb1
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <ItemGroup Label="ProjectConfigurations">
+ <ProjectConfiguration Include="Debug|Win32">
+ <Configuration>Debug</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ <ProjectConfiguration Include="Release|Win32">
+ <Configuration>Release</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ </ItemGroup>
+ <PropertyGroup Label="Globals">
+ <ProjectGuid>{C686325E-3261-42F7-AEB1-DDE5280E1CEB}</ProjectGuid>
+ <ProjectName>RTOSDemo</ProjectName>
+ </PropertyGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
+ <ConfigurationType>Application</ConfigurationType>
+ <UseOfMfc>false</UseOfMfc>
+ <CharacterSet>MultiByte</CharacterSet>
+ </PropertyGroup>
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
+ <ConfigurationType>Application</ConfigurationType>
+ <UseOfMfc>false</UseOfMfc>
+ <CharacterSet>MultiByte</CharacterSet>
+ </PropertyGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
+ <ImportGroup Label="ExtensionSettings">
+ </ImportGroup>
+ <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="PropertySheets">
+ <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+ <Import Project="$(VCTargetsPath)Microsoft.CPP.UpgradeFromVC60.props" />
+ </ImportGroup>
+ <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="PropertySheets">
+ <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+ <Import Project="$(VCTargetsPath)Microsoft.CPP.UpgradeFromVC60.props" />
+ </ImportGroup>
+ <PropertyGroup Label="UserMacros" />
+ <PropertyGroup>
+ <_ProjectFileVersion>10.0.30319.1</_ProjectFileVersion>
+ <OutDir Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">.\Debug\</OutDir>
+ <IntDir Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">.\Debug\</IntDir>
+ <LinkIncremental Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">true</LinkIncremental>
+ <OutDir Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">.\Release\</OutDir>
+ <IntDir Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">.\Release\</IntDir>
+ <LinkIncremental Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">false</LinkIncremental>
+ </PropertyGroup>
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <Midl>
+ <TypeLibraryName>.\Debug/WIN32.tlb</TypeLibraryName>
+ <HeaderFileName>
+ </HeaderFileName>
+ </Midl>
+ <ClCompile>
+ <Optimization>Disabled</Optimization>
+ <AdditionalIncludeDirectories>..\..\Source\CyaSSL;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;.;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ <PreprocessorDefinitions>WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;SIZEOF_LONG_LONG=8;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <MinimalRebuild>true</MinimalRebuild>
+ <BasicRuntimeChecks>EnableFastChecks</BasicRuntimeChecks>
+ <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
+ <PrecompiledHeaderOutputFile>.\Debug/WIN32.pch</PrecompiledHeaderOutputFile>
+ <AssemblerListingLocation>.\Debug/</AssemblerListingLocation>
+ <ObjectFileName>.\Debug/</ObjectFileName>
+ <ProgramDataBaseFileName>.\Debug/</ProgramDataBaseFileName>
+ <WarningLevel>Level4</WarningLevel>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
+ <DisableLanguageExtensions>false</DisableLanguageExtensions>
+ <DebugInformationFormat>EditAndContinue</DebugInformationFormat>
+ </ClCompile>
+ <ResourceCompile>
+ <PreprocessorDefinitions>_DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <Culture>0x0c09</Culture>
+ </ResourceCompile>
+ <Link>
+ <OutputFile>.\Debug/RTOSDemo.exe</OutputFile>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
+ <GenerateDebugInformation>true</GenerateDebugInformation>
+ <ProgramDatabaseFile>.\Debug/WIN32.pdb</ProgramDatabaseFile>
+ <SubSystem>Console</SubSystem>
+ <TargetMachine>MachineX86</TargetMachine>
+ <AdditionalDependencies>%(AdditionalDependencies)</AdditionalDependencies>
+ <AdditionalLibraryDirectories>
+ </AdditionalLibraryDirectories>
+ </Link>
+ <Bscmake>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
+ <OutputFile>.\Debug/WIN32.bsc</OutputFile>
+ </Bscmake>
+ </ItemDefinitionGroup>
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+ <Midl>
+ <TypeLibraryName>.\Release/WIN32.tlb</TypeLibraryName>
+ <HeaderFileName>
+ </HeaderFileName>
+ </Midl>
+ <ClCompile>
+ <Optimization>MaxSpeed</Optimization>
+ <InlineFunctionExpansion>OnlyExplicitInline</InlineFunctionExpansion>
+ <PreprocessorDefinitions>_WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <StringPooling>true</StringPooling>
+ <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
+ <FunctionLevelLinking>true</FunctionLevelLinking>
+ <PrecompiledHeaderOutputFile>.\Release/WIN32.pch</PrecompiledHeaderOutputFile>
+ <AssemblerListingLocation>.\Release/</AssemblerListingLocation>
+ <ObjectFileName>.\Release/</ObjectFileName>
+ <ProgramDataBaseFileName>.\Release/</ProgramDataBaseFileName>
+ <WarningLevel>Level3</WarningLevel>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
+ <AdditionalIncludeDirectories>..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;.;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ </ClCompile>
+ <ResourceCompile>
+ <PreprocessorDefinitions>NDEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <Culture>0x0c09</Culture>
+ </ResourceCompile>
+ <Link>
+ <OutputFile>.\Release/RTOSDemo.exe</OutputFile>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
+ <ProgramDatabaseFile>.\Release/WIN32.pdb</ProgramDatabaseFile>
+ <SubSystem>Console</SubSystem>
+ <TargetMachine>MachineX86</TargetMachine>
+ <AdditionalLibraryDirectories>..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap</AdditionalLibraryDirectories>
+ <AdditionalDependencies>wpcap.lib;%(AdditionalDependencies)</AdditionalDependencies>
+ </Link>
+ <Bscmake>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
+ <OutputFile>.\Release/WIN32.bsc</OutputFile>
+ </Bscmake>
+ </ItemDefinitionGroup>
+ <ItemGroup>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\aes.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\arc4.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\asn.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\coding.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\des3.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dh.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dsa.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\hc128.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\hmac.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\integer.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\logging.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md4.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md5.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\memory.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\misc.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\pwdbased.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rabbit.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\random.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rsa.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\sha.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\sha256.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\src\internal.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\src\io.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\src\keys.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\src\ssl.c" />
+ <ClCompile Include="..\..\Source\CyaSSL\src\tls.c" />
+ <ClCompile Include="..\..\..\FreeRTOS\Source\list.c" />
+ <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MemMang\heap_3.c" />
+ <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MSVC-MingW\port.c" />
+ <ClCompile Include="..\..\..\FreeRTOS\Source\queue.c" />
+ <ClCompile Include="..\..\..\FreeRTOS\Source\tasks.c" />
+ <ClCompile Include="..\..\..\FreeRTOS\Source\timers.c" />
+ <ClCompile Include="main.c">
+ <AdditionalIncludeDirectories Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ <PreprocessorDefinitions Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ </ClCompile>
+ <ClCompile Include="SecureTCPClientTask.c" />
+ <ClCompile Include="SecureTCPServerTask.c" />
+ </ItemGroup>
+ <ItemGroup>
+ <ClInclude Include="FreeRTOSConfig.h" />
+ </ItemGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
+ <ImportGroup Label="ExtensionTargets">
+ </ImportGroup>
+</Project>
\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.filters
new file mode 100644
index 0000000..82abb1f
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.filters
@@ -0,0 +1,144 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <ItemGroup>
+ <Filter Include="Resource Files">
+ <UniqueIdentifier>{38712199-cebf-4124-bf15-398f7c3419ea}</UniqueIdentifier>
+ <Extensions>ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe</Extensions>
+ </Filter>
+ <Filter Include="Demo App Source">
+ <UniqueIdentifier>{34567deb-d5ab-4a56-8640-0aaec609521a}</UniqueIdentifier>
+ <Extensions>cpp;c;cxx;rc;def;r;odl;idl;hpj;bat</Extensions>
+ </Filter>
+ <Filter Include="FreeRTOS">
+ <UniqueIdentifier>{af3445a1-4908-4170-89ed-39345d90d30c}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS\Source">
+ <UniqueIdentifier>{f32be356-4763-4cae-9020-974a2638cb08}</UniqueIdentifier>
+ <Extensions>*.c</Extensions>
+ </Filter>
+ <Filter Include="FreeRTOS\Source\Portable">
+ <UniqueIdentifier>{88f409e6-d396-4ac5-94bd-7a99c914be46}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+">
+ <UniqueIdentifier>{e5ad4ec7-23dc-4295-8add-2acaee488f5a}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\CyaSSL">
+ <UniqueIdentifier>{8b481200-a9e5-48a4-98ad-49d2783cd652}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\CyaSSL\ctaocrypt">
+ <UniqueIdentifier>{738eaad9-4e49-4309-9074-c3d9e102fb4a}</UniqueIdentifier>
+ </Filter>
+ </ItemGroup>
+ <ItemGroup>
+ <ClCompile Include="main.c">
+ <Filter>Demo App Source</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MSVC-MingW\port.c">
+ <Filter>FreeRTOS\Source\Portable</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MemMang\heap_3.c">
+ <Filter>FreeRTOS\Source\Portable</Filter>
+ </ClCompile>
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+ <Filter>FreeRTOS\Source</Filter>
+ </ClCompile>
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+ </ClCompile>
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+ <Filter>FreeRTOS\Source</Filter>
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+ <Filter>FreeRTOS\Source</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\src\internal.c">
+ <Filter>FreeRTOS+\CyaSSL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\src\io.c">
+ <Filter>FreeRTOS+\CyaSSL</Filter>
+ </ClCompile>
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+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\arc4.c">
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\des3.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dh.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dsa.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
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+ </ClCompile>
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\integer.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\logging.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md4.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md5.c">
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+ </ClCompile>
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\pwdbased.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rabbit.c">
+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
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+ </ClCompile>
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+ <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
+ </ClCompile>
+ <ClCompile Include="SecureTCPServerTask.c">
+ <Filter>Demo App Source</Filter>
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+ <ClCompile Include="SecureTCPClientTask.c">
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+ </ItemGroup>
+ <ItemGroup>
+ <ClInclude Include="FreeRTOSConfig.h">
+ <Filter>Demo App Source</Filter>
+ </ClInclude>
+ </ItemGroup>
+</Project>
\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.user
new file mode 100644
index 0000000..695b5c7
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.user
@@ -0,0 +1,3 @@
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\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/ca-cert.pem b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/ca-cert.pem
new file mode 100644
index 0000000..4a9786a
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/ca-cert.pem
@@ -0,0 +1,87 @@
+Certificate:
+ Data:
+ Version: 3 (0x2)
+ Serial Number:
+ e9:d0:a7:5f:79:25:f4:3c
+ Signature Algorithm: sha1WithRSAEncryption
+ Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.yassl.com/emailAddress=info@yassl.com
+ Validity
+ Not Before: Oct 24 18:18:15 2011 GMT
+ Not After : Jul 20 18:18:15 2014 GMT
+ Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.yassl.com/emailAddress=info@yassl.com
+ Subject Public Key Info:
+ Public Key Algorithm: rsaEncryption
+ RSA Public Key: (2048 bit)
+ Modulus (2048 bit):
+ 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a:
+ f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac:
+ de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98:
+ 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77:
+ 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1:
+ 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3:
+ a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed:
+ a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95:
+ 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c:
+ 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db:
+ 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc:
+ 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98:
+ de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68:
+ cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2:
+ b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3:
+ 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98:
+ ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed:
+ 36:79
+ Exponent: 65537 (0x10001)
+ X509v3 extensions:
+ X509v3 Subject Key Identifier:
+ 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5
+ X509v3 Authority Key Identifier:
+ keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5
+ DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.yassl.com/emailAddress=info@yassl.com
+ serial:E9:D0:A7:5F:79:25:F4:3C
+
+ X509v3 Basic Constraints:
+ CA:TRUE
+ Signature Algorithm: sha1WithRSAEncryption
+ 5f:86:14:f4:51:8b:bc:a5:4e:30:da:5e:ac:9a:f8:6c:d9:26:
+ 4b:93:f9:e3:1c:89:6f:9e:ee:b3:9d:77:3e:89:20:76:a3:e6:
+ e8:86:15:21:db:e2:33:b2:34:d5:d0:9f:f3:c1:a4:87:92:5c:
+ f9:d1:ff:30:2f:8e:03:bc:b3:3c:0c:32:a3:90:5f:1a:90:1e:
+ af:9d:f3:9e:d7:07:02:a9:7d:27:66:63:2f:af:18:d7:ac:18:
+ 98:8c:83:8f:38:f3:0b:ac:36:10:75:fb:ca:76:13:50:5b:02:
+ 8f:73:bf:e3:a0:ee:83:52:25:54:ce:26:ce:9c:bd:2f:79:ab:
+ 1b:60:b8:92:f1:03:c0:fc:3b:08:d9:c0:ad:d5:72:08:25:80:
+ 61:2d:dc:9f:a7:83:62:07:47:e0:07:4c:4b:07:30:04:a9:87:
+ 1c:55:7f:07:12:d0:cb:42:5d:cb:cf:66:01:1a:17:ee:f9:0f:
+ 60:b7:db:6f:68:e5:4e:41:62:6e:d3:6f:60:4f:4b:27:de:cf:
+ 18:07:f1:13:5d:cb:3f:a9:25:44:da:52:5c:c8:04:e1:56:12:
+ f5:2a:90:4e:d1:e2:af:01:b5:23:a1:ec:31:da:7b:63:69:c4:
+ b8:f3:e7:ce:a1:3d:c0:db:6d:f3:b2:d9:46:c8:9f:c3:b8:70:
+ 5a:1f:7f:ca
+-----BEGIN CERTIFICATE-----
+MIIEnjCCA4agAwIBAgIJAOnQp195JfQ8MA0GCSqGSIb3DQEBBQUAMIGQMQswCQYD
+VQQGEwJVUzEQMA4GA1UECBMHTW9udGFuYTEQMA4GA1UEBxMHQm96ZW1hbjERMA8G
+A1UEChMIU2F3dG9vdGgxEzARBgNVBAsTCkNvbnN1bHRpbmcxFjAUBgNVBAMTDXd3
+dy55YXNzbC5jb20xHTAbBgkqhkiG9w0BCQEWDmluZm9AeWFzc2wuY29tMB4XDTEx
+MTAyNDE4MTgxNVoXDTE0MDcyMDE4MTgxNVowgZAxCzAJBgNVBAYTAlVTMRAwDgYD
+VQQIEwdNb250YW5hMRAwDgYDVQQHEwdCb3plbWFuMREwDwYDVQQKEwhTYXd0b290
+aDETMBEGA1UECxMKQ29uc3VsdGluZzEWMBQGA1UEAxMNd3d3Lnlhc3NsLmNvbTEd
+MBsGCSqGSIb3DQEJARYOaW5mb0B5YXNzbC5jb20wggEiMA0GCSqGSIb3DQEBAQUA
+A4IBDwAwggEKAoIBAQC/DMotFLIehEJbzTgfSvJNdRDxtjWf38p9A5jTrN4DZu4q
+8diwfW4HVAsQmCFNgMsSIOfMT95FfclydzLqypC7aVIQAy+o85XF8YtiVhvvZ2+k
+EEGVrQqb46XAsNJwdlAwW6joCCx87aeieo04KRysx+3yfJWwlYJ9SVw4zXcl772A
+dVOUPD3KY1ufFbXTHRMvGdE823Y6zLh9yeXC19pAb9gh3HMbQi1TnP4a/H2rejY/
+mN6EfAVnzmoUOIep8Yy1aMtof3EgK/WgY/VWL6Mm0rdvsVoX1ziZCP6TWG/+wxNJ
+CBYLp01nAFIxZyNOmO1RRR25BNkL7Ngos0u97TZ5AgMBAAGjgfgwgfUwHQYDVR0O
+BBYEFCeOZxF0wyYdP+0zY7Ok2B0w5ejVMIHFBgNVHSMEgb0wgbqAFCeOZxF0wyYd
+P+0zY7Ok2B0w5ejVoYGWpIGTMIGQMQswCQYDVQQGEwJVUzEQMA4GA1UECBMHTW9u
+dGFuYTEQMA4GA1UEBxMHQm96ZW1hbjERMA8GA1UEChMIU2F3dG9vdGgxEzARBgNV
+BAsTCkNvbnN1bHRpbmcxFjAUBgNVBAMTDXd3dy55YXNzbC5jb20xHTAbBgkqhkiG
+9w0BCQEWDmluZm9AeWFzc2wuY29tggkA6dCnX3kl9DwwDAYDVR0TBAUwAwEB/zAN
+BgkqhkiG9w0BAQUFAAOCAQEAX4YU9FGLvKVOMNperJr4bNkmS5P54xyJb57us513
+PokgdqPm6IYVIdviM7I01dCf88Gkh5Jc+dH/MC+OA7yzPAwyo5BfGpAer53zntcH
+Aql9J2ZjL68Y16wYmIyDjzjzC6w2EHX7ynYTUFsCj3O/46Dug1IlVM4mzpy9L3mr
+G2C4kvEDwPw7CNnArdVyCCWAYS3cn6eDYgdH4AdMSwcwBKmHHFV/BxLQy0Jdy89m
+ARoX7vkPYLfbb2jlTkFibtNvYE9LJ97PGAfxE13LP6klRNpSXMgE4VYS9SqQTtHi
+rwG1I6HsMdp7Y2nEuPPnzqE9wNtt87LZRsifw7hwWh9/yg==
+-----END CERTIFICATE-----
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/main.c
new file mode 100644
index 0000000..7a2f1ba
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/main.c
@@ -0,0 +1,141 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdio.h>
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+#include "task.h"
+
+/* This application is using the FreeRTOS Windows simulator, which uses the
+FreeRTOS scheduler to schedule FreeRTOS task within the Windows environment.
+The Windows environment must not be allowed to block any Windows threads that
+are running FreeRTOS tasks, unless the FreeRTOS task is running at the FreeRTOS
+idle priority. For simplicity, this demo uses the Windows TCP/IP stack, the
+API for which can cause Windows threads to block. Therefore, any FreeRTOS task
+that makes calls to the Windows TCP/IP stack must be assigned the idle priority.
+Note this is only a restriction of the simulated Windows environment - real
+FreeRTOS ports do not have this restriction. */
+#define mainSECURE_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that implements the server side.
+ */
+extern void vSecureTCPServerTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+const uint32_t ulLongTime_ms = 250UL;
+
+ /* Create the TCP server task. This will itself create the client task
+ once it has completed the CyaSSL initialisation. */
+ xTaskCreate( vSecureTCPServerTask, "Server", configMINIMAL_STACK_SIZE, NULL, mainSECURE_SERVER_TASK_PRIORITY, NULL );
+
+ /* Start the task running. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the idle and/or
+ timer tasks to be created. See the memory management section on the
+ FreeRTOS web site for more details (this is standard text that is not not
+ really applicable to the Win32 simulator port). */
+ for( ;; )
+ {
+ Sleep( ulLongTime_ms );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+const unsigned long ulMSToSleep = 5;
+
+ /* This function is called on each cycle of the idle task if
+ configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU
+ load. */
+ Sleep( ulMSToSleep );
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+const unsigned long ulLongSleep = 1000UL;
+
+ taskDISABLE_INTERRUPTS();
+ for( ;; )
+ {
+ Sleep( ulLongSleep );
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/server-cert.pem b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/server-cert.pem
new file mode 100644
index 0000000..8381265
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/server-cert.pem
@@ -0,0 +1,158 @@
+Certificate:
+ Data:
+ Version: 1 (0x0)
+ Serial Number: 2 (0x2)
+ Signature Algorithm: sha1WithRSAEncryption
+ Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.yassl.com/emailAddress=info@yassl.com
+ Validity
+ Not Before: Oct 24 18:27:13 2011 GMT
+ Not After : Jul 20 18:27:13 2014 GMT
+ Subject: C=US, ST=Montana, L=Bozeman, O=yaSSL, OU=Support, CN=www.yassl.com/emailAddress=info@yassl.com
+ Subject Public Key Info:
+ Public Key Algorithm: rsaEncryption
+ RSA Public Key: (2048 bit)
+ Modulus (2048 bit):
+ 00:c0:95:08:e1:57:41:f2:71:6d:b7:d2:45:41:27:
+ 01:65:c6:45:ae:f2:bc:24:30:b8:95:ce:2f:4e:d6:
+ f6:1c:88:bc:7c:9f:fb:a8:67:7f:fe:5c:9c:51:75:
+ f7:8a:ca:07:e7:35:2f:8f:e1:bd:7b:c0:2f:7c:ab:
+ 64:a8:17:fc:ca:5d:7b:ba:e0:21:e5:72:2e:6f:2e:
+ 86:d8:95:73:da:ac:1b:53:b9:5f:3f:d7:19:0d:25:
+ 4f:e1:63:63:51:8b:0b:64:3f:ad:43:b8:a5:1c:5c:
+ 34:b3:ae:00:a0:63:c5:f6:7f:0b:59:68:78:73:a6:
+ 8c:18:a9:02:6d:af:c3:19:01:2e:b8:10:e3:c6:cc:
+ 40:b4:69:a3:46:33:69:87:6e:c4:bb:17:a6:f3:e8:
+ dd:ad:73:bc:7b:2f:21:b5:fd:66:51:0c:bd:54:b3:
+ e1:6d:5f:1c:bc:23:73:d1:09:03:89:14:d2:10:b9:
+ 64:c3:2a:d0:a1:96:4a:bc:e1:d4:1a:5b:c7:a0:c0:
+ c1:63:78:0f:44:37:30:32:96:80:32:23:95:a1:77:
+ ba:13:d2:97:73:e2:5d:25:c9:6a:0d:c3:39:60:a4:
+ b4:b0:69:42:42:09:e9:d8:08:bc:33:20:b3:58:22:
+ a7:aa:eb:c4:e1:e6:61:83:c5:d2:96:df:d9:d0:4f:
+ ad:d7
+ Exponent: 65537 (0x10001)
+ Signature Algorithm: sha1WithRSAEncryption
+ 71:4e:d3:62:df:cc:4c:f7:cd:b7:6e:52:0b:6c:6e:e0:bd:c2:
+ 2d:07:d7:c0:b0:6e:43:1e:35:bc:30:01:50:f0:ff:99:23:6c:
+ 18:1a:41:b6:11:d6:d4:19:61:fd:e4:77:97:1c:39:e1:57:ab:
+ c5:15:63:77:11:36:5e:74:e2:24:0b:1f:41:78:ad:b7:81:e7:
+ b4:40:66:80:f0:4b:91:a0:6d:a8:6e:3d:53:d9:8b:ce:2a:e1:
+ 0b:45:65:87:a1:96:ae:ee:3e:88:d5:12:1f:78:17:ae:2c:c5:
+ 73:44:d8:dc:f4:af:d8:cc:ae:4c:e1:0c:be:55:a4:99:f7:6e:
+ 96:c0:c8:45:87:bf:dc:51:57:ff:9e:73:37:6a:18:9c:c3:f9:
+ 22:7a:f4:b0:52:bd:fc:21:30:f8:c5:ff:1e:87:7d:ad:a2:5a:
+ 35:f5:22:a8:b4:0a:76:38:e6:76:b0:98:af:1b:ec:8a:0a:43:
+ 74:d2:85:34:37:84:07:e1:f6:23:b2:29:de:a6:b6:b7:4c:57:
+ 7e:96:06:cb:a9:16:25:29:3a:03:2d:55:7d:a6:8c:a4:f7:9e:
+ 81:c9:95:b6:7c:c1:4a:ce:94:66:0c:ca:88:eb:d2:09:f5:5b:
+ 19:58:82:df:27:fd:67:95:78:b7:02:06:d5:a7:61:bd:ef:3a:
+ fc:b2:61:cd
+-----BEGIN CERTIFICATE-----
+MIIDkDCCAngCAQIwDQYJKoZIhvcNAQEFBQAwgZAxCzAJBgNVBAYTAlVTMRAwDgYD
+VQQIEwdNb250YW5hMRAwDgYDVQQHEwdCb3plbWFuMREwDwYDVQQKEwhTYXd0b290
+aDETMBEGA1UECxMKQ29uc3VsdGluZzEWMBQGA1UEAxMNd3d3Lnlhc3NsLmNvbTEd
+MBsGCSqGSIb3DQEJARYOaW5mb0B5YXNzbC5jb20wHhcNMTExMDI0MTgyNzEzWhcN
+MTQwNzIwMTgyNzEzWjCBijELMAkGA1UEBhMCVVMxEDAOBgNVBAgTB01vbnRhbmEx
+EDAOBgNVBAcTB0JvemVtYW4xDjAMBgNVBAoTBXlhU1NMMRAwDgYDVQQLEwdTdXBw
+b3J0MRYwFAYDVQQDEw13d3cueWFzc2wuY29tMR0wGwYJKoZIhvcNAQkBFg5pbmZv
+QHlhc3NsLmNvbTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAMCVCOFX
+QfJxbbfSRUEnAWXGRa7yvCQwuJXOL07W9hyIvHyf+6hnf/5cnFF194rKB+c1L4/h
+vXvAL3yrZKgX/Mpde7rgIeVyLm8uhtiVc9qsG1O5Xz/XGQ0lT+FjY1GLC2Q/rUO4
+pRxcNLOuAKBjxfZ/C1loeHOmjBipAm2vwxkBLrgQ48bMQLRpo0YzaYduxLsXpvPo
+3a1zvHsvIbX9ZlEMvVSz4W1fHLwjc9EJA4kU0hC5ZMMq0KGWSrzh1Bpbx6DAwWN4
+D0Q3MDKWgDIjlaF3uhPSl3PiXSXJag3DOWCktLBpQkIJ6dgIvDMgs1gip6rrxOHm
+YYPF0pbf2dBPrdcCAwEAATANBgkqhkiG9w0BAQUFAAOCAQEAcU7TYt/MTPfNt25S
+C2xu4L3CLQfXwLBuQx41vDABUPD/mSNsGBpBthHW1Blh/eR3lxw54VerxRVjdxE2
+XnTiJAsfQXitt4HntEBmgPBLkaBtqG49U9mLzirhC0Vlh6GWru4+iNUSH3gXrizF
+c0TY3PSv2MyuTOEMvlWkmfdulsDIRYe/3FFX/55zN2oYnMP5Inr0sFK9/CEw+MX/
+Hod9raJaNfUiqLQKdjjmdrCYrxvsigpDdNKFNDeEB+H2I7Ip3qa2t0xXfpYGy6kW
+JSk6Ay1VfaaMpPeegcmVtnzBSs6UZgzKiOvSCfVbGViC3yf9Z5V4twIG1adhve86
+/LJhzQ==
+-----END CERTIFICATE-----
+Certificate:
+ Data:
+ Version: 3 (0x2)
+ Serial Number:
+ e9:d0:a7:5f:79:25:f4:3c
+ Signature Algorithm: sha1WithRSAEncryption
+ Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.yassl.com/emailAddress=info@yassl.com
+ Validity
+ Not Before: Oct 24 18:18:15 2011 GMT
+ Not After : Jul 20 18:18:15 2014 GMT
+ Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.yassl.com/emailAddress=info@yassl.com
+ Subject Public Key Info:
+ Public Key Algorithm: rsaEncryption
+ RSA Public Key: (2048 bit)
+ Modulus (2048 bit):
+ 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a:
+ f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac:
+ de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98:
+ 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77:
+ 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1:
+ 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3:
+ a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed:
+ a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95:
+ 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c:
+ 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db:
+ 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc:
+ 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98:
+ de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68:
+ cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2:
+ b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3:
+ 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98:
+ ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed:
+ 36:79
+ Exponent: 65537 (0x10001)
+ X509v3 extensions:
+ X509v3 Subject Key Identifier:
+ 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5
+ X509v3 Authority Key Identifier:
+ keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5
+ DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.yassl.com/emailAddress=info@yassl.com
+ serial:E9:D0:A7:5F:79:25:F4:3C
+
+ X509v3 Basic Constraints:
+ CA:TRUE
+ Signature Algorithm: sha1WithRSAEncryption
+ 5f:86:14:f4:51:8b:bc:a5:4e:30:da:5e:ac:9a:f8:6c:d9:26:
+ 4b:93:f9:e3:1c:89:6f:9e:ee:b3:9d:77:3e:89:20:76:a3:e6:
+ e8:86:15:21:db:e2:33:b2:34:d5:d0:9f:f3:c1:a4:87:92:5c:
+ f9:d1:ff:30:2f:8e:03:bc:b3:3c:0c:32:a3:90:5f:1a:90:1e:
+ af:9d:f3:9e:d7:07:02:a9:7d:27:66:63:2f:af:18:d7:ac:18:
+ 98:8c:83:8f:38:f3:0b:ac:36:10:75:fb:ca:76:13:50:5b:02:
+ 8f:73:bf:e3:a0:ee:83:52:25:54:ce:26:ce:9c:bd:2f:79:ab:
+ 1b:60:b8:92:f1:03:c0:fc:3b:08:d9:c0:ad:d5:72:08:25:80:
+ 61:2d:dc:9f:a7:83:62:07:47:e0:07:4c:4b:07:30:04:a9:87:
+ 1c:55:7f:07:12:d0:cb:42:5d:cb:cf:66:01:1a:17:ee:f9:0f:
+ 60:b7:db:6f:68:e5:4e:41:62:6e:d3:6f:60:4f:4b:27:de:cf:
+ 18:07:f1:13:5d:cb:3f:a9:25:44:da:52:5c:c8:04:e1:56:12:
+ f5:2a:90:4e:d1:e2:af:01:b5:23:a1:ec:31:da:7b:63:69:c4:
+ b8:f3:e7:ce:a1:3d:c0:db:6d:f3:b2:d9:46:c8:9f:c3:b8:70:
+ 5a:1f:7f:ca
+-----BEGIN CERTIFICATE-----
+MIIEnjCCA4agAwIBAgIJAOnQp195JfQ8MA0GCSqGSIb3DQEBBQUAMIGQMQswCQYD
+VQQGEwJVUzEQMA4GA1UECBMHTW9udGFuYTEQMA4GA1UEBxMHQm96ZW1hbjERMA8G
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+EEGVrQqb46XAsNJwdlAwW6joCCx87aeieo04KRysx+3yfJWwlYJ9SVw4zXcl772A
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+9w0BCQEWDmluZm9AeWFzc2wuY29tggkA6dCnX3kl9DwwDAYDVR0TBAUwAwEB/zAN
+BgkqhkiG9w0BAQUFAAOCAQEAX4YU9FGLvKVOMNperJr4bNkmS5P54xyJb57us513
+PokgdqPm6IYVIdviM7I01dCf88Gkh5Jc+dH/MC+OA7yzPAwyo5BfGpAer53zntcH
+Aql9J2ZjL68Y16wYmIyDjzjzC6w2EHX7ynYTUFsCj3O/46Dug1IlVM4mzpy9L3mr
+G2C4kvEDwPw7CNnArdVyCCWAYS3cn6eDYgdH4AdMSwcwBKmHHFV/BxLQy0Jdy89m
+ARoX7vkPYLfbb2jlTkFibtNvYE9LJ97PGAfxE13LP6klRNpSXMgE4VYS9SqQTtHi
+rwG1I6HsMdp7Y2nEuPPnzqE9wNtt87LZRsifw7hwWh9/yg==
+-----END CERTIFICATE-----
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/server-key.pem b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/server-key.pem
new file mode 100644
index 0000000..d1627f4
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/server-key.pem
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEpQIBAAKCAQEAwJUI4VdB8nFtt9JFQScBZcZFrvK8JDC4lc4vTtb2HIi8fJ/7
+qGd//lycUXX3isoH5zUvj+G9e8AvfKtkqBf8yl17uuAh5XIuby6G2JVz2qwbU7lf
+P9cZDSVP4WNjUYsLZD+tQ7ilHFw0s64AoGPF9n8LWWh4c6aMGKkCba/DGQEuuBDj
+xsxAtGmjRjNph27Euxem8+jdrXO8ey8htf1mUQy9VLPhbV8cvCNz0QkDiRTSELlk
+wyrQoZZKvOHUGlvHoMDBY3gPRDcwMpaAMiOVoXe6E9KXc+JdJclqDcM5YKS0sGlC
+Qgnp2Ai8MyCzWCKnquvE4eZhg8XSlt/Z0E+t1wIDAQABAoIBAQCa0DQPUmIFUAHv
+n+1kbsLE2hryhNeSEEiSxOlq64t1bMZ5OPLJckqGZFSVd8vDmp231B2kAMieTuTd
+x7pnFsF0vKnWlI8rMBr77d8hBSPZSjm9mGtlmrjcxH3upkMVLj2+HSJgKnMw1T7Y
+oqyGQy7E9WReP4l1DxHYUSVOn9iqo85gs+KK2X4b8GTKmlsFC1uqy+XjP24yIgXz
+0PrvdFKB4l90073/MYNFdfpjepcu1rYZxpIm5CgGUFAOeC6peA0Ul7QS2DFAq6EB
+QcIw+AdfFuRhd9Jg8p+N6PS662PeKpeB70xs5lU0USsoNPRTHMRYCj+7r7X3SoVD
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+ZH3c9Bm4w2CxV0hfUk9ZOlV/MsAZQ1A/rs5vF/MOn0DKTq0VO8l56cBZOHNwnAp8
+yTpIMqfYSXUKhcLC/RVz2pkJKmmanwpxv7AEpox6Wm9IWlQ7xrFTF9/nAoGBAMuT
+3ncVXbdcXHzYkKmYLdZpDmOzo9ymzItqpKISjI57SCyySzfcBhh96v52odSh6T8N
+zRtfr1+elltbD6F8r7ObkNtXczrtsCNErkFPHwdCEyNMy/r0FKTV9542fFufqDzB
+hV900jkt/9CE3/uzIHoumxeu5roLrl9TpFLtG8SRAoGBAOyY2rvV/vlSSn0CVUlv
+VW5SL4SjK7OGYrNU0mNS2uOIdqDvixWl0xgUcndex6MEH54ZYrUbG57D8rUy+UzB
+qusMJn3UX0pRXKRFBnBEp1bA1CIUdp7YY1CJkNPiv4GVkjFBhzkaQwsYpVMfORpf
+H0O8h2rfbtMiAP4imHBOGhkpAoGBAIpBVihRnl/Ungs7mKNU8mxW1KrpaTOFJAza
+1AwtxL9PAmk4fNTm3Ezt1xYRwz4A58MmwFEC3rt1nG9WnHrzju/PisUr0toGakTJ
+c/5umYf4W77xfOZltU9s8MnF/xbKixsX4lg9ojerAby/QM5TjI7t7+5ZneBj5nxe
+9Y5L8TvBAoGATUX5QIzFW/QqGoq08hysa+kMVja3TnKW1eWK0uL/8fEYEz2GCbjY
+dqfJHHFSlDBD4PF4dP1hG0wJzOZoKnGtHN9DvFbbpaS+NXCkXs9P/ABVmTo9I89n
+WvUi+LUp0EQR6zUuRr79jhiyX6i/GTKh9dwD5nyaHwx8qbAOITc78bA=
+-----END RSA PRIVATE KEY-----
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h
new file mode 100644
index 0000000..1042d4a
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h
@@ -0,0 +1,168 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *
+ * The bottom of this file contains some constants specific to running the UDP
+ * stack in this demo. Constants specific to FreeRTOS+UDP itself (rather than
+ * the demo) are contained in FreeRTOSIPConfig.h.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
+#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32U * 1024U ) )
+#define configMAX_TASK_NAME_LEN ( 7 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+
+/* Hook function related definitions. */
+#define configUSE_TICK_HOOK 0
+#define configUSE_IDLE_HOOK 1
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+/* Run time stats gathering definitions. */
+unsigned long ulGetRunTimeCounterValue( void );
+void vConfigureTimerForRunTimeStats( void );
+#define configGENERATE_RUN_TIME_STATS 1
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
+#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTimerGetTimerTaskHandle 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xQueueGetMutexHolder 1
+
+/* This demo makes use of one or more example stats formatting functions. These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form. See the notes in the implementation of vTaskList() within
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+
+/* Assert call defined for debug builds. */
+#ifdef _DEBUG
+ extern void vAssertCalled( const char *pcFile, unsigned long ulLine );
+ #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ )
+#endif /* _DEBUG */
+
+
+
+/* Application specific definitions follow. **********************************/
+
+/* The UDP port to use for incoming command inputs. The outgoing port is
+set to ( configUDP_CLI_PORT_NUMBER + 1 ). */
+#define configUDP_CLI_PORT_NUMBER 5001
+
+/* The size of the global output buffer that is available for use when there
+are multiple command interpreters running at once (for example, one on a UART
+and one on TCP/IP). This is done to prevent an output buffer being defined by
+each implementation - which would waste RAM. In this case, there is only one
+command interpreter running, and it has its own local output buffer, so the
+global buffer is just set to be one byte long as it is not used and should not
+take up unnecessary RAM. */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl.h
new file mode 100644
index 0000000..8647077
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl.h
@@ -0,0 +1,67 @@
+/*
+ * FreeRTOS+FAT SL V1.0.1 (C) 2014 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_FAT_SL_H
+#define _CONFIG_FAT_SL_H
+
+#include "../version/ver_fat_sl.h"
+#if VER_FAT_SL_MAJOR != 5 || VER_FAT_SL_MINOR != 2
+ #error Incompatible FAT_SL version number!
+#endif
+
+#include "../api/api_mdriver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************************************************************
+**
+** FAT SL user settings
+**
+**************************************************************************/
+#define F_SECTOR_SIZE 512u /* Disk sector size. */
+#define F_FS_THREAD_AWARE 1 /* Set to one if the file system will be access from more than one task. */
+#define F_MAXPATH 64 /* Maximum length a file name (including its full path) can be. */
+#define F_MAX_LOCK_WAIT_TICKS 20 /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CONFIG_FAT_SL_H */
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl_test.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl_test.h
new file mode 100644
index 0000000..2f56f93
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl_test.h
@@ -0,0 +1,62 @@
+/*
+ * FreeRTOS+FAT SL V1.0.1 (C) 2014 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_FAT_SL_TEST_H
+#define _CONFIG_FAT_SL_TEST_H
+
+#include "../version/ver_fat_sl.h"
+#if VER_FAT_SL_MAJOR != 5 || VER_FAT_SL_MINOR != 2
+ #error Incompatible FAT_SL version number!
+#endif
+
+
+/*
+** Maximum size for seek test.
+** Options: 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768
+*/
+#define F_MAX_SEEK_TEST 16384
+
+
+/*
+** Defines media type for testing.
+** Options: F_FAT12_MEDIA, F_FAT16_MEDIA, F_FAT32_MEDIA
+*/
+#define F_FAT_TYPE F_FAT16_MEDIA
+
+
+#endif /* ifndef _CONFIG_STHIN_TEST_H */
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_mdriver_ram.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_mdriver_ram.h
new file mode 100644
index 0000000..51f2018
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_mdriver_ram.h
@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS+FAT SL V1.0.1 (C) 2014 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_MDRIVER_RAM_H_
+#define _CONFIG_MDRIVER_RAM_H_
+
+#include "../version/ver_mdriver_ram.h"
+#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2
+ #error Incompatible MDRIVER_RAM version number!
+#endif
+
+#define MDRIVER_RAM_SECTOR_SIZE 512 /* Sector size */
+
+#define MDRIVER_RAM_VOLUME0_SIZE (128 * 1024) /* defintion for size of ramdrive0 */
+
+#define MDRIVER_MEM_LONG_ACCESS 1 /* set this value to 1 if 32bit access available */
+
+#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-Releated-CLI-commands.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-Releated-CLI-commands.c
new file mode 100644
index 0000000..1ea3370
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-Releated-CLI-commands.c
@@ -0,0 +1,610 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+#include "test.h"
+
+#ifdef _WINDOWS_
+ #define snprintf _snprintf
+#endif
+
+#define cliNEW_LINE "\r\n"
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/*
+ * Print out information on a single file.
+ */
+static void prvCreateFileInfoString( char *pcBuffer, F_FIND *pxFindStruct );
+
+/*
+ * Copies an existing file into a newly created file.
+ */
+static portBASE_TYPE prvPerformCopy( const char *pcSourceFile,
+ int32_t lSourceFileLength,
+ const char *pcDestinationFile,
+ char *pxWriteBuffer,
+ size_t xWriteBufferLen );
+
+/*
+ * Implements the DIR command.
+ */
+static portBASE_TYPE prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the CD command.
+ */
+static portBASE_TYPE prvCDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the DEL command.
+ */
+static portBASE_TYPE prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the TYPE command.
+ */
+static portBASE_TYPE prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the COPY command.
+ */
+static portBASE_TYPE prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the TEST command.
+ */
+static portBASE_TYPE prvTESTFSCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/* Structure that defines the DIR command line command, which lists all the
+files in the current directory. */
+static const CLI_Command_Definition_t xDIR =
+{
+ "dir", /* The command string to type. */
+ "\r\ndir:\r\n Lists the files in the current directory\r\n",
+ prvDIRCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the CD command line command, which changes the
+working directory. */
+static const CLI_Command_Definition_t xCD =
+{
+ "cd", /* The command string to type. */
+ "\r\ncd <dir name>:\r\n Changes the working directory\r\n",
+ prvCDCommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the TYPE command line command, which prints the
+contents of a file to the console. */
+static const CLI_Command_Definition_t xTYPE =
+{
+ "type", /* The command string to type. */
+ "\r\ntype <filename>:\r\n Prints file contents to the terminal\r\n",
+ prvTYPECommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the DEL command line command, which deletes a file. */
+static const CLI_Command_Definition_t xDEL =
+{
+ "del", /* The command string to type. */
+ "\r\ndel <filename>:\r\n deletes a file or directory\r\n",
+ prvDELCommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the COPY command line command, which deletes a file. */
+static const CLI_Command_Definition_t xCOPY =
+{
+ "copy", /* The command string to type. */
+ "\r\ncopy <source file> <dest file>:\r\n Copies <source file> to <dest file>\r\n",
+ prvCOPYCommand, /* The function to run. */
+ 2 /* Two parameters are expected. */
+};
+
+/* Structure that defines the TEST command line command, which executes some
+file system driver tests. */
+static const CLI_Command_Definition_t xTEST_FS =
+{
+ "test-fs", /* The command string to type. */
+ "\r\ntest-fs:\r\n Executes file system tests. ALL FILES WILL BE DELETED!!!\r\n",
+ prvTESTFSCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/*-----------------------------------------------------------*/
+
+void vRegisterFileSystemCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xDIR );
+ FreeRTOS_CLIRegisterCommand( &xCD );
+ FreeRTOS_CLIRegisterCommand( &xTYPE );
+ FreeRTOS_CLIRegisterCommand( &xDEL );
+ FreeRTOS_CLIRegisterCommand( &xCOPY );
+ FreeRTOS_CLIRegisterCommand( &xTEST_FS );
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;
+static F_FILE *pxFile = NULL;
+int iChar;
+size_t xByte;
+size_t xColumns = 50U;
+
+ /* Ensure there is always a null terminator after each character written. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+
+ /* Ensure the buffer leaves space for the \r\n. */
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+ xWriteBufferLen -= strlen( cliNEW_LINE );
+
+ if( xWriteBufferLen < xColumns )
+ {
+ /* Ensure the loop that uses xColumns as an end condition does not
+ write off the end of the buffer. */
+ xColumns = xWriteBufferLen;
+ }
+
+ if( pxFile == NULL )
+ {
+ /* The file has not been opened yet. Find the file name. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to open the requested file. */
+ pxFile = f_open( pcParameter, "r" );
+ }
+
+ if( pxFile != NULL )
+ {
+ /* Read the next chunk of data from the file. */
+ for( xByte = 0; xByte < xColumns; xByte++ )
+ {
+ iChar = f_getc( pxFile );
+
+ if( iChar == -1 )
+ {
+ /* No more characters to return. */
+ f_close( pxFile );
+ pxFile = NULL;
+ break;
+ }
+ else
+ {
+ pcWriteBuffer[ xByte ] = ( char ) iChar;
+ }
+ }
+ }
+
+ if( pxFile == NULL )
+ {
+ /* Either the file was not opened, or all the data from the file has
+ been returned and the file is now closed. */
+ xReturn = pdFALSE;
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+size_t xStringLength;
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to move to the requested directory. */
+ ucReturned = f_chdir( pcParameter );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ sprintf( pcWriteBuffer, "In: " );
+ xStringLength = strlen( pcWriteBuffer );
+ f_getcwd( &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Error" );
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+static F_FIND *pxFindStruct = NULL;
+unsigned char ucReturned;
+portBASE_TYPE xReturn = pdFALSE;
+
+ /* This assumes pcWriteBuffer is long enough. */
+ ( void ) pcCommandString;
+
+ /* Ensure the buffer leaves space for the \r\n. */
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+ xWriteBufferLen -= strlen( cliNEW_LINE );
+
+ if( pxFindStruct == NULL )
+ {
+ /* This is the first time this function has been executed since the Dir
+ command was run. Create the find structure. */
+ pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );
+
+ if( pxFindStruct != NULL )
+ {
+ ucReturned = f_findfirst( "*.*", pxFindStruct );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ snprintf( pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );
+ }
+ }
+ else
+ {
+ snprintf( pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );
+ }
+ }
+ else
+ {
+ /* The find struct has already been created. Find the next file in
+ the directory. */
+ ucReturned = f_findnext( pxFindStruct );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* There are no more files. Free the find structure. */
+ vPortFree( pxFindStruct );
+ pxFindStruct = NULL;
+
+ /* No string to return. */
+ pcWriteBuffer[ 0 ] = 0x00;
+ }
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+
+ /* This function assumes xWriteBufferLen is large enough! */
+ ( void ) xWriteBufferLen;
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to delete the file. */
+ ucReturned = f_delete( pcParameter );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ sprintf( pcWriteBuffer, "%s was deleted", pcParameter );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Error" );
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTESTFSCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+unsigned portBASE_TYPE uxOriginalPriority;
+
+ /* Avoid compiler warnings. */
+ ( void ) xWriteBufferLen;
+ ( void ) pcCommandString;
+
+ /* Limitations in the interaction with the Windows TCP/IP stack require
+ the command console to run at the idle priority. Raise the priority for
+ the duration of the tests to ensure there are not multiple switches to the
+ idle task as in the simulated environment the idle task hook function may
+ include a (relatively) long delay. */
+ uxOriginalPriority = uxTaskPriorityGet( NULL );
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+
+ f_dotest( 0 );
+
+ /* Reset back to the original priority. */
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+
+ sprintf( pcWriteBuffer, "%s", "Test results were sent to Windows console" );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+char *pcSourceFile;
+const char *pcDestinationFile;
+portBASE_TYPE xParameterStringLength;
+long lSourceLength, lDestinationLength = 0;
+
+ /* Obtain the name of the destination file. */
+ pcDestinationFile = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 2, /* Return the second parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcDestinationFile );
+
+ /* Obtain the name of the source file. */
+ pcSourceFile = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcSourceFile );
+
+ /* Terminate the string. */
+ pcSourceFile[ xParameterStringLength ] = 0x00;
+
+ /* See if the source file exists, obtain its length if it does. */
+ lSourceLength = f_filelength( pcSourceFile );
+
+ if( lSourceLength == 0 )
+ {
+ sprintf( pcWriteBuffer, "Source file does not exist" );
+ }
+ else
+ {
+ /* See if the destination file exists. */
+ lDestinationLength = f_filelength( pcDestinationFile );
+
+ if( lDestinationLength != 0 )
+ {
+ sprintf( pcWriteBuffer, "Error: Destination file already exists" );
+ }
+ }
+
+ /* Continue only if the source file exists and the destination file does
+ not exist. */
+ if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )
+ {
+ if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )
+ {
+ sprintf( pcWriteBuffer, "Copy made" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Error during copy" );
+ }
+ }
+
+ strcat( pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvPerformCopy( const char *pcSourceFile,
+ int32_t lSourceFileLength,
+ const char *pcDestinationFile,
+ char *pxWriteBuffer,
+ size_t xWriteBufferLen )
+{
+int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;
+F_FILE *pxFile;
+portBASE_TYPE xReturn = pdPASS;
+
+ /* NOTE: Error handling has been omitted for clarity. */
+
+ while( lBytesRead < lSourceFileLength )
+ {
+ /* How many bytes are left? */
+ lBytesRemaining = lSourceFileLength - lBytesRead;
+
+ /* How many bytes should be read this time around the loop. Can't
+ read more bytes than will fit into the buffer. */
+ if( lBytesRemaining > ( long ) xWriteBufferLen )
+ {
+ lBytesToRead = ( long ) xWriteBufferLen;
+ }
+ else
+ {
+ lBytesToRead = lBytesRemaining;
+ }
+
+ /* Open the source file, seek past the data that has already been
+ read from the file, read the next block of data, then close the
+ file again so the destination file can be opened. */
+ pxFile = f_open( pcSourceFile, "r" );
+ if( pxFile != NULL )
+ {
+ f_seek( pxFile, lBytesRead, F_SEEK_SET );
+ f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );
+ f_close( pxFile );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ /* Open the destination file and write the block of data to the end of
+ the file. */
+ pxFile = f_open( pcDestinationFile, "a" );
+ if( pxFile != NULL )
+ {
+ f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );
+ f_close( pxFile );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ lBytesRead += lBytesToRead;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateFileInfoString( char *pcBuffer, F_FIND *pxFindStruct )
+{
+const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";
+const char * pcAttrib;
+
+ /* Point pcAttrib to a string that describes the file. */
+ if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )
+ {
+ pcAttrib = pcDirectory;
+ }
+ else if( pxFindStruct->attr & F_ATTR_READONLY )
+ {
+ pcAttrib = pcReadOnlyFile;
+ }
+ else
+ {
+ pcAttrib = pcWritableFile;
+ }
+
+ /* Create a string that includes the file name, the file size and the
+ attributes string. */
+ sprintf( pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, pxFindStruct->filesize );
+}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-system-demo.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-system-demo.c
new file mode 100644
index 0000000..94767c5
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-system-demo.c
@@ -0,0 +1,372 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+
+/* 8.3 format, plus null terminator. */
+#define fsMAX_FILE_NAME_LEN 13
+
+/* The number of bytes read/written to the example files at a time. */
+#define fsRAM_BUFFER_SIZE 200
+
+/* The number of bytes written to the file that uses f_putc() and f_getc(). */
+#define fsPUTC_FILE_SIZE 100
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+void vCreateAndVerifySampleFiles( void );
+
+/*
+ * Create a set of example files in the root directory of the volume using
+ * f_write().
+ */
+static void prvCreateDemoFilesUsing_f_write( void );
+
+/*
+ * Use f_read() to read back and verify the files that were created by
+ * prvCreateDemoFilesUsing_f_write().
+ */
+static void prvVerifyDemoFileUsing_f_read( void );
+
+/*
+ * Create an example file in a sub-directory using f_putc().
+ */
+static void prvCreateDemoFileUsing_f_putc( void );
+
+/*
+ * Use f_getc() to read back and verify the file that was created by
+ * prvCreateDemoFileUsing_f_putc().
+ */
+static void prvVerifyDemoFileUsing_f_getc( void );
+
+/*-----------------------------------------------------------*/
+
+/* A buffer used to both create content to write to disk, and read content back
+from a disk. Note there is no mutual exclusion on this buffer. */
+static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];
+
+/* Names of directories that are created. */
+static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";
+
+/*-----------------------------------------------------------*/
+
+void vCreateAndVerifySampleFiles( void )
+{
+unsigned char ucStatus;
+
+ /* First create the volume. */
+ ucStatus = f_initvolume( ram_initfunc );
+
+ /* It is expected that the volume is not formatted. */
+ if( ucStatus == F_ERR_NOTFORMATTED )
+ {
+ /* Format the created volume. */
+ ucStatus = f_format( F_FAT12_MEDIA );
+ }
+
+ if( ucStatus == F_NO_ERROR )
+ {
+ /* Create a set of files using f_write(). */
+ prvCreateDemoFilesUsing_f_write();
+
+ /* Read back and verify the files that were created using f_write(). */
+ prvVerifyDemoFileUsing_f_read();
+
+ /* Create sub directories two deep then create a file using putc. */
+ prvCreateDemoFileUsing_f_putc();
+
+ /* Read back and verify the file created by
+ prvCreateDemoFileUsing_f_putc(). */
+ prvVerifyDemoFileUsing_f_getc();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFilesUsing_f_write( void )
+{
+portBASE_TYPE xFileNumber, xWriteNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+const portBASE_TYPE xMaxFiles = 5;
+long lItemsWritten;
+F_FILE *pxFile;
+
+ /* Create xMaxFiles files. Each created file will be
+ ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled
+ with a different repeating character. */
+ for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ )
+ {
+ /* Generate a file name. */
+ sprintf( cFileName, "root%03d.txt", xFileNumber );
+
+ /* Obtain the current working directory and print out the file name and
+ the directory into which the file is being written. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Creating file %s in %s\r\n", cFileName, cRAMBuffer );
+
+ /* Open the file, creating the file if it does not already exist. */
+ pxFile = f_open( cFileName, "w" );
+ configASSERT( pxFile );
+
+ /* Fill the RAM buffer with data that will be written to the file. This
+ is just a repeating ascii character that indicates the file number. */
+ memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );
+
+ /* Write the RAM buffer to the opened file a number of times. The
+ number of times the RAM buffer is written to the file depends on the
+ file number, so the length of each created file will be different. */
+ for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )
+ {
+ lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+ configASSERT( lItemsWritten == 1 );
+ }
+
+ /* Close the file so another file can be created. */
+ f_close( pxFile );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_read( void )
+{
+portBASE_TYPE xFileNumber, xReadNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+const portBASE_TYPE xMaxFiles = 5;
+long lItemsRead, lChar;
+F_FILE *pxFile;
+
+ /* Read back the files that were created by
+ prvCreateDemoFilesUsing_f_write(). */
+ for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ )
+ {
+ /* Generate the file name. */
+ sprintf( cFileName, "root%03d.txt", xFileNumber );
+
+ /* Obtain the current working directory and print out the file name and
+ the directory from which the file is being read. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Reading file %s from %s\r\n", cFileName, cRAMBuffer );
+
+ /* Open the file for reading. */
+ pxFile = f_open( cFileName, "r" );
+ configASSERT( pxFile );
+
+ /* Read the file into the RAM buffer, checking the file contents are as
+ expected. The size of the file depends on the file number. */
+ for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )
+ {
+ /* Start with the RAM buffer clear. */
+ memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );
+
+ lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+ configASSERT( lItemsRead == 1 );
+
+ /* Check the RAM buffer is filled with the expected data. Each
+ file contains a different repeating ascii character that indicates
+ the number of the file. */
+ for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )
+ {
+ configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );
+ }
+ }
+
+ /* Close the file. */
+ f_close( pxFile );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFileUsing_f_putc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "In directory %s\r\n", cRAMBuffer );
+
+ /* Create a sub directory. */
+ ucReturn = f_mkdir( pcDirectory1 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Move into the created sub-directory. */
+ ucReturn = f_chdir( pcDirectory1 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "In directory %s\r\n", cRAMBuffer );
+
+ /* Create a subdirectory in the new directory. */
+ ucReturn = f_mkdir( pcDirectory2 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Move into the directory just created - now two directories down from
+ the root. */
+ ucReturn = f_chdir( pcDirectory2 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "In directory %s\r\n", cRAMBuffer );
+ configASSERT( strcmp( cRAMBuffer, pcFullPath ) == 0 );
+
+ /* Generate the file name. */
+ sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+ /* Print out the file name and the directory into which the file is being
+ written. */
+ printf( "Writing file %s in %s\r\n", cFileName, cRAMBuffer );
+
+ pxFile = f_open( cFileName, "w" );
+
+ /* Create a file 1 byte at a time. The file is filled with incrementing
+ ascii characters starting from '0'. */
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+ {
+ iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );
+ }
+
+ /* Finished so close the file. */
+ f_close( pxFile );
+
+ /* Move back to the root directory. */
+ ucReturn = f_chdir( "../.." );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Back in root directory %s\r\n", cRAMBuffer );
+ configASSERT( strcmp( cRAMBuffer, pcRoot ) == 0 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_getc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+ /* Move into the directory in which the file was created. */
+ ucReturn = f_chdir( pcFullPath );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Back in directory %s\r\n", cRAMBuffer );
+ configASSERT( strcmp( cRAMBuffer, pcFullPath ) == 0 );
+
+ /* Generate the file name. */
+ sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+ /* Print out the file name and the directory from which the file is being
+ read. */
+ printf( "Reading file %s in %s\r\n", cFileName, cRAMBuffer );
+
+ /* This time the file is opened for reading. */
+ pxFile = f_open( cFileName, "r" );
+
+ /* Read the file 1 byte at a time. */
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+ {
+ iReturned = f_getc( pxFile );
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );
+ }
+
+ /* Finished so close the file. */
+ f_close( pxFile );
+
+ /* Move back to the root directory. */
+ ucReturn = f_chdir( "../.." );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Back in root directory %s\r\n", cRAMBuffer );
+}
+
+
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/FreeRTOS_Plus_FAT_SL_with_CLI.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/FreeRTOS_Plus_FAT_SL_with_CLI.sln
new file mode 100644
index 0000000..3f819af
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/FreeRTOS_Plus_FAT_SL_with_CLI.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Visual C++ Express 2010
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|Win32 = Debug|Win32
+ Release|Win32 = Release|Win32
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32
+ {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/READ_ME.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/READ_ME.url
new file mode 100644
index 0000000..9c6b614
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/READ_ME.url
@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT_SL/Demos/File_System_Win32_Simulator_demo.shtml
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Run-time-stats-utils.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Run-time-stats-utils.c
new file mode 100644
index 0000000..1d81470
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Run-time-stats-utils.c
@@ -0,0 +1,128 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * Utility functions required to gather run time statistics. See:
+ * http://www.freertos.org/rtos-run-time-stats.html
+ *
+ * Note that this is a simulated port, where simulated time is a lot slower than
+ * real time, therefore the run time counter values have no real meaningful
+ * units.
+ *
+ * Also note that it is assumed this demo is going to be used for short periods
+ * of time only, and therefore timer overflows are not handled.
+*/
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+
+/* Variables used in the creation of the run time stats time base. Run time
+stats record how much time each task spends in the Running state. */
+static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL;
+
+/*-----------------------------------------------------------*/
+
+void vConfigureTimerForRunTimeStats( void )
+{
+LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue;
+
+ /* Initialise the variables used to create the run time stats time base.
+ Run time stats record how much time each task spends in the Running
+ state. */
+
+ if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 )
+ {
+ llTicksPerHundedthMillisecond = 1;
+ }
+ else
+ {
+ /* How many times does the performance counter increment in 1/100th
+ millisecond. */
+ llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL;
+
+ /* What is the performance counter value now, this will be subtracted
+ from readings taken at run time. */
+ QueryPerformanceCounter( &liInitialRunTimeValue );
+ llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart;
+ }
+}
+/*-----------------------------------------------------------*/
+
+unsigned long ulGetRunTimeCounterValue( void )
+{
+LARGE_INTEGER liCurrentCount;
+unsigned long ulReturn;
+
+ /* What is the performance counter value now? */
+ QueryPerformanceCounter( &liCurrentCount );
+
+ /* Subtract the performance counter value reading taken when the
+ application started to get a count from that reference point, then
+ scale to (simulated) 1/100ths of a millisecond. */
+ ulReturn = ( unsigned long ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond );
+
+ return ulReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Sample-CLI-commands.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Sample-CLI-commands.c
new file mode 100644
index 0000000..6d45976
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Sample-CLI-commands.c
@@ -0,0 +1,417 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+ #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+#endif
+
+/* Structure that defines the "run-time-stats" command line command. This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+ "run-time-stats", /* The command string to type. */
+ "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",
+ prvRunTimeStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command. This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+ "task-stats", /* The command string to type. */
+ "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",
+ prvTaskStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command. This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+ "echo-3-parameters",
+ "\r\necho-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n",
+ prvThreeParameterEchoCommand, /* The function to run. */
+ 3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command. This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+ "echo-parameters",
+ "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",
+ prvParameterEchoCommand, /* The function to run. */
+ -1 /* The user can enter any number of commands. */
+};
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ /* Structure that defines the "trace" command line command. This takes a single
+ parameter, which can be either "start" or "stop". */
+ static const CLI_Command_Definition_t xStartStopTrace =
+ {
+ "trace",
+ "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",
+ prvStartStopTraceCommand, /* The function to run. */
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */
+ };
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterSampleCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+
+ #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )
+ {
+ FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskList( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The three parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ if( lParameterNumber == 3L )
+ {
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ xReturn = pdFALSE;
+ lParameterNumber = 0L;
+ }
+ else
+ {
+ /* There are more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter != NULL )
+ {
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* There might be more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ else
+ {
+ /* No more parameters were found. Make sure the write buffer does
+ not contain a valid string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* No more data to return. */
+ xReturn = pdFALSE;
+
+ /* Start over the next time this command is executed. */
+ lParameterNumber = 0;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ const char *pcParameter;
+ portBASE_TYPE lParameterStringLength;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* There are only two valid parameter values. */
+ if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 )
+ {
+ /* Start or restart the trace. */
+ vTraceStop();
+ vTraceClear();
+ vTraceStart();
+
+ sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" );
+ }
+ else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 )
+ {
+ /* End the trace, if one is running. */
+ vTraceStop();
+ sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+ }
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+ }
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/UDPCommandServer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/UDPCommandServer.c
new file mode 100644
index 0000000..8a25339
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/UDPCommandServer.c
@@ -0,0 +1,267 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#pragma comment( lib, "ws2_32.lib" )
+
+/* Win32 includes. */
+#include <WinSock2.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE 60
+
+/* Dimensions the buffer into which string outputs can be placed. */
+#define cmdMAX_OUTPUT_SIZE 1024
+
+/* Dimensions the buffer passed to the recvfrom() call. */
+#define cmdSOCKET_INPUT_BUFFER_SIZE 60
+
+/* DEL acts as a backspace. */
+#define cmdASCII_DEL ( 0x7F )
+
+/*
+ * Open and configure the UDP socket.
+ */
+static SOCKET prvOpenUDPSocket( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Task that provides the input and output for the FreeRTOS+CLI command
+ * interpreter. In this case a WinSock UDP port is used for convenience as this
+ * demo runs in a simulated environment on a Windows PC. See the URL in the
+ * comments within main.c for the location of the online documentation.
+ */
+void vUDPCommandInterpreterTask( void *pvParameters )
+{
+long lBytes, lByte;
+signed char cInChar, cInputIndex = 0;
+static signed char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ];
+portBASE_TYPE xMoreDataToFollow;
+volatile int iErrorCode = 0;
+struct sockaddr_in xClient;
+int xClientAddressLength = sizeof( struct sockaddr_in );
+SOCKET xSocket;
+
+ /* Just to prevent compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Attempt to open the socket. */
+ xSocket = prvOpenUDPSocket();
+
+ if( xSocket != INVALID_SOCKET )
+ {
+ for( ;; )
+ {
+ /* Wait for incoming data on the opened socket. */
+ lBytes = recvfrom( xSocket, cLocalBuffer, sizeof( cLocalBuffer ), 0, ( struct sockaddr * ) &xClient, &xClientAddressLength );
+
+ if( lBytes == SOCKET_ERROR )
+ {
+ /* Something went wrong, but it is not handled by this simple
+ example. */
+ iErrorCode = WSAGetLastError();
+ }
+ else
+ {
+ /* Process each received byte in turn. */
+ lByte = 0;
+ while( lByte < lBytes )
+ {
+ /* The next character in the input buffer. */
+ cInChar = cLocalBuffer[ lByte ];
+ lByte++;
+
+ /* Newline characters are taken as the end of the command
+ string. */
+ if( cInChar == '\n' )
+ {
+ /* Process the input string received prior to the
+ newline. */
+ do
+ {
+ /* Pass the string to FreeRTOS+CLI. */
+ xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE );
+
+ /* Send the output generated by the command's
+ implementation. */
+ sendto( xSocket, cOutputString, strlen( cOutputString ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
+
+ } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */
+
+ /* All the strings generated by the command processing
+ have been sent. Clear the input string ready to receive
+ the next command. */
+ cInputIndex = 0;
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+ /* Transmit a spacer, just to make the command console
+ easier to read. */
+ sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
+ }
+ else
+ {
+ if( cInChar == '\r' )
+ {
+ /* Ignore the character. Newlines are used to
+ detect the end of the input string. */
+ }
+ else if( ( cInChar == '\b' ) || ( cInChar == cmdASCII_DEL ) )
+ {
+ /* Backspace was pressed. Erase the last character
+ in the string - if any. */
+ if( cInputIndex > 0 )
+ {
+ cInputIndex--;
+ cInputString[ cInputIndex ] = '\0';
+ }
+ }
+ else
+ {
+ /* A character was entered. Add it to the string
+ entered so far. When a \n is entered the complete
+ string will be passed to the command interpreter. */
+ if( cInputIndex < cmdMAX_INPUT_SIZE )
+ {
+ cInputString[ cInputIndex ] = cInChar;
+ cInputIndex++;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* The socket could not be opened. */
+ vTaskDelete( NULL );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static SOCKET prvOpenUDPSocket( void )
+{
+WSADATA xWSAData;
+WORD wVersionRequested;
+struct sockaddr_in xServer;
+SOCKET xSocket = INVALID_SOCKET;
+
+ wVersionRequested = MAKEWORD( 2, 2 );
+
+ /* Prepare to use WinSock. */
+ if( WSAStartup( wVersionRequested, &xWSAData ) != 0 )
+ {
+ fprintf( stderr, "Could not open Windows connection.\n" );
+ }
+ else
+ {
+ xSocket = socket( AF_INET, SOCK_DGRAM, 0 );
+ if( xSocket == INVALID_SOCKET)
+ {
+ fprintf( stderr, "Could not create socket.\n" );
+ WSACleanup();
+ }
+ else
+ {
+ /* Zero out the server structure. */
+ memset( ( void * ) &xServer, 0x00, sizeof( struct sockaddr_in ) );
+
+ /* Set family and port. */
+ xServer.sin_family = AF_INET;
+ xServer.sin_port = htons( configUDP_CLI_PORT_NUMBER );
+
+ /* Assign the loopback address */
+ xServer.sin_addr.S_un.S_un_b.s_b1 = 127;
+ xServer.sin_addr.S_un.S_un_b.s_b2 = 0;
+ xServer.sin_addr.S_un.S_un_b.s_b3 = 0;
+ xServer.sin_addr.S_un.S_un_b.s_b4 = 1;
+
+ /* Bind the address to the socket. */
+ if( bind( xSocket, ( struct sockaddr * ) &xServer, sizeof( struct sockaddr_in ) ) == -1 )
+ {
+ fprintf( stderr, "Could not socket to port %d.\n", configUDP_CLI_PORT_NUMBER );
+ closesocket( xSocket );
+ xSocket = INVALID_SOCKET;
+ WSACleanup();
+ }
+ }
+ }
+
+ return xSocket;
+}
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj
new file mode 100644
index 0000000..6257eb7
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj
@@ -0,0 +1,184 @@
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+ <Configuration>Debug</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ <ProjectConfiguration Include="Release|Win32">
+ <Configuration>Release</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ </ItemGroup>
+ <PropertyGroup Label="Globals">
+ <ProjectGuid>{C686325E-3261-42F7-AEB1-DDE5280E1CEB}</ProjectGuid>
+ <ProjectName>RTOSDemo</ProjectName>
+ </PropertyGroup>
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+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
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+ <PropertyGroup>
+ <_ProjectFileVersion>10.0.30319.1</_ProjectFileVersion>
+ <OutDir Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">.\Debug\</OutDir>
+ <IntDir Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">.\Debug\</IntDir>
+ <LinkIncremental Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">true</LinkIncremental>
+ <OutDir Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">.\Release\</OutDir>
+ <IntDir Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">.\Release\</IntDir>
+ <LinkIncremental Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">false</LinkIncremental>
+ </PropertyGroup>
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <Midl>
+ <TypeLibraryName>.\Debug/WIN32.tlb</TypeLibraryName>
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+ <MinimalRebuild>true</MinimalRebuild>
+ <BasicRuntimeChecks>EnableFastChecks</BasicRuntimeChecks>
+ <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
+ <PrecompiledHeaderOutputFile>.\Debug/WIN32.pch</PrecompiledHeaderOutputFile>
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+ <WarningLevel>Level4</WarningLevel>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
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+ <PreprocessorDefinitions>_DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <Culture>0x0c09</Culture>
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+ <Link>
+ <OutputFile>.\Debug/RTOSDemo.exe</OutputFile>
+ <SuppressStartupBanner>true</SuppressStartupBanner>
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+ <ProgramDatabaseFile>.\Debug/WIN32.pdb</ProgramDatabaseFile>
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+ <ClCompile Include="File-system-demo.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\drv.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\fat.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\file.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util_sfn.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\volume.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\media-drv\ram\ramdrv_f.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\psp\target\rtc\psp_rtc.c" />
+ <ClCompile Include="main.c">
+ <AdditionalIncludeDirectories Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ <PreprocessorDefinitions Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ </ClCompile>
+ <ClCompile Include="Run-time-stats-utils.c" />
+ <ClCompile Include="Sample-CLI-commands.c" />
+ <ClCompile Include="UDPCommandServer.c" />
+ </ItemGroup>
+ <ItemGroup>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\FreeRTOS.h" />
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\projdefs.h" />
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\queue.h" />
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\semphr.h" />
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\task.h" />
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\timers.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\api\fat_sl.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\f_lock.h" />
+ <ClInclude Include="ConfigurationFiles\config_fat_sl.h" />
+ <ClInclude Include="ConfigurationFiles\config_fat_sl_test.h" />
+ <ClInclude Include="FreeRTOSConfig.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\drv.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\fat.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\file.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util_sfn.h" />
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\volume.h" />
+ </ItemGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
+ <ImportGroup Label="ExtensionTargets">
+ </ImportGroup>
+</Project>
\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.filters
new file mode 100644
index 0000000..72966a4
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.filters
@@ -0,0 +1,180 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <ItemGroup>
+ <Filter Include="Resource Files">
+ <UniqueIdentifier>{38712199-cebf-4124-bf15-398f7c3419ea}</UniqueIdentifier>
+ <Extensions>ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe</Extensions>
+ </Filter>
+ <Filter Include="FreeRTOS">
+ <UniqueIdentifier>{af3445a1-4908-4170-89ed-39345d90d30c}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS\Source">
+ <UniqueIdentifier>{f32be356-4763-4cae-9020-974a2638cb08}</UniqueIdentifier>
+ <Extensions>*.c</Extensions>
+ </Filter>
+ <Filter Include="FreeRTOS\Source\Portable">
+ <UniqueIdentifier>{88f409e6-d396-4ac5-94bd-7a99c914be46}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+">
+ <UniqueIdentifier>{e5ad4ec7-23dc-4295-8add-2acaee488f5a}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+CLI">
+ <UniqueIdentifier>{fd43c0ed-fdbc-437f-a5a3-c50399690bd7}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+CLI\include">
+ <UniqueIdentifier>{c5889fe2-af0f-4cea-927f-6a6935ec5e14}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL">
+ <UniqueIdentifier>{d261611a-5416-4455-bb33-3bd84381ea40}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL\Media_Driver">
+ <UniqueIdentifier>{17c1a794-a4a6-4358-850f-2a88bfe3bd33}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL\psp">
+ <UniqueIdentifier>{fb7ccc1d-c4ad-475a-98d9-2e8ae2301c99}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL\psp\target">
+ <UniqueIdentifier>{34bb4a98-fb88-41fc-81f2-4e3f1c50c528}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL\psp\target\rtc">
+ <UniqueIdentifier>{286bf65c-93cd-4480-8363-0fb2c2bc7ce1}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="Configuration Files">
+ <UniqueIdentifier>{19ff1a34-36de-4c48-9d10-3fb1fa0d1fa4}</UniqueIdentifier>
+ <Extensions>h;hpp;hxx;hm;inl</Extensions>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL\tests">
+ <UniqueIdentifier>{e4105d81-802a-4210-b40b-d5dd3cf6e643}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS\Source\include">
+ <UniqueIdentifier>{ab23827c-126c-4e5a-bc99-8efa44d8a8bd}</UniqueIdentifier>
+ </Filter>
+ <Filter Include="FreeRTOS+\FreeRTOS+FAT SL\api">
+ <UniqueIdentifier>{9e1c9cf5-c2c7-4f8d-b09d-0b7f329eac57}</UniqueIdentifier>
+ </Filter>
+ </ItemGroup>
+ <ItemGroup>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MSVC-MingW\port.c">
+ <Filter>FreeRTOS\Source\Portable</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\timers.c">
+ <Filter>FreeRTOS\Source</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\list.c">
+ <Filter>FreeRTOS\Source</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\queue.c">
+ <Filter>FreeRTOS\Source</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\tasks.c">
+ <Filter>FreeRTOS\Source</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MemMang\heap_4.c">
+ <Filter>FreeRTOS\Source\Portable</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c">
+ <Filter>FreeRTOS+\FreeRTOS+CLI</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\media-drv\ram\ramdrv_f.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL\Media_Driver</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\psp\target\rtc\psp_rtc.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL\psp\target\rtc</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\drv.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\fat.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\file.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util_sfn.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\volume.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="UDPCommandServer.c" />
+ <ClCompile Include="File-Releated-CLI-commands.c" />
+ <ClCompile Include="File-system-demo.c" />
+ <ClCompile Include="main.c" />
+ <ClCompile Include="Run-time-stats-utils.c" />
+ <ClCompile Include="Sample-CLI-commands.c" />
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\psp\target\fat_sl\psp_test.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\test\test.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL\tests</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\f_lock.c">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClCompile>
+ </ItemGroup>
+ <ItemGroup>
+ <ClInclude Include="FreeRTOSConfig.h">
+ <Filter>Configuration Files</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.h">
+ <Filter>FreeRTOS+\FreeRTOS+CLI\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\volume.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\drv.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\fat.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\file.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util_sfn.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="ConfigurationFiles\config_fat_sl.h">
+ <Filter>Configuration Files</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\timers.h">
+ <Filter>FreeRTOS\Source\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\FreeRTOS.h">
+ <Filter>FreeRTOS\Source\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\projdefs.h">
+ <Filter>FreeRTOS\Source\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\queue.h">
+ <Filter>FreeRTOS\Source\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\semphr.h">
+ <Filter>FreeRTOS\Source\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\..\FreeRTOS\Source\include\task.h">
+ <Filter>FreeRTOS\Source\include</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\api\fat_sl.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL\api</Filter>
+ </ClInclude>
+ <ClInclude Include="..\..\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\f_lock.h">
+ <Filter>FreeRTOS+\FreeRTOS+FAT SL</Filter>
+ </ClInclude>
+ <ClInclude Include="ConfigurationFiles\config_fat_sl_test.h">
+ <Filter>Configuration Files</Filter>
+ </ClInclude>
+ </ItemGroup>
+</Project>
\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.user
new file mode 100644
index 0000000..695b5c7
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.user
@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+</Project>
\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/main.c
new file mode 100644
index 0000000..ee7340f
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/main.c
@@ -0,0 +1,228 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/******************************************************************************
+ *
+ * This demo is described on the following web page:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT_SL/Demos/File_System_Win32_Simulator_demo.shtml
+ *
+ ******************************************************************************/
+
+/* Standard includes. */
+#include <stdio.h>
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* File system includes. */
+#include "config_fat_sl.h"
+
+/* Priorities at which the tasks are created. */
+#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Register the generic commands that can be used with FreeRTOS+CLI.
+ */
+extern void vRegisterSampleCLICommands( void );
+
+/*
+ * Register the file system commands that can be used with FreeRTOS+CLI.
+ */
+extern void vRegisterFileSystemCLICommands( void );
+
+/*
+ * The task that implements the UDP command interpreter using FreeRTOS+CLI.
+ */
+extern void vUDPCommandInterpreterTask( void *pvParameters );
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+extern void vCreateAndVerifySampleFiles( void );
+
+/*-----------------------------------------------------------*/
+
+/******************************************************************************
+ *
+ * This demo is described on the following web page:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT_SL/Demos/File_System_Win32_Simulator_demo.shtml
+ *
+ ******************************************************************************/
+
+int main( void )
+{
+const uint32_t ulLongTime_ms = 250UL;
+
+ /* If the file system is only going to be accessed from one task then
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files are created
+ before the RTOS scheduler is started. If the file system is going to be
+ access from more than one task then F_FS_THREAD_AWARE must be set to 1 and
+ the set of sample files are created from the idle task hook function
+ vApplicationIdleHook() - which is defined in this file. */
+ #if F_FS_THREAD_AWARE == 0
+ {
+ /* Initialise the drive and file system, then create a few example
+ files. The output from this function just goes to the stdout window,
+ allowing the output to be viewed when the UDP command console is not
+ connected. */
+ vCreateAndVerifySampleFiles();
+ }
+ #endif
+
+ /* Register generic commands with the FreeRTOS+CLI command interpreter. */
+ vRegisterSampleCLICommands();
+
+ /* Register file system related commands with the FreeRTOS+CLI command
+ interpreter. */
+ vRegisterFileSystemCLICommands();
+
+ /* Create the task that handles the CLI on a UDP port. The port number
+ is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */
+ xTaskCreate( vUDPCommandInterpreterTask, /* The function that implements the command interpreter IO handling. */
+ "CLI", /* The name of the task - just to assist debugging. */
+ configMINIMAL_STACK_SIZE, NULL, /* The size of the stack allocated to the task. */
+ mainUDP_CLI_TASK_PRIORITY, /* The priority at which the task will run. */
+ NULL ); /* A handle to the task is not required, so NULL is passed. */
+
+ /* Start the RTOS scheduler. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the idle and/or
+ timer tasks to be created. See the memory management section on the
+ FreeRTOS web site for more details (this is standard text that is not not
+ really applicable to the Win32 simulator port). */
+ for( ;; )
+ {
+ Sleep( ulLongTime_ms );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+const unsigned long ulMSToSleep = 5;
+
+ /* If the file system is only going to be accessed from one task then
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files is created
+ before the RTOS scheduler is started. If the file system is going to be
+ access from more than one task then F_FS_THREAD_AWARE must be set to 1 and
+ the set of sample files are created from the idle task hook function. */
+ #if F_FS_THREAD_AWARE == 1
+ {
+ static portBASE_TYPE xCreatedSampleFiles = pdFALSE;
+
+ /* Initialise the drive and file system, then create a few example
+ files. The output from this function just goes to the stdout window,
+ allowing the output to be viewed when the UDP command console is not
+ connected. */
+ if( xCreatedSampleFiles == pdFALSE )
+ {
+ vCreateAndVerifySampleFiles();
+ xCreatedSampleFiles = pdTRUE;
+ }
+ }
+ #endif
+
+ /* This function is called on each cycle of the idle task if
+ configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU
+ load. */
+ Sleep( ulMSToSleep );
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( const char *pcFile, unsigned long ulLine )
+{
+ printf( "ASSERT FAILED: File %s, line %u\r\n", pcFile, ulLine );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the
+ size of the heap available to pvPortMalloc() is defined by
+ configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize()
+ API function can be used to query the size of free heap space that remains
+ (although it does not provide information on how the remaining heap might
+ be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/Read_Me_Instructions.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/Read_Me_Instructions.url
new file mode 100644
index 0000000..86d28f1
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/Read_Me_Instructions.url
@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/Atmel_SAM4E_RTOS_Demo.html
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject
new file mode 100644
index 0000000..8107b25
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject
@@ -0,0 +1,228 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.crt.advproject.config.exe.debug.56486929">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.56486929" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.56486929;com.crt.advproject.config.exe.debug.56486929.;com.crt.advproject.gas.exe.debug.281614531;com.crt.advproject.assembler.input.1243504913">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+</cproject>
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project
new file mode 100644
index 0000000..aa42a5e
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>FreeRTOS_UDP_Demo</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000..733f315
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+useParentScope=false
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs
new file mode 100644
index 0000000..cfcd1d3
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c
new file mode 100644
index 0000000..09ee590
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c
@@ -0,0 +1,667 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+UDP includes, just to make the stats available to the CLI
+commands. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+ #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that prints out IP address information.
+ */
+static portBASE_TYPE prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that prints out the gathered demo debug stats.
+ */
+static portBASE_TYPE prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Defines a command that sends an ICMP ping request to an IP address.
+ */
+static portBASE_TYPE prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+#endif
+
+/* Structure that defines the "ip-config" command line command. */
+static const CLI_Command_Definition_t xIPConfig =
+{
+ "ip-config",
+ "ip-config:\r\n Displays IP address configuration\r\n\r\n",
+ prvDisplayIPConfig,
+ 0
+};
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+ /* Structure that defines the "ip-debug-stats" command line command. */
+ static const CLI_Command_Definition_t xIPDebugStats =
+ {
+ "ip-debug-stats", /* The command string to type. */
+ "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n",
+ prvDisplayIPDebugStats, /* The function to run. */
+ 0 /* No parameters are expected. */
+ };
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+/* Structure that defines the "run-time-stats" command line command. This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+ "run-time-stats", /* The command string to type. */
+ "run-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n",
+ prvRunTimeStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command. This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+ "task-stats", /* The command string to type. */
+ "task-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n",
+ prvTaskStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command. This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+ "echo-3-parameters",
+ "echo-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n\r\n",
+ prvThreeParameterEchoCommand, /* The function to run. */
+ 3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command. This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+ "echo-parameters",
+ "echo-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n",
+ prvParameterEchoCommand, /* The function to run. */
+ -1 /* The user can enter any number of commands. */
+};
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+ /* Structure that defines the "ping" command line command. This takes an IP
+ address or host name and (optionally) the number of bytes to ping as
+ parameters. */
+ static const CLI_Command_Definition_t xPing =
+ {
+ "ping",
+ "ping <ipaddress> <optional:bytes to send>:\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n",
+ prvPingCommand, /* The function to run. */
+ -1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */
+ };
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ /* Structure that defines the "trace" command line command. This takes a single
+ parameter, which can be either "start" or "stop". */
+ static const CLI_Command_Definition_t xStartStopTrace =
+ {
+ "trace",
+ "trace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n",
+ prvStartStopTraceCommand, /* The function to run. */
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */
+ };
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xIPDebugStats );
+ FreeRTOS_CLIRegisterCommand( &xIPConfig );
+
+ #if ipconfigSUPPORT_OUTGOING_PINGS == 1
+ {
+ FreeRTOS_CLIRegisterCommand( &xPing );
+ }
+ #endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+ #if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskList( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( pcWriteBuffer, pcHeader );
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The three parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ if( lParameterNumber == 3L )
+ {
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ xReturn = pdFALSE;
+ lParameterNumber = 0L;
+ }
+ else
+ {
+ /* There are more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+const char *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( pcWriteBuffer, "The parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter != NULL )
+ {
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( pcWriteBuffer, pcParameter, xParameterStringLength );
+ strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* There might be more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ else
+ {
+ /* No more parameters were found. Make sure the write buffer does
+ not contain a valid string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* No more data to return. */
+ xReturn = pdFALSE;
+
+ /* Start over the next time this command is executed. */
+ lParameterNumber = 0;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+ static portBASE_TYPE prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ char * pcParameter;
+ portBASE_TYPE lParameterStringLength, xReturn;
+ uint32_t ulIPAddress, ulBytesToPing;
+ const uint32_t ulDefaultBytesToPing = 8UL;
+ char cBuffer[ 16 ];
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Start with an empty string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* Obtain the number of bytes to ping. */
+ pcParameter = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 2, /* Return the second parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter == NULL )
+ {
+ /* The number of bytes was not specified, so default it. */
+ ulBytesToPing = ulDefaultBytesToPing;
+ }
+ else
+ {
+ ulBytesToPing = atol( pcParameter );
+ }
+
+ /* Obtain the IP address string. */
+ pcParameter = ( char * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to obtain the IP address. If the first character is not a
+ digit, assume the host name has been passed in. */
+ if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) )
+ {
+ ulIPAddress = FreeRTOS_inet_addr( pcParameter );
+ }
+ else
+ {
+ /* Terminate the host name. */
+ pcParameter[ lParameterStringLength ] = 0x00;
+
+ /* Attempt to resolve host. */
+ ulIPAddress = FreeRTOS_gethostbyname( pcParameter );
+ }
+
+ /* Convert IP address, which may have come from a DNS lookup, to string. */
+ FreeRTOS_inet_ntoa( ulIPAddress, cBuffer );
+
+ if( ulIPAddress != 0 )
+ {
+ xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY );
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( xReturn == pdFALSE )
+ {
+ sprintf( pcWriteBuffer, "%s", "Could not send ping request\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, xReturn );
+ }
+
+ return pdFALSE;
+ }
+ /*-----------------------------------------------------------*/
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+
+ static portBASE_TYPE prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ static portBASE_TYPE xIndex = -1;
+ extern xExampleDebugStatEntry_t xIPTraceValues[];
+ portBASE_TYPE xReturn;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ xIndex++;
+
+ if( xIndex < xExampleDebugStatEntries() )
+ {
+ sprintf( pcWriteBuffer, "%s %d\r\n", xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Reset the index for the next time it is called. */
+ xIndex = -1;
+
+ /* Ensure nothing remains in the write buffer. */
+ pcWriteBuffer[ 0 ] = 0x00;
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+ }
+ /*-----------------------------------------------------------*/
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+static portBASE_TYPE prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+static portBASE_TYPE xIndex = 0;
+portBASE_TYPE xReturn;
+uint32_t ulAddress;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ switch( xIndex )
+ {
+ case 0 :
+ FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL );
+ sprintf( pcWriteBuffer, "\r\nIP address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 1 :
+ FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL );
+ sprintf( pcWriteBuffer, "\r\nNet mask " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 2 :
+ FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL );
+ sprintf( pcWriteBuffer, "\r\nGateway address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ case 3 :
+ FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress );
+ sprintf( pcWriteBuffer, "\r\nDNS server address " );
+ xReturn = pdTRUE;
+ xIndex++;
+ break;
+
+ default :
+ ulAddress = 0;
+ sprintf( pcWriteBuffer, "\r\n\r\n" );
+ xReturn = pdFALSE;
+ xIndex = 0;
+ break;
+ }
+
+ if( ulAddress != 0 )
+ {
+ FreeRTOS_inet_ntoa( ulAddress, &( pcWriteBuffer[ strlen( pcWriteBuffer ) ] ) );
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+ static portBASE_TYPE prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+ {
+ const char *pcParameter;
+ portBASE_TYPE lParameterStringLength;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Obtain the parameter string. */
+ pcParameter = FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* There are only two valid parameter values. */
+ if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 )
+ {
+ /* Start or restart the trace. */
+ vTraceStop();
+ vTraceClear();
+ vTraceStart();
+
+ sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" );
+ }
+ else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 )
+ {
+ /* End the trace, if one is running. */
+ vTraceStop();
+ sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" );
+ }
+ else
+ {
+ sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+ }
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+ }
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat
new file mode 100644
index 0000000..e60a79e
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat
@@ -0,0 +1,80 @@
+REM This file should be executed from the command line prior to the first
+REM build. It will be necessary to refresh the Eclipse project once the
+REM .bat file has been executed (normally just press F5 to refresh).
+
+REM Copies all the required files from their location within the standard
+REM FreeRTOS directory structure to under the Eclipse project directory.
+REM This permits the Eclipse project to be used in 'managed' mode and without
+REM having to setup any linked resources.
+
+REM Standard paths
+SET FREERTOS_SOURCE=..\..\..\FreeRTOS\Source
+SET FREERTOS_UDP_SOURCE=..\..\Source\FreeRTOS-Plus-UDP
+SET FREERTOS_CLI_SOURCE=..\..\Source\FreeRTOS-Plus-CLI
+set FREERTOS_TRACE_RECORDER_SOURCE=..\..\Source\FreeRTOS-Plus-Trace
+
+REM Have the files already been copied?
+IF EXIST FreeRTOS_Source Goto END
+
+ REM Create the required directory structure.
+ MD FreeRTOS_Source
+ MD FreeRTOS_Source\include
+ MD FreeRTOS_Source\portable\
+ MD FreeRTOS_Source\portable\GCC
+ MD FreeRTOS_Source\portable\GCC\ARM_CM3
+ MD FreeRTOS_Source\portable\MemMang
+ MD FreeRTOS_Plus_UDP
+ MD FreeRTOS_Plus_UDP\include
+ MD FreeRTOS_Plus_UDP\portable
+ MD FreeRTOS_Plus_UDP\portable\Compiler
+ MD FreeRTOS_Plus_UDP\portable\Compiler\GCC
+ MD FreeRTOS_Plus_UDP\portable\BufferManagement
+ MD FreeRTOS_Plus_UDP\portable\NetworkInterface
+ MD FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
+ MD FreeRTOS_Plus_CLI
+ MD Examples\Ethernet
+
+ REM Copy the core kernel files into the SDK projects directory
+ copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source
+
+ REM Copy the common header files into the SDK projects directory
+ copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include
+
+ REM Copy the portable layer files into the projects directory
+ copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3
+
+ REM Copy the memory allocation file into the project's directory
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang
+
+ REM Copy the FreeRTOS+UDP core files
+ copy %FREERTOS_UDP_SOURCE%\*.c FreeRTOS_Plus_UDP
+ copy %FREERTOS_UDP_SOURCE%\readme.txt FreeRTOS_Plus_UDP
+ copy %FREERTOS_UDP_SOURCE%\include\*.* FreeRTOS_Plus_UDP\include
+
+ REM Copy the FreeRTOS+UDP portable layer files
+ copy %FREERTOS_UDP_SOURCE%\portable\NetworkInterface\LPC18xx\Using_CMSISv2p10_LPC18xx_DriverLib\*.* FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
+ copy %FREERTOS_UDP_SOURCE%\portable\BufferManagement\BufferAllocation_2.c FreeRTOS_Plus_UDP\portable\BufferManagement
+ copy %FREERTOS_UDP_SOURCE%\portable\Compiler\GCC\*.* FreeRTOS_Plus_UDP\portable\Compiler\GCC
+
+ REM Copy the FreeRTOS+CLI files
+ copy %FREERTOS_CLI_SOURCE%\*.* FreeRTOS_Plus_CLI
+
+ REM Copy the FreeRTOS+Trace recorder files
+ copy %FREERTOS_TRACE_RECORDER_SOURCE%\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder
+ copy %FREERTOS_TRACE_RECORDER_SOURCE%\include\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder\include
+
+ REM Copy the echo client example implementation
+ copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c Examples\Ethernet
+ copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.h Examples\include
+
+ REM Copy the example IP trace macro implementation
+ copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.c Examples\Ethernet
+ copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.h Examples\include
+
+ REM Copy the CLI commands implementation into the project directory.
+ copy ..\Common\FreeRTOS_Plus_UDP_Demos\CLICommands\CLI-commands.c .
+
+: END
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c
new file mode 100644
index 0000000..c6d2e33
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c
@@ -0,0 +1,339 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * NOTE: This file uses a third party USB CDC driver.
+ */
+
+/* Standard includes. */
+#include "string.h"
+#include "stdio.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Driver includes. */
+#include "usbhw.h"
+#include "cdcuser.h"
+#include "usbcfg.h"
+#include "usbuser.h"
+
+/* Example includes. */
+#include "FreeRTOS_CLI.h"
+#include "CDCCommandConsole.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE 50
+
+/* The maximum time in ticks to wait for the CDC access mutex. */
+#define cmdMAX_MUTEX_WAIT ( 200 / portTICK_RATE_MS )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that implements the command console processing.
+ */
+static void prvCDCCommandConsoleTask( void *pvParameters );
+
+/*
+ * Obtain a character from the CDC input. The calling task will be held in the
+ * Blocked state (so other tasks can execute) until a character is avilable.
+ */
+char cGetCDCChar( void );
+
+/*
+ * Initialise the third party virtual comport files driver
+ */
+static void prvSetupUSBDrivers( void );
+
+/*-----------------------------------------------------------*/
+
+/* 'Given' by the CDC interrupt to unblock the receiving task when new data
+is available. */
+static xSemaphoreHandle xNewDataSemaphore = NULL;
+
+/* Used to guard access to the CDC output, which is used by more than one
+task. */
+static xSemaphoreHandle xCDCMutex = NULL;
+
+/* Const messages output by the command console. */
+static const char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
+static const char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";
+static const char * const pcNewLine = "\r\n";
+
+/*-----------------------------------------------------------*/
+
+void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority )
+{
+ /* Create the semaphores and mutexes used by the CDC to task interface. */
+ xCDCMutex = xSemaphoreCreateMutex();
+ vSemaphoreCreateBinary( xNewDataSemaphore );
+ configASSERT( xCDCMutex );
+ configASSERT( xNewDataSemaphore );
+
+ /* Add the semaphore and mutex to the queue registry for viewing in the
+ kernel aware state viewer. */
+ vQueueAddToRegistry( xCDCMutex, "CDCMu" );
+ vQueueAddToRegistry( xNewDataSemaphore, "CDCDat" );
+
+ /* Create that task that handles the console itself. */
+ xTaskCreate( prvCDCCommandConsoleTask, /* The task that implements the command console. */
+ "CDCCmd", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */
+ usStackSize, /* The size of the stack allocated to the task. */
+ NULL, /* The parameter is not used, so NULL is passed. */
+ uxPriority, /* The priority allocated to the task. */
+ NULL ); /* A handle is not required, so just pass NULL. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvCDCCommandConsoleTask( void *pvParameters )
+{
+char cRxedChar;
+uint8_t ucInputIndex = 0;
+char *pcOutputString;
+static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
+portBASE_TYPE xReturned;
+
+ ( void ) pvParameters;
+
+ /* Obtain the address of the output buffer. Note there is no mutual
+ exclusion on this buffer as it is assumed only one command console
+ interface will be used at any one time. */
+ pcOutputString = FreeRTOS_CLIGetOutputBuffer();
+
+ /* Initialise the virtual com port (CDC) interface. */
+ prvSetupUSBDrivers();
+
+ /* Send the welcome message. This probably won't be seen as the console
+ will not have been connected yet. */
+ USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcWelcomeMessage, strlen( pcWelcomeMessage ) );
+
+ for( ;; )
+ {
+ /* No characters received yet for the current input string. */
+ cRxedChar = 0;
+
+ /* Only interested in reading one character at a time. */
+ cRxedChar = cGetCDCChar();
+
+ if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+ {
+ /* Echo the character back. */
+ USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) &cRxedChar, sizeof( uint8_t ) );
+
+ /* Was it the end of the line? */
+ if( cRxedChar == '\n' || cRxedChar == '\r' )
+ {
+ /* Just to space the output from the input. */
+ USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcNewLine, strlen( pcNewLine ) );
+
+ /* See if the command is empty, indicating that the last command is
+ to be executed again. */
+ if( ucInputIndex == 0 )
+ {
+ /* Copy the last command back into the input string. */
+ strcpy( cInputString, cLastInputString );
+ }
+
+ /* Pass the received command to the command interpreter. The
+ command interpreter is called repeatedly until it returns pdFALSE
+ (indicating there is no more output) as it might generate more than
+ one string. */
+ do
+ {
+ /* Get the next output string from the command interpreter. */
+ xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
+
+ /* Write the generated string to the CDC. */
+ USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcOutputString, strlen( pcOutputString ) );
+ vTaskDelay( 1 );
+
+ } while( xReturned != pdFALSE );
+
+ /* All the strings generated by the input command have been sent.
+ Clear the input string ready to receive the next command. Remember
+ the command that was just processed first in case it is to be
+ processed again. */
+ strcpy( cLastInputString, cInputString );
+ ucInputIndex = 0;
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+ USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcEndOfOutputMessage, strlen( pcEndOfOutputMessage ) );
+ }
+ else
+ {
+ if( cRxedChar == '\r' )
+ {
+ /* Ignore the character. */
+ }
+ else if( cRxedChar == '\b' )
+ {
+ /* Backspace was pressed. Erase the last character in the
+ string - if any. */
+ if( ucInputIndex > 0 )
+ {
+ ucInputIndex--;
+ cInputString[ ucInputIndex ] = '\0';
+ }
+ }
+ else
+ {
+ /* A character was entered. Add it to the string
+ entered so far. When a \n is entered the complete
+ string will be passed to the command interpreter. */
+ if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
+ {
+ if( ucInputIndex < cmdMAX_INPUT_SIZE )
+ {
+ cInputString[ ucInputIndex ] = cRxedChar;
+ ucInputIndex++;
+ }
+ }
+ }
+ }
+
+ /* Must ensure to give the mutex back. */
+ xSemaphoreGive( xCDCMutex );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vOutputString( const char * const pcMessage )
+{
+ if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+ {
+ USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcMessage, strlen( pcMessage ) );
+ xSemaphoreGive( xCDCMutex );
+ }
+}
+/*-----------------------------------------------------------*/
+
+char cGetCDCChar( void )
+{
+int32_t lAvailableBytes, xBytes = 0;
+char cInputChar;
+
+ do
+ {
+ /* Are there any characters already available? */
+ CDC_OutBufAvailChar( &lAvailableBytes );
+ if( lAvailableBytes > 0 )
+ {
+ if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+ {
+ /* Attempt to read one character. */
+ xBytes = 1;
+ xBytes = CDC_RdOutBuf( &cInputChar, &xBytes );
+
+ xSemaphoreGive( xCDCMutex );
+ }
+ }
+
+ if( xBytes == 0 )
+ {
+ /* A character was not available. Wait until signalled by the
+ CDC Rx callback function that new data has arrived. */
+ xSemaphoreTake( xNewDataSemaphore, portMAX_DELAY );
+ }
+
+ } while( xBytes == 0 );
+
+ return cInputChar;
+}
+/*-----------------------------------------------------------*/
+
+/* Callback function executed by the USB interrupt when new data arrives. */
+void vCDCNewDataNotify( void )
+{
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+ configASSERT( xNewDataSemaphore );
+
+ /* 'Give' the semaphore that signals the arrival of new data to the command
+ console task. */
+ xSemaphoreGiveFromISR( xNewDataSemaphore, &xHigherPriorityTaskWoken );
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupUSBDrivers( void )
+{
+LPC_USBDRV_INIT_T xUSBCallback;
+
+ /* Initialise the callback structure. */
+ memset( ( void * ) &xUSBCallback, 0, sizeof( LPC_USBDRV_INIT_T ) );
+ xUSBCallback.USB_Reset_Event = USB_Reset_Event;
+ xUSBCallback.USB_P_EP[ 0 ] = USB_EndPoint0;
+ xUSBCallback.USB_P_EP[ 1 ] = USB_EndPoint1;
+ xUSBCallback.USB_P_EP[ 2 ] = USB_EndPoint2;
+ xUSBCallback.ep0_maxp = USB_MAX_PACKET0;
+
+ /* Initialise then connect the USB. */
+ USB_Init( &xUSBCallback );
+ USB_Connect( pdTRUE );
+}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h
new file mode 100644
index 0000000..1833c30
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h
@@ -0,0 +1,78 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef CDC_COMMAND_CONSOLE_H
+#define CDC_COMMAND_CONSOLE_H
+
+/*
+ * Create the task that implements a command console using the USB virtual com
+ * port driver for intput and output.
+ */
+void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority );
+
+#endif /* CDC_COMMAND_CONSOLE_H */
+
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h
new file mode 100644
index 0000000..c69748d
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h
@@ -0,0 +1,76 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef TWO_ECHO_CLIENTS_H
+#define TWO_ECHO_CLIENTS_H
+
+/*
+ * Create the two UDP echo client tasks. One task uses the standard interface
+ * to send to and receive from an echo server. The other task uses the zero
+ * copy interface to send to and receive from an echo server.
+ */
+void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority );
+
+#endif /* TWO_ECHO_CLIENTS_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml
new file mode 100644
index 0000000..1fb1cd3
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml
@@ -0,0 +1,12 @@
+<info flash_driver='LPC1850A_4350A_SPIFI.cfx'>
+ <chip>
+ <memory id='Flash' type='Flash' is_ro='true' can_program='true'></memory>
+ <memory id='RAM' type='RAM'></memory>
+ <memoryInstance id='SPIFlash' derived_from='Flash' location='0x14000000' size='0x400000' edited='true'/>
+ <memoryInstance id='RamLoc96' derived_from='RAM' location='0x10000000' size='0x18000' edited='true'/>
+ <memoryInstance id='RamLoc40' derived_from='RAM' location='0x10080000' size='0xa000' edited='true'/>
+ <memoryInstance id='RamAHB32' derived_from='RAM' location='0x20000000' size='0x8000' edited='true'/>
+ <memoryInstance id='RamAHB16' derived_from='RAM' location='0x20008000' size='0x4000' edited='true'/>
+ <memoryInstance id='RamAHB_ETB16' derived_from='RAM' location='0x2000c000' size='0x4000' edited='true'/>
+ </chip>
+</info>
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h
new file mode 100644
index 0000000..a1d8b78
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h
@@ -0,0 +1,282 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <stdint.h>
+extern uint32_t SystemCoreClock;
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *
+ * The bottom of this file contains some constants specific to running the UDP
+ * stack in this demo. Constants specific to FreeRTOS+UDP itself (rather than
+ * the demo) are contained in FreeRTOSIPConfig.h.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configMAX_PRIORITIES ( 7 )
+#define configCPU_CLOCK_HZ ( SystemCoreClock )
+#define configTICK_RATE_HZ 100
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 300 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) /* Has not effect in this demo as the heap is manually pointed to AHB RAM. */
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configIDLE_SHOULD_YIELD 0
+#define configQUEUE_REGISTRY_SIZE 10
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configUSE_MUTEXES 1
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+#define configUSE_RECURSIVE_MUTEXES 1
+
+/* Hook function related definitions. */
+#define configUSE_TICK_HOOK 0
+#define configUSE_IDLE_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Run time stats gathering definitions. */
+void vMainConfigureTimerForRunTimeStats( void );
+uint32_t ulMainGetRunTimeCounterValue( void );
+#define configGENERATE_RUN_TIME_STATS 1
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vMainConfigureTimerForRunTimeStats()
+#define portGET_RUN_TIME_COUNTER_VALUE() ulMainGetRunTimeCounterValue()
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTimerGetTimerTaskHandle 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xQueueGetMutexHolder 1
+
+/* This demo makes use of one or more example stats formatting functions. These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form. See the notes in the implementation of vTaskList() within
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+
+/* Assert statement defined for debug builds. */
+#ifdef DEBUG
+ #define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+#endif
+
+/* Interrupt priority configuration settings follow.
+http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+
+/* Use the system definition for the number of interrupt priorities, if there
+is one */
+#ifdef __NVIC_PRIO_BITS
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS 3 /* 8 priority levels */
+#endif
+
+/* The maximum priority an interrupt that uses an interrupt safe FreeRTOS API
+function can have. Note that lower priority have numerically higher values. */
+#define configMAX_LIBRARY_INTERRUPT_PRIORITY ( 5 )
+
+/* The minimum possible interrupt priority. */
+#define configMIN_LIBRARY_INTERRUPT_PRIORITY ( 7 )
+
+/* The lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY ( configMIN_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Priority 5, or 248 as only the top five bits are implemented. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configMAX_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+
+/*
+ * DEMO APPLICATION SPECIFIC DEFINITIONS FOLLOW FROM HERE
+ */
+
+/* Set to 1 to include "trace start" and "trace stop" CLI commands. These
+commands start and stop the FreeRTOS+Trace recording. */
+#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 1
+
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command
+interpreter. See the FreeRTOS+CLI documentation for more information:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1024
+
+/* The priority used by the Ethernet MAC driver interrupt. */
+#define configMAC_INTERRUPT_PRIORITY ( configMAX_LIBRARY_INTERRUPT_PRIORITY )
+
+/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace
+macros are defined to gather some UDP stack statistics that can then be viewed
+through the CLI interface. See
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml*/
+#define configINCLUDE_DEMO_DEBUG_STATS 1
+
+/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets.
+The DMA uses a chain of descriptors to reference Ethernet buffers, and provide
+information on the state of each buffer (full/empty/error/etc.).
+configNUM_RX_ETHERNET_DMA_DESCRIPTORS defines the total number of receive
+descriptors (descriptors that point to buffers into which the DMA will write
+packets received from the network). An Ethernet buffer is assigned to each
+descriptor. Having too few descriptors will impact reliability because the DMA
+will have to drop packets that are received when there are no receive
+descriptors free. It is however only necessary to have a couple of free
+descriptors at a time, and having more wastes the RAM used by the Ethernet
+buffers that are surplus to requirements. */
+#define configNUM_RX_ETHERNET_DMA_DESCRIPTORS 4
+
+/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets.
+The DMA uses a chain of descriptors to reference Ethernet buffers that are
+waiting to be sent onto the network. configNUM_TX_ETHERNET_DMA_DESCRIPTORS
+defines the total number of transmit descriptors. An Ethernet buffer is
+not assigned to a transmit descriptor until data is actually sent, but will
+remain assigned to the descriptor until the descriptor is re-used. It is not
+necessary to have many transmit descriptors as the IP stack task will be held
+in the Blocked state (so other tasks can run) until a descriptor becomes
+available if it attempts to transmit when all the descriptors are in use. See
+the iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() IP trace macro. */
+#define configNUM_TX_ETHERNET_DMA_DESCRIPTORS 1
+
+/* The address of an echo server that will be used by the two demo echo client
+tasks.
+http://FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
+#define configECHO_SERVER_ADDR0 172
+#define configECHO_SERVER_ADDR1 25
+#define configECHO_SERVER_ADDR2 218
+#define configECHO_SERVER_ADDR3 103
+
+/* MAC address configuration. In a deployed production system this would
+probably be read from an EEPROM. In the demo it is just hard coded. Make sure
+each node on the network has a unique MAC address. */
+#define configMAC_ADDR0 0x00
+#define configMAC_ADDR1 0x01
+#define configMAC_ADDR2 0x02
+#define configMAC_ADDR3 0x03
+#define configMAC_ADDR4 0x04
+#define configMAC_ADDR5 0x08
+
+/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or
+ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
+#define configIP_ADDR0 172
+#define configIP_ADDR1 25
+#define configIP_ADDR2 218
+#define configIP_ADDR3 200
+
+/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to
+0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
+#define configGATEWAY_ADDR0 172
+#define configGATEWAY_ADDR1 25
+#define configGATEWAY_ADDR2 218
+#define configGATEWAY_ADDR3 1
+
+/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and
+208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set
+to 1 but a DNS server cannot be contacted.*/
+#define configDNS_SERVER_ADDR0 208
+#define configDNS_SERVER_ADDR1 67
+#define configDNS_SERVER_ADDR2 222
+#define configDNS_SERVER_ADDR3 222
+
+/* Defalt netmask configuration. Used in ipconfigUSE_DNS is set to 0, or
+ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
+#define configNET_MASK0 255
+#define configNET_MASK1 255
+#define configNET_MASK2 255
+#define configNET_MASK3 0
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ /* Only include the trace macro definitions required by FreeRTOS+Trace if
+ the trace start and trace stop CLI commands are included. */
+ #include "trcKernelPort.h"
+#endif
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h
new file mode 100644
index 0000000..2dd1ae1
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h
@@ -0,0 +1,233 @@
+/*
+ * FreeRTOS+UDP V1.0.1 (C) 2013 Real Time Engineers ltd.
+ * All rights reserved
+ *
+ * FreeRTOS+UDP is an add-on component to FreeRTOS. It is not, in itself, part
+ * of the FreeRTOS kernel. FreeRTOS+UDP is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS. FreeRTOS+UDP uses a dual license
+ * model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+UDP is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+UDP into
+ * proprietary software for redistribution in any form must first obtain a
+ * (very) low cost commercial license - and in-so-doing support the maintenance,
+ * support and further development of the FreeRTOS+UDP product. Commercial
+ * licenses can be obtained from http://shop.freertos.org and do not require any
+ * source files to be changed.
+ *
+ * FreeRTOS+UDP is distributed in the hope that it will be useful. You cannot
+ * use FreeRTOS+UDP unless you agree that you use the software 'as is'.
+ * FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied
+ * warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ * PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they
+ * implied, expressed, or statutory.
+ *
+ * 1 tab == 4 spaces!
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+/*****************************************************************************
+ *
+ * See the following URL for configuration information.
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml
+ *
+ *****************************************************************************/
+
+#ifndef FREERTOS_IP_CONFIG_H
+#define FREERTOS_IP_CONFIG_H
+
+/* The IP stack executes it its own task (although any application task can make
+use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY
+sets the priority of the task that executes the IP stack. The priority is a
+standard FreeRTOS task priority so can take any value from 0 (the lowest
+priority) to (configMAX_PRIORITIES - 1) (the highest priority).
+configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in
+FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to
+the priority assigned to the task executing the IP stack relative to the
+priority assigned to tasks that use the IP stack. */
+#define ipconfigUDP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
+
+/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP
+task. This setting is less important when the FreeRTOS Win32 simulator is used
+as the Win32 simulator only stores a fixed amount of information on the task
+stack. FreeRTOS includes optional stack overflow detection, see:
+http://www.freertos.org/Stacks-and-stack-overflow-checking.html */
+#define ipconfigUDP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 3 )
+
+/* ipconfigRAND32() is called by the IP stack to generate a random number that
+is then used as a DHCP transaction number. Random number generation is performed
+via this macro to allow applications to use their own random number generation
+method. For example, it might be possible to generate a random number by
+sampling noise on an analogue input. */
+#define ipconfigRAND32() 1
+
+/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the
+network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK
+is not set to 1 then the network event hook will never be called. See
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml
+*/
+#define ipconfigUSE_NETWORK_EVENT_HOOK 1
+
+/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but
+a network buffer cannot be obtained then the calling task is held in the Blocked
+state (so other tasks can continue to executed) until either a network buffer
+becomes available or the send block time expires. If the send block time expires
+then the send operation is aborted. The maximum allowable send block time is
+capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the
+maximum allowable send block time prevents prevents a deadlock occurring when
+all the network buffers are in use and the tasks that process (and subsequently
+free) the network buffers are themselves blocked waiting for a network buffer.
+ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in
+milliseconds can be converted to a time in ticks by dividing the time in
+milliseconds by portTICK_RATE_MS. */
+#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS )
+
+/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP
+address, netmask, DNS server address and gateway address from a DHCP server. If
+ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address. The
+stack will revert to using the static IP address even when ipconfigUSE_DHCP is
+set to 1 if a valid configuration cannot be obtained from a DHCP server for any
+reason. The static configuration used is that passed into the stack by the
+FreeRTOS_IPInit() function call. */
+#define ipconfigUSE_DHCP 1
+
+/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at
+increasing time intervals until either a reply is received from a DHCP server
+and accepted, or the interval between transmissions reaches
+ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the
+static IP address passed as a parameter to FreeRTOS_IPInit() if the
+re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without
+a DHCP reply being received. */
+#ifdef _WINDOWS_
+ /* The windows simulated time is not real time so the max delay is much
+ shorter. */
+ #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_RATE_MS )
+#else
+ #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_RATE_MS )
+#endif /* _WINDOWS_ */
+
+/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP
+stack can only send a UDP message to a remove IP address if it knowns the MAC
+address associated with the IP address, or the MAC address of the router used to
+contact the remote IP address. When a UDP message is received from a remote IP
+address the MAC address and IP address are added to the ARP cache. When a UDP
+message is sent to a remote IP address that does not already appear in the ARP
+cache then the UDP message is replaced by a ARP message that solicits the
+required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum
+number of entries that can exist in the ARP table at any one time. */
+#define ipconfigARP_CACHE_ENTRIES 6
+
+/* ARP requests that do not result in an ARP response will be re-transmitted a
+maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is
+aborted. */
+#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 )
+
+/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP
+table being created or refreshed and the entry being removed because it is stale.
+New ARP requests are sent for ARP cache entries that are nearing their maximum
+age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is
+equal to 1500 seconds (or 25 minutes). */
+#define ipconfigMAX_ARP_AGE 150
+
+/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling
+routines, which are relatively large. To save code space the full
+FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster
+alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr()
+takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter.
+FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets
+(for example, 192, 168, 0, 1) as its parameters. If
+ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and
+FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is
+not set to 1 then only FreeRTOS_indet_addr_quick() is available. */
+#define ipconfigINCLUDE_FULL_INET_ADDR 1
+
+/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that
+are available to the IP stack. The total number of network buffers is limited
+to ensure the total amount of RAM that can be consumed by the IP stack is capped
+to a pre-determinable value. */
+#define ipconfigNUM_NETWORK_BUFFERS 10
+
+/* A FreeRTOS queue is used to send events from application tasks to the IP
+stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can
+be queued for processing at any one time. The event queue must be a minimum of
+5 greater than the total number of network buffers. */
+#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 )
+
+/* The address of a socket is the combination of its IP address and its port
+number. FreeRTOS_bind() is used to manually allocate a port number to a socket
+(to 'bind' the socket to a port), but manual binding is not normally necessary
+for client sockets (those sockets that initiate outgoing connections rather than
+wait for incoming connections on a known port number). If
+ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling
+FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP
+stack automatically binding the socket to a port number from the range
+socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If
+ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto()
+on a socket that has not yet been bound will result in the send operation being
+aborted. */
+#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1
+
+/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */
+#define updconfigIP_TIME_TO_LIVE 128
+
+/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that
+contain more data than will fit in a single network frame will be fragmented
+across multiple IP packets. Also see the ipconfigNETWORK_MTU setting. If
+ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
+be divisible by 8. Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will
+increase both the code size and execution time. */
+#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0
+
+/* The MTU is the maximum number of bytes the payload of a network frame can
+contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a
+lower value can save RAM, depending on the buffer management scheme used. If
+ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
+be divisible by 8. */
+#define ipconfigNETWORK_MTU 586
+
+/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used
+through the FreeRTOS_gethostbyname() API function. */
+#define ipconfigUSE_DNS 1
+
+/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will
+generate replies to incoming ICMP echo (ping) requests. */
+#define ipconfigREPLY_TO_INCOMING_PINGS 1
+
+/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the
+FreeRTOS_SendPingRequest() API function is available. */
+#define ipconfigSUPPORT_OUTGOING_PINGS 1
+
+/* Used for stack testing only, and must be implemented in the network
+interface. */
+#define updconfigLOOPBACK_ETHERNET_PACKETS 0
+
+/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames
+that are not in Ethernet II format will be dropped. This option is included for
+potential future IP stack developments. */
+#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1
+
+/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the
+responsibility of the Ethernet interface to filter out packets that are of no
+interest. If the Ethernet interface does not implement this functionality, then
+set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack
+perform the filtering instead (it is much less efficient for the stack to do it
+because the packet will already have been passed into the stack). If the
+Ethernet driver does all the necessary filtering in hardware then software
+filtering can be removed by using a value other than 1 or 0. */
+#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 2
+
+/* The example IP trace macros are included here so the definitions are
+available in all the FreeRTOS+UDP source files. */
+#include "DemoIPTrace.h"
+
+#endif /* FREERTOS_IP_CONFIG_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c
new file mode 100644
index 0000000..833b159
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c
@@ -0,0 +1,137 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* Simple LED IO functions. LED 0 is toggled by a timer every half second. */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "timers.h"
+
+/* Library includes. */
+#include "lpc18xx_gpio.h"
+#include "lpc18xx_scu.h"
+#include "lpc18xx_cgu.h"
+
+#define ledTOGGLE_RATE ( 500 / portTICK_RATE_MS )
+
+#define ledLED0_PORT 1
+#define ledLED0_BIT ( 1UL << 11UL )
+
+#define ledLED1_PORT 2
+#define ledLED1_BIT ( 1UL << 12UL )
+
+/*
+ * Toggles an LED just to show the application is running.
+ */
+static void prvLEDToggleTimerCallback( xTimerHandle xTimer );
+
+/*-----------------------------------------------------------*/
+
+void vLEDsInitialise( void )
+{
+static xTimerHandle xLEDToggleTimer = NULL;
+
+ /* Set the LED pin-muxing and configure as output. */
+ scu_pinmux( 0x2 , 11, MD_PUP, FUNC0 );
+ scu_pinmux( 0x2 , 12, MD_PUP, FUNC0 );
+ GPIO_SetDir( ledLED0_PORT, ledLED0_BIT, 1 );
+ GPIO_SetDir( ledLED1_PORT, ledLED1_BIT, 1 );
+
+ /* Create the timer used to toggle LED0. */
+ xLEDToggleTimer = xTimerCreate( "LEDTmr", /* Just a text name to associate with the timer, useful for debugging, but not used by the kernel. */
+ ledTOGGLE_RATE, /* The period of the timer. */
+ pdTRUE, /* This timer will autoreload, so uxAutoReload is set to pdTRUE. */
+ NULL, /* The timer ID is not used, so can be set to NULL. */
+ prvLEDToggleTimerCallback ); /* The callback function executed each time the timer expires. */
+
+ /* Sanity check that the timer was actually created. */
+ configASSERT( xLEDToggleTimer );
+
+ /* Start the timer. If this is called before the scheduler is started then
+ the block time will automatically get changed to 0 (from portMAX_DELAY). */
+ xTimerStart( xLEDToggleTimer, portMAX_DELAY );
+}
+/*-----------------------------------------------------------*/
+
+static void prvLEDToggleTimerCallback( xTimerHandle xTimer )
+{
+static uint8_t ucState = 0;
+
+ /* Remove compiler warnings. */
+ ( void ) xTimer;
+
+ /* Just toggle an LED to show the program is running. */
+ if( ucState == 0 )
+ {
+ GPIO_SetValue( ledLED0_PORT, ledLED0_BIT );
+ }
+ else
+ {
+ GPIO_ClearValue( ledLED0_PORT, ledLED0_BIT );
+ }
+
+ ucState = !ucState;
+}
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt
new file mode 100644
index 0000000..4311d8b
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt
@@ -0,0 +1,11 @@
+This demo is documented on the following web page:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_and_CLI_LPC1830_NGX.shtml
+
+The FreeRTOS+UDP API is documented on the following web page:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml
+
+Other information, including a FreeRTOS+UDP primer, a description of the
+directory structure, and a glossary of networking terminology, can be found in
+the FreeRTOS+UDP portal:
+http://www.FreeRTOS.org/udp
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c
new file mode 100644
index 0000000..a01641f
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c
@@ -0,0 +1,136 @@
+/*
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* Utility functions to implement run time stats on Cortex-M CPUs. The collected
+run time data can be viewed through the CLI interface. See the following URL for
+more information on run time stats:
+http://www.freertos.org/rtos-run-time-stats.html */
+
+/* Addresses of registers in the Cortex-M debug hardware. */
+#define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) )
+#define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) )
+#define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) )
+#define rtsTRCENA_BIT ( 0x01000000UL )
+#define rtsCOUNTER_ENABLE_BIT ( 0x01UL )
+
+/* Simple shift divide for scaling to avoid an overflow occurring too soon. The
+number of bits to shift depends on the clock speed. */
+#define runtimeSLOWER_CLOCK_SPEEDS ( 70000000UL )
+#define runtimeSHIFT_13 13
+#define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) )
+#define runtimeSHIFT_14 14
+#define runtimeOVERFLOW_BIT_14 ( 1UL << ( 32UL - runtimeSHIFT_14 ) )
+
+/*-----------------------------------------------------------*/
+
+void vMainConfigureTimerForRunTimeStats( void )
+{
+ /* Enable TRCENA. */
+ rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
+
+ /* Reset counter. */
+ rtsDWT_CYCCNT = 0;
+
+ /* Enable counter. */
+ rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulMainGetRunTimeCounterValue( void )
+{
+static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
+unsigned long ulValueNow;
+
+ ulValueNow = rtsDWT_CYCCNT;
+
+ /* Has the value overflowed since it was last read. */
+ if( ulValueNow < ulLastCounterValue )
+ {
+ ulOverflows++;
+ }
+ ulLastCounterValue = ulValueNow;
+
+ /* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant
+ but instead map to a variable that holds the clock speed. */
+
+ /* There is no prescale on the counter, so simulate in software. */
+ if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS )
+ {
+ ulValueNow >>= runtimeSHIFT_13;
+ ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows );
+ }
+ else
+ {
+ ulValueNow >>= runtimeSHIFT_14;
+ ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows );
+ }
+
+ return ulValueNow;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100644
index 0000000..e04afae
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf
Binary files differ
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt
new file mode 100644
index 0000000..316499c
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt
@@ -0,0 +1,44 @@
+CMSIS : Cortex Microcontroller Software Interface Standard
+==========================================================
+
+Introduction
+~~~~~~~~~~~~
+CMSIS defines for a Cortex-M Microcontroller System:
+
+ * A common way to access peripheral registers and a
+ common way to define exception vectors.
+ * The register names of the Core Peripherals and the
+ names of the Core Exception Vectors.
+ * An device independent interface for RTOS Kernels
+ including a debug channel.
+
+By using CMSIS compliant software components, the user can
+easier re-use template code. CMSIS is intended to enable the
+combination of software components from multiple middleware
+vendors.
+
+This project contains appropriate files for this MCU family
+taken from CMSIS. A full copy of the CMSIS files, together
+with additional information on CMSIS can be found at:
+
+ http://www.onarm.com/
+ http://www.arm.com/
+
+Documentation
+~~~~~~~~~~~~~
+The standard CMSIS documentation can be found within the
+Code Red IDE help system, via:
+
+Help -> Help Contents -> Code Red Product Documentation -> CMSIS
+
+More information on the use of CMSIS within the Code Red IDE
+can be found in the Support area of the Code Red website at
+
+ http://www.code-red-tech.com/
+
+At the time of writing, the CMSIS FAQ can be found directly
+at:
+
+ http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt
new file mode 100644
index 0000000..b91c5ee
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt
@@ -0,0 +1,325 @@
+RELEASE CMSIS for REV A 20111209
+1/ New LPC18xx.h header file. Changes GPIO structure.
+2/ Addition of lpc18xx_emc.c and lpc18xx_emc.h to configure memory on Hitex board.
+3/ Addition of spifi_rom_api.h, spifi_drv_M3.lib and SPIFI_ROM_support.doc SPIFI driver package
+4/ Updated SPIFI programming driver for Keil MDK which uses the SPIFI lib
+5/ New BOOTFAST example shows how to boot from external flash or QSPI and ramp to 180 MHz
+
+RELEASE CMSIS for REV A 20111130
+1./ lpc18xx_lcd.h LCD_CFG_type add member pcd, lpc18xx_lcd.c add init pcd in LCD_Init function
+2./ protect MAX and MIN macro in lpc_types.h
+3./ Add getPC function to ARM,GNU, IAR startup_lpc18xx.s
+4./ Add VTOR init in SystemInit function
+5./ Change All ADC examples to use ADC port 0
+6./ These example: CortexM3_Mpu, Pwr_DeepPowerDown, Timer_FreqMeasure, SCT_SimpleMatch and all USBDEV_ROM examples Keil project was adjusted
+7./ SDRAM example and LCD example was changed not to use uint64_t in NS2CLK function
+8./ Nvic_VectorTableRelocation.c
+removed:
+#if __RAM_MODE__//Run in RAM mode
+ memcpy((void *)VTOR_OFFSET, (const void *)0x10000000, 256*4);
+#else
+ memcpy((void *)VTOR_OFFSET, (const void *)0x1C000000, 256*4);
+#endif
+
+added:
+memcpy((void *)VTOR_OFFSET, (const void *)(getPC()& 0xFF000000), 256*4);
+9./ Pwr_PowerDown change method for testing this feature
+
+
+RELEASE CMSIS for REV A 20111028
+1./ Add GNU support
+2./ Addition of new Keil flash drivers for eFlash and SPIFI
+3./ Change of Keil projects to support eFlash and SPIFI operation
+
+PRE-RELEASE CMSIS for REV A 20111011
+1/ PowerDown Example IAR issue fixed
+2/ Upgraded CMSIS to version 2.10
+3/ Upgraded Core header to Rev A
+4/ lpc18xx_can.h remove all bitrates from 8Mhz, add bitrates from 12Mhz
+ /** Bitrate: 100K */
+ #define CAN_BITRATE100K12MHZ 0x00004509
+ /** Bitrate: 125K */
+ #define CAN_BITRATE125K12MHZ 0x00004507
+ /** Bitrate: 250K */
+ #define CAN_BITRATE250K12MHZ 0x00004503
+ /** Bitrate: 500K */
+ #define CAN_BITRATE500K12MHZ 0x00004501
+ /** Bitrate: 1000K */
+ #define CAN_BITRATE1000K12MHZ 0x00004500
+5./ lpc18xx_cgu.* add PLL audio clock, modify alloc connect table and CGU_Entity_ControlReg_Offset
+6./ lpc18xx_evrt.h
+ add EVRT_SRC_SDIO
+7./ lpc18xx_i2s.h separate LPC_I2S0 and LPC_I2S1
+8./ lpc18xx_scu.h
+ redefine, add pin modes and add pin functions 4->7
+9./ debug_frmwrk.c
+ changed pin mode for UART RXD0 and UART RXD1
+10./ lpc_can.c replace LPC_CAN by LPC_CAN0
+11./ lpc18xx_i2c.* replace i2c pin configurations
+12./ lpc18xx_ssp.c down default clock speed to 100kHz
+13./ Examples\CCAN\CCan_SimpleTxRx\CCan_SimpleTxRx.c change RD pin mode to enable input buffer
+14./ Examples\EMAC\Emac_EasyWeb\emac.c
+ replace MII and RMII pin setting by source from CodeBundle
+15./ Examples\EMC\Emc_Sdram\SDRAM_Init.c and Examples\EMC\Emc_NorFlash\SST39VF320.c
+ replace EMC pin setting to be compatible with Rev A
+16./ Examples\I2S\I2s_Audio\I2s_Audio.c
+ replace I2S pin setting to be compatible with Rev A
+ replace I2S to I2S0
+17./ Examples\LCD\Lcd_Demo\IS42S16400D.c
+ replace EMC pin setting to be compatible with Rev A
+18./ Examples\SSP\All SSP examples: replace SSP pin setting to be compatible with Rev A
+19./ Timer_Capture and Timer_FreqMeasure: replace Capture input pin setting to be compatible with Rev A
+20./ Examples\UART\All UART examples: replace UART pin setting to be compatible with Rev A
+21./ Examples\USBDEV\USB_*\usbhw.c
+ replace USB pin setting to be compatible with Rev A
+ correct clock in Init function
+
+RELEASE: LPC1800CMSIS_20110829
+1./ Add GNU Support
+modify pasting in can.c to be compatible with GCC
+
+RELEASE: LPC1800CMSIS_20110729
+1./ IAR flash support is moved to Tools folder
+2./ ADC.h fixed macro ADC_CR_BITACC
+3./ I2S.h fixed comment
+ from #endif /* LPC17XX_SSP_H_ */
+ to #endif /* LPC18XX_I2S_H_ */
+4./ ADC.c fix ADC_Init Clock by rounding clk div value
+5./ i2s.c fixed some comment
+6./ EMC Nor Flash renamed file flash programing function
+7./ SDRAM can run at MAX EMC Speed
+8./ Removed flash programing support for LHF00L28
+
+RELEASE: LPC1800CMSIS_20110627
+1./ Fix abstract
+2./ Fix I2S FreqConfig mistake
+3./ Add DFU Driver and App
+
+
+RELEASE: LPC1800CMSIS_20110613
+1./ Add DSP Document
+2./ Speed Up External FLash Mode
+3./ Add IAR Flash Support
+4./ Fix GPDMA Flash transfer issue in IAR
+5./ Set default taget is EXFLASH(Keil only)
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110603
+1./ Add DSP_lib into Core folder
+2./ Update core_cmFunc.h and core_cmInstr.h for solving conflict with IAR EWARM version 6.20 or later
+3./ add IAR startup file and IAR support files in Core\DeviceSupport\NXP\LPC18xx
+4./ Modify SystemInit function to support RAM mode
+ #if (__RAM_MODE__)
+ SCB->VTOR = 0x10000000;
+ #endif
+5./ Modify CCU1 and CCU2 struct in LPC18xx.h
+6./ Fix bug in uart_set_divisors function
+7./ Change UART clock source from XTAL to PLL1 in uart driver
+8./ Fix RTC bugs
+9./ Modify lpc18xx_GPDMA.c to support IAR compiler
+10./ Modify lpc18xx_cgu.c to support IAR compiler
+11./ Update lpc_types.h to support IAR compiler
+12./ Fix bugs in I2S driver
+13./ Remove Warnings
+14./ Change new header, add more comments
+15./ Standalize example, project, output names
+16./ Support IAR EWARM (RAM mode)
+17./ SUpport Hitex Board as default
+18./ Modify hardware configuration in abstract files
+19./ Set default Target to RAM mode
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110514
+1./ Change all Keil example projects from device Cortex M3 to LPC1850
+2./ change all examples to support Hitex board only
+3./ Verify all project option
+4./ separated CGU and PWR into 2 independent drivers
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110421
+1./ Add CAN driver:
+ Drivers/include/lpc18xx_can.h
+ Drivers/source/lpc18xx_can.c
+
+2./ Add CAN example for simple Transceiver
+ Examples\C_CAN\simpleTxRx
+
+3./ Add 4 USB Rom examples:
+ USB_DFU
+ USB_HID
+ USB_MassStorage
+ USB_Composite
+
+4./ Enable _printf function
+ debug_frmwrk.h:
+ uncomment _printf function declaration
+ debug_frmwrk.c:
+ uncomment _printf function
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110401
+
+1./ Change all Keil example proiects from device NXP LPC1768 to ARM Cortex-M3
+
+2./ Fix bug in I2C driver (customer feedback)
+ Problem description:
+ I2C_MasterTransferData() is not able to
+ (1) Send,
+ (2) doing a repeated Start and
+ (3) starting to receive with one function call.
+ Problem is that the repeated start is not generated, but a retransmission of the
+ last word is startet.
+ Solve: change
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ I2Cx->I2CONSET = I2C_I2CONSET_STA;
+ to
+ I2Cx->I2CONSET = I2C_I2CONSET_STA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ in function I2C_Start ()
+
+3./ lpc18xx_timer.c:
+ Function TIM_ClearIntPending():
+ Change TIMx->IR |= TIM_IR_CLR(IntFlag);
+ To TIMx->IR = TIM_IR_CLR(IntFlag);
+ Function TIM_ClearIntCapturePending():
+ Change TIMx->IR |= (1<<(4+IntFlag));
+ To TIMx->IR = (1<<(4+IntFlag));
+ Function TIM_GetCaptureValue():
+ Add return 0;
+
+4./ EMC - Nor Flash: remove example build target for FLASH mode as it only can run in RAM mode.
+
+5./ SCT: update Fizzim tool to version 1.1
+
+6./ Tools:
+ Update Flash burning for LHF00L28 and SST39X320X
+
+************************************************************************************************************************************************
+
+RELEASE: LPC1800CMSIS_20110324
+
+1./ Current support hardwares:
+ - NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'
+ - Hitex LPC1800 Board through definition 'BOARD_HITEX_LPC1800'
+ Some examples can run on LPC1800 Evaluation board, some can run on Hitex board...Please refer to abstract.txt
+
+2./ Addin new flash support under Tools/Flash/SST39X320X
+
+3./ lpc18xx_evrt.c:
+ Change EVRTx->SET_EN |= (1<<(uint8_t)EVRT_Src);
+ To EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src);
+ Purpose: prevent clearing other set bits as writing '0' has no effect
+
+4./ Fix ATIMER_WIC example:
+ - Configure 32KHZ osc in lpc18xx_atimer.c
+ - Call the configuration function in atimer_wic.c
+
+5./ Fix RTC_Alarm example:
+ - Configure 32KHZ osc in lpc18xx_rtc.c
+ - Update Rtc_Alarm.c
+
+6./ Add in PWR_PowerDown example
+
+7./ Add in PWR_DeepPowerDown example
+
+8./ All example in PWR are modified to wait for '1' sent from PC's COM port to start
+
+9./ Fix LCD Logic4.3 example to run on Hitex LPC1800 Board
+
+10./ Add in GPDMA Flash_2_Ram_Test example
+
+11./ EMC EXT_SDRAM example: join IS42S16400D.c and MT48LC4M32B2.c into SDRAM_Init.c
+
+12./ lpc18xx_i2s.c: update I2S_FreqConfig() function
+
+************************************************************************************************************************************************
+
+RELEASE: LPC1800CMSIS_20110311
+
+1./ This package is compliant to CMSIS 2.0
+
+2./ Add in 'Tools' folder which contains neccessary material for building project, examples like flash burning,..
+
+3./ Examples are given in Keil uVision 4 project
+
+4./ Current support hardwares:
+ - NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'
+
+5./ Examples can run:
+ - RAM (debug) mode
+ - ROM (Flash, stand alone) mode
+ + External Nor Flash. Flash Part supporting:
+ 1) LHF00L28
+
+6./ Each example folder has an 'abstract.txt' file, this is where user can start
+
+7./ Below is list of drivers and examples:
+ - ADC (lpc18xx_adc):
+ + ADC_Interrupt
+ + ADC_Polling
+ + ADC_Burst
+ + ADC_Dma
+ - ATIMER (lpc18xx_atimer):
+ + ATIMER_interrupt
+ - PWR (lpc18xx_clkpwr):
+ + CLKPWR_Sleep
+ + CLKPWR_DeepSleep
+ - DAC (lpc18xx_dac):
+ + DAC_WaveGenerator
+ + DAC_Dma
+ - EMAC (lpc18xx_emac):
+ + EMAC_EasyWeb
+ - EMC (no driver):
+ + EXT_SDRAM
+ + NOR_FLASH
+ - GPDMA (lpc18xx_gpdma):
+ + GPDMA_Ram2Ram
+ + GPDMA_LinkList
+ - GPIO (lpc18xx_gpio):
+ + GPIO_LedBlinky
+ - I2C (lpc18xx_i2c):
+ + I2C_Master
+ - I2S (lpc18xx_i2s):
+ + I2S_Audio
+ - LCD (lpc18xx_lcd)
+ - MCPWM (lpc18xx_mcpwm):
+ + MCPWM_Simple
+ - SCU (lpc18xx_scu)
+ - QEI (lpc18xx_qei):
+ + QEI_Velo
+ - RIT (lpc18xx_rit):
+ + RIT_Interrupt
+ - RTC (lpc18xx_rtc):
+ + RTC_Calib
+ + RTC_Alarm
+ - SSP (lpc18xx_ssp):
+ + SSP_SPI
+ + SSP_Microwire
+ + SSP_TI
+ - TIMER (lpc18xx_timer):
+ + TIMER_Capture
+ + TIMER_MatchInterrupt
+ + TIMER_FreqMeasure
+ - UART (lpc18xx_uart):
+ + UART_Autobaud
+ + UART_Dma
+ + UART_Interrupt
+ + UART_Polling
+ + UART_RS485
+ - SCT(LPC18xx_SCT):
+ + SCT_Capture
+ + SCT_Match
+ - WWDT (lpc18xx_wwdt):
+ + WWDT_Interrupt
+ - CORTEXM3 (no driver):
+ + CORTEXM3_BitBanding
+ + CORTEXM3_MPU
+ + CORTEXM3_PriviledgeMode
+ - USBDEV (no driver):
+ + USBDEV_VirtualCOM
+ + USBDEV_MassStorage
+ - NVIC (no driver):
+ + NVIC_Priority
+ + NVIC_VecRelocation
+ - EVRT (lpc18xx_evrt)
+
\ No newline at end of file
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt
new file mode 100644
index 0000000..cc002c2
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt
@@ -0,0 +1,9 @@
+NXP's documentation for their peripheral driver library can be found
+as a Microsoft Compiled HTML Help file (.chm) within the LPC18xx
+CMSIS Standard Peripheral Driver Library download on NXP's website.
+
+At the time of writing, this can be found at the following link:
+
+http://lpcware.com/file_filter/nxp?term_node_tid_depth=All&term_node_tid_depth_1=103
+
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h
new file mode 100644
index 0000000..32fbff3
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h
@@ -0,0 +1,32280 @@
+
+/****************************************************************************************************//**
+ * @file LPC18xx.h
+ *
+ * @status EXPERIMENTAL
+ *
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * default LPC18xx Device Series
+ *
+ * @version V18
+ * @date 1. December 2011
+ *
+ * @note Generated with SVDConv V2.6 Build 6c on Thursday, 01.12.2011 08:48:39
+ *
+ * from CMSIS SVD File 'LPC18xxv18.xml' Version 18,
+ * created on Tuesday, 22.11.2011 18:06:23, last modified on Tuesday, 22.11.2011 18:38:38
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC18xx
+ * @{
+ */
+
+#ifndef __LPC18XX_H__
+#define __LPC18XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/********************************************
+** Start of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma push
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC18xx Specific Interrupt Numbers -------------------------------
+ DAC_IRQn = 0, /*!< 0 DAC */
+ RESERVED0_IRQn = 1, /*!< 1 M0a */
+ DMA_IRQn = 2, /*!< 2 DMA */
+ RESERVED1_IRQn = 3, /*!< 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5, /*!< 5 ETHERNET */
+ SDIO_IRQn = 6, /*!< 6 SDIO */
+ LCD_IRQn = 7, /*!< 7 LCD */
+ USB0_IRQn = 8, /*!< 8 USB0 */
+ USB1_IRQn = 9, /*!< 9 USB1 */
+ SCT_IRQn = 10, /*!< 10 SCT */
+ RITIMER_IRQn = 11, /*!< 11 RITIMER */
+ TIMER0_IRQn = 12, /*!< 12 TIMER0 */
+ TIMER1_IRQn = 13, /*!< 13 TIMER1 */
+ TIMER2_IRQn = 14, /*!< 14 TIMER2 */
+ TIMER3_IRQn = 15, /*!< 15 TIMER3 */
+ MCPWM_IRQn = 16, /*!< 16 MCPWM */
+ ADC0_IRQn = 17, /*!< 17 ADC0 */
+ I2C0_IRQn = 18, /*!< 18 I2C0 */
+ I2C1_IRQn = 19, /*!< 19 I2C1 */
+ RESERVED3_IRQn = 20,
+ ADC1_IRQn = 21, /*!< 21 ADC1 */
+ SSP0_IRQn = 22, /*!< 22 SSP0 */
+ SSP1_IRQn = 23, /*!< 23 SSP1 */
+ USART0_IRQn = 24, /*!< 24 USART0 */
+ UART1_IRQn = 25, /*!< 25 UART1 */
+ USART2_IRQn = 26, /*!< 26 USART2 */
+ USART3_IRQn = 27, /*!< 27 USART3 */
+ I2S0_IRQn = 28, /*!< 28 I2S0 */
+ I2S1_IRQn = 29, /*!< 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ RESERVED5_IRQn = 31,
+ PIN_INT0_IRQn = 32, /*!< 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33, /*!< 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34, /*!< 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35, /*!< 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36, /*!< 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37, /*!< 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38, /*!< 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39, /*!< 39 PIN_INT7 */
+ GINT0_IRQn = 40, /*!< 40 GINT0 */
+ GINT1_IRQn = 41, /*!< 41 GINT1 */
+ EVENTROUTER_IRQn = 42, /*!< 42 EVENTROUTER */
+ C_CAN1_IRQn = 43, /*!< 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45, /*!< 45 VADC */
+ ATIMER_IRQn = 46, /*!< 46 ATIMER */
+ RTC_IRQn = 47, /*!< 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49, /*!< 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51, /*!< 51 C_CAN0 */
+ QEI_IRQn = 52, /*!< 52 QEI */
+} IRQn_Type;
+
+ /* Event Router Input (ERI) Number Definitions */
+typedef enum {
+ WAKEUP0_ERIn = 0,
+ WAKEUP1_ERIn = 1,
+ WAKEUP2_ERIn = 2,
+ WAKEUP3_ERIn = 3,
+ ATIMER_ERIn = 4,
+ RTC_ERIn = 5,
+ BOD1_ERIn = 6, /* Bod trip 1 */
+ WWDT_ERIn = 7,
+ ETH_ERIn = 8,
+ USB0_ERIn = 9,
+ USB1_ERIn = 10,
+ SDIO_ERIn = 11,
+ CAN_ERIn = 12, /* CAN0/1 or'ed */
+ TIM2_ERIn = 13,
+ TIM6_ERIn = 14,
+ QEI_ERIn = 15,
+ TIM14_ERIn = 16,
+ RESERVED0_ERIn = 17, /* M0s */
+ RESERVED1_ERIn = 18, /* M3/M4 */
+ RESET_ERIn = 19
+}ERIn_Type;
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Template Processor and Core Peripherals */
+
+#define __CM3_REV 0x0101 /*!< Cortex-M3 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
+//#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
+
+#include "system_LPC18xx.h" /*!< LPC18xx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SCT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
+ */
+
+#define CONFIG_SCT_nEV (16) /* Number of events */
+#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (16) /* Number of outputs */
+
+typedef struct
+{
+ __IO uint32_t CONFIG; /* 0x000 Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* 0x004 Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* 0x004 low control register */
+ __IO uint16_t CTRL_H; /* 0x006 high control register */
+ };
+ };
+ __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
+ __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
+ __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
+ __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
+ __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
+ __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
+ __IO uint16_t START_L; /* 0x014 start register for counter L */
+ __IO uint16_t START_H; /* 0x016 start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* 0x040 counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
+ __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
+ };
+ };
+ __IO uint16_t STATE_L; /* 0x044 state register for counter L */
+ __IO uint16_t STATE_H; /* 0x046 state register for counter H */
+ __I uint32_t INPUT; /* 0x048 input register */
+ __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* 0x050 output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
+ __IO uint32_t RES; /* 0x058 conflict resolution register */
+ __IO uint32_t DMA0REQUEST; /* 0x05C DMA0 Request Register */
+ __IO uint32_t DMA1REQUEST; /* 0x060 DMA1 Request Register */
+ uint32_t RESERVED2[35]; /* 0x064-0x0EC reserved */
+ __IO uint32_t EVEN; /* 0x0F0 event enable register */
+ __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
+ __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
+ __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
+
+ union {
+ __IO union { /* 0x100-... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+ } MATCH[CONFIG_SCT_nRG];
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to H value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+ } CAP[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+ uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+ uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+ } MATCHREL[CONFIG_SCT_nRG];
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+ } CAPCTRL[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+ uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+ uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+
+} LPC_SCT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPDMA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (GPDMA)
+ */
+
+typedef struct { /*!< (@ 0x40002000) GPDMA Structure */
+ __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */
+ __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */
+ __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */
+ __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */
+ __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */
+ __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */
+ __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */
+ __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */
+ __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */
+ __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */
+ __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */
+ __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */
+ __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */
+ __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */
+ __I uint32_t RESERVED0[50];
+ __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */
+ __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */
+ __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */
+ __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */
+ __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */
+ __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */
+ __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */
+ __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */
+ __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */
+ __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */
+ __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */
+ __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */
+ __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */
+ __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */
+ __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */
+ __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */
+ __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */
+ __I uint32_t RESERVED4[3];
+ __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */
+ __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */
+ __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */
+ __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */
+ __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */
+ __I uint32_t RESERVED5[3];
+ __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */
+ __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */
+ __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */
+ __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */
+ __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */
+ __I uint32_t RESERVED6[3];
+ __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */
+ __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */
+ __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */
+ __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */
+ __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */
+ __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */
+ __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */
+ __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */
+ __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */
+} LPC_GPDMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SDMMC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a (SDMMC)
+ */
+
+typedef struct { /*!< (@ 0x40004000) SDMMC Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */
+ __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */
+ __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */
+ __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */
+ __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */
+ __IO uint32_t TMOUT; /*!< (@ 0x40004014) Timeout Register */
+ __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */
+ __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */
+ __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */
+ __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */
+ __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */
+ __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */
+ __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */
+ __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */
+ __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */
+ __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */
+ __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */
+ __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */
+ __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */
+ __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */
+ __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */
+ __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */
+ __IO uint32_t GPIO; /*!< (@ 0x40004058) General Purpose Input/Output Register */
+ __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */
+ __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */
+ __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */
+ __IO uint32_t USRID; /*!< (@ 0x40004068) User ID Register */
+ __I uint32_t VERID; /*!< (@ 0x4000406C) Version ID Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t UHS_REG; /*!< (@ 0x40004074) UHS-1 Register */
+ __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */
+ __I uint32_t RESERVED1;
+ __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */
+ __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */
+ __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */
+ __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */
+ __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */
+ __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */
+ __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */
+} LPC_SDMMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EMC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7 (EMC)
+ */
+
+typedef struct { /*!< (@ 0x40005000) EMC Structure */
+ __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */
+ __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */
+ __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */
+ __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */
+ __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */
+ __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */
+ __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */
+ __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */
+ __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */
+ __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */
+ __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */
+ __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */
+ __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */
+ __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */
+ __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */
+ __I uint32_t RESERVED2[9];
+ __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED5[6];
+ __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED7[38];
+ __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects bus turnaround cycles */
+ __I uint32_t RESERVED8;
+ __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects bus turnaround cycles */
+ __I uint32_t RESERVED9;
+ __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects bus turnaround cycles */
+ __I uint32_t RESERVED10;
+ __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects bus turnaround cycles */
+} LPC_EMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB0)
+ */
+
+typedef struct { /*!< (@ 0x40006000) USB0 Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */
+ __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */
+ __I uint32_t RESERVED2[7];
+
+ union {
+ __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */
+ __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */
+ __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */
+ };
+
+ union {
+ __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */
+ __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */
+ };
+ __I uint32_t RESERVED3;
+
+ union {
+ __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */
+ __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */
+ };
+
+ union {
+ __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */
+ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */
+ };
+ __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[3];
+ __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+
+ union {
+ __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */
+ };
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */
+
+ union {
+ __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */
+ };
+ __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */
+ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */
+ __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */
+ __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */
+ __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */
+ __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */
+ __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */
+} LPC_USB0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB1)
+ */
+
+typedef struct { /*!< (@ 0x40007000) USB1 Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */
+ __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */
+ __I uint32_t RESERVED2[7];
+
+ union {
+ __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */
+ __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */
+ __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */
+ };
+
+ union {
+ __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */
+ __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */
+ };
+ __I uint32_t RESERVED3;
+
+ union {
+ __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */
+ __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */
+ };
+
+ union {
+ __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */
+ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */
+ };
+ __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */
+ __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+
+ union {
+ __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */
+ };
+ __I uint32_t RESERVED6[8];
+
+ union {
+ __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */
+ };
+ __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */
+ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */
+ __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */
+ __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */
+ __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */
+} LPC_USB1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- LCD -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7 (LCD)
+ */
+
+typedef struct { /*!< (@ 0x40008000) LCD Structure */
+ __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */
+ __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */
+ __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */
+ __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */
+ __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */
+ __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */
+ __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */
+ __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */
+ __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */
+ __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */
+ __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */
+ __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */
+ __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */
+ __I uint32_t RESERVED0[115];
+ __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */
+ __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */
+ __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */
+ __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */
+ __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */
+ __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */
+ __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */
+ __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */
+ __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */
+ __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */
+} LPC_LCD_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ETHERNET -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=1/20/2011 Major revision=0 Minor revision=7 (ETHERNET)
+ */
+
+typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */
+ __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */
+ __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */
+ __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */
+ __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */
+ __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */
+ __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */
+ __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */
+ __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */
+ __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */
+ __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */
+ __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */
+ __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */
+ __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */
+ __I uint32_t RESERVED2[430];
+ __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */
+ __I uint32_t RESERVED3[575];
+ __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */
+ __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */
+ __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */
+ __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */
+ __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */
+ __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */
+ __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */
+ __IO uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */
+ __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */
+ __I uint32_t RESERVED4[8];
+ __IO uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */
+ __IO uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */
+ __IO uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */
+ __IO uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */
+} LPC_ETHERNET_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ATIMER -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6 (ATIMER)
+ */
+
+typedef struct { /*!< (@ 0x40040000) ATIMER Structure */
+ __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */
+ __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */
+ __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */
+ __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */
+ __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */
+ __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */
+ __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */
+} LPC_ATIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- REGFILE -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7 (REGFILE)
+ */
+
+typedef struct { /*!< (@ 0x40041000) REGFILE Structure */
+ __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */
+} LPC_REGFILE_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (PMC)
+ */
+
+typedef struct { /*!< (@ 0x40042000) PMC Structure */
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */
+} LPC_PMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CREG -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Configuration Registers (CREG) Modification date=8/19/2011 Major revision=0 Minor revision=14 (CREG)
+ */
+
+typedef struct { /*!< (@ 0x40043000) CREG Structure */
+ __I uint32_t IRCTRM; /*!< (@ 0x40043000) IRC trim register */
+ __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */
+ __IO uint32_t PMUCON; /*!< (@ 0x40043008) Power mode control register. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t M3MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M3 memory mapping */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */
+ __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA muxing control */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */
+ __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6 */
+ __I uint32_t RESERVED3[52];
+ __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */
+} LPC_CREG_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EVENTROUTER -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Event router Modification date=1/20/2011 Major revision=0 Minor revision=7 (EVENTROUTER)
+ */
+
+typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */
+ __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */
+ __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Event clear enable register */
+ __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Event set enable register */
+ __I uint32_t STATUS; /*!< (@ 0x40044FE0) Status register */
+ __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Enable register */
+ __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear register */
+ __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set register */
+} LPC_EVENTROUTER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RTC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (RTC)
+ */
+
+typedef struct { /*!< (@ 0x40046000) RTC Structure */
+ __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */
+ __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */
+ __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */
+ __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */
+ __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */
+ __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */
+ __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */
+ __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */
+ __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */
+ __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */
+ __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */
+ __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */
+ __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */
+ __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */
+ __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */
+ __I uint32_t RESERVED1[7];
+ __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */
+ __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */
+ __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */
+ __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */
+ __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */
+ __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */
+ __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */
+ __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */
+} LPC_RTC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CGU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1 (CGU)
+ */
+
+typedef struct { /*!< (@ 0x40050000) CGU Structure */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */
+ __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */
+ __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */
+ __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */
+ __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+ __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+ __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */
+ __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */
+ __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+ __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+ __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */
+ __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */
+ __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */
+ __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */
+ __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */
+ __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */
+ __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */
+ __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */
+ __IO uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */
+ __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */
+ __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */
+ __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */
+ __IO uint32_t BASE_M3_CLK; /*!< (@ 0x4005006C) Output stage control register */
+ __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage control register */
+ __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage control register */
+ __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage control register */
+ __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage control register */
+ __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage control register */
+ __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage control register */
+ __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage control register */
+ __IO uint32_t RESERVED2;
+ __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage control register */
+ __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage control register */
+ __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage control register */
+ __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage control register */
+ __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage control register */
+ __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage control register */
+ __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage control register */
+ __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */
+ __I uint32_t RESERVED3[4];
+ __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */
+ __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 26 control register for base clock BASE_CGU_OUT0_CLK */
+ __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 27 control register for base clock BASE_CGU_OUT1_CLK */
+} LPC_CGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU1)
+ */
+
+typedef struct { /*!< (@ 0x40051000) CCU1 Structure */
+ __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */
+ __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */
+ __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */
+ __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */
+ __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */
+ __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */
+ __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */
+ __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */
+ __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */
+ __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */
+ __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */
+ __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */
+ __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */
+ __I uint32_t RESERVED1[52];
+ __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */
+ __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */
+ __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */
+ __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */
+ __IO uint32_t CLK_ABP1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */
+ __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */
+ __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */
+ __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */
+ __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */
+ __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */
+ __I uint32_t RESERVED2[54];
+ __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */
+ __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */
+ __I uint32_t RESERVED3[62];
+ __IO uint32_t CLK_M3_BUS_CFG; /*!< (@ 0x40051400) CLK_M3_BUS clock configuration register */
+ __I uint32_t CLK_M3_BUS_STAT; /*!< (@ 0x40051404) CLK_M3_BUSclock status register */
+ __IO uint32_t CLK_M3_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M3_SPIFI clock configuration register */
+ __I uint32_t CLK_M3_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M3_SPIFI clock status register */
+ __IO uint32_t CLK_M3_GPIO_CFG; /*!< (@ 0x40051410) CLK_M3_GPIO clock configuration register */
+ __I uint32_t CLK_M3_GPIO_STAT; /*!< (@ 0x40051414) CLK_M3_GPIO clock status register */
+ __IO uint32_t CLK_M3_LCD_CFG; /*!< (@ 0x40051418) CLK_M3_LCD clock configuration register */
+ __I uint32_t CLK_M3_LCD_STAT; /*!< (@ 0x4005141C) CLK_M3_LCD clock status register */
+ __IO uint32_t CLK_M3_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M3_ETHERNET clock configuration register */
+ __I uint32_t CLK_M3_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M3_ETHERNET clock status register */
+ __IO uint32_t CLK_M3_USB0_CFG; /*!< (@ 0x40051428) CLK_M3_USB0 clock configuration register */
+ __I uint32_t CLK_M3_USB0_STAT; /*!< (@ 0x4005142C) CLK_M3_USB0 clock status register */
+ __IO uint32_t CLK_M3_EMC_CFG; /*!< (@ 0x40051430) CLK_M3_EMC clock configuration register */
+ __I uint32_t CLK_M3_EMC_STAT; /*!< (@ 0x40051434) CLK_M3_EMC clock status register */
+ __IO uint32_t CLK_M3_SDIO_CFG; /*!< (@ 0x40051438) CLK_M3_SDIO clock configuration register */
+ __I uint32_t CLK_M3_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M3_SDIO clock status register */
+ __IO uint32_t CLK_M3_DMA_CFG; /*!< (@ 0x40051440) CLK_M3_DMA clock configuration register */
+ __I uint32_t CLK_M3_DMA_STAT; /*!< (@ 0x40051444) CLK_M3_DMA clock status register */
+ __IO uint32_t CLK_M3_M3CORE_CFG; /*!< (@ 0x40051448) CLK_M3_M3CORE clock configuration register */
+ __I uint32_t CLK_M3_M3CORE_STAT; /*!< (@ 0x4005144C) CLK_M3_M3CORE clock status register */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t CLK_M3_SCT_CFG; /*!< (@ 0x40051468) CLK_M3_SCT clock configuration register */
+ __I uint32_t CLK_M3_SCT_STAT; /*!< (@ 0x4005146C) CLK_M3_SCT clock status register */
+ __IO uint32_t CLK_M3_USB1_CFG; /*!< (@ 0x40051470) CLK_M3_USB1 clock configuration register */
+ __I uint32_t CLK_M3_USB1_STAT; /*!< (@ 0x40051474) CLK_M3_USB1 clock status register */
+ __IO uint32_t CLK_M3_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M3_EMCDIV clock configuration register */
+ __I uint32_t CLK_M3_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M3_EMCDIV clock status register */
+ __I uint32_t RESERVED5[32];
+ __IO uint32_t CLK_M3_WWDT_CFG; /*!< (@ 0x40051500) CLK_M3_WWDT clock configuration register */
+ __I uint32_t CLK_M3_WWDT_STAT; /*!< (@ 0x40051504) CLK_M3_WWDT clock status register */
+ __IO uint32_t CLK_M3_USART0_CFG; /*!< (@ 0x40051508) CLK_M3_USART0 clock configuration register */
+ __I uint32_t CLK_M3_USART0_STAT; /*!< (@ 0x4005150C) CLK_M3_USART0 clock status register */
+ __IO uint32_t CLK_M3_UART1_CFG; /*!< (@ 0x40051510) CLK_M3_UART1 clock configuration register */
+ __I uint32_t CLK_M3_UART1_STAT; /*!< (@ 0x40051514) CLK_M3_UART1 clock status register */
+ __IO uint32_t CLK_M3_SSP0_CFG; /*!< (@ 0x40051518) CLK_M3_SSP0 clock configuration register */
+ __I uint32_t CLK_M3_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M3_SSP0 clock status register */
+ __IO uint32_t CLK_M3_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M3_TIMER0 clock configuration register */
+ __I uint32_t CLK_M3_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M3_TIMER0 clock status register */
+ __IO uint32_t CLK_M3_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M3_TIMER1clock configuration register */
+ __I uint32_t CLK_M3_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M3_TIMER1 clock status register */
+ __IO uint32_t CLK_M3_SCU_CFG; /*!< (@ 0x40051530) CLK_M3_SCU clock configuration register */
+ __I uint32_t CLK_M3_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */
+ __IO uint32_t CLK_M3_CREG_CFG; /*!< (@ 0x40051538) CLK_M3_CREGclock configuration register */
+ __I uint32_t CLK_M3_CREG_STAT; /*!< (@ 0x4005153C) CLK_M3_CREG clock status register */
+ __I uint32_t RESERVED6[48];
+ __IO uint32_t CLK_M3_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M3_RITIMER clock configuration register */
+ __I uint32_t CLK_M3_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M3_RITIMER clock status register */
+ __IO uint32_t CLK_M3_USART2_CFG; /*!< (@ 0x40051608) CLK_M3_USART2 clock configuration register */
+ __I uint32_t CLK_M3_USART2_STAT; /*!< (@ 0x4005160C) CLK_M3_USART2 clock status register */
+ __IO uint32_t CLK_M3_USART3_CFG; /*!< (@ 0x40051610) CLK_M3_USART3 clock configuration register */
+ __I uint32_t CLK_M3_USART3_STAT; /*!< (@ 0x40051614) CLK_M3_USART3 clock status register */
+ __IO uint32_t CLK_M3_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M3_TIMER2 clock configuration register */
+ __I uint32_t CLK_M3_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M3_TIMER2 clock status register */
+ __IO uint32_t CLK_M3_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M3_TIMER3 clock configuration register */
+ __I uint32_t CLK_M3_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M3_TIMER3 clock status register */
+ __IO uint32_t CLK_M3_SSP1_CFG; /*!< (@ 0x40051628) CLK_M3_SSP1 clock configuration register */
+ __I uint32_t CLK_M3_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M3_SSP1 clock status register */
+ __IO uint32_t CLK_M3_QEI_CFG; /*!< (@ 0x40051630) CLK_M3_QEIclock configuration register */
+ __I uint32_t CLK_M3_QEI_STAT; /*!< (@ 0x40051634) CLK_M3_QEI clock status register */
+ __I uint32_t RESERVED7[114];
+ __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M3_USB0 clock configuration register */
+ __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */
+ __I uint32_t RESERVED8[62];
+ __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */
+ __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */
+ __I uint32_t RESERVED9[126];
+ __IO uint32_t CLK_VADC_CFG; /*!< (@ 0x40051B00) CLK_VADC clock configuration register */
+ __I uint32_t CLK_VADC_STAT; /*!< (@ 0x40051B04) CLK_VADC clock status register */
+} LPC_CCU1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU2 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU2)
+ */
+
+typedef struct { /*!< (@ 0x40052000) CCU2 Structure */
+ __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */
+ __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t CLK_APLL_CFG; /*!< (@ 0x40052100) CLK_APLL clock configuration register */
+ __I uint32_t CLK_APLL_STAT; /*!< (@ 0x40052104) CLK_APLL clock status register */
+ __I uint32_t RESERVED1[62];
+ __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */
+ __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */
+ __I uint32_t RESERVED2[62];
+ __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */
+ __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */
+ __I uint32_t RESERVED3[62];
+ __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */
+ __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */
+ __I uint32_t RESERVED4[62];
+ __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */
+ __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */
+ __I uint32_t RESERVED5[62];
+ __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */
+ __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */
+ __I uint32_t RESERVED6[62];
+ __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */
+ __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */
+ __I uint32_t RESERVED7[62];
+ __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */
+ __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */
+} LPC_CCU2_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RGU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13 (RGU)
+ */
+
+typedef struct { /*!< (@ 0x40053000) RGU Structure */
+ __I uint32_t RESERVED0[64];
+ __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */
+ __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */
+ __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */
+ __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */
+ __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */
+ __I uint32_t RESERVED2[12];
+ __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */
+ __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */
+ __I uint32_t RESERVED3[170];
+ __IO uint32_t RESET_EXT_STAT0; /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */
+ __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */
+ __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */
+ __I uint32_t RESERVED4;
+ __IO uint32_t RESET_EXT_STAT4; /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */
+ __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */
+ __I uint32_t RESERVED5[2];
+ __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */
+ __I uint32_t RESERVED6[3];
+ __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */
+ __I uint32_t RESERVED7[2];
+ __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT23; /*!< (@ 0x4005345C) Reset external status register */
+ __I uint32_t RESERVED8[4];
+ __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */
+ __I uint32_t RESERVED9[3];
+ __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */
+ __I uint32_t RESERVED10;
+ __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */
+} LPC_RGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40080000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USARTn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (USARTn)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) USARTn Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ __O uint32_t THR; /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+ __I uint32_t RBR; /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+ __IO uint32_t DLM; /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t LSR; /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SCR; /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x400xx024) IrDA control register (UART3 only) */
+ __IO uint32_t FDR; /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __I uint32_t RESERVED2[4];
+ __IO uint32_t HDEN; /*!< (@ 0x400xx03C) Half-duplex enable Register */
+ __I uint32_t RESERVED3[1];
+ __IO uint32_t SCICTRL; /*!< (@ 0x400xx048) Smart card interface control register */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL; /*!< (@ 0x400xx058) Synchronous mode control register. */
+ __IO uint32_t TER; /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+} LPC_USARTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- UART1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (UART1)
+ */
+
+typedef struct { /*!< (@ 0x40082000) UART1 Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */
+ __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */
+ __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t TER; /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+ __I uint32_t RESERVED2[6];
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */
+ __I uint32_t FIFOLVL; /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+} LPC_UART1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSPn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (SSP0)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) SSPn Structure */
+ __IO uint32_t CR0; /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x400xx00C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x400xx010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x400xx018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x400xx01C) Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */
+ __IO uint32_t DMACR; /*!< (@ 0x400xx024) SSPn DMA control register */
+} LPC_SSPn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMERn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (TIMERn)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) TIMERn Structure */
+ __IO uint32_t IR; /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR[4]; /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ __IO uint32_t CCR; /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ __IO uint32_t CR[4]; /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+ __IO uint32_t EMR; /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMERn_Type;
+
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SCU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10 (SCU)
+ */
+
+typedef struct { /*!< (@ 0x40086000) SCU Structure */
+ __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */
+ __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */
+ __I uint32_t RESERVED0[30];
+ __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */
+ __I uint32_t RESERVED1[11];
+ __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */
+ __I uint32_t RESERVED2[18];
+ __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */
+ __I uint32_t RESERVED3[23];
+ __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */
+ __I uint32_t RESERVED4[21];
+ __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */
+ __I uint32_t RESERVED5[24];
+ __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */
+ __I uint32_t RESERVED6[19];
+ __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */
+ __I uint32_t RESERVED7[24];
+ __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */
+ __I uint32_t RESERVED8[23];
+ __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */
+ __I uint32_t RESERVED9[25];
+ __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */
+ __I uint32_t RESERVED10[27];
+ __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */
+ __I uint32_t RESERVED11[25];
+ __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */
+ __I uint32_t RESERVED12[17];
+ __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */
+ __I uint32_t RESERVED13[15];
+ __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */
+ __I uint32_t RESERVED14[16];
+ __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */
+ __I uint32_t RESERVED15[276];
+ __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */
+ __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */
+ __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */
+ __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */
+ __I uint32_t RESERVED16[28];
+ __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for */
+ __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */
+ __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */
+ __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */
+ __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */
+ __I uint32_t RESERVED17[27];
+ __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */
+ __I uint32_t RESERVED18[63];
+ __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */
+ __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief GPIO pin interrupt (GPIO_PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INTn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
+ */
+
+typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */
+} LPC_GPIO_GROUP_INTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- MCPWM -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7 (MCPWM)
+ */
+
+typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */
+ __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */
+ __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */
+ __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */
+ __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */
+ __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */
+ __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */
+ __IO uint32_t TC[3]; /*!< (@ 0x400A0018) Timer Counter register */
+ __IO uint32_t LIM[3]; /*!< (@ 0x400A0024) Limit register */
+ __IO uint32_t MAT[3]; /*!< (@ 0x400A0030) Match register */
+ __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */
+ __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */
+ __I uint32_t CAP[3]; /*!< (@ 0x400A0044) Capture register */
+ __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */
+ __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */
+ __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */
+ __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */
+ __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */
+ __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */
+ __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */
+ __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */
+ __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */
+ __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */
+} LPC_MCPWM_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx I2C0/1-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Cn)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) I2C0 Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /*!< (@ 0x400xx01C) Monitor mode control register. */
+ __IO uint32_t ADR1; /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ __IO uint32_t MASK[4]; /*!< (@ 0x400xx030) I2C Slave address mask register */
+} LPC_I2Cn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2Sn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Sn)
+ 0x400A2000 / 0x400A3000
+ */
+
+typedef struct { /*!< (@ 0x400Ax000) I2S Structure */
+ __IO uint32_t DAO; /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */
+ __IO uint32_t DAI; /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */
+ __O uint32_t TXFIFO; /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */
+ __I uint32_t RXFIFO; /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */
+ __I uint32_t STATE; /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */
+ __IO uint32_t DMA1; /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */
+ __IO uint32_t DMA2; /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */
+ __IO uint32_t IRQ; /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */
+ __IO uint32_t TXRATE; /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+ __IO uint32_t RXRATE; /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+ __IO uint32_t TXBITRATE; /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */
+ __IO uint32_t RXBITRATE; /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */
+ __IO uint32_t TXMODE; /*!< (@ 0x400Ax030) I2S Transmit mode control. */
+ __IO uint32_t RXMODE; /*!< (@ 0x400Ax034) I2S Receive mode control. */
+} LPC_I2Sn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// ----- C_CANn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7 (C_CANn)
+ 0x400A4000 / 0x400E2000
+ */
+
+typedef struct { /*!< (@ 0x400E2000) C_CAN Structure */
+ __IO uint32_t CNTL; /*!< (@ 0x400E2000) CAN control */
+ __IO uint32_t STAT; /*!< (@ 0x400E2004) Status register */
+ __I uint32_t EC; /*!< (@ 0x400E2008) Error counter */
+ __IO uint32_t BT; /*!< (@ 0x400E200C) Bit timing register */
+ __I uint32_t INT; /*!< (@ 0x400E2010) Interrupt register */
+ __IO uint32_t TEST; /*!< (@ 0x400E2014) Test register */
+ __IO uint32_t BRPE; /*!< (@ 0x400E2018) Baud rate prescaler extension register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400E2020) Message interface command request */
+
+ union {
+ __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400E2024) Message interface command mask (read direction) */
+ __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400E2024) Message interface command mask (write direction) */
+ };
+ __IO uint32_t IF1_MSK1; /*!< (@ 0x400E2028) Message interface mask 1 */
+ __IO uint32_t IF1_MSK2; /*!< (@ 0x400E202C) Message interface 1 mask 2 */
+ __IO uint32_t IF1_ARB1; /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */
+ __IO uint32_t IF1_ARB2; /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */
+ __IO uint32_t IF1_MCTRL; /*!< (@ 0x400E2038) Message interface 1 message control */
+ __IO uint32_t IF1_DA1; /*!< (@ 0x400E203C) Message interface data A1 */
+ __IO uint32_t IF1_DA2; /*!< (@ 0x400E2040) Message interface 1 data A2 */
+ __IO uint32_t IF1_DB1; /*!< (@ 0x400E2044) Message interface 1 data B1 */
+ __IO uint32_t IF1_DB2; /*!< (@ 0x400E2048) Message interface 1 data B2 */
+ __I uint32_t RESERVED1[13];
+ __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400E2080) Message interface command request */
+
+ union {
+ __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400E2084) Message interface command mask (read direction) */
+ __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400E2084) Message interface command mask (write direction) */
+ };
+ __IO uint32_t IF2_MSK1; /*!< (@ 0x400E2088) Message interface mask 1 */
+ __IO uint32_t IF2_MSK2; /*!< (@ 0x400E208C) Message interface 1 mask 2 */
+ __IO uint32_t IF2_ARB1; /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */
+ __IO uint32_t IF2_ARB2; /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */
+ __IO uint32_t IF2_MCTRL; /*!< (@ 0x400E2098) Message interface 1 message control */
+ __IO uint32_t IF2_DA1; /*!< (@ 0x400E209C) Message interface data A1 */
+ __IO uint32_t IF2_DA2; /*!< (@ 0x400E20A0) Message interface 1 data A2 */
+ __IO uint32_t IF2_DB1; /*!< (@ 0x400E20A4) Message interface 1 data B1 */
+ __IO uint32_t IF2_DB2; /*!< (@ 0x400E20A8) Message interface 1 data B2 */
+ __I uint32_t RESERVED2[21];
+ __I uint32_t TXREQ1; /*!< (@ 0x400E2100) Transmission request 1 */
+ __I uint32_t TXREQ2; /*!< (@ 0x400E2104) Transmission request 2 */
+ __I uint32_t RESERVED3[6];
+ __I uint32_t ND1; /*!< (@ 0x400E2120) New data 1 */
+ __I uint32_t ND2; /*!< (@ 0x400E2124) New data 2 */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t IR1; /*!< (@ 0x400E2140) Interrupt pending 1 */
+ __I uint32_t IR2; /*!< (@ 0x400E2144) Interrupt pending 2 */
+ __I uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /*!< (@ 0x400E2160) Message valid 1 */
+ __I uint32_t MSGV2; /*!< (@ 0x400E2164) Message valid 2 */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /*!< (@ 0x400E2180) CAN clock divider register */
+} LPC_C_CANn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RITIMER -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (RITIMER)
+ */
+
+typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */
+ __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */
+ __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+ __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */
+ __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- QEI -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7 (QEI)
+ */
+
+typedef struct { /*!< (@ 0x400C6000) QEI Structure */
+ __O uint32_t CON; /*!< (@ 0x400C6000) Control register */
+ __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */
+ __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */
+ __I uint32_t POS; /*!< (@ 0x400C600C) Position register */
+ __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */
+ __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */
+ __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */
+ __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */
+ __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */
+ __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */
+ __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */
+ __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */
+ __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */
+ __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */
+ __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */
+ __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */
+ __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */
+ __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */
+ __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */
+ __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */
+ __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */
+ __I uint32_t RESERVED0[993];
+ __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */
+ __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */
+ __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */
+ __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */
+ __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */
+ __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */
+} LPC_QEI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GIMA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=Falcon Chapter title=Global Input Multiplexer Array (GIMA) Modification date=3/25/2011 Major revision=0 Minor revision=4 (GIMA)
+ */
+
+typedef struct { /*!< (@ 0x400C7000) GIMA Structure */
+ __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+ __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+ __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+ __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+ __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+ __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+ __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+ __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+ __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+ __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+ __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+ __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+ __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+ __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+ __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+ __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+ __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+ __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+ __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+ __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+ __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+ __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+ __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+ __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+ __IO uint32_t VADC_TRIGGER_IN; /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */
+ __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */
+ __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */
+ __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */
+ __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */
+ __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */
+} LPC_GIMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- DAC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7 (DAC)
+ */
+
+typedef struct { /*!< (@ 0x400E1000) DAC Structure */
+ __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */
+ __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */
+ __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */
+} LPC_DAC_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADCn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7 (ADCn)
+ 0x400E3000 / 0x400E4000
+ */
+
+typedef struct { /*!< (@ 0x400Ex000) ADCn Structure */
+ __IO uint32_t CR; /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+ __I uint32_t GDR; /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ __I uint32_t DR[8]; /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+ __I uint32_t STAT; /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADCn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief GPIO port (GPIO_PORT)
+ */
+
+typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */
+ __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
+ __I uint32_t RESERVED0[960];
+ __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */
+ __I uint32_t RESERVED1[768];
+ __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port n */
+ __I uint32_t RESERVED2[24];
+ __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port n */
+ __I uint32_t RESERVED3[24];
+ __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Portpin register port n */
+ __I uint32_t RESERVED4[24];
+ __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port n */
+ __I uint32_t RESERVED5[24];
+ __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */
+ __I uint32_t RESERVED6[24];
+ __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port n */
+ __I uint32_t RESERVED7[24];
+ __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port n */
+} LPC_GPIO_PORT_Type;
+
+
+
+/********************************************
+** End of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma pop
+#else
+ #error Not supported compiler type
+#endif
+
+
+#ifdef CMSIS_BITPOSITIONS
+// ------------------------------------------------------------------------------------------------
+// ----- SCT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- SCT_CONFIG -------------------------------------------
+#define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */
+#define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */
+#define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */
+#define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */
+#define SCT_CONFIG_CLKSEL_Pos 3 /*!< SCT CONFIG: CLKSEL Position */
+#define SCT_CONFIG_CLKSEL_Msk (0x0fUL << SCT_CONFIG_CLKSEL_Pos) /*!< SCT CONFIG: CLKSEL Mask */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Pos 7 /*!< SCT CONFIG: NORELAODL_NORELOADU Position */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Msk (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos) /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */
+#define SCT_CONFIG_NORELOADH_Pos 8 /*!< SCT CONFIG: NORELOADH Position */
+#define SCT_CONFIG_NORELOADH_Msk (0x01UL << SCT_CONFIG_NORELOADH_Pos) /*!< SCT CONFIG: NORELOADH Mask */
+#define SCT_CONFIG_INSYNCn_Pos 9 /*!< SCT CONFIG: INSYNCn Position */
+#define SCT_CONFIG_INSYNCn_Msk (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos) /*!< SCT CONFIG: INSYNCn Mask */
+
+// ---------------------------------------- SCT_CTRL --------------------------------------------
+#define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */
+#define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */
+#define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */
+#define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */
+#define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */
+#define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */
+#define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */
+#define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */
+#define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */
+#define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */
+#define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */
+#define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */
+#define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */
+#define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */
+#define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */
+#define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */
+#define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */
+#define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */
+#define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */
+#define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */
+#define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */
+#define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */
+#define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */
+#define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */
+
+// ---------------------------------------- SCT_LIMIT -------------------------------------------
+#define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */
+#define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */
+#define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */
+#define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */
+
+// ---------------------------------------- SCT_HALT --------------------------------------------
+#define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */
+#define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */
+#define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */
+#define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */
+
+// ---------------------------------------- SCT_STOP --------------------------------------------
+#define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */
+#define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */
+#define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */
+#define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */
+
+// ---------------------------------------- SCT_START -------------------------------------------
+#define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */
+#define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */
+#define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */
+#define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */
+
+// ---------------------------------------- SCT_COUNT -------------------------------------------
+#define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */
+#define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */
+#define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */
+#define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */
+
+// ---------------------------------------- SCT_STATE -------------------------------------------
+#define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */
+#define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */
+#define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */
+#define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */
+
+// ---------------------------------------- SCT_INPUT -------------------------------------------
+#define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */
+#define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */
+#define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */
+#define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */
+#define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */
+#define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */
+#define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */
+#define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */
+#define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */
+#define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */
+#define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */
+#define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */
+#define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */
+#define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */
+#define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */
+#define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */
+#define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */
+#define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */
+#define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */
+#define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */
+#define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */
+#define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */
+#define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */
+#define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */
+#define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */
+#define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */
+#define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */
+#define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */
+#define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */
+#define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */
+#define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */
+#define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */
+
+// --------------------------------------- SCT_REGMODE ------------------------------------------
+#define SCT_REGMODE_REGMOD_L0_Pos 0 /*!< SCT REGMODE: REGMOD_L0 Position */
+#define SCT_REGMODE_REGMOD_L0_Msk (0x01UL << SCT_REGMODE_REGMOD_L0_Pos) /*!< SCT REGMODE: REGMOD_L0 Mask */
+#define SCT_REGMODE_REGMOD_L1_Pos 1 /*!< SCT REGMODE: REGMOD_L1 Position */
+#define SCT_REGMODE_REGMOD_L1_Msk (0x01UL << SCT_REGMODE_REGMOD_L1_Pos) /*!< SCT REGMODE: REGMOD_L1 Mask */
+#define SCT_REGMODE_REGMOD_L2_Pos 2 /*!< SCT REGMODE: REGMOD_L2 Position */
+#define SCT_REGMODE_REGMOD_L2_Msk (0x01UL << SCT_REGMODE_REGMOD_L2_Pos) /*!< SCT REGMODE: REGMOD_L2 Mask */
+#define SCT_REGMODE_REGMOD_L3_Pos 3 /*!< SCT REGMODE: REGMOD_L3 Position */
+#define SCT_REGMODE_REGMOD_L3_Msk (0x01UL << SCT_REGMODE_REGMOD_L3_Pos) /*!< SCT REGMODE: REGMOD_L3 Mask */
+#define SCT_REGMODE_REGMOD_L4_Pos 4 /*!< SCT REGMODE: REGMOD_L4 Position */
+#define SCT_REGMODE_REGMOD_L4_Msk (0x01UL << SCT_REGMODE_REGMOD_L4_Pos) /*!< SCT REGMODE: REGMOD_L4 Mask */
+#define SCT_REGMODE_REGMOD_L5_Pos 5 /*!< SCT REGMODE: REGMOD_L5 Position */
+#define SCT_REGMODE_REGMOD_L5_Msk (0x01UL << SCT_REGMODE_REGMOD_L5_Pos) /*!< SCT REGMODE: REGMOD_L5 Mask */
+#define SCT_REGMODE_REGMOD_L6_Pos 6 /*!< SCT REGMODE: REGMOD_L6 Position */
+#define SCT_REGMODE_REGMOD_L6_Msk (0x01UL << SCT_REGMODE_REGMOD_L6_Pos) /*!< SCT REGMODE: REGMOD_L6 Mask */
+#define SCT_REGMODE_REGMOD_L7_Pos 7 /*!< SCT REGMODE: REGMOD_L7 Position */
+#define SCT_REGMODE_REGMOD_L7_Msk (0x01UL << SCT_REGMODE_REGMOD_L7_Pos) /*!< SCT REGMODE: REGMOD_L7 Mask */
+#define SCT_REGMODE_REGMOD_L8_Pos 8 /*!< SCT REGMODE: REGMOD_L8 Position */
+#define SCT_REGMODE_REGMOD_L8_Msk (0x01UL << SCT_REGMODE_REGMOD_L8_Pos) /*!< SCT REGMODE: REGMOD_L8 Mask */
+#define SCT_REGMODE_REGMOD_L9_Pos 9 /*!< SCT REGMODE: REGMOD_L9 Position */
+#define SCT_REGMODE_REGMOD_L9_Msk (0x01UL << SCT_REGMODE_REGMOD_L9_Pos) /*!< SCT REGMODE: REGMOD_L9 Mask */
+#define SCT_REGMODE_REGMOD_L10_Pos 10 /*!< SCT REGMODE: REGMOD_L10 Position */
+#define SCT_REGMODE_REGMOD_L10_Msk (0x01UL << SCT_REGMODE_REGMOD_L10_Pos) /*!< SCT REGMODE: REGMOD_L10 Mask */
+#define SCT_REGMODE_REGMOD_L11_Pos 11 /*!< SCT REGMODE: REGMOD_L11 Position */
+#define SCT_REGMODE_REGMOD_L11_Msk (0x01UL << SCT_REGMODE_REGMOD_L11_Pos) /*!< SCT REGMODE: REGMOD_L11 Mask */
+#define SCT_REGMODE_REGMOD_L12_Pos 12 /*!< SCT REGMODE: REGMOD_L12 Position */
+#define SCT_REGMODE_REGMOD_L12_Msk (0x01UL << SCT_REGMODE_REGMOD_L12_Pos) /*!< SCT REGMODE: REGMOD_L12 Mask */
+#define SCT_REGMODE_REGMOD_L13_Pos 13 /*!< SCT REGMODE: REGMOD_L13 Position */
+#define SCT_REGMODE_REGMOD_L13_Msk (0x01UL << SCT_REGMODE_REGMOD_L13_Pos) /*!< SCT REGMODE: REGMOD_L13 Mask */
+#define SCT_REGMODE_REGMOD_L14_Pos 14 /*!< SCT REGMODE: REGMOD_L14 Position */
+#define SCT_REGMODE_REGMOD_L14_Msk (0x01UL << SCT_REGMODE_REGMOD_L14_Pos) /*!< SCT REGMODE: REGMOD_L14 Mask */
+#define SCT_REGMODE_REGMOD_L15_Pos 15 /*!< SCT REGMODE: REGMOD_L15 Position */
+#define SCT_REGMODE_REGMOD_L15_Msk (0x01UL << SCT_REGMODE_REGMOD_L15_Pos) /*!< SCT REGMODE: REGMOD_L15 Mask */
+#define SCT_REGMODE_REGMOD_H16_Pos 16 /*!< SCT REGMODE: REGMOD_H16 Position */
+#define SCT_REGMODE_REGMOD_H16_Msk (0x01UL << SCT_REGMODE_REGMOD_H16_Pos) /*!< SCT REGMODE: REGMOD_H16 Mask */
+#define SCT_REGMODE_REGMOD_H17_Pos 17 /*!< SCT REGMODE: REGMOD_H17 Position */
+#define SCT_REGMODE_REGMOD_H17_Msk (0x01UL << SCT_REGMODE_REGMOD_H17_Pos) /*!< SCT REGMODE: REGMOD_H17 Mask */
+#define SCT_REGMODE_REGMOD_H18_Pos 18 /*!< SCT REGMODE: REGMOD_H18 Position */
+#define SCT_REGMODE_REGMOD_H18_Msk (0x01UL << SCT_REGMODE_REGMOD_H18_Pos) /*!< SCT REGMODE: REGMOD_H18 Mask */
+#define SCT_REGMODE_REGMOD_H19_Pos 19 /*!< SCT REGMODE: REGMOD_H19 Position */
+#define SCT_REGMODE_REGMOD_H19_Msk (0x01UL << SCT_REGMODE_REGMOD_H19_Pos) /*!< SCT REGMODE: REGMOD_H19 Mask */
+#define SCT_REGMODE_REGMOD_H20_Pos 20 /*!< SCT REGMODE: REGMOD_H20 Position */
+#define SCT_REGMODE_REGMOD_H20_Msk (0x01UL << SCT_REGMODE_REGMOD_H20_Pos) /*!< SCT REGMODE: REGMOD_H20 Mask */
+#define SCT_REGMODE_REGMOD_H21_Pos 21 /*!< SCT REGMODE: REGMOD_H21 Position */
+#define SCT_REGMODE_REGMOD_H21_Msk (0x01UL << SCT_REGMODE_REGMOD_H21_Pos) /*!< SCT REGMODE: REGMOD_H21 Mask */
+#define SCT_REGMODE_REGMOD_H22_Pos 22 /*!< SCT REGMODE: REGMOD_H22 Position */
+#define SCT_REGMODE_REGMOD_H22_Msk (0x01UL << SCT_REGMODE_REGMOD_H22_Pos) /*!< SCT REGMODE: REGMOD_H22 Mask */
+#define SCT_REGMODE_REGMOD_H23_Pos 23 /*!< SCT REGMODE: REGMOD_H23 Position */
+#define SCT_REGMODE_REGMOD_H23_Msk (0x01UL << SCT_REGMODE_REGMOD_H23_Pos) /*!< SCT REGMODE: REGMOD_H23 Mask */
+#define SCT_REGMODE_REGMOD_H24_Pos 24 /*!< SCT REGMODE: REGMOD_H24 Position */
+#define SCT_REGMODE_REGMOD_H24_Msk (0x01UL << SCT_REGMODE_REGMOD_H24_Pos) /*!< SCT REGMODE: REGMOD_H24 Mask */
+#define SCT_REGMODE_REGMOD_H25_Pos 25 /*!< SCT REGMODE: REGMOD_H25 Position */
+#define SCT_REGMODE_REGMOD_H25_Msk (0x01UL << SCT_REGMODE_REGMOD_H25_Pos) /*!< SCT REGMODE: REGMOD_H25 Mask */
+#define SCT_REGMODE_REGMOD_H26_Pos 26 /*!< SCT REGMODE: REGMOD_H26 Position */
+#define SCT_REGMODE_REGMOD_H26_Msk (0x01UL << SCT_REGMODE_REGMOD_H26_Pos) /*!< SCT REGMODE: REGMOD_H26 Mask */
+#define SCT_REGMODE_REGMOD_H27_Pos 27 /*!< SCT REGMODE: REGMOD_H27 Position */
+#define SCT_REGMODE_REGMOD_H27_Msk (0x01UL << SCT_REGMODE_REGMOD_H27_Pos) /*!< SCT REGMODE: REGMOD_H27 Mask */
+#define SCT_REGMODE_REGMOD_H28_Pos 28 /*!< SCT REGMODE: REGMOD_H28 Position */
+#define SCT_REGMODE_REGMOD_H28_Msk (0x01UL << SCT_REGMODE_REGMOD_H28_Pos) /*!< SCT REGMODE: REGMOD_H28 Mask */
+#define SCT_REGMODE_REGMOD_H29_Pos 29 /*!< SCT REGMODE: REGMOD_H29 Position */
+#define SCT_REGMODE_REGMOD_H29_Msk (0x01UL << SCT_REGMODE_REGMOD_H29_Pos) /*!< SCT REGMODE: REGMOD_H29 Mask */
+#define SCT_REGMODE_REGMOD_H30_Pos 30 /*!< SCT REGMODE: REGMOD_H30 Position */
+#define SCT_REGMODE_REGMOD_H30_Msk (0x01UL << SCT_REGMODE_REGMOD_H30_Pos) /*!< SCT REGMODE: REGMOD_H30 Mask */
+#define SCT_REGMODE_REGMOD_H31_Pos 31 /*!< SCT REGMODE: REGMOD_H31 Position */
+#define SCT_REGMODE_REGMOD_H31_Msk (0x01UL << SCT_REGMODE_REGMOD_H31_Pos) /*!< SCT REGMODE: REGMOD_H31 Mask */
+
+// --------------------------------------- SCT_OUTPUT -------------------------------------------
+#define SCT_OUTPUT_OUT0_Pos 0 /*!< SCT OUTPUT: OUT0 Position */
+#define SCT_OUTPUT_OUT0_Msk (0x01UL << SCT_OUTPUT_OUT0_Pos) /*!< SCT OUTPUT: OUT0 Mask */
+#define SCT_OUTPUT_OUT1_Pos 1 /*!< SCT OUTPUT: OUT1 Position */
+#define SCT_OUTPUT_OUT1_Msk (0x01UL << SCT_OUTPUT_OUT1_Pos) /*!< SCT OUTPUT: OUT1 Mask */
+#define SCT_OUTPUT_OUT2_Pos 2 /*!< SCT OUTPUT: OUT2 Position */
+#define SCT_OUTPUT_OUT2_Msk (0x01UL << SCT_OUTPUT_OUT2_Pos) /*!< SCT OUTPUT: OUT2 Mask */
+#define SCT_OUTPUT_OUT3_Pos 3 /*!< SCT OUTPUT: OUT3 Position */
+#define SCT_OUTPUT_OUT3_Msk (0x01UL << SCT_OUTPUT_OUT3_Pos) /*!< SCT OUTPUT: OUT3 Mask */
+#define SCT_OUTPUT_OUT4_Pos 4 /*!< SCT OUTPUT: OUT4 Position */
+#define SCT_OUTPUT_OUT4_Msk (0x01UL << SCT_OUTPUT_OUT4_Pos) /*!< SCT OUTPUT: OUT4 Mask */
+#define SCT_OUTPUT_OUT5_Pos 5 /*!< SCT OUTPUT: OUT5 Position */
+#define SCT_OUTPUT_OUT5_Msk (0x01UL << SCT_OUTPUT_OUT5_Pos) /*!< SCT OUTPUT: OUT5 Mask */
+#define SCT_OUTPUT_OUT6_Pos 6 /*!< SCT OUTPUT: OUT6 Position */
+#define SCT_OUTPUT_OUT6_Msk (0x01UL << SCT_OUTPUT_OUT6_Pos) /*!< SCT OUTPUT: OUT6 Mask */
+#define SCT_OUTPUT_OUT7_Pos 7 /*!< SCT OUTPUT: OUT7 Position */
+#define SCT_OUTPUT_OUT7_Msk (0x01UL << SCT_OUTPUT_OUT7_Pos) /*!< SCT OUTPUT: OUT7 Mask */
+#define SCT_OUTPUT_OUT8_Pos 8 /*!< SCT OUTPUT: OUT8 Position */
+#define SCT_OUTPUT_OUT8_Msk (0x01UL << SCT_OUTPUT_OUT8_Pos) /*!< SCT OUTPUT: OUT8 Mask */
+#define SCT_OUTPUT_OUT9_Pos 9 /*!< SCT OUTPUT: OUT9 Position */
+#define SCT_OUTPUT_OUT9_Msk (0x01UL << SCT_OUTPUT_OUT9_Pos) /*!< SCT OUTPUT: OUT9 Mask */
+#define SCT_OUTPUT_OUT10_Pos 10 /*!< SCT OUTPUT: OUT10 Position */
+#define SCT_OUTPUT_OUT10_Msk (0x01UL << SCT_OUTPUT_OUT10_Pos) /*!< SCT OUTPUT: OUT10 Mask */
+#define SCT_OUTPUT_OUT11_Pos 11 /*!< SCT OUTPUT: OUT11 Position */
+#define SCT_OUTPUT_OUT11_Msk (0x01UL << SCT_OUTPUT_OUT11_Pos) /*!< SCT OUTPUT: OUT11 Mask */
+#define SCT_OUTPUT_OUT12_Pos 12 /*!< SCT OUTPUT: OUT12 Position */
+#define SCT_OUTPUT_OUT12_Msk (0x01UL << SCT_OUTPUT_OUT12_Pos) /*!< SCT OUTPUT: OUT12 Mask */
+#define SCT_OUTPUT_OUT13_Pos 13 /*!< SCT OUTPUT: OUT13 Position */
+#define SCT_OUTPUT_OUT13_Msk (0x01UL << SCT_OUTPUT_OUT13_Pos) /*!< SCT OUTPUT: OUT13 Mask */
+#define SCT_OUTPUT_OUT14_Pos 14 /*!< SCT OUTPUT: OUT14 Position */
+#define SCT_OUTPUT_OUT14_Msk (0x01UL << SCT_OUTPUT_OUT14_Pos) /*!< SCT OUTPUT: OUT14 Mask */
+#define SCT_OUTPUT_OUT15_Pos 15 /*!< SCT OUTPUT: OUT15 Position */
+#define SCT_OUTPUT_OUT15_Msk (0x01UL << SCT_OUTPUT_OUT15_Pos) /*!< SCT OUTPUT: OUT15 Mask */
+
+// ------------------------------------ SCT_OUTPUTDIRCTRL ---------------------------------------
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */
+
+// ----------------------------------------- SCT_RES --------------------------------------------
+#define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */
+#define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */
+#define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */
+#define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */
+#define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */
+#define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */
+#define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */
+#define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */
+#define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */
+#define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */
+#define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */
+#define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */
+#define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */
+#define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */
+#define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */
+#define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */
+#define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */
+#define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */
+#define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */
+#define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */
+#define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */
+#define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */
+#define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */
+#define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */
+#define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */
+#define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */
+#define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */
+#define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */
+#define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */
+#define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */
+#define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */
+#define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */
+
+// --------------------------------------- SCT_DMAREQ0 ------------------------------------------
+#define SCT_DMAREQ0_DEV_0_0_Pos 0 /*!< SCT DMAREQ0: DEV_0_0 Position */
+#define SCT_DMAREQ0_DEV_0_0_Msk (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos) /*!< SCT DMAREQ0: DEV_0_0 Mask */
+#define SCT_DMAREQ0_DEV_0_1_Pos 1 /*!< SCT DMAREQ0: DEV_0_1 Position */
+#define SCT_DMAREQ0_DEV_0_1_Msk (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos) /*!< SCT DMAREQ0: DEV_0_1 Mask */
+#define SCT_DMAREQ0_DEV_0_2_Pos 2 /*!< SCT DMAREQ0: DEV_0_2 Position */
+#define SCT_DMAREQ0_DEV_0_2_Msk (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos) /*!< SCT DMAREQ0: DEV_0_2 Mask */
+#define SCT_DMAREQ0_DEV_0_3_Pos 3 /*!< SCT DMAREQ0: DEV_0_3 Position */
+#define SCT_DMAREQ0_DEV_0_3_Msk (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos) /*!< SCT DMAREQ0: DEV_0_3 Mask */
+#define SCT_DMAREQ0_DEV_0_4_Pos 4 /*!< SCT DMAREQ0: DEV_0_4 Position */
+#define SCT_DMAREQ0_DEV_0_4_Msk (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos) /*!< SCT DMAREQ0: DEV_0_4 Mask */
+#define SCT_DMAREQ0_DEV_0_5_Pos 5 /*!< SCT DMAREQ0: DEV_0_5 Position */
+#define SCT_DMAREQ0_DEV_0_5_Msk (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos) /*!< SCT DMAREQ0: DEV_0_5 Mask */
+#define SCT_DMAREQ0_DEV_0_6_Pos 6 /*!< SCT DMAREQ0: DEV_0_6 Position */
+#define SCT_DMAREQ0_DEV_0_6_Msk (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos) /*!< SCT DMAREQ0: DEV_0_6 Mask */
+#define SCT_DMAREQ0_DEV_0_7_Pos 7 /*!< SCT DMAREQ0: DEV_0_7 Position */
+#define SCT_DMAREQ0_DEV_0_7_Msk (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos) /*!< SCT DMAREQ0: DEV_0_7 Mask */
+#define SCT_DMAREQ0_DEV_0_8_Pos 8 /*!< SCT DMAREQ0: DEV_0_8 Position */
+#define SCT_DMAREQ0_DEV_0_8_Msk (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos) /*!< SCT DMAREQ0: DEV_0_8 Mask */
+#define SCT_DMAREQ0_DEV_0_9_Pos 9 /*!< SCT DMAREQ0: DEV_0_9 Position */
+#define SCT_DMAREQ0_DEV_0_9_Msk (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos) /*!< SCT DMAREQ0: DEV_0_9 Mask */
+#define SCT_DMAREQ0_DEV_0_10_Pos 10 /*!< SCT DMAREQ0: DEV_0_10 Position */
+#define SCT_DMAREQ0_DEV_0_10_Msk (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos) /*!< SCT DMAREQ0: DEV_0_10 Mask */
+#define SCT_DMAREQ0_DEV_0_11_Pos 11 /*!< SCT DMAREQ0: DEV_0_11 Position */
+#define SCT_DMAREQ0_DEV_0_11_Msk (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos) /*!< SCT DMAREQ0: DEV_0_11 Mask */
+#define SCT_DMAREQ0_DEV_0_12_Pos 12 /*!< SCT DMAREQ0: DEV_0_12 Position */
+#define SCT_DMAREQ0_DEV_0_12_Msk (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos) /*!< SCT DMAREQ0: DEV_0_12 Mask */
+#define SCT_DMAREQ0_DEV_0_13_Pos 13 /*!< SCT DMAREQ0: DEV_0_13 Position */
+#define SCT_DMAREQ0_DEV_0_13_Msk (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos) /*!< SCT DMAREQ0: DEV_0_13 Mask */
+#define SCT_DMAREQ0_DEV_0_14_Pos 14 /*!< SCT DMAREQ0: DEV_0_14 Position */
+#define SCT_DMAREQ0_DEV_0_14_Msk (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos) /*!< SCT DMAREQ0: DEV_0_14 Mask */
+#define SCT_DMAREQ0_DEV_0_15_Pos 15 /*!< SCT DMAREQ0: DEV_0_15 Position */
+#define SCT_DMAREQ0_DEV_0_15_Msk (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos) /*!< SCT DMAREQ0: DEV_0_15 Mask */
+#define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */
+#define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */
+#define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */
+#define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */
+
+// --------------------------------------- SCT_DMAREQ1 ------------------------------------------
+#define SCT_DMAREQ1_DEV_1_0_Pos 0 /*!< SCT DMAREQ1: DEV_1_0 Position */
+#define SCT_DMAREQ1_DEV_1_0_Msk (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos) /*!< SCT DMAREQ1: DEV_1_0 Mask */
+#define SCT_DMAREQ1_DEV_1_1_Pos 1 /*!< SCT DMAREQ1: DEV_1_1 Position */
+#define SCT_DMAREQ1_DEV_1_1_Msk (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos) /*!< SCT DMAREQ1: DEV_1_1 Mask */
+#define SCT_DMAREQ1_DEV_1_2_Pos 2 /*!< SCT DMAREQ1: DEV_1_2 Position */
+#define SCT_DMAREQ1_DEV_1_2_Msk (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos) /*!< SCT DMAREQ1: DEV_1_2 Mask */
+#define SCT_DMAREQ1_DEV_1_3_Pos 3 /*!< SCT DMAREQ1: DEV_1_3 Position */
+#define SCT_DMAREQ1_DEV_1_3_Msk (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos) /*!< SCT DMAREQ1: DEV_1_3 Mask */
+#define SCT_DMAREQ1_DEV_1_4_Pos 4 /*!< SCT DMAREQ1: DEV_1_4 Position */
+#define SCT_DMAREQ1_DEV_1_4_Msk (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos) /*!< SCT DMAREQ1: DEV_1_4 Mask */
+#define SCT_DMAREQ1_DEV_1_5_Pos 5 /*!< SCT DMAREQ1: DEV_1_5 Position */
+#define SCT_DMAREQ1_DEV_1_5_Msk (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos) /*!< SCT DMAREQ1: DEV_1_5 Mask */
+#define SCT_DMAREQ1_DEV_1_6_Pos 6 /*!< SCT DMAREQ1: DEV_1_6 Position */
+#define SCT_DMAREQ1_DEV_1_6_Msk (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos) /*!< SCT DMAREQ1: DEV_1_6 Mask */
+#define SCT_DMAREQ1_DEV_1_7_Pos 7 /*!< SCT DMAREQ1: DEV_1_7 Position */
+#define SCT_DMAREQ1_DEV_1_7_Msk (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos) /*!< SCT DMAREQ1: DEV_1_7 Mask */
+#define SCT_DMAREQ1_DEV_1_8_Pos 8 /*!< SCT DMAREQ1: DEV_1_8 Position */
+#define SCT_DMAREQ1_DEV_1_8_Msk (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos) /*!< SCT DMAREQ1: DEV_1_8 Mask */
+#define SCT_DMAREQ1_DEV_1_9_Pos 9 /*!< SCT DMAREQ1: DEV_1_9 Position */
+#define SCT_DMAREQ1_DEV_1_9_Msk (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos) /*!< SCT DMAREQ1: DEV_1_9 Mask */
+#define SCT_DMAREQ1_DEV_1_10_Pos 10 /*!< SCT DMAREQ1: DEV_1_10 Position */
+#define SCT_DMAREQ1_DEV_1_10_Msk (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos) /*!< SCT DMAREQ1: DEV_1_10 Mask */
+#define SCT_DMAREQ1_DEV_1_11_Pos 11 /*!< SCT DMAREQ1: DEV_1_11 Position */
+#define SCT_DMAREQ1_DEV_1_11_Msk (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos) /*!< SCT DMAREQ1: DEV_1_11 Mask */
+#define SCT_DMAREQ1_DEV_1_12_Pos 12 /*!< SCT DMAREQ1: DEV_1_12 Position */
+#define SCT_DMAREQ1_DEV_1_12_Msk (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos) /*!< SCT DMAREQ1: DEV_1_12 Mask */
+#define SCT_DMAREQ1_DEV_1_13_Pos 13 /*!< SCT DMAREQ1: DEV_1_13 Position */
+#define SCT_DMAREQ1_DEV_1_13_Msk (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos) /*!< SCT DMAREQ1: DEV_1_13 Mask */
+#define SCT_DMAREQ1_DEV_1_14_Pos 14 /*!< SCT DMAREQ1: DEV_1_14 Position */
+#define SCT_DMAREQ1_DEV_1_14_Msk (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos) /*!< SCT DMAREQ1: DEV_1_14 Mask */
+#define SCT_DMAREQ1_DEV_1_15_Pos 15 /*!< SCT DMAREQ1: DEV_1_15 Position */
+#define SCT_DMAREQ1_DEV_1_15_Msk (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos) /*!< SCT DMAREQ1: DEV_1_15 Mask */
+#define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */
+#define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */
+#define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */
+#define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */
+
+// ---------------------------------------- SCT_EVEN --------------------------------------------
+#define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */
+#define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */
+#define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */
+#define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */
+#define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */
+#define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */
+#define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */
+#define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */
+#define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */
+#define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */
+#define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */
+#define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */
+#define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */
+#define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */
+#define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */
+#define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */
+#define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */
+#define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */
+#define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */
+#define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */
+#define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */
+#define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */
+#define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */
+#define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */
+#define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */
+#define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */
+#define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */
+#define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */
+#define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */
+#define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */
+#define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */
+#define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */
+
+// --------------------------------------- SCT_EVFLAG -------------------------------------------
+#define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */
+#define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */
+#define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */
+#define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */
+#define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */
+#define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */
+#define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */
+#define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */
+#define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */
+#define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */
+#define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */
+#define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */
+#define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */
+#define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */
+#define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */
+#define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */
+#define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */
+#define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */
+#define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */
+#define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */
+#define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */
+#define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */
+#define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */
+#define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */
+#define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */
+#define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */
+#define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */
+#define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */
+#define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */
+#define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */
+#define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */
+#define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */
+
+// ---------------------------------------- SCT_CONEN -------------------------------------------
+#define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */
+#define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */
+#define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */
+#define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */
+#define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */
+#define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */
+#define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */
+#define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */
+#define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */
+#define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */
+#define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */
+#define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */
+#define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */
+#define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */
+#define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */
+#define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */
+#define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */
+#define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */
+#define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */
+#define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */
+#define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */
+#define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */
+#define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */
+#define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */
+#define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */
+#define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */
+#define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */
+#define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */
+#define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */
+#define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */
+#define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */
+#define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */
+
+// --------------------------------------- SCT_CONFLAG ------------------------------------------
+#define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */
+#define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */
+#define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */
+#define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */
+#define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */
+#define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */
+#define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */
+#define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */
+#define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */
+#define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */
+#define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */
+#define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */
+#define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */
+#define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */
+#define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */
+#define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */
+#define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */
+#define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */
+#define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */
+#define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */
+#define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */
+#define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */
+#define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */
+#define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */
+#define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */
+#define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */
+#define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */
+#define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */
+#define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */
+#define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */
+#define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */
+#define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */
+#define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */
+#define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */
+#define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */
+#define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */
+
+// --------------------------------------- SCT_MATCH0 -------------------------------------------
+#define SCT_MATCH0_MATCHn_L_Pos 0 /*!< SCT MATCH0: MATCHn_L Position */
+#define SCT_MATCH0_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos) /*!< SCT MATCH0: MATCHn_L Mask */
+#define SCT_MATCH0_MATCHn_H_Pos 16 /*!< SCT MATCH0: MATCHn_H Position */
+#define SCT_MATCH0_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos) /*!< SCT MATCH0: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP0 --------------------------------------------
+#define SCT_CAP0_CAPn_L_Pos 0 /*!< SCT CAP0: CAPn_L Position */
+#define SCT_CAP0_CAPn_L_Msk (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos) /*!< SCT CAP0: CAPn_L Mask */
+#define SCT_CAP0_CAPn_H_Pos 16 /*!< SCT CAP0: CAPn_H Position */
+#define SCT_CAP0_CAPn_H_Msk (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos) /*!< SCT CAP0: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH1 -------------------------------------------
+#define SCT_MATCH1_MATCHn_L_Pos 0 /*!< SCT MATCH1: MATCHn_L Position */
+#define SCT_MATCH1_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos) /*!< SCT MATCH1: MATCHn_L Mask */
+#define SCT_MATCH1_MATCHn_H_Pos 16 /*!< SCT MATCH1: MATCHn_H Position */
+#define SCT_MATCH1_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos) /*!< SCT MATCH1: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP1 --------------------------------------------
+#define SCT_CAP1_CAPn_L_Pos 0 /*!< SCT CAP1: CAPn_L Position */
+#define SCT_CAP1_CAPn_L_Msk (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos) /*!< SCT CAP1: CAPn_L Mask */
+#define SCT_CAP1_CAPn_H_Pos 16 /*!< SCT CAP1: CAPn_H Position */
+#define SCT_CAP1_CAPn_H_Msk (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos) /*!< SCT CAP1: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH2 -------------------------------------------
+#define SCT_MATCH2_MATCHn_L_Pos 0 /*!< SCT MATCH2: MATCHn_L Position */
+#define SCT_MATCH2_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos) /*!< SCT MATCH2: MATCHn_L Mask */
+#define SCT_MATCH2_MATCHn_H_Pos 16 /*!< SCT MATCH2: MATCHn_H Position */
+#define SCT_MATCH2_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos) /*!< SCT MATCH2: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP2 --------------------------------------------
+#define SCT_CAP2_CAPn_L_Pos 0 /*!< SCT CAP2: CAPn_L Position */
+#define SCT_CAP2_CAPn_L_Msk (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos) /*!< SCT CAP2: CAPn_L Mask */
+#define SCT_CAP2_CAPn_H_Pos 16 /*!< SCT CAP2: CAPn_H Position */
+#define SCT_CAP2_CAPn_H_Msk (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos) /*!< SCT CAP2: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP3 --------------------------------------------
+#define SCT_CAP3_CAPn_L_Pos 0 /*!< SCT CAP3: CAPn_L Position */
+#define SCT_CAP3_CAPn_L_Msk (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos) /*!< SCT CAP3: CAPn_L Mask */
+#define SCT_CAP3_CAPn_H_Pos 16 /*!< SCT CAP3: CAPn_H Position */
+#define SCT_CAP3_CAPn_H_Msk (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos) /*!< SCT CAP3: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH3 -------------------------------------------
+#define SCT_MATCH3_MATCHn_L_Pos 0 /*!< SCT MATCH3: MATCHn_L Position */
+#define SCT_MATCH3_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos) /*!< SCT MATCH3: MATCHn_L Mask */
+#define SCT_MATCH3_MATCHn_H_Pos 16 /*!< SCT MATCH3: MATCHn_H Position */
+#define SCT_MATCH3_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos) /*!< SCT MATCH3: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH4 -------------------------------------------
+#define SCT_MATCH4_MATCHn_L_Pos 0 /*!< SCT MATCH4: MATCHn_L Position */
+#define SCT_MATCH4_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos) /*!< SCT MATCH4: MATCHn_L Mask */
+#define SCT_MATCH4_MATCHn_H_Pos 16 /*!< SCT MATCH4: MATCHn_H Position */
+#define SCT_MATCH4_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos) /*!< SCT MATCH4: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP4 --------------------------------------------
+#define SCT_CAP4_CAPn_L_Pos 0 /*!< SCT CAP4: CAPn_L Position */
+#define SCT_CAP4_CAPn_L_Msk (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos) /*!< SCT CAP4: CAPn_L Mask */
+#define SCT_CAP4_CAPn_H_Pos 16 /*!< SCT CAP4: CAPn_H Position */
+#define SCT_CAP4_CAPn_H_Msk (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos) /*!< SCT CAP4: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH5 -------------------------------------------
+#define SCT_MATCH5_MATCHn_L_Pos 0 /*!< SCT MATCH5: MATCHn_L Position */
+#define SCT_MATCH5_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos) /*!< SCT MATCH5: MATCHn_L Mask */
+#define SCT_MATCH5_MATCHn_H_Pos 16 /*!< SCT MATCH5: MATCHn_H Position */
+#define SCT_MATCH5_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos) /*!< SCT MATCH5: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP5 --------------------------------------------
+#define SCT_CAP5_CAPn_L_Pos 0 /*!< SCT CAP5: CAPn_L Position */
+#define SCT_CAP5_CAPn_L_Msk (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos) /*!< SCT CAP5: CAPn_L Mask */
+#define SCT_CAP5_CAPn_H_Pos 16 /*!< SCT CAP5: CAPn_H Position */
+#define SCT_CAP5_CAPn_H_Msk (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos) /*!< SCT CAP5: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH6 -------------------------------------------
+#define SCT_MATCH6_MATCHn_L_Pos 0 /*!< SCT MATCH6: MATCHn_L Position */
+#define SCT_MATCH6_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos) /*!< SCT MATCH6: MATCHn_L Mask */
+#define SCT_MATCH6_MATCHn_H_Pos 16 /*!< SCT MATCH6: MATCHn_H Position */
+#define SCT_MATCH6_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos) /*!< SCT MATCH6: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP6 --------------------------------------------
+#define SCT_CAP6_CAPn_L_Pos 0 /*!< SCT CAP6: CAPn_L Position */
+#define SCT_CAP6_CAPn_L_Msk (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos) /*!< SCT CAP6: CAPn_L Mask */
+#define SCT_CAP6_CAPn_H_Pos 16 /*!< SCT CAP6: CAPn_H Position */
+#define SCT_CAP6_CAPn_H_Msk (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos) /*!< SCT CAP6: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP7 --------------------------------------------
+#define SCT_CAP7_CAPn_L_Pos 0 /*!< SCT CAP7: CAPn_L Position */
+#define SCT_CAP7_CAPn_L_Msk (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos) /*!< SCT CAP7: CAPn_L Mask */
+#define SCT_CAP7_CAPn_H_Pos 16 /*!< SCT CAP7: CAPn_H Position */
+#define SCT_CAP7_CAPn_H_Msk (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos) /*!< SCT CAP7: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH7 -------------------------------------------
+#define SCT_MATCH7_MATCHn_L_Pos 0 /*!< SCT MATCH7: MATCHn_L Position */
+#define SCT_MATCH7_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos) /*!< SCT MATCH7: MATCHn_L Mask */
+#define SCT_MATCH7_MATCHn_H_Pos 16 /*!< SCT MATCH7: MATCHn_H Position */
+#define SCT_MATCH7_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos) /*!< SCT MATCH7: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP8 --------------------------------------------
+#define SCT_CAP8_CAPn_L_Pos 0 /*!< SCT CAP8: CAPn_L Position */
+#define SCT_CAP8_CAPn_L_Msk (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos) /*!< SCT CAP8: CAPn_L Mask */
+#define SCT_CAP8_CAPn_H_Pos 16 /*!< SCT CAP8: CAPn_H Position */
+#define SCT_CAP8_CAPn_H_Msk (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos) /*!< SCT CAP8: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH8 -------------------------------------------
+#define SCT_MATCH8_MATCHn_L_Pos 0 /*!< SCT MATCH8: MATCHn_L Position */
+#define SCT_MATCH8_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos) /*!< SCT MATCH8: MATCHn_L Mask */
+#define SCT_MATCH8_MATCHn_H_Pos 16 /*!< SCT MATCH8: MATCHn_H Position */
+#define SCT_MATCH8_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos) /*!< SCT MATCH8: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH9 -------------------------------------------
+#define SCT_MATCH9_MATCHn_L_Pos 0 /*!< SCT MATCH9: MATCHn_L Position */
+#define SCT_MATCH9_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos) /*!< SCT MATCH9: MATCHn_L Mask */
+#define SCT_MATCH9_MATCHn_H_Pos 16 /*!< SCT MATCH9: MATCHn_H Position */
+#define SCT_MATCH9_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos) /*!< SCT MATCH9: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP9 --------------------------------------------
+#define SCT_CAP9_CAPn_L_Pos 0 /*!< SCT CAP9: CAPn_L Position */
+#define SCT_CAP9_CAPn_L_Msk (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos) /*!< SCT CAP9: CAPn_L Mask */
+#define SCT_CAP9_CAPn_H_Pos 16 /*!< SCT CAP9: CAPn_H Position */
+#define SCT_CAP9_CAPn_H_Msk (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos) /*!< SCT CAP9: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP10 -------------------------------------------
+#define SCT_CAP10_CAPn_L_Pos 0 /*!< SCT CAP10: CAPn_L Position */
+#define SCT_CAP10_CAPn_L_Msk (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos) /*!< SCT CAP10: CAPn_L Mask */
+#define SCT_CAP10_CAPn_H_Pos 16 /*!< SCT CAP10: CAPn_H Position */
+#define SCT_CAP10_CAPn_H_Msk (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos) /*!< SCT CAP10: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH10 ------------------------------------------
+#define SCT_MATCH10_MATCHn_L_Pos 0 /*!< SCT MATCH10: MATCHn_L Position */
+#define SCT_MATCH10_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos) /*!< SCT MATCH10: MATCHn_L Mask */
+#define SCT_MATCH10_MATCHn_H_Pos 16 /*!< SCT MATCH10: MATCHn_H Position */
+#define SCT_MATCH10_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos) /*!< SCT MATCH10: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP11 -------------------------------------------
+#define SCT_CAP11_CAPn_L_Pos 0 /*!< SCT CAP11: CAPn_L Position */
+#define SCT_CAP11_CAPn_L_Msk (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos) /*!< SCT CAP11: CAPn_L Mask */
+#define SCT_CAP11_CAPn_H_Pos 16 /*!< SCT CAP11: CAPn_H Position */
+#define SCT_CAP11_CAPn_H_Msk (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos) /*!< SCT CAP11: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH11 ------------------------------------------
+#define SCT_MATCH11_MATCHn_L_Pos 0 /*!< SCT MATCH11: MATCHn_L Position */
+#define SCT_MATCH11_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos) /*!< SCT MATCH11: MATCHn_L Mask */
+#define SCT_MATCH11_MATCHn_H_Pos 16 /*!< SCT MATCH11: MATCHn_H Position */
+#define SCT_MATCH11_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos) /*!< SCT MATCH11: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH12 ------------------------------------------
+#define SCT_MATCH12_MATCHn_L_Pos 0 /*!< SCT MATCH12: MATCHn_L Position */
+#define SCT_MATCH12_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos) /*!< SCT MATCH12: MATCHn_L Mask */
+#define SCT_MATCH12_MATCHn_H_Pos 16 /*!< SCT MATCH12: MATCHn_H Position */
+#define SCT_MATCH12_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos) /*!< SCT MATCH12: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP12 -------------------------------------------
+#define SCT_CAP12_CAPn_L_Pos 0 /*!< SCT CAP12: CAPn_L Position */
+#define SCT_CAP12_CAPn_L_Msk (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos) /*!< SCT CAP12: CAPn_L Mask */
+#define SCT_CAP12_CAPn_H_Pos 16 /*!< SCT CAP12: CAPn_H Position */
+#define SCT_CAP12_CAPn_H_Msk (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos) /*!< SCT CAP12: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP13 -------------------------------------------
+#define SCT_CAP13_CAPn_L_Pos 0 /*!< SCT CAP13: CAPn_L Position */
+#define SCT_CAP13_CAPn_L_Msk (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos) /*!< SCT CAP13: CAPn_L Mask */
+#define SCT_CAP13_CAPn_H_Pos 16 /*!< SCT CAP13: CAPn_H Position */
+#define SCT_CAP13_CAPn_H_Msk (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos) /*!< SCT CAP13: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH13 ------------------------------------------
+#define SCT_MATCH13_MATCHn_L_Pos 0 /*!< SCT MATCH13: MATCHn_L Position */
+#define SCT_MATCH13_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos) /*!< SCT MATCH13: MATCHn_L Mask */
+#define SCT_MATCH13_MATCHn_H_Pos 16 /*!< SCT MATCH13: MATCHn_H Position */
+#define SCT_MATCH13_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos) /*!< SCT MATCH13: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH14 ------------------------------------------
+#define SCT_MATCH14_MATCHn_L_Pos 0 /*!< SCT MATCH14: MATCHn_L Position */
+#define SCT_MATCH14_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos) /*!< SCT MATCH14: MATCHn_L Mask */
+#define SCT_MATCH14_MATCHn_H_Pos 16 /*!< SCT MATCH14: MATCHn_H Position */
+#define SCT_MATCH14_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos) /*!< SCT MATCH14: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP14 -------------------------------------------
+#define SCT_CAP14_CAPn_L_Pos 0 /*!< SCT CAP14: CAPn_L Position */
+#define SCT_CAP14_CAPn_L_Msk (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos) /*!< SCT CAP14: CAPn_L Mask */
+#define SCT_CAP14_CAPn_H_Pos 16 /*!< SCT CAP14: CAPn_H Position */
+#define SCT_CAP14_CAPn_H_Msk (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos) /*!< SCT CAP14: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH15 ------------------------------------------
+#define SCT_MATCH15_MATCHn_L_Pos 0 /*!< SCT MATCH15: MATCHn_L Position */
+#define SCT_MATCH15_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos) /*!< SCT MATCH15: MATCHn_L Mask */
+#define SCT_MATCH15_MATCHn_H_Pos 16 /*!< SCT MATCH15: MATCHn_H Position */
+#define SCT_MATCH15_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos) /*!< SCT MATCH15: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP15 -------------------------------------------
+#define SCT_CAP15_CAPn_L_Pos 0 /*!< SCT CAP15: CAPn_L Position */
+#define SCT_CAP15_CAPn_L_Msk (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos) /*!< SCT CAP15: CAPn_L Mask */
+#define SCT_CAP15_CAPn_H_Pos 16 /*!< SCT CAP15: CAPn_H Position */
+#define SCT_CAP15_CAPn_H_Msk (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos) /*!< SCT CAP15: CAPn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL0 -----------------------------------------
+#define SCT_MATCHREL0_RELOADn_L_Pos 0 /*!< SCT MATCHREL0: RELOADn_L Position */
+#define SCT_MATCHREL0_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos) /*!< SCT MATCHREL0: RELOADn_L Mask */
+#define SCT_MATCHREL0_RELOADn_H_Pos 16 /*!< SCT MATCHREL0: RELOADn_H Position */
+#define SCT_MATCHREL0_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos) /*!< SCT MATCHREL0: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL0 ------------------------------------------
+#define SCT_CAPCTRL0_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL0: CAPCONn_L0 Position */
+#define SCT_CAPCTRL0_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos) /*!< SCT CAPCTRL0: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL0: CAPCONn_L1 Position */
+#define SCT_CAPCTRL0_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos) /*!< SCT CAPCTRL0: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL0: CAPCONn_L2 Position */
+#define SCT_CAPCTRL0_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos) /*!< SCT CAPCTRL0: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL0: CAPCONn_L3 Position */
+#define SCT_CAPCTRL0_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos) /*!< SCT CAPCTRL0: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL0: CAPCONn_L4 Position */
+#define SCT_CAPCTRL0_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos) /*!< SCT CAPCTRL0: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL0: CAPCONn_L5 Position */
+#define SCT_CAPCTRL0_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos) /*!< SCT CAPCTRL0: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL0: CAPCONn_L6 Position */
+#define SCT_CAPCTRL0_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos) /*!< SCT CAPCTRL0: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL0: CAPCONn_L7 Position */
+#define SCT_CAPCTRL0_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos) /*!< SCT CAPCTRL0: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL0: CAPCONn_L8 Position */
+#define SCT_CAPCTRL0_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos) /*!< SCT CAPCTRL0: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL0: CAPCONn_L9 Position */
+#define SCT_CAPCTRL0_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos) /*!< SCT CAPCTRL0: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL0: CAPCONn_L10 Position */
+#define SCT_CAPCTRL0_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos) /*!< SCT CAPCTRL0: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL0: CAPCONn_L11 Position */
+#define SCT_CAPCTRL0_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos) /*!< SCT CAPCTRL0: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL0: CAPCONn_L12 Position */
+#define SCT_CAPCTRL0_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos) /*!< SCT CAPCTRL0: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL0: CAPCONn_L13 Position */
+#define SCT_CAPCTRL0_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos) /*!< SCT CAPCTRL0: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL0: CAPCONn_L14 Position */
+#define SCT_CAPCTRL0_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos) /*!< SCT CAPCTRL0: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL0: CAPCONn_L15 Position */
+#define SCT_CAPCTRL0_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos) /*!< SCT CAPCTRL0: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL0_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL0: CAPCONn_H Position */
+#define SCT_CAPCTRL0_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos) /*!< SCT CAPCTRL0: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL1 -----------------------------------------
+#define SCT_MATCHREL1_RELOADn_L_Pos 0 /*!< SCT MATCHREL1: RELOADn_L Position */
+#define SCT_MATCHREL1_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos) /*!< SCT MATCHREL1: RELOADn_L Mask */
+#define SCT_MATCHREL1_RELOADn_H_Pos 16 /*!< SCT MATCHREL1: RELOADn_H Position */
+#define SCT_MATCHREL1_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos) /*!< SCT MATCHREL1: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL1 ------------------------------------------
+#define SCT_CAPCTRL1_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL1: CAPCONn_L0 Position */
+#define SCT_CAPCTRL1_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos) /*!< SCT CAPCTRL1: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL1: CAPCONn_L1 Position */
+#define SCT_CAPCTRL1_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos) /*!< SCT CAPCTRL1: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL1: CAPCONn_L2 Position */
+#define SCT_CAPCTRL1_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos) /*!< SCT CAPCTRL1: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL1: CAPCONn_L3 Position */
+#define SCT_CAPCTRL1_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos) /*!< SCT CAPCTRL1: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL1: CAPCONn_L4 Position */
+#define SCT_CAPCTRL1_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos) /*!< SCT CAPCTRL1: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL1: CAPCONn_L5 Position */
+#define SCT_CAPCTRL1_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos) /*!< SCT CAPCTRL1: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL1: CAPCONn_L6 Position */
+#define SCT_CAPCTRL1_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos) /*!< SCT CAPCTRL1: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL1: CAPCONn_L7 Position */
+#define SCT_CAPCTRL1_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos) /*!< SCT CAPCTRL1: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL1: CAPCONn_L8 Position */
+#define SCT_CAPCTRL1_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos) /*!< SCT CAPCTRL1: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL1: CAPCONn_L9 Position */
+#define SCT_CAPCTRL1_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos) /*!< SCT CAPCTRL1: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL1: CAPCONn_L10 Position */
+#define SCT_CAPCTRL1_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos) /*!< SCT CAPCTRL1: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL1: CAPCONn_L11 Position */
+#define SCT_CAPCTRL1_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos) /*!< SCT CAPCTRL1: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL1: CAPCONn_L12 Position */
+#define SCT_CAPCTRL1_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos) /*!< SCT CAPCTRL1: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL1: CAPCONn_L13 Position */
+#define SCT_CAPCTRL1_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos) /*!< SCT CAPCTRL1: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL1: CAPCONn_L14 Position */
+#define SCT_CAPCTRL1_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos) /*!< SCT CAPCTRL1: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL1: CAPCONn_L15 Position */
+#define SCT_CAPCTRL1_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos) /*!< SCT CAPCTRL1: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL1_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL1: CAPCONn_H Position */
+#define SCT_CAPCTRL1_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos) /*!< SCT CAPCTRL1: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL2 -----------------------------------------
+#define SCT_MATCHREL2_RELOADn_L_Pos 0 /*!< SCT MATCHREL2: RELOADn_L Position */
+#define SCT_MATCHREL2_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos) /*!< SCT MATCHREL2: RELOADn_L Mask */
+#define SCT_MATCHREL2_RELOADn_H_Pos 16 /*!< SCT MATCHREL2: RELOADn_H Position */
+#define SCT_MATCHREL2_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos) /*!< SCT MATCHREL2: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL2 ------------------------------------------
+#define SCT_CAPCTRL2_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL2: CAPCONn_L0 Position */
+#define SCT_CAPCTRL2_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos) /*!< SCT CAPCTRL2: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL2: CAPCONn_L1 Position */
+#define SCT_CAPCTRL2_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos) /*!< SCT CAPCTRL2: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL2: CAPCONn_L2 Position */
+#define SCT_CAPCTRL2_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos) /*!< SCT CAPCTRL2: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL2: CAPCONn_L3 Position */
+#define SCT_CAPCTRL2_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos) /*!< SCT CAPCTRL2: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL2: CAPCONn_L4 Position */
+#define SCT_CAPCTRL2_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos) /*!< SCT CAPCTRL2: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL2: CAPCONn_L5 Position */
+#define SCT_CAPCTRL2_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos) /*!< SCT CAPCTRL2: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL2: CAPCONn_L6 Position */
+#define SCT_CAPCTRL2_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos) /*!< SCT CAPCTRL2: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL2: CAPCONn_L7 Position */
+#define SCT_CAPCTRL2_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos) /*!< SCT CAPCTRL2: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL2: CAPCONn_L8 Position */
+#define SCT_CAPCTRL2_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos) /*!< SCT CAPCTRL2: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL2: CAPCONn_L9 Position */
+#define SCT_CAPCTRL2_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos) /*!< SCT CAPCTRL2: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL2: CAPCONn_L10 Position */
+#define SCT_CAPCTRL2_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos) /*!< SCT CAPCTRL2: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL2: CAPCONn_L11 Position */
+#define SCT_CAPCTRL2_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos) /*!< SCT CAPCTRL2: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL2: CAPCONn_L12 Position */
+#define SCT_CAPCTRL2_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos) /*!< SCT CAPCTRL2: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL2: CAPCONn_L13 Position */
+#define SCT_CAPCTRL2_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos) /*!< SCT CAPCTRL2: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL2: CAPCONn_L14 Position */
+#define SCT_CAPCTRL2_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos) /*!< SCT CAPCTRL2: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL2: CAPCONn_L15 Position */
+#define SCT_CAPCTRL2_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos) /*!< SCT CAPCTRL2: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL2_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL2: CAPCONn_H Position */
+#define SCT_CAPCTRL2_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos) /*!< SCT CAPCTRL2: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL3 -----------------------------------------
+#define SCT_MATCHREL3_RELOADn_L_Pos 0 /*!< SCT MATCHREL3: RELOADn_L Position */
+#define SCT_MATCHREL3_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos) /*!< SCT MATCHREL3: RELOADn_L Mask */
+#define SCT_MATCHREL3_RELOADn_H_Pos 16 /*!< SCT MATCHREL3: RELOADn_H Position */
+#define SCT_MATCHREL3_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos) /*!< SCT MATCHREL3: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL3 ------------------------------------------
+#define SCT_CAPCTRL3_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL3: CAPCONn_L0 Position */
+#define SCT_CAPCTRL3_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos) /*!< SCT CAPCTRL3: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL3: CAPCONn_L1 Position */
+#define SCT_CAPCTRL3_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos) /*!< SCT CAPCTRL3: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL3: CAPCONn_L2 Position */
+#define SCT_CAPCTRL3_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos) /*!< SCT CAPCTRL3: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL3: CAPCONn_L3 Position */
+#define SCT_CAPCTRL3_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos) /*!< SCT CAPCTRL3: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL3: CAPCONn_L4 Position */
+#define SCT_CAPCTRL3_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos) /*!< SCT CAPCTRL3: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL3: CAPCONn_L5 Position */
+#define SCT_CAPCTRL3_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos) /*!< SCT CAPCTRL3: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL3: CAPCONn_L6 Position */
+#define SCT_CAPCTRL3_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos) /*!< SCT CAPCTRL3: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL3: CAPCONn_L7 Position */
+#define SCT_CAPCTRL3_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos) /*!< SCT CAPCTRL3: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL3: CAPCONn_L8 Position */
+#define SCT_CAPCTRL3_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos) /*!< SCT CAPCTRL3: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL3: CAPCONn_L9 Position */
+#define SCT_CAPCTRL3_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos) /*!< SCT CAPCTRL3: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL3: CAPCONn_L10 Position */
+#define SCT_CAPCTRL3_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos) /*!< SCT CAPCTRL3: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL3: CAPCONn_L11 Position */
+#define SCT_CAPCTRL3_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos) /*!< SCT CAPCTRL3: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL3: CAPCONn_L12 Position */
+#define SCT_CAPCTRL3_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos) /*!< SCT CAPCTRL3: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL3: CAPCONn_L13 Position */
+#define SCT_CAPCTRL3_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos) /*!< SCT CAPCTRL3: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL3: CAPCONn_L14 Position */
+#define SCT_CAPCTRL3_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos) /*!< SCT CAPCTRL3: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL3: CAPCONn_L15 Position */
+#define SCT_CAPCTRL3_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos) /*!< SCT CAPCTRL3: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL3_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL3: CAPCONn_H Position */
+#define SCT_CAPCTRL3_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos) /*!< SCT CAPCTRL3: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL4 ------------------------------------------
+#define SCT_CAPCTRL4_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL4: CAPCONn_L0 Position */
+#define SCT_CAPCTRL4_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos) /*!< SCT CAPCTRL4: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL4: CAPCONn_L1 Position */
+#define SCT_CAPCTRL4_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos) /*!< SCT CAPCTRL4: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL4: CAPCONn_L2 Position */
+#define SCT_CAPCTRL4_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos) /*!< SCT CAPCTRL4: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL4: CAPCONn_L3 Position */
+#define SCT_CAPCTRL4_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos) /*!< SCT CAPCTRL4: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL4: CAPCONn_L4 Position */
+#define SCT_CAPCTRL4_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos) /*!< SCT CAPCTRL4: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL4: CAPCONn_L5 Position */
+#define SCT_CAPCTRL4_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos) /*!< SCT CAPCTRL4: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL4: CAPCONn_L6 Position */
+#define SCT_CAPCTRL4_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos) /*!< SCT CAPCTRL4: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL4: CAPCONn_L7 Position */
+#define SCT_CAPCTRL4_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos) /*!< SCT CAPCTRL4: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL4: CAPCONn_L8 Position */
+#define SCT_CAPCTRL4_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos) /*!< SCT CAPCTRL4: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL4: CAPCONn_L9 Position */
+#define SCT_CAPCTRL4_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos) /*!< SCT CAPCTRL4: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL4: CAPCONn_L10 Position */
+#define SCT_CAPCTRL4_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos) /*!< SCT CAPCTRL4: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL4: CAPCONn_L11 Position */
+#define SCT_CAPCTRL4_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos) /*!< SCT CAPCTRL4: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL4: CAPCONn_L12 Position */
+#define SCT_CAPCTRL4_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos) /*!< SCT CAPCTRL4: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL4: CAPCONn_L13 Position */
+#define SCT_CAPCTRL4_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos) /*!< SCT CAPCTRL4: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL4: CAPCONn_L14 Position */
+#define SCT_CAPCTRL4_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos) /*!< SCT CAPCTRL4: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL4: CAPCONn_L15 Position */
+#define SCT_CAPCTRL4_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos) /*!< SCT CAPCTRL4: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL4_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL4: CAPCONn_H Position */
+#define SCT_CAPCTRL4_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos) /*!< SCT CAPCTRL4: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL4 -----------------------------------------
+#define SCT_MATCHREL4_RELOADn_L_Pos 0 /*!< SCT MATCHREL4: RELOADn_L Position */
+#define SCT_MATCHREL4_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos) /*!< SCT MATCHREL4: RELOADn_L Mask */
+#define SCT_MATCHREL4_RELOADn_H_Pos 16 /*!< SCT MATCHREL4: RELOADn_H Position */
+#define SCT_MATCHREL4_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos) /*!< SCT MATCHREL4: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL5 ------------------------------------------
+#define SCT_CAPCTRL5_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL5: CAPCONn_L0 Position */
+#define SCT_CAPCTRL5_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos) /*!< SCT CAPCTRL5: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL5: CAPCONn_L1 Position */
+#define SCT_CAPCTRL5_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos) /*!< SCT CAPCTRL5: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL5: CAPCONn_L2 Position */
+#define SCT_CAPCTRL5_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos) /*!< SCT CAPCTRL5: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL5: CAPCONn_L3 Position */
+#define SCT_CAPCTRL5_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos) /*!< SCT CAPCTRL5: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL5: CAPCONn_L4 Position */
+#define SCT_CAPCTRL5_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos) /*!< SCT CAPCTRL5: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL5: CAPCONn_L5 Position */
+#define SCT_CAPCTRL5_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos) /*!< SCT CAPCTRL5: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL5: CAPCONn_L6 Position */
+#define SCT_CAPCTRL5_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos) /*!< SCT CAPCTRL5: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL5: CAPCONn_L7 Position */
+#define SCT_CAPCTRL5_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos) /*!< SCT CAPCTRL5: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL5: CAPCONn_L8 Position */
+#define SCT_CAPCTRL5_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos) /*!< SCT CAPCTRL5: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL5: CAPCONn_L9 Position */
+#define SCT_CAPCTRL5_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos) /*!< SCT CAPCTRL5: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL5: CAPCONn_L10 Position */
+#define SCT_CAPCTRL5_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos) /*!< SCT CAPCTRL5: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL5: CAPCONn_L11 Position */
+#define SCT_CAPCTRL5_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos) /*!< SCT CAPCTRL5: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL5: CAPCONn_L12 Position */
+#define SCT_CAPCTRL5_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos) /*!< SCT CAPCTRL5: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL5: CAPCONn_L13 Position */
+#define SCT_CAPCTRL5_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos) /*!< SCT CAPCTRL5: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL5: CAPCONn_L14 Position */
+#define SCT_CAPCTRL5_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos) /*!< SCT CAPCTRL5: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL5: CAPCONn_L15 Position */
+#define SCT_CAPCTRL5_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos) /*!< SCT CAPCTRL5: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL5_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL5: CAPCONn_H Position */
+#define SCT_CAPCTRL5_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos) /*!< SCT CAPCTRL5: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL5 -----------------------------------------
+#define SCT_MATCHREL5_RELOADn_L_Pos 0 /*!< SCT MATCHREL5: RELOADn_L Position */
+#define SCT_MATCHREL5_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos) /*!< SCT MATCHREL5: RELOADn_L Mask */
+#define SCT_MATCHREL5_RELOADn_H_Pos 16 /*!< SCT MATCHREL5: RELOADn_H Position */
+#define SCT_MATCHREL5_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos) /*!< SCT MATCHREL5: RELOADn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL6 -----------------------------------------
+#define SCT_MATCHREL6_RELOADn_L_Pos 0 /*!< SCT MATCHREL6: RELOADn_L Position */
+#define SCT_MATCHREL6_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos) /*!< SCT MATCHREL6: RELOADn_L Mask */
+#define SCT_MATCHREL6_RELOADn_H_Pos 16 /*!< SCT MATCHREL6: RELOADn_H Position */
+#define SCT_MATCHREL6_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos) /*!< SCT MATCHREL6: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL6 ------------------------------------------
+#define SCT_CAPCTRL6_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL6: CAPCONn_L0 Position */
+#define SCT_CAPCTRL6_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos) /*!< SCT CAPCTRL6: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL6: CAPCONn_L1 Position */
+#define SCT_CAPCTRL6_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos) /*!< SCT CAPCTRL6: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL6: CAPCONn_L2 Position */
+#define SCT_CAPCTRL6_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos) /*!< SCT CAPCTRL6: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL6: CAPCONn_L3 Position */
+#define SCT_CAPCTRL6_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos) /*!< SCT CAPCTRL6: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL6: CAPCONn_L4 Position */
+#define SCT_CAPCTRL6_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos) /*!< SCT CAPCTRL6: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL6: CAPCONn_L5 Position */
+#define SCT_CAPCTRL6_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos) /*!< SCT CAPCTRL6: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL6: CAPCONn_L6 Position */
+#define SCT_CAPCTRL6_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos) /*!< SCT CAPCTRL6: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL6: CAPCONn_L7 Position */
+#define SCT_CAPCTRL6_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos) /*!< SCT CAPCTRL6: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL6: CAPCONn_L8 Position */
+#define SCT_CAPCTRL6_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos) /*!< SCT CAPCTRL6: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL6: CAPCONn_L9 Position */
+#define SCT_CAPCTRL6_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos) /*!< SCT CAPCTRL6: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL6: CAPCONn_L10 Position */
+#define SCT_CAPCTRL6_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos) /*!< SCT CAPCTRL6: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL6: CAPCONn_L11 Position */
+#define SCT_CAPCTRL6_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos) /*!< SCT CAPCTRL6: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL6: CAPCONn_L12 Position */
+#define SCT_CAPCTRL6_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos) /*!< SCT CAPCTRL6: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL6: CAPCONn_L13 Position */
+#define SCT_CAPCTRL6_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos) /*!< SCT CAPCTRL6: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL6: CAPCONn_L14 Position */
+#define SCT_CAPCTRL6_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos) /*!< SCT CAPCTRL6: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL6: CAPCONn_L15 Position */
+#define SCT_CAPCTRL6_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos) /*!< SCT CAPCTRL6: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL6_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL6: CAPCONn_H Position */
+#define SCT_CAPCTRL6_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos) /*!< SCT CAPCTRL6: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL7 ------------------------------------------
+#define SCT_CAPCTRL7_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL7: CAPCONn_L0 Position */
+#define SCT_CAPCTRL7_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos) /*!< SCT CAPCTRL7: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL7: CAPCONn_L1 Position */
+#define SCT_CAPCTRL7_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos) /*!< SCT CAPCTRL7: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL7: CAPCONn_L2 Position */
+#define SCT_CAPCTRL7_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos) /*!< SCT CAPCTRL7: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL7: CAPCONn_L3 Position */
+#define SCT_CAPCTRL7_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos) /*!< SCT CAPCTRL7: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL7: CAPCONn_L4 Position */
+#define SCT_CAPCTRL7_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos) /*!< SCT CAPCTRL7: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL7: CAPCONn_L5 Position */
+#define SCT_CAPCTRL7_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos) /*!< SCT CAPCTRL7: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL7: CAPCONn_L6 Position */
+#define SCT_CAPCTRL7_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos) /*!< SCT CAPCTRL7: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL7: CAPCONn_L7 Position */
+#define SCT_CAPCTRL7_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos) /*!< SCT CAPCTRL7: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL7: CAPCONn_L8 Position */
+#define SCT_CAPCTRL7_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos) /*!< SCT CAPCTRL7: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL7: CAPCONn_L9 Position */
+#define SCT_CAPCTRL7_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos) /*!< SCT CAPCTRL7: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL7: CAPCONn_L10 Position */
+#define SCT_CAPCTRL7_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos) /*!< SCT CAPCTRL7: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL7: CAPCONn_L11 Position */
+#define SCT_CAPCTRL7_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos) /*!< SCT CAPCTRL7: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL7: CAPCONn_L12 Position */
+#define SCT_CAPCTRL7_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos) /*!< SCT CAPCTRL7: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL7: CAPCONn_L13 Position */
+#define SCT_CAPCTRL7_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos) /*!< SCT CAPCTRL7: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL7: CAPCONn_L14 Position */
+#define SCT_CAPCTRL7_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos) /*!< SCT CAPCTRL7: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL7: CAPCONn_L15 Position */
+#define SCT_CAPCTRL7_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos) /*!< SCT CAPCTRL7: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL7_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL7: CAPCONn_H Position */
+#define SCT_CAPCTRL7_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos) /*!< SCT CAPCTRL7: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL7 -----------------------------------------
+#define SCT_MATCHREL7_RELOADn_L_Pos 0 /*!< SCT MATCHREL7: RELOADn_L Position */
+#define SCT_MATCHREL7_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos) /*!< SCT MATCHREL7: RELOADn_L Mask */
+#define SCT_MATCHREL7_RELOADn_H_Pos 16 /*!< SCT MATCHREL7: RELOADn_H Position */
+#define SCT_MATCHREL7_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos) /*!< SCT MATCHREL7: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL8 ------------------------------------------
+#define SCT_CAPCTRL8_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL8: CAPCONn_L0 Position */
+#define SCT_CAPCTRL8_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos) /*!< SCT CAPCTRL8: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL8: CAPCONn_L1 Position */
+#define SCT_CAPCTRL8_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos) /*!< SCT CAPCTRL8: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL8: CAPCONn_L2 Position */
+#define SCT_CAPCTRL8_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos) /*!< SCT CAPCTRL8: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL8: CAPCONn_L3 Position */
+#define SCT_CAPCTRL8_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos) /*!< SCT CAPCTRL8: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL8: CAPCONn_L4 Position */
+#define SCT_CAPCTRL8_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos) /*!< SCT CAPCTRL8: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL8: CAPCONn_L5 Position */
+#define SCT_CAPCTRL8_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos) /*!< SCT CAPCTRL8: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL8: CAPCONn_L6 Position */
+#define SCT_CAPCTRL8_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos) /*!< SCT CAPCTRL8: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL8: CAPCONn_L7 Position */
+#define SCT_CAPCTRL8_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos) /*!< SCT CAPCTRL8: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL8: CAPCONn_L8 Position */
+#define SCT_CAPCTRL8_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos) /*!< SCT CAPCTRL8: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL8: CAPCONn_L9 Position */
+#define SCT_CAPCTRL8_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos) /*!< SCT CAPCTRL8: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL8: CAPCONn_L10 Position */
+#define SCT_CAPCTRL8_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos) /*!< SCT CAPCTRL8: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL8: CAPCONn_L11 Position */
+#define SCT_CAPCTRL8_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos) /*!< SCT CAPCTRL8: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL8: CAPCONn_L12 Position */
+#define SCT_CAPCTRL8_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos) /*!< SCT CAPCTRL8: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL8: CAPCONn_L13 Position */
+#define SCT_CAPCTRL8_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos) /*!< SCT CAPCTRL8: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL8: CAPCONn_L14 Position */
+#define SCT_CAPCTRL8_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos) /*!< SCT CAPCTRL8: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL8: CAPCONn_L15 Position */
+#define SCT_CAPCTRL8_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos) /*!< SCT CAPCTRL8: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL8_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL8: CAPCONn_H Position */
+#define SCT_CAPCTRL8_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos) /*!< SCT CAPCTRL8: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL8 -----------------------------------------
+#define SCT_MATCHREL8_RELOADn_L_Pos 0 /*!< SCT MATCHREL8: RELOADn_L Position */
+#define SCT_MATCHREL8_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos) /*!< SCT MATCHREL8: RELOADn_L Mask */
+#define SCT_MATCHREL8_RELOADn_H_Pos 16 /*!< SCT MATCHREL8: RELOADn_H Position */
+#define SCT_MATCHREL8_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos) /*!< SCT MATCHREL8: RELOADn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL9 -----------------------------------------
+#define SCT_MATCHREL9_RELOADn_L_Pos 0 /*!< SCT MATCHREL9: RELOADn_L Position */
+#define SCT_MATCHREL9_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos) /*!< SCT MATCHREL9: RELOADn_L Mask */
+#define SCT_MATCHREL9_RELOADn_H_Pos 16 /*!< SCT MATCHREL9: RELOADn_H Position */
+#define SCT_MATCHREL9_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos) /*!< SCT MATCHREL9: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL9 ------------------------------------------
+#define SCT_CAPCTRL9_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL9: CAPCONn_L0 Position */
+#define SCT_CAPCTRL9_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos) /*!< SCT CAPCTRL9: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL9: CAPCONn_L1 Position */
+#define SCT_CAPCTRL9_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos) /*!< SCT CAPCTRL9: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL9: CAPCONn_L2 Position */
+#define SCT_CAPCTRL9_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos) /*!< SCT CAPCTRL9: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL9: CAPCONn_L3 Position */
+#define SCT_CAPCTRL9_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos) /*!< SCT CAPCTRL9: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL9: CAPCONn_L4 Position */
+#define SCT_CAPCTRL9_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos) /*!< SCT CAPCTRL9: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL9: CAPCONn_L5 Position */
+#define SCT_CAPCTRL9_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos) /*!< SCT CAPCTRL9: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL9: CAPCONn_L6 Position */
+#define SCT_CAPCTRL9_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos) /*!< SCT CAPCTRL9: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL9: CAPCONn_L7 Position */
+#define SCT_CAPCTRL9_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos) /*!< SCT CAPCTRL9: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL9: CAPCONn_L8 Position */
+#define SCT_CAPCTRL9_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos) /*!< SCT CAPCTRL9: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL9: CAPCONn_L9 Position */
+#define SCT_CAPCTRL9_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos) /*!< SCT CAPCTRL9: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL9: CAPCONn_L10 Position */
+#define SCT_CAPCTRL9_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos) /*!< SCT CAPCTRL9: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL9: CAPCONn_L11 Position */
+#define SCT_CAPCTRL9_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos) /*!< SCT CAPCTRL9: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL9: CAPCONn_L12 Position */
+#define SCT_CAPCTRL9_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos) /*!< SCT CAPCTRL9: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL9: CAPCONn_L13 Position */
+#define SCT_CAPCTRL9_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos) /*!< SCT CAPCTRL9: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL9: CAPCONn_L14 Position */
+#define SCT_CAPCTRL9_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos) /*!< SCT CAPCTRL9: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL9: CAPCONn_L15 Position */
+#define SCT_CAPCTRL9_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos) /*!< SCT CAPCTRL9: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL9_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL9: CAPCONn_H Position */
+#define SCT_CAPCTRL9_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos) /*!< SCT CAPCTRL9: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL10 -----------------------------------------
+#define SCT_MATCHREL10_RELOADn_L_Pos 0 /*!< SCT MATCHREL10: RELOADn_L Position */
+#define SCT_MATCHREL10_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos) /*!< SCT MATCHREL10: RELOADn_L Mask */
+#define SCT_MATCHREL10_RELOADn_H_Pos 16 /*!< SCT MATCHREL10: RELOADn_H Position */
+#define SCT_MATCHREL10_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos) /*!< SCT MATCHREL10: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL10 -----------------------------------------
+#define SCT_CAPCTRL10_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL10: CAPCONn_L0 Position */
+#define SCT_CAPCTRL10_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos) /*!< SCT CAPCTRL10: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL10: CAPCONn_L1 Position */
+#define SCT_CAPCTRL10_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos) /*!< SCT CAPCTRL10: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL10: CAPCONn_L2 Position */
+#define SCT_CAPCTRL10_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos) /*!< SCT CAPCTRL10: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL10: CAPCONn_L3 Position */
+#define SCT_CAPCTRL10_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos) /*!< SCT CAPCTRL10: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL10: CAPCONn_L4 Position */
+#define SCT_CAPCTRL10_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos) /*!< SCT CAPCTRL10: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL10: CAPCONn_L5 Position */
+#define SCT_CAPCTRL10_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos) /*!< SCT CAPCTRL10: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL10: CAPCONn_L6 Position */
+#define SCT_CAPCTRL10_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos) /*!< SCT CAPCTRL10: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL10: CAPCONn_L7 Position */
+#define SCT_CAPCTRL10_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos) /*!< SCT CAPCTRL10: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL10: CAPCONn_L8 Position */
+#define SCT_CAPCTRL10_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos) /*!< SCT CAPCTRL10: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL10: CAPCONn_L9 Position */
+#define SCT_CAPCTRL10_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos) /*!< SCT CAPCTRL10: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL10: CAPCONn_L10 Position */
+#define SCT_CAPCTRL10_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos) /*!< SCT CAPCTRL10: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL10: CAPCONn_L11 Position */
+#define SCT_CAPCTRL10_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos) /*!< SCT CAPCTRL10: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL10: CAPCONn_L12 Position */
+#define SCT_CAPCTRL10_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos) /*!< SCT CAPCTRL10: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL10: CAPCONn_L13 Position */
+#define SCT_CAPCTRL10_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos) /*!< SCT CAPCTRL10: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL10: CAPCONn_L14 Position */
+#define SCT_CAPCTRL10_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos) /*!< SCT CAPCTRL10: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL10: CAPCONn_L15 Position */
+#define SCT_CAPCTRL10_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos) /*!< SCT CAPCTRL10: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL10_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL10: CAPCONn_H Position */
+#define SCT_CAPCTRL10_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos) /*!< SCT CAPCTRL10: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL11 -----------------------------------------
+#define SCT_MATCHREL11_RELOADn_L_Pos 0 /*!< SCT MATCHREL11: RELOADn_L Position */
+#define SCT_MATCHREL11_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos) /*!< SCT MATCHREL11: RELOADn_L Mask */
+#define SCT_MATCHREL11_RELOADn_H_Pos 16 /*!< SCT MATCHREL11: RELOADn_H Position */
+#define SCT_MATCHREL11_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos) /*!< SCT MATCHREL11: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL11 -----------------------------------------
+#define SCT_CAPCTRL11_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL11: CAPCONn_L0 Position */
+#define SCT_CAPCTRL11_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos) /*!< SCT CAPCTRL11: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL11: CAPCONn_L1 Position */
+#define SCT_CAPCTRL11_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos) /*!< SCT CAPCTRL11: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL11: CAPCONn_L2 Position */
+#define SCT_CAPCTRL11_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos) /*!< SCT CAPCTRL11: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL11: CAPCONn_L3 Position */
+#define SCT_CAPCTRL11_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos) /*!< SCT CAPCTRL11: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL11: CAPCONn_L4 Position */
+#define SCT_CAPCTRL11_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos) /*!< SCT CAPCTRL11: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL11: CAPCONn_L5 Position */
+#define SCT_CAPCTRL11_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos) /*!< SCT CAPCTRL11: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL11: CAPCONn_L6 Position */
+#define SCT_CAPCTRL11_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos) /*!< SCT CAPCTRL11: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL11: CAPCONn_L7 Position */
+#define SCT_CAPCTRL11_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos) /*!< SCT CAPCTRL11: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL11: CAPCONn_L8 Position */
+#define SCT_CAPCTRL11_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos) /*!< SCT CAPCTRL11: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL11: CAPCONn_L9 Position */
+#define SCT_CAPCTRL11_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos) /*!< SCT CAPCTRL11: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL11: CAPCONn_L10 Position */
+#define SCT_CAPCTRL11_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos) /*!< SCT CAPCTRL11: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL11: CAPCONn_L11 Position */
+#define SCT_CAPCTRL11_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos) /*!< SCT CAPCTRL11: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL11: CAPCONn_L12 Position */
+#define SCT_CAPCTRL11_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos) /*!< SCT CAPCTRL11: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL11: CAPCONn_L13 Position */
+#define SCT_CAPCTRL11_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos) /*!< SCT CAPCTRL11: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL11: CAPCONn_L14 Position */
+#define SCT_CAPCTRL11_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos) /*!< SCT CAPCTRL11: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL11: CAPCONn_L15 Position */
+#define SCT_CAPCTRL11_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos) /*!< SCT CAPCTRL11: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL11_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL11: CAPCONn_H Position */
+#define SCT_CAPCTRL11_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos) /*!< SCT CAPCTRL11: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL12 -----------------------------------------
+#define SCT_MATCHREL12_RELOADn_L_Pos 0 /*!< SCT MATCHREL12: RELOADn_L Position */
+#define SCT_MATCHREL12_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos) /*!< SCT MATCHREL12: RELOADn_L Mask */
+#define SCT_MATCHREL12_RELOADn_H_Pos 16 /*!< SCT MATCHREL12: RELOADn_H Position */
+#define SCT_MATCHREL12_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos) /*!< SCT MATCHREL12: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL12 -----------------------------------------
+#define SCT_CAPCTRL12_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL12: CAPCONn_L0 Position */
+#define SCT_CAPCTRL12_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos) /*!< SCT CAPCTRL12: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL12: CAPCONn_L1 Position */
+#define SCT_CAPCTRL12_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos) /*!< SCT CAPCTRL12: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL12: CAPCONn_L2 Position */
+#define SCT_CAPCTRL12_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos) /*!< SCT CAPCTRL12: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL12: CAPCONn_L3 Position */
+#define SCT_CAPCTRL12_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos) /*!< SCT CAPCTRL12: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL12: CAPCONn_L4 Position */
+#define SCT_CAPCTRL12_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos) /*!< SCT CAPCTRL12: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL12: CAPCONn_L5 Position */
+#define SCT_CAPCTRL12_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos) /*!< SCT CAPCTRL12: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL12: CAPCONn_L6 Position */
+#define SCT_CAPCTRL12_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos) /*!< SCT CAPCTRL12: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL12: CAPCONn_L7 Position */
+#define SCT_CAPCTRL12_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos) /*!< SCT CAPCTRL12: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL12: CAPCONn_L8 Position */
+#define SCT_CAPCTRL12_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos) /*!< SCT CAPCTRL12: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL12: CAPCONn_L9 Position */
+#define SCT_CAPCTRL12_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos) /*!< SCT CAPCTRL12: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL12: CAPCONn_L10 Position */
+#define SCT_CAPCTRL12_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos) /*!< SCT CAPCTRL12: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL12: CAPCONn_L11 Position */
+#define SCT_CAPCTRL12_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos) /*!< SCT CAPCTRL12: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL12: CAPCONn_L12 Position */
+#define SCT_CAPCTRL12_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos) /*!< SCT CAPCTRL12: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL12: CAPCONn_L13 Position */
+#define SCT_CAPCTRL12_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos) /*!< SCT CAPCTRL12: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL12: CAPCONn_L14 Position */
+#define SCT_CAPCTRL12_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos) /*!< SCT CAPCTRL12: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL12: CAPCONn_L15 Position */
+#define SCT_CAPCTRL12_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos) /*!< SCT CAPCTRL12: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL12_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL12: CAPCONn_H Position */
+#define SCT_CAPCTRL12_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos) /*!< SCT CAPCTRL12: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL13 -----------------------------------------
+#define SCT_MATCHREL13_RELOADn_L_Pos 0 /*!< SCT MATCHREL13: RELOADn_L Position */
+#define SCT_MATCHREL13_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos) /*!< SCT MATCHREL13: RELOADn_L Mask */
+#define SCT_MATCHREL13_RELOADn_H_Pos 16 /*!< SCT MATCHREL13: RELOADn_H Position */
+#define SCT_MATCHREL13_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos) /*!< SCT MATCHREL13: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL13 -----------------------------------------
+#define SCT_CAPCTRL13_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL13: CAPCONn_L0 Position */
+#define SCT_CAPCTRL13_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos) /*!< SCT CAPCTRL13: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL13: CAPCONn_L1 Position */
+#define SCT_CAPCTRL13_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos) /*!< SCT CAPCTRL13: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL13: CAPCONn_L2 Position */
+#define SCT_CAPCTRL13_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos) /*!< SCT CAPCTRL13: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL13: CAPCONn_L3 Position */
+#define SCT_CAPCTRL13_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos) /*!< SCT CAPCTRL13: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL13: CAPCONn_L4 Position */
+#define SCT_CAPCTRL13_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos) /*!< SCT CAPCTRL13: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL13: CAPCONn_L5 Position */
+#define SCT_CAPCTRL13_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos) /*!< SCT CAPCTRL13: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL13: CAPCONn_L6 Position */
+#define SCT_CAPCTRL13_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos) /*!< SCT CAPCTRL13: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL13: CAPCONn_L7 Position */
+#define SCT_CAPCTRL13_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos) /*!< SCT CAPCTRL13: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL13: CAPCONn_L8 Position */
+#define SCT_CAPCTRL13_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos) /*!< SCT CAPCTRL13: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL13: CAPCONn_L9 Position */
+#define SCT_CAPCTRL13_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos) /*!< SCT CAPCTRL13: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL13: CAPCONn_L10 Position */
+#define SCT_CAPCTRL13_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos) /*!< SCT CAPCTRL13: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL13: CAPCONn_L11 Position */
+#define SCT_CAPCTRL13_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos) /*!< SCT CAPCTRL13: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL13: CAPCONn_L12 Position */
+#define SCT_CAPCTRL13_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos) /*!< SCT CAPCTRL13: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL13: CAPCONn_L13 Position */
+#define SCT_CAPCTRL13_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos) /*!< SCT CAPCTRL13: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL13: CAPCONn_L14 Position */
+#define SCT_CAPCTRL13_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos) /*!< SCT CAPCTRL13: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL13: CAPCONn_L15 Position */
+#define SCT_CAPCTRL13_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos) /*!< SCT CAPCTRL13: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL13_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL13: CAPCONn_H Position */
+#define SCT_CAPCTRL13_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos) /*!< SCT CAPCTRL13: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL14 -----------------------------------------
+#define SCT_MATCHREL14_RELOADn_L_Pos 0 /*!< SCT MATCHREL14: RELOADn_L Position */
+#define SCT_MATCHREL14_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos) /*!< SCT MATCHREL14: RELOADn_L Mask */
+#define SCT_MATCHREL14_RELOADn_H_Pos 16 /*!< SCT MATCHREL14: RELOADn_H Position */
+#define SCT_MATCHREL14_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos) /*!< SCT MATCHREL14: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL14 -----------------------------------------
+#define SCT_CAPCTRL14_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL14: CAPCONn_L0 Position */
+#define SCT_CAPCTRL14_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos) /*!< SCT CAPCTRL14: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL14: CAPCONn_L1 Position */
+#define SCT_CAPCTRL14_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos) /*!< SCT CAPCTRL14: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL14: CAPCONn_L2 Position */
+#define SCT_CAPCTRL14_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos) /*!< SCT CAPCTRL14: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL14: CAPCONn_L3 Position */
+#define SCT_CAPCTRL14_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos) /*!< SCT CAPCTRL14: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL14: CAPCONn_L4 Position */
+#define SCT_CAPCTRL14_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos) /*!< SCT CAPCTRL14: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL14: CAPCONn_L5 Position */
+#define SCT_CAPCTRL14_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos) /*!< SCT CAPCTRL14: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL14: CAPCONn_L6 Position */
+#define SCT_CAPCTRL14_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos) /*!< SCT CAPCTRL14: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL14: CAPCONn_L7 Position */
+#define SCT_CAPCTRL14_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos) /*!< SCT CAPCTRL14: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL14: CAPCONn_L8 Position */
+#define SCT_CAPCTRL14_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos) /*!< SCT CAPCTRL14: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL14: CAPCONn_L9 Position */
+#define SCT_CAPCTRL14_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos) /*!< SCT CAPCTRL14: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL14: CAPCONn_L10 Position */
+#define SCT_CAPCTRL14_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos) /*!< SCT CAPCTRL14: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL14: CAPCONn_L11 Position */
+#define SCT_CAPCTRL14_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos) /*!< SCT CAPCTRL14: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL14: CAPCONn_L12 Position */
+#define SCT_CAPCTRL14_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos) /*!< SCT CAPCTRL14: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL14: CAPCONn_L13 Position */
+#define SCT_CAPCTRL14_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos) /*!< SCT CAPCTRL14: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL14: CAPCONn_L14 Position */
+#define SCT_CAPCTRL14_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos) /*!< SCT CAPCTRL14: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL14: CAPCONn_L15 Position */
+#define SCT_CAPCTRL14_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos) /*!< SCT CAPCTRL14: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL14_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL14: CAPCONn_H Position */
+#define SCT_CAPCTRL14_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos) /*!< SCT CAPCTRL14: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL15 -----------------------------------------
+#define SCT_MATCHREL15_RELOADn_L_Pos 0 /*!< SCT MATCHREL15: RELOADn_L Position */
+#define SCT_MATCHREL15_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos) /*!< SCT MATCHREL15: RELOADn_L Mask */
+#define SCT_MATCHREL15_RELOADn_H_Pos 16 /*!< SCT MATCHREL15: RELOADn_H Position */
+#define SCT_MATCHREL15_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos) /*!< SCT MATCHREL15: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL15 -----------------------------------------
+#define SCT_CAPCTRL15_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL15: CAPCONn_L0 Position */
+#define SCT_CAPCTRL15_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos) /*!< SCT CAPCTRL15: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL15: CAPCONn_L1 Position */
+#define SCT_CAPCTRL15_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos) /*!< SCT CAPCTRL15: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL15: CAPCONn_L2 Position */
+#define SCT_CAPCTRL15_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos) /*!< SCT CAPCTRL15: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL15: CAPCONn_L3 Position */
+#define SCT_CAPCTRL15_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos) /*!< SCT CAPCTRL15: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL15: CAPCONn_L4 Position */
+#define SCT_CAPCTRL15_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos) /*!< SCT CAPCTRL15: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL15: CAPCONn_L5 Position */
+#define SCT_CAPCTRL15_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos) /*!< SCT CAPCTRL15: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL15: CAPCONn_L6 Position */
+#define SCT_CAPCTRL15_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos) /*!< SCT CAPCTRL15: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL15: CAPCONn_L7 Position */
+#define SCT_CAPCTRL15_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos) /*!< SCT CAPCTRL15: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL15: CAPCONn_L8 Position */
+#define SCT_CAPCTRL15_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos) /*!< SCT CAPCTRL15: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL15: CAPCONn_L9 Position */
+#define SCT_CAPCTRL15_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos) /*!< SCT CAPCTRL15: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL15: CAPCONn_L10 Position */
+#define SCT_CAPCTRL15_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos) /*!< SCT CAPCTRL15: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL15: CAPCONn_L11 Position */
+#define SCT_CAPCTRL15_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos) /*!< SCT CAPCTRL15: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL15: CAPCONn_L12 Position */
+#define SCT_CAPCTRL15_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos) /*!< SCT CAPCTRL15: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL15: CAPCONn_L13 Position */
+#define SCT_CAPCTRL15_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos) /*!< SCT CAPCTRL15: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL15: CAPCONn_L14 Position */
+#define SCT_CAPCTRL15_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos) /*!< SCT CAPCTRL15: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL15: CAPCONn_L15 Position */
+#define SCT_CAPCTRL15_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos) /*!< SCT CAPCTRL15: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL15_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL15: CAPCONn_H Position */
+#define SCT_CAPCTRL15_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos) /*!< SCT CAPCTRL15: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK0 ----------------------------------------
+#define SCT_EVSTATEMSK0_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL0 ------------------------------------------
+#define SCT_EVCTRL0_MATCHSEL_Pos 0 /*!< SCT EVCTRL0: MATCHSEL Position */
+#define SCT_EVCTRL0_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos) /*!< SCT EVCTRL0: MATCHSEL Mask */
+#define SCT_EVCTRL0_HEVENT_Pos 4 /*!< SCT EVCTRL0: HEVENT Position */
+#define SCT_EVCTRL0_HEVENT_Msk (0x01UL << SCT_EVCTRL0_HEVENT_Pos) /*!< SCT EVCTRL0: HEVENT Mask */
+#define SCT_EVCTRL0_OUTSEL_Pos 5 /*!< SCT EVCTRL0: OUTSEL Position */
+#define SCT_EVCTRL0_OUTSEL_Msk (0x01UL << SCT_EVCTRL0_OUTSEL_Pos) /*!< SCT EVCTRL0: OUTSEL Mask */
+#define SCT_EVCTRL0_IOSEL_Pos 6 /*!< SCT EVCTRL0: IOSEL Position */
+#define SCT_EVCTRL0_IOSEL_Msk (0x0fUL << SCT_EVCTRL0_IOSEL_Pos) /*!< SCT EVCTRL0: IOSEL Mask */
+#define SCT_EVCTRL0_IOCOND_Pos 10 /*!< SCT EVCTRL0: IOCOND Position */
+#define SCT_EVCTRL0_IOCOND_Msk (0x03UL << SCT_EVCTRL0_IOCOND_Pos) /*!< SCT EVCTRL0: IOCOND Mask */
+#define SCT_EVCTRL0_COMBMODE_Pos 12 /*!< SCT EVCTRL0: COMBMODE Position */
+#define SCT_EVCTRL0_COMBMODE_Msk (0x03UL << SCT_EVCTRL0_COMBMODE_Pos) /*!< SCT EVCTRL0: COMBMODE Mask */
+#define SCT_EVCTRL0_STATELD_Pos 14 /*!< SCT EVCTRL0: STATELD Position */
+#define SCT_EVCTRL0_STATELD_Msk (0x01UL << SCT_EVCTRL0_STATELD_Pos) /*!< SCT EVCTRL0: STATELD Mask */
+#define SCT_EVCTRL0_STATEV_Pos 15 /*!< SCT EVCTRL0: STATEV Position */
+#define SCT_EVCTRL0_STATEV_Msk (0x1fUL << SCT_EVCTRL0_STATEV_Pos) /*!< SCT EVCTRL0: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK1 ----------------------------------------
+#define SCT_EVSTATEMSK1_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL1 ------------------------------------------
+#define SCT_EVCTRL1_MATCHSEL_Pos 0 /*!< SCT EVCTRL1: MATCHSEL Position */
+#define SCT_EVCTRL1_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos) /*!< SCT EVCTRL1: MATCHSEL Mask */
+#define SCT_EVCTRL1_HEVENT_Pos 4 /*!< SCT EVCTRL1: HEVENT Position */
+#define SCT_EVCTRL1_HEVENT_Msk (0x01UL << SCT_EVCTRL1_HEVENT_Pos) /*!< SCT EVCTRL1: HEVENT Mask */
+#define SCT_EVCTRL1_OUTSEL_Pos 5 /*!< SCT EVCTRL1: OUTSEL Position */
+#define SCT_EVCTRL1_OUTSEL_Msk (0x01UL << SCT_EVCTRL1_OUTSEL_Pos) /*!< SCT EVCTRL1: OUTSEL Mask */
+#define SCT_EVCTRL1_IOSEL_Pos 6 /*!< SCT EVCTRL1: IOSEL Position */
+#define SCT_EVCTRL1_IOSEL_Msk (0x0fUL << SCT_EVCTRL1_IOSEL_Pos) /*!< SCT EVCTRL1: IOSEL Mask */
+#define SCT_EVCTRL1_IOCOND_Pos 10 /*!< SCT EVCTRL1: IOCOND Position */
+#define SCT_EVCTRL1_IOCOND_Msk (0x03UL << SCT_EVCTRL1_IOCOND_Pos) /*!< SCT EVCTRL1: IOCOND Mask */
+#define SCT_EVCTRL1_COMBMODE_Pos 12 /*!< SCT EVCTRL1: COMBMODE Position */
+#define SCT_EVCTRL1_COMBMODE_Msk (0x03UL << SCT_EVCTRL1_COMBMODE_Pos) /*!< SCT EVCTRL1: COMBMODE Mask */
+#define SCT_EVCTRL1_STATELD_Pos 14 /*!< SCT EVCTRL1: STATELD Position */
+#define SCT_EVCTRL1_STATELD_Msk (0x01UL << SCT_EVCTRL1_STATELD_Pos) /*!< SCT EVCTRL1: STATELD Mask */
+#define SCT_EVCTRL1_STATEV_Pos 15 /*!< SCT EVCTRL1: STATEV Position */
+#define SCT_EVCTRL1_STATEV_Msk (0x1fUL << SCT_EVCTRL1_STATEV_Pos) /*!< SCT EVCTRL1: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK2 ----------------------------------------
+#define SCT_EVSTATEMSK2_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL2 ------------------------------------------
+#define SCT_EVCTRL2_MATCHSEL_Pos 0 /*!< SCT EVCTRL2: MATCHSEL Position */
+#define SCT_EVCTRL2_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos) /*!< SCT EVCTRL2: MATCHSEL Mask */
+#define SCT_EVCTRL2_HEVENT_Pos 4 /*!< SCT EVCTRL2: HEVENT Position */
+#define SCT_EVCTRL2_HEVENT_Msk (0x01UL << SCT_EVCTRL2_HEVENT_Pos) /*!< SCT EVCTRL2: HEVENT Mask */
+#define SCT_EVCTRL2_OUTSEL_Pos 5 /*!< SCT EVCTRL2: OUTSEL Position */
+#define SCT_EVCTRL2_OUTSEL_Msk (0x01UL << SCT_EVCTRL2_OUTSEL_Pos) /*!< SCT EVCTRL2: OUTSEL Mask */
+#define SCT_EVCTRL2_IOSEL_Pos 6 /*!< SCT EVCTRL2: IOSEL Position */
+#define SCT_EVCTRL2_IOSEL_Msk (0x0fUL << SCT_EVCTRL2_IOSEL_Pos) /*!< SCT EVCTRL2: IOSEL Mask */
+#define SCT_EVCTRL2_IOCOND_Pos 10 /*!< SCT EVCTRL2: IOCOND Position */
+#define SCT_EVCTRL2_IOCOND_Msk (0x03UL << SCT_EVCTRL2_IOCOND_Pos) /*!< SCT EVCTRL2: IOCOND Mask */
+#define SCT_EVCTRL2_COMBMODE_Pos 12 /*!< SCT EVCTRL2: COMBMODE Position */
+#define SCT_EVCTRL2_COMBMODE_Msk (0x03UL << SCT_EVCTRL2_COMBMODE_Pos) /*!< SCT EVCTRL2: COMBMODE Mask */
+#define SCT_EVCTRL2_STATELD_Pos 14 /*!< SCT EVCTRL2: STATELD Position */
+#define SCT_EVCTRL2_STATELD_Msk (0x01UL << SCT_EVCTRL2_STATELD_Pos) /*!< SCT EVCTRL2: STATELD Mask */
+#define SCT_EVCTRL2_STATEV_Pos 15 /*!< SCT EVCTRL2: STATEV Position */
+#define SCT_EVCTRL2_STATEV_Msk (0x1fUL << SCT_EVCTRL2_STATEV_Pos) /*!< SCT EVCTRL2: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK3 ----------------------------------------
+#define SCT_EVSTATEMSK3_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL3 ------------------------------------------
+#define SCT_EVCTRL3_MATCHSEL_Pos 0 /*!< SCT EVCTRL3: MATCHSEL Position */
+#define SCT_EVCTRL3_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos) /*!< SCT EVCTRL3: MATCHSEL Mask */
+#define SCT_EVCTRL3_HEVENT_Pos 4 /*!< SCT EVCTRL3: HEVENT Position */
+#define SCT_EVCTRL3_HEVENT_Msk (0x01UL << SCT_EVCTRL3_HEVENT_Pos) /*!< SCT EVCTRL3: HEVENT Mask */
+#define SCT_EVCTRL3_OUTSEL_Pos 5 /*!< SCT EVCTRL3: OUTSEL Position */
+#define SCT_EVCTRL3_OUTSEL_Msk (0x01UL << SCT_EVCTRL3_OUTSEL_Pos) /*!< SCT EVCTRL3: OUTSEL Mask */
+#define SCT_EVCTRL3_IOSEL_Pos 6 /*!< SCT EVCTRL3: IOSEL Position */
+#define SCT_EVCTRL3_IOSEL_Msk (0x0fUL << SCT_EVCTRL3_IOSEL_Pos) /*!< SCT EVCTRL3: IOSEL Mask */
+#define SCT_EVCTRL3_IOCOND_Pos 10 /*!< SCT EVCTRL3: IOCOND Position */
+#define SCT_EVCTRL3_IOCOND_Msk (0x03UL << SCT_EVCTRL3_IOCOND_Pos) /*!< SCT EVCTRL3: IOCOND Mask */
+#define SCT_EVCTRL3_COMBMODE_Pos 12 /*!< SCT EVCTRL3: COMBMODE Position */
+#define SCT_EVCTRL3_COMBMODE_Msk (0x03UL << SCT_EVCTRL3_COMBMODE_Pos) /*!< SCT EVCTRL3: COMBMODE Mask */
+#define SCT_EVCTRL3_STATELD_Pos 14 /*!< SCT EVCTRL3: STATELD Position */
+#define SCT_EVCTRL3_STATELD_Msk (0x01UL << SCT_EVCTRL3_STATELD_Pos) /*!< SCT EVCTRL3: STATELD Mask */
+#define SCT_EVCTRL3_STATEV_Pos 15 /*!< SCT EVCTRL3: STATEV Position */
+#define SCT_EVCTRL3_STATEV_Msk (0x1fUL << SCT_EVCTRL3_STATEV_Pos) /*!< SCT EVCTRL3: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK4 ----------------------------------------
+#define SCT_EVSTATEMSK4_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL4 ------------------------------------------
+#define SCT_EVCTRL4_MATCHSEL_Pos 0 /*!< SCT EVCTRL4: MATCHSEL Position */
+#define SCT_EVCTRL4_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos) /*!< SCT EVCTRL4: MATCHSEL Mask */
+#define SCT_EVCTRL4_HEVENT_Pos 4 /*!< SCT EVCTRL4: HEVENT Position */
+#define SCT_EVCTRL4_HEVENT_Msk (0x01UL << SCT_EVCTRL4_HEVENT_Pos) /*!< SCT EVCTRL4: HEVENT Mask */
+#define SCT_EVCTRL4_OUTSEL_Pos 5 /*!< SCT EVCTRL4: OUTSEL Position */
+#define SCT_EVCTRL4_OUTSEL_Msk (0x01UL << SCT_EVCTRL4_OUTSEL_Pos) /*!< SCT EVCTRL4: OUTSEL Mask */
+#define SCT_EVCTRL4_IOSEL_Pos 6 /*!< SCT EVCTRL4: IOSEL Position */
+#define SCT_EVCTRL4_IOSEL_Msk (0x0fUL << SCT_EVCTRL4_IOSEL_Pos) /*!< SCT EVCTRL4: IOSEL Mask */
+#define SCT_EVCTRL4_IOCOND_Pos 10 /*!< SCT EVCTRL4: IOCOND Position */
+#define SCT_EVCTRL4_IOCOND_Msk (0x03UL << SCT_EVCTRL4_IOCOND_Pos) /*!< SCT EVCTRL4: IOCOND Mask */
+#define SCT_EVCTRL4_COMBMODE_Pos 12 /*!< SCT EVCTRL4: COMBMODE Position */
+#define SCT_EVCTRL4_COMBMODE_Msk (0x03UL << SCT_EVCTRL4_COMBMODE_Pos) /*!< SCT EVCTRL4: COMBMODE Mask */
+#define SCT_EVCTRL4_STATELD_Pos 14 /*!< SCT EVCTRL4: STATELD Position */
+#define SCT_EVCTRL4_STATELD_Msk (0x01UL << SCT_EVCTRL4_STATELD_Pos) /*!< SCT EVCTRL4: STATELD Mask */
+#define SCT_EVCTRL4_STATEV_Pos 15 /*!< SCT EVCTRL4: STATEV Position */
+#define SCT_EVCTRL4_STATEV_Msk (0x1fUL << SCT_EVCTRL4_STATEV_Pos) /*!< SCT EVCTRL4: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK5 ----------------------------------------
+#define SCT_EVSTATEMSK5_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL5 ------------------------------------------
+#define SCT_EVCTRL5_MATCHSEL_Pos 0 /*!< SCT EVCTRL5: MATCHSEL Position */
+#define SCT_EVCTRL5_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos) /*!< SCT EVCTRL5: MATCHSEL Mask */
+#define SCT_EVCTRL5_HEVENT_Pos 4 /*!< SCT EVCTRL5: HEVENT Position */
+#define SCT_EVCTRL5_HEVENT_Msk (0x01UL << SCT_EVCTRL5_HEVENT_Pos) /*!< SCT EVCTRL5: HEVENT Mask */
+#define SCT_EVCTRL5_OUTSEL_Pos 5 /*!< SCT EVCTRL5: OUTSEL Position */
+#define SCT_EVCTRL5_OUTSEL_Msk (0x01UL << SCT_EVCTRL5_OUTSEL_Pos) /*!< SCT EVCTRL5: OUTSEL Mask */
+#define SCT_EVCTRL5_IOSEL_Pos 6 /*!< SCT EVCTRL5: IOSEL Position */
+#define SCT_EVCTRL5_IOSEL_Msk (0x0fUL << SCT_EVCTRL5_IOSEL_Pos) /*!< SCT EVCTRL5: IOSEL Mask */
+#define SCT_EVCTRL5_IOCOND_Pos 10 /*!< SCT EVCTRL5: IOCOND Position */
+#define SCT_EVCTRL5_IOCOND_Msk (0x03UL << SCT_EVCTRL5_IOCOND_Pos) /*!< SCT EVCTRL5: IOCOND Mask */
+#define SCT_EVCTRL5_COMBMODE_Pos 12 /*!< SCT EVCTRL5: COMBMODE Position */
+#define SCT_EVCTRL5_COMBMODE_Msk (0x03UL << SCT_EVCTRL5_COMBMODE_Pos) /*!< SCT EVCTRL5: COMBMODE Mask */
+#define SCT_EVCTRL5_STATELD_Pos 14 /*!< SCT EVCTRL5: STATELD Position */
+#define SCT_EVCTRL5_STATELD_Msk (0x01UL << SCT_EVCTRL5_STATELD_Pos) /*!< SCT EVCTRL5: STATELD Mask */
+#define SCT_EVCTRL5_STATEV_Pos 15 /*!< SCT EVCTRL5: STATEV Position */
+#define SCT_EVCTRL5_STATEV_Msk (0x1fUL << SCT_EVCTRL5_STATEV_Pos) /*!< SCT EVCTRL5: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK6 ----------------------------------------
+#define SCT_EVSTATEMSK6_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL6 ------------------------------------------
+#define SCT_EVCTRL6_MATCHSEL_Pos 0 /*!< SCT EVCTRL6: MATCHSEL Position */
+#define SCT_EVCTRL6_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos) /*!< SCT EVCTRL6: MATCHSEL Mask */
+#define SCT_EVCTRL6_HEVENT_Pos 4 /*!< SCT EVCTRL6: HEVENT Position */
+#define SCT_EVCTRL6_HEVENT_Msk (0x01UL << SCT_EVCTRL6_HEVENT_Pos) /*!< SCT EVCTRL6: HEVENT Mask */
+#define SCT_EVCTRL6_OUTSEL_Pos 5 /*!< SCT EVCTRL6: OUTSEL Position */
+#define SCT_EVCTRL6_OUTSEL_Msk (0x01UL << SCT_EVCTRL6_OUTSEL_Pos) /*!< SCT EVCTRL6: OUTSEL Mask */
+#define SCT_EVCTRL6_IOSEL_Pos 6 /*!< SCT EVCTRL6: IOSEL Position */
+#define SCT_EVCTRL6_IOSEL_Msk (0x0fUL << SCT_EVCTRL6_IOSEL_Pos) /*!< SCT EVCTRL6: IOSEL Mask */
+#define SCT_EVCTRL6_IOCOND_Pos 10 /*!< SCT EVCTRL6: IOCOND Position */
+#define SCT_EVCTRL6_IOCOND_Msk (0x03UL << SCT_EVCTRL6_IOCOND_Pos) /*!< SCT EVCTRL6: IOCOND Mask */
+#define SCT_EVCTRL6_COMBMODE_Pos 12 /*!< SCT EVCTRL6: COMBMODE Position */
+#define SCT_EVCTRL6_COMBMODE_Msk (0x03UL << SCT_EVCTRL6_COMBMODE_Pos) /*!< SCT EVCTRL6: COMBMODE Mask */
+#define SCT_EVCTRL6_STATELD_Pos 14 /*!< SCT EVCTRL6: STATELD Position */
+#define SCT_EVCTRL6_STATELD_Msk (0x01UL << SCT_EVCTRL6_STATELD_Pos) /*!< SCT EVCTRL6: STATELD Mask */
+#define SCT_EVCTRL6_STATEV_Pos 15 /*!< SCT EVCTRL6: STATEV Position */
+#define SCT_EVCTRL6_STATEV_Msk (0x1fUL << SCT_EVCTRL6_STATEV_Pos) /*!< SCT EVCTRL6: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK7 ----------------------------------------
+#define SCT_EVSTATEMSK7_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL7 ------------------------------------------
+#define SCT_EVCTRL7_MATCHSEL_Pos 0 /*!< SCT EVCTRL7: MATCHSEL Position */
+#define SCT_EVCTRL7_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos) /*!< SCT EVCTRL7: MATCHSEL Mask */
+#define SCT_EVCTRL7_HEVENT_Pos 4 /*!< SCT EVCTRL7: HEVENT Position */
+#define SCT_EVCTRL7_HEVENT_Msk (0x01UL << SCT_EVCTRL7_HEVENT_Pos) /*!< SCT EVCTRL7: HEVENT Mask */
+#define SCT_EVCTRL7_OUTSEL_Pos 5 /*!< SCT EVCTRL7: OUTSEL Position */
+#define SCT_EVCTRL7_OUTSEL_Msk (0x01UL << SCT_EVCTRL7_OUTSEL_Pos) /*!< SCT EVCTRL7: OUTSEL Mask */
+#define SCT_EVCTRL7_IOSEL_Pos 6 /*!< SCT EVCTRL7: IOSEL Position */
+#define SCT_EVCTRL7_IOSEL_Msk (0x0fUL << SCT_EVCTRL7_IOSEL_Pos) /*!< SCT EVCTRL7: IOSEL Mask */
+#define SCT_EVCTRL7_IOCOND_Pos 10 /*!< SCT EVCTRL7: IOCOND Position */
+#define SCT_EVCTRL7_IOCOND_Msk (0x03UL << SCT_EVCTRL7_IOCOND_Pos) /*!< SCT EVCTRL7: IOCOND Mask */
+#define SCT_EVCTRL7_COMBMODE_Pos 12 /*!< SCT EVCTRL7: COMBMODE Position */
+#define SCT_EVCTRL7_COMBMODE_Msk (0x03UL << SCT_EVCTRL7_COMBMODE_Pos) /*!< SCT EVCTRL7: COMBMODE Mask */
+#define SCT_EVCTRL7_STATELD_Pos 14 /*!< SCT EVCTRL7: STATELD Position */
+#define SCT_EVCTRL7_STATELD_Msk (0x01UL << SCT_EVCTRL7_STATELD_Pos) /*!< SCT EVCTRL7: STATELD Mask */
+#define SCT_EVCTRL7_STATEV_Pos 15 /*!< SCT EVCTRL7: STATEV Position */
+#define SCT_EVCTRL7_STATEV_Msk (0x1fUL << SCT_EVCTRL7_STATEV_Pos) /*!< SCT EVCTRL7: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK8 ----------------------------------------
+#define SCT_EVSTATEMSK8_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL8 ------------------------------------------
+#define SCT_EVCTRL8_MATCHSEL_Pos 0 /*!< SCT EVCTRL8: MATCHSEL Position */
+#define SCT_EVCTRL8_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos) /*!< SCT EVCTRL8: MATCHSEL Mask */
+#define SCT_EVCTRL8_HEVENT_Pos 4 /*!< SCT EVCTRL8: HEVENT Position */
+#define SCT_EVCTRL8_HEVENT_Msk (0x01UL << SCT_EVCTRL8_HEVENT_Pos) /*!< SCT EVCTRL8: HEVENT Mask */
+#define SCT_EVCTRL8_OUTSEL_Pos 5 /*!< SCT EVCTRL8: OUTSEL Position */
+#define SCT_EVCTRL8_OUTSEL_Msk (0x01UL << SCT_EVCTRL8_OUTSEL_Pos) /*!< SCT EVCTRL8: OUTSEL Mask */
+#define SCT_EVCTRL8_IOSEL_Pos 6 /*!< SCT EVCTRL8: IOSEL Position */
+#define SCT_EVCTRL8_IOSEL_Msk (0x0fUL << SCT_EVCTRL8_IOSEL_Pos) /*!< SCT EVCTRL8: IOSEL Mask */
+#define SCT_EVCTRL8_IOCOND_Pos 10 /*!< SCT EVCTRL8: IOCOND Position */
+#define SCT_EVCTRL8_IOCOND_Msk (0x03UL << SCT_EVCTRL8_IOCOND_Pos) /*!< SCT EVCTRL8: IOCOND Mask */
+#define SCT_EVCTRL8_COMBMODE_Pos 12 /*!< SCT EVCTRL8: COMBMODE Position */
+#define SCT_EVCTRL8_COMBMODE_Msk (0x03UL << SCT_EVCTRL8_COMBMODE_Pos) /*!< SCT EVCTRL8: COMBMODE Mask */
+#define SCT_EVCTRL8_STATELD_Pos 14 /*!< SCT EVCTRL8: STATELD Position */
+#define SCT_EVCTRL8_STATELD_Msk (0x01UL << SCT_EVCTRL8_STATELD_Pos) /*!< SCT EVCTRL8: STATELD Mask */
+#define SCT_EVCTRL8_STATEV_Pos 15 /*!< SCT EVCTRL8: STATEV Position */
+#define SCT_EVCTRL8_STATEV_Msk (0x1fUL << SCT_EVCTRL8_STATEV_Pos) /*!< SCT EVCTRL8: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK9 ----------------------------------------
+#define SCT_EVSTATEMSK9_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL9 ------------------------------------------
+#define SCT_EVCTRL9_MATCHSEL_Pos 0 /*!< SCT EVCTRL9: MATCHSEL Position */
+#define SCT_EVCTRL9_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos) /*!< SCT EVCTRL9: MATCHSEL Mask */
+#define SCT_EVCTRL9_HEVENT_Pos 4 /*!< SCT EVCTRL9: HEVENT Position */
+#define SCT_EVCTRL9_HEVENT_Msk (0x01UL << SCT_EVCTRL9_HEVENT_Pos) /*!< SCT EVCTRL9: HEVENT Mask */
+#define SCT_EVCTRL9_OUTSEL_Pos 5 /*!< SCT EVCTRL9: OUTSEL Position */
+#define SCT_EVCTRL9_OUTSEL_Msk (0x01UL << SCT_EVCTRL9_OUTSEL_Pos) /*!< SCT EVCTRL9: OUTSEL Mask */
+#define SCT_EVCTRL9_IOSEL_Pos 6 /*!< SCT EVCTRL9: IOSEL Position */
+#define SCT_EVCTRL9_IOSEL_Msk (0x0fUL << SCT_EVCTRL9_IOSEL_Pos) /*!< SCT EVCTRL9: IOSEL Mask */
+#define SCT_EVCTRL9_IOCOND_Pos 10 /*!< SCT EVCTRL9: IOCOND Position */
+#define SCT_EVCTRL9_IOCOND_Msk (0x03UL << SCT_EVCTRL9_IOCOND_Pos) /*!< SCT EVCTRL9: IOCOND Mask */
+#define SCT_EVCTRL9_COMBMODE_Pos 12 /*!< SCT EVCTRL9: COMBMODE Position */
+#define SCT_EVCTRL9_COMBMODE_Msk (0x03UL << SCT_EVCTRL9_COMBMODE_Pos) /*!< SCT EVCTRL9: COMBMODE Mask */
+#define SCT_EVCTRL9_STATELD_Pos 14 /*!< SCT EVCTRL9: STATELD Position */
+#define SCT_EVCTRL9_STATELD_Msk (0x01UL << SCT_EVCTRL9_STATELD_Pos) /*!< SCT EVCTRL9: STATELD Mask */
+#define SCT_EVCTRL9_STATEV_Pos 15 /*!< SCT EVCTRL9: STATEV Position */
+#define SCT_EVCTRL9_STATEV_Msk (0x1fUL << SCT_EVCTRL9_STATEV_Pos) /*!< SCT EVCTRL9: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK10 ----------------------------------------
+#define SCT_EVSTATEMSK10_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL10 ------------------------------------------
+#define SCT_EVCTRL10_MATCHSEL_Pos 0 /*!< SCT EVCTRL10: MATCHSEL Position */
+#define SCT_EVCTRL10_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos) /*!< SCT EVCTRL10: MATCHSEL Mask */
+#define SCT_EVCTRL10_HEVENT_Pos 4 /*!< SCT EVCTRL10: HEVENT Position */
+#define SCT_EVCTRL10_HEVENT_Msk (0x01UL << SCT_EVCTRL10_HEVENT_Pos) /*!< SCT EVCTRL10: HEVENT Mask */
+#define SCT_EVCTRL10_OUTSEL_Pos 5 /*!< SCT EVCTRL10: OUTSEL Position */
+#define SCT_EVCTRL10_OUTSEL_Msk (0x01UL << SCT_EVCTRL10_OUTSEL_Pos) /*!< SCT EVCTRL10: OUTSEL Mask */
+#define SCT_EVCTRL10_IOSEL_Pos 6 /*!< SCT EVCTRL10: IOSEL Position */
+#define SCT_EVCTRL10_IOSEL_Msk (0x0fUL << SCT_EVCTRL10_IOSEL_Pos) /*!< SCT EVCTRL10: IOSEL Mask */
+#define SCT_EVCTRL10_IOCOND_Pos 10 /*!< SCT EVCTRL10: IOCOND Position */
+#define SCT_EVCTRL10_IOCOND_Msk (0x03UL << SCT_EVCTRL10_IOCOND_Pos) /*!< SCT EVCTRL10: IOCOND Mask */
+#define SCT_EVCTRL10_COMBMODE_Pos 12 /*!< SCT EVCTRL10: COMBMODE Position */
+#define SCT_EVCTRL10_COMBMODE_Msk (0x03UL << SCT_EVCTRL10_COMBMODE_Pos) /*!< SCT EVCTRL10: COMBMODE Mask */
+#define SCT_EVCTRL10_STATELD_Pos 14 /*!< SCT EVCTRL10: STATELD Position */
+#define SCT_EVCTRL10_STATELD_Msk (0x01UL << SCT_EVCTRL10_STATELD_Pos) /*!< SCT EVCTRL10: STATELD Mask */
+#define SCT_EVCTRL10_STATEV_Pos 15 /*!< SCT EVCTRL10: STATEV Position */
+#define SCT_EVCTRL10_STATEV_Msk (0x1fUL << SCT_EVCTRL10_STATEV_Pos) /*!< SCT EVCTRL10: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK11 ----------------------------------------
+#define SCT_EVSTATEMSK11_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL11 ------------------------------------------
+#define SCT_EVCTRL11_MATCHSEL_Pos 0 /*!< SCT EVCTRL11: MATCHSEL Position */
+#define SCT_EVCTRL11_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos) /*!< SCT EVCTRL11: MATCHSEL Mask */
+#define SCT_EVCTRL11_HEVENT_Pos 4 /*!< SCT EVCTRL11: HEVENT Position */
+#define SCT_EVCTRL11_HEVENT_Msk (0x01UL << SCT_EVCTRL11_HEVENT_Pos) /*!< SCT EVCTRL11: HEVENT Mask */
+#define SCT_EVCTRL11_OUTSEL_Pos 5 /*!< SCT EVCTRL11: OUTSEL Position */
+#define SCT_EVCTRL11_OUTSEL_Msk (0x01UL << SCT_EVCTRL11_OUTSEL_Pos) /*!< SCT EVCTRL11: OUTSEL Mask */
+#define SCT_EVCTRL11_IOSEL_Pos 6 /*!< SCT EVCTRL11: IOSEL Position */
+#define SCT_EVCTRL11_IOSEL_Msk (0x0fUL << SCT_EVCTRL11_IOSEL_Pos) /*!< SCT EVCTRL11: IOSEL Mask */
+#define SCT_EVCTRL11_IOCOND_Pos 10 /*!< SCT EVCTRL11: IOCOND Position */
+#define SCT_EVCTRL11_IOCOND_Msk (0x03UL << SCT_EVCTRL11_IOCOND_Pos) /*!< SCT EVCTRL11: IOCOND Mask */
+#define SCT_EVCTRL11_COMBMODE_Pos 12 /*!< SCT EVCTRL11: COMBMODE Position */
+#define SCT_EVCTRL11_COMBMODE_Msk (0x03UL << SCT_EVCTRL11_COMBMODE_Pos) /*!< SCT EVCTRL11: COMBMODE Mask */
+#define SCT_EVCTRL11_STATELD_Pos 14 /*!< SCT EVCTRL11: STATELD Position */
+#define SCT_EVCTRL11_STATELD_Msk (0x01UL << SCT_EVCTRL11_STATELD_Pos) /*!< SCT EVCTRL11: STATELD Mask */
+#define SCT_EVCTRL11_STATEV_Pos 15 /*!< SCT EVCTRL11: STATEV Position */
+#define SCT_EVCTRL11_STATEV_Msk (0x1fUL << SCT_EVCTRL11_STATEV_Pos) /*!< SCT EVCTRL11: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK12 ----------------------------------------
+#define SCT_EVSTATEMSK12_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL12 ------------------------------------------
+#define SCT_EVCTRL12_MATCHSEL_Pos 0 /*!< SCT EVCTRL12: MATCHSEL Position */
+#define SCT_EVCTRL12_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos) /*!< SCT EVCTRL12: MATCHSEL Mask */
+#define SCT_EVCTRL12_HEVENT_Pos 4 /*!< SCT EVCTRL12: HEVENT Position */
+#define SCT_EVCTRL12_HEVENT_Msk (0x01UL << SCT_EVCTRL12_HEVENT_Pos) /*!< SCT EVCTRL12: HEVENT Mask */
+#define SCT_EVCTRL12_OUTSEL_Pos 5 /*!< SCT EVCTRL12: OUTSEL Position */
+#define SCT_EVCTRL12_OUTSEL_Msk (0x01UL << SCT_EVCTRL12_OUTSEL_Pos) /*!< SCT EVCTRL12: OUTSEL Mask */
+#define SCT_EVCTRL12_IOSEL_Pos 6 /*!< SCT EVCTRL12: IOSEL Position */
+#define SCT_EVCTRL12_IOSEL_Msk (0x0fUL << SCT_EVCTRL12_IOSEL_Pos) /*!< SCT EVCTRL12: IOSEL Mask */
+#define SCT_EVCTRL12_IOCOND_Pos 10 /*!< SCT EVCTRL12: IOCOND Position */
+#define SCT_EVCTRL12_IOCOND_Msk (0x03UL << SCT_EVCTRL12_IOCOND_Pos) /*!< SCT EVCTRL12: IOCOND Mask */
+#define SCT_EVCTRL12_COMBMODE_Pos 12 /*!< SCT EVCTRL12: COMBMODE Position */
+#define SCT_EVCTRL12_COMBMODE_Msk (0x03UL << SCT_EVCTRL12_COMBMODE_Pos) /*!< SCT EVCTRL12: COMBMODE Mask */
+#define SCT_EVCTRL12_STATELD_Pos 14 /*!< SCT EVCTRL12: STATELD Position */
+#define SCT_EVCTRL12_STATELD_Msk (0x01UL << SCT_EVCTRL12_STATELD_Pos) /*!< SCT EVCTRL12: STATELD Mask */
+#define SCT_EVCTRL12_STATEV_Pos 15 /*!< SCT EVCTRL12: STATEV Position */
+#define SCT_EVCTRL12_STATEV_Msk (0x1fUL << SCT_EVCTRL12_STATEV_Pos) /*!< SCT EVCTRL12: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK13 ----------------------------------------
+#define SCT_EVSTATEMSK13_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL13 ------------------------------------------
+#define SCT_EVCTRL13_MATCHSEL_Pos 0 /*!< SCT EVCTRL13: MATCHSEL Position */
+#define SCT_EVCTRL13_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos) /*!< SCT EVCTRL13: MATCHSEL Mask */
+#define SCT_EVCTRL13_HEVENT_Pos 4 /*!< SCT EVCTRL13: HEVENT Position */
+#define SCT_EVCTRL13_HEVENT_Msk (0x01UL << SCT_EVCTRL13_HEVENT_Pos) /*!< SCT EVCTRL13: HEVENT Mask */
+#define SCT_EVCTRL13_OUTSEL_Pos 5 /*!< SCT EVCTRL13: OUTSEL Position */
+#define SCT_EVCTRL13_OUTSEL_Msk (0x01UL << SCT_EVCTRL13_OUTSEL_Pos) /*!< SCT EVCTRL13: OUTSEL Mask */
+#define SCT_EVCTRL13_IOSEL_Pos 6 /*!< SCT EVCTRL13: IOSEL Position */
+#define SCT_EVCTRL13_IOSEL_Msk (0x0fUL << SCT_EVCTRL13_IOSEL_Pos) /*!< SCT EVCTRL13: IOSEL Mask */
+#define SCT_EVCTRL13_IOCOND_Pos 10 /*!< SCT EVCTRL13: IOCOND Position */
+#define SCT_EVCTRL13_IOCOND_Msk (0x03UL << SCT_EVCTRL13_IOCOND_Pos) /*!< SCT EVCTRL13: IOCOND Mask */
+#define SCT_EVCTRL13_COMBMODE_Pos 12 /*!< SCT EVCTRL13: COMBMODE Position */
+#define SCT_EVCTRL13_COMBMODE_Msk (0x03UL << SCT_EVCTRL13_COMBMODE_Pos) /*!< SCT EVCTRL13: COMBMODE Mask */
+#define SCT_EVCTRL13_STATELD_Pos 14 /*!< SCT EVCTRL13: STATELD Position */
+#define SCT_EVCTRL13_STATELD_Msk (0x01UL << SCT_EVCTRL13_STATELD_Pos) /*!< SCT EVCTRL13: STATELD Mask */
+#define SCT_EVCTRL13_STATEV_Pos 15 /*!< SCT EVCTRL13: STATEV Position */
+#define SCT_EVCTRL13_STATEV_Msk (0x1fUL << SCT_EVCTRL13_STATEV_Pos) /*!< SCT EVCTRL13: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK14 ----------------------------------------
+#define SCT_EVSTATEMSK14_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL14 ------------------------------------------
+#define SCT_EVCTRL14_MATCHSEL_Pos 0 /*!< SCT EVCTRL14: MATCHSEL Position */
+#define SCT_EVCTRL14_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos) /*!< SCT EVCTRL14: MATCHSEL Mask */
+#define SCT_EVCTRL14_HEVENT_Pos 4 /*!< SCT EVCTRL14: HEVENT Position */
+#define SCT_EVCTRL14_HEVENT_Msk (0x01UL << SCT_EVCTRL14_HEVENT_Pos) /*!< SCT EVCTRL14: HEVENT Mask */
+#define SCT_EVCTRL14_OUTSEL_Pos 5 /*!< SCT EVCTRL14: OUTSEL Position */
+#define SCT_EVCTRL14_OUTSEL_Msk (0x01UL << SCT_EVCTRL14_OUTSEL_Pos) /*!< SCT EVCTRL14: OUTSEL Mask */
+#define SCT_EVCTRL14_IOSEL_Pos 6 /*!< SCT EVCTRL14: IOSEL Position */
+#define SCT_EVCTRL14_IOSEL_Msk (0x0fUL << SCT_EVCTRL14_IOSEL_Pos) /*!< SCT EVCTRL14: IOSEL Mask */
+#define SCT_EVCTRL14_IOCOND_Pos 10 /*!< SCT EVCTRL14: IOCOND Position */
+#define SCT_EVCTRL14_IOCOND_Msk (0x03UL << SCT_EVCTRL14_IOCOND_Pos) /*!< SCT EVCTRL14: IOCOND Mask */
+#define SCT_EVCTRL14_COMBMODE_Pos 12 /*!< SCT EVCTRL14: COMBMODE Position */
+#define SCT_EVCTRL14_COMBMODE_Msk (0x03UL << SCT_EVCTRL14_COMBMODE_Pos) /*!< SCT EVCTRL14: COMBMODE Mask */
+#define SCT_EVCTRL14_STATELD_Pos 14 /*!< SCT EVCTRL14: STATELD Position */
+#define SCT_EVCTRL14_STATELD_Msk (0x01UL << SCT_EVCTRL14_STATELD_Pos) /*!< SCT EVCTRL14: STATELD Mask */
+#define SCT_EVCTRL14_STATEV_Pos 15 /*!< SCT EVCTRL14: STATEV Position */
+#define SCT_EVCTRL14_STATEV_Msk (0x1fUL << SCT_EVCTRL14_STATEV_Pos) /*!< SCT EVCTRL14: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK15 ----------------------------------------
+#define SCT_EVSTATEMSK15_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL15 ------------------------------------------
+#define SCT_EVCTRL15_MATCHSEL_Pos 0 /*!< SCT EVCTRL15: MATCHSEL Position */
+#define SCT_EVCTRL15_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos) /*!< SCT EVCTRL15: MATCHSEL Mask */
+#define SCT_EVCTRL15_HEVENT_Pos 4 /*!< SCT EVCTRL15: HEVENT Position */
+#define SCT_EVCTRL15_HEVENT_Msk (0x01UL << SCT_EVCTRL15_HEVENT_Pos) /*!< SCT EVCTRL15: HEVENT Mask */
+#define SCT_EVCTRL15_OUTSEL_Pos 5 /*!< SCT EVCTRL15: OUTSEL Position */
+#define SCT_EVCTRL15_OUTSEL_Msk (0x01UL << SCT_EVCTRL15_OUTSEL_Pos) /*!< SCT EVCTRL15: OUTSEL Mask */
+#define SCT_EVCTRL15_IOSEL_Pos 6 /*!< SCT EVCTRL15: IOSEL Position */
+#define SCT_EVCTRL15_IOSEL_Msk (0x0fUL << SCT_EVCTRL15_IOSEL_Pos) /*!< SCT EVCTRL15: IOSEL Mask */
+#define SCT_EVCTRL15_IOCOND_Pos 10 /*!< SCT EVCTRL15: IOCOND Position */
+#define SCT_EVCTRL15_IOCOND_Msk (0x03UL << SCT_EVCTRL15_IOCOND_Pos) /*!< SCT EVCTRL15: IOCOND Mask */
+#define SCT_EVCTRL15_COMBMODE_Pos 12 /*!< SCT EVCTRL15: COMBMODE Position */
+#define SCT_EVCTRL15_COMBMODE_Msk (0x03UL << SCT_EVCTRL15_COMBMODE_Pos) /*!< SCT EVCTRL15: COMBMODE Mask */
+#define SCT_EVCTRL15_STATELD_Pos 14 /*!< SCT EVCTRL15: STATELD Position */
+#define SCT_EVCTRL15_STATELD_Msk (0x01UL << SCT_EVCTRL15_STATELD_Pos) /*!< SCT EVCTRL15: STATELD Mask */
+#define SCT_EVCTRL15_STATEV_Pos 15 /*!< SCT EVCTRL15: STATEV Position */
+#define SCT_EVCTRL15_STATEV_Msk (0x1fUL << SCT_EVCTRL15_STATEV_Pos) /*!< SCT EVCTRL15: STATEV Mask */
+
+// ------------------------------------- SCT_OUTPUTSET0 -----------------------------------------
+#define SCT_OUTPUTSET0_SETn0_Pos 0 /*!< SCT OUTPUTSET0: SETn0 Position */
+#define SCT_OUTPUTSET0_SETn0_Msk (0x01UL << SCT_OUTPUTSET0_SETn0_Pos) /*!< SCT OUTPUTSET0: SETn0 Mask */
+#define SCT_OUTPUTSET0_SETn1_Pos 1 /*!< SCT OUTPUTSET0: SETn1 Position */
+#define SCT_OUTPUTSET0_SETn1_Msk (0x01UL << SCT_OUTPUTSET0_SETn1_Pos) /*!< SCT OUTPUTSET0: SETn1 Mask */
+#define SCT_OUTPUTSET0_SETn2_Pos 2 /*!< SCT OUTPUTSET0: SETn2 Position */
+#define SCT_OUTPUTSET0_SETn2_Msk (0x01UL << SCT_OUTPUTSET0_SETn2_Pos) /*!< SCT OUTPUTSET0: SETn2 Mask */
+#define SCT_OUTPUTSET0_SETn3_Pos 3 /*!< SCT OUTPUTSET0: SETn3 Position */
+#define SCT_OUTPUTSET0_SETn3_Msk (0x01UL << SCT_OUTPUTSET0_SETn3_Pos) /*!< SCT OUTPUTSET0: SETn3 Mask */
+#define SCT_OUTPUTSET0_SETn4_Pos 4 /*!< SCT OUTPUTSET0: SETn4 Position */
+#define SCT_OUTPUTSET0_SETn4_Msk (0x01UL << SCT_OUTPUTSET0_SETn4_Pos) /*!< SCT OUTPUTSET0: SETn4 Mask */
+#define SCT_OUTPUTSET0_SETn5_Pos 5 /*!< SCT OUTPUTSET0: SETn5 Position */
+#define SCT_OUTPUTSET0_SETn5_Msk (0x01UL << SCT_OUTPUTSET0_SETn5_Pos) /*!< SCT OUTPUTSET0: SETn5 Mask */
+#define SCT_OUTPUTSET0_SETn6_Pos 6 /*!< SCT OUTPUTSET0: SETn6 Position */
+#define SCT_OUTPUTSET0_SETn6_Msk (0x01UL << SCT_OUTPUTSET0_SETn6_Pos) /*!< SCT OUTPUTSET0: SETn6 Mask */
+#define SCT_OUTPUTSET0_SETn7_Pos 7 /*!< SCT OUTPUTSET0: SETn7 Position */
+#define SCT_OUTPUTSET0_SETn7_Msk (0x01UL << SCT_OUTPUTSET0_SETn7_Pos) /*!< SCT OUTPUTSET0: SETn7 Mask */
+#define SCT_OUTPUTSET0_SETn8_Pos 8 /*!< SCT OUTPUTSET0: SETn8 Position */
+#define SCT_OUTPUTSET0_SETn8_Msk (0x01UL << SCT_OUTPUTSET0_SETn8_Pos) /*!< SCT OUTPUTSET0: SETn8 Mask */
+#define SCT_OUTPUTSET0_SETn9_Pos 9 /*!< SCT OUTPUTSET0: SETn9 Position */
+#define SCT_OUTPUTSET0_SETn9_Msk (0x01UL << SCT_OUTPUTSET0_SETn9_Pos) /*!< SCT OUTPUTSET0: SETn9 Mask */
+#define SCT_OUTPUTSET0_SETn10_Pos 10 /*!< SCT OUTPUTSET0: SETn10 Position */
+#define SCT_OUTPUTSET0_SETn10_Msk (0x01UL << SCT_OUTPUTSET0_SETn10_Pos) /*!< SCT OUTPUTSET0: SETn10 Mask */
+#define SCT_OUTPUTSET0_SETn11_Pos 11 /*!< SCT OUTPUTSET0: SETn11 Position */
+#define SCT_OUTPUTSET0_SETn11_Msk (0x01UL << SCT_OUTPUTSET0_SETn11_Pos) /*!< SCT OUTPUTSET0: SETn11 Mask */
+#define SCT_OUTPUTSET0_SETn12_Pos 12 /*!< SCT OUTPUTSET0: SETn12 Position */
+#define SCT_OUTPUTSET0_SETn12_Msk (0x01UL << SCT_OUTPUTSET0_SETn12_Pos) /*!< SCT OUTPUTSET0: SETn12 Mask */
+#define SCT_OUTPUTSET0_SETn13_Pos 13 /*!< SCT OUTPUTSET0: SETn13 Position */
+#define SCT_OUTPUTSET0_SETn13_Msk (0x01UL << SCT_OUTPUTSET0_SETn13_Pos) /*!< SCT OUTPUTSET0: SETn13 Mask */
+#define SCT_OUTPUTSET0_SETn14_Pos 14 /*!< SCT OUTPUTSET0: SETn14 Position */
+#define SCT_OUTPUTSET0_SETn14_Msk (0x01UL << SCT_OUTPUTSET0_SETn14_Pos) /*!< SCT OUTPUTSET0: SETn14 Mask */
+#define SCT_OUTPUTSET0_SETn15_Pos 15 /*!< SCT OUTPUTSET0: SETn15 Position */
+#define SCT_OUTPUTSET0_SETn15_Msk (0x01UL << SCT_OUTPUTSET0_SETn15_Pos) /*!< SCT OUTPUTSET0: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR0 -----------------------------------------
+#define SCT_OUTPUTCLR0_CLRn0_Pos 0 /*!< SCT OUTPUTCLR0: CLRn0 Position */
+#define SCT_OUTPUTCLR0_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos) /*!< SCT OUTPUTCLR0: CLRn0 Mask */
+#define SCT_OUTPUTCLR0_CLRn1_Pos 1 /*!< SCT OUTPUTCLR0: CLRn1 Position */
+#define SCT_OUTPUTCLR0_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos) /*!< SCT OUTPUTCLR0: CLRn1 Mask */
+#define SCT_OUTPUTCLR0_CLRn2_Pos 2 /*!< SCT OUTPUTCLR0: CLRn2 Position */
+#define SCT_OUTPUTCLR0_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos) /*!< SCT OUTPUTCLR0: CLRn2 Mask */
+#define SCT_OUTPUTCLR0_CLRn3_Pos 3 /*!< SCT OUTPUTCLR0: CLRn3 Position */
+#define SCT_OUTPUTCLR0_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos) /*!< SCT OUTPUTCLR0: CLRn3 Mask */
+#define SCT_OUTPUTCLR0_CLRn4_Pos 4 /*!< SCT OUTPUTCLR0: CLRn4 Position */
+#define SCT_OUTPUTCLR0_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos) /*!< SCT OUTPUTCLR0: CLRn4 Mask */
+#define SCT_OUTPUTCLR0_CLRn5_Pos 5 /*!< SCT OUTPUTCLR0: CLRn5 Position */
+#define SCT_OUTPUTCLR0_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos) /*!< SCT OUTPUTCLR0: CLRn5 Mask */
+#define SCT_OUTPUTCLR0_CLRn6_Pos 6 /*!< SCT OUTPUTCLR0: CLRn6 Position */
+#define SCT_OUTPUTCLR0_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos) /*!< SCT OUTPUTCLR0: CLRn6 Mask */
+#define SCT_OUTPUTCLR0_CLRn7_Pos 7 /*!< SCT OUTPUTCLR0: CLRn7 Position */
+#define SCT_OUTPUTCLR0_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos) /*!< SCT OUTPUTCLR0: CLRn7 Mask */
+#define SCT_OUTPUTCLR0_CLRn8_Pos 8 /*!< SCT OUTPUTCLR0: CLRn8 Position */
+#define SCT_OUTPUTCLR0_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos) /*!< SCT OUTPUTCLR0: CLRn8 Mask */
+#define SCT_OUTPUTCLR0_CLRn9_Pos 9 /*!< SCT OUTPUTCLR0: CLRn9 Position */
+#define SCT_OUTPUTCLR0_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos) /*!< SCT OUTPUTCLR0: CLRn9 Mask */
+#define SCT_OUTPUTCLR0_CLRn10_Pos 10 /*!< SCT OUTPUTCLR0: CLRn10 Position */
+#define SCT_OUTPUTCLR0_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos) /*!< SCT OUTPUTCLR0: CLRn10 Mask */
+#define SCT_OUTPUTCLR0_CLRn11_Pos 11 /*!< SCT OUTPUTCLR0: CLRn11 Position */
+#define SCT_OUTPUTCLR0_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos) /*!< SCT OUTPUTCLR0: CLRn11 Mask */
+#define SCT_OUTPUTCLR0_CLRn12_Pos 12 /*!< SCT OUTPUTCLR0: CLRn12 Position */
+#define SCT_OUTPUTCLR0_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos) /*!< SCT OUTPUTCLR0: CLRn12 Mask */
+#define SCT_OUTPUTCLR0_CLRn13_Pos 13 /*!< SCT OUTPUTCLR0: CLRn13 Position */
+#define SCT_OUTPUTCLR0_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos) /*!< SCT OUTPUTCLR0: CLRn13 Mask */
+#define SCT_OUTPUTCLR0_CLRn14_Pos 14 /*!< SCT OUTPUTCLR0: CLRn14 Position */
+#define SCT_OUTPUTCLR0_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos) /*!< SCT OUTPUTCLR0: CLRn14 Mask */
+#define SCT_OUTPUTCLR0_CLRn15_Pos 15 /*!< SCT OUTPUTCLR0: CLRn15 Position */
+#define SCT_OUTPUTCLR0_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos) /*!< SCT OUTPUTCLR0: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET1 -----------------------------------------
+#define SCT_OUTPUTSET1_SETn0_Pos 0 /*!< SCT OUTPUTSET1: SETn0 Position */
+#define SCT_OUTPUTSET1_SETn0_Msk (0x01UL << SCT_OUTPUTSET1_SETn0_Pos) /*!< SCT OUTPUTSET1: SETn0 Mask */
+#define SCT_OUTPUTSET1_SETn1_Pos 1 /*!< SCT OUTPUTSET1: SETn1 Position */
+#define SCT_OUTPUTSET1_SETn1_Msk (0x01UL << SCT_OUTPUTSET1_SETn1_Pos) /*!< SCT OUTPUTSET1: SETn1 Mask */
+#define SCT_OUTPUTSET1_SETn2_Pos 2 /*!< SCT OUTPUTSET1: SETn2 Position */
+#define SCT_OUTPUTSET1_SETn2_Msk (0x01UL << SCT_OUTPUTSET1_SETn2_Pos) /*!< SCT OUTPUTSET1: SETn2 Mask */
+#define SCT_OUTPUTSET1_SETn3_Pos 3 /*!< SCT OUTPUTSET1: SETn3 Position */
+#define SCT_OUTPUTSET1_SETn3_Msk (0x01UL << SCT_OUTPUTSET1_SETn3_Pos) /*!< SCT OUTPUTSET1: SETn3 Mask */
+#define SCT_OUTPUTSET1_SETn4_Pos 4 /*!< SCT OUTPUTSET1: SETn4 Position */
+#define SCT_OUTPUTSET1_SETn4_Msk (0x01UL << SCT_OUTPUTSET1_SETn4_Pos) /*!< SCT OUTPUTSET1: SETn4 Mask */
+#define SCT_OUTPUTSET1_SETn5_Pos 5 /*!< SCT OUTPUTSET1: SETn5 Position */
+#define SCT_OUTPUTSET1_SETn5_Msk (0x01UL << SCT_OUTPUTSET1_SETn5_Pos) /*!< SCT OUTPUTSET1: SETn5 Mask */
+#define SCT_OUTPUTSET1_SETn6_Pos 6 /*!< SCT OUTPUTSET1: SETn6 Position */
+#define SCT_OUTPUTSET1_SETn6_Msk (0x01UL << SCT_OUTPUTSET1_SETn6_Pos) /*!< SCT OUTPUTSET1: SETn6 Mask */
+#define SCT_OUTPUTSET1_SETn7_Pos 7 /*!< SCT OUTPUTSET1: SETn7 Position */
+#define SCT_OUTPUTSET1_SETn7_Msk (0x01UL << SCT_OUTPUTSET1_SETn7_Pos) /*!< SCT OUTPUTSET1: SETn7 Mask */
+#define SCT_OUTPUTSET1_SETn8_Pos 8 /*!< SCT OUTPUTSET1: SETn8 Position */
+#define SCT_OUTPUTSET1_SETn8_Msk (0x01UL << SCT_OUTPUTSET1_SETn8_Pos) /*!< SCT OUTPUTSET1: SETn8 Mask */
+#define SCT_OUTPUTSET1_SETn9_Pos 9 /*!< SCT OUTPUTSET1: SETn9 Position */
+#define SCT_OUTPUTSET1_SETn9_Msk (0x01UL << SCT_OUTPUTSET1_SETn9_Pos) /*!< SCT OUTPUTSET1: SETn9 Mask */
+#define SCT_OUTPUTSET1_SETn10_Pos 10 /*!< SCT OUTPUTSET1: SETn10 Position */
+#define SCT_OUTPUTSET1_SETn10_Msk (0x01UL << SCT_OUTPUTSET1_SETn10_Pos) /*!< SCT OUTPUTSET1: SETn10 Mask */
+#define SCT_OUTPUTSET1_SETn11_Pos 11 /*!< SCT OUTPUTSET1: SETn11 Position */
+#define SCT_OUTPUTSET1_SETn11_Msk (0x01UL << SCT_OUTPUTSET1_SETn11_Pos) /*!< SCT OUTPUTSET1: SETn11 Mask */
+#define SCT_OUTPUTSET1_SETn12_Pos 12 /*!< SCT OUTPUTSET1: SETn12 Position */
+#define SCT_OUTPUTSET1_SETn12_Msk (0x01UL << SCT_OUTPUTSET1_SETn12_Pos) /*!< SCT OUTPUTSET1: SETn12 Mask */
+#define SCT_OUTPUTSET1_SETn13_Pos 13 /*!< SCT OUTPUTSET1: SETn13 Position */
+#define SCT_OUTPUTSET1_SETn13_Msk (0x01UL << SCT_OUTPUTSET1_SETn13_Pos) /*!< SCT OUTPUTSET1: SETn13 Mask */
+#define SCT_OUTPUTSET1_SETn14_Pos 14 /*!< SCT OUTPUTSET1: SETn14 Position */
+#define SCT_OUTPUTSET1_SETn14_Msk (0x01UL << SCT_OUTPUTSET1_SETn14_Pos) /*!< SCT OUTPUTSET1: SETn14 Mask */
+#define SCT_OUTPUTSET1_SETn15_Pos 15 /*!< SCT OUTPUTSET1: SETn15 Position */
+#define SCT_OUTPUTSET1_SETn15_Msk (0x01UL << SCT_OUTPUTSET1_SETn15_Pos) /*!< SCT OUTPUTSET1: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR1 -----------------------------------------
+#define SCT_OUTPUTCLR1_CLRn0_Pos 0 /*!< SCT OUTPUTCLR1: CLRn0 Position */
+#define SCT_OUTPUTCLR1_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos) /*!< SCT OUTPUTCLR1: CLRn0 Mask */
+#define SCT_OUTPUTCLR1_CLRn1_Pos 1 /*!< SCT OUTPUTCLR1: CLRn1 Position */
+#define SCT_OUTPUTCLR1_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos) /*!< SCT OUTPUTCLR1: CLRn1 Mask */
+#define SCT_OUTPUTCLR1_CLRn2_Pos 2 /*!< SCT OUTPUTCLR1: CLRn2 Position */
+#define SCT_OUTPUTCLR1_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos) /*!< SCT OUTPUTCLR1: CLRn2 Mask */
+#define SCT_OUTPUTCLR1_CLRn3_Pos 3 /*!< SCT OUTPUTCLR1: CLRn3 Position */
+#define SCT_OUTPUTCLR1_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos) /*!< SCT OUTPUTCLR1: CLRn3 Mask */
+#define SCT_OUTPUTCLR1_CLRn4_Pos 4 /*!< SCT OUTPUTCLR1: CLRn4 Position */
+#define SCT_OUTPUTCLR1_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos) /*!< SCT OUTPUTCLR1: CLRn4 Mask */
+#define SCT_OUTPUTCLR1_CLRn5_Pos 5 /*!< SCT OUTPUTCLR1: CLRn5 Position */
+#define SCT_OUTPUTCLR1_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos) /*!< SCT OUTPUTCLR1: CLRn5 Mask */
+#define SCT_OUTPUTCLR1_CLRn6_Pos 6 /*!< SCT OUTPUTCLR1: CLRn6 Position */
+#define SCT_OUTPUTCLR1_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos) /*!< SCT OUTPUTCLR1: CLRn6 Mask */
+#define SCT_OUTPUTCLR1_CLRn7_Pos 7 /*!< SCT OUTPUTCLR1: CLRn7 Position */
+#define SCT_OUTPUTCLR1_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos) /*!< SCT OUTPUTCLR1: CLRn7 Mask */
+#define SCT_OUTPUTCLR1_CLRn8_Pos 8 /*!< SCT OUTPUTCLR1: CLRn8 Position */
+#define SCT_OUTPUTCLR1_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos) /*!< SCT OUTPUTCLR1: CLRn8 Mask */
+#define SCT_OUTPUTCLR1_CLRn9_Pos 9 /*!< SCT OUTPUTCLR1: CLRn9 Position */
+#define SCT_OUTPUTCLR1_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos) /*!< SCT OUTPUTCLR1: CLRn9 Mask */
+#define SCT_OUTPUTCLR1_CLRn10_Pos 10 /*!< SCT OUTPUTCLR1: CLRn10 Position */
+#define SCT_OUTPUTCLR1_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos) /*!< SCT OUTPUTCLR1: CLRn10 Mask */
+#define SCT_OUTPUTCLR1_CLRn11_Pos 11 /*!< SCT OUTPUTCLR1: CLRn11 Position */
+#define SCT_OUTPUTCLR1_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos) /*!< SCT OUTPUTCLR1: CLRn11 Mask */
+#define SCT_OUTPUTCLR1_CLRn12_Pos 12 /*!< SCT OUTPUTCLR1: CLRn12 Position */
+#define SCT_OUTPUTCLR1_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos) /*!< SCT OUTPUTCLR1: CLRn12 Mask */
+#define SCT_OUTPUTCLR1_CLRn13_Pos 13 /*!< SCT OUTPUTCLR1: CLRn13 Position */
+#define SCT_OUTPUTCLR1_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos) /*!< SCT OUTPUTCLR1: CLRn13 Mask */
+#define SCT_OUTPUTCLR1_CLRn14_Pos 14 /*!< SCT OUTPUTCLR1: CLRn14 Position */
+#define SCT_OUTPUTCLR1_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos) /*!< SCT OUTPUTCLR1: CLRn14 Mask */
+#define SCT_OUTPUTCLR1_CLRn15_Pos 15 /*!< SCT OUTPUTCLR1: CLRn15 Position */
+#define SCT_OUTPUTCLR1_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos) /*!< SCT OUTPUTCLR1: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET2 -----------------------------------------
+#define SCT_OUTPUTSET2_SETn0_Pos 0 /*!< SCT OUTPUTSET2: SETn0 Position */
+#define SCT_OUTPUTSET2_SETn0_Msk (0x01UL << SCT_OUTPUTSET2_SETn0_Pos) /*!< SCT OUTPUTSET2: SETn0 Mask */
+#define SCT_OUTPUTSET2_SETn1_Pos 1 /*!< SCT OUTPUTSET2: SETn1 Position */
+#define SCT_OUTPUTSET2_SETn1_Msk (0x01UL << SCT_OUTPUTSET2_SETn1_Pos) /*!< SCT OUTPUTSET2: SETn1 Mask */
+#define SCT_OUTPUTSET2_SETn2_Pos 2 /*!< SCT OUTPUTSET2: SETn2 Position */
+#define SCT_OUTPUTSET2_SETn2_Msk (0x01UL << SCT_OUTPUTSET2_SETn2_Pos) /*!< SCT OUTPUTSET2: SETn2 Mask */
+#define SCT_OUTPUTSET2_SETn3_Pos 3 /*!< SCT OUTPUTSET2: SETn3 Position */
+#define SCT_OUTPUTSET2_SETn3_Msk (0x01UL << SCT_OUTPUTSET2_SETn3_Pos) /*!< SCT OUTPUTSET2: SETn3 Mask */
+#define SCT_OUTPUTSET2_SETn4_Pos 4 /*!< SCT OUTPUTSET2: SETn4 Position */
+#define SCT_OUTPUTSET2_SETn4_Msk (0x01UL << SCT_OUTPUTSET2_SETn4_Pos) /*!< SCT OUTPUTSET2: SETn4 Mask */
+#define SCT_OUTPUTSET2_SETn5_Pos 5 /*!< SCT OUTPUTSET2: SETn5 Position */
+#define SCT_OUTPUTSET2_SETn5_Msk (0x01UL << SCT_OUTPUTSET2_SETn5_Pos) /*!< SCT OUTPUTSET2: SETn5 Mask */
+#define SCT_OUTPUTSET2_SETn6_Pos 6 /*!< SCT OUTPUTSET2: SETn6 Position */
+#define SCT_OUTPUTSET2_SETn6_Msk (0x01UL << SCT_OUTPUTSET2_SETn6_Pos) /*!< SCT OUTPUTSET2: SETn6 Mask */
+#define SCT_OUTPUTSET2_SETn7_Pos 7 /*!< SCT OUTPUTSET2: SETn7 Position */
+#define SCT_OUTPUTSET2_SETn7_Msk (0x01UL << SCT_OUTPUTSET2_SETn7_Pos) /*!< SCT OUTPUTSET2: SETn7 Mask */
+#define SCT_OUTPUTSET2_SETn8_Pos 8 /*!< SCT OUTPUTSET2: SETn8 Position */
+#define SCT_OUTPUTSET2_SETn8_Msk (0x01UL << SCT_OUTPUTSET2_SETn8_Pos) /*!< SCT OUTPUTSET2: SETn8 Mask */
+#define SCT_OUTPUTSET2_SETn9_Pos 9 /*!< SCT OUTPUTSET2: SETn9 Position */
+#define SCT_OUTPUTSET2_SETn9_Msk (0x01UL << SCT_OUTPUTSET2_SETn9_Pos) /*!< SCT OUTPUTSET2: SETn9 Mask */
+#define SCT_OUTPUTSET2_SETn10_Pos 10 /*!< SCT OUTPUTSET2: SETn10 Position */
+#define SCT_OUTPUTSET2_SETn10_Msk (0x01UL << SCT_OUTPUTSET2_SETn10_Pos) /*!< SCT OUTPUTSET2: SETn10 Mask */
+#define SCT_OUTPUTSET2_SETn11_Pos 11 /*!< SCT OUTPUTSET2: SETn11 Position */
+#define SCT_OUTPUTSET2_SETn11_Msk (0x01UL << SCT_OUTPUTSET2_SETn11_Pos) /*!< SCT OUTPUTSET2: SETn11 Mask */
+#define SCT_OUTPUTSET2_SETn12_Pos 12 /*!< SCT OUTPUTSET2: SETn12 Position */
+#define SCT_OUTPUTSET2_SETn12_Msk (0x01UL << SCT_OUTPUTSET2_SETn12_Pos) /*!< SCT OUTPUTSET2: SETn12 Mask */
+#define SCT_OUTPUTSET2_SETn13_Pos 13 /*!< SCT OUTPUTSET2: SETn13 Position */
+#define SCT_OUTPUTSET2_SETn13_Msk (0x01UL << SCT_OUTPUTSET2_SETn13_Pos) /*!< SCT OUTPUTSET2: SETn13 Mask */
+#define SCT_OUTPUTSET2_SETn14_Pos 14 /*!< SCT OUTPUTSET2: SETn14 Position */
+#define SCT_OUTPUTSET2_SETn14_Msk (0x01UL << SCT_OUTPUTSET2_SETn14_Pos) /*!< SCT OUTPUTSET2: SETn14 Mask */
+#define SCT_OUTPUTSET2_SETn15_Pos 15 /*!< SCT OUTPUTSET2: SETn15 Position */
+#define SCT_OUTPUTSET2_SETn15_Msk (0x01UL << SCT_OUTPUTSET2_SETn15_Pos) /*!< SCT OUTPUTSET2: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR2 -----------------------------------------
+#define SCT_OUTPUTCLR2_CLRn0_Pos 0 /*!< SCT OUTPUTCLR2: CLRn0 Position */
+#define SCT_OUTPUTCLR2_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos) /*!< SCT OUTPUTCLR2: CLRn0 Mask */
+#define SCT_OUTPUTCLR2_CLRn1_Pos 1 /*!< SCT OUTPUTCLR2: CLRn1 Position */
+#define SCT_OUTPUTCLR2_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos) /*!< SCT OUTPUTCLR2: CLRn1 Mask */
+#define SCT_OUTPUTCLR2_CLRn2_Pos 2 /*!< SCT OUTPUTCLR2: CLRn2 Position */
+#define SCT_OUTPUTCLR2_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos) /*!< SCT OUTPUTCLR2: CLRn2 Mask */
+#define SCT_OUTPUTCLR2_CLRn3_Pos 3 /*!< SCT OUTPUTCLR2: CLRn3 Position */
+#define SCT_OUTPUTCLR2_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos) /*!< SCT OUTPUTCLR2: CLRn3 Mask */
+#define SCT_OUTPUTCLR2_CLRn4_Pos 4 /*!< SCT OUTPUTCLR2: CLRn4 Position */
+#define SCT_OUTPUTCLR2_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos) /*!< SCT OUTPUTCLR2: CLRn4 Mask */
+#define SCT_OUTPUTCLR2_CLRn5_Pos 5 /*!< SCT OUTPUTCLR2: CLRn5 Position */
+#define SCT_OUTPUTCLR2_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos) /*!< SCT OUTPUTCLR2: CLRn5 Mask */
+#define SCT_OUTPUTCLR2_CLRn6_Pos 6 /*!< SCT OUTPUTCLR2: CLRn6 Position */
+#define SCT_OUTPUTCLR2_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos) /*!< SCT OUTPUTCLR2: CLRn6 Mask */
+#define SCT_OUTPUTCLR2_CLRn7_Pos 7 /*!< SCT OUTPUTCLR2: CLRn7 Position */
+#define SCT_OUTPUTCLR2_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos) /*!< SCT OUTPUTCLR2: CLRn7 Mask */
+#define SCT_OUTPUTCLR2_CLRn8_Pos 8 /*!< SCT OUTPUTCLR2: CLRn8 Position */
+#define SCT_OUTPUTCLR2_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos) /*!< SCT OUTPUTCLR2: CLRn8 Mask */
+#define SCT_OUTPUTCLR2_CLRn9_Pos 9 /*!< SCT OUTPUTCLR2: CLRn9 Position */
+#define SCT_OUTPUTCLR2_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos) /*!< SCT OUTPUTCLR2: CLRn9 Mask */
+#define SCT_OUTPUTCLR2_CLRn10_Pos 10 /*!< SCT OUTPUTCLR2: CLRn10 Position */
+#define SCT_OUTPUTCLR2_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos) /*!< SCT OUTPUTCLR2: CLRn10 Mask */
+#define SCT_OUTPUTCLR2_CLRn11_Pos 11 /*!< SCT OUTPUTCLR2: CLRn11 Position */
+#define SCT_OUTPUTCLR2_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos) /*!< SCT OUTPUTCLR2: CLRn11 Mask */
+#define SCT_OUTPUTCLR2_CLRn12_Pos 12 /*!< SCT OUTPUTCLR2: CLRn12 Position */
+#define SCT_OUTPUTCLR2_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos) /*!< SCT OUTPUTCLR2: CLRn12 Mask */
+#define SCT_OUTPUTCLR2_CLRn13_Pos 13 /*!< SCT OUTPUTCLR2: CLRn13 Position */
+#define SCT_OUTPUTCLR2_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos) /*!< SCT OUTPUTCLR2: CLRn13 Mask */
+#define SCT_OUTPUTCLR2_CLRn14_Pos 14 /*!< SCT OUTPUTCLR2: CLRn14 Position */
+#define SCT_OUTPUTCLR2_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos) /*!< SCT OUTPUTCLR2: CLRn14 Mask */
+#define SCT_OUTPUTCLR2_CLRn15_Pos 15 /*!< SCT OUTPUTCLR2: CLRn15 Position */
+#define SCT_OUTPUTCLR2_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos) /*!< SCT OUTPUTCLR2: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET3 -----------------------------------------
+#define SCT_OUTPUTSET3_SETn0_Pos 0 /*!< SCT OUTPUTSET3: SETn0 Position */
+#define SCT_OUTPUTSET3_SETn0_Msk (0x01UL << SCT_OUTPUTSET3_SETn0_Pos) /*!< SCT OUTPUTSET3: SETn0 Mask */
+#define SCT_OUTPUTSET3_SETn1_Pos 1 /*!< SCT OUTPUTSET3: SETn1 Position */
+#define SCT_OUTPUTSET3_SETn1_Msk (0x01UL << SCT_OUTPUTSET3_SETn1_Pos) /*!< SCT OUTPUTSET3: SETn1 Mask */
+#define SCT_OUTPUTSET3_SETn2_Pos 2 /*!< SCT OUTPUTSET3: SETn2 Position */
+#define SCT_OUTPUTSET3_SETn2_Msk (0x01UL << SCT_OUTPUTSET3_SETn2_Pos) /*!< SCT OUTPUTSET3: SETn2 Mask */
+#define SCT_OUTPUTSET3_SETn3_Pos 3 /*!< SCT OUTPUTSET3: SETn3 Position */
+#define SCT_OUTPUTSET3_SETn3_Msk (0x01UL << SCT_OUTPUTSET3_SETn3_Pos) /*!< SCT OUTPUTSET3: SETn3 Mask */
+#define SCT_OUTPUTSET3_SETn4_Pos 4 /*!< SCT OUTPUTSET3: SETn4 Position */
+#define SCT_OUTPUTSET3_SETn4_Msk (0x01UL << SCT_OUTPUTSET3_SETn4_Pos) /*!< SCT OUTPUTSET3: SETn4 Mask */
+#define SCT_OUTPUTSET3_SETn5_Pos 5 /*!< SCT OUTPUTSET3: SETn5 Position */
+#define SCT_OUTPUTSET3_SETn5_Msk (0x01UL << SCT_OUTPUTSET3_SETn5_Pos) /*!< SCT OUTPUTSET3: SETn5 Mask */
+#define SCT_OUTPUTSET3_SETn6_Pos 6 /*!< SCT OUTPUTSET3: SETn6 Position */
+#define SCT_OUTPUTSET3_SETn6_Msk (0x01UL << SCT_OUTPUTSET3_SETn6_Pos) /*!< SCT OUTPUTSET3: SETn6 Mask */
+#define SCT_OUTPUTSET3_SETn7_Pos 7 /*!< SCT OUTPUTSET3: SETn7 Position */
+#define SCT_OUTPUTSET3_SETn7_Msk (0x01UL << SCT_OUTPUTSET3_SETn7_Pos) /*!< SCT OUTPUTSET3: SETn7 Mask */
+#define SCT_OUTPUTSET3_SETn8_Pos 8 /*!< SCT OUTPUTSET3: SETn8 Position */
+#define SCT_OUTPUTSET3_SETn8_Msk (0x01UL << SCT_OUTPUTSET3_SETn8_Pos) /*!< SCT OUTPUTSET3: SETn8 Mask */
+#define SCT_OUTPUTSET3_SETn9_Pos 9 /*!< SCT OUTPUTSET3: SETn9 Position */
+#define SCT_OUTPUTSET3_SETn9_Msk (0x01UL << SCT_OUTPUTSET3_SETn9_Pos) /*!< SCT OUTPUTSET3: SETn9 Mask */
+#define SCT_OUTPUTSET3_SETn10_Pos 10 /*!< SCT OUTPUTSET3: SETn10 Position */
+#define SCT_OUTPUTSET3_SETn10_Msk (0x01UL << SCT_OUTPUTSET3_SETn10_Pos) /*!< SCT OUTPUTSET3: SETn10 Mask */
+#define SCT_OUTPUTSET3_SETn11_Pos 11 /*!< SCT OUTPUTSET3: SETn11 Position */
+#define SCT_OUTPUTSET3_SETn11_Msk (0x01UL << SCT_OUTPUTSET3_SETn11_Pos) /*!< SCT OUTPUTSET3: SETn11 Mask */
+#define SCT_OUTPUTSET3_SETn12_Pos 12 /*!< SCT OUTPUTSET3: SETn12 Position */
+#define SCT_OUTPUTSET3_SETn12_Msk (0x01UL << SCT_OUTPUTSET3_SETn12_Pos) /*!< SCT OUTPUTSET3: SETn12 Mask */
+#define SCT_OUTPUTSET3_SETn13_Pos 13 /*!< SCT OUTPUTSET3: SETn13 Position */
+#define SCT_OUTPUTSET3_SETn13_Msk (0x01UL << SCT_OUTPUTSET3_SETn13_Pos) /*!< SCT OUTPUTSET3: SETn13 Mask */
+#define SCT_OUTPUTSET3_SETn14_Pos 14 /*!< SCT OUTPUTSET3: SETn14 Position */
+#define SCT_OUTPUTSET3_SETn14_Msk (0x01UL << SCT_OUTPUTSET3_SETn14_Pos) /*!< SCT OUTPUTSET3: SETn14 Mask */
+#define SCT_OUTPUTSET3_SETn15_Pos 15 /*!< SCT OUTPUTSET3: SETn15 Position */
+#define SCT_OUTPUTSET3_SETn15_Msk (0x01UL << SCT_OUTPUTSET3_SETn15_Pos) /*!< SCT OUTPUTSET3: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR3 -----------------------------------------
+#define SCT_OUTPUTCLR3_CLRn0_Pos 0 /*!< SCT OUTPUTCLR3: CLRn0 Position */
+#define SCT_OUTPUTCLR3_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos) /*!< SCT OUTPUTCLR3: CLRn0 Mask */
+#define SCT_OUTPUTCLR3_CLRn1_Pos 1 /*!< SCT OUTPUTCLR3: CLRn1 Position */
+#define SCT_OUTPUTCLR3_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos) /*!< SCT OUTPUTCLR3: CLRn1 Mask */
+#define SCT_OUTPUTCLR3_CLRn2_Pos 2 /*!< SCT OUTPUTCLR3: CLRn2 Position */
+#define SCT_OUTPUTCLR3_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos) /*!< SCT OUTPUTCLR3: CLRn2 Mask */
+#define SCT_OUTPUTCLR3_CLRn3_Pos 3 /*!< SCT OUTPUTCLR3: CLRn3 Position */
+#define SCT_OUTPUTCLR3_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos) /*!< SCT OUTPUTCLR3: CLRn3 Mask */
+#define SCT_OUTPUTCLR3_CLRn4_Pos 4 /*!< SCT OUTPUTCLR3: CLRn4 Position */
+#define SCT_OUTPUTCLR3_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos) /*!< SCT OUTPUTCLR3: CLRn4 Mask */
+#define SCT_OUTPUTCLR3_CLRn5_Pos 5 /*!< SCT OUTPUTCLR3: CLRn5 Position */
+#define SCT_OUTPUTCLR3_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos) /*!< SCT OUTPUTCLR3: CLRn5 Mask */
+#define SCT_OUTPUTCLR3_CLRn6_Pos 6 /*!< SCT OUTPUTCLR3: CLRn6 Position */
+#define SCT_OUTPUTCLR3_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos) /*!< SCT OUTPUTCLR3: CLRn6 Mask */
+#define SCT_OUTPUTCLR3_CLRn7_Pos 7 /*!< SCT OUTPUTCLR3: CLRn7 Position */
+#define SCT_OUTPUTCLR3_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos) /*!< SCT OUTPUTCLR3: CLRn7 Mask */
+#define SCT_OUTPUTCLR3_CLRn8_Pos 8 /*!< SCT OUTPUTCLR3: CLRn8 Position */
+#define SCT_OUTPUTCLR3_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos) /*!< SCT OUTPUTCLR3: CLRn8 Mask */
+#define SCT_OUTPUTCLR3_CLRn9_Pos 9 /*!< SCT OUTPUTCLR3: CLRn9 Position */
+#define SCT_OUTPUTCLR3_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos) /*!< SCT OUTPUTCLR3: CLRn9 Mask */
+#define SCT_OUTPUTCLR3_CLRn10_Pos 10 /*!< SCT OUTPUTCLR3: CLRn10 Position */
+#define SCT_OUTPUTCLR3_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos) /*!< SCT OUTPUTCLR3: CLRn10 Mask */
+#define SCT_OUTPUTCLR3_CLRn11_Pos 11 /*!< SCT OUTPUTCLR3: CLRn11 Position */
+#define SCT_OUTPUTCLR3_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos) /*!< SCT OUTPUTCLR3: CLRn11 Mask */
+#define SCT_OUTPUTCLR3_CLRn12_Pos 12 /*!< SCT OUTPUTCLR3: CLRn12 Position */
+#define SCT_OUTPUTCLR3_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos) /*!< SCT OUTPUTCLR3: CLRn12 Mask */
+#define SCT_OUTPUTCLR3_CLRn13_Pos 13 /*!< SCT OUTPUTCLR3: CLRn13 Position */
+#define SCT_OUTPUTCLR3_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos) /*!< SCT OUTPUTCLR3: CLRn13 Mask */
+#define SCT_OUTPUTCLR3_CLRn14_Pos 14 /*!< SCT OUTPUTCLR3: CLRn14 Position */
+#define SCT_OUTPUTCLR3_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos) /*!< SCT OUTPUTCLR3: CLRn14 Mask */
+#define SCT_OUTPUTCLR3_CLRn15_Pos 15 /*!< SCT OUTPUTCLR3: CLRn15 Position */
+#define SCT_OUTPUTCLR3_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos) /*!< SCT OUTPUTCLR3: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET4 -----------------------------------------
+#define SCT_OUTPUTSET4_SETn0_Pos 0 /*!< SCT OUTPUTSET4: SETn0 Position */
+#define SCT_OUTPUTSET4_SETn0_Msk (0x01UL << SCT_OUTPUTSET4_SETn0_Pos) /*!< SCT OUTPUTSET4: SETn0 Mask */
+#define SCT_OUTPUTSET4_SETn1_Pos 1 /*!< SCT OUTPUTSET4: SETn1 Position */
+#define SCT_OUTPUTSET4_SETn1_Msk (0x01UL << SCT_OUTPUTSET4_SETn1_Pos) /*!< SCT OUTPUTSET4: SETn1 Mask */
+#define SCT_OUTPUTSET4_SETn2_Pos 2 /*!< SCT OUTPUTSET4: SETn2 Position */
+#define SCT_OUTPUTSET4_SETn2_Msk (0x01UL << SCT_OUTPUTSET4_SETn2_Pos) /*!< SCT OUTPUTSET4: SETn2 Mask */
+#define SCT_OUTPUTSET4_SETn3_Pos 3 /*!< SCT OUTPUTSET4: SETn3 Position */
+#define SCT_OUTPUTSET4_SETn3_Msk (0x01UL << SCT_OUTPUTSET4_SETn3_Pos) /*!< SCT OUTPUTSET4: SETn3 Mask */
+#define SCT_OUTPUTSET4_SETn4_Pos 4 /*!< SCT OUTPUTSET4: SETn4 Position */
+#define SCT_OUTPUTSET4_SETn4_Msk (0x01UL << SCT_OUTPUTSET4_SETn4_Pos) /*!< SCT OUTPUTSET4: SETn4 Mask */
+#define SCT_OUTPUTSET4_SETn5_Pos 5 /*!< SCT OUTPUTSET4: SETn5 Position */
+#define SCT_OUTPUTSET4_SETn5_Msk (0x01UL << SCT_OUTPUTSET4_SETn5_Pos) /*!< SCT OUTPUTSET4: SETn5 Mask */
+#define SCT_OUTPUTSET4_SETn6_Pos 6 /*!< SCT OUTPUTSET4: SETn6 Position */
+#define SCT_OUTPUTSET4_SETn6_Msk (0x01UL << SCT_OUTPUTSET4_SETn6_Pos) /*!< SCT OUTPUTSET4: SETn6 Mask */
+#define SCT_OUTPUTSET4_SETn7_Pos 7 /*!< SCT OUTPUTSET4: SETn7 Position */
+#define SCT_OUTPUTSET4_SETn7_Msk (0x01UL << SCT_OUTPUTSET4_SETn7_Pos) /*!< SCT OUTPUTSET4: SETn7 Mask */
+#define SCT_OUTPUTSET4_SETn8_Pos 8 /*!< SCT OUTPUTSET4: SETn8 Position */
+#define SCT_OUTPUTSET4_SETn8_Msk (0x01UL << SCT_OUTPUTSET4_SETn8_Pos) /*!< SCT OUTPUTSET4: SETn8 Mask */
+#define SCT_OUTPUTSET4_SETn9_Pos 9 /*!< SCT OUTPUTSET4: SETn9 Position */
+#define SCT_OUTPUTSET4_SETn9_Msk (0x01UL << SCT_OUTPUTSET4_SETn9_Pos) /*!< SCT OUTPUTSET4: SETn9 Mask */
+#define SCT_OUTPUTSET4_SETn10_Pos 10 /*!< SCT OUTPUTSET4: SETn10 Position */
+#define SCT_OUTPUTSET4_SETn10_Msk (0x01UL << SCT_OUTPUTSET4_SETn10_Pos) /*!< SCT OUTPUTSET4: SETn10 Mask */
+#define SCT_OUTPUTSET4_SETn11_Pos 11 /*!< SCT OUTPUTSET4: SETn11 Position */
+#define SCT_OUTPUTSET4_SETn11_Msk (0x01UL << SCT_OUTPUTSET4_SETn11_Pos) /*!< SCT OUTPUTSET4: SETn11 Mask */
+#define SCT_OUTPUTSET4_SETn12_Pos 12 /*!< SCT OUTPUTSET4: SETn12 Position */
+#define SCT_OUTPUTSET4_SETn12_Msk (0x01UL << SCT_OUTPUTSET4_SETn12_Pos) /*!< SCT OUTPUTSET4: SETn12 Mask */
+#define SCT_OUTPUTSET4_SETn13_Pos 13 /*!< SCT OUTPUTSET4: SETn13 Position */
+#define SCT_OUTPUTSET4_SETn13_Msk (0x01UL << SCT_OUTPUTSET4_SETn13_Pos) /*!< SCT OUTPUTSET4: SETn13 Mask */
+#define SCT_OUTPUTSET4_SETn14_Pos 14 /*!< SCT OUTPUTSET4: SETn14 Position */
+#define SCT_OUTPUTSET4_SETn14_Msk (0x01UL << SCT_OUTPUTSET4_SETn14_Pos) /*!< SCT OUTPUTSET4: SETn14 Mask */
+#define SCT_OUTPUTSET4_SETn15_Pos 15 /*!< SCT OUTPUTSET4: SETn15 Position */
+#define SCT_OUTPUTSET4_SETn15_Msk (0x01UL << SCT_OUTPUTSET4_SETn15_Pos) /*!< SCT OUTPUTSET4: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR4 -----------------------------------------
+#define SCT_OUTPUTCLR4_CLRn0_Pos 0 /*!< SCT OUTPUTCLR4: CLRn0 Position */
+#define SCT_OUTPUTCLR4_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos) /*!< SCT OUTPUTCLR4: CLRn0 Mask */
+#define SCT_OUTPUTCLR4_CLRn1_Pos 1 /*!< SCT OUTPUTCLR4: CLRn1 Position */
+#define SCT_OUTPUTCLR4_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos) /*!< SCT OUTPUTCLR4: CLRn1 Mask */
+#define SCT_OUTPUTCLR4_CLRn2_Pos 2 /*!< SCT OUTPUTCLR4: CLRn2 Position */
+#define SCT_OUTPUTCLR4_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos) /*!< SCT OUTPUTCLR4: CLRn2 Mask */
+#define SCT_OUTPUTCLR4_CLRn3_Pos 3 /*!< SCT OUTPUTCLR4: CLRn3 Position */
+#define SCT_OUTPUTCLR4_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos) /*!< SCT OUTPUTCLR4: CLRn3 Mask */
+#define SCT_OUTPUTCLR4_CLRn4_Pos 4 /*!< SCT OUTPUTCLR4: CLRn4 Position */
+#define SCT_OUTPUTCLR4_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos) /*!< SCT OUTPUTCLR4: CLRn4 Mask */
+#define SCT_OUTPUTCLR4_CLRn5_Pos 5 /*!< SCT OUTPUTCLR4: CLRn5 Position */
+#define SCT_OUTPUTCLR4_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos) /*!< SCT OUTPUTCLR4: CLRn5 Mask */
+#define SCT_OUTPUTCLR4_CLRn6_Pos 6 /*!< SCT OUTPUTCLR4: CLRn6 Position */
+#define SCT_OUTPUTCLR4_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos) /*!< SCT OUTPUTCLR4: CLRn6 Mask */
+#define SCT_OUTPUTCLR4_CLRn7_Pos 7 /*!< SCT OUTPUTCLR4: CLRn7 Position */
+#define SCT_OUTPUTCLR4_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos) /*!< SCT OUTPUTCLR4: CLRn7 Mask */
+#define SCT_OUTPUTCLR4_CLRn8_Pos 8 /*!< SCT OUTPUTCLR4: CLRn8 Position */
+#define SCT_OUTPUTCLR4_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos) /*!< SCT OUTPUTCLR4: CLRn8 Mask */
+#define SCT_OUTPUTCLR4_CLRn9_Pos 9 /*!< SCT OUTPUTCLR4: CLRn9 Position */
+#define SCT_OUTPUTCLR4_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos) /*!< SCT OUTPUTCLR4: CLRn9 Mask */
+#define SCT_OUTPUTCLR4_CLRn10_Pos 10 /*!< SCT OUTPUTCLR4: CLRn10 Position */
+#define SCT_OUTPUTCLR4_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos) /*!< SCT OUTPUTCLR4: CLRn10 Mask */
+#define SCT_OUTPUTCLR4_CLRn11_Pos 11 /*!< SCT OUTPUTCLR4: CLRn11 Position */
+#define SCT_OUTPUTCLR4_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos) /*!< SCT OUTPUTCLR4: CLRn11 Mask */
+#define SCT_OUTPUTCLR4_CLRn12_Pos 12 /*!< SCT OUTPUTCLR4: CLRn12 Position */
+#define SCT_OUTPUTCLR4_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos) /*!< SCT OUTPUTCLR4: CLRn12 Mask */
+#define SCT_OUTPUTCLR4_CLRn13_Pos 13 /*!< SCT OUTPUTCLR4: CLRn13 Position */
+#define SCT_OUTPUTCLR4_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos) /*!< SCT OUTPUTCLR4: CLRn13 Mask */
+#define SCT_OUTPUTCLR4_CLRn14_Pos 14 /*!< SCT OUTPUTCLR4: CLRn14 Position */
+#define SCT_OUTPUTCLR4_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos) /*!< SCT OUTPUTCLR4: CLRn14 Mask */
+#define SCT_OUTPUTCLR4_CLRn15_Pos 15 /*!< SCT OUTPUTCLR4: CLRn15 Position */
+#define SCT_OUTPUTCLR4_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos) /*!< SCT OUTPUTCLR4: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET5 -----------------------------------------
+#define SCT_OUTPUTSET5_SETn0_Pos 0 /*!< SCT OUTPUTSET5: SETn0 Position */
+#define SCT_OUTPUTSET5_SETn0_Msk (0x01UL << SCT_OUTPUTSET5_SETn0_Pos) /*!< SCT OUTPUTSET5: SETn0 Mask */
+#define SCT_OUTPUTSET5_SETn1_Pos 1 /*!< SCT OUTPUTSET5: SETn1 Position */
+#define SCT_OUTPUTSET5_SETn1_Msk (0x01UL << SCT_OUTPUTSET5_SETn1_Pos) /*!< SCT OUTPUTSET5: SETn1 Mask */
+#define SCT_OUTPUTSET5_SETn2_Pos 2 /*!< SCT OUTPUTSET5: SETn2 Position */
+#define SCT_OUTPUTSET5_SETn2_Msk (0x01UL << SCT_OUTPUTSET5_SETn2_Pos) /*!< SCT OUTPUTSET5: SETn2 Mask */
+#define SCT_OUTPUTSET5_SETn3_Pos 3 /*!< SCT OUTPUTSET5: SETn3 Position */
+#define SCT_OUTPUTSET5_SETn3_Msk (0x01UL << SCT_OUTPUTSET5_SETn3_Pos) /*!< SCT OUTPUTSET5: SETn3 Mask */
+#define SCT_OUTPUTSET5_SETn4_Pos 4 /*!< SCT OUTPUTSET5: SETn4 Position */
+#define SCT_OUTPUTSET5_SETn4_Msk (0x01UL << SCT_OUTPUTSET5_SETn4_Pos) /*!< SCT OUTPUTSET5: SETn4 Mask */
+#define SCT_OUTPUTSET5_SETn5_Pos 5 /*!< SCT OUTPUTSET5: SETn5 Position */
+#define SCT_OUTPUTSET5_SETn5_Msk (0x01UL << SCT_OUTPUTSET5_SETn5_Pos) /*!< SCT OUTPUTSET5: SETn5 Mask */
+#define SCT_OUTPUTSET5_SETn6_Pos 6 /*!< SCT OUTPUTSET5: SETn6 Position */
+#define SCT_OUTPUTSET5_SETn6_Msk (0x01UL << SCT_OUTPUTSET5_SETn6_Pos) /*!< SCT OUTPUTSET5: SETn6 Mask */
+#define SCT_OUTPUTSET5_SETn7_Pos 7 /*!< SCT OUTPUTSET5: SETn7 Position */
+#define SCT_OUTPUTSET5_SETn7_Msk (0x01UL << SCT_OUTPUTSET5_SETn7_Pos) /*!< SCT OUTPUTSET5: SETn7 Mask */
+#define SCT_OUTPUTSET5_SETn8_Pos 8 /*!< SCT OUTPUTSET5: SETn8 Position */
+#define SCT_OUTPUTSET5_SETn8_Msk (0x01UL << SCT_OUTPUTSET5_SETn8_Pos) /*!< SCT OUTPUTSET5: SETn8 Mask */
+#define SCT_OUTPUTSET5_SETn9_Pos 9 /*!< SCT OUTPUTSET5: SETn9 Position */
+#define SCT_OUTPUTSET5_SETn9_Msk (0x01UL << SCT_OUTPUTSET5_SETn9_Pos) /*!< SCT OUTPUTSET5: SETn9 Mask */
+#define SCT_OUTPUTSET5_SETn10_Pos 10 /*!< SCT OUTPUTSET5: SETn10 Position */
+#define SCT_OUTPUTSET5_SETn10_Msk (0x01UL << SCT_OUTPUTSET5_SETn10_Pos) /*!< SCT OUTPUTSET5: SETn10 Mask */
+#define SCT_OUTPUTSET5_SETn11_Pos 11 /*!< SCT OUTPUTSET5: SETn11 Position */
+#define SCT_OUTPUTSET5_SETn11_Msk (0x01UL << SCT_OUTPUTSET5_SETn11_Pos) /*!< SCT OUTPUTSET5: SETn11 Mask */
+#define SCT_OUTPUTSET5_SETn12_Pos 12 /*!< SCT OUTPUTSET5: SETn12 Position */
+#define SCT_OUTPUTSET5_SETn12_Msk (0x01UL << SCT_OUTPUTSET5_SETn12_Pos) /*!< SCT OUTPUTSET5: SETn12 Mask */
+#define SCT_OUTPUTSET5_SETn13_Pos 13 /*!< SCT OUTPUTSET5: SETn13 Position */
+#define SCT_OUTPUTSET5_SETn13_Msk (0x01UL << SCT_OUTPUTSET5_SETn13_Pos) /*!< SCT OUTPUTSET5: SETn13 Mask */
+#define SCT_OUTPUTSET5_SETn14_Pos 14 /*!< SCT OUTPUTSET5: SETn14 Position */
+#define SCT_OUTPUTSET5_SETn14_Msk (0x01UL << SCT_OUTPUTSET5_SETn14_Pos) /*!< SCT OUTPUTSET5: SETn14 Mask */
+#define SCT_OUTPUTSET5_SETn15_Pos 15 /*!< SCT OUTPUTSET5: SETn15 Position */
+#define SCT_OUTPUTSET5_SETn15_Msk (0x01UL << SCT_OUTPUTSET5_SETn15_Pos) /*!< SCT OUTPUTSET5: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR5 -----------------------------------------
+#define SCT_OUTPUTCLR5_CLRn0_Pos 0 /*!< SCT OUTPUTCLR5: CLRn0 Position */
+#define SCT_OUTPUTCLR5_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos) /*!< SCT OUTPUTCLR5: CLRn0 Mask */
+#define SCT_OUTPUTCLR5_CLRn1_Pos 1 /*!< SCT OUTPUTCLR5: CLRn1 Position */
+#define SCT_OUTPUTCLR5_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos) /*!< SCT OUTPUTCLR5: CLRn1 Mask */
+#define SCT_OUTPUTCLR5_CLRn2_Pos 2 /*!< SCT OUTPUTCLR5: CLRn2 Position */
+#define SCT_OUTPUTCLR5_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos) /*!< SCT OUTPUTCLR5: CLRn2 Mask */
+#define SCT_OUTPUTCLR5_CLRn3_Pos 3 /*!< SCT OUTPUTCLR5: CLRn3 Position */
+#define SCT_OUTPUTCLR5_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos) /*!< SCT OUTPUTCLR5: CLRn3 Mask */
+#define SCT_OUTPUTCLR5_CLRn4_Pos 4 /*!< SCT OUTPUTCLR5: CLRn4 Position */
+#define SCT_OUTPUTCLR5_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos) /*!< SCT OUTPUTCLR5: CLRn4 Mask */
+#define SCT_OUTPUTCLR5_CLRn5_Pos 5 /*!< SCT OUTPUTCLR5: CLRn5 Position */
+#define SCT_OUTPUTCLR5_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos) /*!< SCT OUTPUTCLR5: CLRn5 Mask */
+#define SCT_OUTPUTCLR5_CLRn6_Pos 6 /*!< SCT OUTPUTCLR5: CLRn6 Position */
+#define SCT_OUTPUTCLR5_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos) /*!< SCT OUTPUTCLR5: CLRn6 Mask */
+#define SCT_OUTPUTCLR5_CLRn7_Pos 7 /*!< SCT OUTPUTCLR5: CLRn7 Position */
+#define SCT_OUTPUTCLR5_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos) /*!< SCT OUTPUTCLR5: CLRn7 Mask */
+#define SCT_OUTPUTCLR5_CLRn8_Pos 8 /*!< SCT OUTPUTCLR5: CLRn8 Position */
+#define SCT_OUTPUTCLR5_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos) /*!< SCT OUTPUTCLR5: CLRn8 Mask */
+#define SCT_OUTPUTCLR5_CLRn9_Pos 9 /*!< SCT OUTPUTCLR5: CLRn9 Position */
+#define SCT_OUTPUTCLR5_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos) /*!< SCT OUTPUTCLR5: CLRn9 Mask */
+#define SCT_OUTPUTCLR5_CLRn10_Pos 10 /*!< SCT OUTPUTCLR5: CLRn10 Position */
+#define SCT_OUTPUTCLR5_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos) /*!< SCT OUTPUTCLR5: CLRn10 Mask */
+#define SCT_OUTPUTCLR5_CLRn11_Pos 11 /*!< SCT OUTPUTCLR5: CLRn11 Position */
+#define SCT_OUTPUTCLR5_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos) /*!< SCT OUTPUTCLR5: CLRn11 Mask */
+#define SCT_OUTPUTCLR5_CLRn12_Pos 12 /*!< SCT OUTPUTCLR5: CLRn12 Position */
+#define SCT_OUTPUTCLR5_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos) /*!< SCT OUTPUTCLR5: CLRn12 Mask */
+#define SCT_OUTPUTCLR5_CLRn13_Pos 13 /*!< SCT OUTPUTCLR5: CLRn13 Position */
+#define SCT_OUTPUTCLR5_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos) /*!< SCT OUTPUTCLR5: CLRn13 Mask */
+#define SCT_OUTPUTCLR5_CLRn14_Pos 14 /*!< SCT OUTPUTCLR5: CLRn14 Position */
+#define SCT_OUTPUTCLR5_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos) /*!< SCT OUTPUTCLR5: CLRn14 Mask */
+#define SCT_OUTPUTCLR5_CLRn15_Pos 15 /*!< SCT OUTPUTCLR5: CLRn15 Position */
+#define SCT_OUTPUTCLR5_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos) /*!< SCT OUTPUTCLR5: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET6 -----------------------------------------
+#define SCT_OUTPUTSET6_SETn0_Pos 0 /*!< SCT OUTPUTSET6: SETn0 Position */
+#define SCT_OUTPUTSET6_SETn0_Msk (0x01UL << SCT_OUTPUTSET6_SETn0_Pos) /*!< SCT OUTPUTSET6: SETn0 Mask */
+#define SCT_OUTPUTSET6_SETn1_Pos 1 /*!< SCT OUTPUTSET6: SETn1 Position */
+#define SCT_OUTPUTSET6_SETn1_Msk (0x01UL << SCT_OUTPUTSET6_SETn1_Pos) /*!< SCT OUTPUTSET6: SETn1 Mask */
+#define SCT_OUTPUTSET6_SETn2_Pos 2 /*!< SCT OUTPUTSET6: SETn2 Position */
+#define SCT_OUTPUTSET6_SETn2_Msk (0x01UL << SCT_OUTPUTSET6_SETn2_Pos) /*!< SCT OUTPUTSET6: SETn2 Mask */
+#define SCT_OUTPUTSET6_SETn3_Pos 3 /*!< SCT OUTPUTSET6: SETn3 Position */
+#define SCT_OUTPUTSET6_SETn3_Msk (0x01UL << SCT_OUTPUTSET6_SETn3_Pos) /*!< SCT OUTPUTSET6: SETn3 Mask */
+#define SCT_OUTPUTSET6_SETn4_Pos 4 /*!< SCT OUTPUTSET6: SETn4 Position */
+#define SCT_OUTPUTSET6_SETn4_Msk (0x01UL << SCT_OUTPUTSET6_SETn4_Pos) /*!< SCT OUTPUTSET6: SETn4 Mask */
+#define SCT_OUTPUTSET6_SETn5_Pos 5 /*!< SCT OUTPUTSET6: SETn5 Position */
+#define SCT_OUTPUTSET6_SETn5_Msk (0x01UL << SCT_OUTPUTSET6_SETn5_Pos) /*!< SCT OUTPUTSET6: SETn5 Mask */
+#define SCT_OUTPUTSET6_SETn6_Pos 6 /*!< SCT OUTPUTSET6: SETn6 Position */
+#define SCT_OUTPUTSET6_SETn6_Msk (0x01UL << SCT_OUTPUTSET6_SETn6_Pos) /*!< SCT OUTPUTSET6: SETn6 Mask */
+#define SCT_OUTPUTSET6_SETn7_Pos 7 /*!< SCT OUTPUTSET6: SETn7 Position */
+#define SCT_OUTPUTSET6_SETn7_Msk (0x01UL << SCT_OUTPUTSET6_SETn7_Pos) /*!< SCT OUTPUTSET6: SETn7 Mask */
+#define SCT_OUTPUTSET6_SETn8_Pos 8 /*!< SCT OUTPUTSET6: SETn8 Position */
+#define SCT_OUTPUTSET6_SETn8_Msk (0x01UL << SCT_OUTPUTSET6_SETn8_Pos) /*!< SCT OUTPUTSET6: SETn8 Mask */
+#define SCT_OUTPUTSET6_SETn9_Pos 9 /*!< SCT OUTPUTSET6: SETn9 Position */
+#define SCT_OUTPUTSET6_SETn9_Msk (0x01UL << SCT_OUTPUTSET6_SETn9_Pos) /*!< SCT OUTPUTSET6: SETn9 Mask */
+#define SCT_OUTPUTSET6_SETn10_Pos 10 /*!< SCT OUTPUTSET6: SETn10 Position */
+#define SCT_OUTPUTSET6_SETn10_Msk (0x01UL << SCT_OUTPUTSET6_SETn10_Pos) /*!< SCT OUTPUTSET6: SETn10 Mask */
+#define SCT_OUTPUTSET6_SETn11_Pos 11 /*!< SCT OUTPUTSET6: SETn11 Position */
+#define SCT_OUTPUTSET6_SETn11_Msk (0x01UL << SCT_OUTPUTSET6_SETn11_Pos) /*!< SCT OUTPUTSET6: SETn11 Mask */
+#define SCT_OUTPUTSET6_SETn12_Pos 12 /*!< SCT OUTPUTSET6: SETn12 Position */
+#define SCT_OUTPUTSET6_SETn12_Msk (0x01UL << SCT_OUTPUTSET6_SETn12_Pos) /*!< SCT OUTPUTSET6: SETn12 Mask */
+#define SCT_OUTPUTSET6_SETn13_Pos 13 /*!< SCT OUTPUTSET6: SETn13 Position */
+#define SCT_OUTPUTSET6_SETn13_Msk (0x01UL << SCT_OUTPUTSET6_SETn13_Pos) /*!< SCT OUTPUTSET6: SETn13 Mask */
+#define SCT_OUTPUTSET6_SETn14_Pos 14 /*!< SCT OUTPUTSET6: SETn14 Position */
+#define SCT_OUTPUTSET6_SETn14_Msk (0x01UL << SCT_OUTPUTSET6_SETn14_Pos) /*!< SCT OUTPUTSET6: SETn14 Mask */
+#define SCT_OUTPUTSET6_SETn15_Pos 15 /*!< SCT OUTPUTSET6: SETn15 Position */
+#define SCT_OUTPUTSET6_SETn15_Msk (0x01UL << SCT_OUTPUTSET6_SETn15_Pos) /*!< SCT OUTPUTSET6: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR6 -----------------------------------------
+#define SCT_OUTPUTCLR6_CLRn0_Pos 0 /*!< SCT OUTPUTCLR6: CLRn0 Position */
+#define SCT_OUTPUTCLR6_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos) /*!< SCT OUTPUTCLR6: CLRn0 Mask */
+#define SCT_OUTPUTCLR6_CLRn1_Pos 1 /*!< SCT OUTPUTCLR6: CLRn1 Position */
+#define SCT_OUTPUTCLR6_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos) /*!< SCT OUTPUTCLR6: CLRn1 Mask */
+#define SCT_OUTPUTCLR6_CLRn2_Pos 2 /*!< SCT OUTPUTCLR6: CLRn2 Position */
+#define SCT_OUTPUTCLR6_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos) /*!< SCT OUTPUTCLR6: CLRn2 Mask */
+#define SCT_OUTPUTCLR6_CLRn3_Pos 3 /*!< SCT OUTPUTCLR6: CLRn3 Position */
+#define SCT_OUTPUTCLR6_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos) /*!< SCT OUTPUTCLR6: CLRn3 Mask */
+#define SCT_OUTPUTCLR6_CLRn4_Pos 4 /*!< SCT OUTPUTCLR6: CLRn4 Position */
+#define SCT_OUTPUTCLR6_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos) /*!< SCT OUTPUTCLR6: CLRn4 Mask */
+#define SCT_OUTPUTCLR6_CLRn5_Pos 5 /*!< SCT OUTPUTCLR6: CLRn5 Position */
+#define SCT_OUTPUTCLR6_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos) /*!< SCT OUTPUTCLR6: CLRn5 Mask */
+#define SCT_OUTPUTCLR6_CLRn6_Pos 6 /*!< SCT OUTPUTCLR6: CLRn6 Position */
+#define SCT_OUTPUTCLR6_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos) /*!< SCT OUTPUTCLR6: CLRn6 Mask */
+#define SCT_OUTPUTCLR6_CLRn7_Pos 7 /*!< SCT OUTPUTCLR6: CLRn7 Position */
+#define SCT_OUTPUTCLR6_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos) /*!< SCT OUTPUTCLR6: CLRn7 Mask */
+#define SCT_OUTPUTCLR6_CLRn8_Pos 8 /*!< SCT OUTPUTCLR6: CLRn8 Position */
+#define SCT_OUTPUTCLR6_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos) /*!< SCT OUTPUTCLR6: CLRn8 Mask */
+#define SCT_OUTPUTCLR6_CLRn9_Pos 9 /*!< SCT OUTPUTCLR6: CLRn9 Position */
+#define SCT_OUTPUTCLR6_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos) /*!< SCT OUTPUTCLR6: CLRn9 Mask */
+#define SCT_OUTPUTCLR6_CLRn10_Pos 10 /*!< SCT OUTPUTCLR6: CLRn10 Position */
+#define SCT_OUTPUTCLR6_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos) /*!< SCT OUTPUTCLR6: CLRn10 Mask */
+#define SCT_OUTPUTCLR6_CLRn11_Pos 11 /*!< SCT OUTPUTCLR6: CLRn11 Position */
+#define SCT_OUTPUTCLR6_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos) /*!< SCT OUTPUTCLR6: CLRn11 Mask */
+#define SCT_OUTPUTCLR6_CLRn12_Pos 12 /*!< SCT OUTPUTCLR6: CLRn12 Position */
+#define SCT_OUTPUTCLR6_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos) /*!< SCT OUTPUTCLR6: CLRn12 Mask */
+#define SCT_OUTPUTCLR6_CLRn13_Pos 13 /*!< SCT OUTPUTCLR6: CLRn13 Position */
+#define SCT_OUTPUTCLR6_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos) /*!< SCT OUTPUTCLR6: CLRn13 Mask */
+#define SCT_OUTPUTCLR6_CLRn14_Pos 14 /*!< SCT OUTPUTCLR6: CLRn14 Position */
+#define SCT_OUTPUTCLR6_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos) /*!< SCT OUTPUTCLR6: CLRn14 Mask */
+#define SCT_OUTPUTCLR6_CLRn15_Pos 15 /*!< SCT OUTPUTCLR6: CLRn15 Position */
+#define SCT_OUTPUTCLR6_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos) /*!< SCT OUTPUTCLR6: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET7 -----------------------------------------
+#define SCT_OUTPUTSET7_SETn0_Pos 0 /*!< SCT OUTPUTSET7: SETn0 Position */
+#define SCT_OUTPUTSET7_SETn0_Msk (0x01UL << SCT_OUTPUTSET7_SETn0_Pos) /*!< SCT OUTPUTSET7: SETn0 Mask */
+#define SCT_OUTPUTSET7_SETn1_Pos 1 /*!< SCT OUTPUTSET7: SETn1 Position */
+#define SCT_OUTPUTSET7_SETn1_Msk (0x01UL << SCT_OUTPUTSET7_SETn1_Pos) /*!< SCT OUTPUTSET7: SETn1 Mask */
+#define SCT_OUTPUTSET7_SETn2_Pos 2 /*!< SCT OUTPUTSET7: SETn2 Position */
+#define SCT_OUTPUTSET7_SETn2_Msk (0x01UL << SCT_OUTPUTSET7_SETn2_Pos) /*!< SCT OUTPUTSET7: SETn2 Mask */
+#define SCT_OUTPUTSET7_SETn3_Pos 3 /*!< SCT OUTPUTSET7: SETn3 Position */
+#define SCT_OUTPUTSET7_SETn3_Msk (0x01UL << SCT_OUTPUTSET7_SETn3_Pos) /*!< SCT OUTPUTSET7: SETn3 Mask */
+#define SCT_OUTPUTSET7_SETn4_Pos 4 /*!< SCT OUTPUTSET7: SETn4 Position */
+#define SCT_OUTPUTSET7_SETn4_Msk (0x01UL << SCT_OUTPUTSET7_SETn4_Pos) /*!< SCT OUTPUTSET7: SETn4 Mask */
+#define SCT_OUTPUTSET7_SETn5_Pos 5 /*!< SCT OUTPUTSET7: SETn5 Position */
+#define SCT_OUTPUTSET7_SETn5_Msk (0x01UL << SCT_OUTPUTSET7_SETn5_Pos) /*!< SCT OUTPUTSET7: SETn5 Mask */
+#define SCT_OUTPUTSET7_SETn6_Pos 6 /*!< SCT OUTPUTSET7: SETn6 Position */
+#define SCT_OUTPUTSET7_SETn6_Msk (0x01UL << SCT_OUTPUTSET7_SETn6_Pos) /*!< SCT OUTPUTSET7: SETn6 Mask */
+#define SCT_OUTPUTSET7_SETn7_Pos 7 /*!< SCT OUTPUTSET7: SETn7 Position */
+#define SCT_OUTPUTSET7_SETn7_Msk (0x01UL << SCT_OUTPUTSET7_SETn7_Pos) /*!< SCT OUTPUTSET7: SETn7 Mask */
+#define SCT_OUTPUTSET7_SETn8_Pos 8 /*!< SCT OUTPUTSET7: SETn8 Position */
+#define SCT_OUTPUTSET7_SETn8_Msk (0x01UL << SCT_OUTPUTSET7_SETn8_Pos) /*!< SCT OUTPUTSET7: SETn8 Mask */
+#define SCT_OUTPUTSET7_SETn9_Pos 9 /*!< SCT OUTPUTSET7: SETn9 Position */
+#define SCT_OUTPUTSET7_SETn9_Msk (0x01UL << SCT_OUTPUTSET7_SETn9_Pos) /*!< SCT OUTPUTSET7: SETn9 Mask */
+#define SCT_OUTPUTSET7_SETn10_Pos 10 /*!< SCT OUTPUTSET7: SETn10 Position */
+#define SCT_OUTPUTSET7_SETn10_Msk (0x01UL << SCT_OUTPUTSET7_SETn10_Pos) /*!< SCT OUTPUTSET7: SETn10 Mask */
+#define SCT_OUTPUTSET7_SETn11_Pos 11 /*!< SCT OUTPUTSET7: SETn11 Position */
+#define SCT_OUTPUTSET7_SETn11_Msk (0x01UL << SCT_OUTPUTSET7_SETn11_Pos) /*!< SCT OUTPUTSET7: SETn11 Mask */
+#define SCT_OUTPUTSET7_SETn12_Pos 12 /*!< SCT OUTPUTSET7: SETn12 Position */
+#define SCT_OUTPUTSET7_SETn12_Msk (0x01UL << SCT_OUTPUTSET7_SETn12_Pos) /*!< SCT OUTPUTSET7: SETn12 Mask */
+#define SCT_OUTPUTSET7_SETn13_Pos 13 /*!< SCT OUTPUTSET7: SETn13 Position */
+#define SCT_OUTPUTSET7_SETn13_Msk (0x01UL << SCT_OUTPUTSET7_SETn13_Pos) /*!< SCT OUTPUTSET7: SETn13 Mask */
+#define SCT_OUTPUTSET7_SETn14_Pos 14 /*!< SCT OUTPUTSET7: SETn14 Position */
+#define SCT_OUTPUTSET7_SETn14_Msk (0x01UL << SCT_OUTPUTSET7_SETn14_Pos) /*!< SCT OUTPUTSET7: SETn14 Mask */
+#define SCT_OUTPUTSET7_SETn15_Pos 15 /*!< SCT OUTPUTSET7: SETn15 Position */
+#define SCT_OUTPUTSET7_SETn15_Msk (0x01UL << SCT_OUTPUTSET7_SETn15_Pos) /*!< SCT OUTPUTSET7: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR7 -----------------------------------------
+#define SCT_OUTPUTCLR7_CLRn0_Pos 0 /*!< SCT OUTPUTCLR7: CLRn0 Position */
+#define SCT_OUTPUTCLR7_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos) /*!< SCT OUTPUTCLR7: CLRn0 Mask */
+#define SCT_OUTPUTCLR7_CLRn1_Pos 1 /*!< SCT OUTPUTCLR7: CLRn1 Position */
+#define SCT_OUTPUTCLR7_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos) /*!< SCT OUTPUTCLR7: CLRn1 Mask */
+#define SCT_OUTPUTCLR7_CLRn2_Pos 2 /*!< SCT OUTPUTCLR7: CLRn2 Position */
+#define SCT_OUTPUTCLR7_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos) /*!< SCT OUTPUTCLR7: CLRn2 Mask */
+#define SCT_OUTPUTCLR7_CLRn3_Pos 3 /*!< SCT OUTPUTCLR7: CLRn3 Position */
+#define SCT_OUTPUTCLR7_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos) /*!< SCT OUTPUTCLR7: CLRn3 Mask */
+#define SCT_OUTPUTCLR7_CLRn4_Pos 4 /*!< SCT OUTPUTCLR7: CLRn4 Position */
+#define SCT_OUTPUTCLR7_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos) /*!< SCT OUTPUTCLR7: CLRn4 Mask */
+#define SCT_OUTPUTCLR7_CLRn5_Pos 5 /*!< SCT OUTPUTCLR7: CLRn5 Position */
+#define SCT_OUTPUTCLR7_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos) /*!< SCT OUTPUTCLR7: CLRn5 Mask */
+#define SCT_OUTPUTCLR7_CLRn6_Pos 6 /*!< SCT OUTPUTCLR7: CLRn6 Position */
+#define SCT_OUTPUTCLR7_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos) /*!< SCT OUTPUTCLR7: CLRn6 Mask */
+#define SCT_OUTPUTCLR7_CLRn7_Pos 7 /*!< SCT OUTPUTCLR7: CLRn7 Position */
+#define SCT_OUTPUTCLR7_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos) /*!< SCT OUTPUTCLR7: CLRn7 Mask */
+#define SCT_OUTPUTCLR7_CLRn8_Pos 8 /*!< SCT OUTPUTCLR7: CLRn8 Position */
+#define SCT_OUTPUTCLR7_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos) /*!< SCT OUTPUTCLR7: CLRn8 Mask */
+#define SCT_OUTPUTCLR7_CLRn9_Pos 9 /*!< SCT OUTPUTCLR7: CLRn9 Position */
+#define SCT_OUTPUTCLR7_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos) /*!< SCT OUTPUTCLR7: CLRn9 Mask */
+#define SCT_OUTPUTCLR7_CLRn10_Pos 10 /*!< SCT OUTPUTCLR7: CLRn10 Position */
+#define SCT_OUTPUTCLR7_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos) /*!< SCT OUTPUTCLR7: CLRn10 Mask */
+#define SCT_OUTPUTCLR7_CLRn11_Pos 11 /*!< SCT OUTPUTCLR7: CLRn11 Position */
+#define SCT_OUTPUTCLR7_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos) /*!< SCT OUTPUTCLR7: CLRn11 Mask */
+#define SCT_OUTPUTCLR7_CLRn12_Pos 12 /*!< SCT OUTPUTCLR7: CLRn12 Position */
+#define SCT_OUTPUTCLR7_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos) /*!< SCT OUTPUTCLR7: CLRn12 Mask */
+#define SCT_OUTPUTCLR7_CLRn13_Pos 13 /*!< SCT OUTPUTCLR7: CLRn13 Position */
+#define SCT_OUTPUTCLR7_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos) /*!< SCT OUTPUTCLR7: CLRn13 Mask */
+#define SCT_OUTPUTCLR7_CLRn14_Pos 14 /*!< SCT OUTPUTCLR7: CLRn14 Position */
+#define SCT_OUTPUTCLR7_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos) /*!< SCT OUTPUTCLR7: CLRn14 Mask */
+#define SCT_OUTPUTCLR7_CLRn15_Pos 15 /*!< SCT OUTPUTCLR7: CLRn15 Position */
+#define SCT_OUTPUTCLR7_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos) /*!< SCT OUTPUTCLR7: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET8 -----------------------------------------
+#define SCT_OUTPUTSET8_SETn0_Pos 0 /*!< SCT OUTPUTSET8: SETn0 Position */
+#define SCT_OUTPUTSET8_SETn0_Msk (0x01UL << SCT_OUTPUTSET8_SETn0_Pos) /*!< SCT OUTPUTSET8: SETn0 Mask */
+#define SCT_OUTPUTSET8_SETn1_Pos 1 /*!< SCT OUTPUTSET8: SETn1 Position */
+#define SCT_OUTPUTSET8_SETn1_Msk (0x01UL << SCT_OUTPUTSET8_SETn1_Pos) /*!< SCT OUTPUTSET8: SETn1 Mask */
+#define SCT_OUTPUTSET8_SETn2_Pos 2 /*!< SCT OUTPUTSET8: SETn2 Position */
+#define SCT_OUTPUTSET8_SETn2_Msk (0x01UL << SCT_OUTPUTSET8_SETn2_Pos) /*!< SCT OUTPUTSET8: SETn2 Mask */
+#define SCT_OUTPUTSET8_SETn3_Pos 3 /*!< SCT OUTPUTSET8: SETn3 Position */
+#define SCT_OUTPUTSET8_SETn3_Msk (0x01UL << SCT_OUTPUTSET8_SETn3_Pos) /*!< SCT OUTPUTSET8: SETn3 Mask */
+#define SCT_OUTPUTSET8_SETn4_Pos 4 /*!< SCT OUTPUTSET8: SETn4 Position */
+#define SCT_OUTPUTSET8_SETn4_Msk (0x01UL << SCT_OUTPUTSET8_SETn4_Pos) /*!< SCT OUTPUTSET8: SETn4 Mask */
+#define SCT_OUTPUTSET8_SETn5_Pos 5 /*!< SCT OUTPUTSET8: SETn5 Position */
+#define SCT_OUTPUTSET8_SETn5_Msk (0x01UL << SCT_OUTPUTSET8_SETn5_Pos) /*!< SCT OUTPUTSET8: SETn5 Mask */
+#define SCT_OUTPUTSET8_SETn6_Pos 6 /*!< SCT OUTPUTSET8: SETn6 Position */
+#define SCT_OUTPUTSET8_SETn6_Msk (0x01UL << SCT_OUTPUTSET8_SETn6_Pos) /*!< SCT OUTPUTSET8: SETn6 Mask */
+#define SCT_OUTPUTSET8_SETn7_Pos 7 /*!< SCT OUTPUTSET8: SETn7 Position */
+#define SCT_OUTPUTSET8_SETn7_Msk (0x01UL << SCT_OUTPUTSET8_SETn7_Pos) /*!< SCT OUTPUTSET8: SETn7 Mask */
+#define SCT_OUTPUTSET8_SETn8_Pos 8 /*!< SCT OUTPUTSET8: SETn8 Position */
+#define SCT_OUTPUTSET8_SETn8_Msk (0x01UL << SCT_OUTPUTSET8_SETn8_Pos) /*!< SCT OUTPUTSET8: SETn8 Mask */
+#define SCT_OUTPUTSET8_SETn9_Pos 9 /*!< SCT OUTPUTSET8: SETn9 Position */
+#define SCT_OUTPUTSET8_SETn9_Msk (0x01UL << SCT_OUTPUTSET8_SETn9_Pos) /*!< SCT OUTPUTSET8: SETn9 Mask */
+#define SCT_OUTPUTSET8_SETn10_Pos 10 /*!< SCT OUTPUTSET8: SETn10 Position */
+#define SCT_OUTPUTSET8_SETn10_Msk (0x01UL << SCT_OUTPUTSET8_SETn10_Pos) /*!< SCT OUTPUTSET8: SETn10 Mask */
+#define SCT_OUTPUTSET8_SETn11_Pos 11 /*!< SCT OUTPUTSET8: SETn11 Position */
+#define SCT_OUTPUTSET8_SETn11_Msk (0x01UL << SCT_OUTPUTSET8_SETn11_Pos) /*!< SCT OUTPUTSET8: SETn11 Mask */
+#define SCT_OUTPUTSET8_SETn12_Pos 12 /*!< SCT OUTPUTSET8: SETn12 Position */
+#define SCT_OUTPUTSET8_SETn12_Msk (0x01UL << SCT_OUTPUTSET8_SETn12_Pos) /*!< SCT OUTPUTSET8: SETn12 Mask */
+#define SCT_OUTPUTSET8_SETn13_Pos 13 /*!< SCT OUTPUTSET8: SETn13 Position */
+#define SCT_OUTPUTSET8_SETn13_Msk (0x01UL << SCT_OUTPUTSET8_SETn13_Pos) /*!< SCT OUTPUTSET8: SETn13 Mask */
+#define SCT_OUTPUTSET8_SETn14_Pos 14 /*!< SCT OUTPUTSET8: SETn14 Position */
+#define SCT_OUTPUTSET8_SETn14_Msk (0x01UL << SCT_OUTPUTSET8_SETn14_Pos) /*!< SCT OUTPUTSET8: SETn14 Mask */
+#define SCT_OUTPUTSET8_SETn15_Pos 15 /*!< SCT OUTPUTSET8: SETn15 Position */
+#define SCT_OUTPUTSET8_SETn15_Msk (0x01UL << SCT_OUTPUTSET8_SETn15_Pos) /*!< SCT OUTPUTSET8: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR8 -----------------------------------------
+#define SCT_OUTPUTCLR8_CLRn0_Pos 0 /*!< SCT OUTPUTCLR8: CLRn0 Position */
+#define SCT_OUTPUTCLR8_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos) /*!< SCT OUTPUTCLR8: CLRn0 Mask */
+#define SCT_OUTPUTCLR8_CLRn1_Pos 1 /*!< SCT OUTPUTCLR8: CLRn1 Position */
+#define SCT_OUTPUTCLR8_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos) /*!< SCT OUTPUTCLR8: CLRn1 Mask */
+#define SCT_OUTPUTCLR8_CLRn2_Pos 2 /*!< SCT OUTPUTCLR8: CLRn2 Position */
+#define SCT_OUTPUTCLR8_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos) /*!< SCT OUTPUTCLR8: CLRn2 Mask */
+#define SCT_OUTPUTCLR8_CLRn3_Pos 3 /*!< SCT OUTPUTCLR8: CLRn3 Position */
+#define SCT_OUTPUTCLR8_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos) /*!< SCT OUTPUTCLR8: CLRn3 Mask */
+#define SCT_OUTPUTCLR8_CLRn4_Pos 4 /*!< SCT OUTPUTCLR8: CLRn4 Position */
+#define SCT_OUTPUTCLR8_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos) /*!< SCT OUTPUTCLR8: CLRn4 Mask */
+#define SCT_OUTPUTCLR8_CLRn5_Pos 5 /*!< SCT OUTPUTCLR8: CLRn5 Position */
+#define SCT_OUTPUTCLR8_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos) /*!< SCT OUTPUTCLR8: CLRn5 Mask */
+#define SCT_OUTPUTCLR8_CLRn6_Pos 6 /*!< SCT OUTPUTCLR8: CLRn6 Position */
+#define SCT_OUTPUTCLR8_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos) /*!< SCT OUTPUTCLR8: CLRn6 Mask */
+#define SCT_OUTPUTCLR8_CLRn7_Pos 7 /*!< SCT OUTPUTCLR8: CLRn7 Position */
+#define SCT_OUTPUTCLR8_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos) /*!< SCT OUTPUTCLR8: CLRn7 Mask */
+#define SCT_OUTPUTCLR8_CLRn8_Pos 8 /*!< SCT OUTPUTCLR8: CLRn8 Position */
+#define SCT_OUTPUTCLR8_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos) /*!< SCT OUTPUTCLR8: CLRn8 Mask */
+#define SCT_OUTPUTCLR8_CLRn9_Pos 9 /*!< SCT OUTPUTCLR8: CLRn9 Position */
+#define SCT_OUTPUTCLR8_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos) /*!< SCT OUTPUTCLR8: CLRn9 Mask */
+#define SCT_OUTPUTCLR8_CLRn10_Pos 10 /*!< SCT OUTPUTCLR8: CLRn10 Position */
+#define SCT_OUTPUTCLR8_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos) /*!< SCT OUTPUTCLR8: CLRn10 Mask */
+#define SCT_OUTPUTCLR8_CLRn11_Pos 11 /*!< SCT OUTPUTCLR8: CLRn11 Position */
+#define SCT_OUTPUTCLR8_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos) /*!< SCT OUTPUTCLR8: CLRn11 Mask */
+#define SCT_OUTPUTCLR8_CLRn12_Pos 12 /*!< SCT OUTPUTCLR8: CLRn12 Position */
+#define SCT_OUTPUTCLR8_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos) /*!< SCT OUTPUTCLR8: CLRn12 Mask */
+#define SCT_OUTPUTCLR8_CLRn13_Pos 13 /*!< SCT OUTPUTCLR8: CLRn13 Position */
+#define SCT_OUTPUTCLR8_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos) /*!< SCT OUTPUTCLR8: CLRn13 Mask */
+#define SCT_OUTPUTCLR8_CLRn14_Pos 14 /*!< SCT OUTPUTCLR8: CLRn14 Position */
+#define SCT_OUTPUTCLR8_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos) /*!< SCT OUTPUTCLR8: CLRn14 Mask */
+#define SCT_OUTPUTCLR8_CLRn15_Pos 15 /*!< SCT OUTPUTCLR8: CLRn15 Position */
+#define SCT_OUTPUTCLR8_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos) /*!< SCT OUTPUTCLR8: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET9 -----------------------------------------
+#define SCT_OUTPUTSET9_SETn0_Pos 0 /*!< SCT OUTPUTSET9: SETn0 Position */
+#define SCT_OUTPUTSET9_SETn0_Msk (0x01UL << SCT_OUTPUTSET9_SETn0_Pos) /*!< SCT OUTPUTSET9: SETn0 Mask */
+#define SCT_OUTPUTSET9_SETn1_Pos 1 /*!< SCT OUTPUTSET9: SETn1 Position */
+#define SCT_OUTPUTSET9_SETn1_Msk (0x01UL << SCT_OUTPUTSET9_SETn1_Pos) /*!< SCT OUTPUTSET9: SETn1 Mask */
+#define SCT_OUTPUTSET9_SETn2_Pos 2 /*!< SCT OUTPUTSET9: SETn2 Position */
+#define SCT_OUTPUTSET9_SETn2_Msk (0x01UL << SCT_OUTPUTSET9_SETn2_Pos) /*!< SCT OUTPUTSET9: SETn2 Mask */
+#define SCT_OUTPUTSET9_SETn3_Pos 3 /*!< SCT OUTPUTSET9: SETn3 Position */
+#define SCT_OUTPUTSET9_SETn3_Msk (0x01UL << SCT_OUTPUTSET9_SETn3_Pos) /*!< SCT OUTPUTSET9: SETn3 Mask */
+#define SCT_OUTPUTSET9_SETn4_Pos 4 /*!< SCT OUTPUTSET9: SETn4 Position */
+#define SCT_OUTPUTSET9_SETn4_Msk (0x01UL << SCT_OUTPUTSET9_SETn4_Pos) /*!< SCT OUTPUTSET9: SETn4 Mask */
+#define SCT_OUTPUTSET9_SETn5_Pos 5 /*!< SCT OUTPUTSET9: SETn5 Position */
+#define SCT_OUTPUTSET9_SETn5_Msk (0x01UL << SCT_OUTPUTSET9_SETn5_Pos) /*!< SCT OUTPUTSET9: SETn5 Mask */
+#define SCT_OUTPUTSET9_SETn6_Pos 6 /*!< SCT OUTPUTSET9: SETn6 Position */
+#define SCT_OUTPUTSET9_SETn6_Msk (0x01UL << SCT_OUTPUTSET9_SETn6_Pos) /*!< SCT OUTPUTSET9: SETn6 Mask */
+#define SCT_OUTPUTSET9_SETn7_Pos 7 /*!< SCT OUTPUTSET9: SETn7 Position */
+#define SCT_OUTPUTSET9_SETn7_Msk (0x01UL << SCT_OUTPUTSET9_SETn7_Pos) /*!< SCT OUTPUTSET9: SETn7 Mask */
+#define SCT_OUTPUTSET9_SETn8_Pos 8 /*!< SCT OUTPUTSET9: SETn8 Position */
+#define SCT_OUTPUTSET9_SETn8_Msk (0x01UL << SCT_OUTPUTSET9_SETn8_Pos) /*!< SCT OUTPUTSET9: SETn8 Mask */
+#define SCT_OUTPUTSET9_SETn9_Pos 9 /*!< SCT OUTPUTSET9: SETn9 Position */
+#define SCT_OUTPUTSET9_SETn9_Msk (0x01UL << SCT_OUTPUTSET9_SETn9_Pos) /*!< SCT OUTPUTSET9: SETn9 Mask */
+#define SCT_OUTPUTSET9_SETn10_Pos 10 /*!< SCT OUTPUTSET9: SETn10 Position */
+#define SCT_OUTPUTSET9_SETn10_Msk (0x01UL << SCT_OUTPUTSET9_SETn10_Pos) /*!< SCT OUTPUTSET9: SETn10 Mask */
+#define SCT_OUTPUTSET9_SETn11_Pos 11 /*!< SCT OUTPUTSET9: SETn11 Position */
+#define SCT_OUTPUTSET9_SETn11_Msk (0x01UL << SCT_OUTPUTSET9_SETn11_Pos) /*!< SCT OUTPUTSET9: SETn11 Mask */
+#define SCT_OUTPUTSET9_SETn12_Pos 12 /*!< SCT OUTPUTSET9: SETn12 Position */
+#define SCT_OUTPUTSET9_SETn12_Msk (0x01UL << SCT_OUTPUTSET9_SETn12_Pos) /*!< SCT OUTPUTSET9: SETn12 Mask */
+#define SCT_OUTPUTSET9_SETn13_Pos 13 /*!< SCT OUTPUTSET9: SETn13 Position */
+#define SCT_OUTPUTSET9_SETn13_Msk (0x01UL << SCT_OUTPUTSET9_SETn13_Pos) /*!< SCT OUTPUTSET9: SETn13 Mask */
+#define SCT_OUTPUTSET9_SETn14_Pos 14 /*!< SCT OUTPUTSET9: SETn14 Position */
+#define SCT_OUTPUTSET9_SETn14_Msk (0x01UL << SCT_OUTPUTSET9_SETn14_Pos) /*!< SCT OUTPUTSET9: SETn14 Mask */
+#define SCT_OUTPUTSET9_SETn15_Pos 15 /*!< SCT OUTPUTSET9: SETn15 Position */
+#define SCT_OUTPUTSET9_SETn15_Msk (0x01UL << SCT_OUTPUTSET9_SETn15_Pos) /*!< SCT OUTPUTSET9: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR9 -----------------------------------------
+#define SCT_OUTPUTCLR9_CLRn0_Pos 0 /*!< SCT OUTPUTCLR9: CLRn0 Position */
+#define SCT_OUTPUTCLR9_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos) /*!< SCT OUTPUTCLR9: CLRn0 Mask */
+#define SCT_OUTPUTCLR9_CLRn1_Pos 1 /*!< SCT OUTPUTCLR9: CLRn1 Position */
+#define SCT_OUTPUTCLR9_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos) /*!< SCT OUTPUTCLR9: CLRn1 Mask */
+#define SCT_OUTPUTCLR9_CLRn2_Pos 2 /*!< SCT OUTPUTCLR9: CLRn2 Position */
+#define SCT_OUTPUTCLR9_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos) /*!< SCT OUTPUTCLR9: CLRn2 Mask */
+#define SCT_OUTPUTCLR9_CLRn3_Pos 3 /*!< SCT OUTPUTCLR9: CLRn3 Position */
+#define SCT_OUTPUTCLR9_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos) /*!< SCT OUTPUTCLR9: CLRn3 Mask */
+#define SCT_OUTPUTCLR9_CLRn4_Pos 4 /*!< SCT OUTPUTCLR9: CLRn4 Position */
+#define SCT_OUTPUTCLR9_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos) /*!< SCT OUTPUTCLR9: CLRn4 Mask */
+#define SCT_OUTPUTCLR9_CLRn5_Pos 5 /*!< SCT OUTPUTCLR9: CLRn5 Position */
+#define SCT_OUTPUTCLR9_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos) /*!< SCT OUTPUTCLR9: CLRn5 Mask */
+#define SCT_OUTPUTCLR9_CLRn6_Pos 6 /*!< SCT OUTPUTCLR9: CLRn6 Position */
+#define SCT_OUTPUTCLR9_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos) /*!< SCT OUTPUTCLR9: CLRn6 Mask */
+#define SCT_OUTPUTCLR9_CLRn7_Pos 7 /*!< SCT OUTPUTCLR9: CLRn7 Position */
+#define SCT_OUTPUTCLR9_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos) /*!< SCT OUTPUTCLR9: CLRn7 Mask */
+#define SCT_OUTPUTCLR9_CLRn8_Pos 8 /*!< SCT OUTPUTCLR9: CLRn8 Position */
+#define SCT_OUTPUTCLR9_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos) /*!< SCT OUTPUTCLR9: CLRn8 Mask */
+#define SCT_OUTPUTCLR9_CLRn9_Pos 9 /*!< SCT OUTPUTCLR9: CLRn9 Position */
+#define SCT_OUTPUTCLR9_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos) /*!< SCT OUTPUTCLR9: CLRn9 Mask */
+#define SCT_OUTPUTCLR9_CLRn10_Pos 10 /*!< SCT OUTPUTCLR9: CLRn10 Position */
+#define SCT_OUTPUTCLR9_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos) /*!< SCT OUTPUTCLR9: CLRn10 Mask */
+#define SCT_OUTPUTCLR9_CLRn11_Pos 11 /*!< SCT OUTPUTCLR9: CLRn11 Position */
+#define SCT_OUTPUTCLR9_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos) /*!< SCT OUTPUTCLR9: CLRn11 Mask */
+#define SCT_OUTPUTCLR9_CLRn12_Pos 12 /*!< SCT OUTPUTCLR9: CLRn12 Position */
+#define SCT_OUTPUTCLR9_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos) /*!< SCT OUTPUTCLR9: CLRn12 Mask */
+#define SCT_OUTPUTCLR9_CLRn13_Pos 13 /*!< SCT OUTPUTCLR9: CLRn13 Position */
+#define SCT_OUTPUTCLR9_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos) /*!< SCT OUTPUTCLR9: CLRn13 Mask */
+#define SCT_OUTPUTCLR9_CLRn14_Pos 14 /*!< SCT OUTPUTCLR9: CLRn14 Position */
+#define SCT_OUTPUTCLR9_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos) /*!< SCT OUTPUTCLR9: CLRn14 Mask */
+#define SCT_OUTPUTCLR9_CLRn15_Pos 15 /*!< SCT OUTPUTCLR9: CLRn15 Position */
+#define SCT_OUTPUTCLR9_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos) /*!< SCT OUTPUTCLR9: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET10 ----------------------------------------
+#define SCT_OUTPUTSET10_SETn0_Pos 0 /*!< SCT OUTPUTSET10: SETn0 Position */
+#define SCT_OUTPUTSET10_SETn0_Msk (0x01UL << SCT_OUTPUTSET10_SETn0_Pos) /*!< SCT OUTPUTSET10: SETn0 Mask */
+#define SCT_OUTPUTSET10_SETn1_Pos 1 /*!< SCT OUTPUTSET10: SETn1 Position */
+#define SCT_OUTPUTSET10_SETn1_Msk (0x01UL << SCT_OUTPUTSET10_SETn1_Pos) /*!< SCT OUTPUTSET10: SETn1 Mask */
+#define SCT_OUTPUTSET10_SETn2_Pos 2 /*!< SCT OUTPUTSET10: SETn2 Position */
+#define SCT_OUTPUTSET10_SETn2_Msk (0x01UL << SCT_OUTPUTSET10_SETn2_Pos) /*!< SCT OUTPUTSET10: SETn2 Mask */
+#define SCT_OUTPUTSET10_SETn3_Pos 3 /*!< SCT OUTPUTSET10: SETn3 Position */
+#define SCT_OUTPUTSET10_SETn3_Msk (0x01UL << SCT_OUTPUTSET10_SETn3_Pos) /*!< SCT OUTPUTSET10: SETn3 Mask */
+#define SCT_OUTPUTSET10_SETn4_Pos 4 /*!< SCT OUTPUTSET10: SETn4 Position */
+#define SCT_OUTPUTSET10_SETn4_Msk (0x01UL << SCT_OUTPUTSET10_SETn4_Pos) /*!< SCT OUTPUTSET10: SETn4 Mask */
+#define SCT_OUTPUTSET10_SETn5_Pos 5 /*!< SCT OUTPUTSET10: SETn5 Position */
+#define SCT_OUTPUTSET10_SETn5_Msk (0x01UL << SCT_OUTPUTSET10_SETn5_Pos) /*!< SCT OUTPUTSET10: SETn5 Mask */
+#define SCT_OUTPUTSET10_SETn6_Pos 6 /*!< SCT OUTPUTSET10: SETn6 Position */
+#define SCT_OUTPUTSET10_SETn6_Msk (0x01UL << SCT_OUTPUTSET10_SETn6_Pos) /*!< SCT OUTPUTSET10: SETn6 Mask */
+#define SCT_OUTPUTSET10_SETn7_Pos 7 /*!< SCT OUTPUTSET10: SETn7 Position */
+#define SCT_OUTPUTSET10_SETn7_Msk (0x01UL << SCT_OUTPUTSET10_SETn7_Pos) /*!< SCT OUTPUTSET10: SETn7 Mask */
+#define SCT_OUTPUTSET10_SETn8_Pos 8 /*!< SCT OUTPUTSET10: SETn8 Position */
+#define SCT_OUTPUTSET10_SETn8_Msk (0x01UL << SCT_OUTPUTSET10_SETn8_Pos) /*!< SCT OUTPUTSET10: SETn8 Mask */
+#define SCT_OUTPUTSET10_SETn9_Pos 9 /*!< SCT OUTPUTSET10: SETn9 Position */
+#define SCT_OUTPUTSET10_SETn9_Msk (0x01UL << SCT_OUTPUTSET10_SETn9_Pos) /*!< SCT OUTPUTSET10: SETn9 Mask */
+#define SCT_OUTPUTSET10_SETn10_Pos 10 /*!< SCT OUTPUTSET10: SETn10 Position */
+#define SCT_OUTPUTSET10_SETn10_Msk (0x01UL << SCT_OUTPUTSET10_SETn10_Pos) /*!< SCT OUTPUTSET10: SETn10 Mask */
+#define SCT_OUTPUTSET10_SETn11_Pos 11 /*!< SCT OUTPUTSET10: SETn11 Position */
+#define SCT_OUTPUTSET10_SETn11_Msk (0x01UL << SCT_OUTPUTSET10_SETn11_Pos) /*!< SCT OUTPUTSET10: SETn11 Mask */
+#define SCT_OUTPUTSET10_SETn12_Pos 12 /*!< SCT OUTPUTSET10: SETn12 Position */
+#define SCT_OUTPUTSET10_SETn12_Msk (0x01UL << SCT_OUTPUTSET10_SETn12_Pos) /*!< SCT OUTPUTSET10: SETn12 Mask */
+#define SCT_OUTPUTSET10_SETn13_Pos 13 /*!< SCT OUTPUTSET10: SETn13 Position */
+#define SCT_OUTPUTSET10_SETn13_Msk (0x01UL << SCT_OUTPUTSET10_SETn13_Pos) /*!< SCT OUTPUTSET10: SETn13 Mask */
+#define SCT_OUTPUTSET10_SETn14_Pos 14 /*!< SCT OUTPUTSET10: SETn14 Position */
+#define SCT_OUTPUTSET10_SETn14_Msk (0x01UL << SCT_OUTPUTSET10_SETn14_Pos) /*!< SCT OUTPUTSET10: SETn14 Mask */
+#define SCT_OUTPUTSET10_SETn15_Pos 15 /*!< SCT OUTPUTSET10: SETn15 Position */
+#define SCT_OUTPUTSET10_SETn15_Msk (0x01UL << SCT_OUTPUTSET10_SETn15_Pos) /*!< SCT OUTPUTSET10: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR10 ----------------------------------------
+#define SCT_OUTPUTCLR10_CLRn0_Pos 0 /*!< SCT OUTPUTCLR10: CLRn0 Position */
+#define SCT_OUTPUTCLR10_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos) /*!< SCT OUTPUTCLR10: CLRn0 Mask */
+#define SCT_OUTPUTCLR10_CLRn1_Pos 1 /*!< SCT OUTPUTCLR10: CLRn1 Position */
+#define SCT_OUTPUTCLR10_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos) /*!< SCT OUTPUTCLR10: CLRn1 Mask */
+#define SCT_OUTPUTCLR10_CLRn2_Pos 2 /*!< SCT OUTPUTCLR10: CLRn2 Position */
+#define SCT_OUTPUTCLR10_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos) /*!< SCT OUTPUTCLR10: CLRn2 Mask */
+#define SCT_OUTPUTCLR10_CLRn3_Pos 3 /*!< SCT OUTPUTCLR10: CLRn3 Position */
+#define SCT_OUTPUTCLR10_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos) /*!< SCT OUTPUTCLR10: CLRn3 Mask */
+#define SCT_OUTPUTCLR10_CLRn4_Pos 4 /*!< SCT OUTPUTCLR10: CLRn4 Position */
+#define SCT_OUTPUTCLR10_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos) /*!< SCT OUTPUTCLR10: CLRn4 Mask */
+#define SCT_OUTPUTCLR10_CLRn5_Pos 5 /*!< SCT OUTPUTCLR10: CLRn5 Position */
+#define SCT_OUTPUTCLR10_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos) /*!< SCT OUTPUTCLR10: CLRn5 Mask */
+#define SCT_OUTPUTCLR10_CLRn6_Pos 6 /*!< SCT OUTPUTCLR10: CLRn6 Position */
+#define SCT_OUTPUTCLR10_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos) /*!< SCT OUTPUTCLR10: CLRn6 Mask */
+#define SCT_OUTPUTCLR10_CLRn7_Pos 7 /*!< SCT OUTPUTCLR10: CLRn7 Position */
+#define SCT_OUTPUTCLR10_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos) /*!< SCT OUTPUTCLR10: CLRn7 Mask */
+#define SCT_OUTPUTCLR10_CLRn8_Pos 8 /*!< SCT OUTPUTCLR10: CLRn8 Position */
+#define SCT_OUTPUTCLR10_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos) /*!< SCT OUTPUTCLR10: CLRn8 Mask */
+#define SCT_OUTPUTCLR10_CLRn9_Pos 9 /*!< SCT OUTPUTCLR10: CLRn9 Position */
+#define SCT_OUTPUTCLR10_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos) /*!< SCT OUTPUTCLR10: CLRn9 Mask */
+#define SCT_OUTPUTCLR10_CLRn10_Pos 10 /*!< SCT OUTPUTCLR10: CLRn10 Position */
+#define SCT_OUTPUTCLR10_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos) /*!< SCT OUTPUTCLR10: CLRn10 Mask */
+#define SCT_OUTPUTCLR10_CLRn11_Pos 11 /*!< SCT OUTPUTCLR10: CLRn11 Position */
+#define SCT_OUTPUTCLR10_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos) /*!< SCT OUTPUTCLR10: CLRn11 Mask */
+#define SCT_OUTPUTCLR10_CLRn12_Pos 12 /*!< SCT OUTPUTCLR10: CLRn12 Position */
+#define SCT_OUTPUTCLR10_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos) /*!< SCT OUTPUTCLR10: CLRn12 Mask */
+#define SCT_OUTPUTCLR10_CLRn13_Pos 13 /*!< SCT OUTPUTCLR10: CLRn13 Position */
+#define SCT_OUTPUTCLR10_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos) /*!< SCT OUTPUTCLR10: CLRn13 Mask */
+#define SCT_OUTPUTCLR10_CLRn14_Pos 14 /*!< SCT OUTPUTCLR10: CLRn14 Position */
+#define SCT_OUTPUTCLR10_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos) /*!< SCT OUTPUTCLR10: CLRn14 Mask */
+#define SCT_OUTPUTCLR10_CLRn15_Pos 15 /*!< SCT OUTPUTCLR10: CLRn15 Position */
+#define SCT_OUTPUTCLR10_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos) /*!< SCT OUTPUTCLR10: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET11 ----------------------------------------
+#define SCT_OUTPUTSET11_SETn0_Pos 0 /*!< SCT OUTPUTSET11: SETn0 Position */
+#define SCT_OUTPUTSET11_SETn0_Msk (0x01UL << SCT_OUTPUTSET11_SETn0_Pos) /*!< SCT OUTPUTSET11: SETn0 Mask */
+#define SCT_OUTPUTSET11_SETn1_Pos 1 /*!< SCT OUTPUTSET11: SETn1 Position */
+#define SCT_OUTPUTSET11_SETn1_Msk (0x01UL << SCT_OUTPUTSET11_SETn1_Pos) /*!< SCT OUTPUTSET11: SETn1 Mask */
+#define SCT_OUTPUTSET11_SETn2_Pos 2 /*!< SCT OUTPUTSET11: SETn2 Position */
+#define SCT_OUTPUTSET11_SETn2_Msk (0x01UL << SCT_OUTPUTSET11_SETn2_Pos) /*!< SCT OUTPUTSET11: SETn2 Mask */
+#define SCT_OUTPUTSET11_SETn3_Pos 3 /*!< SCT OUTPUTSET11: SETn3 Position */
+#define SCT_OUTPUTSET11_SETn3_Msk (0x01UL << SCT_OUTPUTSET11_SETn3_Pos) /*!< SCT OUTPUTSET11: SETn3 Mask */
+#define SCT_OUTPUTSET11_SETn4_Pos 4 /*!< SCT OUTPUTSET11: SETn4 Position */
+#define SCT_OUTPUTSET11_SETn4_Msk (0x01UL << SCT_OUTPUTSET11_SETn4_Pos) /*!< SCT OUTPUTSET11: SETn4 Mask */
+#define SCT_OUTPUTSET11_SETn5_Pos 5 /*!< SCT OUTPUTSET11: SETn5 Position */
+#define SCT_OUTPUTSET11_SETn5_Msk (0x01UL << SCT_OUTPUTSET11_SETn5_Pos) /*!< SCT OUTPUTSET11: SETn5 Mask */
+#define SCT_OUTPUTSET11_SETn6_Pos 6 /*!< SCT OUTPUTSET11: SETn6 Position */
+#define SCT_OUTPUTSET11_SETn6_Msk (0x01UL << SCT_OUTPUTSET11_SETn6_Pos) /*!< SCT OUTPUTSET11: SETn6 Mask */
+#define SCT_OUTPUTSET11_SETn7_Pos 7 /*!< SCT OUTPUTSET11: SETn7 Position */
+#define SCT_OUTPUTSET11_SETn7_Msk (0x01UL << SCT_OUTPUTSET11_SETn7_Pos) /*!< SCT OUTPUTSET11: SETn7 Mask */
+#define SCT_OUTPUTSET11_SETn8_Pos 8 /*!< SCT OUTPUTSET11: SETn8 Position */
+#define SCT_OUTPUTSET11_SETn8_Msk (0x01UL << SCT_OUTPUTSET11_SETn8_Pos) /*!< SCT OUTPUTSET11: SETn8 Mask */
+#define SCT_OUTPUTSET11_SETn9_Pos 9 /*!< SCT OUTPUTSET11: SETn9 Position */
+#define SCT_OUTPUTSET11_SETn9_Msk (0x01UL << SCT_OUTPUTSET11_SETn9_Pos) /*!< SCT OUTPUTSET11: SETn9 Mask */
+#define SCT_OUTPUTSET11_SETn10_Pos 10 /*!< SCT OUTPUTSET11: SETn10 Position */
+#define SCT_OUTPUTSET11_SETn10_Msk (0x01UL << SCT_OUTPUTSET11_SETn10_Pos) /*!< SCT OUTPUTSET11: SETn10 Mask */
+#define SCT_OUTPUTSET11_SETn11_Pos 11 /*!< SCT OUTPUTSET11: SETn11 Position */
+#define SCT_OUTPUTSET11_SETn11_Msk (0x01UL << SCT_OUTPUTSET11_SETn11_Pos) /*!< SCT OUTPUTSET11: SETn11 Mask */
+#define SCT_OUTPUTSET11_SETn12_Pos 12 /*!< SCT OUTPUTSET11: SETn12 Position */
+#define SCT_OUTPUTSET11_SETn12_Msk (0x01UL << SCT_OUTPUTSET11_SETn12_Pos) /*!< SCT OUTPUTSET11: SETn12 Mask */
+#define SCT_OUTPUTSET11_SETn13_Pos 13 /*!< SCT OUTPUTSET11: SETn13 Position */
+#define SCT_OUTPUTSET11_SETn13_Msk (0x01UL << SCT_OUTPUTSET11_SETn13_Pos) /*!< SCT OUTPUTSET11: SETn13 Mask */
+#define SCT_OUTPUTSET11_SETn14_Pos 14 /*!< SCT OUTPUTSET11: SETn14 Position */
+#define SCT_OUTPUTSET11_SETn14_Msk (0x01UL << SCT_OUTPUTSET11_SETn14_Pos) /*!< SCT OUTPUTSET11: SETn14 Mask */
+#define SCT_OUTPUTSET11_SETn15_Pos 15 /*!< SCT OUTPUTSET11: SETn15 Position */
+#define SCT_OUTPUTSET11_SETn15_Msk (0x01UL << SCT_OUTPUTSET11_SETn15_Pos) /*!< SCT OUTPUTSET11: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR11 ----------------------------------------
+#define SCT_OUTPUTCLR11_CLRn0_Pos 0 /*!< SCT OUTPUTCLR11: CLRn0 Position */
+#define SCT_OUTPUTCLR11_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos) /*!< SCT OUTPUTCLR11: CLRn0 Mask */
+#define SCT_OUTPUTCLR11_CLRn1_Pos 1 /*!< SCT OUTPUTCLR11: CLRn1 Position */
+#define SCT_OUTPUTCLR11_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos) /*!< SCT OUTPUTCLR11: CLRn1 Mask */
+#define SCT_OUTPUTCLR11_CLRn2_Pos 2 /*!< SCT OUTPUTCLR11: CLRn2 Position */
+#define SCT_OUTPUTCLR11_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos) /*!< SCT OUTPUTCLR11: CLRn2 Mask */
+#define SCT_OUTPUTCLR11_CLRn3_Pos 3 /*!< SCT OUTPUTCLR11: CLRn3 Position */
+#define SCT_OUTPUTCLR11_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos) /*!< SCT OUTPUTCLR11: CLRn3 Mask */
+#define SCT_OUTPUTCLR11_CLRn4_Pos 4 /*!< SCT OUTPUTCLR11: CLRn4 Position */
+#define SCT_OUTPUTCLR11_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos) /*!< SCT OUTPUTCLR11: CLRn4 Mask */
+#define SCT_OUTPUTCLR11_CLRn5_Pos 5 /*!< SCT OUTPUTCLR11: CLRn5 Position */
+#define SCT_OUTPUTCLR11_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos) /*!< SCT OUTPUTCLR11: CLRn5 Mask */
+#define SCT_OUTPUTCLR11_CLRn6_Pos 6 /*!< SCT OUTPUTCLR11: CLRn6 Position */
+#define SCT_OUTPUTCLR11_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos) /*!< SCT OUTPUTCLR11: CLRn6 Mask */
+#define SCT_OUTPUTCLR11_CLRn7_Pos 7 /*!< SCT OUTPUTCLR11: CLRn7 Position */
+#define SCT_OUTPUTCLR11_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos) /*!< SCT OUTPUTCLR11: CLRn7 Mask */
+#define SCT_OUTPUTCLR11_CLRn8_Pos 8 /*!< SCT OUTPUTCLR11: CLRn8 Position */
+#define SCT_OUTPUTCLR11_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos) /*!< SCT OUTPUTCLR11: CLRn8 Mask */
+#define SCT_OUTPUTCLR11_CLRn9_Pos 9 /*!< SCT OUTPUTCLR11: CLRn9 Position */
+#define SCT_OUTPUTCLR11_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos) /*!< SCT OUTPUTCLR11: CLRn9 Mask */
+#define SCT_OUTPUTCLR11_CLRn10_Pos 10 /*!< SCT OUTPUTCLR11: CLRn10 Position */
+#define SCT_OUTPUTCLR11_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos) /*!< SCT OUTPUTCLR11: CLRn10 Mask */
+#define SCT_OUTPUTCLR11_CLRn11_Pos 11 /*!< SCT OUTPUTCLR11: CLRn11 Position */
+#define SCT_OUTPUTCLR11_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos) /*!< SCT OUTPUTCLR11: CLRn11 Mask */
+#define SCT_OUTPUTCLR11_CLRn12_Pos 12 /*!< SCT OUTPUTCLR11: CLRn12 Position */
+#define SCT_OUTPUTCLR11_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos) /*!< SCT OUTPUTCLR11: CLRn12 Mask */
+#define SCT_OUTPUTCLR11_CLRn13_Pos 13 /*!< SCT OUTPUTCLR11: CLRn13 Position */
+#define SCT_OUTPUTCLR11_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos) /*!< SCT OUTPUTCLR11: CLRn13 Mask */
+#define SCT_OUTPUTCLR11_CLRn14_Pos 14 /*!< SCT OUTPUTCLR11: CLRn14 Position */
+#define SCT_OUTPUTCLR11_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos) /*!< SCT OUTPUTCLR11: CLRn14 Mask */
+#define SCT_OUTPUTCLR11_CLRn15_Pos 15 /*!< SCT OUTPUTCLR11: CLRn15 Position */
+#define SCT_OUTPUTCLR11_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos) /*!< SCT OUTPUTCLR11: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET12 ----------------------------------------
+#define SCT_OUTPUTSET12_SETn0_Pos 0 /*!< SCT OUTPUTSET12: SETn0 Position */
+#define SCT_OUTPUTSET12_SETn0_Msk (0x01UL << SCT_OUTPUTSET12_SETn0_Pos) /*!< SCT OUTPUTSET12: SETn0 Mask */
+#define SCT_OUTPUTSET12_SETn1_Pos 1 /*!< SCT OUTPUTSET12: SETn1 Position */
+#define SCT_OUTPUTSET12_SETn1_Msk (0x01UL << SCT_OUTPUTSET12_SETn1_Pos) /*!< SCT OUTPUTSET12: SETn1 Mask */
+#define SCT_OUTPUTSET12_SETn2_Pos 2 /*!< SCT OUTPUTSET12: SETn2 Position */
+#define SCT_OUTPUTSET12_SETn2_Msk (0x01UL << SCT_OUTPUTSET12_SETn2_Pos) /*!< SCT OUTPUTSET12: SETn2 Mask */
+#define SCT_OUTPUTSET12_SETn3_Pos 3 /*!< SCT OUTPUTSET12: SETn3 Position */
+#define SCT_OUTPUTSET12_SETn3_Msk (0x01UL << SCT_OUTPUTSET12_SETn3_Pos) /*!< SCT OUTPUTSET12: SETn3 Mask */
+#define SCT_OUTPUTSET12_SETn4_Pos 4 /*!< SCT OUTPUTSET12: SETn4 Position */
+#define SCT_OUTPUTSET12_SETn4_Msk (0x01UL << SCT_OUTPUTSET12_SETn4_Pos) /*!< SCT OUTPUTSET12: SETn4 Mask */
+#define SCT_OUTPUTSET12_SETn5_Pos 5 /*!< SCT OUTPUTSET12: SETn5 Position */
+#define SCT_OUTPUTSET12_SETn5_Msk (0x01UL << SCT_OUTPUTSET12_SETn5_Pos) /*!< SCT OUTPUTSET12: SETn5 Mask */
+#define SCT_OUTPUTSET12_SETn6_Pos 6 /*!< SCT OUTPUTSET12: SETn6 Position */
+#define SCT_OUTPUTSET12_SETn6_Msk (0x01UL << SCT_OUTPUTSET12_SETn6_Pos) /*!< SCT OUTPUTSET12: SETn6 Mask */
+#define SCT_OUTPUTSET12_SETn7_Pos 7 /*!< SCT OUTPUTSET12: SETn7 Position */
+#define SCT_OUTPUTSET12_SETn7_Msk (0x01UL << SCT_OUTPUTSET12_SETn7_Pos) /*!< SCT OUTPUTSET12: SETn7 Mask */
+#define SCT_OUTPUTSET12_SETn8_Pos 8 /*!< SCT OUTPUTSET12: SETn8 Position */
+#define SCT_OUTPUTSET12_SETn8_Msk (0x01UL << SCT_OUTPUTSET12_SETn8_Pos) /*!< SCT OUTPUTSET12: SETn8 Mask */
+#define SCT_OUTPUTSET12_SETn9_Pos 9 /*!< SCT OUTPUTSET12: SETn9 Position */
+#define SCT_OUTPUTSET12_SETn9_Msk (0x01UL << SCT_OUTPUTSET12_SETn9_Pos) /*!< SCT OUTPUTSET12: SETn9 Mask */
+#define SCT_OUTPUTSET12_SETn10_Pos 10 /*!< SCT OUTPUTSET12: SETn10 Position */
+#define SCT_OUTPUTSET12_SETn10_Msk (0x01UL << SCT_OUTPUTSET12_SETn10_Pos) /*!< SCT OUTPUTSET12: SETn10 Mask */
+#define SCT_OUTPUTSET12_SETn11_Pos 11 /*!< SCT OUTPUTSET12: SETn11 Position */
+#define SCT_OUTPUTSET12_SETn11_Msk (0x01UL << SCT_OUTPUTSET12_SETn11_Pos) /*!< SCT OUTPUTSET12: SETn11 Mask */
+#define SCT_OUTPUTSET12_SETn12_Pos 12 /*!< SCT OUTPUTSET12: SETn12 Position */
+#define SCT_OUTPUTSET12_SETn12_Msk (0x01UL << SCT_OUTPUTSET12_SETn12_Pos) /*!< SCT OUTPUTSET12: SETn12 Mask */
+#define SCT_OUTPUTSET12_SETn13_Pos 13 /*!< SCT OUTPUTSET12: SETn13 Position */
+#define SCT_OUTPUTSET12_SETn13_Msk (0x01UL << SCT_OUTPUTSET12_SETn13_Pos) /*!< SCT OUTPUTSET12: SETn13 Mask */
+#define SCT_OUTPUTSET12_SETn14_Pos 14 /*!< SCT OUTPUTSET12: SETn14 Position */
+#define SCT_OUTPUTSET12_SETn14_Msk (0x01UL << SCT_OUTPUTSET12_SETn14_Pos) /*!< SCT OUTPUTSET12: SETn14 Mask */
+#define SCT_OUTPUTSET12_SETn15_Pos 15 /*!< SCT OUTPUTSET12: SETn15 Position */
+#define SCT_OUTPUTSET12_SETn15_Msk (0x01UL << SCT_OUTPUTSET12_SETn15_Pos) /*!< SCT OUTPUTSET12: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR12 ----------------------------------------
+#define SCT_OUTPUTCLR12_CLRn0_Pos 0 /*!< SCT OUTPUTCLR12: CLRn0 Position */
+#define SCT_OUTPUTCLR12_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos) /*!< SCT OUTPUTCLR12: CLRn0 Mask */
+#define SCT_OUTPUTCLR12_CLRn1_Pos 1 /*!< SCT OUTPUTCLR12: CLRn1 Position */
+#define SCT_OUTPUTCLR12_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos) /*!< SCT OUTPUTCLR12: CLRn1 Mask */
+#define SCT_OUTPUTCLR12_CLRn2_Pos 2 /*!< SCT OUTPUTCLR12: CLRn2 Position */
+#define SCT_OUTPUTCLR12_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos) /*!< SCT OUTPUTCLR12: CLRn2 Mask */
+#define SCT_OUTPUTCLR12_CLRn3_Pos 3 /*!< SCT OUTPUTCLR12: CLRn3 Position */
+#define SCT_OUTPUTCLR12_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos) /*!< SCT OUTPUTCLR12: CLRn3 Mask */
+#define SCT_OUTPUTCLR12_CLRn4_Pos 4 /*!< SCT OUTPUTCLR12: CLRn4 Position */
+#define SCT_OUTPUTCLR12_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos) /*!< SCT OUTPUTCLR12: CLRn4 Mask */
+#define SCT_OUTPUTCLR12_CLRn5_Pos 5 /*!< SCT OUTPUTCLR12: CLRn5 Position */
+#define SCT_OUTPUTCLR12_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos) /*!< SCT OUTPUTCLR12: CLRn5 Mask */
+#define SCT_OUTPUTCLR12_CLRn6_Pos 6 /*!< SCT OUTPUTCLR12: CLRn6 Position */
+#define SCT_OUTPUTCLR12_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos) /*!< SCT OUTPUTCLR12: CLRn6 Mask */
+#define SCT_OUTPUTCLR12_CLRn7_Pos 7 /*!< SCT OUTPUTCLR12: CLRn7 Position */
+#define SCT_OUTPUTCLR12_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos) /*!< SCT OUTPUTCLR12: CLRn7 Mask */
+#define SCT_OUTPUTCLR12_CLRn8_Pos 8 /*!< SCT OUTPUTCLR12: CLRn8 Position */
+#define SCT_OUTPUTCLR12_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos) /*!< SCT OUTPUTCLR12: CLRn8 Mask */
+#define SCT_OUTPUTCLR12_CLRn9_Pos 9 /*!< SCT OUTPUTCLR12: CLRn9 Position */
+#define SCT_OUTPUTCLR12_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos) /*!< SCT OUTPUTCLR12: CLRn9 Mask */
+#define SCT_OUTPUTCLR12_CLRn10_Pos 10 /*!< SCT OUTPUTCLR12: CLRn10 Position */
+#define SCT_OUTPUTCLR12_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos) /*!< SCT OUTPUTCLR12: CLRn10 Mask */
+#define SCT_OUTPUTCLR12_CLRn11_Pos 11 /*!< SCT OUTPUTCLR12: CLRn11 Position */
+#define SCT_OUTPUTCLR12_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos) /*!< SCT OUTPUTCLR12: CLRn11 Mask */
+#define SCT_OUTPUTCLR12_CLRn12_Pos 12 /*!< SCT OUTPUTCLR12: CLRn12 Position */
+#define SCT_OUTPUTCLR12_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos) /*!< SCT OUTPUTCLR12: CLRn12 Mask */
+#define SCT_OUTPUTCLR12_CLRn13_Pos 13 /*!< SCT OUTPUTCLR12: CLRn13 Position */
+#define SCT_OUTPUTCLR12_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos) /*!< SCT OUTPUTCLR12: CLRn13 Mask */
+#define SCT_OUTPUTCLR12_CLRn14_Pos 14 /*!< SCT OUTPUTCLR12: CLRn14 Position */
+#define SCT_OUTPUTCLR12_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos) /*!< SCT OUTPUTCLR12: CLRn14 Mask */
+#define SCT_OUTPUTCLR12_CLRn15_Pos 15 /*!< SCT OUTPUTCLR12: CLRn15 Position */
+#define SCT_OUTPUTCLR12_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos) /*!< SCT OUTPUTCLR12: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET13 ----------------------------------------
+#define SCT_OUTPUTSET13_SETn0_Pos 0 /*!< SCT OUTPUTSET13: SETn0 Position */
+#define SCT_OUTPUTSET13_SETn0_Msk (0x01UL << SCT_OUTPUTSET13_SETn0_Pos) /*!< SCT OUTPUTSET13: SETn0 Mask */
+#define SCT_OUTPUTSET13_SETn1_Pos 1 /*!< SCT OUTPUTSET13: SETn1 Position */
+#define SCT_OUTPUTSET13_SETn1_Msk (0x01UL << SCT_OUTPUTSET13_SETn1_Pos) /*!< SCT OUTPUTSET13: SETn1 Mask */
+#define SCT_OUTPUTSET13_SETn2_Pos 2 /*!< SCT OUTPUTSET13: SETn2 Position */
+#define SCT_OUTPUTSET13_SETn2_Msk (0x01UL << SCT_OUTPUTSET13_SETn2_Pos) /*!< SCT OUTPUTSET13: SETn2 Mask */
+#define SCT_OUTPUTSET13_SETn3_Pos 3 /*!< SCT OUTPUTSET13: SETn3 Position */
+#define SCT_OUTPUTSET13_SETn3_Msk (0x01UL << SCT_OUTPUTSET13_SETn3_Pos) /*!< SCT OUTPUTSET13: SETn3 Mask */
+#define SCT_OUTPUTSET13_SETn4_Pos 4 /*!< SCT OUTPUTSET13: SETn4 Position */
+#define SCT_OUTPUTSET13_SETn4_Msk (0x01UL << SCT_OUTPUTSET13_SETn4_Pos) /*!< SCT OUTPUTSET13: SETn4 Mask */
+#define SCT_OUTPUTSET13_SETn5_Pos 5 /*!< SCT OUTPUTSET13: SETn5 Position */
+#define SCT_OUTPUTSET13_SETn5_Msk (0x01UL << SCT_OUTPUTSET13_SETn5_Pos) /*!< SCT OUTPUTSET13: SETn5 Mask */
+#define SCT_OUTPUTSET13_SETn6_Pos 6 /*!< SCT OUTPUTSET13: SETn6 Position */
+#define SCT_OUTPUTSET13_SETn6_Msk (0x01UL << SCT_OUTPUTSET13_SETn6_Pos) /*!< SCT OUTPUTSET13: SETn6 Mask */
+#define SCT_OUTPUTSET13_SETn7_Pos 7 /*!< SCT OUTPUTSET13: SETn7 Position */
+#define SCT_OUTPUTSET13_SETn7_Msk (0x01UL << SCT_OUTPUTSET13_SETn7_Pos) /*!< SCT OUTPUTSET13: SETn7 Mask */
+#define SCT_OUTPUTSET13_SETn8_Pos 8 /*!< SCT OUTPUTSET13: SETn8 Position */
+#define SCT_OUTPUTSET13_SETn8_Msk (0x01UL << SCT_OUTPUTSET13_SETn8_Pos) /*!< SCT OUTPUTSET13: SETn8 Mask */
+#define SCT_OUTPUTSET13_SETn9_Pos 9 /*!< SCT OUTPUTSET13: SETn9 Position */
+#define SCT_OUTPUTSET13_SETn9_Msk (0x01UL << SCT_OUTPUTSET13_SETn9_Pos) /*!< SCT OUTPUTSET13: SETn9 Mask */
+#define SCT_OUTPUTSET13_SETn10_Pos 10 /*!< SCT OUTPUTSET13: SETn10 Position */
+#define SCT_OUTPUTSET13_SETn10_Msk (0x01UL << SCT_OUTPUTSET13_SETn10_Pos) /*!< SCT OUTPUTSET13: SETn10 Mask */
+#define SCT_OUTPUTSET13_SETn11_Pos 11 /*!< SCT OUTPUTSET13: SETn11 Position */
+#define SCT_OUTPUTSET13_SETn11_Msk (0x01UL << SCT_OUTPUTSET13_SETn11_Pos) /*!< SCT OUTPUTSET13: SETn11 Mask */
+#define SCT_OUTPUTSET13_SETn12_Pos 12 /*!< SCT OUTPUTSET13: SETn12 Position */
+#define SCT_OUTPUTSET13_SETn12_Msk (0x01UL << SCT_OUTPUTSET13_SETn12_Pos) /*!< SCT OUTPUTSET13: SETn12 Mask */
+#define SCT_OUTPUTSET13_SETn13_Pos 13 /*!< SCT OUTPUTSET13: SETn13 Position */
+#define SCT_OUTPUTSET13_SETn13_Msk (0x01UL << SCT_OUTPUTSET13_SETn13_Pos) /*!< SCT OUTPUTSET13: SETn13 Mask */
+#define SCT_OUTPUTSET13_SETn14_Pos 14 /*!< SCT OUTPUTSET13: SETn14 Position */
+#define SCT_OUTPUTSET13_SETn14_Msk (0x01UL << SCT_OUTPUTSET13_SETn14_Pos) /*!< SCT OUTPUTSET13: SETn14 Mask */
+#define SCT_OUTPUTSET13_SETn15_Pos 15 /*!< SCT OUTPUTSET13: SETn15 Position */
+#define SCT_OUTPUTSET13_SETn15_Msk (0x01UL << SCT_OUTPUTSET13_SETn15_Pos) /*!< SCT OUTPUTSET13: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR13 ----------------------------------------
+#define SCT_OUTPUTCLR13_CLRn0_Pos 0 /*!< SCT OUTPUTCLR13: CLRn0 Position */
+#define SCT_OUTPUTCLR13_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos) /*!< SCT OUTPUTCLR13: CLRn0 Mask */
+#define SCT_OUTPUTCLR13_CLRn1_Pos 1 /*!< SCT OUTPUTCLR13: CLRn1 Position */
+#define SCT_OUTPUTCLR13_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos) /*!< SCT OUTPUTCLR13: CLRn1 Mask */
+#define SCT_OUTPUTCLR13_CLRn2_Pos 2 /*!< SCT OUTPUTCLR13: CLRn2 Position */
+#define SCT_OUTPUTCLR13_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos) /*!< SCT OUTPUTCLR13: CLRn2 Mask */
+#define SCT_OUTPUTCLR13_CLRn3_Pos 3 /*!< SCT OUTPUTCLR13: CLRn3 Position */
+#define SCT_OUTPUTCLR13_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos) /*!< SCT OUTPUTCLR13: CLRn3 Mask */
+#define SCT_OUTPUTCLR13_CLRn4_Pos 4 /*!< SCT OUTPUTCLR13: CLRn4 Position */
+#define SCT_OUTPUTCLR13_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos) /*!< SCT OUTPUTCLR13: CLRn4 Mask */
+#define SCT_OUTPUTCLR13_CLRn5_Pos 5 /*!< SCT OUTPUTCLR13: CLRn5 Position */
+#define SCT_OUTPUTCLR13_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos) /*!< SCT OUTPUTCLR13: CLRn5 Mask */
+#define SCT_OUTPUTCLR13_CLRn6_Pos 6 /*!< SCT OUTPUTCLR13: CLRn6 Position */
+#define SCT_OUTPUTCLR13_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos) /*!< SCT OUTPUTCLR13: CLRn6 Mask */
+#define SCT_OUTPUTCLR13_CLRn7_Pos 7 /*!< SCT OUTPUTCLR13: CLRn7 Position */
+#define SCT_OUTPUTCLR13_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos) /*!< SCT OUTPUTCLR13: CLRn7 Mask */
+#define SCT_OUTPUTCLR13_CLRn8_Pos 8 /*!< SCT OUTPUTCLR13: CLRn8 Position */
+#define SCT_OUTPUTCLR13_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos) /*!< SCT OUTPUTCLR13: CLRn8 Mask */
+#define SCT_OUTPUTCLR13_CLRn9_Pos 9 /*!< SCT OUTPUTCLR13: CLRn9 Position */
+#define SCT_OUTPUTCLR13_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos) /*!< SCT OUTPUTCLR13: CLRn9 Mask */
+#define SCT_OUTPUTCLR13_CLRn10_Pos 10 /*!< SCT OUTPUTCLR13: CLRn10 Position */
+#define SCT_OUTPUTCLR13_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos) /*!< SCT OUTPUTCLR13: CLRn10 Mask */
+#define SCT_OUTPUTCLR13_CLRn11_Pos 11 /*!< SCT OUTPUTCLR13: CLRn11 Position */
+#define SCT_OUTPUTCLR13_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos) /*!< SCT OUTPUTCLR13: CLRn11 Mask */
+#define SCT_OUTPUTCLR13_CLRn12_Pos 12 /*!< SCT OUTPUTCLR13: CLRn12 Position */
+#define SCT_OUTPUTCLR13_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos) /*!< SCT OUTPUTCLR13: CLRn12 Mask */
+#define SCT_OUTPUTCLR13_CLRn13_Pos 13 /*!< SCT OUTPUTCLR13: CLRn13 Position */
+#define SCT_OUTPUTCLR13_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos) /*!< SCT OUTPUTCLR13: CLRn13 Mask */
+#define SCT_OUTPUTCLR13_CLRn14_Pos 14 /*!< SCT OUTPUTCLR13: CLRn14 Position */
+#define SCT_OUTPUTCLR13_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos) /*!< SCT OUTPUTCLR13: CLRn14 Mask */
+#define SCT_OUTPUTCLR13_CLRn15_Pos 15 /*!< SCT OUTPUTCLR13: CLRn15 Position */
+#define SCT_OUTPUTCLR13_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos) /*!< SCT OUTPUTCLR13: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET14 ----------------------------------------
+#define SCT_OUTPUTSET14_SETn0_Pos 0 /*!< SCT OUTPUTSET14: SETn0 Position */
+#define SCT_OUTPUTSET14_SETn0_Msk (0x01UL << SCT_OUTPUTSET14_SETn0_Pos) /*!< SCT OUTPUTSET14: SETn0 Mask */
+#define SCT_OUTPUTSET14_SETn1_Pos 1 /*!< SCT OUTPUTSET14: SETn1 Position */
+#define SCT_OUTPUTSET14_SETn1_Msk (0x01UL << SCT_OUTPUTSET14_SETn1_Pos) /*!< SCT OUTPUTSET14: SETn1 Mask */
+#define SCT_OUTPUTSET14_SETn2_Pos 2 /*!< SCT OUTPUTSET14: SETn2 Position */
+#define SCT_OUTPUTSET14_SETn2_Msk (0x01UL << SCT_OUTPUTSET14_SETn2_Pos) /*!< SCT OUTPUTSET14: SETn2 Mask */
+#define SCT_OUTPUTSET14_SETn3_Pos 3 /*!< SCT OUTPUTSET14: SETn3 Position */
+#define SCT_OUTPUTSET14_SETn3_Msk (0x01UL << SCT_OUTPUTSET14_SETn3_Pos) /*!< SCT OUTPUTSET14: SETn3 Mask */
+#define SCT_OUTPUTSET14_SETn4_Pos 4 /*!< SCT OUTPUTSET14: SETn4 Position */
+#define SCT_OUTPUTSET14_SETn4_Msk (0x01UL << SCT_OUTPUTSET14_SETn4_Pos) /*!< SCT OUTPUTSET14: SETn4 Mask */
+#define SCT_OUTPUTSET14_SETn5_Pos 5 /*!< SCT OUTPUTSET14: SETn5 Position */
+#define SCT_OUTPUTSET14_SETn5_Msk (0x01UL << SCT_OUTPUTSET14_SETn5_Pos) /*!< SCT OUTPUTSET14: SETn5 Mask */
+#define SCT_OUTPUTSET14_SETn6_Pos 6 /*!< SCT OUTPUTSET14: SETn6 Position */
+#define SCT_OUTPUTSET14_SETn6_Msk (0x01UL << SCT_OUTPUTSET14_SETn6_Pos) /*!< SCT OUTPUTSET14: SETn6 Mask */
+#define SCT_OUTPUTSET14_SETn7_Pos 7 /*!< SCT OUTPUTSET14: SETn7 Position */
+#define SCT_OUTPUTSET14_SETn7_Msk (0x01UL << SCT_OUTPUTSET14_SETn7_Pos) /*!< SCT OUTPUTSET14: SETn7 Mask */
+#define SCT_OUTPUTSET14_SETn8_Pos 8 /*!< SCT OUTPUTSET14: SETn8 Position */
+#define SCT_OUTPUTSET14_SETn8_Msk (0x01UL << SCT_OUTPUTSET14_SETn8_Pos) /*!< SCT OUTPUTSET14: SETn8 Mask */
+#define SCT_OUTPUTSET14_SETn9_Pos 9 /*!< SCT OUTPUTSET14: SETn9 Position */
+#define SCT_OUTPUTSET14_SETn9_Msk (0x01UL << SCT_OUTPUTSET14_SETn9_Pos) /*!< SCT OUTPUTSET14: SETn9 Mask */
+#define SCT_OUTPUTSET14_SETn10_Pos 10 /*!< SCT OUTPUTSET14: SETn10 Position */
+#define SCT_OUTPUTSET14_SETn10_Msk (0x01UL << SCT_OUTPUTSET14_SETn10_Pos) /*!< SCT OUTPUTSET14: SETn10 Mask */
+#define SCT_OUTPUTSET14_SETn11_Pos 11 /*!< SCT OUTPUTSET14: SETn11 Position */
+#define SCT_OUTPUTSET14_SETn11_Msk (0x01UL << SCT_OUTPUTSET14_SETn11_Pos) /*!< SCT OUTPUTSET14: SETn11 Mask */
+#define SCT_OUTPUTSET14_SETn12_Pos 12 /*!< SCT OUTPUTSET14: SETn12 Position */
+#define SCT_OUTPUTSET14_SETn12_Msk (0x01UL << SCT_OUTPUTSET14_SETn12_Pos) /*!< SCT OUTPUTSET14: SETn12 Mask */
+#define SCT_OUTPUTSET14_SETn13_Pos 13 /*!< SCT OUTPUTSET14: SETn13 Position */
+#define SCT_OUTPUTSET14_SETn13_Msk (0x01UL << SCT_OUTPUTSET14_SETn13_Pos) /*!< SCT OUTPUTSET14: SETn13 Mask */
+#define SCT_OUTPUTSET14_SETn14_Pos 14 /*!< SCT OUTPUTSET14: SETn14 Position */
+#define SCT_OUTPUTSET14_SETn14_Msk (0x01UL << SCT_OUTPUTSET14_SETn14_Pos) /*!< SCT OUTPUTSET14: SETn14 Mask */
+#define SCT_OUTPUTSET14_SETn15_Pos 15 /*!< SCT OUTPUTSET14: SETn15 Position */
+#define SCT_OUTPUTSET14_SETn15_Msk (0x01UL << SCT_OUTPUTSET14_SETn15_Pos) /*!< SCT OUTPUTSET14: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR14 ----------------------------------------
+#define SCT_OUTPUTCLR14_CLRn0_Pos 0 /*!< SCT OUTPUTCLR14: CLRn0 Position */
+#define SCT_OUTPUTCLR14_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos) /*!< SCT OUTPUTCLR14: CLRn0 Mask */
+#define SCT_OUTPUTCLR14_CLRn1_Pos 1 /*!< SCT OUTPUTCLR14: CLRn1 Position */
+#define SCT_OUTPUTCLR14_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos) /*!< SCT OUTPUTCLR14: CLRn1 Mask */
+#define SCT_OUTPUTCLR14_CLRn2_Pos 2 /*!< SCT OUTPUTCLR14: CLRn2 Position */
+#define SCT_OUTPUTCLR14_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos) /*!< SCT OUTPUTCLR14: CLRn2 Mask */
+#define SCT_OUTPUTCLR14_CLRn3_Pos 3 /*!< SCT OUTPUTCLR14: CLRn3 Position */
+#define SCT_OUTPUTCLR14_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos) /*!< SCT OUTPUTCLR14: CLRn3 Mask */
+#define SCT_OUTPUTCLR14_CLRn4_Pos 4 /*!< SCT OUTPUTCLR14: CLRn4 Position */
+#define SCT_OUTPUTCLR14_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos) /*!< SCT OUTPUTCLR14: CLRn4 Mask */
+#define SCT_OUTPUTCLR14_CLRn5_Pos 5 /*!< SCT OUTPUTCLR14: CLRn5 Position */
+#define SCT_OUTPUTCLR14_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos) /*!< SCT OUTPUTCLR14: CLRn5 Mask */
+#define SCT_OUTPUTCLR14_CLRn6_Pos 6 /*!< SCT OUTPUTCLR14: CLRn6 Position */
+#define SCT_OUTPUTCLR14_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos) /*!< SCT OUTPUTCLR14: CLRn6 Mask */
+#define SCT_OUTPUTCLR14_CLRn7_Pos 7 /*!< SCT OUTPUTCLR14: CLRn7 Position */
+#define SCT_OUTPUTCLR14_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos) /*!< SCT OUTPUTCLR14: CLRn7 Mask */
+#define SCT_OUTPUTCLR14_CLRn8_Pos 8 /*!< SCT OUTPUTCLR14: CLRn8 Position */
+#define SCT_OUTPUTCLR14_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos) /*!< SCT OUTPUTCLR14: CLRn8 Mask */
+#define SCT_OUTPUTCLR14_CLRn9_Pos 9 /*!< SCT OUTPUTCLR14: CLRn9 Position */
+#define SCT_OUTPUTCLR14_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos) /*!< SCT OUTPUTCLR14: CLRn9 Mask */
+#define SCT_OUTPUTCLR14_CLRn10_Pos 10 /*!< SCT OUTPUTCLR14: CLRn10 Position */
+#define SCT_OUTPUTCLR14_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos) /*!< SCT OUTPUTCLR14: CLRn10 Mask */
+#define SCT_OUTPUTCLR14_CLRn11_Pos 11 /*!< SCT OUTPUTCLR14: CLRn11 Position */
+#define SCT_OUTPUTCLR14_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos) /*!< SCT OUTPUTCLR14: CLRn11 Mask */
+#define SCT_OUTPUTCLR14_CLRn12_Pos 12 /*!< SCT OUTPUTCLR14: CLRn12 Position */
+#define SCT_OUTPUTCLR14_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos) /*!< SCT OUTPUTCLR14: CLRn12 Mask */
+#define SCT_OUTPUTCLR14_CLRn13_Pos 13 /*!< SCT OUTPUTCLR14: CLRn13 Position */
+#define SCT_OUTPUTCLR14_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos) /*!< SCT OUTPUTCLR14: CLRn13 Mask */
+#define SCT_OUTPUTCLR14_CLRn14_Pos 14 /*!< SCT OUTPUTCLR14: CLRn14 Position */
+#define SCT_OUTPUTCLR14_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos) /*!< SCT OUTPUTCLR14: CLRn14 Mask */
+#define SCT_OUTPUTCLR14_CLRn15_Pos 15 /*!< SCT OUTPUTCLR14: CLRn15 Position */
+#define SCT_OUTPUTCLR14_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos) /*!< SCT OUTPUTCLR14: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET15 ----------------------------------------
+#define SCT_OUTPUTSET15_SETn0_Pos 0 /*!< SCT OUTPUTSET15: SETn0 Position */
+#define SCT_OUTPUTSET15_SETn0_Msk (0x01UL << SCT_OUTPUTSET15_SETn0_Pos) /*!< SCT OUTPUTSET15: SETn0 Mask */
+#define SCT_OUTPUTSET15_SETn1_Pos 1 /*!< SCT OUTPUTSET15: SETn1 Position */
+#define SCT_OUTPUTSET15_SETn1_Msk (0x01UL << SCT_OUTPUTSET15_SETn1_Pos) /*!< SCT OUTPUTSET15: SETn1 Mask */
+#define SCT_OUTPUTSET15_SETn2_Pos 2 /*!< SCT OUTPUTSET15: SETn2 Position */
+#define SCT_OUTPUTSET15_SETn2_Msk (0x01UL << SCT_OUTPUTSET15_SETn2_Pos) /*!< SCT OUTPUTSET15: SETn2 Mask */
+#define SCT_OUTPUTSET15_SETn3_Pos 3 /*!< SCT OUTPUTSET15: SETn3 Position */
+#define SCT_OUTPUTSET15_SETn3_Msk (0x01UL << SCT_OUTPUTSET15_SETn3_Pos) /*!< SCT OUTPUTSET15: SETn3 Mask */
+#define SCT_OUTPUTSET15_SETn4_Pos 4 /*!< SCT OUTPUTSET15: SETn4 Position */
+#define SCT_OUTPUTSET15_SETn4_Msk (0x01UL << SCT_OUTPUTSET15_SETn4_Pos) /*!< SCT OUTPUTSET15: SETn4 Mask */
+#define SCT_OUTPUTSET15_SETn5_Pos 5 /*!< SCT OUTPUTSET15: SETn5 Position */
+#define SCT_OUTPUTSET15_SETn5_Msk (0x01UL << SCT_OUTPUTSET15_SETn5_Pos) /*!< SCT OUTPUTSET15: SETn5 Mask */
+#define SCT_OUTPUTSET15_SETn6_Pos 6 /*!< SCT OUTPUTSET15: SETn6 Position */
+#define SCT_OUTPUTSET15_SETn6_Msk (0x01UL << SCT_OUTPUTSET15_SETn6_Pos) /*!< SCT OUTPUTSET15: SETn6 Mask */
+#define SCT_OUTPUTSET15_SETn7_Pos 7 /*!< SCT OUTPUTSET15: SETn7 Position */
+#define SCT_OUTPUTSET15_SETn7_Msk (0x01UL << SCT_OUTPUTSET15_SETn7_Pos) /*!< SCT OUTPUTSET15: SETn7 Mask */
+#define SCT_OUTPUTSET15_SETn8_Pos 8 /*!< SCT OUTPUTSET15: SETn8 Position */
+#define SCT_OUTPUTSET15_SETn8_Msk (0x01UL << SCT_OUTPUTSET15_SETn8_Pos) /*!< SCT OUTPUTSET15: SETn8 Mask */
+#define SCT_OUTPUTSET15_SETn9_Pos 9 /*!< SCT OUTPUTSET15: SETn9 Position */
+#define SCT_OUTPUTSET15_SETn9_Msk (0x01UL << SCT_OUTPUTSET15_SETn9_Pos) /*!< SCT OUTPUTSET15: SETn9 Mask */
+#define SCT_OUTPUTSET15_SETn10_Pos 10 /*!< SCT OUTPUTSET15: SETn10 Position */
+#define SCT_OUTPUTSET15_SETn10_Msk (0x01UL << SCT_OUTPUTSET15_SETn10_Pos) /*!< SCT OUTPUTSET15: SETn10 Mask */
+#define SCT_OUTPUTSET15_SETn11_Pos 11 /*!< SCT OUTPUTSET15: SETn11 Position */
+#define SCT_OUTPUTSET15_SETn11_Msk (0x01UL << SCT_OUTPUTSET15_SETn11_Pos) /*!< SCT OUTPUTSET15: SETn11 Mask */
+#define SCT_OUTPUTSET15_SETn12_Pos 12 /*!< SCT OUTPUTSET15: SETn12 Position */
+#define SCT_OUTPUTSET15_SETn12_Msk (0x01UL << SCT_OUTPUTSET15_SETn12_Pos) /*!< SCT OUTPUTSET15: SETn12 Mask */
+#define SCT_OUTPUTSET15_SETn13_Pos 13 /*!< SCT OUTPUTSET15: SETn13 Position */
+#define SCT_OUTPUTSET15_SETn13_Msk (0x01UL << SCT_OUTPUTSET15_SETn13_Pos) /*!< SCT OUTPUTSET15: SETn13 Mask */
+#define SCT_OUTPUTSET15_SETn14_Pos 14 /*!< SCT OUTPUTSET15: SETn14 Position */
+#define SCT_OUTPUTSET15_SETn14_Msk (0x01UL << SCT_OUTPUTSET15_SETn14_Pos) /*!< SCT OUTPUTSET15: SETn14 Mask */
+#define SCT_OUTPUTSET15_SETn15_Pos 15 /*!< SCT OUTPUTSET15: SETn15 Position */
+#define SCT_OUTPUTSET15_SETn15_Msk (0x01UL << SCT_OUTPUTSET15_SETn15_Pos) /*!< SCT OUTPUTSET15: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR15 ----------------------------------------
+#define SCT_OUTPUTCLR15_CLRn0_Pos 0 /*!< SCT OUTPUTCLR15: CLRn0 Position */
+#define SCT_OUTPUTCLR15_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos) /*!< SCT OUTPUTCLR15: CLRn0 Mask */
+#define SCT_OUTPUTCLR15_CLRn1_Pos 1 /*!< SCT OUTPUTCLR15: CLRn1 Position */
+#define SCT_OUTPUTCLR15_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos) /*!< SCT OUTPUTCLR15: CLRn1 Mask */
+#define SCT_OUTPUTCLR15_CLRn2_Pos 2 /*!< SCT OUTPUTCLR15: CLRn2 Position */
+#define SCT_OUTPUTCLR15_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos) /*!< SCT OUTPUTCLR15: CLRn2 Mask */
+#define SCT_OUTPUTCLR15_CLRn3_Pos 3 /*!< SCT OUTPUTCLR15: CLRn3 Position */
+#define SCT_OUTPUTCLR15_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos) /*!< SCT OUTPUTCLR15: CLRn3 Mask */
+#define SCT_OUTPUTCLR15_CLRn4_Pos 4 /*!< SCT OUTPUTCLR15: CLRn4 Position */
+#define SCT_OUTPUTCLR15_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos) /*!< SCT OUTPUTCLR15: CLRn4 Mask */
+#define SCT_OUTPUTCLR15_CLRn5_Pos 5 /*!< SCT OUTPUTCLR15: CLRn5 Position */
+#define SCT_OUTPUTCLR15_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos) /*!< SCT OUTPUTCLR15: CLRn5 Mask */
+#define SCT_OUTPUTCLR15_CLRn6_Pos 6 /*!< SCT OUTPUTCLR15: CLRn6 Position */
+#define SCT_OUTPUTCLR15_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos) /*!< SCT OUTPUTCLR15: CLRn6 Mask */
+#define SCT_OUTPUTCLR15_CLRn7_Pos 7 /*!< SCT OUTPUTCLR15: CLRn7 Position */
+#define SCT_OUTPUTCLR15_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos) /*!< SCT OUTPUTCLR15: CLRn7 Mask */
+#define SCT_OUTPUTCLR15_CLRn8_Pos 8 /*!< SCT OUTPUTCLR15: CLRn8 Position */
+#define SCT_OUTPUTCLR15_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos) /*!< SCT OUTPUTCLR15: CLRn8 Mask */
+#define SCT_OUTPUTCLR15_CLRn9_Pos 9 /*!< SCT OUTPUTCLR15: CLRn9 Position */
+#define SCT_OUTPUTCLR15_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos) /*!< SCT OUTPUTCLR15: CLRn9 Mask */
+#define SCT_OUTPUTCLR15_CLRn10_Pos 10 /*!< SCT OUTPUTCLR15: CLRn10 Position */
+#define SCT_OUTPUTCLR15_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos) /*!< SCT OUTPUTCLR15: CLRn10 Mask */
+#define SCT_OUTPUTCLR15_CLRn11_Pos 11 /*!< SCT OUTPUTCLR15: CLRn11 Position */
+#define SCT_OUTPUTCLR15_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos) /*!< SCT OUTPUTCLR15: CLRn11 Mask */
+#define SCT_OUTPUTCLR15_CLRn12_Pos 12 /*!< SCT OUTPUTCLR15: CLRn12 Position */
+#define SCT_OUTPUTCLR15_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos) /*!< SCT OUTPUTCLR15: CLRn12 Mask */
+#define SCT_OUTPUTCLR15_CLRn13_Pos 13 /*!< SCT OUTPUTCLR15: CLRn13 Position */
+#define SCT_OUTPUTCLR15_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos) /*!< SCT OUTPUTCLR15: CLRn13 Mask */
+#define SCT_OUTPUTCLR15_CLRn14_Pos 14 /*!< SCT OUTPUTCLR15: CLRn14 Position */
+#define SCT_OUTPUTCLR15_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos) /*!< SCT OUTPUTCLR15: CLRn14 Mask */
+#define SCT_OUTPUTCLR15_CLRn15_Pos 15 /*!< SCT OUTPUTCLR15: CLRn15 Position */
+#define SCT_OUTPUTCLR15_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos) /*!< SCT OUTPUTCLR15: CLRn15 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPDMA Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------- GPDMA_INTSTAT -----------------------------------------
+#define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */
+#define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */
+#define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */
+#define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */
+#define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */
+#define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */
+#define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */
+#define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */
+#define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */
+#define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */
+#define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */
+#define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */
+#define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */
+#define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */
+#define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */
+#define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */
+
+// ------------------------------------- GPDMA_INTTCSTAT ----------------------------------------
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */
+
+// ------------------------------------ GPDMA_INTTCCLEAR ----------------------------------------
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */
+
+// ------------------------------------ GPDMA_INTERRSTAT ----------------------------------------
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */
+
+// ------------------------------------- GPDMA_INTERRCLR ----------------------------------------
+#define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */
+#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */
+#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */
+#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */
+#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */
+#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */
+#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */
+#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */
+#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */
+
+// ----------------------------------- GPDMA_RAWINTTCSTAT ---------------------------------------
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */
+
+// ----------------------------------- GPDMA_RAWINTERRSTAT --------------------------------------
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */
+
+// ------------------------------------- GPDMA_ENBLDCHNS ----------------------------------------
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */
+
+// ------------------------------------- GPDMA_SOFTBREQ -----------------------------------------
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */
+
+// ------------------------------------- GPDMA_SOFTSREQ -----------------------------------------
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */
+
+// ------------------------------------- GPDMA_SOFTLBREQ ----------------------------------------
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */
+
+// ------------------------------------- GPDMA_SOFTLSREQ ----------------------------------------
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */
+
+// -------------------------------------- GPDMA_CONFIG ------------------------------------------
+#define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */
+#define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */
+#define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */
+#define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */
+#define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */
+#define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */
+
+// --------------------------------------- GPDMA_SYNC -------------------------------------------
+#define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */
+#define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */
+#define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */
+#define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */
+#define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */
+#define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */
+#define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */
+#define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */
+#define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */
+#define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */
+#define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */
+#define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */
+#define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */
+#define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */
+#define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */
+#define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */
+#define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */
+#define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */
+#define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */
+#define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */
+#define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */
+#define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */
+#define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */
+#define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */
+#define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */
+#define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */
+#define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */
+#define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */
+#define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */
+#define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */
+#define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */
+#define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */
+
+// ------------------------------------- GPDMA_C0SRCADDR ----------------------------------------
+#define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */
+#define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C0DESTADDR ----------------------------------------
+#define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */
+#define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C0LLI ------------------------------------------
+#define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */
+#define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */
+#define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */
+#define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */
+#define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */
+#define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C0CONTROL ----------------------------------------
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */
+#define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */
+#define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */
+#define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */
+#define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */
+#define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */
+#define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */
+#define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */
+#define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */
+#define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */
+#define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */
+#define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */
+#define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */
+#define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */
+#define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */
+#define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */
+#define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */
+#define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */
+#define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */
+#define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */
+#define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */
+#define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */
+#define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */
+#define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C0CONFIG -----------------------------------------
+#define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */
+#define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */
+#define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */
+#define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */
+#define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */
+#define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */
+#define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */
+#define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */
+#define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */
+#define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */
+#define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C1SRCADDR ----------------------------------------
+#define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */
+#define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C1DESTADDR ----------------------------------------
+#define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */
+#define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C1LLI ------------------------------------------
+#define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */
+#define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */
+#define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */
+#define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */
+#define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */
+#define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C1CONTROL ----------------------------------------
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */
+#define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */
+#define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */
+#define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */
+#define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */
+#define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */
+#define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */
+#define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */
+#define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */
+#define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */
+#define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */
+#define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */
+#define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */
+#define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */
+#define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */
+#define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */
+#define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */
+#define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */
+#define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */
+#define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */
+#define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */
+#define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */
+#define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */
+#define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C1CONFIG -----------------------------------------
+#define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */
+#define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */
+#define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */
+#define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */
+#define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */
+#define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */
+#define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */
+#define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */
+#define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */
+#define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */
+#define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C2SRCADDR ----------------------------------------
+#define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */
+#define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C2DESTADDR ----------------------------------------
+#define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */
+#define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C2LLI ------------------------------------------
+#define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */
+#define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */
+#define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */
+#define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */
+#define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */
+#define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C2CONTROL ----------------------------------------
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */
+#define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */
+#define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */
+#define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */
+#define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */
+#define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */
+#define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */
+#define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */
+#define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */
+#define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */
+#define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */
+#define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */
+#define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */
+#define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */
+#define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */
+#define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */
+#define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */
+#define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */
+#define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */
+#define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */
+#define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */
+#define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */
+#define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */
+#define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C2CONFIG -----------------------------------------
+#define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */
+#define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */
+#define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */
+#define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */
+#define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */
+#define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */
+#define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */
+#define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */
+#define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */
+#define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */
+#define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C3SRCADDR ----------------------------------------
+#define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */
+#define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C3DESTADDR ----------------------------------------
+#define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */
+#define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C3LLI ------------------------------------------
+#define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */
+#define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */
+#define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */
+#define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */
+#define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */
+#define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C3CONTROL ----------------------------------------
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */
+#define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */
+#define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */
+#define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */
+#define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */
+#define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */
+#define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */
+#define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */
+#define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */
+#define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */
+#define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */
+#define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */
+#define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */
+#define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */
+#define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */
+#define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */
+#define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */
+#define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */
+#define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */
+#define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */
+#define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */
+#define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */
+#define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */
+#define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C3CONFIG -----------------------------------------
+#define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */
+#define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */
+#define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */
+#define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */
+#define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */
+#define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */
+#define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */
+#define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */
+#define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */
+#define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */
+#define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C4SRCADDR ----------------------------------------
+#define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */
+#define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C4DESTADDR ----------------------------------------
+#define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */
+#define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C4LLI ------------------------------------------
+#define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */
+#define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */
+#define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */
+#define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */
+#define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */
+#define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C4CONTROL ----------------------------------------
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */
+#define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */
+#define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */
+#define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */
+#define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */
+#define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */
+#define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */
+#define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */
+#define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */
+#define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */
+#define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */
+#define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */
+#define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */
+#define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */
+#define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */
+#define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */
+#define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */
+#define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */
+#define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */
+#define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */
+#define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */
+#define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */
+#define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */
+#define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C4CONFIG -----------------------------------------
+#define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */
+#define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */
+#define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */
+#define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */
+#define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */
+#define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */
+#define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */
+#define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */
+#define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */
+#define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */
+#define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C5SRCADDR ----------------------------------------
+#define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */
+#define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C5DESTADDR ----------------------------------------
+#define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */
+#define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C5LLI ------------------------------------------
+#define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */
+#define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */
+#define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */
+#define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */
+#define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */
+#define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C5CONTROL ----------------------------------------
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */
+#define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */
+#define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */
+#define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */
+#define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */
+#define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */
+#define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */
+#define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */
+#define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */
+#define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */
+#define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */
+#define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */
+#define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */
+#define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */
+#define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */
+#define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */
+#define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */
+#define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */
+#define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */
+#define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */
+#define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */
+#define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */
+#define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */
+#define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C5CONFIG -----------------------------------------
+#define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */
+#define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */
+#define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */
+#define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */
+#define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */
+#define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */
+#define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */
+#define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */
+#define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */
+#define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */
+#define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C6SRCADDR ----------------------------------------
+#define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */
+#define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C6DESTADDR ----------------------------------------
+#define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */
+#define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C6LLI ------------------------------------------
+#define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */
+#define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */
+#define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */
+#define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */
+#define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */
+#define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C6CONTROL ----------------------------------------
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */
+#define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */
+#define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */
+#define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */
+#define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */
+#define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */
+#define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */
+#define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */
+#define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */
+#define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */
+#define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */
+#define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */
+#define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */
+#define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */
+#define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */
+#define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */
+#define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */
+#define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */
+#define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */
+#define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */
+#define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */
+#define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */
+#define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */
+#define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C6CONFIG -----------------------------------------
+#define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */
+#define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */
+#define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */
+#define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */
+#define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */
+#define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */
+#define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */
+#define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */
+#define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */
+#define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */
+#define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C7SRCADDR ----------------------------------------
+#define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */
+#define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C7DESTADDR ----------------------------------------
+#define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */
+#define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C7LLI ------------------------------------------
+#define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */
+#define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */
+#define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */
+#define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */
+#define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */
+#define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C7CONTROL ----------------------------------------
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */
+#define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */
+#define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */
+#define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */
+#define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */
+#define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */
+#define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */
+#define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */
+#define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */
+#define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */
+#define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */
+#define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */
+#define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */
+#define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */
+#define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */
+#define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */
+#define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */
+#define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */
+#define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */
+#define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */
+#define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */
+#define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */
+#define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */
+#define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C7CONFIG -----------------------------------------
+#define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */
+#define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */
+#define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */
+#define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */
+#define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */
+#define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */
+#define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */
+#define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */
+#define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */
+#define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */
+#define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SDMMC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- SDMMC_CTRL -------------------------------------------
+#define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */
+#define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */
+#define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */
+#define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */
+#define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */
+#define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */
+#define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */
+#define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */
+#define SDMMC_CTRL_DMA_ENABLE_Pos 5 /*!< SDMMC CTRL: DMA_ENABLE Position */
+#define SDMMC_CTRL_DMA_ENABLE_Msk (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos) /*!< SDMMC CTRL: DMA_ENABLE Mask */
+#define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */
+#define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */
+#define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */
+#define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */
+#define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */
+#define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos) /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos 20 /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos 24 /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos) /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */
+
+// --------------------------------------- SDMMC_PWREN ------------------------------------------
+#define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */
+#define SDMMC_PWREN_POWER_ENABLE_Msk (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */
+
+// -------------------------------------- SDMMC_CLKDIV ------------------------------------------
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */
+
+// -------------------------------------- SDMMC_CLKSRC ------------------------------------------
+#define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */
+#define SDMMC_CLKSRC_CLK_SOURCE_Msk (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */
+
+// -------------------------------------- SDMMC_CLKENA ------------------------------------------
+#define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */
+#define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */
+
+// --------------------------------------- SDMMC_TMOUT ------------------------------------------
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */
+
+// --------------------------------------- SDMMC_CTYPE ------------------------------------------
+#define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */
+#define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */
+#define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */
+#define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */
+
+// -------------------------------------- SDMMC_BLKSIZ ------------------------------------------
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */
+
+// -------------------------------------- SDMMC_BYTCNT ------------------------------------------
+#define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */
+#define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */
+
+// -------------------------------------- SDMMC_INTMASK -----------------------------------------
+#define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */
+#define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */
+#define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */
+#define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */
+#define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */
+#define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */
+#define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */
+#define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */
+#define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */
+#define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */
+#define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */
+#define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */
+#define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */
+#define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */
+#define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */
+#define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */
+#define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */
+#define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */
+#define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */
+#define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */
+#define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */
+#define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */
+#define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */
+#define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */
+#define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */
+#define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */
+#define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */
+#define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */
+#define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */
+#define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */
+#define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */
+#define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */
+
+// -------------------------------------- SDMMC_CMDARG ------------------------------------------
+#define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */
+#define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */
+
+// ---------------------------------------- SDMMC_CMD -------------------------------------------
+#define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */
+#define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */
+#define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */
+#define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */
+#define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */
+#define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */
+#define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */
+#define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */
+#define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */
+#define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */
+#define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */
+#define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */
+#define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */
+#define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */
+#define SDMMC_CMD_STOP_ABORT_CMd_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMd Position */
+#define SDMMC_CMD_STOP_ABORT_CMd_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos) /*!< SDMMC CMD: STOP_ABORT_CMd Mask */
+#define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */
+#define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */
+#define SDMMC_CMD_CARD_NUMBER_Pos 16 /*!< SDMMC CMD: CARD_NUMBER Position */
+#define SDMMC_CMD_CARD_NUMBER_Msk (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos) /*!< SDMMC CMD: CARD_NUMBER Mask */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos) /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */
+#define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */
+#define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */
+#define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */
+#define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */
+#define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */
+#define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */
+#define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */
+#define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */
+#define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */
+#define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */
+#define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */
+#define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */
+
+// --------------------------------------- SDMMC_RESP0 ------------------------------------------
+#define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */
+#define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */
+
+// --------------------------------------- SDMMC_RESP1 ------------------------------------------
+#define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */
+#define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */
+
+// --------------------------------------- SDMMC_RESP2 ------------------------------------------
+#define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */
+#define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */
+
+// --------------------------------------- SDMMC_RESP3 ------------------------------------------
+#define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */
+#define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */
+
+// -------------------------------------- SDMMC_MINTSTS -----------------------------------------
+#define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */
+#define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */
+#define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */
+#define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */
+#define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */
+#define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */
+#define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */
+#define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */
+#define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */
+#define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */
+#define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */
+#define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */
+#define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */
+#define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */
+#define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */
+#define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */
+#define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */
+#define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */
+#define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */
+#define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */
+#define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */
+#define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */
+#define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */
+#define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */
+#define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */
+#define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */
+#define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */
+#define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */
+#define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */
+#define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */
+#define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */
+#define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */
+
+// -------------------------------------- SDMMC_RINTSTS -----------------------------------------
+#define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */
+#define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */
+#define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */
+#define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */
+#define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */
+#define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */
+#define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */
+#define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */
+#define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */
+#define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */
+#define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */
+#define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */
+#define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */
+#define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */
+#define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */
+#define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */
+#define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */
+#define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */
+#define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */
+#define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */
+#define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */
+#define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */
+#define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */
+#define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */
+#define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */
+#define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */
+#define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */
+#define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */
+#define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */
+#define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */
+#define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */
+#define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */
+
+// -------------------------------------- SDMMC_STATUS ------------------------------------------
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */
+#define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */
+#define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */
+#define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */
+#define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */
+#define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */
+#define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */
+#define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */
+#define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */
+#define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */
+#define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */
+#define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */
+#define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */
+#define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */
+#define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */
+#define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */
+#define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */
+#define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */
+
+// -------------------------------------- SDMMC_FIFOTH ------------------------------------------
+#define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */
+#define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */
+#define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */
+#define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos 28 /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */
+
+// -------------------------------------- SDMMC_CDETECT -----------------------------------------
+#define SDMMC_CDETECT_CARD_DETECT_N_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT_N Position */
+#define SDMMC_CDETECT_CARD_DETECT_N_Msk (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos) /*!< SDMMC CDETECT: CARD_DETECT_N Mask */
+
+// -------------------------------------- SDMMC_WRTPRT ------------------------------------------
+#define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */
+#define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */
+
+// --------------------------------------- SDMMC_GPIO -------------------------------------------
+#define SDMMC_GPIO_GPI_Pos 0 /*!< SDMMC GPIO: GPI Position */
+#define SDMMC_GPIO_GPI_Msk (0x000000ffUL << SDMMC_GPIO_GPI_Pos) /*!< SDMMC GPIO: GPI Mask */
+#define SDMMC_GPIO_GPO_Pos 8 /*!< SDMMC GPIO: GPO Position */
+#define SDMMC_GPIO_GPO_Msk (0x0000ffffUL << SDMMC_GPIO_GPO_Pos) /*!< SDMMC GPIO: GPO Mask */
+
+// -------------------------------------- SDMMC_TCBCNT ------------------------------------------
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos) /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */
+
+// -------------------------------------- SDMMC_TBBCNT ------------------------------------------
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos) /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */
+
+// -------------------------------------- SDMMC_DEBNCE ------------------------------------------
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */
+
+// --------------------------------------- SDMMC_USRID ------------------------------------------
+#define SDMMC_USRID_USRID_Pos 0 /*!< SDMMC USRID: USRID Position */
+#define SDMMC_USRID_USRID_Msk (0xffffffffUL << SDMMC_USRID_USRID_Pos) /*!< SDMMC USRID: USRID Mask */
+
+// --------------------------------------- SDMMC_VERID ------------------------------------------
+#define SDMMC_VERID_VERID_Pos 0 /*!< SDMMC VERID: VERID Position */
+#define SDMMC_VERID_VERID_Msk (0xffffffffUL << SDMMC_VERID_VERID_Pos) /*!< SDMMC VERID: VERID Mask */
+
+// -------------------------------------- SDMMC_UHS_REG -----------------------------------------
+#define SDMMC_UHS_REG_VOLT_REG_Pos 0 /*!< SDMMC UHS_REG: VOLT_REG Position */
+#define SDMMC_UHS_REG_VOLT_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos) /*!< SDMMC UHS_REG: VOLT_REG Mask */
+#define SDMMC_UHS_REG_DDR_REG_Pos 16 /*!< SDMMC UHS_REG: DDR_REG Position */
+#define SDMMC_UHS_REG_DDR_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos) /*!< SDMMC UHS_REG: DDR_REG Mask */
+
+// --------------------------------------- SDMMC_RST_N ------------------------------------------
+#define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */
+#define SDMMC_RST_N_CARD_RESET_Msk (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */
+
+// --------------------------------------- SDMMC_BMOD -------------------------------------------
+#define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */
+#define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */
+#define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */
+#define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */
+#define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */
+#define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */
+#define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */
+#define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */
+#define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */
+#define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */
+
+// -------------------------------------- SDMMC_PLDMND ------------------------------------------
+#define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */
+#define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */
+
+// -------------------------------------- SDMMC_DBADDR ------------------------------------------
+#define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */
+#define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */
+
+// --------------------------------------- SDMMC_IDSTS ------------------------------------------
+#define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */
+#define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */
+#define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */
+#define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */
+#define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */
+#define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */
+#define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */
+#define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */
+#define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */
+#define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */
+#define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */
+#define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */
+#define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */
+#define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */
+#define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */
+#define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */
+#define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */
+#define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */
+
+// -------------------------------------- SDMMC_IDINTEN -----------------------------------------
+#define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */
+#define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */
+#define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */
+#define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */
+#define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */
+#define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */
+#define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */
+#define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */
+#define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */
+#define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */
+#define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */
+#define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */
+#define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */
+#define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */
+
+// -------------------------------------- SDMMC_DSCADDR -----------------------------------------
+#define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */
+#define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */
+
+// -------------------------------------- SDMMC_BUFADDR -----------------------------------------
+#define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */
+#define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EMC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- EMC_CONTROL ------------------------------------------
+#define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */
+#define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */
+#define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */
+#define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */
+#define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */
+#define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */
+
+// --------------------------------------- EMC_STATUS -------------------------------------------
+#define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */
+#define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */
+#define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */
+#define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */
+#define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */
+#define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */
+
+// --------------------------------------- EMC_CONFIG -------------------------------------------
+#define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */
+#define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */
+#define EMC_CONFIG_CR_Pos 8 /*!< EMC CONFIG: CR Position */
+#define EMC_CONFIG_CR_Msk (0x01UL << EMC_CONFIG_CR_Pos) /*!< EMC CONFIG: CR Mask */
+
+// ----------------------------------- EMC_DYNAMICCONTROL ---------------------------------------
+#define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */
+#define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */
+#define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */
+#define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */
+#define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */
+#define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */
+#define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */
+#define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */
+#define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */
+#define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */
+#define EMC_DYNAMICCONTROL_DP_Pos 13 /*!< EMC DYNAMICCONTROL: DP Position */
+#define EMC_DYNAMICCONTROL_DP_Msk (0x01UL << EMC_DYNAMICCONTROL_DP_Pos) /*!< EMC DYNAMICCONTROL: DP Mask */
+
+// ----------------------------------- EMC_DYNAMICREFRESH ---------------------------------------
+#define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */
+#define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */
+
+// ---------------------------------- EMC_DYNAMICREADCONFIG -------------------------------------
+#define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */
+#define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */
+
+// -------------------------------------- EMC_DYNAMICRP -----------------------------------------
+#define EMC_DYNAMICRP_tRP_Pos 0 /*!< EMC DYNAMICRP: tRP Position */
+#define EMC_DYNAMICRP_tRP_Msk (0x0fUL << EMC_DYNAMICRP_tRP_Pos) /*!< EMC DYNAMICRP: tRP Mask */
+
+// ------------------------------------- EMC_DYNAMICRAS -----------------------------------------
+#define EMC_DYNAMICRAS_tRAS_Pos 0 /*!< EMC DYNAMICRAS: tRAS Position */
+#define EMC_DYNAMICRAS_tRAS_Msk (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos) /*!< EMC DYNAMICRAS: tRAS Mask */
+
+// ------------------------------------- EMC_DYNAMICSREX ----------------------------------------
+#define EMC_DYNAMICSREX_tSREX_Pos 0 /*!< EMC DYNAMICSREX: tSREX Position */
+#define EMC_DYNAMICSREX_tSREX_Msk (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos) /*!< EMC DYNAMICSREX: tSREX Mask */
+
+// ------------------------------------- EMC_DYNAMICAPR -----------------------------------------
+#define EMC_DYNAMICAPR_tAPR_Pos 0 /*!< EMC DYNAMICAPR: tAPR Position */
+#define EMC_DYNAMICAPR_tAPR_Msk (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos) /*!< EMC DYNAMICAPR: tAPR Mask */
+
+// ------------------------------------- EMC_DYNAMICDAL -----------------------------------------
+#define EMC_DYNAMICDAL_tDAL_Pos 0 /*!< EMC DYNAMICDAL: tDAL Position */
+#define EMC_DYNAMICDAL_tDAL_Msk (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos) /*!< EMC DYNAMICDAL: tDAL Mask */
+
+// -------------------------------------- EMC_DYNAMICWR -----------------------------------------
+#define EMC_DYNAMICWR_tWR_Pos 0 /*!< EMC DYNAMICWR: tWR Position */
+#define EMC_DYNAMICWR_tWR_Msk (0x0fUL << EMC_DYNAMICWR_tWR_Pos) /*!< EMC DYNAMICWR: tWR Mask */
+
+// -------------------------------------- EMC_DYNAMICRC -----------------------------------------
+#define EMC_DYNAMICRC_tRC_Pos 0 /*!< EMC DYNAMICRC: tRC Position */
+#define EMC_DYNAMICRC_tRC_Msk (0x1fUL << EMC_DYNAMICRC_tRC_Pos) /*!< EMC DYNAMICRC: tRC Mask */
+
+// ------------------------------------- EMC_DYNAMICRFC -----------------------------------------
+#define EMC_DYNAMICRFC_tRFC_Pos 0 /*!< EMC DYNAMICRFC: tRFC Position */
+#define EMC_DYNAMICRFC_tRFC_Msk (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos) /*!< EMC DYNAMICRFC: tRFC Mask */
+
+// ------------------------------------- EMC_DYNAMICXSR -----------------------------------------
+#define EMC_DYNAMICXSR_tXSR_Pos 0 /*!< EMC DYNAMICXSR: tXSR Position */
+#define EMC_DYNAMICXSR_tXSR_Msk (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos) /*!< EMC DYNAMICXSR: tXSR Mask */
+
+// ------------------------------------- EMC_DYNAMICRRD -----------------------------------------
+#define EMC_DYNAMICRRD_tRRD_Pos 0 /*!< EMC DYNAMICRRD: tRRD Position */
+#define EMC_DYNAMICRRD_tRRD_Msk (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos) /*!< EMC DYNAMICRRD: tRRD Mask */
+
+// ------------------------------------- EMC_DYNAMICMRD -----------------------------------------
+#define EMC_DYNAMICMRD_tMRD_Pos 0 /*!< EMC DYNAMICMRD: tMRD Position */
+#define EMC_DYNAMICMRD_tMRD_Msk (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos) /*!< EMC DYNAMICMRD: tMRD Mask */
+
+// --------------------------------- EMC_STATICEXTENDEDWAIT -------------------------------------
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG0 ---------------------------------------
+#define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */
+#define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */
+#define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */
+#define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */
+#define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */
+#define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */
+#define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */
+#define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */
+#define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */
+#define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS0 ---------------------------------------
+#define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */
+#define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */
+#define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */
+#define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG1 ---------------------------------------
+#define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */
+#define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */
+#define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */
+#define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */
+#define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */
+#define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */
+#define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */
+#define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */
+#define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */
+#define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS1 ---------------------------------------
+#define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */
+#define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */
+#define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */
+#define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG2 ---------------------------------------
+#define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */
+#define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */
+#define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */
+#define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */
+#define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */
+#define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */
+#define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */
+#define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */
+#define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */
+#define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS2 ---------------------------------------
+#define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */
+#define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */
+#define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */
+#define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG3 ---------------------------------------
+#define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */
+#define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */
+#define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */
+#define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */
+#define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */
+#define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */
+#define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */
+#define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */
+#define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */
+#define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS3 ---------------------------------------
+#define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */
+#define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */
+#define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */
+#define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */
+
+// ------------------------------------ EMC_STATICCONFIG0 ---------------------------------------
+#define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */
+#define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */
+#define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */
+#define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */
+#define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */
+#define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */
+#define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */
+#define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */
+#define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */
+#define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */
+#define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */
+#define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */
+#define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */
+#define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN0 ---------------------------------------
+#define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */
+#define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN0 ---------------------------------------
+#define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */
+#define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD0 ---------------------------------------
+#define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */
+#define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG0 ---------------------------------------
+#define EMC_STATICWAITPAG0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG0: WAITPAGE Position */
+#define EMC_STATICWAITPAG0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos) /*!< EMC STATICWAITPAG0: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR0 ---------------------------------------
+#define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */
+#define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN0 --------------------------------------
+#define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */
+#define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */
+
+// ------------------------------------ EMC_STATICCONFIG1 ---------------------------------------
+#define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */
+#define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */
+#define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */
+#define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */
+#define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */
+#define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */
+#define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */
+#define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */
+#define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */
+#define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */
+#define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */
+#define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */
+#define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */
+#define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN1 ---------------------------------------
+#define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */
+#define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN1 ---------------------------------------
+#define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */
+#define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD1 ---------------------------------------
+#define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */
+#define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG1 ---------------------------------------
+#define EMC_STATICWAITPAG1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG1: WAITPAGE Position */
+#define EMC_STATICWAITPAG1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos) /*!< EMC STATICWAITPAG1: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR1 ---------------------------------------
+#define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */
+#define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN1 --------------------------------------
+#define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */
+#define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */
+
+// ------------------------------------ EMC_STATICCONFIG2 ---------------------------------------
+#define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */
+#define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */
+#define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */
+#define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */
+#define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */
+#define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */
+#define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */
+#define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */
+#define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */
+#define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */
+#define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */
+#define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */
+#define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */
+#define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN2 ---------------------------------------
+#define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */
+#define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN2 ---------------------------------------
+#define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */
+#define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD2 ---------------------------------------
+#define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */
+#define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG2 ---------------------------------------
+#define EMC_STATICWAITPAG2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG2: WAITPAGE Position */
+#define EMC_STATICWAITPAG2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos) /*!< EMC STATICWAITPAG2: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR2 ---------------------------------------
+#define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */
+#define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN2 --------------------------------------
+#define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */
+#define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */
+
+// ------------------------------------ EMC_STATICCONFIG3 ---------------------------------------
+#define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */
+#define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */
+#define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */
+#define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */
+#define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */
+#define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */
+#define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */
+#define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */
+#define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */
+#define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */
+#define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */
+#define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */
+#define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */
+#define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN3 ---------------------------------------
+#define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */
+#define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN3 ---------------------------------------
+#define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */
+#define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD3 ---------------------------------------
+#define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */
+#define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG3 ---------------------------------------
+#define EMC_STATICWAITPAG3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG3: WAITPAGE Position */
+#define EMC_STATICWAITPAG3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos) /*!< EMC STATICWAITPAG3: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR3 ---------------------------------------
+#define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */
+#define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN3 --------------------------------------
+#define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */
+#define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- USB0_CAPLENGTH -----------------------------------------
+#define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */
+#define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */
+#define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */
+#define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */
+
+// ------------------------------------- USB0_HCSPARAMS -----------------------------------------
+#define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */
+#define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */
+#define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */
+#define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */
+#define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */
+#define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */
+#define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */
+#define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */
+#define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */
+#define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */
+#define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */
+#define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */
+#define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */
+#define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */
+
+// ------------------------------------- USB0_HCCPARAMS -----------------------------------------
+#define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */
+#define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */
+#define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */
+#define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */
+#define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */
+#define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */
+#define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */
+#define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */
+#define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */
+#define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */
+
+// ------------------------------------- USB0_DCIVERSION ----------------------------------------
+#define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */
+#define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */
+
+// -------------------------------------- USB0_USBCMD_D -----------------------------------------
+#define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */
+#define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */
+#define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */
+#define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */
+#define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */
+#define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */
+#define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */
+#define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */
+#define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */
+#define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */
+
+// -------------------------------------- USB0_USBCMD_H -----------------------------------------
+#define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */
+#define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */
+#define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */
+#define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */
+#define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */
+#define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */
+#define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */
+#define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */
+#define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */
+#define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */
+#define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */
+#define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */
+#define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */
+#define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */
+#define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */
+#define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */
+#define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */
+#define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */
+#define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */
+#define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */
+#define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */
+#define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */
+
+// -------------------------------------- USB0_USBSTS_D -----------------------------------------
+#define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */
+#define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */
+#define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */
+#define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */
+#define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */
+#define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */
+#define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */
+#define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */
+#define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */
+#define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */
+#define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */
+#define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */
+#define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */
+#define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */
+#define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */
+#define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */
+
+// -------------------------------------- USB0_USBSTS_H -----------------------------------------
+#define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */
+#define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */
+#define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */
+#define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */
+#define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */
+#define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */
+#define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */
+#define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */
+#define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */
+#define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */
+#define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */
+#define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */
+#define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */
+#define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */
+#define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */
+#define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */
+#define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */
+#define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */
+#define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */
+#define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */
+#define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */
+#define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */
+#define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */
+#define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */
+
+// ------------------------------------- USB0_USBINTR_D -----------------------------------------
+#define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */
+#define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */
+#define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */
+#define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */
+#define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */
+#define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */
+#define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */
+#define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */
+#define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */
+#define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */
+#define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */
+#define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */
+#define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */
+#define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */
+
+// ------------------------------------- USB0_USBINTR_H -----------------------------------------
+#define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */
+#define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */
+#define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */
+#define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */
+#define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */
+#define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */
+#define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */
+#define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */
+#define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */
+#define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */
+#define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */
+#define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */
+#define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */
+#define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */
+#define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */
+#define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */
+
+// ------------------------------------- USB0_FRINDEX_D -----------------------------------------
+#define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */
+#define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */
+#define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */
+#define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */
+
+// ------------------------------------- USB0_FRINDEX_H -----------------------------------------
+#define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */
+#define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */
+#define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */
+#define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */
+
+// ------------------------------------- USB0_DEVICEADDR ----------------------------------------
+#define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */
+#define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */
+#define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */
+#define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */
+
+// ---------------------------------- USB0_PERIODICLISTBASE -------------------------------------
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ---------------------------------- USB0_ENDPOINTLISTADDR -------------------------------------
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// ----------------------------------- USB0_ASYNCLISTADDR ---------------------------------------
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// --------------------------------------- USB0_TTCTRL ------------------------------------------
+#define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */
+#define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */
+
+// ------------------------------------- USB0_BURSTSIZE -----------------------------------------
+#define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */
+#define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */
+#define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */
+#define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */
+
+// ------------------------------------ USB0_TXFILLTUNING ---------------------------------------
+#define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */
+#define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// ------------------------------------- USB0_BINTERVAL -----------------------------------------
+#define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */
+#define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */
+
+// -------------------------------------- USB0_ENDPTNAK -----------------------------------------
+#define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */
+#define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */
+#define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */
+#define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */
+#define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */
+#define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */
+#define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */
+#define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */
+#define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */
+#define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */
+#define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */
+#define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */
+#define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */
+#define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */
+#define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */
+#define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */
+#define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */
+#define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */
+#define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */
+#define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */
+#define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */
+#define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */
+#define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */
+#define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */
+
+// ------------------------------------- USB0_ENDPTNAKEN ----------------------------------------
+#define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */
+#define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */
+#define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */
+#define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */
+#define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */
+#define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */
+#define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */
+#define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */
+#define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */
+#define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */
+#define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */
+#define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */
+#define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */
+#define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */
+#define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */
+#define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */
+#define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */
+#define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */
+#define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */
+#define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */
+#define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */
+#define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */
+#define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */
+#define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */
+
+// ------------------------------------- USB0_PORTSC1_D -----------------------------------------
+#define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */
+#define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */
+#define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */
+#define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */
+#define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */
+#define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */
+#define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */
+#define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */
+#define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */
+#define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */
+#define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */
+#define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */
+#define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */
+#define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */
+#define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */
+#define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */
+#define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */
+#define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */
+#define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */
+#define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */
+#define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */
+#define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */
+#define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */
+#define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */
+
+// ------------------------------------- USB0_PORTSC1_H -----------------------------------------
+#define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */
+#define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */
+#define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */
+#define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */
+#define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */
+#define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */
+#define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */
+#define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */
+#define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */
+#define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */
+#define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */
+#define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */
+#define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */
+#define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */
+#define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */
+#define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */
+#define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */
+#define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */
+#define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */
+#define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */
+#define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */
+#define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */
+#define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */
+#define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */
+#define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */
+#define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */
+#define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */
+#define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */
+#define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */
+#define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */
+#define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */
+#define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */
+#define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */
+#define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */
+#define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */
+#define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */
+#define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */
+#define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */
+#define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */
+#define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */
+
+// --------------------------------------- USB0_OTGSC -------------------------------------------
+#define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */
+#define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */
+#define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */
+#define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */
+#define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */
+#define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */
+#define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */
+#define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */
+#define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */
+#define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */
+#define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */
+#define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */
+#define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */
+#define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */
+#define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */
+#define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */
+#define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */
+#define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */
+#define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */
+#define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */
+#define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */
+#define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */
+#define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */
+#define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */
+#define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */
+#define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */
+#define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */
+#define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */
+#define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */
+#define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */
+#define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */
+#define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */
+#define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */
+#define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */
+#define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */
+#define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */
+#define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */
+#define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */
+#define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */
+#define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */
+#define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */
+#define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */
+#define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */
+#define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */
+#define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */
+#define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */
+#define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */
+#define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */
+#define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */
+#define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */
+#define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */
+#define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */
+#define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */
+#define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */
+#define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */
+#define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */
+#define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */
+#define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */
+
+// ------------------------------------- USB0_USBMODE_D -----------------------------------------
+#define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */
+#define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */
+#define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */
+#define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */
+#define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */
+#define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */
+#define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */
+#define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */
+
+// ------------------------------------- USB0_USBMODE_H -----------------------------------------
+#define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */
+#define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */
+#define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */
+#define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */
+#define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */
+#define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */
+#define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */
+#define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */
+
+// ----------------------------------- USB0_ENDPTSETUPSTAT --------------------------------------
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */
+
+// ------------------------------------- USB0_ENDPTPRIME ----------------------------------------
+#define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */
+#define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */
+#define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */
+#define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */
+#define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */
+#define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */
+#define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */
+#define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */
+#define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */
+#define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */
+#define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */
+#define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */
+#define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */
+#define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */
+#define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */
+#define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */
+#define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */
+#define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */
+#define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */
+#define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */
+#define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */
+#define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */
+#define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */
+#define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */
+
+// ------------------------------------- USB0_ENDPTFLUSH ----------------------------------------
+#define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */
+#define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */
+#define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */
+#define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */
+#define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */
+#define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */
+#define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */
+#define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */
+#define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */
+#define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */
+#define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */
+#define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */
+#define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */
+#define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */
+#define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */
+#define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */
+#define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */
+#define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */
+#define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */
+#define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */
+#define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */
+#define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */
+#define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */
+#define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */
+
+// ------------------------------------- USB0_ENDPTSTAT -----------------------------------------
+#define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */
+#define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */
+#define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */
+#define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */
+#define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */
+#define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */
+#define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */
+#define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */
+#define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */
+#define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */
+#define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */
+#define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */
+#define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */
+#define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */
+#define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */
+#define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */
+#define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */
+#define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */
+#define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */
+#define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */
+#define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */
+#define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */
+#define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */
+#define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */
+
+// ----------------------------------- USB0_ENDPTCOMPLETE ---------------------------------------
+#define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */
+#define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */
+#define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */
+#define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */
+#define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */
+#define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */
+#define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */
+#define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */
+#define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */
+#define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */
+#define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */
+#define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */
+#define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL0 ----------------------------------------
+#define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */
+#define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */
+#define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */
+#define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */
+#define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */
+#define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */
+#define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */
+#define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */
+#define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */
+#define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */
+#define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */
+#define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL1 ----------------------------------------
+#define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */
+#define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */
+#define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */
+#define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */
+#define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */
+#define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */
+#define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */
+#define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */
+#define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */
+#define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */
+#define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */
+#define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */
+#define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */
+#define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */
+#define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */
+#define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */
+#define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */
+#define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */
+#define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */
+#define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL2 ----------------------------------------
+#define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */
+#define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */
+#define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */
+#define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */
+#define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */
+#define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */
+#define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */
+#define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */
+#define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */
+#define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */
+#define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */
+#define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */
+#define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */
+#define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */
+#define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */
+#define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */
+#define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */
+#define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */
+#define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */
+#define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL3 ----------------------------------------
+#define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */
+#define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */
+#define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */
+#define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */
+#define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */
+#define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */
+#define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */
+#define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */
+#define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */
+#define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */
+#define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */
+#define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */
+#define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */
+#define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */
+#define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */
+#define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */
+#define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */
+#define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */
+#define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */
+#define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL4 ----------------------------------------
+#define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */
+#define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */
+#define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */
+#define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */
+#define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */
+#define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */
+#define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */
+#define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */
+#define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */
+#define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */
+#define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */
+#define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */
+#define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */
+#define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */
+#define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */
+#define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */
+#define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */
+#define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */
+#define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */
+#define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL5 ----------------------------------------
+#define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */
+#define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */
+#define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */
+#define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */
+#define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */
+#define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */
+#define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */
+#define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */
+#define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */
+#define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */
+#define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */
+#define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */
+#define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */
+#define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */
+#define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */
+#define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */
+#define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */
+#define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */
+#define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */
+#define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- USB1_CAPLENGTH -----------------------------------------
+#define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */
+#define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */
+#define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */
+#define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */
+
+// ------------------------------------- USB1_HCSPARAMS -----------------------------------------
+#define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */
+#define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */
+#define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */
+#define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */
+#define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */
+#define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */
+#define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */
+#define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */
+#define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */
+#define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */
+#define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */
+#define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */
+#define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */
+#define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */
+
+// ------------------------------------- USB1_HCCPARAMS -----------------------------------------
+#define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */
+#define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */
+#define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */
+#define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */
+#define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */
+#define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */
+#define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */
+#define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */
+#define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */
+#define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */
+
+// ------------------------------------- USB1_DCIVERSION ----------------------------------------
+#define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */
+#define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */
+
+// -------------------------------------- USB1_USBCMD_D -----------------------------------------
+#define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */
+#define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */
+#define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */
+#define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */
+#define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */
+#define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */
+#define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */
+#define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */
+#define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */
+#define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */
+#define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */
+#define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */
+
+// -------------------------------------- USB1_USBCMD_H -----------------------------------------
+#define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */
+#define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */
+#define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */
+#define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */
+#define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */
+#define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */
+#define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */
+#define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */
+#define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */
+#define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */
+#define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */
+#define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */
+#define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */
+#define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */
+#define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */
+#define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */
+#define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */
+#define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */
+#define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */
+#define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */
+#define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */
+#define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */
+
+// -------------------------------------- USB1_USBSTS_D -----------------------------------------
+#define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */
+#define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */
+#define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */
+#define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */
+#define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */
+#define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */
+#define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */
+#define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */
+#define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */
+#define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */
+#define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */
+#define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */
+#define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */
+#define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */
+
+// -------------------------------------- USB1_USBSTS_H -----------------------------------------
+#define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */
+#define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */
+#define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */
+#define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */
+#define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */
+#define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */
+#define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */
+#define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */
+#define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */
+#define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */
+#define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */
+#define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */
+#define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */
+#define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */
+#define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */
+#define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */
+#define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */
+#define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */
+#define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */
+#define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */
+#define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */
+#define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */
+#define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */
+#define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */
+#define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */
+#define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */
+
+// ------------------------------------- USB1_USBINTR_D -----------------------------------------
+#define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */
+#define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */
+#define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */
+#define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */
+#define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */
+#define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */
+#define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */
+#define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */
+#define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */
+#define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */
+#define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */
+#define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */
+#define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */
+#define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */
+#define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */
+#define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */
+#define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */
+#define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */
+
+// ------------------------------------- USB1_USBINTR_H -----------------------------------------
+#define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */
+#define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */
+#define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */
+#define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */
+#define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */
+#define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */
+#define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */
+#define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */
+#define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */
+#define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */
+#define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */
+#define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */
+#define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */
+#define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */
+#define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */
+#define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */
+
+// ------------------------------------- USB1_FRINDEX_D -----------------------------------------
+#define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */
+#define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */
+#define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */
+#define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */
+
+// ------------------------------------- USB1_FRINDEX_H -----------------------------------------
+#define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */
+#define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */
+#define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */
+#define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */
+
+// ------------------------------------- USB1_DEVICEADDR ----------------------------------------
+#define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */
+#define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */
+#define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */
+#define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */
+
+// ---------------------------------- USB1_PERIODICLISTBASE -------------------------------------
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ---------------------------------- USB1_ENDPOINTLISTADDR -------------------------------------
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// ----------------------------------- USB1_ASYNCLISTADDR ---------------------------------------
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// --------------------------------------- USB1_TTCTRL ------------------------------------------
+#define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */
+#define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */
+
+// ------------------------------------- USB1_BURSTSIZE -----------------------------------------
+#define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */
+#define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */
+#define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */
+#define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */
+
+// ------------------------------------ USB1_TXFILLTUNING ---------------------------------------
+#define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */
+#define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// ------------------------------------ USB1_ULPIVIEWPORT ---------------------------------------
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */
+#define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */
+#define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */
+#define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */
+#define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */
+#define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */
+#define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */
+
+// ------------------------------------- USB1_BINTERVAL -----------------------------------------
+#define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */
+#define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */
+
+// -------------------------------------- USB1_ENDPTNAK -----------------------------------------
+#define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */
+#define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */
+#define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */
+#define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */
+#define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */
+#define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */
+#define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */
+#define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */
+#define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */
+#define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */
+#define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */
+#define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */
+#define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */
+#define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */
+#define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */
+#define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */
+
+// ------------------------------------- USB1_ENDPTNAKEN ----------------------------------------
+#define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */
+#define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */
+#define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */
+#define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */
+#define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */
+#define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */
+#define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */
+#define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */
+#define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */
+#define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */
+#define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */
+#define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */
+#define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */
+#define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */
+#define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */
+#define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */
+
+// ------------------------------------- USB1_PORTSC1_D -----------------------------------------
+#define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */
+#define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */
+#define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */
+#define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */
+#define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */
+#define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */
+#define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */
+#define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */
+#define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */
+#define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */
+#define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */
+#define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */
+#define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */
+#define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */
+#define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */
+#define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */
+#define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */
+#define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */
+#define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */
+#define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */
+#define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */
+#define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */
+#define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */
+#define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */
+#define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */
+#define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */
+#define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */
+#define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */
+#define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */
+#define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */
+#define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */
+#define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */
+
+// ------------------------------------- USB1_PORTSC1_H -----------------------------------------
+#define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */
+#define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */
+#define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */
+#define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */
+#define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */
+#define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */
+#define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */
+#define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */
+#define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */
+#define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */
+#define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */
+#define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */
+#define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */
+#define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */
+#define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */
+#define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */
+#define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */
+#define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */
+#define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */
+#define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */
+#define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */
+#define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */
+#define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */
+#define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */
+#define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */
+#define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */
+#define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */
+#define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */
+#define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */
+#define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */
+#define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */
+#define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */
+#define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */
+#define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */
+#define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */
+#define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */
+#define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */
+#define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */
+#define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */
+#define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */
+#define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */
+#define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */
+
+// ------------------------------------- USB1_USBMODE_D -----------------------------------------
+#define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */
+#define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */
+#define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */
+#define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */
+#define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */
+#define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */
+#define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */
+#define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */
+
+// ------------------------------------- USB1_USBMODE_H -----------------------------------------
+#define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */
+#define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */
+#define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */
+#define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */
+#define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */
+#define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */
+#define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */
+#define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */
+
+// ----------------------------------- USB1_ENDPTSETUPSTAT --------------------------------------
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+
+// ------------------------------------- USB1_ENDPTPRIME ----------------------------------------
+#define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */
+#define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */
+#define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */
+#define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */
+#define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */
+#define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */
+#define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */
+#define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */
+#define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */
+#define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */
+#define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */
+#define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */
+#define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */
+#define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */
+#define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */
+#define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */
+
+// ------------------------------------- USB1_ENDPTFLUSH ----------------------------------------
+#define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */
+#define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */
+#define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */
+#define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */
+#define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */
+#define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */
+#define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */
+#define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */
+#define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */
+#define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */
+#define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */
+#define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */
+#define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */
+#define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */
+#define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */
+#define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */
+
+// ------------------------------------- USB1_ENDPTSTAT -----------------------------------------
+#define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */
+#define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */
+#define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */
+#define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */
+#define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */
+#define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */
+#define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */
+#define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */
+#define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */
+#define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */
+#define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */
+#define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */
+#define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */
+#define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */
+#define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */
+#define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */
+
+// ----------------------------------- USB1_ENDPTCOMPLETE ---------------------------------------
+#define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */
+#define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */
+#define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */
+#define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */
+#define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */
+#define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */
+#define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */
+#define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */
+#define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */
+#define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */
+#define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */
+#define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL0 ----------------------------------------
+#define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */
+#define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */
+#define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */
+#define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */
+#define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */
+#define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */
+#define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */
+#define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */
+#define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */
+#define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */
+#define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */
+#define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL1 ----------------------------------------
+#define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */
+#define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */
+#define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */
+#define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */
+#define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */
+#define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */
+#define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */
+#define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */
+#define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */
+#define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */
+#define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */
+#define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */
+#define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */
+#define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */
+#define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */
+#define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */
+#define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */
+#define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */
+#define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */
+#define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL2 ----------------------------------------
+#define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */
+#define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */
+#define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */
+#define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */
+#define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */
+#define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */
+#define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */
+#define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */
+#define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */
+#define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */
+#define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */
+#define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */
+#define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */
+#define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */
+#define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */
+#define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */
+#define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */
+#define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */
+#define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */
+#define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL3 ----------------------------------------
+#define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */
+#define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */
+#define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */
+#define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */
+#define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */
+#define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */
+#define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */
+#define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */
+#define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */
+#define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */
+#define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */
+#define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */
+#define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */
+#define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */
+#define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */
+#define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */
+#define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */
+#define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */
+#define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */
+#define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- LCD Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- LCD_TIMH --------------------------------------------
+#define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */
+#define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */
+#define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */
+#define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */
+#define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */
+#define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */
+#define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */
+#define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */
+
+// ---------------------------------------- LCD_TIMV --------------------------------------------
+#define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */
+#define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */
+#define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */
+#define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */
+#define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */
+#define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */
+#define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */
+#define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */
+
+// ----------------------------------------- LCD_POL --------------------------------------------
+#define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */
+#define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */
+#define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */
+#define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */
+#define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */
+#define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */
+#define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */
+#define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */
+#define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */
+#define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */
+#define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */
+#define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */
+#define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */
+#define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */
+#define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */
+#define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */
+#define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */
+#define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */
+#define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */
+#define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */
+
+// ----------------------------------------- LCD_LE ---------------------------------------------
+#define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */
+#define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */
+#define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */
+#define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */
+
+// --------------------------------------- LCD_UPBASE -------------------------------------------
+#define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */
+#define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */
+
+// --------------------------------------- LCD_LPBASE -------------------------------------------
+#define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */
+#define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */
+
+// ---------------------------------------- LCD_CTRL --------------------------------------------
+#define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */
+#define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */
+#define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */
+#define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */
+#define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */
+#define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */
+#define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */
+#define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */
+#define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */
+#define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */
+#define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */
+#define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */
+#define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */
+#define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */
+#define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */
+#define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */
+#define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */
+#define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */
+#define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */
+#define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */
+#define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */
+#define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */
+#define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */
+#define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */
+
+// --------------------------------------- LCD_INTMSK -------------------------------------------
+#define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */
+#define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */
+#define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */
+#define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */
+#define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */
+#define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */
+#define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */
+#define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */
+
+// --------------------------------------- LCD_INTRAW -------------------------------------------
+#define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */
+#define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */
+#define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */
+#define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */
+#define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */
+#define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */
+#define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */
+#define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */
+
+// --------------------------------------- LCD_INTSTAT ------------------------------------------
+#define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */
+#define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */
+#define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */
+#define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */
+#define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */
+#define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */
+#define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */
+#define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */
+
+// --------------------------------------- LCD_INTCLR -------------------------------------------
+#define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */
+#define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */
+#define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */
+#define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */
+#define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */
+#define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */
+#define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */
+#define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */
+
+// --------------------------------------- LCD_UPCURR -------------------------------------------
+#define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */
+#define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */
+
+// --------------------------------------- LCD_LPCURR -------------------------------------------
+#define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */
+#define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */
+
+// ---------------------------------------- LCD_PAL0 --------------------------------------------
+#define LCD_PAL0_R04_0_Pos 0 /*!< LCD PAL0: R04_0 Position */
+#define LCD_PAL0_R04_0_Msk (0x1fUL << LCD_PAL0_R04_0_Pos) /*!< LCD PAL0: R04_0 Mask */
+#define LCD_PAL0_G04_0_Pos 5 /*!< LCD PAL0: G04_0 Position */
+#define LCD_PAL0_G04_0_Msk (0x1fUL << LCD_PAL0_G04_0_Pos) /*!< LCD PAL0: G04_0 Mask */
+#define LCD_PAL0_B04_0_Pos 10 /*!< LCD PAL0: B04_0 Position */
+#define LCD_PAL0_B04_0_Msk (0x1fUL << LCD_PAL0_B04_0_Pos) /*!< LCD PAL0: B04_0 Mask */
+#define LCD_PAL0_I0_Pos 15 /*!< LCD PAL0: I0 Position */
+#define LCD_PAL0_I0_Msk (0x01UL << LCD_PAL0_I0_Pos) /*!< LCD PAL0: I0 Mask */
+#define LCD_PAL0_R14_0_Pos 16 /*!< LCD PAL0: R14_0 Position */
+#define LCD_PAL0_R14_0_Msk (0x1fUL << LCD_PAL0_R14_0_Pos) /*!< LCD PAL0: R14_0 Mask */
+#define LCD_PAL0_G14_0_Pos 21 /*!< LCD PAL0: G14_0 Position */
+#define LCD_PAL0_G14_0_Msk (0x1fUL << LCD_PAL0_G14_0_Pos) /*!< LCD PAL0: G14_0 Mask */
+#define LCD_PAL0_B14_0_Pos 26 /*!< LCD PAL0: B14_0 Position */
+#define LCD_PAL0_B14_0_Msk (0x1fUL << LCD_PAL0_B14_0_Pos) /*!< LCD PAL0: B14_0 Mask */
+#define LCD_PAL0_I1_Pos 31 /*!< LCD PAL0: I1 Position */
+#define LCD_PAL0_I1_Msk (0x01UL << LCD_PAL0_I1_Pos) /*!< LCD PAL0: I1 Mask */
+
+// ---------------------------------------- LCD_PAL1 --------------------------------------------
+#define LCD_PAL1_R04_0_Pos 0 /*!< LCD PAL1: R04_0 Position */
+#define LCD_PAL1_R04_0_Msk (0x1fUL << LCD_PAL1_R04_0_Pos) /*!< LCD PAL1: R04_0 Mask */
+#define LCD_PAL1_G04_0_Pos 5 /*!< LCD PAL1: G04_0 Position */
+#define LCD_PAL1_G04_0_Msk (0x1fUL << LCD_PAL1_G04_0_Pos) /*!< LCD PAL1: G04_0 Mask */
+#define LCD_PAL1_B04_0_Pos 10 /*!< LCD PAL1: B04_0 Position */
+#define LCD_PAL1_B04_0_Msk (0x1fUL << LCD_PAL1_B04_0_Pos) /*!< LCD PAL1: B04_0 Mask */
+#define LCD_PAL1_I0_Pos 15 /*!< LCD PAL1: I0 Position */
+#define LCD_PAL1_I0_Msk (0x01UL << LCD_PAL1_I0_Pos) /*!< LCD PAL1: I0 Mask */
+#define LCD_PAL1_R14_0_Pos 16 /*!< LCD PAL1: R14_0 Position */
+#define LCD_PAL1_R14_0_Msk (0x1fUL << LCD_PAL1_R14_0_Pos) /*!< LCD PAL1: R14_0 Mask */
+#define LCD_PAL1_G14_0_Pos 21 /*!< LCD PAL1: G14_0 Position */
+#define LCD_PAL1_G14_0_Msk (0x1fUL << LCD_PAL1_G14_0_Pos) /*!< LCD PAL1: G14_0 Mask */
+#define LCD_PAL1_B14_0_Pos 26 /*!< LCD PAL1: B14_0 Position */
+#define LCD_PAL1_B14_0_Msk (0x1fUL << LCD_PAL1_B14_0_Pos) /*!< LCD PAL1: B14_0 Mask */
+#define LCD_PAL1_I1_Pos 31 /*!< LCD PAL1: I1 Position */
+#define LCD_PAL1_I1_Msk (0x01UL << LCD_PAL1_I1_Pos) /*!< LCD PAL1: I1 Mask */
+
+// ---------------------------------------- LCD_PAL2 --------------------------------------------
+#define LCD_PAL2_R04_0_Pos 0 /*!< LCD PAL2: R04_0 Position */
+#define LCD_PAL2_R04_0_Msk (0x1fUL << LCD_PAL2_R04_0_Pos) /*!< LCD PAL2: R04_0 Mask */
+#define LCD_PAL2_G04_0_Pos 5 /*!< LCD PAL2: G04_0 Position */
+#define LCD_PAL2_G04_0_Msk (0x1fUL << LCD_PAL2_G04_0_Pos) /*!< LCD PAL2: G04_0 Mask */
+#define LCD_PAL2_B04_0_Pos 10 /*!< LCD PAL2: B04_0 Position */
+#define LCD_PAL2_B04_0_Msk (0x1fUL << LCD_PAL2_B04_0_Pos) /*!< LCD PAL2: B04_0 Mask */
+#define LCD_PAL2_I0_Pos 15 /*!< LCD PAL2: I0 Position */
+#define LCD_PAL2_I0_Msk (0x01UL << LCD_PAL2_I0_Pos) /*!< LCD PAL2: I0 Mask */
+#define LCD_PAL2_R14_0_Pos 16 /*!< LCD PAL2: R14_0 Position */
+#define LCD_PAL2_R14_0_Msk (0x1fUL << LCD_PAL2_R14_0_Pos) /*!< LCD PAL2: R14_0 Mask */
+#define LCD_PAL2_G14_0_Pos 21 /*!< LCD PAL2: G14_0 Position */
+#define LCD_PAL2_G14_0_Msk (0x1fUL << LCD_PAL2_G14_0_Pos) /*!< LCD PAL2: G14_0 Mask */
+#define LCD_PAL2_B14_0_Pos 26 /*!< LCD PAL2: B14_0 Position */
+#define LCD_PAL2_B14_0_Msk (0x1fUL << LCD_PAL2_B14_0_Pos) /*!< LCD PAL2: B14_0 Mask */
+#define LCD_PAL2_I1_Pos 31 /*!< LCD PAL2: I1 Position */
+#define LCD_PAL2_I1_Msk (0x01UL << LCD_PAL2_I1_Pos) /*!< LCD PAL2: I1 Mask */
+
+// ---------------------------------------- LCD_PAL3 --------------------------------------------
+#define LCD_PAL3_R04_0_Pos 0 /*!< LCD PAL3: R04_0 Position */
+#define LCD_PAL3_R04_0_Msk (0x1fUL << LCD_PAL3_R04_0_Pos) /*!< LCD PAL3: R04_0 Mask */
+#define LCD_PAL3_G04_0_Pos 5 /*!< LCD PAL3: G04_0 Position */
+#define LCD_PAL3_G04_0_Msk (0x1fUL << LCD_PAL3_G04_0_Pos) /*!< LCD PAL3: G04_0 Mask */
+#define LCD_PAL3_B04_0_Pos 10 /*!< LCD PAL3: B04_0 Position */
+#define LCD_PAL3_B04_0_Msk (0x1fUL << LCD_PAL3_B04_0_Pos) /*!< LCD PAL3: B04_0 Mask */
+#define LCD_PAL3_I0_Pos 15 /*!< LCD PAL3: I0 Position */
+#define LCD_PAL3_I0_Msk (0x01UL << LCD_PAL3_I0_Pos) /*!< LCD PAL3: I0 Mask */
+#define LCD_PAL3_R14_0_Pos 16 /*!< LCD PAL3: R14_0 Position */
+#define LCD_PAL3_R14_0_Msk (0x1fUL << LCD_PAL3_R14_0_Pos) /*!< LCD PAL3: R14_0 Mask */
+#define LCD_PAL3_G14_0_Pos 21 /*!< LCD PAL3: G14_0 Position */
+#define LCD_PAL3_G14_0_Msk (0x1fUL << LCD_PAL3_G14_0_Pos) /*!< LCD PAL3: G14_0 Mask */
+#define LCD_PAL3_B14_0_Pos 26 /*!< LCD PAL3: B14_0 Position */
+#define LCD_PAL3_B14_0_Msk (0x1fUL << LCD_PAL3_B14_0_Pos) /*!< LCD PAL3: B14_0 Mask */
+#define LCD_PAL3_I1_Pos 31 /*!< LCD PAL3: I1 Position */
+#define LCD_PAL3_I1_Msk (0x01UL << LCD_PAL3_I1_Pos) /*!< LCD PAL3: I1 Mask */
+
+// ---------------------------------------- LCD_PAL4 --------------------------------------------
+#define LCD_PAL4_R04_0_Pos 0 /*!< LCD PAL4: R04_0 Position */
+#define LCD_PAL4_R04_0_Msk (0x1fUL << LCD_PAL4_R04_0_Pos) /*!< LCD PAL4: R04_0 Mask */
+#define LCD_PAL4_G04_0_Pos 5 /*!< LCD PAL4: G04_0 Position */
+#define LCD_PAL4_G04_0_Msk (0x1fUL << LCD_PAL4_G04_0_Pos) /*!< LCD PAL4: G04_0 Mask */
+#define LCD_PAL4_B04_0_Pos 10 /*!< LCD PAL4: B04_0 Position */
+#define LCD_PAL4_B04_0_Msk (0x1fUL << LCD_PAL4_B04_0_Pos) /*!< LCD PAL4: B04_0 Mask */
+#define LCD_PAL4_I0_Pos 15 /*!< LCD PAL4: I0 Position */
+#define LCD_PAL4_I0_Msk (0x01UL << LCD_PAL4_I0_Pos) /*!< LCD PAL4: I0 Mask */
+#define LCD_PAL4_R14_0_Pos 16 /*!< LCD PAL4: R14_0 Position */
+#define LCD_PAL4_R14_0_Msk (0x1fUL << LCD_PAL4_R14_0_Pos) /*!< LCD PAL4: R14_0 Mask */
+#define LCD_PAL4_G14_0_Pos 21 /*!< LCD PAL4: G14_0 Position */
+#define LCD_PAL4_G14_0_Msk (0x1fUL << LCD_PAL4_G14_0_Pos) /*!< LCD PAL4: G14_0 Mask */
+#define LCD_PAL4_B14_0_Pos 26 /*!< LCD PAL4: B14_0 Position */
+#define LCD_PAL4_B14_0_Msk (0x1fUL << LCD_PAL4_B14_0_Pos) /*!< LCD PAL4: B14_0 Mask */
+#define LCD_PAL4_I1_Pos 31 /*!< LCD PAL4: I1 Position */
+#define LCD_PAL4_I1_Msk (0x01UL << LCD_PAL4_I1_Pos) /*!< LCD PAL4: I1 Mask */
+
+// ---------------------------------------- LCD_PAL5 --------------------------------------------
+#define LCD_PAL5_R04_0_Pos 0 /*!< LCD PAL5: R04_0 Position */
+#define LCD_PAL5_R04_0_Msk (0x1fUL << LCD_PAL5_R04_0_Pos) /*!< LCD PAL5: R04_0 Mask */
+#define LCD_PAL5_G04_0_Pos 5 /*!< LCD PAL5: G04_0 Position */
+#define LCD_PAL5_G04_0_Msk (0x1fUL << LCD_PAL5_G04_0_Pos) /*!< LCD PAL5: G04_0 Mask */
+#define LCD_PAL5_B04_0_Pos 10 /*!< LCD PAL5: B04_0 Position */
+#define LCD_PAL5_B04_0_Msk (0x1fUL << LCD_PAL5_B04_0_Pos) /*!< LCD PAL5: B04_0 Mask */
+#define LCD_PAL5_I0_Pos 15 /*!< LCD PAL5: I0 Position */
+#define LCD_PAL5_I0_Msk (0x01UL << LCD_PAL5_I0_Pos) /*!< LCD PAL5: I0 Mask */
+#define LCD_PAL5_R14_0_Pos 16 /*!< LCD PAL5: R14_0 Position */
+#define LCD_PAL5_R14_0_Msk (0x1fUL << LCD_PAL5_R14_0_Pos) /*!< LCD PAL5: R14_0 Mask */
+#define LCD_PAL5_G14_0_Pos 21 /*!< LCD PAL5: G14_0 Position */
+#define LCD_PAL5_G14_0_Msk (0x1fUL << LCD_PAL5_G14_0_Pos) /*!< LCD PAL5: G14_0 Mask */
+#define LCD_PAL5_B14_0_Pos 26 /*!< LCD PAL5: B14_0 Position */
+#define LCD_PAL5_B14_0_Msk (0x1fUL << LCD_PAL5_B14_0_Pos) /*!< LCD PAL5: B14_0 Mask */
+#define LCD_PAL5_I1_Pos 31 /*!< LCD PAL5: I1 Position */
+#define LCD_PAL5_I1_Msk (0x01UL << LCD_PAL5_I1_Pos) /*!< LCD PAL5: I1 Mask */
+
+// ---------------------------------------- LCD_PAL6 --------------------------------------------
+#define LCD_PAL6_R04_0_Pos 0 /*!< LCD PAL6: R04_0 Position */
+#define LCD_PAL6_R04_0_Msk (0x1fUL << LCD_PAL6_R04_0_Pos) /*!< LCD PAL6: R04_0 Mask */
+#define LCD_PAL6_G04_0_Pos 5 /*!< LCD PAL6: G04_0 Position */
+#define LCD_PAL6_G04_0_Msk (0x1fUL << LCD_PAL6_G04_0_Pos) /*!< LCD PAL6: G04_0 Mask */
+#define LCD_PAL6_B04_0_Pos 10 /*!< LCD PAL6: B04_0 Position */
+#define LCD_PAL6_B04_0_Msk (0x1fUL << LCD_PAL6_B04_0_Pos) /*!< LCD PAL6: B04_0 Mask */
+#define LCD_PAL6_I0_Pos 15 /*!< LCD PAL6: I0 Position */
+#define LCD_PAL6_I0_Msk (0x01UL << LCD_PAL6_I0_Pos) /*!< LCD PAL6: I0 Mask */
+#define LCD_PAL6_R14_0_Pos 16 /*!< LCD PAL6: R14_0 Position */
+#define LCD_PAL6_R14_0_Msk (0x1fUL << LCD_PAL6_R14_0_Pos) /*!< LCD PAL6: R14_0 Mask */
+#define LCD_PAL6_G14_0_Pos 21 /*!< LCD PAL6: G14_0 Position */
+#define LCD_PAL6_G14_0_Msk (0x1fUL << LCD_PAL6_G14_0_Pos) /*!< LCD PAL6: G14_0 Mask */
+#define LCD_PAL6_B14_0_Pos 26 /*!< LCD PAL6: B14_0 Position */
+#define LCD_PAL6_B14_0_Msk (0x1fUL << LCD_PAL6_B14_0_Pos) /*!< LCD PAL6: B14_0 Mask */
+#define LCD_PAL6_I1_Pos 31 /*!< LCD PAL6: I1 Position */
+#define LCD_PAL6_I1_Msk (0x01UL << LCD_PAL6_I1_Pos) /*!< LCD PAL6: I1 Mask */
+
+// ---------------------------------------- LCD_PAL7 --------------------------------------------
+#define LCD_PAL7_R04_0_Pos 0 /*!< LCD PAL7: R04_0 Position */
+#define LCD_PAL7_R04_0_Msk (0x1fUL << LCD_PAL7_R04_0_Pos) /*!< LCD PAL7: R04_0 Mask */
+#define LCD_PAL7_G04_0_Pos 5 /*!< LCD PAL7: G04_0 Position */
+#define LCD_PAL7_G04_0_Msk (0x1fUL << LCD_PAL7_G04_0_Pos) /*!< LCD PAL7: G04_0 Mask */
+#define LCD_PAL7_B04_0_Pos 10 /*!< LCD PAL7: B04_0 Position */
+#define LCD_PAL7_B04_0_Msk (0x1fUL << LCD_PAL7_B04_0_Pos) /*!< LCD PAL7: B04_0 Mask */
+#define LCD_PAL7_I0_Pos 15 /*!< LCD PAL7: I0 Position */
+#define LCD_PAL7_I0_Msk (0x01UL << LCD_PAL7_I0_Pos) /*!< LCD PAL7: I0 Mask */
+#define LCD_PAL7_R14_0_Pos 16 /*!< LCD PAL7: R14_0 Position */
+#define LCD_PAL7_R14_0_Msk (0x1fUL << LCD_PAL7_R14_0_Pos) /*!< LCD PAL7: R14_0 Mask */
+#define LCD_PAL7_G14_0_Pos 21 /*!< LCD PAL7: G14_0 Position */
+#define LCD_PAL7_G14_0_Msk (0x1fUL << LCD_PAL7_G14_0_Pos) /*!< LCD PAL7: G14_0 Mask */
+#define LCD_PAL7_B14_0_Pos 26 /*!< LCD PAL7: B14_0 Position */
+#define LCD_PAL7_B14_0_Msk (0x1fUL << LCD_PAL7_B14_0_Pos) /*!< LCD PAL7: B14_0 Mask */
+#define LCD_PAL7_I1_Pos 31 /*!< LCD PAL7: I1 Position */
+#define LCD_PAL7_I1_Msk (0x01UL << LCD_PAL7_I1_Pos) /*!< LCD PAL7: I1 Mask */
+
+// ---------------------------------------- LCD_PAL8 --------------------------------------------
+#define LCD_PAL8_R04_0_Pos 0 /*!< LCD PAL8: R04_0 Position */
+#define LCD_PAL8_R04_0_Msk (0x1fUL << LCD_PAL8_R04_0_Pos) /*!< LCD PAL8: R04_0 Mask */
+#define LCD_PAL8_G04_0_Pos 5 /*!< LCD PAL8: G04_0 Position */
+#define LCD_PAL8_G04_0_Msk (0x1fUL << LCD_PAL8_G04_0_Pos) /*!< LCD PAL8: G04_0 Mask */
+#define LCD_PAL8_B04_0_Pos 10 /*!< LCD PAL8: B04_0 Position */
+#define LCD_PAL8_B04_0_Msk (0x1fUL << LCD_PAL8_B04_0_Pos) /*!< LCD PAL8: B04_0 Mask */
+#define LCD_PAL8_I0_Pos 15 /*!< LCD PAL8: I0 Position */
+#define LCD_PAL8_I0_Msk (0x01UL << LCD_PAL8_I0_Pos) /*!< LCD PAL8: I0 Mask */
+#define LCD_PAL8_R14_0_Pos 16 /*!< LCD PAL8: R14_0 Position */
+#define LCD_PAL8_R14_0_Msk (0x1fUL << LCD_PAL8_R14_0_Pos) /*!< LCD PAL8: R14_0 Mask */
+#define LCD_PAL8_G14_0_Pos 21 /*!< LCD PAL8: G14_0 Position */
+#define LCD_PAL8_G14_0_Msk (0x1fUL << LCD_PAL8_G14_0_Pos) /*!< LCD PAL8: G14_0 Mask */
+#define LCD_PAL8_B14_0_Pos 26 /*!< LCD PAL8: B14_0 Position */
+#define LCD_PAL8_B14_0_Msk (0x1fUL << LCD_PAL8_B14_0_Pos) /*!< LCD PAL8: B14_0 Mask */
+#define LCD_PAL8_I1_Pos 31 /*!< LCD PAL8: I1 Position */
+#define LCD_PAL8_I1_Msk (0x01UL << LCD_PAL8_I1_Pos) /*!< LCD PAL8: I1 Mask */
+
+// ---------------------------------------- LCD_PAL9 --------------------------------------------
+#define LCD_PAL9_R04_0_Pos 0 /*!< LCD PAL9: R04_0 Position */
+#define LCD_PAL9_R04_0_Msk (0x1fUL << LCD_PAL9_R04_0_Pos) /*!< LCD PAL9: R04_0 Mask */
+#define LCD_PAL9_G04_0_Pos 5 /*!< LCD PAL9: G04_0 Position */
+#define LCD_PAL9_G04_0_Msk (0x1fUL << LCD_PAL9_G04_0_Pos) /*!< LCD PAL9: G04_0 Mask */
+#define LCD_PAL9_B04_0_Pos 10 /*!< LCD PAL9: B04_0 Position */
+#define LCD_PAL9_B04_0_Msk (0x1fUL << LCD_PAL9_B04_0_Pos) /*!< LCD PAL9: B04_0 Mask */
+#define LCD_PAL9_I0_Pos 15 /*!< LCD PAL9: I0 Position */
+#define LCD_PAL9_I0_Msk (0x01UL << LCD_PAL9_I0_Pos) /*!< LCD PAL9: I0 Mask */
+#define LCD_PAL9_R14_0_Pos 16 /*!< LCD PAL9: R14_0 Position */
+#define LCD_PAL9_R14_0_Msk (0x1fUL << LCD_PAL9_R14_0_Pos) /*!< LCD PAL9: R14_0 Mask */
+#define LCD_PAL9_G14_0_Pos 21 /*!< LCD PAL9: G14_0 Position */
+#define LCD_PAL9_G14_0_Msk (0x1fUL << LCD_PAL9_G14_0_Pos) /*!< LCD PAL9: G14_0 Mask */
+#define LCD_PAL9_B14_0_Pos 26 /*!< LCD PAL9: B14_0 Position */
+#define LCD_PAL9_B14_0_Msk (0x1fUL << LCD_PAL9_B14_0_Pos) /*!< LCD PAL9: B14_0 Mask */
+#define LCD_PAL9_I1_Pos 31 /*!< LCD PAL9: I1 Position */
+#define LCD_PAL9_I1_Msk (0x01UL << LCD_PAL9_I1_Pos) /*!< LCD PAL9: I1 Mask */
+
+// ---------------------------------------- LCD_PAL10 -------------------------------------------
+#define LCD_PAL10_R04_0_Pos 0 /*!< LCD PAL10: R04_0 Position */
+#define LCD_PAL10_R04_0_Msk (0x1fUL << LCD_PAL10_R04_0_Pos) /*!< LCD PAL10: R04_0 Mask */
+#define LCD_PAL10_G04_0_Pos 5 /*!< LCD PAL10: G04_0 Position */
+#define LCD_PAL10_G04_0_Msk (0x1fUL << LCD_PAL10_G04_0_Pos) /*!< LCD PAL10: G04_0 Mask */
+#define LCD_PAL10_B04_0_Pos 10 /*!< LCD PAL10: B04_0 Position */
+#define LCD_PAL10_B04_0_Msk (0x1fUL << LCD_PAL10_B04_0_Pos) /*!< LCD PAL10: B04_0 Mask */
+#define LCD_PAL10_I0_Pos 15 /*!< LCD PAL10: I0 Position */
+#define LCD_PAL10_I0_Msk (0x01UL << LCD_PAL10_I0_Pos) /*!< LCD PAL10: I0 Mask */
+#define LCD_PAL10_R14_0_Pos 16 /*!< LCD PAL10: R14_0 Position */
+#define LCD_PAL10_R14_0_Msk (0x1fUL << LCD_PAL10_R14_0_Pos) /*!< LCD PAL10: R14_0 Mask */
+#define LCD_PAL10_G14_0_Pos 21 /*!< LCD PAL10: G14_0 Position */
+#define LCD_PAL10_G14_0_Msk (0x1fUL << LCD_PAL10_G14_0_Pos) /*!< LCD PAL10: G14_0 Mask */
+#define LCD_PAL10_B14_0_Pos 26 /*!< LCD PAL10: B14_0 Position */
+#define LCD_PAL10_B14_0_Msk (0x1fUL << LCD_PAL10_B14_0_Pos) /*!< LCD PAL10: B14_0 Mask */
+#define LCD_PAL10_I1_Pos 31 /*!< LCD PAL10: I1 Position */
+#define LCD_PAL10_I1_Msk (0x01UL << LCD_PAL10_I1_Pos) /*!< LCD PAL10: I1 Mask */
+
+// ---------------------------------------- LCD_PAL11 -------------------------------------------
+#define LCD_PAL11_R04_0_Pos 0 /*!< LCD PAL11: R04_0 Position */
+#define LCD_PAL11_R04_0_Msk (0x1fUL << LCD_PAL11_R04_0_Pos) /*!< LCD PAL11: R04_0 Mask */
+#define LCD_PAL11_G04_0_Pos 5 /*!< LCD PAL11: G04_0 Position */
+#define LCD_PAL11_G04_0_Msk (0x1fUL << LCD_PAL11_G04_0_Pos) /*!< LCD PAL11: G04_0 Mask */
+#define LCD_PAL11_B04_0_Pos 10 /*!< LCD PAL11: B04_0 Position */
+#define LCD_PAL11_B04_0_Msk (0x1fUL << LCD_PAL11_B04_0_Pos) /*!< LCD PAL11: B04_0 Mask */
+#define LCD_PAL11_I0_Pos 15 /*!< LCD PAL11: I0 Position */
+#define LCD_PAL11_I0_Msk (0x01UL << LCD_PAL11_I0_Pos) /*!< LCD PAL11: I0 Mask */
+#define LCD_PAL11_R14_0_Pos 16 /*!< LCD PAL11: R14_0 Position */
+#define LCD_PAL11_R14_0_Msk (0x1fUL << LCD_PAL11_R14_0_Pos) /*!< LCD PAL11: R14_0 Mask */
+#define LCD_PAL11_G14_0_Pos 21 /*!< LCD PAL11: G14_0 Position */
+#define LCD_PAL11_G14_0_Msk (0x1fUL << LCD_PAL11_G14_0_Pos) /*!< LCD PAL11: G14_0 Mask */
+#define LCD_PAL11_B14_0_Pos 26 /*!< LCD PAL11: B14_0 Position */
+#define LCD_PAL11_B14_0_Msk (0x1fUL << LCD_PAL11_B14_0_Pos) /*!< LCD PAL11: B14_0 Mask */
+#define LCD_PAL11_I1_Pos 31 /*!< LCD PAL11: I1 Position */
+#define LCD_PAL11_I1_Msk (0x01UL << LCD_PAL11_I1_Pos) /*!< LCD PAL11: I1 Mask */
+
+// ---------------------------------------- LCD_PAL12 -------------------------------------------
+#define LCD_PAL12_R04_0_Pos 0 /*!< LCD PAL12: R04_0 Position */
+#define LCD_PAL12_R04_0_Msk (0x1fUL << LCD_PAL12_R04_0_Pos) /*!< LCD PAL12: R04_0 Mask */
+#define LCD_PAL12_G04_0_Pos 5 /*!< LCD PAL12: G04_0 Position */
+#define LCD_PAL12_G04_0_Msk (0x1fUL << LCD_PAL12_G04_0_Pos) /*!< LCD PAL12: G04_0 Mask */
+#define LCD_PAL12_B04_0_Pos 10 /*!< LCD PAL12: B04_0 Position */
+#define LCD_PAL12_B04_0_Msk (0x1fUL << LCD_PAL12_B04_0_Pos) /*!< LCD PAL12: B04_0 Mask */
+#define LCD_PAL12_I0_Pos 15 /*!< LCD PAL12: I0 Position */
+#define LCD_PAL12_I0_Msk (0x01UL << LCD_PAL12_I0_Pos) /*!< LCD PAL12: I0 Mask */
+#define LCD_PAL12_R14_0_Pos 16 /*!< LCD PAL12: R14_0 Position */
+#define LCD_PAL12_R14_0_Msk (0x1fUL << LCD_PAL12_R14_0_Pos) /*!< LCD PAL12: R14_0 Mask */
+#define LCD_PAL12_G14_0_Pos 21 /*!< LCD PAL12: G14_0 Position */
+#define LCD_PAL12_G14_0_Msk (0x1fUL << LCD_PAL12_G14_0_Pos) /*!< LCD PAL12: G14_0 Mask */
+#define LCD_PAL12_B14_0_Pos 26 /*!< LCD PAL12: B14_0 Position */
+#define LCD_PAL12_B14_0_Msk (0x1fUL << LCD_PAL12_B14_0_Pos) /*!< LCD PAL12: B14_0 Mask */
+#define LCD_PAL12_I1_Pos 31 /*!< LCD PAL12: I1 Position */
+#define LCD_PAL12_I1_Msk (0x01UL << LCD_PAL12_I1_Pos) /*!< LCD PAL12: I1 Mask */
+
+// ---------------------------------------- LCD_PAL13 -------------------------------------------
+#define LCD_PAL13_R04_0_Pos 0 /*!< LCD PAL13: R04_0 Position */
+#define LCD_PAL13_R04_0_Msk (0x1fUL << LCD_PAL13_R04_0_Pos) /*!< LCD PAL13: R04_0 Mask */
+#define LCD_PAL13_G04_0_Pos 5 /*!< LCD PAL13: G04_0 Position */
+#define LCD_PAL13_G04_0_Msk (0x1fUL << LCD_PAL13_G04_0_Pos) /*!< LCD PAL13: G04_0 Mask */
+#define LCD_PAL13_B04_0_Pos 10 /*!< LCD PAL13: B04_0 Position */
+#define LCD_PAL13_B04_0_Msk (0x1fUL << LCD_PAL13_B04_0_Pos) /*!< LCD PAL13: B04_0 Mask */
+#define LCD_PAL13_I0_Pos 15 /*!< LCD PAL13: I0 Position */
+#define LCD_PAL13_I0_Msk (0x01UL << LCD_PAL13_I0_Pos) /*!< LCD PAL13: I0 Mask */
+#define LCD_PAL13_R14_0_Pos 16 /*!< LCD PAL13: R14_0 Position */
+#define LCD_PAL13_R14_0_Msk (0x1fUL << LCD_PAL13_R14_0_Pos) /*!< LCD PAL13: R14_0 Mask */
+#define LCD_PAL13_G14_0_Pos 21 /*!< LCD PAL13: G14_0 Position */
+#define LCD_PAL13_G14_0_Msk (0x1fUL << LCD_PAL13_G14_0_Pos) /*!< LCD PAL13: G14_0 Mask */
+#define LCD_PAL13_B14_0_Pos 26 /*!< LCD PAL13: B14_0 Position */
+#define LCD_PAL13_B14_0_Msk (0x1fUL << LCD_PAL13_B14_0_Pos) /*!< LCD PAL13: B14_0 Mask */
+#define LCD_PAL13_I1_Pos 31 /*!< LCD PAL13: I1 Position */
+#define LCD_PAL13_I1_Msk (0x01UL << LCD_PAL13_I1_Pos) /*!< LCD PAL13: I1 Mask */
+
+// ---------------------------------------- LCD_PAL14 -------------------------------------------
+#define LCD_PAL14_R04_0_Pos 0 /*!< LCD PAL14: R04_0 Position */
+#define LCD_PAL14_R04_0_Msk (0x1fUL << LCD_PAL14_R04_0_Pos) /*!< LCD PAL14: R04_0 Mask */
+#define LCD_PAL14_G04_0_Pos 5 /*!< LCD PAL14: G04_0 Position */
+#define LCD_PAL14_G04_0_Msk (0x1fUL << LCD_PAL14_G04_0_Pos) /*!< LCD PAL14: G04_0 Mask */
+#define LCD_PAL14_B04_0_Pos 10 /*!< LCD PAL14: B04_0 Position */
+#define LCD_PAL14_B04_0_Msk (0x1fUL << LCD_PAL14_B04_0_Pos) /*!< LCD PAL14: B04_0 Mask */
+#define LCD_PAL14_I0_Pos 15 /*!< LCD PAL14: I0 Position */
+#define LCD_PAL14_I0_Msk (0x01UL << LCD_PAL14_I0_Pos) /*!< LCD PAL14: I0 Mask */
+#define LCD_PAL14_R14_0_Pos 16 /*!< LCD PAL14: R14_0 Position */
+#define LCD_PAL14_R14_0_Msk (0x1fUL << LCD_PAL14_R14_0_Pos) /*!< LCD PAL14: R14_0 Mask */
+#define LCD_PAL14_G14_0_Pos 21 /*!< LCD PAL14: G14_0 Position */
+#define LCD_PAL14_G14_0_Msk (0x1fUL << LCD_PAL14_G14_0_Pos) /*!< LCD PAL14: G14_0 Mask */
+#define LCD_PAL14_B14_0_Pos 26 /*!< LCD PAL14: B14_0 Position */
+#define LCD_PAL14_B14_0_Msk (0x1fUL << LCD_PAL14_B14_0_Pos) /*!< LCD PAL14: B14_0 Mask */
+#define LCD_PAL14_I1_Pos 31 /*!< LCD PAL14: I1 Position */
+#define LCD_PAL14_I1_Msk (0x01UL << LCD_PAL14_I1_Pos) /*!< LCD PAL14: I1 Mask */
+
+// ---------------------------------------- LCD_PAL15 -------------------------------------------
+#define LCD_PAL15_R04_0_Pos 0 /*!< LCD PAL15: R04_0 Position */
+#define LCD_PAL15_R04_0_Msk (0x1fUL << LCD_PAL15_R04_0_Pos) /*!< LCD PAL15: R04_0 Mask */
+#define LCD_PAL15_G04_0_Pos 5 /*!< LCD PAL15: G04_0 Position */
+#define LCD_PAL15_G04_0_Msk (0x1fUL << LCD_PAL15_G04_0_Pos) /*!< LCD PAL15: G04_0 Mask */
+#define LCD_PAL15_B04_0_Pos 10 /*!< LCD PAL15: B04_0 Position */
+#define LCD_PAL15_B04_0_Msk (0x1fUL << LCD_PAL15_B04_0_Pos) /*!< LCD PAL15: B04_0 Mask */
+#define LCD_PAL15_I0_Pos 15 /*!< LCD PAL15: I0 Position */
+#define LCD_PAL15_I0_Msk (0x01UL << LCD_PAL15_I0_Pos) /*!< LCD PAL15: I0 Mask */
+#define LCD_PAL15_R14_0_Pos 16 /*!< LCD PAL15: R14_0 Position */
+#define LCD_PAL15_R14_0_Msk (0x1fUL << LCD_PAL15_R14_0_Pos) /*!< LCD PAL15: R14_0 Mask */
+#define LCD_PAL15_G14_0_Pos 21 /*!< LCD PAL15: G14_0 Position */
+#define LCD_PAL15_G14_0_Msk (0x1fUL << LCD_PAL15_G14_0_Pos) /*!< LCD PAL15: G14_0 Mask */
+#define LCD_PAL15_B14_0_Pos 26 /*!< LCD PAL15: B14_0 Position */
+#define LCD_PAL15_B14_0_Msk (0x1fUL << LCD_PAL15_B14_0_Pos) /*!< LCD PAL15: B14_0 Mask */
+#define LCD_PAL15_I1_Pos 31 /*!< LCD PAL15: I1 Position */
+#define LCD_PAL15_I1_Msk (0x01UL << LCD_PAL15_I1_Pos) /*!< LCD PAL15: I1 Mask */
+
+// ---------------------------------------- LCD_PAL16 -------------------------------------------
+#define LCD_PAL16_R04_0_Pos 0 /*!< LCD PAL16: R04_0 Position */
+#define LCD_PAL16_R04_0_Msk (0x1fUL << LCD_PAL16_R04_0_Pos) /*!< LCD PAL16: R04_0 Mask */
+#define LCD_PAL16_G04_0_Pos 5 /*!< LCD PAL16: G04_0 Position */
+#define LCD_PAL16_G04_0_Msk (0x1fUL << LCD_PAL16_G04_0_Pos) /*!< LCD PAL16: G04_0 Mask */
+#define LCD_PAL16_B04_0_Pos 10 /*!< LCD PAL16: B04_0 Position */
+#define LCD_PAL16_B04_0_Msk (0x1fUL << LCD_PAL16_B04_0_Pos) /*!< LCD PAL16: B04_0 Mask */
+#define LCD_PAL16_I0_Pos 15 /*!< LCD PAL16: I0 Position */
+#define LCD_PAL16_I0_Msk (0x01UL << LCD_PAL16_I0_Pos) /*!< LCD PAL16: I0 Mask */
+#define LCD_PAL16_R14_0_Pos 16 /*!< LCD PAL16: R14_0 Position */
+#define LCD_PAL16_R14_0_Msk (0x1fUL << LCD_PAL16_R14_0_Pos) /*!< LCD PAL16: R14_0 Mask */
+#define LCD_PAL16_G14_0_Pos 21 /*!< LCD PAL16: G14_0 Position */
+#define LCD_PAL16_G14_0_Msk (0x1fUL << LCD_PAL16_G14_0_Pos) /*!< LCD PAL16: G14_0 Mask */
+#define LCD_PAL16_B14_0_Pos 26 /*!< LCD PAL16: B14_0 Position */
+#define LCD_PAL16_B14_0_Msk (0x1fUL << LCD_PAL16_B14_0_Pos) /*!< LCD PAL16: B14_0 Mask */
+#define LCD_PAL16_I1_Pos 31 /*!< LCD PAL16: I1 Position */
+#define LCD_PAL16_I1_Msk (0x01UL << LCD_PAL16_I1_Pos) /*!< LCD PAL16: I1 Mask */
+
+// ---------------------------------------- LCD_PAL17 -------------------------------------------
+#define LCD_PAL17_R04_0_Pos 0 /*!< LCD PAL17: R04_0 Position */
+#define LCD_PAL17_R04_0_Msk (0x1fUL << LCD_PAL17_R04_0_Pos) /*!< LCD PAL17: R04_0 Mask */
+#define LCD_PAL17_G04_0_Pos 5 /*!< LCD PAL17: G04_0 Position */
+#define LCD_PAL17_G04_0_Msk (0x1fUL << LCD_PAL17_G04_0_Pos) /*!< LCD PAL17: G04_0 Mask */
+#define LCD_PAL17_B04_0_Pos 10 /*!< LCD PAL17: B04_0 Position */
+#define LCD_PAL17_B04_0_Msk (0x1fUL << LCD_PAL17_B04_0_Pos) /*!< LCD PAL17: B04_0 Mask */
+#define LCD_PAL17_I0_Pos 15 /*!< LCD PAL17: I0 Position */
+#define LCD_PAL17_I0_Msk (0x01UL << LCD_PAL17_I0_Pos) /*!< LCD PAL17: I0 Mask */
+#define LCD_PAL17_R14_0_Pos 16 /*!< LCD PAL17: R14_0 Position */
+#define LCD_PAL17_R14_0_Msk (0x1fUL << LCD_PAL17_R14_0_Pos) /*!< LCD PAL17: R14_0 Mask */
+#define LCD_PAL17_G14_0_Pos 21 /*!< LCD PAL17: G14_0 Position */
+#define LCD_PAL17_G14_0_Msk (0x1fUL << LCD_PAL17_G14_0_Pos) /*!< LCD PAL17: G14_0 Mask */
+#define LCD_PAL17_B14_0_Pos 26 /*!< LCD PAL17: B14_0 Position */
+#define LCD_PAL17_B14_0_Msk (0x1fUL << LCD_PAL17_B14_0_Pos) /*!< LCD PAL17: B14_0 Mask */
+#define LCD_PAL17_I1_Pos 31 /*!< LCD PAL17: I1 Position */
+#define LCD_PAL17_I1_Msk (0x01UL << LCD_PAL17_I1_Pos) /*!< LCD PAL17: I1 Mask */
+
+// ---------------------------------------- LCD_PAL18 -------------------------------------------
+#define LCD_PAL18_R04_0_Pos 0 /*!< LCD PAL18: R04_0 Position */
+#define LCD_PAL18_R04_0_Msk (0x1fUL << LCD_PAL18_R04_0_Pos) /*!< LCD PAL18: R04_0 Mask */
+#define LCD_PAL18_G04_0_Pos 5 /*!< LCD PAL18: G04_0 Position */
+#define LCD_PAL18_G04_0_Msk (0x1fUL << LCD_PAL18_G04_0_Pos) /*!< LCD PAL18: G04_0 Mask */
+#define LCD_PAL18_B04_0_Pos 10 /*!< LCD PAL18: B04_0 Position */
+#define LCD_PAL18_B04_0_Msk (0x1fUL << LCD_PAL18_B04_0_Pos) /*!< LCD PAL18: B04_0 Mask */
+#define LCD_PAL18_I0_Pos 15 /*!< LCD PAL18: I0 Position */
+#define LCD_PAL18_I0_Msk (0x01UL << LCD_PAL18_I0_Pos) /*!< LCD PAL18: I0 Mask */
+#define LCD_PAL18_R14_0_Pos 16 /*!< LCD PAL18: R14_0 Position */
+#define LCD_PAL18_R14_0_Msk (0x1fUL << LCD_PAL18_R14_0_Pos) /*!< LCD PAL18: R14_0 Mask */
+#define LCD_PAL18_G14_0_Pos 21 /*!< LCD PAL18: G14_0 Position */
+#define LCD_PAL18_G14_0_Msk (0x1fUL << LCD_PAL18_G14_0_Pos) /*!< LCD PAL18: G14_0 Mask */
+#define LCD_PAL18_B14_0_Pos 26 /*!< LCD PAL18: B14_0 Position */
+#define LCD_PAL18_B14_0_Msk (0x1fUL << LCD_PAL18_B14_0_Pos) /*!< LCD PAL18: B14_0 Mask */
+#define LCD_PAL18_I1_Pos 31 /*!< LCD PAL18: I1 Position */
+#define LCD_PAL18_I1_Msk (0x01UL << LCD_PAL18_I1_Pos) /*!< LCD PAL18: I1 Mask */
+
+// ---------------------------------------- LCD_PAL19 -------------------------------------------
+#define LCD_PAL19_R04_0_Pos 0 /*!< LCD PAL19: R04_0 Position */
+#define LCD_PAL19_R04_0_Msk (0x1fUL << LCD_PAL19_R04_0_Pos) /*!< LCD PAL19: R04_0 Mask */
+#define LCD_PAL19_G04_0_Pos 5 /*!< LCD PAL19: G04_0 Position */
+#define LCD_PAL19_G04_0_Msk (0x1fUL << LCD_PAL19_G04_0_Pos) /*!< LCD PAL19: G04_0 Mask */
+#define LCD_PAL19_B04_0_Pos 10 /*!< LCD PAL19: B04_0 Position */
+#define LCD_PAL19_B04_0_Msk (0x1fUL << LCD_PAL19_B04_0_Pos) /*!< LCD PAL19: B04_0 Mask */
+#define LCD_PAL19_I0_Pos 15 /*!< LCD PAL19: I0 Position */
+#define LCD_PAL19_I0_Msk (0x01UL << LCD_PAL19_I0_Pos) /*!< LCD PAL19: I0 Mask */
+#define LCD_PAL19_R14_0_Pos 16 /*!< LCD PAL19: R14_0 Position */
+#define LCD_PAL19_R14_0_Msk (0x1fUL << LCD_PAL19_R14_0_Pos) /*!< LCD PAL19: R14_0 Mask */
+#define LCD_PAL19_G14_0_Pos 21 /*!< LCD PAL19: G14_0 Position */
+#define LCD_PAL19_G14_0_Msk (0x1fUL << LCD_PAL19_G14_0_Pos) /*!< LCD PAL19: G14_0 Mask */
+#define LCD_PAL19_B14_0_Pos 26 /*!< LCD PAL19: B14_0 Position */
+#define LCD_PAL19_B14_0_Msk (0x1fUL << LCD_PAL19_B14_0_Pos) /*!< LCD PAL19: B14_0 Mask */
+#define LCD_PAL19_I1_Pos 31 /*!< LCD PAL19: I1 Position */
+#define LCD_PAL19_I1_Msk (0x01UL << LCD_PAL19_I1_Pos) /*!< LCD PAL19: I1 Mask */
+
+// ---------------------------------------- LCD_PAL20 -------------------------------------------
+#define LCD_PAL20_R04_0_Pos 0 /*!< LCD PAL20: R04_0 Position */
+#define LCD_PAL20_R04_0_Msk (0x1fUL << LCD_PAL20_R04_0_Pos) /*!< LCD PAL20: R04_0 Mask */
+#define LCD_PAL20_G04_0_Pos 5 /*!< LCD PAL20: G04_0 Position */
+#define LCD_PAL20_G04_0_Msk (0x1fUL << LCD_PAL20_G04_0_Pos) /*!< LCD PAL20: G04_0 Mask */
+#define LCD_PAL20_B04_0_Pos 10 /*!< LCD PAL20: B04_0 Position */
+#define LCD_PAL20_B04_0_Msk (0x1fUL << LCD_PAL20_B04_0_Pos) /*!< LCD PAL20: B04_0 Mask */
+#define LCD_PAL20_I0_Pos 15 /*!< LCD PAL20: I0 Position */
+#define LCD_PAL20_I0_Msk (0x01UL << LCD_PAL20_I0_Pos) /*!< LCD PAL20: I0 Mask */
+#define LCD_PAL20_R14_0_Pos 16 /*!< LCD PAL20: R14_0 Position */
+#define LCD_PAL20_R14_0_Msk (0x1fUL << LCD_PAL20_R14_0_Pos) /*!< LCD PAL20: R14_0 Mask */
+#define LCD_PAL20_G14_0_Pos 21 /*!< LCD PAL20: G14_0 Position */
+#define LCD_PAL20_G14_0_Msk (0x1fUL << LCD_PAL20_G14_0_Pos) /*!< LCD PAL20: G14_0 Mask */
+#define LCD_PAL20_B14_0_Pos 26 /*!< LCD PAL20: B14_0 Position */
+#define LCD_PAL20_B14_0_Msk (0x1fUL << LCD_PAL20_B14_0_Pos) /*!< LCD PAL20: B14_0 Mask */
+#define LCD_PAL20_I1_Pos 31 /*!< LCD PAL20: I1 Position */
+#define LCD_PAL20_I1_Msk (0x01UL << LCD_PAL20_I1_Pos) /*!< LCD PAL20: I1 Mask */
+
+// ---------------------------------------- LCD_PAL21 -------------------------------------------
+#define LCD_PAL21_R04_0_Pos 0 /*!< LCD PAL21: R04_0 Position */
+#define LCD_PAL21_R04_0_Msk (0x1fUL << LCD_PAL21_R04_0_Pos) /*!< LCD PAL21: R04_0 Mask */
+#define LCD_PAL21_G04_0_Pos 5 /*!< LCD PAL21: G04_0 Position */
+#define LCD_PAL21_G04_0_Msk (0x1fUL << LCD_PAL21_G04_0_Pos) /*!< LCD PAL21: G04_0 Mask */
+#define LCD_PAL21_B04_0_Pos 10 /*!< LCD PAL21: B04_0 Position */
+#define LCD_PAL21_B04_0_Msk (0x1fUL << LCD_PAL21_B04_0_Pos) /*!< LCD PAL21: B04_0 Mask */
+#define LCD_PAL21_I0_Pos 15 /*!< LCD PAL21: I0 Position */
+#define LCD_PAL21_I0_Msk (0x01UL << LCD_PAL21_I0_Pos) /*!< LCD PAL21: I0 Mask */
+#define LCD_PAL21_R14_0_Pos 16 /*!< LCD PAL21: R14_0 Position */
+#define LCD_PAL21_R14_0_Msk (0x1fUL << LCD_PAL21_R14_0_Pos) /*!< LCD PAL21: R14_0 Mask */
+#define LCD_PAL21_G14_0_Pos 21 /*!< LCD PAL21: G14_0 Position */
+#define LCD_PAL21_G14_0_Msk (0x1fUL << LCD_PAL21_G14_0_Pos) /*!< LCD PAL21: G14_0 Mask */
+#define LCD_PAL21_B14_0_Pos 26 /*!< LCD PAL21: B14_0 Position */
+#define LCD_PAL21_B14_0_Msk (0x1fUL << LCD_PAL21_B14_0_Pos) /*!< LCD PAL21: B14_0 Mask */
+#define LCD_PAL21_I1_Pos 31 /*!< LCD PAL21: I1 Position */
+#define LCD_PAL21_I1_Msk (0x01UL << LCD_PAL21_I1_Pos) /*!< LCD PAL21: I1 Mask */
+
+// ---------------------------------------- LCD_PAL22 -------------------------------------------
+#define LCD_PAL22_R04_0_Pos 0 /*!< LCD PAL22: R04_0 Position */
+#define LCD_PAL22_R04_0_Msk (0x1fUL << LCD_PAL22_R04_0_Pos) /*!< LCD PAL22: R04_0 Mask */
+#define LCD_PAL22_G04_0_Pos 5 /*!< LCD PAL22: G04_0 Position */
+#define LCD_PAL22_G04_0_Msk (0x1fUL << LCD_PAL22_G04_0_Pos) /*!< LCD PAL22: G04_0 Mask */
+#define LCD_PAL22_B04_0_Pos 10 /*!< LCD PAL22: B04_0 Position */
+#define LCD_PAL22_B04_0_Msk (0x1fUL << LCD_PAL22_B04_0_Pos) /*!< LCD PAL22: B04_0 Mask */
+#define LCD_PAL22_I0_Pos 15 /*!< LCD PAL22: I0 Position */
+#define LCD_PAL22_I0_Msk (0x01UL << LCD_PAL22_I0_Pos) /*!< LCD PAL22: I0 Mask */
+#define LCD_PAL22_R14_0_Pos 16 /*!< LCD PAL22: R14_0 Position */
+#define LCD_PAL22_R14_0_Msk (0x1fUL << LCD_PAL22_R14_0_Pos) /*!< LCD PAL22: R14_0 Mask */
+#define LCD_PAL22_G14_0_Pos 21 /*!< LCD PAL22: G14_0 Position */
+#define LCD_PAL22_G14_0_Msk (0x1fUL << LCD_PAL22_G14_0_Pos) /*!< LCD PAL22: G14_0 Mask */
+#define LCD_PAL22_B14_0_Pos 26 /*!< LCD PAL22: B14_0 Position */
+#define LCD_PAL22_B14_0_Msk (0x1fUL << LCD_PAL22_B14_0_Pos) /*!< LCD PAL22: B14_0 Mask */
+#define LCD_PAL22_I1_Pos 31 /*!< LCD PAL22: I1 Position */
+#define LCD_PAL22_I1_Msk (0x01UL << LCD_PAL22_I1_Pos) /*!< LCD PAL22: I1 Mask */
+
+// ---------------------------------------- LCD_PAL23 -------------------------------------------
+#define LCD_PAL23_R04_0_Pos 0 /*!< LCD PAL23: R04_0 Position */
+#define LCD_PAL23_R04_0_Msk (0x1fUL << LCD_PAL23_R04_0_Pos) /*!< LCD PAL23: R04_0 Mask */
+#define LCD_PAL23_G04_0_Pos 5 /*!< LCD PAL23: G04_0 Position */
+#define LCD_PAL23_G04_0_Msk (0x1fUL << LCD_PAL23_G04_0_Pos) /*!< LCD PAL23: G04_0 Mask */
+#define LCD_PAL23_B04_0_Pos 10 /*!< LCD PAL23: B04_0 Position */
+#define LCD_PAL23_B04_0_Msk (0x1fUL << LCD_PAL23_B04_0_Pos) /*!< LCD PAL23: B04_0 Mask */
+#define LCD_PAL23_I0_Pos 15 /*!< LCD PAL23: I0 Position */
+#define LCD_PAL23_I0_Msk (0x01UL << LCD_PAL23_I0_Pos) /*!< LCD PAL23: I0 Mask */
+#define LCD_PAL23_R14_0_Pos 16 /*!< LCD PAL23: R14_0 Position */
+#define LCD_PAL23_R14_0_Msk (0x1fUL << LCD_PAL23_R14_0_Pos) /*!< LCD PAL23: R14_0 Mask */
+#define LCD_PAL23_G14_0_Pos 21 /*!< LCD PAL23: G14_0 Position */
+#define LCD_PAL23_G14_0_Msk (0x1fUL << LCD_PAL23_G14_0_Pos) /*!< LCD PAL23: G14_0 Mask */
+#define LCD_PAL23_B14_0_Pos 26 /*!< LCD PAL23: B14_0 Position */
+#define LCD_PAL23_B14_0_Msk (0x1fUL << LCD_PAL23_B14_0_Pos) /*!< LCD PAL23: B14_0 Mask */
+#define LCD_PAL23_I1_Pos 31 /*!< LCD PAL23: I1 Position */
+#define LCD_PAL23_I1_Msk (0x01UL << LCD_PAL23_I1_Pos) /*!< LCD PAL23: I1 Mask */
+
+// ---------------------------------------- LCD_PAL24 -------------------------------------------
+#define LCD_PAL24_R04_0_Pos 0 /*!< LCD PAL24: R04_0 Position */
+#define LCD_PAL24_R04_0_Msk (0x1fUL << LCD_PAL24_R04_0_Pos) /*!< LCD PAL24: R04_0 Mask */
+#define LCD_PAL24_G04_0_Pos 5 /*!< LCD PAL24: G04_0 Position */
+#define LCD_PAL24_G04_0_Msk (0x1fUL << LCD_PAL24_G04_0_Pos) /*!< LCD PAL24: G04_0 Mask */
+#define LCD_PAL24_B04_0_Pos 10 /*!< LCD PAL24: B04_0 Position */
+#define LCD_PAL24_B04_0_Msk (0x1fUL << LCD_PAL24_B04_0_Pos) /*!< LCD PAL24: B04_0 Mask */
+#define LCD_PAL24_I0_Pos 15 /*!< LCD PAL24: I0 Position */
+#define LCD_PAL24_I0_Msk (0x01UL << LCD_PAL24_I0_Pos) /*!< LCD PAL24: I0 Mask */
+#define LCD_PAL24_R14_0_Pos 16 /*!< LCD PAL24: R14_0 Position */
+#define LCD_PAL24_R14_0_Msk (0x1fUL << LCD_PAL24_R14_0_Pos) /*!< LCD PAL24: R14_0 Mask */
+#define LCD_PAL24_G14_0_Pos 21 /*!< LCD PAL24: G14_0 Position */
+#define LCD_PAL24_G14_0_Msk (0x1fUL << LCD_PAL24_G14_0_Pos) /*!< LCD PAL24: G14_0 Mask */
+#define LCD_PAL24_B14_0_Pos 26 /*!< LCD PAL24: B14_0 Position */
+#define LCD_PAL24_B14_0_Msk (0x1fUL << LCD_PAL24_B14_0_Pos) /*!< LCD PAL24: B14_0 Mask */
+#define LCD_PAL24_I1_Pos 31 /*!< LCD PAL24: I1 Position */
+#define LCD_PAL24_I1_Msk (0x01UL << LCD_PAL24_I1_Pos) /*!< LCD PAL24: I1 Mask */
+
+// ---------------------------------------- LCD_PAL25 -------------------------------------------
+#define LCD_PAL25_R04_0_Pos 0 /*!< LCD PAL25: R04_0 Position */
+#define LCD_PAL25_R04_0_Msk (0x1fUL << LCD_PAL25_R04_0_Pos) /*!< LCD PAL25: R04_0 Mask */
+#define LCD_PAL25_G04_0_Pos 5 /*!< LCD PAL25: G04_0 Position */
+#define LCD_PAL25_G04_0_Msk (0x1fUL << LCD_PAL25_G04_0_Pos) /*!< LCD PAL25: G04_0 Mask */
+#define LCD_PAL25_B04_0_Pos 10 /*!< LCD PAL25: B04_0 Position */
+#define LCD_PAL25_B04_0_Msk (0x1fUL << LCD_PAL25_B04_0_Pos) /*!< LCD PAL25: B04_0 Mask */
+#define LCD_PAL25_I0_Pos 15 /*!< LCD PAL25: I0 Position */
+#define LCD_PAL25_I0_Msk (0x01UL << LCD_PAL25_I0_Pos) /*!< LCD PAL25: I0 Mask */
+#define LCD_PAL25_R14_0_Pos 16 /*!< LCD PAL25: R14_0 Position */
+#define LCD_PAL25_R14_0_Msk (0x1fUL << LCD_PAL25_R14_0_Pos) /*!< LCD PAL25: R14_0 Mask */
+#define LCD_PAL25_G14_0_Pos 21 /*!< LCD PAL25: G14_0 Position */
+#define LCD_PAL25_G14_0_Msk (0x1fUL << LCD_PAL25_G14_0_Pos) /*!< LCD PAL25: G14_0 Mask */
+#define LCD_PAL25_B14_0_Pos 26 /*!< LCD PAL25: B14_0 Position */
+#define LCD_PAL25_B14_0_Msk (0x1fUL << LCD_PAL25_B14_0_Pos) /*!< LCD PAL25: B14_0 Mask */
+#define LCD_PAL25_I1_Pos 31 /*!< LCD PAL25: I1 Position */
+#define LCD_PAL25_I1_Msk (0x01UL << LCD_PAL25_I1_Pos) /*!< LCD PAL25: I1 Mask */
+
+// ---------------------------------------- LCD_PAL26 -------------------------------------------
+#define LCD_PAL26_R04_0_Pos 0 /*!< LCD PAL26: R04_0 Position */
+#define LCD_PAL26_R04_0_Msk (0x1fUL << LCD_PAL26_R04_0_Pos) /*!< LCD PAL26: R04_0 Mask */
+#define LCD_PAL26_G04_0_Pos 5 /*!< LCD PAL26: G04_0 Position */
+#define LCD_PAL26_G04_0_Msk (0x1fUL << LCD_PAL26_G04_0_Pos) /*!< LCD PAL26: G04_0 Mask */
+#define LCD_PAL26_B04_0_Pos 10 /*!< LCD PAL26: B04_0 Position */
+#define LCD_PAL26_B04_0_Msk (0x1fUL << LCD_PAL26_B04_0_Pos) /*!< LCD PAL26: B04_0 Mask */
+#define LCD_PAL26_I0_Pos 15 /*!< LCD PAL26: I0 Position */
+#define LCD_PAL26_I0_Msk (0x01UL << LCD_PAL26_I0_Pos) /*!< LCD PAL26: I0 Mask */
+#define LCD_PAL26_R14_0_Pos 16 /*!< LCD PAL26: R14_0 Position */
+#define LCD_PAL26_R14_0_Msk (0x1fUL << LCD_PAL26_R14_0_Pos) /*!< LCD PAL26: R14_0 Mask */
+#define LCD_PAL26_G14_0_Pos 21 /*!< LCD PAL26: G14_0 Position */
+#define LCD_PAL26_G14_0_Msk (0x1fUL << LCD_PAL26_G14_0_Pos) /*!< LCD PAL26: G14_0 Mask */
+#define LCD_PAL26_B14_0_Pos 26 /*!< LCD PAL26: B14_0 Position */
+#define LCD_PAL26_B14_0_Msk (0x1fUL << LCD_PAL26_B14_0_Pos) /*!< LCD PAL26: B14_0 Mask */
+#define LCD_PAL26_I1_Pos 31 /*!< LCD PAL26: I1 Position */
+#define LCD_PAL26_I1_Msk (0x01UL << LCD_PAL26_I1_Pos) /*!< LCD PAL26: I1 Mask */
+
+// ---------------------------------------- LCD_PAL27 -------------------------------------------
+#define LCD_PAL27_R04_0_Pos 0 /*!< LCD PAL27: R04_0 Position */
+#define LCD_PAL27_R04_0_Msk (0x1fUL << LCD_PAL27_R04_0_Pos) /*!< LCD PAL27: R04_0 Mask */
+#define LCD_PAL27_G04_0_Pos 5 /*!< LCD PAL27: G04_0 Position */
+#define LCD_PAL27_G04_0_Msk (0x1fUL << LCD_PAL27_G04_0_Pos) /*!< LCD PAL27: G04_0 Mask */
+#define LCD_PAL27_B04_0_Pos 10 /*!< LCD PAL27: B04_0 Position */
+#define LCD_PAL27_B04_0_Msk (0x1fUL << LCD_PAL27_B04_0_Pos) /*!< LCD PAL27: B04_0 Mask */
+#define LCD_PAL27_I0_Pos 15 /*!< LCD PAL27: I0 Position */
+#define LCD_PAL27_I0_Msk (0x01UL << LCD_PAL27_I0_Pos) /*!< LCD PAL27: I0 Mask */
+#define LCD_PAL27_R14_0_Pos 16 /*!< LCD PAL27: R14_0 Position */
+#define LCD_PAL27_R14_0_Msk (0x1fUL << LCD_PAL27_R14_0_Pos) /*!< LCD PAL27: R14_0 Mask */
+#define LCD_PAL27_G14_0_Pos 21 /*!< LCD PAL27: G14_0 Position */
+#define LCD_PAL27_G14_0_Msk (0x1fUL << LCD_PAL27_G14_0_Pos) /*!< LCD PAL27: G14_0 Mask */
+#define LCD_PAL27_B14_0_Pos 26 /*!< LCD PAL27: B14_0 Position */
+#define LCD_PAL27_B14_0_Msk (0x1fUL << LCD_PAL27_B14_0_Pos) /*!< LCD PAL27: B14_0 Mask */
+#define LCD_PAL27_I1_Pos 31 /*!< LCD PAL27: I1 Position */
+#define LCD_PAL27_I1_Msk (0x01UL << LCD_PAL27_I1_Pos) /*!< LCD PAL27: I1 Mask */
+
+// ---------------------------------------- LCD_PAL28 -------------------------------------------
+#define LCD_PAL28_R04_0_Pos 0 /*!< LCD PAL28: R04_0 Position */
+#define LCD_PAL28_R04_0_Msk (0x1fUL << LCD_PAL28_R04_0_Pos) /*!< LCD PAL28: R04_0 Mask */
+#define LCD_PAL28_G04_0_Pos 5 /*!< LCD PAL28: G04_0 Position */
+#define LCD_PAL28_G04_0_Msk (0x1fUL << LCD_PAL28_G04_0_Pos) /*!< LCD PAL28: G04_0 Mask */
+#define LCD_PAL28_B04_0_Pos 10 /*!< LCD PAL28: B04_0 Position */
+#define LCD_PAL28_B04_0_Msk (0x1fUL << LCD_PAL28_B04_0_Pos) /*!< LCD PAL28: B04_0 Mask */
+#define LCD_PAL28_I0_Pos 15 /*!< LCD PAL28: I0 Position */
+#define LCD_PAL28_I0_Msk (0x01UL << LCD_PAL28_I0_Pos) /*!< LCD PAL28: I0 Mask */
+#define LCD_PAL28_R14_0_Pos 16 /*!< LCD PAL28: R14_0 Position */
+#define LCD_PAL28_R14_0_Msk (0x1fUL << LCD_PAL28_R14_0_Pos) /*!< LCD PAL28: R14_0 Mask */
+#define LCD_PAL28_G14_0_Pos 21 /*!< LCD PAL28: G14_0 Position */
+#define LCD_PAL28_G14_0_Msk (0x1fUL << LCD_PAL28_G14_0_Pos) /*!< LCD PAL28: G14_0 Mask */
+#define LCD_PAL28_B14_0_Pos 26 /*!< LCD PAL28: B14_0 Position */
+#define LCD_PAL28_B14_0_Msk (0x1fUL << LCD_PAL28_B14_0_Pos) /*!< LCD PAL28: B14_0 Mask */
+#define LCD_PAL28_I1_Pos 31 /*!< LCD PAL28: I1 Position */
+#define LCD_PAL28_I1_Msk (0x01UL << LCD_PAL28_I1_Pos) /*!< LCD PAL28: I1 Mask */
+
+// ---------------------------------------- LCD_PAL29 -------------------------------------------
+#define LCD_PAL29_R04_0_Pos 0 /*!< LCD PAL29: R04_0 Position */
+#define LCD_PAL29_R04_0_Msk (0x1fUL << LCD_PAL29_R04_0_Pos) /*!< LCD PAL29: R04_0 Mask */
+#define LCD_PAL29_G04_0_Pos 5 /*!< LCD PAL29: G04_0 Position */
+#define LCD_PAL29_G04_0_Msk (0x1fUL << LCD_PAL29_G04_0_Pos) /*!< LCD PAL29: G04_0 Mask */
+#define LCD_PAL29_B04_0_Pos 10 /*!< LCD PAL29: B04_0 Position */
+#define LCD_PAL29_B04_0_Msk (0x1fUL << LCD_PAL29_B04_0_Pos) /*!< LCD PAL29: B04_0 Mask */
+#define LCD_PAL29_I0_Pos 15 /*!< LCD PAL29: I0 Position */
+#define LCD_PAL29_I0_Msk (0x01UL << LCD_PAL29_I0_Pos) /*!< LCD PAL29: I0 Mask */
+#define LCD_PAL29_R14_0_Pos 16 /*!< LCD PAL29: R14_0 Position */
+#define LCD_PAL29_R14_0_Msk (0x1fUL << LCD_PAL29_R14_0_Pos) /*!< LCD PAL29: R14_0 Mask */
+#define LCD_PAL29_G14_0_Pos 21 /*!< LCD PAL29: G14_0 Position */
+#define LCD_PAL29_G14_0_Msk (0x1fUL << LCD_PAL29_G14_0_Pos) /*!< LCD PAL29: G14_0 Mask */
+#define LCD_PAL29_B14_0_Pos 26 /*!< LCD PAL29: B14_0 Position */
+#define LCD_PAL29_B14_0_Msk (0x1fUL << LCD_PAL29_B14_0_Pos) /*!< LCD PAL29: B14_0 Mask */
+#define LCD_PAL29_I1_Pos 31 /*!< LCD PAL29: I1 Position */
+#define LCD_PAL29_I1_Msk (0x01UL << LCD_PAL29_I1_Pos) /*!< LCD PAL29: I1 Mask */
+
+// ---------------------------------------- LCD_PAL30 -------------------------------------------
+#define LCD_PAL30_R04_0_Pos 0 /*!< LCD PAL30: R04_0 Position */
+#define LCD_PAL30_R04_0_Msk (0x1fUL << LCD_PAL30_R04_0_Pos) /*!< LCD PAL30: R04_0 Mask */
+#define LCD_PAL30_G04_0_Pos 5 /*!< LCD PAL30: G04_0 Position */
+#define LCD_PAL30_G04_0_Msk (0x1fUL << LCD_PAL30_G04_0_Pos) /*!< LCD PAL30: G04_0 Mask */
+#define LCD_PAL30_B04_0_Pos 10 /*!< LCD PAL30: B04_0 Position */
+#define LCD_PAL30_B04_0_Msk (0x1fUL << LCD_PAL30_B04_0_Pos) /*!< LCD PAL30: B04_0 Mask */
+#define LCD_PAL30_I0_Pos 15 /*!< LCD PAL30: I0 Position */
+#define LCD_PAL30_I0_Msk (0x01UL << LCD_PAL30_I0_Pos) /*!< LCD PAL30: I0 Mask */
+#define LCD_PAL30_R14_0_Pos 16 /*!< LCD PAL30: R14_0 Position */
+#define LCD_PAL30_R14_0_Msk (0x1fUL << LCD_PAL30_R14_0_Pos) /*!< LCD PAL30: R14_0 Mask */
+#define LCD_PAL30_G14_0_Pos 21 /*!< LCD PAL30: G14_0 Position */
+#define LCD_PAL30_G14_0_Msk (0x1fUL << LCD_PAL30_G14_0_Pos) /*!< LCD PAL30: G14_0 Mask */
+#define LCD_PAL30_B14_0_Pos 26 /*!< LCD PAL30: B14_0 Position */
+#define LCD_PAL30_B14_0_Msk (0x1fUL << LCD_PAL30_B14_0_Pos) /*!< LCD PAL30: B14_0 Mask */
+#define LCD_PAL30_I1_Pos 31 /*!< LCD PAL30: I1 Position */
+#define LCD_PAL30_I1_Msk (0x01UL << LCD_PAL30_I1_Pos) /*!< LCD PAL30: I1 Mask */
+
+// ---------------------------------------- LCD_PAL31 -------------------------------------------
+#define LCD_PAL31_R04_0_Pos 0 /*!< LCD PAL31: R04_0 Position */
+#define LCD_PAL31_R04_0_Msk (0x1fUL << LCD_PAL31_R04_0_Pos) /*!< LCD PAL31: R04_0 Mask */
+#define LCD_PAL31_G04_0_Pos 5 /*!< LCD PAL31: G04_0 Position */
+#define LCD_PAL31_G04_0_Msk (0x1fUL << LCD_PAL31_G04_0_Pos) /*!< LCD PAL31: G04_0 Mask */
+#define LCD_PAL31_B04_0_Pos 10 /*!< LCD PAL31: B04_0 Position */
+#define LCD_PAL31_B04_0_Msk (0x1fUL << LCD_PAL31_B04_0_Pos) /*!< LCD PAL31: B04_0 Mask */
+#define LCD_PAL31_I0_Pos 15 /*!< LCD PAL31: I0 Position */
+#define LCD_PAL31_I0_Msk (0x01UL << LCD_PAL31_I0_Pos) /*!< LCD PAL31: I0 Mask */
+#define LCD_PAL31_R14_0_Pos 16 /*!< LCD PAL31: R14_0 Position */
+#define LCD_PAL31_R14_0_Msk (0x1fUL << LCD_PAL31_R14_0_Pos) /*!< LCD PAL31: R14_0 Mask */
+#define LCD_PAL31_G14_0_Pos 21 /*!< LCD PAL31: G14_0 Position */
+#define LCD_PAL31_G14_0_Msk (0x1fUL << LCD_PAL31_G14_0_Pos) /*!< LCD PAL31: G14_0 Mask */
+#define LCD_PAL31_B14_0_Pos 26 /*!< LCD PAL31: B14_0 Position */
+#define LCD_PAL31_B14_0_Msk (0x1fUL << LCD_PAL31_B14_0_Pos) /*!< LCD PAL31: B14_0 Mask */
+#define LCD_PAL31_I1_Pos 31 /*!< LCD PAL31: I1 Position */
+#define LCD_PAL31_I1_Msk (0x01UL << LCD_PAL31_I1_Pos) /*!< LCD PAL31: I1 Mask */
+
+// ---------------------------------------- LCD_PAL32 -------------------------------------------
+#define LCD_PAL32_R04_0_Pos 0 /*!< LCD PAL32: R04_0 Position */
+#define LCD_PAL32_R04_0_Msk (0x1fUL << LCD_PAL32_R04_0_Pos) /*!< LCD PAL32: R04_0 Mask */
+#define LCD_PAL32_G04_0_Pos 5 /*!< LCD PAL32: G04_0 Position */
+#define LCD_PAL32_G04_0_Msk (0x1fUL << LCD_PAL32_G04_0_Pos) /*!< LCD PAL32: G04_0 Mask */
+#define LCD_PAL32_B04_0_Pos 10 /*!< LCD PAL32: B04_0 Position */
+#define LCD_PAL32_B04_0_Msk (0x1fUL << LCD_PAL32_B04_0_Pos) /*!< LCD PAL32: B04_0 Mask */
+#define LCD_PAL32_I0_Pos 15 /*!< LCD PAL32: I0 Position */
+#define LCD_PAL32_I0_Msk (0x01UL << LCD_PAL32_I0_Pos) /*!< LCD PAL32: I0 Mask */
+#define LCD_PAL32_R14_0_Pos 16 /*!< LCD PAL32: R14_0 Position */
+#define LCD_PAL32_R14_0_Msk (0x1fUL << LCD_PAL32_R14_0_Pos) /*!< LCD PAL32: R14_0 Mask */
+#define LCD_PAL32_G14_0_Pos 21 /*!< LCD PAL32: G14_0 Position */
+#define LCD_PAL32_G14_0_Msk (0x1fUL << LCD_PAL32_G14_0_Pos) /*!< LCD PAL32: G14_0 Mask */
+#define LCD_PAL32_B14_0_Pos 26 /*!< LCD PAL32: B14_0 Position */
+#define LCD_PAL32_B14_0_Msk (0x1fUL << LCD_PAL32_B14_0_Pos) /*!< LCD PAL32: B14_0 Mask */
+#define LCD_PAL32_I1_Pos 31 /*!< LCD PAL32: I1 Position */
+#define LCD_PAL32_I1_Msk (0x01UL << LCD_PAL32_I1_Pos) /*!< LCD PAL32: I1 Mask */
+
+// ---------------------------------------- LCD_PAL33 -------------------------------------------
+#define LCD_PAL33_R04_0_Pos 0 /*!< LCD PAL33: R04_0 Position */
+#define LCD_PAL33_R04_0_Msk (0x1fUL << LCD_PAL33_R04_0_Pos) /*!< LCD PAL33: R04_0 Mask */
+#define LCD_PAL33_G04_0_Pos 5 /*!< LCD PAL33: G04_0 Position */
+#define LCD_PAL33_G04_0_Msk (0x1fUL << LCD_PAL33_G04_0_Pos) /*!< LCD PAL33: G04_0 Mask */
+#define LCD_PAL33_B04_0_Pos 10 /*!< LCD PAL33: B04_0 Position */
+#define LCD_PAL33_B04_0_Msk (0x1fUL << LCD_PAL33_B04_0_Pos) /*!< LCD PAL33: B04_0 Mask */
+#define LCD_PAL33_I0_Pos 15 /*!< LCD PAL33: I0 Position */
+#define LCD_PAL33_I0_Msk (0x01UL << LCD_PAL33_I0_Pos) /*!< LCD PAL33: I0 Mask */
+#define LCD_PAL33_R14_0_Pos 16 /*!< LCD PAL33: R14_0 Position */
+#define LCD_PAL33_R14_0_Msk (0x1fUL << LCD_PAL33_R14_0_Pos) /*!< LCD PAL33: R14_0 Mask */
+#define LCD_PAL33_G14_0_Pos 21 /*!< LCD PAL33: G14_0 Position */
+#define LCD_PAL33_G14_0_Msk (0x1fUL << LCD_PAL33_G14_0_Pos) /*!< LCD PAL33: G14_0 Mask */
+#define LCD_PAL33_B14_0_Pos 26 /*!< LCD PAL33: B14_0 Position */
+#define LCD_PAL33_B14_0_Msk (0x1fUL << LCD_PAL33_B14_0_Pos) /*!< LCD PAL33: B14_0 Mask */
+#define LCD_PAL33_I1_Pos 31 /*!< LCD PAL33: I1 Position */
+#define LCD_PAL33_I1_Msk (0x01UL << LCD_PAL33_I1_Pos) /*!< LCD PAL33: I1 Mask */
+
+// ---------------------------------------- LCD_PAL34 -------------------------------------------
+#define LCD_PAL34_R04_0_Pos 0 /*!< LCD PAL34: R04_0 Position */
+#define LCD_PAL34_R04_0_Msk (0x1fUL << LCD_PAL34_R04_0_Pos) /*!< LCD PAL34: R04_0 Mask */
+#define LCD_PAL34_G04_0_Pos 5 /*!< LCD PAL34: G04_0 Position */
+#define LCD_PAL34_G04_0_Msk (0x1fUL << LCD_PAL34_G04_0_Pos) /*!< LCD PAL34: G04_0 Mask */
+#define LCD_PAL34_B04_0_Pos 10 /*!< LCD PAL34: B04_0 Position */
+#define LCD_PAL34_B04_0_Msk (0x1fUL << LCD_PAL34_B04_0_Pos) /*!< LCD PAL34: B04_0 Mask */
+#define LCD_PAL34_I0_Pos 15 /*!< LCD PAL34: I0 Position */
+#define LCD_PAL34_I0_Msk (0x01UL << LCD_PAL34_I0_Pos) /*!< LCD PAL34: I0 Mask */
+#define LCD_PAL34_R14_0_Pos 16 /*!< LCD PAL34: R14_0 Position */
+#define LCD_PAL34_R14_0_Msk (0x1fUL << LCD_PAL34_R14_0_Pos) /*!< LCD PAL34: R14_0 Mask */
+#define LCD_PAL34_G14_0_Pos 21 /*!< LCD PAL34: G14_0 Position */
+#define LCD_PAL34_G14_0_Msk (0x1fUL << LCD_PAL34_G14_0_Pos) /*!< LCD PAL34: G14_0 Mask */
+#define LCD_PAL34_B14_0_Pos 26 /*!< LCD PAL34: B14_0 Position */
+#define LCD_PAL34_B14_0_Msk (0x1fUL << LCD_PAL34_B14_0_Pos) /*!< LCD PAL34: B14_0 Mask */
+#define LCD_PAL34_I1_Pos 31 /*!< LCD PAL34: I1 Position */
+#define LCD_PAL34_I1_Msk (0x01UL << LCD_PAL34_I1_Pos) /*!< LCD PAL34: I1 Mask */
+
+// ---------------------------------------- LCD_PAL35 -------------------------------------------
+#define LCD_PAL35_R04_0_Pos 0 /*!< LCD PAL35: R04_0 Position */
+#define LCD_PAL35_R04_0_Msk (0x1fUL << LCD_PAL35_R04_0_Pos) /*!< LCD PAL35: R04_0 Mask */
+#define LCD_PAL35_G04_0_Pos 5 /*!< LCD PAL35: G04_0 Position */
+#define LCD_PAL35_G04_0_Msk (0x1fUL << LCD_PAL35_G04_0_Pos) /*!< LCD PAL35: G04_0 Mask */
+#define LCD_PAL35_B04_0_Pos 10 /*!< LCD PAL35: B04_0 Position */
+#define LCD_PAL35_B04_0_Msk (0x1fUL << LCD_PAL35_B04_0_Pos) /*!< LCD PAL35: B04_0 Mask */
+#define LCD_PAL35_I0_Pos 15 /*!< LCD PAL35: I0 Position */
+#define LCD_PAL35_I0_Msk (0x01UL << LCD_PAL35_I0_Pos) /*!< LCD PAL35: I0 Mask */
+#define LCD_PAL35_R14_0_Pos 16 /*!< LCD PAL35: R14_0 Position */
+#define LCD_PAL35_R14_0_Msk (0x1fUL << LCD_PAL35_R14_0_Pos) /*!< LCD PAL35: R14_0 Mask */
+#define LCD_PAL35_G14_0_Pos 21 /*!< LCD PAL35: G14_0 Position */
+#define LCD_PAL35_G14_0_Msk (0x1fUL << LCD_PAL35_G14_0_Pos) /*!< LCD PAL35: G14_0 Mask */
+#define LCD_PAL35_B14_0_Pos 26 /*!< LCD PAL35: B14_0 Position */
+#define LCD_PAL35_B14_0_Msk (0x1fUL << LCD_PAL35_B14_0_Pos) /*!< LCD PAL35: B14_0 Mask */
+#define LCD_PAL35_I1_Pos 31 /*!< LCD PAL35: I1 Position */
+#define LCD_PAL35_I1_Msk (0x01UL << LCD_PAL35_I1_Pos) /*!< LCD PAL35: I1 Mask */
+
+// ---------------------------------------- LCD_PAL36 -------------------------------------------
+#define LCD_PAL36_R04_0_Pos 0 /*!< LCD PAL36: R04_0 Position */
+#define LCD_PAL36_R04_0_Msk (0x1fUL << LCD_PAL36_R04_0_Pos) /*!< LCD PAL36: R04_0 Mask */
+#define LCD_PAL36_G04_0_Pos 5 /*!< LCD PAL36: G04_0 Position */
+#define LCD_PAL36_G04_0_Msk (0x1fUL << LCD_PAL36_G04_0_Pos) /*!< LCD PAL36: G04_0 Mask */
+#define LCD_PAL36_B04_0_Pos 10 /*!< LCD PAL36: B04_0 Position */
+#define LCD_PAL36_B04_0_Msk (0x1fUL << LCD_PAL36_B04_0_Pos) /*!< LCD PAL36: B04_0 Mask */
+#define LCD_PAL36_I0_Pos 15 /*!< LCD PAL36: I0 Position */
+#define LCD_PAL36_I0_Msk (0x01UL << LCD_PAL36_I0_Pos) /*!< LCD PAL36: I0 Mask */
+#define LCD_PAL36_R14_0_Pos 16 /*!< LCD PAL36: R14_0 Position */
+#define LCD_PAL36_R14_0_Msk (0x1fUL << LCD_PAL36_R14_0_Pos) /*!< LCD PAL36: R14_0 Mask */
+#define LCD_PAL36_G14_0_Pos 21 /*!< LCD PAL36: G14_0 Position */
+#define LCD_PAL36_G14_0_Msk (0x1fUL << LCD_PAL36_G14_0_Pos) /*!< LCD PAL36: G14_0 Mask */
+#define LCD_PAL36_B14_0_Pos 26 /*!< LCD PAL36: B14_0 Position */
+#define LCD_PAL36_B14_0_Msk (0x1fUL << LCD_PAL36_B14_0_Pos) /*!< LCD PAL36: B14_0 Mask */
+#define LCD_PAL36_I1_Pos 31 /*!< LCD PAL36: I1 Position */
+#define LCD_PAL36_I1_Msk (0x01UL << LCD_PAL36_I1_Pos) /*!< LCD PAL36: I1 Mask */
+
+// ---------------------------------------- LCD_PAL37 -------------------------------------------
+#define LCD_PAL37_R04_0_Pos 0 /*!< LCD PAL37: R04_0 Position */
+#define LCD_PAL37_R04_0_Msk (0x1fUL << LCD_PAL37_R04_0_Pos) /*!< LCD PAL37: R04_0 Mask */
+#define LCD_PAL37_G04_0_Pos 5 /*!< LCD PAL37: G04_0 Position */
+#define LCD_PAL37_G04_0_Msk (0x1fUL << LCD_PAL37_G04_0_Pos) /*!< LCD PAL37: G04_0 Mask */
+#define LCD_PAL37_B04_0_Pos 10 /*!< LCD PAL37: B04_0 Position */
+#define LCD_PAL37_B04_0_Msk (0x1fUL << LCD_PAL37_B04_0_Pos) /*!< LCD PAL37: B04_0 Mask */
+#define LCD_PAL37_I0_Pos 15 /*!< LCD PAL37: I0 Position */
+#define LCD_PAL37_I0_Msk (0x01UL << LCD_PAL37_I0_Pos) /*!< LCD PAL37: I0 Mask */
+#define LCD_PAL37_R14_0_Pos 16 /*!< LCD PAL37: R14_0 Position */
+#define LCD_PAL37_R14_0_Msk (0x1fUL << LCD_PAL37_R14_0_Pos) /*!< LCD PAL37: R14_0 Mask */
+#define LCD_PAL37_G14_0_Pos 21 /*!< LCD PAL37: G14_0 Position */
+#define LCD_PAL37_G14_0_Msk (0x1fUL << LCD_PAL37_G14_0_Pos) /*!< LCD PAL37: G14_0 Mask */
+#define LCD_PAL37_B14_0_Pos 26 /*!< LCD PAL37: B14_0 Position */
+#define LCD_PAL37_B14_0_Msk (0x1fUL << LCD_PAL37_B14_0_Pos) /*!< LCD PAL37: B14_0 Mask */
+#define LCD_PAL37_I1_Pos 31 /*!< LCD PAL37: I1 Position */
+#define LCD_PAL37_I1_Msk (0x01UL << LCD_PAL37_I1_Pos) /*!< LCD PAL37: I1 Mask */
+
+// ---------------------------------------- LCD_PAL38 -------------------------------------------
+#define LCD_PAL38_R04_0_Pos 0 /*!< LCD PAL38: R04_0 Position */
+#define LCD_PAL38_R04_0_Msk (0x1fUL << LCD_PAL38_R04_0_Pos) /*!< LCD PAL38: R04_0 Mask */
+#define LCD_PAL38_G04_0_Pos 5 /*!< LCD PAL38: G04_0 Position */
+#define LCD_PAL38_G04_0_Msk (0x1fUL << LCD_PAL38_G04_0_Pos) /*!< LCD PAL38: G04_0 Mask */
+#define LCD_PAL38_B04_0_Pos 10 /*!< LCD PAL38: B04_0 Position */
+#define LCD_PAL38_B04_0_Msk (0x1fUL << LCD_PAL38_B04_0_Pos) /*!< LCD PAL38: B04_0 Mask */
+#define LCD_PAL38_I0_Pos 15 /*!< LCD PAL38: I0 Position */
+#define LCD_PAL38_I0_Msk (0x01UL << LCD_PAL38_I0_Pos) /*!< LCD PAL38: I0 Mask */
+#define LCD_PAL38_R14_0_Pos 16 /*!< LCD PAL38: R14_0 Position */
+#define LCD_PAL38_R14_0_Msk (0x1fUL << LCD_PAL38_R14_0_Pos) /*!< LCD PAL38: R14_0 Mask */
+#define LCD_PAL38_G14_0_Pos 21 /*!< LCD PAL38: G14_0 Position */
+#define LCD_PAL38_G14_0_Msk (0x1fUL << LCD_PAL38_G14_0_Pos) /*!< LCD PAL38: G14_0 Mask */
+#define LCD_PAL38_B14_0_Pos 26 /*!< LCD PAL38: B14_0 Position */
+#define LCD_PAL38_B14_0_Msk (0x1fUL << LCD_PAL38_B14_0_Pos) /*!< LCD PAL38: B14_0 Mask */
+#define LCD_PAL38_I1_Pos 31 /*!< LCD PAL38: I1 Position */
+#define LCD_PAL38_I1_Msk (0x01UL << LCD_PAL38_I1_Pos) /*!< LCD PAL38: I1 Mask */
+
+// ---------------------------------------- LCD_PAL39 -------------------------------------------
+#define LCD_PAL39_R04_0_Pos 0 /*!< LCD PAL39: R04_0 Position */
+#define LCD_PAL39_R04_0_Msk (0x1fUL << LCD_PAL39_R04_0_Pos) /*!< LCD PAL39: R04_0 Mask */
+#define LCD_PAL39_G04_0_Pos 5 /*!< LCD PAL39: G04_0 Position */
+#define LCD_PAL39_G04_0_Msk (0x1fUL << LCD_PAL39_G04_0_Pos) /*!< LCD PAL39: G04_0 Mask */
+#define LCD_PAL39_B04_0_Pos 10 /*!< LCD PAL39: B04_0 Position */
+#define LCD_PAL39_B04_0_Msk (0x1fUL << LCD_PAL39_B04_0_Pos) /*!< LCD PAL39: B04_0 Mask */
+#define LCD_PAL39_I0_Pos 15 /*!< LCD PAL39: I0 Position */
+#define LCD_PAL39_I0_Msk (0x01UL << LCD_PAL39_I0_Pos) /*!< LCD PAL39: I0 Mask */
+#define LCD_PAL39_R14_0_Pos 16 /*!< LCD PAL39: R14_0 Position */
+#define LCD_PAL39_R14_0_Msk (0x1fUL << LCD_PAL39_R14_0_Pos) /*!< LCD PAL39: R14_0 Mask */
+#define LCD_PAL39_G14_0_Pos 21 /*!< LCD PAL39: G14_0 Position */
+#define LCD_PAL39_G14_0_Msk (0x1fUL << LCD_PAL39_G14_0_Pos) /*!< LCD PAL39: G14_0 Mask */
+#define LCD_PAL39_B14_0_Pos 26 /*!< LCD PAL39: B14_0 Position */
+#define LCD_PAL39_B14_0_Msk (0x1fUL << LCD_PAL39_B14_0_Pos) /*!< LCD PAL39: B14_0 Mask */
+#define LCD_PAL39_I1_Pos 31 /*!< LCD PAL39: I1 Position */
+#define LCD_PAL39_I1_Msk (0x01UL << LCD_PAL39_I1_Pos) /*!< LCD PAL39: I1 Mask */
+
+// ---------------------------------------- LCD_PAL40 -------------------------------------------
+#define LCD_PAL40_R04_0_Pos 0 /*!< LCD PAL40: R04_0 Position */
+#define LCD_PAL40_R04_0_Msk (0x1fUL << LCD_PAL40_R04_0_Pos) /*!< LCD PAL40: R04_0 Mask */
+#define LCD_PAL40_G04_0_Pos 5 /*!< LCD PAL40: G04_0 Position */
+#define LCD_PAL40_G04_0_Msk (0x1fUL << LCD_PAL40_G04_0_Pos) /*!< LCD PAL40: G04_0 Mask */
+#define LCD_PAL40_B04_0_Pos 10 /*!< LCD PAL40: B04_0 Position */
+#define LCD_PAL40_B04_0_Msk (0x1fUL << LCD_PAL40_B04_0_Pos) /*!< LCD PAL40: B04_0 Mask */
+#define LCD_PAL40_I0_Pos 15 /*!< LCD PAL40: I0 Position */
+#define LCD_PAL40_I0_Msk (0x01UL << LCD_PAL40_I0_Pos) /*!< LCD PAL40: I0 Mask */
+#define LCD_PAL40_R14_0_Pos 16 /*!< LCD PAL40: R14_0 Position */
+#define LCD_PAL40_R14_0_Msk (0x1fUL << LCD_PAL40_R14_0_Pos) /*!< LCD PAL40: R14_0 Mask */
+#define LCD_PAL40_G14_0_Pos 21 /*!< LCD PAL40: G14_0 Position */
+#define LCD_PAL40_G14_0_Msk (0x1fUL << LCD_PAL40_G14_0_Pos) /*!< LCD PAL40: G14_0 Mask */
+#define LCD_PAL40_B14_0_Pos 26 /*!< LCD PAL40: B14_0 Position */
+#define LCD_PAL40_B14_0_Msk (0x1fUL << LCD_PAL40_B14_0_Pos) /*!< LCD PAL40: B14_0 Mask */
+#define LCD_PAL40_I1_Pos 31 /*!< LCD PAL40: I1 Position */
+#define LCD_PAL40_I1_Msk (0x01UL << LCD_PAL40_I1_Pos) /*!< LCD PAL40: I1 Mask */
+
+// ---------------------------------------- LCD_PAL41 -------------------------------------------
+#define LCD_PAL41_R04_0_Pos 0 /*!< LCD PAL41: R04_0 Position */
+#define LCD_PAL41_R04_0_Msk (0x1fUL << LCD_PAL41_R04_0_Pos) /*!< LCD PAL41: R04_0 Mask */
+#define LCD_PAL41_G04_0_Pos 5 /*!< LCD PAL41: G04_0 Position */
+#define LCD_PAL41_G04_0_Msk (0x1fUL << LCD_PAL41_G04_0_Pos) /*!< LCD PAL41: G04_0 Mask */
+#define LCD_PAL41_B04_0_Pos 10 /*!< LCD PAL41: B04_0 Position */
+#define LCD_PAL41_B04_0_Msk (0x1fUL << LCD_PAL41_B04_0_Pos) /*!< LCD PAL41: B04_0 Mask */
+#define LCD_PAL41_I0_Pos 15 /*!< LCD PAL41: I0 Position */
+#define LCD_PAL41_I0_Msk (0x01UL << LCD_PAL41_I0_Pos) /*!< LCD PAL41: I0 Mask */
+#define LCD_PAL41_R14_0_Pos 16 /*!< LCD PAL41: R14_0 Position */
+#define LCD_PAL41_R14_0_Msk (0x1fUL << LCD_PAL41_R14_0_Pos) /*!< LCD PAL41: R14_0 Mask */
+#define LCD_PAL41_G14_0_Pos 21 /*!< LCD PAL41: G14_0 Position */
+#define LCD_PAL41_G14_0_Msk (0x1fUL << LCD_PAL41_G14_0_Pos) /*!< LCD PAL41: G14_0 Mask */
+#define LCD_PAL41_B14_0_Pos 26 /*!< LCD PAL41: B14_0 Position */
+#define LCD_PAL41_B14_0_Msk (0x1fUL << LCD_PAL41_B14_0_Pos) /*!< LCD PAL41: B14_0 Mask */
+#define LCD_PAL41_I1_Pos 31 /*!< LCD PAL41: I1 Position */
+#define LCD_PAL41_I1_Msk (0x01UL << LCD_PAL41_I1_Pos) /*!< LCD PAL41: I1 Mask */
+
+// ---------------------------------------- LCD_PAL42 -------------------------------------------
+#define LCD_PAL42_R04_0_Pos 0 /*!< LCD PAL42: R04_0 Position */
+#define LCD_PAL42_R04_0_Msk (0x1fUL << LCD_PAL42_R04_0_Pos) /*!< LCD PAL42: R04_0 Mask */
+#define LCD_PAL42_G04_0_Pos 5 /*!< LCD PAL42: G04_0 Position */
+#define LCD_PAL42_G04_0_Msk (0x1fUL << LCD_PAL42_G04_0_Pos) /*!< LCD PAL42: G04_0 Mask */
+#define LCD_PAL42_B04_0_Pos 10 /*!< LCD PAL42: B04_0 Position */
+#define LCD_PAL42_B04_0_Msk (0x1fUL << LCD_PAL42_B04_0_Pos) /*!< LCD PAL42: B04_0 Mask */
+#define LCD_PAL42_I0_Pos 15 /*!< LCD PAL42: I0 Position */
+#define LCD_PAL42_I0_Msk (0x01UL << LCD_PAL42_I0_Pos) /*!< LCD PAL42: I0 Mask */
+#define LCD_PAL42_R14_0_Pos 16 /*!< LCD PAL42: R14_0 Position */
+#define LCD_PAL42_R14_0_Msk (0x1fUL << LCD_PAL42_R14_0_Pos) /*!< LCD PAL42: R14_0 Mask */
+#define LCD_PAL42_G14_0_Pos 21 /*!< LCD PAL42: G14_0 Position */
+#define LCD_PAL42_G14_0_Msk (0x1fUL << LCD_PAL42_G14_0_Pos) /*!< LCD PAL42: G14_0 Mask */
+#define LCD_PAL42_B14_0_Pos 26 /*!< LCD PAL42: B14_0 Position */
+#define LCD_PAL42_B14_0_Msk (0x1fUL << LCD_PAL42_B14_0_Pos) /*!< LCD PAL42: B14_0 Mask */
+#define LCD_PAL42_I1_Pos 31 /*!< LCD PAL42: I1 Position */
+#define LCD_PAL42_I1_Msk (0x01UL << LCD_PAL42_I1_Pos) /*!< LCD PAL42: I1 Mask */
+
+// ---------------------------------------- LCD_PAL43 -------------------------------------------
+#define LCD_PAL43_R04_0_Pos 0 /*!< LCD PAL43: R04_0 Position */
+#define LCD_PAL43_R04_0_Msk (0x1fUL << LCD_PAL43_R04_0_Pos) /*!< LCD PAL43: R04_0 Mask */
+#define LCD_PAL43_G04_0_Pos 5 /*!< LCD PAL43: G04_0 Position */
+#define LCD_PAL43_G04_0_Msk (0x1fUL << LCD_PAL43_G04_0_Pos) /*!< LCD PAL43: G04_0 Mask */
+#define LCD_PAL43_B04_0_Pos 10 /*!< LCD PAL43: B04_0 Position */
+#define LCD_PAL43_B04_0_Msk (0x1fUL << LCD_PAL43_B04_0_Pos) /*!< LCD PAL43: B04_0 Mask */
+#define LCD_PAL43_I0_Pos 15 /*!< LCD PAL43: I0 Position */
+#define LCD_PAL43_I0_Msk (0x01UL << LCD_PAL43_I0_Pos) /*!< LCD PAL43: I0 Mask */
+#define LCD_PAL43_R14_0_Pos 16 /*!< LCD PAL43: R14_0 Position */
+#define LCD_PAL43_R14_0_Msk (0x1fUL << LCD_PAL43_R14_0_Pos) /*!< LCD PAL43: R14_0 Mask */
+#define LCD_PAL43_G14_0_Pos 21 /*!< LCD PAL43: G14_0 Position */
+#define LCD_PAL43_G14_0_Msk (0x1fUL << LCD_PAL43_G14_0_Pos) /*!< LCD PAL43: G14_0 Mask */
+#define LCD_PAL43_B14_0_Pos 26 /*!< LCD PAL43: B14_0 Position */
+#define LCD_PAL43_B14_0_Msk (0x1fUL << LCD_PAL43_B14_0_Pos) /*!< LCD PAL43: B14_0 Mask */
+#define LCD_PAL43_I1_Pos 31 /*!< LCD PAL43: I1 Position */
+#define LCD_PAL43_I1_Msk (0x01UL << LCD_PAL43_I1_Pos) /*!< LCD PAL43: I1 Mask */
+
+// ---------------------------------------- LCD_PAL44 -------------------------------------------
+#define LCD_PAL44_R04_0_Pos 0 /*!< LCD PAL44: R04_0 Position */
+#define LCD_PAL44_R04_0_Msk (0x1fUL << LCD_PAL44_R04_0_Pos) /*!< LCD PAL44: R04_0 Mask */
+#define LCD_PAL44_G04_0_Pos 5 /*!< LCD PAL44: G04_0 Position */
+#define LCD_PAL44_G04_0_Msk (0x1fUL << LCD_PAL44_G04_0_Pos) /*!< LCD PAL44: G04_0 Mask */
+#define LCD_PAL44_B04_0_Pos 10 /*!< LCD PAL44: B04_0 Position */
+#define LCD_PAL44_B04_0_Msk (0x1fUL << LCD_PAL44_B04_0_Pos) /*!< LCD PAL44: B04_0 Mask */
+#define LCD_PAL44_I0_Pos 15 /*!< LCD PAL44: I0 Position */
+#define LCD_PAL44_I0_Msk (0x01UL << LCD_PAL44_I0_Pos) /*!< LCD PAL44: I0 Mask */
+#define LCD_PAL44_R14_0_Pos 16 /*!< LCD PAL44: R14_0 Position */
+#define LCD_PAL44_R14_0_Msk (0x1fUL << LCD_PAL44_R14_0_Pos) /*!< LCD PAL44: R14_0 Mask */
+#define LCD_PAL44_G14_0_Pos 21 /*!< LCD PAL44: G14_0 Position */
+#define LCD_PAL44_G14_0_Msk (0x1fUL << LCD_PAL44_G14_0_Pos) /*!< LCD PAL44: G14_0 Mask */
+#define LCD_PAL44_B14_0_Pos 26 /*!< LCD PAL44: B14_0 Position */
+#define LCD_PAL44_B14_0_Msk (0x1fUL << LCD_PAL44_B14_0_Pos) /*!< LCD PAL44: B14_0 Mask */
+#define LCD_PAL44_I1_Pos 31 /*!< LCD PAL44: I1 Position */
+#define LCD_PAL44_I1_Msk (0x01UL << LCD_PAL44_I1_Pos) /*!< LCD PAL44: I1 Mask */
+
+// ---------------------------------------- LCD_PAL45 -------------------------------------------
+#define LCD_PAL45_R04_0_Pos 0 /*!< LCD PAL45: R04_0 Position */
+#define LCD_PAL45_R04_0_Msk (0x1fUL << LCD_PAL45_R04_0_Pos) /*!< LCD PAL45: R04_0 Mask */
+#define LCD_PAL45_G04_0_Pos 5 /*!< LCD PAL45: G04_0 Position */
+#define LCD_PAL45_G04_0_Msk (0x1fUL << LCD_PAL45_G04_0_Pos) /*!< LCD PAL45: G04_0 Mask */
+#define LCD_PAL45_B04_0_Pos 10 /*!< LCD PAL45: B04_0 Position */
+#define LCD_PAL45_B04_0_Msk (0x1fUL << LCD_PAL45_B04_0_Pos) /*!< LCD PAL45: B04_0 Mask */
+#define LCD_PAL45_I0_Pos 15 /*!< LCD PAL45: I0 Position */
+#define LCD_PAL45_I0_Msk (0x01UL << LCD_PAL45_I0_Pos) /*!< LCD PAL45: I0 Mask */
+#define LCD_PAL45_R14_0_Pos 16 /*!< LCD PAL45: R14_0 Position */
+#define LCD_PAL45_R14_0_Msk (0x1fUL << LCD_PAL45_R14_0_Pos) /*!< LCD PAL45: R14_0 Mask */
+#define LCD_PAL45_G14_0_Pos 21 /*!< LCD PAL45: G14_0 Position */
+#define LCD_PAL45_G14_0_Msk (0x1fUL << LCD_PAL45_G14_0_Pos) /*!< LCD PAL45: G14_0 Mask */
+#define LCD_PAL45_B14_0_Pos 26 /*!< LCD PAL45: B14_0 Position */
+#define LCD_PAL45_B14_0_Msk (0x1fUL << LCD_PAL45_B14_0_Pos) /*!< LCD PAL45: B14_0 Mask */
+#define LCD_PAL45_I1_Pos 31 /*!< LCD PAL45: I1 Position */
+#define LCD_PAL45_I1_Msk (0x01UL << LCD_PAL45_I1_Pos) /*!< LCD PAL45: I1 Mask */
+
+// ---------------------------------------- LCD_PAL46 -------------------------------------------
+#define LCD_PAL46_R04_0_Pos 0 /*!< LCD PAL46: R04_0 Position */
+#define LCD_PAL46_R04_0_Msk (0x1fUL << LCD_PAL46_R04_0_Pos) /*!< LCD PAL46: R04_0 Mask */
+#define LCD_PAL46_G04_0_Pos 5 /*!< LCD PAL46: G04_0 Position */
+#define LCD_PAL46_G04_0_Msk (0x1fUL << LCD_PAL46_G04_0_Pos) /*!< LCD PAL46: G04_0 Mask */
+#define LCD_PAL46_B04_0_Pos 10 /*!< LCD PAL46: B04_0 Position */
+#define LCD_PAL46_B04_0_Msk (0x1fUL << LCD_PAL46_B04_0_Pos) /*!< LCD PAL46: B04_0 Mask */
+#define LCD_PAL46_I0_Pos 15 /*!< LCD PAL46: I0 Position */
+#define LCD_PAL46_I0_Msk (0x01UL << LCD_PAL46_I0_Pos) /*!< LCD PAL46: I0 Mask */
+#define LCD_PAL46_R14_0_Pos 16 /*!< LCD PAL46: R14_0 Position */
+#define LCD_PAL46_R14_0_Msk (0x1fUL << LCD_PAL46_R14_0_Pos) /*!< LCD PAL46: R14_0 Mask */
+#define LCD_PAL46_G14_0_Pos 21 /*!< LCD PAL46: G14_0 Position */
+#define LCD_PAL46_G14_0_Msk (0x1fUL << LCD_PAL46_G14_0_Pos) /*!< LCD PAL46: G14_0 Mask */
+#define LCD_PAL46_B14_0_Pos 26 /*!< LCD PAL46: B14_0 Position */
+#define LCD_PAL46_B14_0_Msk (0x1fUL << LCD_PAL46_B14_0_Pos) /*!< LCD PAL46: B14_0 Mask */
+#define LCD_PAL46_I1_Pos 31 /*!< LCD PAL46: I1 Position */
+#define LCD_PAL46_I1_Msk (0x01UL << LCD_PAL46_I1_Pos) /*!< LCD PAL46: I1 Mask */
+
+// ---------------------------------------- LCD_PAL47 -------------------------------------------
+#define LCD_PAL47_R04_0_Pos 0 /*!< LCD PAL47: R04_0 Position */
+#define LCD_PAL47_R04_0_Msk (0x1fUL << LCD_PAL47_R04_0_Pos) /*!< LCD PAL47: R04_0 Mask */
+#define LCD_PAL47_G04_0_Pos 5 /*!< LCD PAL47: G04_0 Position */
+#define LCD_PAL47_G04_0_Msk (0x1fUL << LCD_PAL47_G04_0_Pos) /*!< LCD PAL47: G04_0 Mask */
+#define LCD_PAL47_B04_0_Pos 10 /*!< LCD PAL47: B04_0 Position */
+#define LCD_PAL47_B04_0_Msk (0x1fUL << LCD_PAL47_B04_0_Pos) /*!< LCD PAL47: B04_0 Mask */
+#define LCD_PAL47_I0_Pos 15 /*!< LCD PAL47: I0 Position */
+#define LCD_PAL47_I0_Msk (0x01UL << LCD_PAL47_I0_Pos) /*!< LCD PAL47: I0 Mask */
+#define LCD_PAL47_R14_0_Pos 16 /*!< LCD PAL47: R14_0 Position */
+#define LCD_PAL47_R14_0_Msk (0x1fUL << LCD_PAL47_R14_0_Pos) /*!< LCD PAL47: R14_0 Mask */
+#define LCD_PAL47_G14_0_Pos 21 /*!< LCD PAL47: G14_0 Position */
+#define LCD_PAL47_G14_0_Msk (0x1fUL << LCD_PAL47_G14_0_Pos) /*!< LCD PAL47: G14_0 Mask */
+#define LCD_PAL47_B14_0_Pos 26 /*!< LCD PAL47: B14_0 Position */
+#define LCD_PAL47_B14_0_Msk (0x1fUL << LCD_PAL47_B14_0_Pos) /*!< LCD PAL47: B14_0 Mask */
+#define LCD_PAL47_I1_Pos 31 /*!< LCD PAL47: I1 Position */
+#define LCD_PAL47_I1_Msk (0x01UL << LCD_PAL47_I1_Pos) /*!< LCD PAL47: I1 Mask */
+
+// ---------------------------------------- LCD_PAL48 -------------------------------------------
+#define LCD_PAL48_R04_0_Pos 0 /*!< LCD PAL48: R04_0 Position */
+#define LCD_PAL48_R04_0_Msk (0x1fUL << LCD_PAL48_R04_0_Pos) /*!< LCD PAL48: R04_0 Mask */
+#define LCD_PAL48_G04_0_Pos 5 /*!< LCD PAL48: G04_0 Position */
+#define LCD_PAL48_G04_0_Msk (0x1fUL << LCD_PAL48_G04_0_Pos) /*!< LCD PAL48: G04_0 Mask */
+#define LCD_PAL48_B04_0_Pos 10 /*!< LCD PAL48: B04_0 Position */
+#define LCD_PAL48_B04_0_Msk (0x1fUL << LCD_PAL48_B04_0_Pos) /*!< LCD PAL48: B04_0 Mask */
+#define LCD_PAL48_I0_Pos 15 /*!< LCD PAL48: I0 Position */
+#define LCD_PAL48_I0_Msk (0x01UL << LCD_PAL48_I0_Pos) /*!< LCD PAL48: I0 Mask */
+#define LCD_PAL48_R14_0_Pos 16 /*!< LCD PAL48: R14_0 Position */
+#define LCD_PAL48_R14_0_Msk (0x1fUL << LCD_PAL48_R14_0_Pos) /*!< LCD PAL48: R14_0 Mask */
+#define LCD_PAL48_G14_0_Pos 21 /*!< LCD PAL48: G14_0 Position */
+#define LCD_PAL48_G14_0_Msk (0x1fUL << LCD_PAL48_G14_0_Pos) /*!< LCD PAL48: G14_0 Mask */
+#define LCD_PAL48_B14_0_Pos 26 /*!< LCD PAL48: B14_0 Position */
+#define LCD_PAL48_B14_0_Msk (0x1fUL << LCD_PAL48_B14_0_Pos) /*!< LCD PAL48: B14_0 Mask */
+#define LCD_PAL48_I1_Pos 31 /*!< LCD PAL48: I1 Position */
+#define LCD_PAL48_I1_Msk (0x01UL << LCD_PAL48_I1_Pos) /*!< LCD PAL48: I1 Mask */
+
+// ---------------------------------------- LCD_PAL49 -------------------------------------------
+#define LCD_PAL49_R04_0_Pos 0 /*!< LCD PAL49: R04_0 Position */
+#define LCD_PAL49_R04_0_Msk (0x1fUL << LCD_PAL49_R04_0_Pos) /*!< LCD PAL49: R04_0 Mask */
+#define LCD_PAL49_G04_0_Pos 5 /*!< LCD PAL49: G04_0 Position */
+#define LCD_PAL49_G04_0_Msk (0x1fUL << LCD_PAL49_G04_0_Pos) /*!< LCD PAL49: G04_0 Mask */
+#define LCD_PAL49_B04_0_Pos 10 /*!< LCD PAL49: B04_0 Position */
+#define LCD_PAL49_B04_0_Msk (0x1fUL << LCD_PAL49_B04_0_Pos) /*!< LCD PAL49: B04_0 Mask */
+#define LCD_PAL49_I0_Pos 15 /*!< LCD PAL49: I0 Position */
+#define LCD_PAL49_I0_Msk (0x01UL << LCD_PAL49_I0_Pos) /*!< LCD PAL49: I0 Mask */
+#define LCD_PAL49_R14_0_Pos 16 /*!< LCD PAL49: R14_0 Position */
+#define LCD_PAL49_R14_0_Msk (0x1fUL << LCD_PAL49_R14_0_Pos) /*!< LCD PAL49: R14_0 Mask */
+#define LCD_PAL49_G14_0_Pos 21 /*!< LCD PAL49: G14_0 Position */
+#define LCD_PAL49_G14_0_Msk (0x1fUL << LCD_PAL49_G14_0_Pos) /*!< LCD PAL49: G14_0 Mask */
+#define LCD_PAL49_B14_0_Pos 26 /*!< LCD PAL49: B14_0 Position */
+#define LCD_PAL49_B14_0_Msk (0x1fUL << LCD_PAL49_B14_0_Pos) /*!< LCD PAL49: B14_0 Mask */
+#define LCD_PAL49_I1_Pos 31 /*!< LCD PAL49: I1 Position */
+#define LCD_PAL49_I1_Msk (0x01UL << LCD_PAL49_I1_Pos) /*!< LCD PAL49: I1 Mask */
+
+// ---------------------------------------- LCD_PAL50 -------------------------------------------
+#define LCD_PAL50_R04_0_Pos 0 /*!< LCD PAL50: R04_0 Position */
+#define LCD_PAL50_R04_0_Msk (0x1fUL << LCD_PAL50_R04_0_Pos) /*!< LCD PAL50: R04_0 Mask */
+#define LCD_PAL50_G04_0_Pos 5 /*!< LCD PAL50: G04_0 Position */
+#define LCD_PAL50_G04_0_Msk (0x1fUL << LCD_PAL50_G04_0_Pos) /*!< LCD PAL50: G04_0 Mask */
+#define LCD_PAL50_B04_0_Pos 10 /*!< LCD PAL50: B04_0 Position */
+#define LCD_PAL50_B04_0_Msk (0x1fUL << LCD_PAL50_B04_0_Pos) /*!< LCD PAL50: B04_0 Mask */
+#define LCD_PAL50_I0_Pos 15 /*!< LCD PAL50: I0 Position */
+#define LCD_PAL50_I0_Msk (0x01UL << LCD_PAL50_I0_Pos) /*!< LCD PAL50: I0 Mask */
+#define LCD_PAL50_R14_0_Pos 16 /*!< LCD PAL50: R14_0 Position */
+#define LCD_PAL50_R14_0_Msk (0x1fUL << LCD_PAL50_R14_0_Pos) /*!< LCD PAL50: R14_0 Mask */
+#define LCD_PAL50_G14_0_Pos 21 /*!< LCD PAL50: G14_0 Position */
+#define LCD_PAL50_G14_0_Msk (0x1fUL << LCD_PAL50_G14_0_Pos) /*!< LCD PAL50: G14_0 Mask */
+#define LCD_PAL50_B14_0_Pos 26 /*!< LCD PAL50: B14_0 Position */
+#define LCD_PAL50_B14_0_Msk (0x1fUL << LCD_PAL50_B14_0_Pos) /*!< LCD PAL50: B14_0 Mask */
+#define LCD_PAL50_I1_Pos 31 /*!< LCD PAL50: I1 Position */
+#define LCD_PAL50_I1_Msk (0x01UL << LCD_PAL50_I1_Pos) /*!< LCD PAL50: I1 Mask */
+
+// ---------------------------------------- LCD_PAL51 -------------------------------------------
+#define LCD_PAL51_R04_0_Pos 0 /*!< LCD PAL51: R04_0 Position */
+#define LCD_PAL51_R04_0_Msk (0x1fUL << LCD_PAL51_R04_0_Pos) /*!< LCD PAL51: R04_0 Mask */
+#define LCD_PAL51_G04_0_Pos 5 /*!< LCD PAL51: G04_0 Position */
+#define LCD_PAL51_G04_0_Msk (0x1fUL << LCD_PAL51_G04_0_Pos) /*!< LCD PAL51: G04_0 Mask */
+#define LCD_PAL51_B04_0_Pos 10 /*!< LCD PAL51: B04_0 Position */
+#define LCD_PAL51_B04_0_Msk (0x1fUL << LCD_PAL51_B04_0_Pos) /*!< LCD PAL51: B04_0 Mask */
+#define LCD_PAL51_I0_Pos 15 /*!< LCD PAL51: I0 Position */
+#define LCD_PAL51_I0_Msk (0x01UL << LCD_PAL51_I0_Pos) /*!< LCD PAL51: I0 Mask */
+#define LCD_PAL51_R14_0_Pos 16 /*!< LCD PAL51: R14_0 Position */
+#define LCD_PAL51_R14_0_Msk (0x1fUL << LCD_PAL51_R14_0_Pos) /*!< LCD PAL51: R14_0 Mask */
+#define LCD_PAL51_G14_0_Pos 21 /*!< LCD PAL51: G14_0 Position */
+#define LCD_PAL51_G14_0_Msk (0x1fUL << LCD_PAL51_G14_0_Pos) /*!< LCD PAL51: G14_0 Mask */
+#define LCD_PAL51_B14_0_Pos 26 /*!< LCD PAL51: B14_0 Position */
+#define LCD_PAL51_B14_0_Msk (0x1fUL << LCD_PAL51_B14_0_Pos) /*!< LCD PAL51: B14_0 Mask */
+#define LCD_PAL51_I1_Pos 31 /*!< LCD PAL51: I1 Position */
+#define LCD_PAL51_I1_Msk (0x01UL << LCD_PAL51_I1_Pos) /*!< LCD PAL51: I1 Mask */
+
+// ---------------------------------------- LCD_PAL52 -------------------------------------------
+#define LCD_PAL52_R04_0_Pos 0 /*!< LCD PAL52: R04_0 Position */
+#define LCD_PAL52_R04_0_Msk (0x1fUL << LCD_PAL52_R04_0_Pos) /*!< LCD PAL52: R04_0 Mask */
+#define LCD_PAL52_G04_0_Pos 5 /*!< LCD PAL52: G04_0 Position */
+#define LCD_PAL52_G04_0_Msk (0x1fUL << LCD_PAL52_G04_0_Pos) /*!< LCD PAL52: G04_0 Mask */
+#define LCD_PAL52_B04_0_Pos 10 /*!< LCD PAL52: B04_0 Position */
+#define LCD_PAL52_B04_0_Msk (0x1fUL << LCD_PAL52_B04_0_Pos) /*!< LCD PAL52: B04_0 Mask */
+#define LCD_PAL52_I0_Pos 15 /*!< LCD PAL52: I0 Position */
+#define LCD_PAL52_I0_Msk (0x01UL << LCD_PAL52_I0_Pos) /*!< LCD PAL52: I0 Mask */
+#define LCD_PAL52_R14_0_Pos 16 /*!< LCD PAL52: R14_0 Position */
+#define LCD_PAL52_R14_0_Msk (0x1fUL << LCD_PAL52_R14_0_Pos) /*!< LCD PAL52: R14_0 Mask */
+#define LCD_PAL52_G14_0_Pos 21 /*!< LCD PAL52: G14_0 Position */
+#define LCD_PAL52_G14_0_Msk (0x1fUL << LCD_PAL52_G14_0_Pos) /*!< LCD PAL52: G14_0 Mask */
+#define LCD_PAL52_B14_0_Pos 26 /*!< LCD PAL52: B14_0 Position */
+#define LCD_PAL52_B14_0_Msk (0x1fUL << LCD_PAL52_B14_0_Pos) /*!< LCD PAL52: B14_0 Mask */
+#define LCD_PAL52_I1_Pos 31 /*!< LCD PAL52: I1 Position */
+#define LCD_PAL52_I1_Msk (0x01UL << LCD_PAL52_I1_Pos) /*!< LCD PAL52: I1 Mask */
+
+// ---------------------------------------- LCD_PAL53 -------------------------------------------
+#define LCD_PAL53_R04_0_Pos 0 /*!< LCD PAL53: R04_0 Position */
+#define LCD_PAL53_R04_0_Msk (0x1fUL << LCD_PAL53_R04_0_Pos) /*!< LCD PAL53: R04_0 Mask */
+#define LCD_PAL53_G04_0_Pos 5 /*!< LCD PAL53: G04_0 Position */
+#define LCD_PAL53_G04_0_Msk (0x1fUL << LCD_PAL53_G04_0_Pos) /*!< LCD PAL53: G04_0 Mask */
+#define LCD_PAL53_B04_0_Pos 10 /*!< LCD PAL53: B04_0 Position */
+#define LCD_PAL53_B04_0_Msk (0x1fUL << LCD_PAL53_B04_0_Pos) /*!< LCD PAL53: B04_0 Mask */
+#define LCD_PAL53_I0_Pos 15 /*!< LCD PAL53: I0 Position */
+#define LCD_PAL53_I0_Msk (0x01UL << LCD_PAL53_I0_Pos) /*!< LCD PAL53: I0 Mask */
+#define LCD_PAL53_R14_0_Pos 16 /*!< LCD PAL53: R14_0 Position */
+#define LCD_PAL53_R14_0_Msk (0x1fUL << LCD_PAL53_R14_0_Pos) /*!< LCD PAL53: R14_0 Mask */
+#define LCD_PAL53_G14_0_Pos 21 /*!< LCD PAL53: G14_0 Position */
+#define LCD_PAL53_G14_0_Msk (0x1fUL << LCD_PAL53_G14_0_Pos) /*!< LCD PAL53: G14_0 Mask */
+#define LCD_PAL53_B14_0_Pos 26 /*!< LCD PAL53: B14_0 Position */
+#define LCD_PAL53_B14_0_Msk (0x1fUL << LCD_PAL53_B14_0_Pos) /*!< LCD PAL53: B14_0 Mask */
+#define LCD_PAL53_I1_Pos 31 /*!< LCD PAL53: I1 Position */
+#define LCD_PAL53_I1_Msk (0x01UL << LCD_PAL53_I1_Pos) /*!< LCD PAL53: I1 Mask */
+
+// ---------------------------------------- LCD_PAL54 -------------------------------------------
+#define LCD_PAL54_R04_0_Pos 0 /*!< LCD PAL54: R04_0 Position */
+#define LCD_PAL54_R04_0_Msk (0x1fUL << LCD_PAL54_R04_0_Pos) /*!< LCD PAL54: R04_0 Mask */
+#define LCD_PAL54_G04_0_Pos 5 /*!< LCD PAL54: G04_0 Position */
+#define LCD_PAL54_G04_0_Msk (0x1fUL << LCD_PAL54_G04_0_Pos) /*!< LCD PAL54: G04_0 Mask */
+#define LCD_PAL54_B04_0_Pos 10 /*!< LCD PAL54: B04_0 Position */
+#define LCD_PAL54_B04_0_Msk (0x1fUL << LCD_PAL54_B04_0_Pos) /*!< LCD PAL54: B04_0 Mask */
+#define LCD_PAL54_I0_Pos 15 /*!< LCD PAL54: I0 Position */
+#define LCD_PAL54_I0_Msk (0x01UL << LCD_PAL54_I0_Pos) /*!< LCD PAL54: I0 Mask */
+#define LCD_PAL54_R14_0_Pos 16 /*!< LCD PAL54: R14_0 Position */
+#define LCD_PAL54_R14_0_Msk (0x1fUL << LCD_PAL54_R14_0_Pos) /*!< LCD PAL54: R14_0 Mask */
+#define LCD_PAL54_G14_0_Pos 21 /*!< LCD PAL54: G14_0 Position */
+#define LCD_PAL54_G14_0_Msk (0x1fUL << LCD_PAL54_G14_0_Pos) /*!< LCD PAL54: G14_0 Mask */
+#define LCD_PAL54_B14_0_Pos 26 /*!< LCD PAL54: B14_0 Position */
+#define LCD_PAL54_B14_0_Msk (0x1fUL << LCD_PAL54_B14_0_Pos) /*!< LCD PAL54: B14_0 Mask */
+#define LCD_PAL54_I1_Pos 31 /*!< LCD PAL54: I1 Position */
+#define LCD_PAL54_I1_Msk (0x01UL << LCD_PAL54_I1_Pos) /*!< LCD PAL54: I1 Mask */
+
+// ---------------------------------------- LCD_PAL55 -------------------------------------------
+#define LCD_PAL55_R04_0_Pos 0 /*!< LCD PAL55: R04_0 Position */
+#define LCD_PAL55_R04_0_Msk (0x1fUL << LCD_PAL55_R04_0_Pos) /*!< LCD PAL55: R04_0 Mask */
+#define LCD_PAL55_G04_0_Pos 5 /*!< LCD PAL55: G04_0 Position */
+#define LCD_PAL55_G04_0_Msk (0x1fUL << LCD_PAL55_G04_0_Pos) /*!< LCD PAL55: G04_0 Mask */
+#define LCD_PAL55_B04_0_Pos 10 /*!< LCD PAL55: B04_0 Position */
+#define LCD_PAL55_B04_0_Msk (0x1fUL << LCD_PAL55_B04_0_Pos) /*!< LCD PAL55: B04_0 Mask */
+#define LCD_PAL55_I0_Pos 15 /*!< LCD PAL55: I0 Position */
+#define LCD_PAL55_I0_Msk (0x01UL << LCD_PAL55_I0_Pos) /*!< LCD PAL55: I0 Mask */
+#define LCD_PAL55_R14_0_Pos 16 /*!< LCD PAL55: R14_0 Position */
+#define LCD_PAL55_R14_0_Msk (0x1fUL << LCD_PAL55_R14_0_Pos) /*!< LCD PAL55: R14_0 Mask */
+#define LCD_PAL55_G14_0_Pos 21 /*!< LCD PAL55: G14_0 Position */
+#define LCD_PAL55_G14_0_Msk (0x1fUL << LCD_PAL55_G14_0_Pos) /*!< LCD PAL55: G14_0 Mask */
+#define LCD_PAL55_B14_0_Pos 26 /*!< LCD PAL55: B14_0 Position */
+#define LCD_PAL55_B14_0_Msk (0x1fUL << LCD_PAL55_B14_0_Pos) /*!< LCD PAL55: B14_0 Mask */
+#define LCD_PAL55_I1_Pos 31 /*!< LCD PAL55: I1 Position */
+#define LCD_PAL55_I1_Msk (0x01UL << LCD_PAL55_I1_Pos) /*!< LCD PAL55: I1 Mask */
+
+// ---------------------------------------- LCD_PAL56 -------------------------------------------
+#define LCD_PAL56_R04_0_Pos 0 /*!< LCD PAL56: R04_0 Position */
+#define LCD_PAL56_R04_0_Msk (0x1fUL << LCD_PAL56_R04_0_Pos) /*!< LCD PAL56: R04_0 Mask */
+#define LCD_PAL56_G04_0_Pos 5 /*!< LCD PAL56: G04_0 Position */
+#define LCD_PAL56_G04_0_Msk (0x1fUL << LCD_PAL56_G04_0_Pos) /*!< LCD PAL56: G04_0 Mask */
+#define LCD_PAL56_B04_0_Pos 10 /*!< LCD PAL56: B04_0 Position */
+#define LCD_PAL56_B04_0_Msk (0x1fUL << LCD_PAL56_B04_0_Pos) /*!< LCD PAL56: B04_0 Mask */
+#define LCD_PAL56_I0_Pos 15 /*!< LCD PAL56: I0 Position */
+#define LCD_PAL56_I0_Msk (0x01UL << LCD_PAL56_I0_Pos) /*!< LCD PAL56: I0 Mask */
+#define LCD_PAL56_R14_0_Pos 16 /*!< LCD PAL56: R14_0 Position */
+#define LCD_PAL56_R14_0_Msk (0x1fUL << LCD_PAL56_R14_0_Pos) /*!< LCD PAL56: R14_0 Mask */
+#define LCD_PAL56_G14_0_Pos 21 /*!< LCD PAL56: G14_0 Position */
+#define LCD_PAL56_G14_0_Msk (0x1fUL << LCD_PAL56_G14_0_Pos) /*!< LCD PAL56: G14_0 Mask */
+#define LCD_PAL56_B14_0_Pos 26 /*!< LCD PAL56: B14_0 Position */
+#define LCD_PAL56_B14_0_Msk (0x1fUL << LCD_PAL56_B14_0_Pos) /*!< LCD PAL56: B14_0 Mask */
+#define LCD_PAL56_I1_Pos 31 /*!< LCD PAL56: I1 Position */
+#define LCD_PAL56_I1_Msk (0x01UL << LCD_PAL56_I1_Pos) /*!< LCD PAL56: I1 Mask */
+
+// ---------------------------------------- LCD_PAL57 -------------------------------------------
+#define LCD_PAL57_R04_0_Pos 0 /*!< LCD PAL57: R04_0 Position */
+#define LCD_PAL57_R04_0_Msk (0x1fUL << LCD_PAL57_R04_0_Pos) /*!< LCD PAL57: R04_0 Mask */
+#define LCD_PAL57_G04_0_Pos 5 /*!< LCD PAL57: G04_0 Position */
+#define LCD_PAL57_G04_0_Msk (0x1fUL << LCD_PAL57_G04_0_Pos) /*!< LCD PAL57: G04_0 Mask */
+#define LCD_PAL57_B04_0_Pos 10 /*!< LCD PAL57: B04_0 Position */
+#define LCD_PAL57_B04_0_Msk (0x1fUL << LCD_PAL57_B04_0_Pos) /*!< LCD PAL57: B04_0 Mask */
+#define LCD_PAL57_I0_Pos 15 /*!< LCD PAL57: I0 Position */
+#define LCD_PAL57_I0_Msk (0x01UL << LCD_PAL57_I0_Pos) /*!< LCD PAL57: I0 Mask */
+#define LCD_PAL57_R14_0_Pos 16 /*!< LCD PAL57: R14_0 Position */
+#define LCD_PAL57_R14_0_Msk (0x1fUL << LCD_PAL57_R14_0_Pos) /*!< LCD PAL57: R14_0 Mask */
+#define LCD_PAL57_G14_0_Pos 21 /*!< LCD PAL57: G14_0 Position */
+#define LCD_PAL57_G14_0_Msk (0x1fUL << LCD_PAL57_G14_0_Pos) /*!< LCD PAL57: G14_0 Mask */
+#define LCD_PAL57_B14_0_Pos 26 /*!< LCD PAL57: B14_0 Position */
+#define LCD_PAL57_B14_0_Msk (0x1fUL << LCD_PAL57_B14_0_Pos) /*!< LCD PAL57: B14_0 Mask */
+#define LCD_PAL57_I1_Pos 31 /*!< LCD PAL57: I1 Position */
+#define LCD_PAL57_I1_Msk (0x01UL << LCD_PAL57_I1_Pos) /*!< LCD PAL57: I1 Mask */
+
+// ---------------------------------------- LCD_PAL58 -------------------------------------------
+#define LCD_PAL58_R04_0_Pos 0 /*!< LCD PAL58: R04_0 Position */
+#define LCD_PAL58_R04_0_Msk (0x1fUL << LCD_PAL58_R04_0_Pos) /*!< LCD PAL58: R04_0 Mask */
+#define LCD_PAL58_G04_0_Pos 5 /*!< LCD PAL58: G04_0 Position */
+#define LCD_PAL58_G04_0_Msk (0x1fUL << LCD_PAL58_G04_0_Pos) /*!< LCD PAL58: G04_0 Mask */
+#define LCD_PAL58_B04_0_Pos 10 /*!< LCD PAL58: B04_0 Position */
+#define LCD_PAL58_B04_0_Msk (0x1fUL << LCD_PAL58_B04_0_Pos) /*!< LCD PAL58: B04_0 Mask */
+#define LCD_PAL58_I0_Pos 15 /*!< LCD PAL58: I0 Position */
+#define LCD_PAL58_I0_Msk (0x01UL << LCD_PAL58_I0_Pos) /*!< LCD PAL58: I0 Mask */
+#define LCD_PAL58_R14_0_Pos 16 /*!< LCD PAL58: R14_0 Position */
+#define LCD_PAL58_R14_0_Msk (0x1fUL << LCD_PAL58_R14_0_Pos) /*!< LCD PAL58: R14_0 Mask */
+#define LCD_PAL58_G14_0_Pos 21 /*!< LCD PAL58: G14_0 Position */
+#define LCD_PAL58_G14_0_Msk (0x1fUL << LCD_PAL58_G14_0_Pos) /*!< LCD PAL58: G14_0 Mask */
+#define LCD_PAL58_B14_0_Pos 26 /*!< LCD PAL58: B14_0 Position */
+#define LCD_PAL58_B14_0_Msk (0x1fUL << LCD_PAL58_B14_0_Pos) /*!< LCD PAL58: B14_0 Mask */
+#define LCD_PAL58_I1_Pos 31 /*!< LCD PAL58: I1 Position */
+#define LCD_PAL58_I1_Msk (0x01UL << LCD_PAL58_I1_Pos) /*!< LCD PAL58: I1 Mask */
+
+// ---------------------------------------- LCD_PAL59 -------------------------------------------
+#define LCD_PAL59_R04_0_Pos 0 /*!< LCD PAL59: R04_0 Position */
+#define LCD_PAL59_R04_0_Msk (0x1fUL << LCD_PAL59_R04_0_Pos) /*!< LCD PAL59: R04_0 Mask */
+#define LCD_PAL59_G04_0_Pos 5 /*!< LCD PAL59: G04_0 Position */
+#define LCD_PAL59_G04_0_Msk (0x1fUL << LCD_PAL59_G04_0_Pos) /*!< LCD PAL59: G04_0 Mask */
+#define LCD_PAL59_B04_0_Pos 10 /*!< LCD PAL59: B04_0 Position */
+#define LCD_PAL59_B04_0_Msk (0x1fUL << LCD_PAL59_B04_0_Pos) /*!< LCD PAL59: B04_0 Mask */
+#define LCD_PAL59_I0_Pos 15 /*!< LCD PAL59: I0 Position */
+#define LCD_PAL59_I0_Msk (0x01UL << LCD_PAL59_I0_Pos) /*!< LCD PAL59: I0 Mask */
+#define LCD_PAL59_R14_0_Pos 16 /*!< LCD PAL59: R14_0 Position */
+#define LCD_PAL59_R14_0_Msk (0x1fUL << LCD_PAL59_R14_0_Pos) /*!< LCD PAL59: R14_0 Mask */
+#define LCD_PAL59_G14_0_Pos 21 /*!< LCD PAL59: G14_0 Position */
+#define LCD_PAL59_G14_0_Msk (0x1fUL << LCD_PAL59_G14_0_Pos) /*!< LCD PAL59: G14_0 Mask */
+#define LCD_PAL59_B14_0_Pos 26 /*!< LCD PAL59: B14_0 Position */
+#define LCD_PAL59_B14_0_Msk (0x1fUL << LCD_PAL59_B14_0_Pos) /*!< LCD PAL59: B14_0 Mask */
+#define LCD_PAL59_I1_Pos 31 /*!< LCD PAL59: I1 Position */
+#define LCD_PAL59_I1_Msk (0x01UL << LCD_PAL59_I1_Pos) /*!< LCD PAL59: I1 Mask */
+
+// ---------------------------------------- LCD_PAL60 -------------------------------------------
+#define LCD_PAL60_R04_0_Pos 0 /*!< LCD PAL60: R04_0 Position */
+#define LCD_PAL60_R04_0_Msk (0x1fUL << LCD_PAL60_R04_0_Pos) /*!< LCD PAL60: R04_0 Mask */
+#define LCD_PAL60_G04_0_Pos 5 /*!< LCD PAL60: G04_0 Position */
+#define LCD_PAL60_G04_0_Msk (0x1fUL << LCD_PAL60_G04_0_Pos) /*!< LCD PAL60: G04_0 Mask */
+#define LCD_PAL60_B04_0_Pos 10 /*!< LCD PAL60: B04_0 Position */
+#define LCD_PAL60_B04_0_Msk (0x1fUL << LCD_PAL60_B04_0_Pos) /*!< LCD PAL60: B04_0 Mask */
+#define LCD_PAL60_I0_Pos 15 /*!< LCD PAL60: I0 Position */
+#define LCD_PAL60_I0_Msk (0x01UL << LCD_PAL60_I0_Pos) /*!< LCD PAL60: I0 Mask */
+#define LCD_PAL60_R14_0_Pos 16 /*!< LCD PAL60: R14_0 Position */
+#define LCD_PAL60_R14_0_Msk (0x1fUL << LCD_PAL60_R14_0_Pos) /*!< LCD PAL60: R14_0 Mask */
+#define LCD_PAL60_G14_0_Pos 21 /*!< LCD PAL60: G14_0 Position */
+#define LCD_PAL60_G14_0_Msk (0x1fUL << LCD_PAL60_G14_0_Pos) /*!< LCD PAL60: G14_0 Mask */
+#define LCD_PAL60_B14_0_Pos 26 /*!< LCD PAL60: B14_0 Position */
+#define LCD_PAL60_B14_0_Msk (0x1fUL << LCD_PAL60_B14_0_Pos) /*!< LCD PAL60: B14_0 Mask */
+#define LCD_PAL60_I1_Pos 31 /*!< LCD PAL60: I1 Position */
+#define LCD_PAL60_I1_Msk (0x01UL << LCD_PAL60_I1_Pos) /*!< LCD PAL60: I1 Mask */
+
+// ---------------------------------------- LCD_PAL61 -------------------------------------------
+#define LCD_PAL61_R04_0_Pos 0 /*!< LCD PAL61: R04_0 Position */
+#define LCD_PAL61_R04_0_Msk (0x1fUL << LCD_PAL61_R04_0_Pos) /*!< LCD PAL61: R04_0 Mask */
+#define LCD_PAL61_G04_0_Pos 5 /*!< LCD PAL61: G04_0 Position */
+#define LCD_PAL61_G04_0_Msk (0x1fUL << LCD_PAL61_G04_0_Pos) /*!< LCD PAL61: G04_0 Mask */
+#define LCD_PAL61_B04_0_Pos 10 /*!< LCD PAL61: B04_0 Position */
+#define LCD_PAL61_B04_0_Msk (0x1fUL << LCD_PAL61_B04_0_Pos) /*!< LCD PAL61: B04_0 Mask */
+#define LCD_PAL61_I0_Pos 15 /*!< LCD PAL61: I0 Position */
+#define LCD_PAL61_I0_Msk (0x01UL << LCD_PAL61_I0_Pos) /*!< LCD PAL61: I0 Mask */
+#define LCD_PAL61_R14_0_Pos 16 /*!< LCD PAL61: R14_0 Position */
+#define LCD_PAL61_R14_0_Msk (0x1fUL << LCD_PAL61_R14_0_Pos) /*!< LCD PAL61: R14_0 Mask */
+#define LCD_PAL61_G14_0_Pos 21 /*!< LCD PAL61: G14_0 Position */
+#define LCD_PAL61_G14_0_Msk (0x1fUL << LCD_PAL61_G14_0_Pos) /*!< LCD PAL61: G14_0 Mask */
+#define LCD_PAL61_B14_0_Pos 26 /*!< LCD PAL61: B14_0 Position */
+#define LCD_PAL61_B14_0_Msk (0x1fUL << LCD_PAL61_B14_0_Pos) /*!< LCD PAL61: B14_0 Mask */
+#define LCD_PAL61_I1_Pos 31 /*!< LCD PAL61: I1 Position */
+#define LCD_PAL61_I1_Msk (0x01UL << LCD_PAL61_I1_Pos) /*!< LCD PAL61: I1 Mask */
+
+// ---------------------------------------- LCD_PAL62 -------------------------------------------
+#define LCD_PAL62_R04_0_Pos 0 /*!< LCD PAL62: R04_0 Position */
+#define LCD_PAL62_R04_0_Msk (0x1fUL << LCD_PAL62_R04_0_Pos) /*!< LCD PAL62: R04_0 Mask */
+#define LCD_PAL62_G04_0_Pos 5 /*!< LCD PAL62: G04_0 Position */
+#define LCD_PAL62_G04_0_Msk (0x1fUL << LCD_PAL62_G04_0_Pos) /*!< LCD PAL62: G04_0 Mask */
+#define LCD_PAL62_B04_0_Pos 10 /*!< LCD PAL62: B04_0 Position */
+#define LCD_PAL62_B04_0_Msk (0x1fUL << LCD_PAL62_B04_0_Pos) /*!< LCD PAL62: B04_0 Mask */
+#define LCD_PAL62_I0_Pos 15 /*!< LCD PAL62: I0 Position */
+#define LCD_PAL62_I0_Msk (0x01UL << LCD_PAL62_I0_Pos) /*!< LCD PAL62: I0 Mask */
+#define LCD_PAL62_R14_0_Pos 16 /*!< LCD PAL62: R14_0 Position */
+#define LCD_PAL62_R14_0_Msk (0x1fUL << LCD_PAL62_R14_0_Pos) /*!< LCD PAL62: R14_0 Mask */
+#define LCD_PAL62_G14_0_Pos 21 /*!< LCD PAL62: G14_0 Position */
+#define LCD_PAL62_G14_0_Msk (0x1fUL << LCD_PAL62_G14_0_Pos) /*!< LCD PAL62: G14_0 Mask */
+#define LCD_PAL62_B14_0_Pos 26 /*!< LCD PAL62: B14_0 Position */
+#define LCD_PAL62_B14_0_Msk (0x1fUL << LCD_PAL62_B14_0_Pos) /*!< LCD PAL62: B14_0 Mask */
+#define LCD_PAL62_I1_Pos 31 /*!< LCD PAL62: I1 Position */
+#define LCD_PAL62_I1_Msk (0x01UL << LCD_PAL62_I1_Pos) /*!< LCD PAL62: I1 Mask */
+
+// ---------------------------------------- LCD_PAL63 -------------------------------------------
+#define LCD_PAL63_R04_0_Pos 0 /*!< LCD PAL63: R04_0 Position */
+#define LCD_PAL63_R04_0_Msk (0x1fUL << LCD_PAL63_R04_0_Pos) /*!< LCD PAL63: R04_0 Mask */
+#define LCD_PAL63_G04_0_Pos 5 /*!< LCD PAL63: G04_0 Position */
+#define LCD_PAL63_G04_0_Msk (0x1fUL << LCD_PAL63_G04_0_Pos) /*!< LCD PAL63: G04_0 Mask */
+#define LCD_PAL63_B04_0_Pos 10 /*!< LCD PAL63: B04_0 Position */
+#define LCD_PAL63_B04_0_Msk (0x1fUL << LCD_PAL63_B04_0_Pos) /*!< LCD PAL63: B04_0 Mask */
+#define LCD_PAL63_I0_Pos 15 /*!< LCD PAL63: I0 Position */
+#define LCD_PAL63_I0_Msk (0x01UL << LCD_PAL63_I0_Pos) /*!< LCD PAL63: I0 Mask */
+#define LCD_PAL63_R14_0_Pos 16 /*!< LCD PAL63: R14_0 Position */
+#define LCD_PAL63_R14_0_Msk (0x1fUL << LCD_PAL63_R14_0_Pos) /*!< LCD PAL63: R14_0 Mask */
+#define LCD_PAL63_G14_0_Pos 21 /*!< LCD PAL63: G14_0 Position */
+#define LCD_PAL63_G14_0_Msk (0x1fUL << LCD_PAL63_G14_0_Pos) /*!< LCD PAL63: G14_0 Mask */
+#define LCD_PAL63_B14_0_Pos 26 /*!< LCD PAL63: B14_0 Position */
+#define LCD_PAL63_B14_0_Msk (0x1fUL << LCD_PAL63_B14_0_Pos) /*!< LCD PAL63: B14_0 Mask */
+#define LCD_PAL63_I1_Pos 31 /*!< LCD PAL63: I1 Position */
+#define LCD_PAL63_I1_Msk (0x01UL << LCD_PAL63_I1_Pos) /*!< LCD PAL63: I1 Mask */
+
+// ---------------------------------------- LCD_PAL64 -------------------------------------------
+#define LCD_PAL64_R04_0_Pos 0 /*!< LCD PAL64: R04_0 Position */
+#define LCD_PAL64_R04_0_Msk (0x1fUL << LCD_PAL64_R04_0_Pos) /*!< LCD PAL64: R04_0 Mask */
+#define LCD_PAL64_G04_0_Pos 5 /*!< LCD PAL64: G04_0 Position */
+#define LCD_PAL64_G04_0_Msk (0x1fUL << LCD_PAL64_G04_0_Pos) /*!< LCD PAL64: G04_0 Mask */
+#define LCD_PAL64_B04_0_Pos 10 /*!< LCD PAL64: B04_0 Position */
+#define LCD_PAL64_B04_0_Msk (0x1fUL << LCD_PAL64_B04_0_Pos) /*!< LCD PAL64: B04_0 Mask */
+#define LCD_PAL64_I0_Pos 15 /*!< LCD PAL64: I0 Position */
+#define LCD_PAL64_I0_Msk (0x01UL << LCD_PAL64_I0_Pos) /*!< LCD PAL64: I0 Mask */
+#define LCD_PAL64_R14_0_Pos 16 /*!< LCD PAL64: R14_0 Position */
+#define LCD_PAL64_R14_0_Msk (0x1fUL << LCD_PAL64_R14_0_Pos) /*!< LCD PAL64: R14_0 Mask */
+#define LCD_PAL64_G14_0_Pos 21 /*!< LCD PAL64: G14_0 Position */
+#define LCD_PAL64_G14_0_Msk (0x1fUL << LCD_PAL64_G14_0_Pos) /*!< LCD PAL64: G14_0 Mask */
+#define LCD_PAL64_B14_0_Pos 26 /*!< LCD PAL64: B14_0 Position */
+#define LCD_PAL64_B14_0_Msk (0x1fUL << LCD_PAL64_B14_0_Pos) /*!< LCD PAL64: B14_0 Mask */
+#define LCD_PAL64_I1_Pos 31 /*!< LCD PAL64: I1 Position */
+#define LCD_PAL64_I1_Msk (0x01UL << LCD_PAL64_I1_Pos) /*!< LCD PAL64: I1 Mask */
+
+// ---------------------------------------- LCD_PAL65 -------------------------------------------
+#define LCD_PAL65_R04_0_Pos 0 /*!< LCD PAL65: R04_0 Position */
+#define LCD_PAL65_R04_0_Msk (0x1fUL << LCD_PAL65_R04_0_Pos) /*!< LCD PAL65: R04_0 Mask */
+#define LCD_PAL65_G04_0_Pos 5 /*!< LCD PAL65: G04_0 Position */
+#define LCD_PAL65_G04_0_Msk (0x1fUL << LCD_PAL65_G04_0_Pos) /*!< LCD PAL65: G04_0 Mask */
+#define LCD_PAL65_B04_0_Pos 10 /*!< LCD PAL65: B04_0 Position */
+#define LCD_PAL65_B04_0_Msk (0x1fUL << LCD_PAL65_B04_0_Pos) /*!< LCD PAL65: B04_0 Mask */
+#define LCD_PAL65_I0_Pos 15 /*!< LCD PAL65: I0 Position */
+#define LCD_PAL65_I0_Msk (0x01UL << LCD_PAL65_I0_Pos) /*!< LCD PAL65: I0 Mask */
+#define LCD_PAL65_R14_0_Pos 16 /*!< LCD PAL65: R14_0 Position */
+#define LCD_PAL65_R14_0_Msk (0x1fUL << LCD_PAL65_R14_0_Pos) /*!< LCD PAL65: R14_0 Mask */
+#define LCD_PAL65_G14_0_Pos 21 /*!< LCD PAL65: G14_0 Position */
+#define LCD_PAL65_G14_0_Msk (0x1fUL << LCD_PAL65_G14_0_Pos) /*!< LCD PAL65: G14_0 Mask */
+#define LCD_PAL65_B14_0_Pos 26 /*!< LCD PAL65: B14_0 Position */
+#define LCD_PAL65_B14_0_Msk (0x1fUL << LCD_PAL65_B14_0_Pos) /*!< LCD PAL65: B14_0 Mask */
+#define LCD_PAL65_I1_Pos 31 /*!< LCD PAL65: I1 Position */
+#define LCD_PAL65_I1_Msk (0x01UL << LCD_PAL65_I1_Pos) /*!< LCD PAL65: I1 Mask */
+
+// ---------------------------------------- LCD_PAL66 -------------------------------------------
+#define LCD_PAL66_R04_0_Pos 0 /*!< LCD PAL66: R04_0 Position */
+#define LCD_PAL66_R04_0_Msk (0x1fUL << LCD_PAL66_R04_0_Pos) /*!< LCD PAL66: R04_0 Mask */
+#define LCD_PAL66_G04_0_Pos 5 /*!< LCD PAL66: G04_0 Position */
+#define LCD_PAL66_G04_0_Msk (0x1fUL << LCD_PAL66_G04_0_Pos) /*!< LCD PAL66: G04_0 Mask */
+#define LCD_PAL66_B04_0_Pos 10 /*!< LCD PAL66: B04_0 Position */
+#define LCD_PAL66_B04_0_Msk (0x1fUL << LCD_PAL66_B04_0_Pos) /*!< LCD PAL66: B04_0 Mask */
+#define LCD_PAL66_I0_Pos 15 /*!< LCD PAL66: I0 Position */
+#define LCD_PAL66_I0_Msk (0x01UL << LCD_PAL66_I0_Pos) /*!< LCD PAL66: I0 Mask */
+#define LCD_PAL66_R14_0_Pos 16 /*!< LCD PAL66: R14_0 Position */
+#define LCD_PAL66_R14_0_Msk (0x1fUL << LCD_PAL66_R14_0_Pos) /*!< LCD PAL66: R14_0 Mask */
+#define LCD_PAL66_G14_0_Pos 21 /*!< LCD PAL66: G14_0 Position */
+#define LCD_PAL66_G14_0_Msk (0x1fUL << LCD_PAL66_G14_0_Pos) /*!< LCD PAL66: G14_0 Mask */
+#define LCD_PAL66_B14_0_Pos 26 /*!< LCD PAL66: B14_0 Position */
+#define LCD_PAL66_B14_0_Msk (0x1fUL << LCD_PAL66_B14_0_Pos) /*!< LCD PAL66: B14_0 Mask */
+#define LCD_PAL66_I1_Pos 31 /*!< LCD PAL66: I1 Position */
+#define LCD_PAL66_I1_Msk (0x01UL << LCD_PAL66_I1_Pos) /*!< LCD PAL66: I1 Mask */
+
+// ---------------------------------------- LCD_PAL67 -------------------------------------------
+#define LCD_PAL67_R04_0_Pos 0 /*!< LCD PAL67: R04_0 Position */
+#define LCD_PAL67_R04_0_Msk (0x1fUL << LCD_PAL67_R04_0_Pos) /*!< LCD PAL67: R04_0 Mask */
+#define LCD_PAL67_G04_0_Pos 5 /*!< LCD PAL67: G04_0 Position */
+#define LCD_PAL67_G04_0_Msk (0x1fUL << LCD_PAL67_G04_0_Pos) /*!< LCD PAL67: G04_0 Mask */
+#define LCD_PAL67_B04_0_Pos 10 /*!< LCD PAL67: B04_0 Position */
+#define LCD_PAL67_B04_0_Msk (0x1fUL << LCD_PAL67_B04_0_Pos) /*!< LCD PAL67: B04_0 Mask */
+#define LCD_PAL67_I0_Pos 15 /*!< LCD PAL67: I0 Position */
+#define LCD_PAL67_I0_Msk (0x01UL << LCD_PAL67_I0_Pos) /*!< LCD PAL67: I0 Mask */
+#define LCD_PAL67_R14_0_Pos 16 /*!< LCD PAL67: R14_0 Position */
+#define LCD_PAL67_R14_0_Msk (0x1fUL << LCD_PAL67_R14_0_Pos) /*!< LCD PAL67: R14_0 Mask */
+#define LCD_PAL67_G14_0_Pos 21 /*!< LCD PAL67: G14_0 Position */
+#define LCD_PAL67_G14_0_Msk (0x1fUL << LCD_PAL67_G14_0_Pos) /*!< LCD PAL67: G14_0 Mask */
+#define LCD_PAL67_B14_0_Pos 26 /*!< LCD PAL67: B14_0 Position */
+#define LCD_PAL67_B14_0_Msk (0x1fUL << LCD_PAL67_B14_0_Pos) /*!< LCD PAL67: B14_0 Mask */
+#define LCD_PAL67_I1_Pos 31 /*!< LCD PAL67: I1 Position */
+#define LCD_PAL67_I1_Msk (0x01UL << LCD_PAL67_I1_Pos) /*!< LCD PAL67: I1 Mask */
+
+// ---------------------------------------- LCD_PAL68 -------------------------------------------
+#define LCD_PAL68_R04_0_Pos 0 /*!< LCD PAL68: R04_0 Position */
+#define LCD_PAL68_R04_0_Msk (0x1fUL << LCD_PAL68_R04_0_Pos) /*!< LCD PAL68: R04_0 Mask */
+#define LCD_PAL68_G04_0_Pos 5 /*!< LCD PAL68: G04_0 Position */
+#define LCD_PAL68_G04_0_Msk (0x1fUL << LCD_PAL68_G04_0_Pos) /*!< LCD PAL68: G04_0 Mask */
+#define LCD_PAL68_B04_0_Pos 10 /*!< LCD PAL68: B04_0 Position */
+#define LCD_PAL68_B04_0_Msk (0x1fUL << LCD_PAL68_B04_0_Pos) /*!< LCD PAL68: B04_0 Mask */
+#define LCD_PAL68_I0_Pos 15 /*!< LCD PAL68: I0 Position */
+#define LCD_PAL68_I0_Msk (0x01UL << LCD_PAL68_I0_Pos) /*!< LCD PAL68: I0 Mask */
+#define LCD_PAL68_R14_0_Pos 16 /*!< LCD PAL68: R14_0 Position */
+#define LCD_PAL68_R14_0_Msk (0x1fUL << LCD_PAL68_R14_0_Pos) /*!< LCD PAL68: R14_0 Mask */
+#define LCD_PAL68_G14_0_Pos 21 /*!< LCD PAL68: G14_0 Position */
+#define LCD_PAL68_G14_0_Msk (0x1fUL << LCD_PAL68_G14_0_Pos) /*!< LCD PAL68: G14_0 Mask */
+#define LCD_PAL68_B14_0_Pos 26 /*!< LCD PAL68: B14_0 Position */
+#define LCD_PAL68_B14_0_Msk (0x1fUL << LCD_PAL68_B14_0_Pos) /*!< LCD PAL68: B14_0 Mask */
+#define LCD_PAL68_I1_Pos 31 /*!< LCD PAL68: I1 Position */
+#define LCD_PAL68_I1_Msk (0x01UL << LCD_PAL68_I1_Pos) /*!< LCD PAL68: I1 Mask */
+
+// ---------------------------------------- LCD_PAL69 -------------------------------------------
+#define LCD_PAL69_R04_0_Pos 0 /*!< LCD PAL69: R04_0 Position */
+#define LCD_PAL69_R04_0_Msk (0x1fUL << LCD_PAL69_R04_0_Pos) /*!< LCD PAL69: R04_0 Mask */
+#define LCD_PAL69_G04_0_Pos 5 /*!< LCD PAL69: G04_0 Position */
+#define LCD_PAL69_G04_0_Msk (0x1fUL << LCD_PAL69_G04_0_Pos) /*!< LCD PAL69: G04_0 Mask */
+#define LCD_PAL69_B04_0_Pos 10 /*!< LCD PAL69: B04_0 Position */
+#define LCD_PAL69_B04_0_Msk (0x1fUL << LCD_PAL69_B04_0_Pos) /*!< LCD PAL69: B04_0 Mask */
+#define LCD_PAL69_I0_Pos 15 /*!< LCD PAL69: I0 Position */
+#define LCD_PAL69_I0_Msk (0x01UL << LCD_PAL69_I0_Pos) /*!< LCD PAL69: I0 Mask */
+#define LCD_PAL69_R14_0_Pos 16 /*!< LCD PAL69: R14_0 Position */
+#define LCD_PAL69_R14_0_Msk (0x1fUL << LCD_PAL69_R14_0_Pos) /*!< LCD PAL69: R14_0 Mask */
+#define LCD_PAL69_G14_0_Pos 21 /*!< LCD PAL69: G14_0 Position */
+#define LCD_PAL69_G14_0_Msk (0x1fUL << LCD_PAL69_G14_0_Pos) /*!< LCD PAL69: G14_0 Mask */
+#define LCD_PAL69_B14_0_Pos 26 /*!< LCD PAL69: B14_0 Position */
+#define LCD_PAL69_B14_0_Msk (0x1fUL << LCD_PAL69_B14_0_Pos) /*!< LCD PAL69: B14_0 Mask */
+#define LCD_PAL69_I1_Pos 31 /*!< LCD PAL69: I1 Position */
+#define LCD_PAL69_I1_Msk (0x01UL << LCD_PAL69_I1_Pos) /*!< LCD PAL69: I1 Mask */
+
+// ---------------------------------------- LCD_PAL70 -------------------------------------------
+#define LCD_PAL70_R04_0_Pos 0 /*!< LCD PAL70: R04_0 Position */
+#define LCD_PAL70_R04_0_Msk (0x1fUL << LCD_PAL70_R04_0_Pos) /*!< LCD PAL70: R04_0 Mask */
+#define LCD_PAL70_G04_0_Pos 5 /*!< LCD PAL70: G04_0 Position */
+#define LCD_PAL70_G04_0_Msk (0x1fUL << LCD_PAL70_G04_0_Pos) /*!< LCD PAL70: G04_0 Mask */
+#define LCD_PAL70_B04_0_Pos 10 /*!< LCD PAL70: B04_0 Position */
+#define LCD_PAL70_B04_0_Msk (0x1fUL << LCD_PAL70_B04_0_Pos) /*!< LCD PAL70: B04_0 Mask */
+#define LCD_PAL70_I0_Pos 15 /*!< LCD PAL70: I0 Position */
+#define LCD_PAL70_I0_Msk (0x01UL << LCD_PAL70_I0_Pos) /*!< LCD PAL70: I0 Mask */
+#define LCD_PAL70_R14_0_Pos 16 /*!< LCD PAL70: R14_0 Position */
+#define LCD_PAL70_R14_0_Msk (0x1fUL << LCD_PAL70_R14_0_Pos) /*!< LCD PAL70: R14_0 Mask */
+#define LCD_PAL70_G14_0_Pos 21 /*!< LCD PAL70: G14_0 Position */
+#define LCD_PAL70_G14_0_Msk (0x1fUL << LCD_PAL70_G14_0_Pos) /*!< LCD PAL70: G14_0 Mask */
+#define LCD_PAL70_B14_0_Pos 26 /*!< LCD PAL70: B14_0 Position */
+#define LCD_PAL70_B14_0_Msk (0x1fUL << LCD_PAL70_B14_0_Pos) /*!< LCD PAL70: B14_0 Mask */
+#define LCD_PAL70_I1_Pos 31 /*!< LCD PAL70: I1 Position */
+#define LCD_PAL70_I1_Msk (0x01UL << LCD_PAL70_I1_Pos) /*!< LCD PAL70: I1 Mask */
+
+// ---------------------------------------- LCD_PAL71 -------------------------------------------
+#define LCD_PAL71_R04_0_Pos 0 /*!< LCD PAL71: R04_0 Position */
+#define LCD_PAL71_R04_0_Msk (0x1fUL << LCD_PAL71_R04_0_Pos) /*!< LCD PAL71: R04_0 Mask */
+#define LCD_PAL71_G04_0_Pos 5 /*!< LCD PAL71: G04_0 Position */
+#define LCD_PAL71_G04_0_Msk (0x1fUL << LCD_PAL71_G04_0_Pos) /*!< LCD PAL71: G04_0 Mask */
+#define LCD_PAL71_B04_0_Pos 10 /*!< LCD PAL71: B04_0 Position */
+#define LCD_PAL71_B04_0_Msk (0x1fUL << LCD_PAL71_B04_0_Pos) /*!< LCD PAL71: B04_0 Mask */
+#define LCD_PAL71_I0_Pos 15 /*!< LCD PAL71: I0 Position */
+#define LCD_PAL71_I0_Msk (0x01UL << LCD_PAL71_I0_Pos) /*!< LCD PAL71: I0 Mask */
+#define LCD_PAL71_R14_0_Pos 16 /*!< LCD PAL71: R14_0 Position */
+#define LCD_PAL71_R14_0_Msk (0x1fUL << LCD_PAL71_R14_0_Pos) /*!< LCD PAL71: R14_0 Mask */
+#define LCD_PAL71_G14_0_Pos 21 /*!< LCD PAL71: G14_0 Position */
+#define LCD_PAL71_G14_0_Msk (0x1fUL << LCD_PAL71_G14_0_Pos) /*!< LCD PAL71: G14_0 Mask */
+#define LCD_PAL71_B14_0_Pos 26 /*!< LCD PAL71: B14_0 Position */
+#define LCD_PAL71_B14_0_Msk (0x1fUL << LCD_PAL71_B14_0_Pos) /*!< LCD PAL71: B14_0 Mask */
+#define LCD_PAL71_I1_Pos 31 /*!< LCD PAL71: I1 Position */
+#define LCD_PAL71_I1_Msk (0x01UL << LCD_PAL71_I1_Pos) /*!< LCD PAL71: I1 Mask */
+
+// ---------------------------------------- LCD_PAL72 -------------------------------------------
+#define LCD_PAL72_R04_0_Pos 0 /*!< LCD PAL72: R04_0 Position */
+#define LCD_PAL72_R04_0_Msk (0x1fUL << LCD_PAL72_R04_0_Pos) /*!< LCD PAL72: R04_0 Mask */
+#define LCD_PAL72_G04_0_Pos 5 /*!< LCD PAL72: G04_0 Position */
+#define LCD_PAL72_G04_0_Msk (0x1fUL << LCD_PAL72_G04_0_Pos) /*!< LCD PAL72: G04_0 Mask */
+#define LCD_PAL72_B04_0_Pos 10 /*!< LCD PAL72: B04_0 Position */
+#define LCD_PAL72_B04_0_Msk (0x1fUL << LCD_PAL72_B04_0_Pos) /*!< LCD PAL72: B04_0 Mask */
+#define LCD_PAL72_I0_Pos 15 /*!< LCD PAL72: I0 Position */
+#define LCD_PAL72_I0_Msk (0x01UL << LCD_PAL72_I0_Pos) /*!< LCD PAL72: I0 Mask */
+#define LCD_PAL72_R14_0_Pos 16 /*!< LCD PAL72: R14_0 Position */
+#define LCD_PAL72_R14_0_Msk (0x1fUL << LCD_PAL72_R14_0_Pos) /*!< LCD PAL72: R14_0 Mask */
+#define LCD_PAL72_G14_0_Pos 21 /*!< LCD PAL72: G14_0 Position */
+#define LCD_PAL72_G14_0_Msk (0x1fUL << LCD_PAL72_G14_0_Pos) /*!< LCD PAL72: G14_0 Mask */
+#define LCD_PAL72_B14_0_Pos 26 /*!< LCD PAL72: B14_0 Position */
+#define LCD_PAL72_B14_0_Msk (0x1fUL << LCD_PAL72_B14_0_Pos) /*!< LCD PAL72: B14_0 Mask */
+#define LCD_PAL72_I1_Pos 31 /*!< LCD PAL72: I1 Position */
+#define LCD_PAL72_I1_Msk (0x01UL << LCD_PAL72_I1_Pos) /*!< LCD PAL72: I1 Mask */
+
+// ---------------------------------------- LCD_PAL73 -------------------------------------------
+#define LCD_PAL73_R04_0_Pos 0 /*!< LCD PAL73: R04_0 Position */
+#define LCD_PAL73_R04_0_Msk (0x1fUL << LCD_PAL73_R04_0_Pos) /*!< LCD PAL73: R04_0 Mask */
+#define LCD_PAL73_G04_0_Pos 5 /*!< LCD PAL73: G04_0 Position */
+#define LCD_PAL73_G04_0_Msk (0x1fUL << LCD_PAL73_G04_0_Pos) /*!< LCD PAL73: G04_0 Mask */
+#define LCD_PAL73_B04_0_Pos 10 /*!< LCD PAL73: B04_0 Position */
+#define LCD_PAL73_B04_0_Msk (0x1fUL << LCD_PAL73_B04_0_Pos) /*!< LCD PAL73: B04_0 Mask */
+#define LCD_PAL73_I0_Pos 15 /*!< LCD PAL73: I0 Position */
+#define LCD_PAL73_I0_Msk (0x01UL << LCD_PAL73_I0_Pos) /*!< LCD PAL73: I0 Mask */
+#define LCD_PAL73_R14_0_Pos 16 /*!< LCD PAL73: R14_0 Position */
+#define LCD_PAL73_R14_0_Msk (0x1fUL << LCD_PAL73_R14_0_Pos) /*!< LCD PAL73: R14_0 Mask */
+#define LCD_PAL73_G14_0_Pos 21 /*!< LCD PAL73: G14_0 Position */
+#define LCD_PAL73_G14_0_Msk (0x1fUL << LCD_PAL73_G14_0_Pos) /*!< LCD PAL73: G14_0 Mask */
+#define LCD_PAL73_B14_0_Pos 26 /*!< LCD PAL73: B14_0 Position */
+#define LCD_PAL73_B14_0_Msk (0x1fUL << LCD_PAL73_B14_0_Pos) /*!< LCD PAL73: B14_0 Mask */
+#define LCD_PAL73_I1_Pos 31 /*!< LCD PAL73: I1 Position */
+#define LCD_PAL73_I1_Msk (0x01UL << LCD_PAL73_I1_Pos) /*!< LCD PAL73: I1 Mask */
+
+// ---------------------------------------- LCD_PAL74 -------------------------------------------
+#define LCD_PAL74_R04_0_Pos 0 /*!< LCD PAL74: R04_0 Position */
+#define LCD_PAL74_R04_0_Msk (0x1fUL << LCD_PAL74_R04_0_Pos) /*!< LCD PAL74: R04_0 Mask */
+#define LCD_PAL74_G04_0_Pos 5 /*!< LCD PAL74: G04_0 Position */
+#define LCD_PAL74_G04_0_Msk (0x1fUL << LCD_PAL74_G04_0_Pos) /*!< LCD PAL74: G04_0 Mask */
+#define LCD_PAL74_B04_0_Pos 10 /*!< LCD PAL74: B04_0 Position */
+#define LCD_PAL74_B04_0_Msk (0x1fUL << LCD_PAL74_B04_0_Pos) /*!< LCD PAL74: B04_0 Mask */
+#define LCD_PAL74_I0_Pos 15 /*!< LCD PAL74: I0 Position */
+#define LCD_PAL74_I0_Msk (0x01UL << LCD_PAL74_I0_Pos) /*!< LCD PAL74: I0 Mask */
+#define LCD_PAL74_R14_0_Pos 16 /*!< LCD PAL74: R14_0 Position */
+#define LCD_PAL74_R14_0_Msk (0x1fUL << LCD_PAL74_R14_0_Pos) /*!< LCD PAL74: R14_0 Mask */
+#define LCD_PAL74_G14_0_Pos 21 /*!< LCD PAL74: G14_0 Position */
+#define LCD_PAL74_G14_0_Msk (0x1fUL << LCD_PAL74_G14_0_Pos) /*!< LCD PAL74: G14_0 Mask */
+#define LCD_PAL74_B14_0_Pos 26 /*!< LCD PAL74: B14_0 Position */
+#define LCD_PAL74_B14_0_Msk (0x1fUL << LCD_PAL74_B14_0_Pos) /*!< LCD PAL74: B14_0 Mask */
+#define LCD_PAL74_I1_Pos 31 /*!< LCD PAL74: I1 Position */
+#define LCD_PAL74_I1_Msk (0x01UL << LCD_PAL74_I1_Pos) /*!< LCD PAL74: I1 Mask */
+
+// ---------------------------------------- LCD_PAL75 -------------------------------------------
+#define LCD_PAL75_R04_0_Pos 0 /*!< LCD PAL75: R04_0 Position */
+#define LCD_PAL75_R04_0_Msk (0x1fUL << LCD_PAL75_R04_0_Pos) /*!< LCD PAL75: R04_0 Mask */
+#define LCD_PAL75_G04_0_Pos 5 /*!< LCD PAL75: G04_0 Position */
+#define LCD_PAL75_G04_0_Msk (0x1fUL << LCD_PAL75_G04_0_Pos) /*!< LCD PAL75: G04_0 Mask */
+#define LCD_PAL75_B04_0_Pos 10 /*!< LCD PAL75: B04_0 Position */
+#define LCD_PAL75_B04_0_Msk (0x1fUL << LCD_PAL75_B04_0_Pos) /*!< LCD PAL75: B04_0 Mask */
+#define LCD_PAL75_I0_Pos 15 /*!< LCD PAL75: I0 Position */
+#define LCD_PAL75_I0_Msk (0x01UL << LCD_PAL75_I0_Pos) /*!< LCD PAL75: I0 Mask */
+#define LCD_PAL75_R14_0_Pos 16 /*!< LCD PAL75: R14_0 Position */
+#define LCD_PAL75_R14_0_Msk (0x1fUL << LCD_PAL75_R14_0_Pos) /*!< LCD PAL75: R14_0 Mask */
+#define LCD_PAL75_G14_0_Pos 21 /*!< LCD PAL75: G14_0 Position */
+#define LCD_PAL75_G14_0_Msk (0x1fUL << LCD_PAL75_G14_0_Pos) /*!< LCD PAL75: G14_0 Mask */
+#define LCD_PAL75_B14_0_Pos 26 /*!< LCD PAL75: B14_0 Position */
+#define LCD_PAL75_B14_0_Msk (0x1fUL << LCD_PAL75_B14_0_Pos) /*!< LCD PAL75: B14_0 Mask */
+#define LCD_PAL75_I1_Pos 31 /*!< LCD PAL75: I1 Position */
+#define LCD_PAL75_I1_Msk (0x01UL << LCD_PAL75_I1_Pos) /*!< LCD PAL75: I1 Mask */
+
+// ---------------------------------------- LCD_PAL76 -------------------------------------------
+#define LCD_PAL76_R04_0_Pos 0 /*!< LCD PAL76: R04_0 Position */
+#define LCD_PAL76_R04_0_Msk (0x1fUL << LCD_PAL76_R04_0_Pos) /*!< LCD PAL76: R04_0 Mask */
+#define LCD_PAL76_G04_0_Pos 5 /*!< LCD PAL76: G04_0 Position */
+#define LCD_PAL76_G04_0_Msk (0x1fUL << LCD_PAL76_G04_0_Pos) /*!< LCD PAL76: G04_0 Mask */
+#define LCD_PAL76_B04_0_Pos 10 /*!< LCD PAL76: B04_0 Position */
+#define LCD_PAL76_B04_0_Msk (0x1fUL << LCD_PAL76_B04_0_Pos) /*!< LCD PAL76: B04_0 Mask */
+#define LCD_PAL76_I0_Pos 15 /*!< LCD PAL76: I0 Position */
+#define LCD_PAL76_I0_Msk (0x01UL << LCD_PAL76_I0_Pos) /*!< LCD PAL76: I0 Mask */
+#define LCD_PAL76_R14_0_Pos 16 /*!< LCD PAL76: R14_0 Position */
+#define LCD_PAL76_R14_0_Msk (0x1fUL << LCD_PAL76_R14_0_Pos) /*!< LCD PAL76: R14_0 Mask */
+#define LCD_PAL76_G14_0_Pos 21 /*!< LCD PAL76: G14_0 Position */
+#define LCD_PAL76_G14_0_Msk (0x1fUL << LCD_PAL76_G14_0_Pos) /*!< LCD PAL76: G14_0 Mask */
+#define LCD_PAL76_B14_0_Pos 26 /*!< LCD PAL76: B14_0 Position */
+#define LCD_PAL76_B14_0_Msk (0x1fUL << LCD_PAL76_B14_0_Pos) /*!< LCD PAL76: B14_0 Mask */
+#define LCD_PAL76_I1_Pos 31 /*!< LCD PAL76: I1 Position */
+#define LCD_PAL76_I1_Msk (0x01UL << LCD_PAL76_I1_Pos) /*!< LCD PAL76: I1 Mask */
+
+// ---------------------------------------- LCD_PAL77 -------------------------------------------
+#define LCD_PAL77_R04_0_Pos 0 /*!< LCD PAL77: R04_0 Position */
+#define LCD_PAL77_R04_0_Msk (0x1fUL << LCD_PAL77_R04_0_Pos) /*!< LCD PAL77: R04_0 Mask */
+#define LCD_PAL77_G04_0_Pos 5 /*!< LCD PAL77: G04_0 Position */
+#define LCD_PAL77_G04_0_Msk (0x1fUL << LCD_PAL77_G04_0_Pos) /*!< LCD PAL77: G04_0 Mask */
+#define LCD_PAL77_B04_0_Pos 10 /*!< LCD PAL77: B04_0 Position */
+#define LCD_PAL77_B04_0_Msk (0x1fUL << LCD_PAL77_B04_0_Pos) /*!< LCD PAL77: B04_0 Mask */
+#define LCD_PAL77_I0_Pos 15 /*!< LCD PAL77: I0 Position */
+#define LCD_PAL77_I0_Msk (0x01UL << LCD_PAL77_I0_Pos) /*!< LCD PAL77: I0 Mask */
+#define LCD_PAL77_R14_0_Pos 16 /*!< LCD PAL77: R14_0 Position */
+#define LCD_PAL77_R14_0_Msk (0x1fUL << LCD_PAL77_R14_0_Pos) /*!< LCD PAL77: R14_0 Mask */
+#define LCD_PAL77_G14_0_Pos 21 /*!< LCD PAL77: G14_0 Position */
+#define LCD_PAL77_G14_0_Msk (0x1fUL << LCD_PAL77_G14_0_Pos) /*!< LCD PAL77: G14_0 Mask */
+#define LCD_PAL77_B14_0_Pos 26 /*!< LCD PAL77: B14_0 Position */
+#define LCD_PAL77_B14_0_Msk (0x1fUL << LCD_PAL77_B14_0_Pos) /*!< LCD PAL77: B14_0 Mask */
+#define LCD_PAL77_I1_Pos 31 /*!< LCD PAL77: I1 Position */
+#define LCD_PAL77_I1_Msk (0x01UL << LCD_PAL77_I1_Pos) /*!< LCD PAL77: I1 Mask */
+
+// ---------------------------------------- LCD_PAL78 -------------------------------------------
+#define LCD_PAL78_R04_0_Pos 0 /*!< LCD PAL78: R04_0 Position */
+#define LCD_PAL78_R04_0_Msk (0x1fUL << LCD_PAL78_R04_0_Pos) /*!< LCD PAL78: R04_0 Mask */
+#define LCD_PAL78_G04_0_Pos 5 /*!< LCD PAL78: G04_0 Position */
+#define LCD_PAL78_G04_0_Msk (0x1fUL << LCD_PAL78_G04_0_Pos) /*!< LCD PAL78: G04_0 Mask */
+#define LCD_PAL78_B04_0_Pos 10 /*!< LCD PAL78: B04_0 Position */
+#define LCD_PAL78_B04_0_Msk (0x1fUL << LCD_PAL78_B04_0_Pos) /*!< LCD PAL78: B04_0 Mask */
+#define LCD_PAL78_I0_Pos 15 /*!< LCD PAL78: I0 Position */
+#define LCD_PAL78_I0_Msk (0x01UL << LCD_PAL78_I0_Pos) /*!< LCD PAL78: I0 Mask */
+#define LCD_PAL78_R14_0_Pos 16 /*!< LCD PAL78: R14_0 Position */
+#define LCD_PAL78_R14_0_Msk (0x1fUL << LCD_PAL78_R14_0_Pos) /*!< LCD PAL78: R14_0 Mask */
+#define LCD_PAL78_G14_0_Pos 21 /*!< LCD PAL78: G14_0 Position */
+#define LCD_PAL78_G14_0_Msk (0x1fUL << LCD_PAL78_G14_0_Pos) /*!< LCD PAL78: G14_0 Mask */
+#define LCD_PAL78_B14_0_Pos 26 /*!< LCD PAL78: B14_0 Position */
+#define LCD_PAL78_B14_0_Msk (0x1fUL << LCD_PAL78_B14_0_Pos) /*!< LCD PAL78: B14_0 Mask */
+#define LCD_PAL78_I1_Pos 31 /*!< LCD PAL78: I1 Position */
+#define LCD_PAL78_I1_Msk (0x01UL << LCD_PAL78_I1_Pos) /*!< LCD PAL78: I1 Mask */
+
+// ---------------------------------------- LCD_PAL79 -------------------------------------------
+#define LCD_PAL79_R04_0_Pos 0 /*!< LCD PAL79: R04_0 Position */
+#define LCD_PAL79_R04_0_Msk (0x1fUL << LCD_PAL79_R04_0_Pos) /*!< LCD PAL79: R04_0 Mask */
+#define LCD_PAL79_G04_0_Pos 5 /*!< LCD PAL79: G04_0 Position */
+#define LCD_PAL79_G04_0_Msk (0x1fUL << LCD_PAL79_G04_0_Pos) /*!< LCD PAL79: G04_0 Mask */
+#define LCD_PAL79_B04_0_Pos 10 /*!< LCD PAL79: B04_0 Position */
+#define LCD_PAL79_B04_0_Msk (0x1fUL << LCD_PAL79_B04_0_Pos) /*!< LCD PAL79: B04_0 Mask */
+#define LCD_PAL79_I0_Pos 15 /*!< LCD PAL79: I0 Position */
+#define LCD_PAL79_I0_Msk (0x01UL << LCD_PAL79_I0_Pos) /*!< LCD PAL79: I0 Mask */
+#define LCD_PAL79_R14_0_Pos 16 /*!< LCD PAL79: R14_0 Position */
+#define LCD_PAL79_R14_0_Msk (0x1fUL << LCD_PAL79_R14_0_Pos) /*!< LCD PAL79: R14_0 Mask */
+#define LCD_PAL79_G14_0_Pos 21 /*!< LCD PAL79: G14_0 Position */
+#define LCD_PAL79_G14_0_Msk (0x1fUL << LCD_PAL79_G14_0_Pos) /*!< LCD PAL79: G14_0 Mask */
+#define LCD_PAL79_B14_0_Pos 26 /*!< LCD PAL79: B14_0 Position */
+#define LCD_PAL79_B14_0_Msk (0x1fUL << LCD_PAL79_B14_0_Pos) /*!< LCD PAL79: B14_0 Mask */
+#define LCD_PAL79_I1_Pos 31 /*!< LCD PAL79: I1 Position */
+#define LCD_PAL79_I1_Msk (0x01UL << LCD_PAL79_I1_Pos) /*!< LCD PAL79: I1 Mask */
+
+// ---------------------------------------- LCD_PAL80 -------------------------------------------
+#define LCD_PAL80_R04_0_Pos 0 /*!< LCD PAL80: R04_0 Position */
+#define LCD_PAL80_R04_0_Msk (0x1fUL << LCD_PAL80_R04_0_Pos) /*!< LCD PAL80: R04_0 Mask */
+#define LCD_PAL80_G04_0_Pos 5 /*!< LCD PAL80: G04_0 Position */
+#define LCD_PAL80_G04_0_Msk (0x1fUL << LCD_PAL80_G04_0_Pos) /*!< LCD PAL80: G04_0 Mask */
+#define LCD_PAL80_B04_0_Pos 10 /*!< LCD PAL80: B04_0 Position */
+#define LCD_PAL80_B04_0_Msk (0x1fUL << LCD_PAL80_B04_0_Pos) /*!< LCD PAL80: B04_0 Mask */
+#define LCD_PAL80_I0_Pos 15 /*!< LCD PAL80: I0 Position */
+#define LCD_PAL80_I0_Msk (0x01UL << LCD_PAL80_I0_Pos) /*!< LCD PAL80: I0 Mask */
+#define LCD_PAL80_R14_0_Pos 16 /*!< LCD PAL80: R14_0 Position */
+#define LCD_PAL80_R14_0_Msk (0x1fUL << LCD_PAL80_R14_0_Pos) /*!< LCD PAL80: R14_0 Mask */
+#define LCD_PAL80_G14_0_Pos 21 /*!< LCD PAL80: G14_0 Position */
+#define LCD_PAL80_G14_0_Msk (0x1fUL << LCD_PAL80_G14_0_Pos) /*!< LCD PAL80: G14_0 Mask */
+#define LCD_PAL80_B14_0_Pos 26 /*!< LCD PAL80: B14_0 Position */
+#define LCD_PAL80_B14_0_Msk (0x1fUL << LCD_PAL80_B14_0_Pos) /*!< LCD PAL80: B14_0 Mask */
+#define LCD_PAL80_I1_Pos 31 /*!< LCD PAL80: I1 Position */
+#define LCD_PAL80_I1_Msk (0x01UL << LCD_PAL80_I1_Pos) /*!< LCD PAL80: I1 Mask */
+
+// ---------------------------------------- LCD_PAL81 -------------------------------------------
+#define LCD_PAL81_R04_0_Pos 0 /*!< LCD PAL81: R04_0 Position */
+#define LCD_PAL81_R04_0_Msk (0x1fUL << LCD_PAL81_R04_0_Pos) /*!< LCD PAL81: R04_0 Mask */
+#define LCD_PAL81_G04_0_Pos 5 /*!< LCD PAL81: G04_0 Position */
+#define LCD_PAL81_G04_0_Msk (0x1fUL << LCD_PAL81_G04_0_Pos) /*!< LCD PAL81: G04_0 Mask */
+#define LCD_PAL81_B04_0_Pos 10 /*!< LCD PAL81: B04_0 Position */
+#define LCD_PAL81_B04_0_Msk (0x1fUL << LCD_PAL81_B04_0_Pos) /*!< LCD PAL81: B04_0 Mask */
+#define LCD_PAL81_I0_Pos 15 /*!< LCD PAL81: I0 Position */
+#define LCD_PAL81_I0_Msk (0x01UL << LCD_PAL81_I0_Pos) /*!< LCD PAL81: I0 Mask */
+#define LCD_PAL81_R14_0_Pos 16 /*!< LCD PAL81: R14_0 Position */
+#define LCD_PAL81_R14_0_Msk (0x1fUL << LCD_PAL81_R14_0_Pos) /*!< LCD PAL81: R14_0 Mask */
+#define LCD_PAL81_G14_0_Pos 21 /*!< LCD PAL81: G14_0 Position */
+#define LCD_PAL81_G14_0_Msk (0x1fUL << LCD_PAL81_G14_0_Pos) /*!< LCD PAL81: G14_0 Mask */
+#define LCD_PAL81_B14_0_Pos 26 /*!< LCD PAL81: B14_0 Position */
+#define LCD_PAL81_B14_0_Msk (0x1fUL << LCD_PAL81_B14_0_Pos) /*!< LCD PAL81: B14_0 Mask */
+#define LCD_PAL81_I1_Pos 31 /*!< LCD PAL81: I1 Position */
+#define LCD_PAL81_I1_Msk (0x01UL << LCD_PAL81_I1_Pos) /*!< LCD PAL81: I1 Mask */
+
+// ---------------------------------------- LCD_PAL82 -------------------------------------------
+#define LCD_PAL82_R04_0_Pos 0 /*!< LCD PAL82: R04_0 Position */
+#define LCD_PAL82_R04_0_Msk (0x1fUL << LCD_PAL82_R04_0_Pos) /*!< LCD PAL82: R04_0 Mask */
+#define LCD_PAL82_G04_0_Pos 5 /*!< LCD PAL82: G04_0 Position */
+#define LCD_PAL82_G04_0_Msk (0x1fUL << LCD_PAL82_G04_0_Pos) /*!< LCD PAL82: G04_0 Mask */
+#define LCD_PAL82_B04_0_Pos 10 /*!< LCD PAL82: B04_0 Position */
+#define LCD_PAL82_B04_0_Msk (0x1fUL << LCD_PAL82_B04_0_Pos) /*!< LCD PAL82: B04_0 Mask */
+#define LCD_PAL82_I0_Pos 15 /*!< LCD PAL82: I0 Position */
+#define LCD_PAL82_I0_Msk (0x01UL << LCD_PAL82_I0_Pos) /*!< LCD PAL82: I0 Mask */
+#define LCD_PAL82_R14_0_Pos 16 /*!< LCD PAL82: R14_0 Position */
+#define LCD_PAL82_R14_0_Msk (0x1fUL << LCD_PAL82_R14_0_Pos) /*!< LCD PAL82: R14_0 Mask */
+#define LCD_PAL82_G14_0_Pos 21 /*!< LCD PAL82: G14_0 Position */
+#define LCD_PAL82_G14_0_Msk (0x1fUL << LCD_PAL82_G14_0_Pos) /*!< LCD PAL82: G14_0 Mask */
+#define LCD_PAL82_B14_0_Pos 26 /*!< LCD PAL82: B14_0 Position */
+#define LCD_PAL82_B14_0_Msk (0x1fUL << LCD_PAL82_B14_0_Pos) /*!< LCD PAL82: B14_0 Mask */
+#define LCD_PAL82_I1_Pos 31 /*!< LCD PAL82: I1 Position */
+#define LCD_PAL82_I1_Msk (0x01UL << LCD_PAL82_I1_Pos) /*!< LCD PAL82: I1 Mask */
+
+// ---------------------------------------- LCD_PAL83 -------------------------------------------
+#define LCD_PAL83_R04_0_Pos 0 /*!< LCD PAL83: R04_0 Position */
+#define LCD_PAL83_R04_0_Msk (0x1fUL << LCD_PAL83_R04_0_Pos) /*!< LCD PAL83: R04_0 Mask */
+#define LCD_PAL83_G04_0_Pos 5 /*!< LCD PAL83: G04_0 Position */
+#define LCD_PAL83_G04_0_Msk (0x1fUL << LCD_PAL83_G04_0_Pos) /*!< LCD PAL83: G04_0 Mask */
+#define LCD_PAL83_B04_0_Pos 10 /*!< LCD PAL83: B04_0 Position */
+#define LCD_PAL83_B04_0_Msk (0x1fUL << LCD_PAL83_B04_0_Pos) /*!< LCD PAL83: B04_0 Mask */
+#define LCD_PAL83_I0_Pos 15 /*!< LCD PAL83: I0 Position */
+#define LCD_PAL83_I0_Msk (0x01UL << LCD_PAL83_I0_Pos) /*!< LCD PAL83: I0 Mask */
+#define LCD_PAL83_R14_0_Pos 16 /*!< LCD PAL83: R14_0 Position */
+#define LCD_PAL83_R14_0_Msk (0x1fUL << LCD_PAL83_R14_0_Pos) /*!< LCD PAL83: R14_0 Mask */
+#define LCD_PAL83_G14_0_Pos 21 /*!< LCD PAL83: G14_0 Position */
+#define LCD_PAL83_G14_0_Msk (0x1fUL << LCD_PAL83_G14_0_Pos) /*!< LCD PAL83: G14_0 Mask */
+#define LCD_PAL83_B14_0_Pos 26 /*!< LCD PAL83: B14_0 Position */
+#define LCD_PAL83_B14_0_Msk (0x1fUL << LCD_PAL83_B14_0_Pos) /*!< LCD PAL83: B14_0 Mask */
+#define LCD_PAL83_I1_Pos 31 /*!< LCD PAL83: I1 Position */
+#define LCD_PAL83_I1_Msk (0x01UL << LCD_PAL83_I1_Pos) /*!< LCD PAL83: I1 Mask */
+
+// ---------------------------------------- LCD_PAL84 -------------------------------------------
+#define LCD_PAL84_R04_0_Pos 0 /*!< LCD PAL84: R04_0 Position */
+#define LCD_PAL84_R04_0_Msk (0x1fUL << LCD_PAL84_R04_0_Pos) /*!< LCD PAL84: R04_0 Mask */
+#define LCD_PAL84_G04_0_Pos 5 /*!< LCD PAL84: G04_0 Position */
+#define LCD_PAL84_G04_0_Msk (0x1fUL << LCD_PAL84_G04_0_Pos) /*!< LCD PAL84: G04_0 Mask */
+#define LCD_PAL84_B04_0_Pos 10 /*!< LCD PAL84: B04_0 Position */
+#define LCD_PAL84_B04_0_Msk (0x1fUL << LCD_PAL84_B04_0_Pos) /*!< LCD PAL84: B04_0 Mask */
+#define LCD_PAL84_I0_Pos 15 /*!< LCD PAL84: I0 Position */
+#define LCD_PAL84_I0_Msk (0x01UL << LCD_PAL84_I0_Pos) /*!< LCD PAL84: I0 Mask */
+#define LCD_PAL84_R14_0_Pos 16 /*!< LCD PAL84: R14_0 Position */
+#define LCD_PAL84_R14_0_Msk (0x1fUL << LCD_PAL84_R14_0_Pos) /*!< LCD PAL84: R14_0 Mask */
+#define LCD_PAL84_G14_0_Pos 21 /*!< LCD PAL84: G14_0 Position */
+#define LCD_PAL84_G14_0_Msk (0x1fUL << LCD_PAL84_G14_0_Pos) /*!< LCD PAL84: G14_0 Mask */
+#define LCD_PAL84_B14_0_Pos 26 /*!< LCD PAL84: B14_0 Position */
+#define LCD_PAL84_B14_0_Msk (0x1fUL << LCD_PAL84_B14_0_Pos) /*!< LCD PAL84: B14_0 Mask */
+#define LCD_PAL84_I1_Pos 31 /*!< LCD PAL84: I1 Position */
+#define LCD_PAL84_I1_Msk (0x01UL << LCD_PAL84_I1_Pos) /*!< LCD PAL84: I1 Mask */
+
+// ---------------------------------------- LCD_PAL85 -------------------------------------------
+#define LCD_PAL85_R04_0_Pos 0 /*!< LCD PAL85: R04_0 Position */
+#define LCD_PAL85_R04_0_Msk (0x1fUL << LCD_PAL85_R04_0_Pos) /*!< LCD PAL85: R04_0 Mask */
+#define LCD_PAL85_G04_0_Pos 5 /*!< LCD PAL85: G04_0 Position */
+#define LCD_PAL85_G04_0_Msk (0x1fUL << LCD_PAL85_G04_0_Pos) /*!< LCD PAL85: G04_0 Mask */
+#define LCD_PAL85_B04_0_Pos 10 /*!< LCD PAL85: B04_0 Position */
+#define LCD_PAL85_B04_0_Msk (0x1fUL << LCD_PAL85_B04_0_Pos) /*!< LCD PAL85: B04_0 Mask */
+#define LCD_PAL85_I0_Pos 15 /*!< LCD PAL85: I0 Position */
+#define LCD_PAL85_I0_Msk (0x01UL << LCD_PAL85_I0_Pos) /*!< LCD PAL85: I0 Mask */
+#define LCD_PAL85_R14_0_Pos 16 /*!< LCD PAL85: R14_0 Position */
+#define LCD_PAL85_R14_0_Msk (0x1fUL << LCD_PAL85_R14_0_Pos) /*!< LCD PAL85: R14_0 Mask */
+#define LCD_PAL85_G14_0_Pos 21 /*!< LCD PAL85: G14_0 Position */
+#define LCD_PAL85_G14_0_Msk (0x1fUL << LCD_PAL85_G14_0_Pos) /*!< LCD PAL85: G14_0 Mask */
+#define LCD_PAL85_B14_0_Pos 26 /*!< LCD PAL85: B14_0 Position */
+#define LCD_PAL85_B14_0_Msk (0x1fUL << LCD_PAL85_B14_0_Pos) /*!< LCD PAL85: B14_0 Mask */
+#define LCD_PAL85_I1_Pos 31 /*!< LCD PAL85: I1 Position */
+#define LCD_PAL85_I1_Msk (0x01UL << LCD_PAL85_I1_Pos) /*!< LCD PAL85: I1 Mask */
+
+// ---------------------------------------- LCD_PAL86 -------------------------------------------
+#define LCD_PAL86_R04_0_Pos 0 /*!< LCD PAL86: R04_0 Position */
+#define LCD_PAL86_R04_0_Msk (0x1fUL << LCD_PAL86_R04_0_Pos) /*!< LCD PAL86: R04_0 Mask */
+#define LCD_PAL86_G04_0_Pos 5 /*!< LCD PAL86: G04_0 Position */
+#define LCD_PAL86_G04_0_Msk (0x1fUL << LCD_PAL86_G04_0_Pos) /*!< LCD PAL86: G04_0 Mask */
+#define LCD_PAL86_B04_0_Pos 10 /*!< LCD PAL86: B04_0 Position */
+#define LCD_PAL86_B04_0_Msk (0x1fUL << LCD_PAL86_B04_0_Pos) /*!< LCD PAL86: B04_0 Mask */
+#define LCD_PAL86_I0_Pos 15 /*!< LCD PAL86: I0 Position */
+#define LCD_PAL86_I0_Msk (0x01UL << LCD_PAL86_I0_Pos) /*!< LCD PAL86: I0 Mask */
+#define LCD_PAL86_R14_0_Pos 16 /*!< LCD PAL86: R14_0 Position */
+#define LCD_PAL86_R14_0_Msk (0x1fUL << LCD_PAL86_R14_0_Pos) /*!< LCD PAL86: R14_0 Mask */
+#define LCD_PAL86_G14_0_Pos 21 /*!< LCD PAL86: G14_0 Position */
+#define LCD_PAL86_G14_0_Msk (0x1fUL << LCD_PAL86_G14_0_Pos) /*!< LCD PAL86: G14_0 Mask */
+#define LCD_PAL86_B14_0_Pos 26 /*!< LCD PAL86: B14_0 Position */
+#define LCD_PAL86_B14_0_Msk (0x1fUL << LCD_PAL86_B14_0_Pos) /*!< LCD PAL86: B14_0 Mask */
+#define LCD_PAL86_I1_Pos 31 /*!< LCD PAL86: I1 Position */
+#define LCD_PAL86_I1_Msk (0x01UL << LCD_PAL86_I1_Pos) /*!< LCD PAL86: I1 Mask */
+
+// ---------------------------------------- LCD_PAL87 -------------------------------------------
+#define LCD_PAL87_R04_0_Pos 0 /*!< LCD PAL87: R04_0 Position */
+#define LCD_PAL87_R04_0_Msk (0x1fUL << LCD_PAL87_R04_0_Pos) /*!< LCD PAL87: R04_0 Mask */
+#define LCD_PAL87_G04_0_Pos 5 /*!< LCD PAL87: G04_0 Position */
+#define LCD_PAL87_G04_0_Msk (0x1fUL << LCD_PAL87_G04_0_Pos) /*!< LCD PAL87: G04_0 Mask */
+#define LCD_PAL87_B04_0_Pos 10 /*!< LCD PAL87: B04_0 Position */
+#define LCD_PAL87_B04_0_Msk (0x1fUL << LCD_PAL87_B04_0_Pos) /*!< LCD PAL87: B04_0 Mask */
+#define LCD_PAL87_I0_Pos 15 /*!< LCD PAL87: I0 Position */
+#define LCD_PAL87_I0_Msk (0x01UL << LCD_PAL87_I0_Pos) /*!< LCD PAL87: I0 Mask */
+#define LCD_PAL87_R14_0_Pos 16 /*!< LCD PAL87: R14_0 Position */
+#define LCD_PAL87_R14_0_Msk (0x1fUL << LCD_PAL87_R14_0_Pos) /*!< LCD PAL87: R14_0 Mask */
+#define LCD_PAL87_G14_0_Pos 21 /*!< LCD PAL87: G14_0 Position */
+#define LCD_PAL87_G14_0_Msk (0x1fUL << LCD_PAL87_G14_0_Pos) /*!< LCD PAL87: G14_0 Mask */
+#define LCD_PAL87_B14_0_Pos 26 /*!< LCD PAL87: B14_0 Position */
+#define LCD_PAL87_B14_0_Msk (0x1fUL << LCD_PAL87_B14_0_Pos) /*!< LCD PAL87: B14_0 Mask */
+#define LCD_PAL87_I1_Pos 31 /*!< LCD PAL87: I1 Position */
+#define LCD_PAL87_I1_Msk (0x01UL << LCD_PAL87_I1_Pos) /*!< LCD PAL87: I1 Mask */
+
+// ---------------------------------------- LCD_PAL88 -------------------------------------------
+#define LCD_PAL88_R04_0_Pos 0 /*!< LCD PAL88: R04_0 Position */
+#define LCD_PAL88_R04_0_Msk (0x1fUL << LCD_PAL88_R04_0_Pos) /*!< LCD PAL88: R04_0 Mask */
+#define LCD_PAL88_G04_0_Pos 5 /*!< LCD PAL88: G04_0 Position */
+#define LCD_PAL88_G04_0_Msk (0x1fUL << LCD_PAL88_G04_0_Pos) /*!< LCD PAL88: G04_0 Mask */
+#define LCD_PAL88_B04_0_Pos 10 /*!< LCD PAL88: B04_0 Position */
+#define LCD_PAL88_B04_0_Msk (0x1fUL << LCD_PAL88_B04_0_Pos) /*!< LCD PAL88: B04_0 Mask */
+#define LCD_PAL88_I0_Pos 15 /*!< LCD PAL88: I0 Position */
+#define LCD_PAL88_I0_Msk (0x01UL << LCD_PAL88_I0_Pos) /*!< LCD PAL88: I0 Mask */
+#define LCD_PAL88_R14_0_Pos 16 /*!< LCD PAL88: R14_0 Position */
+#define LCD_PAL88_R14_0_Msk (0x1fUL << LCD_PAL88_R14_0_Pos) /*!< LCD PAL88: R14_0 Mask */
+#define LCD_PAL88_G14_0_Pos 21 /*!< LCD PAL88: G14_0 Position */
+#define LCD_PAL88_G14_0_Msk (0x1fUL << LCD_PAL88_G14_0_Pos) /*!< LCD PAL88: G14_0 Mask */
+#define LCD_PAL88_B14_0_Pos 26 /*!< LCD PAL88: B14_0 Position */
+#define LCD_PAL88_B14_0_Msk (0x1fUL << LCD_PAL88_B14_0_Pos) /*!< LCD PAL88: B14_0 Mask */
+#define LCD_PAL88_I1_Pos 31 /*!< LCD PAL88: I1 Position */
+#define LCD_PAL88_I1_Msk (0x01UL << LCD_PAL88_I1_Pos) /*!< LCD PAL88: I1 Mask */
+
+// ---------------------------------------- LCD_PAL89 -------------------------------------------
+#define LCD_PAL89_R04_0_Pos 0 /*!< LCD PAL89: R04_0 Position */
+#define LCD_PAL89_R04_0_Msk (0x1fUL << LCD_PAL89_R04_0_Pos) /*!< LCD PAL89: R04_0 Mask */
+#define LCD_PAL89_G04_0_Pos 5 /*!< LCD PAL89: G04_0 Position */
+#define LCD_PAL89_G04_0_Msk (0x1fUL << LCD_PAL89_G04_0_Pos) /*!< LCD PAL89: G04_0 Mask */
+#define LCD_PAL89_B04_0_Pos 10 /*!< LCD PAL89: B04_0 Position */
+#define LCD_PAL89_B04_0_Msk (0x1fUL << LCD_PAL89_B04_0_Pos) /*!< LCD PAL89: B04_0 Mask */
+#define LCD_PAL89_I0_Pos 15 /*!< LCD PAL89: I0 Position */
+#define LCD_PAL89_I0_Msk (0x01UL << LCD_PAL89_I0_Pos) /*!< LCD PAL89: I0 Mask */
+#define LCD_PAL89_R14_0_Pos 16 /*!< LCD PAL89: R14_0 Position */
+#define LCD_PAL89_R14_0_Msk (0x1fUL << LCD_PAL89_R14_0_Pos) /*!< LCD PAL89: R14_0 Mask */
+#define LCD_PAL89_G14_0_Pos 21 /*!< LCD PAL89: G14_0 Position */
+#define LCD_PAL89_G14_0_Msk (0x1fUL << LCD_PAL89_G14_0_Pos) /*!< LCD PAL89: G14_0 Mask */
+#define LCD_PAL89_B14_0_Pos 26 /*!< LCD PAL89: B14_0 Position */
+#define LCD_PAL89_B14_0_Msk (0x1fUL << LCD_PAL89_B14_0_Pos) /*!< LCD PAL89: B14_0 Mask */
+#define LCD_PAL89_I1_Pos 31 /*!< LCD PAL89: I1 Position */
+#define LCD_PAL89_I1_Msk (0x01UL << LCD_PAL89_I1_Pos) /*!< LCD PAL89: I1 Mask */
+
+// ---------------------------------------- LCD_PAL90 -------------------------------------------
+#define LCD_PAL90_R04_0_Pos 0 /*!< LCD PAL90: R04_0 Position */
+#define LCD_PAL90_R04_0_Msk (0x1fUL << LCD_PAL90_R04_0_Pos) /*!< LCD PAL90: R04_0 Mask */
+#define LCD_PAL90_G04_0_Pos 5 /*!< LCD PAL90: G04_0 Position */
+#define LCD_PAL90_G04_0_Msk (0x1fUL << LCD_PAL90_G04_0_Pos) /*!< LCD PAL90: G04_0 Mask */
+#define LCD_PAL90_B04_0_Pos 10 /*!< LCD PAL90: B04_0 Position */
+#define LCD_PAL90_B04_0_Msk (0x1fUL << LCD_PAL90_B04_0_Pos) /*!< LCD PAL90: B04_0 Mask */
+#define LCD_PAL90_I0_Pos 15 /*!< LCD PAL90: I0 Position */
+#define LCD_PAL90_I0_Msk (0x01UL << LCD_PAL90_I0_Pos) /*!< LCD PAL90: I0 Mask */
+#define LCD_PAL90_R14_0_Pos 16 /*!< LCD PAL90: R14_0 Position */
+#define LCD_PAL90_R14_0_Msk (0x1fUL << LCD_PAL90_R14_0_Pos) /*!< LCD PAL90: R14_0 Mask */
+#define LCD_PAL90_G14_0_Pos 21 /*!< LCD PAL90: G14_0 Position */
+#define LCD_PAL90_G14_0_Msk (0x1fUL << LCD_PAL90_G14_0_Pos) /*!< LCD PAL90: G14_0 Mask */
+#define LCD_PAL90_B14_0_Pos 26 /*!< LCD PAL90: B14_0 Position */
+#define LCD_PAL90_B14_0_Msk (0x1fUL << LCD_PAL90_B14_0_Pos) /*!< LCD PAL90: B14_0 Mask */
+#define LCD_PAL90_I1_Pos 31 /*!< LCD PAL90: I1 Position */
+#define LCD_PAL90_I1_Msk (0x01UL << LCD_PAL90_I1_Pos) /*!< LCD PAL90: I1 Mask */
+
+// ---------------------------------------- LCD_PAL91 -------------------------------------------
+#define LCD_PAL91_R04_0_Pos 0 /*!< LCD PAL91: R04_0 Position */
+#define LCD_PAL91_R04_0_Msk (0x1fUL << LCD_PAL91_R04_0_Pos) /*!< LCD PAL91: R04_0 Mask */
+#define LCD_PAL91_G04_0_Pos 5 /*!< LCD PAL91: G04_0 Position */
+#define LCD_PAL91_G04_0_Msk (0x1fUL << LCD_PAL91_G04_0_Pos) /*!< LCD PAL91: G04_0 Mask */
+#define LCD_PAL91_B04_0_Pos 10 /*!< LCD PAL91: B04_0 Position */
+#define LCD_PAL91_B04_0_Msk (0x1fUL << LCD_PAL91_B04_0_Pos) /*!< LCD PAL91: B04_0 Mask */
+#define LCD_PAL91_I0_Pos 15 /*!< LCD PAL91: I0 Position */
+#define LCD_PAL91_I0_Msk (0x01UL << LCD_PAL91_I0_Pos) /*!< LCD PAL91: I0 Mask */
+#define LCD_PAL91_R14_0_Pos 16 /*!< LCD PAL91: R14_0 Position */
+#define LCD_PAL91_R14_0_Msk (0x1fUL << LCD_PAL91_R14_0_Pos) /*!< LCD PAL91: R14_0 Mask */
+#define LCD_PAL91_G14_0_Pos 21 /*!< LCD PAL91: G14_0 Position */
+#define LCD_PAL91_G14_0_Msk (0x1fUL << LCD_PAL91_G14_0_Pos) /*!< LCD PAL91: G14_0 Mask */
+#define LCD_PAL91_B14_0_Pos 26 /*!< LCD PAL91: B14_0 Position */
+#define LCD_PAL91_B14_0_Msk (0x1fUL << LCD_PAL91_B14_0_Pos) /*!< LCD PAL91: B14_0 Mask */
+#define LCD_PAL91_I1_Pos 31 /*!< LCD PAL91: I1 Position */
+#define LCD_PAL91_I1_Msk (0x01UL << LCD_PAL91_I1_Pos) /*!< LCD PAL91: I1 Mask */
+
+// ---------------------------------------- LCD_PAL92 -------------------------------------------
+#define LCD_PAL92_R04_0_Pos 0 /*!< LCD PAL92: R04_0 Position */
+#define LCD_PAL92_R04_0_Msk (0x1fUL << LCD_PAL92_R04_0_Pos) /*!< LCD PAL92: R04_0 Mask */
+#define LCD_PAL92_G04_0_Pos 5 /*!< LCD PAL92: G04_0 Position */
+#define LCD_PAL92_G04_0_Msk (0x1fUL << LCD_PAL92_G04_0_Pos) /*!< LCD PAL92: G04_0 Mask */
+#define LCD_PAL92_B04_0_Pos 10 /*!< LCD PAL92: B04_0 Position */
+#define LCD_PAL92_B04_0_Msk (0x1fUL << LCD_PAL92_B04_0_Pos) /*!< LCD PAL92: B04_0 Mask */
+#define LCD_PAL92_I0_Pos 15 /*!< LCD PAL92: I0 Position */
+#define LCD_PAL92_I0_Msk (0x01UL << LCD_PAL92_I0_Pos) /*!< LCD PAL92: I0 Mask */
+#define LCD_PAL92_R14_0_Pos 16 /*!< LCD PAL92: R14_0 Position */
+#define LCD_PAL92_R14_0_Msk (0x1fUL << LCD_PAL92_R14_0_Pos) /*!< LCD PAL92: R14_0 Mask */
+#define LCD_PAL92_G14_0_Pos 21 /*!< LCD PAL92: G14_0 Position */
+#define LCD_PAL92_G14_0_Msk (0x1fUL << LCD_PAL92_G14_0_Pos) /*!< LCD PAL92: G14_0 Mask */
+#define LCD_PAL92_B14_0_Pos 26 /*!< LCD PAL92: B14_0 Position */
+#define LCD_PAL92_B14_0_Msk (0x1fUL << LCD_PAL92_B14_0_Pos) /*!< LCD PAL92: B14_0 Mask */
+#define LCD_PAL92_I1_Pos 31 /*!< LCD PAL92: I1 Position */
+#define LCD_PAL92_I1_Msk (0x01UL << LCD_PAL92_I1_Pos) /*!< LCD PAL92: I1 Mask */
+
+// ---------------------------------------- LCD_PAL93 -------------------------------------------
+#define LCD_PAL93_R04_0_Pos 0 /*!< LCD PAL93: R04_0 Position */
+#define LCD_PAL93_R04_0_Msk (0x1fUL << LCD_PAL93_R04_0_Pos) /*!< LCD PAL93: R04_0 Mask */
+#define LCD_PAL93_G04_0_Pos 5 /*!< LCD PAL93: G04_0 Position */
+#define LCD_PAL93_G04_0_Msk (0x1fUL << LCD_PAL93_G04_0_Pos) /*!< LCD PAL93: G04_0 Mask */
+#define LCD_PAL93_B04_0_Pos 10 /*!< LCD PAL93: B04_0 Position */
+#define LCD_PAL93_B04_0_Msk (0x1fUL << LCD_PAL93_B04_0_Pos) /*!< LCD PAL93: B04_0 Mask */
+#define LCD_PAL93_I0_Pos 15 /*!< LCD PAL93: I0 Position */
+#define LCD_PAL93_I0_Msk (0x01UL << LCD_PAL93_I0_Pos) /*!< LCD PAL93: I0 Mask */
+#define LCD_PAL93_R14_0_Pos 16 /*!< LCD PAL93: R14_0 Position */
+#define LCD_PAL93_R14_0_Msk (0x1fUL << LCD_PAL93_R14_0_Pos) /*!< LCD PAL93: R14_0 Mask */
+#define LCD_PAL93_G14_0_Pos 21 /*!< LCD PAL93: G14_0 Position */
+#define LCD_PAL93_G14_0_Msk (0x1fUL << LCD_PAL93_G14_0_Pos) /*!< LCD PAL93: G14_0 Mask */
+#define LCD_PAL93_B14_0_Pos 26 /*!< LCD PAL93: B14_0 Position */
+#define LCD_PAL93_B14_0_Msk (0x1fUL << LCD_PAL93_B14_0_Pos) /*!< LCD PAL93: B14_0 Mask */
+#define LCD_PAL93_I1_Pos 31 /*!< LCD PAL93: I1 Position */
+#define LCD_PAL93_I1_Msk (0x01UL << LCD_PAL93_I1_Pos) /*!< LCD PAL93: I1 Mask */
+
+// ---------------------------------------- LCD_PAL94 -------------------------------------------
+#define LCD_PAL94_R04_0_Pos 0 /*!< LCD PAL94: R04_0 Position */
+#define LCD_PAL94_R04_0_Msk (0x1fUL << LCD_PAL94_R04_0_Pos) /*!< LCD PAL94: R04_0 Mask */
+#define LCD_PAL94_G04_0_Pos 5 /*!< LCD PAL94: G04_0 Position */
+#define LCD_PAL94_G04_0_Msk (0x1fUL << LCD_PAL94_G04_0_Pos) /*!< LCD PAL94: G04_0 Mask */
+#define LCD_PAL94_B04_0_Pos 10 /*!< LCD PAL94: B04_0 Position */
+#define LCD_PAL94_B04_0_Msk (0x1fUL << LCD_PAL94_B04_0_Pos) /*!< LCD PAL94: B04_0 Mask */
+#define LCD_PAL94_I0_Pos 15 /*!< LCD PAL94: I0 Position */
+#define LCD_PAL94_I0_Msk (0x01UL << LCD_PAL94_I0_Pos) /*!< LCD PAL94: I0 Mask */
+#define LCD_PAL94_R14_0_Pos 16 /*!< LCD PAL94: R14_0 Position */
+#define LCD_PAL94_R14_0_Msk (0x1fUL << LCD_PAL94_R14_0_Pos) /*!< LCD PAL94: R14_0 Mask */
+#define LCD_PAL94_G14_0_Pos 21 /*!< LCD PAL94: G14_0 Position */
+#define LCD_PAL94_G14_0_Msk (0x1fUL << LCD_PAL94_G14_0_Pos) /*!< LCD PAL94: G14_0 Mask */
+#define LCD_PAL94_B14_0_Pos 26 /*!< LCD PAL94: B14_0 Position */
+#define LCD_PAL94_B14_0_Msk (0x1fUL << LCD_PAL94_B14_0_Pos) /*!< LCD PAL94: B14_0 Mask */
+#define LCD_PAL94_I1_Pos 31 /*!< LCD PAL94: I1 Position */
+#define LCD_PAL94_I1_Msk (0x01UL << LCD_PAL94_I1_Pos) /*!< LCD PAL94: I1 Mask */
+
+// ---------------------------------------- LCD_PAL95 -------------------------------------------
+#define LCD_PAL95_R04_0_Pos 0 /*!< LCD PAL95: R04_0 Position */
+#define LCD_PAL95_R04_0_Msk (0x1fUL << LCD_PAL95_R04_0_Pos) /*!< LCD PAL95: R04_0 Mask */
+#define LCD_PAL95_G04_0_Pos 5 /*!< LCD PAL95: G04_0 Position */
+#define LCD_PAL95_G04_0_Msk (0x1fUL << LCD_PAL95_G04_0_Pos) /*!< LCD PAL95: G04_0 Mask */
+#define LCD_PAL95_B04_0_Pos 10 /*!< LCD PAL95: B04_0 Position */
+#define LCD_PAL95_B04_0_Msk (0x1fUL << LCD_PAL95_B04_0_Pos) /*!< LCD PAL95: B04_0 Mask */
+#define LCD_PAL95_I0_Pos 15 /*!< LCD PAL95: I0 Position */
+#define LCD_PAL95_I0_Msk (0x01UL << LCD_PAL95_I0_Pos) /*!< LCD PAL95: I0 Mask */
+#define LCD_PAL95_R14_0_Pos 16 /*!< LCD PAL95: R14_0 Position */
+#define LCD_PAL95_R14_0_Msk (0x1fUL << LCD_PAL95_R14_0_Pos) /*!< LCD PAL95: R14_0 Mask */
+#define LCD_PAL95_G14_0_Pos 21 /*!< LCD PAL95: G14_0 Position */
+#define LCD_PAL95_G14_0_Msk (0x1fUL << LCD_PAL95_G14_0_Pos) /*!< LCD PAL95: G14_0 Mask */
+#define LCD_PAL95_B14_0_Pos 26 /*!< LCD PAL95: B14_0 Position */
+#define LCD_PAL95_B14_0_Msk (0x1fUL << LCD_PAL95_B14_0_Pos) /*!< LCD PAL95: B14_0 Mask */
+#define LCD_PAL95_I1_Pos 31 /*!< LCD PAL95: I1 Position */
+#define LCD_PAL95_I1_Msk (0x01UL << LCD_PAL95_I1_Pos) /*!< LCD PAL95: I1 Mask */
+
+// ---------------------------------------- LCD_PAL96 -------------------------------------------
+#define LCD_PAL96_R04_0_Pos 0 /*!< LCD PAL96: R04_0 Position */
+#define LCD_PAL96_R04_0_Msk (0x1fUL << LCD_PAL96_R04_0_Pos) /*!< LCD PAL96: R04_0 Mask */
+#define LCD_PAL96_G04_0_Pos 5 /*!< LCD PAL96: G04_0 Position */
+#define LCD_PAL96_G04_0_Msk (0x1fUL << LCD_PAL96_G04_0_Pos) /*!< LCD PAL96: G04_0 Mask */
+#define LCD_PAL96_B04_0_Pos 10 /*!< LCD PAL96: B04_0 Position */
+#define LCD_PAL96_B04_0_Msk (0x1fUL << LCD_PAL96_B04_0_Pos) /*!< LCD PAL96: B04_0 Mask */
+#define LCD_PAL96_I0_Pos 15 /*!< LCD PAL96: I0 Position */
+#define LCD_PAL96_I0_Msk (0x01UL << LCD_PAL96_I0_Pos) /*!< LCD PAL96: I0 Mask */
+#define LCD_PAL96_R14_0_Pos 16 /*!< LCD PAL96: R14_0 Position */
+#define LCD_PAL96_R14_0_Msk (0x1fUL << LCD_PAL96_R14_0_Pos) /*!< LCD PAL96: R14_0 Mask */
+#define LCD_PAL96_G14_0_Pos 21 /*!< LCD PAL96: G14_0 Position */
+#define LCD_PAL96_G14_0_Msk (0x1fUL << LCD_PAL96_G14_0_Pos) /*!< LCD PAL96: G14_0 Mask */
+#define LCD_PAL96_B14_0_Pos 26 /*!< LCD PAL96: B14_0 Position */
+#define LCD_PAL96_B14_0_Msk (0x1fUL << LCD_PAL96_B14_0_Pos) /*!< LCD PAL96: B14_0 Mask */
+#define LCD_PAL96_I1_Pos 31 /*!< LCD PAL96: I1 Position */
+#define LCD_PAL96_I1_Msk (0x01UL << LCD_PAL96_I1_Pos) /*!< LCD PAL96: I1 Mask */
+
+// ---------------------------------------- LCD_PAL97 -------------------------------------------
+#define LCD_PAL97_R04_0_Pos 0 /*!< LCD PAL97: R04_0 Position */
+#define LCD_PAL97_R04_0_Msk (0x1fUL << LCD_PAL97_R04_0_Pos) /*!< LCD PAL97: R04_0 Mask */
+#define LCD_PAL97_G04_0_Pos 5 /*!< LCD PAL97: G04_0 Position */
+#define LCD_PAL97_G04_0_Msk (0x1fUL << LCD_PAL97_G04_0_Pos) /*!< LCD PAL97: G04_0 Mask */
+#define LCD_PAL97_B04_0_Pos 10 /*!< LCD PAL97: B04_0 Position */
+#define LCD_PAL97_B04_0_Msk (0x1fUL << LCD_PAL97_B04_0_Pos) /*!< LCD PAL97: B04_0 Mask */
+#define LCD_PAL97_I0_Pos 15 /*!< LCD PAL97: I0 Position */
+#define LCD_PAL97_I0_Msk (0x01UL << LCD_PAL97_I0_Pos) /*!< LCD PAL97: I0 Mask */
+#define LCD_PAL97_R14_0_Pos 16 /*!< LCD PAL97: R14_0 Position */
+#define LCD_PAL97_R14_0_Msk (0x1fUL << LCD_PAL97_R14_0_Pos) /*!< LCD PAL97: R14_0 Mask */
+#define LCD_PAL97_G14_0_Pos 21 /*!< LCD PAL97: G14_0 Position */
+#define LCD_PAL97_G14_0_Msk (0x1fUL << LCD_PAL97_G14_0_Pos) /*!< LCD PAL97: G14_0 Mask */
+#define LCD_PAL97_B14_0_Pos 26 /*!< LCD PAL97: B14_0 Position */
+#define LCD_PAL97_B14_0_Msk (0x1fUL << LCD_PAL97_B14_0_Pos) /*!< LCD PAL97: B14_0 Mask */
+#define LCD_PAL97_I1_Pos 31 /*!< LCD PAL97: I1 Position */
+#define LCD_PAL97_I1_Msk (0x01UL << LCD_PAL97_I1_Pos) /*!< LCD PAL97: I1 Mask */
+
+// ---------------------------------------- LCD_PAL98 -------------------------------------------
+#define LCD_PAL98_R04_0_Pos 0 /*!< LCD PAL98: R04_0 Position */
+#define LCD_PAL98_R04_0_Msk (0x1fUL << LCD_PAL98_R04_0_Pos) /*!< LCD PAL98: R04_0 Mask */
+#define LCD_PAL98_G04_0_Pos 5 /*!< LCD PAL98: G04_0 Position */
+#define LCD_PAL98_G04_0_Msk (0x1fUL << LCD_PAL98_G04_0_Pos) /*!< LCD PAL98: G04_0 Mask */
+#define LCD_PAL98_B04_0_Pos 10 /*!< LCD PAL98: B04_0 Position */
+#define LCD_PAL98_B04_0_Msk (0x1fUL << LCD_PAL98_B04_0_Pos) /*!< LCD PAL98: B04_0 Mask */
+#define LCD_PAL98_I0_Pos 15 /*!< LCD PAL98: I0 Position */
+#define LCD_PAL98_I0_Msk (0x01UL << LCD_PAL98_I0_Pos) /*!< LCD PAL98: I0 Mask */
+#define LCD_PAL98_R14_0_Pos 16 /*!< LCD PAL98: R14_0 Position */
+#define LCD_PAL98_R14_0_Msk (0x1fUL << LCD_PAL98_R14_0_Pos) /*!< LCD PAL98: R14_0 Mask */
+#define LCD_PAL98_G14_0_Pos 21 /*!< LCD PAL98: G14_0 Position */
+#define LCD_PAL98_G14_0_Msk (0x1fUL << LCD_PAL98_G14_0_Pos) /*!< LCD PAL98: G14_0 Mask */
+#define LCD_PAL98_B14_0_Pos 26 /*!< LCD PAL98: B14_0 Position */
+#define LCD_PAL98_B14_0_Msk (0x1fUL << LCD_PAL98_B14_0_Pos) /*!< LCD PAL98: B14_0 Mask */
+#define LCD_PAL98_I1_Pos 31 /*!< LCD PAL98: I1 Position */
+#define LCD_PAL98_I1_Msk (0x01UL << LCD_PAL98_I1_Pos) /*!< LCD PAL98: I1 Mask */
+
+// ---------------------------------------- LCD_PAL99 -------------------------------------------
+#define LCD_PAL99_R04_0_Pos 0 /*!< LCD PAL99: R04_0 Position */
+#define LCD_PAL99_R04_0_Msk (0x1fUL << LCD_PAL99_R04_0_Pos) /*!< LCD PAL99: R04_0 Mask */
+#define LCD_PAL99_G04_0_Pos 5 /*!< LCD PAL99: G04_0 Position */
+#define LCD_PAL99_G04_0_Msk (0x1fUL << LCD_PAL99_G04_0_Pos) /*!< LCD PAL99: G04_0 Mask */
+#define LCD_PAL99_B04_0_Pos 10 /*!< LCD PAL99: B04_0 Position */
+#define LCD_PAL99_B04_0_Msk (0x1fUL << LCD_PAL99_B04_0_Pos) /*!< LCD PAL99: B04_0 Mask */
+#define LCD_PAL99_I0_Pos 15 /*!< LCD PAL99: I0 Position */
+#define LCD_PAL99_I0_Msk (0x01UL << LCD_PAL99_I0_Pos) /*!< LCD PAL99: I0 Mask */
+#define LCD_PAL99_R14_0_Pos 16 /*!< LCD PAL99: R14_0 Position */
+#define LCD_PAL99_R14_0_Msk (0x1fUL << LCD_PAL99_R14_0_Pos) /*!< LCD PAL99: R14_0 Mask */
+#define LCD_PAL99_G14_0_Pos 21 /*!< LCD PAL99: G14_0 Position */
+#define LCD_PAL99_G14_0_Msk (0x1fUL << LCD_PAL99_G14_0_Pos) /*!< LCD PAL99: G14_0 Mask */
+#define LCD_PAL99_B14_0_Pos 26 /*!< LCD PAL99: B14_0 Position */
+#define LCD_PAL99_B14_0_Msk (0x1fUL << LCD_PAL99_B14_0_Pos) /*!< LCD PAL99: B14_0 Mask */
+#define LCD_PAL99_I1_Pos 31 /*!< LCD PAL99: I1 Position */
+#define LCD_PAL99_I1_Msk (0x01UL << LCD_PAL99_I1_Pos) /*!< LCD PAL99: I1 Mask */
+
+// --------------------------------------- LCD_PAL100 -------------------------------------------
+#define LCD_PAL100_R04_0_Pos 0 /*!< LCD PAL100: R04_0 Position */
+#define LCD_PAL100_R04_0_Msk (0x1fUL << LCD_PAL100_R04_0_Pos) /*!< LCD PAL100: R04_0 Mask */
+#define LCD_PAL100_G04_0_Pos 5 /*!< LCD PAL100: G04_0 Position */
+#define LCD_PAL100_G04_0_Msk (0x1fUL << LCD_PAL100_G04_0_Pos) /*!< LCD PAL100: G04_0 Mask */
+#define LCD_PAL100_B04_0_Pos 10 /*!< LCD PAL100: B04_0 Position */
+#define LCD_PAL100_B04_0_Msk (0x1fUL << LCD_PAL100_B04_0_Pos) /*!< LCD PAL100: B04_0 Mask */
+#define LCD_PAL100_I0_Pos 15 /*!< LCD PAL100: I0 Position */
+#define LCD_PAL100_I0_Msk (0x01UL << LCD_PAL100_I0_Pos) /*!< LCD PAL100: I0 Mask */
+#define LCD_PAL100_R14_0_Pos 16 /*!< LCD PAL100: R14_0 Position */
+#define LCD_PAL100_R14_0_Msk (0x1fUL << LCD_PAL100_R14_0_Pos) /*!< LCD PAL100: R14_0 Mask */
+#define LCD_PAL100_G14_0_Pos 21 /*!< LCD PAL100: G14_0 Position */
+#define LCD_PAL100_G14_0_Msk (0x1fUL << LCD_PAL100_G14_0_Pos) /*!< LCD PAL100: G14_0 Mask */
+#define LCD_PAL100_B14_0_Pos 26 /*!< LCD PAL100: B14_0 Position */
+#define LCD_PAL100_B14_0_Msk (0x1fUL << LCD_PAL100_B14_0_Pos) /*!< LCD PAL100: B14_0 Mask */
+#define LCD_PAL100_I1_Pos 31 /*!< LCD PAL100: I1 Position */
+#define LCD_PAL100_I1_Msk (0x01UL << LCD_PAL100_I1_Pos) /*!< LCD PAL100: I1 Mask */
+
+// --------------------------------------- LCD_PAL101 -------------------------------------------
+#define LCD_PAL101_R04_0_Pos 0 /*!< LCD PAL101: R04_0 Position */
+#define LCD_PAL101_R04_0_Msk (0x1fUL << LCD_PAL101_R04_0_Pos) /*!< LCD PAL101: R04_0 Mask */
+#define LCD_PAL101_G04_0_Pos 5 /*!< LCD PAL101: G04_0 Position */
+#define LCD_PAL101_G04_0_Msk (0x1fUL << LCD_PAL101_G04_0_Pos) /*!< LCD PAL101: G04_0 Mask */
+#define LCD_PAL101_B04_0_Pos 10 /*!< LCD PAL101: B04_0 Position */
+#define LCD_PAL101_B04_0_Msk (0x1fUL << LCD_PAL101_B04_0_Pos) /*!< LCD PAL101: B04_0 Mask */
+#define LCD_PAL101_I0_Pos 15 /*!< LCD PAL101: I0 Position */
+#define LCD_PAL101_I0_Msk (0x01UL << LCD_PAL101_I0_Pos) /*!< LCD PAL101: I0 Mask */
+#define LCD_PAL101_R14_0_Pos 16 /*!< LCD PAL101: R14_0 Position */
+#define LCD_PAL101_R14_0_Msk (0x1fUL << LCD_PAL101_R14_0_Pos) /*!< LCD PAL101: R14_0 Mask */
+#define LCD_PAL101_G14_0_Pos 21 /*!< LCD PAL101: G14_0 Position */
+#define LCD_PAL101_G14_0_Msk (0x1fUL << LCD_PAL101_G14_0_Pos) /*!< LCD PAL101: G14_0 Mask */
+#define LCD_PAL101_B14_0_Pos 26 /*!< LCD PAL101: B14_0 Position */
+#define LCD_PAL101_B14_0_Msk (0x1fUL << LCD_PAL101_B14_0_Pos) /*!< LCD PAL101: B14_0 Mask */
+#define LCD_PAL101_I1_Pos 31 /*!< LCD PAL101: I1 Position */
+#define LCD_PAL101_I1_Msk (0x01UL << LCD_PAL101_I1_Pos) /*!< LCD PAL101: I1 Mask */
+
+// --------------------------------------- LCD_PAL102 -------------------------------------------
+#define LCD_PAL102_R04_0_Pos 0 /*!< LCD PAL102: R04_0 Position */
+#define LCD_PAL102_R04_0_Msk (0x1fUL << LCD_PAL102_R04_0_Pos) /*!< LCD PAL102: R04_0 Mask */
+#define LCD_PAL102_G04_0_Pos 5 /*!< LCD PAL102: G04_0 Position */
+#define LCD_PAL102_G04_0_Msk (0x1fUL << LCD_PAL102_G04_0_Pos) /*!< LCD PAL102: G04_0 Mask */
+#define LCD_PAL102_B04_0_Pos 10 /*!< LCD PAL102: B04_0 Position */
+#define LCD_PAL102_B04_0_Msk (0x1fUL << LCD_PAL102_B04_0_Pos) /*!< LCD PAL102: B04_0 Mask */
+#define LCD_PAL102_I0_Pos 15 /*!< LCD PAL102: I0 Position */
+#define LCD_PAL102_I0_Msk (0x01UL << LCD_PAL102_I0_Pos) /*!< LCD PAL102: I0 Mask */
+#define LCD_PAL102_R14_0_Pos 16 /*!< LCD PAL102: R14_0 Position */
+#define LCD_PAL102_R14_0_Msk (0x1fUL << LCD_PAL102_R14_0_Pos) /*!< LCD PAL102: R14_0 Mask */
+#define LCD_PAL102_G14_0_Pos 21 /*!< LCD PAL102: G14_0 Position */
+#define LCD_PAL102_G14_0_Msk (0x1fUL << LCD_PAL102_G14_0_Pos) /*!< LCD PAL102: G14_0 Mask */
+#define LCD_PAL102_B14_0_Pos 26 /*!< LCD PAL102: B14_0 Position */
+#define LCD_PAL102_B14_0_Msk (0x1fUL << LCD_PAL102_B14_0_Pos) /*!< LCD PAL102: B14_0 Mask */
+#define LCD_PAL102_I1_Pos 31 /*!< LCD PAL102: I1 Position */
+#define LCD_PAL102_I1_Msk (0x01UL << LCD_PAL102_I1_Pos) /*!< LCD PAL102: I1 Mask */
+
+// --------------------------------------- LCD_PAL103 -------------------------------------------
+#define LCD_PAL103_R04_0_Pos 0 /*!< LCD PAL103: R04_0 Position */
+#define LCD_PAL103_R04_0_Msk (0x1fUL << LCD_PAL103_R04_0_Pos) /*!< LCD PAL103: R04_0 Mask */
+#define LCD_PAL103_G04_0_Pos 5 /*!< LCD PAL103: G04_0 Position */
+#define LCD_PAL103_G04_0_Msk (0x1fUL << LCD_PAL103_G04_0_Pos) /*!< LCD PAL103: G04_0 Mask */
+#define LCD_PAL103_B04_0_Pos 10 /*!< LCD PAL103: B04_0 Position */
+#define LCD_PAL103_B04_0_Msk (0x1fUL << LCD_PAL103_B04_0_Pos) /*!< LCD PAL103: B04_0 Mask */
+#define LCD_PAL103_I0_Pos 15 /*!< LCD PAL103: I0 Position */
+#define LCD_PAL103_I0_Msk (0x01UL << LCD_PAL103_I0_Pos) /*!< LCD PAL103: I0 Mask */
+#define LCD_PAL103_R14_0_Pos 16 /*!< LCD PAL103: R14_0 Position */
+#define LCD_PAL103_R14_0_Msk (0x1fUL << LCD_PAL103_R14_0_Pos) /*!< LCD PAL103: R14_0 Mask */
+#define LCD_PAL103_G14_0_Pos 21 /*!< LCD PAL103: G14_0 Position */
+#define LCD_PAL103_G14_0_Msk (0x1fUL << LCD_PAL103_G14_0_Pos) /*!< LCD PAL103: G14_0 Mask */
+#define LCD_PAL103_B14_0_Pos 26 /*!< LCD PAL103: B14_0 Position */
+#define LCD_PAL103_B14_0_Msk (0x1fUL << LCD_PAL103_B14_0_Pos) /*!< LCD PAL103: B14_0 Mask */
+#define LCD_PAL103_I1_Pos 31 /*!< LCD PAL103: I1 Position */
+#define LCD_PAL103_I1_Msk (0x01UL << LCD_PAL103_I1_Pos) /*!< LCD PAL103: I1 Mask */
+
+// --------------------------------------- LCD_PAL104 -------------------------------------------
+#define LCD_PAL104_R04_0_Pos 0 /*!< LCD PAL104: R04_0 Position */
+#define LCD_PAL104_R04_0_Msk (0x1fUL << LCD_PAL104_R04_0_Pos) /*!< LCD PAL104: R04_0 Mask */
+#define LCD_PAL104_G04_0_Pos 5 /*!< LCD PAL104: G04_0 Position */
+#define LCD_PAL104_G04_0_Msk (0x1fUL << LCD_PAL104_G04_0_Pos) /*!< LCD PAL104: G04_0 Mask */
+#define LCD_PAL104_B04_0_Pos 10 /*!< LCD PAL104: B04_0 Position */
+#define LCD_PAL104_B04_0_Msk (0x1fUL << LCD_PAL104_B04_0_Pos) /*!< LCD PAL104: B04_0 Mask */
+#define LCD_PAL104_I0_Pos 15 /*!< LCD PAL104: I0 Position */
+#define LCD_PAL104_I0_Msk (0x01UL << LCD_PAL104_I0_Pos) /*!< LCD PAL104: I0 Mask */
+#define LCD_PAL104_R14_0_Pos 16 /*!< LCD PAL104: R14_0 Position */
+#define LCD_PAL104_R14_0_Msk (0x1fUL << LCD_PAL104_R14_0_Pos) /*!< LCD PAL104: R14_0 Mask */
+#define LCD_PAL104_G14_0_Pos 21 /*!< LCD PAL104: G14_0 Position */
+#define LCD_PAL104_G14_0_Msk (0x1fUL << LCD_PAL104_G14_0_Pos) /*!< LCD PAL104: G14_0 Mask */
+#define LCD_PAL104_B14_0_Pos 26 /*!< LCD PAL104: B14_0 Position */
+#define LCD_PAL104_B14_0_Msk (0x1fUL << LCD_PAL104_B14_0_Pos) /*!< LCD PAL104: B14_0 Mask */
+#define LCD_PAL104_I1_Pos 31 /*!< LCD PAL104: I1 Position */
+#define LCD_PAL104_I1_Msk (0x01UL << LCD_PAL104_I1_Pos) /*!< LCD PAL104: I1 Mask */
+
+// --------------------------------------- LCD_PAL105 -------------------------------------------
+#define LCD_PAL105_R04_0_Pos 0 /*!< LCD PAL105: R04_0 Position */
+#define LCD_PAL105_R04_0_Msk (0x1fUL << LCD_PAL105_R04_0_Pos) /*!< LCD PAL105: R04_0 Mask */
+#define LCD_PAL105_G04_0_Pos 5 /*!< LCD PAL105: G04_0 Position */
+#define LCD_PAL105_G04_0_Msk (0x1fUL << LCD_PAL105_G04_0_Pos) /*!< LCD PAL105: G04_0 Mask */
+#define LCD_PAL105_B04_0_Pos 10 /*!< LCD PAL105: B04_0 Position */
+#define LCD_PAL105_B04_0_Msk (0x1fUL << LCD_PAL105_B04_0_Pos) /*!< LCD PAL105: B04_0 Mask */
+#define LCD_PAL105_I0_Pos 15 /*!< LCD PAL105: I0 Position */
+#define LCD_PAL105_I0_Msk (0x01UL << LCD_PAL105_I0_Pos) /*!< LCD PAL105: I0 Mask */
+#define LCD_PAL105_R14_0_Pos 16 /*!< LCD PAL105: R14_0 Position */
+#define LCD_PAL105_R14_0_Msk (0x1fUL << LCD_PAL105_R14_0_Pos) /*!< LCD PAL105: R14_0 Mask */
+#define LCD_PAL105_G14_0_Pos 21 /*!< LCD PAL105: G14_0 Position */
+#define LCD_PAL105_G14_0_Msk (0x1fUL << LCD_PAL105_G14_0_Pos) /*!< LCD PAL105: G14_0 Mask */
+#define LCD_PAL105_B14_0_Pos 26 /*!< LCD PAL105: B14_0 Position */
+#define LCD_PAL105_B14_0_Msk (0x1fUL << LCD_PAL105_B14_0_Pos) /*!< LCD PAL105: B14_0 Mask */
+#define LCD_PAL105_I1_Pos 31 /*!< LCD PAL105: I1 Position */
+#define LCD_PAL105_I1_Msk (0x01UL << LCD_PAL105_I1_Pos) /*!< LCD PAL105: I1 Mask */
+
+// --------------------------------------- LCD_PAL106 -------------------------------------------
+#define LCD_PAL106_R04_0_Pos 0 /*!< LCD PAL106: R04_0 Position */
+#define LCD_PAL106_R04_0_Msk (0x1fUL << LCD_PAL106_R04_0_Pos) /*!< LCD PAL106: R04_0 Mask */
+#define LCD_PAL106_G04_0_Pos 5 /*!< LCD PAL106: G04_0 Position */
+#define LCD_PAL106_G04_0_Msk (0x1fUL << LCD_PAL106_G04_0_Pos) /*!< LCD PAL106: G04_0 Mask */
+#define LCD_PAL106_B04_0_Pos 10 /*!< LCD PAL106: B04_0 Position */
+#define LCD_PAL106_B04_0_Msk (0x1fUL << LCD_PAL106_B04_0_Pos) /*!< LCD PAL106: B04_0 Mask */
+#define LCD_PAL106_I0_Pos 15 /*!< LCD PAL106: I0 Position */
+#define LCD_PAL106_I0_Msk (0x01UL << LCD_PAL106_I0_Pos) /*!< LCD PAL106: I0 Mask */
+#define LCD_PAL106_R14_0_Pos 16 /*!< LCD PAL106: R14_0 Position */
+#define LCD_PAL106_R14_0_Msk (0x1fUL << LCD_PAL106_R14_0_Pos) /*!< LCD PAL106: R14_0 Mask */
+#define LCD_PAL106_G14_0_Pos 21 /*!< LCD PAL106: G14_0 Position */
+#define LCD_PAL106_G14_0_Msk (0x1fUL << LCD_PAL106_G14_0_Pos) /*!< LCD PAL106: G14_0 Mask */
+#define LCD_PAL106_B14_0_Pos 26 /*!< LCD PAL106: B14_0 Position */
+#define LCD_PAL106_B14_0_Msk (0x1fUL << LCD_PAL106_B14_0_Pos) /*!< LCD PAL106: B14_0 Mask */
+#define LCD_PAL106_I1_Pos 31 /*!< LCD PAL106: I1 Position */
+#define LCD_PAL106_I1_Msk (0x01UL << LCD_PAL106_I1_Pos) /*!< LCD PAL106: I1 Mask */
+
+// --------------------------------------- LCD_PAL107 -------------------------------------------
+#define LCD_PAL107_R04_0_Pos 0 /*!< LCD PAL107: R04_0 Position */
+#define LCD_PAL107_R04_0_Msk (0x1fUL << LCD_PAL107_R04_0_Pos) /*!< LCD PAL107: R04_0 Mask */
+#define LCD_PAL107_G04_0_Pos 5 /*!< LCD PAL107: G04_0 Position */
+#define LCD_PAL107_G04_0_Msk (0x1fUL << LCD_PAL107_G04_0_Pos) /*!< LCD PAL107: G04_0 Mask */
+#define LCD_PAL107_B04_0_Pos 10 /*!< LCD PAL107: B04_0 Position */
+#define LCD_PAL107_B04_0_Msk (0x1fUL << LCD_PAL107_B04_0_Pos) /*!< LCD PAL107: B04_0 Mask */
+#define LCD_PAL107_I0_Pos 15 /*!< LCD PAL107: I0 Position */
+#define LCD_PAL107_I0_Msk (0x01UL << LCD_PAL107_I0_Pos) /*!< LCD PAL107: I0 Mask */
+#define LCD_PAL107_R14_0_Pos 16 /*!< LCD PAL107: R14_0 Position */
+#define LCD_PAL107_R14_0_Msk (0x1fUL << LCD_PAL107_R14_0_Pos) /*!< LCD PAL107: R14_0 Mask */
+#define LCD_PAL107_G14_0_Pos 21 /*!< LCD PAL107: G14_0 Position */
+#define LCD_PAL107_G14_0_Msk (0x1fUL << LCD_PAL107_G14_0_Pos) /*!< LCD PAL107: G14_0 Mask */
+#define LCD_PAL107_B14_0_Pos 26 /*!< LCD PAL107: B14_0 Position */
+#define LCD_PAL107_B14_0_Msk (0x1fUL << LCD_PAL107_B14_0_Pos) /*!< LCD PAL107: B14_0 Mask */
+#define LCD_PAL107_I1_Pos 31 /*!< LCD PAL107: I1 Position */
+#define LCD_PAL107_I1_Msk (0x01UL << LCD_PAL107_I1_Pos) /*!< LCD PAL107: I1 Mask */
+
+// --------------------------------------- LCD_PAL108 -------------------------------------------
+#define LCD_PAL108_R04_0_Pos 0 /*!< LCD PAL108: R04_0 Position */
+#define LCD_PAL108_R04_0_Msk (0x1fUL << LCD_PAL108_R04_0_Pos) /*!< LCD PAL108: R04_0 Mask */
+#define LCD_PAL108_G04_0_Pos 5 /*!< LCD PAL108: G04_0 Position */
+#define LCD_PAL108_G04_0_Msk (0x1fUL << LCD_PAL108_G04_0_Pos) /*!< LCD PAL108: G04_0 Mask */
+#define LCD_PAL108_B04_0_Pos 10 /*!< LCD PAL108: B04_0 Position */
+#define LCD_PAL108_B04_0_Msk (0x1fUL << LCD_PAL108_B04_0_Pos) /*!< LCD PAL108: B04_0 Mask */
+#define LCD_PAL108_I0_Pos 15 /*!< LCD PAL108: I0 Position */
+#define LCD_PAL108_I0_Msk (0x01UL << LCD_PAL108_I0_Pos) /*!< LCD PAL108: I0 Mask */
+#define LCD_PAL108_R14_0_Pos 16 /*!< LCD PAL108: R14_0 Position */
+#define LCD_PAL108_R14_0_Msk (0x1fUL << LCD_PAL108_R14_0_Pos) /*!< LCD PAL108: R14_0 Mask */
+#define LCD_PAL108_G14_0_Pos 21 /*!< LCD PAL108: G14_0 Position */
+#define LCD_PAL108_G14_0_Msk (0x1fUL << LCD_PAL108_G14_0_Pos) /*!< LCD PAL108: G14_0 Mask */
+#define LCD_PAL108_B14_0_Pos 26 /*!< LCD PAL108: B14_0 Position */
+#define LCD_PAL108_B14_0_Msk (0x1fUL << LCD_PAL108_B14_0_Pos) /*!< LCD PAL108: B14_0 Mask */
+#define LCD_PAL108_I1_Pos 31 /*!< LCD PAL108: I1 Position */
+#define LCD_PAL108_I1_Msk (0x01UL << LCD_PAL108_I1_Pos) /*!< LCD PAL108: I1 Mask */
+
+// --------------------------------------- LCD_PAL109 -------------------------------------------
+#define LCD_PAL109_R04_0_Pos 0 /*!< LCD PAL109: R04_0 Position */
+#define LCD_PAL109_R04_0_Msk (0x1fUL << LCD_PAL109_R04_0_Pos) /*!< LCD PAL109: R04_0 Mask */
+#define LCD_PAL109_G04_0_Pos 5 /*!< LCD PAL109: G04_0 Position */
+#define LCD_PAL109_G04_0_Msk (0x1fUL << LCD_PAL109_G04_0_Pos) /*!< LCD PAL109: G04_0 Mask */
+#define LCD_PAL109_B04_0_Pos 10 /*!< LCD PAL109: B04_0 Position */
+#define LCD_PAL109_B04_0_Msk (0x1fUL << LCD_PAL109_B04_0_Pos) /*!< LCD PAL109: B04_0 Mask */
+#define LCD_PAL109_I0_Pos 15 /*!< LCD PAL109: I0 Position */
+#define LCD_PAL109_I0_Msk (0x01UL << LCD_PAL109_I0_Pos) /*!< LCD PAL109: I0 Mask */
+#define LCD_PAL109_R14_0_Pos 16 /*!< LCD PAL109: R14_0 Position */
+#define LCD_PAL109_R14_0_Msk (0x1fUL << LCD_PAL109_R14_0_Pos) /*!< LCD PAL109: R14_0 Mask */
+#define LCD_PAL109_G14_0_Pos 21 /*!< LCD PAL109: G14_0 Position */
+#define LCD_PAL109_G14_0_Msk (0x1fUL << LCD_PAL109_G14_0_Pos) /*!< LCD PAL109: G14_0 Mask */
+#define LCD_PAL109_B14_0_Pos 26 /*!< LCD PAL109: B14_0 Position */
+#define LCD_PAL109_B14_0_Msk (0x1fUL << LCD_PAL109_B14_0_Pos) /*!< LCD PAL109: B14_0 Mask */
+#define LCD_PAL109_I1_Pos 31 /*!< LCD PAL109: I1 Position */
+#define LCD_PAL109_I1_Msk (0x01UL << LCD_PAL109_I1_Pos) /*!< LCD PAL109: I1 Mask */
+
+// --------------------------------------- LCD_PAL110 -------------------------------------------
+#define LCD_PAL110_R04_0_Pos 0 /*!< LCD PAL110: R04_0 Position */
+#define LCD_PAL110_R04_0_Msk (0x1fUL << LCD_PAL110_R04_0_Pos) /*!< LCD PAL110: R04_0 Mask */
+#define LCD_PAL110_G04_0_Pos 5 /*!< LCD PAL110: G04_0 Position */
+#define LCD_PAL110_G04_0_Msk (0x1fUL << LCD_PAL110_G04_0_Pos) /*!< LCD PAL110: G04_0 Mask */
+#define LCD_PAL110_B04_0_Pos 10 /*!< LCD PAL110: B04_0 Position */
+#define LCD_PAL110_B04_0_Msk (0x1fUL << LCD_PAL110_B04_0_Pos) /*!< LCD PAL110: B04_0 Mask */
+#define LCD_PAL110_I0_Pos 15 /*!< LCD PAL110: I0 Position */
+#define LCD_PAL110_I0_Msk (0x01UL << LCD_PAL110_I0_Pos) /*!< LCD PAL110: I0 Mask */
+#define LCD_PAL110_R14_0_Pos 16 /*!< LCD PAL110: R14_0 Position */
+#define LCD_PAL110_R14_0_Msk (0x1fUL << LCD_PAL110_R14_0_Pos) /*!< LCD PAL110: R14_0 Mask */
+#define LCD_PAL110_G14_0_Pos 21 /*!< LCD PAL110: G14_0 Position */
+#define LCD_PAL110_G14_0_Msk (0x1fUL << LCD_PAL110_G14_0_Pos) /*!< LCD PAL110: G14_0 Mask */
+#define LCD_PAL110_B14_0_Pos 26 /*!< LCD PAL110: B14_0 Position */
+#define LCD_PAL110_B14_0_Msk (0x1fUL << LCD_PAL110_B14_0_Pos) /*!< LCD PAL110: B14_0 Mask */
+#define LCD_PAL110_I1_Pos 31 /*!< LCD PAL110: I1 Position */
+#define LCD_PAL110_I1_Msk (0x01UL << LCD_PAL110_I1_Pos) /*!< LCD PAL110: I1 Mask */
+
+// --------------------------------------- LCD_PAL111 -------------------------------------------
+#define LCD_PAL111_R04_0_Pos 0 /*!< LCD PAL111: R04_0 Position */
+#define LCD_PAL111_R04_0_Msk (0x1fUL << LCD_PAL111_R04_0_Pos) /*!< LCD PAL111: R04_0 Mask */
+#define LCD_PAL111_G04_0_Pos 5 /*!< LCD PAL111: G04_0 Position */
+#define LCD_PAL111_G04_0_Msk (0x1fUL << LCD_PAL111_G04_0_Pos) /*!< LCD PAL111: G04_0 Mask */
+#define LCD_PAL111_B04_0_Pos 10 /*!< LCD PAL111: B04_0 Position */
+#define LCD_PAL111_B04_0_Msk (0x1fUL << LCD_PAL111_B04_0_Pos) /*!< LCD PAL111: B04_0 Mask */
+#define LCD_PAL111_I0_Pos 15 /*!< LCD PAL111: I0 Position */
+#define LCD_PAL111_I0_Msk (0x01UL << LCD_PAL111_I0_Pos) /*!< LCD PAL111: I0 Mask */
+#define LCD_PAL111_R14_0_Pos 16 /*!< LCD PAL111: R14_0 Position */
+#define LCD_PAL111_R14_0_Msk (0x1fUL << LCD_PAL111_R14_0_Pos) /*!< LCD PAL111: R14_0 Mask */
+#define LCD_PAL111_G14_0_Pos 21 /*!< LCD PAL111: G14_0 Position */
+#define LCD_PAL111_G14_0_Msk (0x1fUL << LCD_PAL111_G14_0_Pos) /*!< LCD PAL111: G14_0 Mask */
+#define LCD_PAL111_B14_0_Pos 26 /*!< LCD PAL111: B14_0 Position */
+#define LCD_PAL111_B14_0_Msk (0x1fUL << LCD_PAL111_B14_0_Pos) /*!< LCD PAL111: B14_0 Mask */
+#define LCD_PAL111_I1_Pos 31 /*!< LCD PAL111: I1 Position */
+#define LCD_PAL111_I1_Msk (0x01UL << LCD_PAL111_I1_Pos) /*!< LCD PAL111: I1 Mask */
+
+// --------------------------------------- LCD_PAL112 -------------------------------------------
+#define LCD_PAL112_R04_0_Pos 0 /*!< LCD PAL112: R04_0 Position */
+#define LCD_PAL112_R04_0_Msk (0x1fUL << LCD_PAL112_R04_0_Pos) /*!< LCD PAL112: R04_0 Mask */
+#define LCD_PAL112_G04_0_Pos 5 /*!< LCD PAL112: G04_0 Position */
+#define LCD_PAL112_G04_0_Msk (0x1fUL << LCD_PAL112_G04_0_Pos) /*!< LCD PAL112: G04_0 Mask */
+#define LCD_PAL112_B04_0_Pos 10 /*!< LCD PAL112: B04_0 Position */
+#define LCD_PAL112_B04_0_Msk (0x1fUL << LCD_PAL112_B04_0_Pos) /*!< LCD PAL112: B04_0 Mask */
+#define LCD_PAL112_I0_Pos 15 /*!< LCD PAL112: I0 Position */
+#define LCD_PAL112_I0_Msk (0x01UL << LCD_PAL112_I0_Pos) /*!< LCD PAL112: I0 Mask */
+#define LCD_PAL112_R14_0_Pos 16 /*!< LCD PAL112: R14_0 Position */
+#define LCD_PAL112_R14_0_Msk (0x1fUL << LCD_PAL112_R14_0_Pos) /*!< LCD PAL112: R14_0 Mask */
+#define LCD_PAL112_G14_0_Pos 21 /*!< LCD PAL112: G14_0 Position */
+#define LCD_PAL112_G14_0_Msk (0x1fUL << LCD_PAL112_G14_0_Pos) /*!< LCD PAL112: G14_0 Mask */
+#define LCD_PAL112_B14_0_Pos 26 /*!< LCD PAL112: B14_0 Position */
+#define LCD_PAL112_B14_0_Msk (0x1fUL << LCD_PAL112_B14_0_Pos) /*!< LCD PAL112: B14_0 Mask */
+#define LCD_PAL112_I1_Pos 31 /*!< LCD PAL112: I1 Position */
+#define LCD_PAL112_I1_Msk (0x01UL << LCD_PAL112_I1_Pos) /*!< LCD PAL112: I1 Mask */
+
+// --------------------------------------- LCD_PAL113 -------------------------------------------
+#define LCD_PAL113_R04_0_Pos 0 /*!< LCD PAL113: R04_0 Position */
+#define LCD_PAL113_R04_0_Msk (0x1fUL << LCD_PAL113_R04_0_Pos) /*!< LCD PAL113: R04_0 Mask */
+#define LCD_PAL113_G04_0_Pos 5 /*!< LCD PAL113: G04_0 Position */
+#define LCD_PAL113_G04_0_Msk (0x1fUL << LCD_PAL113_G04_0_Pos) /*!< LCD PAL113: G04_0 Mask */
+#define LCD_PAL113_B04_0_Pos 10 /*!< LCD PAL113: B04_0 Position */
+#define LCD_PAL113_B04_0_Msk (0x1fUL << LCD_PAL113_B04_0_Pos) /*!< LCD PAL113: B04_0 Mask */
+#define LCD_PAL113_I0_Pos 15 /*!< LCD PAL113: I0 Position */
+#define LCD_PAL113_I0_Msk (0x01UL << LCD_PAL113_I0_Pos) /*!< LCD PAL113: I0 Mask */
+#define LCD_PAL113_R14_0_Pos 16 /*!< LCD PAL113: R14_0 Position */
+#define LCD_PAL113_R14_0_Msk (0x1fUL << LCD_PAL113_R14_0_Pos) /*!< LCD PAL113: R14_0 Mask */
+#define LCD_PAL113_G14_0_Pos 21 /*!< LCD PAL113: G14_0 Position */
+#define LCD_PAL113_G14_0_Msk (0x1fUL << LCD_PAL113_G14_0_Pos) /*!< LCD PAL113: G14_0 Mask */
+#define LCD_PAL113_B14_0_Pos 26 /*!< LCD PAL113: B14_0 Position */
+#define LCD_PAL113_B14_0_Msk (0x1fUL << LCD_PAL113_B14_0_Pos) /*!< LCD PAL113: B14_0 Mask */
+#define LCD_PAL113_I1_Pos 31 /*!< LCD PAL113: I1 Position */
+#define LCD_PAL113_I1_Msk (0x01UL << LCD_PAL113_I1_Pos) /*!< LCD PAL113: I1 Mask */
+
+// --------------------------------------- LCD_PAL114 -------------------------------------------
+#define LCD_PAL114_R04_0_Pos 0 /*!< LCD PAL114: R04_0 Position */
+#define LCD_PAL114_R04_0_Msk (0x1fUL << LCD_PAL114_R04_0_Pos) /*!< LCD PAL114: R04_0 Mask */
+#define LCD_PAL114_G04_0_Pos 5 /*!< LCD PAL114: G04_0 Position */
+#define LCD_PAL114_G04_0_Msk (0x1fUL << LCD_PAL114_G04_0_Pos) /*!< LCD PAL114: G04_0 Mask */
+#define LCD_PAL114_B04_0_Pos 10 /*!< LCD PAL114: B04_0 Position */
+#define LCD_PAL114_B04_0_Msk (0x1fUL << LCD_PAL114_B04_0_Pos) /*!< LCD PAL114: B04_0 Mask */
+#define LCD_PAL114_I0_Pos 15 /*!< LCD PAL114: I0 Position */
+#define LCD_PAL114_I0_Msk (0x01UL << LCD_PAL114_I0_Pos) /*!< LCD PAL114: I0 Mask */
+#define LCD_PAL114_R14_0_Pos 16 /*!< LCD PAL114: R14_0 Position */
+#define LCD_PAL114_R14_0_Msk (0x1fUL << LCD_PAL114_R14_0_Pos) /*!< LCD PAL114: R14_0 Mask */
+#define LCD_PAL114_G14_0_Pos 21 /*!< LCD PAL114: G14_0 Position */
+#define LCD_PAL114_G14_0_Msk (0x1fUL << LCD_PAL114_G14_0_Pos) /*!< LCD PAL114: G14_0 Mask */
+#define LCD_PAL114_B14_0_Pos 26 /*!< LCD PAL114: B14_0 Position */
+#define LCD_PAL114_B14_0_Msk (0x1fUL << LCD_PAL114_B14_0_Pos) /*!< LCD PAL114: B14_0 Mask */
+#define LCD_PAL114_I1_Pos 31 /*!< LCD PAL114: I1 Position */
+#define LCD_PAL114_I1_Msk (0x01UL << LCD_PAL114_I1_Pos) /*!< LCD PAL114: I1 Mask */
+
+// --------------------------------------- LCD_PAL115 -------------------------------------------
+#define LCD_PAL115_R04_0_Pos 0 /*!< LCD PAL115: R04_0 Position */
+#define LCD_PAL115_R04_0_Msk (0x1fUL << LCD_PAL115_R04_0_Pos) /*!< LCD PAL115: R04_0 Mask */
+#define LCD_PAL115_G04_0_Pos 5 /*!< LCD PAL115: G04_0 Position */
+#define LCD_PAL115_G04_0_Msk (0x1fUL << LCD_PAL115_G04_0_Pos) /*!< LCD PAL115: G04_0 Mask */
+#define LCD_PAL115_B04_0_Pos 10 /*!< LCD PAL115: B04_0 Position */
+#define LCD_PAL115_B04_0_Msk (0x1fUL << LCD_PAL115_B04_0_Pos) /*!< LCD PAL115: B04_0 Mask */
+#define LCD_PAL115_I0_Pos 15 /*!< LCD PAL115: I0 Position */
+#define LCD_PAL115_I0_Msk (0x01UL << LCD_PAL115_I0_Pos) /*!< LCD PAL115: I0 Mask */
+#define LCD_PAL115_R14_0_Pos 16 /*!< LCD PAL115: R14_0 Position */
+#define LCD_PAL115_R14_0_Msk (0x1fUL << LCD_PAL115_R14_0_Pos) /*!< LCD PAL115: R14_0 Mask */
+#define LCD_PAL115_G14_0_Pos 21 /*!< LCD PAL115: G14_0 Position */
+#define LCD_PAL115_G14_0_Msk (0x1fUL << LCD_PAL115_G14_0_Pos) /*!< LCD PAL115: G14_0 Mask */
+#define LCD_PAL115_B14_0_Pos 26 /*!< LCD PAL115: B14_0 Position */
+#define LCD_PAL115_B14_0_Msk (0x1fUL << LCD_PAL115_B14_0_Pos) /*!< LCD PAL115: B14_0 Mask */
+#define LCD_PAL115_I1_Pos 31 /*!< LCD PAL115: I1 Position */
+#define LCD_PAL115_I1_Msk (0x01UL << LCD_PAL115_I1_Pos) /*!< LCD PAL115: I1 Mask */
+
+// --------------------------------------- LCD_PAL116 -------------------------------------------
+#define LCD_PAL116_R04_0_Pos 0 /*!< LCD PAL116: R04_0 Position */
+#define LCD_PAL116_R04_0_Msk (0x1fUL << LCD_PAL116_R04_0_Pos) /*!< LCD PAL116: R04_0 Mask */
+#define LCD_PAL116_G04_0_Pos 5 /*!< LCD PAL116: G04_0 Position */
+#define LCD_PAL116_G04_0_Msk (0x1fUL << LCD_PAL116_G04_0_Pos) /*!< LCD PAL116: G04_0 Mask */
+#define LCD_PAL116_B04_0_Pos 10 /*!< LCD PAL116: B04_0 Position */
+#define LCD_PAL116_B04_0_Msk (0x1fUL << LCD_PAL116_B04_0_Pos) /*!< LCD PAL116: B04_0 Mask */
+#define LCD_PAL116_I0_Pos 15 /*!< LCD PAL116: I0 Position */
+#define LCD_PAL116_I0_Msk (0x01UL << LCD_PAL116_I0_Pos) /*!< LCD PAL116: I0 Mask */
+#define LCD_PAL116_R14_0_Pos 16 /*!< LCD PAL116: R14_0 Position */
+#define LCD_PAL116_R14_0_Msk (0x1fUL << LCD_PAL116_R14_0_Pos) /*!< LCD PAL116: R14_0 Mask */
+#define LCD_PAL116_G14_0_Pos 21 /*!< LCD PAL116: G14_0 Position */
+#define LCD_PAL116_G14_0_Msk (0x1fUL << LCD_PAL116_G14_0_Pos) /*!< LCD PAL116: G14_0 Mask */
+#define LCD_PAL116_B14_0_Pos 26 /*!< LCD PAL116: B14_0 Position */
+#define LCD_PAL116_B14_0_Msk (0x1fUL << LCD_PAL116_B14_0_Pos) /*!< LCD PAL116: B14_0 Mask */
+#define LCD_PAL116_I1_Pos 31 /*!< LCD PAL116: I1 Position */
+#define LCD_PAL116_I1_Msk (0x01UL << LCD_PAL116_I1_Pos) /*!< LCD PAL116: I1 Mask */
+
+// --------------------------------------- LCD_PAL117 -------------------------------------------
+#define LCD_PAL117_R04_0_Pos 0 /*!< LCD PAL117: R04_0 Position */
+#define LCD_PAL117_R04_0_Msk (0x1fUL << LCD_PAL117_R04_0_Pos) /*!< LCD PAL117: R04_0 Mask */
+#define LCD_PAL117_G04_0_Pos 5 /*!< LCD PAL117: G04_0 Position */
+#define LCD_PAL117_G04_0_Msk (0x1fUL << LCD_PAL117_G04_0_Pos) /*!< LCD PAL117: G04_0 Mask */
+#define LCD_PAL117_B04_0_Pos 10 /*!< LCD PAL117: B04_0 Position */
+#define LCD_PAL117_B04_0_Msk (0x1fUL << LCD_PAL117_B04_0_Pos) /*!< LCD PAL117: B04_0 Mask */
+#define LCD_PAL117_I0_Pos 15 /*!< LCD PAL117: I0 Position */
+#define LCD_PAL117_I0_Msk (0x01UL << LCD_PAL117_I0_Pos) /*!< LCD PAL117: I0 Mask */
+#define LCD_PAL117_R14_0_Pos 16 /*!< LCD PAL117: R14_0 Position */
+#define LCD_PAL117_R14_0_Msk (0x1fUL << LCD_PAL117_R14_0_Pos) /*!< LCD PAL117: R14_0 Mask */
+#define LCD_PAL117_G14_0_Pos 21 /*!< LCD PAL117: G14_0 Position */
+#define LCD_PAL117_G14_0_Msk (0x1fUL << LCD_PAL117_G14_0_Pos) /*!< LCD PAL117: G14_0 Mask */
+#define LCD_PAL117_B14_0_Pos 26 /*!< LCD PAL117: B14_0 Position */
+#define LCD_PAL117_B14_0_Msk (0x1fUL << LCD_PAL117_B14_0_Pos) /*!< LCD PAL117: B14_0 Mask */
+#define LCD_PAL117_I1_Pos 31 /*!< LCD PAL117: I1 Position */
+#define LCD_PAL117_I1_Msk (0x01UL << LCD_PAL117_I1_Pos) /*!< LCD PAL117: I1 Mask */
+
+// --------------------------------------- LCD_PAL118 -------------------------------------------
+#define LCD_PAL118_R04_0_Pos 0 /*!< LCD PAL118: R04_0 Position */
+#define LCD_PAL118_R04_0_Msk (0x1fUL << LCD_PAL118_R04_0_Pos) /*!< LCD PAL118: R04_0 Mask */
+#define LCD_PAL118_G04_0_Pos 5 /*!< LCD PAL118: G04_0 Position */
+#define LCD_PAL118_G04_0_Msk (0x1fUL << LCD_PAL118_G04_0_Pos) /*!< LCD PAL118: G04_0 Mask */
+#define LCD_PAL118_B04_0_Pos 10 /*!< LCD PAL118: B04_0 Position */
+#define LCD_PAL118_B04_0_Msk (0x1fUL << LCD_PAL118_B04_0_Pos) /*!< LCD PAL118: B04_0 Mask */
+#define LCD_PAL118_I0_Pos 15 /*!< LCD PAL118: I0 Position */
+#define LCD_PAL118_I0_Msk (0x01UL << LCD_PAL118_I0_Pos) /*!< LCD PAL118: I0 Mask */
+#define LCD_PAL118_R14_0_Pos 16 /*!< LCD PAL118: R14_0 Position */
+#define LCD_PAL118_R14_0_Msk (0x1fUL << LCD_PAL118_R14_0_Pos) /*!< LCD PAL118: R14_0 Mask */
+#define LCD_PAL118_G14_0_Pos 21 /*!< LCD PAL118: G14_0 Position */
+#define LCD_PAL118_G14_0_Msk (0x1fUL << LCD_PAL118_G14_0_Pos) /*!< LCD PAL118: G14_0 Mask */
+#define LCD_PAL118_B14_0_Pos 26 /*!< LCD PAL118: B14_0 Position */
+#define LCD_PAL118_B14_0_Msk (0x1fUL << LCD_PAL118_B14_0_Pos) /*!< LCD PAL118: B14_0 Mask */
+#define LCD_PAL118_I1_Pos 31 /*!< LCD PAL118: I1 Position */
+#define LCD_PAL118_I1_Msk (0x01UL << LCD_PAL118_I1_Pos) /*!< LCD PAL118: I1 Mask */
+
+// --------------------------------------- LCD_PAL119 -------------------------------------------
+#define LCD_PAL119_R04_0_Pos 0 /*!< LCD PAL119: R04_0 Position */
+#define LCD_PAL119_R04_0_Msk (0x1fUL << LCD_PAL119_R04_0_Pos) /*!< LCD PAL119: R04_0 Mask */
+#define LCD_PAL119_G04_0_Pos 5 /*!< LCD PAL119: G04_0 Position */
+#define LCD_PAL119_G04_0_Msk (0x1fUL << LCD_PAL119_G04_0_Pos) /*!< LCD PAL119: G04_0 Mask */
+#define LCD_PAL119_B04_0_Pos 10 /*!< LCD PAL119: B04_0 Position */
+#define LCD_PAL119_B04_0_Msk (0x1fUL << LCD_PAL119_B04_0_Pos) /*!< LCD PAL119: B04_0 Mask */
+#define LCD_PAL119_I0_Pos 15 /*!< LCD PAL119: I0 Position */
+#define LCD_PAL119_I0_Msk (0x01UL << LCD_PAL119_I0_Pos) /*!< LCD PAL119: I0 Mask */
+#define LCD_PAL119_R14_0_Pos 16 /*!< LCD PAL119: R14_0 Position */
+#define LCD_PAL119_R14_0_Msk (0x1fUL << LCD_PAL119_R14_0_Pos) /*!< LCD PAL119: R14_0 Mask */
+#define LCD_PAL119_G14_0_Pos 21 /*!< LCD PAL119: G14_0 Position */
+#define LCD_PAL119_G14_0_Msk (0x1fUL << LCD_PAL119_G14_0_Pos) /*!< LCD PAL119: G14_0 Mask */
+#define LCD_PAL119_B14_0_Pos 26 /*!< LCD PAL119: B14_0 Position */
+#define LCD_PAL119_B14_0_Msk (0x1fUL << LCD_PAL119_B14_0_Pos) /*!< LCD PAL119: B14_0 Mask */
+#define LCD_PAL119_I1_Pos 31 /*!< LCD PAL119: I1 Position */
+#define LCD_PAL119_I1_Msk (0x01UL << LCD_PAL119_I1_Pos) /*!< LCD PAL119: I1 Mask */
+
+// --------------------------------------- LCD_PAL120 -------------------------------------------
+#define LCD_PAL120_R04_0_Pos 0 /*!< LCD PAL120: R04_0 Position */
+#define LCD_PAL120_R04_0_Msk (0x1fUL << LCD_PAL120_R04_0_Pos) /*!< LCD PAL120: R04_0 Mask */
+#define LCD_PAL120_G04_0_Pos 5 /*!< LCD PAL120: G04_0 Position */
+#define LCD_PAL120_G04_0_Msk (0x1fUL << LCD_PAL120_G04_0_Pos) /*!< LCD PAL120: G04_0 Mask */
+#define LCD_PAL120_B04_0_Pos 10 /*!< LCD PAL120: B04_0 Position */
+#define LCD_PAL120_B04_0_Msk (0x1fUL << LCD_PAL120_B04_0_Pos) /*!< LCD PAL120: B04_0 Mask */
+#define LCD_PAL120_I0_Pos 15 /*!< LCD PAL120: I0 Position */
+#define LCD_PAL120_I0_Msk (0x01UL << LCD_PAL120_I0_Pos) /*!< LCD PAL120: I0 Mask */
+#define LCD_PAL120_R14_0_Pos 16 /*!< LCD PAL120: R14_0 Position */
+#define LCD_PAL120_R14_0_Msk (0x1fUL << LCD_PAL120_R14_0_Pos) /*!< LCD PAL120: R14_0 Mask */
+#define LCD_PAL120_G14_0_Pos 21 /*!< LCD PAL120: G14_0 Position */
+#define LCD_PAL120_G14_0_Msk (0x1fUL << LCD_PAL120_G14_0_Pos) /*!< LCD PAL120: G14_0 Mask */
+#define LCD_PAL120_B14_0_Pos 26 /*!< LCD PAL120: B14_0 Position */
+#define LCD_PAL120_B14_0_Msk (0x1fUL << LCD_PAL120_B14_0_Pos) /*!< LCD PAL120: B14_0 Mask */
+#define LCD_PAL120_I1_Pos 31 /*!< LCD PAL120: I1 Position */
+#define LCD_PAL120_I1_Msk (0x01UL << LCD_PAL120_I1_Pos) /*!< LCD PAL120: I1 Mask */
+
+// --------------------------------------- LCD_PAL121 -------------------------------------------
+#define LCD_PAL121_R04_0_Pos 0 /*!< LCD PAL121: R04_0 Position */
+#define LCD_PAL121_R04_0_Msk (0x1fUL << LCD_PAL121_R04_0_Pos) /*!< LCD PAL121: R04_0 Mask */
+#define LCD_PAL121_G04_0_Pos 5 /*!< LCD PAL121: G04_0 Position */
+#define LCD_PAL121_G04_0_Msk (0x1fUL << LCD_PAL121_G04_0_Pos) /*!< LCD PAL121: G04_0 Mask */
+#define LCD_PAL121_B04_0_Pos 10 /*!< LCD PAL121: B04_0 Position */
+#define LCD_PAL121_B04_0_Msk (0x1fUL << LCD_PAL121_B04_0_Pos) /*!< LCD PAL121: B04_0 Mask */
+#define LCD_PAL121_I0_Pos 15 /*!< LCD PAL121: I0 Position */
+#define LCD_PAL121_I0_Msk (0x01UL << LCD_PAL121_I0_Pos) /*!< LCD PAL121: I0 Mask */
+#define LCD_PAL121_R14_0_Pos 16 /*!< LCD PAL121: R14_0 Position */
+#define LCD_PAL121_R14_0_Msk (0x1fUL << LCD_PAL121_R14_0_Pos) /*!< LCD PAL121: R14_0 Mask */
+#define LCD_PAL121_G14_0_Pos 21 /*!< LCD PAL121: G14_0 Position */
+#define LCD_PAL121_G14_0_Msk (0x1fUL << LCD_PAL121_G14_0_Pos) /*!< LCD PAL121: G14_0 Mask */
+#define LCD_PAL121_B14_0_Pos 26 /*!< LCD PAL121: B14_0 Position */
+#define LCD_PAL121_B14_0_Msk (0x1fUL << LCD_PAL121_B14_0_Pos) /*!< LCD PAL121: B14_0 Mask */
+#define LCD_PAL121_I1_Pos 31 /*!< LCD PAL121: I1 Position */
+#define LCD_PAL121_I1_Msk (0x01UL << LCD_PAL121_I1_Pos) /*!< LCD PAL121: I1 Mask */
+
+// --------------------------------------- LCD_PAL122 -------------------------------------------
+#define LCD_PAL122_R04_0_Pos 0 /*!< LCD PAL122: R04_0 Position */
+#define LCD_PAL122_R04_0_Msk (0x1fUL << LCD_PAL122_R04_0_Pos) /*!< LCD PAL122: R04_0 Mask */
+#define LCD_PAL122_G04_0_Pos 5 /*!< LCD PAL122: G04_0 Position */
+#define LCD_PAL122_G04_0_Msk (0x1fUL << LCD_PAL122_G04_0_Pos) /*!< LCD PAL122: G04_0 Mask */
+#define LCD_PAL122_B04_0_Pos 10 /*!< LCD PAL122: B04_0 Position */
+#define LCD_PAL122_B04_0_Msk (0x1fUL << LCD_PAL122_B04_0_Pos) /*!< LCD PAL122: B04_0 Mask */
+#define LCD_PAL122_I0_Pos 15 /*!< LCD PAL122: I0 Position */
+#define LCD_PAL122_I0_Msk (0x01UL << LCD_PAL122_I0_Pos) /*!< LCD PAL122: I0 Mask */
+#define LCD_PAL122_R14_0_Pos 16 /*!< LCD PAL122: R14_0 Position */
+#define LCD_PAL122_R14_0_Msk (0x1fUL << LCD_PAL122_R14_0_Pos) /*!< LCD PAL122: R14_0 Mask */
+#define LCD_PAL122_G14_0_Pos 21 /*!< LCD PAL122: G14_0 Position */
+#define LCD_PAL122_G14_0_Msk (0x1fUL << LCD_PAL122_G14_0_Pos) /*!< LCD PAL122: G14_0 Mask */
+#define LCD_PAL122_B14_0_Pos 26 /*!< LCD PAL122: B14_0 Position */
+#define LCD_PAL122_B14_0_Msk (0x1fUL << LCD_PAL122_B14_0_Pos) /*!< LCD PAL122: B14_0 Mask */
+#define LCD_PAL122_I1_Pos 31 /*!< LCD PAL122: I1 Position */
+#define LCD_PAL122_I1_Msk (0x01UL << LCD_PAL122_I1_Pos) /*!< LCD PAL122: I1 Mask */
+
+// --------------------------------------- LCD_PAL123 -------------------------------------------
+#define LCD_PAL123_R04_0_Pos 0 /*!< LCD PAL123: R04_0 Position */
+#define LCD_PAL123_R04_0_Msk (0x1fUL << LCD_PAL123_R04_0_Pos) /*!< LCD PAL123: R04_0 Mask */
+#define LCD_PAL123_G04_0_Pos 5 /*!< LCD PAL123: G04_0 Position */
+#define LCD_PAL123_G04_0_Msk (0x1fUL << LCD_PAL123_G04_0_Pos) /*!< LCD PAL123: G04_0 Mask */
+#define LCD_PAL123_B04_0_Pos 10 /*!< LCD PAL123: B04_0 Position */
+#define LCD_PAL123_B04_0_Msk (0x1fUL << LCD_PAL123_B04_0_Pos) /*!< LCD PAL123: B04_0 Mask */
+#define LCD_PAL123_I0_Pos 15 /*!< LCD PAL123: I0 Position */
+#define LCD_PAL123_I0_Msk (0x01UL << LCD_PAL123_I0_Pos) /*!< LCD PAL123: I0 Mask */
+#define LCD_PAL123_R14_0_Pos 16 /*!< LCD PAL123: R14_0 Position */
+#define LCD_PAL123_R14_0_Msk (0x1fUL << LCD_PAL123_R14_0_Pos) /*!< LCD PAL123: R14_0 Mask */
+#define LCD_PAL123_G14_0_Pos 21 /*!< LCD PAL123: G14_0 Position */
+#define LCD_PAL123_G14_0_Msk (0x1fUL << LCD_PAL123_G14_0_Pos) /*!< LCD PAL123: G14_0 Mask */
+#define LCD_PAL123_B14_0_Pos 26 /*!< LCD PAL123: B14_0 Position */
+#define LCD_PAL123_B14_0_Msk (0x1fUL << LCD_PAL123_B14_0_Pos) /*!< LCD PAL123: B14_0 Mask */
+#define LCD_PAL123_I1_Pos 31 /*!< LCD PAL123: I1 Position */
+#define LCD_PAL123_I1_Msk (0x01UL << LCD_PAL123_I1_Pos) /*!< LCD PAL123: I1 Mask */
+
+// --------------------------------------- LCD_PAL124 -------------------------------------------
+#define LCD_PAL124_R04_0_Pos 0 /*!< LCD PAL124: R04_0 Position */
+#define LCD_PAL124_R04_0_Msk (0x1fUL << LCD_PAL124_R04_0_Pos) /*!< LCD PAL124: R04_0 Mask */
+#define LCD_PAL124_G04_0_Pos 5 /*!< LCD PAL124: G04_0 Position */
+#define LCD_PAL124_G04_0_Msk (0x1fUL << LCD_PAL124_G04_0_Pos) /*!< LCD PAL124: G04_0 Mask */
+#define LCD_PAL124_B04_0_Pos 10 /*!< LCD PAL124: B04_0 Position */
+#define LCD_PAL124_B04_0_Msk (0x1fUL << LCD_PAL124_B04_0_Pos) /*!< LCD PAL124: B04_0 Mask */
+#define LCD_PAL124_I0_Pos 15 /*!< LCD PAL124: I0 Position */
+#define LCD_PAL124_I0_Msk (0x01UL << LCD_PAL124_I0_Pos) /*!< LCD PAL124: I0 Mask */
+#define LCD_PAL124_R14_0_Pos 16 /*!< LCD PAL124: R14_0 Position */
+#define LCD_PAL124_R14_0_Msk (0x1fUL << LCD_PAL124_R14_0_Pos) /*!< LCD PAL124: R14_0 Mask */
+#define LCD_PAL124_G14_0_Pos 21 /*!< LCD PAL124: G14_0 Position */
+#define LCD_PAL124_G14_0_Msk (0x1fUL << LCD_PAL124_G14_0_Pos) /*!< LCD PAL124: G14_0 Mask */
+#define LCD_PAL124_B14_0_Pos 26 /*!< LCD PAL124: B14_0 Position */
+#define LCD_PAL124_B14_0_Msk (0x1fUL << LCD_PAL124_B14_0_Pos) /*!< LCD PAL124: B14_0 Mask */
+#define LCD_PAL124_I1_Pos 31 /*!< LCD PAL124: I1 Position */
+#define LCD_PAL124_I1_Msk (0x01UL << LCD_PAL124_I1_Pos) /*!< LCD PAL124: I1 Mask */
+
+// --------------------------------------- LCD_PAL125 -------------------------------------------
+#define LCD_PAL125_R04_0_Pos 0 /*!< LCD PAL125: R04_0 Position */
+#define LCD_PAL125_R04_0_Msk (0x1fUL << LCD_PAL125_R04_0_Pos) /*!< LCD PAL125: R04_0 Mask */
+#define LCD_PAL125_G04_0_Pos 5 /*!< LCD PAL125: G04_0 Position */
+#define LCD_PAL125_G04_0_Msk (0x1fUL << LCD_PAL125_G04_0_Pos) /*!< LCD PAL125: G04_0 Mask */
+#define LCD_PAL125_B04_0_Pos 10 /*!< LCD PAL125: B04_0 Position */
+#define LCD_PAL125_B04_0_Msk (0x1fUL << LCD_PAL125_B04_0_Pos) /*!< LCD PAL125: B04_0 Mask */
+#define LCD_PAL125_I0_Pos 15 /*!< LCD PAL125: I0 Position */
+#define LCD_PAL125_I0_Msk (0x01UL << LCD_PAL125_I0_Pos) /*!< LCD PAL125: I0 Mask */
+#define LCD_PAL125_R14_0_Pos 16 /*!< LCD PAL125: R14_0 Position */
+#define LCD_PAL125_R14_0_Msk (0x1fUL << LCD_PAL125_R14_0_Pos) /*!< LCD PAL125: R14_0 Mask */
+#define LCD_PAL125_G14_0_Pos 21 /*!< LCD PAL125: G14_0 Position */
+#define LCD_PAL125_G14_0_Msk (0x1fUL << LCD_PAL125_G14_0_Pos) /*!< LCD PAL125: G14_0 Mask */
+#define LCD_PAL125_B14_0_Pos 26 /*!< LCD PAL125: B14_0 Position */
+#define LCD_PAL125_B14_0_Msk (0x1fUL << LCD_PAL125_B14_0_Pos) /*!< LCD PAL125: B14_0 Mask */
+#define LCD_PAL125_I1_Pos 31 /*!< LCD PAL125: I1 Position */
+#define LCD_PAL125_I1_Msk (0x01UL << LCD_PAL125_I1_Pos) /*!< LCD PAL125: I1 Mask */
+
+// --------------------------------------- LCD_PAL126 -------------------------------------------
+#define LCD_PAL126_R04_0_Pos 0 /*!< LCD PAL126: R04_0 Position */
+#define LCD_PAL126_R04_0_Msk (0x1fUL << LCD_PAL126_R04_0_Pos) /*!< LCD PAL126: R04_0 Mask */
+#define LCD_PAL126_G04_0_Pos 5 /*!< LCD PAL126: G04_0 Position */
+#define LCD_PAL126_G04_0_Msk (0x1fUL << LCD_PAL126_G04_0_Pos) /*!< LCD PAL126: G04_0 Mask */
+#define LCD_PAL126_B04_0_Pos 10 /*!< LCD PAL126: B04_0 Position */
+#define LCD_PAL126_B04_0_Msk (0x1fUL << LCD_PAL126_B04_0_Pos) /*!< LCD PAL126: B04_0 Mask */
+#define LCD_PAL126_I0_Pos 15 /*!< LCD PAL126: I0 Position */
+#define LCD_PAL126_I0_Msk (0x01UL << LCD_PAL126_I0_Pos) /*!< LCD PAL126: I0 Mask */
+#define LCD_PAL126_R14_0_Pos 16 /*!< LCD PAL126: R14_0 Position */
+#define LCD_PAL126_R14_0_Msk (0x1fUL << LCD_PAL126_R14_0_Pos) /*!< LCD PAL126: R14_0 Mask */
+#define LCD_PAL126_G14_0_Pos 21 /*!< LCD PAL126: G14_0 Position */
+#define LCD_PAL126_G14_0_Msk (0x1fUL << LCD_PAL126_G14_0_Pos) /*!< LCD PAL126: G14_0 Mask */
+#define LCD_PAL126_B14_0_Pos 26 /*!< LCD PAL126: B14_0 Position */
+#define LCD_PAL126_B14_0_Msk (0x1fUL << LCD_PAL126_B14_0_Pos) /*!< LCD PAL126: B14_0 Mask */
+#define LCD_PAL126_I1_Pos 31 /*!< LCD PAL126: I1 Position */
+#define LCD_PAL126_I1_Msk (0x01UL << LCD_PAL126_I1_Pos) /*!< LCD PAL126: I1 Mask */
+
+// --------------------------------------- LCD_PAL127 -------------------------------------------
+#define LCD_PAL127_R04_0_Pos 0 /*!< LCD PAL127: R04_0 Position */
+#define LCD_PAL127_R04_0_Msk (0x1fUL << LCD_PAL127_R04_0_Pos) /*!< LCD PAL127: R04_0 Mask */
+#define LCD_PAL127_G04_0_Pos 5 /*!< LCD PAL127: G04_0 Position */
+#define LCD_PAL127_G04_0_Msk (0x1fUL << LCD_PAL127_G04_0_Pos) /*!< LCD PAL127: G04_0 Mask */
+#define LCD_PAL127_B04_0_Pos 10 /*!< LCD PAL127: B04_0 Position */
+#define LCD_PAL127_B04_0_Msk (0x1fUL << LCD_PAL127_B04_0_Pos) /*!< LCD PAL127: B04_0 Mask */
+#define LCD_PAL127_I0_Pos 15 /*!< LCD PAL127: I0 Position */
+#define LCD_PAL127_I0_Msk (0x01UL << LCD_PAL127_I0_Pos) /*!< LCD PAL127: I0 Mask */
+#define LCD_PAL127_R14_0_Pos 16 /*!< LCD PAL127: R14_0 Position */
+#define LCD_PAL127_R14_0_Msk (0x1fUL << LCD_PAL127_R14_0_Pos) /*!< LCD PAL127: R14_0 Mask */
+#define LCD_PAL127_G14_0_Pos 21 /*!< LCD PAL127: G14_0 Position */
+#define LCD_PAL127_G14_0_Msk (0x1fUL << LCD_PAL127_G14_0_Pos) /*!< LCD PAL127: G14_0 Mask */
+#define LCD_PAL127_B14_0_Pos 26 /*!< LCD PAL127: B14_0 Position */
+#define LCD_PAL127_B14_0_Msk (0x1fUL << LCD_PAL127_B14_0_Pos) /*!< LCD PAL127: B14_0 Mask */
+#define LCD_PAL127_I1_Pos 31 /*!< LCD PAL127: I1 Position */
+#define LCD_PAL127_I1_Msk (0x01UL << LCD_PAL127_I1_Pos) /*!< LCD PAL127: I1 Mask */
+
+// --------------------------------------- LCD_PAL128 -------------------------------------------
+#define LCD_PAL128_R04_0_Pos 0 /*!< LCD PAL128: R04_0 Position */
+#define LCD_PAL128_R04_0_Msk (0x1fUL << LCD_PAL128_R04_0_Pos) /*!< LCD PAL128: R04_0 Mask */
+#define LCD_PAL128_G04_0_Pos 5 /*!< LCD PAL128: G04_0 Position */
+#define LCD_PAL128_G04_0_Msk (0x1fUL << LCD_PAL128_G04_0_Pos) /*!< LCD PAL128: G04_0 Mask */
+#define LCD_PAL128_B04_0_Pos 10 /*!< LCD PAL128: B04_0 Position */
+#define LCD_PAL128_B04_0_Msk (0x1fUL << LCD_PAL128_B04_0_Pos) /*!< LCD PAL128: B04_0 Mask */
+#define LCD_PAL128_I0_Pos 15 /*!< LCD PAL128: I0 Position */
+#define LCD_PAL128_I0_Msk (0x01UL << LCD_PAL128_I0_Pos) /*!< LCD PAL128: I0 Mask */
+#define LCD_PAL128_R14_0_Pos 16 /*!< LCD PAL128: R14_0 Position */
+#define LCD_PAL128_R14_0_Msk (0x1fUL << LCD_PAL128_R14_0_Pos) /*!< LCD PAL128: R14_0 Mask */
+#define LCD_PAL128_G14_0_Pos 21 /*!< LCD PAL128: G14_0 Position */
+#define LCD_PAL128_G14_0_Msk (0x1fUL << LCD_PAL128_G14_0_Pos) /*!< LCD PAL128: G14_0 Mask */
+#define LCD_PAL128_B14_0_Pos 26 /*!< LCD PAL128: B14_0 Position */
+#define LCD_PAL128_B14_0_Msk (0x1fUL << LCD_PAL128_B14_0_Pos) /*!< LCD PAL128: B14_0 Mask */
+#define LCD_PAL128_I1_Pos 31 /*!< LCD PAL128: I1 Position */
+#define LCD_PAL128_I1_Msk (0x01UL << LCD_PAL128_I1_Pos) /*!< LCD PAL128: I1 Mask */
+
+// --------------------------------------- LCD_PAL129 -------------------------------------------
+#define LCD_PAL129_R04_0_Pos 0 /*!< LCD PAL129: R04_0 Position */
+#define LCD_PAL129_R04_0_Msk (0x1fUL << LCD_PAL129_R04_0_Pos) /*!< LCD PAL129: R04_0 Mask */
+#define LCD_PAL129_G04_0_Pos 5 /*!< LCD PAL129: G04_0 Position */
+#define LCD_PAL129_G04_0_Msk (0x1fUL << LCD_PAL129_G04_0_Pos) /*!< LCD PAL129: G04_0 Mask */
+#define LCD_PAL129_B04_0_Pos 10 /*!< LCD PAL129: B04_0 Position */
+#define LCD_PAL129_B04_0_Msk (0x1fUL << LCD_PAL129_B04_0_Pos) /*!< LCD PAL129: B04_0 Mask */
+#define LCD_PAL129_I0_Pos 15 /*!< LCD PAL129: I0 Position */
+#define LCD_PAL129_I0_Msk (0x01UL << LCD_PAL129_I0_Pos) /*!< LCD PAL129: I0 Mask */
+#define LCD_PAL129_R14_0_Pos 16 /*!< LCD PAL129: R14_0 Position */
+#define LCD_PAL129_R14_0_Msk (0x1fUL << LCD_PAL129_R14_0_Pos) /*!< LCD PAL129: R14_0 Mask */
+#define LCD_PAL129_G14_0_Pos 21 /*!< LCD PAL129: G14_0 Position */
+#define LCD_PAL129_G14_0_Msk (0x1fUL << LCD_PAL129_G14_0_Pos) /*!< LCD PAL129: G14_0 Mask */
+#define LCD_PAL129_B14_0_Pos 26 /*!< LCD PAL129: B14_0 Position */
+#define LCD_PAL129_B14_0_Msk (0x1fUL << LCD_PAL129_B14_0_Pos) /*!< LCD PAL129: B14_0 Mask */
+#define LCD_PAL129_I1_Pos 31 /*!< LCD PAL129: I1 Position */
+#define LCD_PAL129_I1_Msk (0x01UL << LCD_PAL129_I1_Pos) /*!< LCD PAL129: I1 Mask */
+
+// --------------------------------------- LCD_PAL130 -------------------------------------------
+#define LCD_PAL130_R04_0_Pos 0 /*!< LCD PAL130: R04_0 Position */
+#define LCD_PAL130_R04_0_Msk (0x1fUL << LCD_PAL130_R04_0_Pos) /*!< LCD PAL130: R04_0 Mask */
+#define LCD_PAL130_G04_0_Pos 5 /*!< LCD PAL130: G04_0 Position */
+#define LCD_PAL130_G04_0_Msk (0x1fUL << LCD_PAL130_G04_0_Pos) /*!< LCD PAL130: G04_0 Mask */
+#define LCD_PAL130_B04_0_Pos 10 /*!< LCD PAL130: B04_0 Position */
+#define LCD_PAL130_B04_0_Msk (0x1fUL << LCD_PAL130_B04_0_Pos) /*!< LCD PAL130: B04_0 Mask */
+#define LCD_PAL130_I0_Pos 15 /*!< LCD PAL130: I0 Position */
+#define LCD_PAL130_I0_Msk (0x01UL << LCD_PAL130_I0_Pos) /*!< LCD PAL130: I0 Mask */
+#define LCD_PAL130_R14_0_Pos 16 /*!< LCD PAL130: R14_0 Position */
+#define LCD_PAL130_R14_0_Msk (0x1fUL << LCD_PAL130_R14_0_Pos) /*!< LCD PAL130: R14_0 Mask */
+#define LCD_PAL130_G14_0_Pos 21 /*!< LCD PAL130: G14_0 Position */
+#define LCD_PAL130_G14_0_Msk (0x1fUL << LCD_PAL130_G14_0_Pos) /*!< LCD PAL130: G14_0 Mask */
+#define LCD_PAL130_B14_0_Pos 26 /*!< LCD PAL130: B14_0 Position */
+#define LCD_PAL130_B14_0_Msk (0x1fUL << LCD_PAL130_B14_0_Pos) /*!< LCD PAL130: B14_0 Mask */
+#define LCD_PAL130_I1_Pos 31 /*!< LCD PAL130: I1 Position */
+#define LCD_PAL130_I1_Msk (0x01UL << LCD_PAL130_I1_Pos) /*!< LCD PAL130: I1 Mask */
+
+// --------------------------------------- LCD_PAL131 -------------------------------------------
+#define LCD_PAL131_R04_0_Pos 0 /*!< LCD PAL131: R04_0 Position */
+#define LCD_PAL131_R04_0_Msk (0x1fUL << LCD_PAL131_R04_0_Pos) /*!< LCD PAL131: R04_0 Mask */
+#define LCD_PAL131_G04_0_Pos 5 /*!< LCD PAL131: G04_0 Position */
+#define LCD_PAL131_G04_0_Msk (0x1fUL << LCD_PAL131_G04_0_Pos) /*!< LCD PAL131: G04_0 Mask */
+#define LCD_PAL131_B04_0_Pos 10 /*!< LCD PAL131: B04_0 Position */
+#define LCD_PAL131_B04_0_Msk (0x1fUL << LCD_PAL131_B04_0_Pos) /*!< LCD PAL131: B04_0 Mask */
+#define LCD_PAL131_I0_Pos 15 /*!< LCD PAL131: I0 Position */
+#define LCD_PAL131_I0_Msk (0x01UL << LCD_PAL131_I0_Pos) /*!< LCD PAL131: I0 Mask */
+#define LCD_PAL131_R14_0_Pos 16 /*!< LCD PAL131: R14_0 Position */
+#define LCD_PAL131_R14_0_Msk (0x1fUL << LCD_PAL131_R14_0_Pos) /*!< LCD PAL131: R14_0 Mask */
+#define LCD_PAL131_G14_0_Pos 21 /*!< LCD PAL131: G14_0 Position */
+#define LCD_PAL131_G14_0_Msk (0x1fUL << LCD_PAL131_G14_0_Pos) /*!< LCD PAL131: G14_0 Mask */
+#define LCD_PAL131_B14_0_Pos 26 /*!< LCD PAL131: B14_0 Position */
+#define LCD_PAL131_B14_0_Msk (0x1fUL << LCD_PAL131_B14_0_Pos) /*!< LCD PAL131: B14_0 Mask */
+#define LCD_PAL131_I1_Pos 31 /*!< LCD PAL131: I1 Position */
+#define LCD_PAL131_I1_Msk (0x01UL << LCD_PAL131_I1_Pos) /*!< LCD PAL131: I1 Mask */
+
+// --------------------------------------- LCD_PAL132 -------------------------------------------
+#define LCD_PAL132_R04_0_Pos 0 /*!< LCD PAL132: R04_0 Position */
+#define LCD_PAL132_R04_0_Msk (0x1fUL << LCD_PAL132_R04_0_Pos) /*!< LCD PAL132: R04_0 Mask */
+#define LCD_PAL132_G04_0_Pos 5 /*!< LCD PAL132: G04_0 Position */
+#define LCD_PAL132_G04_0_Msk (0x1fUL << LCD_PAL132_G04_0_Pos) /*!< LCD PAL132: G04_0 Mask */
+#define LCD_PAL132_B04_0_Pos 10 /*!< LCD PAL132: B04_0 Position */
+#define LCD_PAL132_B04_0_Msk (0x1fUL << LCD_PAL132_B04_0_Pos) /*!< LCD PAL132: B04_0 Mask */
+#define LCD_PAL132_I0_Pos 15 /*!< LCD PAL132: I0 Position */
+#define LCD_PAL132_I0_Msk (0x01UL << LCD_PAL132_I0_Pos) /*!< LCD PAL132: I0 Mask */
+#define LCD_PAL132_R14_0_Pos 16 /*!< LCD PAL132: R14_0 Position */
+#define LCD_PAL132_R14_0_Msk (0x1fUL << LCD_PAL132_R14_0_Pos) /*!< LCD PAL132: R14_0 Mask */
+#define LCD_PAL132_G14_0_Pos 21 /*!< LCD PAL132: G14_0 Position */
+#define LCD_PAL132_G14_0_Msk (0x1fUL << LCD_PAL132_G14_0_Pos) /*!< LCD PAL132: G14_0 Mask */
+#define LCD_PAL132_B14_0_Pos 26 /*!< LCD PAL132: B14_0 Position */
+#define LCD_PAL132_B14_0_Msk (0x1fUL << LCD_PAL132_B14_0_Pos) /*!< LCD PAL132: B14_0 Mask */
+#define LCD_PAL132_I1_Pos 31 /*!< LCD PAL132: I1 Position */
+#define LCD_PAL132_I1_Msk (0x01UL << LCD_PAL132_I1_Pos) /*!< LCD PAL132: I1 Mask */
+
+// --------------------------------------- LCD_PAL133 -------------------------------------------
+#define LCD_PAL133_R04_0_Pos 0 /*!< LCD PAL133: R04_0 Position */
+#define LCD_PAL133_R04_0_Msk (0x1fUL << LCD_PAL133_R04_0_Pos) /*!< LCD PAL133: R04_0 Mask */
+#define LCD_PAL133_G04_0_Pos 5 /*!< LCD PAL133: G04_0 Position */
+#define LCD_PAL133_G04_0_Msk (0x1fUL << LCD_PAL133_G04_0_Pos) /*!< LCD PAL133: G04_0 Mask */
+#define LCD_PAL133_B04_0_Pos 10 /*!< LCD PAL133: B04_0 Position */
+#define LCD_PAL133_B04_0_Msk (0x1fUL << LCD_PAL133_B04_0_Pos) /*!< LCD PAL133: B04_0 Mask */
+#define LCD_PAL133_I0_Pos 15 /*!< LCD PAL133: I0 Position */
+#define LCD_PAL133_I0_Msk (0x01UL << LCD_PAL133_I0_Pos) /*!< LCD PAL133: I0 Mask */
+#define LCD_PAL133_R14_0_Pos 16 /*!< LCD PAL133: R14_0 Position */
+#define LCD_PAL133_R14_0_Msk (0x1fUL << LCD_PAL133_R14_0_Pos) /*!< LCD PAL133: R14_0 Mask */
+#define LCD_PAL133_G14_0_Pos 21 /*!< LCD PAL133: G14_0 Position */
+#define LCD_PAL133_G14_0_Msk (0x1fUL << LCD_PAL133_G14_0_Pos) /*!< LCD PAL133: G14_0 Mask */
+#define LCD_PAL133_B14_0_Pos 26 /*!< LCD PAL133: B14_0 Position */
+#define LCD_PAL133_B14_0_Msk (0x1fUL << LCD_PAL133_B14_0_Pos) /*!< LCD PAL133: B14_0 Mask */
+#define LCD_PAL133_I1_Pos 31 /*!< LCD PAL133: I1 Position */
+#define LCD_PAL133_I1_Msk (0x01UL << LCD_PAL133_I1_Pos) /*!< LCD PAL133: I1 Mask */
+
+// --------------------------------------- LCD_PAL134 -------------------------------------------
+#define LCD_PAL134_R04_0_Pos 0 /*!< LCD PAL134: R04_0 Position */
+#define LCD_PAL134_R04_0_Msk (0x1fUL << LCD_PAL134_R04_0_Pos) /*!< LCD PAL134: R04_0 Mask */
+#define LCD_PAL134_G04_0_Pos 5 /*!< LCD PAL134: G04_0 Position */
+#define LCD_PAL134_G04_0_Msk (0x1fUL << LCD_PAL134_G04_0_Pos) /*!< LCD PAL134: G04_0 Mask */
+#define LCD_PAL134_B04_0_Pos 10 /*!< LCD PAL134: B04_0 Position */
+#define LCD_PAL134_B04_0_Msk (0x1fUL << LCD_PAL134_B04_0_Pos) /*!< LCD PAL134: B04_0 Mask */
+#define LCD_PAL134_I0_Pos 15 /*!< LCD PAL134: I0 Position */
+#define LCD_PAL134_I0_Msk (0x01UL << LCD_PAL134_I0_Pos) /*!< LCD PAL134: I0 Mask */
+#define LCD_PAL134_R14_0_Pos 16 /*!< LCD PAL134: R14_0 Position */
+#define LCD_PAL134_R14_0_Msk (0x1fUL << LCD_PAL134_R14_0_Pos) /*!< LCD PAL134: R14_0 Mask */
+#define LCD_PAL134_G14_0_Pos 21 /*!< LCD PAL134: G14_0 Position */
+#define LCD_PAL134_G14_0_Msk (0x1fUL << LCD_PAL134_G14_0_Pos) /*!< LCD PAL134: G14_0 Mask */
+#define LCD_PAL134_B14_0_Pos 26 /*!< LCD PAL134: B14_0 Position */
+#define LCD_PAL134_B14_0_Msk (0x1fUL << LCD_PAL134_B14_0_Pos) /*!< LCD PAL134: B14_0 Mask */
+#define LCD_PAL134_I1_Pos 31 /*!< LCD PAL134: I1 Position */
+#define LCD_PAL134_I1_Msk (0x01UL << LCD_PAL134_I1_Pos) /*!< LCD PAL134: I1 Mask */
+
+// --------------------------------------- LCD_PAL135 -------------------------------------------
+#define LCD_PAL135_R04_0_Pos 0 /*!< LCD PAL135: R04_0 Position */
+#define LCD_PAL135_R04_0_Msk (0x1fUL << LCD_PAL135_R04_0_Pos) /*!< LCD PAL135: R04_0 Mask */
+#define LCD_PAL135_G04_0_Pos 5 /*!< LCD PAL135: G04_0 Position */
+#define LCD_PAL135_G04_0_Msk (0x1fUL << LCD_PAL135_G04_0_Pos) /*!< LCD PAL135: G04_0 Mask */
+#define LCD_PAL135_B04_0_Pos 10 /*!< LCD PAL135: B04_0 Position */
+#define LCD_PAL135_B04_0_Msk (0x1fUL << LCD_PAL135_B04_0_Pos) /*!< LCD PAL135: B04_0 Mask */
+#define LCD_PAL135_I0_Pos 15 /*!< LCD PAL135: I0 Position */
+#define LCD_PAL135_I0_Msk (0x01UL << LCD_PAL135_I0_Pos) /*!< LCD PAL135: I0 Mask */
+#define LCD_PAL135_R14_0_Pos 16 /*!< LCD PAL135: R14_0 Position */
+#define LCD_PAL135_R14_0_Msk (0x1fUL << LCD_PAL135_R14_0_Pos) /*!< LCD PAL135: R14_0 Mask */
+#define LCD_PAL135_G14_0_Pos 21 /*!< LCD PAL135: G14_0 Position */
+#define LCD_PAL135_G14_0_Msk (0x1fUL << LCD_PAL135_G14_0_Pos) /*!< LCD PAL135: G14_0 Mask */
+#define LCD_PAL135_B14_0_Pos 26 /*!< LCD PAL135: B14_0 Position */
+#define LCD_PAL135_B14_0_Msk (0x1fUL << LCD_PAL135_B14_0_Pos) /*!< LCD PAL135: B14_0 Mask */
+#define LCD_PAL135_I1_Pos 31 /*!< LCD PAL135: I1 Position */
+#define LCD_PAL135_I1_Msk (0x01UL << LCD_PAL135_I1_Pos) /*!< LCD PAL135: I1 Mask */
+
+// --------------------------------------- LCD_PAL136 -------------------------------------------
+#define LCD_PAL136_R04_0_Pos 0 /*!< LCD PAL136: R04_0 Position */
+#define LCD_PAL136_R04_0_Msk (0x1fUL << LCD_PAL136_R04_0_Pos) /*!< LCD PAL136: R04_0 Mask */
+#define LCD_PAL136_G04_0_Pos 5 /*!< LCD PAL136: G04_0 Position */
+#define LCD_PAL136_G04_0_Msk (0x1fUL << LCD_PAL136_G04_0_Pos) /*!< LCD PAL136: G04_0 Mask */
+#define LCD_PAL136_B04_0_Pos 10 /*!< LCD PAL136: B04_0 Position */
+#define LCD_PAL136_B04_0_Msk (0x1fUL << LCD_PAL136_B04_0_Pos) /*!< LCD PAL136: B04_0 Mask */
+#define LCD_PAL136_I0_Pos 15 /*!< LCD PAL136: I0 Position */
+#define LCD_PAL136_I0_Msk (0x01UL << LCD_PAL136_I0_Pos) /*!< LCD PAL136: I0 Mask */
+#define LCD_PAL136_R14_0_Pos 16 /*!< LCD PAL136: R14_0 Position */
+#define LCD_PAL136_R14_0_Msk (0x1fUL << LCD_PAL136_R14_0_Pos) /*!< LCD PAL136: R14_0 Mask */
+#define LCD_PAL136_G14_0_Pos 21 /*!< LCD PAL136: G14_0 Position */
+#define LCD_PAL136_G14_0_Msk (0x1fUL << LCD_PAL136_G14_0_Pos) /*!< LCD PAL136: G14_0 Mask */
+#define LCD_PAL136_B14_0_Pos 26 /*!< LCD PAL136: B14_0 Position */
+#define LCD_PAL136_B14_0_Msk (0x1fUL << LCD_PAL136_B14_0_Pos) /*!< LCD PAL136: B14_0 Mask */
+#define LCD_PAL136_I1_Pos 31 /*!< LCD PAL136: I1 Position */
+#define LCD_PAL136_I1_Msk (0x01UL << LCD_PAL136_I1_Pos) /*!< LCD PAL136: I1 Mask */
+
+// --------------------------------------- LCD_PAL137 -------------------------------------------
+#define LCD_PAL137_R04_0_Pos 0 /*!< LCD PAL137: R04_0 Position */
+#define LCD_PAL137_R04_0_Msk (0x1fUL << LCD_PAL137_R04_0_Pos) /*!< LCD PAL137: R04_0 Mask */
+#define LCD_PAL137_G04_0_Pos 5 /*!< LCD PAL137: G04_0 Position */
+#define LCD_PAL137_G04_0_Msk (0x1fUL << LCD_PAL137_G04_0_Pos) /*!< LCD PAL137: G04_0 Mask */
+#define LCD_PAL137_B04_0_Pos 10 /*!< LCD PAL137: B04_0 Position */
+#define LCD_PAL137_B04_0_Msk (0x1fUL << LCD_PAL137_B04_0_Pos) /*!< LCD PAL137: B04_0 Mask */
+#define LCD_PAL137_I0_Pos 15 /*!< LCD PAL137: I0 Position */
+#define LCD_PAL137_I0_Msk (0x01UL << LCD_PAL137_I0_Pos) /*!< LCD PAL137: I0 Mask */
+#define LCD_PAL137_R14_0_Pos 16 /*!< LCD PAL137: R14_0 Position */
+#define LCD_PAL137_R14_0_Msk (0x1fUL << LCD_PAL137_R14_0_Pos) /*!< LCD PAL137: R14_0 Mask */
+#define LCD_PAL137_G14_0_Pos 21 /*!< LCD PAL137: G14_0 Position */
+#define LCD_PAL137_G14_0_Msk (0x1fUL << LCD_PAL137_G14_0_Pos) /*!< LCD PAL137: G14_0 Mask */
+#define LCD_PAL137_B14_0_Pos 26 /*!< LCD PAL137: B14_0 Position */
+#define LCD_PAL137_B14_0_Msk (0x1fUL << LCD_PAL137_B14_0_Pos) /*!< LCD PAL137: B14_0 Mask */
+#define LCD_PAL137_I1_Pos 31 /*!< LCD PAL137: I1 Position */
+#define LCD_PAL137_I1_Msk (0x01UL << LCD_PAL137_I1_Pos) /*!< LCD PAL137: I1 Mask */
+
+// --------------------------------------- LCD_PAL138 -------------------------------------------
+#define LCD_PAL138_R04_0_Pos 0 /*!< LCD PAL138: R04_0 Position */
+#define LCD_PAL138_R04_0_Msk (0x1fUL << LCD_PAL138_R04_0_Pos) /*!< LCD PAL138: R04_0 Mask */
+#define LCD_PAL138_G04_0_Pos 5 /*!< LCD PAL138: G04_0 Position */
+#define LCD_PAL138_G04_0_Msk (0x1fUL << LCD_PAL138_G04_0_Pos) /*!< LCD PAL138: G04_0 Mask */
+#define LCD_PAL138_B04_0_Pos 10 /*!< LCD PAL138: B04_0 Position */
+#define LCD_PAL138_B04_0_Msk (0x1fUL << LCD_PAL138_B04_0_Pos) /*!< LCD PAL138: B04_0 Mask */
+#define LCD_PAL138_I0_Pos 15 /*!< LCD PAL138: I0 Position */
+#define LCD_PAL138_I0_Msk (0x01UL << LCD_PAL138_I0_Pos) /*!< LCD PAL138: I0 Mask */
+#define LCD_PAL138_R14_0_Pos 16 /*!< LCD PAL138: R14_0 Position */
+#define LCD_PAL138_R14_0_Msk (0x1fUL << LCD_PAL138_R14_0_Pos) /*!< LCD PAL138: R14_0 Mask */
+#define LCD_PAL138_G14_0_Pos 21 /*!< LCD PAL138: G14_0 Position */
+#define LCD_PAL138_G14_0_Msk (0x1fUL << LCD_PAL138_G14_0_Pos) /*!< LCD PAL138: G14_0 Mask */
+#define LCD_PAL138_B14_0_Pos 26 /*!< LCD PAL138: B14_0 Position */
+#define LCD_PAL138_B14_0_Msk (0x1fUL << LCD_PAL138_B14_0_Pos) /*!< LCD PAL138: B14_0 Mask */
+#define LCD_PAL138_I1_Pos 31 /*!< LCD PAL138: I1 Position */
+#define LCD_PAL138_I1_Msk (0x01UL << LCD_PAL138_I1_Pos) /*!< LCD PAL138: I1 Mask */
+
+// --------------------------------------- LCD_PAL139 -------------------------------------------
+#define LCD_PAL139_R04_0_Pos 0 /*!< LCD PAL139: R04_0 Position */
+#define LCD_PAL139_R04_0_Msk (0x1fUL << LCD_PAL139_R04_0_Pos) /*!< LCD PAL139: R04_0 Mask */
+#define LCD_PAL139_G04_0_Pos 5 /*!< LCD PAL139: G04_0 Position */
+#define LCD_PAL139_G04_0_Msk (0x1fUL << LCD_PAL139_G04_0_Pos) /*!< LCD PAL139: G04_0 Mask */
+#define LCD_PAL139_B04_0_Pos 10 /*!< LCD PAL139: B04_0 Position */
+#define LCD_PAL139_B04_0_Msk (0x1fUL << LCD_PAL139_B04_0_Pos) /*!< LCD PAL139: B04_0 Mask */
+#define LCD_PAL139_I0_Pos 15 /*!< LCD PAL139: I0 Position */
+#define LCD_PAL139_I0_Msk (0x01UL << LCD_PAL139_I0_Pos) /*!< LCD PAL139: I0 Mask */
+#define LCD_PAL139_R14_0_Pos 16 /*!< LCD PAL139: R14_0 Position */
+#define LCD_PAL139_R14_0_Msk (0x1fUL << LCD_PAL139_R14_0_Pos) /*!< LCD PAL139: R14_0 Mask */
+#define LCD_PAL139_G14_0_Pos 21 /*!< LCD PAL139: G14_0 Position */
+#define LCD_PAL139_G14_0_Msk (0x1fUL << LCD_PAL139_G14_0_Pos) /*!< LCD PAL139: G14_0 Mask */
+#define LCD_PAL139_B14_0_Pos 26 /*!< LCD PAL139: B14_0 Position */
+#define LCD_PAL139_B14_0_Msk (0x1fUL << LCD_PAL139_B14_0_Pos) /*!< LCD PAL139: B14_0 Mask */
+#define LCD_PAL139_I1_Pos 31 /*!< LCD PAL139: I1 Position */
+#define LCD_PAL139_I1_Msk (0x01UL << LCD_PAL139_I1_Pos) /*!< LCD PAL139: I1 Mask */
+
+// --------------------------------------- LCD_PAL140 -------------------------------------------
+#define LCD_PAL140_R04_0_Pos 0 /*!< LCD PAL140: R04_0 Position */
+#define LCD_PAL140_R04_0_Msk (0x1fUL << LCD_PAL140_R04_0_Pos) /*!< LCD PAL140: R04_0 Mask */
+#define LCD_PAL140_G04_0_Pos 5 /*!< LCD PAL140: G04_0 Position */
+#define LCD_PAL140_G04_0_Msk (0x1fUL << LCD_PAL140_G04_0_Pos) /*!< LCD PAL140: G04_0 Mask */
+#define LCD_PAL140_B04_0_Pos 10 /*!< LCD PAL140: B04_0 Position */
+#define LCD_PAL140_B04_0_Msk (0x1fUL << LCD_PAL140_B04_0_Pos) /*!< LCD PAL140: B04_0 Mask */
+#define LCD_PAL140_I0_Pos 15 /*!< LCD PAL140: I0 Position */
+#define LCD_PAL140_I0_Msk (0x01UL << LCD_PAL140_I0_Pos) /*!< LCD PAL140: I0 Mask */
+#define LCD_PAL140_R14_0_Pos 16 /*!< LCD PAL140: R14_0 Position */
+#define LCD_PAL140_R14_0_Msk (0x1fUL << LCD_PAL140_R14_0_Pos) /*!< LCD PAL140: R14_0 Mask */
+#define LCD_PAL140_G14_0_Pos 21 /*!< LCD PAL140: G14_0 Position */
+#define LCD_PAL140_G14_0_Msk (0x1fUL << LCD_PAL140_G14_0_Pos) /*!< LCD PAL140: G14_0 Mask */
+#define LCD_PAL140_B14_0_Pos 26 /*!< LCD PAL140: B14_0 Position */
+#define LCD_PAL140_B14_0_Msk (0x1fUL << LCD_PAL140_B14_0_Pos) /*!< LCD PAL140: B14_0 Mask */
+#define LCD_PAL140_I1_Pos 31 /*!< LCD PAL140: I1 Position */
+#define LCD_PAL140_I1_Msk (0x01UL << LCD_PAL140_I1_Pos) /*!< LCD PAL140: I1 Mask */
+
+// --------------------------------------- LCD_PAL141 -------------------------------------------
+#define LCD_PAL141_R04_0_Pos 0 /*!< LCD PAL141: R04_0 Position */
+#define LCD_PAL141_R04_0_Msk (0x1fUL << LCD_PAL141_R04_0_Pos) /*!< LCD PAL141: R04_0 Mask */
+#define LCD_PAL141_G04_0_Pos 5 /*!< LCD PAL141: G04_0 Position */
+#define LCD_PAL141_G04_0_Msk (0x1fUL << LCD_PAL141_G04_0_Pos) /*!< LCD PAL141: G04_0 Mask */
+#define LCD_PAL141_B04_0_Pos 10 /*!< LCD PAL141: B04_0 Position */
+#define LCD_PAL141_B04_0_Msk (0x1fUL << LCD_PAL141_B04_0_Pos) /*!< LCD PAL141: B04_0 Mask */
+#define LCD_PAL141_I0_Pos 15 /*!< LCD PAL141: I0 Position */
+#define LCD_PAL141_I0_Msk (0x01UL << LCD_PAL141_I0_Pos) /*!< LCD PAL141: I0 Mask */
+#define LCD_PAL141_R14_0_Pos 16 /*!< LCD PAL141: R14_0 Position */
+#define LCD_PAL141_R14_0_Msk (0x1fUL << LCD_PAL141_R14_0_Pos) /*!< LCD PAL141: R14_0 Mask */
+#define LCD_PAL141_G14_0_Pos 21 /*!< LCD PAL141: G14_0 Position */
+#define LCD_PAL141_G14_0_Msk (0x1fUL << LCD_PAL141_G14_0_Pos) /*!< LCD PAL141: G14_0 Mask */
+#define LCD_PAL141_B14_0_Pos 26 /*!< LCD PAL141: B14_0 Position */
+#define LCD_PAL141_B14_0_Msk (0x1fUL << LCD_PAL141_B14_0_Pos) /*!< LCD PAL141: B14_0 Mask */
+#define LCD_PAL141_I1_Pos 31 /*!< LCD PAL141: I1 Position */
+#define LCD_PAL141_I1_Msk (0x01UL << LCD_PAL141_I1_Pos) /*!< LCD PAL141: I1 Mask */
+
+// --------------------------------------- LCD_PAL142 -------------------------------------------
+#define LCD_PAL142_R04_0_Pos 0 /*!< LCD PAL142: R04_0 Position */
+#define LCD_PAL142_R04_0_Msk (0x1fUL << LCD_PAL142_R04_0_Pos) /*!< LCD PAL142: R04_0 Mask */
+#define LCD_PAL142_G04_0_Pos 5 /*!< LCD PAL142: G04_0 Position */
+#define LCD_PAL142_G04_0_Msk (0x1fUL << LCD_PAL142_G04_0_Pos) /*!< LCD PAL142: G04_0 Mask */
+#define LCD_PAL142_B04_0_Pos 10 /*!< LCD PAL142: B04_0 Position */
+#define LCD_PAL142_B04_0_Msk (0x1fUL << LCD_PAL142_B04_0_Pos) /*!< LCD PAL142: B04_0 Mask */
+#define LCD_PAL142_I0_Pos 15 /*!< LCD PAL142: I0 Position */
+#define LCD_PAL142_I0_Msk (0x01UL << LCD_PAL142_I0_Pos) /*!< LCD PAL142: I0 Mask */
+#define LCD_PAL142_R14_0_Pos 16 /*!< LCD PAL142: R14_0 Position */
+#define LCD_PAL142_R14_0_Msk (0x1fUL << LCD_PAL142_R14_0_Pos) /*!< LCD PAL142: R14_0 Mask */
+#define LCD_PAL142_G14_0_Pos 21 /*!< LCD PAL142: G14_0 Position */
+#define LCD_PAL142_G14_0_Msk (0x1fUL << LCD_PAL142_G14_0_Pos) /*!< LCD PAL142: G14_0 Mask */
+#define LCD_PAL142_B14_0_Pos 26 /*!< LCD PAL142: B14_0 Position */
+#define LCD_PAL142_B14_0_Msk (0x1fUL << LCD_PAL142_B14_0_Pos) /*!< LCD PAL142: B14_0 Mask */
+#define LCD_PAL142_I1_Pos 31 /*!< LCD PAL142: I1 Position */
+#define LCD_PAL142_I1_Msk (0x01UL << LCD_PAL142_I1_Pos) /*!< LCD PAL142: I1 Mask */
+
+// --------------------------------------- LCD_PAL143 -------------------------------------------
+#define LCD_PAL143_R04_0_Pos 0 /*!< LCD PAL143: R04_0 Position */
+#define LCD_PAL143_R04_0_Msk (0x1fUL << LCD_PAL143_R04_0_Pos) /*!< LCD PAL143: R04_0 Mask */
+#define LCD_PAL143_G04_0_Pos 5 /*!< LCD PAL143: G04_0 Position */
+#define LCD_PAL143_G04_0_Msk (0x1fUL << LCD_PAL143_G04_0_Pos) /*!< LCD PAL143: G04_0 Mask */
+#define LCD_PAL143_B04_0_Pos 10 /*!< LCD PAL143: B04_0 Position */
+#define LCD_PAL143_B04_0_Msk (0x1fUL << LCD_PAL143_B04_0_Pos) /*!< LCD PAL143: B04_0 Mask */
+#define LCD_PAL143_I0_Pos 15 /*!< LCD PAL143: I0 Position */
+#define LCD_PAL143_I0_Msk (0x01UL << LCD_PAL143_I0_Pos) /*!< LCD PAL143: I0 Mask */
+#define LCD_PAL143_R14_0_Pos 16 /*!< LCD PAL143: R14_0 Position */
+#define LCD_PAL143_R14_0_Msk (0x1fUL << LCD_PAL143_R14_0_Pos) /*!< LCD PAL143: R14_0 Mask */
+#define LCD_PAL143_G14_0_Pos 21 /*!< LCD PAL143: G14_0 Position */
+#define LCD_PAL143_G14_0_Msk (0x1fUL << LCD_PAL143_G14_0_Pos) /*!< LCD PAL143: G14_0 Mask */
+#define LCD_PAL143_B14_0_Pos 26 /*!< LCD PAL143: B14_0 Position */
+#define LCD_PAL143_B14_0_Msk (0x1fUL << LCD_PAL143_B14_0_Pos) /*!< LCD PAL143: B14_0 Mask */
+#define LCD_PAL143_I1_Pos 31 /*!< LCD PAL143: I1 Position */
+#define LCD_PAL143_I1_Msk (0x01UL << LCD_PAL143_I1_Pos) /*!< LCD PAL143: I1 Mask */
+
+// --------------------------------------- LCD_PAL144 -------------------------------------------
+#define LCD_PAL144_R04_0_Pos 0 /*!< LCD PAL144: R04_0 Position */
+#define LCD_PAL144_R04_0_Msk (0x1fUL << LCD_PAL144_R04_0_Pos) /*!< LCD PAL144: R04_0 Mask */
+#define LCD_PAL144_G04_0_Pos 5 /*!< LCD PAL144: G04_0 Position */
+#define LCD_PAL144_G04_0_Msk (0x1fUL << LCD_PAL144_G04_0_Pos) /*!< LCD PAL144: G04_0 Mask */
+#define LCD_PAL144_B04_0_Pos 10 /*!< LCD PAL144: B04_0 Position */
+#define LCD_PAL144_B04_0_Msk (0x1fUL << LCD_PAL144_B04_0_Pos) /*!< LCD PAL144: B04_0 Mask */
+#define LCD_PAL144_I0_Pos 15 /*!< LCD PAL144: I0 Position */
+#define LCD_PAL144_I0_Msk (0x01UL << LCD_PAL144_I0_Pos) /*!< LCD PAL144: I0 Mask */
+#define LCD_PAL144_R14_0_Pos 16 /*!< LCD PAL144: R14_0 Position */
+#define LCD_PAL144_R14_0_Msk (0x1fUL << LCD_PAL144_R14_0_Pos) /*!< LCD PAL144: R14_0 Mask */
+#define LCD_PAL144_G14_0_Pos 21 /*!< LCD PAL144: G14_0 Position */
+#define LCD_PAL144_G14_0_Msk (0x1fUL << LCD_PAL144_G14_0_Pos) /*!< LCD PAL144: G14_0 Mask */
+#define LCD_PAL144_B14_0_Pos 26 /*!< LCD PAL144: B14_0 Position */
+#define LCD_PAL144_B14_0_Msk (0x1fUL << LCD_PAL144_B14_0_Pos) /*!< LCD PAL144: B14_0 Mask */
+#define LCD_PAL144_I1_Pos 31 /*!< LCD PAL144: I1 Position */
+#define LCD_PAL144_I1_Msk (0x01UL << LCD_PAL144_I1_Pos) /*!< LCD PAL144: I1 Mask */
+
+// --------------------------------------- LCD_PAL145 -------------------------------------------
+#define LCD_PAL145_R04_0_Pos 0 /*!< LCD PAL145: R04_0 Position */
+#define LCD_PAL145_R04_0_Msk (0x1fUL << LCD_PAL145_R04_0_Pos) /*!< LCD PAL145: R04_0 Mask */
+#define LCD_PAL145_G04_0_Pos 5 /*!< LCD PAL145: G04_0 Position */
+#define LCD_PAL145_G04_0_Msk (0x1fUL << LCD_PAL145_G04_0_Pos) /*!< LCD PAL145: G04_0 Mask */
+#define LCD_PAL145_B04_0_Pos 10 /*!< LCD PAL145: B04_0 Position */
+#define LCD_PAL145_B04_0_Msk (0x1fUL << LCD_PAL145_B04_0_Pos) /*!< LCD PAL145: B04_0 Mask */
+#define LCD_PAL145_I0_Pos 15 /*!< LCD PAL145: I0 Position */
+#define LCD_PAL145_I0_Msk (0x01UL << LCD_PAL145_I0_Pos) /*!< LCD PAL145: I0 Mask */
+#define LCD_PAL145_R14_0_Pos 16 /*!< LCD PAL145: R14_0 Position */
+#define LCD_PAL145_R14_0_Msk (0x1fUL << LCD_PAL145_R14_0_Pos) /*!< LCD PAL145: R14_0 Mask */
+#define LCD_PAL145_G14_0_Pos 21 /*!< LCD PAL145: G14_0 Position */
+#define LCD_PAL145_G14_0_Msk (0x1fUL << LCD_PAL145_G14_0_Pos) /*!< LCD PAL145: G14_0 Mask */
+#define LCD_PAL145_B14_0_Pos 26 /*!< LCD PAL145: B14_0 Position */
+#define LCD_PAL145_B14_0_Msk (0x1fUL << LCD_PAL145_B14_0_Pos) /*!< LCD PAL145: B14_0 Mask */
+#define LCD_PAL145_I1_Pos 31 /*!< LCD PAL145: I1 Position */
+#define LCD_PAL145_I1_Msk (0x01UL << LCD_PAL145_I1_Pos) /*!< LCD PAL145: I1 Mask */
+
+// --------------------------------------- LCD_PAL146 -------------------------------------------
+#define LCD_PAL146_R04_0_Pos 0 /*!< LCD PAL146: R04_0 Position */
+#define LCD_PAL146_R04_0_Msk (0x1fUL << LCD_PAL146_R04_0_Pos) /*!< LCD PAL146: R04_0 Mask */
+#define LCD_PAL146_G04_0_Pos 5 /*!< LCD PAL146: G04_0 Position */
+#define LCD_PAL146_G04_0_Msk (0x1fUL << LCD_PAL146_G04_0_Pos) /*!< LCD PAL146: G04_0 Mask */
+#define LCD_PAL146_B04_0_Pos 10 /*!< LCD PAL146: B04_0 Position */
+#define LCD_PAL146_B04_0_Msk (0x1fUL << LCD_PAL146_B04_0_Pos) /*!< LCD PAL146: B04_0 Mask */
+#define LCD_PAL146_I0_Pos 15 /*!< LCD PAL146: I0 Position */
+#define LCD_PAL146_I0_Msk (0x01UL << LCD_PAL146_I0_Pos) /*!< LCD PAL146: I0 Mask */
+#define LCD_PAL146_R14_0_Pos 16 /*!< LCD PAL146: R14_0 Position */
+#define LCD_PAL146_R14_0_Msk (0x1fUL << LCD_PAL146_R14_0_Pos) /*!< LCD PAL146: R14_0 Mask */
+#define LCD_PAL146_G14_0_Pos 21 /*!< LCD PAL146: G14_0 Position */
+#define LCD_PAL146_G14_0_Msk (0x1fUL << LCD_PAL146_G14_0_Pos) /*!< LCD PAL146: G14_0 Mask */
+#define LCD_PAL146_B14_0_Pos 26 /*!< LCD PAL146: B14_0 Position */
+#define LCD_PAL146_B14_0_Msk (0x1fUL << LCD_PAL146_B14_0_Pos) /*!< LCD PAL146: B14_0 Mask */
+#define LCD_PAL146_I1_Pos 31 /*!< LCD PAL146: I1 Position */
+#define LCD_PAL146_I1_Msk (0x01UL << LCD_PAL146_I1_Pos) /*!< LCD PAL146: I1 Mask */
+
+// --------------------------------------- LCD_PAL147 -------------------------------------------
+#define LCD_PAL147_R04_0_Pos 0 /*!< LCD PAL147: R04_0 Position */
+#define LCD_PAL147_R04_0_Msk (0x1fUL << LCD_PAL147_R04_0_Pos) /*!< LCD PAL147: R04_0 Mask */
+#define LCD_PAL147_G04_0_Pos 5 /*!< LCD PAL147: G04_0 Position */
+#define LCD_PAL147_G04_0_Msk (0x1fUL << LCD_PAL147_G04_0_Pos) /*!< LCD PAL147: G04_0 Mask */
+#define LCD_PAL147_B04_0_Pos 10 /*!< LCD PAL147: B04_0 Position */
+#define LCD_PAL147_B04_0_Msk (0x1fUL << LCD_PAL147_B04_0_Pos) /*!< LCD PAL147: B04_0 Mask */
+#define LCD_PAL147_I0_Pos 15 /*!< LCD PAL147: I0 Position */
+#define LCD_PAL147_I0_Msk (0x01UL << LCD_PAL147_I0_Pos) /*!< LCD PAL147: I0 Mask */
+#define LCD_PAL147_R14_0_Pos 16 /*!< LCD PAL147: R14_0 Position */
+#define LCD_PAL147_R14_0_Msk (0x1fUL << LCD_PAL147_R14_0_Pos) /*!< LCD PAL147: R14_0 Mask */
+#define LCD_PAL147_G14_0_Pos 21 /*!< LCD PAL147: G14_0 Position */
+#define LCD_PAL147_G14_0_Msk (0x1fUL << LCD_PAL147_G14_0_Pos) /*!< LCD PAL147: G14_0 Mask */
+#define LCD_PAL147_B14_0_Pos 26 /*!< LCD PAL147: B14_0 Position */
+#define LCD_PAL147_B14_0_Msk (0x1fUL << LCD_PAL147_B14_0_Pos) /*!< LCD PAL147: B14_0 Mask */
+#define LCD_PAL147_I1_Pos 31 /*!< LCD PAL147: I1 Position */
+#define LCD_PAL147_I1_Msk (0x01UL << LCD_PAL147_I1_Pos) /*!< LCD PAL147: I1 Mask */
+
+// --------------------------------------- LCD_PAL148 -------------------------------------------
+#define LCD_PAL148_R04_0_Pos 0 /*!< LCD PAL148: R04_0 Position */
+#define LCD_PAL148_R04_0_Msk (0x1fUL << LCD_PAL148_R04_0_Pos) /*!< LCD PAL148: R04_0 Mask */
+#define LCD_PAL148_G04_0_Pos 5 /*!< LCD PAL148: G04_0 Position */
+#define LCD_PAL148_G04_0_Msk (0x1fUL << LCD_PAL148_G04_0_Pos) /*!< LCD PAL148: G04_0 Mask */
+#define LCD_PAL148_B04_0_Pos 10 /*!< LCD PAL148: B04_0 Position */
+#define LCD_PAL148_B04_0_Msk (0x1fUL << LCD_PAL148_B04_0_Pos) /*!< LCD PAL148: B04_0 Mask */
+#define LCD_PAL148_I0_Pos 15 /*!< LCD PAL148: I0 Position */
+#define LCD_PAL148_I0_Msk (0x01UL << LCD_PAL148_I0_Pos) /*!< LCD PAL148: I0 Mask */
+#define LCD_PAL148_R14_0_Pos 16 /*!< LCD PAL148: R14_0 Position */
+#define LCD_PAL148_R14_0_Msk (0x1fUL << LCD_PAL148_R14_0_Pos) /*!< LCD PAL148: R14_0 Mask */
+#define LCD_PAL148_G14_0_Pos 21 /*!< LCD PAL148: G14_0 Position */
+#define LCD_PAL148_G14_0_Msk (0x1fUL << LCD_PAL148_G14_0_Pos) /*!< LCD PAL148: G14_0 Mask */
+#define LCD_PAL148_B14_0_Pos 26 /*!< LCD PAL148: B14_0 Position */
+#define LCD_PAL148_B14_0_Msk (0x1fUL << LCD_PAL148_B14_0_Pos) /*!< LCD PAL148: B14_0 Mask */
+#define LCD_PAL148_I1_Pos 31 /*!< LCD PAL148: I1 Position */
+#define LCD_PAL148_I1_Msk (0x01UL << LCD_PAL148_I1_Pos) /*!< LCD PAL148: I1 Mask */
+
+// --------------------------------------- LCD_PAL149 -------------------------------------------
+#define LCD_PAL149_R04_0_Pos 0 /*!< LCD PAL149: R04_0 Position */
+#define LCD_PAL149_R04_0_Msk (0x1fUL << LCD_PAL149_R04_0_Pos) /*!< LCD PAL149: R04_0 Mask */
+#define LCD_PAL149_G04_0_Pos 5 /*!< LCD PAL149: G04_0 Position */
+#define LCD_PAL149_G04_0_Msk (0x1fUL << LCD_PAL149_G04_0_Pos) /*!< LCD PAL149: G04_0 Mask */
+#define LCD_PAL149_B04_0_Pos 10 /*!< LCD PAL149: B04_0 Position */
+#define LCD_PAL149_B04_0_Msk (0x1fUL << LCD_PAL149_B04_0_Pos) /*!< LCD PAL149: B04_0 Mask */
+#define LCD_PAL149_I0_Pos 15 /*!< LCD PAL149: I0 Position */
+#define LCD_PAL149_I0_Msk (0x01UL << LCD_PAL149_I0_Pos) /*!< LCD PAL149: I0 Mask */
+#define LCD_PAL149_R14_0_Pos 16 /*!< LCD PAL149: R14_0 Position */
+#define LCD_PAL149_R14_0_Msk (0x1fUL << LCD_PAL149_R14_0_Pos) /*!< LCD PAL149: R14_0 Mask */
+#define LCD_PAL149_G14_0_Pos 21 /*!< LCD PAL149: G14_0 Position */
+#define LCD_PAL149_G14_0_Msk (0x1fUL << LCD_PAL149_G14_0_Pos) /*!< LCD PAL149: G14_0 Mask */
+#define LCD_PAL149_B14_0_Pos 26 /*!< LCD PAL149: B14_0 Position */
+#define LCD_PAL149_B14_0_Msk (0x1fUL << LCD_PAL149_B14_0_Pos) /*!< LCD PAL149: B14_0 Mask */
+#define LCD_PAL149_I1_Pos 31 /*!< LCD PAL149: I1 Position */
+#define LCD_PAL149_I1_Msk (0x01UL << LCD_PAL149_I1_Pos) /*!< LCD PAL149: I1 Mask */
+
+// --------------------------------------- LCD_PAL150 -------------------------------------------
+#define LCD_PAL150_R04_0_Pos 0 /*!< LCD PAL150: R04_0 Position */
+#define LCD_PAL150_R04_0_Msk (0x1fUL << LCD_PAL150_R04_0_Pos) /*!< LCD PAL150: R04_0 Mask */
+#define LCD_PAL150_G04_0_Pos 5 /*!< LCD PAL150: G04_0 Position */
+#define LCD_PAL150_G04_0_Msk (0x1fUL << LCD_PAL150_G04_0_Pos) /*!< LCD PAL150: G04_0 Mask */
+#define LCD_PAL150_B04_0_Pos 10 /*!< LCD PAL150: B04_0 Position */
+#define LCD_PAL150_B04_0_Msk (0x1fUL << LCD_PAL150_B04_0_Pos) /*!< LCD PAL150: B04_0 Mask */
+#define LCD_PAL150_I0_Pos 15 /*!< LCD PAL150: I0 Position */
+#define LCD_PAL150_I0_Msk (0x01UL << LCD_PAL150_I0_Pos) /*!< LCD PAL150: I0 Mask */
+#define LCD_PAL150_R14_0_Pos 16 /*!< LCD PAL150: R14_0 Position */
+#define LCD_PAL150_R14_0_Msk (0x1fUL << LCD_PAL150_R14_0_Pos) /*!< LCD PAL150: R14_0 Mask */
+#define LCD_PAL150_G14_0_Pos 21 /*!< LCD PAL150: G14_0 Position */
+#define LCD_PAL150_G14_0_Msk (0x1fUL << LCD_PAL150_G14_0_Pos) /*!< LCD PAL150: G14_0 Mask */
+#define LCD_PAL150_B14_0_Pos 26 /*!< LCD PAL150: B14_0 Position */
+#define LCD_PAL150_B14_0_Msk (0x1fUL << LCD_PAL150_B14_0_Pos) /*!< LCD PAL150: B14_0 Mask */
+#define LCD_PAL150_I1_Pos 31 /*!< LCD PAL150: I1 Position */
+#define LCD_PAL150_I1_Msk (0x01UL << LCD_PAL150_I1_Pos) /*!< LCD PAL150: I1 Mask */
+
+// --------------------------------------- LCD_PAL151 -------------------------------------------
+#define LCD_PAL151_R04_0_Pos 0 /*!< LCD PAL151: R04_0 Position */
+#define LCD_PAL151_R04_0_Msk (0x1fUL << LCD_PAL151_R04_0_Pos) /*!< LCD PAL151: R04_0 Mask */
+#define LCD_PAL151_G04_0_Pos 5 /*!< LCD PAL151: G04_0 Position */
+#define LCD_PAL151_G04_0_Msk (0x1fUL << LCD_PAL151_G04_0_Pos) /*!< LCD PAL151: G04_0 Mask */
+#define LCD_PAL151_B04_0_Pos 10 /*!< LCD PAL151: B04_0 Position */
+#define LCD_PAL151_B04_0_Msk (0x1fUL << LCD_PAL151_B04_0_Pos) /*!< LCD PAL151: B04_0 Mask */
+#define LCD_PAL151_I0_Pos 15 /*!< LCD PAL151: I0 Position */
+#define LCD_PAL151_I0_Msk (0x01UL << LCD_PAL151_I0_Pos) /*!< LCD PAL151: I0 Mask */
+#define LCD_PAL151_R14_0_Pos 16 /*!< LCD PAL151: R14_0 Position */
+#define LCD_PAL151_R14_0_Msk (0x1fUL << LCD_PAL151_R14_0_Pos) /*!< LCD PAL151: R14_0 Mask */
+#define LCD_PAL151_G14_0_Pos 21 /*!< LCD PAL151: G14_0 Position */
+#define LCD_PAL151_G14_0_Msk (0x1fUL << LCD_PAL151_G14_0_Pos) /*!< LCD PAL151: G14_0 Mask */
+#define LCD_PAL151_B14_0_Pos 26 /*!< LCD PAL151: B14_0 Position */
+#define LCD_PAL151_B14_0_Msk (0x1fUL << LCD_PAL151_B14_0_Pos) /*!< LCD PAL151: B14_0 Mask */
+#define LCD_PAL151_I1_Pos 31 /*!< LCD PAL151: I1 Position */
+#define LCD_PAL151_I1_Msk (0x01UL << LCD_PAL151_I1_Pos) /*!< LCD PAL151: I1 Mask */
+
+// --------------------------------------- LCD_PAL152 -------------------------------------------
+#define LCD_PAL152_R04_0_Pos 0 /*!< LCD PAL152: R04_0 Position */
+#define LCD_PAL152_R04_0_Msk (0x1fUL << LCD_PAL152_R04_0_Pos) /*!< LCD PAL152: R04_0 Mask */
+#define LCD_PAL152_G04_0_Pos 5 /*!< LCD PAL152: G04_0 Position */
+#define LCD_PAL152_G04_0_Msk (0x1fUL << LCD_PAL152_G04_0_Pos) /*!< LCD PAL152: G04_0 Mask */
+#define LCD_PAL152_B04_0_Pos 10 /*!< LCD PAL152: B04_0 Position */
+#define LCD_PAL152_B04_0_Msk (0x1fUL << LCD_PAL152_B04_0_Pos) /*!< LCD PAL152: B04_0 Mask */
+#define LCD_PAL152_I0_Pos 15 /*!< LCD PAL152: I0 Position */
+#define LCD_PAL152_I0_Msk (0x01UL << LCD_PAL152_I0_Pos) /*!< LCD PAL152: I0 Mask */
+#define LCD_PAL152_R14_0_Pos 16 /*!< LCD PAL152: R14_0 Position */
+#define LCD_PAL152_R14_0_Msk (0x1fUL << LCD_PAL152_R14_0_Pos) /*!< LCD PAL152: R14_0 Mask */
+#define LCD_PAL152_G14_0_Pos 21 /*!< LCD PAL152: G14_0 Position */
+#define LCD_PAL152_G14_0_Msk (0x1fUL << LCD_PAL152_G14_0_Pos) /*!< LCD PAL152: G14_0 Mask */
+#define LCD_PAL152_B14_0_Pos 26 /*!< LCD PAL152: B14_0 Position */
+#define LCD_PAL152_B14_0_Msk (0x1fUL << LCD_PAL152_B14_0_Pos) /*!< LCD PAL152: B14_0 Mask */
+#define LCD_PAL152_I1_Pos 31 /*!< LCD PAL152: I1 Position */
+#define LCD_PAL152_I1_Msk (0x01UL << LCD_PAL152_I1_Pos) /*!< LCD PAL152: I1 Mask */
+
+// --------------------------------------- LCD_PAL153 -------------------------------------------
+#define LCD_PAL153_R04_0_Pos 0 /*!< LCD PAL153: R04_0 Position */
+#define LCD_PAL153_R04_0_Msk (0x1fUL << LCD_PAL153_R04_0_Pos) /*!< LCD PAL153: R04_0 Mask */
+#define LCD_PAL153_G04_0_Pos 5 /*!< LCD PAL153: G04_0 Position */
+#define LCD_PAL153_G04_0_Msk (0x1fUL << LCD_PAL153_G04_0_Pos) /*!< LCD PAL153: G04_0 Mask */
+#define LCD_PAL153_B04_0_Pos 10 /*!< LCD PAL153: B04_0 Position */
+#define LCD_PAL153_B04_0_Msk (0x1fUL << LCD_PAL153_B04_0_Pos) /*!< LCD PAL153: B04_0 Mask */
+#define LCD_PAL153_I0_Pos 15 /*!< LCD PAL153: I0 Position */
+#define LCD_PAL153_I0_Msk (0x01UL << LCD_PAL153_I0_Pos) /*!< LCD PAL153: I0 Mask */
+#define LCD_PAL153_R14_0_Pos 16 /*!< LCD PAL153: R14_0 Position */
+#define LCD_PAL153_R14_0_Msk (0x1fUL << LCD_PAL153_R14_0_Pos) /*!< LCD PAL153: R14_0 Mask */
+#define LCD_PAL153_G14_0_Pos 21 /*!< LCD PAL153: G14_0 Position */
+#define LCD_PAL153_G14_0_Msk (0x1fUL << LCD_PAL153_G14_0_Pos) /*!< LCD PAL153: G14_0 Mask */
+#define LCD_PAL153_B14_0_Pos 26 /*!< LCD PAL153: B14_0 Position */
+#define LCD_PAL153_B14_0_Msk (0x1fUL << LCD_PAL153_B14_0_Pos) /*!< LCD PAL153: B14_0 Mask */
+#define LCD_PAL153_I1_Pos 31 /*!< LCD PAL153: I1 Position */
+#define LCD_PAL153_I1_Msk (0x01UL << LCD_PAL153_I1_Pos) /*!< LCD PAL153: I1 Mask */
+
+// --------------------------------------- LCD_PAL154 -------------------------------------------
+#define LCD_PAL154_R04_0_Pos 0 /*!< LCD PAL154: R04_0 Position */
+#define LCD_PAL154_R04_0_Msk (0x1fUL << LCD_PAL154_R04_0_Pos) /*!< LCD PAL154: R04_0 Mask */
+#define LCD_PAL154_G04_0_Pos 5 /*!< LCD PAL154: G04_0 Position */
+#define LCD_PAL154_G04_0_Msk (0x1fUL << LCD_PAL154_G04_0_Pos) /*!< LCD PAL154: G04_0 Mask */
+#define LCD_PAL154_B04_0_Pos 10 /*!< LCD PAL154: B04_0 Position */
+#define LCD_PAL154_B04_0_Msk (0x1fUL << LCD_PAL154_B04_0_Pos) /*!< LCD PAL154: B04_0 Mask */
+#define LCD_PAL154_I0_Pos 15 /*!< LCD PAL154: I0 Position */
+#define LCD_PAL154_I0_Msk (0x01UL << LCD_PAL154_I0_Pos) /*!< LCD PAL154: I0 Mask */
+#define LCD_PAL154_R14_0_Pos 16 /*!< LCD PAL154: R14_0 Position */
+#define LCD_PAL154_R14_0_Msk (0x1fUL << LCD_PAL154_R14_0_Pos) /*!< LCD PAL154: R14_0 Mask */
+#define LCD_PAL154_G14_0_Pos 21 /*!< LCD PAL154: G14_0 Position */
+#define LCD_PAL154_G14_0_Msk (0x1fUL << LCD_PAL154_G14_0_Pos) /*!< LCD PAL154: G14_0 Mask */
+#define LCD_PAL154_B14_0_Pos 26 /*!< LCD PAL154: B14_0 Position */
+#define LCD_PAL154_B14_0_Msk (0x1fUL << LCD_PAL154_B14_0_Pos) /*!< LCD PAL154: B14_0 Mask */
+#define LCD_PAL154_I1_Pos 31 /*!< LCD PAL154: I1 Position */
+#define LCD_PAL154_I1_Msk (0x01UL << LCD_PAL154_I1_Pos) /*!< LCD PAL154: I1 Mask */
+
+// --------------------------------------- LCD_PAL155 -------------------------------------------
+#define LCD_PAL155_R04_0_Pos 0 /*!< LCD PAL155: R04_0 Position */
+#define LCD_PAL155_R04_0_Msk (0x1fUL << LCD_PAL155_R04_0_Pos) /*!< LCD PAL155: R04_0 Mask */
+#define LCD_PAL155_G04_0_Pos 5 /*!< LCD PAL155: G04_0 Position */
+#define LCD_PAL155_G04_0_Msk (0x1fUL << LCD_PAL155_G04_0_Pos) /*!< LCD PAL155: G04_0 Mask */
+#define LCD_PAL155_B04_0_Pos 10 /*!< LCD PAL155: B04_0 Position */
+#define LCD_PAL155_B04_0_Msk (0x1fUL << LCD_PAL155_B04_0_Pos) /*!< LCD PAL155: B04_0 Mask */
+#define LCD_PAL155_I0_Pos 15 /*!< LCD PAL155: I0 Position */
+#define LCD_PAL155_I0_Msk (0x01UL << LCD_PAL155_I0_Pos) /*!< LCD PAL155: I0 Mask */
+#define LCD_PAL155_R14_0_Pos 16 /*!< LCD PAL155: R14_0 Position */
+#define LCD_PAL155_R14_0_Msk (0x1fUL << LCD_PAL155_R14_0_Pos) /*!< LCD PAL155: R14_0 Mask */
+#define LCD_PAL155_G14_0_Pos 21 /*!< LCD PAL155: G14_0 Position */
+#define LCD_PAL155_G14_0_Msk (0x1fUL << LCD_PAL155_G14_0_Pos) /*!< LCD PAL155: G14_0 Mask */
+#define LCD_PAL155_B14_0_Pos 26 /*!< LCD PAL155: B14_0 Position */
+#define LCD_PAL155_B14_0_Msk (0x1fUL << LCD_PAL155_B14_0_Pos) /*!< LCD PAL155: B14_0 Mask */
+#define LCD_PAL155_I1_Pos 31 /*!< LCD PAL155: I1 Position */
+#define LCD_PAL155_I1_Msk (0x01UL << LCD_PAL155_I1_Pos) /*!< LCD PAL155: I1 Mask */
+
+// --------------------------------------- LCD_PAL156 -------------------------------------------
+#define LCD_PAL156_R04_0_Pos 0 /*!< LCD PAL156: R04_0 Position */
+#define LCD_PAL156_R04_0_Msk (0x1fUL << LCD_PAL156_R04_0_Pos) /*!< LCD PAL156: R04_0 Mask */
+#define LCD_PAL156_G04_0_Pos 5 /*!< LCD PAL156: G04_0 Position */
+#define LCD_PAL156_G04_0_Msk (0x1fUL << LCD_PAL156_G04_0_Pos) /*!< LCD PAL156: G04_0 Mask */
+#define LCD_PAL156_B04_0_Pos 10 /*!< LCD PAL156: B04_0 Position */
+#define LCD_PAL156_B04_0_Msk (0x1fUL << LCD_PAL156_B04_0_Pos) /*!< LCD PAL156: B04_0 Mask */
+#define LCD_PAL156_I0_Pos 15 /*!< LCD PAL156: I0 Position */
+#define LCD_PAL156_I0_Msk (0x01UL << LCD_PAL156_I0_Pos) /*!< LCD PAL156: I0 Mask */
+#define LCD_PAL156_R14_0_Pos 16 /*!< LCD PAL156: R14_0 Position */
+#define LCD_PAL156_R14_0_Msk (0x1fUL << LCD_PAL156_R14_0_Pos) /*!< LCD PAL156: R14_0 Mask */
+#define LCD_PAL156_G14_0_Pos 21 /*!< LCD PAL156: G14_0 Position */
+#define LCD_PAL156_G14_0_Msk (0x1fUL << LCD_PAL156_G14_0_Pos) /*!< LCD PAL156: G14_0 Mask */
+#define LCD_PAL156_B14_0_Pos 26 /*!< LCD PAL156: B14_0 Position */
+#define LCD_PAL156_B14_0_Msk (0x1fUL << LCD_PAL156_B14_0_Pos) /*!< LCD PAL156: B14_0 Mask */
+#define LCD_PAL156_I1_Pos 31 /*!< LCD PAL156: I1 Position */
+#define LCD_PAL156_I1_Msk (0x01UL << LCD_PAL156_I1_Pos) /*!< LCD PAL156: I1 Mask */
+
+// --------------------------------------- LCD_PAL157 -------------------------------------------
+#define LCD_PAL157_R04_0_Pos 0 /*!< LCD PAL157: R04_0 Position */
+#define LCD_PAL157_R04_0_Msk (0x1fUL << LCD_PAL157_R04_0_Pos) /*!< LCD PAL157: R04_0 Mask */
+#define LCD_PAL157_G04_0_Pos 5 /*!< LCD PAL157: G04_0 Position */
+#define LCD_PAL157_G04_0_Msk (0x1fUL << LCD_PAL157_G04_0_Pos) /*!< LCD PAL157: G04_0 Mask */
+#define LCD_PAL157_B04_0_Pos 10 /*!< LCD PAL157: B04_0 Position */
+#define LCD_PAL157_B04_0_Msk (0x1fUL << LCD_PAL157_B04_0_Pos) /*!< LCD PAL157: B04_0 Mask */
+#define LCD_PAL157_I0_Pos 15 /*!< LCD PAL157: I0 Position */
+#define LCD_PAL157_I0_Msk (0x01UL << LCD_PAL157_I0_Pos) /*!< LCD PAL157: I0 Mask */
+#define LCD_PAL157_R14_0_Pos 16 /*!< LCD PAL157: R14_0 Position */
+#define LCD_PAL157_R14_0_Msk (0x1fUL << LCD_PAL157_R14_0_Pos) /*!< LCD PAL157: R14_0 Mask */
+#define LCD_PAL157_G14_0_Pos 21 /*!< LCD PAL157: G14_0 Position */
+#define LCD_PAL157_G14_0_Msk (0x1fUL << LCD_PAL157_G14_0_Pos) /*!< LCD PAL157: G14_0 Mask */
+#define LCD_PAL157_B14_0_Pos 26 /*!< LCD PAL157: B14_0 Position */
+#define LCD_PAL157_B14_0_Msk (0x1fUL << LCD_PAL157_B14_0_Pos) /*!< LCD PAL157: B14_0 Mask */
+#define LCD_PAL157_I1_Pos 31 /*!< LCD PAL157: I1 Position */
+#define LCD_PAL157_I1_Msk (0x01UL << LCD_PAL157_I1_Pos) /*!< LCD PAL157: I1 Mask */
+
+// --------------------------------------- LCD_PAL158 -------------------------------------------
+#define LCD_PAL158_R04_0_Pos 0 /*!< LCD PAL158: R04_0 Position */
+#define LCD_PAL158_R04_0_Msk (0x1fUL << LCD_PAL158_R04_0_Pos) /*!< LCD PAL158: R04_0 Mask */
+#define LCD_PAL158_G04_0_Pos 5 /*!< LCD PAL158: G04_0 Position */
+#define LCD_PAL158_G04_0_Msk (0x1fUL << LCD_PAL158_G04_0_Pos) /*!< LCD PAL158: G04_0 Mask */
+#define LCD_PAL158_B04_0_Pos 10 /*!< LCD PAL158: B04_0 Position */
+#define LCD_PAL158_B04_0_Msk (0x1fUL << LCD_PAL158_B04_0_Pos) /*!< LCD PAL158: B04_0 Mask */
+#define LCD_PAL158_I0_Pos 15 /*!< LCD PAL158: I0 Position */
+#define LCD_PAL158_I0_Msk (0x01UL << LCD_PAL158_I0_Pos) /*!< LCD PAL158: I0 Mask */
+#define LCD_PAL158_R14_0_Pos 16 /*!< LCD PAL158: R14_0 Position */
+#define LCD_PAL158_R14_0_Msk (0x1fUL << LCD_PAL158_R14_0_Pos) /*!< LCD PAL158: R14_0 Mask */
+#define LCD_PAL158_G14_0_Pos 21 /*!< LCD PAL158: G14_0 Position */
+#define LCD_PAL158_G14_0_Msk (0x1fUL << LCD_PAL158_G14_0_Pos) /*!< LCD PAL158: G14_0 Mask */
+#define LCD_PAL158_B14_0_Pos 26 /*!< LCD PAL158: B14_0 Position */
+#define LCD_PAL158_B14_0_Msk (0x1fUL << LCD_PAL158_B14_0_Pos) /*!< LCD PAL158: B14_0 Mask */
+#define LCD_PAL158_I1_Pos 31 /*!< LCD PAL158: I1 Position */
+#define LCD_PAL158_I1_Msk (0x01UL << LCD_PAL158_I1_Pos) /*!< LCD PAL158: I1 Mask */
+
+// --------------------------------------- LCD_PAL159 -------------------------------------------
+#define LCD_PAL159_R04_0_Pos 0 /*!< LCD PAL159: R04_0 Position */
+#define LCD_PAL159_R04_0_Msk (0x1fUL << LCD_PAL159_R04_0_Pos) /*!< LCD PAL159: R04_0 Mask */
+#define LCD_PAL159_G04_0_Pos 5 /*!< LCD PAL159: G04_0 Position */
+#define LCD_PAL159_G04_0_Msk (0x1fUL << LCD_PAL159_G04_0_Pos) /*!< LCD PAL159: G04_0 Mask */
+#define LCD_PAL159_B04_0_Pos 10 /*!< LCD PAL159: B04_0 Position */
+#define LCD_PAL159_B04_0_Msk (0x1fUL << LCD_PAL159_B04_0_Pos) /*!< LCD PAL159: B04_0 Mask */
+#define LCD_PAL159_I0_Pos 15 /*!< LCD PAL159: I0 Position */
+#define LCD_PAL159_I0_Msk (0x01UL << LCD_PAL159_I0_Pos) /*!< LCD PAL159: I0 Mask */
+#define LCD_PAL159_R14_0_Pos 16 /*!< LCD PAL159: R14_0 Position */
+#define LCD_PAL159_R14_0_Msk (0x1fUL << LCD_PAL159_R14_0_Pos) /*!< LCD PAL159: R14_0 Mask */
+#define LCD_PAL159_G14_0_Pos 21 /*!< LCD PAL159: G14_0 Position */
+#define LCD_PAL159_G14_0_Msk (0x1fUL << LCD_PAL159_G14_0_Pos) /*!< LCD PAL159: G14_0 Mask */
+#define LCD_PAL159_B14_0_Pos 26 /*!< LCD PAL159: B14_0 Position */
+#define LCD_PAL159_B14_0_Msk (0x1fUL << LCD_PAL159_B14_0_Pos) /*!< LCD PAL159: B14_0 Mask */
+#define LCD_PAL159_I1_Pos 31 /*!< LCD PAL159: I1 Position */
+#define LCD_PAL159_I1_Msk (0x01UL << LCD_PAL159_I1_Pos) /*!< LCD PAL159: I1 Mask */
+
+// --------------------------------------- LCD_PAL160 -------------------------------------------
+#define LCD_PAL160_R04_0_Pos 0 /*!< LCD PAL160: R04_0 Position */
+#define LCD_PAL160_R04_0_Msk (0x1fUL << LCD_PAL160_R04_0_Pos) /*!< LCD PAL160: R04_0 Mask */
+#define LCD_PAL160_G04_0_Pos 5 /*!< LCD PAL160: G04_0 Position */
+#define LCD_PAL160_G04_0_Msk (0x1fUL << LCD_PAL160_G04_0_Pos) /*!< LCD PAL160: G04_0 Mask */
+#define LCD_PAL160_B04_0_Pos 10 /*!< LCD PAL160: B04_0 Position */
+#define LCD_PAL160_B04_0_Msk (0x1fUL << LCD_PAL160_B04_0_Pos) /*!< LCD PAL160: B04_0 Mask */
+#define LCD_PAL160_I0_Pos 15 /*!< LCD PAL160: I0 Position */
+#define LCD_PAL160_I0_Msk (0x01UL << LCD_PAL160_I0_Pos) /*!< LCD PAL160: I0 Mask */
+#define LCD_PAL160_R14_0_Pos 16 /*!< LCD PAL160: R14_0 Position */
+#define LCD_PAL160_R14_0_Msk (0x1fUL << LCD_PAL160_R14_0_Pos) /*!< LCD PAL160: R14_0 Mask */
+#define LCD_PAL160_G14_0_Pos 21 /*!< LCD PAL160: G14_0 Position */
+#define LCD_PAL160_G14_0_Msk (0x1fUL << LCD_PAL160_G14_0_Pos) /*!< LCD PAL160: G14_0 Mask */
+#define LCD_PAL160_B14_0_Pos 26 /*!< LCD PAL160: B14_0 Position */
+#define LCD_PAL160_B14_0_Msk (0x1fUL << LCD_PAL160_B14_0_Pos) /*!< LCD PAL160: B14_0 Mask */
+#define LCD_PAL160_I1_Pos 31 /*!< LCD PAL160: I1 Position */
+#define LCD_PAL160_I1_Msk (0x01UL << LCD_PAL160_I1_Pos) /*!< LCD PAL160: I1 Mask */
+
+// --------------------------------------- LCD_PAL161 -------------------------------------------
+#define LCD_PAL161_R04_0_Pos 0 /*!< LCD PAL161: R04_0 Position */
+#define LCD_PAL161_R04_0_Msk (0x1fUL << LCD_PAL161_R04_0_Pos) /*!< LCD PAL161: R04_0 Mask */
+#define LCD_PAL161_G04_0_Pos 5 /*!< LCD PAL161: G04_0 Position */
+#define LCD_PAL161_G04_0_Msk (0x1fUL << LCD_PAL161_G04_0_Pos) /*!< LCD PAL161: G04_0 Mask */
+#define LCD_PAL161_B04_0_Pos 10 /*!< LCD PAL161: B04_0 Position */
+#define LCD_PAL161_B04_0_Msk (0x1fUL << LCD_PAL161_B04_0_Pos) /*!< LCD PAL161: B04_0 Mask */
+#define LCD_PAL161_I0_Pos 15 /*!< LCD PAL161: I0 Position */
+#define LCD_PAL161_I0_Msk (0x01UL << LCD_PAL161_I0_Pos) /*!< LCD PAL161: I0 Mask */
+#define LCD_PAL161_R14_0_Pos 16 /*!< LCD PAL161: R14_0 Position */
+#define LCD_PAL161_R14_0_Msk (0x1fUL << LCD_PAL161_R14_0_Pos) /*!< LCD PAL161: R14_0 Mask */
+#define LCD_PAL161_G14_0_Pos 21 /*!< LCD PAL161: G14_0 Position */
+#define LCD_PAL161_G14_0_Msk (0x1fUL << LCD_PAL161_G14_0_Pos) /*!< LCD PAL161: G14_0 Mask */
+#define LCD_PAL161_B14_0_Pos 26 /*!< LCD PAL161: B14_0 Position */
+#define LCD_PAL161_B14_0_Msk (0x1fUL << LCD_PAL161_B14_0_Pos) /*!< LCD PAL161: B14_0 Mask */
+#define LCD_PAL161_I1_Pos 31 /*!< LCD PAL161: I1 Position */
+#define LCD_PAL161_I1_Msk (0x01UL << LCD_PAL161_I1_Pos) /*!< LCD PAL161: I1 Mask */
+
+// --------------------------------------- LCD_PAL162 -------------------------------------------
+#define LCD_PAL162_R04_0_Pos 0 /*!< LCD PAL162: R04_0 Position */
+#define LCD_PAL162_R04_0_Msk (0x1fUL << LCD_PAL162_R04_0_Pos) /*!< LCD PAL162: R04_0 Mask */
+#define LCD_PAL162_G04_0_Pos 5 /*!< LCD PAL162: G04_0 Position */
+#define LCD_PAL162_G04_0_Msk (0x1fUL << LCD_PAL162_G04_0_Pos) /*!< LCD PAL162: G04_0 Mask */
+#define LCD_PAL162_B04_0_Pos 10 /*!< LCD PAL162: B04_0 Position */
+#define LCD_PAL162_B04_0_Msk (0x1fUL << LCD_PAL162_B04_0_Pos) /*!< LCD PAL162: B04_0 Mask */
+#define LCD_PAL162_I0_Pos 15 /*!< LCD PAL162: I0 Position */
+#define LCD_PAL162_I0_Msk (0x01UL << LCD_PAL162_I0_Pos) /*!< LCD PAL162: I0 Mask */
+#define LCD_PAL162_R14_0_Pos 16 /*!< LCD PAL162: R14_0 Position */
+#define LCD_PAL162_R14_0_Msk (0x1fUL << LCD_PAL162_R14_0_Pos) /*!< LCD PAL162: R14_0 Mask */
+#define LCD_PAL162_G14_0_Pos 21 /*!< LCD PAL162: G14_0 Position */
+#define LCD_PAL162_G14_0_Msk (0x1fUL << LCD_PAL162_G14_0_Pos) /*!< LCD PAL162: G14_0 Mask */
+#define LCD_PAL162_B14_0_Pos 26 /*!< LCD PAL162: B14_0 Position */
+#define LCD_PAL162_B14_0_Msk (0x1fUL << LCD_PAL162_B14_0_Pos) /*!< LCD PAL162: B14_0 Mask */
+#define LCD_PAL162_I1_Pos 31 /*!< LCD PAL162: I1 Position */
+#define LCD_PAL162_I1_Msk (0x01UL << LCD_PAL162_I1_Pos) /*!< LCD PAL162: I1 Mask */
+
+// --------------------------------------- LCD_PAL163 -------------------------------------------
+#define LCD_PAL163_R04_0_Pos 0 /*!< LCD PAL163: R04_0 Position */
+#define LCD_PAL163_R04_0_Msk (0x1fUL << LCD_PAL163_R04_0_Pos) /*!< LCD PAL163: R04_0 Mask */
+#define LCD_PAL163_G04_0_Pos 5 /*!< LCD PAL163: G04_0 Position */
+#define LCD_PAL163_G04_0_Msk (0x1fUL << LCD_PAL163_G04_0_Pos) /*!< LCD PAL163: G04_0 Mask */
+#define LCD_PAL163_B04_0_Pos 10 /*!< LCD PAL163: B04_0 Position */
+#define LCD_PAL163_B04_0_Msk (0x1fUL << LCD_PAL163_B04_0_Pos) /*!< LCD PAL163: B04_0 Mask */
+#define LCD_PAL163_I0_Pos 15 /*!< LCD PAL163: I0 Position */
+#define LCD_PAL163_I0_Msk (0x01UL << LCD_PAL163_I0_Pos) /*!< LCD PAL163: I0 Mask */
+#define LCD_PAL163_R14_0_Pos 16 /*!< LCD PAL163: R14_0 Position */
+#define LCD_PAL163_R14_0_Msk (0x1fUL << LCD_PAL163_R14_0_Pos) /*!< LCD PAL163: R14_0 Mask */
+#define LCD_PAL163_G14_0_Pos 21 /*!< LCD PAL163: G14_0 Position */
+#define LCD_PAL163_G14_0_Msk (0x1fUL << LCD_PAL163_G14_0_Pos) /*!< LCD PAL163: G14_0 Mask */
+#define LCD_PAL163_B14_0_Pos 26 /*!< LCD PAL163: B14_0 Position */
+#define LCD_PAL163_B14_0_Msk (0x1fUL << LCD_PAL163_B14_0_Pos) /*!< LCD PAL163: B14_0 Mask */
+#define LCD_PAL163_I1_Pos 31 /*!< LCD PAL163: I1 Position */
+#define LCD_PAL163_I1_Msk (0x01UL << LCD_PAL163_I1_Pos) /*!< LCD PAL163: I1 Mask */
+
+// --------------------------------------- LCD_PAL164 -------------------------------------------
+#define LCD_PAL164_R04_0_Pos 0 /*!< LCD PAL164: R04_0 Position */
+#define LCD_PAL164_R04_0_Msk (0x1fUL << LCD_PAL164_R04_0_Pos) /*!< LCD PAL164: R04_0 Mask */
+#define LCD_PAL164_G04_0_Pos 5 /*!< LCD PAL164: G04_0 Position */
+#define LCD_PAL164_G04_0_Msk (0x1fUL << LCD_PAL164_G04_0_Pos) /*!< LCD PAL164: G04_0 Mask */
+#define LCD_PAL164_B04_0_Pos 10 /*!< LCD PAL164: B04_0 Position */
+#define LCD_PAL164_B04_0_Msk (0x1fUL << LCD_PAL164_B04_0_Pos) /*!< LCD PAL164: B04_0 Mask */
+#define LCD_PAL164_I0_Pos 15 /*!< LCD PAL164: I0 Position */
+#define LCD_PAL164_I0_Msk (0x01UL << LCD_PAL164_I0_Pos) /*!< LCD PAL164: I0 Mask */
+#define LCD_PAL164_R14_0_Pos 16 /*!< LCD PAL164: R14_0 Position */
+#define LCD_PAL164_R14_0_Msk (0x1fUL << LCD_PAL164_R14_0_Pos) /*!< LCD PAL164: R14_0 Mask */
+#define LCD_PAL164_G14_0_Pos 21 /*!< LCD PAL164: G14_0 Position */
+#define LCD_PAL164_G14_0_Msk (0x1fUL << LCD_PAL164_G14_0_Pos) /*!< LCD PAL164: G14_0 Mask */
+#define LCD_PAL164_B14_0_Pos 26 /*!< LCD PAL164: B14_0 Position */
+#define LCD_PAL164_B14_0_Msk (0x1fUL << LCD_PAL164_B14_0_Pos) /*!< LCD PAL164: B14_0 Mask */
+#define LCD_PAL164_I1_Pos 31 /*!< LCD PAL164: I1 Position */
+#define LCD_PAL164_I1_Msk (0x01UL << LCD_PAL164_I1_Pos) /*!< LCD PAL164: I1 Mask */
+
+// --------------------------------------- LCD_PAL165 -------------------------------------------
+#define LCD_PAL165_R04_0_Pos 0 /*!< LCD PAL165: R04_0 Position */
+#define LCD_PAL165_R04_0_Msk (0x1fUL << LCD_PAL165_R04_0_Pos) /*!< LCD PAL165: R04_0 Mask */
+#define LCD_PAL165_G04_0_Pos 5 /*!< LCD PAL165: G04_0 Position */
+#define LCD_PAL165_G04_0_Msk (0x1fUL << LCD_PAL165_G04_0_Pos) /*!< LCD PAL165: G04_0 Mask */
+#define LCD_PAL165_B04_0_Pos 10 /*!< LCD PAL165: B04_0 Position */
+#define LCD_PAL165_B04_0_Msk (0x1fUL << LCD_PAL165_B04_0_Pos) /*!< LCD PAL165: B04_0 Mask */
+#define LCD_PAL165_I0_Pos 15 /*!< LCD PAL165: I0 Position */
+#define LCD_PAL165_I0_Msk (0x01UL << LCD_PAL165_I0_Pos) /*!< LCD PAL165: I0 Mask */
+#define LCD_PAL165_R14_0_Pos 16 /*!< LCD PAL165: R14_0 Position */
+#define LCD_PAL165_R14_0_Msk (0x1fUL << LCD_PAL165_R14_0_Pos) /*!< LCD PAL165: R14_0 Mask */
+#define LCD_PAL165_G14_0_Pos 21 /*!< LCD PAL165: G14_0 Position */
+#define LCD_PAL165_G14_0_Msk (0x1fUL << LCD_PAL165_G14_0_Pos) /*!< LCD PAL165: G14_0 Mask */
+#define LCD_PAL165_B14_0_Pos 26 /*!< LCD PAL165: B14_0 Position */
+#define LCD_PAL165_B14_0_Msk (0x1fUL << LCD_PAL165_B14_0_Pos) /*!< LCD PAL165: B14_0 Mask */
+#define LCD_PAL165_I1_Pos 31 /*!< LCD PAL165: I1 Position */
+#define LCD_PAL165_I1_Msk (0x01UL << LCD_PAL165_I1_Pos) /*!< LCD PAL165: I1 Mask */
+
+// --------------------------------------- LCD_PAL166 -------------------------------------------
+#define LCD_PAL166_R04_0_Pos 0 /*!< LCD PAL166: R04_0 Position */
+#define LCD_PAL166_R04_0_Msk (0x1fUL << LCD_PAL166_R04_0_Pos) /*!< LCD PAL166: R04_0 Mask */
+#define LCD_PAL166_G04_0_Pos 5 /*!< LCD PAL166: G04_0 Position */
+#define LCD_PAL166_G04_0_Msk (0x1fUL << LCD_PAL166_G04_0_Pos) /*!< LCD PAL166: G04_0 Mask */
+#define LCD_PAL166_B04_0_Pos 10 /*!< LCD PAL166: B04_0 Position */
+#define LCD_PAL166_B04_0_Msk (0x1fUL << LCD_PAL166_B04_0_Pos) /*!< LCD PAL166: B04_0 Mask */
+#define LCD_PAL166_I0_Pos 15 /*!< LCD PAL166: I0 Position */
+#define LCD_PAL166_I0_Msk (0x01UL << LCD_PAL166_I0_Pos) /*!< LCD PAL166: I0 Mask */
+#define LCD_PAL166_R14_0_Pos 16 /*!< LCD PAL166: R14_0 Position */
+#define LCD_PAL166_R14_0_Msk (0x1fUL << LCD_PAL166_R14_0_Pos) /*!< LCD PAL166: R14_0 Mask */
+#define LCD_PAL166_G14_0_Pos 21 /*!< LCD PAL166: G14_0 Position */
+#define LCD_PAL166_G14_0_Msk (0x1fUL << LCD_PAL166_G14_0_Pos) /*!< LCD PAL166: G14_0 Mask */
+#define LCD_PAL166_B14_0_Pos 26 /*!< LCD PAL166: B14_0 Position */
+#define LCD_PAL166_B14_0_Msk (0x1fUL << LCD_PAL166_B14_0_Pos) /*!< LCD PAL166: B14_0 Mask */
+#define LCD_PAL166_I1_Pos 31 /*!< LCD PAL166: I1 Position */
+#define LCD_PAL166_I1_Msk (0x01UL << LCD_PAL166_I1_Pos) /*!< LCD PAL166: I1 Mask */
+
+// --------------------------------------- LCD_PAL167 -------------------------------------------
+#define LCD_PAL167_R04_0_Pos 0 /*!< LCD PAL167: R04_0 Position */
+#define LCD_PAL167_R04_0_Msk (0x1fUL << LCD_PAL167_R04_0_Pos) /*!< LCD PAL167: R04_0 Mask */
+#define LCD_PAL167_G04_0_Pos 5 /*!< LCD PAL167: G04_0 Position */
+#define LCD_PAL167_G04_0_Msk (0x1fUL << LCD_PAL167_G04_0_Pos) /*!< LCD PAL167: G04_0 Mask */
+#define LCD_PAL167_B04_0_Pos 10 /*!< LCD PAL167: B04_0 Position */
+#define LCD_PAL167_B04_0_Msk (0x1fUL << LCD_PAL167_B04_0_Pos) /*!< LCD PAL167: B04_0 Mask */
+#define LCD_PAL167_I0_Pos 15 /*!< LCD PAL167: I0 Position */
+#define LCD_PAL167_I0_Msk (0x01UL << LCD_PAL167_I0_Pos) /*!< LCD PAL167: I0 Mask */
+#define LCD_PAL167_R14_0_Pos 16 /*!< LCD PAL167: R14_0 Position */
+#define LCD_PAL167_R14_0_Msk (0x1fUL << LCD_PAL167_R14_0_Pos) /*!< LCD PAL167: R14_0 Mask */
+#define LCD_PAL167_G14_0_Pos 21 /*!< LCD PAL167: G14_0 Position */
+#define LCD_PAL167_G14_0_Msk (0x1fUL << LCD_PAL167_G14_0_Pos) /*!< LCD PAL167: G14_0 Mask */
+#define LCD_PAL167_B14_0_Pos 26 /*!< LCD PAL167: B14_0 Position */
+#define LCD_PAL167_B14_0_Msk (0x1fUL << LCD_PAL167_B14_0_Pos) /*!< LCD PAL167: B14_0 Mask */
+#define LCD_PAL167_I1_Pos 31 /*!< LCD PAL167: I1 Position */
+#define LCD_PAL167_I1_Msk (0x01UL << LCD_PAL167_I1_Pos) /*!< LCD PAL167: I1 Mask */
+
+// --------------------------------------- LCD_PAL168 -------------------------------------------
+#define LCD_PAL168_R04_0_Pos 0 /*!< LCD PAL168: R04_0 Position */
+#define LCD_PAL168_R04_0_Msk (0x1fUL << LCD_PAL168_R04_0_Pos) /*!< LCD PAL168: R04_0 Mask */
+#define LCD_PAL168_G04_0_Pos 5 /*!< LCD PAL168: G04_0 Position */
+#define LCD_PAL168_G04_0_Msk (0x1fUL << LCD_PAL168_G04_0_Pos) /*!< LCD PAL168: G04_0 Mask */
+#define LCD_PAL168_B04_0_Pos 10 /*!< LCD PAL168: B04_0 Position */
+#define LCD_PAL168_B04_0_Msk (0x1fUL << LCD_PAL168_B04_0_Pos) /*!< LCD PAL168: B04_0 Mask */
+#define LCD_PAL168_I0_Pos 15 /*!< LCD PAL168: I0 Position */
+#define LCD_PAL168_I0_Msk (0x01UL << LCD_PAL168_I0_Pos) /*!< LCD PAL168: I0 Mask */
+#define LCD_PAL168_R14_0_Pos 16 /*!< LCD PAL168: R14_0 Position */
+#define LCD_PAL168_R14_0_Msk (0x1fUL << LCD_PAL168_R14_0_Pos) /*!< LCD PAL168: R14_0 Mask */
+#define LCD_PAL168_G14_0_Pos 21 /*!< LCD PAL168: G14_0 Position */
+#define LCD_PAL168_G14_0_Msk (0x1fUL << LCD_PAL168_G14_0_Pos) /*!< LCD PAL168: G14_0 Mask */
+#define LCD_PAL168_B14_0_Pos 26 /*!< LCD PAL168: B14_0 Position */
+#define LCD_PAL168_B14_0_Msk (0x1fUL << LCD_PAL168_B14_0_Pos) /*!< LCD PAL168: B14_0 Mask */
+#define LCD_PAL168_I1_Pos 31 /*!< LCD PAL168: I1 Position */
+#define LCD_PAL168_I1_Msk (0x01UL << LCD_PAL168_I1_Pos) /*!< LCD PAL168: I1 Mask */
+
+// --------------------------------------- LCD_PAL169 -------------------------------------------
+#define LCD_PAL169_R04_0_Pos 0 /*!< LCD PAL169: R04_0 Position */
+#define LCD_PAL169_R04_0_Msk (0x1fUL << LCD_PAL169_R04_0_Pos) /*!< LCD PAL169: R04_0 Mask */
+#define LCD_PAL169_G04_0_Pos 5 /*!< LCD PAL169: G04_0 Position */
+#define LCD_PAL169_G04_0_Msk (0x1fUL << LCD_PAL169_G04_0_Pos) /*!< LCD PAL169: G04_0 Mask */
+#define LCD_PAL169_B04_0_Pos 10 /*!< LCD PAL169: B04_0 Position */
+#define LCD_PAL169_B04_0_Msk (0x1fUL << LCD_PAL169_B04_0_Pos) /*!< LCD PAL169: B04_0 Mask */
+#define LCD_PAL169_I0_Pos 15 /*!< LCD PAL169: I0 Position */
+#define LCD_PAL169_I0_Msk (0x01UL << LCD_PAL169_I0_Pos) /*!< LCD PAL169: I0 Mask */
+#define LCD_PAL169_R14_0_Pos 16 /*!< LCD PAL169: R14_0 Position */
+#define LCD_PAL169_R14_0_Msk (0x1fUL << LCD_PAL169_R14_0_Pos) /*!< LCD PAL169: R14_0 Mask */
+#define LCD_PAL169_G14_0_Pos 21 /*!< LCD PAL169: G14_0 Position */
+#define LCD_PAL169_G14_0_Msk (0x1fUL << LCD_PAL169_G14_0_Pos) /*!< LCD PAL169: G14_0 Mask */
+#define LCD_PAL169_B14_0_Pos 26 /*!< LCD PAL169: B14_0 Position */
+#define LCD_PAL169_B14_0_Msk (0x1fUL << LCD_PAL169_B14_0_Pos) /*!< LCD PAL169: B14_0 Mask */
+#define LCD_PAL169_I1_Pos 31 /*!< LCD PAL169: I1 Position */
+#define LCD_PAL169_I1_Msk (0x01UL << LCD_PAL169_I1_Pos) /*!< LCD PAL169: I1 Mask */
+
+// --------------------------------------- LCD_PAL170 -------------------------------------------
+#define LCD_PAL170_R04_0_Pos 0 /*!< LCD PAL170: R04_0 Position */
+#define LCD_PAL170_R04_0_Msk (0x1fUL << LCD_PAL170_R04_0_Pos) /*!< LCD PAL170: R04_0 Mask */
+#define LCD_PAL170_G04_0_Pos 5 /*!< LCD PAL170: G04_0 Position */
+#define LCD_PAL170_G04_0_Msk (0x1fUL << LCD_PAL170_G04_0_Pos) /*!< LCD PAL170: G04_0 Mask */
+#define LCD_PAL170_B04_0_Pos 10 /*!< LCD PAL170: B04_0 Position */
+#define LCD_PAL170_B04_0_Msk (0x1fUL << LCD_PAL170_B04_0_Pos) /*!< LCD PAL170: B04_0 Mask */
+#define LCD_PAL170_I0_Pos 15 /*!< LCD PAL170: I0 Position */
+#define LCD_PAL170_I0_Msk (0x01UL << LCD_PAL170_I0_Pos) /*!< LCD PAL170: I0 Mask */
+#define LCD_PAL170_R14_0_Pos 16 /*!< LCD PAL170: R14_0 Position */
+#define LCD_PAL170_R14_0_Msk (0x1fUL << LCD_PAL170_R14_0_Pos) /*!< LCD PAL170: R14_0 Mask */
+#define LCD_PAL170_G14_0_Pos 21 /*!< LCD PAL170: G14_0 Position */
+#define LCD_PAL170_G14_0_Msk (0x1fUL << LCD_PAL170_G14_0_Pos) /*!< LCD PAL170: G14_0 Mask */
+#define LCD_PAL170_B14_0_Pos 26 /*!< LCD PAL170: B14_0 Position */
+#define LCD_PAL170_B14_0_Msk (0x1fUL << LCD_PAL170_B14_0_Pos) /*!< LCD PAL170: B14_0 Mask */
+#define LCD_PAL170_I1_Pos 31 /*!< LCD PAL170: I1 Position */
+#define LCD_PAL170_I1_Msk (0x01UL << LCD_PAL170_I1_Pos) /*!< LCD PAL170: I1 Mask */
+
+// --------------------------------------- LCD_PAL171 -------------------------------------------
+#define LCD_PAL171_R04_0_Pos 0 /*!< LCD PAL171: R04_0 Position */
+#define LCD_PAL171_R04_0_Msk (0x1fUL << LCD_PAL171_R04_0_Pos) /*!< LCD PAL171: R04_0 Mask */
+#define LCD_PAL171_G04_0_Pos 5 /*!< LCD PAL171: G04_0 Position */
+#define LCD_PAL171_G04_0_Msk (0x1fUL << LCD_PAL171_G04_0_Pos) /*!< LCD PAL171: G04_0 Mask */
+#define LCD_PAL171_B04_0_Pos 10 /*!< LCD PAL171: B04_0 Position */
+#define LCD_PAL171_B04_0_Msk (0x1fUL << LCD_PAL171_B04_0_Pos) /*!< LCD PAL171: B04_0 Mask */
+#define LCD_PAL171_I0_Pos 15 /*!< LCD PAL171: I0 Position */
+#define LCD_PAL171_I0_Msk (0x01UL << LCD_PAL171_I0_Pos) /*!< LCD PAL171: I0 Mask */
+#define LCD_PAL171_R14_0_Pos 16 /*!< LCD PAL171: R14_0 Position */
+#define LCD_PAL171_R14_0_Msk (0x1fUL << LCD_PAL171_R14_0_Pos) /*!< LCD PAL171: R14_0 Mask */
+#define LCD_PAL171_G14_0_Pos 21 /*!< LCD PAL171: G14_0 Position */
+#define LCD_PAL171_G14_0_Msk (0x1fUL << LCD_PAL171_G14_0_Pos) /*!< LCD PAL171: G14_0 Mask */
+#define LCD_PAL171_B14_0_Pos 26 /*!< LCD PAL171: B14_0 Position */
+#define LCD_PAL171_B14_0_Msk (0x1fUL << LCD_PAL171_B14_0_Pos) /*!< LCD PAL171: B14_0 Mask */
+#define LCD_PAL171_I1_Pos 31 /*!< LCD PAL171: I1 Position */
+#define LCD_PAL171_I1_Msk (0x01UL << LCD_PAL171_I1_Pos) /*!< LCD PAL171: I1 Mask */
+
+// --------------------------------------- LCD_PAL172 -------------------------------------------
+#define LCD_PAL172_R04_0_Pos 0 /*!< LCD PAL172: R04_0 Position */
+#define LCD_PAL172_R04_0_Msk (0x1fUL << LCD_PAL172_R04_0_Pos) /*!< LCD PAL172: R04_0 Mask */
+#define LCD_PAL172_G04_0_Pos 5 /*!< LCD PAL172: G04_0 Position */
+#define LCD_PAL172_G04_0_Msk (0x1fUL << LCD_PAL172_G04_0_Pos) /*!< LCD PAL172: G04_0 Mask */
+#define LCD_PAL172_B04_0_Pos 10 /*!< LCD PAL172: B04_0 Position */
+#define LCD_PAL172_B04_0_Msk (0x1fUL << LCD_PAL172_B04_0_Pos) /*!< LCD PAL172: B04_0 Mask */
+#define LCD_PAL172_I0_Pos 15 /*!< LCD PAL172: I0 Position */
+#define LCD_PAL172_I0_Msk (0x01UL << LCD_PAL172_I0_Pos) /*!< LCD PAL172: I0 Mask */
+#define LCD_PAL172_R14_0_Pos 16 /*!< LCD PAL172: R14_0 Position */
+#define LCD_PAL172_R14_0_Msk (0x1fUL << LCD_PAL172_R14_0_Pos) /*!< LCD PAL172: R14_0 Mask */
+#define LCD_PAL172_G14_0_Pos 21 /*!< LCD PAL172: G14_0 Position */
+#define LCD_PAL172_G14_0_Msk (0x1fUL << LCD_PAL172_G14_0_Pos) /*!< LCD PAL172: G14_0 Mask */
+#define LCD_PAL172_B14_0_Pos 26 /*!< LCD PAL172: B14_0 Position */
+#define LCD_PAL172_B14_0_Msk (0x1fUL << LCD_PAL172_B14_0_Pos) /*!< LCD PAL172: B14_0 Mask */
+#define LCD_PAL172_I1_Pos 31 /*!< LCD PAL172: I1 Position */
+#define LCD_PAL172_I1_Msk (0x01UL << LCD_PAL172_I1_Pos) /*!< LCD PAL172: I1 Mask */
+
+// --------------------------------------- LCD_PAL173 -------------------------------------------
+#define LCD_PAL173_R04_0_Pos 0 /*!< LCD PAL173: R04_0 Position */
+#define LCD_PAL173_R04_0_Msk (0x1fUL << LCD_PAL173_R04_0_Pos) /*!< LCD PAL173: R04_0 Mask */
+#define LCD_PAL173_G04_0_Pos 5 /*!< LCD PAL173: G04_0 Position */
+#define LCD_PAL173_G04_0_Msk (0x1fUL << LCD_PAL173_G04_0_Pos) /*!< LCD PAL173: G04_0 Mask */
+#define LCD_PAL173_B04_0_Pos 10 /*!< LCD PAL173: B04_0 Position */
+#define LCD_PAL173_B04_0_Msk (0x1fUL << LCD_PAL173_B04_0_Pos) /*!< LCD PAL173: B04_0 Mask */
+#define LCD_PAL173_I0_Pos 15 /*!< LCD PAL173: I0 Position */
+#define LCD_PAL173_I0_Msk (0x01UL << LCD_PAL173_I0_Pos) /*!< LCD PAL173: I0 Mask */
+#define LCD_PAL173_R14_0_Pos 16 /*!< LCD PAL173: R14_0 Position */
+#define LCD_PAL173_R14_0_Msk (0x1fUL << LCD_PAL173_R14_0_Pos) /*!< LCD PAL173: R14_0 Mask */
+#define LCD_PAL173_G14_0_Pos 21 /*!< LCD PAL173: G14_0 Position */
+#define LCD_PAL173_G14_0_Msk (0x1fUL << LCD_PAL173_G14_0_Pos) /*!< LCD PAL173: G14_0 Mask */
+#define LCD_PAL173_B14_0_Pos 26 /*!< LCD PAL173: B14_0 Position */
+#define LCD_PAL173_B14_0_Msk (0x1fUL << LCD_PAL173_B14_0_Pos) /*!< LCD PAL173: B14_0 Mask */
+#define LCD_PAL173_I1_Pos 31 /*!< LCD PAL173: I1 Position */
+#define LCD_PAL173_I1_Msk (0x01UL << LCD_PAL173_I1_Pos) /*!< LCD PAL173: I1 Mask */
+
+// --------------------------------------- LCD_PAL174 -------------------------------------------
+#define LCD_PAL174_R04_0_Pos 0 /*!< LCD PAL174: R04_0 Position */
+#define LCD_PAL174_R04_0_Msk (0x1fUL << LCD_PAL174_R04_0_Pos) /*!< LCD PAL174: R04_0 Mask */
+#define LCD_PAL174_G04_0_Pos 5 /*!< LCD PAL174: G04_0 Position */
+#define LCD_PAL174_G04_0_Msk (0x1fUL << LCD_PAL174_G04_0_Pos) /*!< LCD PAL174: G04_0 Mask */
+#define LCD_PAL174_B04_0_Pos 10 /*!< LCD PAL174: B04_0 Position */
+#define LCD_PAL174_B04_0_Msk (0x1fUL << LCD_PAL174_B04_0_Pos) /*!< LCD PAL174: B04_0 Mask */
+#define LCD_PAL174_I0_Pos 15 /*!< LCD PAL174: I0 Position */
+#define LCD_PAL174_I0_Msk (0x01UL << LCD_PAL174_I0_Pos) /*!< LCD PAL174: I0 Mask */
+#define LCD_PAL174_R14_0_Pos 16 /*!< LCD PAL174: R14_0 Position */
+#define LCD_PAL174_R14_0_Msk (0x1fUL << LCD_PAL174_R14_0_Pos) /*!< LCD PAL174: R14_0 Mask */
+#define LCD_PAL174_G14_0_Pos 21 /*!< LCD PAL174: G14_0 Position */
+#define LCD_PAL174_G14_0_Msk (0x1fUL << LCD_PAL174_G14_0_Pos) /*!< LCD PAL174: G14_0 Mask */
+#define LCD_PAL174_B14_0_Pos 26 /*!< LCD PAL174: B14_0 Position */
+#define LCD_PAL174_B14_0_Msk (0x1fUL << LCD_PAL174_B14_0_Pos) /*!< LCD PAL174: B14_0 Mask */
+#define LCD_PAL174_I1_Pos 31 /*!< LCD PAL174: I1 Position */
+#define LCD_PAL174_I1_Msk (0x01UL << LCD_PAL174_I1_Pos) /*!< LCD PAL174: I1 Mask */
+
+// --------------------------------------- LCD_PAL175 -------------------------------------------
+#define LCD_PAL175_R04_0_Pos 0 /*!< LCD PAL175: R04_0 Position */
+#define LCD_PAL175_R04_0_Msk (0x1fUL << LCD_PAL175_R04_0_Pos) /*!< LCD PAL175: R04_0 Mask */
+#define LCD_PAL175_G04_0_Pos 5 /*!< LCD PAL175: G04_0 Position */
+#define LCD_PAL175_G04_0_Msk (0x1fUL << LCD_PAL175_G04_0_Pos) /*!< LCD PAL175: G04_0 Mask */
+#define LCD_PAL175_B04_0_Pos 10 /*!< LCD PAL175: B04_0 Position */
+#define LCD_PAL175_B04_0_Msk (0x1fUL << LCD_PAL175_B04_0_Pos) /*!< LCD PAL175: B04_0 Mask */
+#define LCD_PAL175_I0_Pos 15 /*!< LCD PAL175: I0 Position */
+#define LCD_PAL175_I0_Msk (0x01UL << LCD_PAL175_I0_Pos) /*!< LCD PAL175: I0 Mask */
+#define LCD_PAL175_R14_0_Pos 16 /*!< LCD PAL175: R14_0 Position */
+#define LCD_PAL175_R14_0_Msk (0x1fUL << LCD_PAL175_R14_0_Pos) /*!< LCD PAL175: R14_0 Mask */
+#define LCD_PAL175_G14_0_Pos 21 /*!< LCD PAL175: G14_0 Position */
+#define LCD_PAL175_G14_0_Msk (0x1fUL << LCD_PAL175_G14_0_Pos) /*!< LCD PAL175: G14_0 Mask */
+#define LCD_PAL175_B14_0_Pos 26 /*!< LCD PAL175: B14_0 Position */
+#define LCD_PAL175_B14_0_Msk (0x1fUL << LCD_PAL175_B14_0_Pos) /*!< LCD PAL175: B14_0 Mask */
+#define LCD_PAL175_I1_Pos 31 /*!< LCD PAL175: I1 Position */
+#define LCD_PAL175_I1_Msk (0x01UL << LCD_PAL175_I1_Pos) /*!< LCD PAL175: I1 Mask */
+
+// --------------------------------------- LCD_PAL176 -------------------------------------------
+#define LCD_PAL176_R04_0_Pos 0 /*!< LCD PAL176: R04_0 Position */
+#define LCD_PAL176_R04_0_Msk (0x1fUL << LCD_PAL176_R04_0_Pos) /*!< LCD PAL176: R04_0 Mask */
+#define LCD_PAL176_G04_0_Pos 5 /*!< LCD PAL176: G04_0 Position */
+#define LCD_PAL176_G04_0_Msk (0x1fUL << LCD_PAL176_G04_0_Pos) /*!< LCD PAL176: G04_0 Mask */
+#define LCD_PAL176_B04_0_Pos 10 /*!< LCD PAL176: B04_0 Position */
+#define LCD_PAL176_B04_0_Msk (0x1fUL << LCD_PAL176_B04_0_Pos) /*!< LCD PAL176: B04_0 Mask */
+#define LCD_PAL176_I0_Pos 15 /*!< LCD PAL176: I0 Position */
+#define LCD_PAL176_I0_Msk (0x01UL << LCD_PAL176_I0_Pos) /*!< LCD PAL176: I0 Mask */
+#define LCD_PAL176_R14_0_Pos 16 /*!< LCD PAL176: R14_0 Position */
+#define LCD_PAL176_R14_0_Msk (0x1fUL << LCD_PAL176_R14_0_Pos) /*!< LCD PAL176: R14_0 Mask */
+#define LCD_PAL176_G14_0_Pos 21 /*!< LCD PAL176: G14_0 Position */
+#define LCD_PAL176_G14_0_Msk (0x1fUL << LCD_PAL176_G14_0_Pos) /*!< LCD PAL176: G14_0 Mask */
+#define LCD_PAL176_B14_0_Pos 26 /*!< LCD PAL176: B14_0 Position */
+#define LCD_PAL176_B14_0_Msk (0x1fUL << LCD_PAL176_B14_0_Pos) /*!< LCD PAL176: B14_0 Mask */
+#define LCD_PAL176_I1_Pos 31 /*!< LCD PAL176: I1 Position */
+#define LCD_PAL176_I1_Msk (0x01UL << LCD_PAL176_I1_Pos) /*!< LCD PAL176: I1 Mask */
+
+// --------------------------------------- LCD_PAL177 -------------------------------------------
+#define LCD_PAL177_R04_0_Pos 0 /*!< LCD PAL177: R04_0 Position */
+#define LCD_PAL177_R04_0_Msk (0x1fUL << LCD_PAL177_R04_0_Pos) /*!< LCD PAL177: R04_0 Mask */
+#define LCD_PAL177_G04_0_Pos 5 /*!< LCD PAL177: G04_0 Position */
+#define LCD_PAL177_G04_0_Msk (0x1fUL << LCD_PAL177_G04_0_Pos) /*!< LCD PAL177: G04_0 Mask */
+#define LCD_PAL177_B04_0_Pos 10 /*!< LCD PAL177: B04_0 Position */
+#define LCD_PAL177_B04_0_Msk (0x1fUL << LCD_PAL177_B04_0_Pos) /*!< LCD PAL177: B04_0 Mask */
+#define LCD_PAL177_I0_Pos 15 /*!< LCD PAL177: I0 Position */
+#define LCD_PAL177_I0_Msk (0x01UL << LCD_PAL177_I0_Pos) /*!< LCD PAL177: I0 Mask */
+#define LCD_PAL177_R14_0_Pos 16 /*!< LCD PAL177: R14_0 Position */
+#define LCD_PAL177_R14_0_Msk (0x1fUL << LCD_PAL177_R14_0_Pos) /*!< LCD PAL177: R14_0 Mask */
+#define LCD_PAL177_G14_0_Pos 21 /*!< LCD PAL177: G14_0 Position */
+#define LCD_PAL177_G14_0_Msk (0x1fUL << LCD_PAL177_G14_0_Pos) /*!< LCD PAL177: G14_0 Mask */
+#define LCD_PAL177_B14_0_Pos 26 /*!< LCD PAL177: B14_0 Position */
+#define LCD_PAL177_B14_0_Msk (0x1fUL << LCD_PAL177_B14_0_Pos) /*!< LCD PAL177: B14_0 Mask */
+#define LCD_PAL177_I1_Pos 31 /*!< LCD PAL177: I1 Position */
+#define LCD_PAL177_I1_Msk (0x01UL << LCD_PAL177_I1_Pos) /*!< LCD PAL177: I1 Mask */
+
+// --------------------------------------- LCD_PAL178 -------------------------------------------
+#define LCD_PAL178_R04_0_Pos 0 /*!< LCD PAL178: R04_0 Position */
+#define LCD_PAL178_R04_0_Msk (0x1fUL << LCD_PAL178_R04_0_Pos) /*!< LCD PAL178: R04_0 Mask */
+#define LCD_PAL178_G04_0_Pos 5 /*!< LCD PAL178: G04_0 Position */
+#define LCD_PAL178_G04_0_Msk (0x1fUL << LCD_PAL178_G04_0_Pos) /*!< LCD PAL178: G04_0 Mask */
+#define LCD_PAL178_B04_0_Pos 10 /*!< LCD PAL178: B04_0 Position */
+#define LCD_PAL178_B04_0_Msk (0x1fUL << LCD_PAL178_B04_0_Pos) /*!< LCD PAL178: B04_0 Mask */
+#define LCD_PAL178_I0_Pos 15 /*!< LCD PAL178: I0 Position */
+#define LCD_PAL178_I0_Msk (0x01UL << LCD_PAL178_I0_Pos) /*!< LCD PAL178: I0 Mask */
+#define LCD_PAL178_R14_0_Pos 16 /*!< LCD PAL178: R14_0 Position */
+#define LCD_PAL178_R14_0_Msk (0x1fUL << LCD_PAL178_R14_0_Pos) /*!< LCD PAL178: R14_0 Mask */
+#define LCD_PAL178_G14_0_Pos 21 /*!< LCD PAL178: G14_0 Position */
+#define LCD_PAL178_G14_0_Msk (0x1fUL << LCD_PAL178_G14_0_Pos) /*!< LCD PAL178: G14_0 Mask */
+#define LCD_PAL178_B14_0_Pos 26 /*!< LCD PAL178: B14_0 Position */
+#define LCD_PAL178_B14_0_Msk (0x1fUL << LCD_PAL178_B14_0_Pos) /*!< LCD PAL178: B14_0 Mask */
+#define LCD_PAL178_I1_Pos 31 /*!< LCD PAL178: I1 Position */
+#define LCD_PAL178_I1_Msk (0x01UL << LCD_PAL178_I1_Pos) /*!< LCD PAL178: I1 Mask */
+
+// --------------------------------------- LCD_PAL179 -------------------------------------------
+#define LCD_PAL179_R04_0_Pos 0 /*!< LCD PAL179: R04_0 Position */
+#define LCD_PAL179_R04_0_Msk (0x1fUL << LCD_PAL179_R04_0_Pos) /*!< LCD PAL179: R04_0 Mask */
+#define LCD_PAL179_G04_0_Pos 5 /*!< LCD PAL179: G04_0 Position */
+#define LCD_PAL179_G04_0_Msk (0x1fUL << LCD_PAL179_G04_0_Pos) /*!< LCD PAL179: G04_0 Mask */
+#define LCD_PAL179_B04_0_Pos 10 /*!< LCD PAL179: B04_0 Position */
+#define LCD_PAL179_B04_0_Msk (0x1fUL << LCD_PAL179_B04_0_Pos) /*!< LCD PAL179: B04_0 Mask */
+#define LCD_PAL179_I0_Pos 15 /*!< LCD PAL179: I0 Position */
+#define LCD_PAL179_I0_Msk (0x01UL << LCD_PAL179_I0_Pos) /*!< LCD PAL179: I0 Mask */
+#define LCD_PAL179_R14_0_Pos 16 /*!< LCD PAL179: R14_0 Position */
+#define LCD_PAL179_R14_0_Msk (0x1fUL << LCD_PAL179_R14_0_Pos) /*!< LCD PAL179: R14_0 Mask */
+#define LCD_PAL179_G14_0_Pos 21 /*!< LCD PAL179: G14_0 Position */
+#define LCD_PAL179_G14_0_Msk (0x1fUL << LCD_PAL179_G14_0_Pos) /*!< LCD PAL179: G14_0 Mask */
+#define LCD_PAL179_B14_0_Pos 26 /*!< LCD PAL179: B14_0 Position */
+#define LCD_PAL179_B14_0_Msk (0x1fUL << LCD_PAL179_B14_0_Pos) /*!< LCD PAL179: B14_0 Mask */
+#define LCD_PAL179_I1_Pos 31 /*!< LCD PAL179: I1 Position */
+#define LCD_PAL179_I1_Msk (0x01UL << LCD_PAL179_I1_Pos) /*!< LCD PAL179: I1 Mask */
+
+// --------------------------------------- LCD_PAL180 -------------------------------------------
+#define LCD_PAL180_R04_0_Pos 0 /*!< LCD PAL180: R04_0 Position */
+#define LCD_PAL180_R04_0_Msk (0x1fUL << LCD_PAL180_R04_0_Pos) /*!< LCD PAL180: R04_0 Mask */
+#define LCD_PAL180_G04_0_Pos 5 /*!< LCD PAL180: G04_0 Position */
+#define LCD_PAL180_G04_0_Msk (0x1fUL << LCD_PAL180_G04_0_Pos) /*!< LCD PAL180: G04_0 Mask */
+#define LCD_PAL180_B04_0_Pos 10 /*!< LCD PAL180: B04_0 Position */
+#define LCD_PAL180_B04_0_Msk (0x1fUL << LCD_PAL180_B04_0_Pos) /*!< LCD PAL180: B04_0 Mask */
+#define LCD_PAL180_I0_Pos 15 /*!< LCD PAL180: I0 Position */
+#define LCD_PAL180_I0_Msk (0x01UL << LCD_PAL180_I0_Pos) /*!< LCD PAL180: I0 Mask */
+#define LCD_PAL180_R14_0_Pos 16 /*!< LCD PAL180: R14_0 Position */
+#define LCD_PAL180_R14_0_Msk (0x1fUL << LCD_PAL180_R14_0_Pos) /*!< LCD PAL180: R14_0 Mask */
+#define LCD_PAL180_G14_0_Pos 21 /*!< LCD PAL180: G14_0 Position */
+#define LCD_PAL180_G14_0_Msk (0x1fUL << LCD_PAL180_G14_0_Pos) /*!< LCD PAL180: G14_0 Mask */
+#define LCD_PAL180_B14_0_Pos 26 /*!< LCD PAL180: B14_0 Position */
+#define LCD_PAL180_B14_0_Msk (0x1fUL << LCD_PAL180_B14_0_Pos) /*!< LCD PAL180: B14_0 Mask */
+#define LCD_PAL180_I1_Pos 31 /*!< LCD PAL180: I1 Position */
+#define LCD_PAL180_I1_Msk (0x01UL << LCD_PAL180_I1_Pos) /*!< LCD PAL180: I1 Mask */
+
+// --------------------------------------- LCD_PAL181 -------------------------------------------
+#define LCD_PAL181_R04_0_Pos 0 /*!< LCD PAL181: R04_0 Position */
+#define LCD_PAL181_R04_0_Msk (0x1fUL << LCD_PAL181_R04_0_Pos) /*!< LCD PAL181: R04_0 Mask */
+#define LCD_PAL181_G04_0_Pos 5 /*!< LCD PAL181: G04_0 Position */
+#define LCD_PAL181_G04_0_Msk (0x1fUL << LCD_PAL181_G04_0_Pos) /*!< LCD PAL181: G04_0 Mask */
+#define LCD_PAL181_B04_0_Pos 10 /*!< LCD PAL181: B04_0 Position */
+#define LCD_PAL181_B04_0_Msk (0x1fUL << LCD_PAL181_B04_0_Pos) /*!< LCD PAL181: B04_0 Mask */
+#define LCD_PAL181_I0_Pos 15 /*!< LCD PAL181: I0 Position */
+#define LCD_PAL181_I0_Msk (0x01UL << LCD_PAL181_I0_Pos) /*!< LCD PAL181: I0 Mask */
+#define LCD_PAL181_R14_0_Pos 16 /*!< LCD PAL181: R14_0 Position */
+#define LCD_PAL181_R14_0_Msk (0x1fUL << LCD_PAL181_R14_0_Pos) /*!< LCD PAL181: R14_0 Mask */
+#define LCD_PAL181_G14_0_Pos 21 /*!< LCD PAL181: G14_0 Position */
+#define LCD_PAL181_G14_0_Msk (0x1fUL << LCD_PAL181_G14_0_Pos) /*!< LCD PAL181: G14_0 Mask */
+#define LCD_PAL181_B14_0_Pos 26 /*!< LCD PAL181: B14_0 Position */
+#define LCD_PAL181_B14_0_Msk (0x1fUL << LCD_PAL181_B14_0_Pos) /*!< LCD PAL181: B14_0 Mask */
+#define LCD_PAL181_I1_Pos 31 /*!< LCD PAL181: I1 Position */
+#define LCD_PAL181_I1_Msk (0x01UL << LCD_PAL181_I1_Pos) /*!< LCD PAL181: I1 Mask */
+
+// --------------------------------------- LCD_PAL182 -------------------------------------------
+#define LCD_PAL182_R04_0_Pos 0 /*!< LCD PAL182: R04_0 Position */
+#define LCD_PAL182_R04_0_Msk (0x1fUL << LCD_PAL182_R04_0_Pos) /*!< LCD PAL182: R04_0 Mask */
+#define LCD_PAL182_G04_0_Pos 5 /*!< LCD PAL182: G04_0 Position */
+#define LCD_PAL182_G04_0_Msk (0x1fUL << LCD_PAL182_G04_0_Pos) /*!< LCD PAL182: G04_0 Mask */
+#define LCD_PAL182_B04_0_Pos 10 /*!< LCD PAL182: B04_0 Position */
+#define LCD_PAL182_B04_0_Msk (0x1fUL << LCD_PAL182_B04_0_Pos) /*!< LCD PAL182: B04_0 Mask */
+#define LCD_PAL182_I0_Pos 15 /*!< LCD PAL182: I0 Position */
+#define LCD_PAL182_I0_Msk (0x01UL << LCD_PAL182_I0_Pos) /*!< LCD PAL182: I0 Mask */
+#define LCD_PAL182_R14_0_Pos 16 /*!< LCD PAL182: R14_0 Position */
+#define LCD_PAL182_R14_0_Msk (0x1fUL << LCD_PAL182_R14_0_Pos) /*!< LCD PAL182: R14_0 Mask */
+#define LCD_PAL182_G14_0_Pos 21 /*!< LCD PAL182: G14_0 Position */
+#define LCD_PAL182_G14_0_Msk (0x1fUL << LCD_PAL182_G14_0_Pos) /*!< LCD PAL182: G14_0 Mask */
+#define LCD_PAL182_B14_0_Pos 26 /*!< LCD PAL182: B14_0 Position */
+#define LCD_PAL182_B14_0_Msk (0x1fUL << LCD_PAL182_B14_0_Pos) /*!< LCD PAL182: B14_0 Mask */
+#define LCD_PAL182_I1_Pos 31 /*!< LCD PAL182: I1 Position */
+#define LCD_PAL182_I1_Msk (0x01UL << LCD_PAL182_I1_Pos) /*!< LCD PAL182: I1 Mask */
+
+// --------------------------------------- LCD_PAL183 -------------------------------------------
+#define LCD_PAL183_R04_0_Pos 0 /*!< LCD PAL183: R04_0 Position */
+#define LCD_PAL183_R04_0_Msk (0x1fUL << LCD_PAL183_R04_0_Pos) /*!< LCD PAL183: R04_0 Mask */
+#define LCD_PAL183_G04_0_Pos 5 /*!< LCD PAL183: G04_0 Position */
+#define LCD_PAL183_G04_0_Msk (0x1fUL << LCD_PAL183_G04_0_Pos) /*!< LCD PAL183: G04_0 Mask */
+#define LCD_PAL183_B04_0_Pos 10 /*!< LCD PAL183: B04_0 Position */
+#define LCD_PAL183_B04_0_Msk (0x1fUL << LCD_PAL183_B04_0_Pos) /*!< LCD PAL183: B04_0 Mask */
+#define LCD_PAL183_I0_Pos 15 /*!< LCD PAL183: I0 Position */
+#define LCD_PAL183_I0_Msk (0x01UL << LCD_PAL183_I0_Pos) /*!< LCD PAL183: I0 Mask */
+#define LCD_PAL183_R14_0_Pos 16 /*!< LCD PAL183: R14_0 Position */
+#define LCD_PAL183_R14_0_Msk (0x1fUL << LCD_PAL183_R14_0_Pos) /*!< LCD PAL183: R14_0 Mask */
+#define LCD_PAL183_G14_0_Pos 21 /*!< LCD PAL183: G14_0 Position */
+#define LCD_PAL183_G14_0_Msk (0x1fUL << LCD_PAL183_G14_0_Pos) /*!< LCD PAL183: G14_0 Mask */
+#define LCD_PAL183_B14_0_Pos 26 /*!< LCD PAL183: B14_0 Position */
+#define LCD_PAL183_B14_0_Msk (0x1fUL << LCD_PAL183_B14_0_Pos) /*!< LCD PAL183: B14_0 Mask */
+#define LCD_PAL183_I1_Pos 31 /*!< LCD PAL183: I1 Position */
+#define LCD_PAL183_I1_Msk (0x01UL << LCD_PAL183_I1_Pos) /*!< LCD PAL183: I1 Mask */
+
+// --------------------------------------- LCD_PAL184 -------------------------------------------
+#define LCD_PAL184_R04_0_Pos 0 /*!< LCD PAL184: R04_0 Position */
+#define LCD_PAL184_R04_0_Msk (0x1fUL << LCD_PAL184_R04_0_Pos) /*!< LCD PAL184: R04_0 Mask */
+#define LCD_PAL184_G04_0_Pos 5 /*!< LCD PAL184: G04_0 Position */
+#define LCD_PAL184_G04_0_Msk (0x1fUL << LCD_PAL184_G04_0_Pos) /*!< LCD PAL184: G04_0 Mask */
+#define LCD_PAL184_B04_0_Pos 10 /*!< LCD PAL184: B04_0 Position */
+#define LCD_PAL184_B04_0_Msk (0x1fUL << LCD_PAL184_B04_0_Pos) /*!< LCD PAL184: B04_0 Mask */
+#define LCD_PAL184_I0_Pos 15 /*!< LCD PAL184: I0 Position */
+#define LCD_PAL184_I0_Msk (0x01UL << LCD_PAL184_I0_Pos) /*!< LCD PAL184: I0 Mask */
+#define LCD_PAL184_R14_0_Pos 16 /*!< LCD PAL184: R14_0 Position */
+#define LCD_PAL184_R14_0_Msk (0x1fUL << LCD_PAL184_R14_0_Pos) /*!< LCD PAL184: R14_0 Mask */
+#define LCD_PAL184_G14_0_Pos 21 /*!< LCD PAL184: G14_0 Position */
+#define LCD_PAL184_G14_0_Msk (0x1fUL << LCD_PAL184_G14_0_Pos) /*!< LCD PAL184: G14_0 Mask */
+#define LCD_PAL184_B14_0_Pos 26 /*!< LCD PAL184: B14_0 Position */
+#define LCD_PAL184_B14_0_Msk (0x1fUL << LCD_PAL184_B14_0_Pos) /*!< LCD PAL184: B14_0 Mask */
+#define LCD_PAL184_I1_Pos 31 /*!< LCD PAL184: I1 Position */
+#define LCD_PAL184_I1_Msk (0x01UL << LCD_PAL184_I1_Pos) /*!< LCD PAL184: I1 Mask */
+
+// --------------------------------------- LCD_PAL185 -------------------------------------------
+#define LCD_PAL185_R04_0_Pos 0 /*!< LCD PAL185: R04_0 Position */
+#define LCD_PAL185_R04_0_Msk (0x1fUL << LCD_PAL185_R04_0_Pos) /*!< LCD PAL185: R04_0 Mask */
+#define LCD_PAL185_G04_0_Pos 5 /*!< LCD PAL185: G04_0 Position */
+#define LCD_PAL185_G04_0_Msk (0x1fUL << LCD_PAL185_G04_0_Pos) /*!< LCD PAL185: G04_0 Mask */
+#define LCD_PAL185_B04_0_Pos 10 /*!< LCD PAL185: B04_0 Position */
+#define LCD_PAL185_B04_0_Msk (0x1fUL << LCD_PAL185_B04_0_Pos) /*!< LCD PAL185: B04_0 Mask */
+#define LCD_PAL185_I0_Pos 15 /*!< LCD PAL185: I0 Position */
+#define LCD_PAL185_I0_Msk (0x01UL << LCD_PAL185_I0_Pos) /*!< LCD PAL185: I0 Mask */
+#define LCD_PAL185_R14_0_Pos 16 /*!< LCD PAL185: R14_0 Position */
+#define LCD_PAL185_R14_0_Msk (0x1fUL << LCD_PAL185_R14_0_Pos) /*!< LCD PAL185: R14_0 Mask */
+#define LCD_PAL185_G14_0_Pos 21 /*!< LCD PAL185: G14_0 Position */
+#define LCD_PAL185_G14_0_Msk (0x1fUL << LCD_PAL185_G14_0_Pos) /*!< LCD PAL185: G14_0 Mask */
+#define LCD_PAL185_B14_0_Pos 26 /*!< LCD PAL185: B14_0 Position */
+#define LCD_PAL185_B14_0_Msk (0x1fUL << LCD_PAL185_B14_0_Pos) /*!< LCD PAL185: B14_0 Mask */
+#define LCD_PAL185_I1_Pos 31 /*!< LCD PAL185: I1 Position */
+#define LCD_PAL185_I1_Msk (0x01UL << LCD_PAL185_I1_Pos) /*!< LCD PAL185: I1 Mask */
+
+// --------------------------------------- LCD_PAL186 -------------------------------------------
+#define LCD_PAL186_R04_0_Pos 0 /*!< LCD PAL186: R04_0 Position */
+#define LCD_PAL186_R04_0_Msk (0x1fUL << LCD_PAL186_R04_0_Pos) /*!< LCD PAL186: R04_0 Mask */
+#define LCD_PAL186_G04_0_Pos 5 /*!< LCD PAL186: G04_0 Position */
+#define LCD_PAL186_G04_0_Msk (0x1fUL << LCD_PAL186_G04_0_Pos) /*!< LCD PAL186: G04_0 Mask */
+#define LCD_PAL186_B04_0_Pos 10 /*!< LCD PAL186: B04_0 Position */
+#define LCD_PAL186_B04_0_Msk (0x1fUL << LCD_PAL186_B04_0_Pos) /*!< LCD PAL186: B04_0 Mask */
+#define LCD_PAL186_I0_Pos 15 /*!< LCD PAL186: I0 Position */
+#define LCD_PAL186_I0_Msk (0x01UL << LCD_PAL186_I0_Pos) /*!< LCD PAL186: I0 Mask */
+#define LCD_PAL186_R14_0_Pos 16 /*!< LCD PAL186: R14_0 Position */
+#define LCD_PAL186_R14_0_Msk (0x1fUL << LCD_PAL186_R14_0_Pos) /*!< LCD PAL186: R14_0 Mask */
+#define LCD_PAL186_G14_0_Pos 21 /*!< LCD PAL186: G14_0 Position */
+#define LCD_PAL186_G14_0_Msk (0x1fUL << LCD_PAL186_G14_0_Pos) /*!< LCD PAL186: G14_0 Mask */
+#define LCD_PAL186_B14_0_Pos 26 /*!< LCD PAL186: B14_0 Position */
+#define LCD_PAL186_B14_0_Msk (0x1fUL << LCD_PAL186_B14_0_Pos) /*!< LCD PAL186: B14_0 Mask */
+#define LCD_PAL186_I1_Pos 31 /*!< LCD PAL186: I1 Position */
+#define LCD_PAL186_I1_Msk (0x01UL << LCD_PAL186_I1_Pos) /*!< LCD PAL186: I1 Mask */
+
+// --------------------------------------- LCD_PAL187 -------------------------------------------
+#define LCD_PAL187_R04_0_Pos 0 /*!< LCD PAL187: R04_0 Position */
+#define LCD_PAL187_R04_0_Msk (0x1fUL << LCD_PAL187_R04_0_Pos) /*!< LCD PAL187: R04_0 Mask */
+#define LCD_PAL187_G04_0_Pos 5 /*!< LCD PAL187: G04_0 Position */
+#define LCD_PAL187_G04_0_Msk (0x1fUL << LCD_PAL187_G04_0_Pos) /*!< LCD PAL187: G04_0 Mask */
+#define LCD_PAL187_B04_0_Pos 10 /*!< LCD PAL187: B04_0 Position */
+#define LCD_PAL187_B04_0_Msk (0x1fUL << LCD_PAL187_B04_0_Pos) /*!< LCD PAL187: B04_0 Mask */
+#define LCD_PAL187_I0_Pos 15 /*!< LCD PAL187: I0 Position */
+#define LCD_PAL187_I0_Msk (0x01UL << LCD_PAL187_I0_Pos) /*!< LCD PAL187: I0 Mask */
+#define LCD_PAL187_R14_0_Pos 16 /*!< LCD PAL187: R14_0 Position */
+#define LCD_PAL187_R14_0_Msk (0x1fUL << LCD_PAL187_R14_0_Pos) /*!< LCD PAL187: R14_0 Mask */
+#define LCD_PAL187_G14_0_Pos 21 /*!< LCD PAL187: G14_0 Position */
+#define LCD_PAL187_G14_0_Msk (0x1fUL << LCD_PAL187_G14_0_Pos) /*!< LCD PAL187: G14_0 Mask */
+#define LCD_PAL187_B14_0_Pos 26 /*!< LCD PAL187: B14_0 Position */
+#define LCD_PAL187_B14_0_Msk (0x1fUL << LCD_PAL187_B14_0_Pos) /*!< LCD PAL187: B14_0 Mask */
+#define LCD_PAL187_I1_Pos 31 /*!< LCD PAL187: I1 Position */
+#define LCD_PAL187_I1_Msk (0x01UL << LCD_PAL187_I1_Pos) /*!< LCD PAL187: I1 Mask */
+
+// --------------------------------------- LCD_PAL188 -------------------------------------------
+#define LCD_PAL188_R04_0_Pos 0 /*!< LCD PAL188: R04_0 Position */
+#define LCD_PAL188_R04_0_Msk (0x1fUL << LCD_PAL188_R04_0_Pos) /*!< LCD PAL188: R04_0 Mask */
+#define LCD_PAL188_G04_0_Pos 5 /*!< LCD PAL188: G04_0 Position */
+#define LCD_PAL188_G04_0_Msk (0x1fUL << LCD_PAL188_G04_0_Pos) /*!< LCD PAL188: G04_0 Mask */
+#define LCD_PAL188_B04_0_Pos 10 /*!< LCD PAL188: B04_0 Position */
+#define LCD_PAL188_B04_0_Msk (0x1fUL << LCD_PAL188_B04_0_Pos) /*!< LCD PAL188: B04_0 Mask */
+#define LCD_PAL188_I0_Pos 15 /*!< LCD PAL188: I0 Position */
+#define LCD_PAL188_I0_Msk (0x01UL << LCD_PAL188_I0_Pos) /*!< LCD PAL188: I0 Mask */
+#define LCD_PAL188_R14_0_Pos 16 /*!< LCD PAL188: R14_0 Position */
+#define LCD_PAL188_R14_0_Msk (0x1fUL << LCD_PAL188_R14_0_Pos) /*!< LCD PAL188: R14_0 Mask */
+#define LCD_PAL188_G14_0_Pos 21 /*!< LCD PAL188: G14_0 Position */
+#define LCD_PAL188_G14_0_Msk (0x1fUL << LCD_PAL188_G14_0_Pos) /*!< LCD PAL188: G14_0 Mask */
+#define LCD_PAL188_B14_0_Pos 26 /*!< LCD PAL188: B14_0 Position */
+#define LCD_PAL188_B14_0_Msk (0x1fUL << LCD_PAL188_B14_0_Pos) /*!< LCD PAL188: B14_0 Mask */
+#define LCD_PAL188_I1_Pos 31 /*!< LCD PAL188: I1 Position */
+#define LCD_PAL188_I1_Msk (0x01UL << LCD_PAL188_I1_Pos) /*!< LCD PAL188: I1 Mask */
+
+// --------------------------------------- LCD_PAL189 -------------------------------------------
+#define LCD_PAL189_R04_0_Pos 0 /*!< LCD PAL189: R04_0 Position */
+#define LCD_PAL189_R04_0_Msk (0x1fUL << LCD_PAL189_R04_0_Pos) /*!< LCD PAL189: R04_0 Mask */
+#define LCD_PAL189_G04_0_Pos 5 /*!< LCD PAL189: G04_0 Position */
+#define LCD_PAL189_G04_0_Msk (0x1fUL << LCD_PAL189_G04_0_Pos) /*!< LCD PAL189: G04_0 Mask */
+#define LCD_PAL189_B04_0_Pos 10 /*!< LCD PAL189: B04_0 Position */
+#define LCD_PAL189_B04_0_Msk (0x1fUL << LCD_PAL189_B04_0_Pos) /*!< LCD PAL189: B04_0 Mask */
+#define LCD_PAL189_I0_Pos 15 /*!< LCD PAL189: I0 Position */
+#define LCD_PAL189_I0_Msk (0x01UL << LCD_PAL189_I0_Pos) /*!< LCD PAL189: I0 Mask */
+#define LCD_PAL189_R14_0_Pos 16 /*!< LCD PAL189: R14_0 Position */
+#define LCD_PAL189_R14_0_Msk (0x1fUL << LCD_PAL189_R14_0_Pos) /*!< LCD PAL189: R14_0 Mask */
+#define LCD_PAL189_G14_0_Pos 21 /*!< LCD PAL189: G14_0 Position */
+#define LCD_PAL189_G14_0_Msk (0x1fUL << LCD_PAL189_G14_0_Pos) /*!< LCD PAL189: G14_0 Mask */
+#define LCD_PAL189_B14_0_Pos 26 /*!< LCD PAL189: B14_0 Position */
+#define LCD_PAL189_B14_0_Msk (0x1fUL << LCD_PAL189_B14_0_Pos) /*!< LCD PAL189: B14_0 Mask */
+#define LCD_PAL189_I1_Pos 31 /*!< LCD PAL189: I1 Position */
+#define LCD_PAL189_I1_Msk (0x01UL << LCD_PAL189_I1_Pos) /*!< LCD PAL189: I1 Mask */
+
+// --------------------------------------- LCD_PAL190 -------------------------------------------
+#define LCD_PAL190_R04_0_Pos 0 /*!< LCD PAL190: R04_0 Position */
+#define LCD_PAL190_R04_0_Msk (0x1fUL << LCD_PAL190_R04_0_Pos) /*!< LCD PAL190: R04_0 Mask */
+#define LCD_PAL190_G04_0_Pos 5 /*!< LCD PAL190: G04_0 Position */
+#define LCD_PAL190_G04_0_Msk (0x1fUL << LCD_PAL190_G04_0_Pos) /*!< LCD PAL190: G04_0 Mask */
+#define LCD_PAL190_B04_0_Pos 10 /*!< LCD PAL190: B04_0 Position */
+#define LCD_PAL190_B04_0_Msk (0x1fUL << LCD_PAL190_B04_0_Pos) /*!< LCD PAL190: B04_0 Mask */
+#define LCD_PAL190_I0_Pos 15 /*!< LCD PAL190: I0 Position */
+#define LCD_PAL190_I0_Msk (0x01UL << LCD_PAL190_I0_Pos) /*!< LCD PAL190: I0 Mask */
+#define LCD_PAL190_R14_0_Pos 16 /*!< LCD PAL190: R14_0 Position */
+#define LCD_PAL190_R14_0_Msk (0x1fUL << LCD_PAL190_R14_0_Pos) /*!< LCD PAL190: R14_0 Mask */
+#define LCD_PAL190_G14_0_Pos 21 /*!< LCD PAL190: G14_0 Position */
+#define LCD_PAL190_G14_0_Msk (0x1fUL << LCD_PAL190_G14_0_Pos) /*!< LCD PAL190: G14_0 Mask */
+#define LCD_PAL190_B14_0_Pos 26 /*!< LCD PAL190: B14_0 Position */
+#define LCD_PAL190_B14_0_Msk (0x1fUL << LCD_PAL190_B14_0_Pos) /*!< LCD PAL190: B14_0 Mask */
+#define LCD_PAL190_I1_Pos 31 /*!< LCD PAL190: I1 Position */
+#define LCD_PAL190_I1_Msk (0x01UL << LCD_PAL190_I1_Pos) /*!< LCD PAL190: I1 Mask */
+
+// --------------------------------------- LCD_PAL191 -------------------------------------------
+#define LCD_PAL191_R04_0_Pos 0 /*!< LCD PAL191: R04_0 Position */
+#define LCD_PAL191_R04_0_Msk (0x1fUL << LCD_PAL191_R04_0_Pos) /*!< LCD PAL191: R04_0 Mask */
+#define LCD_PAL191_G04_0_Pos 5 /*!< LCD PAL191: G04_0 Position */
+#define LCD_PAL191_G04_0_Msk (0x1fUL << LCD_PAL191_G04_0_Pos) /*!< LCD PAL191: G04_0 Mask */
+#define LCD_PAL191_B04_0_Pos 10 /*!< LCD PAL191: B04_0 Position */
+#define LCD_PAL191_B04_0_Msk (0x1fUL << LCD_PAL191_B04_0_Pos) /*!< LCD PAL191: B04_0 Mask */
+#define LCD_PAL191_I0_Pos 15 /*!< LCD PAL191: I0 Position */
+#define LCD_PAL191_I0_Msk (0x01UL << LCD_PAL191_I0_Pos) /*!< LCD PAL191: I0 Mask */
+#define LCD_PAL191_R14_0_Pos 16 /*!< LCD PAL191: R14_0 Position */
+#define LCD_PAL191_R14_0_Msk (0x1fUL << LCD_PAL191_R14_0_Pos) /*!< LCD PAL191: R14_0 Mask */
+#define LCD_PAL191_G14_0_Pos 21 /*!< LCD PAL191: G14_0 Position */
+#define LCD_PAL191_G14_0_Msk (0x1fUL << LCD_PAL191_G14_0_Pos) /*!< LCD PAL191: G14_0 Mask */
+#define LCD_PAL191_B14_0_Pos 26 /*!< LCD PAL191: B14_0 Position */
+#define LCD_PAL191_B14_0_Msk (0x1fUL << LCD_PAL191_B14_0_Pos) /*!< LCD PAL191: B14_0 Mask */
+#define LCD_PAL191_I1_Pos 31 /*!< LCD PAL191: I1 Position */
+#define LCD_PAL191_I1_Msk (0x01UL << LCD_PAL191_I1_Pos) /*!< LCD PAL191: I1 Mask */
+
+// --------------------------------------- LCD_PAL192 -------------------------------------------
+#define LCD_PAL192_R04_0_Pos 0 /*!< LCD PAL192: R04_0 Position */
+#define LCD_PAL192_R04_0_Msk (0x1fUL << LCD_PAL192_R04_0_Pos) /*!< LCD PAL192: R04_0 Mask */
+#define LCD_PAL192_G04_0_Pos 5 /*!< LCD PAL192: G04_0 Position */
+#define LCD_PAL192_G04_0_Msk (0x1fUL << LCD_PAL192_G04_0_Pos) /*!< LCD PAL192: G04_0 Mask */
+#define LCD_PAL192_B04_0_Pos 10 /*!< LCD PAL192: B04_0 Position */
+#define LCD_PAL192_B04_0_Msk (0x1fUL << LCD_PAL192_B04_0_Pos) /*!< LCD PAL192: B04_0 Mask */
+#define LCD_PAL192_I0_Pos 15 /*!< LCD PAL192: I0 Position */
+#define LCD_PAL192_I0_Msk (0x01UL << LCD_PAL192_I0_Pos) /*!< LCD PAL192: I0 Mask */
+#define LCD_PAL192_R14_0_Pos 16 /*!< LCD PAL192: R14_0 Position */
+#define LCD_PAL192_R14_0_Msk (0x1fUL << LCD_PAL192_R14_0_Pos) /*!< LCD PAL192: R14_0 Mask */
+#define LCD_PAL192_G14_0_Pos 21 /*!< LCD PAL192: G14_0 Position */
+#define LCD_PAL192_G14_0_Msk (0x1fUL << LCD_PAL192_G14_0_Pos) /*!< LCD PAL192: G14_0 Mask */
+#define LCD_PAL192_B14_0_Pos 26 /*!< LCD PAL192: B14_0 Position */
+#define LCD_PAL192_B14_0_Msk (0x1fUL << LCD_PAL192_B14_0_Pos) /*!< LCD PAL192: B14_0 Mask */
+#define LCD_PAL192_I1_Pos 31 /*!< LCD PAL192: I1 Position */
+#define LCD_PAL192_I1_Msk (0x01UL << LCD_PAL192_I1_Pos) /*!< LCD PAL192: I1 Mask */
+
+// --------------------------------------- LCD_PAL193 -------------------------------------------
+#define LCD_PAL193_R04_0_Pos 0 /*!< LCD PAL193: R04_0 Position */
+#define LCD_PAL193_R04_0_Msk (0x1fUL << LCD_PAL193_R04_0_Pos) /*!< LCD PAL193: R04_0 Mask */
+#define LCD_PAL193_G04_0_Pos 5 /*!< LCD PAL193: G04_0 Position */
+#define LCD_PAL193_G04_0_Msk (0x1fUL << LCD_PAL193_G04_0_Pos) /*!< LCD PAL193: G04_0 Mask */
+#define LCD_PAL193_B04_0_Pos 10 /*!< LCD PAL193: B04_0 Position */
+#define LCD_PAL193_B04_0_Msk (0x1fUL << LCD_PAL193_B04_0_Pos) /*!< LCD PAL193: B04_0 Mask */
+#define LCD_PAL193_I0_Pos 15 /*!< LCD PAL193: I0 Position */
+#define LCD_PAL193_I0_Msk (0x01UL << LCD_PAL193_I0_Pos) /*!< LCD PAL193: I0 Mask */
+#define LCD_PAL193_R14_0_Pos 16 /*!< LCD PAL193: R14_0 Position */
+#define LCD_PAL193_R14_0_Msk (0x1fUL << LCD_PAL193_R14_0_Pos) /*!< LCD PAL193: R14_0 Mask */
+#define LCD_PAL193_G14_0_Pos 21 /*!< LCD PAL193: G14_0 Position */
+#define LCD_PAL193_G14_0_Msk (0x1fUL << LCD_PAL193_G14_0_Pos) /*!< LCD PAL193: G14_0 Mask */
+#define LCD_PAL193_B14_0_Pos 26 /*!< LCD PAL193: B14_0 Position */
+#define LCD_PAL193_B14_0_Msk (0x1fUL << LCD_PAL193_B14_0_Pos) /*!< LCD PAL193: B14_0 Mask */
+#define LCD_PAL193_I1_Pos 31 /*!< LCD PAL193: I1 Position */
+#define LCD_PAL193_I1_Msk (0x01UL << LCD_PAL193_I1_Pos) /*!< LCD PAL193: I1 Mask */
+
+// --------------------------------------- LCD_PAL194 -------------------------------------------
+#define LCD_PAL194_R04_0_Pos 0 /*!< LCD PAL194: R04_0 Position */
+#define LCD_PAL194_R04_0_Msk (0x1fUL << LCD_PAL194_R04_0_Pos) /*!< LCD PAL194: R04_0 Mask */
+#define LCD_PAL194_G04_0_Pos 5 /*!< LCD PAL194: G04_0 Position */
+#define LCD_PAL194_G04_0_Msk (0x1fUL << LCD_PAL194_G04_0_Pos) /*!< LCD PAL194: G04_0 Mask */
+#define LCD_PAL194_B04_0_Pos 10 /*!< LCD PAL194: B04_0 Position */
+#define LCD_PAL194_B04_0_Msk (0x1fUL << LCD_PAL194_B04_0_Pos) /*!< LCD PAL194: B04_0 Mask */
+#define LCD_PAL194_I0_Pos 15 /*!< LCD PAL194: I0 Position */
+#define LCD_PAL194_I0_Msk (0x01UL << LCD_PAL194_I0_Pos) /*!< LCD PAL194: I0 Mask */
+#define LCD_PAL194_R14_0_Pos 16 /*!< LCD PAL194: R14_0 Position */
+#define LCD_PAL194_R14_0_Msk (0x1fUL << LCD_PAL194_R14_0_Pos) /*!< LCD PAL194: R14_0 Mask */
+#define LCD_PAL194_G14_0_Pos 21 /*!< LCD PAL194: G14_0 Position */
+#define LCD_PAL194_G14_0_Msk (0x1fUL << LCD_PAL194_G14_0_Pos) /*!< LCD PAL194: G14_0 Mask */
+#define LCD_PAL194_B14_0_Pos 26 /*!< LCD PAL194: B14_0 Position */
+#define LCD_PAL194_B14_0_Msk (0x1fUL << LCD_PAL194_B14_0_Pos) /*!< LCD PAL194: B14_0 Mask */
+#define LCD_PAL194_I1_Pos 31 /*!< LCD PAL194: I1 Position */
+#define LCD_PAL194_I1_Msk (0x01UL << LCD_PAL194_I1_Pos) /*!< LCD PAL194: I1 Mask */
+
+// --------------------------------------- LCD_PAL195 -------------------------------------------
+#define LCD_PAL195_R04_0_Pos 0 /*!< LCD PAL195: R04_0 Position */
+#define LCD_PAL195_R04_0_Msk (0x1fUL << LCD_PAL195_R04_0_Pos) /*!< LCD PAL195: R04_0 Mask */
+#define LCD_PAL195_G04_0_Pos 5 /*!< LCD PAL195: G04_0 Position */
+#define LCD_PAL195_G04_0_Msk (0x1fUL << LCD_PAL195_G04_0_Pos) /*!< LCD PAL195: G04_0 Mask */
+#define LCD_PAL195_B04_0_Pos 10 /*!< LCD PAL195: B04_0 Position */
+#define LCD_PAL195_B04_0_Msk (0x1fUL << LCD_PAL195_B04_0_Pos) /*!< LCD PAL195: B04_0 Mask */
+#define LCD_PAL195_I0_Pos 15 /*!< LCD PAL195: I0 Position */
+#define LCD_PAL195_I0_Msk (0x01UL << LCD_PAL195_I0_Pos) /*!< LCD PAL195: I0 Mask */
+#define LCD_PAL195_R14_0_Pos 16 /*!< LCD PAL195: R14_0 Position */
+#define LCD_PAL195_R14_0_Msk (0x1fUL << LCD_PAL195_R14_0_Pos) /*!< LCD PAL195: R14_0 Mask */
+#define LCD_PAL195_G14_0_Pos 21 /*!< LCD PAL195: G14_0 Position */
+#define LCD_PAL195_G14_0_Msk (0x1fUL << LCD_PAL195_G14_0_Pos) /*!< LCD PAL195: G14_0 Mask */
+#define LCD_PAL195_B14_0_Pos 26 /*!< LCD PAL195: B14_0 Position */
+#define LCD_PAL195_B14_0_Msk (0x1fUL << LCD_PAL195_B14_0_Pos) /*!< LCD PAL195: B14_0 Mask */
+#define LCD_PAL195_I1_Pos 31 /*!< LCD PAL195: I1 Position */
+#define LCD_PAL195_I1_Msk (0x01UL << LCD_PAL195_I1_Pos) /*!< LCD PAL195: I1 Mask */
+
+// --------------------------------------- LCD_PAL196 -------------------------------------------
+#define LCD_PAL196_R04_0_Pos 0 /*!< LCD PAL196: R04_0 Position */
+#define LCD_PAL196_R04_0_Msk (0x1fUL << LCD_PAL196_R04_0_Pos) /*!< LCD PAL196: R04_0 Mask */
+#define LCD_PAL196_G04_0_Pos 5 /*!< LCD PAL196: G04_0 Position */
+#define LCD_PAL196_G04_0_Msk (0x1fUL << LCD_PAL196_G04_0_Pos) /*!< LCD PAL196: G04_0 Mask */
+#define LCD_PAL196_B04_0_Pos 10 /*!< LCD PAL196: B04_0 Position */
+#define LCD_PAL196_B04_0_Msk (0x1fUL << LCD_PAL196_B04_0_Pos) /*!< LCD PAL196: B04_0 Mask */
+#define LCD_PAL196_I0_Pos 15 /*!< LCD PAL196: I0 Position */
+#define LCD_PAL196_I0_Msk (0x01UL << LCD_PAL196_I0_Pos) /*!< LCD PAL196: I0 Mask */
+#define LCD_PAL196_R14_0_Pos 16 /*!< LCD PAL196: R14_0 Position */
+#define LCD_PAL196_R14_0_Msk (0x1fUL << LCD_PAL196_R14_0_Pos) /*!< LCD PAL196: R14_0 Mask */
+#define LCD_PAL196_G14_0_Pos 21 /*!< LCD PAL196: G14_0 Position */
+#define LCD_PAL196_G14_0_Msk (0x1fUL << LCD_PAL196_G14_0_Pos) /*!< LCD PAL196: G14_0 Mask */
+#define LCD_PAL196_B14_0_Pos 26 /*!< LCD PAL196: B14_0 Position */
+#define LCD_PAL196_B14_0_Msk (0x1fUL << LCD_PAL196_B14_0_Pos) /*!< LCD PAL196: B14_0 Mask */
+#define LCD_PAL196_I1_Pos 31 /*!< LCD PAL196: I1 Position */
+#define LCD_PAL196_I1_Msk (0x01UL << LCD_PAL196_I1_Pos) /*!< LCD PAL196: I1 Mask */
+
+// --------------------------------------- LCD_PAL197 -------------------------------------------
+#define LCD_PAL197_R04_0_Pos 0 /*!< LCD PAL197: R04_0 Position */
+#define LCD_PAL197_R04_0_Msk (0x1fUL << LCD_PAL197_R04_0_Pos) /*!< LCD PAL197: R04_0 Mask */
+#define LCD_PAL197_G04_0_Pos 5 /*!< LCD PAL197: G04_0 Position */
+#define LCD_PAL197_G04_0_Msk (0x1fUL << LCD_PAL197_G04_0_Pos) /*!< LCD PAL197: G04_0 Mask */
+#define LCD_PAL197_B04_0_Pos 10 /*!< LCD PAL197: B04_0 Position */
+#define LCD_PAL197_B04_0_Msk (0x1fUL << LCD_PAL197_B04_0_Pos) /*!< LCD PAL197: B04_0 Mask */
+#define LCD_PAL197_I0_Pos 15 /*!< LCD PAL197: I0 Position */
+#define LCD_PAL197_I0_Msk (0x01UL << LCD_PAL197_I0_Pos) /*!< LCD PAL197: I0 Mask */
+#define LCD_PAL197_R14_0_Pos 16 /*!< LCD PAL197: R14_0 Position */
+#define LCD_PAL197_R14_0_Msk (0x1fUL << LCD_PAL197_R14_0_Pos) /*!< LCD PAL197: R14_0 Mask */
+#define LCD_PAL197_G14_0_Pos 21 /*!< LCD PAL197: G14_0 Position */
+#define LCD_PAL197_G14_0_Msk (0x1fUL << LCD_PAL197_G14_0_Pos) /*!< LCD PAL197: G14_0 Mask */
+#define LCD_PAL197_B14_0_Pos 26 /*!< LCD PAL197: B14_0 Position */
+#define LCD_PAL197_B14_0_Msk (0x1fUL << LCD_PAL197_B14_0_Pos) /*!< LCD PAL197: B14_0 Mask */
+#define LCD_PAL197_I1_Pos 31 /*!< LCD PAL197: I1 Position */
+#define LCD_PAL197_I1_Msk (0x01UL << LCD_PAL197_I1_Pos) /*!< LCD PAL197: I1 Mask */
+
+// --------------------------------------- LCD_PAL198 -------------------------------------------
+#define LCD_PAL198_R04_0_Pos 0 /*!< LCD PAL198: R04_0 Position */
+#define LCD_PAL198_R04_0_Msk (0x1fUL << LCD_PAL198_R04_0_Pos) /*!< LCD PAL198: R04_0 Mask */
+#define LCD_PAL198_G04_0_Pos 5 /*!< LCD PAL198: G04_0 Position */
+#define LCD_PAL198_G04_0_Msk (0x1fUL << LCD_PAL198_G04_0_Pos) /*!< LCD PAL198: G04_0 Mask */
+#define LCD_PAL198_B04_0_Pos 10 /*!< LCD PAL198: B04_0 Position */
+#define LCD_PAL198_B04_0_Msk (0x1fUL << LCD_PAL198_B04_0_Pos) /*!< LCD PAL198: B04_0 Mask */
+#define LCD_PAL198_I0_Pos 15 /*!< LCD PAL198: I0 Position */
+#define LCD_PAL198_I0_Msk (0x01UL << LCD_PAL198_I0_Pos) /*!< LCD PAL198: I0 Mask */
+#define LCD_PAL198_R14_0_Pos 16 /*!< LCD PAL198: R14_0 Position */
+#define LCD_PAL198_R14_0_Msk (0x1fUL << LCD_PAL198_R14_0_Pos) /*!< LCD PAL198: R14_0 Mask */
+#define LCD_PAL198_G14_0_Pos 21 /*!< LCD PAL198: G14_0 Position */
+#define LCD_PAL198_G14_0_Msk (0x1fUL << LCD_PAL198_G14_0_Pos) /*!< LCD PAL198: G14_0 Mask */
+#define LCD_PAL198_B14_0_Pos 26 /*!< LCD PAL198: B14_0 Position */
+#define LCD_PAL198_B14_0_Msk (0x1fUL << LCD_PAL198_B14_0_Pos) /*!< LCD PAL198: B14_0 Mask */
+#define LCD_PAL198_I1_Pos 31 /*!< LCD PAL198: I1 Position */
+#define LCD_PAL198_I1_Msk (0x01UL << LCD_PAL198_I1_Pos) /*!< LCD PAL198: I1 Mask */
+
+// --------------------------------------- LCD_PAL199 -------------------------------------------
+#define LCD_PAL199_R04_0_Pos 0 /*!< LCD PAL199: R04_0 Position */
+#define LCD_PAL199_R04_0_Msk (0x1fUL << LCD_PAL199_R04_0_Pos) /*!< LCD PAL199: R04_0 Mask */
+#define LCD_PAL199_G04_0_Pos 5 /*!< LCD PAL199: G04_0 Position */
+#define LCD_PAL199_G04_0_Msk (0x1fUL << LCD_PAL199_G04_0_Pos) /*!< LCD PAL199: G04_0 Mask */
+#define LCD_PAL199_B04_0_Pos 10 /*!< LCD PAL199: B04_0 Position */
+#define LCD_PAL199_B04_0_Msk (0x1fUL << LCD_PAL199_B04_0_Pos) /*!< LCD PAL199: B04_0 Mask */
+#define LCD_PAL199_I0_Pos 15 /*!< LCD PAL199: I0 Position */
+#define LCD_PAL199_I0_Msk (0x01UL << LCD_PAL199_I0_Pos) /*!< LCD PAL199: I0 Mask */
+#define LCD_PAL199_R14_0_Pos 16 /*!< LCD PAL199: R14_0 Position */
+#define LCD_PAL199_R14_0_Msk (0x1fUL << LCD_PAL199_R14_0_Pos) /*!< LCD PAL199: R14_0 Mask */
+#define LCD_PAL199_G14_0_Pos 21 /*!< LCD PAL199: G14_0 Position */
+#define LCD_PAL199_G14_0_Msk (0x1fUL << LCD_PAL199_G14_0_Pos) /*!< LCD PAL199: G14_0 Mask */
+#define LCD_PAL199_B14_0_Pos 26 /*!< LCD PAL199: B14_0 Position */
+#define LCD_PAL199_B14_0_Msk (0x1fUL << LCD_PAL199_B14_0_Pos) /*!< LCD PAL199: B14_0 Mask */
+#define LCD_PAL199_I1_Pos 31 /*!< LCD PAL199: I1 Position */
+#define LCD_PAL199_I1_Msk (0x01UL << LCD_PAL199_I1_Pos) /*!< LCD PAL199: I1 Mask */
+
+// --------------------------------------- LCD_PAL200 -------------------------------------------
+#define LCD_PAL200_R04_0_Pos 0 /*!< LCD PAL200: R04_0 Position */
+#define LCD_PAL200_R04_0_Msk (0x1fUL << LCD_PAL200_R04_0_Pos) /*!< LCD PAL200: R04_0 Mask */
+#define LCD_PAL200_G04_0_Pos 5 /*!< LCD PAL200: G04_0 Position */
+#define LCD_PAL200_G04_0_Msk (0x1fUL << LCD_PAL200_G04_0_Pos) /*!< LCD PAL200: G04_0 Mask */
+#define LCD_PAL200_B04_0_Pos 10 /*!< LCD PAL200: B04_0 Position */
+#define LCD_PAL200_B04_0_Msk (0x1fUL << LCD_PAL200_B04_0_Pos) /*!< LCD PAL200: B04_0 Mask */
+#define LCD_PAL200_I0_Pos 15 /*!< LCD PAL200: I0 Position */
+#define LCD_PAL200_I0_Msk (0x01UL << LCD_PAL200_I0_Pos) /*!< LCD PAL200: I0 Mask */
+#define LCD_PAL200_R14_0_Pos 16 /*!< LCD PAL200: R14_0 Position */
+#define LCD_PAL200_R14_0_Msk (0x1fUL << LCD_PAL200_R14_0_Pos) /*!< LCD PAL200: R14_0 Mask */
+#define LCD_PAL200_G14_0_Pos 21 /*!< LCD PAL200: G14_0 Position */
+#define LCD_PAL200_G14_0_Msk (0x1fUL << LCD_PAL200_G14_0_Pos) /*!< LCD PAL200: G14_0 Mask */
+#define LCD_PAL200_B14_0_Pos 26 /*!< LCD PAL200: B14_0 Position */
+#define LCD_PAL200_B14_0_Msk (0x1fUL << LCD_PAL200_B14_0_Pos) /*!< LCD PAL200: B14_0 Mask */
+#define LCD_PAL200_I1_Pos 31 /*!< LCD PAL200: I1 Position */
+#define LCD_PAL200_I1_Msk (0x01UL << LCD_PAL200_I1_Pos) /*!< LCD PAL200: I1 Mask */
+
+// --------------------------------------- LCD_PAL201 -------------------------------------------
+#define LCD_PAL201_R04_0_Pos 0 /*!< LCD PAL201: R04_0 Position */
+#define LCD_PAL201_R04_0_Msk (0x1fUL << LCD_PAL201_R04_0_Pos) /*!< LCD PAL201: R04_0 Mask */
+#define LCD_PAL201_G04_0_Pos 5 /*!< LCD PAL201: G04_0 Position */
+#define LCD_PAL201_G04_0_Msk (0x1fUL << LCD_PAL201_G04_0_Pos) /*!< LCD PAL201: G04_0 Mask */
+#define LCD_PAL201_B04_0_Pos 10 /*!< LCD PAL201: B04_0 Position */
+#define LCD_PAL201_B04_0_Msk (0x1fUL << LCD_PAL201_B04_0_Pos) /*!< LCD PAL201: B04_0 Mask */
+#define LCD_PAL201_I0_Pos 15 /*!< LCD PAL201: I0 Position */
+#define LCD_PAL201_I0_Msk (0x01UL << LCD_PAL201_I0_Pos) /*!< LCD PAL201: I0 Mask */
+#define LCD_PAL201_R14_0_Pos 16 /*!< LCD PAL201: R14_0 Position */
+#define LCD_PAL201_R14_0_Msk (0x1fUL << LCD_PAL201_R14_0_Pos) /*!< LCD PAL201: R14_0 Mask */
+#define LCD_PAL201_G14_0_Pos 21 /*!< LCD PAL201: G14_0 Position */
+#define LCD_PAL201_G14_0_Msk (0x1fUL << LCD_PAL201_G14_0_Pos) /*!< LCD PAL201: G14_0 Mask */
+#define LCD_PAL201_B14_0_Pos 26 /*!< LCD PAL201: B14_0 Position */
+#define LCD_PAL201_B14_0_Msk (0x1fUL << LCD_PAL201_B14_0_Pos) /*!< LCD PAL201: B14_0 Mask */
+#define LCD_PAL201_I1_Pos 31 /*!< LCD PAL201: I1 Position */
+#define LCD_PAL201_I1_Msk (0x01UL << LCD_PAL201_I1_Pos) /*!< LCD PAL201: I1 Mask */
+
+// --------------------------------------- LCD_PAL202 -------------------------------------------
+#define LCD_PAL202_R04_0_Pos 0 /*!< LCD PAL202: R04_0 Position */
+#define LCD_PAL202_R04_0_Msk (0x1fUL << LCD_PAL202_R04_0_Pos) /*!< LCD PAL202: R04_0 Mask */
+#define LCD_PAL202_G04_0_Pos 5 /*!< LCD PAL202: G04_0 Position */
+#define LCD_PAL202_G04_0_Msk (0x1fUL << LCD_PAL202_G04_0_Pos) /*!< LCD PAL202: G04_0 Mask */
+#define LCD_PAL202_B04_0_Pos 10 /*!< LCD PAL202: B04_0 Position */
+#define LCD_PAL202_B04_0_Msk (0x1fUL << LCD_PAL202_B04_0_Pos) /*!< LCD PAL202: B04_0 Mask */
+#define LCD_PAL202_I0_Pos 15 /*!< LCD PAL202: I0 Position */
+#define LCD_PAL202_I0_Msk (0x01UL << LCD_PAL202_I0_Pos) /*!< LCD PAL202: I0 Mask */
+#define LCD_PAL202_R14_0_Pos 16 /*!< LCD PAL202: R14_0 Position */
+#define LCD_PAL202_R14_0_Msk (0x1fUL << LCD_PAL202_R14_0_Pos) /*!< LCD PAL202: R14_0 Mask */
+#define LCD_PAL202_G14_0_Pos 21 /*!< LCD PAL202: G14_0 Position */
+#define LCD_PAL202_G14_0_Msk (0x1fUL << LCD_PAL202_G14_0_Pos) /*!< LCD PAL202: G14_0 Mask */
+#define LCD_PAL202_B14_0_Pos 26 /*!< LCD PAL202: B14_0 Position */
+#define LCD_PAL202_B14_0_Msk (0x1fUL << LCD_PAL202_B14_0_Pos) /*!< LCD PAL202: B14_0 Mask */
+#define LCD_PAL202_I1_Pos 31 /*!< LCD PAL202: I1 Position */
+#define LCD_PAL202_I1_Msk (0x01UL << LCD_PAL202_I1_Pos) /*!< LCD PAL202: I1 Mask */
+
+// --------------------------------------- LCD_PAL203 -------------------------------------------
+#define LCD_PAL203_R04_0_Pos 0 /*!< LCD PAL203: R04_0 Position */
+#define LCD_PAL203_R04_0_Msk (0x1fUL << LCD_PAL203_R04_0_Pos) /*!< LCD PAL203: R04_0 Mask */
+#define LCD_PAL203_G04_0_Pos 5 /*!< LCD PAL203: G04_0 Position */
+#define LCD_PAL203_G04_0_Msk (0x1fUL << LCD_PAL203_G04_0_Pos) /*!< LCD PAL203: G04_0 Mask */
+#define LCD_PAL203_B04_0_Pos 10 /*!< LCD PAL203: B04_0 Position */
+#define LCD_PAL203_B04_0_Msk (0x1fUL << LCD_PAL203_B04_0_Pos) /*!< LCD PAL203: B04_0 Mask */
+#define LCD_PAL203_I0_Pos 15 /*!< LCD PAL203: I0 Position */
+#define LCD_PAL203_I0_Msk (0x01UL << LCD_PAL203_I0_Pos) /*!< LCD PAL203: I0 Mask */
+#define LCD_PAL203_R14_0_Pos 16 /*!< LCD PAL203: R14_0 Position */
+#define LCD_PAL203_R14_0_Msk (0x1fUL << LCD_PAL203_R14_0_Pos) /*!< LCD PAL203: R14_0 Mask */
+#define LCD_PAL203_G14_0_Pos 21 /*!< LCD PAL203: G14_0 Position */
+#define LCD_PAL203_G14_0_Msk (0x1fUL << LCD_PAL203_G14_0_Pos) /*!< LCD PAL203: G14_0 Mask */
+#define LCD_PAL203_B14_0_Pos 26 /*!< LCD PAL203: B14_0 Position */
+#define LCD_PAL203_B14_0_Msk (0x1fUL << LCD_PAL203_B14_0_Pos) /*!< LCD PAL203: B14_0 Mask */
+#define LCD_PAL203_I1_Pos 31 /*!< LCD PAL203: I1 Position */
+#define LCD_PAL203_I1_Msk (0x01UL << LCD_PAL203_I1_Pos) /*!< LCD PAL203: I1 Mask */
+
+// --------------------------------------- LCD_PAL204 -------------------------------------------
+#define LCD_PAL204_R04_0_Pos 0 /*!< LCD PAL204: R04_0 Position */
+#define LCD_PAL204_R04_0_Msk (0x1fUL << LCD_PAL204_R04_0_Pos) /*!< LCD PAL204: R04_0 Mask */
+#define LCD_PAL204_G04_0_Pos 5 /*!< LCD PAL204: G04_0 Position */
+#define LCD_PAL204_G04_0_Msk (0x1fUL << LCD_PAL204_G04_0_Pos) /*!< LCD PAL204: G04_0 Mask */
+#define LCD_PAL204_B04_0_Pos 10 /*!< LCD PAL204: B04_0 Position */
+#define LCD_PAL204_B04_0_Msk (0x1fUL << LCD_PAL204_B04_0_Pos) /*!< LCD PAL204: B04_0 Mask */
+#define LCD_PAL204_I0_Pos 15 /*!< LCD PAL204: I0 Position */
+#define LCD_PAL204_I0_Msk (0x01UL << LCD_PAL204_I0_Pos) /*!< LCD PAL204: I0 Mask */
+#define LCD_PAL204_R14_0_Pos 16 /*!< LCD PAL204: R14_0 Position */
+#define LCD_PAL204_R14_0_Msk (0x1fUL << LCD_PAL204_R14_0_Pos) /*!< LCD PAL204: R14_0 Mask */
+#define LCD_PAL204_G14_0_Pos 21 /*!< LCD PAL204: G14_0 Position */
+#define LCD_PAL204_G14_0_Msk (0x1fUL << LCD_PAL204_G14_0_Pos) /*!< LCD PAL204: G14_0 Mask */
+#define LCD_PAL204_B14_0_Pos 26 /*!< LCD PAL204: B14_0 Position */
+#define LCD_PAL204_B14_0_Msk (0x1fUL << LCD_PAL204_B14_0_Pos) /*!< LCD PAL204: B14_0 Mask */
+#define LCD_PAL204_I1_Pos 31 /*!< LCD PAL204: I1 Position */
+#define LCD_PAL204_I1_Msk (0x01UL << LCD_PAL204_I1_Pos) /*!< LCD PAL204: I1 Mask */
+
+// --------------------------------------- LCD_PAL205 -------------------------------------------
+#define LCD_PAL205_R04_0_Pos 0 /*!< LCD PAL205: R04_0 Position */
+#define LCD_PAL205_R04_0_Msk (0x1fUL << LCD_PAL205_R04_0_Pos) /*!< LCD PAL205: R04_0 Mask */
+#define LCD_PAL205_G04_0_Pos 5 /*!< LCD PAL205: G04_0 Position */
+#define LCD_PAL205_G04_0_Msk (0x1fUL << LCD_PAL205_G04_0_Pos) /*!< LCD PAL205: G04_0 Mask */
+#define LCD_PAL205_B04_0_Pos 10 /*!< LCD PAL205: B04_0 Position */
+#define LCD_PAL205_B04_0_Msk (0x1fUL << LCD_PAL205_B04_0_Pos) /*!< LCD PAL205: B04_0 Mask */
+#define LCD_PAL205_I0_Pos 15 /*!< LCD PAL205: I0 Position */
+#define LCD_PAL205_I0_Msk (0x01UL << LCD_PAL205_I0_Pos) /*!< LCD PAL205: I0 Mask */
+#define LCD_PAL205_R14_0_Pos 16 /*!< LCD PAL205: R14_0 Position */
+#define LCD_PAL205_R14_0_Msk (0x1fUL << LCD_PAL205_R14_0_Pos) /*!< LCD PAL205: R14_0 Mask */
+#define LCD_PAL205_G14_0_Pos 21 /*!< LCD PAL205: G14_0 Position */
+#define LCD_PAL205_G14_0_Msk (0x1fUL << LCD_PAL205_G14_0_Pos) /*!< LCD PAL205: G14_0 Mask */
+#define LCD_PAL205_B14_0_Pos 26 /*!< LCD PAL205: B14_0 Position */
+#define LCD_PAL205_B14_0_Msk (0x1fUL << LCD_PAL205_B14_0_Pos) /*!< LCD PAL205: B14_0 Mask */
+#define LCD_PAL205_I1_Pos 31 /*!< LCD PAL205: I1 Position */
+#define LCD_PAL205_I1_Msk (0x01UL << LCD_PAL205_I1_Pos) /*!< LCD PAL205: I1 Mask */
+
+// --------------------------------------- LCD_PAL206 -------------------------------------------
+#define LCD_PAL206_R04_0_Pos 0 /*!< LCD PAL206: R04_0 Position */
+#define LCD_PAL206_R04_0_Msk (0x1fUL << LCD_PAL206_R04_0_Pos) /*!< LCD PAL206: R04_0 Mask */
+#define LCD_PAL206_G04_0_Pos 5 /*!< LCD PAL206: G04_0 Position */
+#define LCD_PAL206_G04_0_Msk (0x1fUL << LCD_PAL206_G04_0_Pos) /*!< LCD PAL206: G04_0 Mask */
+#define LCD_PAL206_B04_0_Pos 10 /*!< LCD PAL206: B04_0 Position */
+#define LCD_PAL206_B04_0_Msk (0x1fUL << LCD_PAL206_B04_0_Pos) /*!< LCD PAL206: B04_0 Mask */
+#define LCD_PAL206_I0_Pos 15 /*!< LCD PAL206: I0 Position */
+#define LCD_PAL206_I0_Msk (0x01UL << LCD_PAL206_I0_Pos) /*!< LCD PAL206: I0 Mask */
+#define LCD_PAL206_R14_0_Pos 16 /*!< LCD PAL206: R14_0 Position */
+#define LCD_PAL206_R14_0_Msk (0x1fUL << LCD_PAL206_R14_0_Pos) /*!< LCD PAL206: R14_0 Mask */
+#define LCD_PAL206_G14_0_Pos 21 /*!< LCD PAL206: G14_0 Position */
+#define LCD_PAL206_G14_0_Msk (0x1fUL << LCD_PAL206_G14_0_Pos) /*!< LCD PAL206: G14_0 Mask */
+#define LCD_PAL206_B14_0_Pos 26 /*!< LCD PAL206: B14_0 Position */
+#define LCD_PAL206_B14_0_Msk (0x1fUL << LCD_PAL206_B14_0_Pos) /*!< LCD PAL206: B14_0 Mask */
+#define LCD_PAL206_I1_Pos 31 /*!< LCD PAL206: I1 Position */
+#define LCD_PAL206_I1_Msk (0x01UL << LCD_PAL206_I1_Pos) /*!< LCD PAL206: I1 Mask */
+
+// --------------------------------------- LCD_PAL207 -------------------------------------------
+#define LCD_PAL207_R04_0_Pos 0 /*!< LCD PAL207: R04_0 Position */
+#define LCD_PAL207_R04_0_Msk (0x1fUL << LCD_PAL207_R04_0_Pos) /*!< LCD PAL207: R04_0 Mask */
+#define LCD_PAL207_G04_0_Pos 5 /*!< LCD PAL207: G04_0 Position */
+#define LCD_PAL207_G04_0_Msk (0x1fUL << LCD_PAL207_G04_0_Pos) /*!< LCD PAL207: G04_0 Mask */
+#define LCD_PAL207_B04_0_Pos 10 /*!< LCD PAL207: B04_0 Position */
+#define LCD_PAL207_B04_0_Msk (0x1fUL << LCD_PAL207_B04_0_Pos) /*!< LCD PAL207: B04_0 Mask */
+#define LCD_PAL207_I0_Pos 15 /*!< LCD PAL207: I0 Position */
+#define LCD_PAL207_I0_Msk (0x01UL << LCD_PAL207_I0_Pos) /*!< LCD PAL207: I0 Mask */
+#define LCD_PAL207_R14_0_Pos 16 /*!< LCD PAL207: R14_0 Position */
+#define LCD_PAL207_R14_0_Msk (0x1fUL << LCD_PAL207_R14_0_Pos) /*!< LCD PAL207: R14_0 Mask */
+#define LCD_PAL207_G14_0_Pos 21 /*!< LCD PAL207: G14_0 Position */
+#define LCD_PAL207_G14_0_Msk (0x1fUL << LCD_PAL207_G14_0_Pos) /*!< LCD PAL207: G14_0 Mask */
+#define LCD_PAL207_B14_0_Pos 26 /*!< LCD PAL207: B14_0 Position */
+#define LCD_PAL207_B14_0_Msk (0x1fUL << LCD_PAL207_B14_0_Pos) /*!< LCD PAL207: B14_0 Mask */
+#define LCD_PAL207_I1_Pos 31 /*!< LCD PAL207: I1 Position */
+#define LCD_PAL207_I1_Msk (0x01UL << LCD_PAL207_I1_Pos) /*!< LCD PAL207: I1 Mask */
+
+// --------------------------------------- LCD_PAL208 -------------------------------------------
+#define LCD_PAL208_R04_0_Pos 0 /*!< LCD PAL208: R04_0 Position */
+#define LCD_PAL208_R04_0_Msk (0x1fUL << LCD_PAL208_R04_0_Pos) /*!< LCD PAL208: R04_0 Mask */
+#define LCD_PAL208_G04_0_Pos 5 /*!< LCD PAL208: G04_0 Position */
+#define LCD_PAL208_G04_0_Msk (0x1fUL << LCD_PAL208_G04_0_Pos) /*!< LCD PAL208: G04_0 Mask */
+#define LCD_PAL208_B04_0_Pos 10 /*!< LCD PAL208: B04_0 Position */
+#define LCD_PAL208_B04_0_Msk (0x1fUL << LCD_PAL208_B04_0_Pos) /*!< LCD PAL208: B04_0 Mask */
+#define LCD_PAL208_I0_Pos 15 /*!< LCD PAL208: I0 Position */
+#define LCD_PAL208_I0_Msk (0x01UL << LCD_PAL208_I0_Pos) /*!< LCD PAL208: I0 Mask */
+#define LCD_PAL208_R14_0_Pos 16 /*!< LCD PAL208: R14_0 Position */
+#define LCD_PAL208_R14_0_Msk (0x1fUL << LCD_PAL208_R14_0_Pos) /*!< LCD PAL208: R14_0 Mask */
+#define LCD_PAL208_G14_0_Pos 21 /*!< LCD PAL208: G14_0 Position */
+#define LCD_PAL208_G14_0_Msk (0x1fUL << LCD_PAL208_G14_0_Pos) /*!< LCD PAL208: G14_0 Mask */
+#define LCD_PAL208_B14_0_Pos 26 /*!< LCD PAL208: B14_0 Position */
+#define LCD_PAL208_B14_0_Msk (0x1fUL << LCD_PAL208_B14_0_Pos) /*!< LCD PAL208: B14_0 Mask */
+#define LCD_PAL208_I1_Pos 31 /*!< LCD PAL208: I1 Position */
+#define LCD_PAL208_I1_Msk (0x01UL << LCD_PAL208_I1_Pos) /*!< LCD PAL208: I1 Mask */
+
+// --------------------------------------- LCD_PAL209 -------------------------------------------
+#define LCD_PAL209_R04_0_Pos 0 /*!< LCD PAL209: R04_0 Position */
+#define LCD_PAL209_R04_0_Msk (0x1fUL << LCD_PAL209_R04_0_Pos) /*!< LCD PAL209: R04_0 Mask */
+#define LCD_PAL209_G04_0_Pos 5 /*!< LCD PAL209: G04_0 Position */
+#define LCD_PAL209_G04_0_Msk (0x1fUL << LCD_PAL209_G04_0_Pos) /*!< LCD PAL209: G04_0 Mask */
+#define LCD_PAL209_B04_0_Pos 10 /*!< LCD PAL209: B04_0 Position */
+#define LCD_PAL209_B04_0_Msk (0x1fUL << LCD_PAL209_B04_0_Pos) /*!< LCD PAL209: B04_0 Mask */
+#define LCD_PAL209_I0_Pos 15 /*!< LCD PAL209: I0 Position */
+#define LCD_PAL209_I0_Msk (0x01UL << LCD_PAL209_I0_Pos) /*!< LCD PAL209: I0 Mask */
+#define LCD_PAL209_R14_0_Pos 16 /*!< LCD PAL209: R14_0 Position */
+#define LCD_PAL209_R14_0_Msk (0x1fUL << LCD_PAL209_R14_0_Pos) /*!< LCD PAL209: R14_0 Mask */
+#define LCD_PAL209_G14_0_Pos 21 /*!< LCD PAL209: G14_0 Position */
+#define LCD_PAL209_G14_0_Msk (0x1fUL << LCD_PAL209_G14_0_Pos) /*!< LCD PAL209: G14_0 Mask */
+#define LCD_PAL209_B14_0_Pos 26 /*!< LCD PAL209: B14_0 Position */
+#define LCD_PAL209_B14_0_Msk (0x1fUL << LCD_PAL209_B14_0_Pos) /*!< LCD PAL209: B14_0 Mask */
+#define LCD_PAL209_I1_Pos 31 /*!< LCD PAL209: I1 Position */
+#define LCD_PAL209_I1_Msk (0x01UL << LCD_PAL209_I1_Pos) /*!< LCD PAL209: I1 Mask */
+
+// --------------------------------------- LCD_PAL210 -------------------------------------------
+#define LCD_PAL210_R04_0_Pos 0 /*!< LCD PAL210: R04_0 Position */
+#define LCD_PAL210_R04_0_Msk (0x1fUL << LCD_PAL210_R04_0_Pos) /*!< LCD PAL210: R04_0 Mask */
+#define LCD_PAL210_G04_0_Pos 5 /*!< LCD PAL210: G04_0 Position */
+#define LCD_PAL210_G04_0_Msk (0x1fUL << LCD_PAL210_G04_0_Pos) /*!< LCD PAL210: G04_0 Mask */
+#define LCD_PAL210_B04_0_Pos 10 /*!< LCD PAL210: B04_0 Position */
+#define LCD_PAL210_B04_0_Msk (0x1fUL << LCD_PAL210_B04_0_Pos) /*!< LCD PAL210: B04_0 Mask */
+#define LCD_PAL210_I0_Pos 15 /*!< LCD PAL210: I0 Position */
+#define LCD_PAL210_I0_Msk (0x01UL << LCD_PAL210_I0_Pos) /*!< LCD PAL210: I0 Mask */
+#define LCD_PAL210_R14_0_Pos 16 /*!< LCD PAL210: R14_0 Position */
+#define LCD_PAL210_R14_0_Msk (0x1fUL << LCD_PAL210_R14_0_Pos) /*!< LCD PAL210: R14_0 Mask */
+#define LCD_PAL210_G14_0_Pos 21 /*!< LCD PAL210: G14_0 Position */
+#define LCD_PAL210_G14_0_Msk (0x1fUL << LCD_PAL210_G14_0_Pos) /*!< LCD PAL210: G14_0 Mask */
+#define LCD_PAL210_B14_0_Pos 26 /*!< LCD PAL210: B14_0 Position */
+#define LCD_PAL210_B14_0_Msk (0x1fUL << LCD_PAL210_B14_0_Pos) /*!< LCD PAL210: B14_0 Mask */
+#define LCD_PAL210_I1_Pos 31 /*!< LCD PAL210: I1 Position */
+#define LCD_PAL210_I1_Msk (0x01UL << LCD_PAL210_I1_Pos) /*!< LCD PAL210: I1 Mask */
+
+// --------------------------------------- LCD_PAL211 -------------------------------------------
+#define LCD_PAL211_R04_0_Pos 0 /*!< LCD PAL211: R04_0 Position */
+#define LCD_PAL211_R04_0_Msk (0x1fUL << LCD_PAL211_R04_0_Pos) /*!< LCD PAL211: R04_0 Mask */
+#define LCD_PAL211_G04_0_Pos 5 /*!< LCD PAL211: G04_0 Position */
+#define LCD_PAL211_G04_0_Msk (0x1fUL << LCD_PAL211_G04_0_Pos) /*!< LCD PAL211: G04_0 Mask */
+#define LCD_PAL211_B04_0_Pos 10 /*!< LCD PAL211: B04_0 Position */
+#define LCD_PAL211_B04_0_Msk (0x1fUL << LCD_PAL211_B04_0_Pos) /*!< LCD PAL211: B04_0 Mask */
+#define LCD_PAL211_I0_Pos 15 /*!< LCD PAL211: I0 Position */
+#define LCD_PAL211_I0_Msk (0x01UL << LCD_PAL211_I0_Pos) /*!< LCD PAL211: I0 Mask */
+#define LCD_PAL211_R14_0_Pos 16 /*!< LCD PAL211: R14_0 Position */
+#define LCD_PAL211_R14_0_Msk (0x1fUL << LCD_PAL211_R14_0_Pos) /*!< LCD PAL211: R14_0 Mask */
+#define LCD_PAL211_G14_0_Pos 21 /*!< LCD PAL211: G14_0 Position */
+#define LCD_PAL211_G14_0_Msk (0x1fUL << LCD_PAL211_G14_0_Pos) /*!< LCD PAL211: G14_0 Mask */
+#define LCD_PAL211_B14_0_Pos 26 /*!< LCD PAL211: B14_0 Position */
+#define LCD_PAL211_B14_0_Msk (0x1fUL << LCD_PAL211_B14_0_Pos) /*!< LCD PAL211: B14_0 Mask */
+#define LCD_PAL211_I1_Pos 31 /*!< LCD PAL211: I1 Position */
+#define LCD_PAL211_I1_Msk (0x01UL << LCD_PAL211_I1_Pos) /*!< LCD PAL211: I1 Mask */
+
+// --------------------------------------- LCD_PAL212 -------------------------------------------
+#define LCD_PAL212_R04_0_Pos 0 /*!< LCD PAL212: R04_0 Position */
+#define LCD_PAL212_R04_0_Msk (0x1fUL << LCD_PAL212_R04_0_Pos) /*!< LCD PAL212: R04_0 Mask */
+#define LCD_PAL212_G04_0_Pos 5 /*!< LCD PAL212: G04_0 Position */
+#define LCD_PAL212_G04_0_Msk (0x1fUL << LCD_PAL212_G04_0_Pos) /*!< LCD PAL212: G04_0 Mask */
+#define LCD_PAL212_B04_0_Pos 10 /*!< LCD PAL212: B04_0 Position */
+#define LCD_PAL212_B04_0_Msk (0x1fUL << LCD_PAL212_B04_0_Pos) /*!< LCD PAL212: B04_0 Mask */
+#define LCD_PAL212_I0_Pos 15 /*!< LCD PAL212: I0 Position */
+#define LCD_PAL212_I0_Msk (0x01UL << LCD_PAL212_I0_Pos) /*!< LCD PAL212: I0 Mask */
+#define LCD_PAL212_R14_0_Pos 16 /*!< LCD PAL212: R14_0 Position */
+#define LCD_PAL212_R14_0_Msk (0x1fUL << LCD_PAL212_R14_0_Pos) /*!< LCD PAL212: R14_0 Mask */
+#define LCD_PAL212_G14_0_Pos 21 /*!< LCD PAL212: G14_0 Position */
+#define LCD_PAL212_G14_0_Msk (0x1fUL << LCD_PAL212_G14_0_Pos) /*!< LCD PAL212: G14_0 Mask */
+#define LCD_PAL212_B14_0_Pos 26 /*!< LCD PAL212: B14_0 Position */
+#define LCD_PAL212_B14_0_Msk (0x1fUL << LCD_PAL212_B14_0_Pos) /*!< LCD PAL212: B14_0 Mask */
+#define LCD_PAL212_I1_Pos 31 /*!< LCD PAL212: I1 Position */
+#define LCD_PAL212_I1_Msk (0x01UL << LCD_PAL212_I1_Pos) /*!< LCD PAL212: I1 Mask */
+
+// --------------------------------------- LCD_PAL213 -------------------------------------------
+#define LCD_PAL213_R04_0_Pos 0 /*!< LCD PAL213: R04_0 Position */
+#define LCD_PAL213_R04_0_Msk (0x1fUL << LCD_PAL213_R04_0_Pos) /*!< LCD PAL213: R04_0 Mask */
+#define LCD_PAL213_G04_0_Pos 5 /*!< LCD PAL213: G04_0 Position */
+#define LCD_PAL213_G04_0_Msk (0x1fUL << LCD_PAL213_G04_0_Pos) /*!< LCD PAL213: G04_0 Mask */
+#define LCD_PAL213_B04_0_Pos 10 /*!< LCD PAL213: B04_0 Position */
+#define LCD_PAL213_B04_0_Msk (0x1fUL << LCD_PAL213_B04_0_Pos) /*!< LCD PAL213: B04_0 Mask */
+#define LCD_PAL213_I0_Pos 15 /*!< LCD PAL213: I0 Position */
+#define LCD_PAL213_I0_Msk (0x01UL << LCD_PAL213_I0_Pos) /*!< LCD PAL213: I0 Mask */
+#define LCD_PAL213_R14_0_Pos 16 /*!< LCD PAL213: R14_0 Position */
+#define LCD_PAL213_R14_0_Msk (0x1fUL << LCD_PAL213_R14_0_Pos) /*!< LCD PAL213: R14_0 Mask */
+#define LCD_PAL213_G14_0_Pos 21 /*!< LCD PAL213: G14_0 Position */
+#define LCD_PAL213_G14_0_Msk (0x1fUL << LCD_PAL213_G14_0_Pos) /*!< LCD PAL213: G14_0 Mask */
+#define LCD_PAL213_B14_0_Pos 26 /*!< LCD PAL213: B14_0 Position */
+#define LCD_PAL213_B14_0_Msk (0x1fUL << LCD_PAL213_B14_0_Pos) /*!< LCD PAL213: B14_0 Mask */
+#define LCD_PAL213_I1_Pos 31 /*!< LCD PAL213: I1 Position */
+#define LCD_PAL213_I1_Msk (0x01UL << LCD_PAL213_I1_Pos) /*!< LCD PAL213: I1 Mask */
+
+// --------------------------------------- LCD_PAL214 -------------------------------------------
+#define LCD_PAL214_R04_0_Pos 0 /*!< LCD PAL214: R04_0 Position */
+#define LCD_PAL214_R04_0_Msk (0x1fUL << LCD_PAL214_R04_0_Pos) /*!< LCD PAL214: R04_0 Mask */
+#define LCD_PAL214_G04_0_Pos 5 /*!< LCD PAL214: G04_0 Position */
+#define LCD_PAL214_G04_0_Msk (0x1fUL << LCD_PAL214_G04_0_Pos) /*!< LCD PAL214: G04_0 Mask */
+#define LCD_PAL214_B04_0_Pos 10 /*!< LCD PAL214: B04_0 Position */
+#define LCD_PAL214_B04_0_Msk (0x1fUL << LCD_PAL214_B04_0_Pos) /*!< LCD PAL214: B04_0 Mask */
+#define LCD_PAL214_I0_Pos 15 /*!< LCD PAL214: I0 Position */
+#define LCD_PAL214_I0_Msk (0x01UL << LCD_PAL214_I0_Pos) /*!< LCD PAL214: I0 Mask */
+#define LCD_PAL214_R14_0_Pos 16 /*!< LCD PAL214: R14_0 Position */
+#define LCD_PAL214_R14_0_Msk (0x1fUL << LCD_PAL214_R14_0_Pos) /*!< LCD PAL214: R14_0 Mask */
+#define LCD_PAL214_G14_0_Pos 21 /*!< LCD PAL214: G14_0 Position */
+#define LCD_PAL214_G14_0_Msk (0x1fUL << LCD_PAL214_G14_0_Pos) /*!< LCD PAL214: G14_0 Mask */
+#define LCD_PAL214_B14_0_Pos 26 /*!< LCD PAL214: B14_0 Position */
+#define LCD_PAL214_B14_0_Msk (0x1fUL << LCD_PAL214_B14_0_Pos) /*!< LCD PAL214: B14_0 Mask */
+#define LCD_PAL214_I1_Pos 31 /*!< LCD PAL214: I1 Position */
+#define LCD_PAL214_I1_Msk (0x01UL << LCD_PAL214_I1_Pos) /*!< LCD PAL214: I1 Mask */
+
+// --------------------------------------- LCD_PAL215 -------------------------------------------
+#define LCD_PAL215_R04_0_Pos 0 /*!< LCD PAL215: R04_0 Position */
+#define LCD_PAL215_R04_0_Msk (0x1fUL << LCD_PAL215_R04_0_Pos) /*!< LCD PAL215: R04_0 Mask */
+#define LCD_PAL215_G04_0_Pos 5 /*!< LCD PAL215: G04_0 Position */
+#define LCD_PAL215_G04_0_Msk (0x1fUL << LCD_PAL215_G04_0_Pos) /*!< LCD PAL215: G04_0 Mask */
+#define LCD_PAL215_B04_0_Pos 10 /*!< LCD PAL215: B04_0 Position */
+#define LCD_PAL215_B04_0_Msk (0x1fUL << LCD_PAL215_B04_0_Pos) /*!< LCD PAL215: B04_0 Mask */
+#define LCD_PAL215_I0_Pos 15 /*!< LCD PAL215: I0 Position */
+#define LCD_PAL215_I0_Msk (0x01UL << LCD_PAL215_I0_Pos) /*!< LCD PAL215: I0 Mask */
+#define LCD_PAL215_R14_0_Pos 16 /*!< LCD PAL215: R14_0 Position */
+#define LCD_PAL215_R14_0_Msk (0x1fUL << LCD_PAL215_R14_0_Pos) /*!< LCD PAL215: R14_0 Mask */
+#define LCD_PAL215_G14_0_Pos 21 /*!< LCD PAL215: G14_0 Position */
+#define LCD_PAL215_G14_0_Msk (0x1fUL << LCD_PAL215_G14_0_Pos) /*!< LCD PAL215: G14_0 Mask */
+#define LCD_PAL215_B14_0_Pos 26 /*!< LCD PAL215: B14_0 Position */
+#define LCD_PAL215_B14_0_Msk (0x1fUL << LCD_PAL215_B14_0_Pos) /*!< LCD PAL215: B14_0 Mask */
+#define LCD_PAL215_I1_Pos 31 /*!< LCD PAL215: I1 Position */
+#define LCD_PAL215_I1_Msk (0x01UL << LCD_PAL215_I1_Pos) /*!< LCD PAL215: I1 Mask */
+
+// --------------------------------------- LCD_PAL216 -------------------------------------------
+#define LCD_PAL216_R04_0_Pos 0 /*!< LCD PAL216: R04_0 Position */
+#define LCD_PAL216_R04_0_Msk (0x1fUL << LCD_PAL216_R04_0_Pos) /*!< LCD PAL216: R04_0 Mask */
+#define LCD_PAL216_G04_0_Pos 5 /*!< LCD PAL216: G04_0 Position */
+#define LCD_PAL216_G04_0_Msk (0x1fUL << LCD_PAL216_G04_0_Pos) /*!< LCD PAL216: G04_0 Mask */
+#define LCD_PAL216_B04_0_Pos 10 /*!< LCD PAL216: B04_0 Position */
+#define LCD_PAL216_B04_0_Msk (0x1fUL << LCD_PAL216_B04_0_Pos) /*!< LCD PAL216: B04_0 Mask */
+#define LCD_PAL216_I0_Pos 15 /*!< LCD PAL216: I0 Position */
+#define LCD_PAL216_I0_Msk (0x01UL << LCD_PAL216_I0_Pos) /*!< LCD PAL216: I0 Mask */
+#define LCD_PAL216_R14_0_Pos 16 /*!< LCD PAL216: R14_0 Position */
+#define LCD_PAL216_R14_0_Msk (0x1fUL << LCD_PAL216_R14_0_Pos) /*!< LCD PAL216: R14_0 Mask */
+#define LCD_PAL216_G14_0_Pos 21 /*!< LCD PAL216: G14_0 Position */
+#define LCD_PAL216_G14_0_Msk (0x1fUL << LCD_PAL216_G14_0_Pos) /*!< LCD PAL216: G14_0 Mask */
+#define LCD_PAL216_B14_0_Pos 26 /*!< LCD PAL216: B14_0 Position */
+#define LCD_PAL216_B14_0_Msk (0x1fUL << LCD_PAL216_B14_0_Pos) /*!< LCD PAL216: B14_0 Mask */
+#define LCD_PAL216_I1_Pos 31 /*!< LCD PAL216: I1 Position */
+#define LCD_PAL216_I1_Msk (0x01UL << LCD_PAL216_I1_Pos) /*!< LCD PAL216: I1 Mask */
+
+// --------------------------------------- LCD_PAL217 -------------------------------------------
+#define LCD_PAL217_R04_0_Pos 0 /*!< LCD PAL217: R04_0 Position */
+#define LCD_PAL217_R04_0_Msk (0x1fUL << LCD_PAL217_R04_0_Pos) /*!< LCD PAL217: R04_0 Mask */
+#define LCD_PAL217_G04_0_Pos 5 /*!< LCD PAL217: G04_0 Position */
+#define LCD_PAL217_G04_0_Msk (0x1fUL << LCD_PAL217_G04_0_Pos) /*!< LCD PAL217: G04_0 Mask */
+#define LCD_PAL217_B04_0_Pos 10 /*!< LCD PAL217: B04_0 Position */
+#define LCD_PAL217_B04_0_Msk (0x1fUL << LCD_PAL217_B04_0_Pos) /*!< LCD PAL217: B04_0 Mask */
+#define LCD_PAL217_I0_Pos 15 /*!< LCD PAL217: I0 Position */
+#define LCD_PAL217_I0_Msk (0x01UL << LCD_PAL217_I0_Pos) /*!< LCD PAL217: I0 Mask */
+#define LCD_PAL217_R14_0_Pos 16 /*!< LCD PAL217: R14_0 Position */
+#define LCD_PAL217_R14_0_Msk (0x1fUL << LCD_PAL217_R14_0_Pos) /*!< LCD PAL217: R14_0 Mask */
+#define LCD_PAL217_G14_0_Pos 21 /*!< LCD PAL217: G14_0 Position */
+#define LCD_PAL217_G14_0_Msk (0x1fUL << LCD_PAL217_G14_0_Pos) /*!< LCD PAL217: G14_0 Mask */
+#define LCD_PAL217_B14_0_Pos 26 /*!< LCD PAL217: B14_0 Position */
+#define LCD_PAL217_B14_0_Msk (0x1fUL << LCD_PAL217_B14_0_Pos) /*!< LCD PAL217: B14_0 Mask */
+#define LCD_PAL217_I1_Pos 31 /*!< LCD PAL217: I1 Position */
+#define LCD_PAL217_I1_Msk (0x01UL << LCD_PAL217_I1_Pos) /*!< LCD PAL217: I1 Mask */
+
+// --------------------------------------- LCD_PAL218 -------------------------------------------
+#define LCD_PAL218_R04_0_Pos 0 /*!< LCD PAL218: R04_0 Position */
+#define LCD_PAL218_R04_0_Msk (0x1fUL << LCD_PAL218_R04_0_Pos) /*!< LCD PAL218: R04_0 Mask */
+#define LCD_PAL218_G04_0_Pos 5 /*!< LCD PAL218: G04_0 Position */
+#define LCD_PAL218_G04_0_Msk (0x1fUL << LCD_PAL218_G04_0_Pos) /*!< LCD PAL218: G04_0 Mask */
+#define LCD_PAL218_B04_0_Pos 10 /*!< LCD PAL218: B04_0 Position */
+#define LCD_PAL218_B04_0_Msk (0x1fUL << LCD_PAL218_B04_0_Pos) /*!< LCD PAL218: B04_0 Mask */
+#define LCD_PAL218_I0_Pos 15 /*!< LCD PAL218: I0 Position */
+#define LCD_PAL218_I0_Msk (0x01UL << LCD_PAL218_I0_Pos) /*!< LCD PAL218: I0 Mask */
+#define LCD_PAL218_R14_0_Pos 16 /*!< LCD PAL218: R14_0 Position */
+#define LCD_PAL218_R14_0_Msk (0x1fUL << LCD_PAL218_R14_0_Pos) /*!< LCD PAL218: R14_0 Mask */
+#define LCD_PAL218_G14_0_Pos 21 /*!< LCD PAL218: G14_0 Position */
+#define LCD_PAL218_G14_0_Msk (0x1fUL << LCD_PAL218_G14_0_Pos) /*!< LCD PAL218: G14_0 Mask */
+#define LCD_PAL218_B14_0_Pos 26 /*!< LCD PAL218: B14_0 Position */
+#define LCD_PAL218_B14_0_Msk (0x1fUL << LCD_PAL218_B14_0_Pos) /*!< LCD PAL218: B14_0 Mask */
+#define LCD_PAL218_I1_Pos 31 /*!< LCD PAL218: I1 Position */
+#define LCD_PAL218_I1_Msk (0x01UL << LCD_PAL218_I1_Pos) /*!< LCD PAL218: I1 Mask */
+
+// --------------------------------------- LCD_PAL219 -------------------------------------------
+#define LCD_PAL219_R04_0_Pos 0 /*!< LCD PAL219: R04_0 Position */
+#define LCD_PAL219_R04_0_Msk (0x1fUL << LCD_PAL219_R04_0_Pos) /*!< LCD PAL219: R04_0 Mask */
+#define LCD_PAL219_G04_0_Pos 5 /*!< LCD PAL219: G04_0 Position */
+#define LCD_PAL219_G04_0_Msk (0x1fUL << LCD_PAL219_G04_0_Pos) /*!< LCD PAL219: G04_0 Mask */
+#define LCD_PAL219_B04_0_Pos 10 /*!< LCD PAL219: B04_0 Position */
+#define LCD_PAL219_B04_0_Msk (0x1fUL << LCD_PAL219_B04_0_Pos) /*!< LCD PAL219: B04_0 Mask */
+#define LCD_PAL219_I0_Pos 15 /*!< LCD PAL219: I0 Position */
+#define LCD_PAL219_I0_Msk (0x01UL << LCD_PAL219_I0_Pos) /*!< LCD PAL219: I0 Mask */
+#define LCD_PAL219_R14_0_Pos 16 /*!< LCD PAL219: R14_0 Position */
+#define LCD_PAL219_R14_0_Msk (0x1fUL << LCD_PAL219_R14_0_Pos) /*!< LCD PAL219: R14_0 Mask */
+#define LCD_PAL219_G14_0_Pos 21 /*!< LCD PAL219: G14_0 Position */
+#define LCD_PAL219_G14_0_Msk (0x1fUL << LCD_PAL219_G14_0_Pos) /*!< LCD PAL219: G14_0 Mask */
+#define LCD_PAL219_B14_0_Pos 26 /*!< LCD PAL219: B14_0 Position */
+#define LCD_PAL219_B14_0_Msk (0x1fUL << LCD_PAL219_B14_0_Pos) /*!< LCD PAL219: B14_0 Mask */
+#define LCD_PAL219_I1_Pos 31 /*!< LCD PAL219: I1 Position */
+#define LCD_PAL219_I1_Msk (0x01UL << LCD_PAL219_I1_Pos) /*!< LCD PAL219: I1 Mask */
+
+// --------------------------------------- LCD_PAL220 -------------------------------------------
+#define LCD_PAL220_R04_0_Pos 0 /*!< LCD PAL220: R04_0 Position */
+#define LCD_PAL220_R04_0_Msk (0x1fUL << LCD_PAL220_R04_0_Pos) /*!< LCD PAL220: R04_0 Mask */
+#define LCD_PAL220_G04_0_Pos 5 /*!< LCD PAL220: G04_0 Position */
+#define LCD_PAL220_G04_0_Msk (0x1fUL << LCD_PAL220_G04_0_Pos) /*!< LCD PAL220: G04_0 Mask */
+#define LCD_PAL220_B04_0_Pos 10 /*!< LCD PAL220: B04_0 Position */
+#define LCD_PAL220_B04_0_Msk (0x1fUL << LCD_PAL220_B04_0_Pos) /*!< LCD PAL220: B04_0 Mask */
+#define LCD_PAL220_I0_Pos 15 /*!< LCD PAL220: I0 Position */
+#define LCD_PAL220_I0_Msk (0x01UL << LCD_PAL220_I0_Pos) /*!< LCD PAL220: I0 Mask */
+#define LCD_PAL220_R14_0_Pos 16 /*!< LCD PAL220: R14_0 Position */
+#define LCD_PAL220_R14_0_Msk (0x1fUL << LCD_PAL220_R14_0_Pos) /*!< LCD PAL220: R14_0 Mask */
+#define LCD_PAL220_G14_0_Pos 21 /*!< LCD PAL220: G14_0 Position */
+#define LCD_PAL220_G14_0_Msk (0x1fUL << LCD_PAL220_G14_0_Pos) /*!< LCD PAL220: G14_0 Mask */
+#define LCD_PAL220_B14_0_Pos 26 /*!< LCD PAL220: B14_0 Position */
+#define LCD_PAL220_B14_0_Msk (0x1fUL << LCD_PAL220_B14_0_Pos) /*!< LCD PAL220: B14_0 Mask */
+#define LCD_PAL220_I1_Pos 31 /*!< LCD PAL220: I1 Position */
+#define LCD_PAL220_I1_Msk (0x01UL << LCD_PAL220_I1_Pos) /*!< LCD PAL220: I1 Mask */
+
+// --------------------------------------- LCD_PAL221 -------------------------------------------
+#define LCD_PAL221_R04_0_Pos 0 /*!< LCD PAL221: R04_0 Position */
+#define LCD_PAL221_R04_0_Msk (0x1fUL << LCD_PAL221_R04_0_Pos) /*!< LCD PAL221: R04_0 Mask */
+#define LCD_PAL221_G04_0_Pos 5 /*!< LCD PAL221: G04_0 Position */
+#define LCD_PAL221_G04_0_Msk (0x1fUL << LCD_PAL221_G04_0_Pos) /*!< LCD PAL221: G04_0 Mask */
+#define LCD_PAL221_B04_0_Pos 10 /*!< LCD PAL221: B04_0 Position */
+#define LCD_PAL221_B04_0_Msk (0x1fUL << LCD_PAL221_B04_0_Pos) /*!< LCD PAL221: B04_0 Mask */
+#define LCD_PAL221_I0_Pos 15 /*!< LCD PAL221: I0 Position */
+#define LCD_PAL221_I0_Msk (0x01UL << LCD_PAL221_I0_Pos) /*!< LCD PAL221: I0 Mask */
+#define LCD_PAL221_R14_0_Pos 16 /*!< LCD PAL221: R14_0 Position */
+#define LCD_PAL221_R14_0_Msk (0x1fUL << LCD_PAL221_R14_0_Pos) /*!< LCD PAL221: R14_0 Mask */
+#define LCD_PAL221_G14_0_Pos 21 /*!< LCD PAL221: G14_0 Position */
+#define LCD_PAL221_G14_0_Msk (0x1fUL << LCD_PAL221_G14_0_Pos) /*!< LCD PAL221: G14_0 Mask */
+#define LCD_PAL221_B14_0_Pos 26 /*!< LCD PAL221: B14_0 Position */
+#define LCD_PAL221_B14_0_Msk (0x1fUL << LCD_PAL221_B14_0_Pos) /*!< LCD PAL221: B14_0 Mask */
+#define LCD_PAL221_I1_Pos 31 /*!< LCD PAL221: I1 Position */
+#define LCD_PAL221_I1_Msk (0x01UL << LCD_PAL221_I1_Pos) /*!< LCD PAL221: I1 Mask */
+
+// --------------------------------------- LCD_PAL222 -------------------------------------------
+#define LCD_PAL222_R04_0_Pos 0 /*!< LCD PAL222: R04_0 Position */
+#define LCD_PAL222_R04_0_Msk (0x1fUL << LCD_PAL222_R04_0_Pos) /*!< LCD PAL222: R04_0 Mask */
+#define LCD_PAL222_G04_0_Pos 5 /*!< LCD PAL222: G04_0 Position */
+#define LCD_PAL222_G04_0_Msk (0x1fUL << LCD_PAL222_G04_0_Pos) /*!< LCD PAL222: G04_0 Mask */
+#define LCD_PAL222_B04_0_Pos 10 /*!< LCD PAL222: B04_0 Position */
+#define LCD_PAL222_B04_0_Msk (0x1fUL << LCD_PAL222_B04_0_Pos) /*!< LCD PAL222: B04_0 Mask */
+#define LCD_PAL222_I0_Pos 15 /*!< LCD PAL222: I0 Position */
+#define LCD_PAL222_I0_Msk (0x01UL << LCD_PAL222_I0_Pos) /*!< LCD PAL222: I0 Mask */
+#define LCD_PAL222_R14_0_Pos 16 /*!< LCD PAL222: R14_0 Position */
+#define LCD_PAL222_R14_0_Msk (0x1fUL << LCD_PAL222_R14_0_Pos) /*!< LCD PAL222: R14_0 Mask */
+#define LCD_PAL222_G14_0_Pos 21 /*!< LCD PAL222: G14_0 Position */
+#define LCD_PAL222_G14_0_Msk (0x1fUL << LCD_PAL222_G14_0_Pos) /*!< LCD PAL222: G14_0 Mask */
+#define LCD_PAL222_B14_0_Pos 26 /*!< LCD PAL222: B14_0 Position */
+#define LCD_PAL222_B14_0_Msk (0x1fUL << LCD_PAL222_B14_0_Pos) /*!< LCD PAL222: B14_0 Mask */
+#define LCD_PAL222_I1_Pos 31 /*!< LCD PAL222: I1 Position */
+#define LCD_PAL222_I1_Msk (0x01UL << LCD_PAL222_I1_Pos) /*!< LCD PAL222: I1 Mask */
+
+// --------------------------------------- LCD_PAL223 -------------------------------------------
+#define LCD_PAL223_R04_0_Pos 0 /*!< LCD PAL223: R04_0 Position */
+#define LCD_PAL223_R04_0_Msk (0x1fUL << LCD_PAL223_R04_0_Pos) /*!< LCD PAL223: R04_0 Mask */
+#define LCD_PAL223_G04_0_Pos 5 /*!< LCD PAL223: G04_0 Position */
+#define LCD_PAL223_G04_0_Msk (0x1fUL << LCD_PAL223_G04_0_Pos) /*!< LCD PAL223: G04_0 Mask */
+#define LCD_PAL223_B04_0_Pos 10 /*!< LCD PAL223: B04_0 Position */
+#define LCD_PAL223_B04_0_Msk (0x1fUL << LCD_PAL223_B04_0_Pos) /*!< LCD PAL223: B04_0 Mask */
+#define LCD_PAL223_I0_Pos 15 /*!< LCD PAL223: I0 Position */
+#define LCD_PAL223_I0_Msk (0x01UL << LCD_PAL223_I0_Pos) /*!< LCD PAL223: I0 Mask */
+#define LCD_PAL223_R14_0_Pos 16 /*!< LCD PAL223: R14_0 Position */
+#define LCD_PAL223_R14_0_Msk (0x1fUL << LCD_PAL223_R14_0_Pos) /*!< LCD PAL223: R14_0 Mask */
+#define LCD_PAL223_G14_0_Pos 21 /*!< LCD PAL223: G14_0 Position */
+#define LCD_PAL223_G14_0_Msk (0x1fUL << LCD_PAL223_G14_0_Pos) /*!< LCD PAL223: G14_0 Mask */
+#define LCD_PAL223_B14_0_Pos 26 /*!< LCD PAL223: B14_0 Position */
+#define LCD_PAL223_B14_0_Msk (0x1fUL << LCD_PAL223_B14_0_Pos) /*!< LCD PAL223: B14_0 Mask */
+#define LCD_PAL223_I1_Pos 31 /*!< LCD PAL223: I1 Position */
+#define LCD_PAL223_I1_Msk (0x01UL << LCD_PAL223_I1_Pos) /*!< LCD PAL223: I1 Mask */
+
+// --------------------------------------- LCD_PAL224 -------------------------------------------
+#define LCD_PAL224_R04_0_Pos 0 /*!< LCD PAL224: R04_0 Position */
+#define LCD_PAL224_R04_0_Msk (0x1fUL << LCD_PAL224_R04_0_Pos) /*!< LCD PAL224: R04_0 Mask */
+#define LCD_PAL224_G04_0_Pos 5 /*!< LCD PAL224: G04_0 Position */
+#define LCD_PAL224_G04_0_Msk (0x1fUL << LCD_PAL224_G04_0_Pos) /*!< LCD PAL224: G04_0 Mask */
+#define LCD_PAL224_B04_0_Pos 10 /*!< LCD PAL224: B04_0 Position */
+#define LCD_PAL224_B04_0_Msk (0x1fUL << LCD_PAL224_B04_0_Pos) /*!< LCD PAL224: B04_0 Mask */
+#define LCD_PAL224_I0_Pos 15 /*!< LCD PAL224: I0 Position */
+#define LCD_PAL224_I0_Msk (0x01UL << LCD_PAL224_I0_Pos) /*!< LCD PAL224: I0 Mask */
+#define LCD_PAL224_R14_0_Pos 16 /*!< LCD PAL224: R14_0 Position */
+#define LCD_PAL224_R14_0_Msk (0x1fUL << LCD_PAL224_R14_0_Pos) /*!< LCD PAL224: R14_0 Mask */
+#define LCD_PAL224_G14_0_Pos 21 /*!< LCD PAL224: G14_0 Position */
+#define LCD_PAL224_G14_0_Msk (0x1fUL << LCD_PAL224_G14_0_Pos) /*!< LCD PAL224: G14_0 Mask */
+#define LCD_PAL224_B14_0_Pos 26 /*!< LCD PAL224: B14_0 Position */
+#define LCD_PAL224_B14_0_Msk (0x1fUL << LCD_PAL224_B14_0_Pos) /*!< LCD PAL224: B14_0 Mask */
+#define LCD_PAL224_I1_Pos 31 /*!< LCD PAL224: I1 Position */
+#define LCD_PAL224_I1_Msk (0x01UL << LCD_PAL224_I1_Pos) /*!< LCD PAL224: I1 Mask */
+
+// --------------------------------------- LCD_PAL225 -------------------------------------------
+#define LCD_PAL225_R04_0_Pos 0 /*!< LCD PAL225: R04_0 Position */
+#define LCD_PAL225_R04_0_Msk (0x1fUL << LCD_PAL225_R04_0_Pos) /*!< LCD PAL225: R04_0 Mask */
+#define LCD_PAL225_G04_0_Pos 5 /*!< LCD PAL225: G04_0 Position */
+#define LCD_PAL225_G04_0_Msk (0x1fUL << LCD_PAL225_G04_0_Pos) /*!< LCD PAL225: G04_0 Mask */
+#define LCD_PAL225_B04_0_Pos 10 /*!< LCD PAL225: B04_0 Position */
+#define LCD_PAL225_B04_0_Msk (0x1fUL << LCD_PAL225_B04_0_Pos) /*!< LCD PAL225: B04_0 Mask */
+#define LCD_PAL225_I0_Pos 15 /*!< LCD PAL225: I0 Position */
+#define LCD_PAL225_I0_Msk (0x01UL << LCD_PAL225_I0_Pos) /*!< LCD PAL225: I0 Mask */
+#define LCD_PAL225_R14_0_Pos 16 /*!< LCD PAL225: R14_0 Position */
+#define LCD_PAL225_R14_0_Msk (0x1fUL << LCD_PAL225_R14_0_Pos) /*!< LCD PAL225: R14_0 Mask */
+#define LCD_PAL225_G14_0_Pos 21 /*!< LCD PAL225: G14_0 Position */
+#define LCD_PAL225_G14_0_Msk (0x1fUL << LCD_PAL225_G14_0_Pos) /*!< LCD PAL225: G14_0 Mask */
+#define LCD_PAL225_B14_0_Pos 26 /*!< LCD PAL225: B14_0 Position */
+#define LCD_PAL225_B14_0_Msk (0x1fUL << LCD_PAL225_B14_0_Pos) /*!< LCD PAL225: B14_0 Mask */
+#define LCD_PAL225_I1_Pos 31 /*!< LCD PAL225: I1 Position */
+#define LCD_PAL225_I1_Msk (0x01UL << LCD_PAL225_I1_Pos) /*!< LCD PAL225: I1 Mask */
+
+// --------------------------------------- LCD_PAL226 -------------------------------------------
+#define LCD_PAL226_R04_0_Pos 0 /*!< LCD PAL226: R04_0 Position */
+#define LCD_PAL226_R04_0_Msk (0x1fUL << LCD_PAL226_R04_0_Pos) /*!< LCD PAL226: R04_0 Mask */
+#define LCD_PAL226_G04_0_Pos 5 /*!< LCD PAL226: G04_0 Position */
+#define LCD_PAL226_G04_0_Msk (0x1fUL << LCD_PAL226_G04_0_Pos) /*!< LCD PAL226: G04_0 Mask */
+#define LCD_PAL226_B04_0_Pos 10 /*!< LCD PAL226: B04_0 Position */
+#define LCD_PAL226_B04_0_Msk (0x1fUL << LCD_PAL226_B04_0_Pos) /*!< LCD PAL226: B04_0 Mask */
+#define LCD_PAL226_I0_Pos 15 /*!< LCD PAL226: I0 Position */
+#define LCD_PAL226_I0_Msk (0x01UL << LCD_PAL226_I0_Pos) /*!< LCD PAL226: I0 Mask */
+#define LCD_PAL226_R14_0_Pos 16 /*!< LCD PAL226: R14_0 Position */
+#define LCD_PAL226_R14_0_Msk (0x1fUL << LCD_PAL226_R14_0_Pos) /*!< LCD PAL226: R14_0 Mask */
+#define LCD_PAL226_G14_0_Pos 21 /*!< LCD PAL226: G14_0 Position */
+#define LCD_PAL226_G14_0_Msk (0x1fUL << LCD_PAL226_G14_0_Pos) /*!< LCD PAL226: G14_0 Mask */
+#define LCD_PAL226_B14_0_Pos 26 /*!< LCD PAL226: B14_0 Position */
+#define LCD_PAL226_B14_0_Msk (0x1fUL << LCD_PAL226_B14_0_Pos) /*!< LCD PAL226: B14_0 Mask */
+#define LCD_PAL226_I1_Pos 31 /*!< LCD PAL226: I1 Position */
+#define LCD_PAL226_I1_Msk (0x01UL << LCD_PAL226_I1_Pos) /*!< LCD PAL226: I1 Mask */
+
+// --------------------------------------- LCD_PAL227 -------------------------------------------
+#define LCD_PAL227_R04_0_Pos 0 /*!< LCD PAL227: R04_0 Position */
+#define LCD_PAL227_R04_0_Msk (0x1fUL << LCD_PAL227_R04_0_Pos) /*!< LCD PAL227: R04_0 Mask */
+#define LCD_PAL227_G04_0_Pos 5 /*!< LCD PAL227: G04_0 Position */
+#define LCD_PAL227_G04_0_Msk (0x1fUL << LCD_PAL227_G04_0_Pos) /*!< LCD PAL227: G04_0 Mask */
+#define LCD_PAL227_B04_0_Pos 10 /*!< LCD PAL227: B04_0 Position */
+#define LCD_PAL227_B04_0_Msk (0x1fUL << LCD_PAL227_B04_0_Pos) /*!< LCD PAL227: B04_0 Mask */
+#define LCD_PAL227_I0_Pos 15 /*!< LCD PAL227: I0 Position */
+#define LCD_PAL227_I0_Msk (0x01UL << LCD_PAL227_I0_Pos) /*!< LCD PAL227: I0 Mask */
+#define LCD_PAL227_R14_0_Pos 16 /*!< LCD PAL227: R14_0 Position */
+#define LCD_PAL227_R14_0_Msk (0x1fUL << LCD_PAL227_R14_0_Pos) /*!< LCD PAL227: R14_0 Mask */
+#define LCD_PAL227_G14_0_Pos 21 /*!< LCD PAL227: G14_0 Position */
+#define LCD_PAL227_G14_0_Msk (0x1fUL << LCD_PAL227_G14_0_Pos) /*!< LCD PAL227: G14_0 Mask */
+#define LCD_PAL227_B14_0_Pos 26 /*!< LCD PAL227: B14_0 Position */
+#define LCD_PAL227_B14_0_Msk (0x1fUL << LCD_PAL227_B14_0_Pos) /*!< LCD PAL227: B14_0 Mask */
+#define LCD_PAL227_I1_Pos 31 /*!< LCD PAL227: I1 Position */
+#define LCD_PAL227_I1_Msk (0x01UL << LCD_PAL227_I1_Pos) /*!< LCD PAL227: I1 Mask */
+
+// --------------------------------------- LCD_PAL228 -------------------------------------------
+#define LCD_PAL228_R04_0_Pos 0 /*!< LCD PAL228: R04_0 Position */
+#define LCD_PAL228_R04_0_Msk (0x1fUL << LCD_PAL228_R04_0_Pos) /*!< LCD PAL228: R04_0 Mask */
+#define LCD_PAL228_G04_0_Pos 5 /*!< LCD PAL228: G04_0 Position */
+#define LCD_PAL228_G04_0_Msk (0x1fUL << LCD_PAL228_G04_0_Pos) /*!< LCD PAL228: G04_0 Mask */
+#define LCD_PAL228_B04_0_Pos 10 /*!< LCD PAL228: B04_0 Position */
+#define LCD_PAL228_B04_0_Msk (0x1fUL << LCD_PAL228_B04_0_Pos) /*!< LCD PAL228: B04_0 Mask */
+#define LCD_PAL228_I0_Pos 15 /*!< LCD PAL228: I0 Position */
+#define LCD_PAL228_I0_Msk (0x01UL << LCD_PAL228_I0_Pos) /*!< LCD PAL228: I0 Mask */
+#define LCD_PAL228_R14_0_Pos 16 /*!< LCD PAL228: R14_0 Position */
+#define LCD_PAL228_R14_0_Msk (0x1fUL << LCD_PAL228_R14_0_Pos) /*!< LCD PAL228: R14_0 Mask */
+#define LCD_PAL228_G14_0_Pos 21 /*!< LCD PAL228: G14_0 Position */
+#define LCD_PAL228_G14_0_Msk (0x1fUL << LCD_PAL228_G14_0_Pos) /*!< LCD PAL228: G14_0 Mask */
+#define LCD_PAL228_B14_0_Pos 26 /*!< LCD PAL228: B14_0 Position */
+#define LCD_PAL228_B14_0_Msk (0x1fUL << LCD_PAL228_B14_0_Pos) /*!< LCD PAL228: B14_0 Mask */
+#define LCD_PAL228_I1_Pos 31 /*!< LCD PAL228: I1 Position */
+#define LCD_PAL228_I1_Msk (0x01UL << LCD_PAL228_I1_Pos) /*!< LCD PAL228: I1 Mask */
+
+// --------------------------------------- LCD_PAL229 -------------------------------------------
+#define LCD_PAL229_R04_0_Pos 0 /*!< LCD PAL229: R04_0 Position */
+#define LCD_PAL229_R04_0_Msk (0x1fUL << LCD_PAL229_R04_0_Pos) /*!< LCD PAL229: R04_0 Mask */
+#define LCD_PAL229_G04_0_Pos 5 /*!< LCD PAL229: G04_0 Position */
+#define LCD_PAL229_G04_0_Msk (0x1fUL << LCD_PAL229_G04_0_Pos) /*!< LCD PAL229: G04_0 Mask */
+#define LCD_PAL229_B04_0_Pos 10 /*!< LCD PAL229: B04_0 Position */
+#define LCD_PAL229_B04_0_Msk (0x1fUL << LCD_PAL229_B04_0_Pos) /*!< LCD PAL229: B04_0 Mask */
+#define LCD_PAL229_I0_Pos 15 /*!< LCD PAL229: I0 Position */
+#define LCD_PAL229_I0_Msk (0x01UL << LCD_PAL229_I0_Pos) /*!< LCD PAL229: I0 Mask */
+#define LCD_PAL229_R14_0_Pos 16 /*!< LCD PAL229: R14_0 Position */
+#define LCD_PAL229_R14_0_Msk (0x1fUL << LCD_PAL229_R14_0_Pos) /*!< LCD PAL229: R14_0 Mask */
+#define LCD_PAL229_G14_0_Pos 21 /*!< LCD PAL229: G14_0 Position */
+#define LCD_PAL229_G14_0_Msk (0x1fUL << LCD_PAL229_G14_0_Pos) /*!< LCD PAL229: G14_0 Mask */
+#define LCD_PAL229_B14_0_Pos 26 /*!< LCD PAL229: B14_0 Position */
+#define LCD_PAL229_B14_0_Msk (0x1fUL << LCD_PAL229_B14_0_Pos) /*!< LCD PAL229: B14_0 Mask */
+#define LCD_PAL229_I1_Pos 31 /*!< LCD PAL229: I1 Position */
+#define LCD_PAL229_I1_Msk (0x01UL << LCD_PAL229_I1_Pos) /*!< LCD PAL229: I1 Mask */
+
+// --------------------------------------- LCD_PAL230 -------------------------------------------
+#define LCD_PAL230_R04_0_Pos 0 /*!< LCD PAL230: R04_0 Position */
+#define LCD_PAL230_R04_0_Msk (0x1fUL << LCD_PAL230_R04_0_Pos) /*!< LCD PAL230: R04_0 Mask */
+#define LCD_PAL230_G04_0_Pos 5 /*!< LCD PAL230: G04_0 Position */
+#define LCD_PAL230_G04_0_Msk (0x1fUL << LCD_PAL230_G04_0_Pos) /*!< LCD PAL230: G04_0 Mask */
+#define LCD_PAL230_B04_0_Pos 10 /*!< LCD PAL230: B04_0 Position */
+#define LCD_PAL230_B04_0_Msk (0x1fUL << LCD_PAL230_B04_0_Pos) /*!< LCD PAL230: B04_0 Mask */
+#define LCD_PAL230_I0_Pos 15 /*!< LCD PAL230: I0 Position */
+#define LCD_PAL230_I0_Msk (0x01UL << LCD_PAL230_I0_Pos) /*!< LCD PAL230: I0 Mask */
+#define LCD_PAL230_R14_0_Pos 16 /*!< LCD PAL230: R14_0 Position */
+#define LCD_PAL230_R14_0_Msk (0x1fUL << LCD_PAL230_R14_0_Pos) /*!< LCD PAL230: R14_0 Mask */
+#define LCD_PAL230_G14_0_Pos 21 /*!< LCD PAL230: G14_0 Position */
+#define LCD_PAL230_G14_0_Msk (0x1fUL << LCD_PAL230_G14_0_Pos) /*!< LCD PAL230: G14_0 Mask */
+#define LCD_PAL230_B14_0_Pos 26 /*!< LCD PAL230: B14_0 Position */
+#define LCD_PAL230_B14_0_Msk (0x1fUL << LCD_PAL230_B14_0_Pos) /*!< LCD PAL230: B14_0 Mask */
+#define LCD_PAL230_I1_Pos 31 /*!< LCD PAL230: I1 Position */
+#define LCD_PAL230_I1_Msk (0x01UL << LCD_PAL230_I1_Pos) /*!< LCD PAL230: I1 Mask */
+
+// --------------------------------------- LCD_PAL231 -------------------------------------------
+#define LCD_PAL231_R04_0_Pos 0 /*!< LCD PAL231: R04_0 Position */
+#define LCD_PAL231_R04_0_Msk (0x1fUL << LCD_PAL231_R04_0_Pos) /*!< LCD PAL231: R04_0 Mask */
+#define LCD_PAL231_G04_0_Pos 5 /*!< LCD PAL231: G04_0 Position */
+#define LCD_PAL231_G04_0_Msk (0x1fUL << LCD_PAL231_G04_0_Pos) /*!< LCD PAL231: G04_0 Mask */
+#define LCD_PAL231_B04_0_Pos 10 /*!< LCD PAL231: B04_0 Position */
+#define LCD_PAL231_B04_0_Msk (0x1fUL << LCD_PAL231_B04_0_Pos) /*!< LCD PAL231: B04_0 Mask */
+#define LCD_PAL231_I0_Pos 15 /*!< LCD PAL231: I0 Position */
+#define LCD_PAL231_I0_Msk (0x01UL << LCD_PAL231_I0_Pos) /*!< LCD PAL231: I0 Mask */
+#define LCD_PAL231_R14_0_Pos 16 /*!< LCD PAL231: R14_0 Position */
+#define LCD_PAL231_R14_0_Msk (0x1fUL << LCD_PAL231_R14_0_Pos) /*!< LCD PAL231: R14_0 Mask */
+#define LCD_PAL231_G14_0_Pos 21 /*!< LCD PAL231: G14_0 Position */
+#define LCD_PAL231_G14_0_Msk (0x1fUL << LCD_PAL231_G14_0_Pos) /*!< LCD PAL231: G14_0 Mask */
+#define LCD_PAL231_B14_0_Pos 26 /*!< LCD PAL231: B14_0 Position */
+#define LCD_PAL231_B14_0_Msk (0x1fUL << LCD_PAL231_B14_0_Pos) /*!< LCD PAL231: B14_0 Mask */
+#define LCD_PAL231_I1_Pos 31 /*!< LCD PAL231: I1 Position */
+#define LCD_PAL231_I1_Msk (0x01UL << LCD_PAL231_I1_Pos) /*!< LCD PAL231: I1 Mask */
+
+// --------------------------------------- LCD_PAL232 -------------------------------------------
+#define LCD_PAL232_R04_0_Pos 0 /*!< LCD PAL232: R04_0 Position */
+#define LCD_PAL232_R04_0_Msk (0x1fUL << LCD_PAL232_R04_0_Pos) /*!< LCD PAL232: R04_0 Mask */
+#define LCD_PAL232_G04_0_Pos 5 /*!< LCD PAL232: G04_0 Position */
+#define LCD_PAL232_G04_0_Msk (0x1fUL << LCD_PAL232_G04_0_Pos) /*!< LCD PAL232: G04_0 Mask */
+#define LCD_PAL232_B04_0_Pos 10 /*!< LCD PAL232: B04_0 Position */
+#define LCD_PAL232_B04_0_Msk (0x1fUL << LCD_PAL232_B04_0_Pos) /*!< LCD PAL232: B04_0 Mask */
+#define LCD_PAL232_I0_Pos 15 /*!< LCD PAL232: I0 Position */
+#define LCD_PAL232_I0_Msk (0x01UL << LCD_PAL232_I0_Pos) /*!< LCD PAL232: I0 Mask */
+#define LCD_PAL232_R14_0_Pos 16 /*!< LCD PAL232: R14_0 Position */
+#define LCD_PAL232_R14_0_Msk (0x1fUL << LCD_PAL232_R14_0_Pos) /*!< LCD PAL232: R14_0 Mask */
+#define LCD_PAL232_G14_0_Pos 21 /*!< LCD PAL232: G14_0 Position */
+#define LCD_PAL232_G14_0_Msk (0x1fUL << LCD_PAL232_G14_0_Pos) /*!< LCD PAL232: G14_0 Mask */
+#define LCD_PAL232_B14_0_Pos 26 /*!< LCD PAL232: B14_0 Position */
+#define LCD_PAL232_B14_0_Msk (0x1fUL << LCD_PAL232_B14_0_Pos) /*!< LCD PAL232: B14_0 Mask */
+#define LCD_PAL232_I1_Pos 31 /*!< LCD PAL232: I1 Position */
+#define LCD_PAL232_I1_Msk (0x01UL << LCD_PAL232_I1_Pos) /*!< LCD PAL232: I1 Mask */
+
+// --------------------------------------- LCD_PAL233 -------------------------------------------
+#define LCD_PAL233_R04_0_Pos 0 /*!< LCD PAL233: R04_0 Position */
+#define LCD_PAL233_R04_0_Msk (0x1fUL << LCD_PAL233_R04_0_Pos) /*!< LCD PAL233: R04_0 Mask */
+#define LCD_PAL233_G04_0_Pos 5 /*!< LCD PAL233: G04_0 Position */
+#define LCD_PAL233_G04_0_Msk (0x1fUL << LCD_PAL233_G04_0_Pos) /*!< LCD PAL233: G04_0 Mask */
+#define LCD_PAL233_B04_0_Pos 10 /*!< LCD PAL233: B04_0 Position */
+#define LCD_PAL233_B04_0_Msk (0x1fUL << LCD_PAL233_B04_0_Pos) /*!< LCD PAL233: B04_0 Mask */
+#define LCD_PAL233_I0_Pos 15 /*!< LCD PAL233: I0 Position */
+#define LCD_PAL233_I0_Msk (0x01UL << LCD_PAL233_I0_Pos) /*!< LCD PAL233: I0 Mask */
+#define LCD_PAL233_R14_0_Pos 16 /*!< LCD PAL233: R14_0 Position */
+#define LCD_PAL233_R14_0_Msk (0x1fUL << LCD_PAL233_R14_0_Pos) /*!< LCD PAL233: R14_0 Mask */
+#define LCD_PAL233_G14_0_Pos 21 /*!< LCD PAL233: G14_0 Position */
+#define LCD_PAL233_G14_0_Msk (0x1fUL << LCD_PAL233_G14_0_Pos) /*!< LCD PAL233: G14_0 Mask */
+#define LCD_PAL233_B14_0_Pos 26 /*!< LCD PAL233: B14_0 Position */
+#define LCD_PAL233_B14_0_Msk (0x1fUL << LCD_PAL233_B14_0_Pos) /*!< LCD PAL233: B14_0 Mask */
+#define LCD_PAL233_I1_Pos 31 /*!< LCD PAL233: I1 Position */
+#define LCD_PAL233_I1_Msk (0x01UL << LCD_PAL233_I1_Pos) /*!< LCD PAL233: I1 Mask */
+
+// --------------------------------------- LCD_PAL234 -------------------------------------------
+#define LCD_PAL234_R04_0_Pos 0 /*!< LCD PAL234: R04_0 Position */
+#define LCD_PAL234_R04_0_Msk (0x1fUL << LCD_PAL234_R04_0_Pos) /*!< LCD PAL234: R04_0 Mask */
+#define LCD_PAL234_G04_0_Pos 5 /*!< LCD PAL234: G04_0 Position */
+#define LCD_PAL234_G04_0_Msk (0x1fUL << LCD_PAL234_G04_0_Pos) /*!< LCD PAL234: G04_0 Mask */
+#define LCD_PAL234_B04_0_Pos 10 /*!< LCD PAL234: B04_0 Position */
+#define LCD_PAL234_B04_0_Msk (0x1fUL << LCD_PAL234_B04_0_Pos) /*!< LCD PAL234: B04_0 Mask */
+#define LCD_PAL234_I0_Pos 15 /*!< LCD PAL234: I0 Position */
+#define LCD_PAL234_I0_Msk (0x01UL << LCD_PAL234_I0_Pos) /*!< LCD PAL234: I0 Mask */
+#define LCD_PAL234_R14_0_Pos 16 /*!< LCD PAL234: R14_0 Position */
+#define LCD_PAL234_R14_0_Msk (0x1fUL << LCD_PAL234_R14_0_Pos) /*!< LCD PAL234: R14_0 Mask */
+#define LCD_PAL234_G14_0_Pos 21 /*!< LCD PAL234: G14_0 Position */
+#define LCD_PAL234_G14_0_Msk (0x1fUL << LCD_PAL234_G14_0_Pos) /*!< LCD PAL234: G14_0 Mask */
+#define LCD_PAL234_B14_0_Pos 26 /*!< LCD PAL234: B14_0 Position */
+#define LCD_PAL234_B14_0_Msk (0x1fUL << LCD_PAL234_B14_0_Pos) /*!< LCD PAL234: B14_0 Mask */
+#define LCD_PAL234_I1_Pos 31 /*!< LCD PAL234: I1 Position */
+#define LCD_PAL234_I1_Msk (0x01UL << LCD_PAL234_I1_Pos) /*!< LCD PAL234: I1 Mask */
+
+// --------------------------------------- LCD_PAL235 -------------------------------------------
+#define LCD_PAL235_R04_0_Pos 0 /*!< LCD PAL235: R04_0 Position */
+#define LCD_PAL235_R04_0_Msk (0x1fUL << LCD_PAL235_R04_0_Pos) /*!< LCD PAL235: R04_0 Mask */
+#define LCD_PAL235_G04_0_Pos 5 /*!< LCD PAL235: G04_0 Position */
+#define LCD_PAL235_G04_0_Msk (0x1fUL << LCD_PAL235_G04_0_Pos) /*!< LCD PAL235: G04_0 Mask */
+#define LCD_PAL235_B04_0_Pos 10 /*!< LCD PAL235: B04_0 Position */
+#define LCD_PAL235_B04_0_Msk (0x1fUL << LCD_PAL235_B04_0_Pos) /*!< LCD PAL235: B04_0 Mask */
+#define LCD_PAL235_I0_Pos 15 /*!< LCD PAL235: I0 Position */
+#define LCD_PAL235_I0_Msk (0x01UL << LCD_PAL235_I0_Pos) /*!< LCD PAL235: I0 Mask */
+#define LCD_PAL235_R14_0_Pos 16 /*!< LCD PAL235: R14_0 Position */
+#define LCD_PAL235_R14_0_Msk (0x1fUL << LCD_PAL235_R14_0_Pos) /*!< LCD PAL235: R14_0 Mask */
+#define LCD_PAL235_G14_0_Pos 21 /*!< LCD PAL235: G14_0 Position */
+#define LCD_PAL235_G14_0_Msk (0x1fUL << LCD_PAL235_G14_0_Pos) /*!< LCD PAL235: G14_0 Mask */
+#define LCD_PAL235_B14_0_Pos 26 /*!< LCD PAL235: B14_0 Position */
+#define LCD_PAL235_B14_0_Msk (0x1fUL << LCD_PAL235_B14_0_Pos) /*!< LCD PAL235: B14_0 Mask */
+#define LCD_PAL235_I1_Pos 31 /*!< LCD PAL235: I1 Position */
+#define LCD_PAL235_I1_Msk (0x01UL << LCD_PAL235_I1_Pos) /*!< LCD PAL235: I1 Mask */
+
+// --------------------------------------- LCD_PAL236 -------------------------------------------
+#define LCD_PAL236_R04_0_Pos 0 /*!< LCD PAL236: R04_0 Position */
+#define LCD_PAL236_R04_0_Msk (0x1fUL << LCD_PAL236_R04_0_Pos) /*!< LCD PAL236: R04_0 Mask */
+#define LCD_PAL236_G04_0_Pos 5 /*!< LCD PAL236: G04_0 Position */
+#define LCD_PAL236_G04_0_Msk (0x1fUL << LCD_PAL236_G04_0_Pos) /*!< LCD PAL236: G04_0 Mask */
+#define LCD_PAL236_B04_0_Pos 10 /*!< LCD PAL236: B04_0 Position */
+#define LCD_PAL236_B04_0_Msk (0x1fUL << LCD_PAL236_B04_0_Pos) /*!< LCD PAL236: B04_0 Mask */
+#define LCD_PAL236_I0_Pos 15 /*!< LCD PAL236: I0 Position */
+#define LCD_PAL236_I0_Msk (0x01UL << LCD_PAL236_I0_Pos) /*!< LCD PAL236: I0 Mask */
+#define LCD_PAL236_R14_0_Pos 16 /*!< LCD PAL236: R14_0 Position */
+#define LCD_PAL236_R14_0_Msk (0x1fUL << LCD_PAL236_R14_0_Pos) /*!< LCD PAL236: R14_0 Mask */
+#define LCD_PAL236_G14_0_Pos 21 /*!< LCD PAL236: G14_0 Position */
+#define LCD_PAL236_G14_0_Msk (0x1fUL << LCD_PAL236_G14_0_Pos) /*!< LCD PAL236: G14_0 Mask */
+#define LCD_PAL236_B14_0_Pos 26 /*!< LCD PAL236: B14_0 Position */
+#define LCD_PAL236_B14_0_Msk (0x1fUL << LCD_PAL236_B14_0_Pos) /*!< LCD PAL236: B14_0 Mask */
+#define LCD_PAL236_I1_Pos 31 /*!< LCD PAL236: I1 Position */
+#define LCD_PAL236_I1_Msk (0x01UL << LCD_PAL236_I1_Pos) /*!< LCD PAL236: I1 Mask */
+
+// --------------------------------------- LCD_PAL237 -------------------------------------------
+#define LCD_PAL237_R04_0_Pos 0 /*!< LCD PAL237: R04_0 Position */
+#define LCD_PAL237_R04_0_Msk (0x1fUL << LCD_PAL237_R04_0_Pos) /*!< LCD PAL237: R04_0 Mask */
+#define LCD_PAL237_G04_0_Pos 5 /*!< LCD PAL237: G04_0 Position */
+#define LCD_PAL237_G04_0_Msk (0x1fUL << LCD_PAL237_G04_0_Pos) /*!< LCD PAL237: G04_0 Mask */
+#define LCD_PAL237_B04_0_Pos 10 /*!< LCD PAL237: B04_0 Position */
+#define LCD_PAL237_B04_0_Msk (0x1fUL << LCD_PAL237_B04_0_Pos) /*!< LCD PAL237: B04_0 Mask */
+#define LCD_PAL237_I0_Pos 15 /*!< LCD PAL237: I0 Position */
+#define LCD_PAL237_I0_Msk (0x01UL << LCD_PAL237_I0_Pos) /*!< LCD PAL237: I0 Mask */
+#define LCD_PAL237_R14_0_Pos 16 /*!< LCD PAL237: R14_0 Position */
+#define LCD_PAL237_R14_0_Msk (0x1fUL << LCD_PAL237_R14_0_Pos) /*!< LCD PAL237: R14_0 Mask */
+#define LCD_PAL237_G14_0_Pos 21 /*!< LCD PAL237: G14_0 Position */
+#define LCD_PAL237_G14_0_Msk (0x1fUL << LCD_PAL237_G14_0_Pos) /*!< LCD PAL237: G14_0 Mask */
+#define LCD_PAL237_B14_0_Pos 26 /*!< LCD PAL237: B14_0 Position */
+#define LCD_PAL237_B14_0_Msk (0x1fUL << LCD_PAL237_B14_0_Pos) /*!< LCD PAL237: B14_0 Mask */
+#define LCD_PAL237_I1_Pos 31 /*!< LCD PAL237: I1 Position */
+#define LCD_PAL237_I1_Msk (0x01UL << LCD_PAL237_I1_Pos) /*!< LCD PAL237: I1 Mask */
+
+// --------------------------------------- LCD_PAL238 -------------------------------------------
+#define LCD_PAL238_R04_0_Pos 0 /*!< LCD PAL238: R04_0 Position */
+#define LCD_PAL238_R04_0_Msk (0x1fUL << LCD_PAL238_R04_0_Pos) /*!< LCD PAL238: R04_0 Mask */
+#define LCD_PAL238_G04_0_Pos 5 /*!< LCD PAL238: G04_0 Position */
+#define LCD_PAL238_G04_0_Msk (0x1fUL << LCD_PAL238_G04_0_Pos) /*!< LCD PAL238: G04_0 Mask */
+#define LCD_PAL238_B04_0_Pos 10 /*!< LCD PAL238: B04_0 Position */
+#define LCD_PAL238_B04_0_Msk (0x1fUL << LCD_PAL238_B04_0_Pos) /*!< LCD PAL238: B04_0 Mask */
+#define LCD_PAL238_I0_Pos 15 /*!< LCD PAL238: I0 Position */
+#define LCD_PAL238_I0_Msk (0x01UL << LCD_PAL238_I0_Pos) /*!< LCD PAL238: I0 Mask */
+#define LCD_PAL238_R14_0_Pos 16 /*!< LCD PAL238: R14_0 Position */
+#define LCD_PAL238_R14_0_Msk (0x1fUL << LCD_PAL238_R14_0_Pos) /*!< LCD PAL238: R14_0 Mask */
+#define LCD_PAL238_G14_0_Pos 21 /*!< LCD PAL238: G14_0 Position */
+#define LCD_PAL238_G14_0_Msk (0x1fUL << LCD_PAL238_G14_0_Pos) /*!< LCD PAL238: G14_0 Mask */
+#define LCD_PAL238_B14_0_Pos 26 /*!< LCD PAL238: B14_0 Position */
+#define LCD_PAL238_B14_0_Msk (0x1fUL << LCD_PAL238_B14_0_Pos) /*!< LCD PAL238: B14_0 Mask */
+#define LCD_PAL238_I1_Pos 31 /*!< LCD PAL238: I1 Position */
+#define LCD_PAL238_I1_Msk (0x01UL << LCD_PAL238_I1_Pos) /*!< LCD PAL238: I1 Mask */
+
+// --------------------------------------- LCD_PAL239 -------------------------------------------
+#define LCD_PAL239_R04_0_Pos 0 /*!< LCD PAL239: R04_0 Position */
+#define LCD_PAL239_R04_0_Msk (0x1fUL << LCD_PAL239_R04_0_Pos) /*!< LCD PAL239: R04_0 Mask */
+#define LCD_PAL239_G04_0_Pos 5 /*!< LCD PAL239: G04_0 Position */
+#define LCD_PAL239_G04_0_Msk (0x1fUL << LCD_PAL239_G04_0_Pos) /*!< LCD PAL239: G04_0 Mask */
+#define LCD_PAL239_B04_0_Pos 10 /*!< LCD PAL239: B04_0 Position */
+#define LCD_PAL239_B04_0_Msk (0x1fUL << LCD_PAL239_B04_0_Pos) /*!< LCD PAL239: B04_0 Mask */
+#define LCD_PAL239_I0_Pos 15 /*!< LCD PAL239: I0 Position */
+#define LCD_PAL239_I0_Msk (0x01UL << LCD_PAL239_I0_Pos) /*!< LCD PAL239: I0 Mask */
+#define LCD_PAL239_R14_0_Pos 16 /*!< LCD PAL239: R14_0 Position */
+#define LCD_PAL239_R14_0_Msk (0x1fUL << LCD_PAL239_R14_0_Pos) /*!< LCD PAL239: R14_0 Mask */
+#define LCD_PAL239_G14_0_Pos 21 /*!< LCD PAL239: G14_0 Position */
+#define LCD_PAL239_G14_0_Msk (0x1fUL << LCD_PAL239_G14_0_Pos) /*!< LCD PAL239: G14_0 Mask */
+#define LCD_PAL239_B14_0_Pos 26 /*!< LCD PAL239: B14_0 Position */
+#define LCD_PAL239_B14_0_Msk (0x1fUL << LCD_PAL239_B14_0_Pos) /*!< LCD PAL239: B14_0 Mask */
+#define LCD_PAL239_I1_Pos 31 /*!< LCD PAL239: I1 Position */
+#define LCD_PAL239_I1_Msk (0x01UL << LCD_PAL239_I1_Pos) /*!< LCD PAL239: I1 Mask */
+
+// --------------------------------------- LCD_PAL240 -------------------------------------------
+#define LCD_PAL240_R04_0_Pos 0 /*!< LCD PAL240: R04_0 Position */
+#define LCD_PAL240_R04_0_Msk (0x1fUL << LCD_PAL240_R04_0_Pos) /*!< LCD PAL240: R04_0 Mask */
+#define LCD_PAL240_G04_0_Pos 5 /*!< LCD PAL240: G04_0 Position */
+#define LCD_PAL240_G04_0_Msk (0x1fUL << LCD_PAL240_G04_0_Pos) /*!< LCD PAL240: G04_0 Mask */
+#define LCD_PAL240_B04_0_Pos 10 /*!< LCD PAL240: B04_0 Position */
+#define LCD_PAL240_B04_0_Msk (0x1fUL << LCD_PAL240_B04_0_Pos) /*!< LCD PAL240: B04_0 Mask */
+#define LCD_PAL240_I0_Pos 15 /*!< LCD PAL240: I0 Position */
+#define LCD_PAL240_I0_Msk (0x01UL << LCD_PAL240_I0_Pos) /*!< LCD PAL240: I0 Mask */
+#define LCD_PAL240_R14_0_Pos 16 /*!< LCD PAL240: R14_0 Position */
+#define LCD_PAL240_R14_0_Msk (0x1fUL << LCD_PAL240_R14_0_Pos) /*!< LCD PAL240: R14_0 Mask */
+#define LCD_PAL240_G14_0_Pos 21 /*!< LCD PAL240: G14_0 Position */
+#define LCD_PAL240_G14_0_Msk (0x1fUL << LCD_PAL240_G14_0_Pos) /*!< LCD PAL240: G14_0 Mask */
+#define LCD_PAL240_B14_0_Pos 26 /*!< LCD PAL240: B14_0 Position */
+#define LCD_PAL240_B14_0_Msk (0x1fUL << LCD_PAL240_B14_0_Pos) /*!< LCD PAL240: B14_0 Mask */
+#define LCD_PAL240_I1_Pos 31 /*!< LCD PAL240: I1 Position */
+#define LCD_PAL240_I1_Msk (0x01UL << LCD_PAL240_I1_Pos) /*!< LCD PAL240: I1 Mask */
+
+// --------------------------------------- LCD_PAL241 -------------------------------------------
+#define LCD_PAL241_R04_0_Pos 0 /*!< LCD PAL241: R04_0 Position */
+#define LCD_PAL241_R04_0_Msk (0x1fUL << LCD_PAL241_R04_0_Pos) /*!< LCD PAL241: R04_0 Mask */
+#define LCD_PAL241_G04_0_Pos 5 /*!< LCD PAL241: G04_0 Position */
+#define LCD_PAL241_G04_0_Msk (0x1fUL << LCD_PAL241_G04_0_Pos) /*!< LCD PAL241: G04_0 Mask */
+#define LCD_PAL241_B04_0_Pos 10 /*!< LCD PAL241: B04_0 Position */
+#define LCD_PAL241_B04_0_Msk (0x1fUL << LCD_PAL241_B04_0_Pos) /*!< LCD PAL241: B04_0 Mask */
+#define LCD_PAL241_I0_Pos 15 /*!< LCD PAL241: I0 Position */
+#define LCD_PAL241_I0_Msk (0x01UL << LCD_PAL241_I0_Pos) /*!< LCD PAL241: I0 Mask */
+#define LCD_PAL241_R14_0_Pos 16 /*!< LCD PAL241: R14_0 Position */
+#define LCD_PAL241_R14_0_Msk (0x1fUL << LCD_PAL241_R14_0_Pos) /*!< LCD PAL241: R14_0 Mask */
+#define LCD_PAL241_G14_0_Pos 21 /*!< LCD PAL241: G14_0 Position */
+#define LCD_PAL241_G14_0_Msk (0x1fUL << LCD_PAL241_G14_0_Pos) /*!< LCD PAL241: G14_0 Mask */
+#define LCD_PAL241_B14_0_Pos 26 /*!< LCD PAL241: B14_0 Position */
+#define LCD_PAL241_B14_0_Msk (0x1fUL << LCD_PAL241_B14_0_Pos) /*!< LCD PAL241: B14_0 Mask */
+#define LCD_PAL241_I1_Pos 31 /*!< LCD PAL241: I1 Position */
+#define LCD_PAL241_I1_Msk (0x01UL << LCD_PAL241_I1_Pos) /*!< LCD PAL241: I1 Mask */
+
+// --------------------------------------- LCD_PAL242 -------------------------------------------
+#define LCD_PAL242_R04_0_Pos 0 /*!< LCD PAL242: R04_0 Position */
+#define LCD_PAL242_R04_0_Msk (0x1fUL << LCD_PAL242_R04_0_Pos) /*!< LCD PAL242: R04_0 Mask */
+#define LCD_PAL242_G04_0_Pos 5 /*!< LCD PAL242: G04_0 Position */
+#define LCD_PAL242_G04_0_Msk (0x1fUL << LCD_PAL242_G04_0_Pos) /*!< LCD PAL242: G04_0 Mask */
+#define LCD_PAL242_B04_0_Pos 10 /*!< LCD PAL242: B04_0 Position */
+#define LCD_PAL242_B04_0_Msk (0x1fUL << LCD_PAL242_B04_0_Pos) /*!< LCD PAL242: B04_0 Mask */
+#define LCD_PAL242_I0_Pos 15 /*!< LCD PAL242: I0 Position */
+#define LCD_PAL242_I0_Msk (0x01UL << LCD_PAL242_I0_Pos) /*!< LCD PAL242: I0 Mask */
+#define LCD_PAL242_R14_0_Pos 16 /*!< LCD PAL242: R14_0 Position */
+#define LCD_PAL242_R14_0_Msk (0x1fUL << LCD_PAL242_R14_0_Pos) /*!< LCD PAL242: R14_0 Mask */
+#define LCD_PAL242_G14_0_Pos 21 /*!< LCD PAL242: G14_0 Position */
+#define LCD_PAL242_G14_0_Msk (0x1fUL << LCD_PAL242_G14_0_Pos) /*!< LCD PAL242: G14_0 Mask */
+#define LCD_PAL242_B14_0_Pos 26 /*!< LCD PAL242: B14_0 Position */
+#define LCD_PAL242_B14_0_Msk (0x1fUL << LCD_PAL242_B14_0_Pos) /*!< LCD PAL242: B14_0 Mask */
+#define LCD_PAL242_I1_Pos 31 /*!< LCD PAL242: I1 Position */
+#define LCD_PAL242_I1_Msk (0x01UL << LCD_PAL242_I1_Pos) /*!< LCD PAL242: I1 Mask */
+
+// --------------------------------------- LCD_PAL243 -------------------------------------------
+#define LCD_PAL243_R04_0_Pos 0 /*!< LCD PAL243: R04_0 Position */
+#define LCD_PAL243_R04_0_Msk (0x1fUL << LCD_PAL243_R04_0_Pos) /*!< LCD PAL243: R04_0 Mask */
+#define LCD_PAL243_G04_0_Pos 5 /*!< LCD PAL243: G04_0 Position */
+#define LCD_PAL243_G04_0_Msk (0x1fUL << LCD_PAL243_G04_0_Pos) /*!< LCD PAL243: G04_0 Mask */
+#define LCD_PAL243_B04_0_Pos 10 /*!< LCD PAL243: B04_0 Position */
+#define LCD_PAL243_B04_0_Msk (0x1fUL << LCD_PAL243_B04_0_Pos) /*!< LCD PAL243: B04_0 Mask */
+#define LCD_PAL243_I0_Pos 15 /*!< LCD PAL243: I0 Position */
+#define LCD_PAL243_I0_Msk (0x01UL << LCD_PAL243_I0_Pos) /*!< LCD PAL243: I0 Mask */
+#define LCD_PAL243_R14_0_Pos 16 /*!< LCD PAL243: R14_0 Position */
+#define LCD_PAL243_R14_0_Msk (0x1fUL << LCD_PAL243_R14_0_Pos) /*!< LCD PAL243: R14_0 Mask */
+#define LCD_PAL243_G14_0_Pos 21 /*!< LCD PAL243: G14_0 Position */
+#define LCD_PAL243_G14_0_Msk (0x1fUL << LCD_PAL243_G14_0_Pos) /*!< LCD PAL243: G14_0 Mask */
+#define LCD_PAL243_B14_0_Pos 26 /*!< LCD PAL243: B14_0 Position */
+#define LCD_PAL243_B14_0_Msk (0x1fUL << LCD_PAL243_B14_0_Pos) /*!< LCD PAL243: B14_0 Mask */
+#define LCD_PAL243_I1_Pos 31 /*!< LCD PAL243: I1 Position */
+#define LCD_PAL243_I1_Msk (0x01UL << LCD_PAL243_I1_Pos) /*!< LCD PAL243: I1 Mask */
+
+// --------------------------------------- LCD_PAL244 -------------------------------------------
+#define LCD_PAL244_R04_0_Pos 0 /*!< LCD PAL244: R04_0 Position */
+#define LCD_PAL244_R04_0_Msk (0x1fUL << LCD_PAL244_R04_0_Pos) /*!< LCD PAL244: R04_0 Mask */
+#define LCD_PAL244_G04_0_Pos 5 /*!< LCD PAL244: G04_0 Position */
+#define LCD_PAL244_G04_0_Msk (0x1fUL << LCD_PAL244_G04_0_Pos) /*!< LCD PAL244: G04_0 Mask */
+#define LCD_PAL244_B04_0_Pos 10 /*!< LCD PAL244: B04_0 Position */
+#define LCD_PAL244_B04_0_Msk (0x1fUL << LCD_PAL244_B04_0_Pos) /*!< LCD PAL244: B04_0 Mask */
+#define LCD_PAL244_I0_Pos 15 /*!< LCD PAL244: I0 Position */
+#define LCD_PAL244_I0_Msk (0x01UL << LCD_PAL244_I0_Pos) /*!< LCD PAL244: I0 Mask */
+#define LCD_PAL244_R14_0_Pos 16 /*!< LCD PAL244: R14_0 Position */
+#define LCD_PAL244_R14_0_Msk (0x1fUL << LCD_PAL244_R14_0_Pos) /*!< LCD PAL244: R14_0 Mask */
+#define LCD_PAL244_G14_0_Pos 21 /*!< LCD PAL244: G14_0 Position */
+#define LCD_PAL244_G14_0_Msk (0x1fUL << LCD_PAL244_G14_0_Pos) /*!< LCD PAL244: G14_0 Mask */
+#define LCD_PAL244_B14_0_Pos 26 /*!< LCD PAL244: B14_0 Position */
+#define LCD_PAL244_B14_0_Msk (0x1fUL << LCD_PAL244_B14_0_Pos) /*!< LCD PAL244: B14_0 Mask */
+#define LCD_PAL244_I1_Pos 31 /*!< LCD PAL244: I1 Position */
+#define LCD_PAL244_I1_Msk (0x01UL << LCD_PAL244_I1_Pos) /*!< LCD PAL244: I1 Mask */
+
+// --------------------------------------- LCD_PAL245 -------------------------------------------
+#define LCD_PAL245_R04_0_Pos 0 /*!< LCD PAL245: R04_0 Position */
+#define LCD_PAL245_R04_0_Msk (0x1fUL << LCD_PAL245_R04_0_Pos) /*!< LCD PAL245: R04_0 Mask */
+#define LCD_PAL245_G04_0_Pos 5 /*!< LCD PAL245: G04_0 Position */
+#define LCD_PAL245_G04_0_Msk (0x1fUL << LCD_PAL245_G04_0_Pos) /*!< LCD PAL245: G04_0 Mask */
+#define LCD_PAL245_B04_0_Pos 10 /*!< LCD PAL245: B04_0 Position */
+#define LCD_PAL245_B04_0_Msk (0x1fUL << LCD_PAL245_B04_0_Pos) /*!< LCD PAL245: B04_0 Mask */
+#define LCD_PAL245_I0_Pos 15 /*!< LCD PAL245: I0 Position */
+#define LCD_PAL245_I0_Msk (0x01UL << LCD_PAL245_I0_Pos) /*!< LCD PAL245: I0 Mask */
+#define LCD_PAL245_R14_0_Pos 16 /*!< LCD PAL245: R14_0 Position */
+#define LCD_PAL245_R14_0_Msk (0x1fUL << LCD_PAL245_R14_0_Pos) /*!< LCD PAL245: R14_0 Mask */
+#define LCD_PAL245_G14_0_Pos 21 /*!< LCD PAL245: G14_0 Position */
+#define LCD_PAL245_G14_0_Msk (0x1fUL << LCD_PAL245_G14_0_Pos) /*!< LCD PAL245: G14_0 Mask */
+#define LCD_PAL245_B14_0_Pos 26 /*!< LCD PAL245: B14_0 Position */
+#define LCD_PAL245_B14_0_Msk (0x1fUL << LCD_PAL245_B14_0_Pos) /*!< LCD PAL245: B14_0 Mask */
+#define LCD_PAL245_I1_Pos 31 /*!< LCD PAL245: I1 Position */
+#define LCD_PAL245_I1_Msk (0x01UL << LCD_PAL245_I1_Pos) /*!< LCD PAL245: I1 Mask */
+
+// --------------------------------------- LCD_PAL246 -------------------------------------------
+#define LCD_PAL246_R04_0_Pos 0 /*!< LCD PAL246: R04_0 Position */
+#define LCD_PAL246_R04_0_Msk (0x1fUL << LCD_PAL246_R04_0_Pos) /*!< LCD PAL246: R04_0 Mask */
+#define LCD_PAL246_G04_0_Pos 5 /*!< LCD PAL246: G04_0 Position */
+#define LCD_PAL246_G04_0_Msk (0x1fUL << LCD_PAL246_G04_0_Pos) /*!< LCD PAL246: G04_0 Mask */
+#define LCD_PAL246_B04_0_Pos 10 /*!< LCD PAL246: B04_0 Position */
+#define LCD_PAL246_B04_0_Msk (0x1fUL << LCD_PAL246_B04_0_Pos) /*!< LCD PAL246: B04_0 Mask */
+#define LCD_PAL246_I0_Pos 15 /*!< LCD PAL246: I0 Position */
+#define LCD_PAL246_I0_Msk (0x01UL << LCD_PAL246_I0_Pos) /*!< LCD PAL246: I0 Mask */
+#define LCD_PAL246_R14_0_Pos 16 /*!< LCD PAL246: R14_0 Position */
+#define LCD_PAL246_R14_0_Msk (0x1fUL << LCD_PAL246_R14_0_Pos) /*!< LCD PAL246: R14_0 Mask */
+#define LCD_PAL246_G14_0_Pos 21 /*!< LCD PAL246: G14_0 Position */
+#define LCD_PAL246_G14_0_Msk (0x1fUL << LCD_PAL246_G14_0_Pos) /*!< LCD PAL246: G14_0 Mask */
+#define LCD_PAL246_B14_0_Pos 26 /*!< LCD PAL246: B14_0 Position */
+#define LCD_PAL246_B14_0_Msk (0x1fUL << LCD_PAL246_B14_0_Pos) /*!< LCD PAL246: B14_0 Mask */
+#define LCD_PAL246_I1_Pos 31 /*!< LCD PAL246: I1 Position */
+#define LCD_PAL246_I1_Msk (0x01UL << LCD_PAL246_I1_Pos) /*!< LCD PAL246: I1 Mask */
+
+// --------------------------------------- LCD_PAL247 -------------------------------------------
+#define LCD_PAL247_R04_0_Pos 0 /*!< LCD PAL247: R04_0 Position */
+#define LCD_PAL247_R04_0_Msk (0x1fUL << LCD_PAL247_R04_0_Pos) /*!< LCD PAL247: R04_0 Mask */
+#define LCD_PAL247_G04_0_Pos 5 /*!< LCD PAL247: G04_0 Position */
+#define LCD_PAL247_G04_0_Msk (0x1fUL << LCD_PAL247_G04_0_Pos) /*!< LCD PAL247: G04_0 Mask */
+#define LCD_PAL247_B04_0_Pos 10 /*!< LCD PAL247: B04_0 Position */
+#define LCD_PAL247_B04_0_Msk (0x1fUL << LCD_PAL247_B04_0_Pos) /*!< LCD PAL247: B04_0 Mask */
+#define LCD_PAL247_I0_Pos 15 /*!< LCD PAL247: I0 Position */
+#define LCD_PAL247_I0_Msk (0x01UL << LCD_PAL247_I0_Pos) /*!< LCD PAL247: I0 Mask */
+#define LCD_PAL247_R14_0_Pos 16 /*!< LCD PAL247: R14_0 Position */
+#define LCD_PAL247_R14_0_Msk (0x1fUL << LCD_PAL247_R14_0_Pos) /*!< LCD PAL247: R14_0 Mask */
+#define LCD_PAL247_G14_0_Pos 21 /*!< LCD PAL247: G14_0 Position */
+#define LCD_PAL247_G14_0_Msk (0x1fUL << LCD_PAL247_G14_0_Pos) /*!< LCD PAL247: G14_0 Mask */
+#define LCD_PAL247_B14_0_Pos 26 /*!< LCD PAL247: B14_0 Position */
+#define LCD_PAL247_B14_0_Msk (0x1fUL << LCD_PAL247_B14_0_Pos) /*!< LCD PAL247: B14_0 Mask */
+#define LCD_PAL247_I1_Pos 31 /*!< LCD PAL247: I1 Position */
+#define LCD_PAL247_I1_Msk (0x01UL << LCD_PAL247_I1_Pos) /*!< LCD PAL247: I1 Mask */
+
+// --------------------------------------- LCD_PAL248 -------------------------------------------
+#define LCD_PAL248_R04_0_Pos 0 /*!< LCD PAL248: R04_0 Position */
+#define LCD_PAL248_R04_0_Msk (0x1fUL << LCD_PAL248_R04_0_Pos) /*!< LCD PAL248: R04_0 Mask */
+#define LCD_PAL248_G04_0_Pos 5 /*!< LCD PAL248: G04_0 Position */
+#define LCD_PAL248_G04_0_Msk (0x1fUL << LCD_PAL248_G04_0_Pos) /*!< LCD PAL248: G04_0 Mask */
+#define LCD_PAL248_B04_0_Pos 10 /*!< LCD PAL248: B04_0 Position */
+#define LCD_PAL248_B04_0_Msk (0x1fUL << LCD_PAL248_B04_0_Pos) /*!< LCD PAL248: B04_0 Mask */
+#define LCD_PAL248_I0_Pos 15 /*!< LCD PAL248: I0 Position */
+#define LCD_PAL248_I0_Msk (0x01UL << LCD_PAL248_I0_Pos) /*!< LCD PAL248: I0 Mask */
+#define LCD_PAL248_R14_0_Pos 16 /*!< LCD PAL248: R14_0 Position */
+#define LCD_PAL248_R14_0_Msk (0x1fUL << LCD_PAL248_R14_0_Pos) /*!< LCD PAL248: R14_0 Mask */
+#define LCD_PAL248_G14_0_Pos 21 /*!< LCD PAL248: G14_0 Position */
+#define LCD_PAL248_G14_0_Msk (0x1fUL << LCD_PAL248_G14_0_Pos) /*!< LCD PAL248: G14_0 Mask */
+#define LCD_PAL248_B14_0_Pos 26 /*!< LCD PAL248: B14_0 Position */
+#define LCD_PAL248_B14_0_Msk (0x1fUL << LCD_PAL248_B14_0_Pos) /*!< LCD PAL248: B14_0 Mask */
+#define LCD_PAL248_I1_Pos 31 /*!< LCD PAL248: I1 Position */
+#define LCD_PAL248_I1_Msk (0x01UL << LCD_PAL248_I1_Pos) /*!< LCD PAL248: I1 Mask */
+
+// --------------------------------------- LCD_PAL249 -------------------------------------------
+#define LCD_PAL249_R04_0_Pos 0 /*!< LCD PAL249: R04_0 Position */
+#define LCD_PAL249_R04_0_Msk (0x1fUL << LCD_PAL249_R04_0_Pos) /*!< LCD PAL249: R04_0 Mask */
+#define LCD_PAL249_G04_0_Pos 5 /*!< LCD PAL249: G04_0 Position */
+#define LCD_PAL249_G04_0_Msk (0x1fUL << LCD_PAL249_G04_0_Pos) /*!< LCD PAL249: G04_0 Mask */
+#define LCD_PAL249_B04_0_Pos 10 /*!< LCD PAL249: B04_0 Position */
+#define LCD_PAL249_B04_0_Msk (0x1fUL << LCD_PAL249_B04_0_Pos) /*!< LCD PAL249: B04_0 Mask */
+#define LCD_PAL249_I0_Pos 15 /*!< LCD PAL249: I0 Position */
+#define LCD_PAL249_I0_Msk (0x01UL << LCD_PAL249_I0_Pos) /*!< LCD PAL249: I0 Mask */
+#define LCD_PAL249_R14_0_Pos 16 /*!< LCD PAL249: R14_0 Position */
+#define LCD_PAL249_R14_0_Msk (0x1fUL << LCD_PAL249_R14_0_Pos) /*!< LCD PAL249: R14_0 Mask */
+#define LCD_PAL249_G14_0_Pos 21 /*!< LCD PAL249: G14_0 Position */
+#define LCD_PAL249_G14_0_Msk (0x1fUL << LCD_PAL249_G14_0_Pos) /*!< LCD PAL249: G14_0 Mask */
+#define LCD_PAL249_B14_0_Pos 26 /*!< LCD PAL249: B14_0 Position */
+#define LCD_PAL249_B14_0_Msk (0x1fUL << LCD_PAL249_B14_0_Pos) /*!< LCD PAL249: B14_0 Mask */
+#define LCD_PAL249_I1_Pos 31 /*!< LCD PAL249: I1 Position */
+#define LCD_PAL249_I1_Msk (0x01UL << LCD_PAL249_I1_Pos) /*!< LCD PAL249: I1 Mask */
+
+// --------------------------------------- LCD_PAL250 -------------------------------------------
+#define LCD_PAL250_R04_0_Pos 0 /*!< LCD PAL250: R04_0 Position */
+#define LCD_PAL250_R04_0_Msk (0x1fUL << LCD_PAL250_R04_0_Pos) /*!< LCD PAL250: R04_0 Mask */
+#define LCD_PAL250_G04_0_Pos 5 /*!< LCD PAL250: G04_0 Position */
+#define LCD_PAL250_G04_0_Msk (0x1fUL << LCD_PAL250_G04_0_Pos) /*!< LCD PAL250: G04_0 Mask */
+#define LCD_PAL250_B04_0_Pos 10 /*!< LCD PAL250: B04_0 Position */
+#define LCD_PAL250_B04_0_Msk (0x1fUL << LCD_PAL250_B04_0_Pos) /*!< LCD PAL250: B04_0 Mask */
+#define LCD_PAL250_I0_Pos 15 /*!< LCD PAL250: I0 Position */
+#define LCD_PAL250_I0_Msk (0x01UL << LCD_PAL250_I0_Pos) /*!< LCD PAL250: I0 Mask */
+#define LCD_PAL250_R14_0_Pos 16 /*!< LCD PAL250: R14_0 Position */
+#define LCD_PAL250_R14_0_Msk (0x1fUL << LCD_PAL250_R14_0_Pos) /*!< LCD PAL250: R14_0 Mask */
+#define LCD_PAL250_G14_0_Pos 21 /*!< LCD PAL250: G14_0 Position */
+#define LCD_PAL250_G14_0_Msk (0x1fUL << LCD_PAL250_G14_0_Pos) /*!< LCD PAL250: G14_0 Mask */
+#define LCD_PAL250_B14_0_Pos 26 /*!< LCD PAL250: B14_0 Position */
+#define LCD_PAL250_B14_0_Msk (0x1fUL << LCD_PAL250_B14_0_Pos) /*!< LCD PAL250: B14_0 Mask */
+#define LCD_PAL250_I1_Pos 31 /*!< LCD PAL250: I1 Position */
+#define LCD_PAL250_I1_Msk (0x01UL << LCD_PAL250_I1_Pos) /*!< LCD PAL250: I1 Mask */
+
+// --------------------------------------- LCD_PAL251 -------------------------------------------
+#define LCD_PAL251_R04_0_Pos 0 /*!< LCD PAL251: R04_0 Position */
+#define LCD_PAL251_R04_0_Msk (0x1fUL << LCD_PAL251_R04_0_Pos) /*!< LCD PAL251: R04_0 Mask */
+#define LCD_PAL251_G04_0_Pos 5 /*!< LCD PAL251: G04_0 Position */
+#define LCD_PAL251_G04_0_Msk (0x1fUL << LCD_PAL251_G04_0_Pos) /*!< LCD PAL251: G04_0 Mask */
+#define LCD_PAL251_B04_0_Pos 10 /*!< LCD PAL251: B04_0 Position */
+#define LCD_PAL251_B04_0_Msk (0x1fUL << LCD_PAL251_B04_0_Pos) /*!< LCD PAL251: B04_0 Mask */
+#define LCD_PAL251_I0_Pos 15 /*!< LCD PAL251: I0 Position */
+#define LCD_PAL251_I0_Msk (0x01UL << LCD_PAL251_I0_Pos) /*!< LCD PAL251: I0 Mask */
+#define LCD_PAL251_R14_0_Pos 16 /*!< LCD PAL251: R14_0 Position */
+#define LCD_PAL251_R14_0_Msk (0x1fUL << LCD_PAL251_R14_0_Pos) /*!< LCD PAL251: R14_0 Mask */
+#define LCD_PAL251_G14_0_Pos 21 /*!< LCD PAL251: G14_0 Position */
+#define LCD_PAL251_G14_0_Msk (0x1fUL << LCD_PAL251_G14_0_Pos) /*!< LCD PAL251: G14_0 Mask */
+#define LCD_PAL251_B14_0_Pos 26 /*!< LCD PAL251: B14_0 Position */
+#define LCD_PAL251_B14_0_Msk (0x1fUL << LCD_PAL251_B14_0_Pos) /*!< LCD PAL251: B14_0 Mask */
+#define LCD_PAL251_I1_Pos 31 /*!< LCD PAL251: I1 Position */
+#define LCD_PAL251_I1_Msk (0x01UL << LCD_PAL251_I1_Pos) /*!< LCD PAL251: I1 Mask */
+
+// --------------------------------------- LCD_PAL252 -------------------------------------------
+#define LCD_PAL252_R04_0_Pos 0 /*!< LCD PAL252: R04_0 Position */
+#define LCD_PAL252_R04_0_Msk (0x1fUL << LCD_PAL252_R04_0_Pos) /*!< LCD PAL252: R04_0 Mask */
+#define LCD_PAL252_G04_0_Pos 5 /*!< LCD PAL252: G04_0 Position */
+#define LCD_PAL252_G04_0_Msk (0x1fUL << LCD_PAL252_G04_0_Pos) /*!< LCD PAL252: G04_0 Mask */
+#define LCD_PAL252_B04_0_Pos 10 /*!< LCD PAL252: B04_0 Position */
+#define LCD_PAL252_B04_0_Msk (0x1fUL << LCD_PAL252_B04_0_Pos) /*!< LCD PAL252: B04_0 Mask */
+#define LCD_PAL252_I0_Pos 15 /*!< LCD PAL252: I0 Position */
+#define LCD_PAL252_I0_Msk (0x01UL << LCD_PAL252_I0_Pos) /*!< LCD PAL252: I0 Mask */
+#define LCD_PAL252_R14_0_Pos 16 /*!< LCD PAL252: R14_0 Position */
+#define LCD_PAL252_R14_0_Msk (0x1fUL << LCD_PAL252_R14_0_Pos) /*!< LCD PAL252: R14_0 Mask */
+#define LCD_PAL252_G14_0_Pos 21 /*!< LCD PAL252: G14_0 Position */
+#define LCD_PAL252_G14_0_Msk (0x1fUL << LCD_PAL252_G14_0_Pos) /*!< LCD PAL252: G14_0 Mask */
+#define LCD_PAL252_B14_0_Pos 26 /*!< LCD PAL252: B14_0 Position */
+#define LCD_PAL252_B14_0_Msk (0x1fUL << LCD_PAL252_B14_0_Pos) /*!< LCD PAL252: B14_0 Mask */
+#define LCD_PAL252_I1_Pos 31 /*!< LCD PAL252: I1 Position */
+#define LCD_PAL252_I1_Msk (0x01UL << LCD_PAL252_I1_Pos) /*!< LCD PAL252: I1 Mask */
+
+// --------------------------------------- LCD_PAL253 -------------------------------------------
+#define LCD_PAL253_R04_0_Pos 0 /*!< LCD PAL253: R04_0 Position */
+#define LCD_PAL253_R04_0_Msk (0x1fUL << LCD_PAL253_R04_0_Pos) /*!< LCD PAL253: R04_0 Mask */
+#define LCD_PAL253_G04_0_Pos 5 /*!< LCD PAL253: G04_0 Position */
+#define LCD_PAL253_G04_0_Msk (0x1fUL << LCD_PAL253_G04_0_Pos) /*!< LCD PAL253: G04_0 Mask */
+#define LCD_PAL253_B04_0_Pos 10 /*!< LCD PAL253: B04_0 Position */
+#define LCD_PAL253_B04_0_Msk (0x1fUL << LCD_PAL253_B04_0_Pos) /*!< LCD PAL253: B04_0 Mask */
+#define LCD_PAL253_I0_Pos 15 /*!< LCD PAL253: I0 Position */
+#define LCD_PAL253_I0_Msk (0x01UL << LCD_PAL253_I0_Pos) /*!< LCD PAL253: I0 Mask */
+#define LCD_PAL253_R14_0_Pos 16 /*!< LCD PAL253: R14_0 Position */
+#define LCD_PAL253_R14_0_Msk (0x1fUL << LCD_PAL253_R14_0_Pos) /*!< LCD PAL253: R14_0 Mask */
+#define LCD_PAL253_G14_0_Pos 21 /*!< LCD PAL253: G14_0 Position */
+#define LCD_PAL253_G14_0_Msk (0x1fUL << LCD_PAL253_G14_0_Pos) /*!< LCD PAL253: G14_0 Mask */
+#define LCD_PAL253_B14_0_Pos 26 /*!< LCD PAL253: B14_0 Position */
+#define LCD_PAL253_B14_0_Msk (0x1fUL << LCD_PAL253_B14_0_Pos) /*!< LCD PAL253: B14_0 Mask */
+#define LCD_PAL253_I1_Pos 31 /*!< LCD PAL253: I1 Position */
+#define LCD_PAL253_I1_Msk (0x01UL << LCD_PAL253_I1_Pos) /*!< LCD PAL253: I1 Mask */
+
+// --------------------------------------- LCD_PAL254 -------------------------------------------
+#define LCD_PAL254_R04_0_Pos 0 /*!< LCD PAL254: R04_0 Position */
+#define LCD_PAL254_R04_0_Msk (0x1fUL << LCD_PAL254_R04_0_Pos) /*!< LCD PAL254: R04_0 Mask */
+#define LCD_PAL254_G04_0_Pos 5 /*!< LCD PAL254: G04_0 Position */
+#define LCD_PAL254_G04_0_Msk (0x1fUL << LCD_PAL254_G04_0_Pos) /*!< LCD PAL254: G04_0 Mask */
+#define LCD_PAL254_B04_0_Pos 10 /*!< LCD PAL254: B04_0 Position */
+#define LCD_PAL254_B04_0_Msk (0x1fUL << LCD_PAL254_B04_0_Pos) /*!< LCD PAL254: B04_0 Mask */
+#define LCD_PAL254_I0_Pos 15 /*!< LCD PAL254: I0 Position */
+#define LCD_PAL254_I0_Msk (0x01UL << LCD_PAL254_I0_Pos) /*!< LCD PAL254: I0 Mask */
+#define LCD_PAL254_R14_0_Pos 16 /*!< LCD PAL254: R14_0 Position */
+#define LCD_PAL254_R14_0_Msk (0x1fUL << LCD_PAL254_R14_0_Pos) /*!< LCD PAL254: R14_0 Mask */
+#define LCD_PAL254_G14_0_Pos 21 /*!< LCD PAL254: G14_0 Position */
+#define LCD_PAL254_G14_0_Msk (0x1fUL << LCD_PAL254_G14_0_Pos) /*!< LCD PAL254: G14_0 Mask */
+#define LCD_PAL254_B14_0_Pos 26 /*!< LCD PAL254: B14_0 Position */
+#define LCD_PAL254_B14_0_Msk (0x1fUL << LCD_PAL254_B14_0_Pos) /*!< LCD PAL254: B14_0 Mask */
+#define LCD_PAL254_I1_Pos 31 /*!< LCD PAL254: I1 Position */
+#define LCD_PAL254_I1_Msk (0x01UL << LCD_PAL254_I1_Pos) /*!< LCD PAL254: I1 Mask */
+
+// --------------------------------------- LCD_PAL255 -------------------------------------------
+#define LCD_PAL255_R04_0_Pos 0 /*!< LCD PAL255: R04_0 Position */
+#define LCD_PAL255_R04_0_Msk (0x1fUL << LCD_PAL255_R04_0_Pos) /*!< LCD PAL255: R04_0 Mask */
+#define LCD_PAL255_G04_0_Pos 5 /*!< LCD PAL255: G04_0 Position */
+#define LCD_PAL255_G04_0_Msk (0x1fUL << LCD_PAL255_G04_0_Pos) /*!< LCD PAL255: G04_0 Mask */
+#define LCD_PAL255_B04_0_Pos 10 /*!< LCD PAL255: B04_0 Position */
+#define LCD_PAL255_B04_0_Msk (0x1fUL << LCD_PAL255_B04_0_Pos) /*!< LCD PAL255: B04_0 Mask */
+#define LCD_PAL255_I0_Pos 15 /*!< LCD PAL255: I0 Position */
+#define LCD_PAL255_I0_Msk (0x01UL << LCD_PAL255_I0_Pos) /*!< LCD PAL255: I0 Mask */
+#define LCD_PAL255_R14_0_Pos 16 /*!< LCD PAL255: R14_0 Position */
+#define LCD_PAL255_R14_0_Msk (0x1fUL << LCD_PAL255_R14_0_Pos) /*!< LCD PAL255: R14_0 Mask */
+#define LCD_PAL255_G14_0_Pos 21 /*!< LCD PAL255: G14_0 Position */
+#define LCD_PAL255_G14_0_Msk (0x1fUL << LCD_PAL255_G14_0_Pos) /*!< LCD PAL255: G14_0 Mask */
+#define LCD_PAL255_B14_0_Pos 26 /*!< LCD PAL255: B14_0 Position */
+#define LCD_PAL255_B14_0_Msk (0x1fUL << LCD_PAL255_B14_0_Pos) /*!< LCD PAL255: B14_0 Mask */
+#define LCD_PAL255_I1_Pos 31 /*!< LCD PAL255: I1 Position */
+#define LCD_PAL255_I1_Msk (0x01UL << LCD_PAL255_I1_Pos) /*!< LCD PAL255: I1 Mask */
+
+// -------------------------------------- LCD_CRSR_IMG0 -----------------------------------------
+#define LCD_CRSR_IMG0_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG0: CRSR_IMG Position */
+#define LCD_CRSR_IMG0_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos) /*!< LCD CRSR_IMG0: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG1 -----------------------------------------
+#define LCD_CRSR_IMG1_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG1: CRSR_IMG Position */
+#define LCD_CRSR_IMG1_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos) /*!< LCD CRSR_IMG1: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG2 -----------------------------------------
+#define LCD_CRSR_IMG2_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG2: CRSR_IMG Position */
+#define LCD_CRSR_IMG2_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos) /*!< LCD CRSR_IMG2: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG3 -----------------------------------------
+#define LCD_CRSR_IMG3_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG3: CRSR_IMG Position */
+#define LCD_CRSR_IMG3_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos) /*!< LCD CRSR_IMG3: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG4 -----------------------------------------
+#define LCD_CRSR_IMG4_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG4: CRSR_IMG Position */
+#define LCD_CRSR_IMG4_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos) /*!< LCD CRSR_IMG4: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG5 -----------------------------------------
+#define LCD_CRSR_IMG5_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG5: CRSR_IMG Position */
+#define LCD_CRSR_IMG5_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos) /*!< LCD CRSR_IMG5: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG6 -----------------------------------------
+#define LCD_CRSR_IMG6_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG6: CRSR_IMG Position */
+#define LCD_CRSR_IMG6_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos) /*!< LCD CRSR_IMG6: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG7 -----------------------------------------
+#define LCD_CRSR_IMG7_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG7: CRSR_IMG Position */
+#define LCD_CRSR_IMG7_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos) /*!< LCD CRSR_IMG7: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG8 -----------------------------------------
+#define LCD_CRSR_IMG8_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG8: CRSR_IMG Position */
+#define LCD_CRSR_IMG8_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos) /*!< LCD CRSR_IMG8: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG9 -----------------------------------------
+#define LCD_CRSR_IMG9_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG9: CRSR_IMG Position */
+#define LCD_CRSR_IMG9_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos) /*!< LCD CRSR_IMG9: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG10 -----------------------------------------
+#define LCD_CRSR_IMG10_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG10: CRSR_IMG Position */
+#define LCD_CRSR_IMG10_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos) /*!< LCD CRSR_IMG10: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG11 -----------------------------------------
+#define LCD_CRSR_IMG11_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG11: CRSR_IMG Position */
+#define LCD_CRSR_IMG11_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos) /*!< LCD CRSR_IMG11: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG12 -----------------------------------------
+#define LCD_CRSR_IMG12_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG12: CRSR_IMG Position */
+#define LCD_CRSR_IMG12_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos) /*!< LCD CRSR_IMG12: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG13 -----------------------------------------
+#define LCD_CRSR_IMG13_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG13: CRSR_IMG Position */
+#define LCD_CRSR_IMG13_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos) /*!< LCD CRSR_IMG13: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG14 -----------------------------------------
+#define LCD_CRSR_IMG14_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG14: CRSR_IMG Position */
+#define LCD_CRSR_IMG14_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos) /*!< LCD CRSR_IMG14: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG15 -----------------------------------------
+#define LCD_CRSR_IMG15_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG15: CRSR_IMG Position */
+#define LCD_CRSR_IMG15_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos) /*!< LCD CRSR_IMG15: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG16 -----------------------------------------
+#define LCD_CRSR_IMG16_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG16: CRSR_IMG Position */
+#define LCD_CRSR_IMG16_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos) /*!< LCD CRSR_IMG16: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG17 -----------------------------------------
+#define LCD_CRSR_IMG17_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG17: CRSR_IMG Position */
+#define LCD_CRSR_IMG17_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos) /*!< LCD CRSR_IMG17: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG18 -----------------------------------------
+#define LCD_CRSR_IMG18_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG18: CRSR_IMG Position */
+#define LCD_CRSR_IMG18_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos) /*!< LCD CRSR_IMG18: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG19 -----------------------------------------
+#define LCD_CRSR_IMG19_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG19: CRSR_IMG Position */
+#define LCD_CRSR_IMG19_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos) /*!< LCD CRSR_IMG19: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG20 -----------------------------------------
+#define LCD_CRSR_IMG20_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG20: CRSR_IMG Position */
+#define LCD_CRSR_IMG20_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos) /*!< LCD CRSR_IMG20: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG21 -----------------------------------------
+#define LCD_CRSR_IMG21_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG21: CRSR_IMG Position */
+#define LCD_CRSR_IMG21_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos) /*!< LCD CRSR_IMG21: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG22 -----------------------------------------
+#define LCD_CRSR_IMG22_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG22: CRSR_IMG Position */
+#define LCD_CRSR_IMG22_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos) /*!< LCD CRSR_IMG22: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG23 -----------------------------------------
+#define LCD_CRSR_IMG23_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG23: CRSR_IMG Position */
+#define LCD_CRSR_IMG23_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos) /*!< LCD CRSR_IMG23: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG24 -----------------------------------------
+#define LCD_CRSR_IMG24_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG24: CRSR_IMG Position */
+#define LCD_CRSR_IMG24_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos) /*!< LCD CRSR_IMG24: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG25 -----------------------------------------
+#define LCD_CRSR_IMG25_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG25: CRSR_IMG Position */
+#define LCD_CRSR_IMG25_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos) /*!< LCD CRSR_IMG25: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG26 -----------------------------------------
+#define LCD_CRSR_IMG26_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG26: CRSR_IMG Position */
+#define LCD_CRSR_IMG26_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos) /*!< LCD CRSR_IMG26: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG27 -----------------------------------------
+#define LCD_CRSR_IMG27_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG27: CRSR_IMG Position */
+#define LCD_CRSR_IMG27_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos) /*!< LCD CRSR_IMG27: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG28 -----------------------------------------
+#define LCD_CRSR_IMG28_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG28: CRSR_IMG Position */
+#define LCD_CRSR_IMG28_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos) /*!< LCD CRSR_IMG28: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG29 -----------------------------------------
+#define LCD_CRSR_IMG29_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG29: CRSR_IMG Position */
+#define LCD_CRSR_IMG29_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos) /*!< LCD CRSR_IMG29: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG30 -----------------------------------------
+#define LCD_CRSR_IMG30_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG30: CRSR_IMG Position */
+#define LCD_CRSR_IMG30_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos) /*!< LCD CRSR_IMG30: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG31 -----------------------------------------
+#define LCD_CRSR_IMG31_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG31: CRSR_IMG Position */
+#define LCD_CRSR_IMG31_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos) /*!< LCD CRSR_IMG31: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG32 -----------------------------------------
+#define LCD_CRSR_IMG32_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG32: CRSR_IMG Position */
+#define LCD_CRSR_IMG32_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos) /*!< LCD CRSR_IMG32: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG33 -----------------------------------------
+#define LCD_CRSR_IMG33_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG33: CRSR_IMG Position */
+#define LCD_CRSR_IMG33_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos) /*!< LCD CRSR_IMG33: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG34 -----------------------------------------
+#define LCD_CRSR_IMG34_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG34: CRSR_IMG Position */
+#define LCD_CRSR_IMG34_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos) /*!< LCD CRSR_IMG34: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG35 -----------------------------------------
+#define LCD_CRSR_IMG35_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG35: CRSR_IMG Position */
+#define LCD_CRSR_IMG35_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos) /*!< LCD CRSR_IMG35: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG36 -----------------------------------------
+#define LCD_CRSR_IMG36_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG36: CRSR_IMG Position */
+#define LCD_CRSR_IMG36_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos) /*!< LCD CRSR_IMG36: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG37 -----------------------------------------
+#define LCD_CRSR_IMG37_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG37: CRSR_IMG Position */
+#define LCD_CRSR_IMG37_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos) /*!< LCD CRSR_IMG37: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG38 -----------------------------------------
+#define LCD_CRSR_IMG38_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG38: CRSR_IMG Position */
+#define LCD_CRSR_IMG38_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos) /*!< LCD CRSR_IMG38: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG39 -----------------------------------------
+#define LCD_CRSR_IMG39_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG39: CRSR_IMG Position */
+#define LCD_CRSR_IMG39_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos) /*!< LCD CRSR_IMG39: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG40 -----------------------------------------
+#define LCD_CRSR_IMG40_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG40: CRSR_IMG Position */
+#define LCD_CRSR_IMG40_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos) /*!< LCD CRSR_IMG40: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG41 -----------------------------------------
+#define LCD_CRSR_IMG41_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG41: CRSR_IMG Position */
+#define LCD_CRSR_IMG41_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos) /*!< LCD CRSR_IMG41: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG42 -----------------------------------------
+#define LCD_CRSR_IMG42_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG42: CRSR_IMG Position */
+#define LCD_CRSR_IMG42_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos) /*!< LCD CRSR_IMG42: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG43 -----------------------------------------
+#define LCD_CRSR_IMG43_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG43: CRSR_IMG Position */
+#define LCD_CRSR_IMG43_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos) /*!< LCD CRSR_IMG43: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG44 -----------------------------------------
+#define LCD_CRSR_IMG44_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG44: CRSR_IMG Position */
+#define LCD_CRSR_IMG44_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos) /*!< LCD CRSR_IMG44: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG45 -----------------------------------------
+#define LCD_CRSR_IMG45_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG45: CRSR_IMG Position */
+#define LCD_CRSR_IMG45_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos) /*!< LCD CRSR_IMG45: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG46 -----------------------------------------
+#define LCD_CRSR_IMG46_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG46: CRSR_IMG Position */
+#define LCD_CRSR_IMG46_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos) /*!< LCD CRSR_IMG46: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG47 -----------------------------------------
+#define LCD_CRSR_IMG47_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG47: CRSR_IMG Position */
+#define LCD_CRSR_IMG47_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos) /*!< LCD CRSR_IMG47: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG48 -----------------------------------------
+#define LCD_CRSR_IMG48_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG48: CRSR_IMG Position */
+#define LCD_CRSR_IMG48_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos) /*!< LCD CRSR_IMG48: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG49 -----------------------------------------
+#define LCD_CRSR_IMG49_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG49: CRSR_IMG Position */
+#define LCD_CRSR_IMG49_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos) /*!< LCD CRSR_IMG49: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG50 -----------------------------------------
+#define LCD_CRSR_IMG50_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG50: CRSR_IMG Position */
+#define LCD_CRSR_IMG50_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos) /*!< LCD CRSR_IMG50: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG51 -----------------------------------------
+#define LCD_CRSR_IMG51_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG51: CRSR_IMG Position */
+#define LCD_CRSR_IMG51_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos) /*!< LCD CRSR_IMG51: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG52 -----------------------------------------
+#define LCD_CRSR_IMG52_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG52: CRSR_IMG Position */
+#define LCD_CRSR_IMG52_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos) /*!< LCD CRSR_IMG52: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG53 -----------------------------------------
+#define LCD_CRSR_IMG53_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG53: CRSR_IMG Position */
+#define LCD_CRSR_IMG53_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos) /*!< LCD CRSR_IMG53: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG54 -----------------------------------------
+#define LCD_CRSR_IMG54_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG54: CRSR_IMG Position */
+#define LCD_CRSR_IMG54_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos) /*!< LCD CRSR_IMG54: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG55 -----------------------------------------
+#define LCD_CRSR_IMG55_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG55: CRSR_IMG Position */
+#define LCD_CRSR_IMG55_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos) /*!< LCD CRSR_IMG55: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG56 -----------------------------------------
+#define LCD_CRSR_IMG56_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG56: CRSR_IMG Position */
+#define LCD_CRSR_IMG56_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos) /*!< LCD CRSR_IMG56: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG57 -----------------------------------------
+#define LCD_CRSR_IMG57_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG57: CRSR_IMG Position */
+#define LCD_CRSR_IMG57_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos) /*!< LCD CRSR_IMG57: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG58 -----------------------------------------
+#define LCD_CRSR_IMG58_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG58: CRSR_IMG Position */
+#define LCD_CRSR_IMG58_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos) /*!< LCD CRSR_IMG58: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG59 -----------------------------------------
+#define LCD_CRSR_IMG59_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG59: CRSR_IMG Position */
+#define LCD_CRSR_IMG59_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos) /*!< LCD CRSR_IMG59: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG60 -----------------------------------------
+#define LCD_CRSR_IMG60_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG60: CRSR_IMG Position */
+#define LCD_CRSR_IMG60_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos) /*!< LCD CRSR_IMG60: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG61 -----------------------------------------
+#define LCD_CRSR_IMG61_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG61: CRSR_IMG Position */
+#define LCD_CRSR_IMG61_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos) /*!< LCD CRSR_IMG61: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG62 -----------------------------------------
+#define LCD_CRSR_IMG62_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG62: CRSR_IMG Position */
+#define LCD_CRSR_IMG62_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos) /*!< LCD CRSR_IMG62: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG63 -----------------------------------------
+#define LCD_CRSR_IMG63_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG63: CRSR_IMG Position */
+#define LCD_CRSR_IMG63_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos) /*!< LCD CRSR_IMG63: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG64 -----------------------------------------
+#define LCD_CRSR_IMG64_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG64: CRSR_IMG Position */
+#define LCD_CRSR_IMG64_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos) /*!< LCD CRSR_IMG64: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG65 -----------------------------------------
+#define LCD_CRSR_IMG65_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG65: CRSR_IMG Position */
+#define LCD_CRSR_IMG65_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos) /*!< LCD CRSR_IMG65: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG66 -----------------------------------------
+#define LCD_CRSR_IMG66_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG66: CRSR_IMG Position */
+#define LCD_CRSR_IMG66_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos) /*!< LCD CRSR_IMG66: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG67 -----------------------------------------
+#define LCD_CRSR_IMG67_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG67: CRSR_IMG Position */
+#define LCD_CRSR_IMG67_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos) /*!< LCD CRSR_IMG67: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG68 -----------------------------------------
+#define LCD_CRSR_IMG68_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG68: CRSR_IMG Position */
+#define LCD_CRSR_IMG68_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos) /*!< LCD CRSR_IMG68: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG69 -----------------------------------------
+#define LCD_CRSR_IMG69_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG69: CRSR_IMG Position */
+#define LCD_CRSR_IMG69_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos) /*!< LCD CRSR_IMG69: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG70 -----------------------------------------
+#define LCD_CRSR_IMG70_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG70: CRSR_IMG Position */
+#define LCD_CRSR_IMG70_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos) /*!< LCD CRSR_IMG70: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG71 -----------------------------------------
+#define LCD_CRSR_IMG71_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG71: CRSR_IMG Position */
+#define LCD_CRSR_IMG71_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos) /*!< LCD CRSR_IMG71: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG72 -----------------------------------------
+#define LCD_CRSR_IMG72_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG72: CRSR_IMG Position */
+#define LCD_CRSR_IMG72_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos) /*!< LCD CRSR_IMG72: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG73 -----------------------------------------
+#define LCD_CRSR_IMG73_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG73: CRSR_IMG Position */
+#define LCD_CRSR_IMG73_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos) /*!< LCD CRSR_IMG73: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG74 -----------------------------------------
+#define LCD_CRSR_IMG74_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG74: CRSR_IMG Position */
+#define LCD_CRSR_IMG74_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos) /*!< LCD CRSR_IMG74: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG75 -----------------------------------------
+#define LCD_CRSR_IMG75_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG75: CRSR_IMG Position */
+#define LCD_CRSR_IMG75_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos) /*!< LCD CRSR_IMG75: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG76 -----------------------------------------
+#define LCD_CRSR_IMG76_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG76: CRSR_IMG Position */
+#define LCD_CRSR_IMG76_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos) /*!< LCD CRSR_IMG76: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG77 -----------------------------------------
+#define LCD_CRSR_IMG77_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG77: CRSR_IMG Position */
+#define LCD_CRSR_IMG77_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos) /*!< LCD CRSR_IMG77: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG78 -----------------------------------------
+#define LCD_CRSR_IMG78_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG78: CRSR_IMG Position */
+#define LCD_CRSR_IMG78_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos) /*!< LCD CRSR_IMG78: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG79 -----------------------------------------
+#define LCD_CRSR_IMG79_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG79: CRSR_IMG Position */
+#define LCD_CRSR_IMG79_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos) /*!< LCD CRSR_IMG79: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG80 -----------------------------------------
+#define LCD_CRSR_IMG80_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG80: CRSR_IMG Position */
+#define LCD_CRSR_IMG80_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos) /*!< LCD CRSR_IMG80: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG81 -----------------------------------------
+#define LCD_CRSR_IMG81_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG81: CRSR_IMG Position */
+#define LCD_CRSR_IMG81_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos) /*!< LCD CRSR_IMG81: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG82 -----------------------------------------
+#define LCD_CRSR_IMG82_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG82: CRSR_IMG Position */
+#define LCD_CRSR_IMG82_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos) /*!< LCD CRSR_IMG82: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG83 -----------------------------------------
+#define LCD_CRSR_IMG83_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG83: CRSR_IMG Position */
+#define LCD_CRSR_IMG83_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos) /*!< LCD CRSR_IMG83: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG84 -----------------------------------------
+#define LCD_CRSR_IMG84_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG84: CRSR_IMG Position */
+#define LCD_CRSR_IMG84_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos) /*!< LCD CRSR_IMG84: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG85 -----------------------------------------
+#define LCD_CRSR_IMG85_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG85: CRSR_IMG Position */
+#define LCD_CRSR_IMG85_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos) /*!< LCD CRSR_IMG85: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG86 -----------------------------------------
+#define LCD_CRSR_IMG86_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG86: CRSR_IMG Position */
+#define LCD_CRSR_IMG86_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos) /*!< LCD CRSR_IMG86: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG87 -----------------------------------------
+#define LCD_CRSR_IMG87_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG87: CRSR_IMG Position */
+#define LCD_CRSR_IMG87_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos) /*!< LCD CRSR_IMG87: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG88 -----------------------------------------
+#define LCD_CRSR_IMG88_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG88: CRSR_IMG Position */
+#define LCD_CRSR_IMG88_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos) /*!< LCD CRSR_IMG88: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG89 -----------------------------------------
+#define LCD_CRSR_IMG89_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG89: CRSR_IMG Position */
+#define LCD_CRSR_IMG89_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos) /*!< LCD CRSR_IMG89: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG90 -----------------------------------------
+#define LCD_CRSR_IMG90_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG90: CRSR_IMG Position */
+#define LCD_CRSR_IMG90_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos) /*!< LCD CRSR_IMG90: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG91 -----------------------------------------
+#define LCD_CRSR_IMG91_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG91: CRSR_IMG Position */
+#define LCD_CRSR_IMG91_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos) /*!< LCD CRSR_IMG91: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG92 -----------------------------------------
+#define LCD_CRSR_IMG92_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG92: CRSR_IMG Position */
+#define LCD_CRSR_IMG92_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos) /*!< LCD CRSR_IMG92: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG93 -----------------------------------------
+#define LCD_CRSR_IMG93_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG93: CRSR_IMG Position */
+#define LCD_CRSR_IMG93_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos) /*!< LCD CRSR_IMG93: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG94 -----------------------------------------
+#define LCD_CRSR_IMG94_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG94: CRSR_IMG Position */
+#define LCD_CRSR_IMG94_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos) /*!< LCD CRSR_IMG94: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG95 -----------------------------------------
+#define LCD_CRSR_IMG95_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG95: CRSR_IMG Position */
+#define LCD_CRSR_IMG95_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos) /*!< LCD CRSR_IMG95: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG96 -----------------------------------------
+#define LCD_CRSR_IMG96_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG96: CRSR_IMG Position */
+#define LCD_CRSR_IMG96_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos) /*!< LCD CRSR_IMG96: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG97 -----------------------------------------
+#define LCD_CRSR_IMG97_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG97: CRSR_IMG Position */
+#define LCD_CRSR_IMG97_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos) /*!< LCD CRSR_IMG97: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG98 -----------------------------------------
+#define LCD_CRSR_IMG98_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG98: CRSR_IMG Position */
+#define LCD_CRSR_IMG98_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos) /*!< LCD CRSR_IMG98: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG99 -----------------------------------------
+#define LCD_CRSR_IMG99_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG99: CRSR_IMG Position */
+#define LCD_CRSR_IMG99_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos) /*!< LCD CRSR_IMG99: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG100 ----------------------------------------
+#define LCD_CRSR_IMG100_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG100: CRSR_IMG Position */
+#define LCD_CRSR_IMG100_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos) /*!< LCD CRSR_IMG100: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG101 ----------------------------------------
+#define LCD_CRSR_IMG101_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG101: CRSR_IMG Position */
+#define LCD_CRSR_IMG101_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos) /*!< LCD CRSR_IMG101: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG102 ----------------------------------------
+#define LCD_CRSR_IMG102_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG102: CRSR_IMG Position */
+#define LCD_CRSR_IMG102_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos) /*!< LCD CRSR_IMG102: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG103 ----------------------------------------
+#define LCD_CRSR_IMG103_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG103: CRSR_IMG Position */
+#define LCD_CRSR_IMG103_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos) /*!< LCD CRSR_IMG103: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG104 ----------------------------------------
+#define LCD_CRSR_IMG104_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG104: CRSR_IMG Position */
+#define LCD_CRSR_IMG104_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos) /*!< LCD CRSR_IMG104: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG105 ----------------------------------------
+#define LCD_CRSR_IMG105_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG105: CRSR_IMG Position */
+#define LCD_CRSR_IMG105_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos) /*!< LCD CRSR_IMG105: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG106 ----------------------------------------
+#define LCD_CRSR_IMG106_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG106: CRSR_IMG Position */
+#define LCD_CRSR_IMG106_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos) /*!< LCD CRSR_IMG106: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG107 ----------------------------------------
+#define LCD_CRSR_IMG107_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG107: CRSR_IMG Position */
+#define LCD_CRSR_IMG107_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos) /*!< LCD CRSR_IMG107: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG108 ----------------------------------------
+#define LCD_CRSR_IMG108_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG108: CRSR_IMG Position */
+#define LCD_CRSR_IMG108_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos) /*!< LCD CRSR_IMG108: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG109 ----------------------------------------
+#define LCD_CRSR_IMG109_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG109: CRSR_IMG Position */
+#define LCD_CRSR_IMG109_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos) /*!< LCD CRSR_IMG109: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG110 ----------------------------------------
+#define LCD_CRSR_IMG110_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG110: CRSR_IMG Position */
+#define LCD_CRSR_IMG110_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos) /*!< LCD CRSR_IMG110: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG111 ----------------------------------------
+#define LCD_CRSR_IMG111_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG111: CRSR_IMG Position */
+#define LCD_CRSR_IMG111_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos) /*!< LCD CRSR_IMG111: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG112 ----------------------------------------
+#define LCD_CRSR_IMG112_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG112: CRSR_IMG Position */
+#define LCD_CRSR_IMG112_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos) /*!< LCD CRSR_IMG112: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG113 ----------------------------------------
+#define LCD_CRSR_IMG113_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG113: CRSR_IMG Position */
+#define LCD_CRSR_IMG113_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos) /*!< LCD CRSR_IMG113: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG114 ----------------------------------------
+#define LCD_CRSR_IMG114_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG114: CRSR_IMG Position */
+#define LCD_CRSR_IMG114_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos) /*!< LCD CRSR_IMG114: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG115 ----------------------------------------
+#define LCD_CRSR_IMG115_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG115: CRSR_IMG Position */
+#define LCD_CRSR_IMG115_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos) /*!< LCD CRSR_IMG115: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG116 ----------------------------------------
+#define LCD_CRSR_IMG116_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG116: CRSR_IMG Position */
+#define LCD_CRSR_IMG116_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos) /*!< LCD CRSR_IMG116: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG117 ----------------------------------------
+#define LCD_CRSR_IMG117_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG117: CRSR_IMG Position */
+#define LCD_CRSR_IMG117_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos) /*!< LCD CRSR_IMG117: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG118 ----------------------------------------
+#define LCD_CRSR_IMG118_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG118: CRSR_IMG Position */
+#define LCD_CRSR_IMG118_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos) /*!< LCD CRSR_IMG118: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG119 ----------------------------------------
+#define LCD_CRSR_IMG119_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG119: CRSR_IMG Position */
+#define LCD_CRSR_IMG119_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos) /*!< LCD CRSR_IMG119: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG120 ----------------------------------------
+#define LCD_CRSR_IMG120_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG120: CRSR_IMG Position */
+#define LCD_CRSR_IMG120_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos) /*!< LCD CRSR_IMG120: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG121 ----------------------------------------
+#define LCD_CRSR_IMG121_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG121: CRSR_IMG Position */
+#define LCD_CRSR_IMG121_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos) /*!< LCD CRSR_IMG121: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG122 ----------------------------------------
+#define LCD_CRSR_IMG122_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG122: CRSR_IMG Position */
+#define LCD_CRSR_IMG122_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos) /*!< LCD CRSR_IMG122: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG123 ----------------------------------------
+#define LCD_CRSR_IMG123_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG123: CRSR_IMG Position */
+#define LCD_CRSR_IMG123_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos) /*!< LCD CRSR_IMG123: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG124 ----------------------------------------
+#define LCD_CRSR_IMG124_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG124: CRSR_IMG Position */
+#define LCD_CRSR_IMG124_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos) /*!< LCD CRSR_IMG124: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG125 ----------------------------------------
+#define LCD_CRSR_IMG125_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG125: CRSR_IMG Position */
+#define LCD_CRSR_IMG125_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos) /*!< LCD CRSR_IMG125: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG126 ----------------------------------------
+#define LCD_CRSR_IMG126_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG126: CRSR_IMG Position */
+#define LCD_CRSR_IMG126_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos) /*!< LCD CRSR_IMG126: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG127 ----------------------------------------
+#define LCD_CRSR_IMG127_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG127: CRSR_IMG Position */
+#define LCD_CRSR_IMG127_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos) /*!< LCD CRSR_IMG127: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG128 ----------------------------------------
+#define LCD_CRSR_IMG128_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG128: CRSR_IMG Position */
+#define LCD_CRSR_IMG128_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos) /*!< LCD CRSR_IMG128: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG129 ----------------------------------------
+#define LCD_CRSR_IMG129_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG129: CRSR_IMG Position */
+#define LCD_CRSR_IMG129_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos) /*!< LCD CRSR_IMG129: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG130 ----------------------------------------
+#define LCD_CRSR_IMG130_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG130: CRSR_IMG Position */
+#define LCD_CRSR_IMG130_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos) /*!< LCD CRSR_IMG130: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG131 ----------------------------------------
+#define LCD_CRSR_IMG131_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG131: CRSR_IMG Position */
+#define LCD_CRSR_IMG131_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos) /*!< LCD CRSR_IMG131: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG132 ----------------------------------------
+#define LCD_CRSR_IMG132_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG132: CRSR_IMG Position */
+#define LCD_CRSR_IMG132_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos) /*!< LCD CRSR_IMG132: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG133 ----------------------------------------
+#define LCD_CRSR_IMG133_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG133: CRSR_IMG Position */
+#define LCD_CRSR_IMG133_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos) /*!< LCD CRSR_IMG133: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG134 ----------------------------------------
+#define LCD_CRSR_IMG134_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG134: CRSR_IMG Position */
+#define LCD_CRSR_IMG134_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos) /*!< LCD CRSR_IMG134: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG135 ----------------------------------------
+#define LCD_CRSR_IMG135_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG135: CRSR_IMG Position */
+#define LCD_CRSR_IMG135_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos) /*!< LCD CRSR_IMG135: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG136 ----------------------------------------
+#define LCD_CRSR_IMG136_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG136: CRSR_IMG Position */
+#define LCD_CRSR_IMG136_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos) /*!< LCD CRSR_IMG136: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG137 ----------------------------------------
+#define LCD_CRSR_IMG137_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG137: CRSR_IMG Position */
+#define LCD_CRSR_IMG137_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos) /*!< LCD CRSR_IMG137: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG138 ----------------------------------------
+#define LCD_CRSR_IMG138_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG138: CRSR_IMG Position */
+#define LCD_CRSR_IMG138_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos) /*!< LCD CRSR_IMG138: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG139 ----------------------------------------
+#define LCD_CRSR_IMG139_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG139: CRSR_IMG Position */
+#define LCD_CRSR_IMG139_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos) /*!< LCD CRSR_IMG139: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG140 ----------------------------------------
+#define LCD_CRSR_IMG140_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG140: CRSR_IMG Position */
+#define LCD_CRSR_IMG140_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos) /*!< LCD CRSR_IMG140: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG141 ----------------------------------------
+#define LCD_CRSR_IMG141_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG141: CRSR_IMG Position */
+#define LCD_CRSR_IMG141_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos) /*!< LCD CRSR_IMG141: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG142 ----------------------------------------
+#define LCD_CRSR_IMG142_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG142: CRSR_IMG Position */
+#define LCD_CRSR_IMG142_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos) /*!< LCD CRSR_IMG142: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG143 ----------------------------------------
+#define LCD_CRSR_IMG143_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG143: CRSR_IMG Position */
+#define LCD_CRSR_IMG143_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos) /*!< LCD CRSR_IMG143: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG144 ----------------------------------------
+#define LCD_CRSR_IMG144_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG144: CRSR_IMG Position */
+#define LCD_CRSR_IMG144_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos) /*!< LCD CRSR_IMG144: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG145 ----------------------------------------
+#define LCD_CRSR_IMG145_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG145: CRSR_IMG Position */
+#define LCD_CRSR_IMG145_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos) /*!< LCD CRSR_IMG145: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG146 ----------------------------------------
+#define LCD_CRSR_IMG146_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG146: CRSR_IMG Position */
+#define LCD_CRSR_IMG146_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos) /*!< LCD CRSR_IMG146: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG147 ----------------------------------------
+#define LCD_CRSR_IMG147_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG147: CRSR_IMG Position */
+#define LCD_CRSR_IMG147_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos) /*!< LCD CRSR_IMG147: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG148 ----------------------------------------
+#define LCD_CRSR_IMG148_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG148: CRSR_IMG Position */
+#define LCD_CRSR_IMG148_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos) /*!< LCD CRSR_IMG148: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG149 ----------------------------------------
+#define LCD_CRSR_IMG149_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG149: CRSR_IMG Position */
+#define LCD_CRSR_IMG149_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos) /*!< LCD CRSR_IMG149: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG150 ----------------------------------------
+#define LCD_CRSR_IMG150_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG150: CRSR_IMG Position */
+#define LCD_CRSR_IMG150_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos) /*!< LCD CRSR_IMG150: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG151 ----------------------------------------
+#define LCD_CRSR_IMG151_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG151: CRSR_IMG Position */
+#define LCD_CRSR_IMG151_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos) /*!< LCD CRSR_IMG151: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG152 ----------------------------------------
+#define LCD_CRSR_IMG152_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG152: CRSR_IMG Position */
+#define LCD_CRSR_IMG152_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos) /*!< LCD CRSR_IMG152: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG153 ----------------------------------------
+#define LCD_CRSR_IMG153_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG153: CRSR_IMG Position */
+#define LCD_CRSR_IMG153_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos) /*!< LCD CRSR_IMG153: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG154 ----------------------------------------
+#define LCD_CRSR_IMG154_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG154: CRSR_IMG Position */
+#define LCD_CRSR_IMG154_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos) /*!< LCD CRSR_IMG154: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG155 ----------------------------------------
+#define LCD_CRSR_IMG155_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG155: CRSR_IMG Position */
+#define LCD_CRSR_IMG155_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos) /*!< LCD CRSR_IMG155: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG156 ----------------------------------------
+#define LCD_CRSR_IMG156_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG156: CRSR_IMG Position */
+#define LCD_CRSR_IMG156_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos) /*!< LCD CRSR_IMG156: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG157 ----------------------------------------
+#define LCD_CRSR_IMG157_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG157: CRSR_IMG Position */
+#define LCD_CRSR_IMG157_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos) /*!< LCD CRSR_IMG157: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG158 ----------------------------------------
+#define LCD_CRSR_IMG158_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG158: CRSR_IMG Position */
+#define LCD_CRSR_IMG158_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos) /*!< LCD CRSR_IMG158: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG159 ----------------------------------------
+#define LCD_CRSR_IMG159_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG159: CRSR_IMG Position */
+#define LCD_CRSR_IMG159_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos) /*!< LCD CRSR_IMG159: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG160 ----------------------------------------
+#define LCD_CRSR_IMG160_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG160: CRSR_IMG Position */
+#define LCD_CRSR_IMG160_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos) /*!< LCD CRSR_IMG160: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG161 ----------------------------------------
+#define LCD_CRSR_IMG161_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG161: CRSR_IMG Position */
+#define LCD_CRSR_IMG161_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos) /*!< LCD CRSR_IMG161: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG162 ----------------------------------------
+#define LCD_CRSR_IMG162_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG162: CRSR_IMG Position */
+#define LCD_CRSR_IMG162_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos) /*!< LCD CRSR_IMG162: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG163 ----------------------------------------
+#define LCD_CRSR_IMG163_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG163: CRSR_IMG Position */
+#define LCD_CRSR_IMG163_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos) /*!< LCD CRSR_IMG163: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG164 ----------------------------------------
+#define LCD_CRSR_IMG164_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG164: CRSR_IMG Position */
+#define LCD_CRSR_IMG164_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos) /*!< LCD CRSR_IMG164: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG165 ----------------------------------------
+#define LCD_CRSR_IMG165_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG165: CRSR_IMG Position */
+#define LCD_CRSR_IMG165_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos) /*!< LCD CRSR_IMG165: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG166 ----------------------------------------
+#define LCD_CRSR_IMG166_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG166: CRSR_IMG Position */
+#define LCD_CRSR_IMG166_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos) /*!< LCD CRSR_IMG166: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG167 ----------------------------------------
+#define LCD_CRSR_IMG167_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG167: CRSR_IMG Position */
+#define LCD_CRSR_IMG167_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos) /*!< LCD CRSR_IMG167: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG168 ----------------------------------------
+#define LCD_CRSR_IMG168_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG168: CRSR_IMG Position */
+#define LCD_CRSR_IMG168_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos) /*!< LCD CRSR_IMG168: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG169 ----------------------------------------
+#define LCD_CRSR_IMG169_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG169: CRSR_IMG Position */
+#define LCD_CRSR_IMG169_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos) /*!< LCD CRSR_IMG169: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG170 ----------------------------------------
+#define LCD_CRSR_IMG170_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG170: CRSR_IMG Position */
+#define LCD_CRSR_IMG170_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos) /*!< LCD CRSR_IMG170: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG171 ----------------------------------------
+#define LCD_CRSR_IMG171_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG171: CRSR_IMG Position */
+#define LCD_CRSR_IMG171_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos) /*!< LCD CRSR_IMG171: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG172 ----------------------------------------
+#define LCD_CRSR_IMG172_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG172: CRSR_IMG Position */
+#define LCD_CRSR_IMG172_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos) /*!< LCD CRSR_IMG172: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG173 ----------------------------------------
+#define LCD_CRSR_IMG173_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG173: CRSR_IMG Position */
+#define LCD_CRSR_IMG173_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos) /*!< LCD CRSR_IMG173: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG174 ----------------------------------------
+#define LCD_CRSR_IMG174_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG174: CRSR_IMG Position */
+#define LCD_CRSR_IMG174_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos) /*!< LCD CRSR_IMG174: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG175 ----------------------------------------
+#define LCD_CRSR_IMG175_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG175: CRSR_IMG Position */
+#define LCD_CRSR_IMG175_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos) /*!< LCD CRSR_IMG175: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG176 ----------------------------------------
+#define LCD_CRSR_IMG176_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG176: CRSR_IMG Position */
+#define LCD_CRSR_IMG176_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos) /*!< LCD CRSR_IMG176: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG177 ----------------------------------------
+#define LCD_CRSR_IMG177_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG177: CRSR_IMG Position */
+#define LCD_CRSR_IMG177_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos) /*!< LCD CRSR_IMG177: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG178 ----------------------------------------
+#define LCD_CRSR_IMG178_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG178: CRSR_IMG Position */
+#define LCD_CRSR_IMG178_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos) /*!< LCD CRSR_IMG178: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG179 ----------------------------------------
+#define LCD_CRSR_IMG179_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG179: CRSR_IMG Position */
+#define LCD_CRSR_IMG179_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos) /*!< LCD CRSR_IMG179: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG180 ----------------------------------------
+#define LCD_CRSR_IMG180_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG180: CRSR_IMG Position */
+#define LCD_CRSR_IMG180_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos) /*!< LCD CRSR_IMG180: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG181 ----------------------------------------
+#define LCD_CRSR_IMG181_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG181: CRSR_IMG Position */
+#define LCD_CRSR_IMG181_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos) /*!< LCD CRSR_IMG181: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG182 ----------------------------------------
+#define LCD_CRSR_IMG182_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG182: CRSR_IMG Position */
+#define LCD_CRSR_IMG182_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos) /*!< LCD CRSR_IMG182: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG183 ----------------------------------------
+#define LCD_CRSR_IMG183_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG183: CRSR_IMG Position */
+#define LCD_CRSR_IMG183_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos) /*!< LCD CRSR_IMG183: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG184 ----------------------------------------
+#define LCD_CRSR_IMG184_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG184: CRSR_IMG Position */
+#define LCD_CRSR_IMG184_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos) /*!< LCD CRSR_IMG184: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG185 ----------------------------------------
+#define LCD_CRSR_IMG185_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG185: CRSR_IMG Position */
+#define LCD_CRSR_IMG185_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos) /*!< LCD CRSR_IMG185: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG186 ----------------------------------------
+#define LCD_CRSR_IMG186_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG186: CRSR_IMG Position */
+#define LCD_CRSR_IMG186_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos) /*!< LCD CRSR_IMG186: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG187 ----------------------------------------
+#define LCD_CRSR_IMG187_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG187: CRSR_IMG Position */
+#define LCD_CRSR_IMG187_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos) /*!< LCD CRSR_IMG187: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG188 ----------------------------------------
+#define LCD_CRSR_IMG188_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG188: CRSR_IMG Position */
+#define LCD_CRSR_IMG188_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos) /*!< LCD CRSR_IMG188: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG189 ----------------------------------------
+#define LCD_CRSR_IMG189_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG189: CRSR_IMG Position */
+#define LCD_CRSR_IMG189_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos) /*!< LCD CRSR_IMG189: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG190 ----------------------------------------
+#define LCD_CRSR_IMG190_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG190: CRSR_IMG Position */
+#define LCD_CRSR_IMG190_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos) /*!< LCD CRSR_IMG190: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG191 ----------------------------------------
+#define LCD_CRSR_IMG191_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG191: CRSR_IMG Position */
+#define LCD_CRSR_IMG191_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos) /*!< LCD CRSR_IMG191: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG192 ----------------------------------------
+#define LCD_CRSR_IMG192_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG192: CRSR_IMG Position */
+#define LCD_CRSR_IMG192_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos) /*!< LCD CRSR_IMG192: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG193 ----------------------------------------
+#define LCD_CRSR_IMG193_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG193: CRSR_IMG Position */
+#define LCD_CRSR_IMG193_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos) /*!< LCD CRSR_IMG193: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG194 ----------------------------------------
+#define LCD_CRSR_IMG194_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG194: CRSR_IMG Position */
+#define LCD_CRSR_IMG194_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos) /*!< LCD CRSR_IMG194: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG195 ----------------------------------------
+#define LCD_CRSR_IMG195_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG195: CRSR_IMG Position */
+#define LCD_CRSR_IMG195_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos) /*!< LCD CRSR_IMG195: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG196 ----------------------------------------
+#define LCD_CRSR_IMG196_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG196: CRSR_IMG Position */
+#define LCD_CRSR_IMG196_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos) /*!< LCD CRSR_IMG196: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG197 ----------------------------------------
+#define LCD_CRSR_IMG197_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG197: CRSR_IMG Position */
+#define LCD_CRSR_IMG197_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos) /*!< LCD CRSR_IMG197: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG198 ----------------------------------------
+#define LCD_CRSR_IMG198_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG198: CRSR_IMG Position */
+#define LCD_CRSR_IMG198_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos) /*!< LCD CRSR_IMG198: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG199 ----------------------------------------
+#define LCD_CRSR_IMG199_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG199: CRSR_IMG Position */
+#define LCD_CRSR_IMG199_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos) /*!< LCD CRSR_IMG199: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG200 ----------------------------------------
+#define LCD_CRSR_IMG200_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG200: CRSR_IMG Position */
+#define LCD_CRSR_IMG200_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos) /*!< LCD CRSR_IMG200: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG201 ----------------------------------------
+#define LCD_CRSR_IMG201_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG201: CRSR_IMG Position */
+#define LCD_CRSR_IMG201_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos) /*!< LCD CRSR_IMG201: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG202 ----------------------------------------
+#define LCD_CRSR_IMG202_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG202: CRSR_IMG Position */
+#define LCD_CRSR_IMG202_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos) /*!< LCD CRSR_IMG202: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG203 ----------------------------------------
+#define LCD_CRSR_IMG203_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG203: CRSR_IMG Position */
+#define LCD_CRSR_IMG203_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos) /*!< LCD CRSR_IMG203: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG204 ----------------------------------------
+#define LCD_CRSR_IMG204_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG204: CRSR_IMG Position */
+#define LCD_CRSR_IMG204_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos) /*!< LCD CRSR_IMG204: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG205 ----------------------------------------
+#define LCD_CRSR_IMG205_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG205: CRSR_IMG Position */
+#define LCD_CRSR_IMG205_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos) /*!< LCD CRSR_IMG205: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG206 ----------------------------------------
+#define LCD_CRSR_IMG206_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG206: CRSR_IMG Position */
+#define LCD_CRSR_IMG206_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos) /*!< LCD CRSR_IMG206: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG207 ----------------------------------------
+#define LCD_CRSR_IMG207_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG207: CRSR_IMG Position */
+#define LCD_CRSR_IMG207_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos) /*!< LCD CRSR_IMG207: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG208 ----------------------------------------
+#define LCD_CRSR_IMG208_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG208: CRSR_IMG Position */
+#define LCD_CRSR_IMG208_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos) /*!< LCD CRSR_IMG208: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG209 ----------------------------------------
+#define LCD_CRSR_IMG209_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG209: CRSR_IMG Position */
+#define LCD_CRSR_IMG209_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos) /*!< LCD CRSR_IMG209: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG210 ----------------------------------------
+#define LCD_CRSR_IMG210_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG210: CRSR_IMG Position */
+#define LCD_CRSR_IMG210_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos) /*!< LCD CRSR_IMG210: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG211 ----------------------------------------
+#define LCD_CRSR_IMG211_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG211: CRSR_IMG Position */
+#define LCD_CRSR_IMG211_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos) /*!< LCD CRSR_IMG211: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG212 ----------------------------------------
+#define LCD_CRSR_IMG212_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG212: CRSR_IMG Position */
+#define LCD_CRSR_IMG212_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos) /*!< LCD CRSR_IMG212: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG213 ----------------------------------------
+#define LCD_CRSR_IMG213_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG213: CRSR_IMG Position */
+#define LCD_CRSR_IMG213_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos) /*!< LCD CRSR_IMG213: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG214 ----------------------------------------
+#define LCD_CRSR_IMG214_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG214: CRSR_IMG Position */
+#define LCD_CRSR_IMG214_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos) /*!< LCD CRSR_IMG214: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG215 ----------------------------------------
+#define LCD_CRSR_IMG215_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG215: CRSR_IMG Position */
+#define LCD_CRSR_IMG215_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos) /*!< LCD CRSR_IMG215: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG216 ----------------------------------------
+#define LCD_CRSR_IMG216_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG216: CRSR_IMG Position */
+#define LCD_CRSR_IMG216_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos) /*!< LCD CRSR_IMG216: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG217 ----------------------------------------
+#define LCD_CRSR_IMG217_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG217: CRSR_IMG Position */
+#define LCD_CRSR_IMG217_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos) /*!< LCD CRSR_IMG217: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG218 ----------------------------------------
+#define LCD_CRSR_IMG218_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG218: CRSR_IMG Position */
+#define LCD_CRSR_IMG218_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos) /*!< LCD CRSR_IMG218: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG219 ----------------------------------------
+#define LCD_CRSR_IMG219_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG219: CRSR_IMG Position */
+#define LCD_CRSR_IMG219_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos) /*!< LCD CRSR_IMG219: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG220 ----------------------------------------
+#define LCD_CRSR_IMG220_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG220: CRSR_IMG Position */
+#define LCD_CRSR_IMG220_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos) /*!< LCD CRSR_IMG220: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG221 ----------------------------------------
+#define LCD_CRSR_IMG221_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG221: CRSR_IMG Position */
+#define LCD_CRSR_IMG221_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos) /*!< LCD CRSR_IMG221: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG222 ----------------------------------------
+#define LCD_CRSR_IMG222_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG222: CRSR_IMG Position */
+#define LCD_CRSR_IMG222_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos) /*!< LCD CRSR_IMG222: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG223 ----------------------------------------
+#define LCD_CRSR_IMG223_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG223: CRSR_IMG Position */
+#define LCD_CRSR_IMG223_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos) /*!< LCD CRSR_IMG223: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG224 ----------------------------------------
+#define LCD_CRSR_IMG224_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG224: CRSR_IMG Position */
+#define LCD_CRSR_IMG224_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos) /*!< LCD CRSR_IMG224: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG225 ----------------------------------------
+#define LCD_CRSR_IMG225_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG225: CRSR_IMG Position */
+#define LCD_CRSR_IMG225_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos) /*!< LCD CRSR_IMG225: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG226 ----------------------------------------
+#define LCD_CRSR_IMG226_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG226: CRSR_IMG Position */
+#define LCD_CRSR_IMG226_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos) /*!< LCD CRSR_IMG226: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG227 ----------------------------------------
+#define LCD_CRSR_IMG227_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG227: CRSR_IMG Position */
+#define LCD_CRSR_IMG227_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos) /*!< LCD CRSR_IMG227: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG228 ----------------------------------------
+#define LCD_CRSR_IMG228_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG228: CRSR_IMG Position */
+#define LCD_CRSR_IMG228_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos) /*!< LCD CRSR_IMG228: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG229 ----------------------------------------
+#define LCD_CRSR_IMG229_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG229: CRSR_IMG Position */
+#define LCD_CRSR_IMG229_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos) /*!< LCD CRSR_IMG229: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG230 ----------------------------------------
+#define LCD_CRSR_IMG230_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG230: CRSR_IMG Position */
+#define LCD_CRSR_IMG230_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos) /*!< LCD CRSR_IMG230: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG231 ----------------------------------------
+#define LCD_CRSR_IMG231_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG231: CRSR_IMG Position */
+#define LCD_CRSR_IMG231_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos) /*!< LCD CRSR_IMG231: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG232 ----------------------------------------
+#define LCD_CRSR_IMG232_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG232: CRSR_IMG Position */
+#define LCD_CRSR_IMG232_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos) /*!< LCD CRSR_IMG232: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG233 ----------------------------------------
+#define LCD_CRSR_IMG233_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG233: CRSR_IMG Position */
+#define LCD_CRSR_IMG233_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos) /*!< LCD CRSR_IMG233: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG234 ----------------------------------------
+#define LCD_CRSR_IMG234_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG234: CRSR_IMG Position */
+#define LCD_CRSR_IMG234_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos) /*!< LCD CRSR_IMG234: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG235 ----------------------------------------
+#define LCD_CRSR_IMG235_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG235: CRSR_IMG Position */
+#define LCD_CRSR_IMG235_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos) /*!< LCD CRSR_IMG235: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG236 ----------------------------------------
+#define LCD_CRSR_IMG236_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG236: CRSR_IMG Position */
+#define LCD_CRSR_IMG236_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos) /*!< LCD CRSR_IMG236: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG237 ----------------------------------------
+#define LCD_CRSR_IMG237_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG237: CRSR_IMG Position */
+#define LCD_CRSR_IMG237_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos) /*!< LCD CRSR_IMG237: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG238 ----------------------------------------
+#define LCD_CRSR_IMG238_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG238: CRSR_IMG Position */
+#define LCD_CRSR_IMG238_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos) /*!< LCD CRSR_IMG238: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG239 ----------------------------------------
+#define LCD_CRSR_IMG239_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG239: CRSR_IMG Position */
+#define LCD_CRSR_IMG239_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos) /*!< LCD CRSR_IMG239: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG240 ----------------------------------------
+#define LCD_CRSR_IMG240_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG240: CRSR_IMG Position */
+#define LCD_CRSR_IMG240_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos) /*!< LCD CRSR_IMG240: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG241 ----------------------------------------
+#define LCD_CRSR_IMG241_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG241: CRSR_IMG Position */
+#define LCD_CRSR_IMG241_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos) /*!< LCD CRSR_IMG241: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG242 ----------------------------------------
+#define LCD_CRSR_IMG242_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG242: CRSR_IMG Position */
+#define LCD_CRSR_IMG242_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos) /*!< LCD CRSR_IMG242: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG243 ----------------------------------------
+#define LCD_CRSR_IMG243_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG243: CRSR_IMG Position */
+#define LCD_CRSR_IMG243_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos) /*!< LCD CRSR_IMG243: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG244 ----------------------------------------
+#define LCD_CRSR_IMG244_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG244: CRSR_IMG Position */
+#define LCD_CRSR_IMG244_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos) /*!< LCD CRSR_IMG244: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG245 ----------------------------------------
+#define LCD_CRSR_IMG245_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG245: CRSR_IMG Position */
+#define LCD_CRSR_IMG245_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos) /*!< LCD CRSR_IMG245: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG246 ----------------------------------------
+#define LCD_CRSR_IMG246_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG246: CRSR_IMG Position */
+#define LCD_CRSR_IMG246_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos) /*!< LCD CRSR_IMG246: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG247 ----------------------------------------
+#define LCD_CRSR_IMG247_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG247: CRSR_IMG Position */
+#define LCD_CRSR_IMG247_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos) /*!< LCD CRSR_IMG247: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG248 ----------------------------------------
+#define LCD_CRSR_IMG248_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG248: CRSR_IMG Position */
+#define LCD_CRSR_IMG248_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos) /*!< LCD CRSR_IMG248: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG249 ----------------------------------------
+#define LCD_CRSR_IMG249_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG249: CRSR_IMG Position */
+#define LCD_CRSR_IMG249_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos) /*!< LCD CRSR_IMG249: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG250 ----------------------------------------
+#define LCD_CRSR_IMG250_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG250: CRSR_IMG Position */
+#define LCD_CRSR_IMG250_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos) /*!< LCD CRSR_IMG250: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG251 ----------------------------------------
+#define LCD_CRSR_IMG251_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG251: CRSR_IMG Position */
+#define LCD_CRSR_IMG251_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos) /*!< LCD CRSR_IMG251: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG252 ----------------------------------------
+#define LCD_CRSR_IMG252_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG252: CRSR_IMG Position */
+#define LCD_CRSR_IMG252_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos) /*!< LCD CRSR_IMG252: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG253 ----------------------------------------
+#define LCD_CRSR_IMG253_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG253: CRSR_IMG Position */
+#define LCD_CRSR_IMG253_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos) /*!< LCD CRSR_IMG253: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG254 ----------------------------------------
+#define LCD_CRSR_IMG254_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG254: CRSR_IMG Position */
+#define LCD_CRSR_IMG254_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos) /*!< LCD CRSR_IMG254: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG255 ----------------------------------------
+#define LCD_CRSR_IMG255_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG255: CRSR_IMG Position */
+#define LCD_CRSR_IMG255_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos) /*!< LCD CRSR_IMG255: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_CTRL -----------------------------------------
+#define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */
+#define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */
+
+// -------------------------------------- LCD_CRSR_CFG ------------------------------------------
+#define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */
+#define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */
+#define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */
+#define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */
+
+// -------------------------------------- LCD_CRSR_PAL0 -----------------------------------------
+#define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */
+#define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */
+#define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */
+#define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */
+#define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */
+#define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */
+
+// -------------------------------------- LCD_CRSR_PAL1 -----------------------------------------
+#define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */
+#define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */
+#define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */
+#define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */
+#define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */
+#define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */
+
+// --------------------------------------- LCD_CRSR_XY ------------------------------------------
+#define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */
+#define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */
+#define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */
+#define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */
+
+// -------------------------------------- LCD_CRSR_CLIP -----------------------------------------
+#define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */
+#define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */
+
+// ------------------------------------- LCD_CRSR_INTMSK ----------------------------------------
+#define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */
+#define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */
+
+// ------------------------------------- LCD_CRSR_INTCLR ----------------------------------------
+#define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */
+#define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */
+
+// ------------------------------------- LCD_CRSR_INTRAW ----------------------------------------
+#define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */
+#define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */
+
+// ------------------------------------ LCD_CRSR_INTSTAT ----------------------------------------
+#define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */
+#define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ETHERNET Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------- ETHERNET_MAC_CONFIG --------------------------------------
+#define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */
+#define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */
+#define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */
+#define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */
+#define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */
+#define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */
+#define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */
+#define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */
+#define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */
+#define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */
+#define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */
+#define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */
+#define ETHERNET_MAC_CONFIG_IPC_Pos 10 /*!< ETHERNET MAC_CONFIG: IPC Position */
+#define ETHERNET_MAC_CONFIG_IPC_Msk (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos) /*!< ETHERNET MAC_CONFIG: IPC Mask */
+#define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */
+#define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */
+#define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */
+#define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */
+#define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */
+#define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */
+#define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */
+#define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */
+#define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */
+#define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */
+#define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */
+#define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */
+#define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */
+#define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */
+#define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */
+#define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */
+#define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */
+#define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */
+#define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */
+#define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */
+
+// -------------------------------- ETHERNET_MAC_FRAME_FILTER -----------------------------------
+#define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */
+#define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos 8 /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos 9 /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */
+
+// ------------------------------- ETHERNET_MAC_HASHTABLE_HIGH ----------------------------------
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */
+
+// ------------------------------- ETHERNET_MAC_HASHTABLE_LOW -----------------------------------
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */
+
+// ---------------------------------- ETHERNET_MAC_MII_ADDR -------------------------------------
+#define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */
+#define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */
+#define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */
+#define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */
+#define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */
+#define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */
+#define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */
+#define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */
+#define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */
+#define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */
+
+// ---------------------------------- ETHERNET_MAC_MII_DATA -------------------------------------
+#define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */
+#define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */
+
+// --------------------------------- ETHERNET_MAC_FLOW_CTRL -------------------------------------
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */
+
+// ---------------------------------- ETHERNET_MAC_VLAN_TAG -------------------------------------
+#define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */
+#define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */
+
+// ----------------------------------- ETHERNET_MAC_DEBUG ---------------------------------------
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */
+#define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */
+#define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */
+
+// -------------------------------- ETHERNET_MAC_RWAKE_FRFLT ------------------------------------
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */
+
+// ------------------------------- ETHERNET_MAC_PMT_CTRL_STAT -----------------------------------
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */
+
+// --------------------------------- ETHERNET_MAC_INTR_MASK -------------------------------------
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */
+
+// --------------------------------- ETHERNET_MAC_ADDR0_HIGH ------------------------------------
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */
+
+// --------------------------------- ETHERNET_MAC_ADDR0_LOW -------------------------------------
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */
+
+// -------------------------------- ETHERNET_MAC_TIMESTP_CTRL -----------------------------------
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */
+
+// ---------------------------------- ETHERNET_DMA_BUS_MODE -------------------------------------
+#define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */
+#define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */
+#define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */
+#define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */
+#define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */
+#define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */
+#define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */
+#define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */
+#define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */
+#define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */
+#define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */
+#define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */
+#define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */
+#define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */
+#define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */
+#define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */
+#define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */
+#define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */
+
+// ----------------------------- ETHERNET_DMA_TRANS_POLL_DEMAND ---------------------------------
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos) /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */
+
+// ------------------------------ ETHERNET_DMA_REC_POLL_DEMAND ----------------------------------
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */
+
+// -------------------------------- ETHERNET_DMA_REC_DES_ADDR -----------------------------------
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */
+
+// ------------------------------- ETHERNET_DMA_TRANS_DES_ADDR ----------------------------------
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */
+
+// ------------------------------------ ETHERNET_DMA_STAT ---------------------------------------
+#define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */
+#define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */
+#define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */
+#define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */
+#define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */
+#define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */
+#define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */
+#define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */
+#define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */
+#define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */
+#define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */
+#define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */
+#define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */
+#define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */
+#define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */
+#define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */
+#define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */
+#define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */
+#define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */
+#define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */
+#define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */
+#define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */
+#define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */
+#define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */
+#define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */
+#define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */
+#define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */
+#define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */
+#define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */
+#define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */
+
+// ---------------------------------- ETHERNET_DMA_OP_MODE --------------------------------------
+#define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */
+#define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */
+#define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */
+#define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */
+#define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */
+#define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */
+#define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */
+#define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */
+#define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */
+#define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */
+#define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */
+#define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */
+#define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */
+#define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */
+#define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */
+#define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */
+#define ETHERNET_DMA_OP_MODE_TSF_Pos 21 /*!< ETHERNET DMA_OP_MODE: TSF Position */
+#define ETHERNET_DMA_OP_MODE_TSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos) /*!< ETHERNET DMA_OP_MODE: TSF Mask */
+#define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */
+#define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */
+#define ETHERNET_DMA_OP_MODE_RSF_Pos 25 /*!< ETHERNET DMA_OP_MODE: RSF Position */
+#define ETHERNET_DMA_OP_MODE_RSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos) /*!< ETHERNET DMA_OP_MODE: RSF Mask */
+#define ETHERNET_DMA_OP_MODE_DT_Pos 26 /*!< ETHERNET DMA_OP_MODE: DT Position */
+#define ETHERNET_DMA_OP_MODE_DT_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos) /*!< ETHERNET DMA_OP_MODE: DT Mask */
+
+// ----------------------------------- ETHERNET_DMA_INT_EN --------------------------------------
+#define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */
+#define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */
+#define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */
+#define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */
+#define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */
+#define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */
+#define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */
+#define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */
+#define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */
+#define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */
+#define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */
+#define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */
+#define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */
+#define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */
+#define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */
+#define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */
+#define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */
+#define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */
+#define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */
+#define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */
+#define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */
+#define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */
+#define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */
+#define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */
+#define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */
+#define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */
+#define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */
+#define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */
+#define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */
+#define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */
+
+// --------------------------------- ETHERNET_DMA_MFRM_BUFOF ------------------------------------
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */
+
+// -------------------------------- ETHERNET_DMA_REC_INT_WDT ------------------------------------
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */
+
+// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_DES ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */
+
+// ------------------------------ ETHERNET_DMA_CURHOST_REC_DES ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */
+
+// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_BUF ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */
+
+// ------------------------------ ETHERNET_DMA_CURHOST_REC_BUF ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ATIMER Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------- ATIMER_DOWNCOUNTER ---------------------------------------
+#define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */
+#define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */
+
+// -------------------------------------- ATIMER_PRESET -----------------------------------------
+#define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */
+#define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */
+
+// -------------------------------------- ATIMER_CLR_EN -----------------------------------------
+#define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */
+#define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */
+
+// -------------------------------------- ATIMER_SET_EN -----------------------------------------
+#define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */
+#define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */
+
+// -------------------------------------- ATIMER_STATUS -----------------------------------------
+#define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */
+#define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */
+
+// -------------------------------------- ATIMER_ENABLE -----------------------------------------
+#define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */
+#define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */
+
+// ------------------------------------- ATIMER_CLR_STAT ----------------------------------------
+#define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */
+#define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */
+
+// ------------------------------------- ATIMER_SET_STAT ----------------------------------------
+#define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */
+#define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- REGFILE Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------ REGFILE_REGFILE0 ----------------------------------------
+#define REGFILE_REGFILE0_REGVAL_Pos 0 /*!< REGFILE REGFILE0: REGVAL Position */
+#define REGFILE_REGFILE0_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos) /*!< REGFILE REGFILE0: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE1 ----------------------------------------
+#define REGFILE_REGFILE1_REGVAL_Pos 0 /*!< REGFILE REGFILE1: REGVAL Position */
+#define REGFILE_REGFILE1_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos) /*!< REGFILE REGFILE1: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE2 ----------------------------------------
+#define REGFILE_REGFILE2_REGVAL_Pos 0 /*!< REGFILE REGFILE2: REGVAL Position */
+#define REGFILE_REGFILE2_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos) /*!< REGFILE REGFILE2: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE3 ----------------------------------------
+#define REGFILE_REGFILE3_REGVAL_Pos 0 /*!< REGFILE REGFILE3: REGVAL Position */
+#define REGFILE_REGFILE3_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos) /*!< REGFILE REGFILE3: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE4 ----------------------------------------
+#define REGFILE_REGFILE4_REGVAL_Pos 0 /*!< REGFILE REGFILE4: REGVAL Position */
+#define REGFILE_REGFILE4_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos) /*!< REGFILE REGFILE4: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE5 ----------------------------------------
+#define REGFILE_REGFILE5_REGVAL_Pos 0 /*!< REGFILE REGFILE5: REGVAL Position */
+#define REGFILE_REGFILE5_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos) /*!< REGFILE REGFILE5: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE6 ----------------------------------------
+#define REGFILE_REGFILE6_REGVAL_Pos 0 /*!< REGFILE REGFILE6: REGVAL Position */
+#define REGFILE_REGFILE6_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos) /*!< REGFILE REGFILE6: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE7 ----------------------------------------
+#define REGFILE_REGFILE7_REGVAL_Pos 0 /*!< REGFILE REGFILE7: REGVAL Position */
+#define REGFILE_REGFILE7_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos) /*!< REGFILE REGFILE7: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE8 ----------------------------------------
+#define REGFILE_REGFILE8_REGVAL_Pos 0 /*!< REGFILE REGFILE8: REGVAL Position */
+#define REGFILE_REGFILE8_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos) /*!< REGFILE REGFILE8: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE9 ----------------------------------------
+#define REGFILE_REGFILE9_REGVAL_Pos 0 /*!< REGFILE REGFILE9: REGVAL Position */
+#define REGFILE_REGFILE9_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos) /*!< REGFILE REGFILE9: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE10 ---------------------------------------
+#define REGFILE_REGFILE10_REGVAL_Pos 0 /*!< REGFILE REGFILE10: REGVAL Position */
+#define REGFILE_REGFILE10_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos) /*!< REGFILE REGFILE10: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE11 ---------------------------------------
+#define REGFILE_REGFILE11_REGVAL_Pos 0 /*!< REGFILE REGFILE11: REGVAL Position */
+#define REGFILE_REGFILE11_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos) /*!< REGFILE REGFILE11: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE12 ---------------------------------------
+#define REGFILE_REGFILE12_REGVAL_Pos 0 /*!< REGFILE REGFILE12: REGVAL Position */
+#define REGFILE_REGFILE12_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos) /*!< REGFILE REGFILE12: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE13 ---------------------------------------
+#define REGFILE_REGFILE13_REGVAL_Pos 0 /*!< REGFILE REGFILE13: REGVAL Position */
+#define REGFILE_REGFILE13_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos) /*!< REGFILE REGFILE13: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE14 ---------------------------------------
+#define REGFILE_REGFILE14_REGVAL_Pos 0 /*!< REGFILE REGFILE14: REGVAL Position */
+#define REGFILE_REGFILE14_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos) /*!< REGFILE REGFILE14: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE15 ---------------------------------------
+#define REGFILE_REGFILE15_REGVAL_Pos 0 /*!< REGFILE REGFILE15: REGVAL Position */
+#define REGFILE_REGFILE15_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos) /*!< REGFILE REGFILE15: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE16 ---------------------------------------
+#define REGFILE_REGFILE16_REGVAL_Pos 0 /*!< REGFILE REGFILE16: REGVAL Position */
+#define REGFILE_REGFILE16_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos) /*!< REGFILE REGFILE16: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE17 ---------------------------------------
+#define REGFILE_REGFILE17_REGVAL_Pos 0 /*!< REGFILE REGFILE17: REGVAL Position */
+#define REGFILE_REGFILE17_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos) /*!< REGFILE REGFILE17: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE18 ---------------------------------------
+#define REGFILE_REGFILE18_REGVAL_Pos 0 /*!< REGFILE REGFILE18: REGVAL Position */
+#define REGFILE_REGFILE18_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos) /*!< REGFILE REGFILE18: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE19 ---------------------------------------
+#define REGFILE_REGFILE19_REGVAL_Pos 0 /*!< REGFILE REGFILE19: REGVAL Position */
+#define REGFILE_REGFILE19_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos) /*!< REGFILE REGFILE19: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE20 ---------------------------------------
+#define REGFILE_REGFILE20_REGVAL_Pos 0 /*!< REGFILE REGFILE20: REGVAL Position */
+#define REGFILE_REGFILE20_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos) /*!< REGFILE REGFILE20: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE21 ---------------------------------------
+#define REGFILE_REGFILE21_REGVAL_Pos 0 /*!< REGFILE REGFILE21: REGVAL Position */
+#define REGFILE_REGFILE21_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos) /*!< REGFILE REGFILE21: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE22 ---------------------------------------
+#define REGFILE_REGFILE22_REGVAL_Pos 0 /*!< REGFILE REGFILE22: REGVAL Position */
+#define REGFILE_REGFILE22_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos) /*!< REGFILE REGFILE22: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE23 ---------------------------------------
+#define REGFILE_REGFILE23_REGVAL_Pos 0 /*!< REGFILE REGFILE23: REGVAL Position */
+#define REGFILE_REGFILE23_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos) /*!< REGFILE REGFILE23: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE24 ---------------------------------------
+#define REGFILE_REGFILE24_REGVAL_Pos 0 /*!< REGFILE REGFILE24: REGVAL Position */
+#define REGFILE_REGFILE24_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos) /*!< REGFILE REGFILE24: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE25 ---------------------------------------
+#define REGFILE_REGFILE25_REGVAL_Pos 0 /*!< REGFILE REGFILE25: REGVAL Position */
+#define REGFILE_REGFILE25_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos) /*!< REGFILE REGFILE25: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE26 ---------------------------------------
+#define REGFILE_REGFILE26_REGVAL_Pos 0 /*!< REGFILE REGFILE26: REGVAL Position */
+#define REGFILE_REGFILE26_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos) /*!< REGFILE REGFILE26: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE27 ---------------------------------------
+#define REGFILE_REGFILE27_REGVAL_Pos 0 /*!< REGFILE REGFILE27: REGVAL Position */
+#define REGFILE_REGFILE27_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos) /*!< REGFILE REGFILE27: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE28 ---------------------------------------
+#define REGFILE_REGFILE28_REGVAL_Pos 0 /*!< REGFILE REGFILE28: REGVAL Position */
+#define REGFILE_REGFILE28_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos) /*!< REGFILE REGFILE28: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE29 ---------------------------------------
+#define REGFILE_REGFILE29_REGVAL_Pos 0 /*!< REGFILE REGFILE29: REGVAL Position */
+#define REGFILE_REGFILE29_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos) /*!< REGFILE REGFILE29: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE30 ---------------------------------------
+#define REGFILE_REGFILE30_REGVAL_Pos 0 /*!< REGFILE REGFILE30: REGVAL Position */
+#define REGFILE_REGFILE30_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos) /*!< REGFILE REGFILE30: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE31 ---------------------------------------
+#define REGFILE_REGFILE31_REGVAL_Pos 0 /*!< REGFILE REGFILE31: REGVAL Position */
+#define REGFILE_REGFILE31_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos) /*!< REGFILE REGFILE31: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE32 ---------------------------------------
+#define REGFILE_REGFILE32_REGVAL_Pos 0 /*!< REGFILE REGFILE32: REGVAL Position */
+#define REGFILE_REGFILE32_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos) /*!< REGFILE REGFILE32: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE33 ---------------------------------------
+#define REGFILE_REGFILE33_REGVAL_Pos 0 /*!< REGFILE REGFILE33: REGVAL Position */
+#define REGFILE_REGFILE33_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos) /*!< REGFILE REGFILE33: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE34 ---------------------------------------
+#define REGFILE_REGFILE34_REGVAL_Pos 0 /*!< REGFILE REGFILE34: REGVAL Position */
+#define REGFILE_REGFILE34_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos) /*!< REGFILE REGFILE34: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE35 ---------------------------------------
+#define REGFILE_REGFILE35_REGVAL_Pos 0 /*!< REGFILE REGFILE35: REGVAL Position */
+#define REGFILE_REGFILE35_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos) /*!< REGFILE REGFILE35: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE36 ---------------------------------------
+#define REGFILE_REGFILE36_REGVAL_Pos 0 /*!< REGFILE REGFILE36: REGVAL Position */
+#define REGFILE_REGFILE36_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos) /*!< REGFILE REGFILE36: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE37 ---------------------------------------
+#define REGFILE_REGFILE37_REGVAL_Pos 0 /*!< REGFILE REGFILE37: REGVAL Position */
+#define REGFILE_REGFILE37_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos) /*!< REGFILE REGFILE37: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE38 ---------------------------------------
+#define REGFILE_REGFILE38_REGVAL_Pos 0 /*!< REGFILE REGFILE38: REGVAL Position */
+#define REGFILE_REGFILE38_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos) /*!< REGFILE REGFILE38: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE39 ---------------------------------------
+#define REGFILE_REGFILE39_REGVAL_Pos 0 /*!< REGFILE REGFILE39: REGVAL Position */
+#define REGFILE_REGFILE39_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos) /*!< REGFILE REGFILE39: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE40 ---------------------------------------
+#define REGFILE_REGFILE40_REGVAL_Pos 0 /*!< REGFILE REGFILE40: REGVAL Position */
+#define REGFILE_REGFILE40_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos) /*!< REGFILE REGFILE40: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE41 ---------------------------------------
+#define REGFILE_REGFILE41_REGVAL_Pos 0 /*!< REGFILE REGFILE41: REGVAL Position */
+#define REGFILE_REGFILE41_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos) /*!< REGFILE REGFILE41: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE42 ---------------------------------------
+#define REGFILE_REGFILE42_REGVAL_Pos 0 /*!< REGFILE REGFILE42: REGVAL Position */
+#define REGFILE_REGFILE42_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos) /*!< REGFILE REGFILE42: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE43 ---------------------------------------
+#define REGFILE_REGFILE43_REGVAL_Pos 0 /*!< REGFILE REGFILE43: REGVAL Position */
+#define REGFILE_REGFILE43_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos) /*!< REGFILE REGFILE43: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE44 ---------------------------------------
+#define REGFILE_REGFILE44_REGVAL_Pos 0 /*!< REGFILE REGFILE44: REGVAL Position */
+#define REGFILE_REGFILE44_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos) /*!< REGFILE REGFILE44: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE45 ---------------------------------------
+#define REGFILE_REGFILE45_REGVAL_Pos 0 /*!< REGFILE REGFILE45: REGVAL Position */
+#define REGFILE_REGFILE45_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos) /*!< REGFILE REGFILE45: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE46 ---------------------------------------
+#define REGFILE_REGFILE46_REGVAL_Pos 0 /*!< REGFILE REGFILE46: REGVAL Position */
+#define REGFILE_REGFILE46_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos) /*!< REGFILE REGFILE46: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE47 ---------------------------------------
+#define REGFILE_REGFILE47_REGVAL_Pos 0 /*!< REGFILE REGFILE47: REGVAL Position */
+#define REGFILE_REGFILE47_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos) /*!< REGFILE REGFILE47: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE48 ---------------------------------------
+#define REGFILE_REGFILE48_REGVAL_Pos 0 /*!< REGFILE REGFILE48: REGVAL Position */
+#define REGFILE_REGFILE48_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos) /*!< REGFILE REGFILE48: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE49 ---------------------------------------
+#define REGFILE_REGFILE49_REGVAL_Pos 0 /*!< REGFILE REGFILE49: REGVAL Position */
+#define REGFILE_REGFILE49_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos) /*!< REGFILE REGFILE49: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE50 ---------------------------------------
+#define REGFILE_REGFILE50_REGVAL_Pos 0 /*!< REGFILE REGFILE50: REGVAL Position */
+#define REGFILE_REGFILE50_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos) /*!< REGFILE REGFILE50: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE51 ---------------------------------------
+#define REGFILE_REGFILE51_REGVAL_Pos 0 /*!< REGFILE REGFILE51: REGVAL Position */
+#define REGFILE_REGFILE51_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos) /*!< REGFILE REGFILE51: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE52 ---------------------------------------
+#define REGFILE_REGFILE52_REGVAL_Pos 0 /*!< REGFILE REGFILE52: REGVAL Position */
+#define REGFILE_REGFILE52_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos) /*!< REGFILE REGFILE52: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE53 ---------------------------------------
+#define REGFILE_REGFILE53_REGVAL_Pos 0 /*!< REGFILE REGFILE53: REGVAL Position */
+#define REGFILE_REGFILE53_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos) /*!< REGFILE REGFILE53: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE54 ---------------------------------------
+#define REGFILE_REGFILE54_REGVAL_Pos 0 /*!< REGFILE REGFILE54: REGVAL Position */
+#define REGFILE_REGFILE54_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos) /*!< REGFILE REGFILE54: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE55 ---------------------------------------
+#define REGFILE_REGFILE55_REGVAL_Pos 0 /*!< REGFILE REGFILE55: REGVAL Position */
+#define REGFILE_REGFILE55_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos) /*!< REGFILE REGFILE55: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE56 ---------------------------------------
+#define REGFILE_REGFILE56_REGVAL_Pos 0 /*!< REGFILE REGFILE56: REGVAL Position */
+#define REGFILE_REGFILE56_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos) /*!< REGFILE REGFILE56: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE57 ---------------------------------------
+#define REGFILE_REGFILE57_REGVAL_Pos 0 /*!< REGFILE REGFILE57: REGVAL Position */
+#define REGFILE_REGFILE57_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos) /*!< REGFILE REGFILE57: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE58 ---------------------------------------
+#define REGFILE_REGFILE58_REGVAL_Pos 0 /*!< REGFILE REGFILE58: REGVAL Position */
+#define REGFILE_REGFILE58_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos) /*!< REGFILE REGFILE58: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE59 ---------------------------------------
+#define REGFILE_REGFILE59_REGVAL_Pos 0 /*!< REGFILE REGFILE59: REGVAL Position */
+#define REGFILE_REGFILE59_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos) /*!< REGFILE REGFILE59: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE60 ---------------------------------------
+#define REGFILE_REGFILE60_REGVAL_Pos 0 /*!< REGFILE REGFILE60: REGVAL Position */
+#define REGFILE_REGFILE60_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos) /*!< REGFILE REGFILE60: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE61 ---------------------------------------
+#define REGFILE_REGFILE61_REGVAL_Pos 0 /*!< REGFILE REGFILE61: REGVAL Position */
+#define REGFILE_REGFILE61_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos) /*!< REGFILE REGFILE61: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE62 ---------------------------------------
+#define REGFILE_REGFILE62_REGVAL_Pos 0 /*!< REGFILE REGFILE62: REGVAL Position */
+#define REGFILE_REGFILE62_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos) /*!< REGFILE REGFILE62: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE63 ---------------------------------------
+#define REGFILE_REGFILE63_REGVAL_Pos 0 /*!< REGFILE REGFILE63: REGVAL Position */
+#define REGFILE_REGFILE63_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos) /*!< REGFILE REGFILE63: REGVAL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------- PMC_PD0_SLEEP0_HW_ENA -------------------------------------
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */
+
+// ----------------------------------- PMC_PD0_SLEEP0_MODE --------------------------------------
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CREG Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- CREG_IRCTRM ------------------------------------------
+#define CREG_IRCTRM_TRM_Pos 0 /*!< CREG IRCTRM: TRM Position */
+#define CREG_IRCTRM_TRM_Msk (0x00000fffUL << CREG_IRCTRM_TRM_Pos) /*!< CREG IRCTRM: TRM Mask */
+
+// --------------------------------------- CREG_CREG0 -------------------------------------------
+#define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */
+#define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */
+#define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */
+#define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */
+#define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */
+#define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */
+#define CREG_CREG0_32KHZPD_Pos 3 /*!< CREG CREG0: 32KHZPD Position */
+#define CREG_CREG0_32KHZPD_Msk (0x01UL << CREG_CREG0_32KHZPD_Pos) /*!< CREG CREG0: 32KHZPD Mask */
+#define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */
+#define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */
+#define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */
+#define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */
+#define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */
+#define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */
+#define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */
+#define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */
+#define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */
+#define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */
+#define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */
+#define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */
+
+// --------------------------------------- CREG_PMUCON ------------------------------------------
+#define CREG_PMUCON_PWRCTRL_Pos 0 /*!< CREG PMUCON: PWRCTRL Position */
+#define CREG_PMUCON_PWRCTRL_Msk (0x000001ffUL << CREG_PMUCON_PWRCTRL_Pos) /*!< CREG PMUCON: PWRCTRL Mask */
+#define CREG_PMUCON_DYNAMICPWRCTRL_Pos 15 /*!< CREG PMUCON: DYNAMICPWRCTRL Position */
+#define CREG_PMUCON_DYNAMICPWRCTRL_Msk (0x01UL << CREG_PMUCON_DYNAMICPWRCTRL_Pos) /*!< CREG PMUCON: DYNAMICPWRCTRL Mask */
+
+// -------------------------------------- CREG_M3MEMMAP -----------------------------------------
+#define CREG_M3MEMMAP_M3MAP_Pos 12 /*!< CREG M3MEMMAP: M3MAP Position */
+#define CREG_M3MEMMAP_M3MAP_Msk (0x000fffffUL << CREG_M3MEMMAP_M3MAP_Pos) /*!< CREG M3MEMMAP: M3MAP Mask */
+
+// --------------------------------------- CREG_CREG5 -------------------------------------------
+#define CREG_CREG5_M3TAPSEL_Pos 6 /*!< CREG CREG5: M3TAPSEL Position */
+#define CREG_CREG5_M3TAPSEL_Msk (0x01UL << CREG_CREG5_M3TAPSEL_Pos) /*!< CREG CREG5: M3TAPSEL Mask */
+
+// --------------------------------------- CREG_DMAMUX ------------------------------------------
+#define CREG_DMAMUX_DMAMUXCH0_Pos 0 /*!< CREG DMAMUX: DMAMUXCH0 Position */
+#define CREG_DMAMUX_DMAMUXCH0_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos) /*!< CREG DMAMUX: DMAMUXCH0 Mask */
+#define CREG_DMAMUX_DMAMUXCH1_Pos 2 /*!< CREG DMAMUX: DMAMUXCH1 Position */
+#define CREG_DMAMUX_DMAMUXCH1_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos) /*!< CREG DMAMUX: DMAMUXCH1 Mask */
+#define CREG_DMAMUX_DMAMUXCH2_Pos 4 /*!< CREG DMAMUX: DMAMUXCH2 Position */
+#define CREG_DMAMUX_DMAMUXCH2_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos) /*!< CREG DMAMUX: DMAMUXCH2 Mask */
+#define CREG_DMAMUX_DMAMUXCH3_Pos 6 /*!< CREG DMAMUX: DMAMUXCH3 Position */
+#define CREG_DMAMUX_DMAMUXCH3_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos) /*!< CREG DMAMUX: DMAMUXCH3 Mask */
+#define CREG_DMAMUX_DMAMUXCH4_Pos 8 /*!< CREG DMAMUX: DMAMUXCH4 Position */
+#define CREG_DMAMUX_DMAMUXCH4_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos) /*!< CREG DMAMUX: DMAMUXCH4 Mask */
+#define CREG_DMAMUX_DMAMUXCH5_Pos 10 /*!< CREG DMAMUX: DMAMUXCH5 Position */
+#define CREG_DMAMUX_DMAMUXCH5_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos) /*!< CREG DMAMUX: DMAMUXCH5 Mask */
+#define CREG_DMAMUX_DMAMUXCH6_Pos 12 /*!< CREG DMAMUX: DMAMUXCH6 Position */
+#define CREG_DMAMUX_DMAMUXCH6_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos) /*!< CREG DMAMUX: DMAMUXCH6 Mask */
+#define CREG_DMAMUX_DMAMUXCH7_Pos 14 /*!< CREG DMAMUX: DMAMUXCH7 Position */
+#define CREG_DMAMUX_DMAMUXCH7_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos) /*!< CREG DMAMUX: DMAMUXCH7 Mask */
+#define CREG_DMAMUX_DMAMUXCH8_Pos 16 /*!< CREG DMAMUX: DMAMUXCH8 Position */
+#define CREG_DMAMUX_DMAMUXCH8_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos) /*!< CREG DMAMUX: DMAMUXCH8 Mask */
+#define CREG_DMAMUX_DMAMUXCH9_Pos 18 /*!< CREG DMAMUX: DMAMUXCH9 Position */
+#define CREG_DMAMUX_DMAMUXCH9_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos) /*!< CREG DMAMUX: DMAMUXCH9 Mask */
+#define CREG_DMAMUX_DMAMUXCH10_Pos 20 /*!< CREG DMAMUX: DMAMUXCH10 Position */
+#define CREG_DMAMUX_DMAMUXCH10_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos) /*!< CREG DMAMUX: DMAMUXCH10 Mask */
+#define CREG_DMAMUX_DMAMUXCH11_Pos 22 /*!< CREG DMAMUX: DMAMUXCH11 Position */
+#define CREG_DMAMUX_DMAMUXCH11_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos) /*!< CREG DMAMUX: DMAMUXCH11 Mask */
+#define CREG_DMAMUX_DMAMUXCH12_Pos 24 /*!< CREG DMAMUX: DMAMUXCH12 Position */
+#define CREG_DMAMUX_DMAMUXCH12_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos) /*!< CREG DMAMUX: DMAMUXCH12 Mask */
+#define CREG_DMAMUX_DMAMUXCH13_Pos 26 /*!< CREG DMAMUX: DMAMUXCH13 Position */
+#define CREG_DMAMUX_DMAMUXCH13_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos) /*!< CREG DMAMUX: DMAMUXCH13 Mask */
+#define CREG_DMAMUX_DMAMUXCH14_Pos 28 /*!< CREG DMAMUX: DMAMUXCH14 Position */
+#define CREG_DMAMUX_DMAMUXCH14_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos) /*!< CREG DMAMUX: DMAMUXCH14 Mask */
+#define CREG_DMAMUX_DMAMUXCH15_Pos 30 /*!< CREG DMAMUX: DMAMUXCH15 Position */
+#define CREG_DMAMUX_DMAMUXCH15_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos) /*!< CREG DMAMUX: DMAMUXCH15 Mask */
+
+// --------------------------------------- CREG_ETBCFG ------------------------------------------
+#define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */
+#define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */
+
+// --------------------------------------- CREG_CREG6 -------------------------------------------
+#define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */
+#define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */
+#define CREG_CREG6_TIMCTRL_Pos 4 /*!< CREG CREG6: TIMCTRL Position */
+#define CREG_CREG6_TIMCTRL_Msk (0x01UL << CREG_CREG6_TIMCTRL_Pos) /*!< CREG CREG6: TIMCTRL Mask */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */
+#define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */
+
+// --------------------------------------- CREG_CHIPID ------------------------------------------
+#define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */
+#define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EVENTROUTER Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------ EVENTROUTER_HILO ----------------------------------------
+#define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */
+#define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */
+#define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */
+#define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */
+#define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */
+#define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */
+#define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */
+#define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */
+#define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */
+#define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */
+#define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */
+#define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */
+#define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */
+#define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */
+#define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */
+#define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */
+#define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */
+#define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */
+#define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */
+#define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */
+#define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */
+#define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */
+#define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */
+#define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */
+#define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */
+#define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */
+#define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */
+#define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */
+#define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */
+#define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */
+#define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */
+#define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */
+#define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */
+#define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */
+#define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */
+#define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */
+
+// ------------------------------------ EVENTROUTER_EDGE ----------------------------------------
+#define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */
+#define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */
+#define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */
+#define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */
+#define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */
+#define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */
+#define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */
+#define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */
+#define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */
+#define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */
+#define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */
+#define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */
+#define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */
+#define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */
+#define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */
+#define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */
+#define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */
+#define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */
+#define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */
+#define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */
+#define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */
+#define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */
+#define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */
+#define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */
+#define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */
+#define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */
+#define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */
+#define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */
+#define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */
+#define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */
+
+// ----------------------------------- EVENTROUTER_CLR_EN ---------------------------------------
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */
+
+// ----------------------------------- EVENTROUTER_SET_EN ---------------------------------------
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */
+
+// ----------------------------------- EVENTROUTER_STATUS ---------------------------------------
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */
+#define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */
+#define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */
+#define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */
+#define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */
+#define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */
+#define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */
+#define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */
+#define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */
+#define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */
+#define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */
+#define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */
+#define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */
+#define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */
+#define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */
+#define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */
+#define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */
+#define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */
+#define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */
+#define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */
+#define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */
+#define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */
+#define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */
+#define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */
+#define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */
+#define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */
+#define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */
+#define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */
+#define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */
+
+// ----------------------------------- EVENTROUTER_ENABLE ---------------------------------------
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */
+#define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */
+#define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */
+#define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */
+#define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */
+#define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */
+#define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */
+#define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */
+#define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */
+#define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */
+#define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */
+#define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */
+#define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */
+#define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */
+#define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */
+#define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */
+#define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */
+#define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */
+#define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */
+#define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */
+#define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */
+#define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */
+#define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */
+#define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */
+#define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */
+
+// ---------------------------------- EVENTROUTER_CLR_STAT --------------------------------------
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */
+
+// ---------------------------------- EVENTROUTER_SET_STAT --------------------------------------
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RTC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- RTC_ILR --------------------------------------------
+#define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */
+#define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */
+#define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */
+#define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */
+
+// ----------------------------------------- RTC_CCR --------------------------------------------
+#define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */
+#define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */
+#define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */
+#define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */
+#define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */
+#define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */
+
+// ---------------------------------------- RTC_CIIR --------------------------------------------
+#define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */
+#define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */
+#define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */
+#define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */
+#define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */
+#define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */
+#define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */
+#define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */
+#define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */
+#define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */
+#define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */
+#define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */
+#define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */
+#define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */
+#define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */
+#define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */
+
+// ----------------------------------------- RTC_AMR --------------------------------------------
+#define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */
+#define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */
+#define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */
+#define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */
+#define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */
+#define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */
+#define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */
+#define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */
+#define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */
+#define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */
+#define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */
+#define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */
+#define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */
+#define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */
+#define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */
+#define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */
+
+// --------------------------------------- RTC_CTIME0 -------------------------------------------
+#define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */
+#define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */
+#define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */
+#define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */
+#define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */
+#define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */
+#define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */
+#define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */
+
+// --------------------------------------- RTC_CTIME1 -------------------------------------------
+#define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */
+#define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */
+#define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */
+#define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */
+#define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */
+#define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */
+
+// --------------------------------------- RTC_CTIME2 -------------------------------------------
+#define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */
+#define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */
+
+// ----------------------------------------- RTC_SEC --------------------------------------------
+#define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */
+#define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */
+
+// ----------------------------------------- RTC_MIN --------------------------------------------
+#define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */
+#define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */
+
+// ----------------------------------------- RTC_HRS --------------------------------------------
+#define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */
+#define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */
+
+// ----------------------------------------- RTC_DOM --------------------------------------------
+#define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */
+#define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */
+
+// ----------------------------------------- RTC_DOW --------------------------------------------
+#define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */
+#define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */
+
+// ----------------------------------------- RTC_DOY --------------------------------------------
+#define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */
+#define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */
+
+// ---------------------------------------- RTC_MONTH -------------------------------------------
+#define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */
+#define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */
+
+// ---------------------------------------- RTC_YEAR --------------------------------------------
+#define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */
+#define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */
+
+// ------------------------------------- RTC_CALIBRATION ----------------------------------------
+#define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */
+#define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */
+#define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */
+#define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */
+
+// ---------------------------------------- RTC_ASEC --------------------------------------------
+#define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */
+#define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */
+
+// ---------------------------------------- RTC_AMIN --------------------------------------------
+#define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */
+#define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */
+
+// ---------------------------------------- RTC_AHRS --------------------------------------------
+#define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */
+#define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */
+
+// ---------------------------------------- RTC_ADOM --------------------------------------------
+#define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */
+#define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */
+
+// ---------------------------------------- RTC_ADOW --------------------------------------------
+#define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */
+#define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */
+
+// ---------------------------------------- RTC_ADOY --------------------------------------------
+#define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */
+#define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */
+
+// ---------------------------------------- RTC_AMON --------------------------------------------
+#define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */
+#define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */
+
+// ---------------------------------------- RTC_AYRS --------------------------------------------
+#define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */
+#define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CGU Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------- CGU_FREQ_MON ------------------------------------------
+#define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */
+#define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */
+#define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */
+#define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */
+#define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */
+#define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */
+#define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */
+#define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */
+
+// ------------------------------------ CGU_XTAL_OSC_CTRL ---------------------------------------
+#define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */
+#define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */
+#define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */
+#define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */
+
+// ------------------------------------ CGU_PLL0USB_STAT ----------------------------------------
+#define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */
+#define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */
+#define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */
+#define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */
+
+// ------------------------------------ CGU_PLL0USB_CTRL ----------------------------------------
+#define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */
+#define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */
+#define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */
+#define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */
+#define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */
+#define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */
+#define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */
+#define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */
+#define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */
+#define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */
+#define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */
+#define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */
+
+// ------------------------------------ CGU_PLL0USB_MDIV ----------------------------------------
+#define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */
+#define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */
+#define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */
+#define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */
+#define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */
+#define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */
+#define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */
+#define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */
+
+// ----------------------------------- CGU_PLL0USB_NP_DIV ---------------------------------------
+#define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */
+#define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */
+#define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */
+#define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_STAT ---------------------------------------
+#define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */
+#define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */
+#define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */
+#define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_CTRL ---------------------------------------
+#define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */
+#define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */
+#define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */
+#define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_MDIV ---------------------------------------
+#define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */
+#define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */
+
+// ---------------------------------- CGU_PLL0AUDIO_NP_DIV --------------------------------------
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_FRAC ---------------------------------------
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */
+
+// -------------------------------------- CGU_PLL1_STAT -----------------------------------------
+#define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */
+#define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */
+
+// -------------------------------------- CGU_PLL1_CTRL -----------------------------------------
+#define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */
+#define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */
+#define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */
+#define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */
+#define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */
+#define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */
+#define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */
+#define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */
+#define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */
+#define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */
+#define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */
+#define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */
+#define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */
+#define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */
+#define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */
+#define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVA_CTRL -----------------------------------------
+#define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */
+#define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */
+#define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */
+#define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */
+#define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVB_CTRL -----------------------------------------
+#define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */
+#define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */
+#define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */
+#define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */
+#define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVE_CTRL -----------------------------------------
+#define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */
+#define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */
+#define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */
+#define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */
+#define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SAFE_CLK ---------------------------------------
+#define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */
+#define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_USB0_CLK ---------------------------------------
+#define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */
+#define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_PERIPH_CLK --------------------------------------
+#define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */
+#define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_USB1_CLK ---------------------------------------
+#define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */
+#define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */
+
+// ------------------------------------- CGU_BASE_M4_CLK ----------------------------------------
+#define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */
+#define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */
+#define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_SPIFI_CLK ---------------------------------------
+#define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */
+#define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SPI_CLK ----------------------------------------
+#define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */
+#define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_PHY_RX_CLK --------------------------------------
+#define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */
+#define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_PHY_TX_CLK --------------------------------------
+#define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */
+#define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_APB1_CLK ---------------------------------------
+#define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */
+#define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_APB3_CLK ---------------------------------------
+#define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */
+#define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_LCD_CLK ----------------------------------------
+#define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */
+#define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SDIO_CLK ---------------------------------------
+#define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */
+#define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SSP0_CLK ---------------------------------------
+#define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */
+#define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SSP1_CLK ---------------------------------------
+#define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */
+#define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART0_CLK ---------------------------------------
+#define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */
+#define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART1_CLK ---------------------------------------
+#define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */
+#define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART2_CLK ---------------------------------------
+#define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */
+#define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART3_CLK ---------------------------------------
+#define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */
+#define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_OUT_CLK ----------------------------------------
+#define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */
+#define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_APLL_CLK ---------------------------------------
+#define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */
+#define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */
+
+// ---------------------------------- CGU_BASE_CGU_OUT0_CLK -------------------------------------
+#define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */
+#define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */
+
+// ---------------------------------- CGU_BASE_CGU_OUT1_CLK -------------------------------------
+#define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */
+#define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVC_CTRL -----------------------------------------
+#define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */
+#define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */
+#define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */
+#define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */
+#define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVD_CTRL -----------------------------------------
+#define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */
+#define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */
+#define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */
+#define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */
+#define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- CCU1_PM --------------------------------------------
+#define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */
+#define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */
+
+// ------------------------------------- CCU1_BASE_STAT -----------------------------------------
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */
+
+// ---------------------------------- CCU1_CLK_APB3_BUS_CFG -------------------------------------
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_BUS_STAT -------------------------------------
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_I2C1_CFG -------------------------------------
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_I2C1_STAT ------------------------------------
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_APB3_DAC_CFG -------------------------------------
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_DAC_STAT -------------------------------------
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC0_CFG -------------------------------------
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC0_STAT ------------------------------------
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC1_CFG -------------------------------------
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC1_STAT ------------------------------------
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_CAN0_CFG -------------------------------------
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_CAN0_STAT ------------------------------------
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_APB1_BUS_CFG -------------------------------------
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_BUS_STAT -------------------------------------
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */
+
+// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ----------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */
+
+// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT ---------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_ABP1_I2C0_CFG -------------------------------------
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_I2C0_STAT ------------------------------------
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_APB1_I2S_CFG -------------------------------------
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_I2S_STAT -------------------------------------
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_CAN1_CFG -------------------------------------
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_CAN1_STAT ------------------------------------
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_SPIFI_CFG ---------------------------------------
+#define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */
+#define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_SPIFI_STAT --------------------------------------
+#define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */
+#define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_BUS_CFG --------------------------------------
+#define CCU1_CLK_M3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_BUS_CFG: RUN Position */
+#define CCU1_CLK_M3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M3_BUS_CFG: RUN Mask */
+#define CCU1_CLK_M3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_BUS_CFG: AUTO Position */
+#define CCU1_CLK_M3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_M3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_BUS_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_BUS_STAT --------------------------------------
+#define CCU1_CLK_M3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_BUS_STAT: RUN Position */
+#define CCU1_CLK_M3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M3_BUS_STAT: RUN Mask */
+#define CCU1_CLK_M3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_BUS_STAT: AUTO Position */
+#define CCU1_CLK_M3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_M3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_BUS_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SPIFI_CFG -------------------------------------
+#define CCU1_CLK_M3_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SPIFI_CFG: RUN Position */
+#define CCU1_CLK_M3_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: RUN Mask */
+#define CCU1_CLK_M3_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SPIFI_CFG: AUTO Position */
+#define CCU1_CLK_M3_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: AUTO Mask */
+#define CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_SPIFI_STAT -------------------------------------
+#define CCU1_CLK_M3_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SPIFI_STAT: RUN Position */
+#define CCU1_CLK_M3_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: RUN Mask */
+#define CCU1_CLK_M3_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SPIFI_STAT: AUTO Position */
+#define CCU1_CLK_M3_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: AUTO Mask */
+#define CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_GPIO_CFG --------------------------------------
+#define CCU1_CLK_M3_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_GPIO_CFG: RUN Position */
+#define CCU1_CLK_M3_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: RUN Mask */
+#define CCU1_CLK_M3_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_GPIO_CFG: AUTO Position */
+#define CCU1_CLK_M3_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: AUTO Mask */
+#define CCU1_CLK_M3_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_GPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_GPIO_STAT -------------------------------------
+#define CCU1_CLK_M3_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_GPIO_STAT: RUN Position */
+#define CCU1_CLK_M3_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: RUN Mask */
+#define CCU1_CLK_M3_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_GPIO_STAT: AUTO Position */
+#define CCU1_CLK_M3_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: AUTO Mask */
+#define CCU1_CLK_M3_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_GPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_LCD_CFG --------------------------------------
+#define CCU1_CLK_M3_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_LCD_CFG: RUN Position */
+#define CCU1_CLK_M3_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M3_LCD_CFG: RUN Mask */
+#define CCU1_CLK_M3_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_LCD_CFG: AUTO Position */
+#define CCU1_CLK_M3_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_LCD_CFG: AUTO Mask */
+#define CCU1_CLK_M3_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_LCD_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_LCD_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_LCD_STAT --------------------------------------
+#define CCU1_CLK_M3_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_LCD_STAT: RUN Position */
+#define CCU1_CLK_M3_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M3_LCD_STAT: RUN Mask */
+#define CCU1_CLK_M3_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_LCD_STAT: AUTO Position */
+#define CCU1_CLK_M3_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_LCD_STAT: AUTO Mask */
+#define CCU1_CLK_M3_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_LCD_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_LCD_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_M3_ETHERNET_CFG ------------------------------------
+#define CCU1_CLK_M3_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_ETHERNET_CFG: RUN Position */
+#define CCU1_CLK_M3_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: RUN Mask */
+#define CCU1_CLK_M3_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_ETHERNET_CFG: AUTO Position */
+#define CCU1_CLK_M3_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: AUTO Mask */
+#define CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_ETHERNET_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_M3_ETHERNET_STAT -----------------------------------
+#define CCU1_CLK_M3_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_ETHERNET_STAT: RUN Position */
+#define CCU1_CLK_M3_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: RUN Mask */
+#define CCU1_CLK_M3_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_ETHERNET_STAT: AUTO Position */
+#define CCU1_CLK_M3_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: AUTO Mask */
+#define CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_ETHERNET_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_USB0_CFG --------------------------------------
+#define CCU1_CLK_M3_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USB0_CFG: RUN Position */
+#define CCU1_CLK_M3_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USB0_CFG: RUN Mask */
+#define CCU1_CLK_M3_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB0_CFG: AUTO Position */
+#define CCU1_CLK_M3_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USB0_CFG: AUTO Mask */
+#define CCU1_CLK_M3_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB0_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB0_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_USB0_STAT -------------------------------------
+#define CCU1_CLK_M3_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USB0_STAT: RUN Position */
+#define CCU1_CLK_M3_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USB0_STAT: RUN Mask */
+#define CCU1_CLK_M3_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB0_STAT: AUTO Position */
+#define CCU1_CLK_M3_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USB0_STAT: AUTO Mask */
+#define CCU1_CLK_M3_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB0_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_EMC_CFG --------------------------------------
+#define CCU1_CLK_M3_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_EMC_CFG: RUN Position */
+#define CCU1_CLK_M3_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M3_EMC_CFG: RUN Mask */
+#define CCU1_CLK_M3_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMC_CFG: AUTO Position */
+#define CCU1_CLK_M3_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_EMC_CFG: AUTO Mask */
+#define CCU1_CLK_M3_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMC_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMC_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_EMC_STAT --------------------------------------
+#define CCU1_CLK_M3_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_EMC_STAT: RUN Position */
+#define CCU1_CLK_M3_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M3_EMC_STAT: RUN Mask */
+#define CCU1_CLK_M3_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMC_STAT: AUTO Position */
+#define CCU1_CLK_M3_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_EMC_STAT: AUTO Mask */
+#define CCU1_CLK_M3_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMC_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMC_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SDIO_CFG --------------------------------------
+#define CCU1_CLK_M3_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SDIO_CFG: RUN Position */
+#define CCU1_CLK_M3_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: RUN Mask */
+#define CCU1_CLK_M3_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SDIO_CFG: AUTO Position */
+#define CCU1_CLK_M3_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: AUTO Mask */
+#define CCU1_CLK_M3_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SDIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SDIO_STAT -------------------------------------
+#define CCU1_CLK_M3_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SDIO_STAT: RUN Position */
+#define CCU1_CLK_M3_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: RUN Mask */
+#define CCU1_CLK_M3_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SDIO_STAT: AUTO Position */
+#define CCU1_CLK_M3_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: AUTO Mask */
+#define CCU1_CLK_M3_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SDIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_DMA_CFG --------------------------------------
+#define CCU1_CLK_M3_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_DMA_CFG: RUN Position */
+#define CCU1_CLK_M3_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M3_DMA_CFG: RUN Mask */
+#define CCU1_CLK_M3_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_DMA_CFG: AUTO Position */
+#define CCU1_CLK_M3_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_DMA_CFG: AUTO Mask */
+#define CCU1_CLK_M3_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_DMA_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_DMA_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_DMA_STAT --------------------------------------
+#define CCU1_CLK_M3_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_DMA_STAT: RUN Position */
+#define CCU1_CLK_M3_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M3_DMA_STAT: RUN Mask */
+#define CCU1_CLK_M3_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_DMA_STAT: AUTO Position */
+#define CCU1_CLK_M3_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_DMA_STAT: AUTO Mask */
+#define CCU1_CLK_M3_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_DMA_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_DMA_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_M3CORE_CFG -------------------------------------
+#define CCU1_CLK_M3_M3CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_M3CORE_CFG: RUN Position */
+#define CCU1_CLK_M3_M3CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: RUN Mask */
+#define CCU1_CLK_M3_M3CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_M3CORE_CFG: AUTO Position */
+#define CCU1_CLK_M3_M3CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: AUTO Mask */
+#define CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_M3CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_M3CORE_STAT ------------------------------------
+#define CCU1_CLK_M3_M3CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_M3CORE_STAT: RUN Position */
+#define CCU1_CLK_M3_M3CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: RUN Mask */
+#define CCU1_CLK_M3_M3CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_M3CORE_STAT: AUTO Position */
+#define CCU1_CLK_M3_M3CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: AUTO Mask */
+#define CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_M3CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_SCT_CFG --------------------------------------
+#define CCU1_CLK_M3_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SCT_CFG: RUN Position */
+#define CCU1_CLK_M3_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SCT_CFG: RUN Mask */
+#define CCU1_CLK_M3_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCT_CFG: AUTO Position */
+#define CCU1_CLK_M3_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SCT_CFG: AUTO Mask */
+#define CCU1_CLK_M3_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCT_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCT_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SCT_STAT --------------------------------------
+#define CCU1_CLK_M3_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SCT_STAT: RUN Position */
+#define CCU1_CLK_M3_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SCT_STAT: RUN Mask */
+#define CCU1_CLK_M3_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCT_STAT: AUTO Position */
+#define CCU1_CLK_M3_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SCT_STAT: AUTO Mask */
+#define CCU1_CLK_M3_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCT_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCT_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_USB1_CFG --------------------------------------
+#define CCU1_CLK_M3_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USB1_CFG: RUN Position */
+#define CCU1_CLK_M3_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USB1_CFG: RUN Mask */
+#define CCU1_CLK_M3_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB1_CFG: AUTO Position */
+#define CCU1_CLK_M3_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USB1_CFG: AUTO Mask */
+#define CCU1_CLK_M3_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB1_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB1_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_USB1_STAT -------------------------------------
+#define CCU1_CLK_M3_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USB1_STAT: RUN Position */
+#define CCU1_CLK_M3_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USB1_STAT: RUN Mask */
+#define CCU1_CLK_M3_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB1_STAT: AUTO Position */
+#define CCU1_CLK_M3_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USB1_STAT: AUTO Mask */
+#define CCU1_CLK_M3_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB1_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_EMCDIV_CFG -------------------------------------
+#define CCU1_CLK_M3_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_EMCDIV_CFG: RUN Position */
+#define CCU1_CLK_M3_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: RUN Mask */
+#define CCU1_CLK_M3_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMCDIV_CFG: AUTO Position */
+#define CCU1_CLK_M3_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: AUTO Mask */
+#define CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMCDIV_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_EMCDIV_STAT ------------------------------------
+#define CCU1_CLK_M3_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_EMCDIV_STAT: RUN Position */
+#define CCU1_CLK_M3_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: RUN Mask */
+#define CCU1_CLK_M3_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMCDIV_STAT: AUTO Position */
+#define CCU1_CLK_M3_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: AUTO Mask */
+#define CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMCDIV_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_WWDT_CFG --------------------------------------
+#define CCU1_CLK_M3_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_WWDT_CFG: RUN Position */
+#define CCU1_CLK_M3_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: RUN Mask */
+#define CCU1_CLK_M3_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_WWDT_CFG: AUTO Position */
+#define CCU1_CLK_M3_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: AUTO Mask */
+#define CCU1_CLK_M3_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_WWDT_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_WWDT_STAT -------------------------------------
+#define CCU1_CLK_M3_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_WWDT_STAT: RUN Position */
+#define CCU1_CLK_M3_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: RUN Mask */
+#define CCU1_CLK_M3_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_WWDT_STAT: AUTO Position */
+#define CCU1_CLK_M3_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: AUTO Mask */
+#define CCU1_CLK_M3_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_WWDT_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_USART0_CFG -------------------------------------
+#define CCU1_CLK_M3_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART0_CFG: RUN Position */
+#define CCU1_CLK_M3_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART0_CFG: RUN Mask */
+#define CCU1_CLK_M3_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART0_CFG: AUTO Position */
+#define CCU1_CLK_M3_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART0_CFG: AUTO Mask */
+#define CCU1_CLK_M3_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART0_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_USART0_STAT ------------------------------------
+#define CCU1_CLK_M3_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART0_STAT: RUN Position */
+#define CCU1_CLK_M3_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART0_STAT: RUN Mask */
+#define CCU1_CLK_M3_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART0_STAT: AUTO Position */
+#define CCU1_CLK_M3_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART0_STAT: AUTO Mask */
+#define CCU1_CLK_M3_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART0_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART0_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_UART1_CFG -------------------------------------
+#define CCU1_CLK_M3_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_UART1_CFG: RUN Position */
+#define CCU1_CLK_M3_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_UART1_CFG: RUN Mask */
+#define CCU1_CLK_M3_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_UART1_CFG: AUTO Position */
+#define CCU1_CLK_M3_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_UART1_CFG: AUTO Mask */
+#define CCU1_CLK_M3_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_UART1_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_UART1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_UART1_STAT -------------------------------------
+#define CCU1_CLK_M3_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_UART1_STAT: RUN Position */
+#define CCU1_CLK_M3_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_UART1_STAT: RUN Mask */
+#define CCU1_CLK_M3_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_UART1_STAT: AUTO Position */
+#define CCU1_CLK_M3_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_UART1_STAT: AUTO Mask */
+#define CCU1_CLK_M3_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_UART1_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_UART1_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SSP0_CFG --------------------------------------
+#define CCU1_CLK_M3_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP0_CFG: RUN Position */
+#define CCU1_CLK_M3_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: RUN Mask */
+#define CCU1_CLK_M3_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP0_CFG: AUTO Position */
+#define CCU1_CLK_M3_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: AUTO Mask */
+#define CCU1_CLK_M3_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP0_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SSP0_STAT -------------------------------------
+#define CCU1_CLK_M3_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP0_STAT: RUN Position */
+#define CCU1_CLK_M3_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: RUN Mask */
+#define CCU1_CLK_M3_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP0_STAT: AUTO Position */
+#define CCU1_CLK_M3_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: AUTO Mask */
+#define CCU1_CLK_M3_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP0_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER0_CFG -------------------------------------
+#define CCU1_CLK_M3_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER0_CFG: RUN Position */
+#define CCU1_CLK_M3_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: RUN Mask */
+#define CCU1_CLK_M3_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER0_CFG: AUTO Position */
+#define CCU1_CLK_M3_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: AUTO Mask */
+#define CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER0_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER0_STAT ------------------------------------
+#define CCU1_CLK_M3_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER0_STAT: RUN Position */
+#define CCU1_CLK_M3_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: RUN Mask */
+#define CCU1_CLK_M3_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER0_STAT: AUTO Position */
+#define CCU1_CLK_M3_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: AUTO Mask */
+#define CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER0_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER1_CFG -------------------------------------
+#define CCU1_CLK_M3_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER1_CFG: RUN Position */
+#define CCU1_CLK_M3_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: RUN Mask */
+#define CCU1_CLK_M3_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER1_CFG: AUTO Position */
+#define CCU1_CLK_M3_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: AUTO Mask */
+#define CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER1_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER1_STAT ------------------------------------
+#define CCU1_CLK_M3_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER1_STAT: RUN Position */
+#define CCU1_CLK_M3_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: RUN Mask */
+#define CCU1_CLK_M3_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER1_STAT: AUTO Position */
+#define CCU1_CLK_M3_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: AUTO Mask */
+#define CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER1_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_SCU_CFG --------------------------------------
+#define CCU1_CLK_M3_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SCU_CFG: RUN Position */
+#define CCU1_CLK_M3_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SCU_CFG: RUN Mask */
+#define CCU1_CLK_M3_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCU_CFG: AUTO Position */
+#define CCU1_CLK_M3_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SCU_CFG: AUTO Mask */
+#define CCU1_CLK_M3_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCU_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCU_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SCU_STAT --------------------------------------
+#define CCU1_CLK_M3_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SCU_STAT: RUN Position */
+#define CCU1_CLK_M3_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SCU_STAT: RUN Mask */
+#define CCU1_CLK_M3_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCU_STAT: AUTO Position */
+#define CCU1_CLK_M3_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SCU_STAT: AUTO Mask */
+#define CCU1_CLK_M3_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCU_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCU_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_CREG_CFG --------------------------------------
+#define CCU1_CLK_M3_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_CREG_CFG: RUN Position */
+#define CCU1_CLK_M3_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M3_CREG_CFG: RUN Mask */
+#define CCU1_CLK_M3_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_CREG_CFG: AUTO Position */
+#define CCU1_CLK_M3_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_CREG_CFG: AUTO Mask */
+#define CCU1_CLK_M3_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_CREG_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_CREG_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_CREG_STAT -------------------------------------
+#define CCU1_CLK_M3_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_CREG_STAT: RUN Position */
+#define CCU1_CLK_M3_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M3_CREG_STAT: RUN Mask */
+#define CCU1_CLK_M3_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_CREG_STAT: AUTO Position */
+#define CCU1_CLK_M3_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_CREG_STAT: AUTO Mask */
+#define CCU1_CLK_M3_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_CREG_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_CREG_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_RITIMER_CFG ------------------------------------
+#define CCU1_CLK_M3_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_RITIMER_CFG: RUN Position */
+#define CCU1_CLK_M3_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: RUN Mask */
+#define CCU1_CLK_M3_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_RITIMER_CFG: AUTO Position */
+#define CCU1_CLK_M3_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: AUTO Mask */
+#define CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_RITIMER_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_M3_RITIMER_STAT ------------------------------------
+#define CCU1_CLK_M3_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_RITIMER_STAT: RUN Position */
+#define CCU1_CLK_M3_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: RUN Mask */
+#define CCU1_CLK_M3_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_RITIMER_STAT: AUTO Position */
+#define CCU1_CLK_M3_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: AUTO Mask */
+#define CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_RITIMER_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_USART2_CFG -------------------------------------
+#define CCU1_CLK_M3_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART2_CFG: RUN Position */
+#define CCU1_CLK_M3_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART2_CFG: RUN Mask */
+#define CCU1_CLK_M3_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART2_CFG: AUTO Position */
+#define CCU1_CLK_M3_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART2_CFG: AUTO Mask */
+#define CCU1_CLK_M3_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART2_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART2_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_USART2_STAT ------------------------------------
+#define CCU1_CLK_M3_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART2_STAT: RUN Position */
+#define CCU1_CLK_M3_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART2_STAT: RUN Mask */
+#define CCU1_CLK_M3_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART2_STAT: AUTO Position */
+#define CCU1_CLK_M3_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART2_STAT: AUTO Mask */
+#define CCU1_CLK_M3_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART2_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART2_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_USART3_CFG -------------------------------------
+#define CCU1_CLK_M3_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART3_CFG: RUN Position */
+#define CCU1_CLK_M3_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART3_CFG: RUN Mask */
+#define CCU1_CLK_M3_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART3_CFG: AUTO Position */
+#define CCU1_CLK_M3_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART3_CFG: AUTO Mask */
+#define CCU1_CLK_M3_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART3_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART3_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_USART3_STAT ------------------------------------
+#define CCU1_CLK_M3_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART3_STAT: RUN Position */
+#define CCU1_CLK_M3_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART3_STAT: RUN Mask */
+#define CCU1_CLK_M3_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART3_STAT: AUTO Position */
+#define CCU1_CLK_M3_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART3_STAT: AUTO Mask */
+#define CCU1_CLK_M3_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART3_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART3_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER2_CFG -------------------------------------
+#define CCU1_CLK_M3_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER2_CFG: RUN Position */
+#define CCU1_CLK_M3_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: RUN Mask */
+#define CCU1_CLK_M3_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER2_CFG: AUTO Position */
+#define CCU1_CLK_M3_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: AUTO Mask */
+#define CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER2_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER2_STAT ------------------------------------
+#define CCU1_CLK_M3_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER2_STAT: RUN Position */
+#define CCU1_CLK_M3_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: RUN Mask */
+#define CCU1_CLK_M3_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER2_STAT: AUTO Position */
+#define CCU1_CLK_M3_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: AUTO Mask */
+#define CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER2_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER3_CFG -------------------------------------
+#define CCU1_CLK_M3_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER3_CFG: RUN Position */
+#define CCU1_CLK_M3_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: RUN Mask */
+#define CCU1_CLK_M3_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER3_CFG: AUTO Position */
+#define CCU1_CLK_M3_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: AUTO Mask */
+#define CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER3_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M3_TIMER3_STAT ------------------------------------
+#define CCU1_CLK_M3_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER3_STAT: RUN Position */
+#define CCU1_CLK_M3_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: RUN Mask */
+#define CCU1_CLK_M3_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER3_STAT: AUTO Position */
+#define CCU1_CLK_M3_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: AUTO Mask */
+#define CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER3_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SSP1_CFG --------------------------------------
+#define CCU1_CLK_M3_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP1_CFG: RUN Position */
+#define CCU1_CLK_M3_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: RUN Mask */
+#define CCU1_CLK_M3_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP1_CFG: AUTO Position */
+#define CCU1_CLK_M3_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: AUTO Mask */
+#define CCU1_CLK_M3_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP1_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_SSP1_STAT -------------------------------------
+#define CCU1_CLK_M3_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP1_STAT: RUN Position */
+#define CCU1_CLK_M3_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: RUN Mask */
+#define CCU1_CLK_M3_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP1_STAT: AUTO Position */
+#define CCU1_CLK_M3_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: AUTO Mask */
+#define CCU1_CLK_M3_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP1_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M3_QEI_CFG --------------------------------------
+#define CCU1_CLK_M3_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_QEI_CFG: RUN Position */
+#define CCU1_CLK_M3_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M3_QEI_CFG: RUN Mask */
+#define CCU1_CLK_M3_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_QEI_CFG: AUTO Position */
+#define CCU1_CLK_M3_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_QEI_CFG: AUTO Mask */
+#define CCU1_CLK_M3_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_QEI_CFG: WAKEUP Position */
+#define CCU1_CLK_M3_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_QEI_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M3_QEI_STAT --------------------------------------
+#define CCU1_CLK_M3_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_QEI_STAT: RUN Position */
+#define CCU1_CLK_M3_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M3_QEI_STAT: RUN Mask */
+#define CCU1_CLK_M3_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_QEI_STAT: AUTO Position */
+#define CCU1_CLK_M3_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_QEI_STAT: AUTO Mask */
+#define CCU1_CLK_M3_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_QEI_STAT: WAKEUP Position */
+#define CCU1_CLK_M3_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_QEI_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_PERIPH_BUS_CFG ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_BUS_STAT ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_CORE_CFG ------------------------------------
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_CORE_STAT -----------------------------------
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */
+
+
+// ------------------------------------ CCU1_CLK_USB0_CFG ---------------------------------------
+#define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */
+#define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */
+#define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */
+#define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_USB0_STAT ---------------------------------------
+#define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */
+#define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */
+#define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */
+#define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_USB1_CFG ---------------------------------------
+#define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */
+#define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */
+#define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */
+#define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_USB1_STAT ---------------------------------------
+#define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */
+#define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */
+#define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */
+#define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_VADC_CFG ---------------------------------------
+#define CCU1_CLK_VADC_CFG_RUN_Pos 0 /*!< CCU1 CLK_VADC_CFG: RUN Position */
+#define CCU1_CLK_VADC_CFG_RUN_Msk (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos) /*!< CCU1 CLK_VADC_CFG: RUN Mask */
+#define CCU1_CLK_VADC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_VADC_CFG: AUTO Position */
+#define CCU1_CLK_VADC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos) /*!< CCU1 CLK_VADC_CFG: AUTO Mask */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_CFG: WAKEUP Position */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_VADC_STAT ---------------------------------------
+#define CCU1_CLK_VADC_STAT_RUN_Pos 0 /*!< CCU1 CLK_VADC_STAT: RUN Position */
+#define CCU1_CLK_VADC_STAT_RUN_Msk (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos) /*!< CCU1 CLK_VADC_STAT: RUN Mask */
+#define CCU1_CLK_VADC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_VADC_STAT: AUTO Position */
+#define CCU1_CLK_VADC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos) /*!< CCU1 CLK_VADC_STAT: AUTO Mask */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU2 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- CCU2_PM --------------------------------------------
+#define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */
+#define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */
+
+// ------------------------------------- CCU2_BASE_STAT -----------------------------------------
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */
+
+// ----------------------------------- CCU2_CLK_APLL3_CFG ---------------------------------------
+#define CCU2_CLK_APLL3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APLL3_CFG: RUN Position */
+#define CCU2_CLK_APLL3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APLL3_CFG_RUN_Pos) /*!< CCU2 CLK_APLL3_CFG: RUN Mask */
+#define CCU2_CLK_APLL3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APLL3_CFG: AUTO Position */
+#define CCU2_CLK_APLL3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APLL3_CFG_AUTO_Pos) /*!< CCU2 CLK_APLL3_CFG: AUTO Mask */
+#define CCU2_CLK_APLL3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL3_CFG: WAKEUP Position */
+#define CCU2_CLK_APLL3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APLL3_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU2_CLK_APLL_STAT ---------------------------------------
+#define CCU2_CLK_APLL_STAT_RUN_Pos 0 /*!< CCU2 CLK_APLL_STAT: RUN Position */
+#define CCU2_CLK_APLL_STAT_RUN_Msk (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos) /*!< CCU2 CLK_APLL_STAT: RUN Mask */
+#define CCU2_CLK_APLL_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APLL_STAT: AUTO Position */
+#define CCU2_CLK_APLL_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos) /*!< CCU2 CLK_APLL_STAT: AUTO Mask */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART3_CFG ------------------------------------
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART3_STAT -----------------------------------
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART2_CFG ------------------------------------
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART2_STAT -----------------------------------
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */
+
+// ------------------------------- CCU2_CLK_APB0_UART1_BUS_CFG ----------------------------------
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB0_UART1_STAT ------------------------------------
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB0_USART0_CFG ------------------------------------
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB0_USART0_STAT -----------------------------------
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB2_SSP1_CFG -------------------------------------
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB2_SSP1_STAT ------------------------------------
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB0_SSP0_CFG -------------------------------------
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB0_SSP0_STAT ------------------------------------
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU2_CLK_SDIO_CFG ---------------------------------------
+#define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */
+#define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */
+#define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */
+#define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU2_CLK_SDIO_STAT ---------------------------------------
+#define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */
+#define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */
+#define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */
+#define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RGU Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- RGU_RESET_CTRL0 ----------------------------------------
+#define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */
+#define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */
+#define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */
+#define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */
+#define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */
+#define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */
+#define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */
+#define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */
+#define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */
+#define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */
+#define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */
+#define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */
+#define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */
+#define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */
+#define RGU_RESET_CTRL0_PINMUX_RST_Pos 10 /*!< RGU RESET_CTRL0: PINMUX_RST Position */
+#define RGU_RESET_CTRL0_PINMUX_RST_Msk (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos) /*!< RGU RESET_CTRL0: PINMUX_RST Mask */
+#define RGU_RESET_CTRL0_M3_RST_Pos 13 /*!< RGU RESET_CTRL0: M3_RST Position */
+#define RGU_RESET_CTRL0_M3_RST_Msk (0x01UL << RGU_RESET_CTRL0_M3_RST_Pos) /*!< RGU RESET_CTRL0: M3_RST Mask */
+#define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */
+#define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */
+#define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */
+#define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */
+#define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */
+#define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */
+#define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */
+#define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */
+#define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */
+#define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */
+#define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */
+#define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */
+#define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */
+#define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */
+
+// ------------------------------------- RGU_RESET_CTRL1 ----------------------------------------
+#define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */
+#define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */
+#define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */
+#define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */
+#define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */
+#define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */
+#define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */
+#define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */
+#define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */
+#define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */
+#define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */
+#define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */
+#define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */
+#define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */
+#define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */
+#define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */
+#define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */
+#define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */
+#define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */
+#define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */
+#define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */
+#define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */
+#define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */
+#define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */
+#define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */
+#define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */
+#define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */
+#define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */
+#define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */
+#define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */
+#define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */
+#define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */
+#define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */
+#define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */
+#define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */
+#define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */
+#define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */
+#define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */
+#define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */
+#define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */
+#define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */
+#define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */
+#define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS0 ---------------------------------------
+#define RGU_RESET_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_STATUS0: CORE_RST Position */
+#define RGU_RESET_STATUS0_CORE_RST_Msk (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos) /*!< RGU RESET_STATUS0: CORE_RST Mask */
+#define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */
+#define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */
+#define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */
+#define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */
+#define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */
+#define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */
+#define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */
+#define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */
+#define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */
+#define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */
+#define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */
+#define RGU_RESET_STATUS0_M3_RST_Pos 26 /*!< RGU RESET_STATUS0: M3_RST Position */
+#define RGU_RESET_STATUS0_M3_RST_Msk (0x03UL << RGU_RESET_STATUS0_M3_RST_Pos) /*!< RGU RESET_STATUS0: M3_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS1 ---------------------------------------
+#define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */
+#define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */
+#define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */
+#define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */
+#define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */
+#define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */
+#define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */
+#define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */
+#define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */
+#define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */
+#define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */
+#define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */
+#define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */
+#define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS2 ---------------------------------------
+#define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */
+#define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */
+#define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */
+#define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */
+#define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */
+#define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */
+#define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */
+#define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */
+#define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */
+#define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */
+#define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */
+#define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */
+#define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */
+#define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */
+#define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */
+#define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */
+#define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */
+#define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */
+#define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */
+#define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */
+#define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */
+#define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */
+#define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */
+#define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */
+#define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */
+#define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */
+#define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */
+#define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS3 ---------------------------------------
+#define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */
+#define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */
+#define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */
+#define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */
+#define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */
+#define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */
+#define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */
+#define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */
+#define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */
+#define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */
+#define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */
+#define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */
+#define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */
+#define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */
+#define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */
+#define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */
+
+// -------------------------------- RGU_RESET_ACTIVE_STATUS0 ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */
+
+// -------------------------------- RGU_RESET_ACTIVE_STATUS1 ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT0 --------------------------------------
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos 0 /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos 4 /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos) /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos 5 /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT1 --------------------------------------
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT2 --------------------------------------
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT4 --------------------------------------
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT5 --------------------------------------
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT8 --------------------------------------
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT9 --------------------------------------
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT13 --------------------------------------
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT16 --------------------------------------
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT17 --------------------------------------
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT18 --------------------------------------
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT19 --------------------------------------
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT20 --------------------------------------
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT21 --------------------------------------
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT22 --------------------------------------
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT23 --------------------------------------
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT28 --------------------------------------
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT32 --------------------------------------
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT33 --------------------------------------
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT34 --------------------------------------
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT35 --------------------------------------
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT36 --------------------------------------
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT37 --------------------------------------
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT38 --------------------------------------
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT39 --------------------------------------
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT40 --------------------------------------
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT41 --------------------------------------
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT42 --------------------------------------
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT44 --------------------------------------
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT45 --------------------------------------
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT46 --------------------------------------
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT47 --------------------------------------
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT48 --------------------------------------
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT49 --------------------------------------
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT50 --------------------------------------
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT51 --------------------------------------
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT52 --------------------------------------
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT53 --------------------------------------
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT54 --------------------------------------
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT55 --------------------------------------
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- WWDT_MOD --------------------------------------------
+#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */
+#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */
+#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */
+#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */
+#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */
+#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */
+#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */
+#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */
+#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */
+#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */
+
+// ----------------------------------------- WWDT_TC --------------------------------------------
+#define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */
+#define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */
+
+// ---------------------------------------- WWDT_FEED -------------------------------------------
+#define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */
+#define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */
+
+// ----------------------------------------- WWDT_TV --------------------------------------------
+#define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */
+#define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */
+
+// -------------------------------------- WWDT_WARNINT ------------------------------------------
+#define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */
+#define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */
+
+// --------------------------------------- WWDT_WINDOW ------------------------------------------
+#define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */
+#define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- USART0_RBR -------------------------------------------
+#define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */
+#define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */
+
+// --------------------------------------- USART0_THR -------------------------------------------
+#define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */
+#define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */
+
+// --------------------------------------- USART0_DLL -------------------------------------------
+#define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */
+#define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */
+
+// --------------------------------------- USART0_DLM -------------------------------------------
+#define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */
+#define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */
+
+// --------------------------------------- USART0_IER -------------------------------------------
+#define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */
+#define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */
+#define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */
+#define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */
+#define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */
+#define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */
+#define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */
+#define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */
+#define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */
+#define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */
+
+// --------------------------------------- USART0_IIR -------------------------------------------
+#define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */
+#define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */
+#define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */
+#define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */
+#define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */
+#define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */
+#define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */
+#define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */
+#define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */
+#define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */
+
+// --------------------------------------- USART0_FCR -------------------------------------------
+#define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */
+#define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */
+#define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */
+#define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */
+#define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */
+#define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */
+#define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */
+#define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */
+#define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */
+#define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */
+
+// --------------------------------------- USART0_LCR -------------------------------------------
+#define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */
+#define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */
+#define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */
+#define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */
+#define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */
+#define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */
+#define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */
+#define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */
+#define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */
+#define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */
+#define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */
+#define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */
+
+// --------------------------------------- USART0_LSR -------------------------------------------
+#define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */
+#define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */
+#define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */
+#define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */
+#define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */
+#define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */
+#define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */
+#define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */
+#define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */
+#define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */
+#define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */
+#define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */
+#define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */
+#define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */
+#define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */
+#define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */
+#define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */
+#define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */
+
+// --------------------------------------- USART0_SCR -------------------------------------------
+#define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */
+#define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */
+
+// --------------------------------------- USART0_ACR -------------------------------------------
+#define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */
+#define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */
+#define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */
+#define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */
+#define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */
+#define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */
+#define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */
+#define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */
+#define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */
+#define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */
+
+// --------------------------------------- USART0_ICR -------------------------------------------
+#define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */
+#define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */
+#define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */
+#define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */
+#define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */
+#define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */
+#define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */
+#define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */
+
+// --------------------------------------- USART0_FDR -------------------------------------------
+#define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */
+#define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */
+#define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */
+#define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */
+
+// --------------------------------------- USART0_OSR -------------------------------------------
+#define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */
+#define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */
+#define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */
+#define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */
+#define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */
+#define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */
+
+// --------------------------------------- USART0_HDEN ------------------------------------------
+#define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */
+#define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */
+
+// ------------------------------------- USART0_SCICTRL -----------------------------------------
+#define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */
+#define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */
+#define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */
+#define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */
+#define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */
+#define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */
+#define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */
+#define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */
+#define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */
+#define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */
+
+// ------------------------------------ USART0_RS485CTRL ----------------------------------------
+#define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */
+#define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */
+#define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */
+#define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */
+#define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */
+#define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */
+#define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */
+#define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */
+#define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */
+#define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */
+
+// ---------------------------------- USART0_RS485ADRMATCH --------------------------------------
+#define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */
+#define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- USART0_RS485DLY ----------------------------------------
+#define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */
+#define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */
+
+// ------------------------------------- USART0_SYNCCTRL ----------------------------------------
+#define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */
+#define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */
+#define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */
+#define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */
+#define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */
+#define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */
+#define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */
+#define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */
+#define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */
+#define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */
+#define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */
+#define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */
+#define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */
+#define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */
+
+// --------------------------------------- USART0_TER -------------------------------------------
+#define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */
+#define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART2 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- USART2_DLL -------------------------------------------
+#define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */
+#define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */
+
+// --------------------------------------- USART2_THR -------------------------------------------
+#define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */
+#define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */
+
+// --------------------------------------- USART2_RBR -------------------------------------------
+#define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */
+#define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */
+
+// --------------------------------------- USART2_IER -------------------------------------------
+#define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */
+#define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */
+#define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */
+#define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */
+#define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */
+#define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */
+#define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */
+#define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */
+#define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */
+#define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */
+
+// --------------------------------------- USART2_DLM -------------------------------------------
+#define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */
+#define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */
+
+// --------------------------------------- USART2_FCR -------------------------------------------
+#define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */
+#define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */
+#define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */
+#define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */
+#define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */
+#define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */
+#define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */
+#define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */
+#define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */
+#define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */
+
+// --------------------------------------- USART2_IIR -------------------------------------------
+#define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */
+#define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */
+#define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */
+#define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */
+#define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */
+#define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */
+#define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */
+#define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */
+#define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */
+#define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */
+
+// --------------------------------------- USART2_LCR -------------------------------------------
+#define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */
+#define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */
+#define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */
+#define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */
+#define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */
+#define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */
+#define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */
+#define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */
+#define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */
+#define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */
+#define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */
+#define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */
+
+// --------------------------------------- USART2_LSR -------------------------------------------
+#define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */
+#define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */
+#define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */
+#define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */
+#define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */
+#define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */
+#define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */
+#define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */
+#define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */
+#define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */
+#define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */
+#define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */
+#define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */
+#define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */
+#define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */
+#define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */
+#define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */
+#define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */
+
+// --------------------------------------- USART2_SCR -------------------------------------------
+#define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */
+#define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */
+
+// --------------------------------------- USART2_ACR -------------------------------------------
+#define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */
+#define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */
+#define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */
+#define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */
+#define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */
+#define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */
+#define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */
+#define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */
+#define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */
+#define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */
+
+// --------------------------------------- USART2_ICR -------------------------------------------
+#define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */
+#define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */
+#define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */
+#define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */
+#define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */
+#define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */
+#define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */
+#define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */
+
+// --------------------------------------- USART2_FDR -------------------------------------------
+#define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */
+#define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */
+#define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */
+#define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */
+
+// --------------------------------------- USART2_OSR -------------------------------------------
+#define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */
+#define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */
+#define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */
+#define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */
+#define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */
+#define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */
+
+// --------------------------------------- USART2_HDEN ------------------------------------------
+#define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */
+#define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */
+
+// ------------------------------------- USART2_SCICTRL -----------------------------------------
+#define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */
+#define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */
+#define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */
+#define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */
+#define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */
+#define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */
+#define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */
+#define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */
+#define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */
+#define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */
+
+// ------------------------------------ USART2_RS485CTRL ----------------------------------------
+#define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */
+#define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */
+#define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */
+#define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */
+#define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */
+#define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */
+#define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */
+#define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */
+#define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */
+#define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */
+
+// ---------------------------------- USART2_RS485ADRMATCH --------------------------------------
+#define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */
+#define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- USART2_RS485DLY ----------------------------------------
+#define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */
+#define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */
+
+// ------------------------------------- USART2_SYNCCTRL ----------------------------------------
+#define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */
+#define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */
+#define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */
+#define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */
+#define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */
+#define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */
+#define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */
+#define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */
+#define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */
+#define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */
+#define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */
+#define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */
+#define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */
+#define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */
+
+// --------------------------------------- USART2_TER -------------------------------------------
+#define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */
+#define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART3 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- USART3_DLL -------------------------------------------
+#define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */
+#define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */
+
+// --------------------------------------- USART3_THR -------------------------------------------
+#define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */
+#define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */
+
+// --------------------------------------- USART3_RBR -------------------------------------------
+#define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */
+#define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */
+
+// --------------------------------------- USART3_IER -------------------------------------------
+#define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */
+#define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */
+#define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */
+#define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */
+#define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */
+#define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */
+#define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */
+#define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */
+#define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */
+#define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */
+
+// --------------------------------------- USART3_DLM -------------------------------------------
+#define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */
+#define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */
+
+// --------------------------------------- USART3_FCR -------------------------------------------
+#define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */
+#define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */
+#define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */
+#define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */
+#define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */
+#define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */
+#define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */
+#define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */
+#define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */
+#define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */
+
+// --------------------------------------- USART3_IIR -------------------------------------------
+#define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */
+#define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */
+#define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */
+#define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */
+#define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */
+#define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */
+#define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */
+#define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */
+#define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */
+#define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */
+
+// --------------------------------------- USART3_LCR -------------------------------------------
+#define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */
+#define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */
+#define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */
+#define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */
+#define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */
+#define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */
+#define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */
+#define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */
+#define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */
+#define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */
+#define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */
+#define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */
+
+// --------------------------------------- USART3_LSR -------------------------------------------
+#define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */
+#define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */
+#define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */
+#define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */
+#define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */
+#define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */
+#define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */
+#define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */
+#define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */
+#define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */
+#define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */
+#define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */
+#define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */
+#define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */
+#define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */
+#define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */
+#define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */
+#define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */
+
+// --------------------------------------- USART3_SCR -------------------------------------------
+#define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */
+#define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */
+
+// --------------------------------------- USART3_ACR -------------------------------------------
+#define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */
+#define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */
+#define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */
+#define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */
+#define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */
+#define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */
+#define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */
+#define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */
+#define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */
+#define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */
+
+// --------------------------------------- USART3_ICR -------------------------------------------
+#define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */
+#define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */
+#define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */
+#define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */
+#define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */
+#define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */
+#define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */
+#define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */
+
+// --------------------------------------- USART3_FDR -------------------------------------------
+#define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */
+#define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */
+#define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */
+#define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */
+
+// --------------------------------------- USART3_OSR -------------------------------------------
+#define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */
+#define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */
+#define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */
+#define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */
+#define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */
+#define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */
+
+// --------------------------------------- USART3_HDEN ------------------------------------------
+#define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */
+#define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */
+
+// ------------------------------------- USART3_SCICTRL -----------------------------------------
+#define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */
+#define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */
+#define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */
+#define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */
+#define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */
+#define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */
+#define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */
+#define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */
+#define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */
+#define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */
+
+// ------------------------------------ USART3_RS485CTRL ----------------------------------------
+#define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */
+#define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */
+#define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */
+#define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */
+#define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */
+#define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */
+#define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */
+#define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */
+#define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */
+#define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */
+
+// ---------------------------------- USART3_RS485ADRMATCH --------------------------------------
+#define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */
+#define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- USART3_RS485DLY ----------------------------------------
+#define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */
+#define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */
+
+// ------------------------------------- USART3_SYNCCTRL ----------------------------------------
+#define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */
+#define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */
+#define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */
+#define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */
+#define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */
+#define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */
+#define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */
+#define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */
+#define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */
+#define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */
+#define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */
+#define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */
+#define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */
+#define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */
+
+// --------------------------------------- USART3_TER -------------------------------------------
+#define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */
+#define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- UART1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- UART1_RBR -------------------------------------------
+#define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */
+#define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */
+
+// ---------------------------------------- UART1_THR -------------------------------------------
+#define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */
+#define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */
+
+// ---------------------------------------- UART1_DLL -------------------------------------------
+#define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */
+#define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */
+
+// ---------------------------------------- UART1_DLM -------------------------------------------
+#define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */
+#define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */
+
+// ---------------------------------------- UART1_IER -------------------------------------------
+#define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */
+#define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */
+#define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */
+#define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */
+#define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */
+#define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */
+#define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */
+#define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */
+#define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */
+#define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */
+#define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */
+#define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */
+#define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */
+#define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */
+
+// ---------------------------------------- UART1_IIR -------------------------------------------
+#define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */
+#define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */
+#define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */
+#define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */
+#define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */
+#define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */
+#define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */
+#define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */
+#define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */
+#define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */
+
+// ---------------------------------------- UART1_FCR -------------------------------------------
+#define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */
+#define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */
+#define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */
+#define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */
+#define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */
+#define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */
+#define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */
+#define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */
+#define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */
+#define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */
+
+// ---------------------------------------- UART1_LCR -------------------------------------------
+#define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */
+#define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */
+#define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */
+#define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */
+#define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */
+#define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */
+#define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */
+#define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */
+#define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */
+#define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */
+#define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */
+#define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */
+
+// ---------------------------------------- UART1_MCR -------------------------------------------
+#define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */
+#define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */
+#define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */
+#define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */
+#define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */
+#define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */
+#define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */
+#define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */
+#define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */
+#define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */
+
+// ---------------------------------------- UART1_LSR -------------------------------------------
+#define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */
+#define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */
+#define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */
+#define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */
+#define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */
+#define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */
+#define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */
+#define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */
+#define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */
+#define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */
+#define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */
+#define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */
+#define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */
+#define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */
+#define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */
+#define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */
+
+// ---------------------------------------- UART1_MSR -------------------------------------------
+#define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */
+#define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */
+#define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */
+#define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */
+#define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */
+#define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */
+#define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */
+#define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */
+#define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */
+#define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */
+#define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */
+#define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */
+#define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */
+#define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */
+#define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */
+#define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */
+
+// ---------------------------------------- UART1_SCR -------------------------------------------
+#define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */
+#define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */
+
+// ---------------------------------------- UART1_ACR -------------------------------------------
+#define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */
+#define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */
+#define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */
+#define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */
+#define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */
+#define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */
+#define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */
+#define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */
+#define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */
+#define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */
+
+// ---------------------------------------- UART1_FDR -------------------------------------------
+#define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */
+#define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */
+#define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */
+#define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */
+
+// ---------------------------------------- UART1_TER -------------------------------------------
+#define UART1_TER_TXEN_Pos 7 /*!< UART1 TER: TXEN Position */
+#define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */
+
+// ------------------------------------- UART1_RS485CTRL ----------------------------------------
+#define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */
+#define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */
+#define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */
+#define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */
+#define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */
+#define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */
+#define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */
+#define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */
+#define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */
+#define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */
+#define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */
+#define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */
+
+// ----------------------------------- UART1_RS485ADRMATCH --------------------------------------
+#define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */
+#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- UART1_RS485DLY -----------------------------------------
+#define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */
+#define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */
+
+// -------------------------------------- UART1_FIFOLVL -----------------------------------------
+#define UART1_FIFOLVL_RXFIFILVL_Pos 0 /*!< UART1 FIFOLVL: RXFIFILVL Position */
+#define UART1_FIFOLVL_RXFIFILVL_Msk (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos) /*!< UART1 FIFOLVL: RXFIFILVL Mask */
+#define UART1_FIFOLVL_TXFIFOLVL_Pos 8 /*!< UART1 FIFOLVL: TXFIFOLVL Position */
+#define UART1_FIFOLVL_TXFIFOLVL_Msk (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos) /*!< UART1 FIFOLVL: TXFIFOLVL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- SSP0_CR0 --------------------------------------------
+#define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */
+#define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */
+#define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */
+#define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */
+#define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */
+#define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */
+#define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */
+#define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */
+#define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */
+#define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */
+
+// ---------------------------------------- SSP0_CR1 --------------------------------------------
+#define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */
+#define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */
+#define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */
+#define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */
+#define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */
+#define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */
+#define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */
+#define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */
+
+// ----------------------------------------- SSP0_DR --------------------------------------------
+#define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */
+#define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */
+
+// ----------------------------------------- SSP0_SR --------------------------------------------
+#define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */
+#define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */
+#define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */
+#define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */
+#define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */
+#define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */
+#define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */
+#define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */
+#define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */
+#define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */
+
+// ---------------------------------------- SSP0_CPSR -------------------------------------------
+#define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */
+#define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */
+
+// ---------------------------------------- SSP0_IMSC -------------------------------------------
+#define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */
+#define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */
+#define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */
+#define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */
+#define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */
+#define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */
+#define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */
+#define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */
+
+// ---------------------------------------- SSP0_RIS --------------------------------------------
+#define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */
+#define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */
+#define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */
+#define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */
+#define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */
+#define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */
+#define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */
+#define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */
+
+// ---------------------------------------- SSP0_MIS --------------------------------------------
+#define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */
+#define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */
+#define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */
+#define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */
+#define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */
+#define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */
+#define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */
+#define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */
+
+// ---------------------------------------- SSP0_ICR --------------------------------------------
+#define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */
+#define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */
+#define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */
+#define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */
+
+// --------------------------------------- SSP0_DMACR -------------------------------------------
+#define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */
+#define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */
+#define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */
+#define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- SSP1_CR0 --------------------------------------------
+#define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */
+#define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */
+#define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */
+#define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */
+#define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */
+#define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */
+#define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */
+#define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */
+#define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */
+#define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */
+
+// ---------------------------------------- SSP1_CR1 --------------------------------------------
+#define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */
+#define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */
+#define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */
+#define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */
+#define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */
+#define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */
+#define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */
+#define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */
+
+// ----------------------------------------- SSP1_DR --------------------------------------------
+#define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */
+#define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */
+
+// ----------------------------------------- SSP1_SR --------------------------------------------
+#define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */
+#define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */
+#define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */
+#define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */
+#define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */
+#define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */
+#define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */
+#define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */
+#define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */
+#define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */
+
+// ---------------------------------------- SSP1_CPSR -------------------------------------------
+#define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */
+#define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */
+
+// ---------------------------------------- SSP1_IMSC -------------------------------------------
+#define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */
+#define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */
+#define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */
+#define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */
+#define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */
+#define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */
+#define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */
+#define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */
+
+// ---------------------------------------- SSP1_RIS --------------------------------------------
+#define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */
+#define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */
+#define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */
+#define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */
+#define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */
+#define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */
+#define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */
+#define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */
+
+// ---------------------------------------- SSP1_MIS --------------------------------------------
+#define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */
+#define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */
+#define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */
+#define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */
+#define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */
+#define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */
+#define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */
+#define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */
+
+// ---------------------------------------- SSP1_ICR --------------------------------------------
+#define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */
+#define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */
+#define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */
+#define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */
+
+// --------------------------------------- SSP1_DMACR -------------------------------------------
+#define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */
+#define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */
+#define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */
+#define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER0_IR -------------------------------------------
+#define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */
+#define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */
+#define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */
+#define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */
+#define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */
+#define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */
+#define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */
+#define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */
+#define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */
+#define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */
+#define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */
+#define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */
+#define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */
+#define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */
+#define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */
+#define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER0_TCR -------------------------------------------
+#define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */
+#define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */
+#define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */
+#define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER0_TC -------------------------------------------
+#define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */
+#define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */
+
+// ---------------------------------------- TIMER0_PR -------------------------------------------
+#define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */
+#define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */
+
+// ---------------------------------------- TIMER0_PC -------------------------------------------
+#define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */
+#define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */
+
+// --------------------------------------- TIMER0_MCR -------------------------------------------
+#define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */
+#define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */
+#define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */
+#define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */
+#define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */
+#define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */
+#define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */
+#define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */
+#define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */
+#define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */
+#define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */
+#define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */
+#define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */
+#define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */
+#define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */
+#define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */
+#define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */
+#define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */
+#define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */
+#define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */
+#define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */
+#define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */
+#define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */
+#define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER0_MR0 -------------------------------------------
+#define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */
+#define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER0_MR1 -------------------------------------------
+#define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */
+#define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER0_MR2 -------------------------------------------
+#define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */
+#define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER0_MR3 -------------------------------------------
+#define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */
+#define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER0_CCR -------------------------------------------
+#define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */
+#define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */
+#define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */
+#define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */
+#define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */
+#define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */
+#define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */
+#define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */
+#define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */
+#define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */
+#define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */
+#define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */
+#define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */
+#define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */
+#define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */
+#define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */
+#define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */
+#define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */
+#define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */
+#define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */
+#define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */
+#define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */
+#define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */
+#define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER0_CR0 -------------------------------------------
+#define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */
+#define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */
+
+// --------------------------------------- TIMER0_CR1 -------------------------------------------
+#define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */
+#define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */
+
+// --------------------------------------- TIMER0_CR2 -------------------------------------------
+#define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */
+#define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */
+
+// --------------------------------------- TIMER0_CR3 -------------------------------------------
+#define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */
+#define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */
+
+// --------------------------------------- TIMER0_EMR -------------------------------------------
+#define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */
+#define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */
+#define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */
+#define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */
+#define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */
+#define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */
+#define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */
+#define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */
+#define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */
+#define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */
+#define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */
+#define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */
+#define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */
+#define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */
+#define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */
+#define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER0_CTCR ------------------------------------------
+#define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */
+#define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */
+#define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */
+#define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER1_IR -------------------------------------------
+#define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */
+#define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */
+#define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */
+#define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */
+#define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */
+#define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */
+#define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */
+#define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */
+#define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */
+#define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */
+#define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */
+#define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */
+#define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */
+#define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */
+#define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */
+#define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER1_TCR -------------------------------------------
+#define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */
+#define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */
+#define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */
+#define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER1_TC -------------------------------------------
+#define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */
+#define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */
+
+// ---------------------------------------- TIMER1_PR -------------------------------------------
+#define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */
+#define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */
+
+// ---------------------------------------- TIMER1_PC -------------------------------------------
+#define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */
+#define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */
+
+// --------------------------------------- TIMER1_MCR -------------------------------------------
+#define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */
+#define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */
+#define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */
+#define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */
+#define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */
+#define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */
+#define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */
+#define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */
+#define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */
+#define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */
+#define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */
+#define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */
+#define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */
+#define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */
+#define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */
+#define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */
+#define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */
+#define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */
+#define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */
+#define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */
+#define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */
+#define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */
+#define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */
+#define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER1_MR0 -------------------------------------------
+#define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */
+#define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER1_MR1 -------------------------------------------
+#define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */
+#define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER1_MR2 -------------------------------------------
+#define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */
+#define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER1_MR3 -------------------------------------------
+#define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */
+#define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER1_CCR -------------------------------------------
+#define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */
+#define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */
+#define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */
+#define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */
+#define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */
+#define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */
+#define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */
+#define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */
+#define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */
+#define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */
+#define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */
+#define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */
+#define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */
+#define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */
+#define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */
+#define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */
+#define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */
+#define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */
+#define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */
+#define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */
+#define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */
+#define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */
+#define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */
+#define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER1_CR0 -------------------------------------------
+#define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */
+#define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */
+
+// --------------------------------------- TIMER1_CR1 -------------------------------------------
+#define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */
+#define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */
+
+// --------------------------------------- TIMER1_CR2 -------------------------------------------
+#define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */
+#define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */
+
+// --------------------------------------- TIMER1_CR3 -------------------------------------------
+#define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */
+#define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */
+
+// --------------------------------------- TIMER1_EMR -------------------------------------------
+#define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */
+#define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */
+#define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */
+#define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */
+#define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */
+#define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */
+#define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */
+#define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */
+#define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */
+#define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */
+#define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */
+#define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */
+#define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */
+#define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */
+#define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */
+#define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER1_CTCR ------------------------------------------
+#define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */
+#define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */
+#define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */
+#define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER2 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER2_IR -------------------------------------------
+#define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */
+#define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */
+#define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */
+#define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */
+#define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */
+#define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */
+#define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */
+#define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */
+#define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */
+#define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */
+#define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */
+#define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */
+#define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */
+#define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */
+#define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */
+#define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER2_TCR -------------------------------------------
+#define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */
+#define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */
+#define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */
+#define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER2_TC -------------------------------------------
+#define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */
+#define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */
+
+// ---------------------------------------- TIMER2_PR -------------------------------------------
+#define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */
+#define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */
+
+// ---------------------------------------- TIMER2_PC -------------------------------------------
+#define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */
+#define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */
+
+// --------------------------------------- TIMER2_MCR -------------------------------------------
+#define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */
+#define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */
+#define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */
+#define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */
+#define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */
+#define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */
+#define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */
+#define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */
+#define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */
+#define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */
+#define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */
+#define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */
+#define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */
+#define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */
+#define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */
+#define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */
+#define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */
+#define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */
+#define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */
+#define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */
+#define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */
+#define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */
+#define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */
+#define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER2_MR0 -------------------------------------------
+#define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */
+#define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER2_MR1 -------------------------------------------
+#define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */
+#define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER2_MR2 -------------------------------------------
+#define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */
+#define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER2_MR3 -------------------------------------------
+#define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */
+#define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER2_CCR -------------------------------------------
+#define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */
+#define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */
+#define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */
+#define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */
+#define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */
+#define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */
+#define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */
+#define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */
+#define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */
+#define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */
+#define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */
+#define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */
+#define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */
+#define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */
+#define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */
+#define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */
+#define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */
+#define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */
+#define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */
+#define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */
+#define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */
+#define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */
+#define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */
+#define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER2_CR0 -------------------------------------------
+#define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */
+#define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */
+
+// --------------------------------------- TIMER2_CR1 -------------------------------------------
+#define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */
+#define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */
+
+// --------------------------------------- TIMER2_CR2 -------------------------------------------
+#define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */
+#define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */
+
+// --------------------------------------- TIMER2_CR3 -------------------------------------------
+#define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */
+#define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */
+
+// --------------------------------------- TIMER2_EMR -------------------------------------------
+#define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */
+#define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */
+#define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */
+#define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */
+#define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */
+#define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */
+#define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */
+#define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */
+#define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */
+#define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */
+#define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */
+#define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */
+#define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */
+#define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */
+#define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */
+#define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER2_CTCR ------------------------------------------
+#define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */
+#define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */
+#define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */
+#define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER3 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER3_IR -------------------------------------------
+#define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */
+#define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */
+#define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */
+#define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */
+#define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */
+#define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */
+#define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */
+#define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */
+#define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */
+#define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */
+#define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */
+#define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */
+#define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */
+#define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */
+#define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */
+#define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER3_TCR -------------------------------------------
+#define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */
+#define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */
+#define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */
+#define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER3_TC -------------------------------------------
+#define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */
+#define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */
+
+// ---------------------------------------- TIMER3_PR -------------------------------------------
+#define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */
+#define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */
+
+// ---------------------------------------- TIMER3_PC -------------------------------------------
+#define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */
+#define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */
+
+// --------------------------------------- TIMER3_MCR -------------------------------------------
+#define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */
+#define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */
+#define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */
+#define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */
+#define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */
+#define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */
+#define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */
+#define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */
+#define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */
+#define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */
+#define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */
+#define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */
+#define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */
+#define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */
+#define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */
+#define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */
+#define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */
+#define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */
+#define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */
+#define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */
+#define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */
+#define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */
+#define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */
+#define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER3_MR0 -------------------------------------------
+#define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */
+#define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER3_MR1 -------------------------------------------
+#define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */
+#define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER3_MR2 -------------------------------------------
+#define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */
+#define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER3_MR3 -------------------------------------------
+#define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */
+#define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER3_CCR -------------------------------------------
+#define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */
+#define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */
+#define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */
+#define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */
+#define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */
+#define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */
+#define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */
+#define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */
+#define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */
+#define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */
+#define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */
+#define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */
+#define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */
+#define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */
+#define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */
+#define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */
+#define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */
+#define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */
+#define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */
+#define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */
+#define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */
+#define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */
+#define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */
+#define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER3_CR0 -------------------------------------------
+#define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */
+#define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */
+
+// --------------------------------------- TIMER3_CR1 -------------------------------------------
+#define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */
+#define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */
+
+// --------------------------------------- TIMER3_CR2 -------------------------------------------
+#define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */
+#define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */
+
+// --------------------------------------- TIMER3_CR3 -------------------------------------------
+#define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */
+#define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */
+
+// --------------------------------------- TIMER3_EMR -------------------------------------------
+#define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */
+#define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */
+#define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */
+#define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */
+#define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */
+#define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */
+#define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */
+#define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */
+#define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */
+#define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */
+#define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */
+#define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */
+#define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */
+#define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */
+#define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */
+#define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER3_CTCR ------------------------------------------
+#define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */
+#define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */
+#define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */
+#define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SCU Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- SCU_SFSP0_0 ------------------------------------------
+#define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */
+#define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */
+#define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */
+#define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */
+#define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */
+#define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */
+#define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */
+#define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */
+#define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */
+#define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */
+
+// --------------------------------------- SCU_SFSP0_1 ------------------------------------------
+#define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */
+#define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */
+#define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */
+#define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */
+#define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */
+#define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */
+#define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */
+#define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */
+#define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */
+#define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */
+
+// --------------------------------------- SCU_SFSP1_0 ------------------------------------------
+#define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */
+#define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */
+#define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */
+#define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */
+#define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */
+#define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */
+#define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */
+#define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */
+#define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */
+#define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */
+#define SCU_SFSP1_0_EHD_Pos 8 /*!< SCU SFSP1_0: EHD Position */
+#define SCU_SFSP1_0_EHD_Msk (0x03UL << SCU_SFSP1_0_EHD_Pos) /*!< SCU SFSP1_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_1 ------------------------------------------
+#define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */
+#define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */
+#define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */
+#define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */
+#define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */
+#define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */
+#define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */
+#define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */
+#define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */
+#define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */
+#define SCU_SFSP1_1_EHD_Pos 8 /*!< SCU SFSP1_1: EHD Position */
+#define SCU_SFSP1_1_EHD_Msk (0x03UL << SCU_SFSP1_1_EHD_Pos) /*!< SCU SFSP1_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_2 ------------------------------------------
+#define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */
+#define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */
+#define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */
+#define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */
+#define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */
+#define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */
+#define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */
+#define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */
+#define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */
+#define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */
+#define SCU_SFSP1_2_EHD_Pos 8 /*!< SCU SFSP1_2: EHD Position */
+#define SCU_SFSP1_2_EHD_Msk (0x03UL << SCU_SFSP1_2_EHD_Pos) /*!< SCU SFSP1_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_3 ------------------------------------------
+#define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */
+#define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */
+#define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */
+#define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */
+#define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */
+#define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */
+#define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */
+#define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */
+#define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */
+#define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */
+#define SCU_SFSP1_3_EHD_Pos 8 /*!< SCU SFSP1_3: EHD Position */
+#define SCU_SFSP1_3_EHD_Msk (0x03UL << SCU_SFSP1_3_EHD_Pos) /*!< SCU SFSP1_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_4 ------------------------------------------
+#define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */
+#define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */
+#define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */
+#define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */
+#define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */
+#define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */
+#define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */
+#define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */
+#define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */
+#define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */
+#define SCU_SFSP1_4_EHD_Pos 8 /*!< SCU SFSP1_4: EHD Position */
+#define SCU_SFSP1_4_EHD_Msk (0x03UL << SCU_SFSP1_4_EHD_Pos) /*!< SCU SFSP1_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_5 ------------------------------------------
+#define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */
+#define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */
+#define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */
+#define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */
+#define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */
+#define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */
+#define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */
+#define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */
+#define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */
+#define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */
+#define SCU_SFSP1_5_EHD_Pos 8 /*!< SCU SFSP1_5: EHD Position */
+#define SCU_SFSP1_5_EHD_Msk (0x03UL << SCU_SFSP1_5_EHD_Pos) /*!< SCU SFSP1_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_6 ------------------------------------------
+#define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */
+#define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */
+#define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */
+#define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */
+#define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */
+#define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */
+#define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */
+#define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */
+#define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */
+#define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */
+#define SCU_SFSP1_6_EHD_Pos 8 /*!< SCU SFSP1_6: EHD Position */
+#define SCU_SFSP1_6_EHD_Msk (0x03UL << SCU_SFSP1_6_EHD_Pos) /*!< SCU SFSP1_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_7 ------------------------------------------
+#define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */
+#define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */
+#define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */
+#define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */
+#define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */
+#define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */
+#define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */
+#define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */
+#define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */
+#define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */
+#define SCU_SFSP1_7_EHD_Pos 8 /*!< SCU SFSP1_7: EHD Position */
+#define SCU_SFSP1_7_EHD_Msk (0x03UL << SCU_SFSP1_7_EHD_Pos) /*!< SCU SFSP1_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_8 ------------------------------------------
+#define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */
+#define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */
+#define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */
+#define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */
+#define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */
+#define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */
+#define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */
+#define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */
+#define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */
+#define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */
+#define SCU_SFSP1_8_EHD_Pos 8 /*!< SCU SFSP1_8: EHD Position */
+#define SCU_SFSP1_8_EHD_Msk (0x03UL << SCU_SFSP1_8_EHD_Pos) /*!< SCU SFSP1_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_9 ------------------------------------------
+#define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */
+#define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */
+#define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */
+#define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */
+#define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */
+#define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */
+#define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */
+#define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */
+#define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */
+#define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */
+#define SCU_SFSP1_9_EHD_Pos 8 /*!< SCU SFSP1_9: EHD Position */
+#define SCU_SFSP1_9_EHD_Msk (0x03UL << SCU_SFSP1_9_EHD_Pos) /*!< SCU SFSP1_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_10 ------------------------------------------
+#define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */
+#define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */
+#define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */
+#define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */
+#define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */
+#define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */
+#define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */
+#define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */
+#define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */
+#define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */
+#define SCU_SFSP1_10_EHD_Pos 8 /*!< SCU SFSP1_10: EHD Position */
+#define SCU_SFSP1_10_EHD_Msk (0x03UL << SCU_SFSP1_10_EHD_Pos) /*!< SCU SFSP1_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_11 ------------------------------------------
+#define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */
+#define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */
+#define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */
+#define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */
+#define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */
+#define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */
+#define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */
+#define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */
+#define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */
+#define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */
+#define SCU_SFSP1_11_EHD_Pos 8 /*!< SCU SFSP1_11: EHD Position */
+#define SCU_SFSP1_11_EHD_Msk (0x03UL << SCU_SFSP1_11_EHD_Pos) /*!< SCU SFSP1_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_12 ------------------------------------------
+#define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */
+#define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */
+#define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */
+#define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */
+#define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */
+#define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */
+#define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */
+#define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */
+#define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */
+#define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */
+#define SCU_SFSP1_12_EHD_Pos 8 /*!< SCU SFSP1_12: EHD Position */
+#define SCU_SFSP1_12_EHD_Msk (0x03UL << SCU_SFSP1_12_EHD_Pos) /*!< SCU SFSP1_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_13 ------------------------------------------
+#define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */
+#define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */
+#define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */
+#define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */
+#define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */
+#define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */
+#define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */
+#define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */
+#define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */
+#define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */
+#define SCU_SFSP1_13_EHD_Pos 8 /*!< SCU SFSP1_13: EHD Position */
+#define SCU_SFSP1_13_EHD_Msk (0x03UL << SCU_SFSP1_13_EHD_Pos) /*!< SCU SFSP1_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_14 ------------------------------------------
+#define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */
+#define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */
+#define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */
+#define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */
+#define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */
+#define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */
+#define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */
+#define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */
+#define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */
+#define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */
+#define SCU_SFSP1_14_EHD_Pos 8 /*!< SCU SFSP1_14: EHD Position */
+#define SCU_SFSP1_14_EHD_Msk (0x03UL << SCU_SFSP1_14_EHD_Pos) /*!< SCU SFSP1_14: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_15 ------------------------------------------
+#define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */
+#define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */
+#define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */
+#define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */
+#define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */
+#define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */
+#define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */
+#define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */
+#define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */
+#define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */
+#define SCU_SFSP1_15_EHD_Pos 8 /*!< SCU SFSP1_15: EHD Position */
+#define SCU_SFSP1_15_EHD_Msk (0x03UL << SCU_SFSP1_15_EHD_Pos) /*!< SCU SFSP1_15: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_16 ------------------------------------------
+#define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */
+#define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */
+#define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */
+#define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */
+#define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */
+#define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */
+#define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */
+#define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */
+#define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */
+#define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */
+#define SCU_SFSP1_16_EHD_Pos 8 /*!< SCU SFSP1_16: EHD Position */
+#define SCU_SFSP1_16_EHD_Msk (0x03UL << SCU_SFSP1_16_EHD_Pos) /*!< SCU SFSP1_16: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_17 ------------------------------------------
+#define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */
+#define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */
+#define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */
+#define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */
+#define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */
+#define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */
+#define SCU_SFSP1_17_EHS_Pos 5 /*!< SCU SFSP1_17: EHS Position */
+#define SCU_SFSP1_17_EHS_Msk (0x01UL << SCU_SFSP1_17_EHS_Pos) /*!< SCU SFSP1_17: EHS Mask */
+#define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */
+#define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */
+#define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */
+#define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_18 ------------------------------------------
+#define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */
+#define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */
+#define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */
+#define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */
+#define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */
+#define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */
+#define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */
+#define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */
+#define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */
+#define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */
+#define SCU_SFSP1_18_EHD_Pos 8 /*!< SCU SFSP1_18: EHD Position */
+#define SCU_SFSP1_18_EHD_Msk (0x03UL << SCU_SFSP1_18_EHD_Pos) /*!< SCU SFSP1_18: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_19 ------------------------------------------
+#define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */
+#define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */
+#define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */
+#define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */
+#define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */
+#define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */
+#define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */
+#define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */
+#define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */
+#define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */
+#define SCU_SFSP1_19_EHD_Pos 8 /*!< SCU SFSP1_19: EHD Position */
+#define SCU_SFSP1_19_EHD_Msk (0x03UL << SCU_SFSP1_19_EHD_Pos) /*!< SCU SFSP1_19: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_20 ------------------------------------------
+#define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */
+#define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */
+#define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */
+#define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */
+#define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */
+#define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */
+#define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */
+#define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */
+#define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */
+#define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */
+#define SCU_SFSP1_20_EHD_Pos 8 /*!< SCU SFSP1_20: EHD Position */
+#define SCU_SFSP1_20_EHD_Msk (0x03UL << SCU_SFSP1_20_EHD_Pos) /*!< SCU SFSP1_20: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_0 ------------------------------------------
+#define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */
+#define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */
+#define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */
+#define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */
+#define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */
+#define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */
+#define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */
+#define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */
+#define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */
+#define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */
+#define SCU_SFSP2_0_EHD_Pos 8 /*!< SCU SFSP2_0: EHD Position */
+#define SCU_SFSP2_0_EHD_Msk (0x03UL << SCU_SFSP2_0_EHD_Pos) /*!< SCU SFSP2_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_1 ------------------------------------------
+#define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */
+#define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */
+#define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */
+#define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */
+#define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */
+#define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */
+#define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */
+#define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */
+#define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */
+#define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */
+#define SCU_SFSP2_1_EHD_Pos 8 /*!< SCU SFSP2_1: EHD Position */
+#define SCU_SFSP2_1_EHD_Msk (0x03UL << SCU_SFSP2_1_EHD_Pos) /*!< SCU SFSP2_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_2 ------------------------------------------
+#define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */
+#define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */
+#define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */
+#define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */
+#define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */
+#define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */
+#define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */
+#define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */
+#define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */
+#define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */
+#define SCU_SFSP2_2_EHD_Pos 8 /*!< SCU SFSP2_2: EHD Position */
+#define SCU_SFSP2_2_EHD_Msk (0x03UL << SCU_SFSP2_2_EHD_Pos) /*!< SCU SFSP2_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_3 ------------------------------------------
+#define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */
+#define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */
+#define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */
+#define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */
+#define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */
+#define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */
+#define SCU_SFSP2_3_EHS_Pos 5 /*!< SCU SFSP2_3: EHS Position */
+#define SCU_SFSP2_3_EHS_Msk (0x01UL << SCU_SFSP2_3_EHS_Pos) /*!< SCU SFSP2_3: EHS Mask */
+#define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */
+#define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */
+#define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */
+#define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_4 ------------------------------------------
+#define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */
+#define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */
+#define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */
+#define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */
+#define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */
+#define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */
+#define SCU_SFSP2_4_EHS_Pos 5 /*!< SCU SFSP2_4: EHS Position */
+#define SCU_SFSP2_4_EHS_Msk (0x01UL << SCU_SFSP2_4_EHS_Pos) /*!< SCU SFSP2_4: EHS Mask */
+#define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */
+#define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */
+#define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */
+#define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_5 ------------------------------------------
+#define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */
+#define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */
+#define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */
+#define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */
+#define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */
+#define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */
+#define SCU_SFSP2_5_EHS_Pos 5 /*!< SCU SFSP2_5: EHS Position */
+#define SCU_SFSP2_5_EHS_Msk (0x01UL << SCU_SFSP2_5_EHS_Pos) /*!< SCU SFSP2_5: EHS Mask */
+#define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */
+#define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */
+#define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */
+#define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_6 ------------------------------------------
+#define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */
+#define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */
+#define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */
+#define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */
+#define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */
+#define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */
+#define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */
+#define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */
+#define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */
+#define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */
+#define SCU_SFSP2_6_EHD_Pos 8 /*!< SCU SFSP2_6: EHD Position */
+#define SCU_SFSP2_6_EHD_Msk (0x03UL << SCU_SFSP2_6_EHD_Pos) /*!< SCU SFSP2_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_7 ------------------------------------------
+#define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */
+#define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */
+#define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */
+#define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */
+#define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */
+#define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */
+#define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */
+#define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */
+#define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */
+#define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */
+#define SCU_SFSP2_7_EHD_Pos 8 /*!< SCU SFSP2_7: EHD Position */
+#define SCU_SFSP2_7_EHD_Msk (0x03UL << SCU_SFSP2_7_EHD_Pos) /*!< SCU SFSP2_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_8 ------------------------------------------
+#define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */
+#define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */
+#define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */
+#define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */
+#define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */
+#define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */
+#define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */
+#define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */
+#define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */
+#define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */
+#define SCU_SFSP2_8_EHD_Pos 8 /*!< SCU SFSP2_8: EHD Position */
+#define SCU_SFSP2_8_EHD_Msk (0x03UL << SCU_SFSP2_8_EHD_Pos) /*!< SCU SFSP2_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_9 ------------------------------------------
+#define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */
+#define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */
+#define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */
+#define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */
+#define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */
+#define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */
+#define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */
+#define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */
+#define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */
+#define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */
+#define SCU_SFSP2_9_EHD_Pos 8 /*!< SCU SFSP2_9: EHD Position */
+#define SCU_SFSP2_9_EHD_Msk (0x03UL << SCU_SFSP2_9_EHD_Pos) /*!< SCU SFSP2_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_10 ------------------------------------------
+#define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */
+#define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */
+#define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */
+#define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */
+#define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */
+#define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */
+#define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */
+#define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */
+#define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */
+#define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */
+#define SCU_SFSP2_10_EHD_Pos 8 /*!< SCU SFSP2_10: EHD Position */
+#define SCU_SFSP2_10_EHD_Msk (0x03UL << SCU_SFSP2_10_EHD_Pos) /*!< SCU SFSP2_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_11 ------------------------------------------
+#define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */
+#define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */
+#define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */
+#define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */
+#define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */
+#define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */
+#define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */
+#define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */
+#define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */
+#define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */
+#define SCU_SFSP2_11_EHD_Pos 8 /*!< SCU SFSP2_11: EHD Position */
+#define SCU_SFSP2_11_EHD_Msk (0x03UL << SCU_SFSP2_11_EHD_Pos) /*!< SCU SFSP2_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_12 ------------------------------------------
+#define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */
+#define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */
+#define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */
+#define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */
+#define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */
+#define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */
+#define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */
+#define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */
+#define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */
+#define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */
+#define SCU_SFSP2_12_EHD_Pos 8 /*!< SCU SFSP2_12: EHD Position */
+#define SCU_SFSP2_12_EHD_Msk (0x03UL << SCU_SFSP2_12_EHD_Pos) /*!< SCU SFSP2_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_13 ------------------------------------------
+#define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */
+#define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */
+#define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */
+#define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */
+#define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */
+#define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */
+#define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */
+#define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */
+#define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */
+#define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */
+#define SCU_SFSP2_13_EHD_Pos 8 /*!< SCU SFSP2_13: EHD Position */
+#define SCU_SFSP2_13_EHD_Msk (0x03UL << SCU_SFSP2_13_EHD_Pos) /*!< SCU SFSP2_13: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_0 ------------------------------------------
+#define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */
+#define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */
+#define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */
+#define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */
+#define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */
+#define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */
+#define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */
+#define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */
+#define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */
+#define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */
+#define SCU_SFSP3_0_EHD_Pos 8 /*!< SCU SFSP3_0: EHD Position */
+#define SCU_SFSP3_0_EHD_Msk (0x03UL << SCU_SFSP3_0_EHD_Pos) /*!< SCU SFSP3_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_1 ------------------------------------------
+#define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */
+#define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */
+#define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */
+#define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */
+#define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */
+#define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */
+#define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */
+#define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */
+#define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */
+#define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */
+#define SCU_SFSP3_1_EHD_Pos 8 /*!< SCU SFSP3_1: EHD Position */
+#define SCU_SFSP3_1_EHD_Msk (0x03UL << SCU_SFSP3_1_EHD_Pos) /*!< SCU SFSP3_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_2 ------------------------------------------
+#define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */
+#define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */
+#define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */
+#define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */
+#define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */
+#define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */
+#define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */
+#define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */
+#define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */
+#define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */
+#define SCU_SFSP3_2_EHD_Pos 8 /*!< SCU SFSP3_2: EHD Position */
+#define SCU_SFSP3_2_EHD_Msk (0x03UL << SCU_SFSP3_2_EHD_Pos) /*!< SCU SFSP3_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_3 ------------------------------------------
+#define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */
+#define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */
+#define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */
+#define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */
+#define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */
+#define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */
+#define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */
+#define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */
+#define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */
+#define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */
+#define SCU_SFSP3_3_EHD_Pos 8 /*!< SCU SFSP3_3: EHD Position */
+#define SCU_SFSP3_3_EHD_Msk (0x03UL << SCU_SFSP3_3_EHD_Pos) /*!< SCU SFSP3_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_4 ------------------------------------------
+#define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */
+#define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */
+#define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */
+#define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */
+#define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */
+#define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */
+#define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */
+#define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */
+#define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */
+#define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */
+#define SCU_SFSP3_4_EHD_Pos 8 /*!< SCU SFSP3_4: EHD Position */
+#define SCU_SFSP3_4_EHD_Msk (0x03UL << SCU_SFSP3_4_EHD_Pos) /*!< SCU SFSP3_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_5 ------------------------------------------
+#define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */
+#define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */
+#define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */
+#define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */
+#define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */
+#define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */
+#define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */
+#define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */
+#define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */
+#define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */
+#define SCU_SFSP3_5_EHD_Pos 8 /*!< SCU SFSP3_5: EHD Position */
+#define SCU_SFSP3_5_EHD_Msk (0x03UL << SCU_SFSP3_5_EHD_Pos) /*!< SCU SFSP3_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_6 ------------------------------------------
+#define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */
+#define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */
+#define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */
+#define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */
+#define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */
+#define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */
+#define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */
+#define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */
+#define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */
+#define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */
+#define SCU_SFSP3_6_EHD_Pos 8 /*!< SCU SFSP3_6: EHD Position */
+#define SCU_SFSP3_6_EHD_Msk (0x03UL << SCU_SFSP3_6_EHD_Pos) /*!< SCU SFSP3_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_7 ------------------------------------------
+#define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */
+#define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */
+#define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */
+#define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */
+#define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */
+#define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */
+#define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */
+#define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */
+#define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */
+#define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */
+#define SCU_SFSP3_7_EHD_Pos 8 /*!< SCU SFSP3_7: EHD Position */
+#define SCU_SFSP3_7_EHD_Msk (0x03UL << SCU_SFSP3_7_EHD_Pos) /*!< SCU SFSP3_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_8 ------------------------------------------
+#define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */
+#define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */
+#define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */
+#define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */
+#define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */
+#define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */
+#define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */
+#define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */
+#define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */
+#define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */
+#define SCU_SFSP3_8_EHD_Pos 8 /*!< SCU SFSP3_8: EHD Position */
+#define SCU_SFSP3_8_EHD_Msk (0x03UL << SCU_SFSP3_8_EHD_Pos) /*!< SCU SFSP3_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_0 ------------------------------------------
+#define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */
+#define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */
+#define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */
+#define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */
+#define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */
+#define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */
+#define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */
+#define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */
+#define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */
+#define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */
+#define SCU_SFSP4_0_EHD_Pos 8 /*!< SCU SFSP4_0: EHD Position */
+#define SCU_SFSP4_0_EHD_Msk (0x03UL << SCU_SFSP4_0_EHD_Pos) /*!< SCU SFSP4_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_1 ------------------------------------------
+#define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */
+#define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */
+#define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */
+#define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */
+#define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */
+#define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */
+#define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */
+#define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */
+#define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */
+#define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */
+#define SCU_SFSP4_1_EHD_Pos 8 /*!< SCU SFSP4_1: EHD Position */
+#define SCU_SFSP4_1_EHD_Msk (0x03UL << SCU_SFSP4_1_EHD_Pos) /*!< SCU SFSP4_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_2 ------------------------------------------
+#define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */
+#define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */
+#define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */
+#define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */
+#define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */
+#define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */
+#define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */
+#define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */
+#define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */
+#define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */
+#define SCU_SFSP4_2_EHD_Pos 8 /*!< SCU SFSP4_2: EHD Position */
+#define SCU_SFSP4_2_EHD_Msk (0x03UL << SCU_SFSP4_2_EHD_Pos) /*!< SCU SFSP4_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_3 ------------------------------------------
+#define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */
+#define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */
+#define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */
+#define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */
+#define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */
+#define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */
+#define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */
+#define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */
+#define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */
+#define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */
+#define SCU_SFSP4_3_EHD_Pos 8 /*!< SCU SFSP4_3: EHD Position */
+#define SCU_SFSP4_3_EHD_Msk (0x03UL << SCU_SFSP4_3_EHD_Pos) /*!< SCU SFSP4_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_4 ------------------------------------------
+#define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */
+#define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */
+#define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */
+#define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */
+#define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */
+#define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */
+#define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */
+#define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */
+#define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */
+#define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */
+#define SCU_SFSP4_4_EHD_Pos 8 /*!< SCU SFSP4_4: EHD Position */
+#define SCU_SFSP4_4_EHD_Msk (0x03UL << SCU_SFSP4_4_EHD_Pos) /*!< SCU SFSP4_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_5 ------------------------------------------
+#define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */
+#define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */
+#define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */
+#define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */
+#define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */
+#define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */
+#define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */
+#define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */
+#define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */
+#define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */
+#define SCU_SFSP4_5_EHD_Pos 8 /*!< SCU SFSP4_5: EHD Position */
+#define SCU_SFSP4_5_EHD_Msk (0x03UL << SCU_SFSP4_5_EHD_Pos) /*!< SCU SFSP4_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_6 ------------------------------------------
+#define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */
+#define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */
+#define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */
+#define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */
+#define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */
+#define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */
+#define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */
+#define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */
+#define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */
+#define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */
+#define SCU_SFSP4_6_EHD_Pos 8 /*!< SCU SFSP4_6: EHD Position */
+#define SCU_SFSP4_6_EHD_Msk (0x03UL << SCU_SFSP4_6_EHD_Pos) /*!< SCU SFSP4_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_7 ------------------------------------------
+#define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */
+#define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */
+#define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */
+#define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */
+#define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */
+#define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */
+#define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */
+#define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */
+#define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */
+#define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */
+#define SCU_SFSP4_7_EHD_Pos 8 /*!< SCU SFSP4_7: EHD Position */
+#define SCU_SFSP4_7_EHD_Msk (0x03UL << SCU_SFSP4_7_EHD_Pos) /*!< SCU SFSP4_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_8 ------------------------------------------
+#define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */
+#define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */
+#define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */
+#define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */
+#define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */
+#define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */
+#define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */
+#define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */
+#define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */
+#define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */
+#define SCU_SFSP4_8_EHD_Pos 8 /*!< SCU SFSP4_8: EHD Position */
+#define SCU_SFSP4_8_EHD_Msk (0x03UL << SCU_SFSP4_8_EHD_Pos) /*!< SCU SFSP4_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_9 ------------------------------------------
+#define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */
+#define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */
+#define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */
+#define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */
+#define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */
+#define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */
+#define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */
+#define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */
+#define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */
+#define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */
+#define SCU_SFSP4_9_EHD_Pos 8 /*!< SCU SFSP4_9: EHD Position */
+#define SCU_SFSP4_9_EHD_Msk (0x03UL << SCU_SFSP4_9_EHD_Pos) /*!< SCU SFSP4_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP4_10 ------------------------------------------
+#define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */
+#define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */
+#define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */
+#define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */
+#define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */
+#define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */
+#define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */
+#define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */
+#define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */
+#define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */
+#define SCU_SFSP4_10_EHD_Pos 8 /*!< SCU SFSP4_10: EHD Position */
+#define SCU_SFSP4_10_EHD_Msk (0x03UL << SCU_SFSP4_10_EHD_Pos) /*!< SCU SFSP4_10: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_0 ------------------------------------------
+#define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */
+#define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */
+#define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */
+#define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */
+#define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */
+#define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */
+#define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */
+#define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */
+#define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */
+#define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */
+#define SCU_SFSP5_0_EHD_Pos 8 /*!< SCU SFSP5_0: EHD Position */
+#define SCU_SFSP5_0_EHD_Msk (0x03UL << SCU_SFSP5_0_EHD_Pos) /*!< SCU SFSP5_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_1 ------------------------------------------
+#define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */
+#define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */
+#define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */
+#define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */
+#define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */
+#define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */
+#define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */
+#define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */
+#define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */
+#define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */
+#define SCU_SFSP5_1_EHD_Pos 8 /*!< SCU SFSP5_1: EHD Position */
+#define SCU_SFSP5_1_EHD_Msk (0x03UL << SCU_SFSP5_1_EHD_Pos) /*!< SCU SFSP5_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_2 ------------------------------------------
+#define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */
+#define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */
+#define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */
+#define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */
+#define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */
+#define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */
+#define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */
+#define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */
+#define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */
+#define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */
+#define SCU_SFSP5_2_EHD_Pos 8 /*!< SCU SFSP5_2: EHD Position */
+#define SCU_SFSP5_2_EHD_Msk (0x03UL << SCU_SFSP5_2_EHD_Pos) /*!< SCU SFSP5_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_3 ------------------------------------------
+#define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */
+#define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */
+#define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */
+#define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */
+#define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */
+#define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */
+#define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */
+#define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */
+#define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */
+#define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */
+#define SCU_SFSP5_3_EHD_Pos 8 /*!< SCU SFSP5_3: EHD Position */
+#define SCU_SFSP5_3_EHD_Msk (0x03UL << SCU_SFSP5_3_EHD_Pos) /*!< SCU SFSP5_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_4 ------------------------------------------
+#define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */
+#define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */
+#define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */
+#define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */
+#define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */
+#define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */
+#define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */
+#define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */
+#define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */
+#define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */
+#define SCU_SFSP5_4_EHD_Pos 8 /*!< SCU SFSP5_4: EHD Position */
+#define SCU_SFSP5_4_EHD_Msk (0x03UL << SCU_SFSP5_4_EHD_Pos) /*!< SCU SFSP5_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_5 ------------------------------------------
+#define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */
+#define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */
+#define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */
+#define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */
+#define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */
+#define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */
+#define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */
+#define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */
+#define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */
+#define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */
+#define SCU_SFSP5_5_EHD_Pos 8 /*!< SCU SFSP5_5: EHD Position */
+#define SCU_SFSP5_5_EHD_Msk (0x03UL << SCU_SFSP5_5_EHD_Pos) /*!< SCU SFSP5_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_6 ------------------------------------------
+#define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */
+#define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */
+#define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */
+#define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */
+#define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */
+#define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */
+#define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */
+#define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */
+#define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */
+#define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */
+#define SCU_SFSP5_6_EHD_Pos 8 /*!< SCU SFSP5_6: EHD Position */
+#define SCU_SFSP5_6_EHD_Msk (0x03UL << SCU_SFSP5_6_EHD_Pos) /*!< SCU SFSP5_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_7 ------------------------------------------
+#define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */
+#define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */
+#define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */
+#define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */
+#define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */
+#define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */
+#define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */
+#define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */
+#define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */
+#define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */
+#define SCU_SFSP5_7_EHD_Pos 8 /*!< SCU SFSP5_7: EHD Position */
+#define SCU_SFSP5_7_EHD_Msk (0x03UL << SCU_SFSP5_7_EHD_Pos) /*!< SCU SFSP5_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_0 ------------------------------------------
+#define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */
+#define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */
+#define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */
+#define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */
+#define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */
+#define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */
+#define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */
+#define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */
+#define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */
+#define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */
+#define SCU_SFSP6_0_EHD_Pos 8 /*!< SCU SFSP6_0: EHD Position */
+#define SCU_SFSP6_0_EHD_Msk (0x03UL << SCU_SFSP6_0_EHD_Pos) /*!< SCU SFSP6_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_1 ------------------------------------------
+#define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */
+#define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */
+#define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */
+#define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */
+#define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */
+#define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */
+#define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */
+#define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */
+#define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */
+#define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */
+#define SCU_SFSP6_1_EHD_Pos 8 /*!< SCU SFSP6_1: EHD Position */
+#define SCU_SFSP6_1_EHD_Msk (0x03UL << SCU_SFSP6_1_EHD_Pos) /*!< SCU SFSP6_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_2 ------------------------------------------
+#define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */
+#define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */
+#define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */
+#define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */
+#define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */
+#define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */
+#define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */
+#define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */
+#define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */
+#define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */
+#define SCU_SFSP6_2_EHD_Pos 8 /*!< SCU SFSP6_2: EHD Position */
+#define SCU_SFSP6_2_EHD_Msk (0x03UL << SCU_SFSP6_2_EHD_Pos) /*!< SCU SFSP6_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_3 ------------------------------------------
+#define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */
+#define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */
+#define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */
+#define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */
+#define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */
+#define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */
+#define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */
+#define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */
+#define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */
+#define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */
+#define SCU_SFSP6_3_EHD_Pos 8 /*!< SCU SFSP6_3: EHD Position */
+#define SCU_SFSP6_3_EHD_Msk (0x03UL << SCU_SFSP6_3_EHD_Pos) /*!< SCU SFSP6_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_4 ------------------------------------------
+#define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */
+#define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */
+#define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */
+#define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */
+#define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */
+#define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */
+#define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */
+#define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */
+#define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */
+#define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */
+#define SCU_SFSP6_4_EHD_Pos 8 /*!< SCU SFSP6_4: EHD Position */
+#define SCU_SFSP6_4_EHD_Msk (0x03UL << SCU_SFSP6_4_EHD_Pos) /*!< SCU SFSP6_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_5 ------------------------------------------
+#define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */
+#define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */
+#define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */
+#define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */
+#define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */
+#define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */
+#define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */
+#define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */
+#define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */
+#define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */
+#define SCU_SFSP6_5_EHD_Pos 8 /*!< SCU SFSP6_5: EHD Position */
+#define SCU_SFSP6_5_EHD_Msk (0x03UL << SCU_SFSP6_5_EHD_Pos) /*!< SCU SFSP6_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_6 ------------------------------------------
+#define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */
+#define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */
+#define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */
+#define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */
+#define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */
+#define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */
+#define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */
+#define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */
+#define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */
+#define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */
+#define SCU_SFSP6_6_EHD_Pos 8 /*!< SCU SFSP6_6: EHD Position */
+#define SCU_SFSP6_6_EHD_Msk (0x03UL << SCU_SFSP6_6_EHD_Pos) /*!< SCU SFSP6_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_7 ------------------------------------------
+#define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */
+#define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */
+#define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */
+#define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */
+#define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */
+#define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */
+#define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */
+#define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */
+#define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */
+#define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */
+#define SCU_SFSP6_7_EHD_Pos 8 /*!< SCU SFSP6_7: EHD Position */
+#define SCU_SFSP6_7_EHD_Msk (0x03UL << SCU_SFSP6_7_EHD_Pos) /*!< SCU SFSP6_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_8 ------------------------------------------
+#define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */
+#define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */
+#define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */
+#define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */
+#define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */
+#define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */
+#define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */
+#define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */
+#define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */
+#define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */
+#define SCU_SFSP6_8_EHD_Pos 8 /*!< SCU SFSP6_8: EHD Position */
+#define SCU_SFSP6_8_EHD_Msk (0x03UL << SCU_SFSP6_8_EHD_Pos) /*!< SCU SFSP6_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_9 ------------------------------------------
+#define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */
+#define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */
+#define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */
+#define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */
+#define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */
+#define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */
+#define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */
+#define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */
+#define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */
+#define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */
+#define SCU_SFSP6_9_EHD_Pos 8 /*!< SCU SFSP6_9: EHD Position */
+#define SCU_SFSP6_9_EHD_Msk (0x03UL << SCU_SFSP6_9_EHD_Pos) /*!< SCU SFSP6_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP6_10 ------------------------------------------
+#define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */
+#define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */
+#define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */
+#define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */
+#define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */
+#define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */
+#define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */
+#define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */
+#define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */
+#define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */
+#define SCU_SFSP6_10_EHD_Pos 8 /*!< SCU SFSP6_10: EHD Position */
+#define SCU_SFSP6_10_EHD_Msk (0x03UL << SCU_SFSP6_10_EHD_Pos) /*!< SCU SFSP6_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSP6_11 ------------------------------------------
+#define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */
+#define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */
+#define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */
+#define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */
+#define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */
+#define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */
+#define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */
+#define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */
+#define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */
+#define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */
+#define SCU_SFSP6_11_EHD_Pos 8 /*!< SCU SFSP6_11: EHD Position */
+#define SCU_SFSP6_11_EHD_Msk (0x03UL << SCU_SFSP6_11_EHD_Pos) /*!< SCU SFSP6_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSP6_12 ------------------------------------------
+#define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */
+#define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */
+#define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */
+#define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */
+#define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */
+#define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */
+#define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */
+#define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */
+#define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */
+#define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */
+#define SCU_SFSP6_12_EHD_Pos 8 /*!< SCU SFSP6_12: EHD Position */
+#define SCU_SFSP6_12_EHD_Msk (0x03UL << SCU_SFSP6_12_EHD_Pos) /*!< SCU SFSP6_12: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_0 ------------------------------------------
+#define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */
+#define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */
+#define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */
+#define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */
+#define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */
+#define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */
+#define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */
+#define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */
+#define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */
+#define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */
+#define SCU_SFSP7_0_EHD_Pos 8 /*!< SCU SFSP7_0: EHD Position */
+#define SCU_SFSP7_0_EHD_Msk (0x03UL << SCU_SFSP7_0_EHD_Pos) /*!< SCU SFSP7_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_1 ------------------------------------------
+#define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */
+#define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */
+#define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */
+#define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */
+#define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */
+#define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */
+#define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */
+#define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */
+#define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */
+#define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */
+#define SCU_SFSP7_1_EHD_Pos 8 /*!< SCU SFSP7_1: EHD Position */
+#define SCU_SFSP7_1_EHD_Msk (0x03UL << SCU_SFSP7_1_EHD_Pos) /*!< SCU SFSP7_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_2 ------------------------------------------
+#define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */
+#define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */
+#define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */
+#define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */
+#define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */
+#define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */
+#define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */
+#define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */
+#define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */
+#define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */
+#define SCU_SFSP7_2_EHD_Pos 8 /*!< SCU SFSP7_2: EHD Position */
+#define SCU_SFSP7_2_EHD_Msk (0x03UL << SCU_SFSP7_2_EHD_Pos) /*!< SCU SFSP7_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_3 ------------------------------------------
+#define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */
+#define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */
+#define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */
+#define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */
+#define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */
+#define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */
+#define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */
+#define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */
+#define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */
+#define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */
+#define SCU_SFSP7_3_EHD_Pos 8 /*!< SCU SFSP7_3: EHD Position */
+#define SCU_SFSP7_3_EHD_Msk (0x03UL << SCU_SFSP7_3_EHD_Pos) /*!< SCU SFSP7_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_4 ------------------------------------------
+#define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */
+#define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */
+#define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */
+#define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */
+#define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */
+#define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */
+#define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */
+#define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */
+#define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */
+#define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */
+#define SCU_SFSP7_4_EHD_Pos 8 /*!< SCU SFSP7_4: EHD Position */
+#define SCU_SFSP7_4_EHD_Msk (0x03UL << SCU_SFSP7_4_EHD_Pos) /*!< SCU SFSP7_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_5 ------------------------------------------
+#define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */
+#define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */
+#define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */
+#define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */
+#define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */
+#define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */
+#define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */
+#define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */
+#define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */
+#define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */
+#define SCU_SFSP7_5_EHD_Pos 8 /*!< SCU SFSP7_5: EHD Position */
+#define SCU_SFSP7_5_EHD_Msk (0x03UL << SCU_SFSP7_5_EHD_Pos) /*!< SCU SFSP7_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_6 ------------------------------------------
+#define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */
+#define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */
+#define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */
+#define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */
+#define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */
+#define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */
+#define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */
+#define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */
+#define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */
+#define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */
+#define SCU_SFSP7_6_EHD_Pos 8 /*!< SCU SFSP7_6: EHD Position */
+#define SCU_SFSP7_6_EHD_Msk (0x03UL << SCU_SFSP7_6_EHD_Pos) /*!< SCU SFSP7_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_7 ------------------------------------------
+#define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */
+#define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */
+#define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */
+#define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */
+#define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */
+#define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */
+#define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */
+#define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */
+#define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */
+#define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */
+#define SCU_SFSP7_7_EHD_Pos 8 /*!< SCU SFSP7_7: EHD Position */
+#define SCU_SFSP7_7_EHD_Msk (0x03UL << SCU_SFSP7_7_EHD_Pos) /*!< SCU SFSP7_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_0 ------------------------------------------
+#define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */
+#define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */
+#define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */
+#define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */
+#define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */
+#define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */
+#define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */
+#define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */
+#define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */
+#define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */
+#define SCU_SFSP8_0_EHD_Pos 8 /*!< SCU SFSP8_0: EHD Position */
+#define SCU_SFSP8_0_EHD_Msk (0x03UL << SCU_SFSP8_0_EHD_Pos) /*!< SCU SFSP8_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_1 ------------------------------------------
+#define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */
+#define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */
+#define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */
+#define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */
+#define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */
+#define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */
+#define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */
+#define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */
+#define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */
+#define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */
+#define SCU_SFSP8_1_EHD_Pos 8 /*!< SCU SFSP8_1: EHD Position */
+#define SCU_SFSP8_1_EHD_Msk (0x03UL << SCU_SFSP8_1_EHD_Pos) /*!< SCU SFSP8_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_2 ------------------------------------------
+#define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */
+#define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */
+#define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */
+#define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */
+#define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */
+#define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */
+#define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */
+#define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */
+#define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */
+#define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */
+#define SCU_SFSP8_2_EHD_Pos 8 /*!< SCU SFSP8_2: EHD Position */
+#define SCU_SFSP8_2_EHD_Msk (0x03UL << SCU_SFSP8_2_EHD_Pos) /*!< SCU SFSP8_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_3 ------------------------------------------
+#define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */
+#define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */
+#define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */
+#define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */
+#define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */
+#define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */
+#define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */
+#define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */
+#define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */
+#define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */
+#define SCU_SFSP8_3_EHD_Pos 8 /*!< SCU SFSP8_3: EHD Position */
+#define SCU_SFSP8_3_EHD_Msk (0x03UL << SCU_SFSP8_3_EHD_Pos) /*!< SCU SFSP8_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_4 ------------------------------------------
+#define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */
+#define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */
+#define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */
+#define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */
+#define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */
+#define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */
+#define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */
+#define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */
+#define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */
+#define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */
+#define SCU_SFSP8_4_EHD_Pos 8 /*!< SCU SFSP8_4: EHD Position */
+#define SCU_SFSP8_4_EHD_Msk (0x03UL << SCU_SFSP8_4_EHD_Pos) /*!< SCU SFSP8_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_5 ------------------------------------------
+#define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */
+#define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */
+#define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */
+#define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */
+#define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */
+#define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */
+#define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */
+#define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */
+#define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */
+#define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */
+#define SCU_SFSP8_5_EHD_Pos 8 /*!< SCU SFSP8_5: EHD Position */
+#define SCU_SFSP8_5_EHD_Msk (0x03UL << SCU_SFSP8_5_EHD_Pos) /*!< SCU SFSP8_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_6 ------------------------------------------
+#define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */
+#define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */
+#define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */
+#define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */
+#define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */
+#define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */
+#define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */
+#define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */
+#define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */
+#define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */
+#define SCU_SFSP8_6_EHD_Pos 8 /*!< SCU SFSP8_6: EHD Position */
+#define SCU_SFSP8_6_EHD_Msk (0x03UL << SCU_SFSP8_6_EHD_Pos) /*!< SCU SFSP8_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_7 ------------------------------------------
+#define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */
+#define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */
+#define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */
+#define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */
+#define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */
+#define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */
+#define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */
+#define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */
+#define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */
+#define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */
+#define SCU_SFSP8_7_EHD_Pos 8 /*!< SCU SFSP8_7: EHD Position */
+#define SCU_SFSP8_7_EHD_Msk (0x03UL << SCU_SFSP8_7_EHD_Pos) /*!< SCU SFSP8_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_8 ------------------------------------------
+#define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */
+#define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */
+#define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */
+#define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */
+#define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */
+#define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */
+#define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */
+#define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */
+#define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */
+#define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */
+#define SCU_SFSP8_8_EHD_Pos 8 /*!< SCU SFSP8_8: EHD Position */
+#define SCU_SFSP8_8_EHD_Msk (0x03UL << SCU_SFSP8_8_EHD_Pos) /*!< SCU SFSP8_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_0 ------------------------------------------
+#define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */
+#define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */
+#define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */
+#define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */
+#define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */
+#define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */
+#define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */
+#define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */
+#define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */
+#define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */
+#define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */
+#define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_1 ------------------------------------------
+#define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */
+#define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */
+#define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */
+#define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */
+#define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */
+#define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */
+#define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */
+#define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */
+#define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */
+#define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */
+#define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */
+#define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_2 ------------------------------------------
+#define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */
+#define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */
+#define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */
+#define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */
+#define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */
+#define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */
+#define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */
+#define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */
+#define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */
+#define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */
+#define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */
+#define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_3 ------------------------------------------
+#define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */
+#define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */
+#define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */
+#define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */
+#define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */
+#define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */
+#define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */
+#define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */
+#define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */
+#define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */
+#define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */
+#define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_4 ------------------------------------------
+#define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */
+#define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */
+#define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */
+#define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */
+#define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */
+#define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */
+#define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */
+#define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */
+#define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */
+#define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */
+#define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */
+#define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_5 ------------------------------------------
+#define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */
+#define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */
+#define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */
+#define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */
+#define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */
+#define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */
+#define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */
+#define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */
+#define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */
+#define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */
+#define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */
+#define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_6 ------------------------------------------
+#define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */
+#define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */
+#define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */
+#define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */
+#define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */
+#define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */
+#define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */
+#define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */
+#define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */
+#define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */
+#define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */
+#define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_0 ------------------------------------------
+#define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */
+#define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */
+#define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */
+#define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */
+#define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */
+#define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */
+#define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */
+#define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */
+#define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */
+#define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */
+#define SCU_SFSPA_0_EHD_Pos 8 /*!< SCU SFSPA_0: EHD Position */
+#define SCU_SFSPA_0_EHD_Msk (0x03UL << SCU_SFSPA_0_EHD_Pos) /*!< SCU SFSPA_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_1 ------------------------------------------
+#define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */
+#define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */
+#define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */
+#define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */
+#define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */
+#define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */
+#define SCU_SFSPA_1_EHS_Pos 5 /*!< SCU SFSPA_1: EHS Position */
+#define SCU_SFSPA_1_EHS_Msk (0x01UL << SCU_SFSPA_1_EHS_Pos) /*!< SCU SFSPA_1: EHS Mask */
+#define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */
+#define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */
+#define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */
+#define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_2 ------------------------------------------
+#define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */
+#define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */
+#define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */
+#define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */
+#define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */
+#define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */
+#define SCU_SFSPA_2_EHS_Pos 5 /*!< SCU SFSPA_2: EHS Position */
+#define SCU_SFSPA_2_EHS_Msk (0x01UL << SCU_SFSPA_2_EHS_Pos) /*!< SCU SFSPA_2: EHS Mask */
+#define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */
+#define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */
+#define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */
+#define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_3 ------------------------------------------
+#define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */
+#define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */
+#define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */
+#define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */
+#define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */
+#define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */
+#define SCU_SFSPA_3_EHS_Pos 5 /*!< SCU SFSPA_3: EHS Position */
+#define SCU_SFSPA_3_EHS_Msk (0x01UL << SCU_SFSPA_3_EHS_Pos) /*!< SCU SFSPA_3: EHS Mask */
+#define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */
+#define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */
+#define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */
+#define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_4 ------------------------------------------
+#define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */
+#define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */
+#define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */
+#define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */
+#define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */
+#define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */
+#define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */
+#define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */
+#define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */
+#define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */
+#define SCU_SFSPA_4_EHD_Pos 8 /*!< SCU SFSPA_4: EHD Position */
+#define SCU_SFSPA_4_EHD_Msk (0x03UL << SCU_SFSPA_4_EHD_Pos) /*!< SCU SFSPA_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_0 ------------------------------------------
+#define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */
+#define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */
+#define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */
+#define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */
+#define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */
+#define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */
+#define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */
+#define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */
+#define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */
+#define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */
+#define SCU_SFSPB_0_EHD_Pos 8 /*!< SCU SFSPB_0: EHD Position */
+#define SCU_SFSPB_0_EHD_Msk (0x03UL << SCU_SFSPB_0_EHD_Pos) /*!< SCU SFSPB_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_1 ------------------------------------------
+#define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */
+#define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */
+#define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */
+#define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */
+#define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */
+#define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */
+#define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */
+#define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */
+#define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */
+#define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */
+#define SCU_SFSPB_1_EHD_Pos 8 /*!< SCU SFSPB_1: EHD Position */
+#define SCU_SFSPB_1_EHD_Msk (0x03UL << SCU_SFSPB_1_EHD_Pos) /*!< SCU SFSPB_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_2 ------------------------------------------
+#define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */
+#define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */
+#define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */
+#define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */
+#define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */
+#define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */
+#define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */
+#define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */
+#define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */
+#define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */
+#define SCU_SFSPB_2_EHD_Pos 8 /*!< SCU SFSPB_2: EHD Position */
+#define SCU_SFSPB_2_EHD_Msk (0x03UL << SCU_SFSPB_2_EHD_Pos) /*!< SCU SFSPB_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_3 ------------------------------------------
+#define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */
+#define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */
+#define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */
+#define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */
+#define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */
+#define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */
+#define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */
+#define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */
+#define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */
+#define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */
+#define SCU_SFSPB_3_EHD_Pos 8 /*!< SCU SFSPB_3: EHD Position */
+#define SCU_SFSPB_3_EHD_Msk (0x03UL << SCU_SFSPB_3_EHD_Pos) /*!< SCU SFSPB_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_4 ------------------------------------------
+#define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */
+#define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */
+#define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */
+#define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */
+#define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */
+#define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */
+#define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */
+#define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */
+#define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */
+#define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */
+#define SCU_SFSPB_4_EHD_Pos 8 /*!< SCU SFSPB_4: EHD Position */
+#define SCU_SFSPB_4_EHD_Msk (0x03UL << SCU_SFSPB_4_EHD_Pos) /*!< SCU SFSPB_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_5 ------------------------------------------
+#define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */
+#define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */
+#define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */
+#define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */
+#define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */
+#define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */
+#define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */
+#define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */
+#define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */
+#define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */
+#define SCU_SFSPB_5_EHD_Pos 8 /*!< SCU SFSPB_5: EHD Position */
+#define SCU_SFSPB_5_EHD_Msk (0x03UL << SCU_SFSPB_5_EHD_Pos) /*!< SCU SFSPB_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_6 ------------------------------------------
+#define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */
+#define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */
+#define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */
+#define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */
+#define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */
+#define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */
+#define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */
+#define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */
+#define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */
+#define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */
+#define SCU_SFSPB_6_EHD_Pos 8 /*!< SCU SFSPB_6: EHD Position */
+#define SCU_SFSPB_6_EHD_Msk (0x03UL << SCU_SFSPB_6_EHD_Pos) /*!< SCU SFSPB_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_0 ------------------------------------------
+#define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */
+#define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */
+#define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */
+#define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */
+#define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */
+#define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */
+#define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */
+#define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */
+#define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */
+#define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */
+#define SCU_SFSPC_0_EHD_Pos 8 /*!< SCU SFSPC_0: EHD Position */
+#define SCU_SFSPC_0_EHD_Msk (0x03UL << SCU_SFSPC_0_EHD_Pos) /*!< SCU SFSPC_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_1 ------------------------------------------
+#define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */
+#define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */
+#define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */
+#define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */
+#define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */
+#define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */
+#define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */
+#define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */
+#define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */
+#define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */
+#define SCU_SFSPC_1_EHD_Pos 8 /*!< SCU SFSPC_1: EHD Position */
+#define SCU_SFSPC_1_EHD_Msk (0x03UL << SCU_SFSPC_1_EHD_Pos) /*!< SCU SFSPC_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_2 ------------------------------------------
+#define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */
+#define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */
+#define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */
+#define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */
+#define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */
+#define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */
+#define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */
+#define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */
+#define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */
+#define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */
+#define SCU_SFSPC_2_EHD_Pos 8 /*!< SCU SFSPC_2: EHD Position */
+#define SCU_SFSPC_2_EHD_Msk (0x03UL << SCU_SFSPC_2_EHD_Pos) /*!< SCU SFSPC_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_3 ------------------------------------------
+#define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */
+#define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */
+#define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */
+#define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */
+#define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */
+#define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */
+#define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */
+#define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */
+#define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */
+#define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */
+#define SCU_SFSPC_3_EHD_Pos 8 /*!< SCU SFSPC_3: EHD Position */
+#define SCU_SFSPC_3_EHD_Msk (0x03UL << SCU_SFSPC_3_EHD_Pos) /*!< SCU SFSPC_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_4 ------------------------------------------
+#define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */
+#define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */
+#define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */
+#define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */
+#define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */
+#define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */
+#define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */
+#define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */
+#define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */
+#define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */
+#define SCU_SFSPC_4_EHD_Pos 8 /*!< SCU SFSPC_4: EHD Position */
+#define SCU_SFSPC_4_EHD_Msk (0x03UL << SCU_SFSPC_4_EHD_Pos) /*!< SCU SFSPC_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_5 ------------------------------------------
+#define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */
+#define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */
+#define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */
+#define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */
+#define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */
+#define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */
+#define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */
+#define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */
+#define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */
+#define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */
+#define SCU_SFSPC_5_EHD_Pos 8 /*!< SCU SFSPC_5: EHD Position */
+#define SCU_SFSPC_5_EHD_Msk (0x03UL << SCU_SFSPC_5_EHD_Pos) /*!< SCU SFSPC_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_6 ------------------------------------------
+#define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */
+#define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */
+#define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */
+#define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */
+#define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */
+#define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */
+#define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */
+#define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */
+#define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */
+#define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */
+#define SCU_SFSPC_6_EHD_Pos 8 /*!< SCU SFSPC_6: EHD Position */
+#define SCU_SFSPC_6_EHD_Msk (0x03UL << SCU_SFSPC_6_EHD_Pos) /*!< SCU SFSPC_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_7 ------------------------------------------
+#define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */
+#define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */
+#define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */
+#define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */
+#define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */
+#define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */
+#define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */
+#define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */
+#define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */
+#define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */
+#define SCU_SFSPC_7_EHD_Pos 8 /*!< SCU SFSPC_7: EHD Position */
+#define SCU_SFSPC_7_EHD_Msk (0x03UL << SCU_SFSPC_7_EHD_Pos) /*!< SCU SFSPC_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_8 ------------------------------------------
+#define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */
+#define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */
+#define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */
+#define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */
+#define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */
+#define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */
+#define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */
+#define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */
+#define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */
+#define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */
+#define SCU_SFSPC_8_EHD_Pos 8 /*!< SCU SFSPC_8: EHD Position */
+#define SCU_SFSPC_8_EHD_Msk (0x03UL << SCU_SFSPC_8_EHD_Pos) /*!< SCU SFSPC_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_9 ------------------------------------------
+#define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */
+#define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */
+#define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */
+#define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */
+#define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */
+#define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */
+#define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */
+#define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */
+#define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */
+#define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */
+#define SCU_SFSPC_9_EHD_Pos 8 /*!< SCU SFSPC_9: EHD Position */
+#define SCU_SFSPC_9_EHD_Msk (0x03UL << SCU_SFSPC_9_EHD_Pos) /*!< SCU SFSPC_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_10 ------------------------------------------
+#define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */
+#define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */
+#define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */
+#define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */
+#define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */
+#define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */
+#define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */
+#define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */
+#define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */
+#define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */
+#define SCU_SFSPC_10_EHD_Pos 8 /*!< SCU SFSPC_10: EHD Position */
+#define SCU_SFSPC_10_EHD_Msk (0x03UL << SCU_SFSPC_10_EHD_Pos) /*!< SCU SFSPC_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_11 ------------------------------------------
+#define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */
+#define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */
+#define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */
+#define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */
+#define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */
+#define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */
+#define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */
+#define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */
+#define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */
+#define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */
+#define SCU_SFSPC_11_EHD_Pos 8 /*!< SCU SFSPC_11: EHD Position */
+#define SCU_SFSPC_11_EHD_Msk (0x03UL << SCU_SFSPC_11_EHD_Pos) /*!< SCU SFSPC_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_12 ------------------------------------------
+#define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */
+#define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */
+#define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */
+#define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */
+#define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */
+#define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */
+#define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */
+#define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */
+#define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */
+#define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */
+#define SCU_SFSPC_12_EHD_Pos 8 /*!< SCU SFSPC_12: EHD Position */
+#define SCU_SFSPC_12_EHD_Msk (0x03UL << SCU_SFSPC_12_EHD_Pos) /*!< SCU SFSPC_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_13 ------------------------------------------
+#define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */
+#define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */
+#define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */
+#define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */
+#define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */
+#define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */
+#define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */
+#define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */
+#define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */
+#define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */
+#define SCU_SFSPC_13_EHD_Pos 8 /*!< SCU SFSPC_13: EHD Position */
+#define SCU_SFSPC_13_EHD_Msk (0x03UL << SCU_SFSPC_13_EHD_Pos) /*!< SCU SFSPC_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_14 ------------------------------------------
+#define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */
+#define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */
+#define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */
+#define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */
+#define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */
+#define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */
+#define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */
+#define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */
+#define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */
+#define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */
+#define SCU_SFSPC_14_EHD_Pos 8 /*!< SCU SFSPC_14: EHD Position */
+#define SCU_SFSPC_14_EHD_Msk (0x03UL << SCU_SFSPC_14_EHD_Pos) /*!< SCU SFSPC_14: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_0 ------------------------------------------
+#define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */
+#define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */
+#define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */
+#define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */
+#define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */
+#define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */
+#define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */
+#define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */
+#define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */
+#define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */
+#define SCU_SFSPD_0_EHD_Pos 8 /*!< SCU SFSPD_0: EHD Position */
+#define SCU_SFSPD_0_EHD_Msk (0x03UL << SCU_SFSPD_0_EHD_Pos) /*!< SCU SFSPD_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_1 ------------------------------------------
+#define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */
+#define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */
+#define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */
+#define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */
+#define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */
+#define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */
+#define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */
+#define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */
+#define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */
+#define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */
+#define SCU_SFSPD_1_EHD_Pos 8 /*!< SCU SFSPD_1: EHD Position */
+#define SCU_SFSPD_1_EHD_Msk (0x03UL << SCU_SFSPD_1_EHD_Pos) /*!< SCU SFSPD_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_2 ------------------------------------------
+#define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */
+#define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */
+#define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */
+#define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */
+#define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */
+#define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */
+#define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */
+#define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */
+#define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */
+#define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */
+#define SCU_SFSPD_2_EHD_Pos 8 /*!< SCU SFSPD_2: EHD Position */
+#define SCU_SFSPD_2_EHD_Msk (0x03UL << SCU_SFSPD_2_EHD_Pos) /*!< SCU SFSPD_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_3 ------------------------------------------
+#define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */
+#define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */
+#define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */
+#define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */
+#define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */
+#define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */
+#define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */
+#define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */
+#define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */
+#define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */
+#define SCU_SFSPD_3_EHD_Pos 8 /*!< SCU SFSPD_3: EHD Position */
+#define SCU_SFSPD_3_EHD_Msk (0x03UL << SCU_SFSPD_3_EHD_Pos) /*!< SCU SFSPD_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_4 ------------------------------------------
+#define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */
+#define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */
+#define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */
+#define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */
+#define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */
+#define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */
+#define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */
+#define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */
+#define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */
+#define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */
+#define SCU_SFSPD_4_EHD_Pos 8 /*!< SCU SFSPD_4: EHD Position */
+#define SCU_SFSPD_4_EHD_Msk (0x03UL << SCU_SFSPD_4_EHD_Pos) /*!< SCU SFSPD_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_5 ------------------------------------------
+#define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */
+#define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */
+#define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */
+#define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */
+#define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */
+#define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */
+#define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */
+#define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */
+#define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */
+#define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */
+#define SCU_SFSPD_5_EHD_Pos 8 /*!< SCU SFSPD_5: EHD Position */
+#define SCU_SFSPD_5_EHD_Msk (0x03UL << SCU_SFSPD_5_EHD_Pos) /*!< SCU SFSPD_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_6 ------------------------------------------
+#define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */
+#define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */
+#define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */
+#define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */
+#define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */
+#define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */
+#define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */
+#define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */
+#define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */
+#define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */
+#define SCU_SFSPD_6_EHD_Pos 8 /*!< SCU SFSPD_6: EHD Position */
+#define SCU_SFSPD_6_EHD_Msk (0x03UL << SCU_SFSPD_6_EHD_Pos) /*!< SCU SFSPD_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_7 ------------------------------------------
+#define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */
+#define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */
+#define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */
+#define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */
+#define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */
+#define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */
+#define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */
+#define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */
+#define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */
+#define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */
+#define SCU_SFSPD_7_EHD_Pos 8 /*!< SCU SFSPD_7: EHD Position */
+#define SCU_SFSPD_7_EHD_Msk (0x03UL << SCU_SFSPD_7_EHD_Pos) /*!< SCU SFSPD_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_8 ------------------------------------------
+#define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */
+#define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */
+#define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */
+#define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */
+#define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */
+#define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */
+#define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */
+#define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */
+#define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */
+#define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */
+#define SCU_SFSPD_8_EHD_Pos 8 /*!< SCU SFSPD_8: EHD Position */
+#define SCU_SFSPD_8_EHD_Msk (0x03UL << SCU_SFSPD_8_EHD_Pos) /*!< SCU SFSPD_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_9 ------------------------------------------
+#define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */
+#define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */
+#define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */
+#define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */
+#define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */
+#define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */
+#define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */
+#define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */
+#define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */
+#define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */
+#define SCU_SFSPD_9_EHD_Pos 8 /*!< SCU SFSPD_9: EHD Position */
+#define SCU_SFSPD_9_EHD_Msk (0x03UL << SCU_SFSPD_9_EHD_Pos) /*!< SCU SFSPD_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_10 ------------------------------------------
+#define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */
+#define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */
+#define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */
+#define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */
+#define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */
+#define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */
+#define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */
+#define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */
+#define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */
+#define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */
+#define SCU_SFSPD_10_EHD_Pos 8 /*!< SCU SFSPD_10: EHD Position */
+#define SCU_SFSPD_10_EHD_Msk (0x03UL << SCU_SFSPD_10_EHD_Pos) /*!< SCU SFSPD_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_11 ------------------------------------------
+#define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */
+#define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */
+#define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */
+#define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */
+#define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */
+#define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */
+#define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */
+#define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */
+#define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */
+#define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */
+#define SCU_SFSPD_11_EHD_Pos 8 /*!< SCU SFSPD_11: EHD Position */
+#define SCU_SFSPD_11_EHD_Msk (0x03UL << SCU_SFSPD_11_EHD_Pos) /*!< SCU SFSPD_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_12 ------------------------------------------
+#define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */
+#define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */
+#define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */
+#define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */
+#define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */
+#define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */
+#define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */
+#define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */
+#define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */
+#define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */
+#define SCU_SFSPD_12_EHD_Pos 8 /*!< SCU SFSPD_12: EHD Position */
+#define SCU_SFSPD_12_EHD_Msk (0x03UL << SCU_SFSPD_12_EHD_Pos) /*!< SCU SFSPD_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_13 ------------------------------------------
+#define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */
+#define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */
+#define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */
+#define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */
+#define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */
+#define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */
+#define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */
+#define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */
+#define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */
+#define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */
+#define SCU_SFSPD_13_EHD_Pos 8 /*!< SCU SFSPD_13: EHD Position */
+#define SCU_SFSPD_13_EHD_Msk (0x03UL << SCU_SFSPD_13_EHD_Pos) /*!< SCU SFSPD_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_14 ------------------------------------------
+#define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */
+#define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */
+#define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */
+#define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */
+#define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */
+#define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */
+#define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */
+#define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */
+#define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */
+#define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */
+#define SCU_SFSPD_14_EHD_Pos 8 /*!< SCU SFSPD_14: EHD Position */
+#define SCU_SFSPD_14_EHD_Msk (0x03UL << SCU_SFSPD_14_EHD_Pos) /*!< SCU SFSPD_14: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_15 ------------------------------------------
+#define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */
+#define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */
+#define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */
+#define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */
+#define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */
+#define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */
+#define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */
+#define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */
+#define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */
+#define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */
+#define SCU_SFSPD_15_EHD_Pos 8 /*!< SCU SFSPD_15: EHD Position */
+#define SCU_SFSPD_15_EHD_Msk (0x03UL << SCU_SFSPD_15_EHD_Pos) /*!< SCU SFSPD_15: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_16 ------------------------------------------
+#define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */
+#define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */
+#define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */
+#define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */
+#define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */
+#define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */
+#define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */
+#define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */
+#define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */
+#define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */
+#define SCU_SFSPD_16_EHD_Pos 8 /*!< SCU SFSPD_16: EHD Position */
+#define SCU_SFSPD_16_EHD_Msk (0x03UL << SCU_SFSPD_16_EHD_Pos) /*!< SCU SFSPD_16: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_0 ------------------------------------------
+#define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */
+#define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */
+#define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */
+#define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */
+#define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */
+#define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */
+#define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */
+#define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */
+#define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */
+#define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */
+#define SCU_SFSPE_0_EHD_Pos 8 /*!< SCU SFSPE_0: EHD Position */
+#define SCU_SFSPE_0_EHD_Msk (0x03UL << SCU_SFSPE_0_EHD_Pos) /*!< SCU SFSPE_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_1 ------------------------------------------
+#define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */
+#define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */
+#define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */
+#define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */
+#define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */
+#define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */
+#define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */
+#define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */
+#define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */
+#define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */
+#define SCU_SFSPE_1_EHD_Pos 8 /*!< SCU SFSPE_1: EHD Position */
+#define SCU_SFSPE_1_EHD_Msk (0x03UL << SCU_SFSPE_1_EHD_Pos) /*!< SCU SFSPE_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_2 ------------------------------------------
+#define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */
+#define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */
+#define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */
+#define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */
+#define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */
+#define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */
+#define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */
+#define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */
+#define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */
+#define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */
+#define SCU_SFSPE_2_EHD_Pos 8 /*!< SCU SFSPE_2: EHD Position */
+#define SCU_SFSPE_2_EHD_Msk (0x03UL << SCU_SFSPE_2_EHD_Pos) /*!< SCU SFSPE_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_3 ------------------------------------------
+#define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */
+#define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */
+#define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */
+#define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */
+#define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */
+#define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */
+#define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */
+#define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */
+#define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */
+#define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */
+#define SCU_SFSPE_3_EHD_Pos 8 /*!< SCU SFSPE_3: EHD Position */
+#define SCU_SFSPE_3_EHD_Msk (0x03UL << SCU_SFSPE_3_EHD_Pos) /*!< SCU SFSPE_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_4 ------------------------------------------
+#define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */
+#define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */
+#define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */
+#define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */
+#define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */
+#define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */
+#define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */
+#define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */
+#define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */
+#define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */
+#define SCU_SFSPE_4_EHD_Pos 8 /*!< SCU SFSPE_4: EHD Position */
+#define SCU_SFSPE_4_EHD_Msk (0x03UL << SCU_SFSPE_4_EHD_Pos) /*!< SCU SFSPE_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_5 ------------------------------------------
+#define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */
+#define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */
+#define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */
+#define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */
+#define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */
+#define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */
+#define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */
+#define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */
+#define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */
+#define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */
+#define SCU_SFSPE_5_EHD_Pos 8 /*!< SCU SFSPE_5: EHD Position */
+#define SCU_SFSPE_5_EHD_Msk (0x03UL << SCU_SFSPE_5_EHD_Pos) /*!< SCU SFSPE_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_6 ------------------------------------------
+#define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */
+#define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */
+#define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */
+#define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */
+#define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */
+#define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */
+#define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */
+#define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */
+#define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */
+#define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */
+#define SCU_SFSPE_6_EHD_Pos 8 /*!< SCU SFSPE_6: EHD Position */
+#define SCU_SFSPE_6_EHD_Msk (0x03UL << SCU_SFSPE_6_EHD_Pos) /*!< SCU SFSPE_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_7 ------------------------------------------
+#define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */
+#define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */
+#define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */
+#define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */
+#define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */
+#define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */
+#define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */
+#define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */
+#define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */
+#define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */
+#define SCU_SFSPE_7_EHD_Pos 8 /*!< SCU SFSPE_7: EHD Position */
+#define SCU_SFSPE_7_EHD_Msk (0x03UL << SCU_SFSPE_7_EHD_Pos) /*!< SCU SFSPE_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_8 ------------------------------------------
+#define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */
+#define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */
+#define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */
+#define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */
+#define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */
+#define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */
+#define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */
+#define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */
+#define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */
+#define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */
+#define SCU_SFSPE_8_EHD_Pos 8 /*!< SCU SFSPE_8: EHD Position */
+#define SCU_SFSPE_8_EHD_Msk (0x03UL << SCU_SFSPE_8_EHD_Pos) /*!< SCU SFSPE_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_9 ------------------------------------------
+#define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */
+#define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */
+#define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */
+#define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */
+#define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */
+#define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */
+#define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */
+#define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */
+#define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */
+#define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */
+#define SCU_SFSPE_9_EHD_Pos 8 /*!< SCU SFSPE_9: EHD Position */
+#define SCU_SFSPE_9_EHD_Msk (0x03UL << SCU_SFSPE_9_EHD_Pos) /*!< SCU SFSPE_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_10 ------------------------------------------
+#define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */
+#define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */
+#define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */
+#define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */
+#define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */
+#define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */
+#define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */
+#define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */
+#define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */
+#define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */
+#define SCU_SFSPE_10_EHD_Pos 8 /*!< SCU SFSPE_10: EHD Position */
+#define SCU_SFSPE_10_EHD_Msk (0x03UL << SCU_SFSPE_10_EHD_Pos) /*!< SCU SFSPE_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_11 ------------------------------------------
+#define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */
+#define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */
+#define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */
+#define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */
+#define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */
+#define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */
+#define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */
+#define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */
+#define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */
+#define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */
+#define SCU_SFSPE_11_EHD_Pos 8 /*!< SCU SFSPE_11: EHD Position */
+#define SCU_SFSPE_11_EHD_Msk (0x03UL << SCU_SFSPE_11_EHD_Pos) /*!< SCU SFSPE_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_12 ------------------------------------------
+#define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */
+#define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */
+#define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */
+#define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */
+#define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */
+#define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */
+#define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */
+#define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */
+#define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */
+#define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */
+#define SCU_SFSPE_12_EHD_Pos 8 /*!< SCU SFSPE_12: EHD Position */
+#define SCU_SFSPE_12_EHD_Msk (0x03UL << SCU_SFSPE_12_EHD_Pos) /*!< SCU SFSPE_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_13 ------------------------------------------
+#define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */
+#define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */
+#define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */
+#define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */
+#define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */
+#define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */
+#define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */
+#define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */
+#define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */
+#define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */
+#define SCU_SFSPE_13_EHD_Pos 8 /*!< SCU SFSPE_13: EHD Position */
+#define SCU_SFSPE_13_EHD_Msk (0x03UL << SCU_SFSPE_13_EHD_Pos) /*!< SCU SFSPE_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_14 ------------------------------------------
+#define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */
+#define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */
+#define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */
+#define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */
+#define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */
+#define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */
+#define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */
+#define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */
+#define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */
+#define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */
+#define SCU_SFSPE_14_EHD_Pos 8 /*!< SCU SFSPE_14: EHD Position */
+#define SCU_SFSPE_14_EHD_Msk (0x03UL << SCU_SFSPE_14_EHD_Pos) /*!< SCU SFSPE_14: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_15 ------------------------------------------
+#define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */
+#define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */
+#define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */
+#define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */
+#define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */
+#define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */
+#define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */
+#define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */
+#define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */
+#define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */
+#define SCU_SFSPE_15_EHD_Pos 8 /*!< SCU SFSPE_15: EHD Position */
+#define SCU_SFSPE_15_EHD_Msk (0x03UL << SCU_SFSPE_15_EHD_Pos) /*!< SCU SFSPE_15: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_0 ------------------------------------------
+#define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */
+#define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */
+#define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */
+#define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */
+#define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */
+#define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */
+#define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */
+#define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */
+#define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */
+#define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */
+#define SCU_SFSPF_0_EHD_Pos 8 /*!< SCU SFSPF_0: EHD Position */
+#define SCU_SFSPF_0_EHD_Msk (0x03UL << SCU_SFSPF_0_EHD_Pos) /*!< SCU SFSPF_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_1 ------------------------------------------
+#define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */
+#define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */
+#define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */
+#define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */
+#define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */
+#define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */
+#define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */
+#define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */
+#define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */
+#define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */
+#define SCU_SFSPF_1_EHD_Pos 8 /*!< SCU SFSPF_1: EHD Position */
+#define SCU_SFSPF_1_EHD_Msk (0x03UL << SCU_SFSPF_1_EHD_Pos) /*!< SCU SFSPF_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_2 ------------------------------------------
+#define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */
+#define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */
+#define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */
+#define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */
+#define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */
+#define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */
+#define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */
+#define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */
+#define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */
+#define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */
+#define SCU_SFSPF_2_EHD_Pos 8 /*!< SCU SFSPF_2: EHD Position */
+#define SCU_SFSPF_2_EHD_Msk (0x03UL << SCU_SFSPF_2_EHD_Pos) /*!< SCU SFSPF_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_3 ------------------------------------------
+#define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */
+#define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */
+#define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */
+#define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */
+#define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */
+#define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */
+#define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */
+#define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */
+#define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */
+#define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */
+#define SCU_SFSPF_3_EHD_Pos 8 /*!< SCU SFSPF_3: EHD Position */
+#define SCU_SFSPF_3_EHD_Msk (0x03UL << SCU_SFSPF_3_EHD_Pos) /*!< SCU SFSPF_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_4 ------------------------------------------
+#define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */
+#define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */
+#define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */
+#define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */
+#define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */
+#define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */
+#define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */
+#define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */
+#define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */
+#define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */
+#define SCU_SFSPF_4_EHD_Pos 8 /*!< SCU SFSPF_4: EHD Position */
+#define SCU_SFSPF_4_EHD_Msk (0x03UL << SCU_SFSPF_4_EHD_Pos) /*!< SCU SFSPF_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_5 ------------------------------------------
+#define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */
+#define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */
+#define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */
+#define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */
+#define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */
+#define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */
+#define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */
+#define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */
+#define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */
+#define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */
+#define SCU_SFSPF_5_EHD_Pos 8 /*!< SCU SFSPF_5: EHD Position */
+#define SCU_SFSPF_5_EHD_Msk (0x03UL << SCU_SFSPF_5_EHD_Pos) /*!< SCU SFSPF_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_6 ------------------------------------------
+#define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */
+#define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */
+#define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */
+#define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */
+#define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */
+#define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */
+#define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */
+#define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */
+#define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */
+#define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */
+#define SCU_SFSPF_6_EHD_Pos 8 /*!< SCU SFSPF_6: EHD Position */
+#define SCU_SFSPF_6_EHD_Msk (0x03UL << SCU_SFSPF_6_EHD_Pos) /*!< SCU SFSPF_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_7 ------------------------------------------
+#define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */
+#define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */
+#define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */
+#define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */
+#define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */
+#define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */
+#define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */
+#define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */
+#define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */
+#define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */
+#define SCU_SFSPF_7_EHD_Pos 8 /*!< SCU SFSPF_7: EHD Position */
+#define SCU_SFSPF_7_EHD_Msk (0x03UL << SCU_SFSPF_7_EHD_Pos) /*!< SCU SFSPF_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_8 ------------------------------------------
+#define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */
+#define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */
+#define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */
+#define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */
+#define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */
+#define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */
+#define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */
+#define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */
+#define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */
+#define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */
+#define SCU_SFSPF_8_EHD_Pos 8 /*!< SCU SFSPF_8: EHD Position */
+#define SCU_SFSPF_8_EHD_Msk (0x03UL << SCU_SFSPF_8_EHD_Pos) /*!< SCU SFSPF_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_9 ------------------------------------------
+#define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */
+#define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */
+#define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */
+#define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */
+#define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */
+#define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */
+#define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */
+#define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */
+#define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */
+#define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */
+#define SCU_SFSPF_9_EHD_Pos 8 /*!< SCU SFSPF_9: EHD Position */
+#define SCU_SFSPF_9_EHD_Msk (0x03UL << SCU_SFSPF_9_EHD_Pos) /*!< SCU SFSPF_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPF_10 ------------------------------------------
+#define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */
+#define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */
+#define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */
+#define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */
+#define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */
+#define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */
+#define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */
+#define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */
+#define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */
+#define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */
+#define SCU_SFSPF_10_EHD_Pos 8 /*!< SCU SFSPF_10: EHD Position */
+#define SCU_SFSPF_10_EHD_Msk (0x03UL << SCU_SFSPF_10_EHD_Pos) /*!< SCU SFSPF_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPF_11 ------------------------------------------
+#define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */
+#define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */
+#define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */
+#define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */
+#define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */
+#define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */
+#define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */
+#define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */
+#define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */
+#define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */
+#define SCU_SFSPF_11_EHD_Pos 8 /*!< SCU SFSPF_11: EHD Position */
+#define SCU_SFSPF_11_EHD_Msk (0x03UL << SCU_SFSPF_11_EHD_Pos) /*!< SCU SFSPF_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_0 ------------------------------------------
+#define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */
+#define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */
+#define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */
+#define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */
+#define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */
+#define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */
+#define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */
+#define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */
+#define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */
+#define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */
+#define SCU_SFSCLK_0_EHD_Pos 8 /*!< SCU SFSCLK_0: EHD Position */
+#define SCU_SFSCLK_0_EHD_Msk (0x03UL << SCU_SFSCLK_0_EHD_Pos) /*!< SCU SFSCLK_0: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_1 ------------------------------------------
+#define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */
+#define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */
+#define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */
+#define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */
+#define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */
+#define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */
+#define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */
+#define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */
+#define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */
+#define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */
+#define SCU_SFSCLK_1_EHD_Pos 8 /*!< SCU SFSCLK_1: EHD Position */
+#define SCU_SFSCLK_1_EHD_Msk (0x03UL << SCU_SFSCLK_1_EHD_Pos) /*!< SCU SFSCLK_1: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_2 ------------------------------------------
+#define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */
+#define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */
+#define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */
+#define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */
+#define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */
+#define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */
+#define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */
+#define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */
+#define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */
+#define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */
+#define SCU_SFSCLK_2_EHD_Pos 8 /*!< SCU SFSCLK_2: EHD Position */
+#define SCU_SFSCLK_2_EHD_Msk (0x03UL << SCU_SFSCLK_2_EHD_Pos) /*!< SCU SFSCLK_2: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_3 ------------------------------------------
+#define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */
+#define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */
+#define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */
+#define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */
+#define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */
+#define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */
+#define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */
+#define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */
+#define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */
+#define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */
+#define SCU_SFSCLK_3_EHD_Pos 8 /*!< SCU SFSCLK_3: EHD Position */
+#define SCU_SFSCLK_3_EHD_Msk (0x03UL << SCU_SFSCLK_3_EHD_Pos) /*!< SCU SFSCLK_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSUSB -------------------------------------------
+#define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */
+#define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */
+#define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */
+#define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */
+
+// --------------------------------------- SCU_SFSI2C0 ------------------------------------------
+#define SCU_SFSI2C0_SDA_EHS_Pos 0 /*!< SCU SFSI2C0: SDA_EHS Position */
+#define SCU_SFSI2C0_SDA_EHS_Msk (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos) /*!< SCU SFSI2C0: SDA_EHS Mask */
+#define SCU_SFSI2C0_SCL_EHS_Pos 1 /*!< SCU SFSI2C0: SCL_EHS Position */
+#define SCU_SFSI2C0_SCL_EHS_Msk (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos) /*!< SCU SFSI2C0: SCL_EHS Mask */
+#define SCU_SFSI2C0_SCL_ECS_Pos 2 /*!< SCU SFSI2C0: SCL_ECS Position */
+#define SCU_SFSI2C0_SCL_ECS_Msk (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos) /*!< SCU SFSI2C0: SCL_ECS Mask */
+
+// --------------------------------------- SCU_ENAIO0 -------------------------------------------
+#define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */
+#define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */
+#define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */
+#define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */
+#define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */
+#define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */
+#define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */
+#define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */
+#define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */
+#define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */
+#define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */
+#define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */
+#define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */
+#define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */
+
+// --------------------------------------- SCU_ENAIO1 -------------------------------------------
+#define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */
+#define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */
+#define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */
+#define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */
+#define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */
+#define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */
+#define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */
+#define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */
+#define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */
+#define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */
+#define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */
+#define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */
+#define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */
+#define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */
+#define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */
+#define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */
+
+// --------------------------------------- SCU_ENAIO2 -------------------------------------------
+#define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */
+#define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */
+#define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */
+#define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */
+
+// ------------------------------------- SCU_EMCDELAYCLK ----------------------------------------
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos 4 /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos 8 /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos 12 /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos 16 /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos 20 /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos 24 /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos 28 /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask */
+
+// -------------------------------------- SCU_PINTSEL0 ------------------------------------------
+#define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */
+#define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */
+#define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */
+#define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */
+#define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */
+#define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */
+#define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */
+#define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */
+#define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */
+#define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */
+#define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */
+#define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */
+#define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */
+#define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */
+#define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */
+#define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */
+
+// -------------------------------------- SCU_PINTSEL1 ------------------------------------------
+#define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */
+#define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */
+#define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */
+#define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */
+#define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */
+#define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */
+#define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */
+#define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */
+#define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */
+#define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */
+#define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */
+#define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */
+#define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */
+#define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */
+#define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */
+#define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------ GPIO_PIN_INT_ISEL ---------------------------------------
+#define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */
+#define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */
+#define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */
+#define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */
+#define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */
+#define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */
+#define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */
+#define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */
+#define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_IENR ---------------------------------------
+#define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */
+#define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */
+#define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */
+#define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */
+#define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */
+#define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */
+#define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */
+#define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */
+#define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */
+#define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */
+#define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */
+#define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */
+#define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */
+#define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */
+#define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */
+#define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_SIENR ---------------------------------------
+#define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_CIENR ---------------------------------------
+#define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */
+#define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */
+#define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */
+#define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */
+#define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */
+#define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */
+#define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */
+#define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */
+#define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_IENF ---------------------------------------
+#define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */
+#define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */
+#define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */
+#define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */
+#define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */
+#define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */
+#define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */
+#define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */
+#define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */
+#define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */
+#define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */
+#define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */
+#define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */
+#define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */
+#define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */
+#define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_SIENF ---------------------------------------
+#define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_CIENF ---------------------------------------
+#define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */
+#define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */
+#define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */
+#define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */
+#define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */
+#define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */
+#define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */
+#define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */
+#define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_RISE ---------------------------------------
+#define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */
+#define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */
+#define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */
+#define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */
+#define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */
+#define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */
+#define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */
+#define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */
+#define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */
+#define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */
+#define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */
+#define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */
+#define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */
+#define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */
+#define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */
+#define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_FALL ---------------------------------------
+#define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */
+#define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */
+#define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */
+#define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */
+#define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */
+#define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */
+#define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */
+#define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */
+#define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */
+#define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */
+#define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */
+#define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */
+#define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */
+#define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */
+#define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */
+#define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_IST ----------------------------------------
+#define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */
+#define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */
+#define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */
+#define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */
+#define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */
+#define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */
+#define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */
+#define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */
+#define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */
+#define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */
+#define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */
+#define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */
+#define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */
+#define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */
+#define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */
+#define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INTn Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------- GPIO_GROUP_INTn_CTRL --------------------------------------
+#define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */
+#define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */
+#define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */
+#define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL0 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL1 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL2 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL3 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL4 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL5 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL6 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL7 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA0 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA1 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA2 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA3 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA4 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA5 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA6 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA7 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------- GPIO_GROUP_INT1_CTRL --------------------------------------
+#define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */
+#define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */
+#define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */
+#define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL0 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL1 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL2 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL3 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL4 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL5 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL6 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL7 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA0 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GRO