| /** ################################################################### | |
| ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. | |
| ** Filename : IO_Map.C | |
| ** Project : RTOSDemo | |
| ** Processor : MC9S12DP256BCPV | |
| ** Beantype : IO_Map | |
| ** Version : Driver 01.01 | |
| ** Compiler : Metrowerks HC12 C Compiler | |
| ** Date/Time : 13/06/2005, 20:14 | |
| ** Abstract : | |
| ** This bean "IO_Map" implements an IO devices mapping. | |
| ** Settings : | |
| ** | |
| ** Contents : | |
| ** No public methods | |
| ** | |
| ** (c) Copyright UNIS, spol. s r.o. 1997-2002 | |
| ** UNIS, spol. s r.o. | |
| ** Jundrovska 33 | |
| ** 624 00 Brno | |
| ** Czech Republic | |
| ** http : www.processorexpert.com | |
| ** mail : info@processorexpert.com | |
| ** ###################################################################*/ | |
| /* Based on CPU DB MC9S12DP256_112, version 2.87.278 */ | |
| #include "PE_types.h" | |
| #include "IO_Map.h" | |
| volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ | |
| volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */ | |
| volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */ | |
| volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */ | |
| volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */ | |
| volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */ | |
| volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */ | |
| volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ | |
| volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ | |
| volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ | |
| volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ | |
| volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ | |
| volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ | |
| volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ | |
| volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ | |
| volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ | |
| volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ | |
| volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ | |
| volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */ | |
| volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */ | |
| volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */ | |
| volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */ | |
| volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */ | |
| volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */ | |
| volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */ | |
| volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */ | |
| volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */ | |
| volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */ | |
| volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */ | |
| volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */ | |
| volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */ | |
| volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */ | |
| volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */ | |
| volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */ | |
| volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */ | |
| volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */ | |
| volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */ | |
| volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */ | |
| volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */ | |
| volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */ | |
| volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */ | |
| volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */ | |
| volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */ | |
| volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */ | |
| volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */ | |
| volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */ | |
| volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */ | |
| volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */ | |
| volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */ | |
| volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */ | |
| volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */ | |
| volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */ | |
| volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */ | |
| volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */ | |
| volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */ | |
| volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */ | |
| volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */ | |
| volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */ | |
| volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */ | |
| volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */ | |
| volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */ | |
| volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */ | |
| volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */ | |
| volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */ | |
| volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */ | |
| volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */ | |
| volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */ | |
| volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */ | |
| volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */ | |
| volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */ | |
| volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */ | |
| volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */ | |
| volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */ | |
| volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */ | |
| volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */ | |
| volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */ | |
| volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */ | |
| volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */ | |
| volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */ | |
| volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */ | |
| volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */ | |
| volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */ | |
| volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */ | |
| volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */ | |
| volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */ | |
| volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */ | |
| volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */ | |
| volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */ | |
| volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */ | |
| volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */ | |
| volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */ | |
| volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */ | |
| volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */ | |
| volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */ | |
| volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */ | |
| volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */ | |
| volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */ | |
| volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */ | |
| volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */ | |
| volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */ | |
| volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */ | |
| volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */ | |
| volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */ | |
| volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */ | |
| volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */ | |
| volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */ | |
| volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */ | |
| volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */ | |
| volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */ | |
| volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */ | |
| volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */ | |
| volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */ | |
| volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */ | |
| volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */ | |
| volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */ | |
| volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */ | |
| volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */ | |
| volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */ | |
| volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */ | |
| volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */ | |
| volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */ | |
| volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */ | |
| volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */ | |
| volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */ | |
| volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */ | |
| volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */ | |
| volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */ | |
| volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */ | |
| volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */ | |
| volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */ | |
| volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */ | |
| volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */ | |
| volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */ | |
| volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */ | |
| volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */ | |
| volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */ | |
| volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */ | |
| volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */ | |
| volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */ | |
| volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */ | |
| volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */ | |
| volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */ | |
| volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */ | |
| volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */ | |
| volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */ | |
| volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */ | |
| volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */ | |
| volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */ | |
| volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */ | |
| volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */ | |
| volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */ | |
| volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */ | |
| volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */ | |
| volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */ | |
| volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */ | |
| volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */ | |
| volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */ | |
| volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */ | |
| volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */ | |
| volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */ | |
| volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */ | |
| volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */ | |
| volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */ | |
| volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */ | |
| volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */ | |
| volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */ | |
| volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */ | |
| volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */ | |
| volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */ | |
| volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */ | |
| volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */ | |
| volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */ | |
| volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */ | |
| volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */ | |
| volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */ | |
| volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */ | |
| volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */ | |
| volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */ | |
| volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */ | |
| volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */ | |
| volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */ | |
| volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */ | |
| volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */ | |
| volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */ | |
| volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */ | |
| volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */ | |
| volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */ | |
| volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */ | |
| volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */ | |
| volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */ | |
| volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */ | |
| volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */ | |
| volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */ | |
| volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */ | |
| volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */ | |
| volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */ | |
| volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */ | |
| volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */ | |
| volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */ | |
| volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */ | |
| volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */ | |
| volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */ | |
| volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */ | |
| volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */ | |
| volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */ | |
| volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */ | |
| volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */ | |
| volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */ | |
| volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */ | |
| volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */ | |
| volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */ | |
| volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */ | |
| volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */ | |
| volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */ | |
| volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */ | |
| volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */ | |
| volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */ | |
| volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */ | |
| volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */ | |
| volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */ | |
| volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */ | |
| volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */ | |
| volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */ | |
| volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */ | |
| volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */ | |
| volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */ | |
| volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */ | |
| volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */ | |
| volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */ | |
| volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */ | |
| volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */ | |
| volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */ | |
| volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */ | |
| volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */ | |
| volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */ | |
| volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */ | |
| volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */ | |
| volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */ | |
| volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */ | |
| volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */ | |
| volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */ | |
| volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */ | |
| volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */ | |
| volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */ | |
| volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */ | |
| volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */ | |
| volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */ | |
| volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */ | |
| volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */ | |
| volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */ | |
| volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */ | |
| volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */ | |
| volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */ | |
| volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */ | |
| volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */ | |
| volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */ | |
| volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */ | |
| volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */ | |
| volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */ | |
| volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */ | |
| volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */ | |
| volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */ | |
| volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */ | |
| volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */ | |
| volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */ | |
| volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */ | |
| volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */ | |
| volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */ | |
| volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */ | |
| volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */ | |
| volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */ | |
| volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */ | |
| volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */ | |
| volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */ | |
| volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */ | |
| volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */ | |
| volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */ | |
| volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */ | |
| volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */ | |
| volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */ | |
| volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */ | |
| volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */ | |
| volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */ | |
| volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */ | |
| volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */ | |
| volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */ | |
| volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */ | |
| volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */ | |
| volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */ | |
| volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */ | |
| volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */ | |
| volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */ | |
| volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */ | |
| volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */ | |
| volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */ | |
| volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */ | |
| volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */ | |
| volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */ | |
| volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */ | |
| volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */ | |
| volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */ | |
| volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */ | |
| volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */ | |
| volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ | |
| volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ | |
| volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ | |
| volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ | |
| volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ | |
| volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ | |
| volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ | |
| volatile DDRESTR _DDRE; /* Port E Data Direction Register */ | |
| volatile DDRHSTR _DDRH; /* Port H Data Direction Register */ | |
| volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ | |
| volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ | |
| volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ | |
| volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ | |
| volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ | |
| volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ | |
| volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */ | |
| volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */ | |
| volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */ | |
| volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */ | |
| volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */ | |
| volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */ | |
| volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */ | |
| volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */ | |
| volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ | |
| volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */ | |
| volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */ | |
| volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */ | |
| volatile EPROTSTR _EPROT; /* EEPROM Protection Register */ | |
| volatile ESTATSTR _ESTAT; /* EEPROM Status Register */ | |
| volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ | |
| volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ | |
| volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ | |
| volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */ | |
| volatile FPROTSTR _FPROT; /* Flash Protection Register */ | |
| volatile FSECSTR _FSEC; /* Flash Security Register */ | |
| volatile FSTATSTR _FSTAT; /* Flash Status Register */ | |
| volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ | |
| volatile IBADSTR _IBAD; /* IIC Address Register */ | |
| volatile IBCRSTR _IBCR; /* IIC Control Register */ | |
| volatile IBDRSTR _IBDR; /* IIC Data I/O Register */ | |
| volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */ | |
| volatile IBSRSTR _IBSR; /* IIC Status Register */ | |
| volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */ | |
| volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */ | |
| volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */ | |
| volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ | |
| volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ | |
| volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ | |
| volatile INTCRSTR _INTCR; /* Interrupt Control Register */ | |
| volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ | |
| volatile ITESTSTR _ITEST; /* Interrupt Test Register */ | |
| volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */ | |
| volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */ | |
| volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ | |
| volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ | |
| volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ | |
| volatile MODESTR _MODE; /* Mode Register */ | |
| volatile MODRRSTR _MODRR; /* Module Routing Register */ | |
| volatile MTST0STR _MTST0; /* MTST0 */ | |
| volatile MTST1STR _MTST1; /* MTST1 */ | |
| volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ | |
| volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ | |
| volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ | |
| volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ | |
| volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ | |
| volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ | |
| volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */ | |
| volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */ | |
| volatile PEARSTR _PEAR; /* Port E Assignment Register */ | |
| volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */ | |
| volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ | |
| volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ | |
| volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ | |
| volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ | |
| volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ | |
| volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */ | |
| volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ | |
| volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ | |
| volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */ | |
| volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ | |
| volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ | |
| volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ | |
| volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ | |
| volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */ | |
| volatile PORTESTR _PORTE; /* Port E Register */ | |
| volatile PORTKSTR _PORTK; /* Port K Data Register */ | |
| volatile PPAGESTR _PPAGE; /* Page Index Register */ | |
| volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */ | |
| volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ | |
| volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ | |
| volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ | |
| volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ | |
| volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ | |
| volatile PTHSTR _PTH; /* Port H I/O Register */ | |
| volatile PTIHSTR _PTIH; /* Port H Input Register */ | |
| volatile PTIJSTR _PTIJ; /* Port J Input Register */ | |
| volatile PTIMSTR _PTIM; /* Port M Input */ | |
| volatile PTIPSTR _PTIP; /* Port P Input */ | |
| volatile PTISSTR _PTIS; /* Port S Input */ | |
| volatile PTITSTR _PTIT; /* Port T Input */ | |
| volatile PTJSTR _PTJ; /* Port J I/O Register */ | |
| volatile PTMSTR _PTM; /* Port M I/O Register */ | |
| volatile PTPSTR _PTP; /* Port P I/O Register */ | |
| volatile PTSSTR _PTS; /* Port S I/O Register */ | |
| volatile PTTSTR _PTT; /* Port T I/O Register */ | |
| volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ | |
| volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ | |
| volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ | |
| volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ | |
| volatile PWMESTR _PWME; /* PWM Enable Register */ | |
| volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ | |
| volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ | |
| volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ | |
| volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ | |
| volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ | |
| volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */ | |
| volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ | |
| volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ | |
| volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ | |
| volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ | |
| volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ | |
| volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ | |
| volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ | |
| volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ | |
| volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */ | |
| volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */ | |
| volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */ | |
| volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */ | |
| volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */ | |
| volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */ | |
| volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */ | |
| volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */ | |
| volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */ | |
| volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */ | |
| volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */ | |
| volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */ | |
| volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */ | |
| volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */ | |
| volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */ | |
| volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */ | |
| volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */ | |
| volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */ | |
| volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */ | |
| volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */ | |
| volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */ | |
| volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */ | |
| volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */ | |
| volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */ | |
| volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */ | |
| volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */ | |
| volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */ | |
| volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ | |
| volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */ | |
| volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */ | |
| volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ | |
| volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ | |
| volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ | |
| volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ | |
| volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ | |
| volatile TIMTSTSTR _TIMTST; /* Timer Test Register */ | |
| volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ | |
| volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ | |
| volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ | |
| volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ | |
| volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ | |
| volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ | |
| volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */ | |
| volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */ | |
| volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */ | |
| volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */ | |
| volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */ | |
| volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */ | |
| volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */ | |
| volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */ | |
| volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */ | |
| volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */ | |
| volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */ | |
| volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */ | |
| volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */ | |
| volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */ | |
| volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */ | |
| volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */ | |
| volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */ | |
| volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */ | |
| volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */ | |
| volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */ | |
| volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ | |
| volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */ | |
| volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */ | |
| volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */ | |
| volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */ | |
| volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */ | |
| volatile PORTABSTR _PORTAB; /* Port AB Register */ | |
| volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ | |
| volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ | |
| volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ | |
| volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */ | |
| volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ | |
| volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ | |
| volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ | |
| volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */ | |
| volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ | |
| volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ | |
| volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ | |
| volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */ | |
| volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */ | |
| volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */ | |
| volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ | |
| volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */ | |
| volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ | |
| volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */ | |
| volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ | |
| volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */ | |
| volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ | |
| volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */ | |
| volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ | |
| volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ | |
| volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ | |
| volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ | |
| volatile TCNTSTR _TCNT; /* Timer Count Register */ | |
| /* | |
| ** ################################################################### | |
| ** | |
| ** This file was created by UNIS Processor Expert 03.33 for | |
| ** the Motorola HCS12 series of microcontrollers. | |
| ** | |
| ** ################################################################### | |
| */ |