| #################################################################
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| # Makefile generated by Xilinx Platform Studio
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| # Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.xmp
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| #
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| # WARNING : This file will be re-generated every time a command
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| # to run a make target is invoked. So, any changes made to this
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| # file manually, will be lost when make is invoked next.
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| #################################################################
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|
|
| SHELL = CMD
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|
|
| XILINX_EDK_DIR = C:/devtools/Xilinx/13.1/ISE_DS/EDK
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|
|
| SYSTEM = system
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|
|
| MHSFILE = system.mhs
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|
|
| FPGA_ARCH = spartan6
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|
|
| DEVICE = xc6slx45tfgg484-3
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|
|
| LANGUAGE = vhdl
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| GLOBAL_SEARCHPATHOPT =
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| PROJECT_SEARCHPATHOPT =
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|
|
| SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT)
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|
|
| SUBMODULE_OPT =
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|
|
| PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
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|
|
| OBSERVE_PAR_OPTIONS = -error yes
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|
|
| MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
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| MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf
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| PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
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| PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
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| BOOTLOOP_DIR = bootloops
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|
|
| MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf
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|
|
| BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP)
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| BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP)
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|
|
| BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP)
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| BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP)
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|
|
| SIM_CMD = isim_system
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|
|
| BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl
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|
|
| STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl
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|
|
| TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl
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|
|
| DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
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|
|
| MIX_LANG_SIM_OPT = -mixed yes
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|
|
| SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s isim
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|
|
|
|
| CORE_STATE_DEVELOPMENT_FILES =
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|
|
| WRAPPER_NGC_FILES = implementation/axi4_0_wrapper.ngc \ |
| implementation/axi4lite_0_wrapper.ngc \ |
| implementation/microblaze_0_wrapper.ngc \ |
| implementation/microblaze_0_ilmb_wrapper.ngc \ |
| implementation/microblaze_0_dlmb_wrapper.ngc \ |
| implementation/microblaze_0_i_bram_ctrl_wrapper.ngc \ |
| implementation/microblaze_0_d_bram_ctrl_wrapper.ngc \ |
| implementation/microblaze_0_bram_block_wrapper.ngc \ |
| implementation/proc_sys_reset_0_wrapper.ngc \ |
| implementation/clock_generator_0_wrapper.ngc \ |
| implementation/debug_module_wrapper.ngc \ |
| implementation/rs232_uart_1_wrapper.ngc \ |
| implementation/leds_4bits_wrapper.ngc \ |
| implementation/push_buttons_4bits_wrapper.ngc \ |
| implementation/mcb_ddr3_wrapper.ngc \ |
| implementation/ethernet_lite_wrapper.ngc \ |
| implementation/axi_timer_0_wrapper.ngc \ |
| implementation/microblaze_0_intc_wrapper.ngc
|
|
|
| POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
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|
|
| SYSTEM_BIT = implementation/$(SYSTEM).bit
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|
|
| DOWNLOAD_BIT = implementation/download.bit
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|
|
| SYSTEM_ACE = implementation/$(SYSTEM).ace
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|
|
| UCF_FILE = data/system.ucf
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|
|
| BMM_FILE = implementation/$(SYSTEM).bmm
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|
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| BITGEN_UT_FILE = etc/bitgen.ut
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|
|
| XFLOW_OPT_FILE = etc/fast_runtime.opt
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| XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
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|
|
| XPLORER_DEPENDENCY = __xps/xplorer.opt
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| XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
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|
|
| FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
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|
|
| SDK_EXPORT_DIR = SDK\SDK_Export\hw
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| SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
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| SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
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| SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm
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| SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)
|