| // ---------------------------------------------------------------------------- | |
| // ATMEL Microcontroller Software Support - ROUSSET - | |
| // ---------------------------------------------------------------------------- | |
| // Copyright (c) 2008, Atmel Corporation | |
| // | |
| // All rights reserved. | |
| // | |
| // Redistribution and use in source and binary forms, with or without | |
| // modification, are permitted provided that the following conditions are met: | |
| // | |
| // - Redistributions of source code must retain the above copyright notice, | |
| // this list of conditions and the disclaimer below. | |
| // | |
| // Atmel's name may not be used to endorse or promote products derived from | |
| // this software without specific prior written permission. | |
| // | |
| // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR | |
| // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
| // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE | |
| // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, | |
| // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
| // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
| // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | |
| // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| // ---------------------------------------------------------------------------- | |
| // File Name : AT91SAM3U4.h | |
| // Object : AT91SAM3U4 definitions | |
| // Generated : AT91 SW Application Group 03/09/2009 (11:49:34) | |
| // | |
| // CVS Reference : /AT91SAM3U4.pl/1.32/Mon Feb 9 14:20:58 2009// | |
| // CVS Reference : /SYS_SAM3U4.pl/1.4/Fri Oct 17 13:27:57 2008// | |
| // CVS Reference : /HMATRIX2_SAM3U4.pl/1.3/Mon Mar 2 10:12:07 2009// | |
| // CVS Reference : /PMC_SAM3U4.pl/1.7/Fri Oct 17 13:27:54 2008// | |
| // CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005// | |
| // CVS Reference : /EFC2_SAM3U4.pl/1.3/Mon Mar 2 10:12:06 2009// | |
| // CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004// | |
| // CVS Reference : /HSMC4_xxxx.pl/1.9/Fri Oct 17 13:27:56 2008// | |
| // CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005// | |
| // CVS Reference : /CORTEX_M3_NVIC.pl/1.7/Tue Jan 27 16:16:24 2009// | |
| // CVS Reference : /CORTEX_M3_MPU.pl/1.3/Fri Oct 17 13:27:48 2008// | |
| // CVS Reference : /CORTEX_M3.pl/1.1/Mon Sep 15 15:22:06 2008// | |
| // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// | |
| // CVS Reference : /DBGU_SAM3U4.pl/1.2/Fri Oct 17 13:27:49 2008// | |
| // CVS Reference : /PIO3_xxxx.pl/1.6/Mon Mar 9 10:43:37 2009// | |
| // CVS Reference : /RSTC_6098A.pl/1.4/Fri Oct 17 13:27:55 2008// | |
| // CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004// | |
| // CVS Reference : /SUPC_SAM3U4.pl/1.2/Thu Jun 5 15:27:27 2008// | |
| // CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// | |
| // CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// | |
| // CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// | |
| // CVS Reference : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008// | |
| // CVS Reference : /MCI_6101F.pl/1.3/Fri Jan 23 09:15:32 2009// | |
| // CVS Reference : /TWI_6061B.pl/1.3/Fri Oct 17 13:27:59 2008// | |
| // CVS Reference : /US_6089J.pl/1.3/Fri Oct 17 13:27:59 2008// | |
| // CVS Reference : /SSC_6078B.pl/1.3/Fri Oct 17 13:27:57 2008// | |
| // CVS Reference : /SPI2.pl/1.4/Mon Mar 9 08:56:28 2009// | |
| // CVS Reference : /PWM_6343B_V400.pl/1.3/Fri Oct 17 13:27:54 2008// | |
| // CVS Reference : /HDMA_SAM3U4.pl/1.3/Fri Oct 17 13:27:51 2008// | |
| // CVS Reference : /UDPHS_SAM9_7ept6dma4iso.pl/1.4/Tue Jun 24 13:05:14 2008// | |
| // CVS Reference : /ADC_SAM3UE.pl/1.4/Fri Feb 20 12:19:18 2009// | |
| // CVS Reference : /RTC_1245D.pl/1.3/Fri Sep 17 14:01:31 2004// | |
| // ---------------------------------------------------------------------------- | |
| #ifndef AT91SAM3U4_H | |
| #define AT91SAM3U4_H | |
| #ifndef __ASSEMBLY__ | |
| typedef volatile unsigned int AT91_REG;// Hardware register definition | |
| #define AT91_CAST(a) (a) | |
| #else | |
| #define AT91_CAST(a) | |
| #endif | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR System Peripherals | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_SYS { | |
| AT91_REG HSMC4_CFG; // Configuration Register | |
| AT91_REG HSMC4_CTRL; // Control Register | |
| AT91_REG HSMC4_SR; // Status Register | |
| AT91_REG HSMC4_IER; // Interrupt Enable Register | |
| AT91_REG HSMC4_IDR; // Interrupt Disable Register | |
| AT91_REG HSMC4_IMR; // Interrupt Mask Register | |
| AT91_REG HSMC4_ADDR; // Address Cycle Zero Register | |
| AT91_REG HSMC4_BANK; // Bank Register | |
| AT91_REG HSMC4_ECCCR; // ECC reset register | |
| AT91_REG HSMC4_ECCCMD; // ECC Page size register | |
| AT91_REG HSMC4_ECCSR1; // ECC Status register 1 | |
| AT91_REG HSMC4_ECCPR0; // ECC Parity register 0 | |
| AT91_REG HSMC4_ECCPR1; // ECC Parity register 1 | |
| AT91_REG HSMC4_ECCSR2; // ECC Status register 2 | |
| AT91_REG HSMC4_ECCPR2; // ECC Parity register 2 | |
| AT91_REG HSMC4_ECCPR3; // ECC Parity register 3 | |
| AT91_REG HSMC4_ECCPR4; // ECC Parity register 4 | |
| AT91_REG HSMC4_ECCPR5; // ECC Parity register 5 | |
| AT91_REG HSMC4_ECCPR6; // ECC Parity register 6 | |
| AT91_REG HSMC4_ECCPR7; // ECC Parity register 7 | |
| AT91_REG HSMC4_ECCPR8; // ECC Parity register 8 | |
| AT91_REG HSMC4_ECCPR9; // ECC Parity register 9 | |
| AT91_REG HSMC4_ECCPR10; // ECC Parity register 10 | |
| AT91_REG HSMC4_ECCPR11; // ECC Parity register 11 | |
| AT91_REG HSMC4_ECCPR12; // ECC Parity register 12 | |
| AT91_REG HSMC4_ECCPR13; // ECC Parity register 13 | |
| AT91_REG HSMC4_ECCPR14; // ECC Parity register 14 | |
| AT91_REG HSMC4_Eccpr15; // ECC Parity register 15 | |
| AT91_REG Reserved0[40]; // | |
| AT91_REG HSMC4_OCMS; // OCMS MODE register | |
| AT91_REG HSMC4_KEY1; // KEY1 Register | |
| AT91_REG HSMC4_KEY2; // KEY2 Register | |
| AT91_REG Reserved1[50]; // | |
| AT91_REG HSMC4_WPCR; // Write Protection Control register | |
| AT91_REG HSMC4_WPSR; // Write Protection Status Register | |
| AT91_REG HSMC4_ADDRSIZE; // Write Protection Status Register | |
| AT91_REG HSMC4_IPNAME1; // Write Protection Status Register | |
| AT91_REG HSMC4_IPNAME2; // Write Protection Status Register | |
| AT91_REG HSMC4_FEATURES; // Write Protection Status Register | |
| AT91_REG HSMC4_VER; // HSMC4 Version Register | |
| AT91_REG HMATRIX_MCFG0; // Master Configuration Register 0 : ARM I and D | |
| AT91_REG HMATRIX_MCFG1; // Master Configuration Register 1 : ARM S | |
| AT91_REG HMATRIX_MCFG2; // Master Configuration Register 2 | |
| AT91_REG HMATRIX_MCFG3; // Master Configuration Register 3 | |
| AT91_REG HMATRIX_MCFG4; // Master Configuration Register 4 | |
| AT91_REG HMATRIX_MCFG5; // Master Configuration Register 5 | |
| AT91_REG HMATRIX_MCFG6; // Master Configuration Register 6 | |
| AT91_REG HMATRIX_MCFG7; // Master Configuration Register 7 | |
| AT91_REG Reserved2[8]; // | |
| AT91_REG HMATRIX_SCFG0; // Slave Configuration Register 0 | |
| AT91_REG HMATRIX_SCFG1; // Slave Configuration Register 1 | |
| AT91_REG HMATRIX_SCFG2; // Slave Configuration Register 2 | |
| AT91_REG HMATRIX_SCFG3; // Slave Configuration Register 3 | |
| AT91_REG HMATRIX_SCFG4; // Slave Configuration Register 4 | |
| AT91_REG HMATRIX_SCFG5; // Slave Configuration Register 5 | |
| AT91_REG HMATRIX_SCFG6; // Slave Configuration Register 6 | |
| AT91_REG HMATRIX_SCFG7; // Slave Configuration Register 5 | |
| AT91_REG HMATRIX_SCFG8; // Slave Configuration Register 8 | |
| AT91_REG Reserved3[43]; // | |
| AT91_REG HMATRIX_SFR0 ; // Special Function Register 0 | |
| AT91_REG HMATRIX_SFR1 ; // Special Function Register 1 | |
| AT91_REG HMATRIX_SFR2 ; // Special Function Register 2 | |
| AT91_REG HMATRIX_SFR3 ; // Special Function Register 3 | |
| AT91_REG HMATRIX_SFR4 ; // Special Function Register 4 | |
| AT91_REG HMATRIX_SFR5 ; // Special Function Register 5 | |
| AT91_REG HMATRIX_SFR6 ; // Special Function Register 6 | |
| AT91_REG HMATRIX_SFR7 ; // Special Function Register 7 | |
| AT91_REG HMATRIX_SFR8 ; // Special Function Register 8 | |
| AT91_REG HMATRIX_SFR9 ; // Special Function Register 9 | |
| AT91_REG HMATRIX_SFR10; // Special Function Register 10 | |
| AT91_REG HMATRIX_SFR11; // Special Function Register 11 | |
| AT91_REG HMATRIX_SFR12; // Special Function Register 12 | |
| AT91_REG HMATRIX_SFR13; // Special Function Register 13 | |
| AT91_REG HMATRIX_SFR14; // Special Function Register 14 | |
| AT91_REG HMATRIX_SFR15; // Special Function Register 15 | |
| AT91_REG Reserved4[39]; // | |
| AT91_REG HMATRIX_ADDRSIZE; // HMATRIX2 ADDRSIZE REGISTER | |
| AT91_REG HMATRIX_IPNAME1; // HMATRIX2 IPNAME1 REGISTER | |
| AT91_REG HMATRIX_IPNAME2; // HMATRIX2 IPNAME2 REGISTER | |
| AT91_REG HMATRIX_FEATURES; // HMATRIX2 FEATURES REGISTER | |
| AT91_REG HMATRIX_VER; // HMATRIX2 VERSION REGISTER | |
| AT91_REG PMC_SCER; // System Clock Enable Register | |
| AT91_REG PMC_SCDR; // System Clock Disable Register | |
| AT91_REG PMC_SCSR; // System Clock Status Register | |
| AT91_REG Reserved5[1]; // | |
| AT91_REG PMC_PCER; // Peripheral Clock Enable Register | |
| AT91_REG PMC_PCDR; // Peripheral Clock Disable Register | |
| AT91_REG PMC_PCSR; // Peripheral Clock Status Register | |
| AT91_REG PMC_UCKR; // UTMI Clock Configuration Register | |
| AT91_REG PMC_MOR; // Main Oscillator Register | |
| AT91_REG PMC_MCFR; // Main Clock Frequency Register | |
| AT91_REG PMC_PLLAR; // PLL Register | |
| AT91_REG Reserved6[1]; // | |
| AT91_REG PMC_MCKR; // Master Clock Register | |
| AT91_REG Reserved7[3]; // | |
| AT91_REG PMC_PCKR[8]; // Programmable Clock Register | |
| AT91_REG PMC_IER; // Interrupt Enable Register | |
| AT91_REG PMC_IDR; // Interrupt Disable Register | |
| AT91_REG PMC_SR; // Status Register | |
| AT91_REG PMC_IMR; // Interrupt Mask Register | |
| AT91_REG PMC_FSMR; // Fast Startup Mode Register | |
| AT91_REG PMC_FSPR; // Fast Startup Polarity Register | |
| AT91_REG PMC_FOCR; // Fault Output Clear Register | |
| AT91_REG Reserved8[28]; // | |
| AT91_REG PMC_ADDRSIZE; // PMC ADDRSIZE REGISTER | |
| AT91_REG PMC_IPNAME1; // PMC IPNAME1 REGISTER | |
| AT91_REG PMC_IPNAME2; // PMC IPNAME2 REGISTER | |
| AT91_REG PMC_FEATURES; // PMC FEATURES REGISTER | |
| AT91_REG PMC_VER; // APMC VERSION REGISTER | |
| AT91_REG Reserved9[64]; // | |
| AT91_REG DBGU_CR; // Control Register | |
| AT91_REG DBGU_MR; // Mode Register | |
| AT91_REG DBGU_IER; // Interrupt Enable Register | |
| AT91_REG DBGU_IDR; // Interrupt Disable Register | |
| AT91_REG DBGU_IMR; // Interrupt Mask Register | |
| AT91_REG DBGU_CSR; // Channel Status Register | |
| AT91_REG DBGU_RHR; // Receiver Holding Register | |
| AT91_REG DBGU_THR; // Transmitter Holding Register | |
| AT91_REG DBGU_BRGR; // Baud Rate Generator Register | |
| AT91_REG Reserved10[9]; // | |
| AT91_REG DBGU_FNTR; // Force NTRST Register | |
| AT91_REG Reserved11[40]; // | |
| AT91_REG DBGU_ADDRSIZE; // DBGU ADDRSIZE REGISTER | |
| AT91_REG DBGU_IPNAME1; // DBGU IPNAME1 REGISTER | |
| AT91_REG DBGU_IPNAME2; // DBGU IPNAME2 REGISTER | |
| AT91_REG DBGU_FEATURES; // DBGU FEATURES REGISTER | |
| AT91_REG DBGU_VER; // DBGU VERSION REGISTER | |
| AT91_REG DBGU_RPR; // Receive Pointer Register | |
| AT91_REG DBGU_RCR; // Receive Counter Register | |
| AT91_REG DBGU_TPR; // Transmit Pointer Register | |
| AT91_REG DBGU_TCR; // Transmit Counter Register | |
| AT91_REG DBGU_RNPR; // Receive Next Pointer Register | |
| AT91_REG DBGU_RNCR; // Receive Next Counter Register | |
| AT91_REG DBGU_TNPR; // Transmit Next Pointer Register | |
| AT91_REG DBGU_TNCR; // Transmit Next Counter Register | |
| AT91_REG DBGU_PTCR; // PDC Transfer Control Register | |
| AT91_REG DBGU_PTSR; // PDC Transfer Status Register | |
| AT91_REG Reserved12[6]; // | |
| AT91_REG DBGU_CIDR; // Chip ID Register | |
| AT91_REG DBGU_EXID; // Chip ID Extension Register | |
| AT91_REG Reserved13[46]; // | |
| AT91_REG EFC0_FMR; // EFC Flash Mode Register | |
| AT91_REG EFC0_FCR; // EFC Flash Command Register | |
| AT91_REG EFC0_FSR; // EFC Flash Status Register | |
| AT91_REG EFC0_FRR; // EFC Flash Result Register | |
| AT91_REG Reserved14[1]; // | |
| AT91_REG EFC0_FVR; // EFC Flash Version Register | |
| AT91_REG Reserved15[122]; // | |
| AT91_REG EFC1_FMR; // EFC Flash Mode Register | |
| AT91_REG EFC1_FCR; // EFC Flash Command Register | |
| AT91_REG EFC1_FSR; // EFC Flash Status Register | |
| AT91_REG EFC1_FRR; // EFC Flash Result Register | |
| AT91_REG Reserved16[1]; // | |
| AT91_REG EFC1_FVR; // EFC Flash Version Register | |
| AT91_REG Reserved17[122]; // | |
| AT91_REG PIOA_PER; // PIO Enable Register | |
| AT91_REG PIOA_PDR; // PIO Disable Register | |
| AT91_REG PIOA_PSR; // PIO Status Register | |
| AT91_REG Reserved18[1]; // | |
| AT91_REG PIOA_OER; // Output Enable Register | |
| AT91_REG PIOA_ODR; // Output Disable Registerr | |
| AT91_REG PIOA_OSR; // Output Status Register | |
| AT91_REG Reserved19[1]; // | |
| AT91_REG PIOA_IFER; // Input Filter Enable Register | |
| AT91_REG PIOA_IFDR; // Input Filter Disable Register | |
| AT91_REG PIOA_IFSR; // Input Filter Status Register | |
| AT91_REG Reserved20[1]; // | |
| AT91_REG PIOA_SODR; // Set Output Data Register | |
| AT91_REG PIOA_CODR; // Clear Output Data Register | |
| AT91_REG PIOA_ODSR; // Output Data Status Register | |
| AT91_REG PIOA_PDSR; // Pin Data Status Register | |
| AT91_REG PIOA_IER; // Interrupt Enable Register | |
| AT91_REG PIOA_IDR; // Interrupt Disable Register | |
| AT91_REG PIOA_IMR; // Interrupt Mask Register | |
| AT91_REG PIOA_ISR; // Interrupt Status Register | |
| AT91_REG PIOA_MDER; // Multi-driver Enable Register | |
| AT91_REG PIOA_MDDR; // Multi-driver Disable Register | |
| AT91_REG PIOA_MDSR; // Multi-driver Status Register | |
| AT91_REG Reserved21[1]; // | |
| AT91_REG PIOA_PPUDR; // Pull-up Disable Register | |
| AT91_REG PIOA_PPUER; // Pull-up Enable Register | |
| AT91_REG PIOA_PPUSR; // Pull-up Status Register | |
| AT91_REG Reserved22[1]; // | |
| AT91_REG PIOA_ABSR; // Peripheral AB Select Register | |
| AT91_REG Reserved23[3]; // | |
| AT91_REG PIOA_SCIFSR; // System Clock Glitch Input Filter Select Register | |
| AT91_REG PIOA_DIFSR; // Debouncing Input Filter Select Register | |
| AT91_REG PIOA_IFDGSR; // Glitch or Debouncing Input Filter Clock Selection Status Register | |
| AT91_REG PIOA_SCDR; // Slow Clock Divider Debouncing Register | |
| AT91_REG Reserved24[4]; // | |
| AT91_REG PIOA_OWER; // Output Write Enable Register | |
| AT91_REG PIOA_OWDR; // Output Write Disable Register | |
| AT91_REG PIOA_OWSR; // Output Write Status Register | |
| AT91_REG Reserved25[1]; // | |
| AT91_REG PIOA_AIMER; // Additional Interrupt Modes Enable Register | |
| AT91_REG PIOA_AIMDR; // Additional Interrupt Modes Disables Register | |
| AT91_REG PIOA_AIMMR; // Additional Interrupt Modes Mask Register | |
| AT91_REG Reserved26[1]; // | |
| AT91_REG PIOA_ESR; // Edge Select Register | |
| AT91_REG PIOA_LSR; // Level Select Register | |
| AT91_REG PIOA_ELSR; // Edge/Level Status Register | |
| AT91_REG Reserved27[1]; // | |
| AT91_REG PIOA_FELLSR; // Falling Edge/Low Level Select Register | |
| AT91_REG PIOA_REHLSR; // Rising Edge/ High Level Select Register | |
| AT91_REG PIOA_FRLHSR; // Fall/Rise - Low/High Status Register | |
| AT91_REG Reserved28[1]; // | |
| AT91_REG PIOA_LOCKSR; // Lock Status Register | |
| AT91_REG Reserved29[6]; // | |
| AT91_REG PIOA_VER; // PIO VERSION REGISTER | |
| AT91_REG Reserved30[8]; // | |
| AT91_REG PIOA_KER; // Keypad Controller Enable Register | |
| AT91_REG PIOA_KRCR; // Keypad Controller Row Column Register | |
| AT91_REG PIOA_KDR; // Keypad Controller Debouncing Register | |
| AT91_REG Reserved31[1]; // | |
| AT91_REG PIOA_KIER; // Keypad Controller Interrupt Enable Register | |
| AT91_REG PIOA_KIDR; // Keypad Controller Interrupt Disable Register | |
| AT91_REG PIOA_KIMR; // Keypad Controller Interrupt Mask Register | |
| AT91_REG PIOA_KSR; // Keypad Controller Status Register | |
| AT91_REG PIOA_KKPR; // Keypad Controller Key Press Register | |
| AT91_REG PIOA_KKRR; // Keypad Controller Key Release Register | |
| AT91_REG Reserved32[46]; // | |
| AT91_REG PIOB_PER; // PIO Enable Register | |
| AT91_REG PIOB_PDR; // PIO Disable Register | |
| AT91_REG PIOB_PSR; // PIO Status Register | |
| AT91_REG Reserved33[1]; // | |
| AT91_REG PIOB_OER; // Output Enable Register | |
| AT91_REG PIOB_ODR; // Output Disable Registerr | |
| AT91_REG PIOB_OSR; // Output Status Register | |
| AT91_REG Reserved34[1]; // | |
| AT91_REG PIOB_IFER; // Input Filter Enable Register | |
| AT91_REG PIOB_IFDR; // Input Filter Disable Register | |
| AT91_REG PIOB_IFSR; // Input Filter Status Register | |
| AT91_REG Reserved35[1]; // | |
| AT91_REG PIOB_SODR; // Set Output Data Register | |
| AT91_REG PIOB_CODR; // Clear Output Data Register | |
| AT91_REG PIOB_ODSR; // Output Data Status Register | |
| AT91_REG PIOB_PDSR; // Pin Data Status Register | |
| AT91_REG PIOB_IER; // Interrupt Enable Register | |
| AT91_REG PIOB_IDR; // Interrupt Disable Register | |
| AT91_REG PIOB_IMR; // Interrupt Mask Register | |
| AT91_REG PIOB_ISR; // Interrupt Status Register | |
| AT91_REG PIOB_MDER; // Multi-driver Enable Register | |
| AT91_REG PIOB_MDDR; // Multi-driver Disable Register | |
| AT91_REG PIOB_MDSR; // Multi-driver Status Register | |
| AT91_REG Reserved36[1]; // | |
| AT91_REG PIOB_PPUDR; // Pull-up Disable Register | |
| AT91_REG PIOB_PPUER; // Pull-up Enable Register | |
| AT91_REG PIOB_PPUSR; // Pull-up Status Register | |
| AT91_REG Reserved37[1]; // | |
| AT91_REG PIOB_ABSR; // Peripheral AB Select Register | |
| AT91_REG Reserved38[3]; // | |
| AT91_REG PIOB_SCIFSR; // System Clock Glitch Input Filter Select Register | |
| AT91_REG PIOB_DIFSR; // Debouncing Input Filter Select Register | |
| AT91_REG PIOB_IFDGSR; // Glitch or Debouncing Input Filter Clock Selection Status Register | |
| AT91_REG PIOB_SCDR; // Slow Clock Divider Debouncing Register | |
| AT91_REG Reserved39[4]; // | |
| AT91_REG PIOB_OWER; // Output Write Enable Register | |
| AT91_REG PIOB_OWDR; // Output Write Disable Register | |
| AT91_REG PIOB_OWSR; // Output Write Status Register | |
| AT91_REG Reserved40[1]; // | |
| AT91_REG PIOB_AIMER; // Additional Interrupt Modes Enable Register | |
| AT91_REG PIOB_AIMDR; // Additional Interrupt Modes Disables Register | |
| AT91_REG PIOB_AIMMR; // Additional Interrupt Modes Mask Register | |
| AT91_REG Reserved41[1]; // | |
| AT91_REG PIOB_ESR; // Edge Select Register | |
| AT91_REG PIOB_LSR; // Level Select Register | |
| AT91_REG PIOB_ELSR; // Edge/Level Status Register | |
| AT91_REG Reserved42[1]; // | |
| AT91_REG PIOB_FELLSR; // Falling Edge/Low Level Select Register | |
| AT91_REG PIOB_REHLSR; // Rising Edge/ High Level Select Register | |
| AT91_REG PIOB_FRLHSR; // Fall/Rise - Low/High Status Register | |
| AT91_REG Reserved43[1]; // | |
| AT91_REG PIOB_LOCKSR; // Lock Status Register | |
| AT91_REG Reserved44[6]; // | |
| AT91_REG PIOB_VER; // PIO VERSION REGISTER | |
| AT91_REG Reserved45[8]; // | |
| AT91_REG PIOB_KER; // Keypad Controller Enable Register | |
| AT91_REG PIOB_KRCR; // Keypad Controller Row Column Register | |
| AT91_REG PIOB_KDR; // Keypad Controller Debouncing Register | |
| AT91_REG Reserved46[1]; // | |
| AT91_REG PIOB_KIER; // Keypad Controller Interrupt Enable Register | |
| AT91_REG PIOB_KIDR; // Keypad Controller Interrupt Disable Register | |
| AT91_REG PIOB_KIMR; // Keypad Controller Interrupt Mask Register | |
| AT91_REG PIOB_KSR; // Keypad Controller Status Register | |
| AT91_REG PIOB_KKPR; // Keypad Controller Key Press Register | |
| AT91_REG PIOB_KKRR; // Keypad Controller Key Release Register | |
| AT91_REG Reserved47[46]; // | |
| AT91_REG PIOC_PER; // PIO Enable Register | |
| AT91_REG PIOC_PDR; // PIO Disable Register | |
| AT91_REG PIOC_PSR; // PIO Status Register | |
| AT91_REG Reserved48[1]; // | |
| AT91_REG PIOC_OER; // Output Enable Register | |
| AT91_REG PIOC_ODR; // Output Disable Registerr | |
| AT91_REG PIOC_OSR; // Output Status Register | |
| AT91_REG Reserved49[1]; // | |
| AT91_REG PIOC_IFER; // Input Filter Enable Register | |
| AT91_REG PIOC_IFDR; // Input Filter Disable Register | |
| AT91_REG PIOC_IFSR; // Input Filter Status Register | |
| AT91_REG Reserved50[1]; // | |
| AT91_REG PIOC_SODR; // Set Output Data Register | |
| AT91_REG PIOC_CODR; // Clear Output Data Register | |
| AT91_REG PIOC_ODSR; // Output Data Status Register | |
| AT91_REG PIOC_PDSR; // Pin Data Status Register | |
| AT91_REG PIOC_IER; // Interrupt Enable Register | |
| AT91_REG PIOC_IDR; // Interrupt Disable Register | |
| AT91_REG PIOC_IMR; // Interrupt Mask Register | |
| AT91_REG PIOC_ISR; // Interrupt Status Register | |
| AT91_REG PIOC_MDER; // Multi-driver Enable Register | |
| AT91_REG PIOC_MDDR; // Multi-driver Disable Register | |
| AT91_REG PIOC_MDSR; // Multi-driver Status Register | |
| AT91_REG Reserved51[1]; // | |
| AT91_REG PIOC_PPUDR; // Pull-up Disable Register | |
| AT91_REG PIOC_PPUER; // Pull-up Enable Register | |
| AT91_REG PIOC_PPUSR; // Pull-up Status Register | |
| AT91_REG Reserved52[1]; // | |
| AT91_REG PIOC_ABSR; // Peripheral AB Select Register | |
| AT91_REG Reserved53[3]; // | |
| AT91_REG PIOC_SCIFSR; // System Clock Glitch Input Filter Select Register | |
| AT91_REG PIOC_DIFSR; // Debouncing Input Filter Select Register | |
| AT91_REG PIOC_IFDGSR; // Glitch or Debouncing Input Filter Clock Selection Status Register | |
| AT91_REG PIOC_SCDR; // Slow Clock Divider Debouncing Register | |
| AT91_REG Reserved54[4]; // | |
| AT91_REG PIOC_OWER; // Output Write Enable Register | |
| AT91_REG PIOC_OWDR; // Output Write Disable Register | |
| AT91_REG PIOC_OWSR; // Output Write Status Register | |
| AT91_REG Reserved55[1]; // | |
| AT91_REG PIOC_AIMER; // Additional Interrupt Modes Enable Register | |
| AT91_REG PIOC_AIMDR; // Additional Interrupt Modes Disables Register | |
| AT91_REG PIOC_AIMMR; // Additional Interrupt Modes Mask Register | |
| AT91_REG Reserved56[1]; // | |
| AT91_REG PIOC_ESR; // Edge Select Register | |
| AT91_REG PIOC_LSR; // Level Select Register | |
| AT91_REG PIOC_ELSR; // Edge/Level Status Register | |
| AT91_REG Reserved57[1]; // | |
| AT91_REG PIOC_FELLSR; // Falling Edge/Low Level Select Register | |
| AT91_REG PIOC_REHLSR; // Rising Edge/ High Level Select Register | |
| AT91_REG PIOC_FRLHSR; // Fall/Rise - Low/High Status Register | |
| AT91_REG Reserved58[1]; // | |
| AT91_REG PIOC_LOCKSR; // Lock Status Register | |
| AT91_REG Reserved59[6]; // | |
| AT91_REG PIOC_VER; // PIO VERSION REGISTER | |
| AT91_REG Reserved60[8]; // | |
| AT91_REG PIOC_KER; // Keypad Controller Enable Register | |
| AT91_REG PIOC_KRCR; // Keypad Controller Row Column Register | |
| AT91_REG PIOC_KDR; // Keypad Controller Debouncing Register | |
| AT91_REG Reserved61[1]; // | |
| AT91_REG PIOC_KIER; // Keypad Controller Interrupt Enable Register | |
| AT91_REG PIOC_KIDR; // Keypad Controller Interrupt Disable Register | |
| AT91_REG PIOC_KIMR; // Keypad Controller Interrupt Mask Register | |
| AT91_REG PIOC_KSR; // Keypad Controller Status Register | |
| AT91_REG PIOC_KKPR; // Keypad Controller Key Press Register | |
| AT91_REG PIOC_KKRR; // Keypad Controller Key Release Register | |
| AT91_REG Reserved62[46]; // | |
| AT91_REG RSTC_RCR; // Reset Control Register | |
| AT91_REG RSTC_RSR; // Reset Status Register | |
| AT91_REG RSTC_RMR; // Reset Mode Register | |
| AT91_REG Reserved63[1]; // | |
| AT91_REG SUPC_CR; // Control Register | |
| AT91_REG SUPC_BOMR; // Brown Out Mode Register | |
| AT91_REG SUPC_MR; // Mode Register | |
| AT91_REG SUPC_WUMR; // Wake Up Mode Register | |
| AT91_REG SUPC_WUIR; // Wake Up Inputs Register | |
| AT91_REG SUPC_SR; // Status Register | |
| AT91_REG SUPC_FWUTR; // Flash Wake-up Timer Register | |
| AT91_REG Reserved64[1]; // | |
| AT91_REG RTTC_RTMR; // Real-time Mode Register | |
| AT91_REG RTTC_RTAR; // Real-time Alarm Register | |
| AT91_REG RTTC_RTVR; // Real-time Value Register | |
| AT91_REG RTTC_RTSR; // Real-time Status Register | |
| AT91_REG Reserved65[4]; // | |
| AT91_REG WDTC_WDCR; // Watchdog Control Register | |
| AT91_REG WDTC_WDMR; // Watchdog Mode Register | |
| AT91_REG WDTC_WDSR; // Watchdog Status Register | |
| AT91_REG Reserved66[1]; // | |
| AT91_REG RTC_CR; // Control Register | |
| AT91_REG RTC_MR; // Mode Register | |
| AT91_REG RTC_TIMR; // Time Register | |
| AT91_REG RTC_CALR; // Calendar Register | |
| AT91_REG RTC_TIMALR; // Time Alarm Register | |
| AT91_REG RTC_CALALR; // Calendar Alarm Register | |
| AT91_REG RTC_SR; // Status Register | |
| AT91_REG RTC_SCCR; // Status Clear Command Register | |
| AT91_REG RTC_IER; // Interrupt Enable Register | |
| AT91_REG RTC_IDR; // Interrupt Disable Register | |
| AT91_REG RTC_IMR; // Interrupt Mask Register | |
| AT91_REG RTC_VER; // Valid Entry Register | |
| AT91_REG SYS_GPBR[8]; // General Purpose Register | |
| AT91_REG Reserved67[19]; // | |
| AT91_REG RSTC_VER; // Version Register | |
| } AT91S_SYS, *AT91PS_SYS; | |
| #else | |
| #define GPBR (AT91_CAST(AT91_REG *) 0x00001290) // (GPBR) General Purpose Register | |
| #endif | |
| // -------- GPBR : (SYS Offset: 0x1290) GPBR General Purpose Register -------- | |
| #define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR HSMC4 Chip Select interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_HSMC4_CS { | |
| AT91_REG HSMC4_SETUP; // Setup Register | |
| AT91_REG HSMC4_PULSE; // Pulse Register | |
| AT91_REG HSMC4_CYCLE; // Cycle Register | |
| AT91_REG HSMC4_TIMINGS; // Timmings Register | |
| AT91_REG HSMC4_MODE; // Mode Register | |
| } AT91S_HSMC4_CS, *AT91PS_HSMC4_CS; | |
| #else | |
| #define HSMC4_SETUP (AT91_CAST(AT91_REG *) 0x00000000) // (HSMC4_SETUP) Setup Register | |
| #define HSMC4_PULSE (AT91_CAST(AT91_REG *) 0x00000004) // (HSMC4_PULSE) Pulse Register | |
| #define HSMC4_CYCLE (AT91_CAST(AT91_REG *) 0x00000008) // (HSMC4_CYCLE) Cycle Register | |
| #define HSMC4_TIMINGS (AT91_CAST(AT91_REG *) 0x0000000C) // (HSMC4_TIMINGS) Timmings Register | |
| #define HSMC4_MODE (AT91_CAST(AT91_REG *) 0x00000010) // (HSMC4_MODE) Mode Register | |
| #endif | |
| // -------- HSMC4_SETUP : (HSMC4_CS Offset: 0x0) HSMC4 SETUP -------- | |
| #define AT91C_HSMC4_NWE_SETUP (0x3F << 0) // (HSMC4_CS) NWE Setup length | |
| #define AT91C_HSMC4_NCS_WR_SETUP (0x3F << 8) // (HSMC4_CS) NCS Setup length in Write access | |
| #define AT91C_HSMC4_NRD_SETUP (0x3F << 16) // (HSMC4_CS) NRD Setup length | |
| #define AT91C_HSMC4_NCS_RD_SETUP (0x3F << 24) // (HSMC4_CS) NCS Setup legnth in Read access | |
| // -------- HSMC4_PULSE : (HSMC4_CS Offset: 0x4) HSMC4 PULSE -------- | |
| #define AT91C_HSMC4_NWE_PULSE (0x3F << 0) // (HSMC4_CS) NWE Pulse Length | |
| #define AT91C_HSMC4_NCS_WR_PULSE (0x3F << 8) // (HSMC4_CS) NCS Pulse length in WRITE access | |
| #define AT91C_HSMC4_NRD_PULSE (0x3F << 16) // (HSMC4_CS) NRD Pulse length | |
| #define AT91C_HSMC4_NCS_RD_PULSE (0x3F << 24) // (HSMC4_CS) NCS Pulse length in READ access | |
| // -------- HSMC4_CYCLE : (HSMC4_CS Offset: 0x8) HSMC4 CYCLE -------- | |
| #define AT91C_HSMC4_NWE_CYCLE (0x1FF << 0) // (HSMC4_CS) Total Write Cycle Length | |
| #define AT91C_HSMC4_NRD_CYCLE (0x1FF << 16) // (HSMC4_CS) Total Read Cycle Length | |
| // -------- HSMC4_TIMINGS : (HSMC4_CS Offset: 0xc) HSMC4 TIMINGS -------- | |
| #define AT91C_HSMC4_TCLR (0xF << 0) // (HSMC4_CS) CLE to REN low delay | |
| #define AT91C_HSMC4_TADL (0xF << 4) // (HSMC4_CS) ALE to data start | |
| #define AT91C_HSMC4_TAR (0xF << 8) // (HSMC4_CS) ALE to REN low delay | |
| #define AT91C_HSMC4_OCMSEN (0x1 << 12) // (HSMC4_CS) Off Chip Memory Scrambling Enable | |
| #define AT91C_HSMC4_TRR (0xF << 16) // (HSMC4_CS) Ready to REN low delay | |
| #define AT91C_HSMC4_TWB (0xF << 24) // (HSMC4_CS) WEN high to REN to busy | |
| #define AT91C_HSMC4_RBNSEL (0x7 << 28) // (HSMC4_CS) Ready/Busy Line Selection | |
| #define AT91C_HSMC4_NFSEL (0x1 << 31) // (HSMC4_CS) Nand Flash Selection | |
| // -------- HSMC4_MODE : (HSMC4_CS Offset: 0x10) HSMC4 MODE -------- | |
| #define AT91C_HSMC4_READ_MODE (0x1 << 0) // (HSMC4_CS) Read Mode | |
| #define AT91C_HSMC4_WRITE_MODE (0x1 << 1) // (HSMC4_CS) Write Mode | |
| #define AT91C_HSMC4_EXNW_MODE (0x3 << 4) // (HSMC4_CS) NWAIT Mode | |
| #define AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE (0x0 << 4) // (HSMC4_CS) External NWAIT disabled. | |
| #define AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN (0x2 << 4) // (HSMC4_CS) External NWAIT enabled in frozen mode. | |
| #define AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY (0x3 << 4) // (HSMC4_CS) External NWAIT enabled in ready mode. | |
| #define AT91C_HSMC4_BAT (0x1 << 8) // (HSMC4_CS) Byte Access Type | |
| #define AT91C_HSMC4_BAT_BYTE_SELECT (0x0 << 8) // (HSMC4_CS) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. | |
| #define AT91C_HSMC4_BAT_BYTE_WRITE (0x1 << 8) // (HSMC4_CS) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. | |
| #define AT91C_HSMC4_DBW (0x3 << 12) // (HSMC4_CS) Data Bus Width | |
| #define AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (HSMC4_CS) 8 bits. | |
| #define AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (HSMC4_CS) 16 bits. | |
| #define AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (HSMC4_CS) 32 bits. | |
| #define AT91C_HSMC4_TDF_CYCLES (0xF << 16) // (HSMC4_CS) Data Float Time. | |
| #define AT91C_HSMC4_TDF_MODE (0x1 << 20) // (HSMC4_CS) TDF Enabled. | |
| #define AT91C_HSMC4_PMEN (0x1 << 24) // (HSMC4_CS) Page Mode Enabled. | |
| #define AT91C_HSMC4_PS (0x3 << 28) // (HSMC4_CS) Page Size | |
| #define AT91C_HSMC4_PS_SIZE_FOUR_BYTES (0x0 << 28) // (HSMC4_CS) 4 bytes. | |
| #define AT91C_HSMC4_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (HSMC4_CS) 8 bytes. | |
| #define AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (HSMC4_CS) 16 bytes. | |
| #define AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (HSMC4_CS) 32 bytes. | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR AHB Static Memory Controller 4 Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_HSMC4 { | |
| AT91_REG HSMC4_CFG; // Configuration Register | |
| AT91_REG HSMC4_CTRL; // Control Register | |
| AT91_REG HSMC4_SR; // Status Register | |
| AT91_REG HSMC4_IER; // Interrupt Enable Register | |
| AT91_REG HSMC4_IDR; // Interrupt Disable Register | |
| AT91_REG HSMC4_IMR; // Interrupt Mask Register | |
| AT91_REG HSMC4_ADDR; // Address Cycle Zero Register | |
| AT91_REG HSMC4_BANK; // Bank Register | |
| AT91_REG HSMC4_ECCCR; // ECC reset register | |
| AT91_REG HSMC4_ECCCMD; // ECC Page size register | |
| AT91_REG HSMC4_ECCSR1; // ECC Status register 1 | |
| AT91_REG HSMC4_ECCPR0; // ECC Parity register 0 | |
| AT91_REG HSMC4_ECCPR1; // ECC Parity register 1 | |
| AT91_REG HSMC4_ECCSR2; // ECC Status register 2 | |
| AT91_REG HSMC4_ECCPR2; // ECC Parity register 2 | |
| AT91_REG HSMC4_ECCPR3; // ECC Parity register 3 | |
| AT91_REG HSMC4_ECCPR4; // ECC Parity register 4 | |
| AT91_REG HSMC4_ECCPR5; // ECC Parity register 5 | |
| AT91_REG HSMC4_ECCPR6; // ECC Parity register 6 | |
| AT91_REG HSMC4_ECCPR7; // ECC Parity register 7 | |
| AT91_REG HSMC4_ECCPR8; // ECC Parity register 8 | |
| AT91_REG HSMC4_ECCPR9; // ECC Parity register 9 | |
| AT91_REG HSMC4_ECCPR10; // ECC Parity register 10 | |
| AT91_REG HSMC4_ECCPR11; // ECC Parity register 11 | |
| AT91_REG HSMC4_ECCPR12; // ECC Parity register 12 | |
| AT91_REG HSMC4_ECCPR13; // ECC Parity register 13 | |
| AT91_REG HSMC4_ECCPR14; // ECC Parity register 14 | |
| AT91_REG HSMC4_Eccpr15; // ECC Parity register 15 | |
| AT91_REG Reserved0[40]; // | |
| AT91_REG HSMC4_OCMS; // OCMS MODE register | |
| AT91_REG HSMC4_KEY1; // KEY1 Register | |
| AT91_REG HSMC4_KEY2; // KEY2 Register | |
| AT91_REG Reserved1[50]; // | |
| AT91_REG HSMC4_WPCR; // Write Protection Control register | |
| AT91_REG HSMC4_WPSR; // Write Protection Status Register | |
| AT91_REG HSMC4_ADDRSIZE; // Write Protection Status Register | |
| AT91_REG HSMC4_IPNAME1; // Write Protection Status Register | |
| AT91_REG HSMC4_IPNAME2; // Write Protection Status Register | |
| AT91_REG HSMC4_FEATURES; // Write Protection Status Register | |
| AT91_REG HSMC4_VER; // HSMC4 Version Register | |
| AT91_REG HSMC4_DUMMY; // This rtegister was created only ti have AHB constants | |
| } AT91S_HSMC4, *AT91PS_HSMC4; | |
| #else | |
| #define HSMC4_CFG (AT91_CAST(AT91_REG *) 0x00000000) // (HSMC4_CFG) Configuration Register | |
| #define HSMC4_CTRL (AT91_CAST(AT91_REG *) 0x00000004) // (HSMC4_CTRL) Control Register | |
| #define HSMC4_SR (AT91_CAST(AT91_REG *) 0x00000008) // (HSMC4_SR) Status Register | |
| #define HSMC4_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (HSMC4_IER) Interrupt Enable Register | |
| #define HSMC4_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (HSMC4_IDR) Interrupt Disable Register | |
| #define HSMC4_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (HSMC4_IMR) Interrupt Mask Register | |
| #define HSMC4_ADDR (AT91_CAST(AT91_REG *) 0x00000018) // (HSMC4_ADDR) Address Cycle Zero Register | |
| #define HSMC4_BANK (AT91_CAST(AT91_REG *) 0x0000001C) // (HSMC4_BANK) Bank Register | |
| #define HSMC4_ECCCR (AT91_CAST(AT91_REG *) 0x00000020) // (HSMC4_ECCCR) ECC reset register | |
| #define HSMC4_ECCCMD (AT91_CAST(AT91_REG *) 0x00000024) // (HSMC4_ECCCMD) ECC Page size register | |
| #define HSMC4_ECCSR1 (AT91_CAST(AT91_REG *) 0x00000028) // (HSMC4_ECCSR1) ECC Status register 1 | |
| #define HSMC4_ECCPR0 (AT91_CAST(AT91_REG *) 0x0000002C) // (HSMC4_ECCPR0) ECC Parity register 0 | |
| #define HSMC4_ECCPR1 (AT91_CAST(AT91_REG *) 0x00000030) // (HSMC4_ECCPR1) ECC Parity register 1 | |
| #define HSMC4_ECCSR2 (AT91_CAST(AT91_REG *) 0x00000034) // (HSMC4_ECCSR2) ECC Status register 2 | |
| #define HSMC4_ECCPR2 (AT91_CAST(AT91_REG *) 0x00000038) // (HSMC4_ECCPR2) ECC Parity register 2 | |
| #define HSMC4_ECCPR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (HSMC4_ECCPR3) ECC Parity register 3 | |
| #define HSMC4_ECCPR4 (AT91_CAST(AT91_REG *) 0x00000040) // (HSMC4_ECCPR4) ECC Parity register 4 | |
| #define HSMC4_ECCPR5 (AT91_CAST(AT91_REG *) 0x00000044) // (HSMC4_ECCPR5) ECC Parity register 5 | |
| #define HSMC4_ECCPR6 (AT91_CAST(AT91_REG *) 0x00000048) // (HSMC4_ECCPR6) ECC Parity register 6 | |
| #define HSMC4_ECCPR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (HSMC4_ECCPR7) ECC Parity register 7 | |
| #define HSMC4_ECCPR8 (AT91_CAST(AT91_REG *) 0x00000050) // (HSMC4_ECCPR8) ECC Parity register 8 | |
| #define HSMC4_ECCPR9 (AT91_CAST(AT91_REG *) 0x00000054) // (HSMC4_ECCPR9) ECC Parity register 9 | |
| #define HSMC4_ECCPR10 (AT91_CAST(AT91_REG *) 0x00000058) // (HSMC4_ECCPR10) ECC Parity register 10 | |
| #define HSMC4_ECCPR11 (AT91_CAST(AT91_REG *) 0x0000005C) // (HSMC4_ECCPR11) ECC Parity register 11 | |
| #define HSMC4_ECCPR12 (AT91_CAST(AT91_REG *) 0x00000060) // (HSMC4_ECCPR12) ECC Parity register 12 | |
| #define HSMC4_ECCPR13 (AT91_CAST(AT91_REG *) 0x00000064) // (HSMC4_ECCPR13) ECC Parity register 13 | |
| #define HSMC4_ECCPR14 (AT91_CAST(AT91_REG *) 0x00000068) // (HSMC4_ECCPR14) ECC Parity register 14 | |
| #define Hsmc4_Eccpr15 (AT91_CAST(AT91_REG *) 0x0000006C) // (Hsmc4_Eccpr15) ECC Parity register 15 | |
| #define HSMC4_OCMS (AT91_CAST(AT91_REG *) 0x00000110) // (HSMC4_OCMS) OCMS MODE register | |
| #define HSMC4_KEY1 (AT91_CAST(AT91_REG *) 0x00000114) // (HSMC4_KEY1) KEY1 Register | |
| #define HSMC4_KEY2 (AT91_CAST(AT91_REG *) 0x00000118) // (HSMC4_KEY2) KEY2 Register | |
| #define HSMC4_WPCR (AT91_CAST(AT91_REG *) 0x000001E4) // (HSMC4_WPCR) Write Protection Control register | |
| #define HSMC4_WPSR (AT91_CAST(AT91_REG *) 0x000001E8) // (HSMC4_WPSR) Write Protection Status Register | |
| #define HSMC4_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000001EC) // (HSMC4_ADDRSIZE) Write Protection Status Register | |
| #define HSMC4_IPNAME1 (AT91_CAST(AT91_REG *) 0x000001F0) // (HSMC4_IPNAME1) Write Protection Status Register | |
| #define HSMC4_IPNAME2 (AT91_CAST(AT91_REG *) 0x000001F4) // (HSMC4_IPNAME2) Write Protection Status Register | |
| #define HSMC4_FEATURES (AT91_CAST(AT91_REG *) 0x000001F8) // (HSMC4_FEATURES) Write Protection Status Register | |
| #define HSMC4_VER (AT91_CAST(AT91_REG *) 0x000001FC) // (HSMC4_VER) HSMC4 Version Register | |
| #define HSMC4_DUMMY (AT91_CAST(AT91_REG *) 0x00000200) // (HSMC4_DUMMY) This rtegister was created only ti have AHB constants | |
| #endif | |
| // -------- HSMC4_CFG : (HSMC4 Offset: 0x0) Configuration Register -------- | |
| #define AT91C_HSMC4_PAGESIZE (0x3 << 0) // (HSMC4) PAGESIZE field description | |
| #define AT91C_HSMC4_PAGESIZE_528_Bytes (0x0) // (HSMC4) 512 bytes plus 16 bytes page size | |
| #define AT91C_HSMC4_PAGESIZE_1056_Bytes (0x1) // (HSMC4) 1024 bytes plus 32 bytes page size | |
| #define AT91C_HSMC4_PAGESIZE_2112_Bytes (0x2) // (HSMC4) 2048 bytes plus 64 bytes page size | |
| #define AT91C_HSMC4_PAGESIZE_4224_Bytes (0x3) // (HSMC4) 4096 bytes plus 128 bytes page size | |
| #define AT91C_HSMC4_WSPARE (0x1 << 8) // (HSMC4) Spare area access in Write Mode | |
| #define AT91C_HSMC4_RSPARE (0x1 << 9) // (HSMC4) Spare area access in Read Mode | |
| #define AT91C_HSMC4_EDGECTRL (0x1 << 12) // (HSMC4) Rising/Falling Edge Detection Control | |
| #define AT91C_HSMC4_RBEDGE (0x1 << 13) // (HSMC4) Ready/Busy Signal edge Detection | |
| #define AT91C_HSMC4_DTOCYC (0xF << 16) // (HSMC4) Data Timeout Cycle Number | |
| #define AT91C_HSMC4_DTOMUL (0x7 << 20) // (HSMC4) Data Timeout Multiplier | |
| #define AT91C_HSMC4_DTOMUL_1 (0x0 << 20) // (HSMC4) DTOCYC x 1 | |
| #define AT91C_HSMC4_DTOMUL_16 (0x1 << 20) // (HSMC4) DTOCYC x 16 | |
| #define AT91C_HSMC4_DTOMUL_128 (0x2 << 20) // (HSMC4) DTOCYC x 128 | |
| #define AT91C_HSMC4_DTOMUL_256 (0x3 << 20) // (HSMC4) DTOCYC x 256 | |
| #define AT91C_HSMC4_DTOMUL_1024 (0x4 << 20) // (HSMC4) DTOCYC x 1024 | |
| #define AT91C_HSMC4_DTOMUL_4096 (0x5 << 20) // (HSMC4) DTOCYC x 4096 | |
| #define AT91C_HSMC4_DTOMUL_65536 (0x6 << 20) // (HSMC4) DTOCYC x 65536 | |
| #define AT91C_HSMC4_DTOMUL_1048576 (0x7 << 20) // (HSMC4) DTOCYC x 1048576 | |
| // -------- HSMC4_CTRL : (HSMC4 Offset: 0x4) Control Register -------- | |
| #define AT91C_HSMC4_NFCEN (0x1 << 0) // (HSMC4) Nand Flash Controller Host Enable | |
| #define AT91C_HSMC4_NFCDIS (0x1 << 1) // (HSMC4) Nand Flash Controller Host Disable | |
| #define AT91C_HSMC4_HOSTEN (0x1 << 8) // (HSMC4) If set to one, the Host controller is activated and perform a data transfer phase. | |
| #define AT91C_HSMC4_HOSTWR (0x1 << 11) // (HSMC4) If this field is set to one, the host transfers data from the internal SRAM to the Memory Device. | |
| #define AT91C_HSMC4_HOSTCSID (0x7 << 12) // (HSMC4) Host Controller Chip select Id | |
| #define AT91C_HSMC4_HOSTCSID_0 (0x0 << 12) // (HSMC4) CS0 | |
| #define AT91C_HSMC4_HOSTCSID_1 (0x1 << 12) // (HSMC4) CS1 | |
| #define AT91C_HSMC4_HOSTCSID_2 (0x2 << 12) // (HSMC4) CS2 | |
| #define AT91C_HSMC4_HOSTCSID_3 (0x3 << 12) // (HSMC4) CS3 | |
| #define AT91C_HSMC4_HOSTCSID_4 (0x4 << 12) // (HSMC4) CS4 | |
| #define AT91C_HSMC4_HOSTCSID_5 (0x5 << 12) // (HSMC4) CS5 | |
| #define AT91C_HSMC4_HOSTCSID_6 (0x6 << 12) // (HSMC4) CS6 | |
| #define AT91C_HSMC4_HOSTCSID_7 (0x7 << 12) // (HSMC4) CS7 | |
| #define AT91C_HSMC4_VALID (0x1 << 15) // (HSMC4) When set to 1, a write operation modifies both HOSTCSID and HOSTWR fields. | |
| // -------- HSMC4_SR : (HSMC4 Offset: 0x8) HSMC4 Status Register -------- | |
| #define AT91C_HSMC4_NFCSTS (0x1 << 0) // (HSMC4) Nand Flash Controller status | |
| #define AT91C_HSMC4_RBRISE (0x1 << 4) // (HSMC4) Selected Ready Busy Rising Edge Detected flag | |
| #define AT91C_HSMC4_RBFALL (0x1 << 5) // (HSMC4) Selected Ready Busy Falling Edge Detected flag | |
| #define AT91C_HSMC4_HOSTBUSY (0x1 << 8) // (HSMC4) Host Busy | |
| #define AT91C_HSMC4_HOSTW (0x1 << 11) // (HSMC4) Host Write/Read Operation | |
| #define AT91C_HSMC4_HOSTCS (0x7 << 12) // (HSMC4) Host Controller Chip select Id | |
| #define AT91C_HSMC4_HOSTCS_0 (0x0 << 12) // (HSMC4) CS0 | |
| #define AT91C_HSMC4_HOSTCS_1 (0x1 << 12) // (HSMC4) CS1 | |
| #define AT91C_HSMC4_HOSTCS_2 (0x2 << 12) // (HSMC4) CS2 | |
| #define AT91C_HSMC4_HOSTCS_3 (0x3 << 12) // (HSMC4) CS3 | |
| #define AT91C_HSMC4_HOSTCS_4 (0x4 << 12) // (HSMC4) CS4 | |
| #define AT91C_HSMC4_HOSTCS_5 (0x5 << 12) // (HSMC4) CS5 | |
| #define AT91C_HSMC4_HOSTCS_6 (0x6 << 12) // (HSMC4) CS6 | |
| #define AT91C_HSMC4_HOSTCS_7 (0x7 << 12) // (HSMC4) CS7 | |
| #define AT91C_HSMC4_XFRDONE (0x1 << 16) // (HSMC4) Host Data Transfer Terminated | |
| #define AT91C_HSMC4_CMDDONE (0x1 << 17) // (HSMC4) Command Done | |
| #define AT91C_HSMC4_ECCRDY (0x1 << 18) // (HSMC4) ECC ready | |
| #define AT91C_HSMC4_DTOE (0x1 << 20) // (HSMC4) Data timeout Error | |
| #define AT91C_HSMC4_UNDEF (0x1 << 21) // (HSMC4) Undefined Area Error | |
| #define AT91C_HSMC4_AWB (0x1 << 22) // (HSMC4) Accessing While Busy Error | |
| #define AT91C_HSMC4_HASE (0x1 << 23) // (HSMC4) Host Controller Access Size Error | |
| #define AT91C_HSMC4_RBEDGE0 (0x1 << 24) // (HSMC4) Ready Busy line 0 Edge detected | |
| #define AT91C_HSMC4_RBEDGE1 (0x1 << 25) // (HSMC4) Ready Busy line 1 Edge detected | |
| #define AT91C_HSMC4_RBEDGE2 (0x1 << 26) // (HSMC4) Ready Busy line 2 Edge detected | |
| #define AT91C_HSMC4_RBEDGE3 (0x1 << 27) // (HSMC4) Ready Busy line 3 Edge detected | |
| #define AT91C_HSMC4_RBEDGE4 (0x1 << 28) // (HSMC4) Ready Busy line 4 Edge detected | |
| #define AT91C_HSMC4_RBEDGE5 (0x1 << 29) // (HSMC4) Ready Busy line 5 Edge detected | |
| #define AT91C_HSMC4_RBEDGE6 (0x1 << 30) // (HSMC4) Ready Busy line 6 Edge detected | |
| #define AT91C_HSMC4_RBEDGE7 (0x1 << 31) // (HSMC4) Ready Busy line 7 Edge detected | |
| // -------- HSMC4_IER : (HSMC4 Offset: 0xc) HSMC4 Interrupt Enable Register -------- | |
| // -------- HSMC4_IDR : (HSMC4 Offset: 0x10) HSMC4 Interrupt Disable Register -------- | |
| // -------- HSMC4_IMR : (HSMC4 Offset: 0x14) HSMC4 Interrupt Mask Register -------- | |
| // -------- HSMC4_ADDR : (HSMC4 Offset: 0x18) Address Cycle Zero Register -------- | |
| #define AT91C_HSMC4_ADDRCYCLE0 (0xFF << 0) // (HSMC4) Nand Flash Array Address cycle 0 | |
| // -------- HSMC4_BANK : (HSMC4 Offset: 0x1c) Bank Register -------- | |
| #define AT91C_BANK (0x7 << 0) // (HSMC4) Bank identifier | |
| #define AT91C_BANK_0 (0x0) // (HSMC4) BANK0 | |
| #define AT91C_BANK_1 (0x1) // (HSMC4) BANK1 | |
| #define AT91C_BANK_2 (0x2) // (HSMC4) BANK2 | |
| #define AT91C_BANK_3 (0x3) // (HSMC4) BANK3 | |
| #define AT91C_BANK_4 (0x4) // (HSMC4) BANK4 | |
| #define AT91C_BANK_5 (0x5) // (HSMC4) BANK5 | |
| #define AT91C_BANK_6 (0x6) // (HSMC4) BANK6 | |
| #define AT91C_BANK_7 (0x7) // (HSMC4) BANK7 | |
| // -------- HSMC4_ECCCR : (HSMC4 Offset: 0x20) ECC Control Register -------- | |
| #define AT91C_HSMC4_ECCRESET (0x1 << 0) // (HSMC4) Reset ECC | |
| // -------- HSMC4_ECCCMD : (HSMC4 Offset: 0x24) ECC mode register -------- | |
| #define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (HSMC4) Nand Flash page size | |
| #define AT91C_ECC_TYPCORRECT (0x3 << 4) // (HSMC4) Nand Flash page size | |
| #define AT91C_ECC_TYPCORRECT_ONE_PER_PAGE (0x0 << 4) // (HSMC4) | |
| #define AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES (0x1 << 4) // (HSMC4) | |
| #define AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES (0x2 << 4) // (HSMC4) | |
| // -------- HSMC4_ECCSR1 : (HSMC4 Offset: 0x28) ECC Status Register 1 -------- | |
| #define AT91C_HSMC4_ECC_RECERR0 (0x1 << 0) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR0 (0x1 << 1) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR0 (0x1 << 2) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR1 (0x1 << 4) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR1 (0x1 << 5) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR1 (0x1 << 6) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR2 (0x1 << 8) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR2 (0x1 << 9) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR2 (0x1 << 10) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR3 (0x1 << 12) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR3 (0x1 << 13) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR3 (0x1 << 14) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR4 (0x1 << 16) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR4 (0x1 << 17) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR4 (0x1 << 18) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR5 (0x1 << 20) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR5 (0x1 << 21) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR5 (0x1 << 22) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR6 (0x1 << 24) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR6 (0x1 << 25) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR6 (0x1 << 26) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR7 (0x1 << 28) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR7 (0x1 << 29) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR7 (0x1 << 30) // (HSMC4) Multiple Error | |
| // -------- HSMC4_ECCPR0 : (HSMC4 Offset: 0x2c) HSMC4 ECC parity Register 0 -------- | |
| #define AT91C_HSMC4_ECC_BITADDR (0x7 << 0) // (HSMC4) Corrupted Bit Address in the page | |
| #define AT91C_HSMC4_ECC_WORDADDR (0xFF << 3) // (HSMC4) Corrupted Word Address in the page | |
| #define AT91C_HSMC4_ECC_NPARITY (0x7FF << 12) // (HSMC4) Parity N | |
| // -------- HSMC4_ECCPR1 : (HSMC4 Offset: 0x30) HSMC4 ECC parity Register 1 -------- | |
| // -------- HSMC4_ECCSR2 : (HSMC4 Offset: 0x34) ECC Status Register 2 -------- | |
| #define AT91C_HSMC4_ECC_RECERR8 (0x1 << 0) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR8 (0x1 << 1) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR8 (0x1 << 2) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR9 (0x1 << 4) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR9 (0x1 << 5) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR9 (0x1 << 6) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR10 (0x1 << 8) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR10 (0x1 << 9) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR10 (0x1 << 10) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR11 (0x1 << 12) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR11 (0x1 << 13) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR11 (0x1 << 14) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR12 (0x1 << 16) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR12 (0x1 << 17) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR12 (0x1 << 18) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR13 (0x1 << 20) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR13 (0x1 << 21) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR13 (0x1 << 22) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR14 (0x1 << 24) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR14 (0x1 << 25) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR14 (0x1 << 26) // (HSMC4) Multiple Error | |
| #define AT91C_HSMC4_ECC_RECERR15 (0x1 << 28) // (HSMC4) Recoverable Error | |
| #define AT91C_HSMC4_ECC_ECCERR15 (0x1 << 29) // (HSMC4) ECC Error | |
| #define AT91C_HSMC4_ECC_MULERR15 (0x1 << 30) // (HSMC4) Multiple Error | |
| // -------- HSMC4_ECCPR2 : (HSMC4 Offset: 0x38) HSMC4 ECC parity Register 2 -------- | |
| // -------- HSMC4_ECCPR3 : (HSMC4 Offset: 0x3c) HSMC4 ECC parity Register 3 -------- | |
| // -------- HSMC4_ECCPR4 : (HSMC4 Offset: 0x40) HSMC4 ECC parity Register 4 -------- | |
| // -------- HSMC4_ECCPR5 : (HSMC4 Offset: 0x44) HSMC4 ECC parity Register 5 -------- | |
| // -------- HSMC4_ECCPR6 : (HSMC4 Offset: 0x48) HSMC4 ECC parity Register 6 -------- | |
| // -------- HSMC4_ECCPR7 : (HSMC4 Offset: 0x4c) HSMC4 ECC parity Register 7 -------- | |
| // -------- HSMC4_ECCPR8 : (HSMC4 Offset: 0x50) HSMC4 ECC parity Register 8 -------- | |
| // -------- HSMC4_ECCPR9 : (HSMC4 Offset: 0x54) HSMC4 ECC parity Register 9 -------- | |
| // -------- HSMC4_ECCPR10 : (HSMC4 Offset: 0x58) HSMC4 ECC parity Register 10 -------- | |
| // -------- HSMC4_ECCPR11 : (HSMC4 Offset: 0x5c) HSMC4 ECC parity Register 11 -------- | |
| // -------- HSMC4_ECCPR12 : (HSMC4 Offset: 0x60) HSMC4 ECC parity Register 12 -------- | |
| // -------- HSMC4_ECCPR13 : (HSMC4 Offset: 0x64) HSMC4 ECC parity Register 13 -------- | |
| // -------- HSMC4_ECCPR14 : (HSMC4 Offset: 0x68) HSMC4 ECC parity Register 14 -------- | |
| // -------- HSMC4_ECCPR15 : (HSMC4 Offset: 0x6c) HSMC4 ECC parity Register 15 -------- | |
| // -------- HSMC4_OCMS : (HSMC4 Offset: 0x110) HSMC4 OCMS Register -------- | |
| #define AT91C_HSMC4_OCMS_SRSE (0x1 << 0) // (HSMC4) Static Memory Controller Scrambling Enable | |
| #define AT91C_HSMC4_OCMS_SMSE (0x1 << 1) // (HSMC4) SRAM Scramling Enable | |
| // -------- HSMC4_KEY1 : (HSMC4 Offset: 0x114) HSMC4 OCMS KEY1 Register -------- | |
| #define AT91C_HSMC4_OCMS_KEY1 (0x0 << 0) // (HSMC4) OCMS Key 2 | |
| // -------- HSMC4_OCMS_KEY2 : (HSMC4 Offset: 0x118) HSMC4 OCMS KEY2 Register -------- | |
| #define AT91C_HSMC4_OCMS_KEY2 (0x0 << 0) // (HSMC4) OCMS Key 2 | |
| // -------- HSMC4_WPCR : (HSMC4 Offset: 0x1e4) HSMC4 Witre Protection Control Register -------- | |
| #define AT91C_HSMC4_WP_EN (0x1 << 0) // (HSMC4) Write Protection Enable | |
| #define AT91C_HSMC4_WP_KEY (0xFFFFFF << 8) // (HSMC4) Protection Password | |
| // -------- HSMC4_WPSR : (HSMC4 Offset: 0x1e8) HSMC4 WPSR Register -------- | |
| #define AT91C_HSMC4_WP_VS (0xF << 0) // (HSMC4) Write Protection Violation Status | |
| #define AT91C_HSMC4_WP_VS_WP_VS0 (0x0) // (HSMC4) No write protection violation since the last read of this register | |
| #define AT91C_HSMC4_WP_VS_WP_VS1 (0x1) // (HSMC4) write protection detected unauthorized attempt to write a control register had occured (since the last read) | |
| #define AT91C_HSMC4_WP_VS_WP_VS2 (0x2) // (HSMC4) Software reset had been performed while write protection was enabled (since the last read) | |
| #define AT91C_HSMC4_WP_VS_WP_VS3 (0x3) // (HSMC4) Both write protection violation and software reset with write protection enabled had occured since the last read | |
| #define AT91C_ (0x0 << 8) // (HSMC4) | |
| // -------- HSMC4_VER : (HSMC4 Offset: 0x1fc) HSMC4 VERSION Register -------- | |
| // -------- HSMC4_DUMMY : (HSMC4 Offset: 0x200) HSMC4 DUMMY REGISTER -------- | |
| #define AT91C_HSMC4_CMD1 (0xFF << 2) // (HSMC4) Command Register Value for Cycle 1 | |
| #define AT91C_HSMC4_CMD2 (0xFF << 10) // (HSMC4) Command Register Value for Cycle 2 | |
| #define AT91C_HSMC4_VCMD2 (0x1 << 18) // (HSMC4) Valid Cycle 2 Command | |
| #define AT91C_HSMC4_ACYCLE (0x7 << 19) // (HSMC4) Number of Address required for the current command | |
| #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_NONE (0x0 << 19) // (HSMC4) No address cycle | |
| #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_ONE (0x1 << 19) // (HSMC4) One address cycle | |
| #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_TWO (0x2 << 19) // (HSMC4) Two address cycles | |
| #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_THREE (0x3 << 19) // (HSMC4) Three address cycles | |
| #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FOUR (0x4 << 19) // (HSMC4) Four address cycles | |
| #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FIVE (0x5 << 19) // (HSMC4) Five address cycles | |
| #define AT91C_HSMC4_CSID (0x7 << 22) // (HSMC4) Chip Select Identifier | |
| #define AT91C_HSMC4_CSID_0 (0x0 << 22) // (HSMC4) CS0 | |
| #define AT91C_HSMC4_CSID_1 (0x1 << 22) // (HSMC4) CS1 | |
| #define AT91C_HSMC4_CSID_2 (0x2 << 22) // (HSMC4) CS2 | |
| #define AT91C_HSMC4_CSID_3 (0x3 << 22) // (HSMC4) CS3 | |
| #define AT91C_HSMC4_CSID_4 (0x4 << 22) // (HSMC4) CS4 | |
| #define AT91C_HSMC4_CSID_5 (0x5 << 22) // (HSMC4) CS5 | |
| #define AT91C_HSMC4_CSID_6 (0x6 << 22) // (HSMC4) CS6 | |
| #define AT91C_HSMC4_CSID_7 (0x7 << 22) // (HSMC4) CS7 | |
| #define AT91C_HSMC4_HOST_EN (0x1 << 25) // (HSMC4) Host Main Controller Enable | |
| #define AT91C_HSMC4_HOST_WR (0x1 << 26) // (HSMC4) HOSTWR : Host Main Controller Write Enable | |
| #define AT91C_HSMC4_HOSTCMD (0x1 << 27) // (HSMC4) Host Command Enable | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR AHB Matrix2 Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_HMATRIX2 { | |
| AT91_REG HMATRIX2_MCFG0; // Master Configuration Register 0 : ARM I and D | |
| AT91_REG HMATRIX2_MCFG1; // Master Configuration Register 1 : ARM S | |
| AT91_REG HMATRIX2_MCFG2; // Master Configuration Register 2 | |
| AT91_REG HMATRIX2_MCFG3; // Master Configuration Register 3 | |
| AT91_REG HMATRIX2_MCFG4; // Master Configuration Register 4 | |
| AT91_REG HMATRIX2_MCFG5; // Master Configuration Register 5 | |
| AT91_REG HMATRIX2_MCFG6; // Master Configuration Register 6 | |
| AT91_REG HMATRIX2_MCFG7; // Master Configuration Register 7 | |
| AT91_REG Reserved0[8]; // | |
| AT91_REG HMATRIX2_SCFG0; // Slave Configuration Register 0 | |
| AT91_REG HMATRIX2_SCFG1; // Slave Configuration Register 1 | |
| AT91_REG HMATRIX2_SCFG2; // Slave Configuration Register 2 | |
| AT91_REG HMATRIX2_SCFG3; // Slave Configuration Register 3 | |
| AT91_REG HMATRIX2_SCFG4; // Slave Configuration Register 4 | |
| AT91_REG HMATRIX2_SCFG5; // Slave Configuration Register 5 | |
| AT91_REG HMATRIX2_SCFG6; // Slave Configuration Register 6 | |
| AT91_REG HMATRIX2_SCFG7; // Slave Configuration Register 5 | |
| AT91_REG HMATRIX2_SCFG8; // Slave Configuration Register 8 | |
| AT91_REG Reserved1[43]; // | |
| AT91_REG HMATRIX2_SFR0 ; // Special Function Register 0 | |
| AT91_REG HMATRIX2_SFR1 ; // Special Function Register 1 | |
| AT91_REG HMATRIX2_SFR2 ; // Special Function Register 2 | |
| AT91_REG HMATRIX2_SFR3 ; // Special Function Register 3 | |
| AT91_REG HMATRIX2_SFR4 ; // Special Function Register 4 | |
| AT91_REG HMATRIX2_SFR5 ; // Special Function Register 5 | |
| AT91_REG HMATRIX2_SFR6 ; // Special Function Register 6 | |
| AT91_REG HMATRIX2_SFR7 ; // Special Function Register 7 | |
| AT91_REG HMATRIX2_SFR8 ; // Special Function Register 8 | |
| AT91_REG HMATRIX2_SFR9 ; // Special Function Register 9 | |
| AT91_REG HMATRIX2_SFR10; // Special Function Register 10 | |
| AT91_REG HMATRIX2_SFR11; // Special Function Register 11 | |
| AT91_REG HMATRIX2_SFR12; // Special Function Register 12 | |
| AT91_REG HMATRIX2_SFR13; // Special Function Register 13 | |
| AT91_REG HMATRIX2_SFR14; // Special Function Register 14 | |
| AT91_REG HMATRIX2_SFR15; // Special Function Register 15 | |
| AT91_REG Reserved2[39]; // | |
| AT91_REG HMATRIX2_ADDRSIZE; // HMATRIX2 ADDRSIZE REGISTER | |
| AT91_REG HMATRIX2_IPNAME1; // HMATRIX2 IPNAME1 REGISTER | |
| AT91_REG HMATRIX2_IPNAME2; // HMATRIX2 IPNAME2 REGISTER | |
| AT91_REG HMATRIX2_FEATURES; // HMATRIX2 FEATURES REGISTER | |
| AT91_REG HMATRIX2_VER; // HMATRIX2 VERSION REGISTER | |
| } AT91S_HMATRIX2, *AT91PS_HMATRIX2; | |
| #else | |
| #define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 : ARM I and D | |
| #define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 : ARM S | |
| #define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 | |
| #define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 | |
| #define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 | |
| #define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 | |
| #define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 | |
| #define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 | |
| #define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 | |
| #define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 | |
| #define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 | |
| #define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 | |
| #define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 | |
| #define MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0x00000054) // (MATRIX_SCFG5) Slave Configuration Register 5 | |
| #define MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0x00000058) // (MATRIX_SCFG6) Slave Configuration Register 6 | |
| #define MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0x0000005C) // (MATRIX_SCFG7) Slave Configuration Register 5 | |
| #define MATRIX_SCFG8 (AT91_CAST(AT91_REG *) 0x00000060) // (MATRIX_SCFG8) Slave Configuration Register 8 | |
| #define MATRIX_SFR0 (AT91_CAST(AT91_REG *) 0x00000110) // (MATRIX_SFR0 ) Special Function Register 0 | |
| #define MATRIX_SFR1 (AT91_CAST(AT91_REG *) 0x00000114) // (MATRIX_SFR1 ) Special Function Register 1 | |
| #define MATRIX_SFR2 (AT91_CAST(AT91_REG *) 0x00000118) // (MATRIX_SFR2 ) Special Function Register 2 | |
| #define MATRIX_SFR3 (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_SFR3 ) Special Function Register 3 | |
| #define MATRIX_SFR4 (AT91_CAST(AT91_REG *) 0x00000120) // (MATRIX_SFR4 ) Special Function Register 4 | |
| #define MATRIX_SFR5 (AT91_CAST(AT91_REG *) 0x00000124) // (MATRIX_SFR5 ) Special Function Register 5 | |
| #define MATRIX_SFR6 (AT91_CAST(AT91_REG *) 0x00000128) // (MATRIX_SFR6 ) Special Function Register 6 | |
| #define MATRIX_SFR7 (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_SFR7 ) Special Function Register 7 | |
| #define MATRIX_SFR8 (AT91_CAST(AT91_REG *) 0x00000130) // (MATRIX_SFR8 ) Special Function Register 8 | |
| #define MATRIX_SFR9 (AT91_CAST(AT91_REG *) 0x00000134) // (MATRIX_SFR9 ) Special Function Register 9 | |
| #define MATRIX_SFR10 (AT91_CAST(AT91_REG *) 0x00000138) // (MATRIX_SFR10) Special Function Register 10 | |
| #define MATRIX_SFR11 (AT91_CAST(AT91_REG *) 0x0000013C) // (MATRIX_SFR11) Special Function Register 11 | |
| #define MATRIX_SFR12 (AT91_CAST(AT91_REG *) 0x00000140) // (MATRIX_SFR12) Special Function Register 12 | |
| #define MATRIX_SFR13 (AT91_CAST(AT91_REG *) 0x00000144) // (MATRIX_SFR13) Special Function Register 13 | |
| #define MATRIX_SFR14 (AT91_CAST(AT91_REG *) 0x00000148) // (MATRIX_SFR14) Special Function Register 14 | |
| #define MATRIX_SFR15 (AT91_CAST(AT91_REG *) 0x0000014C) // (MATRIX_SFR15) Special Function Register 15 | |
| #define HMATRIX2_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000001EC) // (HMATRIX2_ADDRSIZE) HMATRIX2 ADDRSIZE REGISTER | |
| #define HMATRIX2_IPNAME1 (AT91_CAST(AT91_REG *) 0x000001F0) // (HMATRIX2_IPNAME1) HMATRIX2 IPNAME1 REGISTER | |
| #define HMATRIX2_IPNAME2 (AT91_CAST(AT91_REG *) 0x000001F4) // (HMATRIX2_IPNAME2) HMATRIX2 IPNAME2 REGISTER | |
| #define HMATRIX2_FEATURES (AT91_CAST(AT91_REG *) 0x000001F8) // (HMATRIX2_FEATURES) HMATRIX2 FEATURES REGISTER | |
| #define HMATRIX2_VER (AT91_CAST(AT91_REG *) 0x000001FC) // (HMATRIX2_VER) HMATRIX2 VERSION REGISTER | |
| #endif | |
| // -------- MATRIX_MCFG0 : (HMATRIX2 Offset: 0x0) Master Configuration Register ARM bus I and D -------- | |
| #define AT91C_MATRIX_ULBT (0x7 << 0) // (HMATRIX2) Undefined Length Burst Type | |
| #define AT91C_MATRIX_ULBT_INFINIT_LENGTH (0x0) // (HMATRIX2) infinite length burst | |
| #define AT91C_MATRIX_ULBT_SINGLE_ACCESS (0x1) // (HMATRIX2) Single Access | |
| #define AT91C_MATRIX_ULBT_4_BEAT (0x2) // (HMATRIX2) 4 Beat Burst | |
| #define AT91C_MATRIX_ULBT_8_BEAT (0x3) // (HMATRIX2) 8 Beat Burst | |
| #define AT91C_MATRIX_ULBT_16_BEAT (0x4) // (HMATRIX2) 16 Beat Burst | |
| #define AT91C_MATRIX_ULBT_32_BEAT (0x5) // (HMATRIX2) 32 Beat Burst | |
| #define AT91C_MATRIX_ULBT_64_BEAT (0x6) // (HMATRIX2) 64 Beat Burst | |
| #define AT91C_MATRIX_ULBT_128_BEAT (0x7) // (HMATRIX2) 128 Beat Burst | |
| // -------- MATRIX_MCFG1 : (HMATRIX2 Offset: 0x4) Master Configuration Register ARM bus S -------- | |
| // -------- MATRIX_MCFG2 : (HMATRIX2 Offset: 0x8) Master Configuration Register -------- | |
| // -------- MATRIX_MCFG3 : (HMATRIX2 Offset: 0xc) Master Configuration Register -------- | |
| // -------- MATRIX_MCFG4 : (HMATRIX2 Offset: 0x10) Master Configuration Register -------- | |
| // -------- MATRIX_MCFG5 : (HMATRIX2 Offset: 0x14) Master Configuration Register -------- | |
| // -------- MATRIX_MCFG6 : (HMATRIX2 Offset: 0x18) Master Configuration Register -------- | |
| // -------- MATRIX_MCFG7 : (HMATRIX2 Offset: 0x1c) Master Configuration Register -------- | |
| // -------- MATRIX_SCFG0 : (HMATRIX2 Offset: 0x40) Slave Configuration Register 0 -------- | |
| #define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (HMATRIX2) Maximum Number of Allowed Cycles for a Burst | |
| #define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (HMATRIX2) Default Master Type | |
| #define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (HMATRIX2) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. | |
| #define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (HMATRIX2) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. | |
| #define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (HMATRIX2) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG1 : (HMATRIX2 Offset: 0x44) Slave Configuration Register 1 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG2 : (HMATRIX2 Offset: 0x48) Slave Configuration Register 2 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG3 : (HMATRIX2 Offset: 0x4c) Slave Configuration Register 3 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC (0x0 << 18) // (HMATRIX2) ARMC is Default Master | |
| // -------- MATRIX_SCFG4 : (HMATRIX2 Offset: 0x50) Slave Configuration Register 4 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG5 : (HMATRIX2 Offset: 0x54) Slave Configuration Register 5 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG6 : (HMATRIX2 Offset: 0x58) Slave Configuration Register 6 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG7 : (HMATRIX2 Offset: 0x5c) Slave Configuration Register 7 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| // -------- MATRIX_SCFG8 : (HMATRIX2 Offset: 0x60) Slave Configuration Register 8 -------- | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master | |
| #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_HDMA (0x4 << 18) // (HMATRIX2) HDMA is Default Master | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x110) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x114) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x118) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x11c) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x120) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x124) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x128) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x12c) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x130) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x134) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x138) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x13c) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x140) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x144) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x148) Special Function Register 0 -------- | |
| // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x14c) Special Function Register 0 -------- | |
| // -------- HMATRIX2_VER : (HMATRIX2 Offset: 0x1fc) VERSION Register -------- | |
| #define AT91C_HMATRIX2_VER (0xF << 0) // (HMATRIX2) VERSION Register | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR NESTED vector Interrupt Controller | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_NVIC { | |
| AT91_REG Reserved0[1]; // | |
| AT91_REG NVIC_ICTR; // Interrupt Control Type Register | |
| AT91_REG Reserved1[2]; // | |
| AT91_REG NVIC_STICKCSR; // SysTick Control and Status Register | |
| AT91_REG NVIC_STICKRVR; // SysTick Reload Value Register | |
| AT91_REG NVIC_STICKCVR; // SysTick Current Value Register | |
| AT91_REG NVIC_STICKCALVR; // SysTick Calibration Value Register | |
| AT91_REG Reserved2[56]; // | |
| AT91_REG NVIC_ISER[8]; // Set Enable Register | |
| AT91_REG Reserved3[24]; // | |
| AT91_REG NVIC_ICER[8]; // Clear enable Register | |
| AT91_REG Reserved4[24]; // | |
| AT91_REG NVIC_ISPR[8]; // Set Pending Register | |
| AT91_REG Reserved5[24]; // | |
| AT91_REG NVIC_ICPR[8]; // Clear Pending Register | |
| AT91_REG Reserved6[24]; // | |
| AT91_REG NVIC_ABR[8]; // Active Bit Register | |
| AT91_REG Reserved7[56]; // | |
| AT91_REG NVIC_IPR[60]; // Interrupt Mask Register | |
| AT91_REG Reserved8[516]; // | |
| AT91_REG NVIC_CPUID; // CPUID Base Register | |
| AT91_REG NVIC_ICSR; // Interrupt Control State Register | |
| AT91_REG NVIC_VTOFFR; // Vector Table Offset Register | |
| AT91_REG NVIC_AIRCR; // Application Interrupt/Reset Control Reg | |
| AT91_REG NVIC_SCR; // System Control Register | |
| AT91_REG NVIC_CCR; // Configuration Control Register | |
| AT91_REG NVIC_HAND4PR; // System Handlers 4-7 Priority Register | |
| AT91_REG NVIC_HAND8PR; // System Handlers 8-11 Priority Register | |
| AT91_REG NVIC_HAND12PR; // System Handlers 12-15 Priority Register | |
| AT91_REG NVIC_HANDCSR; // System Handler Control and State Register | |
| AT91_REG NVIC_CFSR; // Configurable Fault Status Register | |
| AT91_REG NVIC_HFSR; // Hard Fault Status Register | |
| AT91_REG NVIC_DFSR; // Debug Fault Status Register | |
| AT91_REG NVIC_MMAR; // Mem Manage Address Register | |
| AT91_REG NVIC_BFAR; // Bus Fault Address Register | |
| AT91_REG NVIC_AFSR; // Auxiliary Fault Status Register | |
| AT91_REG NVIC_PFR0; // Processor Feature register0 | |
| AT91_REG NVIC_PFR1; // Processor Feature register1 | |
| AT91_REG NVIC_DFR0; // Debug Feature register0 | |
| AT91_REG NVIC_AFR0; // Auxiliary Feature register0 | |
| AT91_REG NVIC_MMFR0; // Memory Model Feature register0 | |
| AT91_REG NVIC_MMFR1; // Memory Model Feature register1 | |
| AT91_REG NVIC_MMFR2; // Memory Model Feature register2 | |
| AT91_REG NVIC_MMFR3; // Memory Model Feature register3 | |
| AT91_REG NVIC_ISAR0; // ISA Feature register0 | |
| AT91_REG NVIC_ISAR1; // ISA Feature register1 | |
| AT91_REG NVIC_ISAR2; // ISA Feature register2 | |
| AT91_REG NVIC_ISAR3; // ISA Feature register3 | |
| AT91_REG NVIC_ISAR4; // ISA Feature register4 | |
| AT91_REG Reserved9[99]; // | |
| AT91_REG NVIC_STIR; // Software Trigger Interrupt Register | |
| AT91_REG Reserved10[51]; // | |
| AT91_REG NVIC_PID4; // Peripheral identification register | |
| AT91_REG NVIC_PID5; // Peripheral identification register | |
| AT91_REG NVIC_PID6; // Peripheral identification register | |
| AT91_REG NVIC_PID7; // Peripheral identification register | |
| AT91_REG NVIC_PID0; // Peripheral identification register b7:0 | |
| AT91_REG NVIC_PID1; // Peripheral identification register b15:8 | |
| AT91_REG NVIC_PID2; // Peripheral identification register b23:16 | |
| AT91_REG NVIC_PID3; // Peripheral identification register b31:24 | |
| AT91_REG NVIC_CID0; // Component identification register b7:0 | |
| AT91_REG NVIC_CID1; // Component identification register b15:8 | |
| AT91_REG NVIC_CID2; // Component identification register b23:16 | |
| AT91_REG NVIC_CID3; // Component identification register b31:24 | |
| } AT91S_NVIC, *AT91PS_NVIC; | |
| #else | |
| #define NVIC_ICTR (AT91_CAST(AT91_REG *) 0x00000004) // (NVIC_ICTR) Interrupt Control Type Register | |
| #define NVIC_STICKCSR (AT91_CAST(AT91_REG *) 0x00000010) // (NVIC_STICKCSR) SysTick Control and Status Register | |
| #define NVIC_STICKRVR (AT91_CAST(AT91_REG *) 0x00000014) // (NVIC_STICKRVR) SysTick Reload Value Register | |
| #define NVIC_STICKCVR (AT91_CAST(AT91_REG *) 0x00000018) // (NVIC_STICKCVR) SysTick Current Value Register | |
| #define NVIC_STICKCALVR (AT91_CAST(AT91_REG *) 0x0000001C) // (NVIC_STICKCALVR) SysTick Calibration Value Register | |
| #define NVIC_ISER (AT91_CAST(AT91_REG *) 0x00000100) // (NVIC_ISER) Set Enable Register | |
| #define NVIC_ICER (AT91_CAST(AT91_REG *) 0x00000180) // (NVIC_ICER) Clear enable Register | |
| #define NVIC_ISPR (AT91_CAST(AT91_REG *) 0x00000200) // (NVIC_ISPR) Set Pending Register | |
| #define NVIC_ICPR (AT91_CAST(AT91_REG *) 0x00000280) // (NVIC_ICPR) Clear Pending Register | |
| #define NVIC_IABR (AT91_CAST(AT91_REG *) 0x00000300) // (NVIC_IABR) Active Bit Register | |
| #define NVIC_IPR (AT91_CAST(AT91_REG *) 0x00000400) // (NVIC_IPR) Interrupt Mask Register | |
| #define NVIC_CPUID (AT91_CAST(AT91_REG *) 0x00000D00) // (NVIC_CPUID) CPUID Base Register | |
| #define NVIC_ICSR (AT91_CAST(AT91_REG *) 0x00000D04) // (NVIC_ICSR) Interrupt Control State Register | |
| #define NVIC_VTOFFR (AT91_CAST(AT91_REG *) 0x00000D08) // (NVIC_VTOFFR) Vector Table Offset Register | |
| #define NVIC_AIRCR (AT91_CAST(AT91_REG *) 0x00000D0C) // (NVIC_AIRCR) Application Interrupt/Reset Control Reg | |
| #define NVIC_SCR (AT91_CAST(AT91_REG *) 0x00000D10) // (NVIC_SCR) System Control Register | |
| #define NVIC_CCR (AT91_CAST(AT91_REG *) 0x00000D14) // (NVIC_CCR) Configuration Control Register | |
| #define NVIC_HAND4PR (AT91_CAST(AT91_REG *) 0x00000D18) // (NVIC_HAND4PR) System Handlers 4-7 Priority Register | |
| #define NVIC_HAND8PR (AT91_CAST(AT91_REG *) 0x00000D1C) // (NVIC_HAND8PR) System Handlers 8-11 Priority Register | |
| #define NVIC_HAND12PR (AT91_CAST(AT91_REG *) 0x00000D20) // (NVIC_HAND12PR) System Handlers 12-15 Priority Register | |
| #define NVIC_HANDCSR (AT91_CAST(AT91_REG *) 0x00000D24) // (NVIC_HANDCSR) System Handler Control and State Register | |
| #define NVIC_CFSR (AT91_CAST(AT91_REG *) 0x00000D28) // (NVIC_CFSR) Configurable Fault Status Register | |
| #define NVIC_HFSR (AT91_CAST(AT91_REG *) 0x00000D2C) // (NVIC_HFSR) Hard Fault Status Register | |
| #define NVIC_DFSR (AT91_CAST(AT91_REG *) 0x00000D30) // (NVIC_DFSR) Debug Fault Status Register | |
| #define NVIC_MMAR (AT91_CAST(AT91_REG *) 0x00000D34) // (NVIC_MMAR) Mem Manage Address Register | |
| #define NVIC_BFAR (AT91_CAST(AT91_REG *) 0x00000D38) // (NVIC_BFAR) Bus Fault Address Register | |
| #define NVIC_AFSR (AT91_CAST(AT91_REG *) 0x00000D3C) // (NVIC_AFSR) Auxiliary Fault Status Register | |
| #define NVIC_PFR0 (AT91_CAST(AT91_REG *) 0x00000D40) // (NVIC_PFR0) Processor Feature register0 | |
| #define NVIC_PFR1 (AT91_CAST(AT91_REG *) 0x00000D44) // (NVIC_PFR1) Processor Feature register1 | |
| #define NVIC_DFR0 (AT91_CAST(AT91_REG *) 0x00000D48) // (NVIC_DFR0) Debug Feature register0 | |
| #define NVIC_AFR0 (AT91_CAST(AT91_REG *) 0x00000D4C) // (NVIC_AFR0) Auxiliary Feature register0 | |
| #define NVIC_MMFR0 (AT91_CAST(AT91_REG *) 0x00000D50) // (NVIC_MMFR0) Memory Model Feature register0 | |
| #define NVIC_MMFR1 (AT91_CAST(AT91_REG *) 0x00000D54) // (NVIC_MMFR1) Memory Model Feature register1 | |
| #define NVIC_MMFR2 (AT91_CAST(AT91_REG *) 0x00000D58) // (NVIC_MMFR2) Memory Model Feature register2 | |
| #define NVIC_MMFR3 (AT91_CAST(AT91_REG *) 0x00000D5C) // (NVIC_MMFR3) Memory Model Feature register3 | |
| #define NVIC_ISAR0 (AT91_CAST(AT91_REG *) 0x00000D60) // (NVIC_ISAR0) ISA Feature register0 | |
| #define NVIC_ISAR1 (AT91_CAST(AT91_REG *) 0x00000D64) // (NVIC_ISAR1) ISA Feature register1 | |
| #define NVIC_ISAR2 (AT91_CAST(AT91_REG *) 0x00000D68) // (NVIC_ISAR2) ISA Feature register2 | |
| #define NVIC_ISAR3 (AT91_CAST(AT91_REG *) 0x00000D6C) // (NVIC_ISAR3) ISA Feature register3 | |
| #define NVIC_ISAR4 (AT91_CAST(AT91_REG *) 0x00000D70) // (NVIC_ISAR4) ISA Feature register4 | |
| #define NVIC_STIR (AT91_CAST(AT91_REG *) 0x00000F00) // (NVIC_STIR) Software Trigger Interrupt Register | |
| #define NVIC_PID4 (AT91_CAST(AT91_REG *) 0x00000FD0) // (NVIC_PID4) Peripheral identification register | |
| #define NVIC_PID5 (AT91_CAST(AT91_REG *) 0x00000FD4) // (NVIC_PID5) Peripheral identification register | |
| #define NVIC_PID6 (AT91_CAST(AT91_REG *) 0x00000FD8) // (NVIC_PID6) Peripheral identification register | |
| #define NVIC_PID7 (AT91_CAST(AT91_REG *) 0x00000FDC) // (NVIC_PID7) Peripheral identification register | |
| #define NVIC_PID0 (AT91_CAST(AT91_REG *) 0x00000FE0) // (NVIC_PID0) Peripheral identification register b7:0 | |
| #define NVIC_PID1 (AT91_CAST(AT91_REG *) 0x00000FE4) // (NVIC_PID1) Peripheral identification register b15:8 | |
| #define NVIC_PID2 (AT91_CAST(AT91_REG *) 0x00000FE8) // (NVIC_PID2) Peripheral identification register b23:16 | |
| #define NVIC_PID3 (AT91_CAST(AT91_REG *) 0x00000FEC) // (NVIC_PID3) Peripheral identification register b31:24 | |
| #define NVIC_CID0 (AT91_CAST(AT91_REG *) 0x00000FF0) // (NVIC_CID0) Component identification register b7:0 | |
| #define NVIC_CID1 (AT91_CAST(AT91_REG *) 0x00000FF4) // (NVIC_CID1) Component identification register b15:8 | |
| #define NVIC_CID2 (AT91_CAST(AT91_REG *) 0x00000FF8) // (NVIC_CID2) Component identification register b23:16 | |
| #define NVIC_CID3 (AT91_CAST(AT91_REG *) 0x00000FFC) // (NVIC_CID3) Component identification register b31:24 | |
| #endif | |
| // -------- NVIC_ICTR : (NVIC Offset: 0x4) Interrupt Controller Type Register -------- | |
| #define AT91C_NVIC_INTLINESNUM (0xF << 0) // (NVIC) Total number of interrupt lines | |
| #define AT91C_NVIC_INTLINESNUM_32 (0x0) // (NVIC) up to 32 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_64 (0x1) // (NVIC) up to 64 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_96 (0x2) // (NVIC) up to 96 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_128 (0x3) // (NVIC) up to 128 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_160 (0x4) // (NVIC) up to 160 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_192 (0x5) // (NVIC) up to 192 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_224 (0x6) // (NVIC) up to 224 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_256 (0x7) // (NVIC) up to 256 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_288 (0x8) // (NVIC) up to 288 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_320 (0x9) // (NVIC) up to 320 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_352 (0xA) // (NVIC) up to 352 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_384 (0xB) // (NVIC) up to 384 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_416 (0xC) // (NVIC) up to 416 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_448 (0xD) // (NVIC) up to 448 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_480 (0xE) // (NVIC) up to 480 interrupt lines supported | |
| #define AT91C_NVIC_INTLINESNUM_496 (0xF) // (NVIC) up to 496 interrupt lines supported) | |
| // -------- NVIC_STICKCSR : (NVIC Offset: 0x10) SysTick Control and Status Register -------- | |
| #define AT91C_NVIC_STICKENABLE (0x1 << 0) // (NVIC) SysTick counter enable. | |
| #define AT91C_NVIC_STICKINT (0x1 << 1) // (NVIC) SysTick interrupt enable. | |
| #define AT91C_NVIC_STICKCLKSOURCE (0x1 << 2) // (NVIC) Reference clock selection. | |
| #define AT91C_NVIC_STICKCOUNTFLAG (0x1 << 16) // (NVIC) Return 1 if timer counted to 0 since last read. | |
| // -------- NVIC_STICKRVR : (NVIC Offset: 0x14) SysTick Reload Value Register -------- | |
| #define AT91C_NVIC_STICKRELOAD (0xFFFFFF << 0) // (NVIC) SysTick reload value. | |
| // -------- NVIC_STICKCVR : (NVIC Offset: 0x18) SysTick Current Value Register -------- | |
| #define AT91C_NVIC_STICKCURRENT (0x7FFFFFFF << 0) // (NVIC) SysTick current value. | |
| // -------- NVIC_STICKCALVR : (NVIC Offset: 0x1c) SysTick Calibration Value Register -------- | |
| #define AT91C_NVIC_STICKTENMS (0xFFFFFF << 0) // (NVIC) Reload value to use for 10ms timing. | |
| #define AT91C_NVIC_STICKSKEW (0x1 << 30) // (NVIC) Read as 1 if the calibration value is not exactly 10ms because of clock frequency. | |
| #define AT91C_NVIC_STICKNOREF (0x1 << 31) // (NVIC) Read as 1 if the reference clock is not provided. | |
| // -------- NVIC_IPR : (NVIC Offset: 0x400) Interrupt Priority Registers -------- | |
| #define AT91C_NVIC_PRI_N (0xFF << 0) // (NVIC) Priority of interrupt N (0, 4, 8, etc) | |
| #define AT91C_NVIC_PRI_N1 (0xFF << 8) // (NVIC) Priority of interrupt N+1 (1, 5, 9, etc) | |
| #define AT91C_NVIC_PRI_N2 (0xFF << 16) // (NVIC) Priority of interrupt N+2 (2, 6, 10, etc) | |
| #define AT91C_NVIC_PRI_N3 (0xFF << 24) // (NVIC) Priority of interrupt N+3 (3, 7, 11, etc) | |
| // -------- NVIC_CPUID : (NVIC Offset: 0xd00) CPU ID Base Register -------- | |
| #define AT91C_NVIC_REVISION (0xF << 0) // (NVIC) Implementation defined revision number. | |
| #define AT91C_NVIC_PARTNO (0xFFF << 4) // (NVIC) Number of processor within family | |
| #define AT91C_NVIC_CONSTANT (0xF << 16) // (NVIC) Reads as 0xF | |
| #define AT91C_NVIC_VARIANT (0xF << 20) // (NVIC) Implementation defined variant number. | |
| #define AT91C_NVIC_IMPLEMENTER (0xFF << 24) // (NVIC) Implementer code. ARM is 0x41 | |
| // -------- NVIC_ICSR : (NVIC Offset: 0xd04) Interrupt Control State Register -------- | |
| #define AT91C_NVIC_VECTACTIVE (0x1FF << 0) // (NVIC) Read-only Active ISR number field | |
| #define AT91C_NVIC_RETTOBASE (0x1 << 11) // (NVIC) Read-only | |
| #define AT91C_NVIC_VECTPENDING (0x1FF << 12) // (NVIC) Read-only Pending ISR number field | |
| #define AT91C_NVIC_ISRPENDING (0x1 << 22) // (NVIC) Read-only Interrupt pending flag. | |
| #define AT91C_NVIC_ISRPREEMPT (0x1 << 23) // (NVIC) Read-only You must only use this at debug time | |
| #define AT91C_NVIC_PENDSTCLR (0x1 << 25) // (NVIC) Write-only Clear pending SysTick bit | |
| #define AT91C_NVIC_PENDSTSET (0x1 << 26) // (NVIC) Read/write Set a pending SysTick bit | |
| #define AT91C_NVIC_PENDSVCLR (0x1 << 27) // (NVIC) Write-only Clear pending pendSV bit | |
| #define AT91C_NVIC_PENDSVSET (0x1 << 28) // (NVIC) Read/write Set pending pendSV bit | |
| #define AT91C_NVIC_NMIPENDSET (0x1 << 31) // (NVIC) Read/write Set pending NMI | |
| // -------- NVIC_VTOFFR : (NVIC Offset: 0xd08) Vector Table Offset Register -------- | |
| #define AT91C_NVIC_TBLOFF (0x3FFFFF << 7) // (NVIC) Vector table base offset field | |
| #define AT91C_NVIC_TBLBASE (0x1 << 29) // (NVIC) Table base is in Code (0) or RAM (1) | |
| #define AT91C_NVIC_TBLBASE_CODE (0x0 << 29) // (NVIC) Table base is in CODE | |
| #define AT91C_NVIC_TBLBASE_RAM (0x1 << 29) // (NVIC) Table base is in RAM | |
| // -------- NVIC_AIRCR : (NVIC Offset: 0xd0c) Application Interrupt and Reset Control Register -------- | |
| #define AT91C_NVIC_VECTRESET (0x1 << 0) // (NVIC) System Reset bit | |
| #define AT91C_NVIC_VECTCLRACTIVE (0x1 << 1) // (NVIC) Clear active vector bit | |
| #define AT91C_NVIC_SYSRESETREQ (0x1 << 2) // (NVIC) Causes a signal to be asserted to the outer system that indicates a reset is requested | |
| #define AT91C_NVIC_PRIGROUP (0x7 << 8) // (NVIC) Interrupt priority grouping field | |
| #define AT91C_NVIC_PRIGROUP_0 (0x0 << 8) // (NVIC) indicates seven bits of pre-emption priority, one bit of subpriority | |
| #define AT91C_NVIC_PRIGROUP_1 (0x1 << 8) // (NVIC) indicates six bits of pre-emption priority, two bits of subpriority | |
| #define AT91C_NVIC_PRIGROUP_2 (0x2 << 8) // (NVIC) indicates five bits of pre-emption priority, three bits of subpriority | |
| #define AT91C_NVIC_PRIGROUP_3 (0x3 << 8) // (NVIC) indicates four bits of pre-emption priority, four bits of subpriority | |
| #define AT91C_NVIC_PRIGROUP_4 (0x4 << 8) // (NVIC) indicates three bits of pre-emption priority, five bits of subpriority | |
| #define AT91C_NVIC_PRIGROUP_5 (0x5 << 8) // (NVIC) indicates two bits of pre-emption priority, six bits of subpriority | |
| #define AT91C_NVIC_PRIGROUP_6 (0x6 << 8) // (NVIC) indicates one bit of pre-emption priority, seven bits of subpriority | |
| #define AT91C_NVIC_PRIGROUP_7 (0x7 << 8) // (NVIC) indicates no pre-emption priority, eight bits of subpriority | |
| #define AT91C_NVIC_ENDIANESS (0x1 << 15) // (NVIC) Data endianness bit | |
| #define AT91C_NVIC_VECTKEY (0xFFFF << 16) // (NVIC) Register key | |
| // -------- NVIC_SCR : (NVIC Offset: 0xd10) System Control Register -------- | |
| #define AT91C_NVIC_SLEEPONEXIT (0x1 << 1) // (NVIC) Sleep on exit when returning from Handler mode to Thread mode | |
| #define AT91C_NVIC_SLEEPDEEP (0x1 << 2) // (NVIC) Sleep deep bit | |
| #define AT91C_NVIC_SEVONPEND (0x1 << 4) // (NVIC) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended | |
| // -------- NVIC_CCR : (NVIC Offset: 0xd14) Configuration Control Register -------- | |
| #define AT91C_NVIC_NONEBASETHRDENA (0x1 << 0) // (NVIC) When 0, default, It is only possible to enter Thread mode when returning from the last exception | |
| #define AT91C_NVIC_USERSETMPEND (0x1 << 1) // (NVIC) | |
| #define AT91C_NVIC_UNALIGN_TRP (0x1 << 3) // (NVIC) Trap for unaligned access | |
| #define AT91C_NVIC_DIV_0_TRP (0x1 << 4) // (NVIC) Trap on Divide by 0 | |
| #define AT91C_NVIC_BFHFNMIGN (0x1 << 8) // (NVIC) | |
| #define AT91C_NVIC_STKALIGN (0x1 << 9) // (NVIC) | |
| // -------- NVIC_HAND4PR : (NVIC Offset: 0xd18) System Handlers 4-7 Priority Register -------- | |
| #define AT91C_NVIC_PRI_4 (0xFF << 0) // (NVIC) | |
| #define AT91C_NVIC_PRI_5 (0xFF << 8) // (NVIC) | |
| #define AT91C_NVIC_PRI_6 (0xFF << 16) // (NVIC) | |
| #define AT91C_NVIC_PRI_7 (0xFF << 24) // (NVIC) | |
| // -------- NVIC_HAND8PR : (NVIC Offset: 0xd1c) System Handlers 8-11 Priority Register -------- | |
| #define AT91C_NVIC_PRI_8 (0xFF << 0) // (NVIC) | |
| #define AT91C_NVIC_PRI_9 (0xFF << 8) // (NVIC) | |
| #define AT91C_NVIC_PRI_10 (0xFF << 16) // (NVIC) | |
| #define AT91C_NVIC_PRI_11 (0xFF << 24) // (NVIC) | |
| // -------- NVIC_HAND12PR : (NVIC Offset: 0xd20) System Handlers 12-15 Priority Register -------- | |
| #define AT91C_NVIC_PRI_12 (0xFF << 0) // (NVIC) | |
| #define AT91C_NVIC_PRI_13 (0xFF << 8) // (NVIC) | |
| #define AT91C_NVIC_PRI_14 (0xFF << 16) // (NVIC) | |
| #define AT91C_NVIC_PRI_15 (0xFF << 24) // (NVIC) | |
| // -------- NVIC_HANDCSR : (NVIC Offset: 0xd24) System Handler Control and State Register -------- | |
| #define AT91C_NVIC_MEMFAULTACT (0x1 << 0) // (NVIC) | |
| #define AT91C_NVIC_BUSFAULTACT (0x1 << 1) // (NVIC) | |
| #define AT91C_NVIC_USGFAULTACT (0x1 << 3) // (NVIC) | |
| #define AT91C_NVIC_SVCALLACT (0x1 << 7) // (NVIC) | |
| #define AT91C_NVIC_MONITORACT (0x1 << 8) // (NVIC) | |
| #define AT91C_NVIC_PENDSVACT (0x1 << 10) // (NVIC) | |
| #define AT91C_NVIC_SYSTICKACT (0x1 << 11) // (NVIC) | |
| #define AT91C_NVIC_USGFAULTPENDED (0x1 << 12) // (NVIC) | |
| #define AT91C_NVIC_MEMFAULTPENDED (0x1 << 13) // (NVIC) | |
| #define AT91C_NVIC_BUSFAULTPENDED (0x1 << 14) // (NVIC) | |
| #define AT91C_NVIC_SVCALLPENDED (0x1 << 15) // (NVIC) | |
| #define AT91C_NVIC_MEMFAULTENA (0x1 << 16) // (NVIC) | |
| #define AT91C_NVIC_BUSFAULTENA (0x1 << 17) // (NVIC) | |
| #define AT91C_NVIC_USGFAULTENA (0x1 << 18) // (NVIC) | |
| // -------- NVIC_CFSR : (NVIC Offset: 0xd28) Configurable Fault Status Registers -------- | |
| #define AT91C_NVIC_MEMMANAGE (0xFF << 0) // (NVIC) | |
| #define AT91C_NVIC_BUSFAULT (0xFF << 8) // (NVIC) | |
| #define AT91C_NVIC_USAGEFAULT (0xFF << 16) // (NVIC) | |
| // -------- NVIC_BFAR : (NVIC Offset: 0xd38) Bus Fault Address Register -------- | |
| #define AT91C_NVIC_IBUSERR (0x1 << 0) // (NVIC) This bit indicates a bus fault on an instruction prefetch | |
| #define AT91C_NVIC_PRECISERR (0x1 << 1) // (NVIC) Precise data access error. The BFAR is written with the faulting address | |
| #define AT91C_NVIC_IMPRECISERR (0x1 << 2) // (NVIC) Imprecise data access error | |
| #define AT91C_NVIC_UNSTKERR (0x1 << 3) // (NVIC) This bit indicates a derived bus fault has occurred on exception return | |
| #define AT91C_NVIC_STKERR (0x1 << 4) // (NVIC) This bit indicates a derived bus fault has occurred on exception entry | |
| #define AT91C_NVIC_BFARVALID (0x1 << 7) // (NVIC) This bit is set if the BFAR register has valid contents | |
| // -------- NVIC_PFR0 : (NVIC Offset: 0xd40) Processor Feature register0 (ID_PFR0) -------- | |
| #define AT91C_NVIC_ID_PFR0_0 (0xF << 0) // (NVIC) State0 (T-bit == 0) | |
| #define AT91C_NVIC_ID_PRF0_1 (0xF << 4) // (NVIC) State1 (T-bit == 1) | |
| // -------- NVIC_PFR1 : (NVIC Offset: 0xd44) Processor Feature register1 (ID_PFR1) -------- | |
| #define AT91C_NVIC_ID_PRF1_MODEL (0xF << 8) // (NVIC) Microcontroller programmerÂ’s model | |
| // -------- NVIC_DFR0 : (NVIC Offset: 0xd48) Debug Feature register0 (ID_DFR0) -------- | |
| #define AT91C_NVIC_ID_DFR0_MODEL (0xF << 20) // (NVIC) Microcontroller Debug Model – memory mapped | |
| // -------- NVIC_MMFR0 : (NVIC Offset: 0xd50) Memory Model Feature register0 (ID_MMFR0) -------- | |
| #define AT91C_NVIC_ID_MMFR0_PMSA (0xF << 4) // (NVIC) Microcontroller Debug Model – memory mapped | |
| #define AT91C_NVIC_ID_MMFR0_CACHE (0xF << 8) // (NVIC) Microcontroller Debug Model – memory mapped | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR NESTED vector Interrupt Controller | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_MPU { | |
| AT91_REG MPU_TYPE; // MPU Type Register | |
| AT91_REG MPU_CTRL; // MPU Control Register | |
| AT91_REG MPU_REG_NB; // MPU Region Number Register | |
| AT91_REG MPU_REG_BASE_ADDR; // MPU Region Base Address Register | |
| AT91_REG MPU_ATTR_SIZE; // MPU Attribute and Size Register | |
| AT91_REG MPU_REG_BASE_ADDR1; // MPU Region Base Address Register alias 1 | |
| AT91_REG MPU_ATTR_SIZE1; // MPU Attribute and Size Register alias 1 | |
| AT91_REG MPU_REG_BASE_ADDR2; // MPU Region Base Address Register alias 2 | |
| AT91_REG MPU_ATTR_SIZE2; // MPU Attribute and Size Register alias 2 | |
| AT91_REG MPU_REG_BASE_ADDR3; // MPU Region Base Address Register alias 3 | |
| AT91_REG MPU_ATTR_SIZE3; // MPU Attribute and Size Register alias 3 | |
| } AT91S_MPU, *AT91PS_MPU; | |
| #else | |
| #define MPU_TYPE (AT91_CAST(AT91_REG *) 0x00000000) // (MPU_TYPE) MPU Type Register | |
| #define MPU_CTRL (AT91_CAST(AT91_REG *) 0x00000004) // (MPU_CTRL) MPU Control Register | |
| #define MPU_REG_NB (AT91_CAST(AT91_REG *) 0x00000008) // (MPU_REG_NB) MPU Region Number Register | |
| #define MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *) 0x0000000C) // (MPU_REG_BASE_ADDR) MPU Region Base Address Register | |
| #define MPU_ATTR_SIZE (AT91_CAST(AT91_REG *) 0x00000010) // (MPU_ATTR_SIZE) MPU Attribute and Size Register | |
| #define MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *) 0x00000014) // (MPU_REG_BASE_ADDR1) MPU Region Base Address Register alias 1 | |
| #define MPU_ATTR_SIZE1 (AT91_CAST(AT91_REG *) 0x00000018) // (MPU_ATTR_SIZE1) MPU Attribute and Size Register alias 1 | |
| #define MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *) 0x0000001C) // (MPU_REG_BASE_ADDR2) MPU Region Base Address Register alias 2 | |
| #define MPU_ATTR_SIZE2 (AT91_CAST(AT91_REG *) 0x00000020) // (MPU_ATTR_SIZE2) MPU Attribute and Size Register alias 2 | |
| #define MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *) 0x00000024) // (MPU_REG_BASE_ADDR3) MPU Region Base Address Register alias 3 | |
| #define MPU_ATTR_SIZE3 (AT91_CAST(AT91_REG *) 0x00000028) // (MPU_ATTR_SIZE3) MPU Attribute and Size Register alias 3 | |
| #endif | |
| // -------- MPU_TYPE : (MPU Offset: 0x0) -------- | |
| #define AT91C_MPU_SEPARATE (0x1 << 0) // (MPU) | |
| #define AT91C_MPU_DREGION (0xFF << 8) // (MPU) | |
| #define AT91C_MPU_IREGION (0xFF << 16) // (MPU) | |
| // -------- MPU_CTRL : (MPU Offset: 0x4) -------- | |
| #define AT91C_MPU_ENABLE (0x1 << 0) // (MPU) | |
| #define AT91C_MPU_HFNMIENA (0x1 << 1) // (MPU) | |
| #define AT91C_MPU_PRIVDEFENA (0x1 << 2) // (MPU) | |
| // -------- MPU_REG_NB : (MPU Offset: 0x8) -------- | |
| #define AT91C_MPU_REGION (0xFF << 0) // (MPU) | |
| // -------- MPU_REG_BASE_ADDR : (MPU Offset: 0xc) -------- | |
| #define AT91C_MPU_REG (0xF << 0) // (MPU) | |
| #define AT91C_MPU_VALID (0x1 << 4) // (MPU) | |
| #define AT91C_MPU_ADDR (0x3FFFFFF << 5) // (MPU) | |
| // -------- MPU_ATTR_SIZE : (MPU Offset: 0x10) -------- | |
| #define AT91C_MPU_ENA (0x1 << 0) // (MPU) | |
| #define AT91C_MPU_SIZE (0xF << 1) // (MPU) | |
| #define AT91C_MPU_SRD (0xFF << 8) // (MPU) | |
| #define AT91C_MPU_B (0x1 << 16) // (MPU) | |
| #define AT91C_MPU_C (0x1 << 17) // (MPU) | |
| #define AT91C_MPU_S (0x1 << 18) // (MPU) | |
| #define AT91C_MPU_TEX (0x7 << 19) // (MPU) | |
| #define AT91C_MPU_AP (0x7 << 24) // (MPU) | |
| #define AT91C_MPU_XN (0x7 << 28) // (MPU) | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR CORTEX_M3 Registers | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_CM3 { | |
| AT91_REG CM3_CPUID; // CPU ID Base Register | |
| AT91_REG CM3_ICSR; // Interrupt Control State Register | |
| AT91_REG CM3_VTOR; // Vector Table Offset Register | |
| AT91_REG CM3_AIRCR; // Application Interrupt and Reset Control Register | |
| AT91_REG CM3_SCR; // System Controller Register | |
| AT91_REG CM3_CCR; // Configuration Control Register | |
| AT91_REG CM3_SHPR[3]; // System Handler Priority Register | |
| AT91_REG CM3_SHCSR; // System Handler Control and State Register | |
| } AT91S_CM3, *AT91PS_CM3; | |
| #else | |
| #define CM3_CPUID (AT91_CAST(AT91_REG *) 0x00000000) // (CM3_CPUID) CPU ID Base Register | |
| #define CM3_ICSR (AT91_CAST(AT91_REG *) 0x00000004) // (CM3_ICSR) Interrupt Control State Register | |
| #define CM3_VTOR (AT91_CAST(AT91_REG *) 0x00000008) // (CM3_VTOR) Vector Table Offset Register | |
| #define CM3_AIRCR (AT91_CAST(AT91_REG *) 0x0000000C) // (CM3_AIRCR) Application Interrupt and Reset Control Register | |
| #define CM3_SCR (AT91_CAST(AT91_REG *) 0x00000010) // (CM3_SCR) System Controller Register | |
| #define CM3_CCR (AT91_CAST(AT91_REG *) 0x00000014) // (CM3_CCR) Configuration Control Register | |
| #define CM3_SHPR (AT91_CAST(AT91_REG *) 0x00000018) // (CM3_SHPR) System Handler Priority Register | |
| #define CM3_SHCSR (AT91_CAST(AT91_REG *) 0x00000024) // (CM3_SHCSR) System Handler Control and State Register | |
| #endif | |
| // -------- CM3_CPUID : (CM3 Offset: 0x0) -------- | |
| // -------- CM3_AIRCR : (CM3 Offset: 0xc) -------- | |
| #define AT91C_CM3_SYSRESETREQ (0x1 << 2) // (CM3) A reset is requested by the processor. | |
| // -------- CM3_SCR : (CM3 Offset: 0x10) -------- | |
| #define AT91C_CM3_SLEEPONEXIT (0x1 << 1) // (CM3) Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. | |
| #define AT91C_CM3_SLEEPDEEP (0x1 << 2) // (CM3) Sleep deep bit. | |
| #define AT91C_CM3_SEVONPEND (0x1 << 4) // (CM3) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. | |
| // -------- CM3_SHCSR : (CM3 Offset: 0x24) -------- | |
| #define AT91C_CM3_SYSTICKACT (0x1 << 11) // (CM3) Reads as 1 if SysTick is active. | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Peripheral DMA Controller | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_PDC { | |
| AT91_REG PDC_RPR; // Receive Pointer Register | |
| AT91_REG PDC_RCR; // Receive Counter Register | |
| AT91_REG PDC_TPR; // Transmit Pointer Register | |
| AT91_REG PDC_TCR; // Transmit Counter Register | |
| AT91_REG PDC_RNPR; // Receive Next Pointer Register | |
| AT91_REG PDC_RNCR; // Receive Next Counter Register | |
| AT91_REG PDC_TNPR; // Transmit Next Pointer Register | |
| AT91_REG PDC_TNCR; // Transmit Next Counter Register | |
| AT91_REG PDC_PTCR; // PDC Transfer Control Register | |
| AT91_REG PDC_PTSR; // PDC Transfer Status Register | |
| } AT91S_PDC, *AT91PS_PDC; | |
| #else | |
| #define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register | |
| #define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register | |
| #define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register | |
| #define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register | |
| #define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register | |
| #define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register | |
| #define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register | |
| #define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register | |
| #define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register | |
| #define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register | |
| #endif | |
| // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- | |
| #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable | |
| #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable | |
| #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable | |
| #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable | |
| // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Debug Unit | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_DBGU { | |
| AT91_REG DBGU_CR; // Control Register | |
| AT91_REG DBGU_MR; // Mode Register | |
| AT91_REG DBGU_IER; // Interrupt Enable Register | |
| AT91_REG DBGU_IDR; // Interrupt Disable Register | |
| AT91_REG DBGU_IMR; // Interrupt Mask Register | |
| AT91_REG DBGU_CSR; // Channel Status Register | |
| AT91_REG DBGU_RHR; // Receiver Holding Register | |
| AT91_REG DBGU_THR; // Transmitter Holding Register | |
| AT91_REG DBGU_BRGR; // Baud Rate Generator Register | |
| AT91_REG Reserved0[9]; // | |
| AT91_REG DBGU_FNTR; // Force NTRST Register | |
| AT91_REG Reserved1[40]; // | |
| AT91_REG DBGU_ADDRSIZE; // DBGU ADDRSIZE REGISTER | |
| AT91_REG DBGU_IPNAME1; // DBGU IPNAME1 REGISTER | |
| AT91_REG DBGU_IPNAME2; // DBGU IPNAME2 REGISTER | |
| AT91_REG DBGU_FEATURES; // DBGU FEATURES REGISTER | |
| AT91_REG DBGU_VER; // DBGU VERSION REGISTER | |
| AT91_REG DBGU_RPR; // Receive Pointer Register | |
| AT91_REG DBGU_RCR; // Receive Counter Register | |
| AT91_REG DBGU_TPR; // Transmit Pointer Register | |
| AT91_REG DBGU_TCR; // Transmit Counter Register | |
| AT91_REG DBGU_RNPR; // Receive Next Pointer Register | |
| AT91_REG DBGU_RNCR; // Receive Next Counter Register | |
| AT91_REG DBGU_TNPR; // Transmit Next Pointer Register | |
| AT91_REG DBGU_TNCR; // Transmit Next Counter Register | |
| AT91_REG DBGU_PTCR; // PDC Transfer Control Register | |
| AT91_REG DBGU_PTSR; // PDC Transfer Status Register | |
| AT91_REG Reserved2[6]; // | |
| AT91_REG DBGU_CIDR; // Chip ID Register | |
| AT91_REG DBGU_EXID; // Chip ID Extension Register | |
| } AT91S_DBGU, *AT91PS_DBGU; | |
| #else | |
| #define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register | |
| #define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register | |
| #define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register | |
| #define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register | |
| #define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register | |
| #define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register | |
| #define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register | |
| #define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register | |
| #define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register | |
| #define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register | |
| #define DBGU_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (DBGU_ADDRSIZE) DBGU ADDRSIZE REGISTER | |
| #define DBGU_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (DBGU_IPNAME1) DBGU IPNAME1 REGISTER | |
| #define DBGU_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (DBGU_IPNAME2) DBGU IPNAME2 REGISTER | |
| #define DBGU_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (DBGU_FEATURES) DBGU FEATURES REGISTER | |
| #define DBGU_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (DBGU_VER) DBGU VERSION REGISTER | |
| #define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000140) // (DBGU_CIDR) Chip ID Register | |
| #define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000144) // (DBGU_EXID) Chip ID Extension Register | |
| #endif | |
| // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- | |
| #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver | |
| #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter | |
| #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable | |
| #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable | |
| #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable | |
| #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable | |
| #define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits | |
| // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- | |
| #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type | |
| #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity | |
| #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity | |
| #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) | |
| #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) | |
| #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity | |
| #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode | |
| #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode | |
| #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. | |
| #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. | |
| #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. | |
| #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. | |
| // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- | |
| #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt | |
| #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt | |
| #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt | |
| #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt | |
| #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt | |
| #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt | |
| #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt | |
| #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt | |
| #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt | |
| #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt | |
| #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt | |
| #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt | |
| // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- | |
| // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- | |
| // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- | |
| // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- | |
| #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Parallel Input Output Controler | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_PIO { | |
| AT91_REG PIO_PER; // PIO Enable Register | |
| AT91_REG PIO_PDR; // PIO Disable Register | |
| AT91_REG PIO_PSR; // PIO Status Register | |
| AT91_REG Reserved0[1]; // | |
| AT91_REG PIO_OER; // Output Enable Register | |
| AT91_REG PIO_ODR; // Output Disable Registerr | |
| AT91_REG PIO_OSR; // Output Status Register | |
| AT91_REG Reserved1[1]; // | |
| AT91_REG PIO_IFER; // Input Filter Enable Register | |
| AT91_REG PIO_IFDR; // Input Filter Disable Register | |
| AT91_REG PIO_IFSR; // Input Filter Status Register | |
| AT91_REG Reserved2[1]; // | |
| AT91_REG PIO_SODR; // Set Output Data Register | |
| AT91_REG PIO_CODR; // Clear Output Data Register | |
| AT91_REG PIO_ODSR; // Output Data Status Register | |
| AT91_REG PIO_PDSR; // Pin Data Status Register | |
| AT91_REG PIO_IER; // Interrupt Enable Register | |
| AT91_REG PIO_IDR; // Interrupt Disable Register | |
| AT91_REG PIO_IMR; // Interrupt Mask Register | |
| AT91_REG PIO_ISR; // Interrupt Status Register | |
| AT91_REG PIO_MDER; // Multi-driver Enable Register | |
| AT91_REG PIO_MDDR; // Multi-driver Disable Register | |
| AT91_REG PIO_MDSR; // Multi-driver Status Register | |
| AT91_REG Reserved3[1]; // | |
| AT91_REG PIO_PPUDR; // Pull-up Disable Register | |
| AT91_REG PIO_PPUER; // Pull-up Enable Register | |
| AT91_REG PIO_PPUSR; // Pull-up Status Register | |
| AT91_REG Reserved4[1]; // | |
| AT91_REG PIO_ABSR; // Peripheral AB Select Register | |
| AT91_REG Reserved5[3]; // | |
| AT91_REG PIO_SCIFSR; // System Clock Glitch Input Filter Select Register | |
| AT91_REG PIO_DIFSR; // Debouncing Input Filter Select Register | |
| AT91_REG PIO_IFDGSR; // Glitch or Debouncing Input Filter Clock Selection Status Register | |
| AT91_REG PIO_SCDR; // Slow Clock Divider Debouncing Register | |
| AT91_REG Reserved6[4]; // | |
| AT91_REG PIO_OWER; // Output Write Enable Register | |
| AT91_REG PIO_OWDR; // Output Write Disable Register | |
| AT91_REG PIO_OWSR; // Output Write Status Register | |
| AT91_REG Reserved7[1]; // | |
| AT91_REG PIO_AIMER; // Additional Interrupt Modes Enable Register | |
| AT91_REG PIO_AIMDR; // Additional Interrupt Modes Disables Register | |
| AT91_REG PIO_AIMMR; // Additional Interrupt Modes Mask Register | |
| AT91_REG Reserved8[1]; // | |
| AT91_REG PIO_ESR; // Edge Select Register | |
| AT91_REG PIO_LSR; // Level Select Register | |
| AT91_REG PIO_ELSR; // Edge/Level Status Register | |
| AT91_REG Reserved9[1]; // | |
| AT91_REG PIO_FELLSR; // Falling Edge/Low Level Select Register | |
| AT91_REG PIO_REHLSR; // Rising Edge/ High Level Select Register | |
| AT91_REG PIO_FRLHSR; // Fall/Rise - Low/High Status Register | |
| AT91_REG Reserved10[1]; // | |
| AT91_REG PIO_LOCKSR; // Lock Status Register | |
| AT91_REG Reserved11[6]; // | |
| AT91_REG PIO_VER; // PIO VERSION REGISTER | |
| AT91_REG Reserved12[8]; // | |
| AT91_REG PIO_KER; // Keypad Controller Enable Register | |
| AT91_REG PIO_KRCR; // Keypad Controller Row Column Register | |
| AT91_REG PIO_KDR; // Keypad Controller Debouncing Register | |
| AT91_REG Reserved13[1]; // | |
| AT91_REG PIO_KIER; // Keypad Controller Interrupt Enable Register | |
| AT91_REG PIO_KIDR; // Keypad Controller Interrupt Disable Register | |
| AT91_REG PIO_KIMR; // Keypad Controller Interrupt Mask Register | |
| AT91_REG PIO_KSR; // Keypad Controller Status Register | |
| AT91_REG PIO_KKPR; // Keypad Controller Key Press Register | |
| AT91_REG PIO_KKRR; // Keypad Controller Key Release Register | |
| } AT91S_PIO, *AT91PS_PIO; | |
| #else | |
| #define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register | |
| #define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register | |
| #define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register | |
| #define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register | |
| #define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr | |
| #define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register | |
| #define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register | |
| #define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register | |
| #define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register | |
| #define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register | |
| #define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register | |
| #define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register | |
| #define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register | |
| #define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register | |
| #define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register | |
| #define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register | |
| #define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register | |
| #define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register | |
| #define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register | |
| #define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register | |
| #define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register | |
| #define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register | |
| #define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register | |
| #define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ABSR) Peripheral AB Select Register | |
| #define PIO_SCIFSR (AT91_CAST(AT91_REG *) 0x00000080) // (PIO_SCIFSR) System Clock Glitch Input Filter Select Register | |
| #define PIO_DIFSR (AT91_CAST(AT91_REG *) 0x00000084) // (PIO_DIFSR) Debouncing Input Filter Select Register | |
| #define PIO_IFDGSR (AT91_CAST(AT91_REG *) 0x00000088) // (PIO_IFDGSR) Glitch or Debouncing Input Filter Clock Selection Status Register | |
| #define PIO_SCDR (AT91_CAST(AT91_REG *) 0x0000008C) // (PIO_SCDR) Slow Clock Divider Debouncing Register | |
| #define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register | |
| #define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register | |
| #define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register | |
| #define PIO_AIMER (AT91_CAST(AT91_REG *) 0x000000B0) // (PIO_AIMER) Additional Interrupt Modes Enable Register | |
| #define PIO_AIMDR (AT91_CAST(AT91_REG *) 0x000000B4) // (PIO_AIMDR) Additional Interrupt Modes Disables Register | |
| #define PIO_AIMMR (AT91_CAST(AT91_REG *) 0x000000B8) // (PIO_AIMMR) Additional Interrupt Modes Mask Register | |
| #define PIO_ESR (AT91_CAST(AT91_REG *) 0x000000C0) // (PIO_ESR) Edge Select Register | |
| #define PIO_LSR (AT91_CAST(AT91_REG *) 0x000000C4) // (PIO_LSR) Level Select Register | |
| #define PIO_ELSR (AT91_CAST(AT91_REG *) 0x000000C8) // (PIO_ELSR) Edge/Level Status Register | |
| #define PIO_FELLSR (AT91_CAST(AT91_REG *) 0x000000D0) // (PIO_FELLSR) Falling Edge/Low Level Select Register | |
| #define PIO_REHLSR (AT91_CAST(AT91_REG *) 0x000000D4) // (PIO_REHLSR) Rising Edge/ High Level Select Register | |
| #define PIO_FRLHSR (AT91_CAST(AT91_REG *) 0x000000D8) // (PIO_FRLHSR) Fall/Rise - Low/High Status Register | |
| #define PIO_LOCKSR (AT91_CAST(AT91_REG *) 0x000000E0) // (PIO_LOCKSR) Lock Status Register | |
| #define PIO_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (PIO_VER) PIO VERSION REGISTER | |
| #define PIO_KER (AT91_CAST(AT91_REG *) 0x00000120) // (PIO_KER) Keypad Controller Enable Register | |
| #define PIO_KRCR (AT91_CAST(AT91_REG *) 0x00000124) // (PIO_KRCR) Keypad Controller Row Column Register | |
| #define PIO_KDR (AT91_CAST(AT91_REG *) 0x00000128) // (PIO_KDR) Keypad Controller Debouncing Register | |
| #define PIO_KIER (AT91_CAST(AT91_REG *) 0x00000130) // (PIO_KIER) Keypad Controller Interrupt Enable Register | |
| #define PIO_KIDR (AT91_CAST(AT91_REG *) 0x00000134) // (PIO_KIDR) Keypad Controller Interrupt Disable Register | |
| #define PIO_KIMR (AT91_CAST(AT91_REG *) 0x00000138) // (PIO_KIMR) Keypad Controller Interrupt Mask Register | |
| #define PIO_KSR (AT91_CAST(AT91_REG *) 0x0000013C) // (PIO_KSR) Keypad Controller Status Register | |
| #define PIO_KKPR (AT91_CAST(AT91_REG *) 0x00000140) // (PIO_KKPR) Keypad Controller Key Press Register | |
| #define PIO_KKRR (AT91_CAST(AT91_REG *) 0x00000144) // (PIO_KKRR) Keypad Controller Key Release Register | |
| #endif | |
| // -------- PIO_KER : (PIO Offset: 0x120) Keypad Controller Enable Register -------- | |
| #define AT91C_PIO_KCE (0x1 << 0) // (PIO) Keypad Controller Enable | |
| // -------- PIO_KRCR : (PIO Offset: 0x124) Keypad Controller Row Column Register -------- | |
| #define AT91C_PIO_NBR (0x7 << 0) // (PIO) Number of Columns of the Keypad Matrix | |
| #define AT91C_PIO_NBC (0x7 << 8) // (PIO) Number of Rows of the Keypad Matrix | |
| // -------- PIO_KDR : (PIO Offset: 0x128) Keypad Controller Debouncing Register -------- | |
| #define AT91C_PIO_DBC (0x3FF << 0) // (PIO) Debouncing Value | |
| // -------- PIO_KIER : (PIO Offset: 0x130) Keypad Controller Interrupt Enable Register -------- | |
| #define AT91C_PIO_KPR (0x1 << 0) // (PIO) Key Press Interrupt Enable | |
| #define AT91C_PIO_KRL (0x1 << 1) // (PIO) Key Release Interrupt Enable | |
| // -------- PIO_KIDR : (PIO Offset: 0x134) Keypad Controller Interrupt Disable Register -------- | |
| // -------- PIO_KIMR : (PIO Offset: 0x138) Keypad Controller Interrupt Mask Register -------- | |
| // -------- PIO_KSR : (PIO Offset: 0x13c) Keypad Controller Status Register -------- | |
| #define AT91C_PIO_NBKPR (0x3 << 8) // (PIO) Number of Simultaneous Key Presses | |
| #define AT91C_PIO_NBKRL (0x3 << 16) // (PIO) Number of Simultaneous Key Releases | |
| // -------- PIO_KKPR : (PIO Offset: 0x140) Keypad Controller Key Press Register -------- | |
| #define AT91C_KEY0ROW (0x7 << 0) // (PIO) Row index of the first detected Key Press | |
| #define AT91C_KEY0COL (0x7 << 4) // (PIO) Column index of the first detected Key Press | |
| #define AT91C_KEY1ROW (0x7 << 8) // (PIO) Row index of the second detected Key Press | |
| #define AT91C_KEY1COL (0x7 << 12) // (PIO) Column index of the second detected Key Press | |
| #define AT91C_KEY2ROW (0x7 << 16) // (PIO) Row index of the third detected Key Press | |
| #define AT91C_KEY2COL (0x7 << 20) // (PIO) Column index of the third detected Key Press | |
| #define AT91C_KEY3ROW (0x7 << 24) // (PIO) Row index of the fourth detected Key Press | |
| #define AT91C_KEY3COL (0x7 << 28) // (PIO) Column index of the fourth detected Key Press | |
| // -------- PIO_KKRR : (PIO Offset: 0x144) Keypad Controller Key Release Register -------- | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Power Management Controler | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_PMC { | |
| AT91_REG PMC_SCER; // System Clock Enable Register | |
| AT91_REG PMC_SCDR; // System Clock Disable Register | |
| AT91_REG PMC_SCSR; // System Clock Status Register | |
| AT91_REG Reserved0[1]; // | |
| AT91_REG PMC_PCER; // Peripheral Clock Enable Register | |
| AT91_REG PMC_PCDR; // Peripheral Clock Disable Register | |
| AT91_REG PMC_PCSR; // Peripheral Clock Status Register | |
| AT91_REG PMC_UCKR; // UTMI Clock Configuration Register | |
| AT91_REG PMC_MOR; // Main Oscillator Register | |
| AT91_REG PMC_MCFR; // Main Clock Frequency Register | |
| AT91_REG PMC_PLLAR; // PLL Register | |
| AT91_REG Reserved1[1]; // | |
| AT91_REG PMC_MCKR; // Master Clock Register | |
| AT91_REG Reserved2[3]; // | |
| AT91_REG PMC_PCKR[8]; // Programmable Clock Register | |
| AT91_REG PMC_IER; // Interrupt Enable Register | |
| AT91_REG PMC_IDR; // Interrupt Disable Register | |
| AT91_REG PMC_SR; // Status Register | |
| AT91_REG PMC_IMR; // Interrupt Mask Register | |
| AT91_REG PMC_FSMR; // Fast Startup Mode Register | |
| AT91_REG PMC_FSPR; // Fast Startup Polarity Register | |
| AT91_REG PMC_FOCR; // Fault Output Clear Register | |
| AT91_REG Reserved3[28]; // | |
| AT91_REG PMC_ADDRSIZE; // PMC ADDRSIZE REGISTER | |
| AT91_REG PMC_IPNAME1; // PMC IPNAME1 REGISTER | |
| AT91_REG PMC_IPNAME2; // PMC IPNAME2 REGISTER | |
| AT91_REG PMC_FEATURES; // PMC FEATURES REGISTER | |
| AT91_REG PMC_VER; // APMC VERSION REGISTER | |
| } AT91S_PMC, *AT91PS_PMC; | |
| #else | |
| #define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register | |
| #define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register | |
| #define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register | |
| #define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register | |
| #define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register | |
| #define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register | |
| #define CKGR_UCKR (AT91_CAST(AT91_REG *) 0x0000001C) // (CKGR_UCKR) UTMI Clock Configuration Register | |
| #define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000020) // (CKGR_MOR) Main Oscillator Register | |
| #define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000024) // (CKGR_MCFR) Main Clock Frequency Register | |
| #define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000028) // (CKGR_PLLAR) PLL Register | |
| #define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register | |
| #define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register | |
| #define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register | |
| #define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register | |
| #define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register | |
| #define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register | |
| #define PMC_FSMR (AT91_CAST(AT91_REG *) 0x00000070) // (PMC_FSMR) Fast Startup Mode Register | |
| #define PMC_FSPR (AT91_CAST(AT91_REG *) 0x00000074) // (PMC_FSPR) Fast Startup Polarity Register | |
| #define PMC_FOCR (AT91_CAST(AT91_REG *) 0x00000078) // (PMC_FOCR) Fault Output Clear Register | |
| #define PMC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (PMC_ADDRSIZE) PMC ADDRSIZE REGISTER | |
| #define PMC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (PMC_IPNAME1) PMC IPNAME1 REGISTER | |
| #define PMC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (PMC_IPNAME2) PMC IPNAME2 REGISTER | |
| #define PMC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (PMC_FEATURES) PMC FEATURES REGISTER | |
| #define PMC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (PMC_VER) APMC VERSION REGISTER | |
| #endif | |
| // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- | |
| #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock | |
| #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output | |
| #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output | |
| #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output | |
| // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- | |
| // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- | |
| // -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- | |
| #define AT91C_CKGR_UPLLEN (0x1 << 16) // (PMC) UTMI PLL Enable | |
| #define AT91C_CKGR_UPLLEN_DISABLED (0x0 << 16) // (PMC) The UTMI PLL is disabled | |
| #define AT91C_CKGR_UPLLEN_ENABLED (0x1 << 16) // (PMC) The UTMI PLL is enabled | |
| #define AT91C_CKGR_UPLLCOUNT (0xF << 20) // (PMC) UTMI Oscillator Start-up Time | |
| #define AT91C_CKGR_BIASEN (0x1 << 24) // (PMC) UTMI BIAS Enable | |
| #define AT91C_CKGR_BIASEN_DISABLED (0x0 << 24) // (PMC) The UTMI BIAS is disabled | |
| #define AT91C_CKGR_BIASEN_ENABLED (0x1 << 24) // (PMC) The UTMI BIAS is enabled | |
| #define AT91C_CKGR_BIASCOUNT (0xF << 28) // (PMC) UTMI BIAS Start-up Time | |
| // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- | |
| #define AT91C_CKGR_MOSCXTEN (0x1 << 0) // (PMC) Main Crystal Oscillator Enable | |
| #define AT91C_CKGR_MOSCXTBY (0x1 << 1) // (PMC) Main Crystal Oscillator Bypass | |
| #define AT91C_CKGR_WAITMODE (0x1 << 2) // (PMC) Main Crystal Oscillator Bypass | |
| #define AT91C_CKGR_MOSCRCEN (0x1 << 3) // (PMC) Main On-Chip RC Oscillator Enable | |
| #define AT91C_CKGR_MOSCRCF (0x7 << 4) // (PMC) Main On-Chip RC Oscillator Frequency Selection | |
| #define AT91C_CKGR_MOSCXTST (0xFF << 8) // (PMC) Main Crystal Oscillator Start-up Time | |
| #define AT91C_CKGR_KEY (0xFF << 16) // (PMC) Clock Generator Controller Writing Protection Key | |
| #define AT91C_CKGR_MOSCSEL (0x1 << 24) // (PMC) Main Oscillator Selection | |
| #define AT91C_CKGR_CFDEN (0x1 << 25) // (PMC) Clock Failure Detector Enable | |
| // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- | |
| #define AT91C_CKGR_MAINF (0xFFFF << 0) // (PMC) Main Clock Frequency | |
| #define AT91C_CKGR_MAINRDY (0x1 << 16) // (PMC) Main Clock Ready | |
| // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- | |
| #define AT91C_CKGR_DIVA (0xFF << 0) // (PMC) Divider Selected | |
| #define AT91C_CKGR_DIVA_0 (0x0) // (PMC) Divider output is 0 | |
| #define AT91C_CKGR_DIVA_BYPASS (0x1) // (PMC) Divider is bypassed | |
| #define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (PMC) PLLA Counter | |
| #define AT91C_CKGR_STMODE (0x3 << 14) // (PMC) Start Mode | |
| #define AT91C_CKGR_STMODE_0 (0x0 << 14) // (PMC) Fast startup | |
| #define AT91C_CKGR_STMODE_1 (0x1 << 14) // (PMC) Reserved | |
| #define AT91C_CKGR_STMODE_2 (0x2 << 14) // (PMC) Normal startup | |
| #define AT91C_CKGR_STMODE_3 (0x3 << 14) // (PMC) Reserved | |
| #define AT91C_CKGR_MULA (0x7FF << 16) // (PMC) PLL Multiplier | |
| #define AT91C_CKGR_SRC (0x1 << 29) // (PMC) | |
| // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- | |
| #define AT91C_PMC_CSS (0x7 << 0) // (PMC) Programmable Clock Selection | |
| #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected | |
| #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected | |
| #define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected | |
| #define AT91C_PMC_CSS_UPLL_CLK (0x3) // (PMC) Clock from UPLL is selected | |
| #define AT91C_PMC_CSS_SYS_CLK (0x4) // (PMC) System clock is selected | |
| #define AT91C_PMC_PRES (0x7 << 4) // (PMC) Programmable Clock Prescaler | |
| #define AT91C_PMC_PRES_CLK (0x0 << 4) // (PMC) Selected clock | |
| #define AT91C_PMC_PRES_CLK_2 (0x1 << 4) // (PMC) Selected clock divided by 2 | |
| #define AT91C_PMC_PRES_CLK_4 (0x2 << 4) // (PMC) Selected clock divided by 4 | |
| #define AT91C_PMC_PRES_CLK_8 (0x3 << 4) // (PMC) Selected clock divided by 8 | |
| #define AT91C_PMC_PRES_CLK_16 (0x4 << 4) // (PMC) Selected clock divided by 16 | |
| #define AT91C_PMC_PRES_CLK_32 (0x5 << 4) // (PMC) Selected clock divided by 32 | |
| #define AT91C_PMC_PRES_CLK_64 (0x6 << 4) // (PMC) Selected clock divided by 64 | |
| #define AT91C_PMC_PRES_CLK_6 (0x7 << 4) // (PMC) Selected clock divided by 6 | |
| // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- | |
| // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- | |
| #define AT91C_PMC_MOSCXTS (0x1 << 0) // (PMC) Main Crystal Oscillator Status/Enable/Disable/Mask | |
| #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask | |
| #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask | |
| #define AT91C_PMC_LOCKU (0x1 << 6) // (PMC) PLL UTMI Status/Enable/Disable/Mask | |
| #define AT91C_PMC_PCKRDY0 (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask | |
| #define AT91C_PMC_PCKRDY1 (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask | |
| #define AT91C_PMC_PCKRDY2 (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask | |
| #define AT91C_PMC_MOSCSELS (0x1 << 16) // (PMC) Main Oscillator Selection Status | |
| #define AT91C_PMC_MOSCRCS (0x1 << 17) // (PMC) Main On-Chip RC Oscillator Status | |
| #define AT91C_PMC_CFDEV (0x1 << 18) // (PMC) Clock Failure Detector Event | |
| // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- | |
| // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- | |
| #define AT91C_PMC_OSCSELS (0x1 << 7) // (PMC) Slow Clock Oscillator Selection | |
| #define AT91C_PMC_CFDS (0x1 << 19) // (PMC) Clock Failure Detector Status | |
| #define AT91C_PMC_FOS (0x1 << 20) // (PMC) Clock Failure Detector Fault Output Status | |
| // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- | |
| // -------- PMC_FSMR : (PMC Offset: 0x70) Fast Startup Mode Register -------- | |
| #define AT91C_PMC_FSTT (0xFFFF << 0) // (PMC) Fast Start-up Input Enable 0 to 15 | |
| #define AT91C_PMC_RTTAL (0x1 << 16) // (PMC) RTT Alarm Enable | |
| #define AT91C_PMC_RTCAL (0x1 << 17) // (PMC) RTC Alarm Enable | |
| #define AT91C_PMC_USBAL (0x1 << 18) // (PMC) USB Alarm Enable | |
| #define AT91C_PMC_LPM (0x1 << 20) // (PMC) Low Power Mode | |
| // -------- PMC_FSPR : (PMC Offset: 0x74) Fast Startup Polarity Register -------- | |
| #define AT91C_PMC_FSTP (0xFFFF << 0) // (PMC) Fast Start-up Input Polarity 0 to 15 | |
| // -------- PMC_FOCR : (PMC Offset: 0x78) Fault Output Clear Register -------- | |
| #define AT91C_PMC_FOCLR (0x1 << 0) // (PMC) Fault Output Clear | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Clock Generator Controler | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_CKGR { | |
| AT91_REG CKGR_UCKR; // UTMI Clock Configuration Register | |
| AT91_REG CKGR_MOR; // Main Oscillator Register | |
| AT91_REG CKGR_MCFR; // Main Clock Frequency Register | |
| AT91_REG CKGR_PLLAR; // PLL Register | |
| } AT91S_CKGR, *AT91PS_CKGR; | |
| #else | |
| #endif | |
| // -------- CKGR_UCKR : (CKGR Offset: 0x0) UTMI Clock Configuration Register -------- | |
| // -------- CKGR_MOR : (CKGR Offset: 0x4) Main Oscillator Register -------- | |
| // -------- CKGR_MCFR : (CKGR Offset: 0x8) Main Clock Frequency Register -------- | |
| // -------- CKGR_PLLAR : (CKGR Offset: 0xc) PLL A Register -------- | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Reset Controller Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_RSTC { | |
| AT91_REG RSTC_RCR; // Reset Control Register | |
| AT91_REG RSTC_RSR; // Reset Status Register | |
| AT91_REG RSTC_RMR; // Reset Mode Register | |
| AT91_REG Reserved0[60]; // | |
| AT91_REG RSTC_VER; // Version Register | |
| } AT91S_RSTC, *AT91PS_RSTC; | |
| #else | |
| #define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register | |
| #define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register | |
| #define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register | |
| #define RSTC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (RSTC_VER) Version Register | |
| #endif | |
| // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- | |
| #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset | |
| #define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset | |
| #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset | |
| #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset | |
| #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password | |
| // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- | |
| #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status | |
| #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type | |
| #define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. | |
| #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. | |
| #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. | |
| #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. | |
| #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. | |
| #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level | |
| #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. | |
| // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- | |
| #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable | |
| #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable | |
| #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Supply Controller Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_SUPC { | |
| AT91_REG SUPC_CR; // Control Register | |
| AT91_REG SUPC_BOMR; // Brown Out Mode Register | |
| AT91_REG SUPC_MR; // Mode Register | |
| AT91_REG SUPC_WUMR; // Wake Up Mode Register | |
| AT91_REG SUPC_WUIR; // Wake Up Inputs Register | |
| AT91_REG SUPC_SR; // Status Register | |
| AT91_REG SUPC_FWUTR; // Flash Wake-up Timer Register | |
| } AT91S_SUPC, *AT91PS_SUPC; | |
| #else | |
| #define SUPC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SUPC_CR) Control Register | |
| #define SUPC_BOMR (AT91_CAST(AT91_REG *) 0x00000004) // (SUPC_BOMR) Brown Out Mode Register | |
| #define SUPC_MR (AT91_CAST(AT91_REG *) 0x00000008) // (SUPC_MR) Mode Register | |
| #define SUPC_WUMR (AT91_CAST(AT91_REG *) 0x0000000C) // (SUPC_WUMR) Wake Up Mode Register | |
| #define SUPC_WUIR (AT91_CAST(AT91_REG *) 0x00000010) // (SUPC_WUIR) Wake Up Inputs Register | |
| #define SUPC_SR (AT91_CAST(AT91_REG *) 0x00000014) // (SUPC_SR) Status Register | |
| #define SUPC_FWUTR (AT91_CAST(AT91_REG *) 0x00000018) // (SUPC_FWUTR) Flash Wake-up Timer Register | |
| #endif | |
| // -------- SUPC_CR : (SUPC Offset: 0x0) Control Register -------- | |
| #define AT91C_SUPC_SHDW (0x1 << 0) // (SUPC) Shut Down Command | |
| #define AT91C_SUPC_SHDWEOF (0x1 << 1) // (SUPC) Shut Down after End Of Frame | |
| #define AT91C_SUPC_VROFF (0x1 << 2) // (SUPC) Voltage Regulator Off | |
| #define AT91C_SUPC_XTALSEL (0x1 << 3) // (SUPC) Crystal Oscillator Select | |
| #define AT91C_SUPC_KEY (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key | |
| // -------- SUPC_BOMR : (SUPC Offset: 0x4) Brown Out Mode Register -------- | |
| #define AT91C_SUPC_BODTH (0xF << 0) // (SUPC) Brown Out Threshold | |
| #define AT91C_SUPC_BODSMPL (0x7 << 8) // (SUPC) Brown Out Sampling Period | |
| #define AT91C_SUPC_BODSMPL_DISABLED (0x0 << 8) // (SUPC) Brown Out Detector disabled | |
| #define AT91C_SUPC_BODSMPL_CONTINUOUS (0x1 << 8) // (SUPC) Continuous Brown Out Detector | |
| #define AT91C_SUPC_BODSMPL_32_SLCK (0x2 << 8) // (SUPC) Brown Out Detector enabled one SLCK period every 32 SLCK periods | |
| #define AT91C_SUPC_BODSMPL_256_SLCK (0x3 << 8) // (SUPC) Brown Out Detector enabled one SLCK period every 256 SLCK periods | |
| #define AT91C_SUPC_BODSMPL_2048_SLCK (0x4 << 8) // (SUPC) Brown Out Detector enabled one SLCK period every 2048 SLCK periods | |
| #define AT91C_SUPC_BODRSTEN (0x1 << 12) // (SUPC) Brownout Reset Enable | |
| // -------- SUPC_MR : (SUPC Offset: 0x8) Supply Controller Mode Register -------- | |
| #define AT91C_SUPC_LCDOUT (0xF << 0) // (SUPC) LCD Charge Pump Output Voltage Selection | |
| #define AT91C_SUPC_LCDMODE (0x3 << 4) // (SUPC) Segment LCD Supply Mode | |
| #define AT91C_SUPC_LCDMODE_OFF (0x0 << 4) // (SUPC) The internal and external supply sources are both deselected and the on-chip charge pump is turned off | |
| #define AT91C_SUPC_LCDMODE_OFF_AFTER_EOF (0x1 << 4) // (SUPC) At the End Of Frame from LCD controller, the internal and external supply sources are both deselected and the on-chip charge pump is turned off | |
| #define AT91C_SUPC_LCDMODE_EXTERNAL (0x2 << 4) // (SUPC) The external supply source is selected | |
| #define AT91C_SUPC_LCDMODE_INTERNAL (0x3 << 4) // (SUPC) The internal supply source is selected and the on-chip charge pump is turned on | |
| #define AT91C_SUPC_VRDEEP (0x1 << 8) // (SUPC) Voltage Regulator Deep Mode | |
| #define AT91C_SUPC_VRVDD (0x7 << 9) // (SUPC) Voltage Regulator Output Voltage Selection | |
| #define AT91C_SUPC_VRRSTEN (0x1 << 12) // (SUPC) Voltage Regulation Loss Reset Enable | |
| #define AT91C_SUPC_GPBRON (0x1 << 16) // (SUPC) GPBR ON | |
| #define AT91C_SUPC_SRAMON (0x1 << 17) // (SUPC) SRAM ON | |
| #define AT91C_SUPC_RTCON (0x1 << 18) // (SUPC) Real Time Clock Power switch ON | |
| #define AT91C_SUPC_FLASHON (0x1 << 19) // (SUPC) Flash Power switch On | |
| #define AT91C_SUPC_BYPASS (0x1 << 20) // (SUPC) 32kHz oscillator bypass | |
| #define AT91C_SUPC_MKEY (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key | |
| // -------- SUPC_WUMR : (SUPC Offset: 0xc) Wake Up Mode Register -------- | |
| #define AT91C_SUPC_FWUPEN (0x1 << 0) // (SUPC) Force Wake Up Enable | |
| #define AT91C_SUPC_BODEN (0x1 << 1) // (SUPC) Brown Out Wake Up Enable | |
| #define AT91C_SUPC_RTTEN (0x1 << 2) // (SUPC) Real Time Timer Wake Up Enable | |
| #define AT91C_SUPC_RTCEN (0x1 << 3) // (SUPC) Real Time Clock Wake Up Enable | |
| #define AT91C_SUPC_FWUPDBC (0x7 << 8) // (SUPC) Force Wake Up debouncer | |
| #define AT91C_SUPC_FWUPDBC_IMMEDIATE (0x0 << 8) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge | |
| #define AT91C_SUPC_FWUPDBC_3_SLCK (0x1 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 3 SLCK periods | |
| #define AT91C_SUPC_FWUPDBC_32_SLCK (0x2 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 32 SLCK periods | |
| #define AT91C_SUPC_FWUPDBC_512_SLCK (0x3 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 512 SLCK periods | |
| #define AT91C_SUPC_FWUPDBC_4096_SLCK (0x4 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 4096 SLCK periods | |
| #define AT91C_SUPC_FWUPDBC_32768_SLCK (0x5 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 32768 SLCK periods | |
| #define AT91C_SUPC_WKUPDBC (0x7 << 12) // (SUPC) Force Wake Up debouncer | |
| #define AT91C_SUPC_WKUPDBC_IMMEDIATE (0x0 << 12) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge | |
| #define AT91C_SUPC_WKUPDBC_3_SLCK (0x1 << 12) // (SUPC) FWUP shall be low for at least 3 SLCK periods | |
| #define AT91C_SUPC_WKUPDBC_32_SLCK (0x2 << 12) // (SUPC) FWUP shall be low for at least 32 SLCK periods | |
| #define AT91C_SUPC_WKUPDBC_512_SLCK (0x3 << 12) // (SUPC) FWUP shall be low for at least 512 SLCK periods | |
| #define AT91C_SUPC_WKUPDBC_4096_SLCK (0x4 << 12) // (SUPC) FWUP shall be low for at least 4096 SLCK periods | |
| #define AT91C_SUPC_WKUPDBC_32768_SLCK (0x5 << 12) // (SUPC) FWUP shall be low for at least 32768 SLCK periods | |
| // -------- SUPC_WUIR : (SUPC Offset: 0x10) Wake Up Inputs Register -------- | |
| #define AT91C_SUPC_WKUPEN0 (0x1 << 0) // (SUPC) Wake Up Input Enable 0 | |
| #define AT91C_SUPC_WKUPEN1 (0x1 << 1) // (SUPC) Wake Up Input Enable 1 | |
| #define AT91C_SUPC_WKUPEN2 (0x1 << 2) // (SUPC) Wake Up Input Enable 2 | |
| #define AT91C_SUPC_WKUPEN3 (0x1 << 3) // (SUPC) Wake Up Input Enable 3 | |
| #define AT91C_SUPC_WKUPEN4 (0x1 << 4) // (SUPC) Wake Up Input Enable 4 | |
| #define AT91C_SUPC_WKUPEN5 (0x1 << 5) // (SUPC) Wake Up Input Enable 5 | |
| #define AT91C_SUPC_WKUPEN6 (0x1 << 6) // (SUPC) Wake Up Input Enable 6 | |
| #define AT91C_SUPC_WKUPEN7 (0x1 << 7) // (SUPC) Wake Up Input Enable 7 | |
| #define AT91C_SUPC_WKUPEN8 (0x1 << 8) // (SUPC) Wake Up Input Enable 8 | |
| #define AT91C_SUPC_WKUPEN9 (0x1 << 9) // (SUPC) Wake Up Input Enable 9 | |
| #define AT91C_SUPC_WKUPEN10 (0x1 << 10) // (SUPC) Wake Up Input Enable 10 | |
| #define AT91C_SUPC_WKUPEN11 (0x1 << 11) // (SUPC) Wake Up Input Enable 11 | |
| #define AT91C_SUPC_WKUPEN12 (0x1 << 12) // (SUPC) Wake Up Input Enable 12 | |
| #define AT91C_SUPC_WKUPEN13 (0x1 << 13) // (SUPC) Wake Up Input Enable 13 | |
| #define AT91C_SUPC_WKUPEN14 (0x1 << 14) // (SUPC) Wake Up Input Enable 14 | |
| #define AT91C_SUPC_WKUPEN15 (0x1 << 15) // (SUPC) Wake Up Input Enable 15 | |
| #define AT91C_SUPC_WKUPT0 (0x1 << 16) // (SUPC) Wake Up Input Transition 0 | |
| #define AT91C_SUPC_WKUPT1 (0x1 << 17) // (SUPC) Wake Up Input Transition 1 | |
| #define AT91C_SUPC_WKUPT2 (0x1 << 18) // (SUPC) Wake Up Input Transition 2 | |
| #define AT91C_SUPC_WKUPT3 (0x1 << 19) // (SUPC) Wake Up Input Transition 3 | |
| #define AT91C_SUPC_WKUPT4 (0x1 << 20) // (SUPC) Wake Up Input Transition 4 | |
| #define AT91C_SUPC_WKUPT5 (0x1 << 21) // (SUPC) Wake Up Input Transition 5 | |
| #define AT91C_SUPC_WKUPT6 (0x1 << 22) // (SUPC) Wake Up Input Transition 6 | |
| #define AT91C_SUPC_WKUPT7 (0x1 << 23) // (SUPC) Wake Up Input Transition 7 | |
| #define AT91C_SUPC_WKUPT8 (0x1 << 24) // (SUPC) Wake Up Input Transition 8 | |
| #define AT91C_SUPC_WKUPT9 (0x1 << 25) // (SUPC) Wake Up Input Transition 9 | |
| #define AT91C_SUPC_WKUPT10 (0x1 << 26) // (SUPC) Wake Up Input Transition 10 | |
| #define AT91C_SUPC_WKUPT11 (0x1 << 27) // (SUPC) Wake Up Input Transition 11 | |
| #define AT91C_SUPC_WKUPT12 (0x1 << 28) // (SUPC) Wake Up Input Transition 12 | |
| #define AT91C_SUPC_WKUPT13 (0x1 << 29) // (SUPC) Wake Up Input Transition 13 | |
| #define AT91C_SUPC_WKUPT14 (0x1 << 30) // (SUPC) Wake Up Input Transition 14 | |
| #define AT91C_SUPC_WKUPT15 (0x1 << 31) // (SUPC) Wake Up Input Transition 15 | |
| // -------- SUPC_SR : (SUPC Offset: 0x14) Status Register -------- | |
| #define AT91C_SUPC_FWUPS (0x1 << 0) // (SUPC) Force Wake Up Status | |
| #define AT91C_SUPC_WKUPS (0x1 << 1) // (SUPC) Wake Up Status | |
| #define AT91C_SUPC_BODWS (0x1 << 2) // (SUPC) BOD Detection Wake Up Status | |
| #define AT91C_SUPC_VRRSTS (0x1 << 3) // (SUPC) Voltage regulation Loss Reset Status | |
| #define AT91C_SUPC_BODRSTS (0x1 << 4) // (SUPC) BOD detection Reset Status | |
| #define AT91C_SUPC_BODS (0x1 << 5) // (SUPC) BOD Status | |
| #define AT91C_SUPC_BROWNOUT (0x1 << 6) // (SUPC) BOD Output Status | |
| #define AT91C_SUPC_OSCSEL (0x1 << 7) // (SUPC) 32kHz Oscillator Selection Status | |
| #define AT91C_SUPC_LCDS (0x1 << 8) // (SUPC) LCD Status | |
| #define AT91C_SUPC_GPBRS (0x1 << 9) // (SUPC) General Purpose Back-up registers Status | |
| #define AT91C_SUPC_RTS (0x1 << 10) // (SUPC) Clock Status | |
| #define AT91C_SUPC_FLASHS (0x1 << 11) // (SUPC) FLASH Memory Status | |
| #define AT91C_SUPC_FWUPIS (0x1 << 12) // (SUPC) WKUP Input Status | |
| #define AT91C_SUPC_WKUPIS0 (0x1 << 16) // (SUPC) WKUP Input 0 Status | |
| #define AT91C_SUPC_WKUPIS1 (0x1 << 17) // (SUPC) WKUP Input 1 Status | |
| #define AT91C_SUPC_WKUPIS2 (0x1 << 18) // (SUPC) WKUP Input 2 Status | |
| #define AT91C_SUPC_WKUPIS3 (0x1 << 19) // (SUPC) WKUP Input 3 Status | |
| #define AT91C_SUPC_WKUPIS4 (0x1 << 20) // (SUPC) WKUP Input 4 Status | |
| #define AT91C_SUPC_WKUPIS5 (0x1 << 21) // (SUPC) WKUP Input 5 Status | |
| #define AT91C_SUPC_WKUPIS6 (0x1 << 22) // (SUPC) WKUP Input 6 Status | |
| #define AT91C_SUPC_WKUPIS7 (0x1 << 23) // (SUPC) WKUP Input 7 Status | |
| #define AT91C_SUPC_WKUPIS8 (0x1 << 24) // (SUPC) WKUP Input 8 Status | |
| #define AT91C_SUPC_WKUPIS9 (0x1 << 25) // (SUPC) WKUP Input 9 Status | |
| #define AT91C_SUPC_WKUPIS10 (0x1 << 26) // (SUPC) WKUP Input 10 Status | |
| #define AT91C_SUPC_WKUPIS11 (0x1 << 27) // (SUPC) WKUP Input 11 Status | |
| #define AT91C_SUPC_WKUPIS12 (0x1 << 28) // (SUPC) WKUP Input 12 Status | |
| #define AT91C_SUPC_WKUPIS13 (0x1 << 29) // (SUPC) WKUP Input 13 Status | |
| #define AT91C_SUPC_WKUPIS14 (0x1 << 30) // (SUPC) WKUP Input 14 Status | |
| #define AT91C_SUPC_WKUPIS15 (0x1 << 31) // (SUPC) WKUP Input 15 Status | |
| // -------- SUPC_FWUTR : (SUPC Offset: 0x18) Flash Wake Up Timer Register -------- | |
| #define AT91C_SUPC_FWUT (0x3FF << 0) // (SUPC) Flash Wake Up Timer | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_RTTC { | |
| AT91_REG RTTC_RTMR; // Real-time Mode Register | |
| AT91_REG RTTC_RTAR; // Real-time Alarm Register | |
| AT91_REG RTTC_RTVR; // Real-time Value Register | |
| AT91_REG RTTC_RTSR; // Real-time Status Register | |
| } AT91S_RTTC, *AT91PS_RTTC; | |
| #else | |
| #define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register | |
| #define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register | |
| #define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register | |
| #define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register | |
| #endif | |
| // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- | |
| #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value | |
| #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable | |
| #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable | |
| #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart | |
| // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- | |
| #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value | |
| // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- | |
| #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value | |
| // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- | |
| #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status | |
| #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_WDTC { | |
| AT91_REG WDTC_WDCR; // Watchdog Control Register | |
| AT91_REG WDTC_WDMR; // Watchdog Mode Register | |
| AT91_REG WDTC_WDSR; // Watchdog Status Register | |
| } AT91S_WDTC, *AT91PS_WDTC; | |
| #else | |
| #define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register | |
| #define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register | |
| #define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register | |
| #endif | |
| // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- | |
| #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart | |
| #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password | |
| // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- | |
| #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart | |
| #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable | |
| #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable | |
| #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart | |
| #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable | |
| #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value | |
| #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt | |
| #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt | |
| // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- | |
| #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow | |
| #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_RTC { | |
| AT91_REG RTC_CR; // Control Register | |
| AT91_REG RTC_MR; // Mode Register | |
| AT91_REG RTC_TIMR; // Time Register | |
| AT91_REG RTC_CALR; // Calendar Register | |
| AT91_REG RTC_TIMALR; // Time Alarm Register | |
| AT91_REG RTC_CALALR; // Calendar Alarm Register | |
| AT91_REG RTC_SR; // Status Register | |
| AT91_REG RTC_SCCR; // Status Clear Command Register | |
| AT91_REG RTC_IER; // Interrupt Enable Register | |
| AT91_REG RTC_IDR; // Interrupt Disable Register | |
| AT91_REG RTC_IMR; // Interrupt Mask Register | |
| AT91_REG RTC_VER; // Valid Entry Register | |
| } AT91S_RTC, *AT91PS_RTC; | |
| #else | |
| #define RTC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (RTC_CR) Control Register | |
| #define RTC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (RTC_MR) Mode Register | |
| #define RTC_TIMR (AT91_CAST(AT91_REG *) 0x00000008) // (RTC_TIMR) Time Register | |
| #define RTC_CALR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTC_CALR) Calendar Register | |
| #define RTC_TIMALR (AT91_CAST(AT91_REG *) 0x00000010) // (RTC_TIMALR) Time Alarm Register | |
| #define RTC_CALALR (AT91_CAST(AT91_REG *) 0x00000014) // (RTC_CALALR) Calendar Alarm Register | |
| #define RTC_SR (AT91_CAST(AT91_REG *) 0x00000018) // (RTC_SR) Status Register | |
| #define RTC_SCCR (AT91_CAST(AT91_REG *) 0x0000001C) // (RTC_SCCR) Status Clear Command Register | |
| #define RTC_IER (AT91_CAST(AT91_REG *) 0x00000020) // (RTC_IER) Interrupt Enable Register | |
| #define RTC_IDR (AT91_CAST(AT91_REG *) 0x00000024) // (RTC_IDR) Interrupt Disable Register | |
| #define RTC_IMR (AT91_CAST(AT91_REG *) 0x00000028) // (RTC_IMR) Interrupt Mask Register | |
| #define RTC_VER (AT91_CAST(AT91_REG *) 0x0000002C) // (RTC_VER) Valid Entry Register | |
| #endif | |
| // -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- | |
| #define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register | |
| #define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register | |
| #define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection | |
| #define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change. | |
| #define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change. | |
| #define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight. | |
| #define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon. | |
| #define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection | |
| #define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). | |
| #define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). | |
| #define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). | |
| // -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- | |
| #define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode | |
| // -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- | |
| #define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second | |
| #define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute | |
| #define AT91C_RTC_HOUR (0x3F << 16) // (RTC) Current Hour | |
| #define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator | |
| // -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- | |
| #define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century | |
| #define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year | |
| #define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month | |
| #define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day | |
| #define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date | |
| // -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- | |
| #define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable | |
| #define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm | |
| #define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour | |
| // -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- | |
| #define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable | |
| #define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable | |
| // -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- | |
| #define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update | |
| #define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag | |
| #define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event | |
| #define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event | |
| #define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event | |
| // -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- | |
| // -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- | |
| // -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- | |
| // -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- | |
| // -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- | |
| #define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time | |
| #define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar | |
| #define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm | |
| #define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Analog to Digital Convertor | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_ADC { | |
| AT91_REG ADC_CR; // ADC Control Register | |
| AT91_REG ADC_MR; // ADC Mode Register | |
| AT91_REG Reserved0[2]; // | |
| AT91_REG ADC_CHER; // ADC Channel Enable Register | |
| AT91_REG ADC_CHDR; // ADC Channel Disable Register | |
| AT91_REG ADC_CHSR; // ADC Channel Status Register | |
| AT91_REG ADC_SR; // ADC Status Register | |
| AT91_REG ADC_LCDR; // ADC Last Converted Data Register | |
| AT91_REG ADC_IER; // ADC Interrupt Enable Register | |
| AT91_REG ADC_IDR; // ADC Interrupt Disable Register | |
| AT91_REG ADC_IMR; // ADC Interrupt Mask Register | |
| AT91_REG ADC_CDR0; // ADC Channel Data Register 0 | |
| AT91_REG ADC_CDR1; // ADC Channel Data Register 1 | |
| AT91_REG ADC_CDR2; // ADC Channel Data Register 2 | |
| AT91_REG ADC_CDR3; // ADC Channel Data Register 3 | |
| AT91_REG ADC_CDR4; // ADC Channel Data Register 4 | |
| AT91_REG ADC_CDR5; // ADC Channel Data Register 5 | |
| AT91_REG ADC_CDR6; // ADC Channel Data Register 6 | |
| AT91_REG ADC_CDR7; // ADC Channel Data Register 7 | |
| AT91_REG Reserved1[5]; // | |
| AT91_REG ADC_ACR; // Analog Control Register | |
| AT91_REG ADC_EMR; // Extended Mode Register | |
| AT91_REG Reserved2[32]; // | |
| AT91_REG ADC_ADDRSIZE; // ADC ADDRSIZE REGISTER | |
| AT91_REG ADC_IPNAME1; // ADC IPNAME1 REGISTER | |
| AT91_REG ADC_IPNAME2; // ADC IPNAME2 REGISTER | |
| AT91_REG ADC_FEATURES; // ADC FEATURES REGISTER | |
| AT91_REG ADC_VER; // ADC VERSION REGISTER | |
| AT91_REG ADC_RPR; // Receive Pointer Register | |
| AT91_REG ADC_RCR; // Receive Counter Register | |
| AT91_REG ADC_TPR; // Transmit Pointer Register | |
| AT91_REG ADC_TCR; // Transmit Counter Register | |
| AT91_REG ADC_RNPR; // Receive Next Pointer Register | |
| AT91_REG ADC_RNCR; // Receive Next Counter Register | |
| AT91_REG ADC_TNPR; // Transmit Next Pointer Register | |
| AT91_REG ADC_TNCR; // Transmit Next Counter Register | |
| AT91_REG ADC_PTCR; // PDC Transfer Control Register | |
| AT91_REG ADC_PTSR; // PDC Transfer Status Register | |
| } AT91S_ADC, *AT91PS_ADC; | |
| #else | |
| #define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register | |
| #define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register | |
| #define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register | |
| #define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register | |
| #define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register | |
| #define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register | |
| #define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register | |
| #define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register | |
| #define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register | |
| #define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register | |
| #define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 | |
| #define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 | |
| #define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 | |
| #define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 | |
| #define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 | |
| #define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 | |
| #define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 | |
| #define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 | |
| #define ADC_ACR (AT91_CAST(AT91_REG *) 0x00000064) // (ADC_ACR) Analog Control Register | |
| #define ADC_EMR (AT91_CAST(AT91_REG *) 0x00000068) // (ADC_EMR) Extended Mode Register | |
| #define ADC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (ADC_ADDRSIZE) ADC ADDRSIZE REGISTER | |
| #define ADC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (ADC_IPNAME1) ADC IPNAME1 REGISTER | |
| #define ADC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (ADC_IPNAME2) ADC IPNAME2 REGISTER | |
| #define ADC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (ADC_FEATURES) ADC FEATURES REGISTER | |
| #define ADC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (ADC_VER) ADC VERSION REGISTER | |
| #endif | |
| // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- | |
| #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset | |
| #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion | |
| // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- | |
| #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable | |
| #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software | |
| #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. | |
| #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection | |
| #define AT91C_ADC_TRGSEL_EXT (0x0 << 1) // (ADC) Selected TRGSEL = External Trigger | |
| #define AT91C_ADC_TRGSEL_TIOA0 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO0 | |
| #define AT91C_ADC_TRGSEL_TIOA1 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO1 | |
| #define AT91C_ADC_TRGSEL_TIOA2 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO2 | |
| #define AT91C_ADC_TRGSEL_PWM0_TRIG (0x4 << 1) // (ADC) Selected TRGSEL = PWM trigger | |
| #define AT91C_ADC_TRGSEL_PWM1_TRIG (0x5 << 1) // (ADC) Selected TRGSEL = PWM Trigger | |
| #define AT91C_ADC_TRGSEL_RESERVED (0x6 << 1) // (ADC) Selected TRGSEL = Reserved | |
| #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. | |
| #define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution | |
| #define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution | |
| #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode | |
| #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode | |
| #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode | |
| #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection | |
| #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time | |
| #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time | |
| // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- | |
| #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 | |
| #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 | |
| #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 | |
| #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 | |
| #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 | |
| #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 | |
| #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 | |
| #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 | |
| // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- | |
| // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- | |
| // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- | |
| #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion | |
| #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion | |
| #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error | |
| #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error | |
| #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready | |
| #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun | |
| #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer | |
| #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt | |
| // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- | |
| #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted | |
| // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- | |
| // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- | |
| // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- | |
| // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- | |
| #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data | |
| // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- | |
| // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- | |
| // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- | |
| // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- | |
| // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- | |
| // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- | |
| // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- | |
| // -------- ADC_ACR : (ADC Offset: 0x64) ADC Analog Controler Register -------- | |
| #define AT91C_ADC_GAIN (0x3 << 0) // (ADC) Input Gain | |
| #define AT91C_ADC_IBCTL (0x3 << 6) // (ADC) Bias Current Control | |
| #define AT91C_ADC_IBCTL_00 (0x0 << 6) // (ADC) typ - 20% | |
| #define AT91C_ADC_IBCTL_01 (0x1 << 6) // (ADC) typ | |
| #define AT91C_ADC_IBCTL_10 (0x2 << 6) // (ADC) typ + 20% | |
| #define AT91C_ADC_IBCTL_11 (0x3 << 6) // (ADC) typ + 40% | |
| #define AT91C_ADC_DIFF (0x1 << 16) // (ADC) Differential Mode | |
| #define AT91C_ADC_OFFSET (0x1 << 17) // (ADC) Input OFFSET | |
| // -------- ADC_EMR : (ADC Offset: 0x68) ADC Extended Mode Register -------- | |
| #define AT91C_OFFMODES (0x1 << 0) // (ADC) Off Mode if | |
| #define AT91C_OFF_MODE_STARTUP_TIME (0x1 << 16) // (ADC) Startup Time | |
| // -------- ADC_VER : (ADC Offset: 0xfc) ADC VER -------- | |
| #define AT91C_ADC_VER (0xF << 0) // (ADC) ADC VER | |
| // ***************************************************************************** | |
| // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface | |
| // ***************************************************************************** | |
| #ifndef __ASSEMBLY__ | |
| typedef struct _AT91S_TC { | |
| AT91_REG TC_CCR; // Channel Control Register | |
| AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) | |
| AT91_REG Reserved0[2]; // | |
| AT91_REG TC_CV; // Counter Value | |
| AT91_REG TC_RA; // Register A | |
| AT91_REG TC_RB; // Register B | |
| AT91_REG TC_RC; // Register C | |
| AT91_REG TC_SR; // Status Register | |
| AT91_REG TC_IER; // Interrupt Enable Register | |
| AT91_REG TC_IDR; // Interrupt Disable Register | |
| AT91_REG TC_IMR; // Interrupt Mask Register | |
| } AT91S_TC, *AT91PS_TC; | |
| #else | |
| #define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register | |
| #define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register |